diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 19da68ebaf..8f57a49415 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -16,8 +16,8 @@ PKG_PATCH_DIRS="${LINUX}" case "${LINUX}" in amlogic) - PKG_VERSION="e8f897f4afef0031fe618a8e94127a0934896aba" # 6.8.0 - PKG_SHA256="52608771cc42196f0a7a71a93270a27ca5f7ba1d9280fb398e521b0620a7a3ac" + PKG_VERSION="1b4861e32e461b6fae14dc49ed0f1c7f20af5146" # 6.9.3 + PKG_SHA256="2502f1858175fc03ba38198df6b7ac62e167c9d2ee9b08b157bff66c73130e2c" PKG_URL="https://github.com/torvalds/linux/archive/${PKG_VERSION}.tar.gz" PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" PKG_PATCH_DIRS="default" diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0001-LOCAL-set-meson-gx-cma-pool-to-896MB.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0001-LOCAL-set-meson-gx-cma-pool-to-896MB.patch index eabb3fe385..499ef2dcb1 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0001-LOCAL-set-meson-gx-cma-pool-to-896MB.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0001-LOCAL-set-meson-gx-cma-pool-to-896MB.patch @@ -1,7 +1,7 @@ -From fa91cacc8756959b9b04b2cd3d369888b9a19e82 Mon Sep 17 00:00:00 2001 +From 623a57187a4893a78bf818f7852b0c4e40936b30 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 13 Apr 2019 05:41:51 +0000 -Subject: [PATCH 01/53] LOCAL: set meson-gx cma pool to 896MB +Subject: [PATCH 01/69] LOCAL: set meson-gx cma pool to 896MB This change sets the CMA pool to a larger 896MB! value for vdec use diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0002-LOCAL-set-meson-g12-cma-pool-to-896MB.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0002-LOCAL-set-meson-g12-cma-pool-to-896MB.patch index 7fb050f369..94d914392d 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0002-LOCAL-set-meson-g12-cma-pool-to-896MB.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0002-LOCAL-set-meson-g12-cma-pool-to-896MB.patch @@ -1,7 +1,7 @@ -From db61fd1f5ac1a4b39f7699ef5583db1464f2a419 Mon Sep 17 00:00:00 2001 +From 927f228f7bff9640c8f848202401a24be426c8b7 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 14 Aug 2019 19:58:14 +0000 -Subject: [PATCH 02/53] LOCAL: set meson-g12 cma pool to 896MB +Subject: [PATCH 02/69] LOCAL: set meson-g12 cma pool to 896MB This change sets the CMA pool to a larger 896MB! value for vdec use @@ -11,7 +11,7 @@ Signed-off-by: Christian Hewitt 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi -index ff68b911b729..f7f8df88d464 100644 +index 9d5eab6595d0..a960d07f9af3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -117,7 +117,7 @@ secmon_reserved_bl32: secmon@5300000 { diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0003-LOCAL-arm64-fix-Kodi-sysinfo-CPU-information.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0003-LOCAL-arm64-fix-Kodi-sysinfo-CPU-information.patch index 33e5b3aefb..d8617d0557 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0003-LOCAL-arm64-fix-Kodi-sysinfo-CPU-information.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0003-LOCAL-arm64-fix-Kodi-sysinfo-CPU-information.patch @@ -1,7 +1,7 @@ -From ee6ecf00c056184730623b0a09f8e1ce0adb3d24 Mon Sep 17 00:00:00 2001 +From 1cb9ad61f678caced45a9b84f19e55fb97add9d1 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 13 Apr 2019 05:45:18 +0000 -Subject: [PATCH 03/53] LOCAL: arm64: fix Kodi sysinfo CPU information +Subject: [PATCH 03/69] LOCAL: arm64: fix Kodi sysinfo CPU information This allows the CPU information to show in the Kodi sysinfo screen, e.g. @@ -13,10 +13,10 @@ Signed-off-by: Christian Hewitt 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c -index 47043c0d95ec..03410a9fac77 100644 +index 09eeaa24d456..b7bf422ce536 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c -@@ -190,8 +190,7 @@ static int c_show(struct seq_file *m, void *v) +@@ -205,8 +205,7 @@ static int c_show(struct seq_file *m, void *v) * "processor". Give glibc what it expects. */ seq_printf(m, "processor\t: %d\n", i); diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0004-LOCAL-arm64-meson-add-Amlogic-Meson-GX-PM-Suspend.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0004-LOCAL-arm64-meson-add-Amlogic-Meson-GX-PM-Suspend.patch index 0f6de6fc9b..d809620af8 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0004-LOCAL-arm64-meson-add-Amlogic-Meson-GX-PM-Suspend.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0004-LOCAL-arm64-meson-add-Amlogic-Meson-GX-PM-Suspend.patch @@ -1,7 +1,7 @@ -From 18375f3ce86dcec9a07f711b696aefb6fcb79829 Mon Sep 17 00:00:00 2001 +From bd0e5a715d103bb88d73ae280655a849f7762ecc Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 3 Nov 2016 15:29:23 +0100 -Subject: [PATCH 04/53] LOCAL: arm64: meson: add Amlogic Meson GX PM Suspend +Subject: [PATCH 04/69] LOCAL: arm64: meson: add Amlogic Meson GX PM Suspend The Amlogic Meson GX SoCs uses a non-standard argument to the PSCI CPU_SUSPEND call to enter system suspend. diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0005-LOCAL-arm64-dts-meson-add-support-for-GX-PM-and-Virt.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0005-LOCAL-arm64-dts-meson-add-support-for-GX-PM-and-Virt.patch index cecc66fa33..c5215ce60c 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0005-LOCAL-arm64-dts-meson-add-support-for-GX-PM-and-Virt.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0005-LOCAL-arm64-dts-meson-add-support-for-GX-PM-and-Virt.patch @@ -1,7 +1,7 @@ -From 346f8f56697d21901ca2c5d48c7beecc654131c0 Mon Sep 17 00:00:00 2001 +From 2e207659c996f765749e32d3ff932ab673965b42 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 3 Nov 2016 15:29:25 +0100 -Subject: [PATCH 05/53] LOCAL: arm64: dts: meson: add support for GX PM and +Subject: [PATCH 05/69] LOCAL: arm64: dts: meson: add support for GX PM and Virtual RTC Signed-off-by: Neil Armstrong diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0006-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0006-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch index 324ef8beed..5bd980b59d 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0006-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0006-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch @@ -1,7 +1,7 @@ -From e288d4c79fb45f1af148b279bcfd091f770e9070 Mon Sep 17 00:00:00 2001 +From 4c9bfede767b2c1e1ff43eda7fbb2b9b7d938761 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 21 Jan 2021 01:35:36 +0000 -Subject: [PATCH 06/53] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to +Subject: [PATCH 06/69] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to Khadas VIM Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1 diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0007-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0007-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch index 75410562d0..dfaf149051 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0007-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0007-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Khadas.patch @@ -1,7 +1,7 @@ -From 1ebc6f1a726d896fb8c72ed5e86423ad2485eea1 Mon Sep 17 00:00:00 2001 +From 36f210099326720a267df7108ef0ea7fb9ae88a7 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 6 Nov 2021 13:01:08 +0000 -Subject: [PATCH 07/53] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to +Subject: [PATCH 07/69] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to Khadas VIM2 Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1 @@ -13,7 +13,7 @@ Signed-off-by: Christian Hewitt 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts -index 860f307494c5..cee27e7222c8 100644 +index 07e7c3bedea0..a03269a00486 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -18,6 +18,8 @@ / { diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0008-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Minix-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0008-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Minix-.patch index f409cb8d95..c2b7b44f4a 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0008-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Minix-.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0008-LOCAL-arm64-dts-meson-add-rtc-vrtc-aliases-to-Minix-.patch @@ -1,7 +1,7 @@ -From 83e3e72c22bd9261d248c2dda723d5fb3abd4ab9 Mon Sep 17 00:00:00 2001 +From 2ca029008c662f81a80a7e694229d1950efe0d9a Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 1 Feb 2021 19:27:40 +0000 -Subject: [PATCH 08/53] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to Minix +Subject: [PATCH 08/69] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to Minix NEO U9-H Add node aliases to prevent meson-vrtc from claiming /dev/rtc0 diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0009-LOCAL-ASoC-meson-assign-internal-PCM-chmap-ELD-IEC95.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0009-LOCAL-ASoC-meson-assign-internal-PCM-chmap-ELD-IEC95.patch index 7149dafbb2..b7290fbe58 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0009-LOCAL-ASoC-meson-assign-internal-PCM-chmap-ELD-IEC95.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0009-LOCAL-ASoC-meson-assign-internal-PCM-chmap-ELD-IEC95.patch @@ -1,7 +1,7 @@ -From b419174ce9cd28aa55673140319aa4317922d0d7 Mon Sep 17 00:00:00 2001 +From 465c8694439773f00bc9088e41354e6d348366ab Mon Sep 17 00:00:00 2001 From: Anssi Hannula Date: Sun, 17 Apr 2022 04:37:48 +0000 -Subject: [PATCH 09/53] LOCAL: ASoC: meson: assign internal PCM +Subject: [PATCH 09/69] LOCAL: ASoC: meson: assign internal PCM chmap/ELD/IEC958 kctls to device 0 On SoC sound devices utilizing codec2codec DAI links with an HDMI codec the kctls @@ -24,10 +24,10 @@ Tested-by: Christian Hewitt 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c -index 41103e5c43ce..0db7fe63911e 100644 +index 6f73b3c2c205..4653351cc4b9 100644 --- a/sound/core/pcm_lib.c +++ b/sound/core/pcm_lib.c -@@ -2581,7 +2581,10 @@ int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream, +@@ -2577,7 +2577,10 @@ int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream, knew.name = "Playback Channel Map"; else knew.name = "Capture Channel Map"; diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0010-LOCAL-media-meson-vdec-disable-MPEG1-MPEG2-hardware-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0010-LOCAL-media-meson-vdec-disable-MPEG1-MPEG2-hardware-.patch index 77f185f16d..1a8a2d7bf2 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0010-LOCAL-media-meson-vdec-disable-MPEG1-MPEG2-hardware-.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0010-LOCAL-media-meson-vdec-disable-MPEG1-MPEG2-hardware-.patch @@ -1,7 +1,7 @@ -From 9787871fe1e00af9f915237be4474a3b1f1e0887 Mon Sep 17 00:00:00 2001 +From 1bdbf76d2a7e0c715469d3bc67f71f8c41c323f1 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 5 Jan 2023 15:16:46 +0000 -Subject: [PATCH 10/53] LOCAL: media: meson: vdec: disable MPEG1/MPEG2 hardware +Subject: [PATCH 10/69] LOCAL: media: meson: vdec: disable MPEG1/MPEG2 hardware decoding The MPEG1/2 decoder is broken and nobody has volunteered to poke diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0011-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-5-GHz-TX-pow.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0011-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-5-GHz-TX-pow.patch new file mode 100644 index 0000000000..3bbb5e5b58 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0011-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-5-GHz-TX-pow.patch @@ -0,0 +1,43 @@ +From b51a3b582d9626e5b896141c9b9edbf0d49d147d Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 25 Apr 2024 21:09:21 +0300 +Subject: [PATCH 11/69] FROMGIT(6.10): wifi: rtlwifi: rtl8192de: Fix 5 GHz TX + power + +Different channels have different TX power settings. rtl8192de is using +the TX power setting from the wrong channel in the 5 GHz band because +_rtl92c_phy_get_rightchnlplace expects an array which includes all the +channel numbers, but it's using an array which includes only the 5 GHz +channel numbers. + +Use the array channel_all (defined in rtl8192de/phy.c) instead of +the incorrect channel5g (defined in core.c). + +Tested only with rtl8192du, which will use the same TX power code. + +Cc: stable@vger.kernel.org +Signed-off-by: Bitterblue Smith +Signed-off-by: Ping-Ke Shih +Link: https://msgid.link/c7653517-cf88-4f57-b79a-8edb0a8b32f0@gmail.com +--- + drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +index d835a27429f0..56b5cd032a9a 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +@@ -892,8 +892,8 @@ static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) + u8 place = chnl; + + if (chnl > 14) { +- for (place = 14; place < ARRAY_SIZE(channel5g); place++) { +- if (channel5g[place] == chnl) { ++ for (place = 14; place < ARRAY_SIZE(channel_all); place++) { ++ if (channel_all[place] == chnl) { + place++; + break; + } +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0011-FROMGIT-6.9-arm64-dts-meson-g12-common-Set-the-rates.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0011-FROMGIT-6.9-arm64-dts-meson-g12-common-Set-the-rates.patch deleted file mode 100644 index 3776c6bccb..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0011-FROMGIT-6.9-arm64-dts-meson-g12-common-Set-the-rates.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f376bb7ba1afbca87fba7b98f31697cba6776b1b Mon Sep 17 00:00:00 2001 -From: Tomeu Vizoso -Date: Mon, 16 Oct 2023 10:02:03 +0200 -Subject: [PATCH 11/53] FROMGIT(6.9): arm64: dts: meson-g12-common: Set the - rates of the clocks for the NPU - -Otherwise they are left at 24MHz and the NPU runs very slowly. - -Signed-off-by: Tomeu Vizoso -Suggested-by: Lucas Stach ---- - arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi -index f7f8df88d464..a960d07f9af3 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi -@@ -2502,6 +2502,9 @@ npu: npu@ff100000 { - clocks = <&clkc CLKID_NNA_CORE_CLK>, - <&clkc CLKID_NNA_AXI_CLK>; - clock-names = "core", "bus"; -+ assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>, -+ <&clkc CLKID_NNA_AXI_CLK>; -+ assigned-clock-rates = <800000000>, <800000000>; - resets = <&reset RESET_NNA>; - status = "disabled"; - }; --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0012-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-low-speed-wi.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0012-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-low-speed-wi.patch new file mode 100644 index 0000000000..1b9a997c43 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0012-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-low-speed-wi.patch @@ -0,0 +1,83 @@ +From 93f781bf3955bd65a73ad8878c6f76439cdd4aaf Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 25 Apr 2024 21:12:38 +0300 +Subject: [PATCH 12/69] FROMGIT(6.10): wifi: rtlwifi: rtl8192de: Fix low speed + with WPA3-SAE + +Some (all?) management frames are incorrectly reported to mac80211 as +decrypted when actually the hardware did not decrypt them. This results +in speeds 3-5 times lower than expected, 20-30 Mbps instead of 100 +Mbps. + +Fix this by checking the encryption type field of the RX descriptor. +rtw88 does the same thing. + +This fix was tested only with rtl8192du, which will use the same code. + +Cc: stable@vger.kernel.org +Signed-off-by: Bitterblue Smith +Signed-off-by: Ping-Ke Shih +Link: https://msgid.link/4d600435-f0ea-46b0-bdb4-e60f173da8dd@gmail.com +--- + .../net/wireless/realtek/rtlwifi/rtl8192de/trx.c | 5 ++--- + .../net/wireless/realtek/rtlwifi/rtl8192de/trx.h | 14 ++++++++++++++ + 2 files changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +index 192982ec8152..30b262c3f6d0 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +@@ -413,7 +413,8 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, + stats->icv = (u16)get_rx_desc_icv(pdesc); + stats->crc = (u16)get_rx_desc_crc32(pdesc); + stats->hwerror = (stats->crc | stats->icv); +- stats->decrypted = !get_rx_desc_swdec(pdesc); ++ stats->decrypted = !get_rx_desc_swdec(pdesc) && ++ get_rx_desc_enc_type(pdesc) != RX_DESC_ENC_NONE; + stats->rate = (u8)get_rx_desc_rxmcs(pdesc); + stats->shortpreamble = (u16)get_rx_desc_splcp(pdesc); + stats->isampdu = (bool)(get_rx_desc_paggr(pdesc) == 1); +@@ -426,8 +427,6 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, + rx_status->band = hw->conf.chandef.chan->band; + if (get_rx_desc_crc32(pdesc)) + rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; +- if (!get_rx_desc_swdec(pdesc)) +- rx_status->flag |= RX_FLAG_DECRYPTED; + if (get_rx_desc_bw(pdesc)) + rx_status->bw = RATE_INFO_BW_40; + if (get_rx_desc_rxht(pdesc)) +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +index 2992668c156c..f189ee2d9be2 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +@@ -14,6 +14,15 @@ + #define USB_HWDESC_HEADER_LEN 32 + #define CRCLENGTH 4 + ++enum rtl92d_rx_desc_enc { ++ RX_DESC_ENC_NONE = 0, ++ RX_DESC_ENC_WEP40 = 1, ++ RX_DESC_ENC_TKIP_WO_MIC = 2, ++ RX_DESC_ENC_TKIP_MIC = 3, ++ RX_DESC_ENC_AES = 4, ++ RX_DESC_ENC_WEP104 = 5, ++}; ++ + /* macros to read/write various fields in RX or TX descriptors */ + + static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val) +@@ -246,6 +255,11 @@ static inline u32 get_rx_desc_drv_info_size(__le32 *__pdesc) + return le32_get_bits(*__pdesc, GENMASK(19, 16)); + } + ++static inline u32 get_rx_desc_enc_type(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, GENMASK(22, 20)); ++} ++ + static inline u32 get_rx_desc_shift(__le32 *__pdesc) + { + return le32_get_bits(*__pdesc, GENMASK(25, 24)); +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0012-FROMGIT-6.9-arm64-dts-amlogic-replace-underscores-in.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0012-FROMGIT-6.9-arm64-dts-amlogic-replace-underscores-in.patch deleted file mode 100644 index eea4349c90..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0012-FROMGIT-6.9-arm64-dts-amlogic-replace-underscores-in.patch +++ /dev/null @@ -1,1667 +0,0 @@ -From 9a7fc97f7f23a93a23d3325a3a01ec4df23ac274 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Tue, 13 Feb 2024 15:32:17 +0100 -Subject: [PATCH 12/53] FROMGIT(6.9): arm64: dts: amlogic: replace underscores - in node names - -Underscores should not be used in node names (dtc with W=2 warns about -them), so replace them with hyphens. - -Cc: Marc Gonzalez -Signed-off-by: Krzysztof Kozlowski -Reviewed-by: Neil Armstrong ---- - .../arm64/boot/dts/amlogic/meson-a1-ad402.dts | 2 +- - .../meson-axg-jethome-jethub-j1xx.dtsi | 14 ++++++------- - .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 16 +++++++-------- - .../dts/amlogic/meson-g12a-radxa-zero.dts | 12 +++++------ - .../boot/dts/amlogic/meson-g12a-sei510.dts | 14 ++++++------- - .../boot/dts/amlogic/meson-g12a-u200.dts | 16 +++++++-------- - .../boot/dts/amlogic/meson-g12a-x96-max.dts | 14 ++++++------- - .../dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +- - .../boot/dts/amlogic/meson-g12b-odroid.dtsi | 20 +++++++++---------- - .../boot/dts/amlogic/meson-g12b-w400.dtsi | 10 +++++----- - .../dts/amlogic/meson-gx-libretech-pc.dtsi | 12 +++++------ - .../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 8 ++++---- - .../dts/amlogic/meson-gxbb-nexbox-a95x.dts | 6 +++--- - .../boot/dts/amlogic/meson-gxbb-odroidc2.dts | 8 ++++---- - .../boot/dts/amlogic/meson-gxbb-p200.dts | 4 ++-- - .../boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 +++--- - .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 8 ++++---- - .../boot/dts/amlogic/meson-gxbb-wetek.dtsi | 8 ++++---- - .../amlogic/meson-gxl-s805x-libretech-ac.dts | 8 ++++---- - .../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 8 ++++---- - .../meson-gxl-s905w-jethome-jethub-j80.dts | 8 ++++---- - .../meson-gxl-s905x-hwacom-amazetv.dts | 6 +++--- - .../meson-gxl-s905x-libretech-cc-v2.dts | 12 +++++------ - .../amlogic/meson-gxl-s905x-libretech-cc.dts | 6 +++--- - .../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 6 +++--- - .../dts/amlogic/meson-gxl-s905x-p212.dtsi | 8 ++++---- - .../dts/amlogic/meson-gxm-khadas-vim2.dts | 8 ++++---- - .../amlogic/meson-gxm-s912-libretech-pc.dts | 2 +- - .../boot/dts/amlogic/meson-khadas-vim3.dtsi | 16 +++++++-------- - .../amlogic/meson-libretech-cottonwood.dtsi | 6 +++--- - .../boot/dts/amlogic/meson-sm1-ac2xx.dtsi | 10 +++++----- - .../boot/dts/amlogic/meson-sm1-bananapi.dtsi | 14 ++++++------- - .../boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 4 ++-- - .../boot/dts/amlogic/meson-sm1-odroid.dtsi | 20 +++++++++---------- - .../boot/dts/amlogic/meson-sm1-sei610.dts | 12 +++++------ - 35 files changed, 167 insertions(+), 167 deletions(-) - -diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts -index 1c20516fa653..4bc30af05848 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts -@@ -106,7 +106,7 @@ &spifc { - pinctrl-0 = <&spifc_pins>; - pinctrl-names = "default"; - -- spi_nand@0 { -+ flash@0 { - compatible = "spi-nand"; - status = "okay"; - reg = <0>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi -index db605f3a22b4..a53e1fe9ac1e 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi -@@ -35,7 +35,7 @@ emmc_pwrseq: emmc-pwrseq { - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -44,7 +44,7 @@ vcc_3v3: regulator-vcc_3v3 { - regulator-always-on; - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; -@@ -52,7 +52,7 @@ vcc_5v: regulator-vcc_5v { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -@@ -61,7 +61,7 @@ vddao_3v3: regulator-vddao_3v3 { - regulator-always-on; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -70,7 +70,7 @@ vddio_ao18: regulator-vddio_ao18 { - regulator-always-on; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <3300000>; -@@ -79,7 +79,7 @@ vddio_boot: regulator-vddio_boot { - regulator-always-on; - }; - -- vccq_1v8: regulator-vccq_1v8 { -+ vccq_1v8: regulator-vccq-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCCQ_1V8"; - regulator-min-microvolt = <1800000>; -@@ -88,7 +88,7 @@ vccq_1v8: regulator-vccq_1v8 { - regulator-always-on; - }; - -- usb_pwr: regulator-usb_pwr { -+ usb_pwr: regulator-usb-pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts -index c8905663bc75..7ed526f45175 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts -@@ -12,7 +12,7 @@ / { - compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; - model = "Amlogic Meson AXG S400 Development Board"; - -- adc_keys { -+ keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; -@@ -111,7 +111,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x40000000>; - }; - -- main_12v: regulator-main_12v { -+ main_12v: regulator-main-12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; -@@ -119,7 +119,7 @@ main_12v: regulator-main_12v { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -128,7 +128,7 @@ vcc_3v3: regulator-vcc_3v3 { - regulator-always-on; - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; -@@ -139,7 +139,7 @@ vcc_5v: regulator-vcc_5v { - enable-active-high; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -@@ -148,7 +148,7 @@ vddao_3v3: regulator-vddao_3v3 { - regulator-always-on; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -157,7 +157,7 @@ vddio_ao18: regulator-vddio_ao18 { - regulator-always-on; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; -@@ -166,7 +166,7 @@ vddio_boot: regulator-vddio_boot { - regulator-always-on; - }; - -- usb_pwr: regulator-usb_pwr { -+ usb_pwr: regulator-usb-pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts -index fcd7e1d8e16f..15b9bc280706 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts -@@ -60,7 +60,7 @@ sdio_pwrseq: sdio-pwrseq { - clock-names = "ext_clock"; - }; - -- ao_5v: regulator-ao_5v { -+ ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; -@@ -68,7 +68,7 @@ ao_5v: regulator-ao_5v { - regulator-always-on; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -77,7 +77,7 @@ vcc_1v8: regulator-vcc_1v8 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -86,7 +86,7 @@ vcc_3v3: regulator-vcc_3v3 { - regulator-always-on; - }; - -- hdmi_pw: regulator-hdmi_pw { -+ hdmi_pw: regulator-hdmi-pw { - compatible = "regulator-fixed"; - regulator-name = "HDMI_PW"; - regulator-min-microvolt = <5000000>; -@@ -95,7 +95,7 @@ hdmi_pw: regulator-hdmi_pw { - regulator-always-on; - }; - -- vddao_1v8: regulator-vddao_1v8 { -+ vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; -@@ -104,7 +104,7 @@ vddao_1v8: regulator-vddao_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts -index 4c4550dd4711..61cb8135a392 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts -@@ -15,7 +15,7 @@ / { - compatible = "seirobotics,sei510", "amlogic,g12a"; - model = "SEI Robotics SEI510"; - -- adc_keys { -+ keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; -@@ -83,7 +83,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x40000000>; - }; - -- ao_5v: regulator-ao_5v { -+ ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; -@@ -92,7 +92,7 @@ ao_5v: regulator-ao_5v { - regulator-always-on; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -100,7 +100,7 @@ dc_in: regulator-dc_in { - regulator-always-on; - }; - -- emmc_1v8: regulator-emmc_1v8 { -+ emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -109,7 +109,7 @@ emmc_1v8: regulator-emmc_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -@@ -118,7 +118,7 @@ vddao_3v3: regulator-vddao_3v3 { - regulator-always-on; - }; - -- vddao_3v3_t: regultor-vddao_3v3_t { -+ vddao_3v3_t: regulator-vddao-3v3-t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; -@@ -147,7 +147,7 @@ vddcpu: regulator-vddcpu { - regulator-always-on; - }; - -- vddio_ao1v8: regulator-vddio_ao1v8 { -+ vddio_ao1v8: regulator-vddio-ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts -index 8355ddd7e9ae..3da7922d83f1 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts -@@ -75,7 +75,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x40000000>; - }; - -- flash_1v8: regulator-flash_1v8 { -+ flash_1v8: regulator-flash-1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; -@@ -84,7 +84,7 @@ flash_1v8: regulator-flash_1v8 { - regulator-always-on; - }; - -- main_12v: regulator-main_12v { -+ main_12v: regulator-main-12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; -@@ -92,7 +92,7 @@ main_12v: regulator-main_12v { - regulator-always-on; - }; - -- usb_pwr_en: regulator-usb_pwr_en { -+ usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; -@@ -103,7 +103,7 @@ usb_pwr_en: regulator-usb_pwr_en { - enable-active-high; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -112,7 +112,7 @@ vcc_1v8: regulator-vcc_1v8 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -122,7 +122,7 @@ vcc_3v3: regulator-vcc_3v3 { - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; -@@ -133,7 +133,7 @@ vcc_5v: regulator-vcc_5v { - enable-active-high; - }; - -- vddao_1v8: regulator-vddao_1v8 { -+ vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; -@@ -142,7 +142,7 @@ vddao_1v8: regulator-vddao_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts -index 9b55982b6a6b..05c7a1e3f1b7 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts -@@ -66,7 +66,7 @@ sdio_pwrseq: sdio-pwrseq { - clock-names = "ext_clock"; - }; - -- flash_1v8: regulator-flash_1v8 { -+ flash_1v8: regulator-flash-1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; -@@ -75,7 +75,7 @@ flash_1v8: regulator-flash_1v8 { - regulator-always-on; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -83,7 +83,7 @@ dc_in: regulator-dc_in { - regulator-always-on; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -92,7 +92,7 @@ vcc_1v8: regulator-vcc_1v8 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -102,7 +102,7 @@ vcc_3v3: regulator-vcc_3v3 { - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; -@@ -112,7 +112,7 @@ vcc_5v: regulator-vcc_5v { - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - }; - -- vddao_1v8: regulator-vddao_1v8 { -+ vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; -@@ -121,7 +121,7 @@ vddao_1v8: regulator-vddao_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi -index 91c9769fda20..d80dd9a3da31 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi -@@ -19,7 +19,7 @@ dio2133: audio-amplifier-0 { - status = "okay"; - }; - -- hub_5v: regulator-hub_5v { -+ hub_5v: regulator-hub-5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi -index 9e12a34b2840..09d959aefb18 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi -@@ -48,7 +48,7 @@ led-blue { - }; - }; - -- tflash_vdd: regulator-tflash_vdd { -+ tflash_vdd: regulator-tflash-vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; -@@ -60,7 +60,7 @@ tflash_vdd: regulator-tflash_vdd { - regulator-always-on; - }; - -- tf_io: gpio-regulator-tf_io { -+ tf_io: gpio-regulator-tf-io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; -@@ -74,7 +74,7 @@ tf_io: gpio-regulator-tf_io { - <1800000 1>; - }; - -- flash_1v8: regulator-flash_1v8 { -+ flash_1v8: regulator-flash-1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; -@@ -83,7 +83,7 @@ flash_1v8: regulator-flash_1v8 { - regulator-always-on; - }; - -- main_12v: regulator-main_12v { -+ main_12v: regulator-main-12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; -@@ -91,7 +91,7 @@ main_12v: regulator-main_12v { - regulator-always-on; - }; - -- usb_pwr_en: regulator-usb_pwr_en { -+ usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; -@@ -103,7 +103,7 @@ usb_pwr_en: regulator-usb_pwr_en { - enable-active-high; - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; -@@ -114,7 +114,7 @@ vcc_5v: regulator-vcc_5v { - enable-active-high; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -123,7 +123,7 @@ vcc_1v8: regulator-vcc_1v8 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -171,7 +171,7 @@ vddcpu_b: regulator-vddcpu-b { - regulator-always-on; - }; - -- vddao_1v8: regulator-vddao_1v8 { -+ vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; -@@ -180,7 +180,7 @@ vddao_1v8: regulator-vddao_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi -index ac8b7178257e..4cb6930ffb19 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi -@@ -39,7 +39,7 @@ sdio_pwrseq: sdio-pwrseq { - clock-names = "ext_clock"; - }; - -- flash_1v8: regulator-flash_1v8 { -+ flash_1v8: regulator-flash-1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; -@@ -48,7 +48,7 @@ flash_1v8: regulator-flash_1v8 { - regulator-always-on; - }; - -- main_12v: regulator-main_12v { -+ main_12v: regulator-main-12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; -@@ -56,7 +56,7 @@ main_12v: regulator-main_12v { - regulator-always-on; - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; -@@ -67,7 +67,7 @@ vcc_5v: regulator-vcc_5v { - enable-active-high; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -76,7 +76,7 @@ vcc_1v8: regulator-vcc_1v8 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi -index 5e7b9273b062..efd662a452e8 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi -@@ -84,7 +84,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x80000000>; - }; - -- ao_5v: regulator-ao_5v { -+ ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; -@@ -93,7 +93,7 @@ ao_5v: regulator-ao_5v { - regulator-always-on; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -120,7 +120,7 @@ led-blue { - }; - }; - -- vcc_card: regulator-vcc_card { -+ vcc_card: regulator-vcc-card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; -@@ -141,7 +141,7 @@ vcc5v: regulator-vcc5v { - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -150,7 +150,7 @@ vddio_ao18: regulator-vddio_ao18 { - regulator-always-on; - }; - -- vddio_ao3v3: regulator-vddio_ao3v3 { -+ vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; -@@ -159,7 +159,7 @@ vddio_ao3v3: regulator-vddio_ao3v3 { - regulator-always-on; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi -index e59c3c92b1e7..08d6b69ba469 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi -@@ -50,28 +50,28 @@ hdmi_5v: regulator-hdmi-5v { - regulator-always-on; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts -index 4aab1ab705b4..cca129ce2c58 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts -@@ -78,21 +78,21 @@ vddio_card: gpio-regulator { - <3300000 1>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts -index e6d2de7c45a9..c431986e6a33 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts -@@ -67,7 +67,7 @@ p5v0: regulator-p5v0 { - regulator-always-on; - }; - -- hdmi_p5v0: regulator-hdmi_p5v0 { -+ hdmi_p5v0: regulator-hdmi-p5v0 { - compatible = "regulator-fixed"; - regulator-name = "HDMI_P5V0"; - regulator-min-microvolt = <5000000>; -@@ -76,7 +76,7 @@ hdmi_p5v0: regulator-hdmi_p5v0 { - vin-supply = <&p5v0>; - }; - -- tflash_vdd: regulator-tflash_vdd { -+ tflash_vdd: regulator-tflash-vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; -@@ -92,7 +92,7 @@ tflash_vdd: regulator-tflash_vdd { - vin-supply = <&vddio_ao3v3>; - }; - -- tf_io: gpio-regulator-tf_io { -+ tf_io: gpio-regulator-tf-io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; -@@ -148,7 +148,7 @@ vddio_ao3v3: regulator-vddio-ao3v3 { - vin-supply = <&p5v0>; - }; - -- ddr3_1v5: regulator-ddr3_1v5 { -+ ddr3_1v5: regulator-ddr3-1v5 { - compatible = "regulator-fixed"; - regulator-name = "DDR3_1V5"; - regulator-min-microvolt = <1500000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts -index 591455c50e88..7f94716876d3 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts -@@ -21,14 +21,14 @@ spdif_dit: audio-codec-0 { - sound-name-prefix = "DIT"; - }; - -- avdd18_usb_adc: regulator-avdd18_usb_adc { -+ avdd18_usb_adc: regulator-avdd18-usb-adc { - compatible = "regulator-fixed"; - regulator-name = "AVDD18_USB_ADC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- adc_keys { -+ keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi -index e803a466fe4e..52d57773a77f 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi -@@ -53,21 +53,21 @@ vddio_card: gpio-regulator { - regulator-settling-time-down-us = <150000>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi -index 74df32534231..255e93a0b36d 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi -@@ -47,28 +47,28 @@ usb_pwr: regulator-usb-pwrs { - enable-active-high; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi -index 94dafb955301..deb295227189 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi -@@ -49,21 +49,21 @@ usb_pwr: regulator-usb-pwrs { - enable-active-high; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -71,7 +71,7 @@ vddio_ao18: regulator-vddio_ao18 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts -index a29b49f051ae..90ef9c17d80b 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts -@@ -42,7 +42,7 @@ cvbs_connector_in: endpoint { - }; - }; - -- dc_5v: regulator-dc_5v { -+ dc_5v: regulator-dc-5v { - compatible = "regulator-fixed"; - regulator-name = "DC_5V"; - regulator-min-microvolt = <5000000>; -@@ -89,7 +89,7 @@ vcck: regulator-vcck { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -98,7 +98,7 @@ vcc_3v3: regulator-vcc_3v3 { - regulator-always-on; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -107,7 +107,7 @@ vddio_ao18: regulator-vddio_ao18 { - regulator-always-on; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts -index c0d6eb55100a..08a4718219b1 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts -@@ -64,28 +64,28 @@ memory@0 { - reg = <0x0 0x0 0x0 0x20000000>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts -index a18d6d241a5a..2b94b6e5285e 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts -@@ -37,28 +37,28 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts -index c8d74e61dec1..89fe5110f7a2 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts -@@ -42,21 +42,21 @@ vddio_card: gpio-regulator { - <3300000 1>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts -index 2825db91e462..63b20860067c 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts -@@ -67,7 +67,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x80000000>; - }; - -- ao_5v: regulator-ao_5v { -+ ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; -@@ -76,7 +76,7 @@ ao_5v: regulator-ao_5v { - regulator-always-on; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -93,7 +93,7 @@ vcck: regulator-vcck { - regulator-always-on; - }; - -- vcc_card: regulator-vcc_card { -+ vcc_card: regulator-vcc-card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; -@@ -114,7 +114,7 @@ vcc5v: regulator-vcc5v { - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - -- vddio_ao3v3: regulator-vddio_ao3v3 { -+ vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; -@@ -139,7 +139,7 @@ vddio_card: regulator-vddio-card { - regulator-settling-time-down-us = <50000>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -148,7 +148,7 @@ vddio_ao18: regulator-vddio_ao18 { - regulator-always-on; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC 1V8"; - regulator-min-microvolt = <1800000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts -index 27093e6ac9e2..8b26c9661be1 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts -@@ -93,7 +93,7 @@ hdmi_5v: regulator-hdmi-5v { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -117,7 +117,7 @@ vcc_card: regulator-vcc-card { - regulator-settling-time-down-us = <50000>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -125,7 +125,7 @@ vddio_ao18: regulator-vddio_ao18 { - }; - - /* This is provided by LDOs on the eMMC daugther card */ -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts -index f1acca5c4434..c79f9f2099bf 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts -@@ -42,21 +42,21 @@ vddio_card: gpio-regulator { - <3300000 1>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi -index a150cc0e18ff..7e7dc87ede2d 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi -@@ -39,28 +39,28 @@ hdmi_5v: regulator-hdmi-5v { - regulator-always-on; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts -index cee27e7222c8..a03269a00486 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts -@@ -114,28 +114,28 @@ hdmi_5v: regulator-hdmi-5v { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddio_boot: regulator-vddio_boot { -+ vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts -index 4eda9f634c42..a66f19851ac9 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts -@@ -14,7 +14,7 @@ / { - "amlogic,meson-gxm"; - model = "Libre Computer AML-S912-PC"; - -- typec2_vbus: regulator-typec2_vbus { -+ typec2_vbus: regulator-typec2-vbus { - compatible = "regulator-fixed"; - regulator-name = "TYPEC2_VBUS"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi -index 514a6dd4b124..e78cc9b577a0 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi -@@ -80,7 +80,7 @@ sdio_pwrseq: sdio-pwrseq { - clock-names = "ext_clock"; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -88,7 +88,7 @@ dc_in: regulator-dc_in { - regulator-always-on; - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; -@@ -99,7 +99,7 @@ vcc_5v: regulator-vcc_5v { - enable-active-high; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -108,7 +108,7 @@ vcc_1v8: regulator-vcc_1v8 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -118,7 +118,7 @@ vcc_3v3: regulator-vcc_3v3 { - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - -- vddao_1v8: regulator-vddao_1v8 { -+ vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; -@@ -127,7 +127,7 @@ vddao_1v8: regulator-vddao_1v8 { - regulator-always-on; - }; - -- emmc_1v8: regulator-emmc_1v8 { -+ emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_AO1V8"; - regulator-min-microvolt = <1800000>; -@@ -136,7 +136,7 @@ emmc_1v8: regulator-emmc_1v8 { - regulator-always-on; - }; - -- vsys_3v3: regulator-vsys_3v3 { -+ vsys_3v3: regulator-vsys-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V3"; - regulator-min-microvolt = <3300000>; -@@ -145,7 +145,7 @@ vsys_3v3: regulator-vsys_3v3 { - regulator-always-on; - }; - -- usb_pwr: regulator-usb_pwr { -+ usb_pwr: regulator-usb-pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi -index 35e8f5bae990..082b72703cdf 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi -@@ -150,7 +150,7 @@ vcc_5v: regulator-vcc-5v { - gpio-open-drain; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -@@ -171,7 +171,7 @@ vddcpu_b: regulator-vddcpu-b { - pwm-dutycycle-range = <100 0>; - }; - -- vddio_ao18: regulator-vddio_ao18 { -+ vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; -@@ -180,7 +180,7 @@ vddio_ao18: regulator-vddio_ao18 { - vin-supply = <&vddao_3v3>; - }; - -- vddio_c: regulator-vddio_c { -+ vddio_c: regulator-vddio-c { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_C"; - regulator-min-microvolt = <1800000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi -index 46a34731f7e2..d1fa8b8bf795 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi -@@ -54,7 +54,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x40000000>; - }; - -- ao_5v: regulator-ao_5v { -+ ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; -@@ -63,7 +63,7 @@ ao_5v: regulator-ao_5v { - regulator-always-on; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -71,7 +71,7 @@ dc_in: regulator-dc_in { - regulator-always-on; - }; - -- emmc_1v8: regulator-emmc_1v8 { -+ emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -80,7 +80,7 @@ emmc_1v8: regulator-emmc_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -@@ -105,7 +105,7 @@ vddcpu: regulator-vddcpu { - regulator-always-on; - }; - -- vddio_ao1v8: regulator-vddio_ao1v8 { -+ vddio_ao1v8: regulator-vddio-ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi -index 62404743e62d..81dce862902a 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi -@@ -82,7 +82,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x40000000>; - }; - -- emmc_1v8: regulator-emmc_1v8 { -+ emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -91,7 +91,7 @@ emmc_1v8: regulator-emmc_1v8 { - regulator-always-on; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -99,7 +99,7 @@ dc_in: regulator-dc_in { - regulator-always-on; - }; - -- vddio_c: regulator-vddio_c { -+ vddio_c: regulator-vddio-c { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_C"; - regulator-min-microvolt = <1800000>; -@@ -116,7 +116,7 @@ vddio_c: regulator-vddio_c { - <3300000 1>; - }; - -- tflash_vdd: regulator-tflash_vdd { -+ tflash_vdd: regulator-tflash-vdd { - compatible = "regulator-fixed"; - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; -@@ -127,7 +127,7 @@ tflash_vdd: regulator-tflash_vdd { - regulator-always-on; - }; - -- vddao_1v8: regulator-vddao_1v8 { -+ vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; -@@ -136,7 +136,7 @@ vddao_1v8: regulator-vddao_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -@@ -165,7 +165,7 @@ vddcpu: regulator-vddcpu { - }; - - /* USB Hub Power Enable */ -- vl_pwr_en: regulator-vl_pwr_en { -+ vl_pwr_en: regulator-vl-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "VL_PWR_EN"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts -index 846a2d6c20e5..0170139b8d32 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts -@@ -43,7 +43,7 @@ led-red { - }; - - /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ -- p12v_0: regulator-p12v_0 { -+ p12v_0: regulator-p12v-0 { - compatible = "regulator-fixed"; - regulator-name = "P12V_0"; - regulator-min-microvolt = <12000000>; -@@ -56,7 +56,7 @@ p12v_0: regulator-p12v_0 { - }; - - /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ -- p12v_1: regulator-p12v_1 { -+ p12v_1: regulator-p12v-1 { - compatible = "regulator-fixed"; - regulator-name = "P12V_1"; - regulator-min-microvolt = <12000000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi -index 1db2327bbd13..951eb8e3f0c0 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi -+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi -@@ -28,7 +28,7 @@ emmc_pwrseq: emmc-pwrseq { - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - -- tflash_vdd: regulator-tflash_vdd { -+ tflash_vdd: regulator-tflash-vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; -@@ -40,7 +40,7 @@ tflash_vdd: regulator-tflash_vdd { - regulator-always-on; - }; - -- tf_io: gpio-regulator-tf_io { -+ tf_io: gpio-regulator-tf-io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; -@@ -59,7 +59,7 @@ tf_io: gpio-regulator-tf_io { - <1800000 1>; - }; - -- flash_1v8: regulator-flash_1v8 { -+ flash_1v8: regulator-flash-1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; -@@ -68,7 +68,7 @@ flash_1v8: regulator-flash_1v8 { - regulator-always-on; - }; - -- main_12v: regulator-main_12v { -+ main_12v: regulator-main-12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; -@@ -76,7 +76,7 @@ main_12v: regulator-main_12v { - regulator-always-on; - }; - -- vcc_5v: regulator-vcc_5v { -+ vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; -@@ -87,7 +87,7 @@ vcc_5v: regulator-vcc_5v { - enable-active-high; - }; - -- vcc_1v8: regulator-vcc_1v8 { -+ vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -96,7 +96,7 @@ vcc_1v8: regulator-vcc_1v8 { - regulator-always-on; - }; - -- vcc_3v3: regulator-vcc_3v3 { -+ vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; -@@ -125,7 +125,7 @@ vddcpu: regulator-vddcpu { - regulator-always-on; - }; - -- usb_pwr_en: regulator-usb_pwr_en { -+ usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; -@@ -137,7 +137,7 @@ usb_pwr_en: regulator-usb_pwr_en { - enable-active-high; - }; - -- vddao_1v8: regulator-vddao_1v8 { -+ vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; -@@ -146,7 +146,7 @@ vddao_1v8: regulator-vddao_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts -index 109932068dbe..3581e14cbf18 100644 ---- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts -+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts -@@ -127,7 +127,7 @@ memory@0 { - reg = <0x0 0x0 0x0 0x40000000>; - }; - -- ao_5v: regulator-ao_5v { -+ ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; -@@ -136,7 +136,7 @@ ao_5v: regulator-ao_5v { - regulator-always-on; - }; - -- dc_in: regulator-dc_in { -+ dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; -@@ -144,7 +144,7 @@ dc_in: regulator-dc_in { - regulator-always-on; - }; - -- emmc_1v8: regulator-emmc_1v8 { -+ emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; -@@ -153,7 +153,7 @@ emmc_1v8: regulator-emmc_1v8 { - regulator-always-on; - }; - -- vddao_3v3: regulator-vddao_3v3 { -+ vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; -@@ -163,7 +163,7 @@ vddao_3v3: regulator-vddao_3v3 { - }; - - /* Used by Tuner, RGB Led & IR Emitter LED array */ -- vddao_3v3_t: regulator-vddao_3v3_t { -+ vddao_3v3_t: regulator-vddao-3v3-t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; -@@ -192,7 +192,7 @@ vddcpu: regulator-vddcpu { - regulator-always-on; - }; - -- vddio_ao1v8: regulator-vddio_ao1v8 { -+ vddio_ao1v8: regulator-vddio-ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0013-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-endianness-i.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0013-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-endianness-i.patch new file mode 100644 index 0000000000..5194a48e79 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0013-FROMGIT-6.10-wifi-rtlwifi-rtl8192de-Fix-endianness-i.patch @@ -0,0 +1,174 @@ +From 91b01523927c0e78c0c53c0c8347ee9d194d34f0 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 25 Apr 2024 21:13:12 +0300 +Subject: [PATCH 13/69] FROMGIT(6.10): wifi: rtlwifi: rtl8192de: Fix endianness + issue in RX path + +Structs rx_desc_92d and rx_fwinfo_92d will not work for big endian +systems. + +Delete rx_desc_92d because it's big and barely used, and instead use +the get_rx_desc_rxmcs and get_rx_desc_rxht functions, which work on big +endian systems too. + +Fix rx_fwinfo_92d by duplicating four of its members in the correct +order. + +Tested only with RTL8192DU, which will use the same code. +Tested only on a little endian system. + +Cc: stable@vger.kernel.org +Signed-off-by: Bitterblue Smith +Signed-off-by: Ping-Ke Shih +Link: https://msgid.link/698463da-5ef1-40c7-b744-fa51ad847caf@gmail.com +--- + .../wireless/realtek/rtlwifi/rtl8192de/trx.c | 16 ++--- + .../wireless/realtek/rtlwifi/rtl8192de/trx.h | 65 ++----------------- + 2 files changed, 15 insertions(+), 66 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +index 30b262c3f6d0..cbc7b4dbea9a 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +@@ -35,7 +35,7 @@ static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, + + static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, + struct rtl_stats *pstats, +- struct rx_desc_92d *pdesc, ++ __le32 *pdesc, + struct rx_fwinfo_92d *p_drvinfo, + bool packet_match_bssid, + bool packet_toself, +@@ -50,8 +50,10 @@ static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, + u8 i, max_spatial_stream; + u32 rssi, total_rssi = 0; + bool is_cck_rate; ++ u8 rxmcs; + +- is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc->rxmcs); ++ rxmcs = get_rx_desc_rxmcs(pdesc); ++ is_cck_rate = rxmcs <= DESC_RATE11M; + pstats->packet_matchbssid = packet_match_bssid; + pstats->packet_toself = packet_toself; + pstats->packet_beacon = packet_beacon; +@@ -157,8 +159,8 @@ static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, + pstats->rx_pwdb_all = pwdb_all; + pstats->rxpower = rx_pwr_all; + pstats->recvsignalpower = rx_pwr_all; +- if (pdesc->rxht && pdesc->rxmcs >= DESC_RATEMCS8 && +- pdesc->rxmcs <= DESC_RATEMCS15) ++ if (get_rx_desc_rxht(pdesc) && rxmcs >= DESC_RATEMCS8 && ++ rxmcs <= DESC_RATEMCS15) + max_spatial_stream = 2; + else + max_spatial_stream = 1; +@@ -364,7 +366,7 @@ static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw, + static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, + struct sk_buff *skb, + struct rtl_stats *pstats, +- struct rx_desc_92d *pdesc, ++ __le32 *pdesc, + struct rx_fwinfo_92d *p_drvinfo) + { + struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +@@ -440,9 +442,7 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, + if (phystatus) { + p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + + stats->rx_bufshift); +- _rtl92de_translate_rx_signal_stuff(hw, +- skb, stats, +- (struct rx_desc_92d *)pdesc, ++ _rtl92de_translate_rx_signal_stuff(hw, skb, stats, pdesc, + p_drvinfo); + } + /*rx_status->qual = stats->signal; */ +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +index f189ee2d9be2..2d4887490f00 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +@@ -394,10 +394,17 @@ struct rx_fwinfo_92d { + u8 csi_target[2]; + u8 sigevm; + u8 max_ex_pwr; ++#ifdef __LITTLE_ENDIAN + u8 ex_intf_flag:1; + u8 sgi_en:1; + u8 rxsc:2; + u8 reserve:4; ++#else ++ u8 reserve:4; ++ u8 rxsc:2; ++ u8 sgi_en:1; ++ u8 ex_intf_flag:1; ++#endif + } __packed; + + struct tx_desc_92d { +@@ -502,64 +509,6 @@ struct tx_desc_92d { + u32 reserve_pass_pcie_mm_limit[4]; + } __packed; + +-struct rx_desc_92d { +- u32 length:14; +- u32 crc32:1; +- u32 icverror:1; +- u32 drv_infosize:4; +- u32 security:3; +- u32 qos:1; +- u32 shift:2; +- u32 phystatus:1; +- u32 swdec:1; +- u32 lastseg:1; +- u32 firstseg:1; +- u32 eor:1; +- u32 own:1; +- +- u32 macid:5; +- u32 tid:4; +- u32 hwrsvd:5; +- u32 paggr:1; +- u32 faggr:1; +- u32 a1_fit:4; +- u32 a2_fit:4; +- u32 pam:1; +- u32 pwr:1; +- u32 moredata:1; +- u32 morefrag:1; +- u32 type:2; +- u32 mc:1; +- u32 bc:1; +- +- u32 seq:12; +- u32 frag:4; +- u32 nextpktlen:14; +- u32 nextind:1; +- u32 rsvd:1; +- +- u32 rxmcs:6; +- u32 rxht:1; +- u32 amsdu:1; +- u32 splcp:1; +- u32 bandwidth:1; +- u32 htc:1; +- u32 tcpchk_rpt:1; +- u32 ipcchk_rpt:1; +- u32 tcpchk_valid:1; +- u32 hwpcerr:1; +- u32 hwpcind:1; +- u32 iv0:16; +- +- u32 iv1; +- +- u32 tsfl; +- +- u32 bufferaddress; +- u32 bufferaddress64; +- +-} __packed; +- + void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, + struct ieee80211_hdr *hdr, u8 *pdesc, + u8 *pbd_desc_tx, struct ieee80211_tx_info *info, +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0014-FROMGIT-6.10-wifi-rtlwifi-Move-code-from-rtl8192de-t.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0014-FROMGIT-6.10-wifi-rtlwifi-Move-code-from-rtl8192de-t.patch new file mode 100644 index 0000000000..2712aa8b85 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0014-FROMGIT-6.10-wifi-rtlwifi-Move-code-from-rtl8192de-t.patch @@ -0,0 +1,11050 @@ +From eb9c40199ae9ae29f43705a11b7a0dba79dcfb8b Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 25 Apr 2024 21:14:04 +0300 +Subject: [PATCH 14/69] FROMGIT(6.10): wifi: rtlwifi: Move code from rtl8192de + to rtl8192d-common + +Create the new module rtl8192d-common and move some code into it from +rtl8192de. Now the rtl8192de driver (PCI) and the new rtl8192du driver +(USB) can share some of the code. + +This is mostly the code that required little effort to make it +shareable. There are a few more functions which they could share, with +more changes. + +Add phy_iq_calibrate member to struct rtl_hal_ops to allow moving the +TX power tracking code from dm.c. + +The other changes in this patch are adjusting whitespace, renaming some +functions, making some arrays const, and making checkpatch.pl less +unhappy. + +rtl8192de is compile-tested only. rtl8192d-common is tested with the +new rtl8192du driver. + +Signed-off-by: Bitterblue Smith +Signed-off-by: Ping-Ke Shih +Link: https://msgid.link/69c4358a-6fbf-4433-92a6-341c83e9dd48@gmail.com +--- + drivers/net/wireless/realtek/rtlwifi/Kconfig | 4 + + drivers/net/wireless/realtek/rtlwifi/Makefile | 1 + + drivers/net/wireless/realtek/rtlwifi/cam.c | 5 +- + drivers/net/wireless/realtek/rtlwifi/cam.h | 6 +- + .../realtek/rtlwifi/rtl8192d/Makefile | 11 + + .../rtlwifi/{rtl8192de => rtl8192d}/def.h | 0 + .../realtek/rtlwifi/rtl8192d/dm_common.c | 1079 +++++++++++++++ + .../realtek/rtlwifi/rtl8192d/dm_common.h | 100 ++ + .../realtek/rtlwifi/rtl8192d/fw_common.c | 369 +++++ + .../realtek/rtlwifi/rtl8192d/fw_common.h | 39 + + .../realtek/rtlwifi/rtl8192d/hw_common.c | 1191 +++++++++++++++++ + .../realtek/rtlwifi/rtl8192d/hw_common.h | 24 + + .../wireless/realtek/rtlwifi/rtl8192d/main.c | 9 + + .../realtek/rtlwifi/rtl8192d/phy_common.c | 846 ++++++++++++ + .../realtek/rtlwifi/rtl8192d/phy_common.h | 87 ++ + .../rtlwifi/{rtl8192de => rtl8192d}/reg.h | 0 + .../realtek/rtlwifi/rtl8192d/rf_common.c | 353 +++++ + .../realtek/rtlwifi/rtl8192d/rf_common.h | 13 + + .../realtek/rtlwifi/rtl8192d/trx_common.c | 515 +++++++ + .../realtek/rtlwifi/rtl8192d/trx_common.h | 405 ++++++ + .../wireless/realtek/rtlwifi/rtl8192de/dm.c | 1072 +-------------- + .../wireless/realtek/rtlwifi/rtl8192de/dm.h | 91 +- + .../wireless/realtek/rtlwifi/rtl8192de/fw.c | 375 +----- + .../wireless/realtek/rtlwifi/rtl8192de/fw.h | 37 - + .../wireless/realtek/rtlwifi/rtl8192de/hw.c | 1168 +--------------- + .../wireless/realtek/rtlwifi/rtl8192de/hw.h | 11 - + .../wireless/realtek/rtlwifi/rtl8192de/led.c | 2 +- + .../wireless/realtek/rtlwifi/rtl8192de/phy.c | 918 +------------ + .../wireless/realtek/rtlwifi/rtl8192de/phy.h | 59 +- + .../wireless/realtek/rtlwifi/rtl8192de/rf.c | 375 +----- + .../wireless/realtek/rtlwifi/rtl8192de/rf.h | 5 - + .../wireless/realtek/rtlwifi/rtl8192de/sw.c | 12 +- + .../wireless/realtek/rtlwifi/rtl8192de/trx.c | 514 +------ + .../wireless/realtek/rtlwifi/rtl8192de/trx.h | 396 ------ + drivers/net/wireless/realtek/rtlwifi/wifi.h | 1 + + 35 files changed, 5166 insertions(+), 4927 deletions(-) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile + rename drivers/net/wireless/realtek/rtlwifi/{rtl8192de => rtl8192d}/def.h (100%) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h + rename drivers/net/wireless/realtek/rtlwifi/{rtl8192de => rtl8192d}/reg.h (100%) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/Kconfig b/drivers/net/wireless/realtek/rtlwifi/Kconfig +index 9f6a4e35543c..cfe63f7b28d9 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/Kconfig ++++ b/drivers/net/wireless/realtek/rtlwifi/Kconfig +@@ -37,6 +37,7 @@ config RTL8192SE + config RTL8192DE + tristate "Realtek RTL8192DE/RTL8188DE PCIe Wireless Network Adapter" + depends on PCI ++ select RTL8192D_COMMON + select RTLWIFI + select RTLWIFI_PCI + help +@@ -142,6 +143,9 @@ config RTL8192C_COMMON + depends on RTL8192CE || RTL8192CU + default y + ++config RTL8192D_COMMON ++ tristate ++ + config RTL8723_COMMON + tristate + depends on RTL8723AE || RTL8723BE +diff --git a/drivers/net/wireless/realtek/rtlwifi/Makefile b/drivers/net/wireless/realtek/rtlwifi/Makefile +index 09c30e428375..423981b148df 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/Makefile ++++ b/drivers/net/wireless/realtek/rtlwifi/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_RTL8192C_COMMON) += rtl8192c/ + obj-$(CONFIG_RTL8192CE) += rtl8192ce/ + obj-$(CONFIG_RTL8192CU) += rtl8192cu/ + obj-$(CONFIG_RTL8192SE) += rtl8192se/ ++obj-$(CONFIG_RTL8192D_COMMON) += rtl8192d/ + obj-$(CONFIG_RTL8192DE) += rtl8192de/ + obj-$(CONFIG_RTL8723AE) += rtl8723ae/ + obj-$(CONFIG_RTL8723BE) += rtl8723be/ +diff --git a/drivers/net/wireless/realtek/rtlwifi/cam.c b/drivers/net/wireless/realtek/rtlwifi/cam.c +index 32970ea4b4e7..f9d0d1394442 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/cam.c ++++ b/drivers/net/wireless/realtek/rtlwifi/cam.c +@@ -18,7 +18,8 @@ void rtl_cam_reset_sec_info(struct ieee80211_hw *hw) + } + + static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, +- u8 *mac_addr, u8 *key_cont_128, u16 us_config) ++ const u8 *mac_addr, u8 *key_cont_128, ++ u16 us_config) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + +@@ -94,7 +95,7 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, + "after set key, usconfig:%x\n", us_config); + } + +-u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, ++u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, const u8 *mac_addr, + u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg, + u32 ul_default_key, u8 *key_content) + { +diff --git a/drivers/net/wireless/realtek/rtlwifi/cam.h b/drivers/net/wireless/realtek/rtlwifi/cam.h +index 2461fa9afda0..144807a405b7 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/cam.h ++++ b/drivers/net/wireless/realtek/rtlwifi/cam.h +@@ -14,9 +14,9 @@ + #define CAM_CONFIG_NO_USEDK 0 + + void rtl_cam_reset_all_entry(struct ieee80211_hw *hw); +-u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, +- u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg, +- u32 ul_default_key, u8 *key_content); ++u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, const u8 *mac_addr, ++ u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg, ++ u32 ul_default_key, u8 *key_content); + int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, + u32 ul_key_id); + void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile +new file mode 100644 +index 000000000000..beebdfa3f7ff +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile +@@ -0,0 +1,11 @@ ++# SPDX-License-Identifier: GPL-2.0 ++rtl8192d-common-objs := \ ++ dm_common.o \ ++ fw_common.o \ ++ hw_common.o \ ++ main.o \ ++ phy_common.o \ ++ rf_common.o \ ++ trx_common.o ++ ++obj-$(CONFIG_RTL8192D_COMMON) += rtl8192d-common.o +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/def.h +similarity index 100% +rename from drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h +rename to drivers/net/wireless/realtek/rtlwifi/rtl8192d/def.h +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c +new file mode 100644 +index 000000000000..d376e4584454 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c +@@ -0,0 +1,1079 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../base.h" ++#include "../core.h" ++#include "reg.h" ++#include "def.h" ++#include "phy_common.h" ++#include "dm_common.h" ++ ++#define UNDEC_SM_PWDB entry_min_undec_sm_pwdb ++ ++static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = { ++ 0x7f8001fe, /* 0, +6.0dB */ ++ 0x788001e2, /* 1, +5.5dB */ ++ 0x71c001c7, /* 2, +5.0dB */ ++ 0x6b8001ae, /* 3, +4.5dB */ ++ 0x65400195, /* 4, +4.0dB */ ++ 0x5fc0017f, /* 5, +3.5dB */ ++ 0x5a400169, /* 6, +3.0dB */ ++ 0x55400155, /* 7, +2.5dB */ ++ 0x50800142, /* 8, +2.0dB */ ++ 0x4c000130, /* 9, +1.5dB */ ++ 0x47c0011f, /* 10, +1.0dB */ ++ 0x43c0010f, /* 11, +0.5dB */ ++ 0x40000100, /* 12, +0dB */ ++ 0x3c8000f2, /* 13, -0.5dB */ ++ 0x390000e4, /* 14, -1.0dB */ ++ 0x35c000d7, /* 15, -1.5dB */ ++ 0x32c000cb, /* 16, -2.0dB */ ++ 0x300000c0, /* 17, -2.5dB */ ++ 0x2d4000b5, /* 18, -3.0dB */ ++ 0x2ac000ab, /* 19, -3.5dB */ ++ 0x288000a2, /* 20, -4.0dB */ ++ 0x26000098, /* 21, -4.5dB */ ++ 0x24000090, /* 22, -5.0dB */ ++ 0x22000088, /* 23, -5.5dB */ ++ 0x20000080, /* 24, -6.0dB */ ++ 0x1e400079, /* 25, -6.5dB */ ++ 0x1c800072, /* 26, -7.0dB */ ++ 0x1b00006c, /* 27. -7.5dB */ ++ 0x19800066, /* 28, -8.0dB */ ++ 0x18000060, /* 29, -8.5dB */ ++ 0x16c0005b, /* 30, -9.0dB */ ++ 0x15800056, /* 31, -9.5dB */ ++ 0x14400051, /* 32, -10.0dB */ ++ 0x1300004c, /* 33, -10.5dB */ ++ 0x12000048, /* 34, -11.0dB */ ++ 0x11000044, /* 35, -11.5dB */ ++ 0x10000040, /* 36, -12.0dB */ ++ 0x0f00003c, /* 37, -12.5dB */ ++ 0x0e400039, /* 38, -13.0dB */ ++ 0x0d800036, /* 39, -13.5dB */ ++ 0x0cc00033, /* 40, -14.0dB */ ++ 0x0c000030, /* 41, -14.5dB */ ++ 0x0b40002d, /* 42, -15.0dB */ ++}; ++ ++static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { ++ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ ++ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ ++ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ ++ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ ++ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ ++ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ ++ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ ++ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ ++ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ ++ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ ++ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ ++ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ ++ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ ++ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ ++ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ ++ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ ++ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ ++ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ ++ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ ++ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ ++ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ ++ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ ++ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ ++ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ ++ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ ++ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ ++ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ ++ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ ++ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ ++ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ ++ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ ++ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ ++ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ ++}; ++ ++static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { ++ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ ++ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ ++ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ ++ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ ++ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ ++ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ ++ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ ++ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ ++ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ ++ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ ++ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ ++ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ ++ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ ++ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ ++ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ ++ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ ++ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ ++ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ ++ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ ++ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ ++ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ ++ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ ++ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ ++ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ ++ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ ++ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ ++ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ ++ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ ++ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ ++ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ ++ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ ++ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ ++ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ ++}; ++ ++static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) ++{ ++ static const u8 index_mapping[RX_INDEX_MAPPING_NUM] = { ++ 0x0f, 0x0f, 0x0d, 0x0c, 0x0b, ++ 0x0a, 0x09, 0x08, 0x07, 0x06, ++ 0x05, 0x04, 0x04, 0x03, 0x02 ++ }; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 u4tmp; ++ int i; ++ ++ u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter - ++ rtlpriv->dm.thermalvalue_rxgain)]) << 12; ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "===> Rx Gain %x\n", u4tmp); ++ for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) ++ rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK, ++ (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); ++} ++ ++static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, ++ u8 *cck_index_old) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ unsigned long flag = 0; ++ const u8 *cckswing; ++ long temp_cck; ++ int i; ++ ++ /* Query CCK default setting From 0xa24 */ ++ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); ++ temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, ++ MASKDWORD) & MASKCCK; ++ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); ++ for (i = 0; i < CCK_TABLE_LENGTH; i++) { ++ if (rtlpriv->dm.cck_inch14) ++ cckswing = &cckswing_table_ch14[i][2]; ++ else ++ cckswing = &cckswing_table_ch1ch13[i][2]; ++ ++ if (temp_cck == le32_to_cpu(*((__le32 *)cckswing))) { ++ *cck_index_old = (u8)i; ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n", ++ RCCK0_TXFILTER2, temp_cck, ++ *cck_index_old, ++ rtlpriv->dm.cck_inch14); ++ break; ++ } ++ } ++ *temp_cckg = temp_cck; ++} ++ ++static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, ++ bool *internal_pa, u8 thermalvalue, u8 delta, ++ u8 rf, struct rtl_efuse *rtlefuse, ++ struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy, ++ const u8 index_mapping[5][INDEX_MAPPING_NUM], ++ const u8 index_mapping_pa[8][INDEX_MAPPING_NUM]) ++{ ++ u8 offset = 0; ++ u8 index; ++ int i; ++ ++ for (i = 0; i < rf; i++) { ++ if (rtlhal->macphymode == DUALMAC_DUALPHY && ++ rtlhal->interfaceindex == 1) /* MAC 1 5G */ ++ *internal_pa = rtlefuse->internal_pa_5g[1]; ++ else ++ *internal_pa = rtlefuse->internal_pa_5g[i]; ++ if (*internal_pa) { ++ if (rtlhal->interfaceindex == 1 || i == rf) ++ offset = 4; ++ else ++ offset = 0; ++ if (rtlphy->current_channel >= 100 && ++ rtlphy->current_channel <= 165) ++ offset += 2; ++ } else { ++ if (rtlhal->interfaceindex == 1 || i == rf) ++ offset = 2; ++ else ++ offset = 0; ++ } ++ if (thermalvalue > rtlefuse->eeprom_thermalmeter) ++ offset++; ++ if (*internal_pa) { ++ if (delta > INDEX_MAPPING_NUM - 1) ++ index = index_mapping_pa[offset] ++ [INDEX_MAPPING_NUM - 1]; ++ else ++ index = ++ index_mapping_pa[offset][delta]; ++ } else { ++ if (delta > INDEX_MAPPING_NUM - 1) ++ index = ++ index_mapping[offset][INDEX_MAPPING_NUM - 1]; ++ else ++ index = index_mapping[offset][delta]; ++ } ++ if (thermalvalue > rtlefuse->eeprom_thermalmeter) { ++ if (*internal_pa && thermalvalue > 0x12) { ++ ofdm_index[i] = rtlpriv->dm.ofdm_index[i] - ++ ((delta / 2) * 3 + (delta % 2)); ++ } else { ++ ofdm_index[i] -= index; ++ } ++ } else { ++ ofdm_index[i] += index; ++ } ++ } ++} ++ ++static void ++rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) ++{ ++ static const u8 index_mapping[5][INDEX_MAPPING_NUM] = { ++ /* 5G, path A/MAC 0, decrease power */ ++ {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, ++ /* 5G, path A/MAC 0, increase power */ ++ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, ++ /* 5G, path B/MAC 1, decrease power */ ++ {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, ++ /* 5G, path B/MAC 1, increase power */ ++ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, ++ /* 2.4G, for decreas power */ ++ {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, ++ }; ++ static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = { ++ /* 5G, path A/MAC 0, ch36-64, decrease power */ ++ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, ++ /* 5G, path A/MAC 0, ch36-64, increase power */ ++ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, ++ /* 5G, path A/MAC 0, ch100-165, decrease power */ ++ {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, ++ /* 5G, path A/MAC 0, ch100-165, increase power */ ++ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, ++ /* 5G, path B/MAC 1, ch36-64, decrease power */ ++ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, ++ /* 5G, path B/MAC 1, ch36-64, increase power */ ++ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, ++ /* 5G, path B/MAC 1, ch100-165, decrease power */ ++ {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, ++ /* 5G, path B/MAC 1, ch100-165, increase power */ ++ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, ++ }; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain; ++ u8 offset, thermalvalue_avg_count = 0; ++ u32 thermalvalue_avg = 0; ++ bool internal_pa = false; ++ long ele_a = 0, ele_d, temp_cck, val_x, value32; ++ long val_y, ele_c = 0; ++ u8 ofdm_index[2]; ++ s8 cck_index = 0; ++ u8 ofdm_index_old[2] = {0, 0}; ++ s8 cck_index_old = 0; ++ u8 index; ++ int i; ++ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); ++ u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; ++ u8 indexforchannel = ++ rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); ++ ++ rtlpriv->dm.txpower_trackinginit = true; ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n"); ++ thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800); ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", ++ thermalvalue, ++ rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); ++ ++ if (!thermalvalue) ++ goto exit; ++ ++ if (is2t) ++ rf = 2; ++ else ++ rf = 1; ++ ++ if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex) ++ goto old_index_done; ++ ++ ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; ++ for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { ++ if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { ++ ofdm_index_old[0] = (u8)i; ++ ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", ++ ROFDM0_XATXIQIMBALANCE, ++ ele_d, ofdm_index_old[0]); ++ break; ++ } ++ } ++ if (is2t) { ++ ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, ++ MASKDWORD) & MASKOFDM_D; ++ for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { ++ if (ele_d == ++ (ofdmswing_table[i] & MASKOFDM_D)) { ++ ofdm_index_old[1] = (u8)i; ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, ++ DBG_LOUD, ++ "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n", ++ ROFDM0_XBTXIQIMBALANCE, ele_d, ++ ofdm_index_old[1]); ++ break; ++ } ++ } ++ } ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old); ++ } else { ++ temp_cck = 0x090e1317; ++ cck_index_old = 12; ++ } ++ ++ if (!rtlpriv->dm.thermalvalue) { ++ rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; ++ rtlpriv->dm.thermalvalue_lck = thermalvalue; ++ rtlpriv->dm.thermalvalue_iqk = thermalvalue; ++ rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; ++ for (i = 0; i < rf; i++) ++ rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; ++ rtlpriv->dm.cck_index = cck_index_old; ++ } ++ if (rtlhal->reloadtxpowerindex) { ++ for (i = 0; i < rf; i++) ++ rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; ++ rtlpriv->dm.cck_index = cck_index_old; ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "reload ofdm index for band switch\n"); ++ } ++old_index_done: ++ for (i = 0; i < rf; i++) ++ ofdm_index[i] = rtlpriv->dm.ofdm_index[i]; ++ ++ rtlpriv->dm.thermalvalue_avg ++ [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue; ++ rtlpriv->dm.thermalvalue_avg_index++; ++ if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM) ++ rtlpriv->dm.thermalvalue_avg_index = 0; ++ for (i = 0; i < AVG_THERMAL_NUM; i++) { ++ if (rtlpriv->dm.thermalvalue_avg[i]) { ++ thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i]; ++ thermalvalue_avg_count++; ++ } ++ } ++ if (thermalvalue_avg_count) ++ thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); ++ if (rtlhal->reloadtxpowerindex) { ++ delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? ++ (thermalvalue - rtlefuse->eeprom_thermalmeter) : ++ (rtlefuse->eeprom_thermalmeter - thermalvalue); ++ rtlhal->reloadtxpowerindex = false; ++ rtlpriv->dm.done_txpower = false; ++ } else if (rtlpriv->dm.done_txpower) { ++ delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? ++ (thermalvalue - rtlpriv->dm.thermalvalue) : ++ (rtlpriv->dm.thermalvalue - thermalvalue); ++ } else { ++ delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? ++ (thermalvalue - rtlefuse->eeprom_thermalmeter) : ++ (rtlefuse->eeprom_thermalmeter - thermalvalue); ++ } ++ delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? ++ (thermalvalue - rtlpriv->dm.thermalvalue_lck) : ++ (rtlpriv->dm.thermalvalue_lck - thermalvalue); ++ delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? ++ (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : ++ (rtlpriv->dm.thermalvalue_iqk - thermalvalue); ++ delta_rxgain = ++ (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ? ++ (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) : ++ (rtlpriv->dm.thermalvalue_rxgain - thermalvalue); ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", ++ thermalvalue, rtlpriv->dm.thermalvalue, ++ rtlefuse->eeprom_thermalmeter, delta, delta_lck, ++ delta_iqk); ++ if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) { ++ rtlpriv->dm.thermalvalue_lck = thermalvalue; ++ rtlpriv->cfg->ops->phy_lc_calibrate(hw, is2t); ++ } ++ ++ if (delta == 0 || !rtlpriv->dm.txpower_track_control) ++ goto check_delta; ++ ++ rtlpriv->dm.done_txpower = true; ++ delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? ++ (thermalvalue - rtlefuse->eeprom_thermalmeter) : ++ (rtlefuse->eeprom_thermalmeter - thermalvalue); ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ offset = 4; ++ if (delta > INDEX_MAPPING_NUM - 1) ++ index = index_mapping[offset][INDEX_MAPPING_NUM - 1]; ++ else ++ index = index_mapping[offset][delta]; ++ if (thermalvalue > rtlpriv->dm.thermalvalue) { ++ for (i = 0; i < rf; i++) ++ ofdm_index[i] -= delta; ++ cck_index -= delta; ++ } else { ++ for (i = 0; i < rf; i++) ++ ofdm_index[i] += index; ++ cck_index += index; ++ } ++ } else if (rtlhal->current_bandtype == BAND_ON_5G) { ++ rtl92d_bandtype_5G(rtlhal, ofdm_index, ++ &internal_pa, thermalvalue, ++ delta, rf, rtlefuse, rtlpriv, ++ rtlphy, index_mapping, ++ index_mapping_internal_pa); ++ } ++ if (is2t) { ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n", ++ rtlpriv->dm.ofdm_index[0], ++ rtlpriv->dm.ofdm_index[1], ++ rtlpriv->dm.cck_index); ++ } else { ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "temp OFDM_A_index=0x%x,cck_index = 0x%x\n", ++ rtlpriv->dm.ofdm_index[0], ++ rtlpriv->dm.cck_index); ++ } ++ for (i = 0; i < rf; i++) { ++ if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) { ++ ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1; ++ } else if (internal_pa || ++ rtlhal->current_bandtype == BAND_ON_2_4G) { ++ if (ofdm_index[i] < ofdm_min_index_internal_pa) ++ ofdm_index[i] = ofdm_min_index_internal_pa; ++ } else if (ofdm_index[i] < ofdm_min_index) { ++ ofdm_index[i] = ofdm_min_index; ++ } ++ } ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ if (cck_index > CCK_TABLE_SIZE - 1) ++ cck_index = CCK_TABLE_SIZE - 1; ++ else if (cck_index < 0) ++ cck_index = 0; ++ } ++ if (is2t) { ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", ++ ofdm_index[0], ofdm_index[1], ++ cck_index); ++ } else { ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "new OFDM_A_index=0x%x,cck_index = 0x%x\n", ++ ofdm_index[0], cck_index); ++ } ++ ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; ++ val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0]; ++ val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1]; ++ if (val_x != 0) { ++ if ((val_x & 0x00000200) != 0) ++ val_x = val_x | 0xFFFFFC00; ++ ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; ++ ++ /* new element C = element D x Y */ ++ if ((val_y & 0x00000200) != 0) ++ val_y = val_y | 0xFFFFFC00; ++ ele_c = ((val_y * ele_d) >> 8) & 0x000003FF; ++ ++ /* write new elements A, C, D to regC80 and ++ * regC94, element B is always 0 ++ */ ++ value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, ++ MASKDWORD, value32); ++ ++ value32 = (ele_c & 0x000003C0) >> 6; ++ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, ++ value32); ++ ++ value32 = ((val_x * ele_d) >> 7) & 0x01; ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), ++ value32); ++ ++ } else { ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, ++ MASKDWORD, ++ ofdmswing_table[(u8)ofdm_index[0]]); ++ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, ++ 0x00); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, ++ BIT(24), 0x00); ++ } ++ ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n", ++ rtlhal->interfaceindex, ++ val_x, val_y, ele_a, ele_c, ele_d, ++ val_x, val_y); ++ ++ if (cck_index >= CCK_TABLE_SIZE) ++ cck_index = CCK_TABLE_SIZE - 1; ++ if (cck_index < 0) ++ cck_index = 0; ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ /* Adjust CCK according to IQK result */ ++ if (!rtlpriv->dm.cck_inch14) { ++ rtl_write_byte(rtlpriv, 0xa22, ++ cckswing_table_ch1ch13[cck_index][0]); ++ rtl_write_byte(rtlpriv, 0xa23, ++ cckswing_table_ch1ch13[cck_index][1]); ++ rtl_write_byte(rtlpriv, 0xa24, ++ cckswing_table_ch1ch13[cck_index][2]); ++ rtl_write_byte(rtlpriv, 0xa25, ++ cckswing_table_ch1ch13[cck_index][3]); ++ rtl_write_byte(rtlpriv, 0xa26, ++ cckswing_table_ch1ch13[cck_index][4]); ++ rtl_write_byte(rtlpriv, 0xa27, ++ cckswing_table_ch1ch13[cck_index][5]); ++ rtl_write_byte(rtlpriv, 0xa28, ++ cckswing_table_ch1ch13[cck_index][6]); ++ rtl_write_byte(rtlpriv, 0xa29, ++ cckswing_table_ch1ch13[cck_index][7]); ++ } else { ++ rtl_write_byte(rtlpriv, 0xa22, ++ cckswing_table_ch14[cck_index][0]); ++ rtl_write_byte(rtlpriv, 0xa23, ++ cckswing_table_ch14[cck_index][1]); ++ rtl_write_byte(rtlpriv, 0xa24, ++ cckswing_table_ch14[cck_index][2]); ++ rtl_write_byte(rtlpriv, 0xa25, ++ cckswing_table_ch14[cck_index][3]); ++ rtl_write_byte(rtlpriv, 0xa26, ++ cckswing_table_ch14[cck_index][4]); ++ rtl_write_byte(rtlpriv, 0xa27, ++ cckswing_table_ch14[cck_index][5]); ++ rtl_write_byte(rtlpriv, 0xa28, ++ cckswing_table_ch14[cck_index][6]); ++ rtl_write_byte(rtlpriv, 0xa29, ++ cckswing_table_ch14[cck_index][7]); ++ } ++ } ++ if (is2t) { ++ ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22; ++ val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4]; ++ val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5]; ++ if (val_x != 0) { ++ if ((val_x & 0x00000200) != 0) ++ /* consider minus */ ++ val_x = val_x | 0xFFFFFC00; ++ ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; ++ /* new element C = element D x Y */ ++ if ((val_y & 0x00000200) != 0) ++ val_y = val_y | 0xFFFFFC00; ++ ele_c = ((val_y * ele_d) >> 8) & 0x00003FF; ++ /* write new elements A, C, D to regC88 ++ * and regC9C, element B is always 0 ++ */ ++ value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; ++ rtl_set_bbreg(hw, ++ ROFDM0_XBTXIQIMBALANCE, ++ MASKDWORD, value32); ++ value32 = (ele_c & 0x000003C0) >> 6; ++ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, ++ MASKH4BITS, value32); ++ value32 = ((val_x * ele_d) >> 7) & 0x01; ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, ++ BIT(28), value32); ++ } else { ++ rtl_set_bbreg(hw, ++ ROFDM0_XBTXIQIMBALANCE, ++ MASKDWORD, ++ ofdmswing_table[ofdm_index[1]]); ++ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, ++ MASKH4BITS, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, ++ BIT(28), 0x00); ++ } ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n", ++ val_x, val_y, ele_a, ele_c, ++ ele_d, val_x, val_y); ++ } ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", ++ rtl_get_bbreg(hw, 0xc80, MASKDWORD), ++ rtl_get_bbreg(hw, 0xc94, MASKDWORD), ++ rtl_get_rfreg(hw, RF90_PATH_A, 0x24, ++ RFREG_OFFSET_MASK)); ++ ++check_delta: ++ if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) { ++ rtl92d_phy_reset_iqk_result(hw); ++ rtlpriv->dm.thermalvalue_iqk = thermalvalue; ++ rtlpriv->cfg->ops->phy_iq_calibrate(hw); ++ } ++ if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G && ++ thermalvalue <= rtlefuse->eeprom_thermalmeter) { ++ rtlpriv->dm.thermalvalue_rxgain = thermalvalue; ++ rtl92d_dm_rxgain_tracking_thermalmeter(hw); ++ } ++ if (rtlpriv->dm.txpower_track_control) ++ rtlpriv->dm.thermalvalue = thermalvalue; ++ ++exit: ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); ++} ++ ++void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ rtlpriv->dm.txpower_tracking = true; ++ rtlpriv->dm.txpower_trackinginit = false; ++ rtlpriv->dm.txpower_track_control = true; ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "pMgntInfo->txpower_tracking = %d\n", ++ rtlpriv->dm.txpower_tracking); ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_initialize_txpower_tracking); ++ ++void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ if (!rtlpriv->dm.txpower_tracking) ++ return; ++ ++ if (!rtlpriv->dm.tm_trigger) { ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) | ++ BIT(16), 0x03); ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "Trigger 92S Thermal Meter!!\n"); ++ rtlpriv->dm.tm_trigger = 1; ++ } else { ++ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ++ "Schedule TxPowerTracking direct call!!\n"); ++ rtl92d_dm_txpower_tracking_callback_thermalmeter(hw); ++ rtlpriv->dm.tm_trigger = 0; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_check_txpower_tracking_thermal_meter); ++ ++void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) ++{ ++ u32 ret_value; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; ++ unsigned long flag = 0; ++ ++ /* hold ofdm counter */ ++ rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ ++ ++ ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); ++ falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); ++ falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); ++ ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); ++ falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); ++ ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); ++ falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); ++ falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); ++ ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); ++ falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); ++ falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + ++ falsealm_cnt->cnt_rate_illegal + ++ falsealm_cnt->cnt_crc8_fail + ++ falsealm_cnt->cnt_mcs_fail + ++ falsealm_cnt->cnt_fast_fsync_fail + ++ falsealm_cnt->cnt_sb_search_fail; ++ ++ if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { ++ /* hold cck counter */ ++ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); ++ ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); ++ falsealm_cnt->cnt_cck_fail = ret_value; ++ ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); ++ falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; ++ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); ++ } else { ++ falsealm_cnt->cnt_cck_fail = 0; ++ } ++ ++ /* reset false alarm counter registers */ ++ falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail + ++ falsealm_cnt->cnt_sb_search_fail + ++ falsealm_cnt->cnt_parity_fail + ++ falsealm_cnt->cnt_rate_illegal + ++ falsealm_cnt->cnt_crc8_fail + ++ falsealm_cnt->cnt_mcs_fail + ++ falsealm_cnt->cnt_cck_fail; ++ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); ++ /* update ofdm counter */ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); ++ /* update page C counter */ ++ rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); ++ /* update page D counter */ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); ++ if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { ++ /* reset cck counter */ ++ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); ++ rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); ++ /* enable cck counter */ ++ rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); ++ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); ++ } ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n", ++ falsealm_cnt->cnt_fast_fsync_fail, ++ falsealm_cnt->cnt_sb_search_fail); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n", ++ falsealm_cnt->cnt_parity_fail, ++ falsealm_cnt->cnt_rate_illegal, ++ falsealm_cnt->cnt_crc8_fail, ++ falsealm_cnt->cnt_mcs_fail); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n", ++ falsealm_cnt->cnt_ofdm_fail, ++ falsealm_cnt->cnt_cck_fail, ++ falsealm_cnt->cnt_all); ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_false_alarm_counter_statistics); ++ ++void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct dig_t *de_digtable = &rtlpriv->dm_digtable; ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ ++ /* Determine the minimum RSSI */ ++ if (mac->link_state < MAC80211_LINKED && ++ rtlpriv->dm.UNDEC_SM_PWDB == 0) { ++ de_digtable->min_undec_pwdb_for_dm = 0; ++ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, ++ "Not connected to any\n"); ++ } ++ if (mac->link_state >= MAC80211_LINKED) { ++ if (mac->opmode == NL80211_IFTYPE_AP || ++ mac->opmode == NL80211_IFTYPE_ADHOC) { ++ de_digtable->min_undec_pwdb_for_dm = ++ rtlpriv->dm.UNDEC_SM_PWDB; ++ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, ++ "AP Client PWDB = 0x%lx\n", ++ rtlpriv->dm.UNDEC_SM_PWDB); ++ } else { ++ de_digtable->min_undec_pwdb_for_dm = ++ rtlpriv->dm.undec_sm_pwdb; ++ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, ++ "STA Default Port PWDB = 0x%x\n", ++ de_digtable->min_undec_pwdb_for_dm); ++ } ++ } else { ++ de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB; ++ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, ++ "AP Ext Port or disconnect PWDB = 0x%x\n", ++ de_digtable->min_undec_pwdb_for_dm); ++ } ++ ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n", ++ de_digtable->min_undec_pwdb_for_dm); ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_find_minimum_rssi); ++ ++static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct dig_t *de_digtable = &rtlpriv->dm_digtable; ++ unsigned long flag = 0; ++ ++ if (de_digtable->cursta_cstate == DIG_STA_CONNECT) { ++ if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { ++ if (de_digtable->min_undec_pwdb_for_dm <= 25) ++ de_digtable->cur_cck_pd_state = ++ CCK_PD_STAGE_LOWRSSI; ++ else ++ de_digtable->cur_cck_pd_state = ++ CCK_PD_STAGE_HIGHRSSI; ++ } else { ++ if (de_digtable->min_undec_pwdb_for_dm <= 20) ++ de_digtable->cur_cck_pd_state = ++ CCK_PD_STAGE_LOWRSSI; ++ else ++ de_digtable->cur_cck_pd_state = ++ CCK_PD_STAGE_HIGHRSSI; ++ } ++ } else { ++ de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI; ++ } ++ if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) { ++ if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { ++ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); ++ rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); ++ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); ++ } else { ++ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); ++ rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); ++ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); ++ } ++ de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state; ++ } ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n", ++ de_digtable->cursta_cstate == DIG_STA_CONNECT ? ++ "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT"); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n", ++ de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ? ++ "Low RSSI " : "High RSSI "); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n", ++ IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)); ++} ++ ++void rtl92d_dm_write_dig(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct dig_t *de_digtable = &rtlpriv->dm_digtable; ++ ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", ++ de_digtable->cur_igvalue, de_digtable->pre_igvalue, ++ de_digtable->back_val); ++ if (!de_digtable->dig_enable_flag) { ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n"); ++ de_digtable->pre_igvalue = 0x17; ++ return; ++ } ++ if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) { ++ rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, ++ de_digtable->cur_igvalue); ++ rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, ++ de_digtable->cur_igvalue); ++ de_digtable->pre_igvalue = de_digtable->cur_igvalue; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_write_dig); ++ ++static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv) ++{ ++ struct dig_t *de_digtable = &rtlpriv->dm_digtable; ++ ++ if (rtlpriv->mac80211.link_state >= MAC80211_LINKED && ++ rtlpriv->mac80211.vendor == PEER_CISCO) { ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n"); ++ if (de_digtable->last_min_undec_pwdb_for_dm >= 50 && ++ de_digtable->min_undec_pwdb_for_dm < 50) { ++ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "Early Mode Off\n"); ++ } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 && ++ de_digtable->min_undec_pwdb_for_dm > 55) { ++ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "Early Mode On\n"); ++ } ++ } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) { ++ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n"); ++ } ++} ++ ++void rtl92d_dm_dig(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct dig_t *de_digtable = &rtlpriv->dm_digtable; ++ u8 value_igi = de_digtable->cur_igvalue; ++ struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; ++ ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n"); ++ if (rtlpriv->rtlhal.earlymode_enable) { ++ rtl92d_early_mode_enabled(rtlpriv); ++ de_digtable->last_min_undec_pwdb_for_dm = ++ de_digtable->min_undec_pwdb_for_dm; ++ } ++ if (!rtlpriv->dm.dm_initialgain_enable) ++ return; ++ ++ /* because we will send data pkt when scanning ++ * this will cause some ap like gear-3700 wep TP ++ * lower if we return here, this is the diff of ++ * mac80211 driver vs ieee80211 driver ++ */ ++ /* if (rtlpriv->mac80211.act_scanning) ++ * return; ++ */ ++ ++ /* Not STA mode return tmp */ ++ if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) ++ return; ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n"); ++ /* Decide the current status and if modify initial gain or not */ ++ if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) ++ de_digtable->cursta_cstate = DIG_STA_CONNECT; ++ else ++ de_digtable->cursta_cstate = DIG_STA_DISCONNECT; ++ ++ /* adjust initial gain according to false alarm counter */ ++ if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0) ++ value_igi--; ++ else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1) ++ value_igi += 0; ++ else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2) ++ value_igi++; ++ else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2) ++ value_igi += 2; ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n", ++ de_digtable->large_fa_hit, de_digtable->forbidden_igi); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n", ++ de_digtable->recover_cnt, de_digtable->rx_gain_min); ++ ++ /* deal with abnormally large false alarm */ ++ if (falsealm_cnt->cnt_all > 10000) { ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "dm_DIG(): Abnormally false alarm case\n"); ++ ++ de_digtable->large_fa_hit++; ++ if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) { ++ de_digtable->forbidden_igi = de_digtable->cur_igvalue; ++ de_digtable->large_fa_hit = 1; ++ } ++ if (de_digtable->large_fa_hit >= 3) { ++ if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX) ++ de_digtable->rx_gain_min = DM_DIG_MAX; ++ else ++ de_digtable->rx_gain_min = ++ (de_digtable->forbidden_igi + 1); ++ de_digtable->recover_cnt = 3600; /* 3600=2hr */ ++ } ++ } else { ++ /* Recovery mechanism for IGI lower bound */ ++ if (de_digtable->recover_cnt != 0) { ++ de_digtable->recover_cnt--; ++ } else { ++ if (de_digtable->large_fa_hit == 0) { ++ if ((de_digtable->forbidden_igi - 1) < ++ DM_DIG_FA_LOWER) { ++ de_digtable->forbidden_igi = ++ DM_DIG_FA_LOWER; ++ de_digtable->rx_gain_min = ++ DM_DIG_FA_LOWER; ++ ++ } else { ++ de_digtable->forbidden_igi--; ++ de_digtable->rx_gain_min = ++ (de_digtable->forbidden_igi + 1); ++ } ++ } else if (de_digtable->large_fa_hit == 3) { ++ de_digtable->large_fa_hit = 0; ++ } ++ } ++ } ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n", ++ de_digtable->large_fa_hit, de_digtable->forbidden_igi); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, ++ "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n", ++ de_digtable->recover_cnt, de_digtable->rx_gain_min); ++ ++ if (value_igi > DM_DIG_MAX) ++ value_igi = DM_DIG_MAX; ++ else if (value_igi < de_digtable->rx_gain_min) ++ value_igi = de_digtable->rx_gain_min; ++ de_digtable->cur_igvalue = value_igi; ++ rtl92d_dm_write_dig(hw); ++ if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) ++ rtl92d_dm_cck_packet_detection_thresh(hw); ++ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n"); ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_dig); ++ ++void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ rtlpriv->dm.current_turbo_edca = false; ++ rtlpriv->dm.is_any_nonbepkts = false; ++ rtlpriv->dm.is_cur_rdlstate = false; ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_init_edca_turbo); ++ ++void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ const u32 edca_be_ul = 0x5ea42b; ++ const u32 edca_be_dl = 0x5ea42b; ++ static u64 last_txok_cnt; ++ static u64 last_rxok_cnt; ++ u64 cur_txok_cnt; ++ u64 cur_rxok_cnt; ++ ++ if (mac->link_state != MAC80211_LINKED) { ++ rtlpriv->dm.current_turbo_edca = false; ++ goto exit; ++ } ++ ++ if (!rtlpriv->dm.is_any_nonbepkts && ++ !rtlpriv->dm.disable_framebursting) { ++ cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; ++ cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; ++ if (cur_rxok_cnt > 4 * cur_txok_cnt) { ++ if (!rtlpriv->dm.is_cur_rdlstate || ++ !rtlpriv->dm.current_turbo_edca) { ++ rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, ++ edca_be_dl); ++ rtlpriv->dm.is_cur_rdlstate = true; ++ } ++ } else { ++ if (rtlpriv->dm.is_cur_rdlstate || ++ !rtlpriv->dm.current_turbo_edca) { ++ rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, ++ edca_be_ul); ++ rtlpriv->dm.is_cur_rdlstate = false; ++ } ++ } ++ rtlpriv->dm.current_turbo_edca = true; ++ } else { ++ if (rtlpriv->dm.current_turbo_edca) { ++ u8 tmp = AC0_BE; ++ ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, ++ &tmp); ++ rtlpriv->dm.current_turbo_edca = false; ++ } ++ } ++ ++exit: ++ rtlpriv->dm.is_any_nonbepkts = false; ++ last_txok_cnt = rtlpriv->stats.txbytesunicast; ++ last_rxok_cnt = rtlpriv->stats.rxbytesunicast; ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_check_edca_turbo); ++ ++void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rate_adaptive *ra = &rtlpriv->ra; ++ ++ ra->ratr_state = DM_RATR_STA_INIT; ++ ra->pre_ratr_state = DM_RATR_STA_INIT; ++ if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) ++ rtlpriv->dm.useramask = true; ++ else ++ rtlpriv->dm.useramask = false; ++} ++EXPORT_SYMBOL_GPL(rtl92d_dm_init_rate_adaptive_mask); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h +new file mode 100644 +index 000000000000..9dc0df5bb068 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h +@@ -0,0 +1,100 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#ifndef __RTL92D_DM_COMMON_H__ ++#define __RTL92D_DM_COMMON_H__ ++ ++#define HAL_DM_DIG_DISABLE BIT(0) ++#define HAL_DM_HIPWR_DISABLE BIT(1) ++ ++#define OFDM_TABLE_LENGTH 37 ++#define OFDM_TABLE_SIZE_92D 43 ++#define CCK_TABLE_LENGTH 33 ++ ++#define CCK_TABLE_SIZE 33 ++ ++#define BW_AUTO_SWITCH_HIGH_LOW 25 ++#define BW_AUTO_SWITCH_LOW_HIGH 30 ++ ++#define DM_DIG_FA_UPPER 0x32 ++#define DM_DIG_FA_LOWER 0x20 ++#define DM_DIG_FA_TH0 0x100 ++#define DM_DIG_FA_TH1 0x400 ++#define DM_DIG_FA_TH2 0x600 ++ ++#define RXPATHSELECTION_SS_TH_LOW 30 ++#define RXPATHSELECTION_DIFF_TH 18 ++ ++#define DM_RATR_STA_INIT 0 ++#define DM_RATR_STA_HIGH 1 ++#define DM_RATR_STA_MIDDLE 2 ++#define DM_RATR_STA_LOW 3 ++ ++#define CTS2SELF_THVAL 30 ++#define REGC38_TH 20 ++ ++#define WAIOTTHVAL 25 ++ ++#define TXHIGHPWRLEVEL_NORMAL 0 ++#define TXHIGHPWRLEVEL_LEVEL1 1 ++#define TXHIGHPWRLEVEL_LEVEL2 2 ++#define TXHIGHPWRLEVEL_BT1 3 ++#define TXHIGHPWRLEVEL_BT2 4 ++ ++#define DM_TYPE_BYFW 0 ++#define DM_TYPE_BYDRIVER 1 ++ ++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 ++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 ++#define INDEX_MAPPING_NUM 13 ++ ++struct swat { ++ u8 failure_cnt; ++ u8 try_flag; ++ u8 stop_trying; ++ long pre_rssi; ++ long trying_threshold; ++ u8 cur_antenna; ++ u8 pre_antenna; ++}; ++ ++enum tag_dynamic_init_gain_operation_type_definition { ++ DIG_TYPE_THRESH_HIGH = 0, ++ DIG_TYPE_THRESH_LOW = 1, ++ DIG_TYPE_BACKOFF = 2, ++ DIG_TYPE_RX_GAIN_MIN = 3, ++ DIG_TYPE_RX_GAIN_MAX = 4, ++ DIG_TYPE_ENABLE = 5, ++ DIG_TYPE_DISABLE = 6, ++ DIG_OP_TYPE_MAX ++}; ++ ++enum dm_1r_cca { ++ CCA_1R = 0, ++ CCA_2R = 1, ++ CCA_MAX = 2, ++}; ++ ++enum dm_rf { ++ RF_SAVE = 0, ++ RF_NORMAL = 1, ++ RF_MAX = 2, ++}; ++ ++enum dm_sw_ant_switch { ++ ANS_ANTENNA_B = 1, ++ ANS_ANTENNA_A = 2, ++ ANS_ANTENNA_MAX = 3, ++}; ++ ++void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw); ++void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw); ++void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw); ++void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw); ++void rtl92d_dm_write_dig(struct ieee80211_hw *hw); ++void rtl92d_dm_dig(struct ieee80211_hw *hw); ++void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw); ++void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw); ++void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c +new file mode 100644 +index 000000000000..73cfa9ad78ae +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c +@@ -0,0 +1,369 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../pci.h" ++#include "../base.h" ++#include "../efuse.h" ++#include "def.h" ++#include "reg.h" ++#include "fw_common.h" ++ ++bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv) ++{ ++ return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ? ++ true : false; ++} ++EXPORT_SYMBOL_GPL(rtl92d_is_fw_downloaded); ++ ++void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 tmp; ++ ++ if (enable) { ++ tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04); ++ tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); ++ rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01); ++ tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2); ++ rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7); ++ } else { ++ tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); ++ rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe); ++ /* Reserved for fw extension. ++ * 0x81[7] is used for mac0 status , ++ * so don't write this reg here ++ * rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00); ++ */ ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_enable_fw_download); ++ ++void rtl92d_write_fw(struct ieee80211_hw *hw, ++ enum version_8192d version, u8 *buffer, u32 size) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u8 *bufferptr = buffer; ++ u32 pagenums, remainsize; ++ u32 page, offset; ++ ++ rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size); ++ if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) ++ rtl_fill_dummy(bufferptr, &size); ++ pagenums = size / FW_8192D_PAGE_SIZE; ++ remainsize = size % FW_8192D_PAGE_SIZE; ++ if (pagenums > 8) ++ pr_err("Page numbers should not greater then 8\n"); ++ for (page = 0; page < pagenums; page++) { ++ offset = page * FW_8192D_PAGE_SIZE; ++ rtl_fw_page_write(hw, page, (bufferptr + offset), ++ FW_8192D_PAGE_SIZE); ++ } ++ if (remainsize) { ++ offset = pagenums * FW_8192D_PAGE_SIZE; ++ page = pagenums; ++ rtl_fw_page_write(hw, page, (bufferptr + offset), remainsize); ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_write_fw); ++ ++int rtl92d_fw_free_to_go(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 counter = 0; ++ u32 value32; ++ ++ do { ++ value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); ++ } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) && ++ (!(value32 & FWDL_CHKSUM_RPT))); ++ if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) { ++ pr_err("chksum report fail! REG_MCUFWDL:0x%08x\n", ++ value32); ++ return -EIO; ++ } ++ value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); ++ value32 |= MCUFWDL_RDY; ++ rtl_write_dword(rtlpriv, REG_MCUFWDL, value32); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go); ++ ++void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 u1b_tmp; ++ u8 delay = 100; ++ ++ /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ ++ rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); ++ u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); ++ while (u1b_tmp & BIT(2)) { ++ delay--; ++ if (delay == 0) ++ break; ++ udelay(50); ++ u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); ++ } ++ WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n"); ++ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, ++ "=====> 8051 reset success (%d)\n", delay); ++} ++EXPORT_SYMBOL_GPL(rtl92d_firmware_selfreset); ++ ++int rtl92d_fw_init(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u32 counter; ++ ++ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, "FW already have download\n"); ++ /* polling for FW ready */ ++ counter = 0; ++ do { ++ if (rtlhal->interfaceindex == 0) { ++ if (rtl_read_byte(rtlpriv, FW_MAC0_READY) & ++ MAC0_READY) { ++ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, ++ "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", ++ rtl_read_byte(rtlpriv, ++ FW_MAC0_READY)); ++ return 0; ++ } ++ udelay(5); ++ } else { ++ if (rtl_read_byte(rtlpriv, FW_MAC1_READY) & ++ MAC1_READY) { ++ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, ++ "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", ++ rtl_read_byte(rtlpriv, ++ FW_MAC1_READY)); ++ return 0; ++ } ++ udelay(5); ++ } ++ } while (counter++ < POLLING_READY_TIMEOUT_COUNT); ++ ++ if (rtlhal->interfaceindex == 0) { ++ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, ++ "Polling FW ready fail!! MAC0 FW init not ready: 0x%x\n", ++ rtl_read_byte(rtlpriv, FW_MAC0_READY)); ++ } else { ++ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, ++ "Polling FW ready fail!! MAC1 FW init not ready: 0x%x\n", ++ rtl_read_byte(rtlpriv, FW_MAC1_READY)); ++ } ++ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, ++ "Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", ++ rtl_read_dword(rtlpriv, REG_MCUFWDL)); ++ return -1; ++} ++EXPORT_SYMBOL_GPL(rtl92d_fw_init); ++ ++static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 val_hmetfr; ++ bool result = false; ++ ++ val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR); ++ if (((val_hmetfr >> boxnum) & BIT(0)) == 0) ++ result = true; ++ return result; ++} ++ ++static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, ++ u8 element_id, u32 cmd_len, u8 *cmdbuffer) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); ++ u8 boxnum; ++ u16 box_reg = 0, box_extreg = 0; ++ u8 u1b_tmp; ++ bool isfw_read = false; ++ u8 buf_index = 0; ++ bool bwrite_success = false; ++ u8 wait_h2c_limmit = 100; ++ u8 wait_writeh2c_limmit = 100; ++ u8 boxcontent[4], boxextcontent[2]; ++ u32 h2c_waitcounter = 0; ++ unsigned long flag; ++ u8 idx; ++ ++ if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) { ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "Return as RF is off!!!\n"); ++ return; ++ } ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n"); ++ while (true) { ++ spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); ++ if (rtlhal->h2c_setinprogress) { ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "H2C set in progress! Wait to set..element_id(%d)\n", ++ element_id); ++ ++ while (rtlhal->h2c_setinprogress) { ++ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, ++ flag); ++ h2c_waitcounter++; ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "Wait 100 us (%d times)...\n", ++ h2c_waitcounter); ++ udelay(100); ++ ++ if (h2c_waitcounter > 1000) ++ return; ++ ++ spin_lock_irqsave(&rtlpriv->locks.h2c_lock, ++ flag); ++ } ++ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); ++ } else { ++ rtlhal->h2c_setinprogress = true; ++ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); ++ break; ++ } ++ } ++ while (!bwrite_success) { ++ wait_writeh2c_limmit--; ++ if (wait_writeh2c_limmit == 0) { ++ pr_err("Write H2C fail because no trigger for FW INT!\n"); ++ break; ++ } ++ boxnum = rtlhal->last_hmeboxnum; ++ switch (boxnum) { ++ case 0: ++ box_reg = REG_HMEBOX_0; ++ box_extreg = REG_HMEBOX_EXT_0; ++ break; ++ case 1: ++ box_reg = REG_HMEBOX_1; ++ box_extreg = REG_HMEBOX_EXT_1; ++ break; ++ case 2: ++ box_reg = REG_HMEBOX_2; ++ box_extreg = REG_HMEBOX_EXT_2; ++ break; ++ case 3: ++ box_reg = REG_HMEBOX_3; ++ box_extreg = REG_HMEBOX_EXT_3; ++ break; ++ default: ++ pr_err("switch case %#x not processed\n", ++ boxnum); ++ break; ++ } ++ isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); ++ while (!isfw_read) { ++ wait_h2c_limmit--; ++ if (wait_h2c_limmit == 0) { ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "Waiting too long for FW read clear HMEBox(%d)!\n", ++ boxnum); ++ break; ++ } ++ udelay(10); ++ isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); ++ u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF); ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", ++ boxnum, u1b_tmp); ++ } ++ if (!isfw_read) { ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n", ++ boxnum); ++ break; ++ } ++ memset(boxcontent, 0, sizeof(boxcontent)); ++ memset(boxextcontent, 0, sizeof(boxextcontent)); ++ boxcontent[0] = element_id; ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "Write element_id box_reg(%4x) = %2x\n", ++ box_reg, element_id); ++ switch (cmd_len) { ++ case 1: ++ boxcontent[0] &= ~(BIT(7)); ++ memcpy(boxcontent + 1, cmdbuffer + buf_index, 1); ++ for (idx = 0; idx < 4; idx++) ++ rtl_write_byte(rtlpriv, box_reg + idx, ++ boxcontent[idx]); ++ break; ++ case 2: ++ boxcontent[0] &= ~(BIT(7)); ++ memcpy(boxcontent + 1, cmdbuffer + buf_index, 2); ++ for (idx = 0; idx < 4; idx++) ++ rtl_write_byte(rtlpriv, box_reg + idx, ++ boxcontent[idx]); ++ break; ++ case 3: ++ boxcontent[0] &= ~(BIT(7)); ++ memcpy(boxcontent + 1, cmdbuffer + buf_index, 3); ++ for (idx = 0; idx < 4; idx++) ++ rtl_write_byte(rtlpriv, box_reg + idx, ++ boxcontent[idx]); ++ break; ++ case 4: ++ boxcontent[0] |= (BIT(7)); ++ memcpy(boxextcontent, cmdbuffer + buf_index, 2); ++ memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2); ++ for (idx = 0; idx < 2; idx++) ++ rtl_write_byte(rtlpriv, box_extreg + idx, ++ boxextcontent[idx]); ++ for (idx = 0; idx < 4; idx++) ++ rtl_write_byte(rtlpriv, box_reg + idx, ++ boxcontent[idx]); ++ break; ++ case 5: ++ boxcontent[0] |= (BIT(7)); ++ memcpy(boxextcontent, cmdbuffer + buf_index, 2); ++ memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3); ++ for (idx = 0; idx < 2; idx++) ++ rtl_write_byte(rtlpriv, box_extreg + idx, ++ boxextcontent[idx]); ++ for (idx = 0; idx < 4; idx++) ++ rtl_write_byte(rtlpriv, box_reg + idx, ++ boxcontent[idx]); ++ break; ++ default: ++ pr_err("switch case %#x not processed\n", ++ cmd_len); ++ break; ++ } ++ bwrite_success = true; ++ rtlhal->last_hmeboxnum = boxnum + 1; ++ if (rtlhal->last_hmeboxnum == 4) ++ rtlhal->last_hmeboxnum = 0; ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, ++ "pHalData->last_hmeboxnum = %d\n", ++ rtlhal->last_hmeboxnum); ++ } ++ spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); ++ rtlhal->h2c_setinprogress = false; ++ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n"); ++} ++ ++void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, ++ u8 element_id, u32 cmd_len, u8 *cmdbuffer) ++{ ++ u32 tmp_cmdbuf[2]; ++ ++ memset(tmp_cmdbuf, 0, 8); ++ memcpy(tmp_cmdbuf, cmdbuffer, cmd_len); ++ _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf); ++} ++EXPORT_SYMBOL_GPL(rtl92d_fill_h2c_cmd); ++ ++void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) ++{ ++ u8 u1_joinbssrpt_parm[1] = {0}; ++ ++ u1_joinbssrpt_parm[0] = mstatus; ++ rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm); ++} ++EXPORT_SYMBOL_GPL(rtl92d_set_fw_joinbss_report_cmd); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h +new file mode 100644 +index 000000000000..4e8e2b716f88 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h +@@ -0,0 +1,39 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#ifndef __RTL92D_FW_COMMON_H__ ++#define __RTL92D_FW_COMMON_H__ ++ ++#define FW_8192D_START_ADDRESS 0x1000 ++#define FW_8192D_PAGE_SIZE 4096 ++#define FW_8192D_POLLING_TIMEOUT_COUNT 1000 ++ ++#define IS_FW_HEADER_EXIST(_pfwhdr) \ ++ ((GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x92C0 || \ ++ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x88C0 || \ ++ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D0 || \ ++ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D1 || \ ++ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D2 || \ ++ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D3) ++ ++/* Firmware Header(8-byte alinment required) */ ++/* --- LONG WORD 0 ---- */ ++#define GET_FIRMWARE_HDR_SIGNATURE(__fwhdr) \ ++ le32_get_bits(*(__le32 *)__fwhdr, GENMASK(15, 0)) ++#define GET_FIRMWARE_HDR_VERSION(__fwhdr) \ ++ le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(15, 0)) ++#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \ ++ le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(23, 16)) ++ ++bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv); ++void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable); ++void rtl92d_write_fw(struct ieee80211_hw *hw, ++ enum version_8192d version, u8 *buffer, u32 size); ++int rtl92d_fw_free_to_go(struct ieee80211_hw *hw); ++void rtl92d_firmware_selfreset(struct ieee80211_hw *hw); ++int rtl92d_fw_init(struct ieee80211_hw *hw); ++void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, ++ u32 cmd_len, u8 *p_cmdbuffer); ++void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +new file mode 100644 +index 000000000000..e70e83252e16 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +@@ -0,0 +1,1191 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../base.h" ++#include "../cam.h" ++#include "../efuse.h" ++#include "../pci.h" ++#include "../regd.h" ++#include "def.h" ++#include "reg.h" ++#include "dm_common.h" ++#include "fw_common.h" ++#include "hw_common.h" ++#include "phy_common.h" ++ ++void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 tmp1byte; ++ ++ tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); ++ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); ++ rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); ++ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); ++ tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); ++ tmp1byte &= ~(BIT(0)); ++ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); ++} ++EXPORT_SYMBOL_GPL(rtl92de_stop_tx_beacon); ++ ++void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 tmp1byte; ++ ++ tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); ++ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); ++ rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); ++ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); ++ tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); ++ tmp1byte |= BIT(0); ++ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); ++} ++EXPORT_SYMBOL_GPL(rtl92de_resume_tx_beacon); ++ ++void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); ++ ++ switch (variable) { ++ case HW_VAR_RF_STATE: ++ *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; ++ break; ++ case HW_VAR_FWLPS_RF_ON:{ ++ enum rf_pwrstate rfstate; ++ u32 val_rcr; ++ ++ rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, ++ (u8 *)(&rfstate)); ++ if (rfstate == ERFOFF) { ++ *((bool *)(val)) = true; ++ } else { ++ val_rcr = rtl_read_dword(rtlpriv, REG_RCR); ++ val_rcr &= 0x00070000; ++ if (val_rcr) ++ *((bool *)(val)) = false; ++ else ++ *((bool *)(val)) = true; ++ } ++ break; ++ } ++ case HW_VAR_FW_PSMODE_STATUS: ++ *((bool *)(val)) = ppsc->fw_current_inpsmode; ++ break; ++ case HW_VAR_CORRECT_TSF:{ ++ u64 tsf; ++ u32 *ptsf_low = (u32 *)&tsf; ++ u32 *ptsf_high = ((u32 *)&tsf) + 1; ++ ++ *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); ++ *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); ++ *((u64 *)(val)) = tsf; ++ break; ++ } ++ case HW_VAR_INT_MIGRATION: ++ *((bool *)(val)) = rtlpriv->dm.interrupt_migration; ++ break; ++ case HW_VAR_INT_AC: ++ *((bool *)(val)) = rtlpriv->dm.disable_tx_int; ++ break; ++ case HAL_DEF_WOWLAN: ++ break; ++ default: ++ pr_err("switch case %#x not processed\n", variable); ++ break; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_get_hw_reg); ++ ++void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); ++ u8 idx; ++ ++ switch (variable) { ++ case HW_VAR_ETHER_ADDR: ++ for (idx = 0; idx < ETH_ALEN; idx++) { ++ rtl_write_byte(rtlpriv, (REG_MACID + idx), ++ val[idx]); ++ } ++ break; ++ case HW_VAR_BASIC_RATE: { ++ u16 rate_cfg = ((u16 *)val)[0]; ++ u8 rate_index = 0; ++ ++ rate_cfg = rate_cfg & 0x15f; ++ if (mac->vendor == PEER_CISCO && ++ ((rate_cfg & 0x150) == 0)) ++ rate_cfg |= 0x01; ++ rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); ++ rtl_write_byte(rtlpriv, REG_RRSR + 1, ++ (rate_cfg >> 8) & 0xff); ++ while (rate_cfg > 0x1) { ++ rate_cfg = (rate_cfg >> 1); ++ rate_index++; ++ } ++ if (rtlhal->fw_version > 0xe) ++ rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, ++ rate_index); ++ break; ++ } ++ case HW_VAR_BSSID: ++ for (idx = 0; idx < ETH_ALEN; idx++) { ++ rtl_write_byte(rtlpriv, (REG_BSSID + idx), ++ val[idx]); ++ } ++ break; ++ case HW_VAR_SIFS: ++ rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); ++ rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); ++ rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); ++ rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); ++ if (!mac->ht_enable) ++ rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, ++ 0x0e0e); ++ else ++ rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, ++ *((u16 *)val)); ++ break; ++ case HW_VAR_SLOT_TIME: { ++ u8 e_aci; ++ ++ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, ++ "HW_VAR_SLOT_TIME %x\n", val[0]); ++ rtl_write_byte(rtlpriv, REG_SLOT, val[0]); ++ for (e_aci = 0; e_aci < AC_MAX; e_aci++) ++ rtlpriv->cfg->ops->set_hw_reg(hw, ++ HW_VAR_AC_PARAM, ++ (&e_aci)); ++ break; ++ } ++ case HW_VAR_ACK_PREAMBLE: { ++ u8 reg_tmp; ++ u8 short_preamble = (bool)(*val); ++ ++ reg_tmp = (mac->cur_40_prime_sc) << 5; ++ if (short_preamble) ++ reg_tmp |= 0x80; ++ rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); ++ break; ++ } ++ case HW_VAR_AMPDU_MIN_SPACE: { ++ u8 min_spacing_to_set; ++ ++ min_spacing_to_set = *val; ++ if (min_spacing_to_set <= 7) { ++ mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | ++ min_spacing_to_set); ++ *val = min_spacing_to_set; ++ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, ++ "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", ++ mac->min_space_cfg); ++ rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, ++ mac->min_space_cfg); ++ } ++ break; ++ } ++ case HW_VAR_SHORTGI_DENSITY: { ++ u8 density_to_set; ++ ++ density_to_set = *val; ++ mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; ++ mac->min_space_cfg |= (density_to_set << 3); ++ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, ++ "Set HW_VAR_SHORTGI_DENSITY: %#x\n", ++ mac->min_space_cfg); ++ rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, ++ mac->min_space_cfg); ++ break; ++ } ++ case HW_VAR_AMPDU_FACTOR: { ++ u8 factor_toset; ++ u32 regtoset; ++ u8 *ptmp_byte = NULL; ++ u8 index; ++ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY) ++ regtoset = 0xb9726641; ++ else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) ++ regtoset = 0x66626641; ++ else ++ regtoset = 0xb972a841; ++ factor_toset = *val; ++ if (factor_toset <= 3) { ++ factor_toset = (1 << (factor_toset + 2)); ++ if (factor_toset > 0xf) ++ factor_toset = 0xf; ++ for (index = 0; index < 4; index++) { ++ ptmp_byte = (u8 *)(®toset) + index; ++ if ((*ptmp_byte & 0xf0) > ++ (factor_toset << 4)) ++ *ptmp_byte = (*ptmp_byte & 0x0f) ++ | (factor_toset << 4); ++ if ((*ptmp_byte & 0x0f) > factor_toset) ++ *ptmp_byte = (*ptmp_byte & 0xf0) ++ | (factor_toset); ++ } ++ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset); ++ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, ++ "Set HW_VAR_AMPDU_FACTOR: %#x\n", ++ factor_toset); ++ } ++ break; ++ } ++ case HW_VAR_RETRY_LIMIT: { ++ u8 retry_limit = val[0]; ++ ++ rtl_write_word(rtlpriv, REG_RL, ++ retry_limit << RETRY_LIMIT_SHORT_SHIFT | ++ retry_limit << RETRY_LIMIT_LONG_SHIFT); ++ break; ++ } ++ case HW_VAR_DUAL_TSF_RST: ++ rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); ++ break; ++ case HW_VAR_EFUSE_BYTES: ++ rtlefuse->efuse_usedbytes = *((u16 *)val); ++ break; ++ case HW_VAR_EFUSE_USAGE: ++ rtlefuse->efuse_usedpercentage = *val; ++ break; ++ case HW_VAR_IO_CMD: ++ rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); ++ break; ++ case HW_VAR_WPA_CONFIG: ++ rtl_write_byte(rtlpriv, REG_SECCFG, *val); ++ break; ++ case HW_VAR_SET_RPWM: ++ rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val)); ++ break; ++ case HW_VAR_H2C_FW_PWRMODE: ++ break; ++ case HW_VAR_FW_PSMODE_STATUS: ++ ppsc->fw_current_inpsmode = *((bool *)val); ++ break; ++ case HW_VAR_AID: { ++ u16 u2btmp; ++ ++ u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); ++ u2btmp &= 0xC000; ++ rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | ++ mac->assoc_id)); ++ break; ++ } ++ default: ++ pr_err("switch case %#x not processed\n", variable); ++ break; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_set_hw_reg); ++ ++bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ bool status = true; ++ long count = 0; ++ u32 value = _LLT_INIT_ADDR(address) | ++ _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); ++ ++ rtl_write_dword(rtlpriv, REG_LLT_INIT, value); ++ do { ++ value = rtl_read_dword(rtlpriv, REG_LLT_INIT); ++ if (_LLT_OP_VALUE(value) == _LLT_NO_ACTIVE) ++ break; ++ if (count > POLLING_LLT_THRESHOLD) { ++ pr_err("Failed to polling write LLT done at address %d!\n", ++ address); ++ status = false; ++ break; ++ } ++ } while (++count); ++ return status; ++} ++EXPORT_SYMBOL_GPL(rtl92de_llt_write); ++ ++void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 sec_reg_value; ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", ++ rtlpriv->sec.pairwise_enc_algorithm, ++ rtlpriv->sec.group_enc_algorithm); ++ if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, ++ "not open hw encryption\n"); ++ return; ++ } ++ sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; ++ if (rtlpriv->sec.use_defaultkey) { ++ sec_reg_value |= SCR_TXUSEDK; ++ sec_reg_value |= SCR_RXUSEDK; ++ } ++ sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); ++ rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, ++ "The SECR-value %x\n", sec_reg_value); ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); ++} ++EXPORT_SYMBOL_GPL(rtl92de_enable_hw_security_config); ++ ++/* don't set REG_EDCA_BE_PARAM here because ++ * mac80211 will send pkt when scan ++ */ ++void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) ++{ ++ rtl92d_dm_init_edca_turbo(hw); ++} ++EXPORT_SYMBOL_GPL(rtl92de_set_qos); ++ ++static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; ++ u32 value32; ++ ++ value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); ++ if (!(value32 & 0x000f0000)) { ++ version = VERSION_TEST_CHIP_92D_SINGLEPHY; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); ++ } else { ++ version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); ++ } ++ return version; ++} ++ ++static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, ++ u8 *rom_content, bool autoloadfail) ++{ ++ u32 rfpath, eeaddr, group, offset1, offset2; ++ u8 i; ++ ++ memset(pwrinfo, 0, sizeof(struct txpower_info)); ++ if (autoloadfail) { ++ for (group = 0; group < CHANNEL_GROUP_MAX; group++) { ++ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { ++ if (group < CHANNEL_GROUP_MAX_2G) { ++ pwrinfo->cck_index[rfpath][group] = ++ EEPROM_DEFAULT_TXPOWERLEVEL_2G; ++ pwrinfo->ht40_1sindex[rfpath][group] = ++ EEPROM_DEFAULT_TXPOWERLEVEL_2G; ++ } else { ++ pwrinfo->ht40_1sindex[rfpath][group] = ++ EEPROM_DEFAULT_TXPOWERLEVEL_5G; ++ } ++ pwrinfo->ht40_2sindexdiff[rfpath][group] = ++ EEPROM_DEFAULT_HT40_2SDIFF; ++ pwrinfo->ht20indexdiff[rfpath][group] = ++ EEPROM_DEFAULT_HT20_DIFF; ++ pwrinfo->ofdmindexdiff[rfpath][group] = ++ EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; ++ pwrinfo->ht40maxoffset[rfpath][group] = ++ EEPROM_DEFAULT_HT40_PWRMAXOFFSET; ++ pwrinfo->ht20maxoffset[rfpath][group] = ++ EEPROM_DEFAULT_HT20_PWRMAXOFFSET; ++ } ++ } ++ for (i = 0; i < 3; i++) { ++ pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; ++ pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; ++ } ++ return; ++ } ++ ++ /* Maybe autoload OK,buf the tx power index value is not filled. ++ * If we find it, we set it to default value. ++ */ ++ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { ++ for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { ++ eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) ++ + group; ++ pwrinfo->cck_index[rfpath][group] = ++ (rom_content[eeaddr] == 0xFF) ? ++ (eeaddr > 0x7B ? ++ EEPROM_DEFAULT_TXPOWERLEVEL_5G : ++ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : ++ rom_content[eeaddr]; ++ } ++ } ++ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { ++ for (group = 0; group < CHANNEL_GROUP_MAX; group++) { ++ offset1 = group / 3; ++ offset2 = group % 3; ++ eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + ++ offset2 + offset1 * 21; ++ pwrinfo->ht40_1sindex[rfpath][group] = ++ (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? ++ EEPROM_DEFAULT_TXPOWERLEVEL_5G : ++ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : ++ rom_content[eeaddr]; ++ } ++ } ++ /* These just for 92D efuse offset. */ ++ for (group = 0; group < CHANNEL_GROUP_MAX; group++) { ++ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { ++ int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; ++ ++ offset1 = group / 3; ++ offset2 = group % 3; ++ ++ if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) ++ pwrinfo->ht40_2sindexdiff[rfpath][group] = ++ (rom_content[base1 + ++ offset2 + offset1 * 21] >> (rfpath * 4)) ++ & 0xF; ++ else ++ pwrinfo->ht40_2sindexdiff[rfpath][group] = ++ EEPROM_DEFAULT_HT40_2SDIFF; ++ if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 ++ + offset1 * 21] != 0xFF) ++ pwrinfo->ht20indexdiff[rfpath][group] = ++ (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G ++ + offset2 + offset1 * 21] >> (rfpath * 4)) ++ & 0xF; ++ else ++ pwrinfo->ht20indexdiff[rfpath][group] = ++ EEPROM_DEFAULT_HT20_DIFF; ++ if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 ++ + offset1 * 21] != 0xFF) ++ pwrinfo->ofdmindexdiff[rfpath][group] = ++ (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G ++ + offset2 + offset1 * 21] >> (rfpath * 4)) ++ & 0xF; ++ else ++ pwrinfo->ofdmindexdiff[rfpath][group] = ++ EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; ++ if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 ++ + offset1 * 21] != 0xFF) ++ pwrinfo->ht40maxoffset[rfpath][group] = ++ (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G ++ + offset2 + offset1 * 21] >> (rfpath * 4)) ++ & 0xF; ++ else ++ pwrinfo->ht40maxoffset[rfpath][group] = ++ EEPROM_DEFAULT_HT40_PWRMAXOFFSET; ++ if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 ++ + offset1 * 21] != 0xFF) ++ pwrinfo->ht20maxoffset[rfpath][group] = ++ (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + ++ offset2 + offset1 * 21] >> (rfpath * 4)) & ++ 0xF; ++ else ++ pwrinfo->ht20maxoffset[rfpath][group] = ++ EEPROM_DEFAULT_HT20_PWRMAXOFFSET; ++ } ++ } ++ if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { ++ /* 5GL */ ++ pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; ++ pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; ++ /* 5GM */ ++ pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; ++ pwrinfo->tssi_b[1] = ++ (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | ++ (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; ++ /* 5GH */ ++ pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & ++ 0xF0) >> 4 | ++ (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; ++ pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & ++ 0xFC) >> 2; ++ } else { ++ for (i = 0; i < 3; i++) { ++ pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; ++ pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; ++ } ++ } ++} ++ ++static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, ++ bool autoload_fail, u8 *hwinfo) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct txpower_info pwrinfo; ++ u8 tempval[2], i, pwr, diff; ++ u32 ch, rfpath, group; ++ ++ _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); ++ if (!autoload_fail) { ++ /* bit0~2 */ ++ rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); ++ rtlefuse->eeprom_thermalmeter = ++ hwinfo[EEPROM_THERMAL_METER] & 0x1f; ++ rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K]; ++ tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; ++ tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; ++ rtlefuse->txpwr_fromeprom = true; ++ if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || ++ IS_92D_E_CUT(rtlpriv->rtlhal.version)) { ++ rtlefuse->internal_pa_5g[0] = ++ !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); ++ rtlefuse->internal_pa_5g[1] = ++ !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, ++ "Is D cut,Internal PA0 %d Internal PA1 %d\n", ++ rtlefuse->internal_pa_5g[0], ++ rtlefuse->internal_pa_5g[1]); ++ } ++ rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6]; ++ rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7]; ++ } else { ++ rtlefuse->eeprom_regulatory = 0; ++ rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; ++ rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP; ++ tempval[0] = 3; ++ tempval[1] = tempval[0]; ++ } ++ ++ /* Use default value to fill parameters if ++ * efuse is not filled on some place. ++ */ ++ ++ /* ThermalMeter from EEPROM */ ++ if (rtlefuse->eeprom_thermalmeter < 0x06 || ++ rtlefuse->eeprom_thermalmeter > 0x1c) ++ rtlefuse->eeprom_thermalmeter = 0x12; ++ rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; ++ ++ /* check XTAL_K */ ++ if (rtlefuse->crystalcap == 0xFF) ++ rtlefuse->crystalcap = 0; ++ if (rtlefuse->eeprom_regulatory > 3) ++ rtlefuse->eeprom_regulatory = 0; ++ ++ for (i = 0; i < 2; i++) { ++ switch (tempval[i]) { ++ case 0: ++ tempval[i] = 5; ++ break; ++ case 1: ++ tempval[i] = 4; ++ break; ++ case 2: ++ tempval[i] = 3; ++ break; ++ case 3: ++ default: ++ tempval[i] = 0; ++ break; ++ } ++ } ++ ++ rtlefuse->delta_iqk = tempval[0]; ++ if (tempval[1] > 0) ++ rtlefuse->delta_lck = tempval[1] - 1; ++ if (rtlefuse->eeprom_c9 == 0xFF) ++ rtlefuse->eeprom_c9 = 0x00; ++ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, ++ "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory); ++ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, ++ "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); ++ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, ++ "CrystalCap = 0x%x\n", rtlefuse->crystalcap); ++ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, ++ "Delta_IQK = 0x%x Delta_LCK = 0x%x\n", ++ rtlefuse->delta_iqk, rtlefuse->delta_lck); ++ ++ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { ++ for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { ++ group = rtl92d_get_chnlgroup_fromarray((u8)ch); ++ if (ch < CHANNEL_MAX_NUMBER_2G) ++ rtlefuse->txpwrlevel_cck[rfpath][ch] = ++ pwrinfo.cck_index[rfpath][group]; ++ rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] = ++ pwrinfo.ht40_1sindex[rfpath][group]; ++ rtlefuse->txpwr_ht20diff[rfpath][ch] = ++ pwrinfo.ht20indexdiff[rfpath][group]; ++ rtlefuse->txpwr_legacyhtdiff[rfpath][ch] = ++ pwrinfo.ofdmindexdiff[rfpath][group]; ++ rtlefuse->pwrgroup_ht20[rfpath][ch] = ++ pwrinfo.ht20maxoffset[rfpath][group]; ++ rtlefuse->pwrgroup_ht40[rfpath][ch] = ++ pwrinfo.ht40maxoffset[rfpath][group]; ++ pwr = pwrinfo.ht40_1sindex[rfpath][group]; ++ diff = pwrinfo.ht40_2sindexdiff[rfpath][group]; ++ rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] = ++ (pwr > diff) ? (pwr - diff) : 0; ++ } ++ } ++} ++ ++static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, ++ u8 *content) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; ++ ++ if (macphy_crvalue & BIT(3)) { ++ rtlhal->macphymode = SINGLEMAC_SINGLEPHY; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "MacPhyMode SINGLEMAC_SINGLEPHY\n"); ++ } else { ++ rtlhal->macphymode = DUALMAC_DUALPHY; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "MacPhyMode DUALMAC_DUALPHY\n"); ++ } ++} ++ ++static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, ++ u8 *content) ++{ ++ _rtl92de_read_macphymode_from_prom(hw, content); ++ rtl92d_phy_config_macphymode(hw); ++ rtl92d_phy_config_macphymode_info(hw); ++} ++ ++static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ enum version_8192d chipver = rtlpriv->rtlhal.version; ++ u8 cutvalue[2]; ++ u16 chipvalue; ++ ++ read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, &cutvalue[1]); ++ read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, &cutvalue[0]); ++ chipvalue = (cutvalue[1] << 8) | cutvalue[0]; ++ switch (chipvalue) { ++ case 0xAA55: ++ chipver |= CHIP_92D_C_CUT; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); ++ break; ++ case 0x9966: ++ chipver |= CHIP_92D_D_CUT; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); ++ break; ++ case 0xCC33: ++ chipver |= CHIP_92D_E_CUT; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); ++ break; ++ default: ++ chipver |= CHIP_92D_D_CUT; ++ pr_err("Unknown CUT!\n"); ++ break; ++ } ++ rtlpriv->rtlhal.version = chipver; ++} ++ ++static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, ++ EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, ++ EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, ++ COUNTRY_CODE_WORLD_WIDE_13}; ++ int i; ++ u16 usvalue; ++ u8 *hwinfo; ++ ++ hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); ++ if (!hwinfo) ++ return; ++ ++ if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) ++ goto exit; ++ ++ _rtl92de_efuse_update_chip_version(hw); ++ _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); ++ ++ /* Read Permanent MAC address for 2nd interface */ ++ if (rtlhal->interfaceindex != 0) { ++ for (i = 0; i < 6; i += 2) { ++ usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; ++ *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue; ++ } ++ } ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, ++ rtlefuse->dev_addr); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); ++ _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); ++ ++ /* Read Channel Plan */ ++ switch (rtlhal->bandset) { ++ case BAND_ON_2_4G: ++ rtlefuse->channel_plan = COUNTRY_CODE_TELEC; ++ break; ++ case BAND_ON_5G: ++ rtlefuse->channel_plan = COUNTRY_CODE_FCC; ++ break; ++ case BAND_ON_BOTH: ++ rtlefuse->channel_plan = COUNTRY_CODE_FCC; ++ break; ++ default: ++ rtlefuse->channel_plan = COUNTRY_CODE_FCC; ++ break; ++ } ++ rtlefuse->txpwr_fromeprom = true; ++exit: ++ kfree(hwinfo); ++} ++ ++void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u8 tmp_u1b; ++ ++ rtlhal->version = _rtl92d_read_chip_version(hw); ++ tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); ++ rtlefuse->autoload_status = tmp_u1b; ++ if (tmp_u1b & BIT(4)) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); ++ rtlefuse->epromtype = EEPROM_93C46; ++ } else { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); ++ rtlefuse->epromtype = EEPROM_BOOT_EFUSE; ++ } ++ if (tmp_u1b & BIT(5)) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); ++ ++ rtlefuse->autoload_failflag = false; ++ _rtl92de_read_adapter_info(hw); ++ } else { ++ pr_err("Autoload ERR!!\n"); ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92de_read_eeprom_info); ++ ++static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u32 ratr_value; ++ u8 ratr_index = 0; ++ u8 nmode = mac->ht_enable; ++ u8 mimo_ps = IEEE80211_SMPS_OFF; ++ u16 shortgi_rate; ++ u32 tmp_ratr_value; ++ u8 curtxbw_40mhz = mac->bw_40; ++ u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? ++ 1 : 0; ++ u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? ++ 1 : 0; ++ enum wireless_mode wirelessmode = mac->mode; ++ ++ if (rtlhal->current_bandtype == BAND_ON_5G) ++ ratr_value = sta->deflink.supp_rates[1] << 4; ++ else ++ ratr_value = sta->deflink.supp_rates[0]; ++ ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | ++ sta->deflink.ht_cap.mcs.rx_mask[0] << 12); ++ switch (wirelessmode) { ++ case WIRELESS_MODE_A: ++ ratr_value &= 0x00000FF0; ++ break; ++ case WIRELESS_MODE_B: ++ if (ratr_value & 0x0000000c) ++ ratr_value &= 0x0000000d; ++ else ++ ratr_value &= 0x0000000f; ++ break; ++ case WIRELESS_MODE_G: ++ ratr_value &= 0x00000FF5; ++ break; ++ case WIRELESS_MODE_N_24G: ++ case WIRELESS_MODE_N_5G: ++ nmode = 1; ++ if (mimo_ps == IEEE80211_SMPS_STATIC) { ++ ratr_value &= 0x0007F005; ++ } else { ++ u32 ratr_mask; ++ ++ if (get_rf_type(rtlphy) == RF_1T2R || ++ get_rf_type(rtlphy) == RF_1T1R) { ++ ratr_mask = 0x000ff005; ++ } else { ++ ratr_mask = 0x0f0ff005; ++ } ++ ++ ratr_value &= ratr_mask; ++ } ++ break; ++ default: ++ if (rtlphy->rf_type == RF_1T2R) ++ ratr_value &= 0x000ff0ff; ++ else ++ ratr_value &= 0x0f0ff0ff; ++ ++ break; ++ } ++ ratr_value &= 0x0FFFFFFF; ++ if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || ++ (!curtxbw_40mhz && curshortgi_20mhz))) { ++ ratr_value |= 0x10000000; ++ tmp_ratr_value = (ratr_value >> 12); ++ for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { ++ if ((1 << shortgi_rate) & tmp_ratr_value) ++ break; ++ } ++ shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | ++ (shortgi_rate << 4) | (shortgi_rate); ++ } ++ rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); ++ rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", ++ rtl_read_dword(rtlpriv, REG_ARFR0)); ++} ++ ++static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta, ++ u8 rssi_level, bool update_bw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_sta_info *sta_entry = NULL; ++ u32 ratr_bitmap; ++ u8 ratr_index; ++ u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; ++ u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? ++ 1 : 0; ++ u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? ++ 1 : 0; ++ enum wireless_mode wirelessmode = 0; ++ bool shortgi = false; ++ u32 value[2]; ++ u8 macid = 0; ++ u8 mimo_ps = IEEE80211_SMPS_OFF; ++ ++ sta_entry = (struct rtl_sta_info *)sta->drv_priv; ++ mimo_ps = sta_entry->mimo_ps; ++ wirelessmode = sta_entry->wireless_mode; ++ if (mac->opmode == NL80211_IFTYPE_STATION) ++ curtxbw_40mhz = mac->bw_40; ++ else if (mac->opmode == NL80211_IFTYPE_AP || ++ mac->opmode == NL80211_IFTYPE_ADHOC) ++ macid = sta->aid + 1; ++ ++ if (rtlhal->current_bandtype == BAND_ON_5G) ++ ratr_bitmap = sta->deflink.supp_rates[1] << 4; ++ else ++ ratr_bitmap = sta->deflink.supp_rates[0]; ++ ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | ++ sta->deflink.ht_cap.mcs.rx_mask[0] << 12); ++ switch (wirelessmode) { ++ case WIRELESS_MODE_B: ++ ratr_index = RATR_INX_WIRELESS_B; ++ if (ratr_bitmap & 0x0000000c) ++ ratr_bitmap &= 0x0000000d; ++ else ++ ratr_bitmap &= 0x0000000f; ++ break; ++ case WIRELESS_MODE_G: ++ ratr_index = RATR_INX_WIRELESS_GB; ++ ++ if (rssi_level == 1) ++ ratr_bitmap &= 0x00000f00; ++ else if (rssi_level == 2) ++ ratr_bitmap &= 0x00000ff0; ++ else ++ ratr_bitmap &= 0x00000ff5; ++ break; ++ case WIRELESS_MODE_A: ++ ratr_index = RATR_INX_WIRELESS_G; ++ ratr_bitmap &= 0x00000ff0; ++ break; ++ case WIRELESS_MODE_N_24G: ++ case WIRELESS_MODE_N_5G: ++ if (wirelessmode == WIRELESS_MODE_N_24G) ++ ratr_index = RATR_INX_WIRELESS_NGB; ++ else ++ ratr_index = RATR_INX_WIRELESS_NG; ++ if (mimo_ps == IEEE80211_SMPS_STATIC) { ++ if (rssi_level == 1) ++ ratr_bitmap &= 0x00070000; ++ else if (rssi_level == 2) ++ ratr_bitmap &= 0x0007f000; ++ else ++ ratr_bitmap &= 0x0007f005; ++ } else { ++ if (rtlphy->rf_type == RF_1T2R || ++ rtlphy->rf_type == RF_1T1R) { ++ if (curtxbw_40mhz) { ++ if (rssi_level == 1) ++ ratr_bitmap &= 0x000f0000; ++ else if (rssi_level == 2) ++ ratr_bitmap &= 0x000ff000; ++ else ++ ratr_bitmap &= 0x000ff015; ++ } else { ++ if (rssi_level == 1) ++ ratr_bitmap &= 0x000f0000; ++ else if (rssi_level == 2) ++ ratr_bitmap &= 0x000ff000; ++ else ++ ratr_bitmap &= 0x000ff005; ++ } ++ } else { ++ if (curtxbw_40mhz) { ++ if (rssi_level == 1) ++ ratr_bitmap &= 0x0f0f0000; ++ else if (rssi_level == 2) ++ ratr_bitmap &= 0x0f0ff000; ++ else ++ ratr_bitmap &= 0x0f0ff015; ++ } else { ++ if (rssi_level == 1) ++ ratr_bitmap &= 0x0f0f0000; ++ else if (rssi_level == 2) ++ ratr_bitmap &= 0x0f0ff000; ++ else ++ ratr_bitmap &= 0x0f0ff005; ++ } ++ } ++ } ++ if ((curtxbw_40mhz && curshortgi_40mhz) || ++ (!curtxbw_40mhz && curshortgi_20mhz)) { ++ if (macid == 0) ++ shortgi = true; ++ else if (macid == 1) ++ shortgi = false; ++ } ++ break; ++ default: ++ ratr_index = RATR_INX_WIRELESS_NGB; ++ ++ if (rtlphy->rf_type == RF_1T2R) ++ ratr_bitmap &= 0x000ff0ff; ++ else ++ ratr_bitmap &= 0x0f0ff0ff; ++ break; ++ } ++ ++ value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); ++ value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; ++ rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, ++ "ratr_bitmap :%x value0:%x value1:%x\n", ++ ratr_bitmap, value[0], value[1]); ++ rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *)value); ++ if (macid != 0) ++ sta_entry->ratr_index = ratr_index; ++} ++ ++void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta, ++ u8 rssi_level, bool update_bw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ if (rtlpriv->dm.useramask) ++ rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw); ++ else ++ rtl92de_update_hal_rate_table(hw, sta); ++} ++EXPORT_SYMBOL_GPL(rtl92de_update_hal_rate_tbl); ++ ++void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ u16 sifs_timer; ++ ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, ++ &mac->slot_time); ++ if (!mac->ht_enable) ++ sifs_timer = 0x0a0a; ++ else ++ sifs_timer = 0x1010; ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); ++} ++EXPORT_SYMBOL_GPL(rtl92de_update_channel_access_setting); ++ ++bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); ++ struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); ++ enum rf_pwrstate e_rfpowerstate_toset; ++ u8 u1tmp; ++ bool actuallyset = false; ++ unsigned long flag; ++ ++ if (rtlpci->being_init_adapter) ++ return false; ++ if (ppsc->swrf_processing) ++ return false; ++ spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); ++ if (ppsc->rfchange_inprogress) { ++ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); ++ return false; ++ } ++ ++ ppsc->rfchange_inprogress = true; ++ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); ++ ++ rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ++ rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG) & ~(BIT(3))); ++ u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); ++ e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; ++ if (ppsc->hwradiooff && e_rfpowerstate_toset == ERFON) { ++ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, ++ "GPIOChangeRF - HW Radio ON, RF ON\n"); ++ e_rfpowerstate_toset = ERFON; ++ ppsc->hwradiooff = false; ++ actuallyset = true; ++ } else if (!ppsc->hwradiooff && e_rfpowerstate_toset == ERFOFF) { ++ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, ++ "GPIOChangeRF - HW Radio OFF, RF OFF\n"); ++ e_rfpowerstate_toset = ERFOFF; ++ ppsc->hwradiooff = true; ++ actuallyset = true; ++ } ++ if (actuallyset) { ++ spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); ++ ppsc->rfchange_inprogress = false; ++ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); ++ } else { ++ if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) ++ RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); ++ spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); ++ ppsc->rfchange_inprogress = false; ++ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); ++ } ++ *valid = 1; ++ return !ppsc->hwradiooff; ++} ++EXPORT_SYMBOL_GPL(rtl92de_gpio_radio_on_off_checking); ++ ++void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, ++ u8 *p_macaddr, bool is_group, u8 enc_algo, ++ bool is_wepkey, bool clear_all) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ const u8 *macaddr = p_macaddr; ++ u32 entry_id; ++ bool is_pairwise = false; ++ static const u8 cam_const_addr[4][6] = { ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, ++ {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} ++ }; ++ static const u8 cam_const_broad[] = { ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff ++ }; ++ ++ if (clear_all) { ++ u8 idx; ++ u8 cam_offset = 0; ++ u8 clear_number = 5; ++ ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); ++ for (idx = 0; idx < clear_number; idx++) { ++ rtl_cam_mark_invalid(hw, cam_offset + idx); ++ rtl_cam_empty_entry(hw, cam_offset + idx); ++ ++ if (idx < 5) { ++ memset(rtlpriv->sec.key_buf[idx], 0, ++ MAX_KEY_LEN); ++ rtlpriv->sec.key_len[idx] = 0; ++ } ++ } ++ ++ return; ++ } ++ ++ switch (enc_algo) { ++ case WEP40_ENCRYPTION: ++ enc_algo = CAM_WEP40; ++ break; ++ case WEP104_ENCRYPTION: ++ enc_algo = CAM_WEP104; ++ break; ++ case TKIP_ENCRYPTION: ++ enc_algo = CAM_TKIP; ++ break; ++ case AESCCMP_ENCRYPTION: ++ enc_algo = CAM_AES; ++ break; ++ default: ++ pr_err("switch case %#x not processed\n", ++ enc_algo); ++ enc_algo = CAM_TKIP; ++ break; ++ } ++ if (is_wepkey || rtlpriv->sec.use_defaultkey) { ++ macaddr = cam_const_addr[key_index]; ++ entry_id = key_index; ++ } else { ++ if (is_group) { ++ macaddr = cam_const_broad; ++ entry_id = key_index; ++ } else { ++ if (mac->opmode == NL80211_IFTYPE_AP) { ++ entry_id = rtl_cam_get_free_entry(hw, p_macaddr); ++ if (entry_id >= TOTAL_CAM_ENTRY) { ++ pr_err("Can not find free hw security cam entry\n"); ++ return; ++ } ++ } else { ++ entry_id = CAM_PAIRWISE_KEY_POSITION; ++ } ++ key_index = PAIRWISE_KEYIDX; ++ is_pairwise = true; ++ } ++ } ++ if (rtlpriv->sec.key_len[key_index] == 0) { ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, ++ "delete one entry, entry_id is %d\n", ++ entry_id); ++ if (mac->opmode == NL80211_IFTYPE_AP) ++ rtl_cam_del_entry(hw, p_macaddr); ++ rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); ++ } else { ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, ++ "The insert KEY length is %d\n", ++ rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, ++ "The insert KEY is %x %x\n", ++ rtlpriv->sec.key_buf[0][0], ++ rtlpriv->sec.key_buf[0][1]); ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, ++ "add one entry\n"); ++ if (is_pairwise) { ++ RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, ++ "Pairwise Key content", ++ rtlpriv->sec.pairwise_key, ++ rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, ++ "set Pairwise key\n"); ++ rtl_cam_add_one_entry(hw, macaddr, key_index, ++ entry_id, enc_algo, ++ CAM_CONFIG_NO_USEDK, ++ rtlpriv->sec.key_buf[key_index]); ++ } else { ++ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, ++ "set group key\n"); ++ if (mac->opmode == NL80211_IFTYPE_ADHOC) { ++ rtl_cam_add_one_entry(hw, ++ rtlefuse->dev_addr, ++ PAIRWISE_KEYIDX, ++ CAM_PAIRWISE_KEY_POSITION, ++ enc_algo, CAM_CONFIG_NO_USEDK, ++ rtlpriv->sec.key_buf[entry_id]); ++ } ++ rtl_cam_add_one_entry(hw, macaddr, key_index, ++ entry_id, enc_algo, ++ CAM_CONFIG_NO_USEDK, ++ rtlpriv->sec.key_buf ++ [entry_id]); ++ } ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92de_set_key); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h +new file mode 100644 +index 000000000000..2c07f5cc5766 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#ifndef __RTL92D_HW_COMMON_H__ ++#define __RTL92D_HW_COMMON_H__ ++ ++void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw); ++void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw); ++void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); ++void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); ++bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data); ++void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw); ++void rtl92de_set_qos(struct ieee80211_hw *hw, int aci); ++void rtl92de_read_eeprom_info(struct ieee80211_hw *hw); ++void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta, ++ u8 rssi_level, bool update_bw); ++void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw); ++bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); ++void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, ++ u8 *p_macaddr, bool is_group, u8 enc_algo, ++ bool is_wepkey, bool clear_all); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c +new file mode 100644 +index 000000000000..e58dc4000c19 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c +@@ -0,0 +1,9 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include ++ ++MODULE_AUTHOR("Realtek WlanFAE "); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Realtek 8192D 802.11n common routines"); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c +new file mode 100644 +index 000000000000..87c458b27f4f +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c +@@ -0,0 +1,846 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../core.h" ++#include "def.h" ++#include "reg.h" ++#include "dm_common.h" ++#include "phy_common.h" ++#include "rf_common.h" ++ ++static const u8 channel_all[59] = { ++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, ++ 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, ++ 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, ++ 114, 116, 118, 120, 122, 124, 126, 128, 130, ++ 132, 134, 136, 138, 140, 149, 151, 153, 155, ++ 157, 159, 161, 163, 165 ++}; ++ ++static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, ++ enum radio_path rfpath, u32 offset) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; ++ u32 newoffset; ++ u32 tmplong, tmplong2; ++ u8 rfpi_enable = 0; ++ u32 retvalue; ++ ++ newoffset = offset; ++ tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); ++ if (rfpath == RF90_PATH_A) ++ tmplong2 = tmplong; ++ else ++ tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); ++ tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | ++ (newoffset << 23) | BLSSIREADEDGE; ++ rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, ++ tmplong & (~BLSSIREADEDGE)); ++ udelay(10); ++ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); ++ udelay(50); ++ udelay(50); ++ rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, ++ tmplong | BLSSIREADEDGE); ++ udelay(10); ++ if (rfpath == RF90_PATH_A) ++ rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, ++ BIT(8)); ++ else if (rfpath == RF90_PATH_B) ++ rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, ++ BIT(8)); ++ if (rfpi_enable) ++ retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, ++ BLSSIREADBACKDATA); ++ else ++ retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, ++ BLSSIREADBACKDATA); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", ++ rfpath, pphyreg->rf_rb, retvalue); ++ return retvalue; ++} ++ ++static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, ++ enum radio_path rfpath, ++ u32 offset, u32 data) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; ++ u32 data_and_addr; ++ u32 newoffset; ++ ++ newoffset = offset; ++ /* T65 RF */ ++ data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; ++ rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", ++ rfpath, pphyreg->rf3wire_offset, data_and_addr); ++} ++ ++u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, ++ u32 regaddr, u32 bitmask) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 original_value, readback_value, bitshift; ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", ++ regaddr, rfpath, bitmask); ++ spin_lock(&rtlpriv->locks.rf_lock); ++ original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); ++ bitshift = calculate_bit_shift(bitmask); ++ readback_value = (original_value & bitmask) >> bitshift; ++ spin_unlock(&rtlpriv->locks.rf_lock); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", ++ regaddr, rfpath, bitmask, original_value); ++ return readback_value; ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_query_rf_reg); ++ ++void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, ++ u32 regaddr, u32 bitmask, u32 data) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u32 original_value, bitshift; ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", ++ regaddr, bitmask, data, rfpath); ++ if (bitmask == 0) ++ return; ++ spin_lock(&rtlpriv->locks.rf_lock); ++ if (rtlphy->rf_mode != RF_OP_BY_FW) { ++ if (bitmask != RFREG_OFFSET_MASK) { ++ original_value = _rtl92d_phy_rf_serial_read(hw, ++ rfpath, ++ regaddr); ++ bitshift = calculate_bit_shift(bitmask); ++ data = ((original_value & (~bitmask)) | ++ (data << bitshift)); ++ } ++ _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); ++ } ++ spin_unlock(&rtlpriv->locks.rf_lock); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", ++ regaddr, bitmask, data, rfpath); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_set_rf_reg); ++ ++void rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ ++ /* RF Interface Sowrtware Control */ ++ /* 16 LSBs if read 32-bit from 0x870 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; ++ /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ ++ rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; ++ /* 16 LSBs if read 32-bit from 0x874 */ ++ rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; ++ /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ ++ ++ rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; ++ /* RF Interface Readback Value */ ++ /* 16 LSBs if read 32-bit from 0x8E0 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; ++ /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ ++ rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; ++ /* 16 LSBs if read 32-bit from 0x8E4 */ ++ rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; ++ /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ ++ rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; ++ ++ /* RF Interface Output (and Enable) */ ++ /* 16 LSBs if read 32-bit from 0x860 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; ++ /* 16 LSBs if read 32-bit from 0x864 */ ++ rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; ++ ++ /* RF Interface (Output and) Enable */ ++ /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; ++ /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ ++ rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; ++ ++ /* Addr of LSSI. Write RF register by driver */ ++ /* LSSI Parameter */ ++ rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = ++ RFPGA0_XA_LSSIPARAMETER; ++ rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = ++ RFPGA0_XB_LSSIPARAMETER; ++ ++ /* RF parameter */ ++ /* BB Band Select */ ++ rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; ++ rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; ++ rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; ++ rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; ++ ++ /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ ++ /* Tx gain stage */ ++ rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; ++ /* Tx gain stage */ ++ rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; ++ /* Tx gain stage */ ++ rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; ++ /* Tx gain stage */ ++ rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; ++ ++ /* Transceiver A~D HSSI Parameter-1 */ ++ /* wire control parameter1 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; ++ /* wire control parameter1 */ ++ rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; ++ ++ /* Transceiver A~D HSSI Parameter-2 */ ++ /* wire control parameter2 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; ++ /* wire control parameter2 */ ++ rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; ++ ++ /* RF switch Control */ ++ /* TR/Ant switch control */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; ++ rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; ++ rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; ++ rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; ++ ++ /* AGC control 1 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; ++ rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; ++ rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; ++ rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; ++ ++ /* AGC control 2 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; ++ rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; ++ rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; ++ rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; ++ ++ /* RX AFE control 1 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; ++ rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; ++ rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; ++ rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; ++ ++ /*RX AFE control 1 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; ++ rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; ++ rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; ++ rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; ++ ++ /* Tx AFE control 1 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; ++ rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; ++ rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; ++ rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; ++ ++ /* Tx AFE control 2 */ ++ rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; ++ rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; ++ rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; ++ rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; ++ ++ /* Transceiver LSSI Readback SI mode */ ++ rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; ++ rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; ++ rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; ++ rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; ++ ++ /* Transceiver LSSI Readback PI mode */ ++ rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; ++ rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_init_bb_rf_register_definition); ++ ++void rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, ++ u32 regaddr, u32 bitmask, u32 data) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ int index; ++ ++ if (regaddr == RTXAGC_A_RATE18_06) ++ index = 0; ++ else if (regaddr == RTXAGC_A_RATE54_24) ++ index = 1; ++ else if (regaddr == RTXAGC_A_CCK1_MCS32) ++ index = 6; ++ else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) ++ index = 7; ++ else if (regaddr == RTXAGC_A_MCS03_MCS00) ++ index = 2; ++ else if (regaddr == RTXAGC_A_MCS07_MCS04) ++ index = 3; ++ else if (regaddr == RTXAGC_A_MCS11_MCS08) ++ index = 4; ++ else if (regaddr == RTXAGC_A_MCS15_MCS12) ++ index = 5; ++ else if (regaddr == RTXAGC_B_RATE18_06) ++ index = 8; ++ else if (regaddr == RTXAGC_B_RATE54_24) ++ index = 9; ++ else if (regaddr == RTXAGC_B_CCK1_55_MCS32) ++ index = 14; ++ else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) ++ index = 15; ++ else if (regaddr == RTXAGC_B_MCS03_MCS00) ++ index = 10; ++ else if (regaddr == RTXAGC_B_MCS07_MCS04) ++ index = 11; ++ else if (regaddr == RTXAGC_B_MCS11_MCS08) ++ index = 12; ++ else if (regaddr == RTXAGC_B_MCS15_MCS12) ++ index = 13; ++ else ++ return; ++ ++ rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ rtlphy->pwrgroup_cnt, index, ++ rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); ++ if (index == 13) ++ rtlphy->pwrgroup_cnt++; ++} ++EXPORT_SYMBOL_GPL(rtl92d_store_pwrindex_diffrate_offset); ++ ++void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ ++ rtlphy->default_initialgain[0] = ++ (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); ++ rtlphy->default_initialgain[1] = ++ (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); ++ rtlphy->default_initialgain[2] = ++ (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); ++ rtlphy->default_initialgain[3] = ++ (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", ++ rtlphy->default_initialgain[0], ++ rtlphy->default_initialgain[1], ++ rtlphy->default_initialgain[2], ++ rtlphy->default_initialgain[3]); ++ rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, ++ MASKBYTE0); ++ rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, ++ MASKDWORD); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "Default framesync (0x%x) = 0x%x\n", ++ ROFDM0_RXDETECTOR3, rtlphy->framesync); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_get_hw_reg_originalvalue); ++ ++static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, ++ u8 *cckpowerlevel, u8 *ofdmpowerlevel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ u8 index = (channel - 1); ++ ++ /* 1. CCK */ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ /* RF-A */ ++ cckpowerlevel[RF90_PATH_A] = ++ rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; ++ /* RF-B */ ++ cckpowerlevel[RF90_PATH_B] = ++ rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; ++ } else { ++ cckpowerlevel[RF90_PATH_A] = 0; ++ cckpowerlevel[RF90_PATH_B] = 0; ++ } ++ /* 2. OFDM for 1S or 2S */ ++ if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { ++ /* Read HT 40 OFDM TX power */ ++ ofdmpowerlevel[RF90_PATH_A] = ++ rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; ++ ofdmpowerlevel[RF90_PATH_B] = ++ rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; ++ } else if (rtlphy->rf_type == RF_2T2R) { ++ /* Read HT 40 OFDM TX power */ ++ ofdmpowerlevel[RF90_PATH_A] = ++ rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; ++ ofdmpowerlevel[RF90_PATH_B] = ++ rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; ++ } ++} ++ ++static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, ++ u8 channel, u8 *cckpowerlevel, ++ u8 *ofdmpowerlevel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ ++ rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; ++ rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; ++} ++ ++static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) ++{ ++ u8 place = chnl; ++ ++ if (chnl > 14) { ++ for (place = 14; place < ARRAY_SIZE(channel_all); place++) { ++ if (channel_all[place] == chnl) { ++ place++; ++ break; ++ } ++ } ++ } ++ return place; ++} ++ ++void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) ++{ ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 cckpowerlevel[2], ofdmpowerlevel[2]; ++ ++ if (!rtlefuse->txpwr_fromeprom) ++ return; ++ channel = _rtl92c_phy_get_rightchnlplace(channel); ++ _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], ++ &ofdmpowerlevel[0]); ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) ++ _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], ++ &ofdmpowerlevel[0]); ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) ++ rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); ++ rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_set_txpower_level); ++ ++void rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, u8 rfpath, ++ u32 *pu4_regval) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); ++ /*----Store original RFENV control type----*/ ++ switch (rfpath) { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); ++ break; ++ case RF90_PATH_B: ++ case RF90_PATH_D: ++ *pu4_regval = ++ rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); ++ break; ++ } ++ /*----Set RF_ENV enable----*/ ++ rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); ++ udelay(1); ++ /*----Set RF_ENV output high----*/ ++ rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); ++ udelay(1); ++ /* Set bit number of Address and Data for RF register */ ++ /* Set 1 to 4 bits for 8255 */ ++ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); ++ udelay(1); ++ /*Set 0 to 12 bits for 8255 */ ++ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); ++ udelay(1); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_enable_rf_env); ++ ++void rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, ++ u32 *pu4_regval) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); ++ /*----Restore RFENV control type----*/ ++ switch (rfpath) { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); ++ break; ++ case RF90_PATH_B: ++ case RF90_PATH_D: ++ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, ++ *pu4_regval); ++ break; ++ } ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_restore_rf_env); ++ ++u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) ++{ ++ u8 place; ++ ++ if (chnl > 14) { ++ for (place = 14; place < ARRAY_SIZE(channel_all); place++) { ++ if (channel_all[place] == chnl) ++ return place - 13; ++ } ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(rtl92d_get_rightchnlplace_for_iqk); ++ ++void rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, const u32 *adda_reg, ++ u32 *adda_backup, u32 regnum) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); ++ for (i = 0; i < regnum; i++) ++ adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_save_adda_registers); ++ ++void rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, ++ const u32 *macreg, u32 *macbackup) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); ++ for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) ++ macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); ++ macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_save_mac_registers); ++ ++void rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, ++ const u32 *adda_reg, bool patha_on, bool is2t) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 pathon; ++ u32 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); ++ pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; ++ if (patha_on) ++ pathon = rtlpriv->rtlhal.interfaceindex == 0 ? ++ 0x04db25a4 : 0x0b1b25a4; ++ for (i = 0; i < IQK_ADDA_REG_NUM; i++) ++ rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_path_adda_on); ++ ++void rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, ++ const u32 *macreg, u32 *macbackup) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); ++ rtl_write_byte(rtlpriv, macreg[0], 0x3F); ++ ++ for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) ++ rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & ++ (~BIT(3)))); ++ rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5)))); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_mac_setting_calibration); ++ ++static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) ++{ ++ u32 ret; ++ ++ if (val1 >= val2) ++ ret = val1 - val2; ++ else ++ ret = val2 - val1; ++ return ret; ++} ++ ++static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(channel5g); i++) ++ if (channel == channel5g[i]) ++ return true; ++ return false; ++} ++ ++void rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, ++ const u32 *targetchnl, u32 *curvecount_val, ++ bool is5g, u32 *curveindex) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 smallest_abs_val = 0xffffffff, u4tmp; ++ u8 i, j; ++ u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; ++ ++ for (i = 0; i < chnl_num; i++) { ++ if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) ++ continue; ++ curveindex[i] = 0; ++ for (j = 0; j < (CV_CURVE_CNT * 2); j++) { ++ u4tmp = _rtl92d_phy_get_abs(targetchnl[i], ++ curvecount_val[j]); ++ ++ if (u4tmp < smallest_abs_val) { ++ curveindex[i] = j; ++ smallest_abs_val = u4tmp; ++ } ++ } ++ smallest_abs_val = 0xffffffff; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", ++ i, curveindex[i]); ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_calc_curvindex); ++ ++void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 i; ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "settings regs %zu default regs %d\n", ++ ARRAY_SIZE(rtlphy->iqk_matrix), ++ IQK_MATRIX_REG_NUM); ++ /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ ++ for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { ++ rtlphy->iqk_matrix[i].value[0][0] = 0x100; ++ rtlphy->iqk_matrix[i].value[0][2] = 0x100; ++ rtlphy->iqk_matrix[i].value[0][4] = 0x100; ++ rtlphy->iqk_matrix[i].value[0][6] = 0x100; ++ rtlphy->iqk_matrix[i].value[0][1] = 0x0; ++ rtlphy->iqk_matrix[i].value[0][3] = 0x0; ++ rtlphy->iqk_matrix[i].value[0][5] = 0x0; ++ rtlphy->iqk_matrix[i].value[0][7] = 0x0; ++ rtlphy->iqk_matrix[i].iqk_done = false; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_reset_iqk_result); ++ ++static void rtl92d_phy_set_io(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct dig_t *de_digtable = &rtlpriv->dm_digtable; ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, ++ "--->Cmd(%#x), set_io_inprogress(%d)\n", ++ rtlphy->current_io_type, rtlphy->set_io_inprogress); ++ switch (rtlphy->current_io_type) { ++ case IO_CMD_RESUME_DM_BY_SCAN: ++ de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; ++ rtl92d_dm_write_dig(hw); ++ rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); ++ break; ++ case IO_CMD_PAUSE_DM_BY_SCAN: ++ rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; ++ de_digtable->cur_igvalue = 0x37; ++ rtl92d_dm_write_dig(hw); ++ break; ++ default: ++ pr_err("switch case %#x not processed\n", ++ rtlphy->current_io_type); ++ break; ++ } ++ rtlphy->set_io_inprogress = false; ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", ++ rtlphy->current_io_type); ++} ++ ++bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ bool postprocessing = false; ++ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, ++ "-->IO Cmd(%#x), set_io_inprogress(%d)\n", ++ iotype, rtlphy->set_io_inprogress); ++ do { ++ switch (iotype) { ++ case IO_CMD_RESUME_DM_BY_SCAN: ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, ++ "[IO CMD] Resume DM after scan\n"); ++ postprocessing = true; ++ break; ++ case IO_CMD_PAUSE_DM_BY_SCAN: ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, ++ "[IO CMD] Pause DM before scan\n"); ++ postprocessing = true; ++ break; ++ default: ++ pr_err("switch case %#x not processed\n", ++ iotype); ++ break; ++ } ++ } while (false); ++ if (postprocessing && !rtlphy->set_io_inprogress) { ++ rtlphy->set_io_inprogress = true; ++ rtlphy->current_io_type = iotype; ++ } else { ++ return false; ++ } ++ rtl92d_phy_set_io(hw); ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); ++ return true; ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_set_io_cmd); ++ ++void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u8 offset = REG_MAC_PHY_CTRL_NORMAL; ++ ++ switch (rtlhal->macphymode) { ++ case DUALMAC_DUALPHY: ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "MacPhyMode: DUALMAC_DUALPHY\n"); ++ rtl_write_byte(rtlpriv, offset, 0xF3); ++ break; ++ case SINGLEMAC_SINGLEPHY: ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); ++ rtl_write_byte(rtlpriv, offset, 0xF4); ++ break; ++ case DUALMAC_SINGLEPHY: ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "MacPhyMode: DUALMAC_SINGLEPHY\n"); ++ rtl_write_byte(rtlpriv, offset, 0xF1); ++ break; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_config_macphymode); ++ ++void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ ++ switch (rtlhal->macphymode) { ++ case DUALMAC_SINGLEPHY: ++ rtlphy->rf_type = RF_2T2R; ++ rtlhal->version |= RF_TYPE_2T2R; ++ rtlhal->bandset = BAND_ON_BOTH; ++ rtlhal->current_bandtype = BAND_ON_2_4G; ++ break; ++ ++ case SINGLEMAC_SINGLEPHY: ++ rtlphy->rf_type = RF_2T2R; ++ rtlhal->version |= RF_TYPE_2T2R; ++ rtlhal->bandset = BAND_ON_BOTH; ++ rtlhal->current_bandtype = BAND_ON_2_4G; ++ break; ++ ++ case DUALMAC_DUALPHY: ++ rtlphy->rf_type = RF_1T1R; ++ rtlhal->version &= RF_TYPE_1T1R; ++ /* Now we let MAC0 run on 5G band. */ ++ if (rtlhal->interfaceindex == 0) { ++ rtlhal->bandset = BAND_ON_5G; ++ rtlhal->current_bandtype = BAND_ON_5G; ++ } else { ++ rtlhal->bandset = BAND_ON_2_4G; ++ rtlhal->current_bandtype = BAND_ON_2_4G; ++ } ++ break; ++ default: ++ break; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_config_macphymode_info); ++ ++u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) ++{ ++ u8 group; ++ ++ if (channel_all[chnl] <= 3) ++ group = 0; ++ else if (channel_all[chnl] <= 9) ++ group = 1; ++ else if (channel_all[chnl] <= 14) ++ group = 2; ++ else if (channel_all[chnl] <= 44) ++ group = 3; ++ else if (channel_all[chnl] <= 54) ++ group = 4; ++ else if (channel_all[chnl] <= 64) ++ group = 5; ++ else if (channel_all[chnl] <= 112) ++ group = 6; ++ else if (channel_all[chnl] <= 126) ++ group = 7; ++ else if (channel_all[chnl] <= 140) ++ group = 8; ++ else if (channel_all[chnl] <= 153) ++ group = 9; ++ else if (channel_all[chnl] <= 159) ++ group = 10; ++ else ++ group = 11; ++ return group; ++} ++EXPORT_SYMBOL_GPL(rtl92d_get_chnlgroup_fromarray); ++ ++u8 rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex) ++{ ++ u8 group; ++ ++ if (channel_all[chnlindex] <= 3) /* Chanel 1-3 */ ++ group = 0; ++ else if (channel_all[chnlindex] <= 9) /* Channel 4-9 */ ++ group = 1; ++ else if (channel_all[chnlindex] <= 14) /* Channel 10-14 */ ++ group = 2; ++ else if (channel_all[chnlindex] <= 64) ++ group = 6; ++ else if (channel_all[chnlindex] <= 140) ++ group = 7; ++ else ++ group = 8; ++ return group; ++} ++ ++void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ switch (rtlpriv->rtlhal.macphymode) { ++ case DUALMAC_DUALPHY: ++ rtl_write_byte(rtlpriv, REG_DMC, 0x0); ++ rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); ++ rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); ++ break; ++ case DUALMAC_SINGLEPHY: ++ rtl_write_byte(rtlpriv, REG_DMC, 0xf8); ++ rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); ++ rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); ++ break; ++ case SINGLEMAC_SINGLEPHY: ++ rtl_write_byte(rtlpriv, REG_DMC, 0x0); ++ rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); ++ rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); ++ break; ++ default: ++ break; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_config_maccoexist_rfpage); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h +new file mode 100644 +index 000000000000..f9b5d0d3a7e6 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h +@@ -0,0 +1,87 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#ifndef __RTL92D_PHY_COMMON_H__ ++#define __RTL92D_PHY_COMMON_H__ ++ ++#define TARGET_CHNL_NUM_5G 221 ++#define TARGET_CHNL_NUM_2G 14 ++#define CV_CURVE_CNT 64 ++#define RT_CANNOT_IO(hw) false ++#define RX_INDEX_MAPPING_NUM 15 ++#define IQK_BB_REG_NUM 10 ++ ++#define IQK_DELAY_TIME 1 ++#define MAX_TOLERANCE 5 ++#define MAX_TOLERANCE_92D 3 ++ ++enum baseband_config_type { ++ BASEBAND_CONFIG_PHY_REG = 0, ++ BASEBAND_CONFIG_AGC_TAB = 1, ++}; ++ ++enum rf_content { ++ radioa_txt = 0, ++ radiob_txt = 1, ++ radioc_txt = 2, ++ radiod_txt = 3 ++}; ++ ++static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, ++ unsigned long *flag) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ if (rtlpriv->rtlhal.interfaceindex == 1) ++ spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag); ++} ++ ++static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, ++ unsigned long *flag) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ if (rtlpriv->rtlhal.interfaceindex == 1) ++ spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock, ++ *flag); ++} ++ ++u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, ++ u32 regaddr, u32 bitmask); ++void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, ++ u32 regaddr, u32 bitmask, u32 data); ++void rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); ++void rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, ++ u32 regaddr, u32 bitmask, u32 data); ++void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); ++void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel); ++void rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, u8 rfpath, ++ u32 *pu4_regval); ++void rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, ++ u32 *pu4_regval); ++u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl); ++void rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, const u32 *adda_reg, ++ u32 *adda_backup, u32 regnum); ++void rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, ++ const u32 *macreg, u32 *macbackup); ++void rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, ++ const u32 *adda_reg, bool patha_on, bool is2t); ++void rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, ++ const u32 *macreg, u32 *macbackup); ++void rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, ++ const u32 *targetchnl, u32 *curvecount_val, ++ bool is5g, u32 *curveindex); ++void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw); ++bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); ++void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw); ++void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw); ++u8 rtl92d_get_chnlgroup_fromarray(u8 chnl); ++u8 rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex); ++void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw); ++/* Without these declarations sparse warns about context imbalance. */ ++void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, ++ unsigned long *flag); ++void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, ++ unsigned long *flag); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h +similarity index 100% +rename from drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h +rename to drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c +new file mode 100644 +index 000000000000..8af166183688 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c +@@ -0,0 +1,353 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "def.h" ++#include "reg.h" ++#include "phy_common.h" ++#include "rf_common.h" ++ ++void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 rfpath; ++ ++ switch (bandwidth) { ++ case HT_CHANNEL_WIDTH_20: ++ for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { ++ rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval ++ [rfpath] & 0xfffff3ff) | 0x0400); ++ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | ++ BIT(11), 0x01); ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, ++ "20M RF 0x18 = 0x%x\n", ++ rtlphy->rfreg_chnlval[rfpath]); ++ } ++ ++ break; ++ case HT_CHANNEL_WIDTH_20_40: ++ for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { ++ rtlphy->rfreg_chnlval[rfpath] = ++ ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff)); ++ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), ++ 0x00); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, ++ "40M RF 0x18 = 0x%x\n", ++ rtlphy->rfreg_chnlval[rfpath]); ++ } ++ break; ++ default: ++ pr_err("unknown bandwidth: %#X\n", bandwidth); ++ break; ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_rf6052_set_bandwidth); ++ ++void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, ++ u8 *ppowerlevel) ++{ ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u32 tx_agc[2] = {0, 0}, tmpval; ++ bool turbo_scanoff = false; ++ u8 idx1, idx2; ++ u8 *ptr; ++ ++ if (rtlefuse->eeprom_regulatory != 0) ++ turbo_scanoff = true; ++ if (mac->act_scanning) { ++ tx_agc[RF90_PATH_A] = 0x3f3f3f3f; ++ tx_agc[RF90_PATH_B] = 0x3f3f3f3f; ++ if (turbo_scanoff) { ++ for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { ++ tx_agc[idx1] = ppowerlevel[idx1] | ++ (ppowerlevel[idx1] << 8) | ++ (ppowerlevel[idx1] << 16) | ++ (ppowerlevel[idx1] << 24); ++ } ++ } ++ } else { ++ for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { ++ tx_agc[idx1] = ppowerlevel[idx1] | ++ (ppowerlevel[idx1] << 8) | ++ (ppowerlevel[idx1] << 16) | ++ (ppowerlevel[idx1] << 24); ++ } ++ if (rtlefuse->eeprom_regulatory == 0) { ++ tmpval = (rtlphy->mcs_offset[0][6]) + ++ (rtlphy->mcs_offset[0][7] << 8); ++ tx_agc[RF90_PATH_A] += tmpval; ++ tmpval = (rtlphy->mcs_offset[0][14]) + ++ (rtlphy->mcs_offset[0][15] << 24); ++ tx_agc[RF90_PATH_B] += tmpval; ++ } ++ } ++ ++ for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { ++ ptr = (u8 *)(&tx_agc[idx1]); ++ for (idx2 = 0; idx2 < 4; idx2++) { ++ if (*ptr > RF6052_MAX_TX_PWR) ++ *ptr = RF6052_MAX_TX_PWR; ++ ptr++; ++ } ++ } ++ ++ tmpval = tx_agc[RF90_PATH_A] & 0xff; ++ rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", ++ tmpval, RTXAGC_A_CCK1_MCS32); ++ tmpval = tx_agc[RF90_PATH_A] >> 8; ++ rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", ++ tmpval, RTXAGC_B_CCK11_A_CCK2_11); ++ tmpval = tx_agc[RF90_PATH_B] >> 24; ++ rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", ++ tmpval, RTXAGC_B_CCK11_A_CCK2_11); ++ tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; ++ rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", ++ tmpval, RTXAGC_B_CCK1_55_MCS32); ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_rf6052_set_cck_txpower); ++ ++static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, ++ u8 *ppowerlevel, u8 channel, ++ u32 *ofdmbase, u32 *mcsbase) ++{ ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u32 powerbase0, powerbase1; ++ u8 legacy_pwrdiff, ht20_pwrdiff; ++ u8 i, powerlevel[2]; ++ ++ for (i = 0; i < 2; i++) { ++ powerlevel[i] = ppowerlevel[i]; ++ legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; ++ powerbase0 = powerlevel[i] + legacy_pwrdiff; ++ powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | ++ (powerbase0 << 8) | powerbase0; ++ *(ofdmbase + i) = powerbase0; ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ " [OFDM power base index rf(%c) = 0x%x]\n", ++ i == 0 ? 'A' : 'B', *(ofdmbase + i)); ++ } ++ ++ for (i = 0; i < 2; i++) { ++ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { ++ ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1]; ++ powerlevel[i] += ht20_pwrdiff; ++ } ++ powerbase1 = powerlevel[i]; ++ powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) | ++ (powerbase1 << 8) | powerbase1; ++ *(mcsbase + i) = powerbase1; ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ " [MCS power base index rf(%c) = 0x%x]\n", ++ i == 0 ? 'A' : 'B', *(mcsbase + i)); ++ } ++} ++ ++static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, ++ u8 channel, u8 index, ++ u32 *powerbase0, ++ u32 *powerbase1, ++ u32 *p_outwriteval) ++{ ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 i, chnlgroup = 0, pwr_diff_limit[4]; ++ u32 writeval = 0, customer_limit, rf; ++ ++ for (rf = 0; rf < 2; rf++) { ++ switch (rtlefuse->eeprom_regulatory) { ++ case 0: ++ chnlgroup = 0; ++ writeval = rtlphy->mcs_offset ++ [chnlgroup][index + ++ (rf ? 8 : 0)] + ((index < 2) ? ++ powerbase0[rf] : ++ powerbase1[rf]); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "RTK better performance, writeval(%c) = 0x%x\n", ++ rf == 0 ? 'A' : 'B', writeval); ++ break; ++ case 1: ++ if (rtlphy->pwrgroup_cnt == 1) ++ chnlgroup = 0; ++ if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) { ++ chnlgroup = rtl92d_phy_get_chnlgroup_bypg(channel - 1); ++ if (rtlphy->current_chan_bw == ++ HT_CHANNEL_WIDTH_20) ++ chnlgroup++; ++ else ++ chnlgroup += 4; ++ writeval = rtlphy->mcs_offset ++ [chnlgroup][index + ++ (rf ? 8 : 0)] + ((index < 2) ? ++ powerbase0[rf] : ++ powerbase1[rf]); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", ++ rf == 0 ? 'A' : 'B', writeval); ++ } ++ break; ++ case 2: ++ writeval = ((index < 2) ? powerbase0[rf] : ++ powerbase1[rf]); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "Better regulatory, writeval(%c) = 0x%x\n", ++ rf == 0 ? 'A' : 'B', writeval); ++ break; ++ case 3: ++ chnlgroup = 0; ++ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "customer's limit, 40MHz rf(%c) = 0x%x\n", ++ rf == 0 ? 'A' : 'B', ++ rtlefuse->pwrgroup_ht40[rf] ++ [channel - 1]); ++ } else { ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "customer's limit, 20MHz rf(%c) = 0x%x\n", ++ rf == 0 ? 'A' : 'B', ++ rtlefuse->pwrgroup_ht20[rf] ++ [channel - 1]); ++ } ++ for (i = 0; i < 4; i++) { ++ pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset ++ [chnlgroup][index + (rf ? 8 : 0)] & ++ (0x7f << (i * 8))) >> (i * 8)); ++ if (rtlphy->current_chan_bw == ++ HT_CHANNEL_WIDTH_20_40) { ++ if (pwr_diff_limit[i] > ++ rtlefuse->pwrgroup_ht40[rf] ++ [channel - 1]) ++ pwr_diff_limit[i] = ++ rtlefuse->pwrgroup_ht40 ++ [rf][channel - 1]; ++ } else { ++ if (pwr_diff_limit[i] > ++ rtlefuse->pwrgroup_ht20[rf][channel - 1]) ++ pwr_diff_limit[i] = ++ rtlefuse->pwrgroup_ht20[rf] ++ [channel - 1]; ++ } ++ } ++ customer_limit = (pwr_diff_limit[3] << 24) | ++ (pwr_diff_limit[2] << 16) | ++ (pwr_diff_limit[1] << 8) | ++ (pwr_diff_limit[0]); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "Customer's limit rf(%c) = 0x%x\n", ++ rf == 0 ? 'A' : 'B', customer_limit); ++ writeval = customer_limit + ((index < 2) ? ++ powerbase0[rf] : powerbase1[rf]); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "Customer, writeval rf(%c)= 0x%x\n", ++ rf == 0 ? 'A' : 'B', writeval); ++ break; ++ default: ++ chnlgroup = 0; ++ writeval = rtlphy->mcs_offset[chnlgroup][index + ++ (rf ? 8 : 0)] + ((index < 2) ? ++ powerbase0[rf] : powerbase1[rf]); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "RTK better performance, writeval rf(%c) = 0x%x\n", ++ rf == 0 ? 'A' : 'B', writeval); ++ break; ++ } ++ *(p_outwriteval + rf) = writeval; ++ } ++} ++ ++static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw, ++ u8 index, u32 *pvalue) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ static const u16 regoffset_a[6] = { ++ RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, ++ RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04, ++ RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12 ++ }; ++ static const u16 regoffset_b[6] = { ++ RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24, ++ RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04, ++ RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 ++ }; ++ u8 i, rf, pwr_val[4]; ++ u32 writeval; ++ u16 regoffset; ++ ++ for (rf = 0; rf < 2; rf++) { ++ writeval = pvalue[rf]; ++ for (i = 0; i < 4; i++) { ++ pwr_val[i] = (u8)((writeval & (0x7f << ++ (i * 8))) >> (i * 8)); ++ if (pwr_val[i] > RF6052_MAX_TX_PWR) ++ pwr_val[i] = RF6052_MAX_TX_PWR; ++ } ++ writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) | ++ (pwr_val[1] << 8) | pwr_val[0]; ++ if (rf == 0) ++ regoffset = regoffset_a[index]; ++ else ++ regoffset = regoffset_b[index]; ++ rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "Set 0x%x = %08x\n", regoffset, writeval); ++ if (((get_rf_type(rtlphy) == RF_2T2R) && ++ (regoffset == RTXAGC_A_MCS15_MCS12 || ++ regoffset == RTXAGC_B_MCS15_MCS12)) || ++ ((get_rf_type(rtlphy) != RF_2T2R) && ++ (regoffset == RTXAGC_A_MCS07_MCS04 || ++ regoffset == RTXAGC_B_MCS07_MCS04))) { ++ writeval = pwr_val[3]; ++ if (regoffset == RTXAGC_A_MCS15_MCS12 || ++ regoffset == RTXAGC_A_MCS07_MCS04) ++ regoffset = 0xc90; ++ if (regoffset == RTXAGC_B_MCS15_MCS12 || ++ regoffset == RTXAGC_B_MCS07_MCS04) ++ regoffset = 0xc98; ++ for (i = 0; i < 3; i++) { ++ if (i != 2) ++ writeval = (writeval > 8) ? ++ (writeval - 8) : 0; ++ else ++ writeval = (writeval > 6) ? ++ (writeval - 6) : 0; ++ rtl_write_byte(rtlpriv, (u32)(regoffset + i), ++ (u8)writeval); ++ } ++ } ++ } ++} ++ ++void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, ++ u8 *ppowerlevel, u8 channel) ++{ ++ u32 writeval[2], powerbase0[2], powerbase1[2]; ++ u8 index; ++ ++ _rtl92d_phy_get_power_base(hw, ppowerlevel, channel, ++ &powerbase0[0], &powerbase1[0]); ++ for (index = 0; index < 6; index++) { ++ _rtl92d_get_txpower_writeval_by_regulatory(hw, channel, index, ++ &powerbase0[0], ++ &powerbase1[0], ++ &writeval[0]); ++ _rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]); ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92d_phy_rf6052_set_ofdm_txpower); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h +new file mode 100644 +index 000000000000..c243ec08369b +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#ifndef __RTL92D_RF_COMMON_H__ ++#define __RTL92D_RF_COMMON_H__ ++ ++void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth); ++void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, ++ u8 *ppowerlevel); ++void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, ++ u8 *ppowerlevel, u8 channel); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c +new file mode 100644 +index 000000000000..5b8f404373ea +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c +@@ -0,0 +1,515 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../base.h" ++#include "../stats.h" ++#include "def.h" ++#include "trx_common.h" ++ ++static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, ++ u8 signal_strength_index) ++{ ++ long signal_power; ++ ++ signal_power = (long)((signal_strength_index + 1) >> 1); ++ signal_power -= 95; ++ return signal_power; ++} ++ ++static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats, ++ __le32 *pdesc, ++ struct rx_fwinfo_92d *p_drvinfo, ++ bool packet_match_bssid, ++ bool packet_toself, ++ bool packet_beacon) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); ++ struct phy_sts_cck_8192d *cck_buf; ++ s8 rx_pwr_all, rx_pwr[4]; ++ u8 rf_rx_num = 0, evm, pwdb_all; ++ u8 i, max_spatial_stream; ++ u32 rssi, total_rssi = 0; ++ bool is_cck_rate; ++ u8 rxmcs; ++ ++ rxmcs = get_rx_desc_rxmcs(pdesc); ++ is_cck_rate = rxmcs <= DESC_RATE11M; ++ pstats->packet_matchbssid = packet_match_bssid; ++ pstats->packet_toself = packet_toself; ++ pstats->packet_beacon = packet_beacon; ++ pstats->is_cck = is_cck_rate; ++ pstats->rx_mimo_sig_qual[0] = -1; ++ pstats->rx_mimo_sig_qual[1] = -1; ++ ++ if (is_cck_rate) { ++ u8 report, cck_highpwr; ++ ++ cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo; ++ if (ppsc->rfpwr_state == ERFON) ++ cck_highpwr = rtlphy->cck_high_power; ++ else ++ cck_highpwr = false; ++ if (!cck_highpwr) { ++ u8 cck_agc_rpt = cck_buf->cck_agc_rpt; ++ ++ report = cck_buf->cck_agc_rpt & 0xc0; ++ report = report >> 6; ++ switch (report) { ++ case 0x3: ++ rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); ++ break; ++ case 0x2: ++ rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); ++ break; ++ case 0x1: ++ rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); ++ break; ++ case 0x0: ++ rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); ++ break; ++ } ++ } else { ++ u8 cck_agc_rpt = cck_buf->cck_agc_rpt; ++ ++ report = p_drvinfo->cfosho[0] & 0x60; ++ report = report >> 5; ++ switch (report) { ++ case 0x3: ++ rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); ++ break; ++ case 0x2: ++ rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); ++ break; ++ case 0x1: ++ rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); ++ break; ++ case 0x0: ++ rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); ++ break; ++ } ++ } ++ pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); ++ /* CCK gain is smaller than OFDM/MCS gain, */ ++ /* so we add gain diff by experiences, the val is 6 */ ++ pwdb_all += 6; ++ if (pwdb_all > 100) ++ pwdb_all = 100; ++ /* modify the offset to make the same gain index with OFDM. */ ++ if (pwdb_all > 34 && pwdb_all <= 42) ++ pwdb_all -= 2; ++ else if (pwdb_all > 26 && pwdb_all <= 34) ++ pwdb_all -= 6; ++ else if (pwdb_all > 14 && pwdb_all <= 26) ++ pwdb_all -= 8; ++ else if (pwdb_all > 4 && pwdb_all <= 14) ++ pwdb_all -= 4; ++ pstats->rx_pwdb_all = pwdb_all; ++ pstats->recvsignalpower = rx_pwr_all; ++ if (packet_match_bssid) { ++ u8 sq; ++ ++ if (pstats->rx_pwdb_all > 40) { ++ sq = 100; ++ } else { ++ sq = cck_buf->sq_rpt; ++ if (sq > 64) ++ sq = 0; ++ else if (sq < 20) ++ sq = 100; ++ else ++ sq = ((64 - sq) * 100) / 44; ++ } ++ pstats->signalquality = sq; ++ pstats->rx_mimo_sig_qual[0] = sq; ++ pstats->rx_mimo_sig_qual[1] = -1; ++ } ++ } else { ++ rtlpriv->dm.rfpath_rxenable[0] = true; ++ rtlpriv->dm.rfpath_rxenable[1] = true; ++ for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) { ++ if (rtlpriv->dm.rfpath_rxenable[i]) ++ rf_rx_num++; ++ rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) ++ - 110; ++ rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); ++ total_rssi += rssi; ++ rtlpriv->stats.rx_snr_db[i] = ++ (long)(p_drvinfo->rxsnr[i] / 2); ++ if (packet_match_bssid) ++ pstats->rx_mimo_signalstrength[i] = (u8)rssi; ++ } ++ rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 106; ++ pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); ++ pstats->rx_pwdb_all = pwdb_all; ++ pstats->rxpower = rx_pwr_all; ++ pstats->recvsignalpower = rx_pwr_all; ++ if (get_rx_desc_rxht(pdesc) && rxmcs >= DESC_RATEMCS8 && ++ rxmcs <= DESC_RATEMCS15) ++ max_spatial_stream = 2; ++ else ++ max_spatial_stream = 1; ++ for (i = 0; i < max_spatial_stream; i++) { ++ evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]); ++ if (packet_match_bssid) { ++ if (i == 0) ++ pstats->signalquality = ++ (u8)(evm & 0xff); ++ pstats->rx_mimo_sig_qual[i] = ++ (u8)(evm & 0xff); ++ } ++ } ++ } ++ if (is_cck_rate) ++ pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, ++ pwdb_all)); ++ else if (rf_rx_num != 0) ++ pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, ++ total_rssi /= rf_rx_num)); ++} ++ ++static void rtl92d_loop_over_paths(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 rfpath; ++ ++ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; ++ rfpath++) { ++ if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) { ++ rtlpriv->stats.rx_rssi_percentage[rfpath] = ++ pstats->rx_mimo_signalstrength[rfpath]; ++ } ++ if (pstats->rx_mimo_signalstrength[rfpath] > ++ rtlpriv->stats.rx_rssi_percentage[rfpath]) { ++ rtlpriv->stats.rx_rssi_percentage[rfpath] = ++ ((rtlpriv->stats.rx_rssi_percentage[rfpath] * ++ (RX_SMOOTH_FACTOR - 1)) + ++ (pstats->rx_mimo_signalstrength[rfpath])) / ++ (RX_SMOOTH_FACTOR); ++ rtlpriv->stats.rx_rssi_percentage[rfpath] = ++ rtlpriv->stats.rx_rssi_percentage[rfpath] + 1; ++ } else { ++ rtlpriv->stats.rx_rssi_percentage[rfpath] = ++ ((rtlpriv->stats.rx_rssi_percentage[rfpath] * ++ (RX_SMOOTH_FACTOR - 1)) + ++ (pstats->rx_mimo_signalstrength[rfpath])) / ++ (RX_SMOOTH_FACTOR); ++ } ++ } ++} ++ ++static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rt_smooth_data *ui_rssi; ++ u32 last_rssi, tmpval; ++ ++ if (!pstats->packet_toself && !pstats->packet_beacon) ++ return; ++ ++ ui_rssi = &rtlpriv->stats.ui_rssi; ++ ++ rtlpriv->stats.rssi_calculate_cnt++; ++ if (ui_rssi->total_num++ >= PHY_RSSI_SLID_WIN_MAX) { ++ ui_rssi->total_num = PHY_RSSI_SLID_WIN_MAX; ++ last_rssi = ui_rssi->elements[ui_rssi->index]; ++ ui_rssi->total_val -= last_rssi; ++ } ++ ui_rssi->total_val += pstats->signalstrength; ++ ui_rssi->elements[ui_rssi->index++] = pstats->signalstrength; ++ if (ui_rssi->index >= PHY_RSSI_SLID_WIN_MAX) ++ ui_rssi->index = 0; ++ tmpval = ui_rssi->total_val / ui_rssi->total_num; ++ rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw, (u8)tmpval); ++ pstats->rssi = rtlpriv->stats.signal_strength; ++ ++ if (!pstats->is_cck && pstats->packet_toself) ++ rtl92d_loop_over_paths(hw, pstats); ++} ++ ++static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ int weighting = 0; ++ ++ if (rtlpriv->stats.recv_signal_power == 0) ++ rtlpriv->stats.recv_signal_power = pstats->recvsignalpower; ++ if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power) ++ weighting = 5; ++ else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power) ++ weighting = (-5); ++ rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power * ++ 5 + pstats->recvsignalpower + weighting) / 6; ++} ++ ++static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ long undec_sm_pwdb; ++ ++ if (mac->opmode == NL80211_IFTYPE_ADHOC || ++ mac->opmode == NL80211_IFTYPE_AP) ++ return; ++ ++ undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; ++ ++ if (pstats->packet_toself || pstats->packet_beacon) { ++ if (undec_sm_pwdb < 0) ++ undec_sm_pwdb = pstats->rx_pwdb_all; ++ if (pstats->rx_pwdb_all > (u32)undec_sm_pwdb) { ++ undec_sm_pwdb = (((undec_sm_pwdb) * ++ (RX_SMOOTH_FACTOR - 1)) + ++ (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); ++ undec_sm_pwdb = undec_sm_pwdb + 1; ++ } else { ++ undec_sm_pwdb = (((undec_sm_pwdb) * ++ (RX_SMOOTH_FACTOR - 1)) + ++ (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); ++ } ++ rtlpriv->dm.undec_sm_pwdb = undec_sm_pwdb; ++ _rtl92de_update_rxsignalstatistics(hw, pstats); ++ } ++} ++ ++static void rtl92d_loop_over_streams(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ int stream; ++ ++ for (stream = 0; stream < 2; stream++) { ++ if (pstats->rx_mimo_sig_qual[stream] != -1) { ++ if (rtlpriv->stats.rx_evm_percentage[stream] == 0) { ++ rtlpriv->stats.rx_evm_percentage[stream] = ++ pstats->rx_mimo_sig_qual[stream]; ++ } ++ rtlpriv->stats.rx_evm_percentage[stream] = ++ ((rtlpriv->stats.rx_evm_percentage[stream] ++ * (RX_SMOOTH_FACTOR - 1)) + ++ (pstats->rx_mimo_sig_qual[stream] * 1)) / ++ (RX_SMOOTH_FACTOR); ++ } ++ } ++} ++ ++static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rt_smooth_data *ui_link_quality; ++ u32 last_evm, tmpval; ++ ++ if (pstats->signalquality == 0) ++ return; ++ if (!pstats->packet_toself && !pstats->packet_beacon) ++ return; ++ ++ ui_link_quality = &rtlpriv->stats.ui_link_quality; ++ ++ if (ui_link_quality->total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) { ++ ui_link_quality->total_num = PHY_LINKQUALITY_SLID_WIN_MAX; ++ last_evm = ui_link_quality->elements[ui_link_quality->index]; ++ ui_link_quality->total_val -= last_evm; ++ } ++ ui_link_quality->total_val += pstats->signalquality; ++ ui_link_quality->elements[ui_link_quality->index++] = pstats->signalquality; ++ if (ui_link_quality->index >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ ui_link_quality->index = 0; ++ tmpval = ui_link_quality->total_val / ui_link_quality->total_num; ++ rtlpriv->stats.signal_quality = tmpval; ++ rtlpriv->stats.last_sigstrength_inpercent = tmpval; ++ rtl92d_loop_over_streams(hw, pstats); ++} ++ ++static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw, ++ u8 *buffer, ++ struct rtl_stats *pcurrent_stats) ++{ ++ if (!pcurrent_stats->packet_matchbssid && ++ !pcurrent_stats->packet_beacon) ++ return; ++ ++ _rtl92de_process_ui_rssi(hw, pcurrent_stats); ++ _rtl92de_process_pwdb(hw, pcurrent_stats); ++ _rtl92de_process_ui_link_quality(hw, pcurrent_stats); ++} ++ ++static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, ++ struct sk_buff *skb, ++ struct rtl_stats *pstats, ++ __le32 *pdesc, ++ struct rx_fwinfo_92d *p_drvinfo) ++{ ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct ieee80211_hdr *hdr; ++ u8 *tmp_buf; ++ u8 *praddr; ++ u16 type, cfc; ++ __le16 fc; ++ bool packet_matchbssid, packet_toself, packet_beacon = false; ++ ++ tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; ++ hdr = (struct ieee80211_hdr *)tmp_buf; ++ fc = hdr->frame_control; ++ cfc = le16_to_cpu(fc); ++ type = WLAN_FC_GET_TYPE(fc); ++ praddr = hdr->addr1; ++ packet_matchbssid = ((type != IEEE80211_FTYPE_CTL) && ++ ether_addr_equal(mac->bssid, ++ (cfc & IEEE80211_FCTL_TODS) ? hdr->addr1 : ++ (cfc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : ++ hdr->addr3) && ++ (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); ++ packet_toself = packet_matchbssid && ++ ether_addr_equal(praddr, rtlefuse->dev_addr); ++ if (ieee80211_is_beacon(fc)) ++ packet_beacon = true; ++ _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, ++ packet_matchbssid, packet_toself, ++ packet_beacon); ++ _rtl92de_process_phyinfo(hw, tmp_buf, pstats); ++} ++ ++bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, ++ struct ieee80211_rx_status *rx_status, ++ u8 *pdesc8, struct sk_buff *skb) ++{ ++ __le32 *pdesc = (__le32 *)pdesc8; ++ struct rx_fwinfo_92d *p_drvinfo; ++ u32 phystatus = get_rx_desc_physt(pdesc); ++ ++ stats->length = (u16)get_rx_desc_pkt_len(pdesc); ++ stats->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(pdesc) * ++ RX_DRV_INFO_SIZE_UNIT; ++ stats->rx_bufshift = (u8)(get_rx_desc_shift(pdesc) & 0x03); ++ stats->icv = (u16)get_rx_desc_icv(pdesc); ++ stats->crc = (u16)get_rx_desc_crc32(pdesc); ++ stats->hwerror = (stats->crc | stats->icv); ++ stats->decrypted = !get_rx_desc_swdec(pdesc) && ++ get_rx_desc_enc_type(pdesc) != RX_DESC_ENC_NONE; ++ stats->rate = (u8)get_rx_desc_rxmcs(pdesc); ++ stats->shortpreamble = (u16)get_rx_desc_splcp(pdesc); ++ stats->isampdu = (bool)(get_rx_desc_paggr(pdesc) == 1); ++ stats->isfirst_ampdu = (bool)((get_rx_desc_paggr(pdesc) == 1) && ++ (get_rx_desc_faggr(pdesc) == 1)); ++ stats->timestamp_low = get_rx_desc_tsfl(pdesc); ++ stats->rx_is40mhzpacket = (bool)get_rx_desc_bw(pdesc); ++ stats->is_ht = (bool)get_rx_desc_rxht(pdesc); ++ rx_status->freq = hw->conf.chandef.chan->center_freq; ++ rx_status->band = hw->conf.chandef.chan->band; ++ if (get_rx_desc_crc32(pdesc)) ++ rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; ++ if (get_rx_desc_bw(pdesc)) ++ rx_status->bw = RATE_INFO_BW_40; ++ if (get_rx_desc_rxht(pdesc)) ++ rx_status->encoding = RX_ENC_HT; ++ rx_status->flag |= RX_FLAG_MACTIME_START; ++ if (stats->decrypted) ++ rx_status->flag |= RX_FLAG_DECRYPTED; ++ rx_status->rate_idx = rtlwifi_rate_mapping(hw, stats->is_ht, ++ false, stats->rate); ++ rx_status->mactime = get_rx_desc_tsfl(pdesc); ++ if (phystatus) { ++ p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + ++ stats->rx_bufshift); ++ _rtl92de_translate_rx_signal_stuff(hw, skb, stats, pdesc, ++ p_drvinfo); ++ } ++ /*rx_status->qual = stats->signal; */ ++ rx_status->signal = stats->recvsignalpower + 10; ++ return true; ++} ++EXPORT_SYMBOL_GPL(rtl92de_rx_query_desc); ++ ++void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, ++ u8 desc_name, u8 *val) ++{ ++ __le32 *pdesc = (__le32 *)pdesc8; ++ ++ if (istx) { ++ switch (desc_name) { ++ case HW_DESC_OWN: ++ wmb(); ++ set_tx_desc_own(pdesc, 1); ++ break; ++ case HW_DESC_TX_NEXTDESC_ADDR: ++ set_tx_desc_next_desc_address(pdesc, *(u32 *)val); ++ break; ++ default: ++ WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", ++ desc_name); ++ break; ++ } ++ } else { ++ switch (desc_name) { ++ case HW_DESC_RXOWN: ++ wmb(); ++ set_rx_desc_own(pdesc, 1); ++ break; ++ case HW_DESC_RXBUFF_ADDR: ++ set_rx_desc_buff_addr(pdesc, *(u32 *)val); ++ break; ++ case HW_DESC_RXPKT_LEN: ++ set_rx_desc_pkt_len(pdesc, *(u32 *)val); ++ break; ++ case HW_DESC_RXERO: ++ set_rx_desc_eor(pdesc, 1); ++ break; ++ default: ++ WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", ++ desc_name); ++ break; ++ } ++ } ++} ++EXPORT_SYMBOL_GPL(rtl92de_set_desc); ++ ++u64 rtl92de_get_desc(struct ieee80211_hw *hw, ++ u8 *p_desc8, bool istx, u8 desc_name) ++{ ++ __le32 *p_desc = (__le32 *)p_desc8; ++ u32 ret = 0; ++ ++ if (istx) { ++ switch (desc_name) { ++ case HW_DESC_OWN: ++ ret = get_tx_desc_own(p_desc); ++ break; ++ case HW_DESC_TXBUFF_ADDR: ++ ret = get_tx_desc_tx_buffer_address(p_desc); ++ break; ++ default: ++ WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", ++ desc_name); ++ break; ++ } ++ } else { ++ switch (desc_name) { ++ case HW_DESC_OWN: ++ ret = get_rx_desc_own(p_desc); ++ break; ++ case HW_DESC_RXPKT_LEN: ++ ret = get_rx_desc_pkt_len(p_desc); ++ break; ++ case HW_DESC_RXBUFF_ADDR: ++ ret = get_rx_desc_buff_addr(p_desc); ++ break; ++ default: ++ WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", ++ desc_name); ++ break; ++ } ++ } ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rtl92de_get_desc); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h +new file mode 100644 +index 000000000000..87d956d771eb +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h +@@ -0,0 +1,405 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2009-2012 Realtek Corporation.*/ ++ ++#ifndef __RTL92D_TRX_COMMON_H__ ++#define __RTL92D_TRX_COMMON_H__ ++ ++#define RX_DRV_INFO_SIZE_UNIT 8 ++ ++enum rtl92d_rx_desc_enc { ++ RX_DESC_ENC_NONE = 0, ++ RX_DESC_ENC_WEP40 = 1, ++ RX_DESC_ENC_TKIP_WO_MIC = 2, ++ RX_DESC_ENC_TKIP_MIC = 3, ++ RX_DESC_ENC_AES = 4, ++ RX_DESC_ENC_WEP104 = 5, ++}; ++ ++/* macros to read/write various fields in RX or TX descriptors */ ++ ++static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, GENMASK(15, 0)); ++} ++ ++static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, GENMASK(23, 16)); ++} ++ ++static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, BIT(25)); ++} ++ ++static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, BIT(26)); ++} ++ ++static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, BIT(27)); ++} ++ ++static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, BIT(28)); ++} ++ ++static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, BIT(31)); ++} ++ ++static inline u32 get_tx_desc_own(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, BIT(31)); ++} ++ ++static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0)); ++} ++ ++static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 1), __val, BIT(5)); ++} ++ ++static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 1), __val, BIT(7)); ++} ++ ++static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8)); ++} ++ ++static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16)); ++} ++ ++static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22)); ++} ++ ++static inline void set_tx_desc_pkt_offset(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 1), __val, GENMASK(30, 26)); ++} ++ ++static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 2), __val, BIT(17)); ++} ++ ++static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20)); ++} ++ ++static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16)); ++} ++ ++static inline void set_tx_desc_pkt_id(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28)); ++} ++ ++static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0)); ++} ++ ++static inline void set_tx_desc_qos(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(6)); ++} ++ ++static inline void set_tx_desc_hwseq_en(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(7)); ++} ++ ++static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(8)); ++} ++ ++static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(10)); ++} ++ ++static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(11)); ++} ++ ++static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(12)); ++} ++ ++static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(13)); ++} ++ ++static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20)); ++} ++ ++static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(25)); ++} ++ ++static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(26)); ++} ++ ++static inline void set_tx_desc_rts_bw(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, BIT(27)); ++} ++ ++static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28)); ++} ++ ++static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30)); ++} ++ ++static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); ++} ++ ++static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 5), __val, BIT(6)); ++} ++ ++static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8)); ++} ++ ++static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13)); ++} ++ ++static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11)); ++} ++ ++static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0)); ++} ++ ++static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val) ++{ ++ *(__pdesc + 8) = cpu_to_le32(__val); ++} ++ ++static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc) ++{ ++ return le32_to_cpu(*(__pdesc + 8)); ++} ++ ++static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val) ++{ ++ *(__pdesc + 10) = cpu_to_le32(__val); ++} ++ ++static inline u32 get_rx_desc_pkt_len(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, GENMASK(13, 0)); ++} ++ ++static inline u32 get_rx_desc_crc32(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, BIT(14)); ++} ++ ++static inline u32 get_rx_desc_icv(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, BIT(15)); ++} ++ ++static inline u32 get_rx_desc_drv_info_size(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, GENMASK(19, 16)); ++} ++ ++static inline u32 get_rx_desc_enc_type(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, GENMASK(22, 20)); ++} ++ ++static inline u32 get_rx_desc_shift(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, GENMASK(25, 24)); ++} ++ ++static inline u32 get_rx_desc_physt(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, BIT(26)); ++} ++ ++static inline u32 get_rx_desc_swdec(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, BIT(27)); ++} ++ ++static inline u32 get_rx_desc_own(__le32 *__pdesc) ++{ ++ return le32_get_bits(*__pdesc, BIT(31)); ++} ++ ++static inline void set_rx_desc_pkt_len(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, GENMASK(13, 0)); ++} ++ ++static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, BIT(30)); ++} ++ ++static inline void set_rx_desc_own(__le32 *__pdesc, u32 __val) ++{ ++ le32p_replace_bits(__pdesc, __val, BIT(31)); ++} ++ ++static inline u32 get_rx_desc_paggr(__le32 *__pdesc) ++{ ++ return le32_get_bits(*(__pdesc + 1), BIT(14)); ++} ++ ++static inline u32 get_rx_desc_faggr(__le32 *__pdesc) ++{ ++ return le32_get_bits(*(__pdesc + 1), BIT(15)); ++} ++ ++static inline u32 get_rx_desc_rxmcs(__le32 *__pdesc) ++{ ++ return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0)); ++} ++ ++static inline u32 get_rx_desc_rxht(__le32 *__pdesc) ++{ ++ return le32_get_bits(*(__pdesc + 3), BIT(6)); ++} ++ ++static inline u32 get_rx_desc_splcp(__le32 *__pdesc) ++{ ++ return le32_get_bits(*(__pdesc + 3), BIT(8)); ++} ++ ++static inline u32 get_rx_desc_bw(__le32 *__pdesc) ++{ ++ return le32_get_bits(*(__pdesc + 3), BIT(9)); ++} ++ ++static inline u32 get_rx_desc_tsfl(__le32 *__pdesc) ++{ ++ return le32_to_cpu(*(__pdesc + 5)); ++} ++ ++static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc) ++{ ++ return le32_to_cpu(*(__pdesc + 6)); ++} ++ ++static inline void set_rx_desc_buff_addr(__le32 *__pdesc, u32 __val) ++{ ++ *(__pdesc + 6) = cpu_to_le32(__val); ++} ++ ++/* For 92D early mode */ ++static inline void set_earlymode_pktnum(__le32 *__paddr, u32 __value) ++{ ++ le32p_replace_bits(__paddr, __value, GENMASK(2, 0)); ++} ++ ++static inline void set_earlymode_len0(__le32 *__paddr, u32 __value) ++{ ++ le32p_replace_bits(__paddr, __value, GENMASK(15, 4)); ++} ++ ++static inline void set_earlymode_len1(__le32 *__paddr, u32 __value) ++{ ++ le32p_replace_bits(__paddr, __value, GENMASK(27, 16)); ++} ++ ++static inline void set_earlymode_len2_1(__le32 *__paddr, u32 __value) ++{ ++ le32p_replace_bits(__paddr, __value, GENMASK(31, 28)); ++} ++ ++static inline void set_earlymode_len2_2(__le32 *__paddr, u32 __value) ++{ ++ le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0)); ++} ++ ++static inline void set_earlymode_len3(__le32 *__paddr, u32 __value) ++{ ++ le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8)); ++} ++ ++static inline void set_earlymode_len4(__le32 *__paddr, u32 __value) ++{ ++ le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20)); ++} ++ ++struct rx_fwinfo_92d { ++ u8 gain_trsw[4]; ++ u8 pwdb_all; ++ u8 cfosho[4]; ++ u8 cfotail[4]; ++ s8 rxevm[2]; ++ s8 rxsnr[4]; ++ u8 pdsnr[2]; ++ u8 csi_current[2]; ++ u8 csi_target[2]; ++ u8 sigevm; ++ u8 max_ex_pwr; ++#ifdef __LITTLE_ENDIAN ++ u8 ex_intf_flag:1; ++ u8 sgi_en:1; ++ u8 rxsc:2; ++ u8 reserve:4; ++#else ++ u8 reserve:4; ++ u8 rxsc:2; ++ u8 sgi_en:1; ++ u8 ex_intf_flag:1; ++#endif ++} __packed; ++ ++bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, ++ struct rtl_stats *stats, ++ struct ieee80211_rx_status *rx_status, ++ u8 *pdesc, struct sk_buff *skb); ++void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, ++ u8 desc_name, u8 *val); ++u64 rtl92de_get_desc(struct ieee80211_hw *hw, ++ u8 *p_desc, bool istx, u8 desc_name); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c +index cf4aca83bd05..c6a2e8b22fa0 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c +@@ -4,455 +4,16 @@ + #include "../wifi.h" + #include "../base.h" + #include "../core.h" +-#include "reg.h" +-#include "def.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/dm_common.h" ++#include "../rtl8192d/phy_common.h" ++#include "../rtl8192d/fw_common.h" + #include "phy.h" + #include "dm.h" +-#include "fw.h" + + #define UNDEC_SM_PWDB entry_min_undec_sm_pwdb + +-static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = { +- 0x7f8001fe, /* 0, +6.0dB */ +- 0x788001e2, /* 1, +5.5dB */ +- 0x71c001c7, /* 2, +5.0dB */ +- 0x6b8001ae, /* 3, +4.5dB */ +- 0x65400195, /* 4, +4.0dB */ +- 0x5fc0017f, /* 5, +3.5dB */ +- 0x5a400169, /* 6, +3.0dB */ +- 0x55400155, /* 7, +2.5dB */ +- 0x50800142, /* 8, +2.0dB */ +- 0x4c000130, /* 9, +1.5dB */ +- 0x47c0011f, /* 10, +1.0dB */ +- 0x43c0010f, /* 11, +0.5dB */ +- 0x40000100, /* 12, +0dB */ +- 0x3c8000f2, /* 13, -0.5dB */ +- 0x390000e4, /* 14, -1.0dB */ +- 0x35c000d7, /* 15, -1.5dB */ +- 0x32c000cb, /* 16, -2.0dB */ +- 0x300000c0, /* 17, -2.5dB */ +- 0x2d4000b5, /* 18, -3.0dB */ +- 0x2ac000ab, /* 19, -3.5dB */ +- 0x288000a2, /* 20, -4.0dB */ +- 0x26000098, /* 21, -4.5dB */ +- 0x24000090, /* 22, -5.0dB */ +- 0x22000088, /* 23, -5.5dB */ +- 0x20000080, /* 24, -6.0dB */ +- 0x1e400079, /* 25, -6.5dB */ +- 0x1c800072, /* 26, -7.0dB */ +- 0x1b00006c, /* 27. -7.5dB */ +- 0x19800066, /* 28, -8.0dB */ +- 0x18000060, /* 29, -8.5dB */ +- 0x16c0005b, /* 30, -9.0dB */ +- 0x15800056, /* 31, -9.5dB */ +- 0x14400051, /* 32, -10.0dB */ +- 0x1300004c, /* 33, -10.5dB */ +- 0x12000048, /* 34, -11.0dB */ +- 0x11000044, /* 35, -11.5dB */ +- 0x10000040, /* 36, -12.0dB */ +- 0x0f00003c, /* 37, -12.5dB */ +- 0x0e400039, /* 38, -13.0dB */ +- 0x0d800036, /* 39, -13.5dB */ +- 0x0cc00033, /* 40, -14.0dB */ +- 0x0c000030, /* 41, -14.5dB */ +- 0x0b40002d, /* 42, -15.0dB */ +-}; +- +-static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { +- {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ +- {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ +- {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ +- {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ +- {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ +- {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ +- {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ +- {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ +- {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ +- {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ +- {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ +- {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ +- {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ +- {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ +- {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ +- {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ +- {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ +- {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ +- {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ +- {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ +- {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ +- {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ +- {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ +- {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ +- {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ +- {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ +- {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ +- {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ +- {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ +- {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ +- {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ +- {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ +- {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ +-}; +- +-static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { +- {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ +- {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ +- {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ +- {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ +- {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ +- {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ +- {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ +- {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ +- {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ +- {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ +- {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ +- {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ +- {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ +- {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ +- {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ +- {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ +- {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ +- {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ +- {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ +- {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ +- {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ +- {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ +- {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ +- {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ +- {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ +- {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ +- {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ +- {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ +- {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ +- {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ +- {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ +- {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ +- {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ +-}; +- +-static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) +-{ +- u32 ret_value; +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); +- unsigned long flag = 0; +- +- /* hold ofdm counter */ +- rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ +- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ +- +- ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); +- falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); +- falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); +- ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); +- falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); +- ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); +- falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); +- falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); +- ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); +- falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); +- falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + +- falsealm_cnt->cnt_rate_illegal + +- falsealm_cnt->cnt_crc8_fail + +- falsealm_cnt->cnt_mcs_fail + +- falsealm_cnt->cnt_fast_fsync_fail + +- falsealm_cnt->cnt_sb_search_fail; +- +- if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { +- /* hold cck counter */ +- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); +- ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); +- falsealm_cnt->cnt_cck_fail = ret_value; +- ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); +- falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; +- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); +- } else { +- falsealm_cnt->cnt_cck_fail = 0; +- } +- +- /* reset false alarm counter registers */ +- falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail + +- falsealm_cnt->cnt_sb_search_fail + +- falsealm_cnt->cnt_parity_fail + +- falsealm_cnt->cnt_rate_illegal + +- falsealm_cnt->cnt_crc8_fail + +- falsealm_cnt->cnt_mcs_fail + +- falsealm_cnt->cnt_cck_fail; +- +- rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); +- /* update ofdm counter */ +- rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); +- /* update page C counter */ +- rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); +- /* update page D counter */ +- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); +- if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { +- /* reset cck counter */ +- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); +- rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); +- /* enable cck counter */ +- rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); +- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); +- } +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n", +- falsealm_cnt->cnt_fast_fsync_fail, +- falsealm_cnt->cnt_sb_search_fail); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n", +- falsealm_cnt->cnt_parity_fail, +- falsealm_cnt->cnt_rate_illegal, +- falsealm_cnt->cnt_crc8_fail, +- falsealm_cnt->cnt_mcs_fail); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n", +- falsealm_cnt->cnt_ofdm_fail, +- falsealm_cnt->cnt_cck_fail, +- falsealm_cnt->cnt_all); +-} +- +-static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct dig_t *de_digtable = &rtlpriv->dm_digtable; +- struct rtl_mac *mac = rtl_mac(rtlpriv); +- +- /* Determine the minimum RSSI */ +- if ((mac->link_state < MAC80211_LINKED) && +- (rtlpriv->dm.UNDEC_SM_PWDB == 0)) { +- de_digtable->min_undec_pwdb_for_dm = 0; +- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, +- "Not connected to any\n"); +- } +- if (mac->link_state >= MAC80211_LINKED) { +- if (mac->opmode == NL80211_IFTYPE_AP || +- mac->opmode == NL80211_IFTYPE_ADHOC) { +- de_digtable->min_undec_pwdb_for_dm = +- rtlpriv->dm.UNDEC_SM_PWDB; +- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, +- "AP Client PWDB = 0x%lx\n", +- rtlpriv->dm.UNDEC_SM_PWDB); +- } else { +- de_digtable->min_undec_pwdb_for_dm = +- rtlpriv->dm.undec_sm_pwdb; +- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, +- "STA Default Port PWDB = 0x%x\n", +- de_digtable->min_undec_pwdb_for_dm); +- } +- } else { +- de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB; +- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, +- "AP Ext Port or disconnect PWDB = 0x%x\n", +- de_digtable->min_undec_pwdb_for_dm); +- } +- +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n", +- de_digtable->min_undec_pwdb_for_dm); +-} +- +-static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct dig_t *de_digtable = &rtlpriv->dm_digtable; +- unsigned long flag = 0; +- +- if (de_digtable->cursta_cstate == DIG_STA_CONNECT) { +- if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { +- if (de_digtable->min_undec_pwdb_for_dm <= 25) +- de_digtable->cur_cck_pd_state = +- CCK_PD_STAGE_LOWRSSI; +- else +- de_digtable->cur_cck_pd_state = +- CCK_PD_STAGE_HIGHRSSI; +- } else { +- if (de_digtable->min_undec_pwdb_for_dm <= 20) +- de_digtable->cur_cck_pd_state = +- CCK_PD_STAGE_LOWRSSI; +- else +- de_digtable->cur_cck_pd_state = +- CCK_PD_STAGE_HIGHRSSI; +- } +- } else { +- de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI; +- } +- if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) { +- if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { +- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); +- rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); +- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); +- } else { +- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); +- rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); +- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); +- } +- de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state; +- } +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n", +- de_digtable->cursta_cstate == DIG_STA_CONNECT ? +- "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT"); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n", +- de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ? +- "Low RSSI " : "High RSSI "); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n", +- IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)); +- +-} +- +-void rtl92d_dm_write_dig(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct dig_t *de_digtable = &rtlpriv->dm_digtable; +- +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", +- de_digtable->cur_igvalue, de_digtable->pre_igvalue, +- de_digtable->back_val); +- if (de_digtable->dig_enable_flag == false) { +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n"); +- de_digtable->pre_igvalue = 0x17; +- return; +- } +- if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) { +- rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, +- de_digtable->cur_igvalue); +- rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, +- de_digtable->cur_igvalue); +- de_digtable->pre_igvalue = de_digtable->cur_igvalue; +- } +-} +- +-static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv) +-{ +- struct dig_t *de_digtable = &rtlpriv->dm_digtable; +- +- if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) && +- (rtlpriv->mac80211.vendor == PEER_CISCO)) { +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n"); +- if (de_digtable->last_min_undec_pwdb_for_dm >= 50 +- && de_digtable->min_undec_pwdb_for_dm < 50) { +- rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "Early Mode Off\n"); +- } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 && +- de_digtable->min_undec_pwdb_for_dm > 55) { +- rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "Early Mode On\n"); +- } +- } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) { +- rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n"); +- } +-} +- +-static void rtl92d_dm_dig(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct dig_t *de_digtable = &rtlpriv->dm_digtable; +- u8 value_igi = de_digtable->cur_igvalue; +- struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); +- +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n"); +- if (rtlpriv->rtlhal.earlymode_enable) { +- rtl92d_early_mode_enabled(rtlpriv); +- de_digtable->last_min_undec_pwdb_for_dm = +- de_digtable->min_undec_pwdb_for_dm; +- } +- if (!rtlpriv->dm.dm_initialgain_enable) +- return; +- +- /* because we will send data pkt when scanning +- * this will cause some ap like gear-3700 wep TP +- * lower if we return here, this is the diff of +- * mac80211 driver vs ieee80211 driver */ +- /* if (rtlpriv->mac80211.act_scanning) +- * return; */ +- +- /* Not STA mode return tmp */ +- if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) +- return; +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n"); +- /* Decide the current status and if modify initial gain or not */ +- if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) +- de_digtable->cursta_cstate = DIG_STA_CONNECT; +- else +- de_digtable->cursta_cstate = DIG_STA_DISCONNECT; +- +- /* adjust initial gain according to false alarm counter */ +- if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0) +- value_igi--; +- else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1) +- value_igi += 0; +- else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2) +- value_igi++; +- else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2) +- value_igi += 2; +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n", +- de_digtable->large_fa_hit, de_digtable->forbidden_igi); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n", +- de_digtable->recover_cnt, de_digtable->rx_gain_min); +- +- /* deal with abnormally large false alarm */ +- if (falsealm_cnt->cnt_all > 10000) { +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "dm_DIG(): Abnormally false alarm case\n"); +- +- de_digtable->large_fa_hit++; +- if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) { +- de_digtable->forbidden_igi = de_digtable->cur_igvalue; +- de_digtable->large_fa_hit = 1; +- } +- if (de_digtable->large_fa_hit >= 3) { +- if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX) +- de_digtable->rx_gain_min = DM_DIG_MAX; +- else +- de_digtable->rx_gain_min = +- (de_digtable->forbidden_igi + 1); +- de_digtable->recover_cnt = 3600; /* 3600=2hr */ +- } +- } else { +- /* Recovery mechanism for IGI lower bound */ +- if (de_digtable->recover_cnt != 0) { +- de_digtable->recover_cnt--; +- } else { +- if (de_digtable->large_fa_hit == 0) { +- if ((de_digtable->forbidden_igi - 1) < +- DM_DIG_FA_LOWER) { +- de_digtable->forbidden_igi = +- DM_DIG_FA_LOWER; +- de_digtable->rx_gain_min = +- DM_DIG_FA_LOWER; +- +- } else { +- de_digtable->forbidden_igi--; +- de_digtable->rx_gain_min = +- (de_digtable->forbidden_igi + 1); +- } +- } else if (de_digtable->large_fa_hit == 3) { +- de_digtable->large_fa_hit = 0; +- } +- } +- } +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n", +- de_digtable->large_fa_hit, de_digtable->forbidden_igi); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, +- "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n", +- de_digtable->recover_cnt, de_digtable->rx_gain_min); +- +- if (value_igi > DM_DIG_MAX) +- value_igi = DM_DIG_MAX; +- else if (value_igi < de_digtable->rx_gain_min) +- value_igi = de_digtable->rx_gain_min; +- de_digtable->cur_igvalue = value_igi; +- rtl92d_dm_write_dig(hw); +- if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) +- rtl92d_dm_cck_packet_detection_thresh(hw); +- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n"); +-} +- + static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -579,626 +140,7 @@ static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw) + } + } + +-void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- +- rtlpriv->dm.current_turbo_edca = false; +- rtlpriv->dm.is_any_nonbepkts = false; +- rtlpriv->dm.is_cur_rdlstate = false; +-} +- +-static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- const u32 edca_be_ul = 0x5ea42b; +- const u32 edca_be_dl = 0x5ea42b; +- static u64 last_txok_cnt; +- static u64 last_rxok_cnt; +- u64 cur_txok_cnt; +- u64 cur_rxok_cnt; +- +- if (mac->link_state != MAC80211_LINKED) { +- rtlpriv->dm.current_turbo_edca = false; +- goto exit; +- } +- +- if ((!rtlpriv->dm.is_any_nonbepkts) && +- (!rtlpriv->dm.disable_framebursting)) { +- cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; +- cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; +- if (cur_rxok_cnt > 4 * cur_txok_cnt) { +- if (!rtlpriv->dm.is_cur_rdlstate || +- !rtlpriv->dm.current_turbo_edca) { +- rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, +- edca_be_dl); +- rtlpriv->dm.is_cur_rdlstate = true; +- } +- } else { +- if (rtlpriv->dm.is_cur_rdlstate || +- !rtlpriv->dm.current_turbo_edca) { +- rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, +- edca_be_ul); +- rtlpriv->dm.is_cur_rdlstate = false; +- } +- } +- rtlpriv->dm.current_turbo_edca = true; +- } else { +- if (rtlpriv->dm.current_turbo_edca) { +- u8 tmp = AC0_BE; +- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, +- &tmp); +- rtlpriv->dm.current_turbo_edca = false; +- } +- } +- +-exit: +- rtlpriv->dm.is_any_nonbepkts = false; +- last_txok_cnt = rtlpriv->stats.txbytesunicast; +- last_rxok_cnt = rtlpriv->stats.rxbytesunicast; +-} +- +-static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 index_mapping[RX_INDEX_MAPPING_NUM] = { +- 0x0f, 0x0f, 0x0d, 0x0c, 0x0b, +- 0x0a, 0x09, 0x08, 0x07, 0x06, +- 0x05, 0x04, 0x04, 0x03, 0x02 +- }; +- int i; +- u32 u4tmp; +- +- u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter - +- rtlpriv->dm.thermalvalue_rxgain)]) << 12; +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "===> Rx Gain %x\n", u4tmp); +- for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) +- rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK, +- (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); +-} +- +-static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, +- u8 *cck_index_old) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- int i; +- unsigned long flag = 0; +- long temp_cck; +- const u8 *cckswing; +- +- /* Query CCK default setting From 0xa24 */ +- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); +- temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, +- MASKDWORD) & MASKCCK; +- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); +- for (i = 0; i < CCK_TABLE_LENGTH; i++) { +- if (rtlpriv->dm.cck_inch14) +- cckswing = &cckswing_table_ch14[i][2]; +- else +- cckswing = &cckswing_table_ch1ch13[i][2]; +- +- if (temp_cck == le32_to_cpu(*((__le32 *)cckswing))) { +- *cck_index_old = (u8)i; +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n", +- RCCK0_TXFILTER2, temp_cck, +- *cck_index_old, +- rtlpriv->dm.cck_inch14); +- break; +- } +- } +- *temp_cckg = temp_cck; +-} +- +-static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, +- bool *internal_pa, u8 thermalvalue, u8 delta, +- u8 rf, struct rtl_efuse *rtlefuse, +- struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy, +- const u8 index_mapping[5][INDEX_MAPPING_NUM], +- const u8 index_mapping_pa[8][INDEX_MAPPING_NUM]) +-{ +- int i; +- u8 index; +- u8 offset = 0; +- +- for (i = 0; i < rf; i++) { +- if (rtlhal->macphymode == DUALMAC_DUALPHY && +- rtlhal->interfaceindex == 1) /* MAC 1 5G */ +- *internal_pa = rtlefuse->internal_pa_5g[1]; +- else +- *internal_pa = rtlefuse->internal_pa_5g[i]; +- if (*internal_pa) { +- if (rtlhal->interfaceindex == 1 || i == rf) +- offset = 4; +- else +- offset = 0; +- if (rtlphy->current_channel >= 100 && +- rtlphy->current_channel <= 165) +- offset += 2; +- } else { +- if (rtlhal->interfaceindex == 1 || i == rf) +- offset = 2; +- else +- offset = 0; +- } +- if (thermalvalue > rtlefuse->eeprom_thermalmeter) +- offset++; +- if (*internal_pa) { +- if (delta > INDEX_MAPPING_NUM - 1) +- index = index_mapping_pa[offset] +- [INDEX_MAPPING_NUM - 1]; +- else +- index = +- index_mapping_pa[offset][delta]; +- } else { +- if (delta > INDEX_MAPPING_NUM - 1) +- index = +- index_mapping[offset][INDEX_MAPPING_NUM - 1]; +- else +- index = index_mapping[offset][delta]; +- } +- if (thermalvalue > rtlefuse->eeprom_thermalmeter) { +- if (*internal_pa && thermalvalue > 0x12) { +- ofdm_index[i] = rtlpriv->dm.ofdm_index[i] - +- ((delta / 2) * 3 + (delta % 2)); +- } else { +- ofdm_index[i] -= index; +- } +- } else { +- ofdm_index[i] += index; +- } +- } +-} +- +-static void rtl92d_dm_txpower_tracking_callback_thermalmeter( +- struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain; +- u8 offset, thermalvalue_avg_count = 0; +- u32 thermalvalue_avg = 0; +- bool internal_pa = false; +- long ele_a = 0, ele_d, temp_cck, val_x, value32; +- long val_y, ele_c = 0; +- u8 ofdm_index[2]; +- s8 cck_index = 0; +- u8 ofdm_index_old[2] = {0, 0}; +- s8 cck_index_old = 0; +- u8 index; +- int i; +- bool is2t = IS_92D_SINGLEPHY(rtlhal->version); +- u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; +- u8 indexforchannel = +- rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); +- static const u8 index_mapping[5][INDEX_MAPPING_NUM] = { +- /* 5G, path A/MAC 0, decrease power */ +- {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, +- /* 5G, path A/MAC 0, increase power */ +- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, +- /* 5G, path B/MAC 1, decrease power */ +- {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, +- /* 5G, path B/MAC 1, increase power */ +- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, +- /* 2.4G, for decreas power */ +- {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, +- }; +- static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = { +- /* 5G, path A/MAC 0, ch36-64, decrease power */ +- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, +- /* 5G, path A/MAC 0, ch36-64, increase power */ +- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, +- /* 5G, path A/MAC 0, ch100-165, decrease power */ +- {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, +- /* 5G, path A/MAC 0, ch100-165, increase power */ +- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, +- /* 5G, path B/MAC 1, ch36-64, decrease power */ +- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, +- /* 5G, path B/MAC 1, ch36-64, increase power */ +- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, +- /* 5G, path B/MAC 1, ch100-165, decrease power */ +- {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, +- /* 5G, path B/MAC 1, ch100-165, increase power */ +- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, +- }; +- +- rtlpriv->dm.txpower_trackinginit = true; +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n"); +- thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800); +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", +- thermalvalue, +- rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); +- rtl92d_phy_ap_calibrate(hw, (thermalvalue - +- rtlefuse->eeprom_thermalmeter)); +- +- if (!thermalvalue) +- goto exit; +- +- if (is2t) +- rf = 2; +- else +- rf = 1; +- +- if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex) +- goto old_index_done; +- +- ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; +- for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { +- if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { +- ofdm_index_old[0] = (u8)i; +- +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", +- ROFDM0_XATXIQIMBALANCE, +- ele_d, ofdm_index_old[0]); +- break; +- } +- } +- if (is2t) { +- ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, +- MASKDWORD) & MASKOFDM_D; +- for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { +- if (ele_d == +- (ofdmswing_table[i] & MASKOFDM_D)) { +- ofdm_index_old[1] = (u8)i; +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, +- DBG_LOUD, +- "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n", +- ROFDM0_XBTXIQIMBALANCE, ele_d, +- ofdm_index_old[1]); +- break; +- } +- } +- } +- if (rtlhal->current_bandtype == BAND_ON_2_4G) { +- rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old); +- } else { +- temp_cck = 0x090e1317; +- cck_index_old = 12; +- } +- +- if (!rtlpriv->dm.thermalvalue) { +- rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; +- rtlpriv->dm.thermalvalue_lck = thermalvalue; +- rtlpriv->dm.thermalvalue_iqk = thermalvalue; +- rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; +- for (i = 0; i < rf; i++) +- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; +- rtlpriv->dm.cck_index = cck_index_old; +- } +- if (rtlhal->reloadtxpowerindex) { +- for (i = 0; i < rf; i++) +- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; +- rtlpriv->dm.cck_index = cck_index_old; +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "reload ofdm index for band switch\n"); +- } +-old_index_done: +- for (i = 0; i < rf; i++) +- ofdm_index[i] = rtlpriv->dm.ofdm_index[i]; +- +- rtlpriv->dm.thermalvalue_avg +- [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue; +- rtlpriv->dm.thermalvalue_avg_index++; +- if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM) +- rtlpriv->dm.thermalvalue_avg_index = 0; +- for (i = 0; i < AVG_THERMAL_NUM; i++) { +- if (rtlpriv->dm.thermalvalue_avg[i]) { +- thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i]; +- thermalvalue_avg_count++; +- } +- } +- if (thermalvalue_avg_count) +- thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); +- if (rtlhal->reloadtxpowerindex) { +- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? +- (thermalvalue - rtlefuse->eeprom_thermalmeter) : +- (rtlefuse->eeprom_thermalmeter - thermalvalue); +- rtlhal->reloadtxpowerindex = false; +- rtlpriv->dm.done_txpower = false; +- } else if (rtlpriv->dm.done_txpower) { +- delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? +- (thermalvalue - rtlpriv->dm.thermalvalue) : +- (rtlpriv->dm.thermalvalue - thermalvalue); +- } else { +- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? +- (thermalvalue - rtlefuse->eeprom_thermalmeter) : +- (rtlefuse->eeprom_thermalmeter - thermalvalue); +- } +- delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? +- (thermalvalue - rtlpriv->dm.thermalvalue_lck) : +- (rtlpriv->dm.thermalvalue_lck - thermalvalue); +- delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? +- (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : +- (rtlpriv->dm.thermalvalue_iqk - thermalvalue); +- delta_rxgain = +- (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ? +- (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) : +- (rtlpriv->dm.thermalvalue_rxgain - thermalvalue); +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", +- thermalvalue, rtlpriv->dm.thermalvalue, +- rtlefuse->eeprom_thermalmeter, delta, delta_lck, +- delta_iqk); +- if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) { +- rtlpriv->dm.thermalvalue_lck = thermalvalue; +- rtl92d_phy_lc_calibrate(hw); +- } +- +- if (delta == 0 || !rtlpriv->dm.txpower_track_control) +- goto check_delta; +- +- rtlpriv->dm.done_txpower = true; +- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? +- (thermalvalue - rtlefuse->eeprom_thermalmeter) : +- (rtlefuse->eeprom_thermalmeter - thermalvalue); +- if (rtlhal->current_bandtype == BAND_ON_2_4G) { +- offset = 4; +- if (delta > INDEX_MAPPING_NUM - 1) +- index = index_mapping[offset][INDEX_MAPPING_NUM - 1]; +- else +- index = index_mapping[offset][delta]; +- if (thermalvalue > rtlpriv->dm.thermalvalue) { +- for (i = 0; i < rf; i++) +- ofdm_index[i] -= delta; +- cck_index -= delta; +- } else { +- for (i = 0; i < rf; i++) +- ofdm_index[i] += index; +- cck_index += index; +- } +- } else if (rtlhal->current_bandtype == BAND_ON_5G) { +- rtl92d_bandtype_5G(rtlhal, ofdm_index, +- &internal_pa, thermalvalue, +- delta, rf, rtlefuse, rtlpriv, +- rtlphy, index_mapping, +- index_mapping_internal_pa); +- } +- if (is2t) { +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n", +- rtlpriv->dm.ofdm_index[0], +- rtlpriv->dm.ofdm_index[1], +- rtlpriv->dm.cck_index); +- } else { +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "temp OFDM_A_index=0x%x,cck_index = 0x%x\n", +- rtlpriv->dm.ofdm_index[0], +- rtlpriv->dm.cck_index); +- } +- for (i = 0; i < rf; i++) { +- if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) { +- ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1; +- } else if (internal_pa || +- rtlhal->current_bandtype == BAND_ON_2_4G) { +- if (ofdm_index[i] < ofdm_min_index_internal_pa) +- ofdm_index[i] = ofdm_min_index_internal_pa; +- } else if (ofdm_index[i] < ofdm_min_index) { +- ofdm_index[i] = ofdm_min_index; +- } +- } +- if (rtlhal->current_bandtype == BAND_ON_2_4G) { +- if (cck_index > CCK_TABLE_SIZE - 1) { +- cck_index = CCK_TABLE_SIZE - 1; +- } else if (cck_index < 0) { +- cck_index = 0; +- } +- } +- if (is2t) { +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", +- ofdm_index[0], ofdm_index[1], +- cck_index); +- } else { +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "new OFDM_A_index=0x%x,cck_index = 0x%x\n", +- ofdm_index[0], cck_index); +- } +- ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; +- val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0]; +- val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1]; +- if (val_x != 0) { +- if ((val_x & 0x00000200) != 0) +- val_x = val_x | 0xFFFFFC00; +- ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; +- +- /* new element C = element D x Y */ +- if ((val_y & 0x00000200) != 0) +- val_y = val_y | 0xFFFFFC00; +- ele_c = ((val_y * ele_d) >> 8) & 0x000003FF; +- +- /* write new elements A, C, D to regC80 and +- * regC94, element B is always 0 +- */ +- value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; +- rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, +- MASKDWORD, value32); +- +- value32 = (ele_c & 0x000003C0) >> 6; +- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, +- value32); +- +- value32 = ((val_x * ele_d) >> 7) & 0x01; +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), +- value32); +- +- } else { +- rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, +- MASKDWORD, +- ofdmswing_table[(u8)ofdm_index[0]]); +- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, +- 0x00); +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, +- BIT(24), 0x00); +- } +- +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n", +- rtlhal->interfaceindex, +- val_x, val_y, ele_a, ele_c, ele_d, +- val_x, val_y); +- +- if (cck_index >= CCK_TABLE_SIZE) +- cck_index = CCK_TABLE_SIZE - 1; +- if (cck_index < 0) +- cck_index = 0; +- if (rtlhal->current_bandtype == BAND_ON_2_4G) { +- /* Adjust CCK according to IQK result */ +- if (!rtlpriv->dm.cck_inch14) { +- rtl_write_byte(rtlpriv, 0xa22, +- cckswing_table_ch1ch13[cck_index][0]); +- rtl_write_byte(rtlpriv, 0xa23, +- cckswing_table_ch1ch13[cck_index][1]); +- rtl_write_byte(rtlpriv, 0xa24, +- cckswing_table_ch1ch13[cck_index][2]); +- rtl_write_byte(rtlpriv, 0xa25, +- cckswing_table_ch1ch13[cck_index][3]); +- rtl_write_byte(rtlpriv, 0xa26, +- cckswing_table_ch1ch13[cck_index][4]); +- rtl_write_byte(rtlpriv, 0xa27, +- cckswing_table_ch1ch13[cck_index][5]); +- rtl_write_byte(rtlpriv, 0xa28, +- cckswing_table_ch1ch13[cck_index][6]); +- rtl_write_byte(rtlpriv, 0xa29, +- cckswing_table_ch1ch13[cck_index][7]); +- } else { +- rtl_write_byte(rtlpriv, 0xa22, +- cckswing_table_ch14[cck_index][0]); +- rtl_write_byte(rtlpriv, 0xa23, +- cckswing_table_ch14[cck_index][1]); +- rtl_write_byte(rtlpriv, 0xa24, +- cckswing_table_ch14[cck_index][2]); +- rtl_write_byte(rtlpriv, 0xa25, +- cckswing_table_ch14[cck_index][3]); +- rtl_write_byte(rtlpriv, 0xa26, +- cckswing_table_ch14[cck_index][4]); +- rtl_write_byte(rtlpriv, 0xa27, +- cckswing_table_ch14[cck_index][5]); +- rtl_write_byte(rtlpriv, 0xa28, +- cckswing_table_ch14[cck_index][6]); +- rtl_write_byte(rtlpriv, 0xa29, +- cckswing_table_ch14[cck_index][7]); +- } +- } +- if (is2t) { +- ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22; +- val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4]; +- val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5]; +- if (val_x != 0) { +- if ((val_x & 0x00000200) != 0) +- /* consider minus */ +- val_x = val_x | 0xFFFFFC00; +- ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; +- /* new element C = element D x Y */ +- if ((val_y & 0x00000200) != 0) +- val_y = val_y | 0xFFFFFC00; +- ele_c = ((val_y * ele_d) >> 8) & 0x00003FF; +- /* write new elements A, C, D to regC88 +- * and regC9C, element B is always 0 +- */ +- value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; +- rtl_set_bbreg(hw, +- ROFDM0_XBTXIQIMBALANCE, +- MASKDWORD, value32); +- value32 = (ele_c & 0x000003C0) >> 6; +- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, +- MASKH4BITS, value32); +- value32 = ((val_x * ele_d) >> 7) & 0x01; +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, +- BIT(28), value32); +- } else { +- rtl_set_bbreg(hw, +- ROFDM0_XBTXIQIMBALANCE, +- MASKDWORD, +- ofdmswing_table[ofdm_index[1]]); +- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, +- MASKH4BITS, 0x00); +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, +- BIT(28), 0x00); +- } +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n", +- val_x, val_y, ele_a, ele_c, +- ele_d, val_x, val_y); +- } +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", +- rtl_get_bbreg(hw, 0xc80, MASKDWORD), +- rtl_get_bbreg(hw, 0xc94, MASKDWORD), +- rtl_get_rfreg(hw, RF90_PATH_A, 0x24, +- RFREG_OFFSET_MASK)); +- +-check_delta: +- if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) { +- rtl92d_phy_reset_iqk_result(hw); +- rtlpriv->dm.thermalvalue_iqk = thermalvalue; +- rtl92d_phy_iq_calibrate(hw); +- } +- if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G && +- thermalvalue <= rtlefuse->eeprom_thermalmeter) { +- rtlpriv->dm.thermalvalue_rxgain = thermalvalue; +- rtl92d_dm_rxgain_tracking_thermalmeter(hw); +- } +- if (rtlpriv->dm.txpower_track_control) +- rtlpriv->dm.thermalvalue = thermalvalue; +- +-exit: +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); +-} +- +-static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- +- rtlpriv->dm.txpower_tracking = true; +- rtlpriv->dm.txpower_trackinginit = false; +- rtlpriv->dm.txpower_track_control = true; +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "pMgntInfo->txpower_tracking = %d\n", +- rtlpriv->dm.txpower_tracking); +-} +- +-void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- +- if (!rtlpriv->dm.txpower_tracking) +- return; +- +- if (!rtlpriv->dm.tm_trigger) { +- rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) | +- BIT(16), 0x03); +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "Trigger 92S Thermal Meter!!\n"); +- rtlpriv->dm.tm_trigger = 1; +- return; +- } else { +- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "Schedule TxPowerTracking direct call!!\n"); +- rtl92d_dm_txpower_tracking_callback_thermalmeter(hw); +- rtlpriv->dm.tm_trigger = 0; +- } +-} +- +-void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rate_adaptive *ra = &(rtlpriv->ra); +- +- ra->ratr_state = DM_RATR_STA_INIT; +- ra->pre_ratr_state = DM_RATR_STA_INIT; +- if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) +- rtlpriv->dm.useramask = true; +- else +- rtlpriv->dm.useramask = false; +-} +- +-void rtl92d_dm_init(struct ieee80211_hw *hw) ++void rtl92de_dm_init(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + +@@ -1212,7 +154,7 @@ void rtl92d_dm_init(struct ieee80211_hw *hw) + rtl92d_dm_initialize_txpower_tracking(hw); + } + +-void rtl92d_dm_watchdog(struct ieee80211_hw *hw) ++void rtl92de_dm_watchdog(struct ieee80211_hw *hw) + { + struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); + bool fw_current_inpsmode = false; +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h +index 939cc45bfebd..beade227b442 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h +@@ -4,94 +4,7 @@ + #ifndef __RTL92C_DM_H__ + #define __RTL92C_DM_H__ + +-#define HAL_DM_DIG_DISABLE BIT(0) +-#define HAL_DM_HIPWR_DISABLE BIT(1) +- +-#define OFDM_TABLE_LENGTH 37 +-#define OFDM_TABLE_SIZE_92D 43 +-#define CCK_TABLE_LENGTH 33 +- +-#define CCK_TABLE_SIZE 33 +- +-#define BW_AUTO_SWITCH_HIGH_LOW 25 +-#define BW_AUTO_SWITCH_LOW_HIGH 30 +- +-#define DM_DIG_FA_UPPER 0x32 +-#define DM_DIG_FA_LOWER 0x20 +-#define DM_DIG_FA_TH0 0x100 +-#define DM_DIG_FA_TH1 0x400 +-#define DM_DIG_FA_TH2 0x600 +- +-#define RXPATHSELECTION_SS_TH_LOW 30 +-#define RXPATHSELECTION_DIFF_TH 18 +- +-#define DM_RATR_STA_INIT 0 +-#define DM_RATR_STA_HIGH 1 +-#define DM_RATR_STA_MIDDLE 2 +-#define DM_RATR_STA_LOW 3 +- +-#define CTS2SELF_THVAL 30 +-#define REGC38_TH 20 +- +-#define WAIOTTHVAL 25 +- +-#define TXHIGHPWRLEVEL_NORMAL 0 +-#define TXHIGHPWRLEVEL_LEVEL1 1 +-#define TXHIGHPWRLEVEL_LEVEL2 2 +-#define TXHIGHPWRLEVEL_BT1 3 +-#define TXHIGHPWRLEVEL_BT2 4 +- +-#define DM_TYPE_BYFW 0 +-#define DM_TYPE_BYDRIVER 1 +- +-#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +-#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +-#define INDEX_MAPPING_NUM 13 +- +-struct swat { +- u8 failure_cnt; +- u8 try_flag; +- u8 stop_trying; +- long pre_rssi; +- long trying_threshold; +- u8 cur_antenna; +- u8 pre_antenna; +-}; +- +-enum tag_dynamic_init_gain_operation_type_definition { +- DIG_TYPE_THRESH_HIGH = 0, +- DIG_TYPE_THRESH_LOW = 1, +- DIG_TYPE_BACKOFF = 2, +- DIG_TYPE_RX_GAIN_MIN = 3, +- DIG_TYPE_RX_GAIN_MAX = 4, +- DIG_TYPE_ENABLE = 5, +- DIG_TYPE_DISABLE = 6, +- DIG_OP_TYPE_MAX +-}; +- +-enum dm_1r_cca { +- CCA_1R = 0, +- CCA_2R = 1, +- CCA_MAX = 2, +-}; +- +-enum dm_rf { +- RF_SAVE = 0, +- RF_NORMAL = 1, +- RF_MAX = 2, +-}; +- +-enum dm_sw_ant_switch { +- ANS_ANTENNA_B = 1, +- ANS_ANTENNA_A = 2, +- ANS_ANTENNA_MAX = 3, +-}; +- +-void rtl92d_dm_init(struct ieee80211_hw *hw); +-void rtl92d_dm_watchdog(struct ieee80211_hw *hw); +-void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw); +-void rtl92d_dm_write_dig(struct ieee80211_hw *hw); +-void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw); +-void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); ++void rtl92de_dm_init(struct ieee80211_hw *hw); ++void rtl92de_dm_watchdog(struct ieee80211_hw *hw); + + #endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c +index e1fb29962801..c8444a72ff69 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c +@@ -5,157 +5,12 @@ + #include "../pci.h" + #include "../base.h" + #include "../efuse.h" +-#include "reg.h" +-#include "def.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/fw_common.h" + #include "fw.h" + #include "sw.h" + +-static bool _rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv) +-{ +- return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ? +- true : false; +-} +- +-static void _rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 tmp; +- +- if (enable) { +- tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); +- rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04); +- tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); +- rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01); +- tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2); +- rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7); +- } else { +- tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); +- rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe); +- /* Reserved for fw extension. +- * 0x81[7] is used for mac0 status , +- * so don't write this reg here +- * rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);*/ +- } +-} +- +-static void _rtl92d_write_fw(struct ieee80211_hw *hw, +- enum version_8192d version, u8 *buffer, u32 size) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u8 *bufferptr = buffer; +- u32 pagenums, remainsize; +- u32 page, offset; +- +- rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size); +- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) +- rtl_fill_dummy(bufferptr, &size); +- pagenums = size / FW_8192D_PAGE_SIZE; +- remainsize = size % FW_8192D_PAGE_SIZE; +- if (pagenums > 8) +- pr_err("Page numbers should not greater then 8\n"); +- for (page = 0; page < pagenums; page++) { +- offset = page * FW_8192D_PAGE_SIZE; +- rtl_fw_page_write(hw, page, (bufferptr + offset), +- FW_8192D_PAGE_SIZE); +- } +- if (remainsize) { +- offset = pagenums * FW_8192D_PAGE_SIZE; +- page = pagenums; +- rtl_fw_page_write(hw, page, (bufferptr + offset), remainsize); +- } +-} +- +-static int _rtl92d_fw_free_to_go(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 counter = 0; +- u32 value32; +- +- do { +- value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); +- } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) && +- (!(value32 & FWDL_CHKSUM_RPT))); +- if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) { +- pr_err("chksum report fail! REG_MCUFWDL:0x%08x\n", +- value32); +- return -EIO; +- } +- value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); +- value32 |= MCUFWDL_RDY; +- rtl_write_dword(rtlpriv, REG_MCUFWDL, value32); +- return 0; +-} +- +-void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 u1b_tmp; +- u8 delay = 100; +- +- /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ +- rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); +- u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); +- while (u1b_tmp & BIT(2)) { +- delay--; +- if (delay == 0) +- break; +- udelay(50); +- u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); +- } +- WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n"); +- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, +- "=====> 8051 reset success (%d)\n", delay); +-} +- +-static int _rtl92d_fw_init(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u32 counter; +- +- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, "FW already have download\n"); +- /* polling for FW ready */ +- counter = 0; +- do { +- if (rtlhal->interfaceindex == 0) { +- if (rtl_read_byte(rtlpriv, FW_MAC0_READY) & +- MAC0_READY) { +- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, +- "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", +- rtl_read_byte(rtlpriv, +- FW_MAC0_READY)); +- return 0; +- } +- udelay(5); +- } else { +- if (rtl_read_byte(rtlpriv, FW_MAC1_READY) & +- MAC1_READY) { +- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, +- "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", +- rtl_read_byte(rtlpriv, +- FW_MAC1_READY)); +- return 0; +- } +- udelay(5); +- } +- } while (counter++ < POLLING_READY_TIMEOUT_COUNT); +- +- if (rtlhal->interfaceindex == 0) { +- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, +- "Polling FW ready fail!! MAC0 FW init not ready: 0x%x\n", +- rtl_read_byte(rtlpriv, FW_MAC0_READY)); +- } else { +- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, +- "Polling FW ready fail!! MAC1 FW init not ready: 0x%x\n", +- rtl_read_byte(rtlpriv, FW_MAC1_READY)); +- } +- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, +- "Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", +- rtl_read_dword(rtlpriv, REG_MCUFWDL)); +- return -1; +-} +- + int rtl92d_download_fw(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -189,7 +44,7 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) + } + + spin_lock_irqsave(&globalmutex_for_fwdownload, flags); +- fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv); ++ fw_downloaded = rtl92d_is_fw_downloaded(rtlpriv); + if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) + fwdl_in_process = true; + else +@@ -202,7 +57,7 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) + for (count = 0; count < 5000; count++) { + udelay(500); + spin_lock_irqsave(&globalmutex_for_fwdownload, flags); +- fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv); ++ fw_downloaded = rtl92d_is_fw_downloaded(rtlpriv); + if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) + fwdl_in_process = true; + else +@@ -237,11 +92,11 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) + rtl92d_firmware_selfreset(hw); + rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); + } +- _rtl92d_enable_fw_download(hw, true); +- _rtl92d_write_fw(hw, version, pfwdata, fwsize); +- _rtl92d_enable_fw_download(hw, false); ++ rtl92d_enable_fw_download(hw, true); ++ rtl92d_write_fw(hw, version, pfwdata, fwsize); ++ rtl92d_enable_fw_download(hw, false); + spin_lock_irqsave(&globalmutex_for_fwdownload, flags); +- err = _rtl92d_fw_free_to_go(hw); ++ err = rtl92d_fw_free_to_go(hw); + /* download fw over,clear 0x1f[5] */ + value = rtl_read_byte(rtlpriv, 0x1f); + value &= (~BIT(5)); +@@ -250,207 +105,10 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) + if (err) + pr_err("fw is not ready to run!\n"); + exit: +- err = _rtl92d_fw_init(hw); ++ err = rtl92d_fw_init(hw); + return err; + } + +-static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 val_hmetfr; +- bool result = false; +- +- val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR); +- if (((val_hmetfr >> boxnum) & BIT(0)) == 0) +- result = true; +- return result; +-} +- +-static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, +- u8 element_id, u32 cmd_len, u8 *cmdbuffer) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); +- u8 boxnum; +- u16 box_reg = 0, box_extreg = 0; +- u8 u1b_tmp; +- bool isfw_read = false; +- u8 buf_index = 0; +- bool bwrite_success = false; +- u8 wait_h2c_limmit = 100; +- u8 wait_writeh2c_limmit = 100; +- u8 boxcontent[4], boxextcontent[2]; +- u32 h2c_waitcounter = 0; +- unsigned long flag; +- u8 idx; +- +- if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) { +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "Return as RF is off!!!\n"); +- return; +- } +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n"); +- while (true) { +- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); +- if (rtlhal->h2c_setinprogress) { +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "H2C set in progress! Wait to set..element_id(%d)\n", +- element_id); +- +- while (rtlhal->h2c_setinprogress) { +- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, +- flag); +- h2c_waitcounter++; +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "Wait 100 us (%d times)...\n", +- h2c_waitcounter); +- udelay(100); +- +- if (h2c_waitcounter > 1000) +- return; +- +- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, +- flag); +- } +- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); +- } else { +- rtlhal->h2c_setinprogress = true; +- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); +- break; +- } +- } +- while (!bwrite_success) { +- wait_writeh2c_limmit--; +- if (wait_writeh2c_limmit == 0) { +- pr_err("Write H2C fail because no trigger for FW INT!\n"); +- break; +- } +- boxnum = rtlhal->last_hmeboxnum; +- switch (boxnum) { +- case 0: +- box_reg = REG_HMEBOX_0; +- box_extreg = REG_HMEBOX_EXT_0; +- break; +- case 1: +- box_reg = REG_HMEBOX_1; +- box_extreg = REG_HMEBOX_EXT_1; +- break; +- case 2: +- box_reg = REG_HMEBOX_2; +- box_extreg = REG_HMEBOX_EXT_2; +- break; +- case 3: +- box_reg = REG_HMEBOX_3; +- box_extreg = REG_HMEBOX_EXT_3; +- break; +- default: +- pr_err("switch case %#x not processed\n", +- boxnum); +- break; +- } +- isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); +- while (!isfw_read) { +- wait_h2c_limmit--; +- if (wait_h2c_limmit == 0) { +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "Waiting too long for FW read clear HMEBox(%d)!\n", +- boxnum); +- break; +- } +- udelay(10); +- isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); +- u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF); +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", +- boxnum, u1b_tmp); +- } +- if (!isfw_read) { +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n", +- boxnum); +- break; +- } +- memset(boxcontent, 0, sizeof(boxcontent)); +- memset(boxextcontent, 0, sizeof(boxextcontent)); +- boxcontent[0] = element_id; +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "Write element_id box_reg(%4x) = %2x\n", +- box_reg, element_id); +- switch (cmd_len) { +- case 1: +- boxcontent[0] &= ~(BIT(7)); +- memcpy(boxcontent + 1, cmdbuffer + buf_index, 1); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- case 2: +- boxcontent[0] &= ~(BIT(7)); +- memcpy(boxcontent + 1, cmdbuffer + buf_index, 2); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- case 3: +- boxcontent[0] &= ~(BIT(7)); +- memcpy(boxcontent + 1, cmdbuffer + buf_index, 3); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- case 4: +- boxcontent[0] |= (BIT(7)); +- memcpy(boxextcontent, cmdbuffer + buf_index, 2); +- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2); +- for (idx = 0; idx < 2; idx++) +- rtl_write_byte(rtlpriv, box_extreg + idx, +- boxextcontent[idx]); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- case 5: +- boxcontent[0] |= (BIT(7)); +- memcpy(boxextcontent, cmdbuffer + buf_index, 2); +- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3); +- for (idx = 0; idx < 2; idx++) +- rtl_write_byte(rtlpriv, box_extreg + idx, +- boxextcontent[idx]); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- default: +- pr_err("switch case %#x not processed\n", +- cmd_len); +- break; +- } +- bwrite_success = true; +- rtlhal->last_hmeboxnum = boxnum + 1; +- if (rtlhal->last_hmeboxnum == 4) +- rtlhal->last_hmeboxnum = 0; +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, +- "pHalData->last_hmeboxnum = %d\n", +- rtlhal->last_hmeboxnum); +- } +- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); +- rtlhal->h2c_setinprogress = false; +- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); +- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n"); +-} +- +-void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, +- u8 element_id, u32 cmd_len, u8 *cmdbuffer) +-{ +- u32 tmp_cmdbuf[2]; +- +- memset(tmp_cmdbuf, 0, 8); +- memcpy(tmp_cmdbuf, cmdbuffer, cmd_len); +- _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf); +- return; +-} +- + static bool _rtl92d_cmd_send_packet(struct ieee80211_hw *hw, + struct sk_buff *skb) + { +@@ -599,7 +257,7 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) + struct sk_buff *skb = NULL; + u32 totalpacketlen; + bool rtstatus; +- u8 u1rsvdpageloc[3] = { 0 }; ++ u8 u1rsvdpageloc[3] = { PROBERSP_PG, PSPOLL_PG, NULL_PG }; + bool dlok = false; + u8 *beacon; + u8 *p_pspoll; +@@ -618,7 +276,6 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) + SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000)); + SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid); + SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr); +- SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG); + /*-------------------------------------------------------- + (3) null data + ---------------------------------------------------------*/ +@@ -626,7 +283,6 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) + SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid); + SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr); + SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid); +- SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG); + /*--------------------------------------------------------- + (4) probe response + ----------------------------------------------------------*/ +@@ -634,7 +290,6 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) + SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid); + SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr); + SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid); +- SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG); + totalpacketlen = TOTAL_RESERVED_PKT_LEN; + RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, + "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL", +@@ -663,11 +318,3 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "Set RSVD page location to Fw FAIL!!!!!!\n"); + } +- +-void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) +-{ +- u8 u1_joinbssrpt_parm[1] = {0}; +- +- SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus); +- rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm); +-} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h +index 7f0a17c1a9ea..9e1385ac17b1 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h +@@ -4,44 +4,7 @@ + #ifndef __RTL92D__FW__H__ + #define __RTL92D__FW__H__ + +-#define FW_8192D_START_ADDRESS 0x1000 +-#define FW_8192D_PAGE_SIZE 4096 +-#define FW_8192D_POLLING_TIMEOUT_COUNT 1000 +- +-#define IS_FW_HEADER_EXIST(_pfwhdr) \ +- ((GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x92C0 || \ +- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x88C0 || \ +- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D0 || \ +- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D1 || \ +- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D2 || \ +- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D3) +- +-/* Firmware Header(8-byte alinment required) */ +-/* --- LONG WORD 0 ---- */ +-#define GET_FIRMWARE_HDR_SIGNATURE(__fwhdr) \ +- le32_get_bits(*(__le32 *)__fwhdr, GENMASK(15, 0)) +-#define GET_FIRMWARE_HDR_VERSION(__fwhdr) \ +- le32_get_bits(*(__le32 *)(__fwhdr + 4), GENMASK(15, 0)) +-#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \ +- le32_get_bits(*(__le32 *)(__fwhdr + 4), GENMASK(23, 16)) +- +-#define pagenum_128(_len) \ +- (u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0)) +- +-#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \ +- *(u8 *)__ph2ccmd = __val; +-#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \ +- *(u8 *)__ph2ccmd = __val; +-#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \ +- *(u8 *)(__ph2ccmd + 1) = __val; +-#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \ +- *(u8 *)(__ph2ccmd + 2) = __val; +- + int rtl92d_download_fw(struct ieee80211_hw *hw); +-void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, +- u32 cmd_len, u8 *p_cmdbuffer); +-void rtl92d_firmware_selfreset(struct ieee80211_hw *hw); + void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished); +-void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus); + + #endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c +index 4ba42f6be3f2..73b81e60cfa9 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c +@@ -8,8 +8,12 @@ + #include "../cam.h" + #include "../ps.h" + #include "../pci.h" +-#include "reg.h" +-#include "def.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/dm_common.h" ++#include "../rtl8192d/fw_common.h" ++#include "../rtl8192d/hw_common.h" ++#include "../rtl8192d/phy_common.h" + #include "phy.h" + #include "dm.h" + #include "fw.h" +@@ -50,34 +54,6 @@ static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw, + rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); + } + +-static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 tmp1byte; +- +- tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); +- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); +- rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); +- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); +- tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); +- tmp1byte &= ~(BIT(0)); +- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); +-} +- +-static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 tmp1byte; +- +- tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); +- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); +- rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); +- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); +- tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); +- tmp1byte |= BIT(0); +- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); +-} +- + static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw) + { + _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); +@@ -90,58 +66,14 @@ static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw) + + void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + { +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); + struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); + + switch (variable) { + case HW_VAR_RCR: + *((u32 *) (val)) = rtlpci->receive_config; + break; +- case HW_VAR_RF_STATE: +- *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; +- break; +- case HW_VAR_FWLPS_RF_ON:{ +- enum rf_pwrstate rfstate; +- u32 val_rcr; +- +- rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, +- (u8 *)(&rfstate)); +- if (rfstate == ERFOFF) { +- *((bool *) (val)) = true; +- } else { +- val_rcr = rtl_read_dword(rtlpriv, REG_RCR); +- val_rcr &= 0x00070000; +- if (val_rcr) +- *((bool *) (val)) = false; +- else +- *((bool *) (val)) = true; +- } +- break; +- } +- case HW_VAR_FW_PSMODE_STATUS: +- *((bool *) (val)) = ppsc->fw_current_inpsmode; +- break; +- case HW_VAR_CORRECT_TSF:{ +- u64 tsf; +- u32 *ptsf_low = (u32 *)&tsf; +- u32 *ptsf_high = ((u32 *)&tsf) + 1; +- +- *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); +- *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); +- *((u64 *) (val)) = tsf; +- break; +- } +- case HW_VAR_INT_MIGRATION: +- *((bool *)(val)) = rtlpriv->dm.interrupt_migration; +- break; +- case HW_VAR_INT_AC: +- *((bool *)(val)) = rtlpriv->dm.disable_tx_int; +- break; +- case HAL_DEF_WOWLAN: +- break; + default: +- pr_err("switch case %#x not processed\n", variable); ++ rtl92d_get_hw_reg(hw, variable, val); + break; + } + } +@@ -151,141 +83,8 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); + struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); +- u8 idx; + + switch (variable) { +- case HW_VAR_ETHER_ADDR: +- for (idx = 0; idx < ETH_ALEN; idx++) { +- rtl_write_byte(rtlpriv, (REG_MACID + idx), +- val[idx]); +- } +- break; +- case HW_VAR_BASIC_RATE: { +- u16 rate_cfg = ((u16 *) val)[0]; +- u8 rate_index = 0; +- +- rate_cfg = rate_cfg & 0x15f; +- if (mac->vendor == PEER_CISCO && +- ((rate_cfg & 0x150) == 0)) +- rate_cfg |= 0x01; +- rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); +- rtl_write_byte(rtlpriv, REG_RRSR + 1, +- (rate_cfg >> 8) & 0xff); +- while (rate_cfg > 0x1) { +- rate_cfg = (rate_cfg >> 1); +- rate_index++; +- } +- if (rtlhal->fw_version > 0xe) +- rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, +- rate_index); +- break; +- } +- case HW_VAR_BSSID: +- for (idx = 0; idx < ETH_ALEN; idx++) { +- rtl_write_byte(rtlpriv, (REG_BSSID + idx), +- val[idx]); +- } +- break; +- case HW_VAR_SIFS: +- rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); +- rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); +- rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); +- rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); +- if (!mac->ht_enable) +- rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, +- 0x0e0e); +- else +- rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, +- *((u16 *) val)); +- break; +- case HW_VAR_SLOT_TIME: { +- u8 e_aci; +- +- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, +- "HW_VAR_SLOT_TIME %x\n", val[0]); +- rtl_write_byte(rtlpriv, REG_SLOT, val[0]); +- for (e_aci = 0; e_aci < AC_MAX; e_aci++) +- rtlpriv->cfg->ops->set_hw_reg(hw, +- HW_VAR_AC_PARAM, +- (&e_aci)); +- break; +- } +- case HW_VAR_ACK_PREAMBLE: { +- u8 reg_tmp; +- u8 short_preamble = (bool) (*val); +- +- reg_tmp = (mac->cur_40_prime_sc) << 5; +- if (short_preamble) +- reg_tmp |= 0x80; +- rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); +- break; +- } +- case HW_VAR_AMPDU_MIN_SPACE: { +- u8 min_spacing_to_set; +- +- min_spacing_to_set = *val; +- if (min_spacing_to_set <= 7) { +- mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | +- min_spacing_to_set); +- *val = min_spacing_to_set; +- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, +- "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", +- mac->min_space_cfg); +- rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, +- mac->min_space_cfg); +- } +- break; +- } +- case HW_VAR_SHORTGI_DENSITY: { +- u8 density_to_set; +- +- density_to_set = *val; +- mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; +- mac->min_space_cfg |= (density_to_set << 3); +- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, +- "Set HW_VAR_SHORTGI_DENSITY: %#x\n", +- mac->min_space_cfg); +- rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, +- mac->min_space_cfg); +- break; +- } +- case HW_VAR_AMPDU_FACTOR: { +- u8 factor_toset; +- u32 regtoset; +- u8 *ptmp_byte = NULL; +- u8 index; +- +- if (rtlhal->macphymode == DUALMAC_DUALPHY) +- regtoset = 0xb9726641; +- else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) +- regtoset = 0x66626641; +- else +- regtoset = 0xb972a841; +- factor_toset = *val; +- if (factor_toset <= 3) { +- factor_toset = (1 << (factor_toset + 2)); +- if (factor_toset > 0xf) +- factor_toset = 0xf; +- for (index = 0; index < 4; index++) { +- ptmp_byte = (u8 *)(®toset) + index; +- if ((*ptmp_byte & 0xf0) > +- (factor_toset << 4)) +- *ptmp_byte = (*ptmp_byte & 0x0f) +- | (factor_toset << 4); +- if ((*ptmp_byte & 0x0f) > factor_toset) +- *ptmp_byte = (*ptmp_byte & 0xf0) +- | (factor_toset); +- } +- rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset); +- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, +- "Set HW_VAR_AMPDU_FACTOR: %#x\n", +- factor_toset); +- } +- break; +- } + case HW_VAR_AC_PARAM: { + u8 e_aci = *val; + rtl92d_dm_init_edca_turbo(hw); +@@ -346,37 +145,6 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); + rtlpci->receive_config = ((u32 *) (val))[0]; + break; +- case HW_VAR_RETRY_LIMIT: { +- u8 retry_limit = val[0]; +- +- rtl_write_word(rtlpriv, REG_RL, +- retry_limit << RETRY_LIMIT_SHORT_SHIFT | +- retry_limit << RETRY_LIMIT_LONG_SHIFT); +- break; +- } +- case HW_VAR_DUAL_TSF_RST: +- rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); +- break; +- case HW_VAR_EFUSE_BYTES: +- rtlefuse->efuse_usedbytes = *((u16 *) val); +- break; +- case HW_VAR_EFUSE_USAGE: +- rtlefuse->efuse_usedpercentage = *val; +- break; +- case HW_VAR_IO_CMD: +- rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); +- break; +- case HW_VAR_WPA_CONFIG: +- rtl_write_byte(rtlpriv, REG_SECCFG, *val); +- break; +- case HW_VAR_SET_RPWM: +- rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val)); +- break; +- case HW_VAR_H2C_FW_PWRMODE: +- break; +- case HW_VAR_FW_PSMODE_STATUS: +- ppsc->fw_current_inpsmode = *((bool *) val); +- break; + case HW_VAR_H2C_FW_JOINBSSRPT: { + u8 mstatus = (*val); + u8 tmp_regcr, tmp_reg422; +@@ -409,19 +177,11 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + rtl92d_set_fw_joinbss_report_cmd(hw, (*val)); + break; + } +- case HW_VAR_AID: { +- u16 u2btmp; +- u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); +- u2btmp &= 0xC000; +- rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | +- mac->assoc_id)); +- break; +- } + case HW_VAR_CORRECT_TSF: { + u8 btype_ibss = val[0]; + + if (btype_ibss) +- _rtl92de_stop_tx_beacon(hw); ++ rtl92de_stop_tx_beacon(hw); + _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); + rtl_write_dword(rtlpriv, REG_TSFTR, + (u32) (mac->tsf & 0xffffffff)); +@@ -429,7 +189,7 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + (u32) ((mac->tsf >> 32) & 0xffffffff)); + _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); + if (btype_ibss) +- _rtl92de_resume_tx_beacon(hw); ++ rtl92de_resume_tx_beacon(hw); + + break; + } +@@ -472,34 +232,11 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + break; + } + default: +- pr_err("switch case %#x not processed\n", variable); ++ rtl92d_set_hw_reg(hw, variable, val); + break; + } + } + +-static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- bool status = true; +- long count = 0; +- u32 value = _LLT_INIT_ADDR(address) | +- _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); +- +- rtl_write_dword(rtlpriv, REG_LLT_INIT, value); +- do { +- value = rtl_read_dword(rtlpriv, REG_LLT_INIT); +- if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) +- break; +- if (count > POLLING_LLT_THRESHOLD) { +- pr_err("Failed to polling write LLT done at address %d!\n", +- address); +- status = false; +- break; +- } +- } while (++count); +- return status; +-} +- + static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -558,13 +295,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) + + /* 18. LLT_table_init(Adapter); */ + for (i = 0; i < (txpktbuf_bndy - 1); i++) { +- status = _rtl92de_llt_write(hw, i, i + 1); ++ status = rtl92de_llt_write(hw, i, i + 1); + if (!status) + return status; + } + + /* end of list */ +- status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); ++ status = rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); + if (!status) + return status; + +@@ -573,13 +310,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) + /* config this MAC as two MAC transfer. */ + /* Otherwise used as local loopback buffer. */ + for (i = txpktbuf_bndy; i < maxpage; i++) { +- status = _rtl92de_llt_write(hw, i, (i + 1)); ++ status = rtl92de_llt_write(hw, i, (i + 1)); + if (!status) + return status; + } + + /* Let last entry point to the start entry of ring buffer */ +- status = _rtl92de_llt_write(hw, maxpage, txpktbuf_bndy); ++ status = rtl92de_llt_write(hw, maxpage, txpktbuf_bndy); + if (!status) + return status; + +@@ -842,32 +579,6 @@ static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw) + rtl_write_byte(rtlpriv, 0x352, 0x1); + } + +-void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 sec_reg_value; +- +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, +- "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", +- rtlpriv->sec.pairwise_enc_algorithm, +- rtlpriv->sec.group_enc_algorithm); +- if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { +- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, +- "not open hw encryption\n"); +- return; +- } +- sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; +- if (rtlpriv->sec.use_defaultkey) { +- sec_reg_value |= SCR_TXUSEDK; +- sec_reg_value |= SCR_RXUSEDK; +- } +- sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); +- rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); +- rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, +- "The SECR-value %x\n", sec_reg_value); +- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); +-} +- + int rtl92de_hw_init(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -991,11 +702,11 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) + _rtl92de_enable_aspm_back_door(hw); + /* rtlpriv->intf_ops->enable_aspm(hw); */ + +- rtl92d_dm_init(hw); ++ rtl92de_dm_init(hw); + rtlpci->being_init_adapter = false; + + if (ppsc->rfpwr_state == ERFON) { +- rtl92d_phy_lc_calibrate(hw); ++ rtl92d_phy_lc_calibrate(hw, IS_92D_SINGLEPHY(rtlhal->version)); + /* 5G and 2.4G must wait sometime to let RF LO ready */ + if (rtlhal->macphymode == DUALMAC_DUALPHY) { + u32 tmp_rega; +@@ -1020,23 +731,6 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) + return err; + } + +-static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; +- u32 value32; +- +- value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); +- if (!(value32 & 0x000f0000)) { +- version = VERSION_TEST_CHIP_92D_SINGLEPHY; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); +- } else { +- version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); +- } +- return version; +-} +- + static int _rtl92de_set_media_status(struct ieee80211_hw *hw, + enum nl80211_iftype type) + { +@@ -1048,11 +742,11 @@ static int _rtl92de_set_media_status(struct ieee80211_hw *hw, + + if (type == NL80211_IFTYPE_UNSPECIFIED || + type == NL80211_IFTYPE_STATION) { +- _rtl92de_stop_tx_beacon(hw); ++ rtl92de_stop_tx_beacon(hw); + _rtl92de_enable_bcn_sub_func(hw); + } else if (type == NL80211_IFTYPE_ADHOC || + type == NL80211_IFTYPE_AP) { +- _rtl92de_resume_tx_beacon(hw); ++ rtl92de_resume_tx_beacon(hw); + _rtl92de_disable_bcn_sub_func(hw); + } else { + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, +@@ -1152,13 +846,6 @@ void rtl92d_linked_set_reg(struct ieee80211_hw *hw) + } + } + +-/* don't set REG_EDCA_BE_PARAM here because +- * mac80211 will send pkt when scan */ +-void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) +-{ +- rtl92d_dm_init_edca_turbo(hw); +-} +- + void rtl92de_enable_interrupt(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -1383,825 +1070,6 @@ void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw, + rtl92de_enable_interrupt(hw); + } + +-static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, +- u8 *rom_content, bool autoloadfail) +-{ +- u32 rfpath, eeaddr, group, offset1, offset2; +- u8 i; +- +- memset(pwrinfo, 0, sizeof(struct txpower_info)); +- if (autoloadfail) { +- for (group = 0; group < CHANNEL_GROUP_MAX; group++) { +- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { +- if (group < CHANNEL_GROUP_MAX_2G) { +- pwrinfo->cck_index[rfpath][group] = +- EEPROM_DEFAULT_TXPOWERLEVEL_2G; +- pwrinfo->ht40_1sindex[rfpath][group] = +- EEPROM_DEFAULT_TXPOWERLEVEL_2G; +- } else { +- pwrinfo->ht40_1sindex[rfpath][group] = +- EEPROM_DEFAULT_TXPOWERLEVEL_5G; +- } +- pwrinfo->ht40_2sindexdiff[rfpath][group] = +- EEPROM_DEFAULT_HT40_2SDIFF; +- pwrinfo->ht20indexdiff[rfpath][group] = +- EEPROM_DEFAULT_HT20_DIFF; +- pwrinfo->ofdmindexdiff[rfpath][group] = +- EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; +- pwrinfo->ht40maxoffset[rfpath][group] = +- EEPROM_DEFAULT_HT40_PWRMAXOFFSET; +- pwrinfo->ht20maxoffset[rfpath][group] = +- EEPROM_DEFAULT_HT20_PWRMAXOFFSET; +- } +- } +- for (i = 0; i < 3; i++) { +- pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; +- pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; +- } +- return; +- } +- +- /* Maybe autoload OK,buf the tx power index value is not filled. +- * If we find it, we set it to default value. */ +- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { +- for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { +- eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) +- + group; +- pwrinfo->cck_index[rfpath][group] = +- (rom_content[eeaddr] == 0xFF) ? +- (eeaddr > 0x7B ? +- EEPROM_DEFAULT_TXPOWERLEVEL_5G : +- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : +- rom_content[eeaddr]; +- } +- } +- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { +- for (group = 0; group < CHANNEL_GROUP_MAX; group++) { +- offset1 = group / 3; +- offset2 = group % 3; +- eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + +- offset2 + offset1 * 21; +- pwrinfo->ht40_1sindex[rfpath][group] = +- (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? +- EEPROM_DEFAULT_TXPOWERLEVEL_5G : +- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : +- rom_content[eeaddr]; +- } +- } +- /* These just for 92D efuse offset. */ +- for (group = 0; group < CHANNEL_GROUP_MAX; group++) { +- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { +- int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; +- +- offset1 = group / 3; +- offset2 = group % 3; +- +- if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) +- pwrinfo->ht40_2sindexdiff[rfpath][group] = +- (rom_content[base1 + +- offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; +- else +- pwrinfo->ht40_2sindexdiff[rfpath][group] = +- EEPROM_DEFAULT_HT40_2SDIFF; +- if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 +- + offset1 * 21] != 0xFF) +- pwrinfo->ht20indexdiff[rfpath][group] = +- (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G +- + offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; +- else +- pwrinfo->ht20indexdiff[rfpath][group] = +- EEPROM_DEFAULT_HT20_DIFF; +- if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 +- + offset1 * 21] != 0xFF) +- pwrinfo->ofdmindexdiff[rfpath][group] = +- (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G +- + offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; +- else +- pwrinfo->ofdmindexdiff[rfpath][group] = +- EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; +- if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 +- + offset1 * 21] != 0xFF) +- pwrinfo->ht40maxoffset[rfpath][group] = +- (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G +- + offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; +- else +- pwrinfo->ht40maxoffset[rfpath][group] = +- EEPROM_DEFAULT_HT40_PWRMAXOFFSET; +- if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 +- + offset1 * 21] != 0xFF) +- pwrinfo->ht20maxoffset[rfpath][group] = +- (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + +- offset2 + offset1 * 21] >> (rfpath * 4)) & +- 0xF; +- else +- pwrinfo->ht20maxoffset[rfpath][group] = +- EEPROM_DEFAULT_HT20_PWRMAXOFFSET; +- } +- } +- if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { +- /* 5GL */ +- pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; +- pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; +- /* 5GM */ +- pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; +- pwrinfo->tssi_b[1] = +- (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | +- (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; +- /* 5GH */ +- pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & +- 0xF0) >> 4 | +- (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; +- pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & +- 0xFC) >> 2; +- } else { +- for (i = 0; i < 3; i++) { +- pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; +- pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; +- } +- } +-} +- +-static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, +- bool autoload_fail, u8 *hwinfo) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- struct txpower_info pwrinfo; +- u8 tempval[2], i, pwr, diff; +- u32 ch, rfpath, group; +- +- _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); +- if (!autoload_fail) { +- /* bit0~2 */ +- rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); +- rtlefuse->eeprom_thermalmeter = +- hwinfo[EEPROM_THERMAL_METER] & 0x1f; +- rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K]; +- tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; +- tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; +- rtlefuse->txpwr_fromeprom = true; +- if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || +- IS_92D_E_CUT(rtlpriv->rtlhal.version)) { +- rtlefuse->internal_pa_5g[0] = +- !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); +- rtlefuse->internal_pa_5g[1] = +- !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); +- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, +- "Is D cut,Internal PA0 %d Internal PA1 %d\n", +- rtlefuse->internal_pa_5g[0], +- rtlefuse->internal_pa_5g[1]); +- } +- rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6]; +- rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7]; +- } else { +- rtlefuse->eeprom_regulatory = 0; +- rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; +- rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP; +- tempval[0] = tempval[1] = 3; +- } +- +- /* Use default value to fill parameters if +- * efuse is not filled on some place. */ +- +- /* ThermalMeter from EEPROM */ +- if (rtlefuse->eeprom_thermalmeter < 0x06 || +- rtlefuse->eeprom_thermalmeter > 0x1c) +- rtlefuse->eeprom_thermalmeter = 0x12; +- rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; +- +- /* check XTAL_K */ +- if (rtlefuse->crystalcap == 0xFF) +- rtlefuse->crystalcap = 0; +- if (rtlefuse->eeprom_regulatory > 3) +- rtlefuse->eeprom_regulatory = 0; +- +- for (i = 0; i < 2; i++) { +- switch (tempval[i]) { +- case 0: +- tempval[i] = 5; +- break; +- case 1: +- tempval[i] = 4; +- break; +- case 2: +- tempval[i] = 3; +- break; +- case 3: +- default: +- tempval[i] = 0; +- break; +- } +- } +- +- rtlefuse->delta_iqk = tempval[0]; +- if (tempval[1] > 0) +- rtlefuse->delta_lck = tempval[1] - 1; +- if (rtlefuse->eeprom_c9 == 0xFF) +- rtlefuse->eeprom_c9 = 0x00; +- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, +- "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory); +- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, +- "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); +- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, +- "CrystalCap = 0x%x\n", rtlefuse->crystalcap); +- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, +- "Delta_IQK = 0x%x Delta_LCK = 0x%x\n", +- rtlefuse->delta_iqk, rtlefuse->delta_lck); +- +- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { +- for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { +- group = rtl92d_get_chnlgroup_fromarray((u8) ch); +- if (ch < CHANNEL_MAX_NUMBER_2G) +- rtlefuse->txpwrlevel_cck[rfpath][ch] = +- pwrinfo.cck_index[rfpath][group]; +- rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] = +- pwrinfo.ht40_1sindex[rfpath][group]; +- rtlefuse->txpwr_ht20diff[rfpath][ch] = +- pwrinfo.ht20indexdiff[rfpath][group]; +- rtlefuse->txpwr_legacyhtdiff[rfpath][ch] = +- pwrinfo.ofdmindexdiff[rfpath][group]; +- rtlefuse->pwrgroup_ht20[rfpath][ch] = +- pwrinfo.ht20maxoffset[rfpath][group]; +- rtlefuse->pwrgroup_ht40[rfpath][ch] = +- pwrinfo.ht40maxoffset[rfpath][group]; +- pwr = pwrinfo.ht40_1sindex[rfpath][group]; +- diff = pwrinfo.ht40_2sindexdiff[rfpath][group]; +- rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] = +- (pwr > diff) ? (pwr - diff) : 0; +- } +- } +-} +- +-static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, +- u8 *content) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; +- +- if (macphy_crvalue & BIT(3)) { +- rtlhal->macphymode = SINGLEMAC_SINGLEPHY; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, +- "MacPhyMode SINGLEMAC_SINGLEPHY\n"); +- } else { +- rtlhal->macphymode = DUALMAC_DUALPHY; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, +- "MacPhyMode DUALMAC_DUALPHY\n"); +- } +-} +- +-static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, +- u8 *content) +-{ +- _rtl92de_read_macphymode_from_prom(hw, content); +- rtl92d_phy_config_macphymode(hw); +- rtl92d_phy_config_macphymode_info(hw); +-} +- +-static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- enum version_8192d chipver = rtlpriv->rtlhal.version; +- u8 cutvalue[2]; +- u16 chipvalue; +- +- read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, &cutvalue[1]); +- read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, &cutvalue[0]); +- chipvalue = (cutvalue[1] << 8) | cutvalue[0]; +- switch (chipvalue) { +- case 0xAA55: +- chipver |= CHIP_92D_C_CUT; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); +- break; +- case 0x9966: +- chipver |= CHIP_92D_D_CUT; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); +- break; +- case 0xCC33: +- chipver |= CHIP_92D_E_CUT; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); +- break; +- default: +- chipver |= CHIP_92D_D_CUT; +- pr_err("Unknown CUT!\n"); +- break; +- } +- rtlpriv->rtlhal.version = chipver; +-} +- +-static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, +- EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, +- EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, +- COUNTRY_CODE_WORLD_WIDE_13}; +- int i; +- u16 usvalue; +- u8 *hwinfo; +- +- hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); +- if (!hwinfo) +- return; +- +- if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) +- goto exit; +- +- _rtl92de_efuse_update_chip_version(hw); +- _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); +- +- /* Read Permanent MAC address for 2nd interface */ +- if (rtlhal->interfaceindex != 0) { +- for (i = 0; i < 6; i += 2) { +- usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; +- *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; +- } +- } +- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, +- rtlefuse->dev_addr); +- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); +- _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); +- +- /* Read Channel Plan */ +- switch (rtlhal->bandset) { +- case BAND_ON_2_4G: +- rtlefuse->channel_plan = COUNTRY_CODE_TELEC; +- break; +- case BAND_ON_5G: +- rtlefuse->channel_plan = COUNTRY_CODE_FCC; +- break; +- case BAND_ON_BOTH: +- rtlefuse->channel_plan = COUNTRY_CODE_FCC; +- break; +- default: +- rtlefuse->channel_plan = COUNTRY_CODE_FCC; +- break; +- } +- rtlefuse->txpwr_fromeprom = true; +-exit: +- kfree(hwinfo); +-} +- +-void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u8 tmp_u1b; +- +- rtlhal->version = _rtl92de_read_chip_version(hw); +- tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); +- rtlefuse->autoload_status = tmp_u1b; +- if (tmp_u1b & BIT(4)) { +- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); +- rtlefuse->epromtype = EEPROM_93C46; +- } else { +- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); +- rtlefuse->epromtype = EEPROM_BOOT_EFUSE; +- } +- if (tmp_u1b & BIT(5)) { +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); +- +- rtlefuse->autoload_failflag = false; +- _rtl92de_read_adapter_info(hw); +- } else { +- pr_err("Autoload ERR!!\n"); +- } +- return; +-} +- +-static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u32 ratr_value; +- u8 ratr_index = 0; +- u8 nmode = mac->ht_enable; +- u8 mimo_ps = IEEE80211_SMPS_OFF; +- u16 shortgi_rate; +- u32 tmp_ratr_value; +- u8 curtxbw_40mhz = mac->bw_40; +- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? +- 1 : 0; +- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? +- 1 : 0; +- enum wireless_mode wirelessmode = mac->mode; +- +- if (rtlhal->current_bandtype == BAND_ON_5G) +- ratr_value = sta->deflink.supp_rates[1] << 4; +- else +- ratr_value = sta->deflink.supp_rates[0]; +- ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | +- sta->deflink.ht_cap.mcs.rx_mask[0] << 12); +- switch (wirelessmode) { +- case WIRELESS_MODE_A: +- ratr_value &= 0x00000FF0; +- break; +- case WIRELESS_MODE_B: +- if (ratr_value & 0x0000000c) +- ratr_value &= 0x0000000d; +- else +- ratr_value &= 0x0000000f; +- break; +- case WIRELESS_MODE_G: +- ratr_value &= 0x00000FF5; +- break; +- case WIRELESS_MODE_N_24G: +- case WIRELESS_MODE_N_5G: +- nmode = 1; +- if (mimo_ps == IEEE80211_SMPS_STATIC) { +- ratr_value &= 0x0007F005; +- } else { +- u32 ratr_mask; +- +- if (get_rf_type(rtlphy) == RF_1T2R || +- get_rf_type(rtlphy) == RF_1T1R) { +- ratr_mask = 0x000ff005; +- } else { +- ratr_mask = 0x0f0ff005; +- } +- +- ratr_value &= ratr_mask; +- } +- break; +- default: +- if (rtlphy->rf_type == RF_1T2R) +- ratr_value &= 0x000ff0ff; +- else +- ratr_value &= 0x0f0ff0ff; +- +- break; +- } +- ratr_value &= 0x0FFFFFFF; +- if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || +- (!curtxbw_40mhz && curshortgi_20mhz))) { +- ratr_value |= 0x10000000; +- tmp_ratr_value = (ratr_value >> 12); +- for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { +- if ((1 << shortgi_rate) & tmp_ratr_value) +- break; +- } +- shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | +- (shortgi_rate << 4) | (shortgi_rate); +- } +- rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); +- rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", +- rtl_read_dword(rtlpriv, REG_ARFR0)); +-} +- +-static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- struct rtl_sta_info *sta_entry = NULL; +- u32 ratr_bitmap; +- u8 ratr_index; +- u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; +- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? +- 1 : 0; +- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? +- 1 : 0; +- enum wireless_mode wirelessmode = 0; +- bool shortgi = false; +- u32 value[2]; +- u8 macid = 0; +- u8 mimo_ps = IEEE80211_SMPS_OFF; +- +- sta_entry = (struct rtl_sta_info *) sta->drv_priv; +- mimo_ps = sta_entry->mimo_ps; +- wirelessmode = sta_entry->wireless_mode; +- if (mac->opmode == NL80211_IFTYPE_STATION) +- curtxbw_40mhz = mac->bw_40; +- else if (mac->opmode == NL80211_IFTYPE_AP || +- mac->opmode == NL80211_IFTYPE_ADHOC) +- macid = sta->aid + 1; +- +- if (rtlhal->current_bandtype == BAND_ON_5G) +- ratr_bitmap = sta->deflink.supp_rates[1] << 4; +- else +- ratr_bitmap = sta->deflink.supp_rates[0]; +- ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | +- sta->deflink.ht_cap.mcs.rx_mask[0] << 12); +- switch (wirelessmode) { +- case WIRELESS_MODE_B: +- ratr_index = RATR_INX_WIRELESS_B; +- if (ratr_bitmap & 0x0000000c) +- ratr_bitmap &= 0x0000000d; +- else +- ratr_bitmap &= 0x0000000f; +- break; +- case WIRELESS_MODE_G: +- ratr_index = RATR_INX_WIRELESS_GB; +- +- if (rssi_level == 1) +- ratr_bitmap &= 0x00000f00; +- else if (rssi_level == 2) +- ratr_bitmap &= 0x00000ff0; +- else +- ratr_bitmap &= 0x00000ff5; +- break; +- case WIRELESS_MODE_A: +- ratr_index = RATR_INX_WIRELESS_G; +- ratr_bitmap &= 0x00000ff0; +- break; +- case WIRELESS_MODE_N_24G: +- case WIRELESS_MODE_N_5G: +- if (wirelessmode == WIRELESS_MODE_N_24G) +- ratr_index = RATR_INX_WIRELESS_NGB; +- else +- ratr_index = RATR_INX_WIRELESS_NG; +- if (mimo_ps == IEEE80211_SMPS_STATIC) { +- if (rssi_level == 1) +- ratr_bitmap &= 0x00070000; +- else if (rssi_level == 2) +- ratr_bitmap &= 0x0007f000; +- else +- ratr_bitmap &= 0x0007f005; +- } else { +- if (rtlphy->rf_type == RF_1T2R || +- rtlphy->rf_type == RF_1T1R) { +- if (curtxbw_40mhz) { +- if (rssi_level == 1) +- ratr_bitmap &= 0x000f0000; +- else if (rssi_level == 2) +- ratr_bitmap &= 0x000ff000; +- else +- ratr_bitmap &= 0x000ff015; +- } else { +- if (rssi_level == 1) +- ratr_bitmap &= 0x000f0000; +- else if (rssi_level == 2) +- ratr_bitmap &= 0x000ff000; +- else +- ratr_bitmap &= 0x000ff005; +- } +- } else { +- if (curtxbw_40mhz) { +- if (rssi_level == 1) +- ratr_bitmap &= 0x0f0f0000; +- else if (rssi_level == 2) +- ratr_bitmap &= 0x0f0ff000; +- else +- ratr_bitmap &= 0x0f0ff015; +- } else { +- if (rssi_level == 1) +- ratr_bitmap &= 0x0f0f0000; +- else if (rssi_level == 2) +- ratr_bitmap &= 0x0f0ff000; +- else +- ratr_bitmap &= 0x0f0ff005; +- } +- } +- } +- if ((curtxbw_40mhz && curshortgi_40mhz) || +- (!curtxbw_40mhz && curshortgi_20mhz)) { +- +- if (macid == 0) +- shortgi = true; +- else if (macid == 1) +- shortgi = false; +- } +- break; +- default: +- ratr_index = RATR_INX_WIRELESS_NGB; +- +- if (rtlphy->rf_type == RF_1T2R) +- ratr_bitmap &= 0x000ff0ff; +- else +- ratr_bitmap &= 0x0f0ff0ff; +- break; +- } +- +- value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); +- value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; +- rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, +- "ratr_bitmap :%x value0:%x value1:%x\n", +- ratr_bitmap, value[0], value[1]); +- rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value); +- if (macid != 0) +- sta_entry->ratr_index = ratr_index; +-} +- +-void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- +- if (rtlpriv->dm.useramask) +- rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw); +- else +- rtl92de_update_hal_rate_table(hw, sta); +-} +- +-void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- u16 sifs_timer; +- +- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, +- &mac->slot_time); +- if (!mac->ht_enable) +- sifs_timer = 0x0a0a; +- else +- sifs_timer = 0x1010; +- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); +-} +- +-bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); +- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); +- enum rf_pwrstate e_rfpowerstate_toset; +- u8 u1tmp; +- bool actuallyset = false; +- unsigned long flag; +- +- if (rtlpci->being_init_adapter) +- return false; +- if (ppsc->swrf_processing) +- return false; +- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); +- if (ppsc->rfchange_inprogress) { +- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); +- return false; +- } else { +- ppsc->rfchange_inprogress = true; +- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); +- } +- rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, +- REG_MAC_PINMUX_CFG) & ~(BIT(3))); +- u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); +- e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; +- if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { +- rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, +- "GPIOChangeRF - HW Radio ON, RF ON\n"); +- e_rfpowerstate_toset = ERFON; +- ppsc->hwradiooff = false; +- actuallyset = true; +- } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { +- rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, +- "GPIOChangeRF - HW Radio OFF, RF OFF\n"); +- e_rfpowerstate_toset = ERFOFF; +- ppsc->hwradiooff = true; +- actuallyset = true; +- } +- if (actuallyset) { +- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); +- ppsc->rfchange_inprogress = false; +- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); +- } else { +- if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) +- RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); +- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); +- ppsc->rfchange_inprogress = false; +- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); +- } +- *valid = 1; +- return !ppsc->hwradiooff; +-} +- +-void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, +- u8 *p_macaddr, bool is_group, u8 enc_algo, +- bool is_wepkey, bool clear_all) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- u8 *macaddr = p_macaddr; +- u32 entry_id; +- bool is_pairwise = false; +- static u8 cam_const_addr[4][6] = { +- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, +- {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, +- {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, +- {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} +- }; +- static u8 cam_const_broad[] = { +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +- }; +- +- if (clear_all) { +- u8 idx; +- u8 cam_offset = 0; +- u8 clear_number = 5; +- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); +- for (idx = 0; idx < clear_number; idx++) { +- rtl_cam_mark_invalid(hw, cam_offset + idx); +- rtl_cam_empty_entry(hw, cam_offset + idx); +- +- if (idx < 5) { +- memset(rtlpriv->sec.key_buf[idx], 0, +- MAX_KEY_LEN); +- rtlpriv->sec.key_len[idx] = 0; +- } +- } +- } else { +- switch (enc_algo) { +- case WEP40_ENCRYPTION: +- enc_algo = CAM_WEP40; +- break; +- case WEP104_ENCRYPTION: +- enc_algo = CAM_WEP104; +- break; +- case TKIP_ENCRYPTION: +- enc_algo = CAM_TKIP; +- break; +- case AESCCMP_ENCRYPTION: +- enc_algo = CAM_AES; +- break; +- default: +- pr_err("switch case %#x not processed\n", +- enc_algo); +- enc_algo = CAM_TKIP; +- break; +- } +- if (is_wepkey || rtlpriv->sec.use_defaultkey) { +- macaddr = cam_const_addr[key_index]; +- entry_id = key_index; +- } else { +- if (is_group) { +- macaddr = cam_const_broad; +- entry_id = key_index; +- } else { +- if (mac->opmode == NL80211_IFTYPE_AP) { +- entry_id = rtl_cam_get_free_entry(hw, +- p_macaddr); +- if (entry_id >= TOTAL_CAM_ENTRY) { +- pr_err("Can not find free hw security cam entry\n"); +- return; +- } +- } else { +- entry_id = CAM_PAIRWISE_KEY_POSITION; +- } +- key_index = PAIRWISE_KEYIDX; +- is_pairwise = true; +- } +- } +- if (rtlpriv->sec.key_len[key_index] == 0) { +- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, +- "delete one entry, entry_id is %d\n", +- entry_id); +- if (mac->opmode == NL80211_IFTYPE_AP) +- rtl_cam_del_entry(hw, p_macaddr); +- rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); +- } else { +- rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, +- "The insert KEY length is %d\n", +- rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); +- rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, +- "The insert KEY is %x %x\n", +- rtlpriv->sec.key_buf[0][0], +- rtlpriv->sec.key_buf[0][1]); +- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, +- "add one entry\n"); +- if (is_pairwise) { +- RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, +- "Pairwise Key content", +- rtlpriv->sec.pairwise_key, +- rtlpriv-> +- sec.key_len[PAIRWISE_KEYIDX]); +- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, +- "set Pairwise key\n"); +- rtl_cam_add_one_entry(hw, macaddr, key_index, +- entry_id, enc_algo, +- CAM_CONFIG_NO_USEDK, +- rtlpriv-> +- sec.key_buf[key_index]); +- } else { +- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, +- "set group key\n"); +- if (mac->opmode == NL80211_IFTYPE_ADHOC) { +- rtl_cam_add_one_entry(hw, +- rtlefuse->dev_addr, +- PAIRWISE_KEYIDX, +- CAM_PAIRWISE_KEY_POSITION, +- enc_algo, CAM_CONFIG_NO_USEDK, +- rtlpriv->sec.key_buf[entry_id]); +- } +- rtl_cam_add_one_entry(hw, macaddr, key_index, +- entry_id, enc_algo, +- CAM_CONFIG_NO_USEDK, +- rtlpriv->sec.key_buf +- [entry_id]); +- } +- } +- } +-} +- + void rtl92de_suspend(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h +index ea495216d394..bda4a1a7c91d 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h +@@ -5,7 +5,6 @@ + #define __RTL92DE_HW_H__ + + void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); +-void rtl92de_read_eeprom_info(struct ieee80211_hw *hw); + void rtl92de_interrupt_recognized(struct ieee80211_hw *hw, + struct rtl_int *int_vec); + int rtl92de_hw_init(struct ieee80211_hw *hw); +@@ -14,21 +13,11 @@ void rtl92de_enable_interrupt(struct ieee80211_hw *hw); + void rtl92de_disable_interrupt(struct ieee80211_hw *hw); + int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type); + void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid); +-void rtl92de_set_qos(struct ieee80211_hw *hw, int aci); + void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw); + void rtl92de_set_beacon_interval(struct ieee80211_hw *hw); + void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw, + u32 add_msr, u32 rm_msr); + void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); +-void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta, u8 rssi_level, +- bool update_bw); +-void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw); +-bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); +-void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw); +-void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, +- u8 *p_macaddr, bool is_group, u8 enc_algo, +- bool is_wepkey, bool clear_all); + + void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, u16 offset, u32 value, + u8 direct); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c +index 4bd708570992..33aede56c81b 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c +@@ -3,7 +3,7 @@ + + #include "../wifi.h" + #include "../pci.h" +-#include "reg.h" ++#include "../rtl8192d/reg.h" + #include "led.h" + + void rtl92de_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin) +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +index 56b5cd032a9a..d429560009bb 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +@@ -5,8 +5,11 @@ + #include "../pci.h" + #include "../ps.h" + #include "../core.h" +-#include "reg.h" +-#include "def.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/dm_common.h" ++#include "../rtl8192d/phy_common.h" ++#include "../rtl8192d/rf_common.h" + #include "phy.h" + #include "rf.h" + #include "dm.h" +@@ -21,9 +24,6 @@ + #define RF_REG_NUM_FOR_C_CUT_2G 5 + #define RF_CHNL_NUM_5G 19 + #define RF_CHNL_NUM_5G_40M 17 +-#define TARGET_CHNL_NUM_5G 221 +-#define TARGET_CHNL_NUM_2G 14 +-#define CV_CURVE_CNT 64 + + static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { + 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 +@@ -160,15 +160,6 @@ static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { + 25711, 25658, 25606, 25554, 25502, 25451, 25328 + }; + +-static const u8 channel_all[59] = { +- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, +- 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, +- 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, +- 114, 116, 118, 120, 122, 124, 126, 128, 130, +- 132, 134, 136, 138, 140, 149, 151, 153, 155, +- 157, 159, 161, 163, 165 +-}; +- + u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -235,119 +226,6 @@ void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, + regaddr, bitmask, data); + } + +-static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, +- enum radio_path rfpath, u32 offset) +-{ +- +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; +- u32 newoffset; +- u32 tmplong, tmplong2; +- u8 rfpi_enable = 0; +- u32 retvalue; +- +- newoffset = offset; +- tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); +- if (rfpath == RF90_PATH_A) +- tmplong2 = tmplong; +- else +- tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); +- tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | +- (newoffset << 23) | BLSSIREADEDGE; +- rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, +- tmplong & (~BLSSIREADEDGE)); +- udelay(10); +- rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); +- udelay(50); +- udelay(50); +- rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, +- tmplong | BLSSIREADEDGE); +- udelay(10); +- if (rfpath == RF90_PATH_A) +- rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, +- BIT(8)); +- else if (rfpath == RF90_PATH_B) +- rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, +- BIT(8)); +- if (rfpi_enable) +- retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, +- BLSSIREADBACKDATA); +- else +- retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, +- BLSSIREADBACKDATA); +- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", +- rfpath, pphyreg->rf_rb, retvalue); +- return retvalue; +-} +- +-static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, +- enum radio_path rfpath, +- u32 offset, u32 data) +-{ +- u32 data_and_addr; +- u32 newoffset; +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; +- +- newoffset = offset; +- /* T65 RF */ +- data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; +- rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); +- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", +- rfpath, pphyreg->rf3wire_offset, data_and_addr); +-} +- +-u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, +- enum radio_path rfpath, u32 regaddr, u32 bitmask) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 original_value, readback_value, bitshift; +- +- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, +- "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", +- regaddr, rfpath, bitmask); +- spin_lock(&rtlpriv->locks.rf_lock); +- original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); +- bitshift = calculate_bit_shift(bitmask); +- readback_value = (original_value & bitmask) >> bitshift; +- spin_unlock(&rtlpriv->locks.rf_lock); +- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, +- "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", +- regaddr, rfpath, bitmask, original_value); +- return readback_value; +-} +- +-void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, +- u32 regaddr, u32 bitmask, u32 data) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- u32 original_value, bitshift; +- +- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, +- "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", +- regaddr, bitmask, data, rfpath); +- if (bitmask == 0) +- return; +- spin_lock(&rtlpriv->locks.rf_lock); +- if (rtlphy->rf_mode != RF_OP_BY_FW) { +- if (bitmask != RFREG_OFFSET_MASK) { +- original_value = _rtl92d_phy_rf_serial_read(hw, +- rfpath, regaddr); +- bitshift = calculate_bit_shift(bitmask); +- data = ((original_value & (~bitmask)) | +- (data << bitshift)); +- } +- _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); +- } +- spin_unlock(&rtlpriv->locks.rf_lock); +- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, +- "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", +- regaddr, bitmask, data, rfpath); +-} +- + bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -374,133 +252,6 @@ bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) + return true; + } + +-static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- +- /* RF Interface Sowrtware Control */ +- /* 16 LSBs if read 32-bit from 0x870 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; +- /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ +- rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; +- /* 16 LSBs if read 32-bit from 0x874 */ +- rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; +- /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ +- +- rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; +- /* RF Interface Readback Value */ +- /* 16 LSBs if read 32-bit from 0x8E0 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; +- /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ +- rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; +- /* 16 LSBs if read 32-bit from 0x8E4 */ +- rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; +- /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ +- rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; +- +- /* RF Interface Output (and Enable) */ +- /* 16 LSBs if read 32-bit from 0x860 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; +- /* 16 LSBs if read 32-bit from 0x864 */ +- rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; +- +- /* RF Interface (Output and) Enable */ +- /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ +- rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; +- /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ +- rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; +- +- /* Addr of LSSI. Wirte RF register by driver */ +- /* LSSI Parameter */ +- rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = +- RFPGA0_XA_LSSIPARAMETER; +- rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = +- RFPGA0_XB_LSSIPARAMETER; +- +- /* RF parameter */ +- /* BB Band Select */ +- rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; +- rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; +- rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; +- rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; +- +- /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ +- /* Tx gain stage */ +- rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; +- /* Tx gain stage */ +- rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; +- /* Tx gain stage */ +- rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; +- /* Tx gain stage */ +- rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; +- +- /* Tranceiver A~D HSSI Parameter-1 */ +- /* wire control parameter1 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; +- /* wire control parameter1 */ +- rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; +- +- /* Tranceiver A~D HSSI Parameter-2 */ +- /* wire control parameter2 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; +- /* wire control parameter2 */ +- rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; +- +- /* RF switch Control */ +- /* TR/Ant switch control */ +- rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; +- rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; +- rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; +- rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; +- +- /* AGC control 1 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; +- rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; +- rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; +- rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; +- +- /* AGC control 2 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; +- rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; +- rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; +- rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; +- +- /* RX AFE control 1 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; +- rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; +- rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; +- rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; +- +- /*RX AFE control 1 */ +- rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; +- rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; +- rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; +- rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; +- +- /* Tx AFE control 1 */ +- rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; +- rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; +- rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; +- rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; +- +- /* Tx AFE control 2 */ +- rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; +- rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; +- rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; +- rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; +- +- /* Tranceiver LSSI Readback SI mode */ +- rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; +- rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; +- rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; +- rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; +- +- /* Tranceiver LSSI Readback PI mode */ +- rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; +- rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; +-} +- + static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, + u8 configtype) + { +@@ -601,58 +352,6 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, + return true; + } + +-static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, +- u32 regaddr, u32 bitmask, +- u32 data) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- int index; +- +- if (regaddr == RTXAGC_A_RATE18_06) +- index = 0; +- else if (regaddr == RTXAGC_A_RATE54_24) +- index = 1; +- else if (regaddr == RTXAGC_A_CCK1_MCS32) +- index = 6; +- else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) +- index = 7; +- else if (regaddr == RTXAGC_A_MCS03_MCS00) +- index = 2; +- else if (regaddr == RTXAGC_A_MCS07_MCS04) +- index = 3; +- else if (regaddr == RTXAGC_A_MCS11_MCS08) +- index = 4; +- else if (regaddr == RTXAGC_A_MCS15_MCS12) +- index = 5; +- else if (regaddr == RTXAGC_B_RATE18_06) +- index = 8; +- else if (regaddr == RTXAGC_B_RATE54_24) +- index = 9; +- else if (regaddr == RTXAGC_B_CCK1_55_MCS32) +- index = 14; +- else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) +- index = 15; +- else if (regaddr == RTXAGC_B_MCS03_MCS00) +- index = 10; +- else if (regaddr == RTXAGC_B_MCS07_MCS04) +- index = 11; +- else if (regaddr == RTXAGC_B_MCS11_MCS08) +- index = 12; +- else if (regaddr == RTXAGC_B_MCS15_MCS12) +- index = 13; +- else +- return; +- +- rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; +- rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, +- "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", +- rtlphy->pwrgroup_cnt, index, +- rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); +- if (index == 13) +- rtlphy->pwrgroup_cnt++; +-} +- + static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, + u8 configtype) + { +@@ -666,7 +365,7 @@ static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, + if (configtype == BASEBAND_CONFIG_PHY_REG) { + for (i = 0; i < phy_regarray_pg_len; i = i + 3) { + rtl_addr_delay(phy_regarray_table_pg[i]); +- _rtl92d_store_pwrindex_diffrate_offset(hw, ++ rtl92d_store_pwrindex_diffrate_offset(hw, + phy_regarray_table_pg[i], + phy_regarray_table_pg[i + 1], + phy_regarray_table_pg[i + 2]); +@@ -726,7 +425,7 @@ bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) + u32 regvaldw; + u8 value; + +- _rtl92d_phy_init_bb_rf_register_definition(hw); ++ rtl92d_phy_init_bb_rf_register_definition(hw); + regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); + rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, + regval | BIT(13) | BIT(0) | BIT(1)); +@@ -812,115 +511,6 @@ bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, + return true; + } + +-void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- +- rtlphy->default_initialgain[0] = +- (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); +- rtlphy->default_initialgain[1] = +- (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); +- rtlphy->default_initialgain[2] = +- (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); +- rtlphy->default_initialgain[3] = +- (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); +- rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, +- "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", +- rtlphy->default_initialgain[0], +- rtlphy->default_initialgain[1], +- rtlphy->default_initialgain[2], +- rtlphy->default_initialgain[3]); +- rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, +- MASKBYTE0); +- rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, +- MASKDWORD); +- rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, +- "Default framesync (0x%x) = 0x%x\n", +- ROFDM0_RXDETECTOR3, rtlphy->framesync); +-} +- +-static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, +- u8 *cckpowerlevel, u8 *ofdmpowerlevel) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- u8 index = (channel - 1); +- +- /* 1. CCK */ +- if (rtlhal->current_bandtype == BAND_ON_2_4G) { +- /* RF-A */ +- cckpowerlevel[RF90_PATH_A] = +- rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; +- /* RF-B */ +- cckpowerlevel[RF90_PATH_B] = +- rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; +- } else { +- cckpowerlevel[RF90_PATH_A] = 0; +- cckpowerlevel[RF90_PATH_B] = 0; +- } +- /* 2. OFDM for 1S or 2S */ +- if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { +- /* Read HT 40 OFDM TX power */ +- ofdmpowerlevel[RF90_PATH_A] = +- rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; +- ofdmpowerlevel[RF90_PATH_B] = +- rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; +- } else if (rtlphy->rf_type == RF_2T2R) { +- /* Read HT 40 OFDM TX power */ +- ofdmpowerlevel[RF90_PATH_A] = +- rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; +- ofdmpowerlevel[RF90_PATH_B] = +- rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; +- } +-} +- +-static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, +- u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- +- rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; +- rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; +-} +- +-static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) +-{ +- u8 place = chnl; +- +- if (chnl > 14) { +- for (place = 14; place < ARRAY_SIZE(channel_all); place++) { +- if (channel_all[place] == chnl) { +- place++; +- break; +- } +- } +- } +- return place; +-} +- +-void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) +-{ +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u8 cckpowerlevel[2], ofdmpowerlevel[2]; +- +- if (!rtlefuse->txpwr_fromeprom) +- return; +- channel = _rtl92c_phy_get_rightchnlplace(channel); +- _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], +- &ofdmpowerlevel[0]); +- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) +- _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], +- &ofdmpowerlevel[0]); +- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) +- rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); +- rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); +-} +- + void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, + enum nl80211_channel_type ch_type) + { +@@ -1122,65 +712,6 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); + } + +-static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, +- u8 rfpath, u32 *pu4_regval) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; +- +- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); +- /*----Store original RFENV control type----*/ +- switch (rfpath) { +- case RF90_PATH_A: +- case RF90_PATH_C: +- *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); +- break; +- case RF90_PATH_B: +- case RF90_PATH_D: +- *pu4_regval = +- rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); +- break; +- } +- /*----Set RF_ENV enable----*/ +- rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); +- udelay(1); +- /*----Set RF_ENV output high----*/ +- rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); +- udelay(1); +- /* Set bit number of Address and Data for RF register */ +- /* Set 1 to 4 bits for 8255 */ +- rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); +- udelay(1); +- /*Set 0 to 12 bits for 8255 */ +- rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); +- udelay(1); +- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); +-} +- +-static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, +- u32 *pu4_regval) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; +- +- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); +- /*----Restore RFENV control type----*/ +- switch (rfpath) { +- case RF90_PATH_A: +- case RF90_PATH_C: +- rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); +- break; +- case RF90_PATH_B: +- case RF90_PATH_D: +- rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, +- *pu4_regval); +- break; +- } +- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); +-} +- + static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -1221,8 +752,8 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) + rtlhal->during_mac1init_radioa = true; + /* asume no this case */ + if (need_pwr_down) +- _rtl92d_phy_enable_rf_env(hw, path, +- &u4regvalue); ++ rtl92d_phy_enable_rf_env(hw, path, ++ &u4regvalue); + } + for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { + if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { +@@ -1253,7 +784,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) + RFREG_OFFSET_MASK)); + } + if (need_pwr_down) +- _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); ++ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); + if (rtlhal->during_mac1init_radioa) + rtl92d_phy_powerdown_anotherphy(hw, false); + if (channel < 149) +@@ -1313,8 +844,8 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) + rtlhal->during_mac0init_radiob = true; + + if (need_pwr_down) +- _rtl92d_phy_enable_rf_env(hw, path, +- &u4regvalue); ++ rtl92d_phy_enable_rf_env(hw, path, ++ &u4regvalue); + } + } + for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { +@@ -1347,31 +878,13 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) + RFREG_OFFSET_MASK, + rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); + if (need_pwr_down) +- _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); ++ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); + if (rtlhal->during_mac0init_radiob) + rtl92d_phy_powerdown_anotherphy(hw, true); + } + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); + } + +-u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) +-{ +- u8 place; +- +- if (chnl > 14) { +- for (place = 14; place < ARRAY_SIZE(channel_all); place++) { +- if (channel_all[place] == chnl) +- return place - 13; +- } +- } +- +- return 0; +-} +- +-#define MAX_TOLERANCE 5 +-#define IQK_DELAY_TIME 1 /* ms */ +-#define MAX_TOLERANCE_92D 3 +- + /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ + static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) + { +@@ -1636,30 +1149,6 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) + return result; + } + +-static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, +- u32 *adda_reg, u32 *adda_backup, +- u32 regnum) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 i; +- +- RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); +- for (i = 0; i < regnum; i++) +- adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); +-} +- +-static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, +- u32 *macreg, u32 *macbackup) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 i; +- +- RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); +- for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) +- macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); +- macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); +-} +- + static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, + u32 *adda_reg, u32 *adda_backup, + u32 regnum) +@@ -1685,37 +1174,6 @@ static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, + rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); + } + +-static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, +- u32 *adda_reg, bool patha_on, bool is2t) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 pathon; +- u32 i; +- +- RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); +- pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; +- if (patha_on) +- pathon = rtlpriv->rtlhal.interfaceindex == 0 ? +- 0x04db25a4 : 0x0b1b25a4; +- for (i = 0; i < IQK_ADDA_REG_NUM; i++) +- rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); +-} +- +-static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, +- u32 *macreg, u32 *macbackup) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 i; +- +- RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); +- rtl_write_byte(rtlpriv, macreg[0], 0x3F); +- +- for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) +- rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & +- (~BIT(3)))); +- rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); +-} +- + static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -1772,14 +1230,16 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], + is2t ? "2T2R" : "1T1R"); + + /* Save ADDA parameters, turn Path A ADDA on */ +- _rtl92d_phy_save_adda_registers(hw, adda_reg, +- rtlphy->adda_backup, IQK_ADDA_REG_NUM); +- _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, +- rtlphy->iqk_mac_backup); +- _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, +- rtlphy->iqk_bb_backup, IQK_BB_REG_NUM); +- } +- _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); ++ rtl92d_phy_save_adda_registers(hw, adda_reg, ++ rtlphy->adda_backup, ++ IQK_ADDA_REG_NUM); ++ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); ++ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM); ++ } ++ rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); + if (t == 0) + rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, + RFPGA0_XA_HSSIPARAMETER1, BIT(8)); +@@ -1800,8 +1260,8 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], + 0x00010000); + } + /* MAC settings */ +- _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, +- rtlphy->iqk_mac_backup); ++ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); + /* Page B init */ + rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); + if (is2t) +@@ -1841,7 +1301,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], + if (is2t) { + _rtl92d_phy_patha_standby(hw); + /* Turn Path B ADDA on */ +- _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); ++ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); + for (i = 0; i < retrycount; i++) { + pathb_ok = _rtl92d_phy_pathb_iqk(hw); + if (pathb_ok == 0x03) { +@@ -1938,24 +1398,24 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, + RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", + is2t ? "2T2R" : "1T1R"); + /* Save ADDA parameters, turn Path A ADDA on */ +- _rtl92d_phy_save_adda_registers(hw, adda_reg, +- rtlphy->adda_backup, +- IQK_ADDA_REG_NUM); +- _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, +- rtlphy->iqk_mac_backup); ++ rtl92d_phy_save_adda_registers(hw, adda_reg, ++ rtlphy->adda_backup, ++ IQK_ADDA_REG_NUM); ++ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); + if (is2t) +- _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, +- rtlphy->iqk_bb_backup, +- IQK_BB_REG_NUM); ++ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM); + else +- _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, +- rtlphy->iqk_bb_backup, +- IQK_BB_REG_NUM - 1); ++ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM - 1); + } +- _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); ++ rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); + /* MAC settings */ +- _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, +- rtlphy->iqk_mac_backup); ++ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); + if (t == 0) + rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, + RFPGA0_XA_HSSIPARAMETER1, BIT(8)); +@@ -2002,7 +1462,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, + if (is2t) { + /* _rtl92d_phy_patha_standby(hw); */ + /* Turn Path B ADDA on */ +- _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); ++ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); + pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); + if (pathb_ok == 0x03) { + RTPRINT(rtlpriv, FINIT, INIT_IQK, +@@ -2401,56 +1861,6 @@ void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); + } + +-static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) +-{ +- u32 ret; +- +- if (val1 >= val2) +- ret = val1 - val2; +- else +- ret = val2 - val1; +- return ret; +-} +- +-static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) +-{ +- +- int i; +- +- for (i = 0; i < ARRAY_SIZE(channel5g); i++) +- if (channel == channel5g[i]) +- return true; +- return false; +-} +- +-static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, +- u32 *targetchnl, u32 * curvecount_val, +- bool is5g, u32 *curveindex) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 smallest_abs_val = 0xffffffff, u4tmp; +- u8 i, j; +- u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; +- +- for (i = 0; i < chnl_num; i++) { +- if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) +- continue; +- curveindex[i] = 0; +- for (j = 0; j < (CV_CURVE_CNT * 2); j++) { +- u4tmp = _rtl92d_phy_get_abs(targetchnl[i], +- curvecount_val[j]); +- +- if (u4tmp < smallest_abs_val) { +- curveindex[i] = j; +- smallest_abs_val = u4tmp; +- } +- } +- smallest_abs_val = 0xffffffff; +- RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", +- i, curveindex[i]); +- } +-} +- + static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, + u8 channel) + { +@@ -2477,12 +1887,12 @@ static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, + rtlpriv->rtlhal.during_mac1init_radioa = true; + /* asume no this case */ + if (bneed_powerdown_radio) +- _rtl92d_phy_enable_rf_env(hw, erfpath, +- &u4regvalue); ++ rtl92d_phy_enable_rf_env(hw, erfpath, ++ &u4regvalue); + } + rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); + if (bneed_powerdown_radio) +- _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); ++ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); + if (rtlpriv->rtlhal.during_mac1init_radioa) + rtl92d_phy_powerdown_anotherphy(hw, false); + } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { +@@ -2495,15 +1905,15 @@ static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, + rtl92d_phy_enable_anotherphy(hw, true); + rtlpriv->rtlhal.during_mac0init_radiob = true; + if (bneed_powerdown_radio) +- _rtl92d_phy_enable_rf_env(hw, erfpath, +- &u4regvalue); ++ rtl92d_phy_enable_rf_env(hw, erfpath, ++ &u4regvalue); + } + rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); + RTPRINT(rtlpriv, FINIT, INIT_IQK, + "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", + rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); + if (bneed_powerdown_radio) +- _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); ++ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); + if (rtlpriv->rtlhal.during_mac0init_radiob) + rtl92d_phy_powerdown_anotherphy(hw, true); + } +@@ -2588,13 +1998,13 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) + readval2); + } + if (index == 0 && rtlhal->interfaceindex == 0) +- _rtl92d_phy_calc_curvindex(hw, targetchnl_5g, +- curvecount_val, +- true, curveindex_5g); ++ rtl92d_phy_calc_curvindex(hw, targetchnl_5g, ++ curvecount_val, ++ true, curveindex_5g); + else +- _rtl92d_phy_calc_curvindex(hw, targetchnl_2g, +- curvecount_val, +- false, curveindex_2g); ++ rtl92d_phy_calc_curvindex(hw, targetchnl_2g, ++ curvecount_val, ++ false, curveindex_2g); + /* switch CV-curve control mode */ + rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, + BIT(17), 0x1); +@@ -2622,7 +2032,7 @@ static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) + _rtl92d_phy_lc_calibrate_sw(hw, is2t); + } + +-void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) ++void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_phy *rtlphy = &(rtlpriv->phy); +@@ -2638,12 +2048,9 @@ void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) + RTPRINT(rtlpriv, FINIT, INIT_IQK, + "LCK:Start!!! currentband %x delay %d ms\n", + rtlhal->current_bandtype, timecount); +- if (IS_92D_SINGLEPHY(rtlhal->version)) { +- _rtl92d_phy_lc_calibrate(hw, true); +- } else { +- /* For 1T1R */ +- _rtl92d_phy_lc_calibrate(hw, false); +- } ++ ++ _rtl92d_phy_lc_calibrate(hw, is2t); ++ + rtlphy->lck_inprogress = false; + RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); + } +@@ -2674,30 +2081,6 @@ static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, + return true; + } + +-void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- u8 i; +- +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, +- "settings regs %zu default regs %d\n", +- ARRAY_SIZE(rtlphy->iqk_matrix), +- IQK_MATRIX_REG_NUM); +- /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ +- for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { +- rtlphy->iqk_matrix[i].value[0][0] = 0x100; +- rtlphy->iqk_matrix[i].value[0][2] = 0x100; +- rtlphy->iqk_matrix[i].value[0][4] = 0x100; +- rtlphy->iqk_matrix[i].value[0][6] = 0x100; +- rtlphy->iqk_matrix[i].value[0][1] = 0x0; +- rtlphy->iqk_matrix[i].value[0][3] = 0x0; +- rtlphy->iqk_matrix[i].value[0][5] = 0x0; +- rtlphy->iqk_matrix[i].value[0][7] = 0x0; +- rtlphy->iqk_matrix[i].iqk_done = false; +- } +-} +- + static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, + u8 channel, u8 *stage, u8 *step, + u32 *delay) +@@ -2891,74 +2274,6 @@ u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) + return 1; + } + +-static void rtl92d_phy_set_io(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct dig_t *de_digtable = &rtlpriv->dm_digtable; +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- +- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, +- "--->Cmd(%#x), set_io_inprogress(%d)\n", +- rtlphy->current_io_type, rtlphy->set_io_inprogress); +- switch (rtlphy->current_io_type) { +- case IO_CMD_RESUME_DM_BY_SCAN: +- de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; +- rtl92d_dm_write_dig(hw); +- rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); +- break; +- case IO_CMD_PAUSE_DM_BY_SCAN: +- rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; +- de_digtable->cur_igvalue = 0x37; +- rtl92d_dm_write_dig(hw); +- break; +- default: +- pr_err("switch case %#x not processed\n", +- rtlphy->current_io_type); +- break; +- } +- rtlphy->set_io_inprogress = false; +- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", +- rtlphy->current_io_type); +-} +- +-bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- bool postprocessing = false; +- +- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, +- "-->IO Cmd(%#x), set_io_inprogress(%d)\n", +- iotype, rtlphy->set_io_inprogress); +- do { +- switch (iotype) { +- case IO_CMD_RESUME_DM_BY_SCAN: +- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, +- "[IO CMD] Resume DM after scan\n"); +- postprocessing = true; +- break; +- case IO_CMD_PAUSE_DM_BY_SCAN: +- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, +- "[IO CMD] Pause DM before scan\n"); +- postprocessing = true; +- break; +- default: +- pr_err("switch case %#x not processed\n", +- iotype); +- break; +- } +- } while (false); +- if (postprocessing && !rtlphy->set_io_inprogress) { +- rtlphy->set_io_inprogress = true; +- rtlphy->current_io_type = iotype; +- } else { +- return false; +- } +- rtl92d_phy_set_io(hw); +- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); +- return true; +-} +- + static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -3141,100 +2456,6 @@ bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, + return bresult; + } + +-void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u8 offset = REG_MAC_PHY_CTRL_NORMAL; +- +- switch (rtlhal->macphymode) { +- case DUALMAC_DUALPHY: +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, +- "MacPhyMode: DUALMAC_DUALPHY\n"); +- rtl_write_byte(rtlpriv, offset, 0xF3); +- break; +- case SINGLEMAC_SINGLEPHY: +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, +- "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); +- rtl_write_byte(rtlpriv, offset, 0xF4); +- break; +- case DUALMAC_SINGLEPHY: +- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, +- "MacPhyMode: DUALMAC_SINGLEPHY\n"); +- rtl_write_byte(rtlpriv, offset, 0xF1); +- break; +- } +-} +- +-void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- +- switch (rtlhal->macphymode) { +- case DUALMAC_SINGLEPHY: +- rtlphy->rf_type = RF_2T2R; +- rtlhal->version |= RF_TYPE_2T2R; +- rtlhal->bandset = BAND_ON_BOTH; +- rtlhal->current_bandtype = BAND_ON_2_4G; +- break; +- +- case SINGLEMAC_SINGLEPHY: +- rtlphy->rf_type = RF_2T2R; +- rtlhal->version |= RF_TYPE_2T2R; +- rtlhal->bandset = BAND_ON_BOTH; +- rtlhal->current_bandtype = BAND_ON_2_4G; +- break; +- +- case DUALMAC_DUALPHY: +- rtlphy->rf_type = RF_1T1R; +- rtlhal->version &= RF_TYPE_1T1R; +- /* Now we let MAC0 run on 5G band. */ +- if (rtlhal->interfaceindex == 0) { +- rtlhal->bandset = BAND_ON_5G; +- rtlhal->current_bandtype = BAND_ON_5G; +- } else { +- rtlhal->bandset = BAND_ON_2_4G; +- rtlhal->current_bandtype = BAND_ON_2_4G; +- } +- break; +- default: +- break; +- } +-} +- +-u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) +-{ +- u8 group; +- +- if (channel_all[chnl] <= 3) +- group = 0; +- else if (channel_all[chnl] <= 9) +- group = 1; +- else if (channel_all[chnl] <= 14) +- group = 2; +- else if (channel_all[chnl] <= 44) +- group = 3; +- else if (channel_all[chnl] <= 54) +- group = 4; +- else if (channel_all[chnl] <= 64) +- group = 5; +- else if (channel_all[chnl] <= 112) +- group = 6; +- else if (channel_all[chnl] <= 126) +- group = 7; +- else if (channel_all[chnl] <= 140) +- group = 8; +- else if (channel_all[chnl] <= 153) +- group = 9; +- else if (channel_all[chnl] <= 159) +- group = 10; +- else +- group = 11; +- return group; +-} +- + void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +@@ -3286,31 +2507,6 @@ void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) + } + } + +-void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- +- switch (rtlpriv->rtlhal.macphymode) { +- case DUALMAC_DUALPHY: +- rtl_write_byte(rtlpriv, REG_DMC, 0x0); +- rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); +- rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); +- break; +- case DUALMAC_SINGLEPHY: +- rtl_write_byte(rtlpriv, REG_DMC, 0xf8); +- rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); +- rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); +- break; +- case SINGLEMAC_SINGLEPHY: +- rtl_write_byte(rtlpriv, REG_DMC, 0x0); +- rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); +- rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); +- break; +- default: +- break; +- } +-} +- + void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h +index 8d07c783a023..bbe9ef77225e 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h +@@ -10,11 +10,8 @@ + + #define MAX_DOZE_WAITING_TIMES_9x 64 + +-#define RT_CANNOT_IO(hw) false + #define HIGHPOWER_RADIOA_ARRAYLEN 22 + +-#define MAX_TOLERANCE 5 +- + #define APK_BB_REG_NUM 5 + #define APK_AFE_REG_NUM 16 + #define APK_CURVE_REG_NUM 4 +@@ -27,12 +24,8 @@ + #define RESET_CNT_LIMIT 3 + + #define IQK_ADDA_REG_NUM 16 +-#define IQK_BB_REG_NUM 10 + #define IQK_BB_REG_NUM_test 6 + #define IQK_MAC_REG_NUM 4 +-#define RX_INDEX_MAPPING_NUM 15 +- +-#define IQK_DELAY_TIME 1 + + #define CT_OFFSET_MAC_ADDR 0X16 + +@@ -68,80 +61,30 @@ struct swchnlcmd { + u32 msdelay; + }; + +-enum baseband_config_type { +- BASEBAND_CONFIG_PHY_REG = 0, +- BASEBAND_CONFIG_AGC_TAB = 1, +-}; +- +-enum rf_content { +- radioa_txt = 0, +- radiob_txt = 1, +- radioc_txt = 2, +- radiod_txt = 3 +-}; +- +-static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, +- unsigned long *flag) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- +- if (rtlpriv->rtlhal.interfaceindex == 1) +- spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag); +-} +- +-static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, +- unsigned long *flag) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- +- if (rtlpriv->rtlhal.interfaceindex == 1) +- spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock, +- *flag); +-} +- + u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, + u32 regaddr, u32 bitmask); + void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, + u32 regaddr, u32 bitmask, u32 data); +-u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, +- enum radio_path rfpath, u32 regaddr, +- u32 bitmask); +-void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, +- enum radio_path rfpath, u32 regaddr, +- u32 bitmask, u32 data); + bool rtl92d_phy_mac_config(struct ieee80211_hw *hw); + bool rtl92d_phy_bb_config(struct ieee80211_hw *hw); + bool rtl92d_phy_rf_config(struct ieee80211_hw *hw); + bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw, + enum radio_path rfpath); +-void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); +-void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel); + void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, + enum nl80211_channel_type ch_type); + u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw); + bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, + enum rf_content content, + enum radio_path rfpath); +-bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); + bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, + enum rf_pwrstate rfpwr_state); + +-void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw); +-void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw); +-u8 rtl92d_get_chnlgroup_fromarray(u8 chnl); + void rtl92d_phy_set_poweron(struct ieee80211_hw *hw); +-void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw); + bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw); +-void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw); ++void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t); + void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw); + void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta); + void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw); +-void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw); +-void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, +- unsigned long *flag); +-void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, +- unsigned long *flag); +-u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl); + void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel); + + #endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c +index 83787fd293de..eb7d8b070cc7 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c +@@ -2,383 +2,14 @@ + /* Copyright(c) 2009-2012 Realtek Corporation.*/ + + #include "../wifi.h" +-#include "reg.h" +-#include "def.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/phy_common.h" + #include "phy.h" + #include "rf.h" + #include "dm.h" + #include "hw.h" + +-void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- u8 rfpath; +- +- switch (bandwidth) { +- case HT_CHANNEL_WIDTH_20: +- for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { +- rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval +- [rfpath] & 0xfffff3ff) | 0x0400); +- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | +- BIT(11), 0x01); +- +- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, +- "20M RF 0x18 = 0x%x\n", +- rtlphy->rfreg_chnlval[rfpath]); +- } +- +- break; +- case HT_CHANNEL_WIDTH_20_40: +- for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { +- rtlphy->rfreg_chnlval[rfpath] = +- ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff)); +- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), +- 0x00); +- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, +- "40M RF 0x18 = 0x%x\n", +- rtlphy->rfreg_chnlval[rfpath]); +- } +- break; +- default: +- pr_err("unknown bandwidth: %#X\n", bandwidth); +- break; +- } +-} +- +-void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, +- u8 *ppowerlevel) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- u32 tx_agc[2] = {0, 0}, tmpval; +- bool turbo_scanoff = false; +- u8 idx1, idx2; +- u8 *ptr; +- +- if (rtlefuse->eeprom_regulatory != 0) +- turbo_scanoff = true; +- if (mac->act_scanning) { +- tx_agc[RF90_PATH_A] = 0x3f3f3f3f; +- tx_agc[RF90_PATH_B] = 0x3f3f3f3f; +- if (turbo_scanoff) { +- for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { +- tx_agc[idx1] = ppowerlevel[idx1] | +- (ppowerlevel[idx1] << 8) | +- (ppowerlevel[idx1] << 16) | +- (ppowerlevel[idx1] << 24); +- } +- } +- } else { +- for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { +- tx_agc[idx1] = ppowerlevel[idx1] | +- (ppowerlevel[idx1] << 8) | +- (ppowerlevel[idx1] << 16) | +- (ppowerlevel[idx1] << 24); +- } +- if (rtlefuse->eeprom_regulatory == 0) { +- tmpval = (rtlphy->mcs_offset[0][6]) + +- (rtlphy->mcs_offset[0][7] << 8); +- tx_agc[RF90_PATH_A] += tmpval; +- tmpval = (rtlphy->mcs_offset[0][14]) + +- (rtlphy->mcs_offset[0][15] << 24); +- tx_agc[RF90_PATH_B] += tmpval; +- } +- } +- +- for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { +- ptr = (u8 *) (&(tx_agc[idx1])); +- for (idx2 = 0; idx2 < 4; idx2++) { +- if (*ptr > RF6052_MAX_TX_PWR) +- *ptr = RF6052_MAX_TX_PWR; +- ptr++; +- } +- } +- +- tmpval = tx_agc[RF90_PATH_A] & 0xff; +- rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", +- tmpval, RTXAGC_A_CCK1_MCS32); +- tmpval = tx_agc[RF90_PATH_A] >> 8; +- rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", +- tmpval, RTXAGC_B_CCK11_A_CCK2_11); +- tmpval = tx_agc[RF90_PATH_B] >> 24; +- rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", +- tmpval, RTXAGC_B_CCK11_A_CCK2_11); +- tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; +- rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", +- tmpval, RTXAGC_B_CCK1_55_MCS32); +-} +- +-static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, +- u8 *ppowerlevel, u8 channel, +- u32 *ofdmbase, u32 *mcsbase) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- u32 powerbase0, powerbase1; +- u8 legacy_pwrdiff, ht20_pwrdiff; +- u8 i, powerlevel[2]; +- +- for (i = 0; i < 2; i++) { +- powerlevel[i] = ppowerlevel[i]; +- legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; +- powerbase0 = powerlevel[i] + legacy_pwrdiff; +- powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | +- (powerbase0 << 8) | powerbase0; +- *(ofdmbase + i) = powerbase0; +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- " [OFDM power base index rf(%c) = 0x%x]\n", +- i == 0 ? 'A' : 'B', *(ofdmbase + i)); +- } +- +- for (i = 0; i < 2; i++) { +- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { +- ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1]; +- powerlevel[i] += ht20_pwrdiff; +- } +- powerbase1 = powerlevel[i]; +- powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) | +- (powerbase1 << 8) | powerbase1; +- *(mcsbase + i) = powerbase1; +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- " [MCS power base index rf(%c) = 0x%x]\n", +- i == 0 ? 'A' : 'B', *(mcsbase + i)); +- } +-} +- +-static u8 _rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex) +-{ +- u8 group; +- u8 channel_info[59] = { +- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, +- 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, +- 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, +- 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, +- 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, +- 161, 163, 165 +- }; +- +- if (channel_info[chnlindex] <= 3) /* Chanel 1-3 */ +- group = 0; +- else if (channel_info[chnlindex] <= 9) /* Channel 4-9 */ +- group = 1; +- else if (channel_info[chnlindex] <= 14) /* Channel 10-14 */ +- group = 2; +- else if (channel_info[chnlindex] <= 64) +- group = 6; +- else if (channel_info[chnlindex] <= 140) +- group = 7; +- else +- group = 8; +- return group; +-} +- +-static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, +- u8 channel, u8 index, +- u32 *powerbase0, +- u32 *powerbase1, +- u32 *p_outwriteval) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- u8 i, chnlgroup = 0, pwr_diff_limit[4]; +- u32 writeval = 0, customer_limit, rf; +- +- for (rf = 0; rf < 2; rf++) { +- switch (rtlefuse->eeprom_regulatory) { +- case 0: +- chnlgroup = 0; +- writeval = rtlphy->mcs_offset +- [chnlgroup][index + +- (rf ? 8 : 0)] + ((index < 2) ? +- powerbase0[rf] : +- powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "RTK better performance, writeval(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); +- break; +- case 1: +- if (rtlphy->pwrgroup_cnt == 1) +- chnlgroup = 0; +- if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) { +- chnlgroup = _rtl92d_phy_get_chnlgroup_bypg( +- channel - 1); +- if (rtlphy->current_chan_bw == +- HT_CHANNEL_WIDTH_20) +- chnlgroup++; +- else +- chnlgroup += 4; +- writeval = rtlphy->mcs_offset +- [chnlgroup][index + +- (rf ? 8 : 0)] + ((index < 2) ? +- powerbase0[rf] : +- powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); +- } +- break; +- case 2: +- writeval = ((index < 2) ? powerbase0[rf] : +- powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Better regulatory, writeval(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); +- break; +- case 3: +- chnlgroup = 0; +- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "customer's limit, 40MHz rf(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', +- rtlefuse->pwrgroup_ht40[rf] +- [channel - 1]); +- } else { +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "customer's limit, 20MHz rf(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', +- rtlefuse->pwrgroup_ht20[rf] +- [channel - 1]); +- } +- for (i = 0; i < 4; i++) { +- pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset +- [chnlgroup][index + (rf ? 8 : 0)] & +- (0x7f << (i * 8))) >> (i * 8)); +- if (rtlphy->current_chan_bw == +- HT_CHANNEL_WIDTH_20_40) { +- if (pwr_diff_limit[i] > +- rtlefuse->pwrgroup_ht40[rf] +- [channel - 1]) +- pwr_diff_limit[i] = +- rtlefuse->pwrgroup_ht40 +- [rf][channel - 1]; +- } else { +- if (pwr_diff_limit[i] > +- rtlefuse->pwrgroup_ht20[rf][ +- channel - 1]) +- pwr_diff_limit[i] = +- rtlefuse->pwrgroup_ht20[rf] +- [channel - 1]; +- } +- } +- customer_limit = (pwr_diff_limit[3] << 24) | +- (pwr_diff_limit[2] << 16) | +- (pwr_diff_limit[1] << 8) | +- (pwr_diff_limit[0]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Customer's limit rf(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', customer_limit); +- writeval = customer_limit + ((index < 2) ? +- powerbase0[rf] : powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Customer, writeval rf(%c)= 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); +- break; +- default: +- chnlgroup = 0; +- writeval = rtlphy->mcs_offset[chnlgroup][index + +- (rf ? 8 : 0)] + ((index < 2) ? +- powerbase0[rf] : powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "RTK better performance, writeval rf(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); +- break; +- } +- *(p_outwriteval + rf) = writeval; +- } +-} +- +-static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw, +- u8 index, u32 *pvalue) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- static u16 regoffset_a[6] = { +- RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, +- RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04, +- RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12 +- }; +- static u16 regoffset_b[6] = { +- RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24, +- RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04, +- RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 +- }; +- u8 i, rf, pwr_val[4]; +- u32 writeval; +- u16 regoffset; +- +- for (rf = 0; rf < 2; rf++) { +- writeval = pvalue[rf]; +- for (i = 0; i < 4; i++) { +- pwr_val[i] = (u8) ((writeval & (0x7f << +- (i * 8))) >> (i * 8)); +- if (pwr_val[i] > RF6052_MAX_TX_PWR) +- pwr_val[i] = RF6052_MAX_TX_PWR; +- } +- writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) | +- (pwr_val[1] << 8) | pwr_val[0]; +- if (rf == 0) +- regoffset = regoffset_a[index]; +- else +- regoffset = regoffset_b[index]; +- rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Set 0x%x = %08x\n", regoffset, writeval); +- if (((get_rf_type(rtlphy) == RF_2T2R) && +- (regoffset == RTXAGC_A_MCS15_MCS12 || +- regoffset == RTXAGC_B_MCS15_MCS12)) || +- ((get_rf_type(rtlphy) != RF_2T2R) && +- (regoffset == RTXAGC_A_MCS07_MCS04 || +- regoffset == RTXAGC_B_MCS07_MCS04))) { +- writeval = pwr_val[3]; +- if (regoffset == RTXAGC_A_MCS15_MCS12 || +- regoffset == RTXAGC_A_MCS07_MCS04) +- regoffset = 0xc90; +- if (regoffset == RTXAGC_B_MCS15_MCS12 || +- regoffset == RTXAGC_B_MCS07_MCS04) +- regoffset = 0xc98; +- for (i = 0; i < 3; i++) { +- if (i != 2) +- writeval = (writeval > 8) ? +- (writeval - 8) : 0; +- else +- writeval = (writeval > 6) ? +- (writeval - 6) : 0; +- rtl_write_byte(rtlpriv, (u32) (regoffset + i), +- (u8) writeval); +- } +- } +- } +-} +- +-void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, +- u8 *ppowerlevel, u8 channel) +-{ +- u32 writeval[2], powerbase0[2], powerbase1[2]; +- u8 index; +- +- _rtl92d_phy_get_power_base(hw, ppowerlevel, channel, +- &powerbase0[0], &powerbase1[0]); +- for (index = 0; index < 6; index++) { +- _rtl92d_get_txpower_writeval_by_regulatory(hw, +- channel, index, &powerbase0[0], +- &powerbase1[0], &writeval[0]); +- _rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]); +- } +-} +- + bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h +index 4e646cc9ebc0..c097d90cc99c 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h +@@ -4,11 +4,6 @@ + #ifndef __RTL92D_RF_H__ + #define __RTL92D_RF_H__ + +-void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth); +-void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, +- u8 *ppowerlevel); +-void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, +- u8 *ppowerlevel, u8 channel); + bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw); + bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0); + void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c +index afd685ed460a..5f6311c2aac4 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c +@@ -5,8 +5,12 @@ + #include "../core.h" + #include "../pci.h" + #include "../base.h" +-#include "reg.h" +-#include "def.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/dm_common.h" ++#include "../rtl8192d/hw_common.h" ++#include "../rtl8192d/phy_common.h" ++#include "../rtl8192d/trx_common.h" + #include "phy.h" + #include "dm.h" + #include "hw.h" +@@ -207,7 +211,7 @@ static struct rtl_hal_ops rtl8192de_hal_ops = { + .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, + .set_bw_mode = rtl92d_phy_set_bw_mode, + .switch_channel = rtl92d_phy_sw_chnl, +- .dm_watchdog = rtl92d_dm_watchdog, ++ .dm_watchdog = rtl92de_dm_watchdog, + .scan_operation_backup = rtl_phy_scan_operation_backup, + .set_rf_power_state = rtl92d_phy_set_rf_power_state, + .led_control = rtl92de_led_control, +@@ -223,6 +227,8 @@ static struct rtl_hal_ops rtl8192de_hal_ops = { + .set_rfreg = rtl92d_phy_set_rf_reg, + .linked_set_reg = rtl92d_linked_set_reg, + .get_btc_status = rtl_btc_status_false, ++ .phy_iq_calibrate = rtl92d_phy_iq_calibrate, ++ .phy_lc_calibrate = rtl92d_phy_lc_calibrate, + }; + + static struct rtl_mod_params rtl92de_mod_params = { +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +index cbc7b4dbea9a..2b9b352f7783 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +@@ -5,8 +5,10 @@ + #include "../pci.h" + #include "../base.h" + #include "../stats.h" +-#include "reg.h" +-#include "def.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/phy_common.h" ++#include "../rtl8192d/trx_common.h" + #include "phy.h" + #include "trx.h" + #include "led.h" +@@ -23,433 +25,6 @@ static u8 _rtl92de_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue) + return skb->priority; + } + +-static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, +- u8 signal_strength_index) +-{ +- long signal_power; +- +- signal_power = (long)((signal_strength_index + 1) >> 1); +- signal_power -= 95; +- return signal_power; +-} +- +-static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, +- struct rtl_stats *pstats, +- __le32 *pdesc, +- struct rx_fwinfo_92d *p_drvinfo, +- bool packet_match_bssid, +- bool packet_toself, +- bool packet_beacon) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); +- struct phy_sts_cck_8192d *cck_buf; +- s8 rx_pwr_all, rx_pwr[4]; +- u8 rf_rx_num = 0, evm, pwdb_all; +- u8 i, max_spatial_stream; +- u32 rssi, total_rssi = 0; +- bool is_cck_rate; +- u8 rxmcs; +- +- rxmcs = get_rx_desc_rxmcs(pdesc); +- is_cck_rate = rxmcs <= DESC_RATE11M; +- pstats->packet_matchbssid = packet_match_bssid; +- pstats->packet_toself = packet_toself; +- pstats->packet_beacon = packet_beacon; +- pstats->is_cck = is_cck_rate; +- pstats->rx_mimo_sig_qual[0] = -1; +- pstats->rx_mimo_sig_qual[1] = -1; +- +- if (is_cck_rate) { +- u8 report, cck_highpwr; +- cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo; +- if (ppsc->rfpwr_state == ERFON) +- cck_highpwr = rtlphy->cck_high_power; +- else +- cck_highpwr = false; +- if (!cck_highpwr) { +- u8 cck_agc_rpt = cck_buf->cck_agc_rpt; +- report = cck_buf->cck_agc_rpt & 0xc0; +- report = report >> 6; +- switch (report) { +- case 0x3: +- rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); +- break; +- case 0x2: +- rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); +- break; +- case 0x1: +- rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); +- break; +- case 0x0: +- rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); +- break; +- } +- } else { +- u8 cck_agc_rpt = cck_buf->cck_agc_rpt; +- report = p_drvinfo->cfosho[0] & 0x60; +- report = report >> 5; +- switch (report) { +- case 0x3: +- rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); +- break; +- case 0x2: +- rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); +- break; +- case 0x1: +- rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); +- break; +- case 0x0: +- rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); +- break; +- } +- } +- pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); +- /* CCK gain is smaller than OFDM/MCS gain, */ +- /* so we add gain diff by experiences, the val is 6 */ +- pwdb_all += 6; +- if (pwdb_all > 100) +- pwdb_all = 100; +- /* modify the offset to make the same gain index with OFDM. */ +- if (pwdb_all > 34 && pwdb_all <= 42) +- pwdb_all -= 2; +- else if (pwdb_all > 26 && pwdb_all <= 34) +- pwdb_all -= 6; +- else if (pwdb_all > 14 && pwdb_all <= 26) +- pwdb_all -= 8; +- else if (pwdb_all > 4 && pwdb_all <= 14) +- pwdb_all -= 4; +- pstats->rx_pwdb_all = pwdb_all; +- pstats->recvsignalpower = rx_pwr_all; +- if (packet_match_bssid) { +- u8 sq; +- if (pstats->rx_pwdb_all > 40) { +- sq = 100; +- } else { +- sq = cck_buf->sq_rpt; +- if (sq > 64) +- sq = 0; +- else if (sq < 20) +- sq = 100; +- else +- sq = ((64 - sq) * 100) / 44; +- } +- pstats->signalquality = sq; +- pstats->rx_mimo_sig_qual[0] = sq; +- pstats->rx_mimo_sig_qual[1] = -1; +- } +- } else { +- rtlpriv->dm.rfpath_rxenable[0] = true; +- rtlpriv->dm.rfpath_rxenable[1] = true; +- for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) { +- if (rtlpriv->dm.rfpath_rxenable[i]) +- rf_rx_num++; +- rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) +- - 110; +- rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); +- total_rssi += rssi; +- rtlpriv->stats.rx_snr_db[i] = +- (long)(p_drvinfo->rxsnr[i] / 2); +- if (packet_match_bssid) +- pstats->rx_mimo_signalstrength[i] = (u8) rssi; +- } +- rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 106; +- pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); +- pstats->rx_pwdb_all = pwdb_all; +- pstats->rxpower = rx_pwr_all; +- pstats->recvsignalpower = rx_pwr_all; +- if (get_rx_desc_rxht(pdesc) && rxmcs >= DESC_RATEMCS8 && +- rxmcs <= DESC_RATEMCS15) +- max_spatial_stream = 2; +- else +- max_spatial_stream = 1; +- for (i = 0; i < max_spatial_stream; i++) { +- evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]); +- if (packet_match_bssid) { +- if (i == 0) +- pstats->signalquality = +- (u8)(evm & 0xff); +- pstats->rx_mimo_sig_qual[i] = +- (u8)(evm & 0xff); +- } +- } +- } +- if (is_cck_rate) +- pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, +- pwdb_all)); +- else if (rf_rx_num != 0) +- pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, +- total_rssi /= rf_rx_num)); +-} +- +-static void rtl92d_loop_over_paths(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_phy *rtlphy = &(rtlpriv->phy); +- u8 rfpath; +- +- for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; +- rfpath++) { +- if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) { +- rtlpriv->stats.rx_rssi_percentage[rfpath] = +- pstats->rx_mimo_signalstrength[rfpath]; +- +- } +- if (pstats->rx_mimo_signalstrength[rfpath] > +- rtlpriv->stats.rx_rssi_percentage[rfpath]) { +- rtlpriv->stats.rx_rssi_percentage[rfpath] = +- ((rtlpriv->stats.rx_rssi_percentage[rfpath] * +- (RX_SMOOTH_FACTOR - 1)) + +- (pstats->rx_mimo_signalstrength[rfpath])) / +- (RX_SMOOTH_FACTOR); +- rtlpriv->stats.rx_rssi_percentage[rfpath] = +- rtlpriv->stats.rx_rssi_percentage[rfpath] + 1; +- } else { +- rtlpriv->stats.rx_rssi_percentage[rfpath] = +- ((rtlpriv->stats.rx_rssi_percentage[rfpath] * +- (RX_SMOOTH_FACTOR - 1)) + +- (pstats->rx_mimo_signalstrength[rfpath])) / +- (RX_SMOOTH_FACTOR); +- } +- } +-} +- +-static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 last_rssi, tmpval; +- +- if (pstats->packet_toself || pstats->packet_beacon) { +- rtlpriv->stats.rssi_calculate_cnt++; +- if (rtlpriv->stats.ui_rssi.total_num++ >= +- PHY_RSSI_SLID_WIN_MAX) { +- rtlpriv->stats.ui_rssi.total_num = +- PHY_RSSI_SLID_WIN_MAX; +- last_rssi = rtlpriv->stats.ui_rssi.elements[ +- rtlpriv->stats.ui_rssi.index]; +- rtlpriv->stats.ui_rssi.total_val -= last_rssi; +- } +- rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength; +- rtlpriv->stats.ui_rssi.elements +- [rtlpriv->stats.ui_rssi.index++] = +- pstats->signalstrength; +- if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX) +- rtlpriv->stats.ui_rssi.index = 0; +- tmpval = rtlpriv->stats.ui_rssi.total_val / +- rtlpriv->stats.ui_rssi.total_num; +- rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw, +- (u8) tmpval); +- pstats->rssi = rtlpriv->stats.signal_strength; +- } +- if (!pstats->is_cck && pstats->packet_toself) +- rtl92d_loop_over_paths(hw, pstats); +-} +- +-static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- int weighting = 0; +- +- if (rtlpriv->stats.recv_signal_power == 0) +- rtlpriv->stats.recv_signal_power = pstats->recvsignalpower; +- if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power) +- weighting = 5; +- else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power) +- weighting = (-5); +- rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power * +- 5 + pstats->recvsignalpower + weighting) / 6; +-} +- +-static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- long undec_sm_pwdb; +- +- if (mac->opmode == NL80211_IFTYPE_ADHOC || +- mac->opmode == NL80211_IFTYPE_AP) +- return; +- else +- undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; +- +- if (pstats->packet_toself || pstats->packet_beacon) { +- if (undec_sm_pwdb < 0) +- undec_sm_pwdb = pstats->rx_pwdb_all; +- if (pstats->rx_pwdb_all > (u32) undec_sm_pwdb) { +- undec_sm_pwdb = (((undec_sm_pwdb) * +- (RX_SMOOTH_FACTOR - 1)) + +- (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); +- undec_sm_pwdb = undec_sm_pwdb + 1; +- } else { +- undec_sm_pwdb = (((undec_sm_pwdb) * +- (RX_SMOOTH_FACTOR - 1)) + +- (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); +- } +- rtlpriv->dm.undec_sm_pwdb = undec_sm_pwdb; +- _rtl92de_update_rxsignalstatistics(hw, pstats); +- } +-} +- +-static void rtl92d_loop_over_streams(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- int stream; +- +- for (stream = 0; stream < 2; stream++) { +- if (pstats->rx_mimo_sig_qual[stream] != -1) { +- if (rtlpriv->stats.rx_evm_percentage[stream] == 0) { +- rtlpriv->stats.rx_evm_percentage[stream] = +- pstats->rx_mimo_sig_qual[stream]; +- } +- rtlpriv->stats.rx_evm_percentage[stream] = +- ((rtlpriv->stats.rx_evm_percentage[stream] +- * (RX_SMOOTH_FACTOR - 1)) + +- (pstats->rx_mimo_sig_qual[stream] * 1)) / +- (RX_SMOOTH_FACTOR); +- } +- } +-} +- +-static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) +-{ +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- u32 last_evm, tmpval; +- +- if (pstats->signalquality == 0) +- return; +- if (pstats->packet_toself || pstats->packet_beacon) { +- if (rtlpriv->stats.ui_link_quality.total_num++ >= +- PHY_LINKQUALITY_SLID_WIN_MAX) { +- rtlpriv->stats.ui_link_quality.total_num = +- PHY_LINKQUALITY_SLID_WIN_MAX; +- last_evm = rtlpriv->stats.ui_link_quality.elements[ +- rtlpriv->stats.ui_link_quality.index]; +- rtlpriv->stats.ui_link_quality.total_val -= last_evm; +- } +- rtlpriv->stats.ui_link_quality.total_val += +- pstats->signalquality; +- rtlpriv->stats.ui_link_quality.elements[ +- rtlpriv->stats.ui_link_quality.index++] = +- pstats->signalquality; +- if (rtlpriv->stats.ui_link_quality.index >= +- PHY_LINKQUALITY_SLID_WIN_MAX) +- rtlpriv->stats.ui_link_quality.index = 0; +- tmpval = rtlpriv->stats.ui_link_quality.total_val / +- rtlpriv->stats.ui_link_quality.total_num; +- rtlpriv->stats.signal_quality = tmpval; +- rtlpriv->stats.last_sigstrength_inpercent = tmpval; +- rtl92d_loop_over_streams(hw, pstats); +- } +-} +- +-static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw, +- u8 *buffer, +- struct rtl_stats *pcurrent_stats) +-{ +- +- if (!pcurrent_stats->packet_matchbssid && +- !pcurrent_stats->packet_beacon) +- return; +- +- _rtl92de_process_ui_rssi(hw, pcurrent_stats); +- _rtl92de_process_pwdb(hw, pcurrent_stats); +- _rtl92de_process_ui_link_quality(hw, pcurrent_stats); +-} +- +-static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, +- struct sk_buff *skb, +- struct rtl_stats *pstats, +- __le32 *pdesc, +- struct rx_fwinfo_92d *p_drvinfo) +-{ +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- struct ieee80211_hdr *hdr; +- u8 *tmp_buf; +- u8 *praddr; +- u16 type, cfc; +- __le16 fc; +- bool packet_matchbssid, packet_toself, packet_beacon = false; +- +- tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; +- hdr = (struct ieee80211_hdr *)tmp_buf; +- fc = hdr->frame_control; +- cfc = le16_to_cpu(fc); +- type = WLAN_FC_GET_TYPE(fc); +- praddr = hdr->addr1; +- packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) && +- ether_addr_equal(mac->bssid, +- (cfc & IEEE80211_FCTL_TODS) ? hdr->addr1 : +- (cfc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : +- hdr->addr3) && +- (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); +- packet_toself = packet_matchbssid && +- ether_addr_equal(praddr, rtlefuse->dev_addr); +- if (ieee80211_is_beacon(fc)) +- packet_beacon = true; +- _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, +- packet_matchbssid, packet_toself, +- packet_beacon); +- _rtl92de_process_phyinfo(hw, tmp_buf, pstats); +-} +- +-bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, +- struct ieee80211_rx_status *rx_status, +- u8 *pdesc8, struct sk_buff *skb) +-{ +- __le32 *pdesc = (__le32 *)pdesc8; +- struct rx_fwinfo_92d *p_drvinfo; +- u32 phystatus = get_rx_desc_physt(pdesc); +- +- stats->length = (u16)get_rx_desc_pkt_len(pdesc); +- stats->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(pdesc) * +- RX_DRV_INFO_SIZE_UNIT; +- stats->rx_bufshift = (u8)(get_rx_desc_shift(pdesc) & 0x03); +- stats->icv = (u16)get_rx_desc_icv(pdesc); +- stats->crc = (u16)get_rx_desc_crc32(pdesc); +- stats->hwerror = (stats->crc | stats->icv); +- stats->decrypted = !get_rx_desc_swdec(pdesc) && +- get_rx_desc_enc_type(pdesc) != RX_DESC_ENC_NONE; +- stats->rate = (u8)get_rx_desc_rxmcs(pdesc); +- stats->shortpreamble = (u16)get_rx_desc_splcp(pdesc); +- stats->isampdu = (bool)(get_rx_desc_paggr(pdesc) == 1); +- stats->isfirst_ampdu = (bool)((get_rx_desc_paggr(pdesc) == 1) && +- (get_rx_desc_faggr(pdesc) == 1)); +- stats->timestamp_low = get_rx_desc_tsfl(pdesc); +- stats->rx_is40mhzpacket = (bool)get_rx_desc_bw(pdesc); +- stats->is_ht = (bool)get_rx_desc_rxht(pdesc); +- rx_status->freq = hw->conf.chandef.chan->center_freq; +- rx_status->band = hw->conf.chandef.chan->band; +- if (get_rx_desc_crc32(pdesc)) +- rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; +- if (get_rx_desc_bw(pdesc)) +- rx_status->bw = RATE_INFO_BW_40; +- if (get_rx_desc_rxht(pdesc)) +- rx_status->encoding = RX_ENC_HT; +- rx_status->flag |= RX_FLAG_MACTIME_START; +- if (stats->decrypted) +- rx_status->flag |= RX_FLAG_DECRYPTED; +- rx_status->rate_idx = rtlwifi_rate_mapping(hw, stats->is_ht, +- false, stats->rate); +- rx_status->mactime = get_rx_desc_tsfl(pdesc); +- if (phystatus) { +- p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + +- stats->rx_bufshift); +- _rtl92de_translate_rx_signal_stuff(hw, skb, stats, pdesc, +- p_drvinfo); +- } +- /*rx_status->qual = stats->signal; */ +- rx_status->signal = stats->recvsignalpower + 10; +- return true; +-} +- + static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc, + u8 *virtualaddress8) + { +@@ -711,87 +286,6 @@ void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, + set_tx_desc_own(pdesc, 1); + } + +-void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, +- u8 desc_name, u8 *val) +-{ +- __le32 *pdesc = (__le32 *)pdesc8; +- +- if (istx) { +- switch (desc_name) { +- case HW_DESC_OWN: +- wmb(); +- set_tx_desc_own(pdesc, 1); +- break; +- case HW_DESC_TX_NEXTDESC_ADDR: +- set_tx_desc_next_desc_address(pdesc, *(u32 *)val); +- break; +- default: +- WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", +- desc_name); +- break; +- } +- } else { +- switch (desc_name) { +- case HW_DESC_RXOWN: +- wmb(); +- set_rx_desc_own(pdesc, 1); +- break; +- case HW_DESC_RXBUFF_ADDR: +- set_rx_desc_buff_addr(pdesc, *(u32 *)val); +- break; +- case HW_DESC_RXPKT_LEN: +- set_rx_desc_pkt_len(pdesc, *(u32 *)val); +- break; +- case HW_DESC_RXERO: +- set_rx_desc_eor(pdesc, 1); +- break; +- default: +- WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", +- desc_name); +- break; +- } +- } +-} +- +-u64 rtl92de_get_desc(struct ieee80211_hw *hw, +- u8 *p_desc8, bool istx, u8 desc_name) +-{ +- __le32 *p_desc = (__le32 *)p_desc8; +- u32 ret = 0; +- +- if (istx) { +- switch (desc_name) { +- case HW_DESC_OWN: +- ret = get_tx_desc_own(p_desc); +- break; +- case HW_DESC_TXBUFF_ADDR: +- ret = get_tx_desc_tx_buffer_address(p_desc); +- break; +- default: +- WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", +- desc_name); +- break; +- } +- } else { +- switch (desc_name) { +- case HW_DESC_OWN: +- ret = get_rx_desc_own(p_desc); +- break; +- case HW_DESC_RXPKT_LEN: +- ret = get_rx_desc_pkt_len(p_desc); +- break; +- case HW_DESC_RXBUFF_ADDR: +- ret = get_rx_desc_buff_addr(p_desc); +- break; +- default: +- WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", +- desc_name); +- break; +- } +- } +- return ret; +-} +- + bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, + u8 hw_queue, u16 index) + { +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +index 2d4887490f00..d3c480c75678 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +@@ -8,405 +8,17 @@ + #define TX_DESC_AGGR_SUBFRAME_SIZE 32 + + #define RX_DESC_SIZE 32 +-#define RX_DRV_INFO_SIZE_UNIT 8 + + #define TX_DESC_NEXT_DESC_OFFSET 40 + #define USB_HWDESC_HEADER_LEN 32 + #define CRCLENGTH 4 + +-enum rtl92d_rx_desc_enc { +- RX_DESC_ENC_NONE = 0, +- RX_DESC_ENC_WEP40 = 1, +- RX_DESC_ENC_TKIP_WO_MIC = 2, +- RX_DESC_ENC_TKIP_MIC = 3, +- RX_DESC_ENC_AES = 4, +- RX_DESC_ENC_WEP104 = 5, +-}; +- +-/* macros to read/write various fields in RX or TX descriptors */ +- +-static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, GENMASK(15, 0)); +-} +- +-static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, GENMASK(23, 16)); +-} +- +-static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, BIT(25)); +-} +- +-static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, BIT(26)); +-} +- +-static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, BIT(27)); +-} +- +-static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, BIT(28)); +-} +- +-static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, BIT(31)); +-} +- +-static inline u32 get_tx_desc_own(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, BIT(31)); +-} +- +-static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0)); +-} +- +-static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 1), __val, BIT(5)); +-} +- +-static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 1), __val, BIT(7)); +-} +- +-static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8)); +-} +- +-static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16)); +-} +- +-static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22)); +-} +- +-static inline void set_tx_desc_pkt_offset(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 1), __val, GENMASK(30, 26)); +-} +- +-static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 2), __val, BIT(17)); +-} +- +-static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20)); +-} +- +-static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16)); +-} +- +-static inline void set_tx_desc_pkt_id(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28)); +-} +- +-static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0)); +-} +- +-static inline void set_tx_desc_qos(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(6)); +-} +- +-static inline void set_tx_desc_hwseq_en(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(7)); +-} +- +-static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(8)); +-} +- +-static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(10)); +-} +- +-static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(11)); +-} +- +-static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(12)); +-} +- +-static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(13)); +-} +- +-static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20)); +-} +- +-static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(25)); +-} +- +-static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(26)); +-} +- +-static inline void set_tx_desc_rts_bw(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, BIT(27)); +-} +- +-static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28)); +-} +- +-static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30)); +-} +- +-static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); +-} +- +-static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 5), __val, BIT(6)); +-} +- +-static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8)); +-} +- +-static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13)); +-} +- +-static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11)); +-} +- +-static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0)); +-} +- +-static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val) +-{ +- *(__pdesc + 8) = cpu_to_le32(__val); +-} +- +-static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc) +-{ +- return le32_to_cpu(*(__pdesc + 8)); +-} +- +-static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val) +-{ +- *(__pdesc + 10) = cpu_to_le32(__val); +-} +- +-static inline u32 get_rx_desc_pkt_len(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, GENMASK(13, 0)); +-} +- +-static inline u32 get_rx_desc_crc32(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, BIT(14)); +-} +- +-static inline u32 get_rx_desc_icv(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, BIT(15)); +-} +- +-static inline u32 get_rx_desc_drv_info_size(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, GENMASK(19, 16)); +-} +- +-static inline u32 get_rx_desc_enc_type(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, GENMASK(22, 20)); +-} +- +-static inline u32 get_rx_desc_shift(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, GENMASK(25, 24)); +-} +- +-static inline u32 get_rx_desc_physt(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, BIT(26)); +-} +- +-static inline u32 get_rx_desc_swdec(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, BIT(27)); +-} +- +-static inline u32 get_rx_desc_own(__le32 *__pdesc) +-{ +- return le32_get_bits(*__pdesc, BIT(31)); +-} +- +-static inline void set_rx_desc_pkt_len(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, GENMASK(13, 0)); +-} +- +-static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, BIT(30)); +-} +- +-static inline void set_rx_desc_own(__le32 *__pdesc, u32 __val) +-{ +- le32p_replace_bits(__pdesc, __val, BIT(31)); +-} +- +-static inline u32 get_rx_desc_paggr(__le32 *__pdesc) +-{ +- return le32_get_bits(*(__pdesc + 1), BIT(14)); +-} +- +-static inline u32 get_rx_desc_faggr(__le32 *__pdesc) +-{ +- return le32_get_bits(*(__pdesc + 1), BIT(15)); +-} +- +-static inline u32 get_rx_desc_rxmcs(__le32 *__pdesc) +-{ +- return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0)); +-} +- +-static inline u32 get_rx_desc_rxht(__le32 *__pdesc) +-{ +- return le32_get_bits(*(__pdesc + 3), BIT(6)); +-} +- +-static inline u32 get_rx_desc_splcp(__le32 *__pdesc) +-{ +- return le32_get_bits(*(__pdesc + 3), BIT(8)); +-} +- +-static inline u32 get_rx_desc_bw(__le32 *__pdesc) +-{ +- return le32_get_bits(*(__pdesc + 3), BIT(9)); +-} +- +-static inline u32 get_rx_desc_tsfl(__le32 *__pdesc) +-{ +- return le32_to_cpu(*(__pdesc + 5)); +-} +- +-static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc) +-{ +- return le32_to_cpu(*(__pdesc + 6)); +-} +- +-static inline void set_rx_desc_buff_addr(__le32 *__pdesc, u32 __val) +-{ +- *(__pdesc + 6) = cpu_to_le32(__val); +-} +- + static inline void clear_pci_tx_desc_content(__le32 *__pdesc, u32 _size) + { + memset((void *)__pdesc, 0, + min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)); + } + +-/* For 92D early mode */ +-static inline void set_earlymode_pktnum(__le32 *__paddr, u32 __value) +-{ +- le32p_replace_bits(__paddr, __value, GENMASK(2, 0)); +-} +- +-static inline void set_earlymode_len0(__le32 *__paddr, u32 __value) +-{ +- le32p_replace_bits(__paddr, __value, GENMASK(15, 4)); +-} +- +-static inline void set_earlymode_len1(__le32 *__paddr, u32 __value) +-{ +- le32p_replace_bits(__paddr, __value, GENMASK(27, 16)); +-} +- +-static inline void set_earlymode_len2_1(__le32 *__paddr, u32 __value) +-{ +- le32p_replace_bits(__paddr, __value, GENMASK(31, 28)); +-} +- +-static inline void set_earlymode_len2_2(__le32 *__paddr, u32 __value) +-{ +- le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0)); +-} +- +-static inline void set_earlymode_len3(__le32 *__paddr, u32 __value) +-{ +- le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8)); +-} +- +-static inline void set_earlymode_len4(__le32 *__paddr, u32 __value) +-{ +- le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20)); +-} +- +-struct rx_fwinfo_92d { +- u8 gain_trsw[4]; +- u8 pwdb_all; +- u8 cfosho[4]; +- u8 cfotail[4]; +- s8 rxevm[2]; +- s8 rxsnr[4]; +- u8 pdsnr[2]; +- u8 csi_current[2]; +- u8 csi_target[2]; +- u8 sigevm; +- u8 max_ex_pwr; +-#ifdef __LITTLE_ENDIAN +- u8 ex_intf_flag:1; +- u8 sgi_en:1; +- u8 rxsc:2; +- u8 reserve:4; +-#else +- u8 reserve:4; +- u8 rxsc:2; +- u8 sgi_en:1; +- u8 ex_intf_flag:1; +-#endif +-} __packed; +- + struct tx_desc_92d { + u32 pktsize:16; + u32 offset:8; +@@ -515,14 +127,6 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, + struct ieee80211_sta *sta, + struct sk_buff *skb, u8 hw_queue, + struct rtl_tcb_desc *ptcb_desc); +-bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, +- struct rtl_stats *stats, +- struct ieee80211_rx_status *rx_status, +- u8 *pdesc, struct sk_buff *skb); +-void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, +- u8 desc_name, u8 *val); +-u64 rtl92de_get_desc(struct ieee80211_hw *hw, +- u8 *p_desc, bool istx, u8 desc_name); + bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, + u8 hw_queue, u16 index); + void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); +diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h +index 9fabf597cfd6..098db85e381c 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/wifi.h ++++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h +@@ -2268,6 +2268,7 @@ struct rtl_hal_ops { + bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw, + u8 configtype); + void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t); ++ void (*phy_iq_calibrate)(struct ieee80211_hw *hw); + void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw); + void (*dm_dynamic_txpower)(struct ieee80211_hw *hw); + void (*c2h_command_handle)(struct ieee80211_hw *hw); +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0015-FROMGIT-6.10-wifi-rtlwifi-Clean-up-rtl8192d-common-a.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0015-FROMGIT-6.10-wifi-rtlwifi-Clean-up-rtl8192d-common-a.patch new file mode 100644 index 0000000000..779ae4bfee --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0015-FROMGIT-6.10-wifi-rtlwifi-Clean-up-rtl8192d-common-a.patch @@ -0,0 +1,1749 @@ +From 01596bb6b5fa383bd37590981b6cf660ad5d51f4 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 25 Apr 2024 21:14:35 +0300 +Subject: [PATCH 15/69] FROMGIT(6.10): wifi: rtlwifi: Clean up rtl8192d-common + a bit + +Improve readability: + * add empty lines + * use abs_diff in rtl92d_dm_txpower_tracking_callback_thermalmeter + * roll up repeated statements into a for loop in + rtl92d_dm_txpower_tracking_callback_thermalmeter + * shorten lines by replacing many instances of "rtlpriv->dm" with "dm" + pointer in rtl92d_dm_txpower_tracking_callback_thermalmeter + * sort some declarations by length + * refactor _rtl92d_get_txpower_writeval_by_regulatory a little + * refactor _rtl92de_readpowervalue_fromprom a little + +Delete unused structs tag_dynamic_init_gain_operation_type_definition +and swat. + +Simplify rtl92d_fill_h2c_cmd a little and delete a pointless wrapper +function. + +Tested with a single MAC single PHY USB dongle from Aliexpress labelled +"CC&C WL-6210-V3". + +Signed-off-by: Bitterblue Smith +Acked-by: Ping-Ke Shih +Signed-off-by: Ping-Ke Shih +Link: https://msgid.link/f6acfa78-2f4e-47f1-95d4-65aa77510113@gmail.com +--- + .../realtek/rtlwifi/rtl8192d/dm_common.c | 368 +++++++++--------- + .../realtek/rtlwifi/rtl8192d/dm_common.h | 21 - + .../realtek/rtlwifi/rtl8192d/fw_common.c | 132 +++---- + .../realtek/rtlwifi/rtl8192d/hw_common.c | 179 +++++---- + .../realtek/rtlwifi/rtl8192d/phy_common.c | 24 +- + .../wireless/realtek/rtlwifi/rtl8192d/reg.h | 2 + + .../realtek/rtlwifi/rtl8192d/rf_common.c | 156 ++++---- + .../realtek/rtlwifi/rtl8192d/trx_common.c | 11 +- + 8 files changed, 422 insertions(+), 471 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c +index d376e4584454..20373ce998bf 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c +@@ -9,8 +9,6 @@ + #include "phy_common.h" + #include "dm_common.h" + +-#define UNDEC_SM_PWDB entry_min_undec_sm_pwdb +- + static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ +@@ -137,16 +135,18 @@ static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) + 0x05, 0x04, 0x04, 0x03, 0x02 + }; + struct rtl_priv *rtlpriv = rtl_priv(hw); ++ int i, idx; + u32 u4tmp; +- int i; + +- u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter - +- rtlpriv->dm.thermalvalue_rxgain)]) << 12; ++ idx = rtlpriv->efuse.eeprom_thermalmeter - rtlpriv->dm.thermalvalue_rxgain; ++ u4tmp = index_mapping[idx] << 12; ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, + "===> Rx Gain %x\n", u4tmp); ++ + for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) + rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK, +- (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); ++ (rtlpriv->phy.reg_rf3c[i] & ~0xF000) | u4tmp); + } + + static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, +@@ -163,6 +163,7 @@ static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, + temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, + MASKDWORD) & MASKCCK; + rtl92d_release_cckandrw_pagea_ctl(hw, &flag); ++ + for (i = 0; i < CCK_TABLE_LENGTH; i++) { + if (rtlpriv->dm.cck_inch14) + cckswing = &cckswing_table_ch14[i][2]; +@@ -199,6 +200,7 @@ static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, + *internal_pa = rtlefuse->internal_pa_5g[1]; + else + *internal_pa = rtlefuse->internal_pa_5g[i]; ++ + if (*internal_pa) { + if (rtlhal->interfaceindex == 1 || i == rf) + offset = 4; +@@ -213,8 +215,10 @@ static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, + else + offset = 0; + } ++ + if (thermalvalue > rtlefuse->eeprom_thermalmeter) + offset++; ++ + if (*internal_pa) { + if (delta > INDEX_MAPPING_NUM - 1) + index = index_mapping_pa[offset] +@@ -229,6 +233,7 @@ static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, + else + index = index_mapping[offset][delta]; + } ++ + if (thermalvalue > rtlefuse->eeprom_thermalmeter) { + if (*internal_pa && thermalvalue > 0x12) { + ofdm_index[i] = rtlpriv->dm.ofdm_index[i] - +@@ -247,62 +252,67 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + { + static const u8 index_mapping[5][INDEX_MAPPING_NUM] = { + /* 5G, path A/MAC 0, decrease power */ +- {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, ++ {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, + /* 5G, path A/MAC 0, increase power */ +- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, ++ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, + /* 5G, path B/MAC 1, decrease power */ +- {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, ++ {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, + /* 5G, path B/MAC 1, increase power */ +- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, ++ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, + /* 2.4G, for decreas power */ +- {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, ++ {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, + }; + static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = { + /* 5G, path A/MAC 0, ch36-64, decrease power */ +- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, ++ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, + /* 5G, path A/MAC 0, ch36-64, increase power */ +- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, ++ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, + /* 5G, path A/MAC 0, ch100-165, decrease power */ +- {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, ++ {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, + /* 5G, path A/MAC 0, ch100-165, increase power */ +- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, ++ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, + /* 5G, path B/MAC 1, ch36-64, decrease power */ +- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, ++ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, + /* 5G, path B/MAC 1, ch36-64, increase power */ +- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, ++ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, + /* 5G, path B/MAC 1, ch100-165, decrease power */ +- {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, ++ {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, + /* 5G, path B/MAC 1, ch100-165, increase power */ +- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, ++ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, + }; + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); + struct rtl_hal *rtlhal = rtl_hal(rtlpriv); + struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_dm *dm = &rtlpriv->dm; + u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain; ++ u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; ++ long ele_a = 0, ele_d, temp_cck, val_x, value32; ++ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); + u8 offset, thermalvalue_avg_count = 0; ++ u8 ofdm_index_old[2] = {0, 0}; + u32 thermalvalue_avg = 0; + bool internal_pa = false; +- long ele_a = 0, ele_d, temp_cck, val_x, value32; + long val_y, ele_c = 0; ++ s8 cck_index_old = 0; ++ u8 indexforchannel; + u8 ofdm_index[2]; + s8 cck_index = 0; +- u8 ofdm_index_old[2] = {0, 0}; +- s8 cck_index_old = 0; +- u8 index; ++ u8 index, swing; + int i; +- bool is2t = IS_92D_SINGLEPHY(rtlhal->version); +- u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; +- u8 indexforchannel = +- rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); + +- rtlpriv->dm.txpower_trackinginit = true; ++ indexforchannel = rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); ++ ++ dm->txpower_trackinginit = true; ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n"); ++ + thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800); ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, + "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", + thermalvalue, +- rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); ++ dm->thermalvalue, rtlefuse->eeprom_thermalmeter); + + if (!thermalvalue) + goto exit; +@@ -312,10 +322,11 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + else + rf = 1; + +- if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex) ++ if (dm->thermalvalue && !rtlhal->reloadtxpowerindex) + goto old_index_done; + +- ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; ++ ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; ++ + for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { + if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { + ofdm_index_old[0] = (u8)i; +@@ -327,13 +338,15 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + break; + } + } ++ + if (is2t) { +- ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, +- MASKDWORD) & MASKOFDM_D; ++ ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD); ++ ele_d &= MASKOFDM_D; ++ + for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { +- if (ele_d == +- (ofdmswing_table[i] & MASKOFDM_D)) { ++ if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { + ofdm_index_old[1] = (u8)i; ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, + DBG_LOUD, + "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n", +@@ -343,6 +356,7 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + } + } + } ++ + if (rtlhal->current_bandtype == BAND_ON_2_4G) { + rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old); + } else { +@@ -350,115 +364,113 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + cck_index_old = 12; + } + +- if (!rtlpriv->dm.thermalvalue) { +- rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; +- rtlpriv->dm.thermalvalue_lck = thermalvalue; +- rtlpriv->dm.thermalvalue_iqk = thermalvalue; +- rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; ++ if (!dm->thermalvalue) { ++ dm->thermalvalue = rtlefuse->eeprom_thermalmeter; ++ dm->thermalvalue_lck = thermalvalue; ++ dm->thermalvalue_iqk = thermalvalue; ++ dm->thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; ++ + for (i = 0; i < rf; i++) +- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; +- rtlpriv->dm.cck_index = cck_index_old; ++ dm->ofdm_index[i] = ofdm_index_old[i]; ++ ++ dm->cck_index = cck_index_old; + } ++ + if (rtlhal->reloadtxpowerindex) { + for (i = 0; i < rf; i++) +- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; +- rtlpriv->dm.cck_index = cck_index_old; ++ dm->ofdm_index[i] = ofdm_index_old[i]; ++ ++ dm->cck_index = cck_index_old; ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, + "reload ofdm index for band switch\n"); + } ++ + old_index_done: + for (i = 0; i < rf; i++) +- ofdm_index[i] = rtlpriv->dm.ofdm_index[i]; ++ ofdm_index[i] = dm->ofdm_index[i]; ++ ++ dm->thermalvalue_avg[dm->thermalvalue_avg_index] = thermalvalue; ++ dm->thermalvalue_avg_index++; ++ ++ if (dm->thermalvalue_avg_index == AVG_THERMAL_NUM) ++ dm->thermalvalue_avg_index = 0; + +- rtlpriv->dm.thermalvalue_avg +- [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue; +- rtlpriv->dm.thermalvalue_avg_index++; +- if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM) +- rtlpriv->dm.thermalvalue_avg_index = 0; + for (i = 0; i < AVG_THERMAL_NUM; i++) { +- if (rtlpriv->dm.thermalvalue_avg[i]) { +- thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i]; ++ if (dm->thermalvalue_avg[i]) { ++ thermalvalue_avg += dm->thermalvalue_avg[i]; + thermalvalue_avg_count++; + } + } ++ + if (thermalvalue_avg_count) + thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); ++ + if (rtlhal->reloadtxpowerindex) { +- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? +- (thermalvalue - rtlefuse->eeprom_thermalmeter) : +- (rtlefuse->eeprom_thermalmeter - thermalvalue); ++ delta = abs_diff(thermalvalue, rtlefuse->eeprom_thermalmeter); + rtlhal->reloadtxpowerindex = false; +- rtlpriv->dm.done_txpower = false; +- } else if (rtlpriv->dm.done_txpower) { +- delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? +- (thermalvalue - rtlpriv->dm.thermalvalue) : +- (rtlpriv->dm.thermalvalue - thermalvalue); ++ dm->done_txpower = false; ++ } else if (dm->done_txpower) { ++ delta = abs_diff(thermalvalue, dm->thermalvalue); + } else { +- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? +- (thermalvalue - rtlefuse->eeprom_thermalmeter) : +- (rtlefuse->eeprom_thermalmeter - thermalvalue); ++ delta = abs_diff(thermalvalue, rtlefuse->eeprom_thermalmeter); + } +- delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? +- (thermalvalue - rtlpriv->dm.thermalvalue_lck) : +- (rtlpriv->dm.thermalvalue_lck - thermalvalue); +- delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? +- (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : +- (rtlpriv->dm.thermalvalue_iqk - thermalvalue); +- delta_rxgain = +- (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ? +- (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) : +- (rtlpriv->dm.thermalvalue_rxgain - thermalvalue); ++ ++ delta_lck = abs_diff(thermalvalue, dm->thermalvalue_lck); ++ delta_iqk = abs_diff(thermalvalue, dm->thermalvalue_iqk); ++ delta_rxgain = abs_diff(thermalvalue, dm->thermalvalue_rxgain); ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, + "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", +- thermalvalue, rtlpriv->dm.thermalvalue, +- rtlefuse->eeprom_thermalmeter, delta, delta_lck, +- delta_iqk); ++ thermalvalue, dm->thermalvalue, rtlefuse->eeprom_thermalmeter, ++ delta, delta_lck, delta_iqk); ++ + if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) { +- rtlpriv->dm.thermalvalue_lck = thermalvalue; ++ dm->thermalvalue_lck = thermalvalue; + rtlpriv->cfg->ops->phy_lc_calibrate(hw, is2t); + } + +- if (delta == 0 || !rtlpriv->dm.txpower_track_control) ++ if (delta == 0 || !dm->txpower_track_control) + goto check_delta; + +- rtlpriv->dm.done_txpower = true; +- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? +- (thermalvalue - rtlefuse->eeprom_thermalmeter) : +- (rtlefuse->eeprom_thermalmeter - thermalvalue); ++ dm->done_txpower = true; ++ delta = abs_diff(thermalvalue, rtlefuse->eeprom_thermalmeter); ++ + if (rtlhal->current_bandtype == BAND_ON_2_4G) { + offset = 4; + if (delta > INDEX_MAPPING_NUM - 1) + index = index_mapping[offset][INDEX_MAPPING_NUM - 1]; + else + index = index_mapping[offset][delta]; +- if (thermalvalue > rtlpriv->dm.thermalvalue) { ++ ++ if (thermalvalue > dm->thermalvalue) { + for (i = 0; i < rf; i++) + ofdm_index[i] -= delta; ++ + cck_index -= delta; + } else { + for (i = 0; i < rf; i++) + ofdm_index[i] += index; ++ + cck_index += index; + } + } else if (rtlhal->current_bandtype == BAND_ON_5G) { +- rtl92d_bandtype_5G(rtlhal, ofdm_index, +- &internal_pa, thermalvalue, +- delta, rf, rtlefuse, rtlpriv, ++ rtl92d_bandtype_5G(rtlhal, ofdm_index, &internal_pa, ++ thermalvalue, delta, rf, rtlefuse, rtlpriv, + rtlphy, index_mapping, + index_mapping_internal_pa); + } ++ + if (is2t) { + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n", +- rtlpriv->dm.ofdm_index[0], +- rtlpriv->dm.ofdm_index[1], +- rtlpriv->dm.cck_index); ++ "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", ++ dm->ofdm_index[0], dm->ofdm_index[1], dm->cck_index); + } else { + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "temp OFDM_A_index=0x%x,cck_index = 0x%x\n", +- rtlpriv->dm.ofdm_index[0], +- rtlpriv->dm.cck_index); ++ "temp OFDM_A_index=0x%x, cck_index = 0x%x\n", ++ dm->ofdm_index[0], dm->cck_index); + } ++ + for (i = 0; i < rf; i++) { + if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) { + ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1; +@@ -470,25 +482,28 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + ofdm_index[i] = ofdm_min_index; + } + } ++ + if (rtlhal->current_bandtype == BAND_ON_2_4G) { + if (cck_index > CCK_TABLE_SIZE - 1) + cck_index = CCK_TABLE_SIZE - 1; + else if (cck_index < 0) + cck_index = 0; + } ++ + if (is2t) { + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, + "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", +- ofdm_index[0], ofdm_index[1], +- cck_index); ++ ofdm_index[0], ofdm_index[1], cck_index); + } else { + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +- "new OFDM_A_index=0x%x,cck_index = 0x%x\n", ++ "new OFDM_A_index=0x%x, cck_index = 0x%x\n", + ofdm_index[0], cck_index); + } ++ + ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; + val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0]; + val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1]; ++ + if (val_x != 0) { + if ((val_x & 0x00000200) != 0) + val_x = val_x | 0xFFFFFC00; +@@ -507,21 +522,16 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + MASKDWORD, value32); + + value32 = (ele_c & 0x000003C0) >> 6; +- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, +- value32); ++ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, value32); + + value32 = ((val_x * ele_d) >> 7) & 0x01; +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), +- value32); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), value32); + + } else { +- rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, +- MASKDWORD, +- ofdmswing_table[(u8)ofdm_index[0]]); +- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, +- 0x00); +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, +- BIT(24), 0x00); ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, ++ ofdmswing_table[ofdm_index[0]]); ++ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0x00); + } + + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, +@@ -530,109 +540,79 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) + val_x, val_y, ele_a, ele_c, ele_d, + val_x, val_y); + +- if (cck_index >= CCK_TABLE_SIZE) +- cck_index = CCK_TABLE_SIZE - 1; +- if (cck_index < 0) +- cck_index = 0; + if (rtlhal->current_bandtype == BAND_ON_2_4G) { + /* Adjust CCK according to IQK result */ +- if (!rtlpriv->dm.cck_inch14) { +- rtl_write_byte(rtlpriv, 0xa22, +- cckswing_table_ch1ch13[cck_index][0]); +- rtl_write_byte(rtlpriv, 0xa23, +- cckswing_table_ch1ch13[cck_index][1]); +- rtl_write_byte(rtlpriv, 0xa24, +- cckswing_table_ch1ch13[cck_index][2]); +- rtl_write_byte(rtlpriv, 0xa25, +- cckswing_table_ch1ch13[cck_index][3]); +- rtl_write_byte(rtlpriv, 0xa26, +- cckswing_table_ch1ch13[cck_index][4]); +- rtl_write_byte(rtlpriv, 0xa27, +- cckswing_table_ch1ch13[cck_index][5]); +- rtl_write_byte(rtlpriv, 0xa28, +- cckswing_table_ch1ch13[cck_index][6]); +- rtl_write_byte(rtlpriv, 0xa29, +- cckswing_table_ch1ch13[cck_index][7]); +- } else { +- rtl_write_byte(rtlpriv, 0xa22, +- cckswing_table_ch14[cck_index][0]); +- rtl_write_byte(rtlpriv, 0xa23, +- cckswing_table_ch14[cck_index][1]); +- rtl_write_byte(rtlpriv, 0xa24, +- cckswing_table_ch14[cck_index][2]); +- rtl_write_byte(rtlpriv, 0xa25, +- cckswing_table_ch14[cck_index][3]); +- rtl_write_byte(rtlpriv, 0xa26, +- cckswing_table_ch14[cck_index][4]); +- rtl_write_byte(rtlpriv, 0xa27, +- cckswing_table_ch14[cck_index][5]); +- rtl_write_byte(rtlpriv, 0xa28, +- cckswing_table_ch14[cck_index][6]); +- rtl_write_byte(rtlpriv, 0xa29, +- cckswing_table_ch14[cck_index][7]); ++ for (i = 0; i < 8; i++) { ++ if (dm->cck_inch14) ++ swing = cckswing_table_ch14[cck_index][i]; ++ else ++ swing = cckswing_table_ch1ch13[cck_index][i]; ++ ++ rtl_write_byte(rtlpriv, 0xa22 + i, swing); + } + } ++ + if (is2t) { + ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22; + val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4]; + val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5]; ++ + if (val_x != 0) { + if ((val_x & 0x00000200) != 0) + /* consider minus */ + val_x = val_x | 0xFFFFFC00; + ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; ++ + /* new element C = element D x Y */ + if ((val_y & 0x00000200) != 0) + val_y = val_y | 0xFFFFFC00; + ele_c = ((val_y * ele_d) >> 8) & 0x00003FF; ++ + /* write new elements A, C, D to regC88 + * and regC9C, element B is always 0 + */ + value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; +- rtl_set_bbreg(hw, +- ROFDM0_XBTXIQIMBALANCE, ++ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, + MASKDWORD, value32); ++ + value32 = (ele_c & 0x000003C0) >> 6; +- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, +- MASKH4BITS, value32); ++ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32); ++ + value32 = ((val_x * ele_d) >> 7) & 0x01; +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, +- BIT(28), value32); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), value32); + } else { +- rtl_set_bbreg(hw, +- ROFDM0_XBTXIQIMBALANCE, +- MASKDWORD, +- ofdmswing_table[ofdm_index[1]]); +- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, +- MASKH4BITS, 0x00); +- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, +- BIT(28), 0x00); ++ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, ++ MASKDWORD, ofdmswing_table[ofdm_index[1]]); ++ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 0x00); + } ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, + "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n", +- val_x, val_y, ele_a, ele_c, +- ele_d, val_x, val_y); ++ val_x, val_y, ele_a, ele_c, ele_d, val_x, val_y); + } ++ + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, + "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", + rtl_get_bbreg(hw, 0xc80, MASKDWORD), + rtl_get_bbreg(hw, 0xc94, MASKDWORD), +- rtl_get_rfreg(hw, RF90_PATH_A, 0x24, +- RFREG_OFFSET_MASK)); ++ rtl_get_rfreg(hw, RF90_PATH_A, 0x24, RFREG_OFFSET_MASK)); + + check_delta: + if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) { + rtl92d_phy_reset_iqk_result(hw); +- rtlpriv->dm.thermalvalue_iqk = thermalvalue; ++ dm->thermalvalue_iqk = thermalvalue; + rtlpriv->cfg->ops->phy_iq_calibrate(hw); + } ++ + if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G && + thermalvalue <= rtlefuse->eeprom_thermalmeter) { +- rtlpriv->dm.thermalvalue_rxgain = thermalvalue; ++ dm->thermalvalue_rxgain = thermalvalue; + rtl92d_dm_rxgain_tracking_thermalmeter(hw); + } +- if (rtlpriv->dm.txpower_track_control) +- rtlpriv->dm.thermalvalue = thermalvalue; ++ ++ if (dm->txpower_track_control) ++ dm->thermalvalue = thermalvalue; + + exit: + rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); +@@ -675,25 +655,29 @@ EXPORT_SYMBOL_GPL(rtl92d_dm_check_txpower_tracking_thermal_meter); + + void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) + { +- u32 ret_value; + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; + unsigned long flag = 0; ++ u32 ret_value; + + /* hold ofdm counter */ + rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ +- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /* hold page D counter */ + + ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); +- falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); +- falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); ++ falsealm_cnt->cnt_fast_fsync_fail = ret_value & 0xffff; ++ falsealm_cnt->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16; ++ + ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); +- falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); ++ falsealm_cnt->cnt_parity_fail = (ret_value & 0xffff0000) >> 16; ++ + ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); +- falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); +- falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); ++ falsealm_cnt->cnt_rate_illegal = ret_value & 0xffff; ++ falsealm_cnt->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16; ++ + ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); +- falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); ++ falsealm_cnt->cnt_mcs_fail = ret_value & 0xffff; ++ + falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + + falsealm_cnt->cnt_rate_illegal + + falsealm_cnt->cnt_crc8_fail + +@@ -702,7 +686,6 @@ void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) + falsealm_cnt->cnt_sb_search_fail; + + if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { +- /* hold cck counter */ + rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); + ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); + falsealm_cnt->cnt_cck_fail = ret_value; +@@ -713,22 +696,17 @@ void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) + falsealm_cnt->cnt_cck_fail = 0; + } + +- /* reset false alarm counter registers */ +- falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail + +- falsealm_cnt->cnt_sb_search_fail + +- falsealm_cnt->cnt_parity_fail + +- falsealm_cnt->cnt_rate_illegal + +- falsealm_cnt->cnt_crc8_fail + +- falsealm_cnt->cnt_mcs_fail + ++ falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail + + falsealm_cnt->cnt_cck_fail; + ++ /* reset false alarm counter registers */ + rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); +- /* update ofdm counter */ + rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); +- /* update page C counter */ +- rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); +- /* update page D counter */ +- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); ++ ++ /* update ofdm counter */ ++ rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); /* update page C counter */ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); /* update page D counter */ ++ + if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { + /* reset cck counter */ + rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); +@@ -737,16 +715,19 @@ void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) + rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); + rtl92d_release_cckandrw_pagea_ctl(hw, &flag); + } ++ + rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, + "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n", + falsealm_cnt->cnt_fast_fsync_fail, + falsealm_cnt->cnt_sb_search_fail); ++ + rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, + "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n", + falsealm_cnt->cnt_parity_fail, + falsealm_cnt->cnt_rate_illegal, + falsealm_cnt->cnt_crc8_fail, + falsealm_cnt->cnt_mcs_fail); ++ + rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, + "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n", + falsealm_cnt->cnt_ofdm_fail, +@@ -763,7 +744,7 @@ void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) + + /* Determine the minimum RSSI */ + if (mac->link_state < MAC80211_LINKED && +- rtlpriv->dm.UNDEC_SM_PWDB == 0) { ++ rtlpriv->dm.entry_min_undec_sm_pwdb == 0) { + de_digtable->min_undec_pwdb_for_dm = 0; + rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, + "Not connected to any\n"); +@@ -772,19 +753,20 @@ void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) + if (mac->opmode == NL80211_IFTYPE_AP || + mac->opmode == NL80211_IFTYPE_ADHOC) { + de_digtable->min_undec_pwdb_for_dm = +- rtlpriv->dm.UNDEC_SM_PWDB; ++ rtlpriv->dm.entry_min_undec_sm_pwdb; + rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, + "AP Client PWDB = 0x%lx\n", +- rtlpriv->dm.UNDEC_SM_PWDB); ++ rtlpriv->dm.entry_min_undec_sm_pwdb); + } else { + de_digtable->min_undec_pwdb_for_dm = +- rtlpriv->dm.undec_sm_pwdb; ++ rtlpriv->dm.undec_sm_pwdb; + rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, + "STA Default Port PWDB = 0x%x\n", + de_digtable->min_undec_pwdb_for_dm); + } + } else { +- de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB; ++ de_digtable->min_undec_pwdb_for_dm = ++ rtlpriv->dm.entry_min_undec_sm_pwdb; + rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, + "AP Ext Port or disconnect PWDB = 0x%x\n", + de_digtable->min_undec_pwdb_for_dm); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h +index 9dc0df5bb068..a146fc975421 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h +@@ -48,27 +48,6 @@ + #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 + #define INDEX_MAPPING_NUM 13 + +-struct swat { +- u8 failure_cnt; +- u8 try_flag; +- u8 stop_trying; +- long pre_rssi; +- long trying_threshold; +- u8 cur_antenna; +- u8 pre_antenna; +-}; +- +-enum tag_dynamic_init_gain_operation_type_definition { +- DIG_TYPE_THRESH_HIGH = 0, +- DIG_TYPE_THRESH_LOW = 1, +- DIG_TYPE_BACKOFF = 2, +- DIG_TYPE_RX_GAIN_MIN = 3, +- DIG_TYPE_RX_GAIN_MAX = 4, +- DIG_TYPE_ENABLE = 5, +- DIG_TYPE_DISABLE = 6, +- DIG_OP_TYPE_MAX +-}; +- + enum dm_1r_cca { + CCA_1R = 0, + CCA_2R = 1, +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c +index 73cfa9ad78ae..ecdbe3cd5161 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c +@@ -11,8 +11,7 @@ + + bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv) + { +- return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ? +- true : false; ++ return !!(rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY); + } + EXPORT_SYMBOL_GPL(rtl92d_is_fw_downloaded); + +@@ -50,17 +49,22 @@ void rtl92d_write_fw(struct ieee80211_hw *hw, + u32 page, offset; + + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size); ++ + if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) + rtl_fill_dummy(bufferptr, &size); ++ + pagenums = size / FW_8192D_PAGE_SIZE; + remainsize = size % FW_8192D_PAGE_SIZE; ++ + if (pagenums > 8) + pr_err("Page numbers should not greater then 8\n"); ++ + for (page = 0; page < pagenums; page++) { + offset = page * FW_8192D_PAGE_SIZE; + rtl_fw_page_write(hw, page, (bufferptr + offset), + FW_8192D_PAGE_SIZE); + } ++ + if (remainsize) { + offset = pagenums * FW_8192D_PAGE_SIZE; + page = pagenums; +@@ -79,14 +83,17 @@ int rtl92d_fw_free_to_go(struct ieee80211_hw *hw) + value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); + } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) && + (!(value32 & FWDL_CHKSUM_RPT))); ++ + if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) { + pr_err("chksum report fail! REG_MCUFWDL:0x%08x\n", + value32); + return -EIO; + } ++ + value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); + value32 |= MCUFWDL_RDY; + rtl_write_dword(rtlpriv, REG_MCUFWDL, value32); ++ + return 0; + } + EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go); +@@ -99,7 +106,9 @@ void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) + + /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ + rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); ++ + u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); ++ + while (u1b_tmp & BIT(2)) { + delay--; + if (delay == 0) +@@ -174,23 +183,22 @@ static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) + return result; + } + +-static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, +- u8 element_id, u32 cmd_len, u8 *cmdbuffer) ++void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, ++ u8 element_id, u32 cmd_len, u8 *cmdbuffer) + { +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); + struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); +- u8 boxnum; ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 boxcontent[4], boxextcontent[2]; + u16 box_reg = 0, box_extreg = 0; +- u8 u1b_tmp; +- bool isfw_read = false; +- u8 buf_index = 0; ++ u8 wait_writeh2c_limmit = 100; + bool bwrite_success = false; + u8 wait_h2c_limmit = 100; +- u8 wait_writeh2c_limmit = 100; +- u8 boxcontent[4], boxextcontent[2]; + u32 h2c_waitcounter = 0; ++ bool isfw_read = false; + unsigned long flag; ++ u8 u1b_tmp; ++ u8 boxnum; + u8 idx; + + if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) { +@@ -198,7 +206,9 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, + "Return as RF is off!!!\n"); + return; + } ++ + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n"); ++ + while (true) { + spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); + if (rtlhal->h2c_setinprogress) { +@@ -228,35 +238,23 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, + break; + } + } ++ + while (!bwrite_success) { + wait_writeh2c_limmit--; + if (wait_writeh2c_limmit == 0) { + pr_err("Write H2C fail because no trigger for FW INT!\n"); + break; + } ++ + boxnum = rtlhal->last_hmeboxnum; +- switch (boxnum) { +- case 0: +- box_reg = REG_HMEBOX_0; +- box_extreg = REG_HMEBOX_EXT_0; +- break; +- case 1: +- box_reg = REG_HMEBOX_1; +- box_extreg = REG_HMEBOX_EXT_1; +- break; +- case 2: +- box_reg = REG_HMEBOX_2; +- box_extreg = REG_HMEBOX_EXT_2; +- break; +- case 3: +- box_reg = REG_HMEBOX_3; +- box_extreg = REG_HMEBOX_EXT_3; +- break; +- default: +- pr_err("switch case %#x not processed\n", +- boxnum); ++ if (boxnum > 3) { ++ pr_err("boxnum %#x too big\n", boxnum); + break; + } ++ ++ box_reg = REG_HMEBOX_0 + boxnum * SIZE_OF_REG_HMEBOX; ++ box_extreg = REG_HMEBOX_EXT_0 + boxnum * SIZE_OF_REG_HMEBOX_EXT; ++ + isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); + while (!isfw_read) { + wait_h2c_limmit--; +@@ -266,78 +264,70 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, + boxnum); + break; + } ++ + udelay(10); ++ + isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); + u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF); + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, + "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", + boxnum, u1b_tmp); + } ++ + if (!isfw_read) { + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, + "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n", + boxnum); + break; + } ++ + memset(boxcontent, 0, sizeof(boxcontent)); + memset(boxextcontent, 0, sizeof(boxextcontent)); + boxcontent[0] = element_id; ++ + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, + "Write element_id box_reg(%4x) = %2x\n", + box_reg, element_id); ++ + switch (cmd_len) { +- case 1: +- boxcontent[0] &= ~(BIT(7)); +- memcpy(boxcontent + 1, cmdbuffer + buf_index, 1); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- case 2: +- boxcontent[0] &= ~(BIT(7)); +- memcpy(boxcontent + 1, cmdbuffer + buf_index, 2); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- case 3: +- boxcontent[0] &= ~(BIT(7)); +- memcpy(boxcontent + 1, cmdbuffer + buf_index, 3); +- for (idx = 0; idx < 4; idx++) +- rtl_write_byte(rtlpriv, box_reg + idx, +- boxcontent[idx]); +- break; +- case 4: +- boxcontent[0] |= (BIT(7)); +- memcpy(boxextcontent, cmdbuffer + buf_index, 2); +- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2); +- for (idx = 0; idx < 2; idx++) +- rtl_write_byte(rtlpriv, box_extreg + idx, +- boxextcontent[idx]); ++ case 1 ... 3: ++ /* BOX: | ID | A0 | A1 | A2 | ++ * BOX_EXT: --- N/A ------ ++ */ ++ boxcontent[0] &= ~BIT(7); ++ memcpy(boxcontent + 1, cmdbuffer, cmd_len); ++ + for (idx = 0; idx < 4; idx++) + rtl_write_byte(rtlpriv, box_reg + idx, + boxcontent[idx]); + break; +- case 5: +- boxcontent[0] |= (BIT(7)); +- memcpy(boxextcontent, cmdbuffer + buf_index, 2); +- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3); ++ case 4 ... 5: ++ /* * ID ext = ID | BIT(7) ++ * BOX: | ID ext | A2 | A3 | A4 | ++ * BOX_EXT: | A0 | A1 | ++ */ ++ boxcontent[0] |= BIT(7); ++ memcpy(boxextcontent, cmdbuffer, 2); ++ memcpy(boxcontent + 1, cmdbuffer + 2, cmd_len - 2); ++ + for (idx = 0; idx < 2; idx++) + rtl_write_byte(rtlpriv, box_extreg + idx, + boxextcontent[idx]); ++ + for (idx = 0; idx < 4; idx++) + rtl_write_byte(rtlpriv, box_reg + idx, + boxcontent[idx]); + break; + default: +- pr_err("switch case %#x not processed\n", +- cmd_len); ++ pr_err("switch case %#x not processed\n", cmd_len); + break; + } ++ + bwrite_success = true; + rtlhal->last_hmeboxnum = boxnum + 1; + if (rtlhal->last_hmeboxnum == 4) + rtlhal->last_hmeboxnum = 0; ++ + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, + "pHalData->last_hmeboxnum = %d\n", + rtlhal->last_hmeboxnum); +@@ -347,16 +337,6 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, + spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); + rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n"); + } +- +-void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, +- u8 element_id, u32 cmd_len, u8 *cmdbuffer) +-{ +- u32 tmp_cmdbuf[2]; +- +- memset(tmp_cmdbuf, 0, 8); +- memcpy(tmp_cmdbuf, cmdbuffer, cmd_len); +- _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf); +-} + EXPORT_SYMBOL_GPL(rtl92d_fill_h2c_cmd); + + void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +index e70e83252e16..40aadb9c4609 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +@@ -363,10 +363,10 @@ static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) + } + + static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, +- u8 *rom_content, bool autoloadfail) ++ u8 *efuse, bool autoloadfail) + { +- u32 rfpath, eeaddr, group, offset1, offset2; +- u8 i; ++ u32 rfpath, eeaddr, group, offset, offset1, offset2; ++ u8 i, val8; + + memset(pwrinfo, 0, sizeof(struct txpower_info)); + if (autoloadfail) { +@@ -405,98 +405,93 @@ static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, + */ + for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { + for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { +- eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) +- + group; ++ eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) + group; ++ + pwrinfo->cck_index[rfpath][group] = +- (rom_content[eeaddr] == 0xFF) ? +- (eeaddr > 0x7B ? +- EEPROM_DEFAULT_TXPOWERLEVEL_5G : +- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : +- rom_content[eeaddr]; ++ efuse[eeaddr] == 0xFF ? ++ (eeaddr > 0x7B ? ++ EEPROM_DEFAULT_TXPOWERLEVEL_5G : ++ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : ++ efuse[eeaddr]; + } + } + for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { + for (group = 0; group < CHANNEL_GROUP_MAX; group++) { + offset1 = group / 3; + offset2 = group % 3; +- eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + +- offset2 + offset1 * 21; ++ eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3); ++ eeaddr += offset2 + offset1 * 21; ++ + pwrinfo->ht40_1sindex[rfpath][group] = +- (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? +- EEPROM_DEFAULT_TXPOWERLEVEL_5G : +- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : +- rom_content[eeaddr]; ++ efuse[eeaddr] == 0xFF ? ++ (eeaddr > 0x7B ? ++ EEPROM_DEFAULT_TXPOWERLEVEL_5G : ++ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : ++ efuse[eeaddr]; + } + } ++ + /* These just for 92D efuse offset. */ + for (group = 0; group < CHANNEL_GROUP_MAX; group++) { + for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { +- int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; +- + offset1 = group / 3; + offset2 = group % 3; ++ offset = offset2 + offset1 * 21; + +- if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) ++ val8 = efuse[EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G + offset]; ++ if (val8 != 0xFF) + pwrinfo->ht40_2sindexdiff[rfpath][group] = +- (rom_content[base1 + +- offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; ++ (val8 >> (rfpath * 4)) & 0xF; + else + pwrinfo->ht40_2sindexdiff[rfpath][group] = + EEPROM_DEFAULT_HT40_2SDIFF; +- if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 +- + offset1 * 21] != 0xFF) ++ ++ val8 = efuse[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset]; ++ if (val8 != 0xFF) + pwrinfo->ht20indexdiff[rfpath][group] = +- (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G +- + offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; ++ (val8 >> (rfpath * 4)) & 0xF; + else + pwrinfo->ht20indexdiff[rfpath][group] = + EEPROM_DEFAULT_HT20_DIFF; +- if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 +- + offset1 * 21] != 0xFF) ++ ++ val8 = efuse[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset]; ++ if (val8 != 0xFF) + pwrinfo->ofdmindexdiff[rfpath][group] = +- (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G +- + offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; ++ (val8 >> (rfpath * 4)) & 0xF; + else + pwrinfo->ofdmindexdiff[rfpath][group] = + EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; +- if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 +- + offset1 * 21] != 0xFF) ++ ++ val8 = efuse[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset]; ++ if (val8 != 0xFF) + pwrinfo->ht40maxoffset[rfpath][group] = +- (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G +- + offset2 + offset1 * 21] >> (rfpath * 4)) +- & 0xF; ++ (val8 >> (rfpath * 4)) & 0xF; + else + pwrinfo->ht40maxoffset[rfpath][group] = + EEPROM_DEFAULT_HT40_PWRMAXOFFSET; +- if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 +- + offset1 * 21] != 0xFF) ++ ++ val8 = efuse[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset]; ++ if (val8 != 0xFF) + pwrinfo->ht20maxoffset[rfpath][group] = +- (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + +- offset2 + offset1 * 21] >> (rfpath * 4)) & +- 0xF; ++ (val8 >> (rfpath * 4)) & 0xF; + else + pwrinfo->ht20maxoffset[rfpath][group] = + EEPROM_DEFAULT_HT20_PWRMAXOFFSET; + } + } +- if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { ++ ++ if (efuse[EEPROM_TSSI_A_5G] != 0xFF) { + /* 5GL */ +- pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; +- pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; ++ pwrinfo->tssi_a[0] = efuse[EEPROM_TSSI_A_5G] & 0x3F; ++ pwrinfo->tssi_b[0] = efuse[EEPROM_TSSI_B_5G] & 0x3F; + /* 5GM */ +- pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; +- pwrinfo->tssi_b[1] = +- (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | +- (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; ++ pwrinfo->tssi_a[1] = efuse[EEPROM_TSSI_AB_5G] & 0x3F; ++ pwrinfo->tssi_b[1] = (efuse[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | ++ (efuse[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; + /* 5GH */ +- pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & +- 0xF0) >> 4 | +- (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; +- pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & +- 0xFC) >> 2; ++ pwrinfo->tssi_a[2] = (efuse[EEPROM_TSSI_AB_5G + 1] & 0xF0) >> 4 | ++ (efuse[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; ++ pwrinfo->tssi_b[2] = (efuse[EEPROM_TSSI_AB_5G + 2] & 0xFC) >> 2; + } else { + for (i = 0; i < 3; i++) { + pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; +@@ -684,8 +679,6 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) + EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, + EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, + COUNTRY_CODE_WORLD_WIDE_13}; +- int i; +- u16 usvalue; + u8 *hwinfo; + + hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); +@@ -699,12 +692,10 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) + _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); + + /* Read Permanent MAC address for 2nd interface */ +- if (rtlhal->interfaceindex != 0) { +- for (i = 0; i < 6; i += 2) { +- usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; +- *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue; +- } +- } ++ if (rtlhal->interfaceindex != 0) ++ ether_addr_copy(rtlefuse->dev_addr, ++ &hwinfo[EEPROM_MAC_ADDR_MAC1_92D]); ++ + rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, + rtlefuse->dev_addr); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); +@@ -761,22 +752,24 @@ EXPORT_SYMBOL_GPL(rtl92de_read_eeprom_info); + static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, + struct ieee80211_sta *sta) + { ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_phy *rtlphy = &rtlpriv->phy; +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u32 ratr_value; +- u8 ratr_index = 0; +- u8 nmode = mac->ht_enable; ++ enum wireless_mode wirelessmode; + u8 mimo_ps = IEEE80211_SMPS_OFF; +- u16 shortgi_rate; +- u32 tmp_ratr_value; + u8 curtxbw_40mhz = mac->bw_40; +- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? +- 1 : 0; +- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? +- 1 : 0; +- enum wireless_mode wirelessmode = mac->mode; ++ u8 nmode = mac->ht_enable; ++ u8 curshortgi_40mhz; ++ u8 curshortgi_20mhz; ++ u32 tmp_ratr_value; ++ u8 ratr_index = 0; ++ u16 shortgi_rate; ++ u32 ratr_value; ++ ++ curshortgi_40mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); ++ curshortgi_20mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); ++ wirelessmode = mac->mode; + + if (rtlhal->current_bandtype == BAND_ON_5G) + ratr_value = sta->deflink.supp_rates[1] << 4; +@@ -844,27 +837,30 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + struct ieee80211_sta *sta, + u8 rssi_level, bool update_bw) + { ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_phy *rtlphy = &rtlpriv->phy; +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); + struct rtl_sta_info *sta_entry = NULL; ++ enum wireless_mode wirelessmode; ++ bool shortgi = false; ++ u8 curshortgi_40mhz; ++ u8 curshortgi_20mhz; ++ u8 curtxbw_40mhz; + u32 ratr_bitmap; + u8 ratr_index; +- u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; +- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? +- 1 : 0; +- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? +- 1 : 0; +- enum wireless_mode wirelessmode = 0; +- bool shortgi = false; + u32 value[2]; + u8 macid = 0; +- u8 mimo_ps = IEEE80211_SMPS_OFF; ++ u8 mimo_ps; ++ ++ curtxbw_40mhz = sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40; ++ curshortgi_40mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); ++ curshortgi_20mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); + + sta_entry = (struct rtl_sta_info *)sta->drv_priv; + mimo_ps = sta_entry->mimo_ps; + wirelessmode = sta_entry->wireless_mode; ++ + if (mac->opmode == NL80211_IFTYPE_STATION) + curtxbw_40mhz = mac->bw_40; + else if (mac->opmode == NL80211_IFTYPE_AP || +@@ -877,6 +873,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + ratr_bitmap = sta->deflink.supp_rates[0]; + ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | + sta->deflink.ht_cap.mcs.rx_mask[0] << 12); ++ + switch (wirelessmode) { + case WIRELESS_MODE_B: + ratr_index = RATR_INX_WIRELESS_B; +@@ -905,6 +902,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + ratr_index = RATR_INX_WIRELESS_NGB; + else + ratr_index = RATR_INX_WIRELESS_NG; ++ + if (mimo_ps == IEEE80211_SMPS_STATIC) { + if (rssi_level == 1) + ratr_bitmap &= 0x00070000; +@@ -948,6 +946,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + } + } + } ++ + if ((curtxbw_40mhz && curshortgi_40mhz) || + (!curtxbw_40mhz && curshortgi_20mhz)) { + if (macid == 0) +@@ -1065,12 +1064,6 @@ void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, + u8 *p_macaddr, bool is_group, u8 enc_algo, + bool is_wepkey, bool clear_all) + { +- struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- const u8 *macaddr = p_macaddr; +- u32 entry_id; +- bool is_pairwise = false; + static const u8 cam_const_addr[4][6] = { + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, +@@ -1080,6 +1073,12 @@ void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, + static const u8 cam_const_broad[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }; ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ const u8 *macaddr = p_macaddr; ++ bool is_pairwise = false; ++ u32 entry_id; + + if (clear_all) { + u8 idx; +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c +index 87c458b27f4f..dbc8ea39d6fc 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c +@@ -41,8 +41,7 @@ static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, + tmplong & (~BLSSIREADEDGE)); + udelay(10); + rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); +- udelay(50); +- udelay(50); ++ udelay(100); + rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, + tmplong | BLSSIREADEDGE); + udelay(10); +@@ -319,23 +318,21 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) + struct rtl_phy *rtlphy = &rtlpriv->phy; + + rtlphy->default_initialgain[0] = +- (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); ++ rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); + rtlphy->default_initialgain[1] = +- (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); ++ rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); + rtlphy->default_initialgain[2] = +- (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); ++ rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); + rtlphy->default_initialgain[3] = +- (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); ++ rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", + rtlphy->default_initialgain[0], + rtlphy->default_initialgain[1], + rtlphy->default_initialgain[2], + rtlphy->default_initialgain[3]); +- rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, +- MASKBYTE0); +- rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, +- MASKDWORD); ++ rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0); ++ rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, MASKDWORD); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "Default framesync (0x%x) = 0x%x\n", + ROFDM0_RXDETECTOR3, rtlphy->framesync); +@@ -349,7 +346,7 @@ static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, + struct rtl_phy *rtlphy = &rtlpriv->phy; + struct rtl_hal *rtlhal = &rtlpriv->rtlhal; + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +- u8 index = (channel - 1); ++ u8 index = channel - 1; + + /* 1. CCK */ + if (rtlhal->current_bandtype == BAND_ON_2_4G) { +@@ -643,6 +640,7 @@ static void rtl92d_phy_set_io(struct ieee80211_hw *hw) + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, + "--->Cmd(%#x), set_io_inprogress(%d)\n", + rtlphy->current_io_type, rtlphy->set_io_inprogress); ++ + switch (rtlphy->current_io_type) { + case IO_CMD_RESUME_DM_BY_SCAN: + de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; +@@ -659,6 +657,7 @@ static void rtl92d_phy_set_io(struct ieee80211_hw *hw) + rtlphy->current_io_type); + break; + } ++ + rtlphy->set_io_inprogress = false; + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", + rtlphy->current_io_type); +@@ -673,6 +672,7 @@ bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, + "-->IO Cmd(%#x), set_io_inprogress(%d)\n", + iotype, rtlphy->set_io_inprogress); ++ + do { + switch (iotype) { + case IO_CMD_RESUME_DM_BY_SCAN: +@@ -691,12 +691,14 @@ bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) + break; + } + } while (false); ++ + if (postprocessing && !rtlphy->set_io_inprogress) { + rtlphy->set_io_inprogress = true; + rtlphy->current_io_type = iotype; + } else { + return false; + } ++ + rtl92d_phy_set_io(hw); + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); + return true; +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h +index 2783d7e7b227..1dc52abe3d0d 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h +@@ -50,6 +50,7 @@ + #define REG_HMEBOX_EXT_1 0x008A + #define REG_HMEBOX_EXT_2 0x008C + #define REG_HMEBOX_EXT_3 0x008E ++#define SIZE_OF_REG_HMEBOX_EXT 2 + + #define REG_BIST_SCAN 0x00D0 + #define REG_BIST_RPT 0x00D4 +@@ -109,6 +110,7 @@ + #define REG_HMEBOX_1 0x01D4 + #define REG_HMEBOX_2 0x01D8 + #define REG_HMEBOX_3 0x01DC ++#define SIZE_OF_REG_HMEBOX 4 + + #define REG_LLT_INIT 0x01E0 + #define REG_BB_ACCEESS_CTRL 0x01E8 +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c +index 8af166183688..427d1877f431 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c +@@ -16,10 +16,11 @@ void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) + switch (bandwidth) { + case HT_CHANNEL_WIDTH_20: + for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { +- rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval +- [rfpath] & 0xfffff3ff) | 0x0400); +- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | +- BIT(11), 0x01); ++ rtlphy->rfreg_chnlval[rfpath] &= 0xfffff3ff; ++ rtlphy->rfreg_chnlval[rfpath] |= 0x0400; ++ ++ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, ++ BIT(10) | BIT(11), 0x01); + + rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, + "20M RF 0x18 = 0x%x\n", +@@ -29,10 +30,11 @@ void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) + break; + case HT_CHANNEL_WIDTH_20_40: + for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { +- rtlphy->rfreg_chnlval[rfpath] = +- ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff)); +- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), +- 0x00); ++ rtlphy->rfreg_chnlval[rfpath] &= 0xfffff3ff; ++ ++ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, ++ BIT(10) | BIT(11), 0x00); ++ + rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, + "40M RF 0x18 = 0x%x\n", + rtlphy->rfreg_chnlval[rfpath]); +@@ -135,7 +137,7 @@ static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, + legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; + powerbase0 = powerlevel[i] + legacy_pwrdiff; + powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | +- (powerbase0 << 8) | powerbase0; ++ (powerbase0 << 8) | powerbase0; + *(ofdmbase + i) = powerbase0; + RTPRINT(rtlpriv, FPHY, PHY_TXPWR, + " [OFDM power base index rf(%c) = 0x%x]\n", +@@ -157,6 +159,31 @@ static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, + } + } + ++static void _rtl92d_get_pwr_diff_limit(struct ieee80211_hw *hw, u8 channel, ++ u8 index, u8 rf, u8 pwr_diff_limit[4]) ++{ ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u32 mcs_offset; ++ u8 limit; ++ int i; ++ ++ mcs_offset = rtlphy->mcs_offset[0][index + (rf ? 8 : 0)]; ++ ++ for (i = 0; i < 4; i++) { ++ pwr_diff_limit[i] = (mcs_offset >> (i * 8)) & 0x7f; ++ ++ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) ++ limit = rtlefuse->pwrgroup_ht40[rf][channel - 1]; ++ else ++ limit = rtlefuse->pwrgroup_ht20[rf][channel - 1]; ++ ++ if (pwr_diff_limit[i] > limit) ++ pwr_diff_limit[i] = limit; ++ } ++} ++ + static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, + u8 channel, u8 index, + u32 *powerbase0, +@@ -166,107 +193,86 @@ static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_phy *rtlphy = &rtlpriv->phy; +- u8 i, chnlgroup = 0, pwr_diff_limit[4]; + u32 writeval = 0, customer_limit, rf; ++ u8 chnlgroup = 0, pwr_diff_limit[4]; + + for (rf = 0; rf < 2; rf++) { + switch (rtlefuse->eeprom_regulatory) { + case 0: +- chnlgroup = 0; +- writeval = rtlphy->mcs_offset +- [chnlgroup][index + +- (rf ? 8 : 0)] + ((index < 2) ? +- powerbase0[rf] : +- powerbase1[rf]); ++ writeval = rtlphy->mcs_offset[0][index + (rf ? 8 : 0)]; ++ + RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "RTK better performance, writeval(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); ++ "RTK better performance\n"); + break; + case 1: + if (rtlphy->pwrgroup_cnt == 1) + chnlgroup = 0; +- if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) { +- chnlgroup = rtl92d_phy_get_chnlgroup_bypg(channel - 1); +- if (rtlphy->current_chan_bw == +- HT_CHANNEL_WIDTH_20) +- chnlgroup++; +- else +- chnlgroup += 4; +- writeval = rtlphy->mcs_offset +- [chnlgroup][index + +- (rf ? 8 : 0)] + ((index < 2) ? +- powerbase0[rf] : +- powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); +- } ++ ++ if (rtlphy->pwrgroup_cnt < MAX_PG_GROUP) ++ break; ++ ++ chnlgroup = rtl92d_phy_get_chnlgroup_bypg(channel - 1); ++ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) ++ chnlgroup++; ++ else ++ chnlgroup += 4; ++ ++ writeval = rtlphy->mcs_offset ++ [chnlgroup][index + (rf ? 8 : 0)]; ++ ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ++ "Realtek regulatory, 20MHz\n"); + break; + case 2: +- writeval = ((index < 2) ? powerbase0[rf] : +- powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Better regulatory, writeval(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); ++ writeval = 0; ++ ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, "Better regulatory\n"); + break; + case 3: +- chnlgroup = 0; + if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { + RTPRINT(rtlpriv, FPHY, PHY_TXPWR, + "customer's limit, 40MHz rf(%c) = 0x%x\n", + rf == 0 ? 'A' : 'B', +- rtlefuse->pwrgroup_ht40[rf] +- [channel - 1]); ++ rtlefuse->pwrgroup_ht40[rf][channel - 1]); + } else { + RTPRINT(rtlpriv, FPHY, PHY_TXPWR, + "customer's limit, 20MHz rf(%c) = 0x%x\n", + rf == 0 ? 'A' : 'B', +- rtlefuse->pwrgroup_ht20[rf] +- [channel - 1]); +- } +- for (i = 0; i < 4; i++) { +- pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset +- [chnlgroup][index + (rf ? 8 : 0)] & +- (0x7f << (i * 8))) >> (i * 8)); +- if (rtlphy->current_chan_bw == +- HT_CHANNEL_WIDTH_20_40) { +- if (pwr_diff_limit[i] > +- rtlefuse->pwrgroup_ht40[rf] +- [channel - 1]) +- pwr_diff_limit[i] = +- rtlefuse->pwrgroup_ht40 +- [rf][channel - 1]; +- } else { +- if (pwr_diff_limit[i] > +- rtlefuse->pwrgroup_ht20[rf][channel - 1]) +- pwr_diff_limit[i] = +- rtlefuse->pwrgroup_ht20[rf] +- [channel - 1]; +- } ++ rtlefuse->pwrgroup_ht20[rf][channel - 1]); + } ++ ++ _rtl92d_get_pwr_diff_limit(hw, channel, index, rf, ++ pwr_diff_limit); ++ + customer_limit = (pwr_diff_limit[3] << 24) | + (pwr_diff_limit[2] << 16) | + (pwr_diff_limit[1] << 8) | + (pwr_diff_limit[0]); ++ + RTPRINT(rtlpriv, FPHY, PHY_TXPWR, + "Customer's limit rf(%c) = 0x%x\n", + rf == 0 ? 'A' : 'B', customer_limit); +- writeval = customer_limit + ((index < 2) ? +- powerbase0[rf] : powerbase1[rf]); +- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "Customer, writeval rf(%c)= 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); ++ ++ writeval = customer_limit; ++ ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, "Customer\n"); + break; + default: +- chnlgroup = 0; +- writeval = rtlphy->mcs_offset[chnlgroup][index + +- (rf ? 8 : 0)] + ((index < 2) ? +- powerbase0[rf] : powerbase1[rf]); ++ writeval = rtlphy->mcs_offset[0][index + (rf ? 8 : 0)]; ++ + RTPRINT(rtlpriv, FPHY, PHY_TXPWR, +- "RTK better performance, writeval rf(%c) = 0x%x\n", +- rf == 0 ? 'A' : 'B', writeval); ++ "RTK better performance\n"); + break; + } ++ ++ if (index < 2) ++ writeval += powerbase0[rf]; ++ else ++ writeval += powerbase1[rf]; ++ ++ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, "writeval rf(%c)= 0x%x\n", ++ rf == 0 ? 'A' : 'B', writeval); ++ + *(p_outwriteval + rf) = writeval; + } + } +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c +index 5b8f404373ea..72d2b7426d82 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c +@@ -349,14 +349,16 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, + __le32 *pdesc, + struct rx_fwinfo_92d *p_drvinfo) + { +- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); + struct ieee80211_hdr *hdr; ++ bool packet_matchbssid; ++ bool packet_beacon; ++ bool packet_toself; ++ u16 type, cfc; + u8 *tmp_buf; + u8 *praddr; +- u16 type, cfc; + __le16 fc; +- bool packet_matchbssid, packet_toself, packet_beacon = false; + + tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; + hdr = (struct ieee80211_hdr *)tmp_buf; +@@ -372,8 +374,7 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, + (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); + packet_toself = packet_matchbssid && + ether_addr_equal(praddr, rtlefuse->dev_addr); +- if (ieee80211_is_beacon(fc)) +- packet_beacon = true; ++ packet_beacon = ieee80211_is_beacon(fc); + _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, + packet_matchbssid, packet_toself, + packet_beacon); +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0016-FROMGIT-6.10-wifi-rtlwifi-Adjust-rtl8192d-common-for.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0016-FROMGIT-6.10-wifi-rtlwifi-Adjust-rtl8192d-common-for.patch new file mode 100644 index 0000000000..3f9561fed8 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0016-FROMGIT-6.10-wifi-rtlwifi-Adjust-rtl8192d-common-for.patch @@ -0,0 +1,683 @@ +From 7335e62025a7cfe186aab54609b23c4f24d838e0 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 25 Apr 2024 21:15:20 +0300 +Subject: [PATCH 16/69] FROMGIT(6.10): wifi: rtlwifi: Adjust rtl8192d-common + for USB + +A few of the shared functions need small changes for the USB driver: + - firmware loading + - efuse reading + - rate mask updating + - rf register reading + - initial gain for scanning + +Also, add a few macros to wifi.h and initialise rtlhal.interfaceindex +for USB devices. + +Signed-off-by: Bitterblue Smith +Acked-by: Ping-Ke Shih +Signed-off-by: Ping-Ke Shih +Link: https://msgid.link/28100330-f421-4b85-b41b-f1045380cef2@gmail.com +--- + drivers/net/wireless/realtek/rtlwifi/efuse.c | 2 +- + drivers/net/wireless/realtek/rtlwifi/efuse.h | 2 +- + .../realtek/rtlwifi/rtl8192d/fw_common.c | 23 ++- + .../realtek/rtlwifi/rtl8192d/fw_common.h | 10 ++ + .../realtek/rtlwifi/rtl8192d/hw_common.c | 61 +++++-- + .../realtek/rtlwifi/rtl8192d/phy_common.c | 22 ++- + .../realtek/rtlwifi/rtl8192d/phy_common.h | 24 +++ + .../wireless/realtek/rtlwifi/rtl8192d/reg.h | 160 +++++++++++++++--- + drivers/net/wireless/realtek/rtlwifi/usb.c | 3 + + drivers/net/wireless/realtek/rtlwifi/wifi.h | 5 + + 10 files changed, 268 insertions(+), 44 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/efuse.c b/drivers/net/wireless/realtek/rtlwifi/efuse.c +index c1fbc29d5ca1..82cf5fb5175f 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/efuse.c ++++ b/drivers/net/wireless/realtek/rtlwifi/efuse.c +@@ -1211,7 +1211,7 @@ static u8 efuse_calculate_word_cnts(u8 word_en) + } + + int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, +- int max_size, u8 *hwinfo, int *params) ++ int max_size, u8 *hwinfo, const int *params) + { + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); + struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); +diff --git a/drivers/net/wireless/realtek/rtlwifi/efuse.h b/drivers/net/wireless/realtek/rtlwifi/efuse.h +index 4821625ad1e5..e250ffb0f4b2 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/efuse.h ++++ b/drivers/net/wireless/realtek/rtlwifi/efuse.h +@@ -89,7 +89,7 @@ void efuse_force_write_vendor_id(struct ieee80211_hw *hw); + void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx); + void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate); + int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, +- int max_size, u8 *hwinfo, int *params); ++ int max_size, u8 *hwinfo, const int *params); + void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen); + void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, u8 *buffer, + u32 size); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c +index ecdbe3cd5161..aa54dbde6ea8 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c +@@ -98,24 +98,45 @@ int rtl92d_fw_free_to_go(struct ieee80211_hw *hw) + } + EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go); + ++#define RTL_USB_DELAY_FACTOR 60 ++ + void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); + u8 u1b_tmp; + u8 delay = 100; + ++ if (rtlhal->interface == INTF_USB) { ++ delay *= RTL_USB_DELAY_FACTOR; ++ ++ rtl_write_byte(rtlpriv, REG_FSIMR, 0); ++ ++ /* We need to disable other HRCV INT to influence 8051 reset. */ ++ rtl_write_byte(rtlpriv, REG_FWIMR, 0x20); ++ ++ /* Close mask to prevent incorrect FW write operation. */ ++ rtl_write_byte(rtlpriv, REG_FTIMR, 0); ++ } ++ + /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ + rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); + + u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); + +- while (u1b_tmp & BIT(2)) { ++ while (u1b_tmp & (FEN_CPUEN >> 8)) { + delay--; + if (delay == 0) + break; + udelay(50); + u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); + } ++ ++ if (rtlhal->interface == INTF_USB) { ++ if ((u1b_tmp & (FEN_CPUEN >> 8)) && delay == 0) ++ rtl_write_byte(rtlpriv, REG_FWIMR, 0); ++ } ++ + WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, + "=====> 8051 reset success (%d)\n", delay); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h +index 4e8e2b716f88..4b73e0bd4ac4 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h +@@ -25,6 +25,16 @@ + #define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \ + le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(23, 16)) + ++#define RAID_MASK GENMASK(31, 28) ++#define RATE_MASK_MASK GENMASK(27, 0) ++#define SHORT_GI_MASK BIT(5) ++#define MACID_MASK GENMASK(4, 0) ++ ++struct rtl92d_rate_mask_h2c { ++ __le32 rate_mask_and_raid; ++ u8 macid_and_short_gi; ++} __packed; ++ + bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv); + void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable); + void rtl92d_write_fw(struct ieee80211_hw *hw, +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +index 40aadb9c4609..920bfb4eaaef 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +@@ -618,9 +618,14 @@ static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; ++ bool is_single_mac = true; + +- if (macphy_crvalue & BIT(3)) { ++ if (rtlhal->interface == INTF_PCI) ++ is_single_mac = !!(content[EEPROM_MAC_FUNCTION] & BIT(3)); ++ else if (rtlhal->interface == INTF_USB) ++ is_single_mac = !(content[EEPROM_ENDPOINT_SETTING] & BIT(0)); ++ ++ if (is_single_mac) { + rtlhal->macphymode = SINGLEMAC_SINGLEPHY; + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "MacPhyMode SINGLEMAC_SINGLEPHY\n"); +@@ -659,6 +664,7 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); + break; + case 0xCC33: ++ case 0x33CC: + chipver |= CHIP_92D_E_CUT; + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); + break; +@@ -672,15 +678,27 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) + + static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) + { ++ static const int params_pci[] = { ++ RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, ++ EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, ++ EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, ++ COUNTRY_CODE_WORLD_WIDE_13 ++ }; ++ static const int params_usb[] = { ++ RTL8190_EEPROM_ID, EEPROM_VID_USB, EEPROM_PID_USB, ++ EEPROM_VID_USB, EEPROM_PID_USB, EEPROM_MAC_ADDR_MAC0_92DU, ++ EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, ++ COUNTRY_CODE_WORLD_WIDE_13 ++ }; + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +- int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, +- EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, +- EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, +- COUNTRY_CODE_WORLD_WIDE_13}; ++ const int *params = params_pci; + u8 *hwinfo; + ++ if (rtlhal->interface == INTF_USB) ++ params = params_usb; ++ + hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); + if (!hwinfo) + return; +@@ -842,6 +860,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_phy *rtlphy = &rtlpriv->phy; + struct rtl_sta_info *sta_entry = NULL; ++ struct rtl92d_rate_mask_h2c rate_mask; + enum wireless_mode wirelessmode; + bool shortgi = false; + u8 curshortgi_40mhz; +@@ -849,7 +868,6 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + u8 curtxbw_40mhz; + u32 ratr_bitmap; + u8 ratr_index; +- u32 value[2]; + u8 macid = 0; + u8 mimo_ps; + +@@ -965,12 +983,28 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + break; + } + +- value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); +- value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; ++ le32p_replace_bits(&rate_mask.rate_mask_and_raid, ratr_bitmap, RATE_MASK_MASK); ++ le32p_replace_bits(&rate_mask.rate_mask_and_raid, ratr_index, RAID_MASK); ++ u8p_replace_bits(&rate_mask.macid_and_short_gi, macid, MACID_MASK); ++ u8p_replace_bits(&rate_mask.macid_and_short_gi, shortgi, SHORT_GI_MASK); ++ u8p_replace_bits(&rate_mask.macid_and_short_gi, 1, BIT(7)); ++ + rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, +- "ratr_bitmap :%x value0:%x value1:%x\n", +- ratr_bitmap, value[0], value[1]); +- rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *)value); ++ "Rate_index:%x, ratr_val:%x, %5phC\n", ++ ratr_index, ratr_bitmap, &rate_mask); ++ ++ if (rtlhal->interface == INTF_PCI) { ++ rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, sizeof(rate_mask), ++ (u8 *)&rate_mask); ++ } else { ++ /* rtl92d_fill_h2c_cmd() does USB I/O and will result in a ++ * "scheduled while atomic" if called directly ++ */ ++ memcpy(rtlpriv->rate_mask, &rate_mask, ++ sizeof(rtlpriv->rate_mask)); ++ schedule_work(&rtlpriv->works.fill_h2c_cmd); ++ } ++ + if (macid != 0) + sta_entry->ratr_index = ratr_index; + } +@@ -1014,7 +1048,8 @@ bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) + bool actuallyset = false; + unsigned long flag; + +- if (rtlpci->being_init_adapter) ++ if (rtlpriv->rtlhal.interface == INTF_PCI && ++ rtlpci->being_init_adapter) + return false; + if (ppsc->swrf_processing) + return false; +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c +index dbc8ea39d6fc..228c84ab5b90 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c +@@ -89,11 +89,11 @@ u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, + rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, + "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", + regaddr, rfpath, bitmask); +- spin_lock(&rtlpriv->locks.rf_lock); ++ rtl92d_pci_lock(rtlpriv); + original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); + bitshift = calculate_bit_shift(bitmask); + readback_value = (original_value & bitmask) >> bitshift; +- spin_unlock(&rtlpriv->locks.rf_lock); ++ rtl92d_pci_unlock(rtlpriv); + rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, + "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", + regaddr, rfpath, bitmask, original_value); +@@ -113,7 +113,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, + regaddr, bitmask, data, rfpath); + if (bitmask == 0) + return; +- spin_lock(&rtlpriv->locks.rf_lock); ++ rtl92d_pci_lock(rtlpriv); + if (rtlphy->rf_mode != RF_OP_BY_FW) { + if (bitmask != RFREG_OFFSET_MASK) { + original_value = _rtl92d_phy_rf_serial_read(hw, +@@ -125,7 +125,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, + } + _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); + } +- spin_unlock(&rtlpriv->locks.rf_lock); ++ rtl92d_pci_unlock(rtlpriv); + rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, + "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", + regaddr, bitmask, data, rfpath); +@@ -650,6 +650,8 @@ static void rtl92d_phy_set_io(struct ieee80211_hw *hw) + case IO_CMD_PAUSE_DM_BY_SCAN: + rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; + de_digtable->cur_igvalue = 0x37; ++ if (rtlpriv->rtlhal.interface == INTF_USB) ++ de_digtable->cur_igvalue = 0x17; + rtl92d_dm_write_dig(hw); + break; + default: +@@ -710,22 +712,28 @@ void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); + u8 offset = REG_MAC_PHY_CTRL_NORMAL; ++ u8 phy_ctrl = 0xf0; ++ ++ if (rtlhal->interface == INTF_USB) { ++ phy_ctrl = rtl_read_byte(rtlpriv, offset); ++ phy_ctrl &= ~(BIT(0) | BIT(1) | BIT(2)); ++ } + + switch (rtlhal->macphymode) { + case DUALMAC_DUALPHY: + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "MacPhyMode: DUALMAC_DUALPHY\n"); +- rtl_write_byte(rtlpriv, offset, 0xF3); ++ rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0) | BIT(1)); + break; + case SINGLEMAC_SINGLEPHY: + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); +- rtl_write_byte(rtlpriv, offset, 0xF4); ++ rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(2)); + break; + case DUALMAC_SINGLEPHY: + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "MacPhyMode: DUALMAC_SINGLEPHY\n"); +- rtl_write_byte(rtlpriv, offset, 0xF1); ++ rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0)); + break; + } + } +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h +index f9b5d0d3a7e6..0f794557af47 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h +@@ -32,6 +32,9 @@ static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + ++ if (rtlpriv->rtlhal.interface == INTF_USB) ++ return; ++ + if (rtlpriv->rtlhal.interfaceindex == 1) + spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag); + } +@@ -41,6 +44,9 @@ static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + ++ if (rtlpriv->rtlhal.interface == INTF_USB) ++ return; ++ + if (rtlpriv->rtlhal.interfaceindex == 1) + spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock, + *flag); +@@ -84,4 +90,22 @@ void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, + void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, + unsigned long *flag); + ++/* Without these helpers and the declarations sparse warns about ++ * context imbalance. ++ */ ++static inline void rtl92d_pci_lock(struct rtl_priv *rtlpriv) ++{ ++ if (rtlpriv->rtlhal.interface == INTF_PCI) ++ spin_lock(&rtlpriv->locks.rf_lock); ++} ++ ++static inline void rtl92d_pci_unlock(struct rtl_priv *rtlpriv) ++{ ++ if (rtlpriv->rtlhal.interface == INTF_PCI) ++ spin_unlock(&rtlpriv->locks.rf_lock); ++} ++ ++void rtl92d_pci_lock(struct rtl_priv *rtlpriv); ++void rtl92d_pci_unlock(struct rtl_priv *rtlpriv); ++ + #endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h +index 1dc52abe3d0d..b5b906b799cb 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h +@@ -52,6 +52,8 @@ + #define REG_HMEBOX_EXT_3 0x008E + #define SIZE_OF_REG_HMEBOX_EXT 2 + ++#define REG_EFUSE_ACCESS 0x00CF ++ + #define REG_BIST_SCAN 0x00D0 + #define REG_BIST_RPT 0x00D4 + #define REG_BIST_ROM_RPT 0x00D8 +@@ -87,6 +89,7 @@ + #define REG_CPWM 0x012F + #define REG_FWIMR 0x0130 + #define REG_FWISR 0x0134 ++#define REG_FTIMR 0x0138 + #define REG_PKTBUF_DBG_CTRL 0x0140 + #define REG_PKTBUF_DBG_DATA_L 0x0144 + #define REG_PKTBUF_DBG_DATA_H 0x0148 +@@ -199,6 +202,8 @@ + #define REG_POWER_STAGE1 0x04B4 + #define REG_POWER_STAGE2 0x04B8 + #define REG_PKT_LIFE_TIME 0x04C0 ++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 ++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 + #define REG_STBC_SETTING 0x04C4 + #define REG_PROT_MODE_CTRL 0x04C8 + #define REG_MAX_AGGR_NUM 0x04CA +@@ -235,6 +240,7 @@ + #define REG_RD_NAV_NXT 0x0544 + #define REG_NAV_PROT_LEN 0x0546 + #define REG_BCN_CTRL 0x0550 ++#define REG_BCN_CTRL_1 0x0551 + #define REG_MBID_NUM 0x0552 + #define REG_DUAL_TSF_RST 0x0553 + #define REG_BCN_INTERVAL 0x0554 +@@ -321,6 +327,8 @@ + #define REG_BT_COEX_TABLE 0x06C0 + #define REG_WMAC_RESP_TXINFO 0x06D8 + ++#define REG_USB_Queue_Select_MAC0 0xFE44 ++#define REG_USB_Queue_Select_MAC1 0xFE47 + + /* ----------------------------------------------------- */ + /* Redifine 8192C register definition for compatibility */ +@@ -357,27 +365,27 @@ + #define RRSR_RSC_UPSUBCHNL 0x400000 + #define RRSR_RSC_LOWSUBCHNL 0x200000 + #define RRSR_SHORT 0x800000 +-#define RRSR_1M BIT0 +-#define RRSR_2M BIT1 +-#define RRSR_5_5M BIT2 +-#define RRSR_11M BIT3 +-#define RRSR_6M BIT4 +-#define RRSR_9M BIT5 +-#define RRSR_12M BIT6 +-#define RRSR_18M BIT7 +-#define RRSR_24M BIT8 +-#define RRSR_36M BIT9 +-#define RRSR_48M BIT10 +-#define RRSR_54M BIT11 +-#define RRSR_MCS0 BIT12 +-#define RRSR_MCS1 BIT13 +-#define RRSR_MCS2 BIT14 +-#define RRSR_MCS3 BIT15 +-#define RRSR_MCS4 BIT16 +-#define RRSR_MCS5 BIT17 +-#define RRSR_MCS6 BIT18 +-#define RRSR_MCS7 BIT19 +-#define BRSR_ACKSHORTPMB BIT23 ++#define RRSR_1M BIT(0) ++#define RRSR_2M BIT(1) ++#define RRSR_5_5M BIT(2) ++#define RRSR_11M BIT(3) ++#define RRSR_6M BIT(4) ++#define RRSR_9M BIT(5) ++#define RRSR_12M BIT(6) ++#define RRSR_18M BIT(7) ++#define RRSR_24M BIT(8) ++#define RRSR_36M BIT(9) ++#define RRSR_48M BIT(10) ++#define RRSR_54M BIT(11) ++#define RRSR_MCS0 BIT(12) ++#define RRSR_MCS1 BIT(13) ++#define RRSR_MCS2 BIT(14) ++#define RRSR_MCS3 BIT(15) ++#define RRSR_MCS4 BIT(16) ++#define RRSR_MCS5 BIT(17) ++#define RRSR_MCS6 BIT(18) ++#define RRSR_MCS7 BIT(19) ++#define BRSR_ACKSHORTPMB BIT(23) + + /* ----------------------------------------------------- */ + /* 8192C Rate Definition */ +@@ -602,7 +610,11 @@ + #define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */ + #define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */ + ++#define EEPROM_VID_USB 0xC ++#define EEPROM_PID_USB 0xE ++#define EEPROM_ENDPOINT_SETTING 0x10 + #define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */ ++#define EEPROM_MAC_ADDR_MAC0_92DU 0x19 + #define EEPROM_MAC_ADDR_MAC0_92D 0x55 + #define EEPROM_MAC_ADDR_MAC1_92D 0x5B + +@@ -917,6 +929,42 @@ + #define BD_HCI_SEL BIT(26) + #define TYPE_ID BIT(27) + ++#define HCI_TXDMA_EN BIT(0) ++#define HCI_RXDMA_EN BIT(1) ++#define TXDMA_EN BIT(2) ++#define RXDMA_EN BIT(3) ++#define PROTOCOL_EN BIT(4) ++#define SCHEDULE_EN BIT(5) ++#define MACTXEN BIT(6) ++#define MACRXEN BIT(7) ++#define ENSWBCN BIT(8) ++#define ENSEC BIT(9) ++ ++#define HQSEL_VOQ BIT(0) ++#define HQSEL_VIQ BIT(1) ++#define HQSEL_BEQ BIT(2) ++#define HQSEL_BKQ BIT(3) ++#define HQSEL_MGTQ BIT(4) ++#define HQSEL_HIQ BIT(5) ++ ++#define TXDMA_HIQ_MAP GENMASK(15, 14) ++#define TXDMA_MGQ_MAP GENMASK(13, 12) ++#define TXDMA_BKQ_MAP GENMASK(11, 10) ++#define TXDMA_BEQ_MAP GENMASK(9, 8) ++#define TXDMA_VIQ_MAP GENMASK(7, 6) ++#define TXDMA_VOQ_MAP GENMASK(5, 4) ++ ++#define QUEUE_LOW 1 ++#define QUEUE_NORMAL 2 ++#define QUEUE_HIGH 3 ++ ++#define HPQ_MASK GENMASK(7, 0) ++#define LPQ_MASK GENMASK(15, 8) ++#define PUBQ_MASK GENMASK(23, 16) ++#define LD_RQPN BIT(31) ++ ++#define DROP_DATA_EN BIT(9) ++ + /* LLT_INIT */ + #define _LLT_NO_ACTIVE 0x0 + #define _LLT_WRITE_ACCESS 0x1 +@@ -931,6 +979,10 @@ + /* ----------------------------------------------------- */ + /* 0x0400h ~ 0x047Fh Protocol Configuration */ + /* ----------------------------------------------------- */ ++/* FWHW_TXQ_CTRL */ ++#define EN_AMPDU_RTY_NEW BIT(7) ++#define EN_BCNQ_DL BIT(22) ++ + #define RETRY_LIMIT_SHORT_SHIFT 8 + #define RETRY_LIMIT_LONG_SHIFT 0 + +@@ -944,6 +996,13 @@ + #define AC_PARAM_ECW_MIN_OFFSET 8 + #define AC_PARAM_AIFS_OFFSET 0 + ++/* REG_RD_CTRL */ ++#define DIS_EDCA_CNT_DWN BIT(11) ++ ++/* REG_BCN_CTRL */ ++#define EN_BCN_FUNCTION BIT(3) ++#define DIS_TSF_UDT BIT(4) ++ + /* ACMHWCTRL */ + #define ACMHW_HWEN BIT(0) + #define ACMHW_BEQEN BIT(1) +@@ -1075,6 +1134,11 @@ + #define RCCK0_FACOUNTERLOWER 0xa5c + #define RCCK0_FACOUNTERUPPER 0xa58 + ++#define RPDP_ANTA 0xb00 ++#define RCONFIG_ANTA 0xb68 ++#define RCONFIG_ANTB 0xb6c ++#define RPDP_ANTB 0xb70 ++ + /* 6. PageC(0xC00) */ + #define ROFDM0_LSTF 0xc00 + +@@ -1128,6 +1192,7 @@ + #define ROFDM0_TXPSEUDONOISEWGT 0xce4 + #define ROFDM0_FRAMESYNC 0xcf0 + #define ROFDM0_DFSREPORT 0xcf4 ++#define ROFDM0_RXIQEXTANTA 0xca0 + #define ROFDM0_TXCOEFF1 0xca4 + #define ROFDM0_TXCOEFF2 0xca8 + #define ROFDM0_TXCOEFF3 0xcac +@@ -1186,17 +1251,70 @@ + #define RTXAGC_B_MCS15_MCS12 0x868 + #define RTXAGC_B_CCK11_A_CCK2_11 0x86c + ++#define RFPGA0_IQK 0xe28 ++#define RTX_IQK_TONE_A 0xe30 ++#define RRX_IQK_TONE_A 0xe34 ++#define RTX_IQK_PI_A 0xe38 ++#define RRX_IQK_PI_A 0xe3c ++ ++#define RTX_IQK 0xe40 ++#define RRX_IQK 0xe44 ++#define RIQK_AGC_PTS 0xe48 ++#define RIQK_AGC_RSP 0xe4c ++#define RTX_IQK_TONE_B 0xe50 ++#define RRX_IQK_TONE_B 0xe54 ++#define RTX_IQK_PI_B 0xe58 ++#define RRX_IQK_PI_B 0xe5c ++#define RIQK_AGC_CONT 0xe60 ++ ++#define RBLUE_TOOTH 0xe6c ++#define RRX_WAIT_CCA 0xe70 ++#define RTX_CCK_RFON 0xe74 ++#define RTX_CCK_BBON 0xe78 ++#define RTX_OFDM_RFON 0xe7c ++#define RTX_OFDM_BBON 0xe80 ++#define RTX_TO_RX 0xe84 ++#define RTX_TO_TX 0xe88 ++#define RRX_CCK 0xe8c ++ ++#define RTX_POWER_BEFORE_IQK_A 0xe94 ++#define RTX_POWER_AFTER_IQK_A 0xe9c ++ ++#define RRX_POWER_BEFORE_IQK_A 0xea0 ++#define RRX_POWER_BEFORE_IQK_A_2 0xea4 ++#define RRX_POWER_AFTER_IQK_A 0xea8 ++#define RRX_POWER_AFTER_IQK_A_2 0xeac ++ ++#define RTX_POWER_BEFORE_IQK_B 0xeb4 ++#define RTX_POWER_AFTER_IQK_B 0xebc ++ ++#define RRX_POWER_BEFORE_IQK_B 0xec0 ++#define RRX_POWER_BEFORE_IQK_B_2 0xec4 ++#define RRX_POWER_AFTER_IQK_B 0xec8 ++#define RRX_POWER_AFTER_IQK_B_2 0xecc ++ ++#define MASK_IQK_RESULT 0x03ff0000 ++ ++#define RRX_OFDM 0xed0 ++#define RRX_WAIT_RIFS 0xed4 ++#define RRX_TO_RX 0xed8 ++#define RSTANDBY 0xedc ++#define RSLEEP 0xee0 ++#define RPMPD_ANAEN 0xeec ++ + /* RL6052 Register definition */ + #define RF_AC 0x00 + + #define RF_IQADJ_G1 0x01 + #define RF_IQADJ_G2 0x02 ++#define RF_BS_PA_APSET_G1_G4 0x03 + #define RF_POW_TRSW 0x05 + + #define RF_GAIN_RX 0x06 + #define RF_GAIN_TX 0x07 + + #define RF_TXM_IDAC 0x08 ++#define RF_TXPA_AG 0x0B + #define RF_BS_IQGEN 0x0F + + #define RF_MODE1 0x10 +diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c +index 6e8c87a2fae4..2ea72d9e3957 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/usb.c ++++ b/drivers/net/wireless/realtek/rtlwifi/usb.c +@@ -979,6 +979,9 @@ int rtl_usb_probe(struct usb_interface *intf, + usb_priv->dev.intf = intf; + usb_priv->dev.udev = udev; + usb_set_intfdata(intf, hw); ++ /* For dual MAC RTL8192DU, which has two interfaces. */ ++ rtlpriv->rtlhal.interfaceindex = ++ intf->altsetting[0].desc.bInterfaceNumber; + /* init cfg & intf_ops */ + rtlpriv->rtlhal.interface = INTF_USB; + rtlpriv->cfg = rtl_hal_cfg; +diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h +index 098db85e381c..4f1c21c130f4 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/wifi.h ++++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h +@@ -20,6 +20,7 @@ + #define MASKBYTE1 0xff00 + #define MASKBYTE2 0xff0000 + #define MASKBYTE3 0xff000000 ++#define MASKH3BYTES 0xffffff00 + #define MASKHWORD 0xffff0000 + #define MASKLWORD 0x0000ffff + #define MASKDWORD 0xffffffff +@@ -48,6 +49,10 @@ + #define MASK20BITS 0xfffff + #define RFREG_OFFSET_MASK 0xfffff + ++/* For dual MAC RTL8192DU */ ++#define MAC0_ACCESS_PHY1 0x4000 ++#define MAC1_ACCESS_PHY0 0x2000 ++ + #define RF_CHANGE_BY_INIT 0 + #define RF_CHANGE_BY_IPS BIT(28) + #define RF_CHANGE_BY_PS BIT(29) +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0017-FROMGIT-6.10-wifi-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0017-FROMGIT-6.10-wifi-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch new file mode 100644 index 0000000000..6bf0f71a6a --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0017-FROMGIT-6.10-wifi-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch @@ -0,0 +1,52 @@ +From d34a7e456b723f5b5b11834abd39f46352d2b776 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Wed, 29 May 2024 20:19:47 +0300 +Subject: [PATCH 17/69] FROMGIT(6.10): wifi: rtlwifi: Ignore + IEEE80211_CONF_CHANGE_RETRY_LIMITS + +Since commit 0a44dfc07074 ("wifi: mac80211: simplify non-chanctx +drivers") ieee80211_hw_config() is no longer called with changed = ~0. +rtlwifi relied on ~0 in order to ignore the default retry limits of +4/7, preferring 48/48 in station mode and 7/7 in AP/IBSS. + +RTL8192DU has a lot of packet loss with the default limits from +mac80211. Fix it by ignoring IEEE80211_CONF_CHANGE_RETRY_LIMITS +completely, because it's the simplest solution. + +Link: https://lore.kernel.org/linux-wireless/cedd13d7691f4692b2a2fa5a24d44a22@realtek.com/ +Cc: stable@vger.kernel.org # 6.9.x +Signed-off-by: Bitterblue Smith +Acked-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtlwifi/core.c | 15 --------------- + 1 file changed, 15 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/core.c b/drivers/net/wireless/realtek/rtlwifi/core.c +index 2e60a6991ca1..42b7db12b1bd 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/core.c ++++ b/drivers/net/wireless/realtek/rtlwifi/core.c +@@ -633,21 +633,6 @@ static int rtl_op_config(struct ieee80211_hw *hw, u32 changed) + } + } + +- if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { +- rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, +- "IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n", +- hw->conf.long_frame_max_tx_count); +- /* brought up everything changes (changed == ~0) indicates first +- * open, so use our default value instead of that of wiphy. +- */ +- if (changed != ~0) { +- mac->retry_long = hw->conf.long_frame_max_tx_count; +- mac->retry_short = hw->conf.long_frame_max_tx_count; +- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, +- (u8 *)(&hw->conf.long_frame_max_tx_count)); +- } +- } +- + if (changed & IEEE80211_CONF_CHANGE_CHANNEL && + !rtlpriv->proximity.proxim_on) { + struct ieee80211_channel *channel = hw->conf.chandef.chan; +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0018-FROMGIT-6.11-wifi-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0018-FROMGIT-6.11-wifi-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch new file mode 100644 index 0000000000..a4b6a3aade --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0018-FROMGIT-6.11-wifi-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch @@ -0,0 +1,701 @@ +From dec5fc45e4b69ac5c4c628fa9e482199d6e5ad71 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:43:37 +0300 +Subject: [PATCH 18/69] FROMGIT(6.11): wifi: rtlwifi: rtl8192d: Use "rtl92d" + prefix + +Some functions moved from rtl8192de still use the "rtl92de" prefix. +Rename them. + +Signed-off-by: Bitterblue Smith +--- + .../realtek/rtlwifi/rtl8192d/hw_common.c | 94 +++++++++---------- + .../realtek/rtlwifi/rtl8192d/hw_common.h | 28 +++--- + .../realtek/rtlwifi/rtl8192d/trx_common.c | 92 +++++++++--------- + .../realtek/rtlwifi/rtl8192d/trx_common.h | 16 ++-- + .../wireless/realtek/rtlwifi/rtl8192de/hw.c | 18 ++-- + .../wireless/realtek/rtlwifi/rtl8192de/sw.c | 20 ++-- + .../wireless/realtek/rtlwifi/rtl8192de/trx.c | 2 +- + 7 files changed, 135 insertions(+), 135 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +index 920bfb4eaaef..3b14eec08b64 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c +@@ -14,7 +14,7 @@ + #include "hw_common.h" + #include "phy_common.h" + +-void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) ++void rtl92d_stop_tx_beacon(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + u8 tmp1byte; +@@ -27,9 +27,9 @@ void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) + tmp1byte &= ~(BIT(0)); + rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); + } +-EXPORT_SYMBOL_GPL(rtl92de_stop_tx_beacon); ++EXPORT_SYMBOL_GPL(rtl92d_stop_tx_beacon); + +-void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) ++void rtl92d_resume_tx_beacon(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + u8 tmp1byte; +@@ -42,7 +42,7 @@ void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) + tmp1byte |= BIT(0); + rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); + } +-EXPORT_SYMBOL_GPL(rtl92de_resume_tx_beacon); ++EXPORT_SYMBOL_GPL(rtl92d_resume_tx_beacon); + + void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + { +@@ -285,7 +285,7 @@ void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + } + EXPORT_SYMBOL_GPL(rtl92d_set_hw_reg); + +-bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) ++bool rtl92d_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + bool status = true; +@@ -307,9 +307,9 @@ bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) + } while (++count); + return status; + } +-EXPORT_SYMBOL_GPL(rtl92de_llt_write); ++EXPORT_SYMBOL_GPL(rtl92d_llt_write); + +-void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) ++void rtl92d_enable_hw_security_config(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + u8 sec_reg_value; +@@ -334,16 +334,16 @@ void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) + "The SECR-value %x\n", sec_reg_value); + rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); + } +-EXPORT_SYMBOL_GPL(rtl92de_enable_hw_security_config); ++EXPORT_SYMBOL_GPL(rtl92d_enable_hw_security_config); + + /* don't set REG_EDCA_BE_PARAM here because + * mac80211 will send pkt when scan + */ +-void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) ++void rtl92d_set_qos(struct ieee80211_hw *hw, int aci) + { + rtl92d_dm_init_edca_turbo(hw); + } +-EXPORT_SYMBOL_GPL(rtl92de_set_qos); ++EXPORT_SYMBOL_GPL(rtl92d_set_qos); + + static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) + { +@@ -362,8 +362,8 @@ static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) + return version; + } + +-static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, +- u8 *efuse, bool autoloadfail) ++static void _rtl92d_readpowervalue_fromprom(struct txpower_info *pwrinfo, ++ u8 *efuse, bool autoloadfail) + { + u32 rfpath, eeaddr, group, offset, offset1, offset2; + u8 i, val8; +@@ -500,8 +500,8 @@ static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, + } + } + +-static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, +- bool autoload_fail, u8 *hwinfo) ++static void _rtl92d_read_txpower_info(struct ieee80211_hw *hw, ++ bool autoload_fail, u8 *hwinfo) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +@@ -509,7 +509,7 @@ static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, + u8 tempval[2], i, pwr, diff; + u32 ch, rfpath, group; + +- _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); ++ _rtl92d_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); + if (!autoload_fail) { + /* bit0~2 */ + rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); +@@ -613,8 +613,8 @@ static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, + } + } + +-static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, +- u8 *content) ++static void _rtl92d_read_macphymode_from_prom(struct ieee80211_hw *hw, ++ u8 *content) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); +@@ -636,15 +636,15 @@ static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, + } + } + +-static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, +- u8 *content) ++static void _rtl92d_read_macphymode_and_bandtype(struct ieee80211_hw *hw, ++ u8 *content) + { +- _rtl92de_read_macphymode_from_prom(hw, content); ++ _rtl92d_read_macphymode_from_prom(hw, content); + rtl92d_phy_config_macphymode(hw); + rtl92d_phy_config_macphymode_info(hw); + } + +-static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) ++static void _rtl92d_efuse_update_chip_version(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + enum version_8192d chipver = rtlpriv->rtlhal.version; +@@ -676,7 +676,7 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) + rtlpriv->rtlhal.version = chipver; + } + +-static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) ++static void _rtl92d_read_adapter_info(struct ieee80211_hw *hw) + { + static const int params_pci[] = { + RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, +@@ -706,8 +706,8 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) + if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) + goto exit; + +- _rtl92de_efuse_update_chip_version(hw); +- _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); ++ _rtl92d_efuse_update_chip_version(hw); ++ _rtl92d_read_macphymode_and_bandtype(hw, hwinfo); + + /* Read Permanent MAC address for 2nd interface */ + if (rtlhal->interfaceindex != 0) +@@ -717,7 +717,7 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) + rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, + rtlefuse->dev_addr); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); +- _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); ++ _rtl92d_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); + + /* Read Channel Plan */ + switch (rtlhal->bandset) { +@@ -739,7 +739,7 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) + kfree(hwinfo); + } + +-void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) ++void rtl92d_read_eeprom_info(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); +@@ -760,15 +760,15 @@ void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); + + rtlefuse->autoload_failflag = false; +- _rtl92de_read_adapter_info(hw); ++ _rtl92d_read_adapter_info(hw); + } else { + pr_err("Autoload ERR!!\n"); + } + } +-EXPORT_SYMBOL_GPL(rtl92de_read_eeprom_info); ++EXPORT_SYMBOL_GPL(rtl92d_read_eeprom_info); + +-static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta) ++static void rtl92d_update_hal_rate_table(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta) + { + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); + struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +@@ -851,9 +851,9 @@ static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, + rtl_read_dword(rtlpriv, REG_ARFR0)); + } + +-static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta, +- u8 rssi_level, bool update_bw) ++static void rtl92d_update_hal_rate_mask(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta, ++ u8 rssi_level, bool update_bw) + { + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); + struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +@@ -1009,20 +1009,20 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, + sta_entry->ratr_index = ratr_index; + } + +-void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta, +- u8 rssi_level, bool update_bw) ++void rtl92d_update_hal_rate_tbl(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta, ++ u8 rssi_level, bool update_bw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + + if (rtlpriv->dm.useramask) +- rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw); ++ rtl92d_update_hal_rate_mask(hw, sta, rssi_level, update_bw); + else +- rtl92de_update_hal_rate_table(hw, sta); ++ rtl92d_update_hal_rate_table(hw, sta); + } +-EXPORT_SYMBOL_GPL(rtl92de_update_hal_rate_tbl); ++EXPORT_SYMBOL_GPL(rtl92d_update_hal_rate_tbl); + +-void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) ++void rtl92d_update_channel_access_setting(struct ieee80211_hw *hw) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +@@ -1036,9 +1036,9 @@ void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) + sifs_timer = 0x1010; + rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); + } +-EXPORT_SYMBOL_GPL(rtl92de_update_channel_access_setting); ++EXPORT_SYMBOL_GPL(rtl92d_update_channel_access_setting); + +-bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) ++bool rtl92d_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); +@@ -1093,11 +1093,11 @@ bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) + *valid = 1; + return !ppsc->hwradiooff; + } +-EXPORT_SYMBOL_GPL(rtl92de_gpio_radio_on_off_checking); ++EXPORT_SYMBOL_GPL(rtl92d_gpio_radio_on_off_checking); + +-void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, +- u8 *p_macaddr, bool is_group, u8 enc_algo, +- bool is_wepkey, bool clear_all) ++void rtl92d_set_key(struct ieee80211_hw *hw, u32 key_index, ++ u8 *p_macaddr, bool is_group, u8 enc_algo, ++ bool is_wepkey, bool clear_all) + { + static const u8 cam_const_addr[4][6] = { + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, +@@ -1222,4 +1222,4 @@ void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, + } + } + } +-EXPORT_SYMBOL_GPL(rtl92de_set_key); ++EXPORT_SYMBOL_GPL(rtl92d_set_key); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h +index 2c07f5cc5766..4da1bab15f36 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h +@@ -4,21 +4,21 @@ + #ifndef __RTL92D_HW_COMMON_H__ + #define __RTL92D_HW_COMMON_H__ + +-void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw); +-void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw); ++void rtl92d_stop_tx_beacon(struct ieee80211_hw *hw); ++void rtl92d_resume_tx_beacon(struct ieee80211_hw *hw); + void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); + void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); +-bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data); +-void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw); +-void rtl92de_set_qos(struct ieee80211_hw *hw, int aci); +-void rtl92de_read_eeprom_info(struct ieee80211_hw *hw); +-void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, +- struct ieee80211_sta *sta, +- u8 rssi_level, bool update_bw); +-void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw); +-bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); +-void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, +- u8 *p_macaddr, bool is_group, u8 enc_algo, +- bool is_wepkey, bool clear_all); ++bool rtl92d_llt_write(struct ieee80211_hw *hw, u32 address, u32 data); ++void rtl92d_enable_hw_security_config(struct ieee80211_hw *hw); ++void rtl92d_set_qos(struct ieee80211_hw *hw, int aci); ++void rtl92d_read_eeprom_info(struct ieee80211_hw *hw); ++void rtl92d_update_hal_rate_tbl(struct ieee80211_hw *hw, ++ struct ieee80211_sta *sta, ++ u8 rssi_level, bool update_bw); ++void rtl92d_update_channel_access_setting(struct ieee80211_hw *hw); ++bool rtl92d_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); ++void rtl92d_set_key(struct ieee80211_hw *hw, u32 key_index, ++ u8 *p_macaddr, bool is_group, u8 enc_algo, ++ bool is_wepkey, bool clear_all); + + #endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c +index 72d2b7426d82..9f9a34492030 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c +@@ -7,8 +7,8 @@ + #include "def.h" + #include "trx_common.h" + +-static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, +- u8 signal_strength_index) ++static long _rtl92d_translate_todbm(struct ieee80211_hw *hw, ++ u8 signal_strength_index) + { + long signal_power; + +@@ -17,13 +17,13 @@ static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, + return signal_power; + } + +-static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, +- struct rtl_stats *pstats, +- __le32 *pdesc, +- struct rx_fwinfo_92d *p_drvinfo, +- bool packet_match_bssid, +- bool packet_toself, +- bool packet_beacon) ++static void _rtl92d_query_rxphystatus(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats, ++ __le32 *pdesc, ++ struct rx_fwinfo_92d *p_drvinfo, ++ bool packet_match_bssid, ++ bool packet_toself, ++ bool packet_beacon) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_phy *rtlphy = &rtlpriv->phy; +@@ -203,8 +203,8 @@ static void rtl92d_loop_over_paths(struct ieee80211_hw *hw, + } + } + +-static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) ++static void _rtl92d_process_ui_rssi(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rt_smooth_data *ui_rssi; +@@ -226,15 +226,15 @@ static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, + if (ui_rssi->index >= PHY_RSSI_SLID_WIN_MAX) + ui_rssi->index = 0; + tmpval = ui_rssi->total_val / ui_rssi->total_num; +- rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw, (u8)tmpval); ++ rtlpriv->stats.signal_strength = _rtl92d_translate_todbm(hw, (u8)tmpval); + pstats->rssi = rtlpriv->stats.signal_strength; + + if (!pstats->is_cck && pstats->packet_toself) + rtl92d_loop_over_paths(hw, pstats); + } + +-static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) ++static void _rtl92d_update_rxsignalstatistics(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + int weighting = 0; +@@ -249,8 +249,8 @@ static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, + 5 + pstats->recvsignalpower + weighting) / 6; + } + +-static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) ++static void _rtl92d_process_pwdb(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +@@ -276,7 +276,7 @@ static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, + (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); + } + rtlpriv->dm.undec_sm_pwdb = undec_sm_pwdb; +- _rtl92de_update_rxsignalstatistics(hw, pstats); ++ _rtl92d_update_rxsignalstatistics(hw, pstats); + } + } + +@@ -301,8 +301,8 @@ static void rtl92d_loop_over_streams(struct ieee80211_hw *hw, + } + } + +-static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, +- struct rtl_stats *pstats) ++static void _rtl92d_process_ui_link_quality(struct ieee80211_hw *hw, ++ struct rtl_stats *pstats) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); + struct rt_smooth_data *ui_link_quality; +@@ -330,24 +330,24 @@ static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, + rtl92d_loop_over_streams(hw, pstats); + } + +-static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw, +- u8 *buffer, +- struct rtl_stats *pcurrent_stats) ++static void _rtl92d_process_phyinfo(struct ieee80211_hw *hw, ++ u8 *buffer, ++ struct rtl_stats *pcurrent_stats) + { + if (!pcurrent_stats->packet_matchbssid && + !pcurrent_stats->packet_beacon) + return; + +- _rtl92de_process_ui_rssi(hw, pcurrent_stats); +- _rtl92de_process_pwdb(hw, pcurrent_stats); +- _rtl92de_process_ui_link_quality(hw, pcurrent_stats); ++ _rtl92d_process_ui_rssi(hw, pcurrent_stats); ++ _rtl92d_process_pwdb(hw, pcurrent_stats); ++ _rtl92d_process_ui_link_quality(hw, pcurrent_stats); + } + +-static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, +- struct sk_buff *skb, +- struct rtl_stats *pstats, +- __le32 *pdesc, +- struct rx_fwinfo_92d *p_drvinfo) ++static void _rtl92d_translate_rx_signal_stuff(struct ieee80211_hw *hw, ++ struct sk_buff *skb, ++ struct rtl_stats *pstats, ++ __le32 *pdesc, ++ struct rx_fwinfo_92d *p_drvinfo) + { + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); + struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); +@@ -375,15 +375,15 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, + packet_toself = packet_matchbssid && + ether_addr_equal(praddr, rtlefuse->dev_addr); + packet_beacon = ieee80211_is_beacon(fc); +- _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, +- packet_matchbssid, packet_toself, +- packet_beacon); +- _rtl92de_process_phyinfo(hw, tmp_buf, pstats); ++ _rtl92d_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, ++ packet_matchbssid, packet_toself, ++ packet_beacon); ++ _rtl92d_process_phyinfo(hw, tmp_buf, pstats); + } + +-bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, +- struct ieee80211_rx_status *rx_status, +- u8 *pdesc8, struct sk_buff *skb) ++bool rtl92d_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, ++ struct ieee80211_rx_status *rx_status, ++ u8 *pdesc8, struct sk_buff *skb) + { + __le32 *pdesc = (__le32 *)pdesc8; + struct rx_fwinfo_92d *p_drvinfo; +@@ -423,17 +423,17 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, + if (phystatus) { + p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + + stats->rx_bufshift); +- _rtl92de_translate_rx_signal_stuff(hw, skb, stats, pdesc, +- p_drvinfo); ++ _rtl92d_translate_rx_signal_stuff(hw, skb, stats, pdesc, ++ p_drvinfo); + } + /*rx_status->qual = stats->signal; */ + rx_status->signal = stats->recvsignalpower + 10; + return true; + } +-EXPORT_SYMBOL_GPL(rtl92de_rx_query_desc); ++EXPORT_SYMBOL_GPL(rtl92d_rx_query_desc); + +-void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, +- u8 desc_name, u8 *val) ++void rtl92d_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, ++ u8 desc_name, u8 *val) + { + __le32 *pdesc = (__le32 *)pdesc8; + +@@ -473,10 +473,10 @@ void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, + } + } + } +-EXPORT_SYMBOL_GPL(rtl92de_set_desc); ++EXPORT_SYMBOL_GPL(rtl92d_set_desc); + +-u64 rtl92de_get_desc(struct ieee80211_hw *hw, +- u8 *p_desc8, bool istx, u8 desc_name) ++u64 rtl92d_get_desc(struct ieee80211_hw *hw, ++ u8 *p_desc8, bool istx, u8 desc_name) + { + __le32 *p_desc = (__le32 *)p_desc8; + u32 ret = 0; +@@ -513,4 +513,4 @@ u64 rtl92de_get_desc(struct ieee80211_hw *hw, + } + return ret; + } +-EXPORT_SYMBOL_GPL(rtl92de_get_desc); ++EXPORT_SYMBOL_GPL(rtl92d_get_desc); +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h +index 87d956d771eb..528182b1eba6 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h +@@ -393,13 +393,13 @@ struct rx_fwinfo_92d { + #endif + } __packed; + +-bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, +- struct rtl_stats *stats, +- struct ieee80211_rx_status *rx_status, +- u8 *pdesc, struct sk_buff *skb); +-void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, +- u8 desc_name, u8 *val); +-u64 rtl92de_get_desc(struct ieee80211_hw *hw, +- u8 *p_desc, bool istx, u8 desc_name); ++bool rtl92d_rx_query_desc(struct ieee80211_hw *hw, ++ struct rtl_stats *stats, ++ struct ieee80211_rx_status *rx_status, ++ u8 *pdesc, struct sk_buff *skb); ++void rtl92d_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, ++ u8 desc_name, u8 *val); ++u64 rtl92d_get_desc(struct ieee80211_hw *hw, ++ u8 *p_desc, bool istx, u8 desc_name); + + #endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c +index 73b81e60cfa9..03f4314bdb2e 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c +@@ -181,7 +181,7 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + u8 btype_ibss = val[0]; + + if (btype_ibss) +- rtl92de_stop_tx_beacon(hw); ++ rtl92d_stop_tx_beacon(hw); + _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); + rtl_write_dword(rtlpriv, REG_TSFTR, + (u32) (mac->tsf & 0xffffffff)); +@@ -189,7 +189,7 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) + (u32) ((mac->tsf >> 32) & 0xffffffff)); + _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); + if (btype_ibss) +- rtl92de_resume_tx_beacon(hw); ++ rtl92d_resume_tx_beacon(hw); + + break; + } +@@ -295,13 +295,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) + + /* 18. LLT_table_init(Adapter); */ + for (i = 0; i < (txpktbuf_bndy - 1); i++) { +- status = rtl92de_llt_write(hw, i, i + 1); ++ status = rtl92d_llt_write(hw, i, i + 1); + if (!status) + return status; + } + + /* end of list */ +- status = rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); ++ status = rtl92d_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); + if (!status) + return status; + +@@ -310,13 +310,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) + /* config this MAC as two MAC transfer. */ + /* Otherwise used as local loopback buffer. */ + for (i = txpktbuf_bndy; i < maxpage; i++) { +- status = rtl92de_llt_write(hw, i, (i + 1)); ++ status = rtl92d_llt_write(hw, i, (i + 1)); + if (!status) + return status; + } + + /* Let last entry point to the start entry of ring buffer */ +- status = rtl92de_llt_write(hw, maxpage, txpktbuf_bndy); ++ status = rtl92d_llt_write(hw, maxpage, txpktbuf_bndy); + if (!status) + return status; + +@@ -688,7 +688,7 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) + + /* reset hw sec */ + rtl_cam_reset_all_entry(hw); +- rtl92de_enable_hw_security_config(hw); ++ rtl92d_enable_hw_security_config(hw); + + /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ + /* TX power index for different rate set. */ +@@ -742,11 +742,11 @@ static int _rtl92de_set_media_status(struct ieee80211_hw *hw, + + if (type == NL80211_IFTYPE_UNSPECIFIED || + type == NL80211_IFTYPE_STATION) { +- rtl92de_stop_tx_beacon(hw); ++ rtl92d_stop_tx_beacon(hw); + _rtl92de_enable_bcn_sub_func(hw); + } else if (type == NL80211_IFTYPE_ADHOC || + type == NL80211_IFTYPE_AP) { +- rtl92de_resume_tx_beacon(hw); ++ rtl92d_resume_tx_beacon(hw); + _rtl92de_disable_bcn_sub_func(hw); + } else { + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c +index 5f6311c2aac4..f5ce4889523e 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c +@@ -187,7 +187,7 @@ static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw) + static struct rtl_hal_ops rtl8192de_hal_ops = { + .init_sw_vars = rtl92d_init_sw_vars, + .deinit_sw_vars = rtl92d_deinit_sw_vars, +- .read_eeprom_info = rtl92de_read_eeprom_info, ++ .read_eeprom_info = rtl92d_read_eeprom_info, + .interrupt_recognized = rtl92de_interrupt_recognized, + .hw_init = rtl92de_hw_init, + .hw_disable = rtl92de_card_disable, +@@ -197,30 +197,30 @@ static struct rtl_hal_ops rtl8192de_hal_ops = { + .disable_interrupt = rtl92de_disable_interrupt, + .set_network_type = rtl92de_set_network_type, + .set_chk_bssid = rtl92de_set_check_bssid, +- .set_qos = rtl92de_set_qos, ++ .set_qos = rtl92d_set_qos, + .set_bcn_reg = rtl92de_set_beacon_related_registers, + .set_bcn_intv = rtl92de_set_beacon_interval, + .update_interrupt_mask = rtl92de_update_interrupt_mask, + .get_hw_reg = rtl92de_get_hw_reg, + .set_hw_reg = rtl92de_set_hw_reg, +- .update_rate_tbl = rtl92de_update_hal_rate_tbl, ++ .update_rate_tbl = rtl92d_update_hal_rate_tbl, + .fill_tx_desc = rtl92de_tx_fill_desc, + .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc, +- .query_rx_desc = rtl92de_rx_query_desc, +- .set_channel_access = rtl92de_update_channel_access_setting, +- .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, ++ .query_rx_desc = rtl92d_rx_query_desc, ++ .set_channel_access = rtl92d_update_channel_access_setting, ++ .radio_onoff_checking = rtl92d_gpio_radio_on_off_checking, + .set_bw_mode = rtl92d_phy_set_bw_mode, + .switch_channel = rtl92d_phy_sw_chnl, + .dm_watchdog = rtl92de_dm_watchdog, + .scan_operation_backup = rtl_phy_scan_operation_backup, + .set_rf_power_state = rtl92d_phy_set_rf_power_state, + .led_control = rtl92de_led_control, +- .set_desc = rtl92de_set_desc, +- .get_desc = rtl92de_get_desc, ++ .set_desc = rtl92d_set_desc, ++ .get_desc = rtl92d_get_desc, + .is_tx_desc_closed = rtl92de_is_tx_desc_closed, + .tx_polling = rtl92de_tx_polling, +- .enable_hw_sec = rtl92de_enable_hw_security_config, +- .set_key = rtl92de_set_key, ++ .enable_hw_sec = rtl92d_enable_hw_security_config, ++ .set_key = rtl92d_set_key, + .get_bbreg = rtl92d_phy_query_bb_reg, + .set_bbreg = rtl92d_phy_set_bb_reg, + .get_rfreg = rtl92d_phy_query_rf_reg, +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +index 2b9b352f7783..91bf399c9ef1 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +@@ -292,7 +292,7 @@ bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, + struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); + struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; + u8 *entry = (u8 *)(&ring->desc[ring->idx]); +- u8 own = (u8)rtl92de_get_desc(hw, entry, true, HW_DESC_OWN); ++ u8 own = (u8)rtl92d_get_desc(hw, entry, true, HW_DESC_OWN); + + /* a beacon packet will only use the first + * descriptor by defaut, and the own bit may not +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0019-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-table.-c-h.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0019-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-table.-c-h.patch new file mode 100644 index 0000000000..e673c551a2 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0019-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-table.-c-h.patch @@ -0,0 +1,1735 @@ +From 76b9d3316e2d5db38de05e1ad8fe3c6acaabf21a Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:44:09 +0300 +Subject: [PATCH 19/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/table.{c,h} + +These contain the MAC, BB, RF, and AGC initialisation tables for +RTL8192DU. + +Signed-off-by: Bitterblue Smith +--- + .../realtek/rtlwifi/rtl8192du/table.c | 1675 +++++++++++++++++ + .../realtek/rtlwifi/rtl8192du/table.h | 29 + + 2 files changed, 1704 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c +new file mode 100644 +index 000000000000..036701433d85 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c +@@ -0,0 +1,1675 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include ++ ++#include "table.h" ++ ++const u32 rtl8192du_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH] = { ++ 0x800, 0x80040002, ++ 0x804, 0x00000003, ++ 0x808, 0x0000fc00, ++ 0x80c, 0x0000000a, ++ 0x810, 0x10001331, ++ 0x814, 0x020c3d10, ++ 0x818, 0x02200385, ++ 0x81c, 0x00000000, ++ 0x820, 0x01000100, ++ 0x824, 0x00390004, ++ 0x828, 0x01000100, ++ 0x82c, 0x00390004, ++ 0x830, 0x27272727, ++ 0x834, 0x27272727, ++ 0x838, 0x27272727, ++ 0x83c, 0x27272727, ++ 0x840, 0x00010000, ++ 0x844, 0x00010000, ++ 0x848, 0x27272727, ++ 0x84c, 0x27272727, ++ 0x850, 0x00000000, ++ 0x854, 0x00000000, ++ 0x858, 0x569a569a, ++ 0x85c, 0x0c1b25a4, ++ 0x860, 0x66e60250, ++ 0x864, 0x061f0150, ++ 0x868, 0x27272727, ++ 0x86c, 0x272b2b2b, ++ 0x870, 0x07000700, ++ 0x874, 0x22188000, ++ 0x878, 0x08080808, ++ 0x87c, 0x0001fff8, ++ 0x880, 0xc0083070, ++ 0x884, 0x00000cd5, ++ 0x888, 0x00000000, ++ 0x88c, 0xcc0000c0, ++ 0x890, 0x00000800, ++ 0x894, 0xfffffffe, ++ 0x898, 0x40302010, ++ 0x89c, 0x00706050, ++ 0x900, 0x00000000, ++ 0x904, 0x00000023, ++ 0x908, 0x00000000, ++ 0x90c, 0x81121313, ++ 0xa00, 0x00d047c8, ++ 0xa04, 0x80ff000c, ++ 0xa08, 0x8c8a8300, ++ 0xa0c, 0x2e68120f, ++ 0xa10, 0x9500bb78, ++ 0xa14, 0x11144028, ++ 0xa18, 0x00881117, ++ 0xa1c, 0x89140f00, ++ 0xa20, 0x1a1b0000, ++ 0xa24, 0x090e1317, ++ 0xa28, 0x00000204, ++ 0xa2c, 0x00d30000, ++ 0xa70, 0x101fff00, ++ 0xa74, 0x00000007, ++ 0xc00, 0x40071d40, ++ 0xc04, 0x03a05633, ++ 0xc08, 0x001000e4, ++ 0xc0c, 0x6c6c6c6c, ++ 0xc10, 0x08800000, ++ 0xc14, 0x40000100, ++ 0xc18, 0x08800000, ++ 0xc1c, 0x40000100, ++ 0xc20, 0x00000000, ++ 0xc24, 0x00000000, ++ 0xc28, 0x00000000, ++ 0xc2c, 0x00000000, ++ 0xc30, 0x69e9ac44, ++ 0xc34, 0x469652af, ++ 0xc38, 0x49795994, ++ 0xc3c, 0x0a979718, ++ 0xc40, 0x1f7c403f, ++ 0xc44, 0x000100b7, ++ 0xc48, 0xec020107, ++ 0xc4c, 0x007f037f, ++ 0xc50, 0x69543420, ++ 0xc54, 0x43bc009e, ++ 0xc58, 0x69543420, ++ 0xc5c, 0x433c00a8, ++ 0xc60, 0x00000000, ++ 0xc64, 0x7112848b, ++ 0xc68, 0x47c00bff, ++ 0xc6c, 0x00000036, ++ 0xc70, 0x2c7f000d, ++ 0xc74, 0x258610db, ++ 0xc78, 0x0000001f, ++ 0xc7c, 0x40b95612, ++ 0xc80, 0x40000100, ++ 0xc84, 0x20f60000, ++ 0xc88, 0x40000100, ++ 0xc8c, 0xa0e40000, ++ 0xc90, 0x00121820, ++ 0xc94, 0x00000007, ++ 0xc98, 0x00121820, ++ 0xc9c, 0x00007f7f, ++ 0xca0, 0x00000000, ++ 0xca4, 0x00000080, ++ 0xca8, 0x00000000, ++ 0xcac, 0x00000000, ++ 0xcb0, 0x00000000, ++ 0xcb4, 0x00000000, ++ 0xcb8, 0x00000000, ++ 0xcbc, 0x28000000, ++ 0xcc0, 0x00000000, ++ 0xcc4, 0x00000000, ++ 0xcc8, 0x00000000, ++ 0xccc, 0x00000000, ++ 0xcd0, 0x00000000, ++ 0xcd4, 0x00000000, ++ 0xcd8, 0x64b11e20, ++ 0xcdc, 0xe0767533, ++ 0xce0, 0x00222222, ++ 0xce4, 0x00000000, ++ 0xce8, 0x37644302, ++ 0xcec, 0x2f97d40c, ++ 0xd00, 0x00080740, ++ 0xd04, 0x00020403, ++ 0xd08, 0x0000907f, ++ 0xd0c, 0x20010201, ++ 0xd10, 0xa0633333, ++ 0xd14, 0x3333bc43, ++ 0xd18, 0x7a8f5b6b, ++ 0xd2c, 0xcc979975, ++ 0xd30, 0x00000000, ++ 0xd34, 0x80608404, ++ 0xd38, 0x00000000, ++ 0xd3c, 0x00027353, ++ 0xd40, 0x00000000, ++ 0xd44, 0x00000000, ++ 0xd48, 0x00000000, ++ 0xd4c, 0x00000000, ++ 0xd50, 0x6437140a, ++ 0xd54, 0x00000000, ++ 0xd58, 0x00000000, ++ 0xd5c, 0x30032064, ++ 0xd60, 0x4653de68, ++ 0xd64, 0x04518a3c, ++ 0xd68, 0x00002101, ++ 0xd6c, 0x2a201c16, ++ 0xd70, 0x1812362e, ++ 0xd74, 0x322c2220, ++ 0xd78, 0x000e3c24, ++ 0xe00, 0x2a2a2a2a, ++ 0xe04, 0x2a2a2a2a, ++ 0xe08, 0x03902a2a, ++ 0xe10, 0x2a2a2a2a, ++ 0xe14, 0x2a2a2a2a, ++ 0xe18, 0x2a2a2a2a, ++ 0xe1c, 0x2a2a2a2a, ++ 0xe28, 0x00000000, ++ 0xe30, 0x1000dc1f, ++ 0xe34, 0x10008c1f, ++ 0xe38, 0x02140102, ++ 0xe3c, 0x681604c2, ++ 0xe40, 0x01007c00, ++ 0xe44, 0x01004800, ++ 0xe48, 0xfb000000, ++ 0xe4c, 0x000028d1, ++ 0xe50, 0x1000dc1f, ++ 0xe54, 0x10008c1f, ++ 0xe58, 0x02140102, ++ 0xe5c, 0x28160d05, ++ 0xe60, 0x00000010, ++ 0xe68, 0x001b25a4, ++ 0xe6c, 0x63db25a4, ++ 0xe70, 0x63db25a4, ++ 0xe74, 0x0c126da4, ++ 0xe78, 0x0c126da4, ++ 0xe7c, 0x0c126da4, ++ 0xe80, 0x0c126da4, ++ 0xe84, 0x63db25a4, ++ 0xe88, 0x0c126da4, ++ 0xe8c, 0x63db25a4, ++ 0xed0, 0x63db25a4, ++ 0xed4, 0x63db25a4, ++ 0xed8, 0x63db25a4, ++ 0xedc, 0x001b25a4, ++ 0xee0, 0x001b25a4, ++ 0xeec, 0x6fdb25a4, ++ 0xf14, 0x00000003, ++ 0xf1c, 0x00000064, ++ 0xf4c, 0x00000004, ++ 0xf00, 0x00000300, ++}; ++ ++const u32 rtl8192du_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH] = { ++ 0xe00, 0xffffffff, 0x07090c0c, ++ 0xe04, 0xffffffff, 0x01020405, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x0b0c0c0e, ++ 0xe14, 0xffffffff, 0x01030506, ++ 0xe18, 0xffffffff, 0x0b0c0d0e, ++ 0xe1c, 0xffffffff, 0x01030509, ++ 0x830, 0xffffffff, 0x07090c0c, ++ 0x834, 0xffffffff, 0x01020405, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x0b0c0c0e, ++ 0x848, 0xffffffff, 0x01030506, ++ 0x84c, 0xffffffff, 0x0b0c0d0e, ++ 0x868, 0xffffffff, 0x01030509, ++ 0xe00, 0xffffffff, 0x00000000, ++ 0xe04, 0xffffffff, 0x00000000, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x00000000, ++ 0xe14, 0xffffffff, 0x00000000, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x00000000, ++ 0x834, 0xffffffff, 0x00000000, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x00000000, ++ 0x848, 0xffffffff, 0x00000000, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x06060606, ++ 0xe14, 0xffffffff, 0x00020406, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x06060606, ++ 0x848, 0xffffffff, 0x00020406, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x00000000, ++ 0xe04, 0xffffffff, 0x00000000, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x00000000, ++ 0xe14, 0xffffffff, 0x00000000, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x00000000, ++ 0x834, 0xffffffff, 0x00000000, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x00000000, ++ 0x848, 0xffffffff, 0x00000000, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x00000000, ++ 0xe04, 0xffffffff, 0x00000000, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x00000000, ++ 0xe14, 0xffffffff, 0x00000000, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x00000000, ++ 0x834, 0xffffffff, 0x00000000, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x00000000, ++ 0x848, 0xffffffff, 0x00000000, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x00000000, ++ 0xe14, 0xffffffff, 0x00000000, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x00000000, ++ 0x848, 0xffffffff, 0x00000000, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x00000000, ++ 0xe04, 0xffffffff, 0x00000000, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x00000000, ++ 0xe14, 0xffffffff, 0x00000000, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x00000000, ++ 0x834, 0xffffffff, 0x00000000, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x00000000, ++ 0x848, 0xffffffff, 0x00000000, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x08080808, ++ 0xe14, 0xffffffff, 0x00040408, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x08080808, ++ 0x848, 0xffffffff, 0x00040408, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x08080808, ++ 0xe14, 0xffffffff, 0x00040408, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x08080808, ++ 0x848, 0xffffffff, 0x00040408, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x08080808, ++ 0xe14, 0xffffffff, 0x00040408, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x08080808, ++ 0x848, 0xffffffff, 0x00040408, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x08080808, ++ 0xe14, 0xffffffff, 0x00040408, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x08080808, ++ 0x848, 0xffffffff, 0x00040408, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x08080808, ++ 0xe14, 0xffffffff, 0x00040408, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x08080808, ++ 0x848, 0xffffffff, 0x00040408, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++ 0xe00, 0xffffffff, 0x04040404, ++ 0xe04, 0xffffffff, 0x00020204, ++ 0xe08, 0x0000ff00, 0x00000000, ++ 0x86c, 0xffffff00, 0x00000000, ++ 0xe10, 0xffffffff, 0x08080808, ++ 0xe14, 0xffffffff, 0x00040408, ++ 0xe18, 0xffffffff, 0x00000000, ++ 0xe1c, 0xffffffff, 0x00000000, ++ 0x830, 0xffffffff, 0x04040404, ++ 0x834, 0xffffffff, 0x00020204, ++ 0x838, 0xffffff00, 0x00000000, ++ 0x86c, 0x000000ff, 0x00000000, ++ 0x83c, 0xffffffff, 0x08080808, ++ 0x848, 0xffffffff, 0x00040408, ++ 0x84c, 0xffffffff, 0x00000000, ++ 0x868, 0xffffffff, 0x00000000, ++}; ++ ++const u32 rtl8192du_radioa_2tarray[RADIOA_2T_ARRAYLENGTH] = { ++ 0x000, 0x00030000, ++ 0x001, 0x00030000, ++ 0x002, 0x00000000, ++ 0x003, 0x00018c63, ++ 0x004, 0x00018c63, ++ 0x008, 0x00084000, ++ 0x00b, 0x0001c000, ++ 0x00e, 0x00018c67, ++ 0x00f, 0x00000851, ++ 0x014, 0x00021440, ++ 0x018, 0x00017524, ++ 0x019, 0x00000000, ++ 0x01d, 0x000a1290, ++ 0x023, 0x00001558, ++ 0x01a, 0x00030a99, ++ 0x01b, 0x00040b00, ++ 0x01c, 0x000fc339, ++ 0x03a, 0x000a57eb, ++ 0x03b, 0x00020000, ++ 0x03c, 0x000ff454, ++ 0x020, 0x0000aa52, ++ 0x021, 0x00054000, ++ 0x040, 0x0000aa52, ++ 0x041, 0x00014000, ++ 0x025, 0x000803be, ++ 0x026, 0x000fc638, ++ 0x027, 0x00077c18, ++ 0x028, 0x000de471, ++ 0x029, 0x000d7110, ++ 0x02a, 0x0008cb04, ++ 0x02b, 0x0004128b, ++ 0x02c, 0x00001840, ++ 0x043, 0x0002444f, ++ 0x044, 0x0001adb0, ++ 0x045, 0x00056467, ++ 0x046, 0x0008992c, ++ 0x047, 0x0000452c, ++ 0x048, 0x000f9c43, ++ 0x049, 0x00002e0c, ++ 0x04a, 0x000546eb, ++ 0x04b, 0x0008966c, ++ 0x04c, 0x0000dde9, ++ 0x018, 0x00007401, ++ 0x000, 0x00070000, ++ 0x012, 0x000dc000, ++ 0x012, 0x00090000, ++ 0x012, 0x00051000, ++ 0x012, 0x00012000, ++ 0x013, 0x000287b7, ++ 0x013, 0x000247ab, ++ 0x013, 0x0002079f, ++ 0x013, 0x0001c793, ++ 0x013, 0x0001839b, ++ 0x013, 0x00014392, ++ 0x013, 0x0001019a, ++ 0x013, 0x0000c191, ++ 0x013, 0x00008194, ++ 0x013, 0x000040a0, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f424, ++ 0x015, 0x0004f424, ++ 0x015, 0x0008f424, ++ 0x016, 0x000e1330, ++ 0x016, 0x000a1330, ++ 0x016, 0x00061330, ++ 0x016, 0x00021330, ++ 0x018, 0x00017524, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bc, ++ 0x013, 0x000247b0, ++ 0x013, 0x000203b4, ++ 0x013, 0x0001c3a8, ++ 0x013, 0x000181b4, ++ 0x013, 0x000141a8, ++ 0x013, 0x000100b4, ++ 0x013, 0x0000c0a8, ++ 0x013, 0x0000b030, ++ 0x013, 0x00004024, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f4c3, ++ 0x015, 0x0004f4c3, ++ 0x015, 0x0008f4c3, ++ 0x016, 0x000e085f, ++ 0x016, 0x000a085f, ++ 0x016, 0x0006085f, ++ 0x016, 0x0002085f, ++ 0x018, 0x00037524, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bc, ++ 0x013, 0x000247b0, ++ 0x013, 0x000203b4, ++ 0x013, 0x0001c3a8, ++ 0x013, 0x000181b4, ++ 0x013, 0x000141a8, ++ 0x013, 0x000100b4, ++ 0x013, 0x0000c0a8, ++ 0x013, 0x0000b030, ++ 0x013, 0x00004024, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f4c3, ++ 0x015, 0x0004f4c3, ++ 0x015, 0x0008f4c3, ++ 0x016, 0x000e085f, ++ 0x016, 0x000a085f, ++ 0x016, 0x0006085f, ++ 0x016, 0x0002085f, ++ 0x018, 0x00057568, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bc, ++ 0x013, 0x000247b0, ++ 0x013, 0x000203b4, ++ 0x013, 0x0001c3a8, ++ 0x013, 0x000181b4, ++ 0x013, 0x000141a8, ++ 0x013, 0x000100b4, ++ 0x013, 0x0000c0a8, ++ 0x013, 0x0000b030, ++ 0x013, 0x00004024, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f4c3, ++ 0x015, 0x0004f4c3, ++ 0x015, 0x0008f4c3, ++ 0x016, 0x000e085f, ++ 0x016, 0x000a085f, ++ 0x016, 0x0006085f, ++ 0x016, 0x0002085f, ++ 0x030, 0x0004470f, ++ 0x031, 0x00044ff0, ++ 0x032, 0x00000070, ++ 0x033, 0x000dd480, ++ 0x034, 0x000ffac0, ++ 0x035, 0x000b80c0, ++ 0x036, 0x00077000, ++ 0x037, 0x00064ff2, ++ 0x038, 0x000e7661, ++ 0x039, 0x00000e90, ++ 0x000, 0x00030000, ++ 0x018, 0x0000f401, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088009, ++ 0x01f, 0x00080003, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088001, ++ 0x01f, 0x00080000, ++ 0x0fe, 0x00000000, ++ 0x018, 0x00097524, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x02b, 0x00041289, ++ 0x0fe, 0x00000000, ++ 0x02d, 0x0006aaaa, ++ 0x02e, 0x000b4d01, ++ 0x02d, 0x00080000, ++ 0x02e, 0x00004d02, ++ 0x02d, 0x00095555, ++ 0x02e, 0x00054d03, ++ 0x02d, 0x000aaaaa, ++ 0x02e, 0x000b4d04, ++ 0x02d, 0x000c0000, ++ 0x02e, 0x00004d05, ++ 0x02d, 0x000d5555, ++ 0x02e, 0x00054d06, ++ 0x02d, 0x000eaaaa, ++ 0x02e, 0x000b4d07, ++ 0x02d, 0x00000000, ++ 0x02e, 0x00005108, ++ 0x02d, 0x00015555, ++ 0x02e, 0x00055109, ++ 0x02d, 0x0002aaaa, ++ 0x02e, 0x000b510a, ++ 0x02d, 0x00040000, ++ 0x02e, 0x0000510b, ++ 0x02d, 0x00055555, ++ 0x02e, 0x0005510c, ++}; ++ ++const u32 rtl8192du_radiob_2tarray[RADIOB_2T_ARRAYLENGTH] = { ++ 0x000, 0x00030000, ++ 0x001, 0x00030000, ++ 0x002, 0x00000000, ++ 0x003, 0x00018c63, ++ 0x004, 0x00018c63, ++ 0x008, 0x00084000, ++ 0x00b, 0x0001c000, ++ 0x00e, 0x00018c67, ++ 0x00f, 0x00000851, ++ 0x014, 0x00021440, ++ 0x018, 0x00007401, ++ 0x019, 0x00000060, ++ 0x01d, 0x000a1290, ++ 0x023, 0x00001558, ++ 0x01a, 0x00030a99, ++ 0x01b, 0x00040b00, ++ 0x01c, 0x000fc339, ++ 0x03a, 0x000a57eb, ++ 0x03b, 0x00020000, ++ 0x03c, 0x000ff454, ++ 0x020, 0x0000aa52, ++ 0x021, 0x00054000, ++ 0x040, 0x0000aa52, ++ 0x041, 0x00014000, ++ 0x025, 0x000803be, ++ 0x026, 0x000fc638, ++ 0x027, 0x00077c18, ++ 0x028, 0x000d1c31, ++ 0x029, 0x000d7110, ++ 0x02a, 0x000aeb04, ++ 0x02b, 0x0004128b, ++ 0x02c, 0x00001840, ++ 0x043, 0x0002444f, ++ 0x044, 0x0001adb0, ++ 0x045, 0x00056467, ++ 0x046, 0x0008992c, ++ 0x047, 0x0000452c, ++ 0x048, 0x000f9c43, ++ 0x049, 0x00002e0c, ++ 0x04a, 0x000546eb, ++ 0x04b, 0x0008966c, ++ 0x04c, 0x0000dde9, ++ 0x018, 0x00007401, ++ 0x000, 0x00070000, ++ 0x012, 0x000dc000, ++ 0x012, 0x00090000, ++ 0x012, 0x00051000, ++ 0x012, 0x00012000, ++ 0x013, 0x000287b7, ++ 0x013, 0x000247ab, ++ 0x013, 0x0002079f, ++ 0x013, 0x0001c793, ++ 0x013, 0x0001839b, ++ 0x013, 0x00014392, ++ 0x013, 0x0001019a, ++ 0x013, 0x0000c191, ++ 0x013, 0x00008194, ++ 0x013, 0x000040a0, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f424, ++ 0x015, 0x0004f424, ++ 0x015, 0x0008f424, ++ 0x016, 0x000e1330, ++ 0x016, 0x000a1330, ++ 0x016, 0x00061330, ++ 0x016, 0x00021330, ++ 0x018, 0x00017524, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bc, ++ 0x013, 0x000247b0, ++ 0x013, 0x000203b4, ++ 0x013, 0x0001c3a8, ++ 0x013, 0x000181b4, ++ 0x013, 0x000141a8, ++ 0x013, 0x000100b4, ++ 0x013, 0x0000c0a8, ++ 0x013, 0x0000b030, ++ 0x013, 0x00004024, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f4c3, ++ 0x015, 0x0004f4c3, ++ 0x015, 0x0008f4c3, ++ 0x016, 0x000e085f, ++ 0x016, 0x000a085f, ++ 0x016, 0x0006085f, ++ 0x016, 0x0002085f, ++ 0x018, 0x00037524, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bc, ++ 0x013, 0x000247b0, ++ 0x013, 0x000203b4, ++ 0x013, 0x0001c3a8, ++ 0x013, 0x000181b4, ++ 0x013, 0x000141a8, ++ 0x013, 0x000100b4, ++ 0x013, 0x0000c0a8, ++ 0x013, 0x0000b030, ++ 0x013, 0x00004024, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f4c3, ++ 0x015, 0x0004f4c3, ++ 0x015, 0x0008f4c3, ++ 0x016, 0x000e085f, ++ 0x016, 0x000a085f, ++ 0x016, 0x0006085f, ++ 0x016, 0x0002085f, ++ 0x018, 0x00057524, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bc, ++ 0x013, 0x000247b0, ++ 0x013, 0x000203b4, ++ 0x013, 0x0001c3a8, ++ 0x013, 0x000181b4, ++ 0x013, 0x000141a8, ++ 0x013, 0x000100b4, ++ 0x013, 0x0000c0a8, ++ 0x013, 0x0000b030, ++ 0x013, 0x00004024, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f4c3, ++ 0x015, 0x0004f4c3, ++ 0x015, 0x0008f4c3, ++ 0x016, 0x000e085f, ++ 0x016, 0x000a085f, ++ 0x016, 0x0006085f, ++ 0x016, 0x0002085f, ++ 0x030, 0x0004470f, ++ 0x031, 0x00044ff0, ++ 0x032, 0x00000070, ++ 0x033, 0x000dd480, ++ 0x034, 0x000ffac0, ++ 0x035, 0x000b80c0, ++ 0x036, 0x00077000, ++ 0x037, 0x00064ff2, ++ 0x038, 0x000e7661, ++ 0x039, 0x00000e90, ++ 0x000, 0x00030000, ++ 0x018, 0x0000f401, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088009, ++ 0x01f, 0x00080003, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088001, ++ 0x01f, 0x00080000, ++ 0x0fe, 0x00000000, ++ 0x018, 0x00087401, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x02b, 0x00041289, ++ 0x0fe, 0x00000000, ++ 0x02d, 0x00066666, ++ 0x02e, 0x00064001, ++ 0x02d, 0x00091111, ++ 0x02e, 0x00014002, ++ 0x02d, 0x000bbbbb, ++ 0x02e, 0x000b4003, ++ 0x02d, 0x000e6666, ++ 0x02e, 0x00064004, ++ 0x02d, 0x00088888, ++ 0x02e, 0x00084005, ++ 0x02d, 0x0009dddd, ++ 0x02e, 0x000d4006, ++ 0x02d, 0x000b3333, ++ 0x02e, 0x00034007, ++ 0x02d, 0x00048888, ++ 0x02e, 0x00084408, ++ 0x02d, 0x000bbbbb, ++ 0x02e, 0x000b4409, ++ 0x02d, 0x000e6666, ++ 0x02e, 0x0006440a, ++ 0x02d, 0x00011111, ++ 0x02e, 0x0001480b, ++ 0x02d, 0x0003bbbb, ++ 0x02e, 0x000b480c, ++ 0x02d, 0x00066666, ++ 0x02e, 0x0006480d, ++ 0x02d, 0x000ccccc, ++ 0x02e, 0x000c480e, ++}; ++ ++const u32 rtl8192du_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH] = { ++ 0x000, 0x00030000, ++ 0x001, 0x00030000, ++ 0x002, 0x00000000, ++ 0x003, 0x00018c63, ++ 0x004, 0x00018c63, ++ 0x008, 0x00084000, ++ 0x00b, 0x0001c000, ++ 0x00e, 0x00018c67, ++ 0x00f, 0x00000851, ++ 0x014, 0x00021440, ++ 0x018, 0x00017524, ++ 0x019, 0x00000000, ++ 0x01d, 0x000a1290, ++ 0x023, 0x00001558, ++ 0x01a, 0x00030a99, ++ 0x01b, 0x00040b00, ++ 0x01c, 0x000fc339, ++ 0x03a, 0x000a57eb, ++ 0x03b, 0x00020000, ++ 0x03c, 0x000ff455, ++ 0x020, 0x0000aa52, ++ 0x021, 0x00054000, ++ 0x040, 0x0000aa52, ++ 0x041, 0x00014000, ++ 0x025, 0x000803be, ++ 0x026, 0x000fc638, ++ 0x027, 0x00077c18, ++ 0x028, 0x000de471, ++ 0x029, 0x000d7110, ++ 0x02a, 0x0008eb04, ++ 0x02b, 0x0004128b, ++ 0x02c, 0x00001840, ++ 0x043, 0x0002444f, ++ 0x044, 0x0001adb0, ++ 0x045, 0x00056467, ++ 0x046, 0x0008992c, ++ 0x047, 0x0000452c, ++ 0x048, 0x000c0443, ++ 0x049, 0x00000730, ++ 0x04a, 0x00050f0f, ++ 0x04b, 0x000896ef, ++ 0x04c, 0x0000ddee, ++ 0x018, 0x00007401, ++ 0x000, 0x00070000, ++ 0x012, 0x000dc000, ++ 0x012, 0x00090000, ++ 0x012, 0x00051000, ++ 0x012, 0x00012000, ++ 0x013, 0x000287b7, ++ 0x013, 0x000247ab, ++ 0x013, 0x0002079f, ++ 0x013, 0x0001c793, ++ 0x013, 0x0001839b, ++ 0x013, 0x00014392, ++ 0x013, 0x0001019a, ++ 0x013, 0x0000c191, ++ 0x013, 0x00008194, ++ 0x013, 0x000040a0, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f424, ++ 0x015, 0x0004f424, ++ 0x015, 0x0008f424, ++ 0x016, 0x000e1330, ++ 0x016, 0x000a1330, ++ 0x016, 0x00061330, ++ 0x016, 0x00021330, ++ 0x018, 0x00017524, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bf, ++ 0x013, 0x000247b3, ++ 0x013, 0x000207a7, ++ 0x013, 0x0001c79b, ++ 0x013, 0x0001839f, ++ 0x013, 0x00014393, ++ 0x013, 0x00010399, ++ 0x013, 0x0000c38d, ++ 0x013, 0x00008199, ++ 0x013, 0x0000418d, ++ 0x013, 0x00000099, ++ 0x015, 0x0000f495, ++ 0x015, 0x0004f495, ++ 0x015, 0x0008f495, ++ 0x016, 0x000e1874, ++ 0x016, 0x000a1874, ++ 0x016, 0x00061874, ++ 0x016, 0x00021874, ++ 0x018, 0x00037564, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bf, ++ 0x013, 0x000247b3, ++ 0x013, 0x000207a7, ++ 0x013, 0x0001c79b, ++ 0x013, 0x0001839f, ++ 0x013, 0x00014393, ++ 0x013, 0x00010399, ++ 0x013, 0x0000c38d, ++ 0x013, 0x00008199, ++ 0x013, 0x0000418d, ++ 0x013, 0x00000099, ++ 0x015, 0x0000f495, ++ 0x015, 0x0004f495, ++ 0x015, 0x0008f495, ++ 0x016, 0x000e1874, ++ 0x016, 0x000a1874, ++ 0x016, 0x00061874, ++ 0x016, 0x00021874, ++ 0x018, 0x00057595, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bf, ++ 0x013, 0x000247b3, ++ 0x013, 0x000207a7, ++ 0x013, 0x0001c79b, ++ 0x013, 0x0001839f, ++ 0x013, 0x00014393, ++ 0x013, 0x00010399, ++ 0x013, 0x0000c38d, ++ 0x013, 0x00008199, ++ 0x013, 0x0000418d, ++ 0x013, 0x00000099, ++ 0x015, 0x0000f495, ++ 0x015, 0x0004f495, ++ 0x015, 0x0008f495, ++ 0x016, 0x000e1874, ++ 0x016, 0x000a1874, ++ 0x016, 0x00061874, ++ 0x016, 0x00021874, ++ 0x030, 0x0004470f, ++ 0x031, 0x00044ff0, ++ 0x032, 0x00000070, ++ 0x033, 0x000dd480, ++ 0x034, 0x000ffac0, ++ 0x035, 0x000b80c0, ++ 0x036, 0x00077000, ++ 0x037, 0x00064ff2, ++ 0x038, 0x000e7661, ++ 0x039, 0x00000e90, ++ 0x000, 0x00030000, ++ 0x018, 0x0000f401, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088009, ++ 0x01f, 0x00080003, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088001, ++ 0x01f, 0x00080000, ++ 0x0fe, 0x00000000, ++ 0x018, 0x00097524, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x02b, 0x00041289, ++ 0x0fe, 0x00000000, ++ 0x02d, 0x0006aaaa, ++ 0x02e, 0x000b4d01, ++ 0x02d, 0x00080000, ++ 0x02e, 0x00004d02, ++ 0x02d, 0x00095555, ++ 0x02e, 0x00054d03, ++ 0x02d, 0x000aaaaa, ++ 0x02e, 0x000b4d04, ++ 0x02d, 0x000c0000, ++ 0x02e, 0x00004d05, ++ 0x02d, 0x000d5555, ++ 0x02e, 0x00054d06, ++ 0x02d, 0x000eaaaa, ++ 0x02e, 0x000b4d07, ++ 0x02d, 0x00000000, ++ 0x02e, 0x00005108, ++ 0x02d, 0x00015555, ++ 0x02e, 0x00055109, ++ 0x02d, 0x0002aaaa, ++ 0x02e, 0x000b510a, ++ 0x02d, 0x00040000, ++ 0x02e, 0x0000510b, ++ 0x02d, 0x00055555, ++ 0x02e, 0x0005510c, ++}; ++ ++const u32 rtl8192du_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH] = { ++ 0x000, 0x00030000, ++ 0x001, 0x00030000, ++ 0x002, 0x00000000, ++ 0x003, 0x00018c63, ++ 0x004, 0x00018c63, ++ 0x008, 0x00084000, ++ 0x00b, 0x0001c000, ++ 0x00e, 0x00018c67, ++ 0x00f, 0x00000851, ++ 0x014, 0x00021440, ++ 0x018, 0x00007401, ++ 0x019, 0x00000060, ++ 0x01d, 0x000a1290, ++ 0x023, 0x00001558, ++ 0x01a, 0x00030a99, ++ 0x01b, 0x00040b00, ++ 0x01c, 0x000fc339, ++ 0x03a, 0x000a57eb, ++ 0x03b, 0x00020000, ++ 0x03c, 0x000ff455, ++ 0x020, 0x0000aa52, ++ 0x021, 0x00054000, ++ 0x040, 0x0000aa52, ++ 0x041, 0x00014000, ++ 0x025, 0x000803be, ++ 0x026, 0x000fc638, ++ 0x027, 0x00077c18, ++ 0x028, 0x000d1c31, ++ 0x029, 0x000d7110, ++ 0x02a, 0x000aeb04, ++ 0x02b, 0x0004128b, ++ 0x02c, 0x00001840, ++ 0x043, 0x0002444f, ++ 0x044, 0x0001adb0, ++ 0x045, 0x00056467, ++ 0x046, 0x0008992c, ++ 0x047, 0x0000452c, ++ 0x048, 0x000c0443, ++ 0x049, 0x00000730, ++ 0x04a, 0x00050f0f, ++ 0x04b, 0x000896ef, ++ 0x04c, 0x0000ddee, ++ 0x018, 0x00007401, ++ 0x000, 0x00070000, ++ 0x012, 0x000dc000, ++ 0x012, 0x00090000, ++ 0x012, 0x00051000, ++ 0x012, 0x00012000, ++ 0x013, 0x000287b7, ++ 0x013, 0x000247ab, ++ 0x013, 0x0002079f, ++ 0x013, 0x0001c793, ++ 0x013, 0x0001839b, ++ 0x013, 0x00014392, ++ 0x013, 0x0001019a, ++ 0x013, 0x0000c191, ++ 0x013, 0x00008194, ++ 0x013, 0x000040a0, ++ 0x013, 0x00000018, ++ 0x015, 0x0000f424, ++ 0x015, 0x0004f424, ++ 0x015, 0x0008f424, ++ 0x016, 0x000e1330, ++ 0x016, 0x000a1330, ++ 0x016, 0x00061330, ++ 0x016, 0x00021330, ++ 0x018, 0x00017524, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bf, ++ 0x013, 0x000247b3, ++ 0x013, 0x000207a7, ++ 0x013, 0x0001c79b, ++ 0x013, 0x0001839f, ++ 0x013, 0x00014393, ++ 0x013, 0x00010399, ++ 0x013, 0x0000c38d, ++ 0x013, 0x00008199, ++ 0x013, 0x0000418d, ++ 0x013, 0x00000099, ++ 0x015, 0x0000f495, ++ 0x015, 0x0004f495, ++ 0x015, 0x0008f495, ++ 0x016, 0x000e1874, ++ 0x016, 0x000a1874, ++ 0x016, 0x00061874, ++ 0x016, 0x00021874, ++ 0x018, 0x00037564, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bf, ++ 0x013, 0x000247b3, ++ 0x013, 0x000207a7, ++ 0x013, 0x0001c79b, ++ 0x013, 0x0001839f, ++ 0x013, 0x00014393, ++ 0x013, 0x00010399, ++ 0x013, 0x0000c38d, ++ 0x013, 0x00008199, ++ 0x013, 0x0000418d, ++ 0x013, 0x00000099, ++ 0x015, 0x0000f495, ++ 0x015, 0x0004f495, ++ 0x015, 0x0008f495, ++ 0x016, 0x000e1874, ++ 0x016, 0x000a1874, ++ 0x016, 0x00061874, ++ 0x016, 0x00021874, ++ 0x018, 0x00057595, ++ 0x000, 0x00070000, ++ 0x012, 0x000cf000, ++ 0x012, 0x000bc000, ++ 0x012, 0x00078000, ++ 0x012, 0x00000000, ++ 0x013, 0x000287bf, ++ 0x013, 0x000247b3, ++ 0x013, 0x000207a7, ++ 0x013, 0x0001c79b, ++ 0x013, 0x0001839f, ++ 0x013, 0x00014393, ++ 0x013, 0x00010399, ++ 0x013, 0x0000c38d, ++ 0x013, 0x00008199, ++ 0x013, 0x0000418d, ++ 0x013, 0x00000099, ++ 0x015, 0x0000f495, ++ 0x015, 0x0004f495, ++ 0x015, 0x0008f495, ++ 0x016, 0x000e1874, ++ 0x016, 0x000a1874, ++ 0x016, 0x00061874, ++ 0x016, 0x00021874, ++ 0x030, 0x0004470f, ++ 0x031, 0x00044ff0, ++ 0x032, 0x00000070, ++ 0x033, 0x000dd480, ++ 0x034, 0x000ffac0, ++ 0x035, 0x000b80c0, ++ 0x036, 0x00077000, ++ 0x037, 0x00064ff2, ++ 0x038, 0x000e7661, ++ 0x039, 0x00000e90, ++ 0x000, 0x00030000, ++ 0x018, 0x0000f401, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088009, ++ 0x01f, 0x00080003, ++ 0x0fe, 0x00000000, ++ 0x01e, 0x00088001, ++ 0x01f, 0x00080000, ++ 0x0fe, 0x00000000, ++ 0x018, 0x00087401, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x0fe, 0x00000000, ++ 0x02b, 0x00041289, ++ 0x0fe, 0x00000000, ++ 0x02d, 0x00066666, ++ 0x02e, 0x00064001, ++ 0x02d, 0x00091111, ++ 0x02e, 0x00014002, ++ 0x02d, 0x000bbbbb, ++ 0x02e, 0x000b4003, ++ 0x02d, 0x000e6666, ++ 0x02e, 0x00064004, ++ 0x02d, 0x00088888, ++ 0x02e, 0x00084005, ++ 0x02d, 0x0009dddd, ++ 0x02e, 0x000d4006, ++ 0x02d, 0x000b3333, ++ 0x02e, 0x00034007, ++ 0x02d, 0x00048888, ++ 0x02e, 0x00084408, ++ 0x02d, 0x000bbbbb, ++ 0x02e, 0x000b4409, ++ 0x02d, 0x000e6666, ++ 0x02e, 0x0006440a, ++ 0x02d, 0x00011111, ++ 0x02e, 0x0001480b, ++ 0x02d, 0x0003bbbb, ++ 0x02e, 0x000b480c, ++ 0x02d, 0x00066666, ++ 0x02e, 0x0006480d, ++ 0x02d, 0x000ccccc, ++ 0x02e, 0x000c480e, ++}; ++ ++const u32 rtl8192du_mac_2tarray[MAC_2T_ARRAYLENGTH] = { ++ 0x420, 0x00000080, ++ 0x423, 0x00000000, ++ 0x430, 0x00000000, ++ 0x431, 0x00000000, ++ 0x432, 0x00000000, ++ 0x433, 0x00000001, ++ 0x434, 0x00000004, ++ 0x435, 0x00000005, ++ 0x436, 0x00000006, ++ 0x437, 0x00000007, ++ 0x438, 0x00000000, ++ 0x439, 0x00000000, ++ 0x43a, 0x00000000, ++ 0x43b, 0x00000001, ++ 0x43c, 0x00000004, ++ 0x43d, 0x00000005, ++ 0x43e, 0x00000006, ++ 0x43f, 0x00000007, ++ 0x440, 0x00000050, ++ 0x441, 0x00000001, ++ 0x442, 0x00000000, ++ 0x444, 0x00000015, ++ 0x445, 0x000000f0, ++ 0x446, 0x0000000f, ++ 0x447, 0x00000000, ++ 0x462, 0x00000008, ++ 0x463, 0x00000003, ++ 0x4c8, 0x000000ff, ++ 0x4c9, 0x00000008, ++ 0x4cc, 0x000000ff, ++ 0x4cd, 0x000000ff, ++ 0x4ce, 0x00000001, ++ 0x500, 0x00000026, ++ 0x501, 0x000000a2, ++ 0x502, 0x0000002f, ++ 0x503, 0x00000000, ++ 0x504, 0x00000028, ++ 0x505, 0x000000a3, ++ 0x506, 0x0000005e, ++ 0x507, 0x00000000, ++ 0x508, 0x0000002b, ++ 0x509, 0x000000a4, ++ 0x50a, 0x0000005e, ++ 0x50b, 0x00000000, ++ 0x50c, 0x0000004f, ++ 0x50d, 0x000000a4, ++ 0x50e, 0x00000000, ++ 0x50f, 0x00000000, ++ 0x512, 0x0000001c, ++ 0x514, 0x0000000a, ++ 0x515, 0x00000010, ++ 0x516, 0x0000000a, ++ 0x517, 0x00000010, ++ 0x51a, 0x00000016, ++ 0x524, 0x0000000f, ++ 0x525, 0x0000004f, ++ 0x546, 0x00000040, ++ 0x547, 0x00000000, ++ 0x550, 0x00000010, ++ 0x551, 0x00000010, ++ 0x559, 0x00000002, ++ 0x55a, 0x00000002, ++ 0x55d, 0x000000ff, ++ 0x605, 0x00000080, ++ 0x608, 0x0000000e, ++ 0x609, 0x0000002a, ++ 0x652, 0x00000020, ++ 0x63c, 0x0000000a, ++ 0x63d, 0x0000000a, ++ 0x63e, 0x0000000e, ++ 0x63f, 0x0000000e, ++ 0x66e, 0x00000005, ++ 0x700, 0x00000021, ++ 0x701, 0x00000043, ++ 0x702, 0x00000065, ++ 0x703, 0x00000087, ++ 0x708, 0x00000021, ++ 0x709, 0x00000043, ++ 0x70a, 0x00000065, ++ 0x70b, 0x00000087, ++ 0x024, 0x0000000d, ++ 0x025, 0x00000080, ++ 0x026, 0x00000011, ++ 0x027, 0x00000000, ++ 0x028, 0x00000083, ++ 0x029, 0x000000db, ++ 0x02a, 0x000000ff, ++ 0x02b, 0x00000000, ++ 0x014, 0x00000055, ++ 0x015, 0x000000a9, ++ 0x016, 0x0000008b, ++ 0x017, 0x00000008, ++ 0x010, 0x00000003, ++ 0x011, 0x0000002b, ++ 0x012, 0x00000002, ++ 0x013, 0x00000049, ++}; ++ ++const u32 rtl8192du_agctab_array[AGCTAB_ARRAYLENGTH] = { ++ 0xc78, 0x7b000001, ++ 0xc78, 0x7b010001, ++ 0xc78, 0x7b020001, ++ 0xc78, 0x7b030001, ++ 0xc78, 0x7b040001, ++ 0xc78, 0x7b050001, ++ 0xc78, 0x7b060001, ++ 0xc78, 0x7a070001, ++ 0xc78, 0x79080001, ++ 0xc78, 0x78090001, ++ 0xc78, 0x770a0001, ++ 0xc78, 0x760b0001, ++ 0xc78, 0x750c0001, ++ 0xc78, 0x740d0001, ++ 0xc78, 0x730e0001, ++ 0xc78, 0x720f0001, ++ 0xc78, 0x71100001, ++ 0xc78, 0x70110001, ++ 0xc78, 0x6f120001, ++ 0xc78, 0x6e130001, ++ 0xc78, 0x6d140001, ++ 0xc78, 0x6c150001, ++ 0xc78, 0x6b160001, ++ 0xc78, 0x6a170001, ++ 0xc78, 0x69180001, ++ 0xc78, 0x68190001, ++ 0xc78, 0x671a0001, ++ 0xc78, 0x661b0001, ++ 0xc78, 0x651c0001, ++ 0xc78, 0x641d0001, ++ 0xc78, 0x631e0001, ++ 0xc78, 0x621f0001, ++ 0xc78, 0x61200001, ++ 0xc78, 0x60210001, ++ 0xc78, 0x49220001, ++ 0xc78, 0x48230001, ++ 0xc78, 0x47240001, ++ 0xc78, 0x46250001, ++ 0xc78, 0x45260001, ++ 0xc78, 0x44270001, ++ 0xc78, 0x43280001, ++ 0xc78, 0x42290001, ++ 0xc78, 0x412a0001, ++ 0xc78, 0x402b0001, ++ 0xc78, 0x262c0001, ++ 0xc78, 0x252d0001, ++ 0xc78, 0x242e0001, ++ 0xc78, 0x232f0001, ++ 0xc78, 0x22300001, ++ 0xc78, 0x21310001, ++ 0xc78, 0x20320001, ++ 0xc78, 0x06330001, ++ 0xc78, 0x05340001, ++ 0xc78, 0x04350001, ++ 0xc78, 0x03360001, ++ 0xc78, 0x02370001, ++ 0xc78, 0x01380001, ++ 0xc78, 0x00390001, ++ 0xc78, 0x003a0001, ++ 0xc78, 0x003b0001, ++ 0xc78, 0x003c0001, ++ 0xc78, 0x003d0001, ++ 0xc78, 0x003e0001, ++ 0xc78, 0x003f0001, ++ 0xc78, 0x7b400001, ++ 0xc78, 0x7b410001, ++ 0xc78, 0x7a420001, ++ 0xc78, 0x79430001, ++ 0xc78, 0x78440001, ++ 0xc78, 0x77450001, ++ 0xc78, 0x76460001, ++ 0xc78, 0x75470001, ++ 0xc78, 0x74480001, ++ 0xc78, 0x73490001, ++ 0xc78, 0x724a0001, ++ 0xc78, 0x714b0001, ++ 0xc78, 0x704c0001, ++ 0xc78, 0x6f4d0001, ++ 0xc78, 0x6e4e0001, ++ 0xc78, 0x6d4f0001, ++ 0xc78, 0x6c500001, ++ 0xc78, 0x6b510001, ++ 0xc78, 0x6a520001, ++ 0xc78, 0x69530001, ++ 0xc78, 0x68540001, ++ 0xc78, 0x67550001, ++ 0xc78, 0x66560001, ++ 0xc78, 0x65570001, ++ 0xc78, 0x64580001, ++ 0xc78, 0x63590001, ++ 0xc78, 0x625a0001, ++ 0xc78, 0x615b0001, ++ 0xc78, 0x605c0001, ++ 0xc78, 0x485d0001, ++ 0xc78, 0x475e0001, ++ 0xc78, 0x465f0001, ++ 0xc78, 0x45600001, ++ 0xc78, 0x44610001, ++ 0xc78, 0x43620001, ++ 0xc78, 0x42630001, ++ 0xc78, 0x41640001, ++ 0xc78, 0x40650001, ++ 0xc78, 0x27660001, ++ 0xc78, 0x26670001, ++ 0xc78, 0x25680001, ++ 0xc78, 0x24690001, ++ 0xc78, 0x236a0001, ++ 0xc78, 0x226b0001, ++ 0xc78, 0x216c0001, ++ 0xc78, 0x206d0001, ++ 0xc78, 0x206e0001, ++ 0xc78, 0x206f0001, ++ 0xc78, 0x20700001, ++ 0xc78, 0x20710001, ++ 0xc78, 0x20720001, ++ 0xc78, 0x20730001, ++ 0xc78, 0x20740001, ++ 0xc78, 0x20750001, ++ 0xc78, 0x20760001, ++ 0xc78, 0x20770001, ++ 0xc78, 0x20780001, ++ 0xc78, 0x20790001, ++ 0xc78, 0x207a0001, ++ 0xc78, 0x207b0001, ++ 0xc78, 0x207c0001, ++ 0xc78, 0x207d0001, ++ 0xc78, 0x207e0001, ++ 0xc78, 0x207f0001, ++ 0xc78, 0x38000002, ++ 0xc78, 0x38010002, ++ 0xc78, 0x38020002, ++ 0xc78, 0x38030002, ++ 0xc78, 0x38040002, ++ 0xc78, 0x38050002, ++ 0xc78, 0x38060002, ++ 0xc78, 0x38070002, ++ 0xc78, 0x38080002, ++ 0xc78, 0x3c090002, ++ 0xc78, 0x3e0a0002, ++ 0xc78, 0x400b0002, ++ 0xc78, 0x440c0002, ++ 0xc78, 0x480d0002, ++ 0xc78, 0x4c0e0002, ++ 0xc78, 0x500f0002, ++ 0xc78, 0x52100002, ++ 0xc78, 0x56110002, ++ 0xc78, 0x5a120002, ++ 0xc78, 0x5e130002, ++ 0xc78, 0x60140002, ++ 0xc78, 0x60150002, ++ 0xc78, 0x60160002, ++ 0xc78, 0x62170002, ++ 0xc78, 0x62180002, ++ 0xc78, 0x62190002, ++ 0xc78, 0x621a0002, ++ 0xc78, 0x621b0002, ++ 0xc78, 0x621c0002, ++ 0xc78, 0x621d0002, ++ 0xc78, 0x621e0002, ++ 0xc78, 0x621f0002, ++ 0xc78, 0x32000044, ++ 0xc78, 0x32010044, ++ 0xc78, 0x32020044, ++ 0xc78, 0x32030044, ++ 0xc78, 0x32040044, ++ 0xc78, 0x32050044, ++ 0xc78, 0x32060044, ++ 0xc78, 0x34070044, ++ 0xc78, 0x35080044, ++ 0xc78, 0x36090044, ++ 0xc78, 0x370a0044, ++ 0xc78, 0x380b0044, ++ 0xc78, 0x390c0044, ++ 0xc78, 0x3a0d0044, ++ 0xc78, 0x3e0e0044, ++ 0xc78, 0x420f0044, ++ 0xc78, 0x44100044, ++ 0xc78, 0x46110044, ++ 0xc78, 0x4a120044, ++ 0xc78, 0x4e130044, ++ 0xc78, 0x50140044, ++ 0xc78, 0x55150044, ++ 0xc78, 0x5a160044, ++ 0xc78, 0x5e170044, ++ 0xc78, 0x64180044, ++ 0xc78, 0x6e190044, ++ 0xc78, 0x6e1a0044, ++ 0xc78, 0x6e1b0044, ++ 0xc78, 0x6e1c0044, ++ 0xc78, 0x6e1d0044, ++ 0xc78, 0x6e1e0044, ++ 0xc78, 0x6e1f0044, ++ 0xc78, 0x6e1f0000, ++}; ++ ++const u32 rtl8192du_agctab_5garray[AGCTAB_5G_ARRAYLENGTH] = { ++ 0xc78, 0x7b000001, ++ 0xc78, 0x7b010001, ++ 0xc78, 0x7a020001, ++ 0xc78, 0x79030001, ++ 0xc78, 0x78040001, ++ 0xc78, 0x77050001, ++ 0xc78, 0x76060001, ++ 0xc78, 0x75070001, ++ 0xc78, 0x74080001, ++ 0xc78, 0x73090001, ++ 0xc78, 0x720a0001, ++ 0xc78, 0x710b0001, ++ 0xc78, 0x700c0001, ++ 0xc78, 0x6f0d0001, ++ 0xc78, 0x6e0e0001, ++ 0xc78, 0x6d0f0001, ++ 0xc78, 0x6c100001, ++ 0xc78, 0x6b110001, ++ 0xc78, 0x6a120001, ++ 0xc78, 0x69130001, ++ 0xc78, 0x68140001, ++ 0xc78, 0x67150001, ++ 0xc78, 0x66160001, ++ 0xc78, 0x65170001, ++ 0xc78, 0x64180001, ++ 0xc78, 0x63190001, ++ 0xc78, 0x621a0001, ++ 0xc78, 0x611b0001, ++ 0xc78, 0x601c0001, ++ 0xc78, 0x481d0001, ++ 0xc78, 0x471e0001, ++ 0xc78, 0x461f0001, ++ 0xc78, 0x45200001, ++ 0xc78, 0x44210001, ++ 0xc78, 0x43220001, ++ 0xc78, 0x42230001, ++ 0xc78, 0x41240001, ++ 0xc78, 0x40250001, ++ 0xc78, 0x27260001, ++ 0xc78, 0x26270001, ++ 0xc78, 0x25280001, ++ 0xc78, 0x24290001, ++ 0xc78, 0x232a0001, ++ 0xc78, 0x222b0001, ++ 0xc78, 0x212c0001, ++ 0xc78, 0x202d0001, ++ 0xc78, 0x202e0001, ++ 0xc78, 0x202f0001, ++ 0xc78, 0x20300001, ++ 0xc78, 0x20310001, ++ 0xc78, 0x20320001, ++ 0xc78, 0x20330001, ++ 0xc78, 0x20340001, ++ 0xc78, 0x20350001, ++ 0xc78, 0x20360001, ++ 0xc78, 0x20370001, ++ 0xc78, 0x20380001, ++ 0xc78, 0x20390001, ++ 0xc78, 0x203a0001, ++ 0xc78, 0x203b0001, ++ 0xc78, 0x203c0001, ++ 0xc78, 0x203d0001, ++ 0xc78, 0x203e0001, ++ 0xc78, 0x203f0001, ++ 0xc78, 0x32000044, ++ 0xc78, 0x32010044, ++ 0xc78, 0x32020044, ++ 0xc78, 0x32030044, ++ 0xc78, 0x32040044, ++ 0xc78, 0x32050044, ++ 0xc78, 0x32060044, ++ 0xc78, 0x34070044, ++ 0xc78, 0x35080044, ++ 0xc78, 0x36090044, ++ 0xc78, 0x370a0044, ++ 0xc78, 0x380b0044, ++ 0xc78, 0x390c0044, ++ 0xc78, 0x3a0d0044, ++ 0xc78, 0x3e0e0044, ++ 0xc78, 0x420f0044, ++ 0xc78, 0x44100044, ++ 0xc78, 0x46110044, ++ 0xc78, 0x4a120044, ++ 0xc78, 0x4e130044, ++ 0xc78, 0x50140044, ++ 0xc78, 0x55150044, ++ 0xc78, 0x5a160044, ++ 0xc78, 0x5e170044, ++ 0xc78, 0x64180044, ++ 0xc78, 0x6e190044, ++ 0xc78, 0x6e1a0044, ++ 0xc78, 0x6e1b0044, ++ 0xc78, 0x6e1c0044, ++ 0xc78, 0x6e1d0044, ++ 0xc78, 0x6e1e0044, ++ 0xc78, 0x6e1f0044, ++ 0xc78, 0x6e1f0000, ++}; ++ ++const u32 rtl8192du_agctab_2garray[AGCTAB_2G_ARRAYLENGTH] = { ++ 0xc78, 0x7b000001, ++ 0xc78, 0x7b010001, ++ 0xc78, 0x7b020001, ++ 0xc78, 0x7b030001, ++ 0xc78, 0x7b040001, ++ 0xc78, 0x7b050001, ++ 0xc78, 0x7b060001, ++ 0xc78, 0x7a070001, ++ 0xc78, 0x79080001, ++ 0xc78, 0x78090001, ++ 0xc78, 0x770a0001, ++ 0xc78, 0x760b0001, ++ 0xc78, 0x750c0001, ++ 0xc78, 0x740d0001, ++ 0xc78, 0x730e0001, ++ 0xc78, 0x720f0001, ++ 0xc78, 0x71100001, ++ 0xc78, 0x70110001, ++ 0xc78, 0x6f120001, ++ 0xc78, 0x6e130001, ++ 0xc78, 0x6d140001, ++ 0xc78, 0x6c150001, ++ 0xc78, 0x6b160001, ++ 0xc78, 0x6a170001, ++ 0xc78, 0x69180001, ++ 0xc78, 0x68190001, ++ 0xc78, 0x671a0001, ++ 0xc78, 0x661b0001, ++ 0xc78, 0x651c0001, ++ 0xc78, 0x641d0001, ++ 0xc78, 0x631e0001, ++ 0xc78, 0x621f0001, ++ 0xc78, 0x61200001, ++ 0xc78, 0x60210001, ++ 0xc78, 0x49220001, ++ 0xc78, 0x48230001, ++ 0xc78, 0x47240001, ++ 0xc78, 0x46250001, ++ 0xc78, 0x45260001, ++ 0xc78, 0x44270001, ++ 0xc78, 0x43280001, ++ 0xc78, 0x42290001, ++ 0xc78, 0x412a0001, ++ 0xc78, 0x402b0001, ++ 0xc78, 0x262c0001, ++ 0xc78, 0x252d0001, ++ 0xc78, 0x242e0001, ++ 0xc78, 0x232f0001, ++ 0xc78, 0x22300001, ++ 0xc78, 0x21310001, ++ 0xc78, 0x20320001, ++ 0xc78, 0x06330001, ++ 0xc78, 0x05340001, ++ 0xc78, 0x04350001, ++ 0xc78, 0x03360001, ++ 0xc78, 0x02370001, ++ 0xc78, 0x01380001, ++ 0xc78, 0x00390001, ++ 0xc78, 0x003a0001, ++ 0xc78, 0x003b0001, ++ 0xc78, 0x003c0001, ++ 0xc78, 0x003d0001, ++ 0xc78, 0x003e0001, ++ 0xc78, 0x003f0001, ++ 0xc78, 0x38000002, ++ 0xc78, 0x38010002, ++ 0xc78, 0x38020002, ++ 0xc78, 0x38030002, ++ 0xc78, 0x38040002, ++ 0xc78, 0x38050002, ++ 0xc78, 0x38060002, ++ 0xc78, 0x38070002, ++ 0xc78, 0x38080002, ++ 0xc78, 0x3c090002, ++ 0xc78, 0x3e0a0002, ++ 0xc78, 0x400b0002, ++ 0xc78, 0x440c0002, ++ 0xc78, 0x480d0002, ++ 0xc78, 0x4c0e0002, ++ 0xc78, 0x500f0002, ++ 0xc78, 0x52100002, ++ 0xc78, 0x56110002, ++ 0xc78, 0x5a120002, ++ 0xc78, 0x5e130002, ++ 0xc78, 0x60140002, ++ 0xc78, 0x60150002, ++ 0xc78, 0x60160002, ++ 0xc78, 0x62170002, ++ 0xc78, 0x62180002, ++ 0xc78, 0x62190002, ++ 0xc78, 0x621a0002, ++ 0xc78, 0x621b0002, ++ 0xc78, 0x621c0002, ++ 0xc78, 0x621d0002, ++ 0xc78, 0x621e0002, ++ 0xc78, 0x621f0002, ++ 0xc78, 0x6e1f0000, ++}; +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h +new file mode 100644 +index 000000000000..b809ba511320 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h +@@ -0,0 +1,29 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_TABLE_H__ ++#define __RTL92DU_TABLE_H__ ++ ++#define PHY_REG_2T_ARRAYLENGTH 372 ++#define PHY_REG_ARRAY_PG_LENGTH 624 ++#define RADIOA_2T_ARRAYLENGTH 378 ++#define RADIOB_2T_ARRAYLENGTH 384 ++#define RADIOA_2T_INT_PA_ARRAYLENGTH 378 ++#define RADIOB_2T_INT_PA_ARRAYLENGTH 384 ++#define MAC_2T_ARRAYLENGTH 192 ++#define AGCTAB_ARRAYLENGTH 386 ++#define AGCTAB_5G_ARRAYLENGTH 194 ++#define AGCTAB_2G_ARRAYLENGTH 194 ++ ++extern const u32 rtl8192du_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH]; ++extern const u32 rtl8192du_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH]; ++extern const u32 rtl8192du_radioa_2tarray[RADIOA_2T_ARRAYLENGTH]; ++extern const u32 rtl8192du_radiob_2tarray[RADIOB_2T_ARRAYLENGTH]; ++extern const u32 rtl8192du_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH]; ++extern const u32 rtl8192du_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH]; ++extern const u32 rtl8192du_mac_2tarray[MAC_2T_ARRAYLENGTH]; ++extern const u32 rtl8192du_agctab_array[AGCTAB_ARRAYLENGTH]; ++extern const u32 rtl8192du_agctab_5garray[AGCTAB_5G_ARRAYLENGTH]; ++extern const u32 rtl8192du_agctab_2garray[AGCTAB_2G_ARRAYLENGTH]; ++ ++#endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0020-FROMGIT-6.11-wifi-rtlwifi-Add-new-members-to-struct-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0020-FROMGIT-6.11-wifi-rtlwifi-Add-new-members-to-struct-.patch new file mode 100644 index 0000000000..3f8ca00177 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0020-FROMGIT-6.11-wifi-rtlwifi-Add-new-members-to-struct-.patch @@ -0,0 +1,39 @@ +From 34ddbe7398b1e23d78192999dcc88a7f57bcaae5 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:44:39 +0300 +Subject: [PATCH 20/69] FROMGIT(6.11): wifi: rtlwifi: Add new members to struct + rtl_priv for RTL8192DU + +These are needed for the dual MAC version of RTL8192DU. + +The two mutexes are used to avoid concurrent access to the hardware +from the two USB interfaces. + +The two arrays are filled by one interface during LC calibration and +accessed by the other interface during channel switching. + +Signed-off-by: Bitterblue Smith +--- + drivers/net/wireless/realtek/rtlwifi/wifi.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h +index 4f1c21c130f4..2e88359ba917 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/wifi.h ++++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h +@@ -2773,6 +2773,12 @@ struct rtl_priv { + */ + bool use_new_trx_flow; + ++ /* For dual MAC RTL8192DU, things shared by the 2 USB interfaces */ ++ u32 *curveindex_2g; ++ u32 *curveindex_5g; ++ struct mutex *mutex_for_power_on_off; /* for power on/off */ ++ struct mutex *mutex_for_hw_init; /* for hardware init */ ++ + #ifdef CONFIG_PM + struct wiphy_wowlan_support wowlan; + #endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0021-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0021-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch new file mode 100644 index 0000000000..ede573a835 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0021-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch @@ -0,0 +1,1264 @@ +From 37626e4f236435875f40fd3e8a463aac1cd47c8b Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:45:31 +0300 +Subject: [PATCH 21/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/hw.{c,h} + +These contain mostly hardware init/deinit routines for RTL8192DU. + +Signed-off-by: Bitterblue Smith +--- + .../wireless/realtek/rtlwifi/rtl8192du/hw.c | 1212 +++++++++++++++++ + .../wireless/realtek/rtlwifi/rtl8192du/hw.h | 22 + + 2 files changed, 1234 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c +new file mode 100644 +index 000000000000..700c6e2bcad1 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c +@@ -0,0 +1,1212 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../cam.h" ++#include "../usb.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/dm_common.h" ++#include "../rtl8192d/fw_common.h" ++#include "../rtl8192d/hw_common.h" ++#include "../rtl8192d/phy_common.h" ++#include "phy.h" ++#include "dm.h" ++#include "fw.h" ++#include "hw.h" ++#include "trx.h" ++ ++static void _rtl92du_set_bcn_ctrl_reg(struct ieee80211_hw *hw, ++ u8 set_bits, u8 clear_bits) ++{ ++ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ rtlusb->reg_bcn_ctrl_val |= set_bits; ++ rtlusb->reg_bcn_ctrl_val &= ~clear_bits; ++ rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); ++} ++ ++static void _rtl92du_enable_bcn_sub_func(struct ieee80211_hw *hw) ++{ ++ _rtl92du_set_bcn_ctrl_reg(hw, 0, BIT(1)); ++} ++ ++static void _rtl92du_disable_bcn_sub_func(struct ieee80211_hw *hw) ++{ ++ _rtl92du_set_bcn_ctrl_reg(hw, BIT(1), 0); ++} ++ ++void rtl92du_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) ++{ ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ ++ switch (variable) { ++ case HW_VAR_RCR: ++ *((u32 *)val) = mac->rx_conf; ++ break; ++ default: ++ rtl92d_get_hw_reg(hw, variable, val); ++ break; ++ } ++} ++ ++void rtl92du_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ ++ switch (variable) { ++ case HW_VAR_AC_PARAM: ++ rtl92d_dm_init_edca_turbo(hw); ++ break; ++ case HW_VAR_ACM_CTRL: { ++ u8 e_aci = *val; ++ union aci_aifsn *p_aci_aifsn = ++ (union aci_aifsn *)(&mac->ac[0].aifs); ++ u8 acm = p_aci_aifsn->f.acm; ++ u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); ++ ++ if (acm) { ++ switch (e_aci) { ++ case AC0_BE: ++ acm_ctrl |= ACMHW_BEQEN; ++ break; ++ case AC2_VI: ++ acm_ctrl |= ACMHW_VIQEN; ++ break; ++ case AC3_VO: ++ acm_ctrl |= ACMHW_VOQEN; ++ break; ++ default: ++ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, ++ "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", ++ acm); ++ break; ++ } ++ } else { ++ switch (e_aci) { ++ case AC0_BE: ++ acm_ctrl &= (~ACMHW_BEQEN); ++ break; ++ case AC2_VI: ++ acm_ctrl &= (~ACMHW_VIQEN); ++ break; ++ case AC3_VO: ++ acm_ctrl &= (~ACMHW_VOQEN); ++ break; ++ default: ++ pr_err("%s:%d switch case %#x not processed\n", ++ __func__, __LINE__, e_aci); ++ break; ++ } ++ } ++ rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, ++ "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", ++ acm_ctrl); ++ rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); ++ break; ++ } ++ case HW_VAR_RCR: ++ mac->rx_conf = ((u32 *)val)[0]; ++ rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf); ++ break; ++ case HW_VAR_H2C_FW_JOINBSSRPT: { ++ u8 tmp_regcr, tmp_reg422; ++ bool recover = false; ++ u8 mstatus = *val; ++ ++ if (mstatus == RT_MEDIA_CONNECT) { ++ rtlpriv->cfg->ops->set_hw_reg(hw, ++ HW_VAR_AID, NULL); ++ tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); ++ rtl_write_byte(rtlpriv, REG_CR + 1, ++ tmp_regcr | ENSWBCN); ++ _rtl92du_set_bcn_ctrl_reg(hw, 0, EN_BCN_FUNCTION); ++ _rtl92du_set_bcn_ctrl_reg(hw, DIS_TSF_UDT, 0); ++ tmp_reg422 = rtl_read_byte(rtlpriv, ++ REG_FWHW_TXQ_CTRL + 2); ++ if (tmp_reg422 & (EN_BCNQ_DL >> 16)) ++ recover = true; ++ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, ++ tmp_reg422 & ~(EN_BCNQ_DL >> 16)); ++ ++ /* We don't implement FW LPS so this is not needed. */ ++ /* rtl92d_set_fw_rsvdpagepkt(hw, 0); */ ++ ++ _rtl92du_set_bcn_ctrl_reg(hw, EN_BCN_FUNCTION, 0); ++ _rtl92du_set_bcn_ctrl_reg(hw, 0, DIS_TSF_UDT); ++ if (recover) ++ rtl_write_byte(rtlpriv, ++ REG_FWHW_TXQ_CTRL + 2, ++ tmp_reg422); ++ rtl_write_byte(rtlpriv, REG_CR + 1, ++ tmp_regcr & ~ENSWBCN); ++ } ++ rtl92d_set_fw_joinbss_report_cmd(hw, (*val)); ++ break; ++ } ++ case HW_VAR_CORRECT_TSF: { ++ u8 btype_ibss = val[0]; ++ ++ if (btype_ibss) ++ rtl92d_stop_tx_beacon(hw); ++ _rtl92du_set_bcn_ctrl_reg(hw, 0, EN_BCN_FUNCTION); ++ rtl_write_dword(rtlpriv, REG_TSFTR, ++ (u32)(mac->tsf & 0xffffffff)); ++ rtl_write_dword(rtlpriv, REG_TSFTR + 4, ++ (u32)((mac->tsf >> 32) & 0xffffffff)); ++ _rtl92du_set_bcn_ctrl_reg(hw, EN_BCN_FUNCTION, 0); ++ if (btype_ibss) ++ rtl92d_resume_tx_beacon(hw); ++ ++ break; ++ } ++ case HW_VAR_KEEP_ALIVE: ++ /* Avoid "switch case not processed" error. RTL8192DU doesn't ++ * need to do anything here, maybe. ++ */ ++ break; ++ default: ++ rtl92d_set_hw_reg(hw, variable, val); ++ break; ++ } ++} ++ ++static void _rtl92du_init_queue_reserved_page(struct ieee80211_hw *hw, ++ u8 out_ep_num, ++ u8 queue_sel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ u32 txqpagenum, txqpageunit; ++ u32 txqremainingpage; ++ u32 numhq = 0; ++ u32 numlq = 0; ++ u32 numnq = 0; ++ u32 numpubq; ++ u32 value32; ++ ++ if (rtlhal->macphymode != SINGLEMAC_SINGLEPHY) { ++ numpubq = NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC; ++ txqpagenum = TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC - numpubq; ++ } else { ++ numpubq = TEST_PAGE_NUM_PUBQ_92DU; ++ txqpagenum = TX_TOTAL_PAGE_NUMBER_92DU - numpubq; ++ } ++ ++ if (rtlhal->macphymode != SINGLEMAC_SINGLEPHY && out_ep_num == 3) { ++ numhq = NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC; ++ numlq = NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC; ++ numnq = NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC; ++ } else { ++ txqpageunit = txqpagenum / out_ep_num; ++ txqremainingpage = txqpagenum % out_ep_num; ++ ++ if (queue_sel & TX_SELE_HQ) ++ numhq = txqpageunit; ++ if (queue_sel & TX_SELE_LQ) ++ numlq = txqpageunit; ++ if (queue_sel & TX_SELE_NQ) ++ numnq = txqpageunit; ++ ++ /* HIGH priority queue always present in the ++ * configuration of 2 or 3 out-ep. Remainder pages ++ * assigned to High queue ++ */ ++ if (out_ep_num > 1 && txqremainingpage) ++ numhq += txqremainingpage; ++ } ++ ++ /* NOTE: This step done before writing REG_RQPN. */ ++ rtl_write_byte(rtlpriv, REG_RQPN_NPQ, (u8)numnq); ++ ++ /* TX DMA */ ++ u32p_replace_bits(&value32, numhq, HPQ_MASK); ++ u32p_replace_bits(&value32, numlq, LPQ_MASK); ++ u32p_replace_bits(&value32, numpubq, PUBQ_MASK); ++ value32 |= LD_RQPN; ++ rtl_write_dword(rtlpriv, REG_RQPN, value32); ++} ++ ++static void _rtl92du_init_tx_buffer_boundary(struct ieee80211_hw *hw, ++ u8 txpktbuf_bndy) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); ++ rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); ++ ++ rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); ++ ++ /* TXRKTBUG_PG_BNDY */ ++ rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); ++ ++ /* Beacon Head for TXDMA */ ++ rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); ++} ++ ++static bool _rtl92du_llt_table_init(struct ieee80211_hw *hw, u8 txpktbuf_bndy) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ unsigned short i; ++ bool status; ++ u8 maxpage; ++ ++ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) ++ maxpage = 255; ++ else ++ maxpage = 127; ++ ++ for (i = 0; i < (txpktbuf_bndy - 1); i++) { ++ status = rtl92d_llt_write(hw, i, i + 1); ++ if (!status) ++ return status; ++ } ++ ++ /* end of list */ ++ status = rtl92d_llt_write(hw, txpktbuf_bndy - 1, 0xFF); ++ if (!status) ++ return status; ++ ++ /* Make the other pages as ring buffer ++ * This ring buffer is used as beacon buffer if we ++ * config this MAC as two MAC transfer. ++ * Otherwise used as local loopback buffer. ++ */ ++ for (i = txpktbuf_bndy; i < maxpage; i++) { ++ status = rtl92d_llt_write(hw, i, i + 1); ++ if (!status) ++ return status; ++ } ++ ++ /* Let last entry point to the start entry of ring buffer */ ++ status = rtl92d_llt_write(hw, maxpage, txpktbuf_bndy); ++ if (!status) ++ return status; ++ ++ return true; ++} ++ ++static void _rtl92du_init_chipn_reg_priority(struct ieee80211_hw *hw, u16 beq, ++ u16 bkq, u16 viq, u16 voq, ++ u16 mgtq, u16 hiq) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u16 value16; ++ ++ value16 = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7; ++ u16p_replace_bits(&value16, beq, TXDMA_BEQ_MAP); ++ u16p_replace_bits(&value16, bkq, TXDMA_BKQ_MAP); ++ u16p_replace_bits(&value16, viq, TXDMA_VIQ_MAP); ++ u16p_replace_bits(&value16, voq, TXDMA_VOQ_MAP); ++ u16p_replace_bits(&value16, mgtq, TXDMA_MGQ_MAP); ++ u16p_replace_bits(&value16, hiq, TXDMA_HIQ_MAP); ++ rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); ++} ++ ++static void _rtl92du_init_chipn_one_out_ep_priority(struct ieee80211_hw *hw, ++ u8 queue_sel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u16 value; ++ ++ switch (queue_sel) { ++ case TX_SELE_HQ: ++ value = QUEUE_HIGH; ++ break; ++ case TX_SELE_LQ: ++ value = QUEUE_LOW; ++ break; ++ case TX_SELE_NQ: ++ value = QUEUE_NORMAL; ++ break; ++ default: ++ WARN_ON(1); /* Shall not reach here! */ ++ return; ++ } ++ _rtl92du_init_chipn_reg_priority(hw, value, value, value, value, ++ value, value); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "Tx queue select: 0x%02x\n", queue_sel); ++} ++ ++static void _rtl92du_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw, ++ u8 queue_sel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u16 beq, bkq, viq, voq, mgtq, hiq; ++ u16 valuehi, valuelow; ++ ++ switch (queue_sel) { ++ default: ++ WARN_ON(1); ++ fallthrough; ++ case (TX_SELE_HQ | TX_SELE_LQ): ++ valuehi = QUEUE_HIGH; ++ valuelow = QUEUE_LOW; ++ break; ++ case (TX_SELE_NQ | TX_SELE_LQ): ++ valuehi = QUEUE_NORMAL; ++ valuelow = QUEUE_LOW; ++ break; ++ case (TX_SELE_HQ | TX_SELE_NQ): ++ valuehi = QUEUE_HIGH; ++ valuelow = QUEUE_NORMAL; ++ break; ++ } ++ ++ beq = valuelow; ++ bkq = valuelow; ++ viq = valuehi; ++ voq = valuehi; ++ mgtq = valuehi; ++ hiq = valuehi; ++ ++ _rtl92du_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "Tx queue select: 0x%02x\n", queue_sel); ++} ++ ++static void _rtl92du_init_chipn_three_out_ep_priority(struct ieee80211_hw *hw, ++ u8 queue_sel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u16 beq, bkq, viq, voq, mgtq, hiq; ++ ++ beq = QUEUE_LOW; ++ bkq = QUEUE_LOW; ++ viq = QUEUE_NORMAL; ++ voq = QUEUE_HIGH; ++ mgtq = QUEUE_HIGH; ++ hiq = QUEUE_HIGH; ++ ++ _rtl92du_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "Tx queue select: 0x%02x\n", queue_sel); ++} ++ ++static void _rtl92du_init_queue_priority(struct ieee80211_hw *hw, ++ u8 out_ep_num, ++ u8 queue_sel) ++{ ++ switch (out_ep_num) { ++ case 1: ++ _rtl92du_init_chipn_one_out_ep_priority(hw, queue_sel); ++ break; ++ case 2: ++ _rtl92du_init_chipn_two_out_ep_priority(hw, queue_sel); ++ break; ++ case 3: ++ _rtl92du_init_chipn_three_out_ep_priority(hw, queue_sel); ++ break; ++ default: ++ WARN_ON(1); /* Shall not reach here! */ ++ break; ++ } ++} ++ ++static void _rtl92du_init_wmac_setting(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ ++ mac->rx_conf = RCR_APM | RCR_AM | RCR_AB | RCR_ADF | RCR_APP_ICV | ++ RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | ++ RCR_APP_PHYST_RXFF | RCR_APPFCS; ++ ++ rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf); ++ ++ /* Set Multicast Address. */ ++ rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); ++ rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); ++} ++ ++static void _rtl92du_init_adaptive_ctrl(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 val32; ++ ++ val32 = rtl_read_dword(rtlpriv, REG_RRSR); ++ val32 &= ~0xfffff; ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) ++ val32 |= 0xffff0; /* No CCK */ ++ else ++ val32 |= 0xffff1; ++ rtl_write_dword(rtlpriv, REG_RRSR, val32); ++ ++ /* Set Spec SIFS (used in NAV) */ ++ rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); ++ ++ /* Retry limit 0x30 */ ++ rtl_write_word(rtlpriv, REG_RL, 0x3030); ++} ++ ++static void _rtl92du_init_edca(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u16 val16; ++ ++ /* Disable EDCCA count down, to reduce collison and retry */ ++ val16 = rtl_read_word(rtlpriv, REG_RD_CTRL); ++ val16 |= DIS_EDCA_CNT_DWN; ++ rtl_write_word(rtlpriv, REG_RD_CTRL, val16); ++ ++ /* CCK SIFS shall always be 10us. */ ++ rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x0a0a); ++ /* Set SIFS for OFDM */ ++ rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); ++ ++ rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204); ++ ++ rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004); ++ ++ /* TXOP */ ++ rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B); ++ rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F); ++ rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324); ++ rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226); ++ ++ rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); ++ ++ rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); ++ ++ rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); ++ ++ rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x2); ++ rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); ++} ++ ++static void _rtl92du_init_retry_function(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 val8; ++ ++ val8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL); ++ val8 |= EN_AMPDU_RTY_NEW; ++ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, val8); ++ ++ rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); ++} ++ ++static void _rtl92du_init_operation_mode(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ ++ rtl_write_byte(rtlpriv, REG_BWOPMODE, BW_OPMODE_20MHZ); ++ ++ switch (rtlpriv->phy.rf_type) { ++ case RF_1T2R: ++ case RF_1T1R: ++ rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); ++ break; ++ case RF_2T2R: ++ case RF_2T2R_GREEN: ++ rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); ++ break; ++ } ++ rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, rtlhal->minspace_cfg); ++} ++ ++static void _rtl92du_init_beacon_parameters(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); ++ ++ rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x3c02); ++ rtl_write_byte(rtlpriv, REG_DRVERLYINT, 0x05); ++ rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x03); ++ ++ rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); ++} ++ ++static void _rtl92du_init_ampdu_aggregation(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ ++ /* Aggregation threshold */ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY) ++ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66525541); ++ else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) ++ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x44444441); ++ else ++ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x88728841); ++ ++ rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); ++} ++ ++static bool _rtl92du_init_power_on(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ unsigned short wordtmp; ++ unsigned char bytetmp; ++ u16 retry = 0; ++ ++ do { ++ if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) ++ break; ++ ++ if (retry++ > 1000) ++ return false; ++ } while (true); ++ ++ /* Unlock ISO/CLK/Power control register */ ++ rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); ++ ++ /* SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */ ++ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); ++ ++ msleep(1); ++ ++ bytetmp = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); ++ if ((bytetmp & LDV12_EN) == 0) { ++ bytetmp |= LDV12_EN; ++ rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, bytetmp); ++ ++ msleep(1); ++ ++ bytetmp = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); ++ bytetmp &= ~ISO_MD2PP; ++ rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, bytetmp); ++ } ++ ++ /* Auto enable WLAN */ ++ wordtmp = rtl_read_word(rtlpriv, REG_APS_FSMCO); ++ wordtmp |= APFM_ONMAC; ++ rtl_write_word(rtlpriv, REG_APS_FSMCO, wordtmp); ++ ++ wordtmp = rtl_read_word(rtlpriv, REG_APS_FSMCO); ++ retry = 0; ++ while ((wordtmp & APFM_ONMAC) && retry < 1000) { ++ retry++; ++ wordtmp = rtl_read_word(rtlpriv, REG_APS_FSMCO); ++ } ++ ++ /* Release RF digital isolation */ ++ wordtmp = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); ++ wordtmp &= ~ISO_DIOR; ++ rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, wordtmp); ++ ++ /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ ++ wordtmp = rtl_read_word(rtlpriv, REG_CR); ++ wordtmp |= HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | ++ PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC; ++ rtl_write_word(rtlpriv, REG_CR, wordtmp); ++ ++ return true; ++} ++ ++static bool _rtl92du_init_mac(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 val8; ++ ++ rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); ++ ++ val8 = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); ++ val8 &= ~(FEN_MREGEN >> 8); ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, val8); ++ ++ /* For s3/s4 may reset mac, Reg0xf8 may be set to 0, ++ * so reset macphy control reg here. ++ */ ++ rtl92d_phy_config_macphymode(hw); ++ ++ rtl92du_phy_set_poweron(hw); ++ ++ if (!_rtl92du_init_power_on(hw)) { ++ pr_err("Failed to init power on!\n"); ++ return false; ++ } ++ ++ rtl92d_phy_config_maccoexist_rfpage(hw); ++ ++ return true; ++} ++ ++int rtl92du_hw_init(struct ieee80211_hw *hw) ++{ ++ struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); ++ struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 val8, txpktbuf_bndy; ++ int err, i; ++ u32 val32; ++ u16 val16; ++ ++ mutex_lock(rtlpriv->mutex_for_hw_init); ++ ++ /* we should do iqk after disable/enable */ ++ rtl92d_phy_reset_iqk_result(hw); ++ ++ if (!_rtl92du_init_mac(hw)) { ++ pr_err("Init MAC failed\n"); ++ mutex_unlock(rtlpriv->mutex_for_hw_init); ++ return 1; ++ } ++ ++ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) ++ txpktbuf_bndy = 249; ++ else ++ txpktbuf_bndy = 123; ++ ++ if (!_rtl92du_llt_table_init(hw, txpktbuf_bndy)) { ++ pr_err("Init LLT failed\n"); ++ mutex_unlock(rtlpriv->mutex_for_hw_init); ++ return 1; ++ } ++ ++ err = rtl92du_download_fw(hw); ++ ++ /* return fail only when part number check fail */ ++ if (err && rtl_read_byte(rtlpriv, 0x1c5) == 0xe0) { ++ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, ++ "Failed to download FW. Init HW without FW..\n"); ++ mutex_unlock(rtlpriv->mutex_for_hw_init); ++ return 1; ++ } ++ rtlhal->last_hmeboxnum = 0; ++ rtlpriv->psc.fw_current_inpsmode = false; ++ ++ rtl92du_phy_mac_config(hw); ++ ++ /* Set reserved page for each queue */ ++ _rtl92du_init_queue_reserved_page(hw, rtlusb->out_ep_nums, ++ rtlusb->out_queue_sel); ++ ++ _rtl92du_init_tx_buffer_boundary(hw, txpktbuf_bndy); ++ ++ _rtl92du_init_queue_priority(hw, rtlusb->out_ep_nums, ++ rtlusb->out_queue_sel); ++ ++ /* Set Tx/Rx page size (Tx must be 128 Bytes, ++ * Rx can be 64, 128, 256, 512, 1024 bytes) ++ */ ++ rtl_write_byte(rtlpriv, REG_PBP, 0x11); ++ ++ /* Get Rx PHY status in order to report RSSI and others. */ ++ rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); ++ ++ rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); ++ rtl_write_dword(rtlpriv, REG_HIMR, 0xffffffff); ++ ++ val8 = rtl_read_byte(rtlpriv, MSR); ++ val8 &= ~MSR_MASK; ++ val8 |= MSR_INFRA; ++ rtl_write_byte(rtlpriv, MSR, val8); ++ ++ _rtl92du_init_wmac_setting(hw); ++ _rtl92du_init_adaptive_ctrl(hw); ++ _rtl92du_init_edca(hw); ++ ++ rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000); ++ rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x10080404); ++ rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201); ++ rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x08070605); ++ ++ _rtl92du_init_retry_function(hw); ++ /* _InitUsbAggregationSetting(padapter); no aggregation for now */ ++ _rtl92du_init_operation_mode(hw); ++ _rtl92du_init_beacon_parameters(hw); ++ _rtl92du_init_ampdu_aggregation(hw); ++ ++ rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); ++ ++ /* unit: 256us. 256ms */ ++ rtl_write_word(rtlpriv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); ++ rtl_write_word(rtlpriv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); ++ ++ /* Hardware-controlled blinking. */ ++ rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8282); ++ rtl_write_byte(rtlpriv, REG_LEDCFG2, 0x82); ++ ++ val32 = rtl_read_dword(rtlpriv, REG_TXDMA_OFFSET_CHK); ++ val32 |= DROP_DATA_EN; ++ rtl_write_dword(rtlpriv, REG_TXDMA_OFFSET_CHK, val32); ++ ++ if (mac->rdg_en) { ++ rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); ++ rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); ++ rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); ++ } ++ ++ for (i = 0; i < 4; i++) ++ rtl_write_dword(rtlpriv, REG_ARFR0 + i * 4, 0x1f8ffff0); ++ ++ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { ++ if (rtlusb->out_ep_nums == 2) ++ rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03066666); ++ else ++ rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x8888); ++ } else { ++ rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x5555); ++ } ++ ++ val8 = rtl_read_byte(rtlpriv, 0x605); ++ val8 |= 0xf0; ++ rtl_write_byte(rtlpriv, 0x605, val8); ++ ++ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x30); ++ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); ++ rtl_write_byte(rtlpriv, 0x606, 0x30); ++ ++ /* temp for high queue and mgnt Queue corrupt in time; it may ++ * cause hang when sw beacon use high_Q, other frame use mgnt_Q; ++ * or, sw beacon use mgnt_Q, other frame use high_Q; ++ */ ++ rtl_write_byte(rtlpriv, REG_DIS_TXREQ_CLR, 0x10); ++ val16 = rtl_read_word(rtlpriv, REG_RD_CTRL); ++ val16 |= BIT(12); ++ rtl_write_word(rtlpriv, REG_RD_CTRL, val16); ++ ++ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0); ++ ++ /* usb suspend idle time count for bitfile0927 */ ++ val8 = rtl_read_byte(rtlpriv, 0xfe56); ++ val8 |= BIT(0) | BIT(1); ++ rtl_write_byte(rtlpriv, 0xfe56, val8); ++ ++ if (rtlhal->earlymode_enable) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "EarlyMode Enabled!!!\n"); ++ ++ val8 = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL); ++ val8 |= 0x1f; ++ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, val8); ++ ++ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL + 3, 0x80); ++ ++ val8 = rtl_read_byte(rtlpriv, 0x605); ++ val8 |= 0x40; ++ rtl_write_byte(rtlpriv, 0x605, val8); ++ } else { ++ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0); ++ } ++ ++ rtl92du_phy_bb_config(hw); ++ ++ rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; ++ /* set before initialize RF */ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); ++ ++ /* config RF */ ++ rtl92du_phy_rf_config(hw); ++ ++ /* set default value after initialize RF */ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); ++ ++ /* After load BB, RF params, we need to do more for 92D. */ ++ rtl92du_update_bbrf_configuration(hw); ++ ++ rtlphy->rfreg_chnlval[0] = ++ rtl_get_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK); ++ rtlphy->rfreg_chnlval[1] = ++ rtl_get_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK); ++ ++ /*---- Set CCK and OFDM Block "ON"----*/ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) ++ rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); ++ rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); ++ ++ /* reset hw sec */ ++ rtl_cam_reset_all_entry(hw); ++ rtl92d_enable_hw_security_config(hw); ++ ++ rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); ++ ++ /* schmitt trigger, improve tx evm for 92du */ ++ val8 = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL); ++ val8 |= BIT(1); ++ rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, val8); ++ ++ /* Disable bar */ ++ rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0xffff); ++ ++ /* Nav limit */ ++ rtl_write_byte(rtlpriv, REG_NAV_CTRL + 2, 0); ++ rtl_write_byte(rtlpriv, ROFDM0_XATXAFE + 3, 0x50); ++ ++ /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct ++ * TX power index for different rate set. ++ */ ++ rtl92d_phy_get_hw_reg_originalvalue(hw); ++ ++ ppsc->rfpwr_state = ERFON; ++ ++ /* do IQK for 2.4G for better scan result */ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) ++ rtl92du_phy_iq_calibrate(hw); ++ ++ rtl92du_phy_lc_calibrate(hw, IS_92D_SINGLEPHY(rtlhal->version)); ++ ++ rtl92du_phy_init_pa_bias(hw); ++ ++ mutex_unlock(rtlpriv->mutex_for_hw_init); ++ ++ rtl92du_dm_init(hw); ++ ++ /* For 2 PORT TSF SYNC */ ++ rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1818); ++ rtlusb->reg_bcn_ctrl_val = 0x18; ++ ++ udelay(500); ++ ++ if (rtlhal->macphymode != DUALMAC_DUALPHY) { ++ rtl_write_dword(rtlpriv, RFPGA1_TXINFO, ++ rtl_read_dword(rtlpriv, RFPGA1_TXINFO) & ~BIT(30)); ++ ++ rtl_write_dword(rtlpriv, RFPGA0_TXGAINSTAGE, ++ rtl_read_dword(rtlpriv, RFPGA0_TXGAINSTAGE) & ~BIT(31)); ++ ++ rtl_write_dword(rtlpriv, ROFDM0_XBTXAFE, 0xa0e40000); ++ } ++ ++ val32 = rtl_read_dword(rtlpriv, REG_FWHW_TXQ_CTRL); ++ val32 |= BIT(12); ++ rtl_write_dword(rtlpriv, REG_FWHW_TXQ_CTRL, val32); ++ ++ return err; ++} ++ ++static int _rtl92du_set_media_status(struct ieee80211_hw *hw, ++ enum nl80211_iftype type) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ enum led_ctl_mode ledaction = LED_CTL_NO_LINK; ++ u8 bt_msr = rtl_read_byte(rtlpriv, MSR); ++ ++ bt_msr &= 0xfc; ++ ++ if (type == NL80211_IFTYPE_UNSPECIFIED || ++ type == NL80211_IFTYPE_STATION) { ++ rtl92d_stop_tx_beacon(hw); ++ _rtl92du_enable_bcn_sub_func(hw); ++ } else if (type == NL80211_IFTYPE_ADHOC || ++ type == NL80211_IFTYPE_AP) { ++ rtl92d_resume_tx_beacon(hw); ++ _rtl92du_disable_bcn_sub_func(hw); ++ } else { ++ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, ++ "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n", ++ type); ++ } ++ ++ switch (type) { ++ case NL80211_IFTYPE_UNSPECIFIED: ++ bt_msr |= MSR_NOLINK; ++ ledaction = LED_CTL_LINK; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "Set Network type to NO LINK!\n"); ++ break; ++ case NL80211_IFTYPE_ADHOC: ++ bt_msr |= MSR_ADHOC; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "Set Network type to Ad Hoc!\n"); ++ break; ++ case NL80211_IFTYPE_STATION: ++ bt_msr |= MSR_INFRA; ++ ledaction = LED_CTL_LINK; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "Set Network type to STA!\n"); ++ break; ++ case NL80211_IFTYPE_AP: ++ bt_msr |= MSR_AP; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "Set Network type to AP!\n"); ++ break; ++ default: ++ pr_err("Network type %d not supported!\n", type); ++ return 1; ++ } ++ rtl_write_byte(rtlpriv, MSR, bt_msr); ++ ++ rtlpriv->cfg->ops->led_control(hw, ledaction); ++ ++ if ((bt_msr & MSR_MASK) == MSR_AP) ++ rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); ++ else ++ rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); ++ ++ return 0; ++} ++ ++void rtl92du_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 reg_rcr; ++ ++ if (rtlpriv->psc.rfpwr_state != ERFON) ++ return; ++ ++ rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); ++ ++ if (check_bssid) { ++ reg_rcr |= RCR_CBSSID_DATA | RCR_CBSSID_BCN; ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)®_rcr); ++ _rtl92du_set_bcn_ctrl_reg(hw, 0, DIS_TSF_UDT); ++ } else if (!check_bssid) { ++ reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); ++ _rtl92du_set_bcn_ctrl_reg(hw, DIS_TSF_UDT, 0); ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)®_rcr); ++ } ++} ++ ++int rtl92du_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ if (_rtl92du_set_media_status(hw, type)) ++ return -EOPNOTSUPP; ++ ++ /* check bssid */ ++ if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { ++ if (type != NL80211_IFTYPE_AP) ++ rtl92du_set_check_bssid(hw, true); ++ } else { ++ rtl92du_set_check_bssid(hw, false); ++ } ++ ++ return 0; ++} ++ ++/* do iqk or reload iqk */ ++/* windows just rtl92d_phy_reload_iqk_setting in set channel, ++ * but it's very strict for time sequence so we add ++ * rtl92d_phy_reload_iqk_setting here ++ */ ++void rtl92du_linked_set_reg(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 channel = rtlphy->current_channel; ++ u8 indexforchannel; ++ ++ indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); ++ if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) { ++ rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG, ++ "Do IQK for channel:%d\n", channel); ++ rtl92du_phy_iq_calibrate(hw); ++ } ++} ++ ++void rtl92du_enable_interrupt(struct ieee80211_hw *hw) ++{ ++ /* Nothing to do. */ ++} ++ ++void rtl92du_disable_interrupt(struct ieee80211_hw *hw) ++{ ++ /* Nothing to do. */ ++} ++ ++static void _rtl92du_poweroff_adapter(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 retry = 100; ++ u8 u1b_tmp; ++ u16 val16; ++ u32 val32; ++ ++ rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); ++ ++ rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); ++ ++ /* IF fw in RAM code, do reset */ ++ if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) { ++ rtl_write_byte(rtlpriv, REG_FSIMR, 0); ++ ++ /* We need to disable other HRCV INT to influence 8051 reset. */ ++ rtl_write_byte(rtlpriv, REG_FWIMR, 0x20); ++ ++ /* Close mask to prevent incorrect FW write operation. */ ++ rtl_write_byte(rtlpriv, REG_FTIMR, 0); ++ ++ rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); ++ ++ /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ ++ rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); ++ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); ++ while (val16 & FEN_CPUEN) { ++ retry--; ++ if (retry == 0) ++ break; ++ udelay(50); ++ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); ++ } ++ ++ if (retry == 0) { ++ rtl_write_byte(rtlpriv, REG_FWIMR, 0); ++ ++ /* if 8051 reset fail, reset MAC directly. */ ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x50); ++ ++ mdelay(10); ++ } ++ } ++ ++ /* reset MCU, MAC register, DCORE */ ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); ++ ++ /* reset MCU ready status */ ++ rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); ++ ++ /* Pull GPIO PIN to balance level and LED control */ ++ ++ /* Disable GPIO[7:0] */ ++ rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL + 2, 0x0000); ++ val32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL); ++ u32p_replace_bits(&val32, val32 & 0xff, 0x0000ff00); ++ u32p_replace_bits(&val32, 0xff, 0x00ff0000); ++ rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, val32); ++ ++ /* Disable GPIO[10:8] */ ++ rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 0); ++ val16 = rtl_read_word(rtlpriv, REG_GPIO_IO_SEL); ++ u16p_replace_bits(&val16, val16 & 0xf, 0x00f0); ++ u16p_replace_bits(&val16, 0xf, 0x0780); ++ rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, val16); ++ ++ /* Disable LED 0, 1, and 2 */ ++ rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8888); ++ rtl_write_byte(rtlpriv, REG_LEDCFG2, 0x88); ++ ++ /* Disable analog sequence */ ++ ++ /* enter PFM mode */ ++ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); ++ ++ rtl_write_word(rtlpriv, REG_APS_FSMCO, ++ APDM_HOST | AFSM_HSUS | PFM_ALDN); ++ ++ /* lock ISO/CLK/Power control register */ ++ rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "In PowerOff,reg0x%x=%X\n", ++ REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL)); ++ ++ /* 0x17[7] 1b': power off in process 0b' : power off over */ ++ if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { ++ mutex_lock(rtlpriv->mutex_for_power_on_off); ++ u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); ++ u1b_tmp &= ~BIT(7); ++ rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp); ++ mutex_unlock(rtlpriv->mutex_for_power_on_off); ++ } ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n"); ++} ++ ++void rtl92du_card_disable(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ enum nl80211_iftype opmode; ++ u32 val32; ++ u16 val16; ++ u8 val8; ++ ++ mac->link_state = MAC80211_NOLINK; ++ opmode = NL80211_IFTYPE_UNSPECIFIED; ++ _rtl92du_set_media_status(hw, opmode); ++ ++ RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); ++ /* Power sequence for each MAC. */ ++ /* a. stop tx DMA */ ++ /* b. close RF */ ++ /* c. clear rx buf */ ++ /* d. stop rx DMA */ ++ /* e. reset MAC */ ++ ++ val16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG); ++ val16 &= ~BIT(12); ++ rtl_write_word(rtlpriv, REG_GPIO_MUXCFG, val16); ++ ++ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xff); ++ udelay(500); ++ rtl_write_byte(rtlpriv, REG_CR, 0); ++ ++ /* RF OFF sequence */ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x00); ++ ++ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); ++ ++ val8 = FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTN; ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, val8); ++ ++ /* Mac0 can not do Global reset. Mac1 can do. */ ++ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY || ++ rtlhal->interfaceindex == 1) { ++ /* before BB reset should do clock gated */ ++ val32 = rtl_read_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER); ++ val32 |= BIT(31); ++ rtl_write_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER, val32); ++ ++ val8 &= ~FEN_BB_GLB_RSTN; ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, val8); ++ } ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n"); ++ if (!rtl92du_phy_check_poweroff(hw)) ++ return; ++ ++ _rtl92du_poweroff_adapter(hw); ++} ++ ++void rtl92du_set_beacon_related_registers(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ u16 bcn_interval, atim_window; ++ ++ bcn_interval = mac->beacon_interval; ++ atim_window = 2; ++ rtl92du_disable_interrupt(hw); ++ rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); ++ rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); ++ rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); ++ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) ++ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); ++ else ++ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); ++ rtl_write_byte(rtlpriv, 0x606, 0x30); ++} ++ ++void rtl92du_set_beacon_interval(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); ++ u16 bcn_interval = mac->beacon_interval; ++ ++ rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, ++ "beacon_interval:%d\n", bcn_interval); ++ rtl92du_disable_interrupt(hw); ++ rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); ++ rtl92du_enable_interrupt(hw); ++} ++ ++void rtl92du_update_interrupt_mask(struct ieee80211_hw *hw, ++ u32 add_msr, u32 rm_msr) ++{ ++ /* Nothing to do here. */ ++} ++ ++void rtl92du_read_chip_version(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ /* Chip version reading is done in rtl92d_read_eeprom_info. */ ++ ++ rtlpriv->rtlhal.hw_type = HARDWARE_TYPE_RTL8192DU; ++} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h +new file mode 100644 +index 000000000000..80ed00c90c16 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_HW_H__ ++#define __RTL92DU_HW_H__ ++ ++void rtl92du_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); ++void rtl92du_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); ++void rtl92du_read_chip_version(struct ieee80211_hw *hw); ++int rtl92du_hw_init(struct ieee80211_hw *hw); ++void rtl92du_card_disable(struct ieee80211_hw *hw); ++void rtl92du_enable_interrupt(struct ieee80211_hw *hw); ++void rtl92du_disable_interrupt(struct ieee80211_hw *hw); ++int rtl92du_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type); ++void rtl92du_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid); ++void rtl92du_set_beacon_related_registers(struct ieee80211_hw *hw); ++void rtl92du_set_beacon_interval(struct ieee80211_hw *hw); ++void rtl92du_update_interrupt_mask(struct ieee80211_hw *hw, ++ u32 add_msr, u32 rm_msr); ++void rtl92du_linked_set_reg(struct ieee80211_hw *hw); ++ ++#endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0022-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0022-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch new file mode 100644 index 0000000000..ddbc3925c5 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0022-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch @@ -0,0 +1,3186 @@ +From 40249d26740fceb059f121dde0922de1f9ec209a Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:46:02 +0300 +Subject: [PATCH 22/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/phy.{c,h} + +These contain mostly the calibration and channel switching routines +for RTL8192DU. + +Signed-off-by: Bitterblue Smith +--- + .../wireless/realtek/rtlwifi/rtl8192du/phy.c | 3123 +++++++++++++++++ + .../wireless/realtek/rtlwifi/rtl8192du/phy.h | 32 + + 2 files changed, 3155 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c +new file mode 100644 +index 000000000000..289ec71ce3e5 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c +@@ -0,0 +1,3123 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../ps.h" ++#include "../core.h" ++#include "../efuse.h" ++#include "../usb.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/phy_common.h" ++#include "../rtl8192d/rf_common.h" ++#include "phy.h" ++#include "rf.h" ++#include "table.h" ++ ++#define MAX_RF_IMR_INDEX 12 ++#define MAX_RF_IMR_INDEX_NORMAL 13 ++#define RF_REG_NUM_FOR_C_CUT_5G 6 ++#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 ++#define RF_REG_NUM_FOR_C_CUT_2G 5 ++#define RF_CHNL_NUM_5G 19 ++#define RF_CHNL_NUM_5G_40M 17 ++#define CV_CURVE_CNT 64 ++ ++static const u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { ++ 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 ++}; ++ ++static const u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { ++ RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 ++}; ++ ++static const u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { ++ RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 ++}; ++ ++static const u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { ++ 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E ++}; ++ ++static const u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { ++ BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), ++ BIT(10) | BIT(9), ++ BIT(18) | BIT(17) | BIT(16) | BIT(1), ++ BIT(2) | BIT(1), ++ BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) ++}; ++ ++static const u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { ++ 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, ++ 112, 116, 120, 124, 128, 132, 136, 140 ++}; ++ ++static const u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { ++ 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, ++ 118, 122, 126, 130, 134, 138 ++}; ++ ++static const u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { ++ {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, ++ {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, ++ {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, ++ {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, ++ {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} ++}; ++ ++static const u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { ++ {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, ++ {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, ++ {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} ++}; ++ ++static const u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; ++ ++static const u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { ++ {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, ++ {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, ++ {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} ++}; ++ ++/* [patha+b][reg] */ ++static const u32 rf_imr_param_normal[3][MAX_RF_IMR_INDEX_NORMAL] = { ++ /* channels 1-14. */ ++ { ++ 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, ++ 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff ++ }, ++ /* channels 36-64 */ ++ { ++ 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, ++ 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, ++ 0x32c9a ++ }, ++ /* channels 100-165 */ ++ { ++ 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, ++ 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a ++ } ++}; ++ ++static const u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { ++ 25141, 25116, 25091, 25066, 25041, ++ 25016, 24991, 24966, 24941, 24917, ++ 24892, 24867, 24843, 24818, 24794, ++ 24770, 24765, 24721, 24697, 24672, ++ 24648, 24624, 24600, 24576, 24552, ++ 24528, 24504, 24480, 24457, 24433, ++ 24409, 24385, 24362, 24338, 24315, ++ 24291, 24268, 24245, 24221, 24198, ++ 24175, 24151, 24128, 24105, 24082, ++ 24059, 24036, 24013, 23990, 23967, ++ 23945, 23922, 23899, 23876, 23854, ++ 23831, 23809, 23786, 23764, 23741, ++ 23719, 23697, 23674, 23652, 23630, ++ 23608, 23586, 23564, 23541, 23519, ++ 23498, 23476, 23454, 23432, 23410, ++ 23388, 23367, 23345, 23323, 23302, ++ 23280, 23259, 23237, 23216, 23194, ++ 23173, 23152, 23130, 23109, 23088, ++ 23067, 23046, 23025, 23003, 22982, ++ 22962, 22941, 22920, 22899, 22878, ++ 22857, 22837, 22816, 22795, 22775, ++ 22754, 22733, 22713, 22692, 22672, ++ 22652, 22631, 22611, 22591, 22570, ++ 22550, 22530, 22510, 22490, 22469, ++ 22449, 22429, 22409, 22390, 22370, ++ 22350, 22336, 22310, 22290, 22271, ++ 22251, 22231, 22212, 22192, 22173, ++ 22153, 22134, 22114, 22095, 22075, ++ 22056, 22037, 22017, 21998, 21979, ++ 21960, 21941, 21921, 21902, 21883, ++ 21864, 21845, 21826, 21807, 21789, ++ 21770, 21751, 21732, 21713, 21695, ++ 21676, 21657, 21639, 21620, 21602, ++ 21583, 21565, 21546, 21528, 21509, ++ 21491, 21473, 21454, 21436, 21418, ++ 21400, 21381, 21363, 21345, 21327, ++ 21309, 21291, 21273, 21255, 21237, ++ 21219, 21201, 21183, 21166, 21148, ++ 21130, 21112, 21095, 21077, 21059, ++ 21042, 21024, 21007, 20989, 20972, ++ 25679, 25653, 25627, 25601, 25575, ++ 25549, 25523, 25497, 25471, 25446, ++ 25420, 25394, 25369, 25343, 25318, ++ 25292, 25267, 25242, 25216, 25191, ++ 25166 ++}; ++ ++/* channel 1~14 */ ++static const u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { ++ 26084, 26030, 25976, 25923, 25869, 25816, 25764, ++ 25711, 25658, 25606, 25554, 25502, 25451, 25328 ++}; ++ ++u32 rtl92du_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ u32 returnvalue, originalvalue, bitshift; ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", ++ regaddr, bitmask); ++ ++ if (rtlhal->during_mac1init_radioa) ++ regaddr |= MAC1_ACCESS_PHY0; ++ else if (rtlhal->during_mac0init_radiob) ++ regaddr |= MAC0_ACCESS_PHY1; ++ ++ originalvalue = rtl_read_dword(rtlpriv, regaddr); ++ bitshift = calculate_bit_shift(bitmask); ++ returnvalue = (originalvalue & bitmask) >> bitshift; ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "BBR MASK=0x%x Addr[0x%x]=0x%x\n", ++ bitmask, regaddr, originalvalue); ++ return returnvalue; ++} ++ ++void rtl92du_phy_set_bb_reg(struct ieee80211_hw *hw, ++ u32 regaddr, u32 bitmask, u32 data) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ u32 originalvalue, bitshift; ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "regaddr(%#x), bitmask(%#x), data(%#x)\n", ++ regaddr, bitmask, data); ++ ++ if (rtlhal->during_mac1init_radioa) ++ regaddr |= MAC1_ACCESS_PHY0; ++ else if (rtlhal->during_mac0init_radiob) ++ regaddr |= MAC0_ACCESS_PHY1; ++ ++ if (bitmask != MASKDWORD) { ++ originalvalue = rtl_read_dword(rtlpriv, regaddr); ++ bitshift = calculate_bit_shift(bitmask); ++ data = (originalvalue & (~bitmask)) | ++ ((data << bitshift) & bitmask); ++ } ++ ++ rtl_write_dword(rtlpriv, regaddr, data); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "regaddr(%#x), bitmask(%#x), data(%#x)\n", ++ regaddr, bitmask, data); ++} ++ ++/* To avoid miswrite Reg0x800 for 92D */ ++static void rtl92du_phy_set_bb_reg_1byte(struct ieee80211_hw *hw, ++ u32 regaddr, u32 bitmask, u32 data) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 originalvalue, bitshift, offset; ++ u8 value; ++ ++ /* BitMask only support bit0~bit7 or bit8~bit15, bit16~bit23, ++ * bit24~bit31, should be in 1 byte scale; ++ */ ++ bitshift = calculate_bit_shift(bitmask); ++ offset = bitshift / 8; ++ ++ originalvalue = rtl_read_dword(rtlpriv, regaddr); ++ data = (originalvalue & (~bitmask)) | ((data << bitshift) & bitmask); ++ ++ value = data >> (8 * offset); ++ ++ rtl_write_byte(rtlpriv, regaddr + offset, value); ++} ++ ++bool rtl92du_phy_mac_config(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 arraylength; ++ const u32 *ptrarray; ++ u32 i; ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); ++ ++ arraylength = MAC_2T_ARRAYLENGTH; ++ ptrarray = rtl8192du_mac_2tarray; ++ ++ for (i = 0; i < arraylength; i = i + 2) ++ rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); ++ ++ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { ++ /* improve 2-stream TX EVM */ ++ /* rtl_write_byte(rtlpriv, 0x14,0x71); */ ++ /* AMPDU aggregation number 9 */ ++ /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ ++ rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); ++ } else { ++ /* 92D need to test to decide the num. */ ++ rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); ++ } ++ ++ return true; ++} ++ ++static bool _rtl92du_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ u16 phy_reg_arraylen, agctab_arraylen = 0; ++ const u32 *agctab_array_table = NULL; ++ const u32 *phy_regarray_table; ++ int i; ++ ++ /* Normal chip, Mac0 use AGC_TAB.txt for 2G and 5G band. */ ++ if (rtlhal->interfaceindex == 0) { ++ agctab_arraylen = AGCTAB_ARRAYLENGTH; ++ agctab_array_table = rtl8192du_agctab_array; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); ++ } else { ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; ++ agctab_array_table = rtl8192du_agctab_2garray; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); ++ } else { ++ agctab_arraylen = AGCTAB_5G_ARRAYLENGTH; ++ agctab_array_table = rtl8192du_agctab_5garray; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); ++ } ++ } ++ phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; ++ phy_regarray_table = rtl8192du_phy_reg_2tarray; ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ " ===> phy:Rtl819XPHY_REG_Array_PG\n"); ++ ++ if (configtype == BASEBAND_CONFIG_PHY_REG) { ++ for (i = 0; i < phy_reg_arraylen; i = i + 2) { ++ rtl_addr_delay(phy_regarray_table[i]); ++ rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, ++ phy_regarray_table[i + 1]); ++ udelay(1); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", ++ phy_regarray_table[i], ++ phy_regarray_table[i + 1]); ++ } ++ } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { ++ for (i = 0; i < agctab_arraylen; i = i + 2) { ++ rtl_set_bbreg(hw, agctab_array_table[i], ++ MASKDWORD, agctab_array_table[i + 1]); ++ ++ /* Add 1us delay between BB/RF register setting. */ ++ udelay(1); ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "AGC table %u %u\n", ++ agctab_array_table[i], ++ agctab_array_table[i + 1]); ++ } ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "Normal Chip, loaded AGC table\n"); ++ } ++ return true; ++} ++ ++static bool _rtl92du_phy_config_bb_pg(struct ieee80211_hw *hw, u8 configtype) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ const u32 *phy_regarray_table_pg; ++ u16 phy_regarray_pg_len; ++ int i; ++ ++ phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; ++ phy_regarray_table_pg = rtl8192du_phy_reg_array_pg; ++ ++ if (configtype == BASEBAND_CONFIG_PHY_REG) { ++ for (i = 0; i < phy_regarray_pg_len; i = i + 3) { ++ rtl_addr_delay(phy_regarray_table_pg[i]); ++ rtl92d_store_pwrindex_diffrate_offset(hw, ++ phy_regarray_table_pg[i], ++ phy_regarray_table_pg[i + 1], ++ phy_regarray_table_pg[i + 2]); ++ } ++ } else { ++ rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, ++ "configtype != BaseBand_Config_PHY_REG\n"); ++ } ++ return true; ++} ++ ++static bool _rtl92du_phy_bb_config(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ bool ret; ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); ++ ret = _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG); ++ if (!ret) { ++ pr_err("Write BB Reg Fail!!\n"); ++ return false; ++ } ++ ++ if (!rtlefuse->autoload_failflag) { ++ rtlphy->pwrgroup_cnt = 0; ++ ret = _rtl92du_phy_config_bb_pg(hw, BASEBAND_CONFIG_PHY_REG); ++ } ++ if (!ret) { ++ pr_err("BB_PG Reg Fail!!\n"); ++ return false; ++ } ++ ++ ret = _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); ++ if (!ret) { ++ pr_err("AGC Table Fail\n"); ++ return false; ++ } ++ ++ rtlphy->cck_high_power = (bool)rtl_get_bbreg(hw, ++ RFPGA0_XA_HSSIPARAMETER2, ++ 0x200); ++ ++ return true; ++} ++ ++bool rtl92du_phy_bb_config(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ bool rtstatus; ++ u32 regvaldw; ++ u16 regval; ++ u8 value; ++ ++ rtl92d_phy_init_bb_rf_register_definition(hw); ++ ++ regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); ++ rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, ++ regval | BIT(13) | BIT(0) | BIT(1)); ++ ++ rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); ++ rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); ++ ++ /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ ++ value = rtl_read_byte(rtlpriv, REG_RF_CTRL); ++ rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | ++ RF_SDMRSTB); ++ ++ value = FEN_BB_GLB_RSTN | FEN_BBRSTB; ++ if (rtlhal->interface == INTF_PCI) ++ value |= FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE; ++ else if (rtlhal->interface == INTF_USB) ++ value |= FEN_USBA | FEN_USBD; ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value); ++ ++ regvaldw = rtl_read_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER); ++ regvaldw &= ~BIT(31); ++ rtl_write_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER, regvaldw); ++ ++ /* To Fix MAC loopback mode fail. */ ++ rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); ++ rtl_write_byte(rtlpriv, 0x15, 0xe9); ++ ++ rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); ++ if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)) && ++ rtlhal->interface == INTF_PCI) { ++ regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); ++ rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); ++ } ++ ++ rtstatus = _rtl92du_phy_bb_config(hw); ++ ++ /* Crystal calibration */ ++ rtl_set_bbreg(hw, REG_AFE_XTAL_CTRL, 0xf0, ++ rtlpriv->efuse.crystalcap & 0x0f); ++ rtl_set_bbreg(hw, REG_AFE_PLL_CTRL, 0xf0000000, ++ (rtlpriv->efuse.crystalcap & 0xf0) >> 4); ++ ++ return rtstatus; ++} ++ ++bool rtl92du_phy_rf_config(struct ieee80211_hw *hw) ++{ ++ return rtl92du_phy_rf6052_config(hw); ++} ++ ++bool rtl92du_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, ++ enum rf_content content, ++ enum radio_path rfpath) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u16 radioa_arraylen, radiob_arraylen; ++ const u32 *radioa_array_table; ++ const u32 *radiob_array_table; ++ int i; ++ ++ radioa_arraylen = RADIOA_2T_ARRAYLENGTH; ++ radioa_array_table = rtl8192du_radioa_2tarray; ++ radiob_arraylen = RADIOB_2T_ARRAYLENGTH; ++ radiob_array_table = rtl8192du_radiob_2tarray; ++ if (rtlpriv->efuse.internal_pa_5g[0]) { ++ radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; ++ radioa_array_table = rtl8192du_radioa_2t_int_paarray; ++ } ++ if (rtlpriv->efuse.internal_pa_5g[1]) { ++ radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; ++ radiob_array_table = rtl8192du_radiob_2t_int_paarray; ++ } ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); ++ ++ /* this only happens when DMDP, mac0 start on 2.4G, ++ * mac1 start on 5G, mac 0 has to set phy0 & phy1 ++ * pathA or mac1 has to set phy0 & phy1 pathA ++ */ ++ if (content == radiob_txt && rfpath == RF90_PATH_A) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ " ===> althougth Path A, we load radiob.txt\n"); ++ radioa_arraylen = radiob_arraylen; ++ radioa_array_table = radiob_array_table; ++ } ++ ++ switch (rfpath) { ++ case RF90_PATH_A: ++ for (i = 0; i < radioa_arraylen; i = i + 2) { ++ rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], ++ RFREG_OFFSET_MASK, ++ radioa_array_table[i + 1]); ++ } ++ break; ++ case RF90_PATH_B: ++ for (i = 0; i < radiob_arraylen; i = i + 2) { ++ rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], ++ RFREG_OFFSET_MASK, ++ radiob_array_table[i + 1]); ++ } ++ break; ++ case RF90_PATH_C: ++ case RF90_PATH_D: ++ pr_err("switch case %#x not processed\n", rfpath); ++ break; ++ } ++ ++ return true; ++} ++ ++void rtl92du_phy_set_bw_mode(struct ieee80211_hw *hw, ++ enum nl80211_channel_type ch_type) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ u8 reg_bw_opmode; ++ u8 reg_prsr_rsc; ++ ++ if (rtlphy->set_bwmode_inprogress) ++ return; ++ ++ if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { ++ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, ++ "FALSE driver sleep or unload\n"); ++ return; ++ } ++ ++ rtlphy->set_bwmode_inprogress = true; ++ ++ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", ++ rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? ++ "20MHz" : "40MHz"); ++ ++ reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); ++ reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); ++ ++ switch (rtlphy->current_chan_bw) { ++ case HT_CHANNEL_WIDTH_20: ++ reg_bw_opmode |= BW_OPMODE_20MHZ; ++ rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); ++ break; ++ case HT_CHANNEL_WIDTH_20_40: ++ reg_bw_opmode &= ~BW_OPMODE_20MHZ; ++ rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); ++ ++ reg_prsr_rsc = (reg_prsr_rsc & 0x90) | ++ (mac->cur_40_prime_sc << 5); ++ rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); ++ break; ++ default: ++ pr_err("unknown bandwidth: %#X\n", ++ rtlphy->current_chan_bw); ++ break; ++ } ++ ++ switch (rtlphy->current_chan_bw) { ++ case HT_CHANNEL_WIDTH_20: ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x0); ++ rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); ++ /* SET BIT10 BIT11 for receive cck */ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | BIT(11), 3); ++ break; ++ case HT_CHANNEL_WIDTH_20_40: ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x1); ++ rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); ++ /* Set Control channel to upper or lower. ++ * These settings are required only for 40MHz ++ */ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) ++ rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, ++ mac->cur_40_prime_sc >> 1); ++ rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); ++ /* SET BIT10 BIT11 for receive cck */ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, ++ BIT(10) | BIT(11), 0); ++ rtl_set_bbreg(hw, 0x818, BIT(26) | BIT(27), ++ mac->cur_40_prime_sc == ++ HAL_PRIME_CHNL_OFFSET_LOWER ? 2 : 1); ++ break; ++ default: ++ pr_err("unknown bandwidth: %#X\n", ++ rtlphy->current_chan_bw); ++ break; ++ } ++ ++ rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); ++ ++ rtlphy->set_bwmode_inprogress = false; ++ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); ++} ++ ++static void _rtl92du_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) ++{ ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0); ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); ++ rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); ++} ++ ++static void rtl92du_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ u16 basic_rates; ++ u32 reg_mac; ++ u8 value8; ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); ++ rtlhal->bandset = band; ++ rtlhal->current_bandtype = band; ++ if (IS_92D_SINGLEPHY(rtlhal->version)) ++ rtlhal->bandset = BAND_ON_BOTH; ++ ++ /* stop RX/Tx */ ++ _rtl92du_phy_stop_trx_before_changeband(hw); ++ ++ /* reconfig BB/RF according to wireless mode */ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) ++ /* BB & RF Config */ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); ++ else ++ /* 5G band */ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); ++ ++ if (rtlhal->interfaceindex == 1) ++ _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); ++ ++ rtl92du_update_bbrf_configuration(hw); ++ ++ basic_rates = RRSR_6M | RRSR_12M | RRSR_24M; ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) ++ basic_rates |= RRSR_1M | RRSR_2M | RRSR_5_5M | RRSR_11M; ++ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE, ++ (u8 *)&basic_rates); ++ ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0x3); ++ ++ /* 20M BW. */ ++ /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ ++ rtlhal->reloadtxpowerindex = true; ++ ++ reg_mac = rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1; ++ ++ /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ value8 = rtl_read_byte(rtlpriv, reg_mac); ++ value8 |= BIT(1); ++ rtl_write_byte(rtlpriv, reg_mac, value8); ++ } else { ++ value8 = rtl_read_byte(rtlpriv, reg_mac); ++ value8 &= ~BIT(1); ++ rtl_write_byte(rtlpriv, reg_mac, value8); ++ } ++ mdelay(1); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); ++} ++ ++static void _rtl92du_phy_reload_imr_setting(struct ieee80211_hw *hw, ++ u8 channel, u8 rfpath) ++{ ++ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u8 group, i; ++ ++ if (rtlusb->udev->speed != USB_SPEED_HIGH) ++ return; ++ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, ++ BOFDMEN | BCCKEN, 0); ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); ++ ++ /* fc area 0xd2c */ ++ if (channel >= 149) ++ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | ++ BIT(14), 2); ++ else ++ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | ++ BIT(14), 1); ++ ++ /* leave 0 for channel1-14. */ ++ group = channel <= 64 ? 1 : 2; ++ for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++) ++ rtl_set_rfreg(hw, (enum radio_path)rfpath, ++ rf_reg_for_5g_swchnl_normal[i], ++ RFREG_OFFSET_MASK, ++ rf_imr_param_normal[group][i]); ++ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, ++ BOFDMEN | BCCKEN, 3); ++ } else { ++ /* G band. */ ++ rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, ++ "Load RF IMR parameters for G band. IMR already setting %d\n", ++ rtlpriv->rtlhal.load_imrandiqk_setting_for2g); ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); ++ ++ if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { ++ rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, ++ "Load RF IMR parameters for G band. %d\n", ++ rfpath); ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, ++ BOFDMEN | BCCKEN, 0); ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, ++ 0x00f00000, 0xf); ++ ++ for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++) { ++ rtl_set_rfreg(hw, (enum radio_path)rfpath, ++ rf_reg_for_5g_swchnl_normal[i], ++ RFREG_OFFSET_MASK, ++ rf_imr_param_normal[0][i]); ++ } ++ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, ++ 0x00f00000, 0); ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, ++ BOFDMEN | BCCKEN, 3); ++ } ++ } ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); ++} ++ ++static void _rtl92du_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) ++{ ++ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 path = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A ++ : RF90_PATH_B; ++ u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; ++ bool need_pwr_down = false, internal_pa = false; ++ u32 regb30 = rtl_get_bbreg(hw, 0xb30, BIT(27)); ++ u8 index = 0, i, rfpath; ++ ++ if (rtlusb->udev->speed != USB_SPEED_HIGH) ++ return; ++ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); ++ /* config path A for 5G */ ++ if (rtlhal->current_bandtype == BAND_ON_5G) { ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); ++ u4tmp = rtlpriv->curveindex_5g[channel - 1]; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); ++ ++ for (i = 0; i < RF_CHNL_NUM_5G; i++) { ++ if (channel == rf_chnl_5g[i] && channel <= 140) ++ index = 0; ++ } ++ for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { ++ if (channel == rf_chnl_5g_40m[i] && channel <= 140) ++ index = 1; ++ } ++ if (channel == 149 || channel == 155 || channel == 161) ++ index = 2; ++ else if (channel == 151 || channel == 153 || channel == 163 || ++ channel == 165) ++ index = 3; ++ else if (channel == 157 || channel == 159) ++ index = 4; ++ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY && ++ rtlhal->interfaceindex == 1) { ++ need_pwr_down = rtl92du_phy_enable_anotherphy(hw, false); ++ rtlhal->during_mac1init_radioa = true; ++ /* asume no this case */ ++ if (need_pwr_down) ++ rtl92d_phy_enable_rf_env(hw, path, ++ &u4regvalue); ++ } ++ ++ /* DMDP, if band = 5G, Mac0 need to set PHY1 when regB30[27]=1 */ ++ if (regb30 && rtlhal->interfaceindex == 0) { ++ need_pwr_down = rtl92du_phy_enable_anotherphy(hw, true); ++ rtlhal->during_mac0init_radiob = true; ++ if (need_pwr_down) ++ rtl92d_phy_enable_rf_env(hw, path, ++ &u4regvalue); ++ } ++ ++ for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { ++ if (i == 0 && rtlhal->macphymode == DUALMAC_DUALPHY) { ++ rtl_set_rfreg(hw, (enum radio_path)path, ++ rf_reg_for_c_cut_5g[i], ++ RFREG_OFFSET_MASK, 0xE439D); ++ } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { ++ u4tmp2 = (rf_reg_pram_c_5g[index][i] & ++ 0x7FF) | (u4tmp << 11); ++ if (channel == 36) ++ u4tmp2 &= ~(BIT(7) | BIT(6)); ++ rtl_set_rfreg(hw, (enum radio_path)path, ++ rf_reg_for_c_cut_5g[i], ++ RFREG_OFFSET_MASK, u4tmp2); ++ } else { ++ rtl_set_rfreg(hw, (enum radio_path)path, ++ rf_reg_for_c_cut_5g[i], ++ RFREG_OFFSET_MASK, ++ rf_reg_pram_c_5g[index][i]); ++ } ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", ++ rf_reg_for_c_cut_5g[i], ++ rf_reg_pram_c_5g[index][i], ++ path, index, ++ rtl_get_rfreg(hw, (enum radio_path)path, ++ rf_reg_for_c_cut_5g[i], ++ RFREG_OFFSET_MASK)); ++ } ++ if (rtlhal->macphymode == DUALMAC_DUALPHY && ++ rtlhal->interfaceindex == 1) { ++ if (need_pwr_down) ++ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); ++ ++ rtl92du_phy_powerdown_anotherphy(hw, false); ++ } ++ ++ if (regb30 && rtlhal->interfaceindex == 0) { ++ if (need_pwr_down) ++ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); ++ ++ rtl92du_phy_powerdown_anotherphy(hw, true); ++ } ++ ++ if (channel < 149) ++ value = 0x07; ++ else if (channel >= 149) ++ value = 0x02; ++ if (channel >= 36 && channel <= 64) ++ index = 0; ++ else if (channel >= 100 && channel <= 140) ++ index = 1; ++ else ++ index = 2; ++ ++ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; ++ rfpath++) { ++ if (rtlhal->macphymode == DUALMAC_DUALPHY && ++ rtlhal->interfaceindex == 1) /* MAC 1 5G */ ++ internal_pa = rtlpriv->efuse.internal_pa_5g[1]; ++ else ++ internal_pa = ++ rtlpriv->efuse.internal_pa_5g[rfpath]; ++ ++ if (internal_pa) { ++ for (i = 0; ++ i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; ++ i++) { ++ if (rf_for_c_cut_5g_internal_pa[i] == 0x03 && ++ channel >= 36 && channel <= 64) ++ rtl_set_rfreg(hw, rfpath, ++ rf_for_c_cut_5g_internal_pa[i], ++ RFREG_OFFSET_MASK, ++ 0x7bdef); ++ else ++ rtl_set_rfreg(hw, rfpath, ++ rf_for_c_cut_5g_internal_pa[i], ++ RFREG_OFFSET_MASK, ++ rf_pram_c_5g_int_pa[index][i]); ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, ++ "offset 0x%x value 0x%x path %d index %d\n", ++ rf_for_c_cut_5g_internal_pa[i], ++ rf_pram_c_5g_int_pa[index][i], ++ rfpath, index); ++ } ++ } else { ++ rtl_set_rfreg(hw, (enum radio_path)rfpath, RF_TXPA_AG, ++ mask, value); ++ } ++ } ++ } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); ++ u4tmp = rtlpriv->curveindex_2g[channel - 1]; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); ++ ++ if (channel == 1 || channel == 2 || channel == 4 || ++ channel == 9 || channel == 10 || channel == 11 || ++ channel == 12) ++ index = 0; ++ else if (channel == 3 || channel == 13 || channel == 14) ++ index = 1; ++ else if (channel >= 5 && channel <= 8) ++ index = 2; ++ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY) { ++ path = RF90_PATH_A; ++ if (rtlhal->interfaceindex == 0) { ++ need_pwr_down = ++ rtl92du_phy_enable_anotherphy(hw, true); ++ rtlhal->during_mac0init_radiob = true; ++ ++ if (need_pwr_down) ++ rtl92d_phy_enable_rf_env(hw, path, ++ &u4regvalue); ++ } ++ ++ /* DMDP, if band = 2G, MAC1 need to set PHY0 when regB30[27]=1 */ ++ if (regb30 && rtlhal->interfaceindex == 1) { ++ need_pwr_down = ++ rtl92du_phy_enable_anotherphy(hw, false); ++ rtlhal->during_mac1init_radioa = true; ++ ++ if (need_pwr_down) ++ rtl92d_phy_enable_rf_env(hw, path, ++ &u4regvalue); ++ } ++ } ++ ++ for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { ++ if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) ++ rtl_set_rfreg(hw, (enum radio_path)path, ++ rf_reg_for_c_cut_2g[i], ++ RFREG_OFFSET_MASK, ++ rf_reg_param_for_c_cut_2g[index][i] | ++ BIT(17)); ++ else ++ rtl_set_rfreg(hw, (enum radio_path)path, ++ rf_reg_for_c_cut_2g[i], ++ RFREG_OFFSET_MASK, ++ rf_reg_param_for_c_cut_2g ++ [index][i]); ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, ++ "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", ++ rf_reg_for_c_cut_2g[i], ++ rf_reg_param_for_c_cut_2g[index][i], ++ rf_reg_mask_for_c_cut_2g[i], path, index, ++ rtl_get_rfreg(hw, (enum radio_path)path, ++ rf_reg_for_c_cut_2g[i], ++ RFREG_OFFSET_MASK)); ++ } ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", ++ rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); ++ ++ rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, ++ RFREG_OFFSET_MASK, ++ rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); ++ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY && ++ rtlhal->interfaceindex == 0) { ++ if (need_pwr_down) ++ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); ++ ++ rtl92du_phy_powerdown_anotherphy(hw, true); ++ } ++ ++ if (regb30 && rtlhal->interfaceindex == 1) { ++ if (need_pwr_down) ++ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); ++ ++ rtl92du_phy_powerdown_anotherphy(hw, false); ++ } ++ } ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); ++} ++ ++/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ ++static u8 _rtl92du_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u32 regeac, rege94, rege9c, regea4; ++ u8 result = 0; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); ++ ++ if (rtlhal->interfaceindex == 0) { ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1f); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1f); ++ } else { ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c22); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c22); ++ } ++ rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140102); ++ rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, ++ configpathb ? 0x28160202 : 0x28160502); ++ /* path-B IQK setting */ ++ if (configpathb) { ++ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x10008c22); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x10008c22); ++ rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140102); ++ rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160206); ++ } ++ ++ /* LO calibration setting */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); ++ rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); ++ ++ /* One shot, path A LOK & IQK */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); ++ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); ++ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Delay %d ms for One shot, path A LOK & IQK\n", ++ IQK_DELAY_TIME); ++ mdelay(IQK_DELAY_TIME); ++ ++ /* Check failed */ ++ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); ++ rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); ++ rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); ++ regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); ++ ++ if (!(regeac & BIT(28)) && ++ (((rege94 & 0x03FF0000) >> 16) != 0x142) && ++ (((rege9c & 0x03FF0000) >> 16) != 0x42)) ++ result |= 0x01; ++ else /* if Tx not OK, ignore Rx */ ++ return result; ++ ++ /* if Tx is OK, check whether Rx is OK */ ++ if (!(regeac & BIT(27)) && ++ (((regea4 & 0x03FF0000) >> 16) != 0x132) && ++ (((regeac & 0x03FF0000) >> 16) != 0x36)) ++ result |= 0x02; ++ else ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); ++ ++ return result; ++} ++ ++/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ ++static u8 _rtl92du_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, ++ bool configpathb) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27); ++ u32 regeac, rege94, rege9c, regea4; ++ u8 timeout = 20, timecount = 0; ++ u8 retrycount = 2; ++ u8 result = 0; ++ u8 i; ++ ++ if (rtlhal->interfaceindex == 1) { /* PHY1 */ ++ TXOKBIT = BIT(31); ++ RXOKBIT = BIT(30); ++ } ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); ++ rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140307); ++ rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160960); ++ /* path-B IQK setting */ ++ if (configpathb) { ++ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); ++ rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); ++ rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68110000); ++ } ++ ++ /* LO calibration setting */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); ++ rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); ++ ++ /* path-A PA on */ ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); ++ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); ++ ++ for (i = 0; i < retrycount; i++) { ++ /* One shot, path A LOK & IQK */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "One shot, path A LOK & IQK!\n"); ++ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); ++ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Delay %d ms for One shot, path A LOK & IQK.\n", ++ IQK_DELAY_TIME); ++ mdelay(IQK_DELAY_TIME * 10); ++ ++ while (timecount < timeout && ++ rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(26)) == 0) { ++ udelay(IQK_DELAY_TIME * 1000 * 2); ++ timecount++; ++ } ++ ++ timecount = 0; ++ while (timecount < timeout && ++ rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASK_IQK_RESULT) == 0) { ++ udelay(IQK_DELAY_TIME * 1000 * 2); ++ timecount++; ++ } ++ ++ /* Check failed */ ++ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); ++ rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); ++ rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); ++ regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); ++ ++ if (!(regeac & TXOKBIT) && ++ (((rege94 & 0x03FF0000) >> 16) != 0x142)) { ++ result |= 0x01; ++ } else { /* if Tx not OK, ignore Rx */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path A Tx IQK fail!!\n"); ++ continue; ++ } ++ ++ /* if Tx is OK, check whether Rx is OK */ ++ if (!(regeac & RXOKBIT) && ++ (((regea4 & 0x03FF0000) >> 16) != 0x132)) { ++ result |= 0x02; ++ break; ++ } ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); ++ } ++ ++ /* path A PA off */ ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, ++ rtlphy->iqk_bb_backup[0]); ++ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, ++ rtlphy->iqk_bb_backup[1]); ++ ++ if (!(result & 0x01)) /* Tx IQK fail */ ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); ++ ++ if (!(result & 0x02)) { /* Rx IQK fail */ ++ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path A Rx IQK fail!! 0xe34 = %#x\n", ++ rtl_get_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD)); ++ } ++ ++ return result; ++} ++ ++/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ ++static u8 _rtl92du_phy_pathb_iqk(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 regeac, regeb4, regebc, regec4, regecc; ++ u8 result = 0; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path B LOK & IQK!\n"); ++ rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000002); ++ rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000000); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); ++ mdelay(IQK_DELAY_TIME); ++ ++ /* Check failed */ ++ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); ++ regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); ++ regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); ++ regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); ++ regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); ++ ++ if (!(regeac & BIT(31)) && ++ (((regeb4 & 0x03FF0000) >> 16) != 0x142) && ++ (((regebc & 0x03FF0000) >> 16) != 0x42)) ++ result |= 0x01; ++ else ++ return result; ++ ++ if (!(regeac & BIT(30)) && ++ (((regec4 & 0x03FF0000) >> 16) != 0x132) && ++ (((regecc & 0x03FF0000) >> 16) != 0x36)) ++ result |= 0x02; ++ else ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); ++ ++ return result; ++} ++ ++/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ ++static u8 _rtl92du_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u32 regeac, regeb4, regebc, regec4, regecc; ++ u8 timeout = 20, timecount = 0; ++ u8 retrycount = 2; ++ u8 result = 0; ++ u8 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-B IQK setting!\n"); ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); ++ rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); ++ rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68110000); ++ ++ /* path-B IQK setting */ ++ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); ++ rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140307); ++ rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160960); ++ ++ /* LO calibration setting */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); ++ rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); ++ ++ /* path-B PA on */ ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); ++ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); ++ ++ for (i = 0; i < retrycount; i++) { ++ /* One shot, path B LOK & IQK */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "One shot, path A LOK & IQK!\n"); ++ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); ++ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Delay %d ms for One shot, path B LOK & IQK.\n", 10); ++ mdelay(IQK_DELAY_TIME * 10); ++ ++ while (timecount < timeout && ++ rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(29)) == 0) { ++ udelay(IQK_DELAY_TIME * 1000 * 2); ++ timecount++; ++ } ++ ++ timecount = 0; ++ while (timecount < timeout && ++ rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASK_IQK_RESULT) == 0) { ++ udelay(IQK_DELAY_TIME * 1000 * 2); ++ timecount++; ++ } ++ ++ /* Check failed */ ++ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); ++ regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); ++ regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); ++ regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); ++ regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); ++ ++ if (!(regeac & BIT(31)) && ++ (((regeb4 & 0x03FF0000) >> 16) != 0x142)) ++ result |= 0x01; ++ else ++ continue; ++ ++ if (!(regeac & BIT(30)) && ++ (((regec4 & 0x03FF0000) >> 16) != 0x132)) { ++ result |= 0x02; ++ break; ++ } ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); ++ } ++ ++ /* path B PA off */ ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, ++ rtlphy->iqk_bb_backup[0]); ++ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, ++ rtlphy->iqk_bb_backup[2]); ++ ++ if (!(result & 0x01)) ++ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); ++ ++ if (!(result & 0x02)) { ++ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B Rx IQK fail!! 0xe54 = %#x\n", ++ rtl_get_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD)); ++ } ++ ++ return result; ++} ++ ++static void _rtl92du_phy_reload_adda_registers(struct ieee80211_hw *hw, ++ const u32 *adda_reg, ++ u32 *adda_backup, u32 regnum) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Reload ADDA power saving parameters !\n"); ++ for (i = 0; i < regnum; i++) { ++ /* path-A/B BB to initial gain */ ++ if (adda_reg[i] == ROFDM0_XAAGCCORE1 || ++ adda_reg[i] == ROFDM0_XBAGCCORE1) ++ rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, 0x50); ++ ++ rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); ++ } ++} ++ ++static void _rtl92du_phy_reload_mac_registers(struct ieee80211_hw *hw, ++ const u32 *macreg, u32 *macbackup) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); ++ for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) ++ rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]); ++ rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); ++} ++ ++static void _rtl92du_phy_patha_standby(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); ++ ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x0); ++ rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); ++} ++ ++static void _rtl92du_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 mode; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); ++ mode = pi_mode ? 0x01000100 : 0x01000000; ++ rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, MASKDWORD, mode); ++ rtl_set_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, MASKDWORD, mode); ++} ++ ++static void _rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], ++ u8 t, bool is2t) ++{ ++ static const u32 adda_reg[IQK_ADDA_REG_NUM] = { ++ RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA, ++ RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON, ++ RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS, ++ RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN ++ }; ++ static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { ++ REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG ++ }; ++ static const u32 iqk_bb_reg[IQK_BB_REG_NUM] = { ++ RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, ++ RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, ++ RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, ++ RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, ++ ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 ++ }; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ const u32 retrycount = 2; ++ u8 patha_ok, pathb_ok; ++ u32 bbvalue; ++ u32 i; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); ++ if (t == 0) { ++ bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", ++ is2t ? "2T2R" : "1T1R"); ++ ++ /* Save ADDA parameters, turn Path A ADDA on */ ++ rtl92d_phy_save_adda_registers(hw, adda_reg, ++ rtlphy->adda_backup, ++ IQK_ADDA_REG_NUM); ++ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); ++ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM); ++ } ++ rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); ++ ++ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); ++ ++ if (t == 0) ++ rtlphy->rfpi_enable = (u8)rtl_get_bbreg(hw, ++ RFPGA0_XA_HSSIPARAMETER1, BIT(8)); ++ ++ /* Switch BB to PI mode to do IQ Calibration. */ ++ if (!rtlphy->rfpi_enable) ++ _rtl92du_phy_pimode_switch(hw, true); ++ ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); ++ rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); ++ rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); ++ if (is2t) { ++ rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, ++ 0x00010000); ++ rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, ++ 0x00010000); ++ } ++ ++ /* MAC settings */ ++ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); ++ ++ /* Page B init */ ++ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); ++ if (is2t) ++ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); ++ ++ /* IQ calibration setting */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); ++ rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); ++ rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); ++ ++ for (i = 0; i < retrycount; i++) { ++ patha_ok = _rtl92du_phy_patha_iqk(hw, is2t); ++ if (patha_ok == 0x03) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path A IQK Success!!\n"); ++ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, ++ MASK_IQK_RESULT); ++ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, ++ MASK_IQK_RESULT); ++ result[t][2] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, ++ MASK_IQK_RESULT); ++ result[t][3] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, ++ MASK_IQK_RESULT); ++ break; ++ } else if (i == (retrycount - 1) && patha_ok == 0x01) { ++ /* Tx IQK OK */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path A IQK Only Tx Success!!\n"); ++ ++ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, ++ MASK_IQK_RESULT); ++ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, ++ MASK_IQK_RESULT); ++ } ++ } ++ if (patha_ok == 0x00) ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); ++ ++ if (is2t) { ++ _rtl92du_phy_patha_standby(hw); ++ /* Turn Path B ADDA on */ ++ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); ++ ++ for (i = 0; i < retrycount; i++) { ++ pathb_ok = _rtl92du_phy_pathb_iqk(hw); ++ if (pathb_ok == 0x03) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B IQK Success!!\n"); ++ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, ++ MASK_IQK_RESULT); ++ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, ++ MASK_IQK_RESULT); ++ result[t][6] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, ++ MASK_IQK_RESULT); ++ result[t][7] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, ++ MASK_IQK_RESULT); ++ break; ++ } else if (i == (retrycount - 1) && pathb_ok == 0x01) { ++ /* Tx IQK OK */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B Only Tx IQK Success!!\n"); ++ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, ++ MASK_IQK_RESULT); ++ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, ++ MASK_IQK_RESULT); ++ } ++ } ++ if (pathb_ok == 0x00) ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B IQK failed!!\n"); ++ } ++ ++ /* Back to BB mode, load original value */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "IQK:Back to BB mode, load original value!\n"); ++ ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); ++ ++ if (t != 0) { ++ /* Switch back BB to SI mode after finish IQ Calibration. */ ++ if (!rtlphy->rfpi_enable) ++ _rtl92du_phy_pimode_switch(hw, false); ++ ++ /* Reload ADDA power saving parameters */ ++ _rtl92du_phy_reload_adda_registers(hw, adda_reg, ++ rtlphy->adda_backup, ++ IQK_ADDA_REG_NUM); ++ ++ /* Reload MAC parameters */ ++ _rtl92du_phy_reload_mac_registers(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); ++ ++ if (is2t) ++ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM); ++ else ++ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM - 1); ++ ++ /* load 0xe30 IQC default value */ ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); ++ } ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); ++} ++ ++static void _rtl92du_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, ++ long result[][8], u8 t) ++{ ++ static const u32 adda_reg[IQK_ADDA_REG_NUM] = { ++ RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA, ++ RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON, ++ RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS, ++ RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN ++ }; ++ static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { ++ REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG ++ }; ++ static const u32 iqk_bb_reg[IQK_BB_REG_NUM] = { ++ RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, ++ RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, ++ RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, ++ RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, ++ ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 ++ }; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); ++ u8 patha_ok, pathb_ok; ++ bool rf_path_div; ++ u32 bbvalue; ++ ++ /* Note: IQ calibration must be performed after loading ++ * PHY_REG.txt , and radio_a, radio_b.txt ++ */ ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); ++ ++ mdelay(IQK_DELAY_TIME * 20); ++ ++ if (t == 0) { ++ bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", ++ is2t ? "2T2R" : "1T1R"); ++ ++ /* Save ADDA parameters, turn Path A ADDA on */ ++ rtl92d_phy_save_adda_registers(hw, adda_reg, ++ rtlphy->adda_backup, ++ IQK_ADDA_REG_NUM); ++ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); ++ if (is2t) ++ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM); ++ else ++ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM - 1); ++ } ++ ++ rf_path_div = rtl_get_bbreg(hw, 0xb30, BIT(27)); ++ rtl92d_phy_path_adda_on(hw, adda_reg, !rf_path_div, is2t); ++ ++ if (t == 0) ++ rtlphy->rfpi_enable = rtl_get_bbreg(hw, ++ RFPGA0_XA_HSSIPARAMETER1, ++ BIT(8)); ++ ++ /* Switch BB to PI mode to do IQ Calibration. */ ++ if (!rtlphy->rfpi_enable) ++ _rtl92du_phy_pimode_switch(hw, true); ++ ++ /* MAC settings */ ++ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); ++ ++ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); ++ rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); ++ rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); ++ ++ /* Page A AP setting for IQK */ ++ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0); ++ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); ++ if (is2t) { ++ /* Page B AP setting for IQK */ ++ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0); ++ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); ++ } ++ ++ /* IQ calibration setting */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); ++ rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x10007c00); ++ rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); ++ ++ patha_ok = _rtl92du_phy_patha_iqk_5g_normal(hw, is2t); ++ if (patha_ok == 0x03) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); ++ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, ++ MASK_IQK_RESULT); ++ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, ++ MASK_IQK_RESULT); ++ result[t][2] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, ++ MASK_IQK_RESULT); ++ result[t][3] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, ++ MASK_IQK_RESULT); ++ } else if (patha_ok == 0x01) { /* Tx IQK OK */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path A IQK Only Tx Success!!\n"); ++ ++ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, ++ MASK_IQK_RESULT); ++ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, ++ MASK_IQK_RESULT); ++ } else { ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe70 = %#x\n", ++ rtl_get_bbreg(hw, RRX_WAIT_CCA, MASKDWORD)); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "RF path A 0x0 = %#x\n", ++ rtl_get_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK)); ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); ++ } ++ ++ if (is2t) { ++ /* _rtl92d_phy_patha_standby(hw); */ ++ /* Turn Path B ADDA on */ ++ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); ++ ++ pathb_ok = _rtl92du_phy_pathb_iqk_5g_normal(hw); ++ if (pathb_ok == 0x03) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B IQK Success!!\n"); ++ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, ++ MASK_IQK_RESULT); ++ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, ++ MASK_IQK_RESULT); ++ result[t][6] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, ++ MASK_IQK_RESULT); ++ result[t][7] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, ++ MASK_IQK_RESULT); ++ } else if (pathb_ok == 0x01) { /* Tx IQK OK */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B Only Tx IQK Success!!\n"); ++ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, ++ MASK_IQK_RESULT); ++ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, ++ MASK_IQK_RESULT); ++ } else { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B IQK failed!!\n"); ++ } ++ } ++ ++ /* Back to BB mode, load original value */ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "IQK:Back to BB mode, load original value!\n"); ++ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0); ++ ++ if (is2t) ++ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM); ++ else ++ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, ++ rtlphy->iqk_bb_backup, ++ IQK_BB_REG_NUM - 1); ++ ++ /* path A IQ path to DP block */ ++ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x010170b8); ++ if (is2t) /* path B IQ path to DP block */ ++ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x010170b8); ++ ++ /* Reload MAC parameters */ ++ _rtl92du_phy_reload_mac_registers(hw, iqk_mac_reg, ++ rtlphy->iqk_mac_backup); ++ ++ /* Switch back BB to SI mode after finish IQ Calibration. */ ++ if (!rtlphy->rfpi_enable) ++ _rtl92du_phy_pimode_switch(hw, false); ++ ++ /* Reload ADDA power saving parameters */ ++ _rtl92du_phy_reload_adda_registers(hw, adda_reg, ++ rtlphy->adda_backup, ++ IQK_ADDA_REG_NUM); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); ++} ++ ++static bool _rtl92du_phy_simularity_compare(struct ieee80211_hw *hw, ++ long result[][8], u8 c1, u8 c2) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u32 i, j, diff, sim_bitmap, bound, u4temp = 0; ++ u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ ++ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); ++ bool bresult = true; ++ ++ if (is2t) ++ bound = 8; ++ else ++ bound = 4; ++ ++ sim_bitmap = 0; ++ ++ for (i = 0; i < bound; i++) { ++ diff = abs_diff(result[c1][i], result[c2][i]); ++ ++ if (diff > MAX_TOLERANCE_92D) { ++ if ((i == 2 || i == 6) && !sim_bitmap) { ++ if (result[c1][i] + result[c1][i + 1] == 0) ++ final_candidate[(i / 4)] = c2; ++ else if (result[c2][i] + result[c2][i + 1] == 0) ++ final_candidate[(i / 4)] = c1; ++ else ++ sim_bitmap = sim_bitmap | (1 << i); ++ } else { ++ sim_bitmap = sim_bitmap | (1 << i); ++ } ++ } ++ } ++ ++ if (sim_bitmap == 0) { ++ for (i = 0; i < (bound / 4); i++) { ++ if (final_candidate[i] != 0xFF) { ++ for (j = i * 4; j < (i + 1) * 4 - 2; j++) ++ result[3][j] = ++ result[final_candidate[i]][j]; ++ bresult = false; ++ } ++ } ++ ++ for (i = 0; i < bound; i++) ++ u4temp += result[c1][i] + result[c2][i]; ++ ++ if (u4temp == 0) /* IQK fail for c1 & c2 */ ++ bresult = false; ++ ++ return bresult; ++ } ++ ++ if (!(sim_bitmap & 0x0F)) { /* path A OK */ ++ for (i = 0; i < 4; i++) ++ result[3][i] = result[c1][i]; ++ } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ ++ for (i = 0; i < 2; i++) ++ result[3][i] = result[c1][i]; ++ } ++ ++ if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ ++ for (i = 4; i < 8; i++) ++ result[3][i] = result[c1][i]; ++ } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ ++ for (i = 4; i < 6; i++) ++ result[3][i] = result[c1][i]; ++ } ++ ++ return false; ++} ++ ++static void _rtl92du_phy_patha_fill_iqk_matrix_5g_normal(struct ieee80211_hw *hw, ++ bool iqk_ok, ++ long result[][8], ++ u8 final_candidate, ++ bool txonly) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u32 val_x, reg; ++ int val_y; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); ++ if (iqk_ok && final_candidate != 0xFF) { ++ val_x = result[final_candidate][0]; ++ if ((val_x & 0x00000200) != 0) ++ val_x = val_x | 0xFFFFFC00; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x); ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF0000, val_x); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0); ++ ++ val_y = result[final_candidate][1]; ++ if ((val_y & 0x00000200) != 0) ++ val_y = val_y | 0xFFFFFC00; ++ ++ /* path B IQK result + 3 */ ++ if (rtlhal->current_bandtype == BAND_ON_5G) ++ val_y += 3; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y); ++ ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF, val_y); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 0); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe30 = 0x%x\n", ++ rtl_get_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD)); ++ ++ if (txonly) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); ++ return; ++ } ++ ++ reg = result[final_candidate][2]; ++ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); ++ reg = result[final_candidate][3] & 0x3F; ++ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); ++ reg = (result[final_candidate][3] >> 6) & 0xF; ++ rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); ++ } else { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "%s: Tx/Rx fail restore default value\n", __func__); ++ ++ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); ++ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); ++ } ++} ++ ++static void _rtl92du_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, ++ bool iqk_ok, long result[][8], ++ u8 final_candidate, bool txonly) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u32 oldval_0, val_x, tx0_a, reg; ++ long val_y, tx0_c; ++ bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || ++ rtlhal->macphymode == DUALMAC_DUALPHY; ++ ++ if (rtlhal->current_bandtype == BAND_ON_5G) { ++ _rtl92du_phy_patha_fill_iqk_matrix_5g_normal(hw, iqk_ok, result, ++ final_candidate, ++ txonly); ++ return; ++ } ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); ++ if (final_candidate == 0xFF || !iqk_ok) ++ return; ++ ++ /* OFDM0_D */ ++ oldval_0 = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0xffc00000); ++ ++ val_x = result[final_candidate][0]; ++ if ((val_x & 0x00000200) != 0) ++ val_x = val_x | 0xFFFFFC00; ++ ++ tx0_a = (val_x * oldval_0) >> 8; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", ++ val_x, tx0_a, oldval_0); ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), ++ ((val_x * oldval_0 >> 7) & 0x1)); ++ ++ val_y = result[final_candidate][1]; ++ if ((val_y & 0x00000200) != 0) ++ val_y = val_y | 0xFFFFFC00; ++ ++ /* path B IQK result + 3 */ ++ if (rtlhal->interfaceindex == 1 && ++ rtlhal->current_bandtype == BAND_ON_5G) ++ val_y += 3; ++ ++ tx0_c = (val_y * oldval_0) >> 8; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Y = 0x%lx, tx0_c = 0x%lx\n", ++ val_y, tx0_c); ++ ++ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, (tx0_c & 0x3C0) >> 6); ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, tx0_c & 0x3F); ++ if (is2t) ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), ++ (val_y * oldval_0 >> 7) & 0x1); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", ++ rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, ++ MASKDWORD)); ++ ++ if (txonly) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); ++ return; ++ } ++ ++ reg = result[final_candidate][2]; ++ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); ++ reg = result[final_candidate][3] & 0x3F; ++ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); ++ reg = (result[final_candidate][3] >> 6) & 0xF; ++ rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); ++} ++ ++static void _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal(struct ieee80211_hw *hw, ++ bool iqk_ok, ++ long result[][8], ++ u8 final_candidate, ++ bool txonly) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u32 val_x, reg; ++ int val_y; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "Path B IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); ++ if (iqk_ok && final_candidate != 0xFF) { ++ val_x = result[final_candidate][4]; ++ if ((val_x & 0x00000200) != 0) ++ val_x = val_x | 0xFFFFFC00; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x); ++ rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF0000, val_x); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 0); ++ ++ val_y = result[final_candidate][5]; ++ if ((val_y & 0x00000200) != 0) ++ val_y = val_y | 0xFFFFFC00; ++ ++ /* path B IQK result + 3 */ ++ if (rtlhal->current_bandtype == BAND_ON_5G) ++ val_y += 3; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y); ++ ++ rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF, val_y); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 0); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe50 = 0x%x\n", ++ rtl_get_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD)); ++ ++ if (txonly) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); ++ return; ++ } ++ ++ reg = result[final_candidate][6]; ++ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); ++ reg = result[final_candidate][7] & 0x3F; ++ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); ++ reg = (result[final_candidate][7] >> 6) & 0xF; ++ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); ++ } else { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "%s: Tx/Rx fail restore default value\n", __func__); ++ ++ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); ++ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); ++ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); ++ } ++} ++ ++static void _rtl92du_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, ++ bool iqk_ok, long result[][8], ++ u8 final_candidate, bool txonly) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u32 oldval_1, val_x, tx1_a, reg; ++ long val_y, tx1_c; ++ ++ if (rtlhal->current_bandtype == BAND_ON_5G) { ++ _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal(hw, iqk_ok, result, ++ final_candidate, ++ txonly); ++ return; ++ } ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", ++ iqk_ok ? "Success" : "Failed"); ++ ++ if (final_candidate == 0xFF || !iqk_ok) ++ return; ++ ++ oldval_1 = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0xffc00000); ++ ++ val_x = result[final_candidate][4]; ++ if ((val_x & 0x00000200) != 0) ++ val_x = val_x | 0xFFFFFC00; ++ ++ tx1_a = (val_x * oldval_1) >> 8; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", ++ val_x, tx1_a); ++ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), ++ (val_x * oldval_1 >> 7) & 0x1); ++ ++ val_y = result[final_candidate][5]; ++ if ((val_y & 0x00000200) != 0) ++ val_y = val_y | 0xFFFFFC00; ++ ++ if (rtlhal->current_bandtype == BAND_ON_5G) ++ val_y += 3; ++ ++ tx1_c = (val_y * oldval_1) >> 8; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", ++ val_y, tx1_c); ++ ++ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, (tx1_c & 0x3C0) >> 6); ++ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, tx1_c & 0x3F); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), ++ (val_y * oldval_1 >> 7) & 0x1); ++ ++ if (txonly) ++ return; ++ ++ reg = result[final_candidate][6]; ++ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); ++ reg = result[final_candidate][7] & 0x3F; ++ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); ++ reg = (result[final_candidate][7] >> 6) & 0xF; ++ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); ++} ++ ++void rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw) ++{ ++ long rege94, rege9c, regea4, regeac, regeb4; ++ bool is12simular, is13simular, is23simular; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ long regebc, regec4, regecc, regtmp = 0; ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 i, final_candidate, indexforchannel; ++ bool patha_ok, pathb_ok; ++ long result[4][8] = {}; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "IQK:Start!!!channel %d\n", rtlphy->current_channel); ++ ++ final_candidate = 0xff; ++ patha_ok = false; ++ pathb_ok = false; ++ is12simular = false; ++ is23simular = false; ++ is13simular = false; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "IQK !!!currentband %d\n", rtlhal->current_bandtype); ++ ++ for (i = 0; i < 3; i++) { ++ if (rtlhal->current_bandtype == BAND_ON_5G) { ++ _rtl92du_phy_iq_calibrate_5g_normal(hw, result, i); ++ } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ if (IS_92D_SINGLEPHY(rtlhal->version)) ++ _rtl92du_phy_iq_calibrate(hw, result, i, true); ++ else ++ _rtl92du_phy_iq_calibrate(hw, result, i, false); ++ } ++ ++ if (i == 1) { ++ is12simular = _rtl92du_phy_simularity_compare(hw, result, ++ 0, 1); ++ if (is12simular) { ++ final_candidate = 0; ++ break; ++ } ++ } ++ ++ if (i == 2) { ++ is13simular = _rtl92du_phy_simularity_compare(hw, result, ++ 0, 2); ++ if (is13simular) { ++ final_candidate = 0; ++ break; ++ } ++ ++ is23simular = _rtl92du_phy_simularity_compare(hw, result, ++ 1, 2); ++ if (is23simular) { ++ final_candidate = 1; ++ } else { ++ for (i = 0; i < 8; i++) ++ regtmp += result[3][i]; ++ ++ if (regtmp != 0) ++ final_candidate = 3; ++ else ++ final_candidate = 0xFF; ++ } ++ } ++ } ++ ++ for (i = 0; i < 4; i++) { ++ rege94 = result[i][0]; ++ rege9c = result[i][1]; ++ regea4 = result[i][2]; ++ regeac = result[i][3]; ++ regeb4 = result[i][4]; ++ regebc = result[i][5]; ++ regec4 = result[i][6]; ++ regecc = result[i][7]; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", ++ rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, ++ regecc); ++ } ++ ++ if (final_candidate != 0xff) { ++ rege94 = result[final_candidate][0]; ++ rtlphy->reg_e94 = rege94; ++ rege9c = result[final_candidate][1]; ++ rtlphy->reg_e9c = rege9c; ++ regea4 = result[final_candidate][2]; ++ regeac = result[final_candidate][3]; ++ regeb4 = result[final_candidate][4]; ++ rtlphy->reg_eb4 = regeb4; ++ regebc = result[final_candidate][5]; ++ rtlphy->reg_ebc = regebc; ++ regec4 = result[final_candidate][6]; ++ regecc = result[final_candidate][7]; ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "IQK: final_candidate is %x\n", final_candidate); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", ++ rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, ++ regecc); ++ ++ patha_ok = true; ++ pathb_ok = true; ++ } else { ++ rtlphy->reg_e94 = 0x100; ++ rtlphy->reg_eb4 = 0x100; /* X default value */ ++ rtlphy->reg_e9c = 0x0; ++ rtlphy->reg_ebc = 0x0; /* Y default value */ ++ } ++ if (rege94 != 0 /*&& regea4 != 0*/) ++ _rtl92du_phy_patha_fill_iqk_matrix(hw, patha_ok, result, ++ final_candidate, ++ regea4 == 0); ++ if (IS_92D_SINGLEPHY(rtlhal->version) && ++ regeb4 != 0 /*&& regec4 != 0*/) ++ _rtl92du_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, ++ final_candidate, ++ regec4 == 0); ++ ++ if (final_candidate != 0xFF) { ++ indexforchannel = ++ rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); ++ ++ for (i = 0; i < IQK_MATRIX_REG_NUM; i++) ++ rtlphy->iqk_matrix[indexforchannel].value[0][i] = ++ result[final_candidate][i]; ++ ++ rtlphy->iqk_matrix[indexforchannel].iqk_done = true; ++ ++ rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, ++ "IQK OK indexforchannel %d\n", indexforchannel); ++ } ++} ++ ++void rtl92du_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ u8 indexforchannel; ++ bool need_iqk; ++ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); ++ /*------Do IQK for normal chip and test chip 5G band------- */ ++ ++ indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", ++ indexforchannel, ++ rtlphy->iqk_matrix[indexforchannel].iqk_done); ++ ++ /* We need to do IQK if we're about to connect to a network on 5 GHz. ++ * On 5 GHz a channel switch outside of scanning happens only before ++ * connecting. ++ */ ++ need_iqk = !mac->act_scanning; ++ ++ if (!rtlphy->iqk_matrix[indexforchannel].iqk_done && need_iqk) { ++ rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, ++ "Do IQK Matrix reg for channel:%d....\n", channel); ++ rtl92du_phy_iq_calibrate(hw); ++ return; ++ } ++ ++ /* Just load the value. */ ++ /* 2G band just load once. */ ++ if ((!rtlhal->load_imrandiqk_setting_for2g && indexforchannel == 0) || ++ indexforchannel > 0) { ++ rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, ++ "Just Read IQK Matrix reg for channel:%d....\n", ++ channel); ++ ++ if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) ++ _rtl92du_phy_patha_fill_iqk_matrix(hw, true, ++ rtlphy->iqk_matrix[indexforchannel].value, 0, ++ rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); ++ ++ if (IS_92D_SINGLEPHY(rtlhal->version) && ++ rtlphy->iqk_matrix[indexforchannel].value[0][4] != 0) ++ _rtl92du_phy_pathb_fill_iqk_matrix(hw, true, ++ rtlphy->iqk_matrix[indexforchannel].value, 0, ++ rtlphy->iqk_matrix[indexforchannel].value[0][6] == 0); ++ } ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); ++} ++ ++static void _rtl92du_phy_reload_lck_setting(struct ieee80211_hw *hw, u8 channel) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u8 erfpath = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A : ++ IS_92D_SINGLEPHY(rtlhal->version) ? RF90_PATH_B : RF90_PATH_A; ++ bool bneed_powerdown_radio = false; ++ u32 u4tmp, u4regvalue; ++ ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", ++ rtlpriv->rtlhal.current_bandtype); ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); ++ ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ ++ u4tmp = rtlpriv->curveindex_5g[channel - 1]; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); ++ ++ if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && ++ rtlpriv->rtlhal.interfaceindex == 1) { ++ bneed_powerdown_radio = ++ rtl92du_phy_enable_anotherphy(hw, false); ++ rtlpriv->rtlhal.during_mac1init_radioa = true; ++ /* asume no this case */ ++ if (bneed_powerdown_radio) ++ rtl92d_phy_enable_rf_env(hw, erfpath, ++ &u4regvalue); ++ } ++ ++ rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); ++ ++ if (bneed_powerdown_radio) { ++ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); ++ rtl92du_phy_powerdown_anotherphy(hw, false); ++ } ++ } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { ++ u4tmp = rtlpriv->curveindex_2g[channel - 1]; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); ++ ++ if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && ++ rtlpriv->rtlhal.interfaceindex == 0) { ++ bneed_powerdown_radio = ++ rtl92du_phy_enable_anotherphy(hw, true); ++ rtlpriv->rtlhal.during_mac0init_radiob = true; ++ if (bneed_powerdown_radio) ++ rtl92d_phy_enable_rf_env(hw, erfpath, ++ &u4regvalue); ++ } ++ ++ rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", ++ rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); ++ ++ if (bneed_powerdown_radio) { ++ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); ++ rtl92du_phy_powerdown_anotherphy(hw, true); ++ } ++ } ++ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); ++} ++ ++static void _rtl92du_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u32 curvecount_val[CV_CURVE_CNT * 2]; ++ u16 timeout = 800, timecount = 0; ++ u32 u4tmp, offset, rf_syn_g4[2]; ++ u8 tmpreg, index, rf_mode[2]; ++ u8 path = is2t ? 2 : 1; ++ u8 i; ++ ++ /* Check continuous TX and Packet TX */ ++ tmpreg = rtl_read_byte(rtlpriv, 0xd03); ++ if ((tmpreg & 0x70) != 0) ++ /* if Deal with contisuous TX case, disable all continuous TX */ ++ rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); ++ else ++ /* if Deal with Packet TX case, block all queues */ ++ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); ++ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); ++ ++ for (index = 0; index < path; index++) { ++ /* 1. Read original RF mode */ ++ offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; ++ rf_mode[index] = rtl_read_byte(rtlpriv, offset); ++ ++ /* 2. Set RF mode = standby mode */ ++ rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, ++ RFREG_OFFSET_MASK, 0x010000); ++ ++ rf_syn_g4[index] = rtl_get_rfreg(hw, index, RF_SYN_G4, ++ RFREG_OFFSET_MASK); ++ rtl_set_rfreg(hw, index, RF_SYN_G4, 0x700, 0x7); ++ ++ /* switch CV-curve control by LC-calibration */ ++ rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, ++ BIT(17), 0x0); ++ ++ /* 4. Set LC calibration begin */ ++ rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, ++ 0x08000, 0x01); ++ } ++ ++ for (index = 0; index < path; index++) { ++ u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, ++ RFREG_OFFSET_MASK); ++ ++ while ((!(u4tmp & BIT(11))) && timecount <= timeout) { ++ mdelay(50); ++ timecount += 50; ++ u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, ++ RF_SYN_G6, RFREG_OFFSET_MASK); ++ } ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "PHY_LCK finish delay for %d ms=2\n", timecount); ++ } ++ ++ if ((tmpreg & 0x70) != 0) ++ rtl_write_byte(rtlpriv, 0xd03, tmpreg); ++ else /* Deal with Packet TX case */ ++ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); ++ ++ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); ++ ++ for (index = 0; index < path; index++) { ++ rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); ++ ++ if (index == 0 && rtlhal->interfaceindex == 0) { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "path-A / 5G LCK\n"); ++ } else { ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "path-B / 2.4G LCK\n"); ++ } ++ ++ memset(curvecount_val, 0, sizeof(curvecount_val)); ++ ++ /* Set LC calibration off */ ++ rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, ++ 0x08000, 0x0); ++ ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); ++ ++ /* save Curve-counting number */ ++ for (i = 0; i < CV_CURVE_CNT; i++) { ++ u32 readval = 0, readval2 = 0; ++ ++ rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, ++ 0x7f, i); ++ ++ rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, ++ RFREG_OFFSET_MASK, 0x0); ++ ++ readval = rtl_get_rfreg(hw, (enum radio_path)index, ++ 0x4F, RFREG_OFFSET_MASK); ++ curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; ++ ++ /* reg 0x4f [4:0] */ ++ /* reg 0x50 [19:10] */ ++ readval2 = rtl_get_rfreg(hw, (enum radio_path)index, ++ 0x50, 0xffc00); ++ curvecount_val[2 * i] = (((readval & 0x1F) << 10) | ++ readval2); ++ } ++ ++ if (index == 0 && rtlhal->interfaceindex == 0) ++ rtl92d_phy_calc_curvindex(hw, targetchnl_5g, ++ curvecount_val, ++ true, rtlpriv->curveindex_5g); ++ else ++ rtl92d_phy_calc_curvindex(hw, targetchnl_2g, ++ curvecount_val, ++ false, rtlpriv->curveindex_2g); ++ ++ /* switch CV-curve control mode */ ++ rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, ++ BIT(17), 0x1); ++ } ++ ++ /* Restore original situation */ ++ for (index = 0; index < path; index++) { ++ rtl_set_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK, ++ rf_syn_g4[index]); ++ ++ offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; ++ rtl_write_byte(rtlpriv, offset, 0x50); ++ rtl_write_byte(rtlpriv, offset, rf_mode[index]); ++ } ++ ++ _rtl92du_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); ++} ++ ++void rtl92du_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u32 timeout = 2000, timecount = 0; ++ ++ while (rtlpriv->mac80211.act_scanning && timecount < timeout) { ++ udelay(50); ++ timecount += 50; ++ } ++ ++ rtlphy->lck_inprogress = true; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, ++ "LCK:Start!!! currentband %x delay %d ms\n", ++ rtlhal->current_bandtype, timecount); ++ ++ _rtl92du_phy_lc_calibrate_sw(hw, is2t); ++ ++ rtlphy->lck_inprogress = false; ++ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); ++} ++ ++void rtl92du_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) ++{ ++ /* Nothing to do. */ ++} ++ ++u8 rtl92du_phy_sw_chnl(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 num_total_rfpath = rtlphy->num_total_rfpath; ++ u8 channel = rtlphy->current_channel; ++ u32 timeout = 1000, timecount = 0; ++ u32 ret_value; ++ u8 rfpath; ++ ++ if (rtlphy->sw_chnl_inprogress) ++ return 0; ++ if (rtlphy->set_bwmode_inprogress) ++ return 0; ++ ++ if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { ++ rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, ++ "sw_chnl_inprogress false driver sleep or unload\n"); ++ return 0; ++ } ++ ++ while (rtlphy->lck_inprogress && timecount < timeout) { ++ mdelay(50); ++ timecount += 50; ++ } ++ ++ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && ++ rtlhal->bandset == BAND_ON_BOTH) { ++ ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, ++ MASKDWORD); ++ if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) ++ rtl92du_phy_switch_wirelessband(hw, BAND_ON_5G); ++ else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) ++ rtl92du_phy_switch_wirelessband(hw, BAND_ON_2_4G); ++ } ++ ++ switch (rtlhal->current_bandtype) { ++ case BAND_ON_5G: ++ /* Get first channel error when change between ++ * 5G and 2.4G band. ++ */ ++ if (WARN_ONCE(channel <= 14, "rtl8192du: 5G but channel<=14\n")) ++ return 0; ++ break; ++ case BAND_ON_2_4G: ++ /* Get first channel error when change between ++ * 5G and 2.4G band. ++ */ ++ if (WARN_ONCE(channel > 14, "rtl8192du: 2G but channel>14\n")) ++ return 0; ++ break; ++ default: ++ WARN_ONCE(true, "rtl8192du: Invalid WirelessMode(%#x)!!\n", ++ rtlpriv->mac80211.mode); ++ break; ++ } ++ ++ rtlphy->sw_chnl_inprogress = true; ++ ++ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, ++ "switch to channel%d\n", rtlphy->current_channel); ++ ++ rtl92d_phy_set_txpower_level(hw, channel); ++ ++ for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { ++ u32p_replace_bits(&rtlphy->rfreg_chnlval[rfpath], ++ channel, 0xff); ++ ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { ++ if (channel > 99) ++ rtlphy->rfreg_chnlval[rfpath] |= (BIT(18)); ++ else ++ rtlphy->rfreg_chnlval[rfpath] &= ~BIT(18); ++ rtlphy->rfreg_chnlval[rfpath] |= (BIT(16) | BIT(8)); ++ } else { ++ rtlphy->rfreg_chnlval[rfpath] &= ++ ~(BIT(8) | BIT(16) | BIT(18)); ++ } ++ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, RFREG_OFFSET_MASK, ++ rtlphy->rfreg_chnlval[rfpath]); ++ ++ _rtl92du_phy_reload_imr_setting(hw, channel, rfpath); ++ } ++ ++ _rtl92du_phy_switch_rf_setting(hw, channel); ++ ++ /* do IQK when all parameters are ready */ ++ rtl92du_phy_reload_iqk_setting(hw, channel); ++ ++ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); ++ rtlphy->sw_chnl_inprogress = false; ++ return 1; ++} ++ ++static void _rtl92du_phy_set_rfon(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ ++ /* b. SPS_CTRL 0x11[7:0] = 0x2b */ ++ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) ++ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); ++ ++ /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); ++ ++ /* RF_ON_EXCEP(d~g): */ ++ /* d. APSD_CTRL 0x600[7:0] = 0x00 */ ++ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); ++ ++ /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ ++ /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); ++ ++ /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ ++ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); ++} ++ ++static void _rtl92du_phy_set_rfsleep(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ u32 u4btmp; ++ u8 retry = 5; ++ ++ /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ ++ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); ++ ++ /* b. RF path 0 offset 0x00 = 0x00 disable RF */ ++ rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); ++ ++ /* c. APSD_CTRL 0x600[7:0] = 0x40 */ ++ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); ++ ++ /* d. APSD_CTRL 0x600[7:0] = 0x00 ++ * APSD_CTRL 0x600[7:0] = 0x00 ++ * RF path 0 offset 0x00 = 0x00 ++ * APSD_CTRL 0x600[7:0] = 0x40 ++ */ ++ u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); ++ while (u4btmp != 0 && retry > 0) { ++ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); ++ rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); ++ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); ++ u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); ++ retry--; ++ } ++ if (retry == 0) { ++ /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ ++ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); ++ ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); ++ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); ++ rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, ++ "Fail !!! Switch RF timeout\n"); ++ return; ++ } ++ ++ /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ ++ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); ++ ++ /* f. SPS_CTRL 0x11[7:0] = 0x22 */ ++ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) ++ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); ++} ++ ++bool rtl92du_phy_set_rf_power_state(struct ieee80211_hw *hw, ++ enum rf_pwrstate rfpwr_state) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ bool bresult = true; ++ ++ if (rfpwr_state == ppsc->rfpwr_state) ++ return false; ++ ++ switch (rfpwr_state) { ++ case ERFON: ++ if (ppsc->rfpwr_state == ERFOFF && ++ RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { ++ u32 initializecount = 0; ++ bool rtstatus; ++ ++ do { ++ initializecount++; ++ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, ++ "IPS Set eRf nic enable\n"); ++ rtstatus = rtl_ps_enable_nic(hw); ++ } while (!rtstatus && (initializecount < 10)); ++ ++ RT_CLEAR_PS_LEVEL(ppsc, ++ RT_RF_OFF_LEVL_HALT_NIC); ++ } else { ++ rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, ++ "awake, slept:%d ms state_inap:%x\n", ++ jiffies_to_msecs(jiffies - ++ ppsc->last_sleep_jiffies), ++ rtlpriv->psc.state_inap); ++ ppsc->last_awake_jiffies = jiffies; ++ _rtl92du_phy_set_rfon(hw); ++ } ++ ++ if (mac->link_state == MAC80211_LINKED) ++ rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); ++ else ++ rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); ++ break; ++ case ERFOFF: ++ if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { ++ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, ++ "IPS Set eRf nic disable\n"); ++ rtl_ps_disable_nic(hw); ++ RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); ++ } else { ++ if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ++ rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); ++ else ++ rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); ++ } ++ break; ++ case ERFSLEEP: ++ if (ppsc->rfpwr_state == ERFOFF) ++ return false; ++ ++ rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, ++ "sleep awakened:%d ms state_inap:%x\n", ++ jiffies_to_msecs(jiffies - ++ ppsc->last_awake_jiffies), ++ rtlpriv->psc.state_inap); ++ ppsc->last_sleep_jiffies = jiffies; ++ _rtl92du_phy_set_rfsleep(hw); ++ break; ++ default: ++ pr_err("switch case %#x not processed\n", ++ rfpwr_state); ++ return false; ++ } ++ ++ if (bresult) ++ ppsc->rfpwr_state = rfpwr_state; ++ ++ return bresult; ++} ++ ++void rtl92du_phy_set_poweron(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); ++ u8 value8; ++ u16 i; ++ ++ /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ value8 = rtl_read_byte(rtlpriv, mac_reg); ++ value8 |= BIT(1); ++ rtl_write_byte(rtlpriv, mac_reg, value8); ++ } else { ++ value8 = rtl_read_byte(rtlpriv, mac_reg); ++ value8 &= ~BIT(1); ++ rtl_write_byte(rtlpriv, mac_reg, value8); ++ } ++ ++ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { ++ value8 = rtl_read_byte(rtlpriv, REG_MAC0); ++ rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); ++ } else { ++ mutex_lock(rtlpriv->mutex_for_power_on_off); ++ if (rtlhal->interfaceindex == 0) { ++ value8 = rtl_read_byte(rtlpriv, REG_MAC0); ++ rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); ++ } else { ++ value8 = rtl_read_byte(rtlpriv, REG_MAC1); ++ rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); ++ } ++ value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); ++ mutex_unlock(rtlpriv->mutex_for_power_on_off); ++ ++ for (i = 0; i < 200; i++) { ++ if ((value8 & BIT(7)) == 0) ++ break; ++ ++ udelay(500); ++ mutex_lock(rtlpriv->mutex_for_power_on_off); ++ value8 = rtl_read_byte(rtlpriv, ++ REG_POWER_OFF_IN_PROCESS); ++ mutex_unlock(rtlpriv->mutex_for_power_on_off); ++ } ++ if (i == 200) ++ WARN_ONCE(true, "rtl8192du: Another mac power off over time\n"); ++ } ++} ++ ++void rtl92du_update_bbrf_configuration(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ u8 rfpath, i; ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); ++ /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ /* r_select_5G for path_A/B, 0x878 */ ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); ++ if (rtlhal->macphymode != DUALMAC_DUALPHY) { ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); ++ } ++ ++ /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G, 0xc78 */ ++ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); ++ ++ /* fc_area 0xd2c */ ++ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); ++ ++ /* 5G LAN ON */ ++ rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); ++ ++ /* TX BB gain shift*1, Just for testchip, 0xc80, 0xc88 */ ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 0x40000100); ++ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 0x40000100); ++ if (rtlhal->macphymode == DUALMAC_DUALPHY) { ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, ++ BIT(10) | BIT(6) | BIT(5), ++ ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | ++ (rtlefuse->eeprom_c9 & BIT(1)) | ++ ((rtlefuse->eeprom_cc & BIT(1)) << 4)); ++ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, ++ BIT(10) | BIT(6) | BIT(5), ++ ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | ++ ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | ++ ((rtlefuse->eeprom_cc & BIT(0)) << 5)); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); ++ ++ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); ++ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); ++ } else { ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, ++ BIT(26) | BIT(22) | BIT(21) | BIT(10) | ++ BIT(6) | BIT(5), ++ ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | ++ (rtlefuse->eeprom_c9 & BIT(1)) | ++ ((rtlefuse->eeprom_cc & BIT(1)) << 4) | ++ ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | ++ ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | ++ ((rtlefuse->eeprom_cc & BIT(3)) << 18)); ++ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, ++ BIT(10) | BIT(6) | BIT(5), ++ ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | ++ ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | ++ ((rtlefuse->eeprom_cc & BIT(0)) << 5)); ++ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, ++ BIT(10) | BIT(6) | BIT(5), ++ ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | ++ ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | ++ ((rtlefuse->eeprom_cc & BIT(2)) << 3)); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, ++ BIT(31) | BIT(15), 0); ++ ++ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); ++ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017038); ++ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); ++ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); ++ } ++ /* 1.5V_LDO */ ++ } else { ++ /* r_select_5G for path_A/B */ ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); ++ if (rtlhal->macphymode != DUALMAC_DUALPHY) { ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); ++ } ++ ++ /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G */ ++ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); ++ ++ /* fc_area */ ++ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); ++ ++ /* 5G LAN ON */ ++ rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); ++ ++ /* TX BB gain shift, Just for testchip, 0xc80, 0xc88 */ ++ if (rtlefuse->internal_pa_5g[rtlhal->interfaceindex]) ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, ++ 0x2d4000b5); ++ else ++ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, ++ 0x20000080); ++ ++ if (rtlhal->macphymode != DUALMAC_DUALPHY) { ++ if (rtlefuse->internal_pa_5g[1]) ++ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, ++ MASKDWORD, 0x2d4000b5); ++ else ++ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, ++ MASKDWORD, 0x20000080); ++ } ++ ++ rtl_set_bbreg(hw, 0xB30, BIT(27), 0); ++ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY) { ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, ++ BIT(10) | BIT(6) | BIT(5), ++ (rtlefuse->eeprom_cc & BIT(5))); ++ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), ++ ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), ++ (rtlefuse->eeprom_cc & BIT(4)) >> 4); ++ ++ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); ++ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); ++ } else { ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, ++ BIT(26) | BIT(22) | BIT(21) | BIT(10) | ++ BIT(6) | BIT(5), ++ (rtlefuse->eeprom_cc & BIT(5)) | ++ ((rtlefuse->eeprom_cc & BIT(7)) << 14)); ++ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), ++ ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); ++ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), ++ ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); ++ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, ++ BIT(31) | BIT(15), ++ ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | ++ ((rtlefuse->eeprom_cc & BIT(6)) << 10)); ++ ++ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); ++ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017098); ++ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); ++ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); ++ } ++ } ++ ++ /* update IQK related settings */ ++ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); ++ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); ++ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | ++ BIT(26) | BIT(24), 0x00); ++ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, 0x00); ++ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); ++ ++ /* Update RF */ ++ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; ++ rfpath++) { ++ if (rtlhal->current_bandtype == BAND_ON_2_4G) { ++ /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ ++ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | ++ BIT(18) | 0xff, 1); ++ ++ /* RF0x0b[16:14] =3b'111 */ ++ rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, ++ 0x1c000, 0x07); ++ } else { ++ /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, ++ 0x97524); ++ } ++ ++ /* Set right channel on RF reg0x18 for another mac. */ ++ if (rtlhal->interfaceindex == 0 && rtlhal->bandset == BAND_ON_2_4G) { ++ /* Set MAC1 default channel if MAC1 not up. */ ++ if (!(rtl_read_byte(rtlpriv, REG_MAC1) & MAC1_ON)) { ++ rtl92du_phy_enable_anotherphy(hw, true); ++ rtlhal->during_mac0init_radiob = true; ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, ++ RFREG_OFFSET_MASK, 0x97524); ++ rtl92du_phy_powerdown_anotherphy(hw, true); ++ } ++ } else if (rtlhal->interfaceindex == 1 && rtlhal->bandset == BAND_ON_5G) { ++ /* Set MAC0 default channel */ ++ if (!(rtl_read_byte(rtlpriv, REG_MAC0) & MAC0_ON)) { ++ rtl92du_phy_enable_anotherphy(hw, false); ++ rtlhal->during_mac1init_radioa = true; ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, ++ RFREG_OFFSET_MASK, 0x87401); ++ rtl92du_phy_powerdown_anotherphy(hw, false); ++ } ++ } ++ } ++ ++ /* Update for all band. */ ++ /* DMDP */ ++ if (rtlphy->rf_type == RF_1T1R) { ++ /* Use antenna 0, 0xc04, 0xd04 */ ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); ++ rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); ++ ++ /* enable ad/da clock1 for dual-phy reg0x888 */ ++ if (rtlhal->interfaceindex == 0) { ++ rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | ++ BIT(13), 0x3); ++ } else if (rtl92du_phy_enable_anotherphy(hw, false)) { ++ rtlhal->during_mac1init_radioa = true; ++ rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, ++ BIT(12) | BIT(13), 0x3); ++ rtl92du_phy_powerdown_anotherphy(hw, false); ++ } ++ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x0); ++ } else { ++ /* Single PHY */ ++ /* Use antenna 0 & 1, 0xc04, 0xd04 */ ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); ++ rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); ++ /* disable ad/da clock1,0x888 */ ++ rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); ++ ++ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x1); ++ } ++ ++ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; ++ rfpath++) { ++ rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, ++ RF_CHNLBW, ++ RFREG_OFFSET_MASK); ++ rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, ++ RFREG_OFFSET_MASK); ++ } ++ ++ for (i = 0; i < 2; i++) ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", ++ rtlphy->rfreg_chnlval[i]); ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); ++} ++ ++bool rtl92du_phy_check_poweroff(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); ++ u8 u1btmp; ++ ++ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { ++ u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); ++ rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & ~MAC0_ON); ++ return true; ++ } ++ ++ mutex_lock(rtlpriv->mutex_for_power_on_off); ++ if (rtlhal->interfaceindex == 0) { ++ u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); ++ rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & ~MAC0_ON); ++ u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); ++ u1btmp &= MAC1_ON; ++ } else { ++ u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); ++ rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & ~MAC1_ON); ++ u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); ++ u1btmp &= MAC0_ON; ++ } ++ if (u1btmp) { ++ mutex_unlock(rtlpriv->mutex_for_power_on_off); ++ return false; ++ } ++ u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); ++ u1btmp |= BIT(7); ++ rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); ++ mutex_unlock(rtlpriv->mutex_for_power_on_off); ++ ++ return true; ++} ++ ++void rtl92du_phy_init_pa_bias(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ bool is_single_mac = rtlhal->macphymode == SINGLEMAC_SINGLEPHY; ++ enum radio_path rf_path; ++ u8 val8; ++ ++ read_efuse_byte(hw, 0x3FA, &val8); ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "%s: 0x3FA %#x\n", ++ __func__, val8); ++ ++ if (!(val8 & BIT(0)) && (is_single_mac || rtlhal->interfaceindex == 0)) { ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F425); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F425); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F425); ++ ++ /* Back to RX Mode */ ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000); ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "2G PA BIAS path A\n"); ++ } ++ ++ if (!(val8 & BIT(1)) && (is_single_mac || rtlhal->interfaceindex == 1)) { ++ rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B; ++ ++ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401); ++ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F425); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F425); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F425); ++ ++ /* Back to RX Mode */ ++ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000); ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "2G PA BIAS path B\n"); ++ } ++ ++ if (!(val8 & BIT(2)) && (is_single_mac || rtlhal->interfaceindex == 0)) { ++ /* 5GL_channel */ ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); ++ ++ /* 5GM_channel */ ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); ++ ++ /* 5GH_channel */ ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); ++ ++ /* Back to RX Mode */ ++ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000); ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "5G PA BIAS path A\n"); ++ } ++ ++ if (!(val8 & BIT(3)) && (is_single_mac || rtlhal->interfaceindex == 1)) { ++ rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B; ++ ++ /* 5GL_channel */ ++ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524); ++ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); ++ ++ /* 5GM_channel */ ++ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564); ++ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); ++ ++ /* 5GH_channel */ ++ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595); ++ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); ++ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); ++ ++ /* Back to RX Mode */ ++ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000); ++ ++ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "5G PA BIAS path B\n"); ++ } ++} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h +new file mode 100644 +index 000000000000..090a6203db7e +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_PHY_H__ ++#define __RTL92DU_PHY_H__ ++ ++u32 rtl92du_phy_query_bb_reg(struct ieee80211_hw *hw, ++ u32 regaddr, u32 bitmask); ++void rtl92du_phy_set_bb_reg(struct ieee80211_hw *hw, ++ u32 regaddr, u32 bitmask, u32 data); ++bool rtl92du_phy_mac_config(struct ieee80211_hw *hw); ++bool rtl92du_phy_bb_config(struct ieee80211_hw *hw); ++bool rtl92du_phy_rf_config(struct ieee80211_hw *hw); ++void rtl92du_phy_set_bw_mode(struct ieee80211_hw *hw, ++ enum nl80211_channel_type ch_type); ++u8 rtl92du_phy_sw_chnl(struct ieee80211_hw *hw); ++bool rtl92du_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, ++ enum rf_content content, ++ enum radio_path rfpath); ++bool rtl92du_phy_set_rf_power_state(struct ieee80211_hw *hw, ++ enum rf_pwrstate rfpwr_state); ++ ++void rtl92du_phy_set_poweron(struct ieee80211_hw *hw); ++bool rtl92du_phy_check_poweroff(struct ieee80211_hw *hw); ++void rtl92du_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t); ++void rtl92du_update_bbrf_configuration(struct ieee80211_hw *hw); ++void rtl92du_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta); ++void rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw); ++void rtl92du_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel); ++void rtl92du_phy_init_pa_bias(struct ieee80211_hw *hw); ++ ++#endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0023-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0023-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch new file mode 100644 index 0000000000..3274cf29dd --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0023-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch @@ -0,0 +1,462 @@ +From 8125d619567b9a3620244251b8eab25074cafcfa Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:46:26 +0300 +Subject: [PATCH 23/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/trx.{c,h} + +These contain routines related to sending frames to the chip. + +Signed-off-by: Bitterblue Smith +--- + .../wireless/realtek/rtlwifi/rtl8192du/trx.c | 372 ++++++++++++++++++ + .../wireless/realtek/rtlwifi/rtl8192du/trx.h | 60 +++ + 2 files changed, 432 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c +new file mode 100644 +index 000000000000..743ce0cfffe6 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c +@@ -0,0 +1,372 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../base.h" ++#include "../usb.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/trx_common.h" ++#include "trx.h" ++ ++void rtl92du_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb) ++{ ++} ++ ++int rtl92du_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb, ++ struct sk_buff *skb) ++{ ++ return 0; ++} ++ ++struct sk_buff *rtl92du_tx_aggregate_hdl(struct ieee80211_hw *hw, ++ struct sk_buff_head *list) ++{ ++ return skb_dequeue(list); ++} ++ ++static enum rtl_desc_qsel _rtl92du_hwq_to_descq(u16 queue_index) ++{ ++ switch (queue_index) { ++ case RTL_TXQ_BCN: ++ return QSLT_BEACON; ++ case RTL_TXQ_MGT: ++ return QSLT_MGNT; ++ case RTL_TXQ_VO: ++ return QSLT_VO; ++ case RTL_TXQ_VI: ++ return QSLT_VI; ++ case RTL_TXQ_BK: ++ return QSLT_BK; ++ default: ++ case RTL_TXQ_BE: ++ return QSLT_BE; ++ } ++} ++ ++/* For HW recovery information */ ++static void _rtl92du_tx_desc_checksum(__le32 *txdesc) ++{ ++ __le16 *ptr = (__le16 *)txdesc; ++ u16 checksum = 0; ++ u32 index; ++ ++ /* Clear first */ ++ set_tx_desc_tx_desc_checksum(txdesc, 0); ++ for (index = 0; index < 16; index++) ++ checksum = checksum ^ le16_to_cpu(*(ptr + index)); ++ set_tx_desc_tx_desc_checksum(txdesc, checksum); ++} ++ ++void rtl92du_tx_fill_desc(struct ieee80211_hw *hw, ++ struct ieee80211_hdr *hdr, u8 *pdesc_tx, ++ u8 *pbd_desc_tx, struct ieee80211_tx_info *info, ++ struct ieee80211_sta *sta, ++ struct sk_buff *skb, ++ u8 queue_index, ++ struct rtl_tcb_desc *tcb_desc) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ struct rtl_mac *mac = rtl_mac(rtlpriv); ++ struct rtl_sta_info *sta_entry; ++ __le16 fc = hdr->frame_control; ++ u8 agg_state = RTL_AGG_STOP; ++ u16 pktlen = skb->len; ++ u32 rts_en, hw_rts_en; ++ u8 ampdu_density = 0; ++ u16 seq_number; ++ __le32 *txdesc; ++ u8 rate_flag; ++ u8 tid; ++ ++ rtl_get_tcb_desc(hw, info, sta, skb, tcb_desc); ++ ++ txdesc = (__le32 *)skb_push(skb, RTL_TX_HEADER_SIZE); ++ memset(txdesc, 0, RTL_TX_HEADER_SIZE); ++ ++ set_tx_desc_pkt_size(txdesc, pktlen); ++ set_tx_desc_linip(txdesc, 0); ++ set_tx_desc_pkt_offset(txdesc, RTL_DUMMY_OFFSET); ++ set_tx_desc_offset(txdesc, RTL_TX_HEADER_SIZE); ++ /* 5G have no CCK rate */ ++ if (rtlhal->current_bandtype == BAND_ON_5G) ++ if (tcb_desc->hw_rate < DESC_RATE6M) ++ tcb_desc->hw_rate = DESC_RATE6M; ++ ++ set_tx_desc_tx_rate(txdesc, tcb_desc->hw_rate); ++ if (tcb_desc->use_shortgi || tcb_desc->use_shortpreamble) ++ set_tx_desc_data_shortgi(txdesc, 1); ++ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY && ++ tcb_desc->hw_rate == DESC_RATEMCS7) ++ set_tx_desc_data_shortgi(txdesc, 1); ++ ++ if (sta) { ++ sta_entry = (struct rtl_sta_info *)sta->drv_priv; ++ tid = ieee80211_get_tid(hdr); ++ agg_state = sta_entry->tids[tid].agg.agg_state; ++ ampdu_density = sta->deflink.ht_cap.ampdu_density; ++ } ++ ++ if (agg_state == RTL_AGG_OPERATIONAL && ++ info->flags & IEEE80211_TX_CTL_AMPDU) { ++ set_tx_desc_agg_enable(txdesc, 1); ++ set_tx_desc_max_agg_num(txdesc, 0x14); ++ set_tx_desc_ampdu_density(txdesc, ampdu_density); ++ tcb_desc->rts_enable = 1; ++ tcb_desc->rts_rate = DESC_RATE24M; ++ } else { ++ set_tx_desc_agg_break(txdesc, 1); ++ } ++ seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; ++ set_tx_desc_seq(txdesc, seq_number); ++ ++ rts_en = tcb_desc->rts_enable && !tcb_desc->cts_enable; ++ hw_rts_en = tcb_desc->rts_enable || tcb_desc->cts_enable; ++ set_tx_desc_rts_enable(txdesc, rts_en); ++ set_tx_desc_hw_rts_enable(txdesc, hw_rts_en); ++ set_tx_desc_cts2self(txdesc, tcb_desc->cts_enable); ++ set_tx_desc_rts_stbc(txdesc, tcb_desc->rts_stbc); ++ /* 5G have no CCK rate */ ++ if (rtlhal->current_bandtype == BAND_ON_5G) ++ if (tcb_desc->rts_rate < DESC_RATE6M) ++ tcb_desc->rts_rate = DESC_RATE6M; ++ set_tx_desc_rts_rate(txdesc, tcb_desc->rts_rate); ++ set_tx_desc_rts_bw(txdesc, 0); ++ set_tx_desc_rts_sc(txdesc, tcb_desc->rts_sc); ++ set_tx_desc_rts_short(txdesc, tcb_desc->rts_use_shortpreamble); ++ ++ rate_flag = info->control.rates[0].flags; ++ if (mac->bw_40) { ++ if (rate_flag & IEEE80211_TX_RC_DUP_DATA) { ++ set_tx_desc_data_bw(txdesc, 1); ++ set_tx_desc_tx_sub_carrier(txdesc, 3); ++ } else if (rate_flag & IEEE80211_TX_RC_40_MHZ_WIDTH) { ++ set_tx_desc_data_bw(txdesc, 1); ++ set_tx_desc_tx_sub_carrier(txdesc, mac->cur_40_prime_sc); ++ } else { ++ set_tx_desc_data_bw(txdesc, 0); ++ set_tx_desc_tx_sub_carrier(txdesc, 0); ++ } ++ } else { ++ set_tx_desc_data_bw(txdesc, 0); ++ set_tx_desc_tx_sub_carrier(txdesc, 0); ++ } ++ ++ if (info->control.hw_key) { ++ struct ieee80211_key_conf *keyconf = info->control.hw_key; ++ ++ switch (keyconf->cipher) { ++ case WLAN_CIPHER_SUITE_WEP40: ++ case WLAN_CIPHER_SUITE_WEP104: ++ case WLAN_CIPHER_SUITE_TKIP: ++ set_tx_desc_sec_type(txdesc, 0x1); ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ set_tx_desc_sec_type(txdesc, 0x3); ++ break; ++ default: ++ set_tx_desc_sec_type(txdesc, 0x0); ++ break; ++ } ++ } ++ ++ set_tx_desc_pkt_id(txdesc, 0); ++ set_tx_desc_queue_sel(txdesc, _rtl92du_hwq_to_descq(queue_index)); ++ set_tx_desc_data_rate_fb_limit(txdesc, 0x1F); ++ set_tx_desc_rts_rate_fb_limit(txdesc, 0xF); ++ set_tx_desc_disable_fb(txdesc, 0); ++ set_tx_desc_use_rate(txdesc, tcb_desc->use_driver_rate); ++ ++ if (ieee80211_is_data_qos(fc)) { ++ if (mac->rdg_en) { ++ rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, ++ "Enable RDG function\n"); ++ set_tx_desc_rdg_enable(txdesc, 1); ++ set_tx_desc_htc(txdesc, 1); ++ } ++ set_tx_desc_qos(txdesc, 1); ++ } ++ ++ if (rtlpriv->dm.useramask) { ++ set_tx_desc_rate_id(txdesc, tcb_desc->ratr_index); ++ set_tx_desc_macid(txdesc, tcb_desc->mac_id); ++ } else { ++ set_tx_desc_rate_id(txdesc, 0xC + tcb_desc->ratr_index); ++ set_tx_desc_macid(txdesc, tcb_desc->ratr_index); ++ } ++ ++ if (!ieee80211_is_data_qos(fc) && ppsc->leisure_ps && ++ ppsc->fwctrl_lps) { ++ set_tx_desc_hwseq_en(txdesc, 1); ++ set_tx_desc_pkt_id(txdesc, 8); ++ } ++ ++ if (ieee80211_has_morefrags(fc)) ++ set_tx_desc_more_frag(txdesc, 1); ++ if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || ++ is_broadcast_ether_addr(ieee80211_get_DA(hdr))) ++ set_tx_desc_bmc(txdesc, 1); ++ ++ set_tx_desc_own(txdesc, 1); ++ set_tx_desc_last_seg(txdesc, 1); ++ set_tx_desc_first_seg(txdesc, 1); ++ _rtl92du_tx_desc_checksum(txdesc); ++ ++ rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "==>\n"); ++} ++ ++static void _rtl92du_config_out_ep(struct ieee80211_hw *hw, u8 num_out_pipe) ++{ ++ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ u16 ep_cfg; ++ ++ rtlusb->out_queue_sel = 0; ++ rtlusb->out_ep_nums = 0; ++ ++ if (rtlhal->interfaceindex == 0) ++ ep_cfg = rtl_read_word(rtlpriv, REG_USB_Queue_Select_MAC0); ++ else ++ ep_cfg = rtl_read_word(rtlpriv, REG_USB_Queue_Select_MAC1); ++ ++ if (ep_cfg & 0x00f) { ++ rtlusb->out_queue_sel |= TX_SELE_HQ; ++ rtlusb->out_ep_nums++; ++ } ++ if (ep_cfg & 0x0f0) { ++ rtlusb->out_queue_sel |= TX_SELE_NQ; ++ rtlusb->out_ep_nums++; ++ } ++ if (ep_cfg & 0xf00) { ++ rtlusb->out_queue_sel |= TX_SELE_LQ; ++ rtlusb->out_ep_nums++; ++ } ++ ++ switch (num_out_pipe) { ++ case 3: ++ rtlusb->out_queue_sel = TX_SELE_HQ | TX_SELE_NQ | TX_SELE_LQ; ++ rtlusb->out_ep_nums = 3; ++ break; ++ case 2: ++ rtlusb->out_queue_sel = TX_SELE_HQ | TX_SELE_NQ; ++ rtlusb->out_ep_nums = 2; ++ break; ++ case 1: ++ rtlusb->out_queue_sel = TX_SELE_HQ; ++ rtlusb->out_ep_nums = 1; ++ break; ++ default: ++ break; ++ } ++} ++ ++static void _rtl92du_one_out_ep_mapping(struct rtl_usb *rtlusb, ++ struct rtl_ep_map *ep_map) ++{ ++ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; ++} ++ ++static void _rtl92du_two_out_ep_mapping(struct rtl_usb *rtlusb, ++ struct rtl_ep_map *ep_map) ++{ ++ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[1]; ++ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[1]; ++ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; ++} ++ ++static void _rtl92du_three_out_ep_mapping(struct rtl_usb *rtlusb, ++ struct rtl_ep_map *ep_map) ++{ ++ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[2]; ++ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[2]; ++ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[1]; ++ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; ++ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; ++} ++ ++static int _rtl92du_out_ep_mapping(struct ieee80211_hw *hw) ++{ ++ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); ++ struct rtl_ep_map *ep_map = &rtlusb->ep_map; ++ ++ switch (rtlusb->out_ep_nums) { ++ case 1: ++ _rtl92du_one_out_ep_mapping(rtlusb, ep_map); ++ break; ++ case 2: ++ _rtl92du_two_out_ep_mapping(rtlusb, ep_map); ++ break; ++ case 3: ++ _rtl92du_three_out_ep_mapping(rtlusb, ep_map); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int rtl92du_endpoint_mapping(struct ieee80211_hw *hw) ++{ ++ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); ++ ++ _rtl92du_config_out_ep(hw, rtlusb->out_ep_nums); ++ ++ /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */ ++ if (rtlusb->out_ep_nums == 1 && rtlusb->in_ep_nums != 1) ++ return -EINVAL; ++ ++ return _rtl92du_out_ep_mapping(hw); ++} ++ ++u16 rtl92du_mq_to_hwq(__le16 fc, u16 mac80211_queue_index) ++{ ++ u16 hw_queue_index; ++ ++ if (unlikely(ieee80211_is_beacon(fc))) { ++ hw_queue_index = RTL_TXQ_BCN; ++ goto out; ++ } ++ if (ieee80211_is_mgmt(fc)) { ++ hw_queue_index = RTL_TXQ_MGT; ++ goto out; ++ } ++ ++ switch (mac80211_queue_index) { ++ case 0: ++ hw_queue_index = RTL_TXQ_VO; ++ break; ++ case 1: ++ hw_queue_index = RTL_TXQ_VI; ++ break; ++ case 2: ++ hw_queue_index = RTL_TXQ_BE; ++ break; ++ case 3: ++ hw_queue_index = RTL_TXQ_BK; ++ break; ++ default: ++ hw_queue_index = RTL_TXQ_BE; ++ WARN_ONCE(true, "rtl8192du: QSLT_BE queue, skb_queue:%d\n", ++ mac80211_queue_index); ++ break; ++ } ++out: ++ return hw_queue_index; ++} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h +new file mode 100644 +index 000000000000..8c3d24622fa7 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h +@@ -0,0 +1,60 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_TRX_H__ ++#define __RTL92DU_TRX_H__ ++ ++#define TX_SELE_HQ BIT(0) /* High Queue */ ++#define TX_SELE_LQ BIT(1) /* Low Queue */ ++#define TX_SELE_NQ BIT(2) /* Normal Queue */ ++ ++#define TX_TOTAL_PAGE_NUMBER_92DU 0xF8 ++#define TEST_PAGE_NUM_PUBQ_92DU 0x89 ++#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A ++#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A ++#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10 ++#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10 ++#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0 ++ ++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0x65 ++#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0x30 ++#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0x30 ++#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0x30 ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x32 ++#define WMM_NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x18 ++#define WMM_NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x18 ++#define WMM_NORMAL_PAGE_NUM_NPQ_92D_DUAL_MAC 0x18 ++ ++static inline void set_tx_desc_bmc(__le32 *__txdesc, u32 __value) ++{ ++ le32p_replace_bits(__txdesc, __value, BIT(24)); ++} ++ ++static inline void set_tx_desc_agg_break(__le32 *__txdesc, u32 __value) ++{ ++ le32p_replace_bits((__txdesc + 1), __value, BIT(6)); ++} ++ ++static inline void set_tx_desc_tx_desc_checksum(__le32 *__txdesc, u32 __value) ++{ ++ le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0)); ++} ++ ++void rtl92du_tx_fill_desc(struct ieee80211_hw *hw, ++ struct ieee80211_hdr *hdr, u8 *pdesc, ++ u8 *pbd_desc_tx, struct ieee80211_tx_info *info, ++ struct ieee80211_sta *sta, ++ struct sk_buff *skb, u8 hw_queue, ++ struct rtl_tcb_desc *ptcb_desc); ++int rtl92du_endpoint_mapping(struct ieee80211_hw *hw); ++u16 rtl92du_mq_to_hwq(__le16 fc, u16 mac80211_queue_index); ++struct sk_buff *rtl92du_tx_aggregate_hdl(struct ieee80211_hw *hw, ++ struct sk_buff_head *list); ++void rtl92du_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb); ++int rtl92du_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb, ++ struct sk_buff *skb); ++ ++#endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0024-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0024-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch new file mode 100644 index 0000000000..e5b6473523 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0024-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch @@ -0,0 +1,282 @@ +From f42c4cb0031563e684a66ea2e21072387d9fcc7f Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:46:51 +0300 +Subject: [PATCH 24/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/rf.{c,h} + +These contain one RF configuration function and some functions related +to dual MAC operation. + +Signed-off-by: Bitterblue Smith +--- + .../wireless/realtek/rtlwifi/rtl8192du/rf.c | 240 ++++++++++++++++++ + .../wireless/realtek/rtlwifi/rtl8192du/rf.h | 11 + + 2 files changed, 251 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c +new file mode 100644 +index 000000000000..044dd65eafd0 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c +@@ -0,0 +1,240 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/phy_common.h" ++#include "phy.h" ++#include "rf.h" ++ ++bool rtl92du_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON; ++ u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0; ++ bool bresult = true; /* true: need to enable BB/RF power */ ++ u32 maskforphyset = 0; ++ u16 val16; ++ u8 u1btmp; ++ ++ rtlhal->during_mac0init_radiob = false; ++ rtlhal->during_mac1init_radioa = false; ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "===>\n"); ++ ++ /* MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write. */ ++ u1btmp = rtl_read_byte(rtlpriv, mac_reg); ++ if (!(u1btmp & mac_on_bit)) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable BB & RF\n"); ++ /* Enable BB and RF power */ ++ ++ maskforphyset = bmac0 ? MAC0_ACCESS_PHY1 : MAC1_ACCESS_PHY0; ++ ++ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset); ++ val16 &= 0xfffc; ++ rtl_write_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset, val16); ++ ++ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset); ++ val16 |= BIT(13) | BIT(0) | BIT(1); ++ rtl_write_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset, val16); ++ } else { ++ /* We think if MAC1 is ON,then radio_a.txt ++ * and radio_b.txt has been load. ++ */ ++ bresult = false; ++ } ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<===\n"); ++ return bresult; ++} ++ ++void rtl92du_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON; ++ u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0; ++ u32 maskforphyset = 0; ++ u8 u1btmp; ++ ++ rtlhal->during_mac0init_radiob = false; ++ rtlhal->during_mac1init_radioa = false; ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); ++ ++ /* check MAC0 enable or not again now, if ++ * enabled, not power down radio A. ++ */ ++ u1btmp = rtl_read_byte(rtlpriv, mac_reg); ++ if (!(u1btmp & mac_on_bit)) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "power down\n"); ++ /* power down RF radio A according to YuNan's advice. */ ++ maskforphyset = bmac0 ? MAC0_ACCESS_PHY1 : MAC1_ACCESS_PHY0; ++ rtl_write_dword(rtlpriv, RFPGA0_XA_LSSIPARAMETER | maskforphyset, ++ 0x00000000); ++ } ++ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); ++} ++ ++bool rtl92du_phy_rf6052_config(struct ieee80211_hw *hw) ++{ ++ bool mac1_initradioa_first = false, mac0_initradiob_first = false; ++ bool need_pwrdown_radioa = false, need_pwrdown_radiob = false; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; ++ struct rtl_phy *rtlphy = &rtlpriv->phy; ++ struct bb_reg_def *pphyreg; ++ bool true_bpath = false; ++ bool rtstatus = true; ++ u32 u4_regvalue = 0; ++ u8 rfpath; ++ ++ if (rtlphy->rf_type == RF_1T1R) ++ rtlphy->num_total_rfpath = 1; ++ else ++ rtlphy->num_total_rfpath = 2; ++ ++ /* Single phy mode: use radio_a radio_b config path_A path_B ++ * separately by MAC0, and MAC1 needn't configure RF; ++ * Dual PHY mode: MAC0 use radio_a config 1st phy path_A, ++ * MAC1 use radio_b config 2nd PHY path_A. ++ * DMDP, MAC0 on G band, MAC1 on A band. ++ */ ++ if (rtlhal->macphymode == DUALMAC_DUALPHY) { ++ if (rtlhal->current_bandtype == BAND_ON_2_4G && ++ rtlhal->interfaceindex == 0) { ++ /* MAC0 needs PHY1 load radio_b.txt. */ ++ if (rtl92du_phy_enable_anotherphy(hw, true)) { ++ rtlphy->num_total_rfpath = 2; ++ mac0_initradiob_first = true; ++ } else { ++ /* We think if MAC1 is ON,then radio_a.txt and ++ * radio_b.txt has been load. ++ */ ++ return rtstatus; ++ } ++ } else if (rtlhal->current_bandtype == BAND_ON_5G && ++ rtlhal->interfaceindex == 1) { ++ /* MAC1 needs PHY0 load radio_a.txt. */ ++ if (rtl92du_phy_enable_anotherphy(hw, false)) { ++ rtlphy->num_total_rfpath = 2; ++ mac1_initradioa_first = true; ++ } else { ++ /* We think if MAC0 is ON, then radio_a.txt and ++ * radio_b.txt has been load. ++ */ ++ return rtstatus; ++ } ++ } else if (rtlhal->interfaceindex == 1) { ++ /* MAC0 enabled, only init radia B. */ ++ true_bpath = true; ++ } ++ } ++ ++ for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { ++ /* Mac1 use PHY0 write */ ++ if (mac1_initradioa_first) { ++ if (rfpath == RF90_PATH_A) { ++ rtlhal->during_mac1init_radioa = true; ++ need_pwrdown_radioa = true; ++ } else if (rfpath == RF90_PATH_B) { ++ rtlhal->during_mac1init_radioa = false; ++ mac1_initradioa_first = false; ++ rfpath = RF90_PATH_A; ++ true_bpath = true; ++ rtlphy->num_total_rfpath = 1; ++ } ++ } else if (mac0_initradiob_first) { ++ /* Mac0 use PHY1 write */ ++ if (rfpath == RF90_PATH_A) ++ rtlhal->during_mac0init_radiob = false; ++ if (rfpath == RF90_PATH_B) { ++ rtlhal->during_mac0init_radiob = true; ++ mac0_initradiob_first = false; ++ need_pwrdown_radiob = true; ++ rfpath = RF90_PATH_A; ++ true_bpath = true; ++ rtlphy->num_total_rfpath = 1; ++ } ++ } ++ ++ pphyreg = &rtlphy->phyreg_def[rfpath]; ++ ++ switch (rfpath) { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, ++ BRFSI_RFENV); ++ break; ++ case RF90_PATH_B: ++ case RF90_PATH_D: ++ u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, ++ BRFSI_RFENV << 16); ++ break; ++ } ++ ++ rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); ++ udelay(1); ++ rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); ++ udelay(1); ++ ++ /* Set bit number of Address and Data for RF register */ ++ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, ++ B3WIREADDRESSLENGTH, 0x0); ++ udelay(1); ++ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); ++ udelay(1); ++ ++ switch (rfpath) { ++ case RF90_PATH_A: ++ if (true_bpath) ++ rtstatus = rtl92du_phy_config_rf_with_headerfile( ++ hw, radiob_txt, ++ (enum radio_path)rfpath); ++ else ++ rtstatus = rtl92du_phy_config_rf_with_headerfile( ++ hw, radioa_txt, ++ (enum radio_path)rfpath); ++ break; ++ case RF90_PATH_B: ++ rtstatus = ++ rtl92du_phy_config_rf_with_headerfile(hw, radiob_txt, ++ (enum radio_path)rfpath); ++ break; ++ case RF90_PATH_C: ++ break; ++ case RF90_PATH_D: ++ break; ++ } ++ ++ switch (rfpath) { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, ++ u4_regvalue); ++ break; ++ case RF90_PATH_B: ++ case RF90_PATH_D: ++ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, ++ u4_regvalue); ++ break; ++ } ++ ++ if (!rtstatus) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, ++ "Radio[%d] Fail!!\n", rfpath); ++ return rtstatus; ++ } ++ } ++ ++ /* check MAC0 enable or not again, if enabled, ++ * not power down radio A. ++ * check MAC1 enable or not again, if enabled, ++ * not power down radio B. ++ */ ++ if (need_pwrdown_radioa) ++ rtl92du_phy_powerdown_anotherphy(hw, false); ++ else if (need_pwrdown_radiob) ++ rtl92du_phy_powerdown_anotherphy(hw, true); ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n"); ++ ++ return rtstatus; ++} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h +new file mode 100644 +index 000000000000..4a92cbdd00c0 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_RF_H__ ++#define __RTL92DU_RF_H__ ++ ++bool rtl92du_phy_rf6052_config(struct ieee80211_hw *hw); ++bool rtl92du_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0); ++void rtl92du_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0); ++ ++#endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0025-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0025-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch new file mode 100644 index 0000000000..951ad60703 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0025-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch @@ -0,0 +1,139 @@ +From 07d8e12d4523008675013f91d46a8a8d133a41c2 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:47:19 +0300 +Subject: [PATCH 25/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/fw.{c,h} + and rtl8192du/led.{c,h} + +fw.c contains a function for loading the firmware. +led.c contains a function for controlling the LED. + +Signed-off-by: Bitterblue Smith +--- + .../wireless/realtek/rtlwifi/rtl8192du/fw.c | 63 +++++++++++++++++++ + .../wireless/realtek/rtlwifi/rtl8192du/fw.h | 9 +++ + .../wireless/realtek/rtlwifi/rtl8192du/led.c | 10 +++ + .../wireless/realtek/rtlwifi/rtl8192du/led.h | 9 +++ + 4 files changed, 91 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c +new file mode 100644 +index 000000000000..f74e4e84fe39 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c +@@ -0,0 +1,63 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/fw_common.h" ++#include "fw.h" ++ ++int rtl92du_download_fw(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ enum version_8192d version = rtlhal->version; ++ u8 *pfwheader; ++ u8 *pfwdata; ++ u32 fwsize; ++ int err; ++ ++ if (rtlpriv->max_fw_size == 0 || !rtlhal->pfirmware) ++ return 1; ++ ++ fwsize = rtlhal->fwsize; ++ pfwheader = rtlhal->pfirmware; ++ pfwdata = rtlhal->pfirmware; ++ rtlhal->fw_version = (u16)GET_FIRMWARE_HDR_VERSION(pfwheader); ++ rtlhal->fw_subversion = (u16)GET_FIRMWARE_HDR_SUB_VER(pfwheader); ++ ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "FirmwareVersion(%d), FirmwareSubVersion(%d), Signature(%#x)\n", ++ rtlhal->fw_version, rtlhal->fw_subversion, ++ GET_FIRMWARE_HDR_SIGNATURE(pfwheader)); ++ ++ if (IS_FW_HEADER_EXIST(pfwheader)) { ++ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, ++ "Shift 32 bytes for FW header!!\n"); ++ pfwdata = pfwdata + 32; ++ fwsize = fwsize - 32; ++ } ++ ++ if (rtl92d_is_fw_downloaded(rtlpriv)) ++ goto exit; ++ ++ /* If 8051 is running in RAM code, driver should ++ * inform Fw to reset by itself, or it will cause ++ * download Fw fail. ++ */ ++ if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) { ++ rtl92d_firmware_selfreset(hw); ++ rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); ++ } ++ ++ rtl92d_enable_fw_download(hw, true); ++ rtl92d_write_fw(hw, version, pfwdata, fwsize); ++ rtl92d_enable_fw_download(hw, false); ++ ++ err = rtl92d_fw_free_to_go(hw); ++ if (err) ++ pr_err("fw is not ready to run!\n"); ++exit: ++ err = rtl92d_fw_init(hw); ++ return err; ++} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h +new file mode 100644 +index 000000000000..7904bfbda4ba +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_FW_H__ ++#define __RTL92DU_FW_H__ ++ ++int rtl92du_download_fw(struct ieee80211_hw *hw); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c +new file mode 100644 +index 000000000000..6c12dfbd6367 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c +@@ -0,0 +1,10 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "led.h" ++ ++void rtl92du_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction) ++{ ++ /* The hardware has control. */ ++} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h +new file mode 100644 +index 000000000000..d7ebc8afcc7b +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_LED_H__ ++#define __RTL92DU_LED_H__ ++ ++void rtl92du_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction); ++ ++#endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0026-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0026-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch new file mode 100644 index 0000000000..a5317f7002 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0026-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch @@ -0,0 +1,161 @@ +From e4592b803eb8ff3eda15c030906cc33226cc794e Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:47:40 +0300 +Subject: [PATCH 26/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/dm.{c,h} + +These contain functions related to the dynamic mechanism, which runs +every two seconds to adjust to changes in the environment. + +Signed-off-by: Bitterblue Smith +--- + .../wireless/realtek/rtlwifi/rtl8192du/dm.c | 120 ++++++++++++++++++ + .../wireless/realtek/rtlwifi/rtl8192du/dm.h | 10 ++ + 2 files changed, 130 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c +new file mode 100644 +index 000000000000..dd57707a9184 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c +@@ -0,0 +1,120 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../core.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/dm_common.h" ++#include "../rtl8192d/fw_common.h" ++#include "dm.h" ++ ++static void rtl92du_dm_init_1r_cca(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct ps_t *dm_pstable = &rtlpriv->dm_pstable; ++ ++ dm_pstable->pre_ccastate = CCA_MAX; ++ dm_pstable->cur_ccasate = CCA_MAX; ++} ++ ++static void rtl92du_dm_1r_cca(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct ps_t *dm_pstable = &rtlpriv->dm_pstable; ++ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); ++ int pwdb = rtlpriv->dm_digtable.min_undec_pwdb_for_dm; ++ ++ if (rtlhal->macphymode != SINGLEMAC_SINGLEPHY || ++ rtlhal->current_bandtype != BAND_ON_5G) ++ return; ++ ++ if (pwdb != 0) { ++ if (dm_pstable->pre_ccastate == CCA_2R || ++ dm_pstable->pre_ccastate == CCA_MAX) ++ dm_pstable->cur_ccasate = (pwdb >= 35) ? CCA_1R : CCA_2R; ++ else ++ dm_pstable->cur_ccasate = (pwdb <= 30) ? CCA_2R : CCA_1R; ++ } else { ++ dm_pstable->cur_ccasate = CCA_MAX; ++ } ++ ++ if (dm_pstable->pre_ccastate == dm_pstable->cur_ccasate) ++ return; ++ ++ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_TRACE, ++ "Old CCA state: %d new CCA state: %d\n", ++ dm_pstable->pre_ccastate, dm_pstable->cur_ccasate); ++ ++ if (dm_pstable->cur_ccasate == CCA_1R) { ++ if (rtlpriv->phy.rf_type == RF_2T2R) ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x13); ++ else /* Is this branch reachable? */ ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); ++ } else { /* CCA_2R or CCA_MAX */ ++ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); ++ } ++} ++ ++static void rtl92du_dm_pwdb_monitor(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ const u32 max_macid = 32; ++ u32 temp; ++ ++ /* AP & ADHOC & MESH will return tmp */ ++ if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) ++ return; ++ ++ /* Indicate Rx signal strength to FW. */ ++ if (rtlpriv->dm.useramask) { ++ temp = rtlpriv->dm.undec_sm_pwdb << 16; ++ temp |= max_macid << 8; ++ ++ rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *)(&temp)); ++ } else { ++ rtl_write_byte(rtlpriv, 0x4fe, (u8)rtlpriv->dm.undec_sm_pwdb); ++ } ++} ++ ++void rtl92du_dm_init(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; ++ rtl_dm_diginit(hw, 0x20); ++ rtlpriv->dm_digtable.rx_gain_max = DM_DIG_FA_UPPER; ++ rtlpriv->dm_digtable.rx_gain_min = DM_DIG_FA_LOWER; ++ rtl92d_dm_init_edca_turbo(hw); ++ rtl92du_dm_init_1r_cca(hw); ++ rtl92d_dm_init_rate_adaptive_mask(hw); ++ rtl92d_dm_initialize_txpower_tracking(hw); ++} ++ ++void rtl92du_dm_watchdog(struct ieee80211_hw *hw) ++{ ++ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); ++ bool fw_current_inpsmode = false; ++ bool fwps_awake = true; ++ ++ /* 1. RF is OFF. (No need to do DM.) ++ * 2. Fw is under power saving mode for FwLPS. ++ * (Prevent from SW/FW I/O racing.) ++ * 3. IPS workitem is scheduled. (Prevent from IPS sequence ++ * to be swapped with DM. ++ * 4. RFChangeInProgress is TRUE. ++ * (Prevent from broken by IPS/HW/SW Rf off.) ++ */ ++ ++ if (ppsc->rfpwr_state != ERFON || fw_current_inpsmode || ++ !fwps_awake || ppsc->rfchange_inprogress) ++ return; ++ ++ rtl92du_dm_pwdb_monitor(hw); ++ rtl92d_dm_false_alarm_counter_statistics(hw); ++ rtl92d_dm_find_minimum_rssi(hw); ++ rtl92d_dm_dig(hw); ++ rtl92d_dm_check_txpower_tracking_thermal_meter(hw); ++ rtl92d_dm_check_edca_turbo(hw); ++ rtl92du_dm_1r_cca(hw); ++} +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h +new file mode 100644 +index 000000000000..2f283bf1e4d8 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#ifndef __RTL92DU_DM_H__ ++#define __RTL92DU_DM_H__ ++ ++void rtl92du_dm_init(struct ieee80211_hw *hw); ++void rtl92du_dm_watchdog(struct ieee80211_hw *hw); ++ ++#endif +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0027-FROMGIT-6.11-wifi-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0027-FROMGIT-6.11-wifi-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch new file mode 100644 index 0000000000..1bc1efe00a --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0027-FROMGIT-6.11-wifi-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch @@ -0,0 +1,106 @@ +From c791ad6e48ba58f4473b899ba7bf2de1d1536d17 Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:48:02 +0300 +Subject: [PATCH 27/69] FROMGIT(6.11): wifi: rtlwifi: Constify + rtl_hal_cfg.{ops,usb_interface_cfg} and rtl_priv.cfg + +This allows the drivers to declare the structs rtl_hal_cfg, rtl_hal_ops, +and rtl_hal_usbint_cfg as const. + +Signed-off-by: Bitterblue Smith +--- + drivers/net/wireless/realtek/rtlwifi/base.c | 2 +- + drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c | 3 +-- + drivers/net/wireless/realtek/rtlwifi/usb.c | 2 +- + drivers/net/wireless/realtek/rtlwifi/usb.h | 2 +- + drivers/net/wireless/realtek/rtlwifi/wifi.h | 6 +++--- + 5 files changed, 7 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtlwifi/base.c b/drivers/net/wireless/realtek/rtlwifi/base.c +index 1a8d715b7c07..aab4605de9c4 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/base.c ++++ b/drivers/net/wireless/realtek/rtlwifi/base.c +@@ -2272,7 +2272,7 @@ static void rtl_c2h_content_parsing(struct ieee80211_hw *hw, + struct sk_buff *skb) + { + struct rtl_priv *rtlpriv = rtl_priv(hw); +- struct rtl_hal_ops *hal_ops = rtlpriv->cfg->ops; ++ const struct rtl_hal_ops *hal_ops = rtlpriv->cfg->ops; + const struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; + u8 cmd_id, cmd_len; + u8 *cmd_buf = NULL; +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c +index 48be7e346efc..c9b9e2bc90cc 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c +@@ -53,8 +53,6 @@ static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw) + } else { + fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; + } +- /* provide name of alternative file */ +- rtlpriv->cfg->alt_fw_name = "rtlwifi/rtl8192cufw.bin"; + pr_info("Loading firmware %s\n", fw_name); + rtlpriv->max_fw_size = 0x4000; + err = request_firmware_nowait(THIS_MODULE, 1, +@@ -160,6 +158,7 @@ static struct rtl_hal_usbint_cfg rtl92cu_interface_cfg = { + + static struct rtl_hal_cfg rtl92cu_hal_cfg = { + .name = "rtl92c_usb", ++ .alt_fw_name = "rtlwifi/rtl8192cufw.bin", + .ops = &rtl8192cu_hal_ops, + .mod_params = &rtl92cu_mod_params, + .usb_interface_cfg = &rtl92cu_interface_cfg, +diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c +index 2ea72d9e3957..b6d300bec1e9 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/usb.c ++++ b/drivers/net/wireless/realtek/rtlwifi/usb.c +@@ -937,7 +937,7 @@ static const struct rtl_intf_ops rtl_usb_ops = { + + int rtl_usb_probe(struct usb_interface *intf, + const struct usb_device_id *id, +- struct rtl_hal_cfg *rtl_hal_cfg) ++ const struct rtl_hal_cfg *rtl_hal_cfg) + { + int err; + struct ieee80211_hw *hw = NULL; +diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.h b/drivers/net/wireless/realtek/rtlwifi/usb.h +index 12529afc0510..b66d6f9ae564 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/usb.h ++++ b/drivers/net/wireless/realtek/rtlwifi/usb.h +@@ -136,7 +136,7 @@ struct rtl_usb_priv { + + int rtl_usb_probe(struct usb_interface *intf, + const struct usb_device_id *id, +- struct rtl_hal_cfg *rtl92cu_hal_cfg); ++ const struct rtl_hal_cfg *rtl92cu_hal_cfg); + void rtl_usb_disconnect(struct usb_interface *intf); + int rtl_usb_suspend(struct usb_interface *pusb_intf, pm_message_t message); + int rtl_usb_resume(struct usb_interface *pusb_intf); +diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h +index 2e88359ba917..940df771a764 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/wifi.h ++++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h +@@ -2383,9 +2383,9 @@ struct rtl_hal_cfg { + bool write_readback; + char *name; + char *alt_fw_name; +- struct rtl_hal_ops *ops; ++ const struct rtl_hal_ops *ops; + struct rtl_mod_params *mod_params; +- struct rtl_hal_usbint_cfg *usb_interface_cfg; ++ const struct rtl_hal_usbint_cfg *usb_interface_cfg; + enum rtl_spec_ver spec_ver; + + /*this map used for some registers or vars +@@ -2734,7 +2734,7 @@ struct rtl_priv { + /* hal_cfg : for diff cards + * intf_ops : for diff interrface usb/pcie + */ +- struct rtl_hal_cfg *cfg; ++ const struct rtl_hal_cfg *cfg; + const struct rtl_intf_ops *intf_ops; + + /* this var will be set by set_bit, +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0027-FROMLIST-v1-drm-meson-improve-encoder-probe-initiali.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0027-FROMLIST-v1-drm-meson-improve-encoder-probe-initiali.patch deleted file mode 100644 index ccf146549e..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0027-FROMLIST-v1-drm-meson-improve-encoder-probe-initiali.patch +++ /dev/null @@ -1,262 +0,0 @@ -From 6fd27cae52fb7b81a1a00822cd1e378ebb3de32b Mon Sep 17 00:00:00 2001 -From: Martin Blumenstingl -Date: Sun, 18 Feb 2024 18:50:35 +0100 -Subject: [PATCH 27/53] FROMLIST(v1): drm/meson: improve encoder probe / - initialization error handling - -Rename meson_encoder_{cvbs,dsi,hdmi}_init() to -meson_encoder_{cvbs,dsi,hdmi}_probe() so it's clear that these functions -are used at probe time during driver initialization. Also switch all -error prints inside those functions to use dev_err_probe() for -consistency. - -This makes the code more straight forward to read and makes the error -prints within those functions consistent (by logging all -EPROBE_DEFER -with dev_dbg(), while actual errors are logged with dev_err() and get -the error value printed). - -Signed-off-by: Martin Blumenstingl -Reviewed-by: Neil Armstrong ---- - drivers/gpu/drm/meson/meson_drv.c | 6 +++--- - drivers/gpu/drm/meson/meson_encoder_cvbs.c | 24 ++++++++++------------ - drivers/gpu/drm/meson/meson_encoder_cvbs.h | 2 +- - drivers/gpu/drm/meson/meson_encoder_dsi.c | 23 +++++++++------------ - drivers/gpu/drm/meson/meson_encoder_dsi.h | 2 +- - drivers/gpu/drm/meson/meson_encoder_hdmi.c | 15 +++++++------- - drivers/gpu/drm/meson/meson_encoder_hdmi.h | 2 +- - 7 files changed, 35 insertions(+), 39 deletions(-) - -diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c -index cb674966e9ac..17a5cca007e2 100644 ---- a/drivers/gpu/drm/meson/meson_drv.c -+++ b/drivers/gpu/drm/meson/meson_drv.c -@@ -312,7 +312,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - - /* Encoder Initialization */ - -- ret = meson_encoder_cvbs_init(priv); -+ ret = meson_encoder_cvbs_probe(priv); - if (ret) - goto exit_afbcd; - -@@ -326,12 +326,12 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - } - } - -- ret = meson_encoder_hdmi_init(priv); -+ ret = meson_encoder_hdmi_probe(priv); - if (ret) - goto exit_afbcd; - - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -- ret = meson_encoder_dsi_init(priv); -+ ret = meson_encoder_dsi_probe(priv); - if (ret) - goto exit_afbcd; - } -diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c -index 3407450435e2..d1191de855d9 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c -+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c -@@ -219,7 +219,7 @@ static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = { - .atomic_reset = drm_atomic_helper_bridge_reset, - }; - --int meson_encoder_cvbs_init(struct meson_drm *priv) -+int meson_encoder_cvbs_probe(struct meson_drm *priv) - { - struct drm_device *drm = priv->drm; - struct meson_encoder_cvbs *meson_encoder_cvbs; -@@ -240,10 +240,9 @@ int meson_encoder_cvbs_init(struct meson_drm *priv) - - meson_encoder_cvbs->next_bridge = of_drm_find_bridge(remote); - of_node_put(remote); -- if (!meson_encoder_cvbs->next_bridge) { -- dev_err(priv->dev, "Failed to find CVBS Connector bridge\n"); -- return -EPROBE_DEFER; -- } -+ if (!meson_encoder_cvbs->next_bridge) -+ return dev_err_probe(priv->dev, -EPROBE_DEFER, -+ "Failed to find CVBS Connector bridge\n"); - - /* CVBS Encoder Bridge */ - meson_encoder_cvbs->bridge.funcs = &meson_encoder_cvbs_bridge_funcs; -@@ -259,10 +258,9 @@ int meson_encoder_cvbs_init(struct meson_drm *priv) - /* Encoder */ - ret = drm_simple_encoder_init(priv->drm, &meson_encoder_cvbs->encoder, - DRM_MODE_ENCODER_TVDAC); -- if (ret) { -- dev_err(priv->dev, "Failed to init CVBS encoder: %d\n", ret); -- return ret; -- } -+ if (ret) -+ return dev_err_probe(priv->dev, ret, -+ "Failed to init CVBS encoder\n"); - - meson_encoder_cvbs->encoder.possible_crtcs = BIT(0); - -@@ -276,10 +274,10 @@ int meson_encoder_cvbs_init(struct meson_drm *priv) - - /* Initialize & attach Bridge Connector */ - connector = drm_bridge_connector_init(priv->drm, &meson_encoder_cvbs->encoder); -- if (IS_ERR(connector)) { -- dev_err(priv->dev, "Unable to create CVBS bridge connector\n"); -- return PTR_ERR(connector); -- } -+ if (IS_ERR(connector)) -+ return dev_err_probe(priv->dev, PTR_ERR(connector), -+ "Unable to create CVBS bridge connector\n"); -+ - drm_connector_attach_encoder(connector, &meson_encoder_cvbs->encoder); - - priv->encoders[MESON_ENC_CVBS] = meson_encoder_cvbs; -diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.h b/drivers/gpu/drm/meson/meson_encoder_cvbs.h -index 09710fec3c66..7b7bc85c03f7 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_cvbs.h -+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.h -@@ -24,7 +24,7 @@ struct meson_cvbs_mode { - /* Modes supported by the CVBS output */ - extern struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT]; - --int meson_encoder_cvbs_init(struct meson_drm *priv); -+int meson_encoder_cvbs_probe(struct meson_drm *priv); - void meson_encoder_cvbs_remove(struct meson_drm *priv); - - #endif /* __MESON_VENC_CVBS_H */ -diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c -index 311b91630fbe..7816902f5907 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_dsi.c -+++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c -@@ -100,7 +100,7 @@ static const struct drm_bridge_funcs meson_encoder_dsi_bridge_funcs = { - .atomic_reset = drm_atomic_helper_bridge_reset, - }; - --int meson_encoder_dsi_init(struct meson_drm *priv) -+int meson_encoder_dsi_probe(struct meson_drm *priv) - { - struct meson_encoder_dsi *meson_encoder_dsi; - struct device_node *remote; -@@ -118,10 +118,9 @@ int meson_encoder_dsi_init(struct meson_drm *priv) - } - - meson_encoder_dsi->next_bridge = of_drm_find_bridge(remote); -- if (!meson_encoder_dsi->next_bridge) { -- dev_dbg(priv->dev, "Failed to find DSI transceiver bridge\n"); -- return -EPROBE_DEFER; -- } -+ if (!meson_encoder_dsi->next_bridge) -+ return dev_err_probe(priv->dev, -EPROBE_DEFER, -+ "Failed to find DSI transceiver bridge\n"); - - /* DSI Encoder Bridge */ - meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs; -@@ -135,19 +134,17 @@ int meson_encoder_dsi_init(struct meson_drm *priv) - /* Encoder */ - ret = drm_simple_encoder_init(priv->drm, &meson_encoder_dsi->encoder, - DRM_MODE_ENCODER_DSI); -- if (ret) { -- dev_err(priv->dev, "Failed to init DSI encoder: %d\n", ret); -- return ret; -- } -+ if (ret) -+ return dev_err_probe(priv->dev, ret, -+ "Failed to init DSI encoder\n"); - - meson_encoder_dsi->encoder.possible_crtcs = BIT(0); - - /* Attach DSI Encoder Bridge to Encoder */ - ret = drm_bridge_attach(&meson_encoder_dsi->encoder, &meson_encoder_dsi->bridge, NULL, 0); -- if (ret) { -- dev_err(priv->dev, "Failed to attach bridge: %d\n", ret); -- return ret; -- } -+ if (ret) -+ return dev_err_probe(priv->dev, ret, -+ "Failed to attach bridge\n"); - - /* - * We should have now in place: -diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.h b/drivers/gpu/drm/meson/meson_encoder_dsi.h -index 9277d7015193..85d5b61805f2 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_dsi.h -+++ b/drivers/gpu/drm/meson/meson_encoder_dsi.h -@@ -7,7 +7,7 @@ - #ifndef __MESON_ENCODER_DSI_H - #define __MESON_ENCODER_DSI_H - --int meson_encoder_dsi_init(struct meson_drm *priv); -+int meson_encoder_dsi_probe(struct meson_drm *priv); - void meson_encoder_dsi_remove(struct meson_drm *priv); - - #endif /* __MESON_ENCODER_DSI_H */ -diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c -index c4686568c9ca..22e07847a9a7 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c -+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c -@@ -354,7 +354,7 @@ static const struct drm_bridge_funcs meson_encoder_hdmi_bridge_funcs = { - .atomic_reset = drm_atomic_helper_bridge_reset, - }; - --int meson_encoder_hdmi_init(struct meson_drm *priv) -+int meson_encoder_hdmi_probe(struct meson_drm *priv) - { - struct meson_encoder_hdmi *meson_encoder_hdmi; - struct platform_device *pdev; -@@ -374,8 +374,8 @@ int meson_encoder_hdmi_init(struct meson_drm *priv) - - meson_encoder_hdmi->next_bridge = of_drm_find_bridge(remote); - if (!meson_encoder_hdmi->next_bridge) { -- dev_err(priv->dev, "Failed to find HDMI transceiver bridge\n"); -- ret = -EPROBE_DEFER; -+ ret = dev_err_probe(priv->dev, -EPROBE_DEFER, -+ "Failed to find HDMI transceiver bridge\n"); - goto err_put_node; - } - -@@ -393,7 +393,7 @@ int meson_encoder_hdmi_init(struct meson_drm *priv) - ret = drm_simple_encoder_init(priv->drm, &meson_encoder_hdmi->encoder, - DRM_MODE_ENCODER_TMDS); - if (ret) { -- dev_err(priv->dev, "Failed to init HDMI encoder: %d\n", ret); -+ dev_err_probe(priv->dev, ret, "Failed to init HDMI encoder\n"); - goto err_put_node; - } - -@@ -403,7 +403,7 @@ int meson_encoder_hdmi_init(struct meson_drm *priv) - ret = drm_bridge_attach(&meson_encoder_hdmi->encoder, &meson_encoder_hdmi->bridge, NULL, - DRM_BRIDGE_ATTACH_NO_CONNECTOR); - if (ret) { -- dev_err(priv->dev, "Failed to attach bridge: %d\n", ret); -+ dev_err_probe(priv->dev, ret, "Failed to attach bridge\n"); - goto err_put_node; - } - -@@ -411,8 +411,9 @@ int meson_encoder_hdmi_init(struct meson_drm *priv) - meson_encoder_hdmi->connector = drm_bridge_connector_init(priv->drm, - &meson_encoder_hdmi->encoder); - if (IS_ERR(meson_encoder_hdmi->connector)) { -- dev_err(priv->dev, "Unable to create HDMI bridge connector\n"); -- ret = PTR_ERR(meson_encoder_hdmi->connector); -+ ret = dev_err_probe(priv->dev, -+ PTR_ERR(meson_encoder_hdmi->connector), -+ "Unable to create HDMI bridge connector\n"); - goto err_put_node; - } - drm_connector_attach_encoder(meson_encoder_hdmi->connector, -diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.h b/drivers/gpu/drm/meson/meson_encoder_hdmi.h -index a6cd38eb5f71..fd5485875db8 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_hdmi.h -+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.h -@@ -7,7 +7,7 @@ - #ifndef __MESON_ENCODER_HDMI_H - #define __MESON_ENCODER_HDMI_H - --int meson_encoder_hdmi_init(struct meson_drm *priv); -+int meson_encoder_hdmi_probe(struct meson_drm *priv); - void meson_encoder_hdmi_remove(struct meson_drm *priv); - - #endif /* __MESON_ENCODER_HDMI_H */ --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0028-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0028-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch new file mode 100644 index 0000000000..963d691ae7 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0028-FROMGIT-6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch @@ -0,0 +1,417 @@ +From 11fc9ecc1d73fd506a3bd359bf3f8b9a94ca59df Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:48:32 +0300 +Subject: [PATCH 28/69] FROMGIT(6.11): wifi: rtlwifi: Add rtl8192du/sw.c + +This contains the new module's entry point. + +Signed-off-by: Bitterblue Smith +--- + .../wireless/realtek/rtlwifi/rtl8192du/sw.c | 395 ++++++++++++++++++ + 1 file changed, 395 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c + +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c +new file mode 100644 +index 000000000000..d069a81ac617 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c +@@ -0,0 +1,395 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright(c) 2024 Realtek Corporation.*/ ++ ++#include "../wifi.h" ++#include "../core.h" ++#include "../usb.h" ++#include "../base.h" ++#include "../rtl8192d/reg.h" ++#include "../rtl8192d/def.h" ++#include "../rtl8192d/fw_common.h" ++#include "../rtl8192d/hw_common.h" ++#include "../rtl8192d/phy_common.h" ++#include "../rtl8192d/trx_common.h" ++#include "phy.h" ++#include "dm.h" ++#include "hw.h" ++#include "trx.h" ++#include "led.h" ++ ++#include ++ ++static struct usb_interface *rtl92du_get_other_intf(struct ieee80211_hw *hw) ++{ ++ struct usb_interface *intf; ++ struct usb_device *udev; ++ u8 other_interfaceindex; ++ ++ /* See SET_IEEE80211_DEV(hw, &intf->dev); in usb.c */ ++ intf = container_of_const(wiphy_dev(hw->wiphy), struct usb_interface, dev); ++ ++ if (intf->altsetting[0].desc.bInterfaceNumber == 0) ++ other_interfaceindex = 1; ++ else ++ other_interfaceindex = 0; ++ ++ udev = interface_to_usbdev(intf); ++ ++ return usb_ifnum_to_if(udev, other_interfaceindex); ++} ++ ++static int rtl92du_init_shared_data(struct ieee80211_hw *hw) ++{ ++ struct usb_interface *other_intf = rtl92du_get_other_intf(hw); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ struct rtl_priv *other_rtlpriv = NULL; ++ struct ieee80211_hw *other_hw = NULL; ++ ++ if (other_intf) ++ other_hw = usb_get_intfdata(other_intf); ++ ++ if (other_hw) { ++ /* The other interface was already probed. */ ++ other_rtlpriv = rtl_priv(other_hw); ++ rtlpriv->curveindex_2g = other_rtlpriv->curveindex_2g; ++ rtlpriv->curveindex_5g = other_rtlpriv->curveindex_5g; ++ rtlpriv->mutex_for_power_on_off = other_rtlpriv->mutex_for_power_on_off; ++ rtlpriv->mutex_for_hw_init = other_rtlpriv->mutex_for_hw_init; ++ ++ if (!rtlpriv->curveindex_2g || !rtlpriv->curveindex_5g || ++ !rtlpriv->mutex_for_power_on_off || !rtlpriv->mutex_for_hw_init) ++ return -ENOMEM; ++ ++ return 0; ++ } ++ ++ /* The other interface doesn't exist or was not probed yet. */ ++ rtlpriv->curveindex_2g = kcalloc(TARGET_CHNL_NUM_2G, ++ sizeof(*rtlpriv->curveindex_2g), ++ GFP_KERNEL); ++ rtlpriv->curveindex_5g = kcalloc(TARGET_CHNL_NUM_5G, ++ sizeof(*rtlpriv->curveindex_5g), ++ GFP_KERNEL); ++ rtlpriv->mutex_for_power_on_off = ++ kzalloc(sizeof(*rtlpriv->mutex_for_power_on_off), GFP_KERNEL); ++ rtlpriv->mutex_for_hw_init = ++ kzalloc(sizeof(*rtlpriv->mutex_for_hw_init), GFP_KERNEL); ++ ++ if (!rtlpriv->curveindex_2g || !rtlpriv->curveindex_5g || ++ !rtlpriv->mutex_for_power_on_off || !rtlpriv->mutex_for_hw_init) { ++ kfree(rtlpriv->curveindex_2g); ++ kfree(rtlpriv->curveindex_5g); ++ kfree(rtlpriv->mutex_for_power_on_off); ++ kfree(rtlpriv->mutex_for_hw_init); ++ rtlpriv->curveindex_2g = NULL; ++ rtlpriv->curveindex_5g = NULL; ++ rtlpriv->mutex_for_power_on_off = NULL; ++ rtlpriv->mutex_for_hw_init = NULL; ++ return -ENOMEM; ++ } ++ ++ mutex_init(rtlpriv->mutex_for_power_on_off); ++ mutex_init(rtlpriv->mutex_for_hw_init); ++ ++ return 0; ++} ++ ++static void rtl92du_deinit_shared_data(struct ieee80211_hw *hw) ++{ ++ struct usb_interface *other_intf = rtl92du_get_other_intf(hw); ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ if (!other_intf || !usb_get_intfdata(other_intf)) { ++ /* The other interface doesn't exist or was already disconnected. */ ++ kfree(rtlpriv->curveindex_2g); ++ kfree(rtlpriv->curveindex_5g); ++ if (rtlpriv->mutex_for_power_on_off) ++ mutex_destroy(rtlpriv->mutex_for_power_on_off); ++ if (rtlpriv->mutex_for_hw_init) ++ mutex_destroy(rtlpriv->mutex_for_hw_init); ++ kfree(rtlpriv->mutex_for_power_on_off); ++ kfree(rtlpriv->mutex_for_hw_init); ++ } ++} ++ ++static int rtl92du_init_sw_vars(struct ieee80211_hw *hw) ++{ ++ const char *fw_name = "rtlwifi/rtl8192dufw.bin"; ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ int err; ++ ++ err = rtl92du_init_shared_data(hw); ++ if (err) ++ return err; ++ ++ rtlpriv->dm.dm_initialgain_enable = true; ++ rtlpriv->dm.dm_flag = 0; ++ rtlpriv->dm.disable_framebursting = false; ++ rtlpriv->dm.thermalvalue = 0; ++ rtlpriv->dm.useramask = true; ++ ++ /* dual mac */ ++ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) ++ rtlpriv->phy.current_channel = 36; ++ else ++ rtlpriv->phy.current_channel = 1; ++ ++ if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) ++ rtlpriv->rtlhal.disable_amsdu_8k = true; ++ ++ /* for LPS & IPS */ ++ rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; ++ rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; ++ rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; ++ ++ /* for early mode */ ++ rtlpriv->rtlhal.earlymode_enable = false; ++ ++ /* for firmware buf */ ++ rtlpriv->rtlhal.pfirmware = kmalloc(0x8000, GFP_KERNEL); ++ if (!rtlpriv->rtlhal.pfirmware) ++ return -ENOMEM; ++ ++ rtlpriv->max_fw_size = 0x8000; ++ pr_info("Driver for Realtek RTL8192DU WLAN interface\n"); ++ pr_info("Loading firmware file %s\n", fw_name); ++ ++ /* request fw */ ++ err = request_firmware_nowait(THIS_MODULE, 1, fw_name, ++ rtlpriv->io.dev, GFP_KERNEL, hw, ++ rtl_fw_cb); ++ if (err) { ++ pr_err("Failed to request firmware!\n"); ++ kfree(rtlpriv->rtlhal.pfirmware); ++ rtlpriv->rtlhal.pfirmware = NULL; ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void rtl92du_deinit_sw_vars(struct ieee80211_hw *hw) ++{ ++ struct rtl_priv *rtlpriv = rtl_priv(hw); ++ ++ kfree(rtlpriv->rtlhal.pfirmware); ++ rtlpriv->rtlhal.pfirmware = NULL; ++ ++ rtl92du_deinit_shared_data(hw); ++} ++ ++static const struct rtl_hal_ops rtl8192du_hal_ops = { ++ .init_sw_vars = rtl92du_init_sw_vars, ++ .deinit_sw_vars = rtl92du_deinit_sw_vars, ++ .read_chip_version = rtl92du_read_chip_version, ++ .read_eeprom_info = rtl92d_read_eeprom_info, ++ .hw_init = rtl92du_hw_init, ++ .hw_disable = rtl92du_card_disable, ++ .enable_interrupt = rtl92du_enable_interrupt, ++ .disable_interrupt = rtl92du_disable_interrupt, ++ .set_network_type = rtl92du_set_network_type, ++ .set_chk_bssid = rtl92du_set_check_bssid, ++ .set_qos = rtl92d_set_qos, ++ .set_bcn_reg = rtl92du_set_beacon_related_registers, ++ .set_bcn_intv = rtl92du_set_beacon_interval, ++ .update_interrupt_mask = rtl92du_update_interrupt_mask, ++ .get_hw_reg = rtl92du_get_hw_reg, ++ .set_hw_reg = rtl92du_set_hw_reg, ++ .update_rate_tbl = rtl92d_update_hal_rate_tbl, ++ .fill_tx_desc = rtl92du_tx_fill_desc, ++ .query_rx_desc = rtl92d_rx_query_desc, ++ .set_channel_access = rtl92d_update_channel_access_setting, ++ .radio_onoff_checking = rtl92d_gpio_radio_on_off_checking, ++ .set_bw_mode = rtl92du_phy_set_bw_mode, ++ .switch_channel = rtl92du_phy_sw_chnl, ++ .dm_watchdog = rtl92du_dm_watchdog, ++ .scan_operation_backup = rtl_phy_scan_operation_backup, ++ .set_rf_power_state = rtl92du_phy_set_rf_power_state, ++ .led_control = rtl92du_led_control, ++ .set_desc = rtl92d_set_desc, ++ .get_desc = rtl92d_get_desc, ++ .enable_hw_sec = rtl92d_enable_hw_security_config, ++ .set_key = rtl92d_set_key, ++ .get_bbreg = rtl92du_phy_query_bb_reg, ++ .set_bbreg = rtl92du_phy_set_bb_reg, ++ .get_rfreg = rtl92d_phy_query_rf_reg, ++ .set_rfreg = rtl92d_phy_set_rf_reg, ++ .linked_set_reg = rtl92du_linked_set_reg, ++ .fill_h2c_cmd = rtl92d_fill_h2c_cmd, ++ .get_btc_status = rtl_btc_status_false, ++ .phy_iq_calibrate = rtl92du_phy_iq_calibrate, ++ .phy_lc_calibrate = rtl92du_phy_lc_calibrate, ++}; ++ ++static struct rtl_mod_params rtl92du_mod_params = { ++ .sw_crypto = false, ++ .inactiveps = false, ++ .swctrl_lps = false, ++ .debug_level = 0, ++ .debug_mask = 0, ++}; ++ ++static const struct rtl_hal_usbint_cfg rtl92du_interface_cfg = { ++ /* rx */ ++ .rx_urb_num = 8, ++ .rx_max_size = 15360, ++ .usb_rx_hdl = NULL, ++ .usb_rx_segregate_hdl = NULL, ++ /* tx */ ++ .usb_tx_cleanup = rtl92du_tx_cleanup, ++ .usb_tx_post_hdl = rtl92du_tx_post_hdl, ++ .usb_tx_aggregate_hdl = rtl92du_tx_aggregate_hdl, ++ .usb_endpoint_mapping = rtl92du_endpoint_mapping, ++ .usb_mq_to_hwq = rtl92du_mq_to_hwq, ++}; ++ ++static const struct rtl_hal_cfg rtl92du_hal_cfg = { ++ .name = "rtl8192du", ++ .ops = &rtl8192du_hal_ops, ++ .mod_params = &rtl92du_mod_params, ++ .usb_interface_cfg = &rtl92du_interface_cfg, ++ ++ .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, ++ .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, ++ .maps[SYS_CLK] = REG_SYS_CLKR, ++ .maps[MAC_RCR_AM] = RCR_AM, ++ .maps[MAC_RCR_AB] = RCR_AB, ++ .maps[MAC_RCR_ACRC32] = RCR_ACRC32, ++ .maps[MAC_RCR_ACF] = RCR_ACF, ++ .maps[MAC_RCR_AAP] = RCR_AAP, ++ ++ .maps[EFUSE_TEST] = REG_EFUSE_TEST, ++ .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS, ++ .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, ++ .maps[EFUSE_CLK] = 0, /* just for 92se */ ++ .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, ++ .maps[EFUSE_PWC_EV12V] = PWC_EV12V, ++ .maps[EFUSE_FEN_ELDR] = FEN_ELDR, ++ .maps[EFUSE_LOADER_CLK_EN] = 0, ++ .maps[EFUSE_ANA8M] = 0, /* just for 92se */ ++ .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, ++ .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, ++ .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, ++ ++ .maps[RWCAM] = REG_CAMCMD, ++ .maps[WCAMI] = REG_CAMWRITE, ++ .maps[RCAMO] = REG_CAMREAD, ++ .maps[CAMDBG] = REG_CAMDBG, ++ .maps[SECR] = REG_SECCFG, ++ .maps[SEC_CAM_NONE] = CAM_NONE, ++ .maps[SEC_CAM_WEP40] = CAM_WEP40, ++ .maps[SEC_CAM_TKIP] = CAM_TKIP, ++ .maps[SEC_CAM_AES] = CAM_AES, ++ .maps[SEC_CAM_WEP104] = CAM_WEP104, ++ ++ .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, ++ .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, ++ .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, ++ .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, ++ .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, ++ .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, ++ .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, ++ .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, ++ .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, ++ .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, ++ .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, ++ .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, ++ .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, ++ .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, ++ .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, ++ .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, ++ ++ .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, ++ .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, ++ .maps[RTL_IMR_BCNINT] = IMR_BCNINT, ++ .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, ++ .maps[RTL_IMR_RDU] = IMR_RDU, ++ .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, ++ .maps[RTL_IMR_BDOK] = IMR_BDOK, ++ .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, ++ .maps[RTL_IMR_TBDER] = IMR_TBDER, ++ .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, ++ .maps[RTL_IMR_TBDOK] = IMR_TBDOK, ++ .maps[RTL_IMR_BKDOK] = IMR_BKDOK, ++ .maps[RTL_IMR_BEDOK] = IMR_BEDOK, ++ .maps[RTL_IMR_VIDOK] = IMR_VIDOK, ++ .maps[RTL_IMR_VODOK] = IMR_VODOK, ++ .maps[RTL_IMR_ROK] = IMR_ROK, ++ .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), ++ ++ .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M, ++ .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M, ++ .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M, ++ .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M, ++ .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M, ++ .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M, ++ .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M, ++ .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M, ++ .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M, ++ .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M, ++ .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M, ++ .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M, ++ ++ .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7, ++ .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15, ++}; ++ ++module_param_named(swenc, rtl92du_mod_params.sw_crypto, bool, 0444); ++module_param_named(debug_level, rtl92du_mod_params.debug_level, int, 0644); ++module_param_named(ips, rtl92du_mod_params.inactiveps, bool, 0444); ++module_param_named(swlps, rtl92du_mod_params.swctrl_lps, bool, 0444); ++module_param_named(debug_mask, rtl92du_mod_params.debug_mask, ullong, 0644); ++MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); ++MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 0)\n"); ++MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); ++MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)"); ++MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)"); ++ ++#define USB_VENDOR_ID_REALTEK 0x0bda ++ ++static const struct usb_device_id rtl8192d_usb_ids[] = { ++ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8193, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8194, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8111, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x0193, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8171, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0xe194, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x2019, 0xab2c, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x2019, 0xab2d, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x2019, 0x4903, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x2019, 0x4904, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x07b8, 0x8193, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x20f4, 0x664b, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x04dd, 0x954f, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x04dd, 0x96a6, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x050d, 0x110a, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x050d, 0x1105, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x050d, 0x120a, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x1668, 0x8102, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x0930, 0x0a0a, rtl92du_hal_cfg)}, ++ {RTL_USB_DEVICE(0x2001, 0x330c, rtl92du_hal_cfg)}, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(usb, rtl8192d_usb_ids); ++ ++static int rtl8192du_probe(struct usb_interface *intf, ++ const struct usb_device_id *id) ++{ ++ return rtl_usb_probe(intf, id, &rtl92du_hal_cfg); ++} ++ ++static struct usb_driver rtl8192du_driver = { ++ .name = "rtl8192du", ++ .probe = rtl8192du_probe, ++ .disconnect = rtl_usb_disconnect, ++ .id_table = rtl8192d_usb_ids, ++ .disable_hub_initiated_lpm = 1, ++}; ++ ++module_usb_driver(rtl8192du_driver); ++ ++MODULE_AUTHOR("Bitterblue Smith "); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Realtek 8192DU 802.11n Dual Mac USB wireless"); ++MODULE_FIRMWARE("rtlwifi/rtl8192dufw.bin"); +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0028-FROMLIST-v1-drm-meson-vclk-fix-calculation-of-59.94-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0028-FROMLIST-v1-drm-meson-vclk-fix-calculation-of-59.94-.patch deleted file mode 100644 index fe5c85f5c5..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0028-FROMLIST-v1-drm-meson-vclk-fix-calculation-of-59.94-.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 9fa5e4f1d94a0ca01deb5bbe03299e415f0df8c3 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Tue, 9 Jan 2024 16:20:14 +0000 -Subject: [PATCH 28/53] FROMLIST(v1): drm/meson: vclk: fix calculation of 59.94 - fractional rates - -Playing 4K media with 59.94 fractional rate (typically VP9) causes the screen to lose -sync with the following error reported in the system log: - -[ 89.610280] Fatal Error, invalid HDMI vclk freq 593406 - -Modetest shows the following: - -3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407 flags: phsync, pvsync; type: driver -drm calculated value -------------------------------------^ - -Change the fractional rate calculation to stop DIV_ROUND_CLOSEST rounding down which -results in vclk freq failing to match correctly. - -Fixes: e5fab2ec9ca4 ("drm/meson: vclk: add support for YUV420 setup") -Signed-off-by: Christian Hewitt ---- - drivers/gpu/drm/meson/meson_vclk.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c -index 2a82119eb58e..2a942dc6a6dc 100644 ---- a/drivers/gpu/drm/meson/meson_vclk.c -+++ b/drivers/gpu/drm/meson/meson_vclk.c -@@ -790,13 +790,13 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq, - FREQ_1000_1001(params[i].pixel_freq)); - DRM_DEBUG_DRIVER("i = %d phy_freq = %d alt = %d\n", - i, params[i].phy_freq, -- FREQ_1000_1001(params[i].phy_freq/10)*10); -+ FREQ_1000_1001(params[i].phy_freq/1000)*1000); - /* Match strict frequency */ - if (phy_freq == params[i].phy_freq && - vclk_freq == params[i].vclk_freq) - return MODE_OK; - /* Match 1000/1001 variant */ -- if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/10)*10) && -+ if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/1000)*1000) && - vclk_freq == FREQ_1000_1001(params[i].vclk_freq)) - return MODE_OK; - } -@@ -1070,7 +1070,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - - for (freq = 0 ; params[freq].pixel_freq ; ++freq) { - if ((phy_freq == params[freq].phy_freq || -- phy_freq == FREQ_1000_1001(params[freq].phy_freq/10)*10) && -+ phy_freq == FREQ_1000_1001(params[freq].phy_freq/1000)*1000) && - (vclk_freq == params[freq].vclk_freq || - vclk_freq == FREQ_1000_1001(params[freq].vclk_freq))) { - if (vclk_freq != params[freq].vclk_freq) --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0029-FROMGIT-6.11-wifi-rtlwifi-Enable-the-new-rtl8192du-d.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0029-FROMGIT-6.11-wifi-rtlwifi-Enable-the-new-rtl8192du-d.patch new file mode 100644 index 0000000000..c263902e66 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0029-FROMGIT-6.11-wifi-rtlwifi-Enable-the-new-rtl8192du-d.patch @@ -0,0 +1,92 @@ +From da2287b41888e02866f1416caa36c148c5723f8b Mon Sep 17 00:00:00 2001 +From: Bitterblue Smith +Date: Thu, 23 May 2024 17:49:00 +0300 +Subject: [PATCH 29/69] FROMGIT(6.11): wifi: rtlwifi: Enable the new rtl8192du + driver + +The RTL8192DU is an older Wifi 4 dual band chip. It comes in two +flavours: single MAC single PHY (like most Realtek Wifi 4 USB devices), +and dual MAC dual PHY. + +The single MAC single PHY version is 2T2R and can work either in the +2.4 GHz band or the 5 GHz band. + +The dual MAC dual PHY version has two USB interfaces and appears to the +system as two separate 1T1R Wifi devices, one working in the 2.4 GHz +band, the other in the 5 GHz band. + +This was tested only with a single MAC single PHY device, mostly in +station mode. The speeds in the 2.4 GHz band with 20 MHz channel width +are similar to the out-of-tree driver: 85/51 megabits/second. + +Stefan Lippers-Hollmann tested the speed in the 5 GHz band with 40 MHz +channel width: 173/99 megabits/second. + +It was also tested briefly in AP mode. It's emitting beacons and my +phone can connect to it. + +Signed-off-by: Bitterblue Smith +--- + drivers/net/wireless/realtek/rtlwifi/Kconfig | 12 ++++++++++++ + drivers/net/wireless/realtek/rtlwifi/Makefile | 1 + + .../net/wireless/realtek/rtlwifi/rtl8192du/Makefile | 13 +++++++++++++ + 3 files changed, 26 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile + +diff --git a/drivers/net/wireless/realtek/rtlwifi/Kconfig b/drivers/net/wireless/realtek/rtlwifi/Kconfig +index cfe63f7b28d9..1e66c1bf7c8b 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/Kconfig ++++ b/drivers/net/wireless/realtek/rtlwifi/Kconfig +@@ -119,6 +119,18 @@ config RTL8192CU + + If you choose to build it as a module, it will be called rtl8192cu + ++config RTL8192DU ++ tristate "Realtek RTL8192DU USB Wireless Network Adapter" ++ depends on USB ++ select RTLWIFI ++ select RTLWIFI_USB ++ select RTL8192D_COMMON ++ help ++ This is the driver for Realtek RTL8192DU 802.11n USB ++ wireless network adapters. ++ ++ If you choose to build it as a module, it will be called rtl8192du ++ + config RTLWIFI + tristate + select FW_LOADER +diff --git a/drivers/net/wireless/realtek/rtlwifi/Makefile b/drivers/net/wireless/realtek/rtlwifi/Makefile +index 423981b148df..9cf32277c7f1 100644 +--- a/drivers/net/wireless/realtek/rtlwifi/Makefile ++++ b/drivers/net/wireless/realtek/rtlwifi/Makefile +@@ -25,6 +25,7 @@ obj-$(CONFIG_RTL8192CU) += rtl8192cu/ + obj-$(CONFIG_RTL8192SE) += rtl8192se/ + obj-$(CONFIG_RTL8192D_COMMON) += rtl8192d/ + obj-$(CONFIG_RTL8192DE) += rtl8192de/ ++obj-$(CONFIG_RTL8192DU) += rtl8192du/ + obj-$(CONFIG_RTL8723AE) += rtl8723ae/ + obj-$(CONFIG_RTL8723BE) += rtl8723be/ + obj-$(CONFIG_RTL8188EE) += rtl8188ee/ +diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile +new file mode 100644 +index 000000000000..569bfd3d5030 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile +@@ -0,0 +1,13 @@ ++# SPDX-License-Identifier: GPL-2.0 ++rtl8192du-objs := \ ++ dm.o \ ++ fw.o \ ++ hw.o \ ++ led.o \ ++ phy.o \ ++ rf.o \ ++ sw.o \ ++ table.o \ ++ trx.o ++ ++obj-$(CONFIG_RTL8192DU) += rtl8192du.o +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0029-FROMLIST-v1-ASoC-meson-axg-tdm-interface-fix-mclk-se.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0029-FROMLIST-v1-ASoC-meson-axg-tdm-interface-fix-mclk-se.patch deleted file mode 100644 index 5d469047b4..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0029-FROMLIST-v1-ASoC-meson-axg-tdm-interface-fix-mclk-se.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 5cddc22049efb7e7aa5382ce789379c943170187 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 23 Feb 2024 18:51:07 +0100 -Subject: [PATCH 29/53] FROMLIST(v1): ASoC: meson: axg-tdm-interface: fix mclk - setup without mclk-fs - -By default, when mclk-fs is not provided, the tdm-interface driver -requests an MCLK that is 4x the bit clock, SCLK. - -However there is no justification for this: - -* If the codec needs MCLK for its operation, mclk-fs is expected to be set - according to the codec requirements. -* If the codec does not need MCLK the minimum is 2 * SCLK, because this is - minimum the divider between SCLK and MCLK can do. - -Multiplying by 4 may cause problems because the PLL limit may be reached -sooner than it should, so use 2x instead. - -Fixes: d60e4f1e4be5 ("ASoC: meson: add tdm interface driver") -Signed-off-by: Jerome Brunet ---- - sound/soc/meson/axg-tdm-interface.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-interface.c -index 1c3d433cefd2..cd5168e826df 100644 ---- a/sound/soc/meson/axg-tdm-interface.c -+++ b/sound/soc/meson/axg-tdm-interface.c -@@ -264,8 +264,8 @@ static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai, - srate = iface->slots * iface->slot_width * params_rate(params); - - if (!iface->mclk_rate) { -- /* If no specific mclk is requested, default to bit clock * 4 */ -- clk_set_rate(iface->mclk, 4 * srate); -+ /* If no specific mclk is requested, default to bit clock * 2 */ -+ clk_set_rate(iface->mclk, 2 * srate); - } else { - /* Check if we can actually get the bit clock from mclk */ - if (iface->mclk_rate % srate) { --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0030-FROMLIST-v1-ASoC-meson-axg-tdm-interface-add-frame-r.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0030-FROMLIST-v1-ASoC-meson-axg-tdm-interface-add-frame-r.patch deleted file mode 100644 index b9532ab4de..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0030-FROMLIST-v1-ASoC-meson-axg-tdm-interface-add-frame-r.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 69a95e8b2be63812ca0b8e3b59786a21f074cfe9 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 23 Feb 2024 18:51:08 +0100 -Subject: [PATCH 30/53] FROMLIST(v1): ASoC: meson: axg-tdm-interface: add frame - rate constraint - -According to Amlogic datasheets for the SoCs supported by this driver, the -maximum bit clock rate is 100MHz. - -The tdm interface allows the rates listed by the DAI driver, regardless of -the number slots or their width. However, these will impact the bit clock -rate. - -Hitting the 100MHz limit is very unlikely for most use cases but it is -possible. - -For example with 32 slots / 32 bits wide, the maximum rate is no longer -384kHz but ~96kHz. - -Add the constraint accordingly if the component is not already active. -If it is active, the rate is already constrained by the first stream rate. - -Fixes: d60e4f1e4be5 ("ASoC: meson: add tdm interface driver") -Signed-off-by: Jerome Brunet ---- - sound/soc/meson/axg-tdm-interface.c | 25 ++++++++++++++++++------- - 1 file changed, 18 insertions(+), 7 deletions(-) - -diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-interface.c -index cd5168e826df..2cedbce73837 100644 ---- a/sound/soc/meson/axg-tdm-interface.c -+++ b/sound/soc/meson/axg-tdm-interface.c -@@ -12,6 +12,9 @@ - - #include "axg-tdm.h" - -+/* Maximum bit clock frequency according the datasheets */ -+#define MAX_SCLK 100000000 /* Hz */ -+ - enum { - TDM_IFACE_PAD, - TDM_IFACE_LOOPBACK, -@@ -153,19 +156,27 @@ static int axg_tdm_iface_startup(struct snd_pcm_substream *substream, - return -EINVAL; - } - -- /* Apply component wide rate symmetry */ - if (snd_soc_component_active(dai->component)) { -+ /* Apply component wide rate symmetry */ - ret = snd_pcm_hw_constraint_single(substream->runtime, - SNDRV_PCM_HW_PARAM_RATE, - iface->rate); -- if (ret < 0) { -- dev_err(dai->dev, -- "can't set iface rate constraint\n"); -- return ret; -- } -+ -+ } else { -+ /* Limit rate according to the slot number and width */ -+ unsigned int max_rate = -+ MAX_SCLK / (iface->slots * iface->slot_width); -+ ret = snd_pcm_hw_constraint_minmax(substream->runtime, -+ SNDRV_PCM_HW_PARAM_RATE, -+ 0, max_rate); - } - -- return 0; -+ if (ret < 0) -+ dev_err(dai->dev, "can't set iface rate constraint\n"); -+ else -+ ret = 0; -+ -+ return ret; - } - - static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream, --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0013-FROMLIST-v5-dt-bindings-vendor-prefixes-Add-Titan-Mi.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0030-FROMLIST-v5-dt-bindings-vendor-prefixes-Add-Titan-Mi.patch similarity index 83% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0013-FROMLIST-v5-dt-bindings-vendor-prefixes-Add-Titan-Mi.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0030-FROMLIST-v5-dt-bindings-vendor-prefixes-Add-Titan-Mi.patch index 8b1f89b610..3ac63a4e59 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0013-FROMLIST-v5-dt-bindings-vendor-prefixes-Add-Titan-Mi.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0030-FROMLIST-v5-dt-bindings-vendor-prefixes-Add-Titan-Mi.patch @@ -1,7 +1,7 @@ -From 58d3f1f106febd55da1b5e56016fb8e33fde09bd Mon Sep 17 00:00:00 2001 +From e72bd54794e45ae480928111c53b03f178d81998 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 20 Feb 2022 08:23:12 +0000 -Subject: [PATCH 13/53] FROMLIST(v5): dt-bindings: vendor-prefixes: Add Titan +Subject: [PATCH 30/69] FROMLIST(v5): dt-bindings: vendor-prefixes: Add Titan Micro Electronics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -17,10 +17,10 @@ Signed-off-by: Heiner Kallweit 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 1a0dc04f1db4..a3c08f859ab1 100644 +index b97d298b3eb6..3979d9ebb62a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -1427,6 +1427,8 @@ patternProperties: +@@ -1464,6 +1464,8 @@ patternProperties: description: Texas Instruments "^tianma,.*": description: Tianma Micro-electronics Co., Ltd. diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0031-FROMLIST-v1-ASoC-meson-axg-tdm-interface-update-erro.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0031-FROMLIST-v1-ASoC-meson-axg-tdm-interface-update-erro.patch deleted file mode 100644 index 2311277a38..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0031-FROMLIST-v1-ASoC-meson-axg-tdm-interface-update-erro.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 9b3d51967fcfe47d82f280e8030aa3dc5fcc5c02 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 23 Feb 2024 18:51:09 +0100 -Subject: [PATCH 31/53] FROMLIST(v1): ASoC: meson: axg-tdm-interface: update - error format error traces - -ASoC stopped using CBS_CFS and CBM_CFM a few years ago but the traces in -the amlogic tdm interface driver did not follow. - -Update this to match the new format names - -Signed-off-by: Jerome Brunet ---- - sound/soc/meson/axg-tdm-interface.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-interface.c -index 2cedbce73837..bf708717635b 100644 ---- a/sound/soc/meson/axg-tdm-interface.c -+++ b/sound/soc/meson/axg-tdm-interface.c -@@ -133,7 +133,7 @@ static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) - - case SND_SOC_DAIFMT_BP_FC: - case SND_SOC_DAIFMT_BC_FP: -- dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n"); -+ dev_err(dai->dev, "only BP_FP and BC_FC are supported\n"); - fallthrough; - default: - return -EINVAL; --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0014-FROMLIST-v5-dt-bindings-auxdisplay-Add-Titan-Micro-E.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0031-FROMLIST-v5-dt-bindings-auxdisplay-Add-Titan-Micro-E.patch similarity index 95% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0014-FROMLIST-v5-dt-bindings-auxdisplay-Add-Titan-Micro-E.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0031-FROMLIST-v5-dt-bindings-auxdisplay-Add-Titan-Micro-E.patch index 2ae6915799..350d16955a 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0014-FROMLIST-v5-dt-bindings-auxdisplay-Add-Titan-Micro-E.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0031-FROMLIST-v5-dt-bindings-auxdisplay-Add-Titan-Micro-E.patch @@ -1,7 +1,7 @@ -From 24712c83de1ef21e7263f7c3bbe4423068070089 Mon Sep 17 00:00:00 2001 +From 1dd793f369319025118ca526d0fc899cc78eaeae Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 20 Feb 2022 08:24:47 +0000 -Subject: [PATCH 14/53] FROMLIST(v5): dt-bindings: auxdisplay: Add Titan Micro +Subject: [PATCH 31/69] FROMLIST(v5): dt-bindings: auxdisplay: Add Titan Micro Electronics TM1628 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0032-FROMLIST-v1-ASoC-meson-axg-spdifin-use-max-width-for.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0032-FROMLIST-v1-ASoC-meson-axg-spdifin-use-max-width-for.patch deleted file mode 100644 index 9812538b92..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0032-FROMLIST-v1-ASoC-meson-axg-spdifin-use-max-width-for.patch +++ /dev/null @@ -1,47 +0,0 @@ -From b399257ec04a93856fd0f1ebf5b6060dddf6aaed Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 23 Feb 2024 18:51:10 +0100 -Subject: [PATCH 32/53] FROMLIST(v1): ASoC: meson: axg-spdifin: use max width - for rate detection - -Use maximum width between 2 edges to setup spdifin thresholds -and detect the input sample rate. This comes from Amlogic SDK and -seems to be marginally more reliable than minimum width. - -This is done to align with a future eARC support. -No issue was reported with minimum width so far, this is considered -to be an update so no Fixes tag is set. - -Signed-off-by: Jerome Brunet ---- - sound/soc/meson/axg-spdifin.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/sound/soc/meson/axg-spdifin.c b/sound/soc/meson/axg-spdifin.c -index bc2f2849ecfb..e721f579321e 100644 ---- a/sound/soc/meson/axg-spdifin.c -+++ b/sound/soc/meson/axg-spdifin.c -@@ -179,9 +179,9 @@ static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai, - SPDIFIN_CTRL1_BASE_TIMER, - FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000)); - -- /* Threshold based on the minimum width between two edges */ -+ /* Threshold based on the maximum width between two edges */ - regmap_update_bits(priv->map, SPDIFIN_CTRL0, -- SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL); -+ SPDIFIN_CTRL0_WIDTH_SEL, 0); - - /* Calculate the last timer which has no threshold */ - t_next = axg_spdifin_mode_timer(priv, i, rate); -@@ -199,7 +199,7 @@ static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai, - axg_spdifin_write_timer(priv->map, i, t); - - /* Set the threshold value */ -- axg_spdifin_write_threshold(priv->map, i, t + t_next); -+ axg_spdifin_write_threshold(priv->map, i, 3 * (t + t_next)); - - /* Save the current timer for the next threshold calculation */ - t_next = t; --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0015-FROMLIST-v5-docs-ABI-document-tm1628-attribute-displ.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0032-FROMLIST-v5-docs-ABI-document-tm1628-attribute-displ.patch similarity index 89% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0015-FROMLIST-v5-docs-ABI-document-tm1628-attribute-displ.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0032-FROMLIST-v5-docs-ABI-document-tm1628-attribute-displ.patch index f04e8801ec..4d85cd9ed6 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0015-FROMLIST-v5-docs-ABI-document-tm1628-attribute-displ.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0032-FROMLIST-v5-docs-ABI-document-tm1628-attribute-displ.patch @@ -1,7 +1,7 @@ -From 35a48968c689d245bbe3dd2ff5cd9192d3a16e62 Mon Sep 17 00:00:00 2001 +From 77408aa188572b17c585b3f8a2074e2dad8ad2ed Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 20 Feb 2022 08:26:27 +0000 -Subject: [PATCH 15/53] FROMLIST(v5): docs: ABI: document tm1628 attribute +Subject: [PATCH 32/69] FROMLIST(v5): docs: ABI: document tm1628 attribute display-text Document the attribute for reading / writing the text to be displayed on diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0033-FROMLIST-v1-ASoC-meson-axg-fifo-take-continuous-rate.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0033-FROMLIST-v1-ASoC-meson-axg-fifo-take-continuous-rate.patch deleted file mode 100644 index 1348494da3..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0033-FROMLIST-v1-ASoC-meson-axg-fifo-take-continuous-rate.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 453af3a1ee8cea68dfdbdaed7a0a41f4a3743c76 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 23 Feb 2024 18:51:11 +0100 -Subject: [PATCH 33/53] FROMLIST(v1): ASoC: meson: axg-fifo: take continuous - rates - -The rate of the stream does not matter for the fifos of the axg family. -Fifos will just push or pull data to/from the DDR according to consumption -or production of the downstream element, which is the DPCM backend. - -Drop the rate list and allow continuous rates. The lower and upper rate are -set according what is known to work with the different backends - -This allows the PDM input backend to also use continuous rates. - -Signed-off-by: Jerome Brunet ---- - sound/soc/meson/axg-fifo.h | 2 -- - sound/soc/meson/axg-frddr.c | 8 ++++++-- - sound/soc/meson/axg-toddr.c | 8 ++++++-- - 3 files changed, 12 insertions(+), 6 deletions(-) - -diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h -index df528e8cb7c9..a14c31eb06d8 100644 ---- a/sound/soc/meson/axg-fifo.h -+++ b/sound/soc/meson/axg-fifo.h -@@ -21,8 +21,6 @@ struct snd_soc_dai_driver; - struct snd_soc_pcm_runtime; - - #define AXG_FIFO_CH_MAX 128 --#define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \ -- SNDRV_PCM_RATE_8000_384000) - #define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ - SNDRV_PCM_FMTBIT_S16_LE | \ - SNDRV_PCM_FMTBIT_S20_LE | \ -diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c -index 8c166a5f338c..98140f449eb3 100644 ---- a/sound/soc/meson/axg-frddr.c -+++ b/sound/soc/meson/axg-frddr.c -@@ -109,7 +109,9 @@ static struct snd_soc_dai_driver axg_frddr_dai_drv = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = AXG_FIFO_CH_MAX, -- .rates = AXG_FIFO_RATES, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .rate_min = 5515, -+ .rate_max = 384000, - .formats = AXG_FIFO_FORMATS, - }, - .ops = &axg_frddr_ops, -@@ -184,7 +186,9 @@ static struct snd_soc_dai_driver g12a_frddr_dai_drv = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = AXG_FIFO_CH_MAX, -- .rates = AXG_FIFO_RATES, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .rate_min = 5515, -+ .rate_max = 384000, - .formats = AXG_FIFO_FORMATS, - }, - .ops = &g12a_frddr_ops, -diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c -index 1a0be177b8fe..32ee45cce7f8 100644 ---- a/sound/soc/meson/axg-toddr.c -+++ b/sound/soc/meson/axg-toddr.c -@@ -131,7 +131,9 @@ static struct snd_soc_dai_driver axg_toddr_dai_drv = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = AXG_FIFO_CH_MAX, -- .rates = AXG_FIFO_RATES, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .rate_min = 5515, -+ .rate_max = 384000, - .formats = AXG_FIFO_FORMATS, - }, - .ops = &axg_toddr_ops, -@@ -226,7 +228,9 @@ static struct snd_soc_dai_driver g12a_toddr_dai_drv = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = AXG_FIFO_CH_MAX, -- .rates = AXG_FIFO_RATES, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .rate_min = 5515, -+ .rate_max = 384000, - .formats = AXG_FIFO_FORMATS, - }, - .ops = &g12a_toddr_ops, --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0016-FROMLIST-v5-auxdisplay-add-support-for-Titanmec-TM16.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0033-FROMLIST-v5-auxdisplay-add-support-for-Titanmec-TM16.patch similarity index 95% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0016-FROMLIST-v5-auxdisplay-add-support-for-Titanmec-TM16.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0033-FROMLIST-v5-auxdisplay-add-support-for-Titanmec-TM16.patch index 0b3b424855..b717506940 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0016-FROMLIST-v5-auxdisplay-add-support-for-Titanmec-TM16.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0033-FROMLIST-v5-auxdisplay-add-support-for-Titanmec-TM16.patch @@ -1,7 +1,7 @@ -From e7c3f45587cda5b5b445df7434f38a0d751bb197 Mon Sep 17 00:00:00 2001 +From 41fa0e4796e981b1874233c36af38583a2f9d07d Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Mon, 4 Apr 2022 18:51:20 +0000 -Subject: [PATCH 16/53] FROMLIST(v5): auxdisplay: add support for Titanmec +Subject: [PATCH 33/69] FROMLIST(v5): auxdisplay: add support for Titanmec TM1628 7 segment display controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -44,12 +44,12 @@ Signed-off-by: Heiner Kallweit create mode 100644 drivers/auxdisplay/tm1628.c diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig -index d944d5298eca..f3d513139e5c 100644 +index 69d2138d7efb..dca186b9f2c1 100644 --- a/drivers/auxdisplay/Kconfig +++ b/drivers/auxdisplay/Kconfig -@@ -197,6 +197,17 @@ config ARM_CHARLCD - line and the Linux version on the second line, but that's - still useful. +@@ -525,6 +525,17 @@ config SEG_LED_GPIO + This driver can also be built as a module. If so, the module + will be called seg-led-gpio. +config TM1628 + tristate "TM1628 driver for LED 7/11 segment displays" @@ -62,17 +62,17 @@ index d944d5298eca..f3d513139e5c 100644 + It's a 3-wire SPI device controlling a two-dimensional grid of + LEDs. Dimming is applied to all outputs through an internal PWM. + - menuconfig PARPORT_PANEL - tristate "Parallel port LCD/Keypad Panel support" - depends on PARPORT + # + # Character LCD with non-conforming interface section + # diff --git a/drivers/auxdisplay/Makefile b/drivers/auxdisplay/Makefile -index 6968ed4d3f0a..7728e17e1c5a 100644 +index f5c13ed1cd4f..82818251ffaf 100644 --- a/drivers/auxdisplay/Makefile +++ b/drivers/auxdisplay/Makefile -@@ -14,3 +14,4 @@ obj-$(CONFIG_HT16K33) += ht16k33.o +@@ -16,3 +16,4 @@ obj-$(CONFIG_LINEDISP) += line-display.o + obj-$(CONFIG_MAX6959) += max6959.o obj-$(CONFIG_PARPORT_PANEL) += panel.o - obj-$(CONFIG_LCD2S) += lcd2s.o - obj-$(CONFIG_LINEDISP) += line-display.o + obj-$(CONFIG_SEG_LED_GPIO) += seg-led-gpio.o +obj-$(CONFIG_TM1628) += tm1628.o diff --git a/drivers/auxdisplay/tm1628.c b/drivers/auxdisplay/tm1628.c new file mode 100644 diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0034-FROMLIST-v1-ASoC-meson-axg-fifo-use-FIELD-helpers.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0034-FROMLIST-v1-ASoC-meson-axg-fifo-use-FIELD-helpers.patch deleted file mode 100644 index 4a00d59064..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0034-FROMLIST-v1-ASoC-meson-axg-fifo-use-FIELD-helpers.patch +++ /dev/null @@ -1,176 +0,0 @@ -From 3e72fee0fba2026ba5c16a4a3f329fc04fcce310 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Fri, 23 Feb 2024 18:51:12 +0100 -Subject: [PATCH 34/53] FROMLIST(v1): ASoC: meson: axg-fifo: use FIELD helpers - -Use FIELD_GET() and FIELD_PREP() helpers instead of doing it manually. - -Signed-off-by: Jerome Brunet ---- - sound/soc/meson/axg-fifo.c | 24 ++++++++++++------------ - sound/soc/meson/axg-fifo.h | 12 +++++------- - sound/soc/meson/axg-frddr.c | 4 ++-- - sound/soc/meson/axg-toddr.c | 21 +++++++++------------ - 4 files changed, 28 insertions(+), 33 deletions(-) - -diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c -index 65541fdb0038..597fd39e6e48 100644 ---- a/sound/soc/meson/axg-fifo.c -+++ b/sound/soc/meson/axg-fifo.c -@@ -145,8 +145,8 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component, - /* Enable irq if necessary */ - irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT; - regmap_update_bits(fifo->map, FIFO_CTRL0, -- CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), -- CTRL0_INT_EN(irq_en)); -+ CTRL0_INT_EN, -+ FIELD_PREP(CTRL0_INT_EN, irq_en)); - - return 0; - } -@@ -176,9 +176,9 @@ int axg_fifo_pcm_hw_free(struct snd_soc_component *component, - { - struct axg_fifo *fifo = axg_fifo_data(ss); - -- /* Disable the block count irq */ -+ /* Disable irqs */ - regmap_update_bits(fifo->map, FIFO_CTRL0, -- CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0); -+ CTRL0_INT_EN, 0); - - return 0; - } -@@ -187,13 +187,13 @@ EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free); - static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask) - { - regmap_update_bits(fifo->map, FIFO_CTRL1, -- CTRL1_INT_CLR(FIFO_INT_MASK), -- CTRL1_INT_CLR(mask)); -+ CTRL1_INT_CLR, -+ FIELD_PREP(CTRL1_INT_CLR, mask)); - - /* Clear must also be cleared */ - regmap_update_bits(fifo->map, FIFO_CTRL1, -- CTRL1_INT_CLR(FIFO_INT_MASK), -- 0); -+ CTRL1_INT_CLR, -+ FIELD_PREP(CTRL1_INT_CLR, 0)); - } - - static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) -@@ -204,7 +204,7 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) - - regmap_read(fifo->map, FIFO_STATUS1, &status); - -- status = STATUS1_INT_STS(status) & FIFO_INT_MASK; -+ status = FIELD_GET(STATUS1_INT_STS, status); - if (status & FIFO_INT_COUNT_REPEAT) - snd_pcm_period_elapsed(ss); - else -@@ -254,15 +254,15 @@ int axg_fifo_pcm_open(struct snd_soc_component *component, - - /* Setup status2 so it reports the memory pointer */ - regmap_update_bits(fifo->map, FIFO_CTRL1, -- CTRL1_STATUS2_SEL_MASK, -- CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ)); -+ CTRL1_STATUS2_SEL, -+ FIELD_PREP(CTRL1_STATUS2_SEL, STATUS2_SEL_DDR_READ)); - - /* Make sure the dma is initially disabled */ - __dma_enable(fifo, false); - - /* Disable irqs until params are ready */ - regmap_update_bits(fifo->map, FIFO_CTRL0, -- CTRL0_INT_EN(FIFO_INT_MASK), 0); -+ CTRL0_INT_EN, 0); - - /* Clear any pending interrupt */ - axg_fifo_ack_irq(fifo, FIFO_INT_MASK); -diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h -index a14c31eb06d8..4c48c0a08481 100644 ---- a/sound/soc/meson/axg-fifo.h -+++ b/sound/soc/meson/axg-fifo.h -@@ -40,21 +40,19 @@ struct snd_soc_pcm_runtime; - - #define FIFO_CTRL0 0x00 - #define CTRL0_DMA_EN BIT(31) --#define CTRL0_INT_EN(x) ((x) << 16) -+#define CTRL0_INT_EN GENMASK(23, 16) - #define CTRL0_SEL_MASK GENMASK(2, 0) - #define CTRL0_SEL_SHIFT 0 - #define FIFO_CTRL1 0x04 --#define CTRL1_INT_CLR(x) ((x) << 0) --#define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) --#define CTRL1_STATUS2_SEL(x) ((x) << 8) -+#define CTRL1_INT_CLR GENMASK(7, 0) -+#define CTRL1_STATUS2_SEL GENMASK(11, 8) - #define STATUS2_SEL_DDR_READ 0 --#define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) --#define CTRL1_FRDDR_DEPTH(x) ((x) << 24) -+#define CTRL1_FRDDR_DEPTH GENMASK(31, 24) - #define FIFO_START_ADDR 0x08 - #define FIFO_FINISH_ADDR 0x0c - #define FIFO_INT_ADDR 0x10 - #define FIFO_STATUS1 0x14 --#define STATUS1_INT_STS(x) ((x) << 0) -+#define STATUS1_INT_STS GENMASK(7, 0) - #define FIFO_STATUS2 0x18 - #define FIFO_INIT_ADDR 0x24 - #define FIFO_CTRL2 0x28 -diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c -index 98140f449eb3..97ca0ea5faa5 100644 ---- a/sound/soc/meson/axg-frddr.c -+++ b/sound/soc/meson/axg-frddr.c -@@ -59,8 +59,8 @@ static int axg_frddr_dai_hw_params(struct snd_pcm_substream *substream, - /* Trim the FIFO depth if the period is small to improve latency */ - depth = min(period, fifo->depth); - val = (depth / AXG_FIFO_BURST) - 1; -- regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, -- CTRL1_FRDDR_DEPTH(val)); -+ regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH, -+ FIELD_PREP(CTRL1_FRDDR_DEPTH, val)); - - return 0; - } -diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c -index 32ee45cce7f8..5b08b4e841ad 100644 ---- a/sound/soc/meson/axg-toddr.c -+++ b/sound/soc/meson/axg-toddr.c -@@ -19,12 +19,9 @@ - #define CTRL0_TODDR_EXT_SIGNED BIT(29) - #define CTRL0_TODDR_PP_MODE BIT(28) - #define CTRL0_TODDR_SYNC_CH BIT(27) --#define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13) --#define CTRL0_TODDR_TYPE(x) ((x) << 13) --#define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8) --#define CTRL0_TODDR_MSB_POS(x) ((x) << 8) --#define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3) --#define CTRL0_TODDR_LSB_POS(x) ((x) << 3) -+#define CTRL0_TODDR_TYPE GENMASK(15, 13) -+#define CTRL0_TODDR_MSB_POS GENMASK(12, 8) -+#define CTRL0_TODDR_LSB_POS GENMASK(7, 3) - #define CTRL1_TODDR_FORCE_FINISH BIT(25) - #define CTRL1_SEL_SHIFT 28 - -@@ -76,12 +73,12 @@ static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream, - width = params_width(params); - - regmap_update_bits(fifo->map, FIFO_CTRL0, -- CTRL0_TODDR_TYPE_MASK | -- CTRL0_TODDR_MSB_POS_MASK | -- CTRL0_TODDR_LSB_POS_MASK, -- CTRL0_TODDR_TYPE(type) | -- CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) | -- CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1))); -+ CTRL0_TODDR_TYPE | -+ CTRL0_TODDR_MSB_POS | -+ CTRL0_TODDR_LSB_POS, -+ FIELD_PREP(CTRL0_TODDR_TYPE, type) | -+ FIELD_PREP(CTRL0_TODDR_MSB_POS, TODDR_MSB_POS) | -+ FIELD_PREP(CTRL0_TODDR_LSB_POS, TODDR_MSB_POS - (width - 1))); - - return 0; - } --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0017-FROMLIST-v5-arm64-dts-meson-gxl-s905w-tx3-mini-add-s.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0034-FROMLIST-v5-arm64-dts-meson-gxl-s905w-tx3-mini-add-s.patch similarity index 94% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0017-FROMLIST-v5-arm64-dts-meson-gxl-s905w-tx3-mini-add-s.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0034-FROMLIST-v5-arm64-dts-meson-gxl-s905w-tx3-mini-add-s.patch index 5405a1ebc5..11c3376bfe 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0017-FROMLIST-v5-arm64-dts-meson-gxl-s905w-tx3-mini-add-s.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0034-FROMLIST-v5-arm64-dts-meson-gxl-s905w-tx3-mini-add-s.patch @@ -1,7 +1,7 @@ -From 8dd34cfc3fdb2ae31c34492b8b25bdf7d8c3352b Mon Sep 17 00:00:00 2001 +From c248e93fb876f2131e823757aacb6770a4bb9a57 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Mon, 4 Apr 2022 18:52:34 +0000 -Subject: [PATCH 17/53] FROMLIST(v5): arm64: dts: meson-gxl-s905w-tx3-mini: add +Subject: [PATCH 34/69] FROMLIST(v5): arm64: dts: meson-gxl-s905w-tx3-mini: add support for the 7 segment display This patch adds support for the 7 segment display of the device. diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0035-FROMLIST-v1-drm-panfrost-fix-power-transition-timeou.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0035-FROMLIST-v1-drm-panfrost-fix-power-transition-timeou.patch deleted file mode 100644 index 0fcced7db4..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0035-FROMLIST-v1-drm-panfrost-fix-power-transition-timeou.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 75a8df6a4644ae9399d277c164e591130ee1c776 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Wed, 20 Mar 2024 13:28:08 +0000 -Subject: [PATCH 35/53] FROMLIST(v1): drm/panfrost: fix power transition - timeout warnings - -Increase the timeout value to prevent system logs on Amlogic boards flooding -with power transition warnings: - -[ 13.047638] panfrost ffe40000.gpu: shader power transition timeout -[ 13.048674] panfrost ffe40000.gpu: l2 power transition timeout -[ 13.937324] panfrost ffe40000.gpu: shader power transition timeout -[ 13.938351] panfrost ffe40000.gpu: l2 power transition timeout -... -[39829.506904] panfrost ffe40000.gpu: shader power transition timeout -[39829.507938] panfrost ffe40000.gpu: l2 power transition timeout -[39949.508369] panfrost ffe40000.gpu: shader power transition timeout -[39949.509405] panfrost ffe40000.gpu: l2 power transition timeout - -The 2000 value has been found through trial and error testing on Amlogic boards -with G52 and G31 GPU's. - -Fixes: 22aa1a209018 ("drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off()") -Signed-off-by: Christian Hewitt ---- - drivers/gpu/drm/panfrost/panfrost_gpu.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c -index 9063ce254642..fd8e44992184 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_gpu.c -+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c -@@ -441,19 +441,19 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev) - - gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present); - ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, -- val, !val, 1, 1000); -+ val, !val, 1, 2000); - if (ret) - dev_err(pfdev->dev, "shader power transition timeout"); - - gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present); - ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO, -- val, !val, 1, 1000); -+ val, !val, 1, 2000); - if (ret) - dev_err(pfdev->dev, "tiler power transition timeout"); - - gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present); - ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, -- val, !val, 0, 1000); -+ val, !val, 0, 2000); - if (ret) - dev_err(pfdev->dev, "l2 power transition timeout"); - } --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0018-FROMLIST-v5-MAINTAINERS-Add-entry-for-tm1628-auxdisp.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0035-FROMLIST-v5-MAINTAINERS-Add-entry-for-tm1628-auxdisp.patch similarity index 77% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0018-FROMLIST-v5-MAINTAINERS-Add-entry-for-tm1628-auxdisp.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0035-FROMLIST-v5-MAINTAINERS-Add-entry-for-tm1628-auxdisp.patch index a5e70d0581..b22c5ce478 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0018-FROMLIST-v5-MAINTAINERS-Add-entry-for-tm1628-auxdisp.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0035-FROMLIST-v5-MAINTAINERS-Add-entry-for-tm1628-auxdisp.patch @@ -1,7 +1,7 @@ -From 3a59c995a56b3802ceb6db413c81e2170fa767cb Mon Sep 17 00:00:00 2001 +From 4b711a4fa9907a0b0c786619833015bad8940568 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Mon, 4 Apr 2022 18:53:32 +0000 -Subject: [PATCH 18/53] FROMLIST(v5): MAINTAINERS: Add entry for tm1628 +Subject: [PATCH 35/69] FROMLIST(v5): MAINTAINERS: Add entry for tm1628 auxdisplay driver Signed-off-by: Heiner Kallweit @@ -10,10 +10,10 @@ Signed-off-by: Heiner Kallweit 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS -index 1aabf1c15bb3..ea6d2ff2eb20 100644 +index 28e20975c26f..82cce970986a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -22155,6 +22155,13 @@ W: http://sourceforge.net/projects/tlan/ +@@ -22310,6 +22310,13 @@ W: http://sourceforge.net/projects/tlan/ F: Documentation/networking/device_drivers/ethernet/ti/tlan.rst F: drivers/net/ethernet/ti/tlan.* diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0019-FROMLIST-v1-ASoC-hdmi-codec-reorder-channel-allocati.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0036-FROMLIST-v1-ASoC-hdmi-codec-reorder-channel-allocati.patch similarity index 98% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0019-FROMLIST-v1-ASoC-hdmi-codec-reorder-channel-allocati.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0036-FROMLIST-v1-ASoC-hdmi-codec-reorder-channel-allocati.patch index 3d61af0a7d..fcdaab4e6c 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0019-FROMLIST-v1-ASoC-hdmi-codec-reorder-channel-allocati.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0036-FROMLIST-v1-ASoC-hdmi-codec-reorder-channel-allocati.patch @@ -1,7 +1,7 @@ -From 665584f98081e481e77286b49b6a0e1ce9fe5655 Mon Sep 17 00:00:00 2001 +From 6949c51b8190a3ec6c82b0362ce45b9a87acf7b5 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 23 Dec 2018 02:24:38 +0100 -Subject: [PATCH 19/53] FROMLIST(v1): ASoC: hdmi-codec: reorder channel +Subject: [PATCH 36/69] FROMLIST(v1): ASoC: hdmi-codec: reorder channel allocation list Wrong channel allocation is selected by hdmi_codec_get_ch_alloc_table_idx(). diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0020-FROMLIST-v1-media-meson-vdec-esparser-check-parsing-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0037-FROMLIST-v1-media-meson-vdec-esparser-check-parsing-.patch similarity index 93% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0020-FROMLIST-v1-media-meson-vdec-esparser-check-parsing-.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0037-FROMLIST-v1-media-meson-vdec-esparser-check-parsing-.patch index 1f32853b3d..4717fbcff0 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0020-FROMLIST-v1-media-meson-vdec-esparser-check-parsing-.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0037-FROMLIST-v1-media-meson-vdec-esparser-check-parsing-.patch @@ -1,7 +1,7 @@ -From b4b3656688319a77827ce533f8797f317dfaa01c Mon Sep 17 00:00:00 2001 +From 94cbc52d4336ac9d9db13db90f0f2c7264368c81 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 22 Nov 2021 09:15:21 +0000 -Subject: [PATCH 20/53] FROMLIST(v1): media: meson: vdec: esparser: check +Subject: [PATCH 37/69] FROMLIST(v1): media: meson: vdec: esparser: check parsing state with hardware write pointer Also check the hardware write pointer to check if ES Parser has stalled. diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0021-FROMLIST-v2-media-meson-vdec-implement-10bit-bitstre.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0038-FROMLIST-v2-media-meson-vdec-implement-10bit-bitstre.patch similarity index 99% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0021-FROMLIST-v2-media-meson-vdec-implement-10bit-bitstre.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0038-FROMLIST-v2-media-meson-vdec-implement-10bit-bitstre.patch index 46840b6b3f..261d400fb6 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0021-FROMLIST-v2-media-meson-vdec-implement-10bit-bitstre.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0038-FROMLIST-v2-media-meson-vdec-implement-10bit-bitstre.patch @@ -1,7 +1,7 @@ -From 73aa203801527e081409ead1c5708552ecc5f82b Mon Sep 17 00:00:00 2001 +From 24058bc29c31131aed9f446b8d207f30e08c77be Mon Sep 17 00:00:00 2001 From: Benjamin Roszak Date: Mon, 23 Jan 2023 10:56:46 +0000 -Subject: [PATCH 21/53] FROMLIST(v2): media: meson: vdec: implement 10bit +Subject: [PATCH 38/69] FROMLIST(v2): media: meson: vdec: implement 10bit bitstream handling In order to support 10bit bitstream decoding, buffers and MMU @@ -453,10 +453,10 @@ index baf0dba3c418..ef6dd05d89c8 100644 return -EAGAIN; } diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h -index 0906b8fb5cc6..a48170fe4cff 100644 +index 258685177700..e1e731b7d431 100644 --- a/drivers/staging/media/meson/vdec/vdec.h +++ b/drivers/staging/media/meson/vdec/vdec.h -@@ -244,6 +244,7 @@ struct amvdec_session { +@@ -243,6 +243,7 @@ struct amvdec_session { u32 width; u32 height; u32 colorspace; diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0022-FROMLIST-v2-media-meson-vdec-add-HEVC-decode-codec.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0039-FROMLIST-v2-media-meson-vdec-add-HEVC-decode-codec.patch similarity index 99% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0022-FROMLIST-v2-media-meson-vdec-add-HEVC-decode-codec.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0039-FROMLIST-v2-media-meson-vdec-add-HEVC-decode-codec.patch index 44edd7f875..8ec5c05585 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0022-FROMLIST-v2-media-meson-vdec-add-HEVC-decode-codec.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0039-FROMLIST-v2-media-meson-vdec-add-HEVC-decode-codec.patch @@ -1,7 +1,7 @@ -From 00829e834a4cd6594b076550fd18be30ddba5b0e Mon Sep 17 00:00:00 2001 +From 024027c2878c87f5ee0963439fae1c24164bc382 Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Mon, 23 Jan 2023 11:07:04 +0000 -Subject: [PATCH 22/53] FROMLIST(v2): media: meson: vdec: add HEVC decode codec +Subject: [PATCH 39/69] FROMLIST(v2): media: meson: vdec: add HEVC decode codec Add initial HEVC codec for the Amlogic GXBB/GXL/GXM SoCs using the common "HEVC" decoder driver. diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0023-FROMLIST-v4-dt-bindings-usb-Add-the-binding-example-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0040-FROMLIST-v4-dt-bindings-usb-Add-the-binding-example-.patch similarity index 96% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0023-FROMLIST-v4-dt-bindings-usb-Add-the-binding-example-.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0040-FROMLIST-v4-dt-bindings-usb-Add-the-binding-example-.patch index 362987de3b..bbc086e2bd 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0023-FROMLIST-v4-dt-bindings-usb-Add-the-binding-example-.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0040-FROMLIST-v4-dt-bindings-usb-Add-the-binding-example-.patch @@ -1,7 +1,7 @@ -From 1283c858520094cb01ff6fc133eab9cad8c7e276 Mon Sep 17 00:00:00 2001 +From 4663bf7102e82064d156a9a12e24139f516098c3 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 22 Nov 2023 23:53:46 +0530 -Subject: [PATCH 23/53] FROMLIST(v4): dt-bindings: usb: Add the binding example +Subject: [PATCH 40/69] FROMLIST(v4): dt-bindings: usb: Add the binding example for the Genesys Logic GL3523 hub Add the binding example for the USB3.1 Genesys Logic GL3523 diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0024-FROMLIST-v4-arm64-dts-amlogic-Used-onboard-usb-hub-r.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0041-FROMLIST-v4-arm64-dts-amlogic-Used-onboard-usb-hub-r.patch similarity index 93% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0024-FROMLIST-v4-arm64-dts-amlogic-Used-onboard-usb-hub-r.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0041-FROMLIST-v4-arm64-dts-amlogic-Used-onboard-usb-hub-r.patch index 620a6e4a4d..1fff230b0e 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0024-FROMLIST-v4-arm64-dts-amlogic-Used-onboard-usb-hub-r.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0041-FROMLIST-v4-arm64-dts-amlogic-Used-onboard-usb-hub-r.patch @@ -1,7 +1,7 @@ -From 3b361c7741a8c9a7ba990eda872fcc7817d35b23 Mon Sep 17 00:00:00 2001 +From bfd238dd418d92920dc5d14c97bb6743a23fe187 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Tue, 10 Oct 2023 08:54:43 +0530 -Subject: [PATCH 24/53] FROMLIST(v4): arm64: dts: amlogic: Used onboard usb hub +Subject: [PATCH 41/69] FROMLIST(v4): arm64: dts: amlogic: Used onboard usb hub reset on odroid n2 On Odroid n2/n2+ previously use gpio-hog to reset the usb hub, diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0025-FROMLIST-v1-arm64-dts-meson-radxa-zero2-add-pwm-fan-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0042-FROMLIST-v1-arm64-dts-meson-radxa-zero2-add-pwm-fan-.patch similarity index 92% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0025-FROMLIST-v1-arm64-dts-meson-radxa-zero2-add-pwm-fan-.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0042-FROMLIST-v1-arm64-dts-meson-radxa-zero2-add-pwm-fan-.patch index 2cede28a35..d220eb6e26 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0025-FROMLIST-v1-arm64-dts-meson-radxa-zero2-add-pwm-fan-.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0042-FROMLIST-v1-arm64-dts-meson-radxa-zero2-add-pwm-fan-.patch @@ -1,7 +1,7 @@ -From 983b5729b97918d6c860bdfd01093cf60b0ea83e Mon Sep 17 00:00:00 2001 +From fb42c49d5c13762278e961748f99a135b16aa54e Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 30 Jan 2023 05:09:18 +0000 -Subject: [PATCH 25/53] FROMLIST(v1): arm64: dts: meson: radxa-zero2: add +Subject: [PATCH 42/69] FROMLIST(v1): arm64: dts: meson: radxa-zero2: add pwm-fan support The A311D on Zero2 needs active cooling and the board includes a header to diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0026-FROMLIST-v2-meson_plane-Add-error-handling.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0043-FROMLIST-v2-meson_plane-Add-error-handling.patch similarity index 93% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0026-FROMLIST-v2-meson_plane-Add-error-handling.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0043-FROMLIST-v2-meson_plane-Add-error-handling.patch index d16f35b3bc..0b7d776cce 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0026-FROMLIST-v2-meson_plane-Add-error-handling.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0043-FROMLIST-v2-meson_plane-Add-error-handling.patch @@ -1,7 +1,7 @@ -From a4c4025275bcce3c13ff2d2b46dfa49ff947804a Mon Sep 17 00:00:00 2001 +From f88d7a934300717d0098341c27a069d263680f09 Mon Sep 17 00:00:00 2001 From: Haoran Liu Date: Wed, 29 Nov 2023 03:34:05 -0800 -Subject: [PATCH 26/53] FROMLIST(v2): meson_plane: Add error handling +Subject: [PATCH 43/69] FROMLIST(v2): meson_plane: Add error handling This patch adds robust error handling to the meson_plane_create function in drivers/gpu/drm/meson/meson_plane.c. The function diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0036-FROMLIST-v1-iio-adc-meson-fix-voltage-reference-sele.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0044-FROMLIST-v1-iio-adc-meson-fix-voltage-reference-sele.patch similarity index 93% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0036-FROMLIST-v1-iio-adc-meson-fix-voltage-reference-sele.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0044-FROMLIST-v1-iio-adc-meson-fix-voltage-reference-sele.patch index 59d76c848f..e562ca7b92 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0036-FROMLIST-v1-iio-adc-meson-fix-voltage-reference-sele.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0044-FROMLIST-v1-iio-adc-meson-fix-voltage-reference-sele.patch @@ -1,7 +1,7 @@ -From ff1b40e46c3498843e616b364e8f985b0146255f Mon Sep 17 00:00:00 2001 +From 0ada604eb1aee519e7014605061c20ef7763763c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 23 Mar 2024 20:04:49 +0100 -Subject: [PATCH 36/53] FROMLIST(v1): iio: adc: meson: fix voltage reference +Subject: [PATCH 44/69] FROMLIST(v1): iio: adc: meson: fix voltage reference selection field name typo The field should be called "vref_voltage", without a typo in the word diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0037-FROMLIST-v1-iio-adc-consistently-use-bool-and-enum-i.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0045-FROMLIST-v1-iio-adc-consistently-use-bool-and-enum-i.patch similarity index 97% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0037-FROMLIST-v1-iio-adc-consistently-use-bool-and-enum-i.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0045-FROMLIST-v1-iio-adc-consistently-use-bool-and-enum-i.patch index 2f725545a8..b810d30213 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0037-FROMLIST-v1-iio-adc-consistently-use-bool-and-enum-i.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0045-FROMLIST-v1-iio-adc-consistently-use-bool-and-enum-i.patch @@ -1,7 +1,7 @@ -From e75fe79643d8d1be19c91d195b9fa1cc16bfffa8 Mon Sep 17 00:00:00 2001 +From 590a7fda90807fbf9c58d644145426960a610fcc Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 23 Mar 2024 20:30:02 +0100 -Subject: [PATCH 37/53] FROMLIST(v1): iio: adc: consistently use bool and enum +Subject: [PATCH 45/69] FROMLIST(v1): iio: adc: consistently use bool and enum in struct meson_sar_adc_param Consistently use bool for any register bit that enables/disables diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0038-FROMLIST-v1-iio-adc-meson-simplify-MESON_SAR_ADC_REG.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0046-FROMLIST-v1-iio-adc-meson-simplify-MESON_SAR_ADC_REG.patch similarity index 97% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0038-FROMLIST-v1-iio-adc-meson-simplify-MESON_SAR_ADC_REG.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0046-FROMLIST-v1-iio-adc-meson-simplify-MESON_SAR_ADC_REG.patch index 1f5bbecb3f..ccb4a2f61a 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0038-FROMLIST-v1-iio-adc-meson-simplify-MESON_SAR_ADC_REG.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0046-FROMLIST-v1-iio-adc-meson-simplify-MESON_SAR_ADC_REG.patch @@ -1,7 +1,7 @@ -From c6a0829ea93c2460d1fcc79eb59f9704832a073c Mon Sep 17 00:00:00 2001 +From 37255e6d2fa6341a76518a632ee556813539973f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 23 Mar 2024 20:35:58 +0100 -Subject: [PATCH 38/53] FROMLIST(v1): iio: adc: meson: simplify +Subject: [PATCH 46/69] FROMLIST(v1): iio: adc: meson: simplify MESON_SAR_ADC_REG11 register access Simply check the max_register value to decide whether diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0047-FROMLIST-v1-ASoC-meson-Constify-static-snd_pcm_hardw.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0047-FROMLIST-v1-ASoC-meson-Constify-static-snd_pcm_hardw.patch new file mode 100644 index 0000000000..31b6d6f79c --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0047-FROMLIST-v1-ASoC-meson-Constify-static-snd_pcm_hardw.patch @@ -0,0 +1,73 @@ +From 6e79b2f5914f98242351d29897c391c8778c2172 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Mon, 29 Apr 2024 13:48:48 +0200 +Subject: [PATCH 47/69] FROMLIST(v1): ASoC: meson: Constify static + snd_pcm_hardware + +Static 'struct snd_pcm_hardware' is not modified by the driver and its +copy is passed to the core, so it can be made const for increased code +safety. + +Signed-off-by: Krzysztof Kozlowski +--- + sound/soc/meson/aiu-fifo-i2s.c | 2 +- + sound/soc/meson/aiu-fifo-spdif.c | 2 +- + sound/soc/meson/aiu-fifo.h | 2 +- + sound/soc/meson/axg-fifo.c | 2 +- + 4 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/sound/soc/meson/aiu-fifo-i2s.c b/sound/soc/meson/aiu-fifo-i2s.c +index 7d833500c799..eccbc16b293a 100644 +--- a/sound/soc/meson/aiu-fifo-i2s.c ++++ b/sound/soc/meson/aiu-fifo-i2s.c +@@ -25,7 +25,7 @@ + + #define AIU_FIFO_I2S_BLOCK 256 + +-static struct snd_pcm_hardware fifo_i2s_pcm = { ++static const struct snd_pcm_hardware fifo_i2s_pcm = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | +diff --git a/sound/soc/meson/aiu-fifo-spdif.c b/sound/soc/meson/aiu-fifo-spdif.c +index fa91f3c53fa4..e0e00ec026dc 100644 +--- a/sound/soc/meson/aiu-fifo-spdif.c ++++ b/sound/soc/meson/aiu-fifo-spdif.c +@@ -27,7 +27,7 @@ + + #define AIU_FIFO_SPDIF_BLOCK 8 + +-static struct snd_pcm_hardware fifo_spdif_pcm = { ++static const struct snd_pcm_hardware fifo_spdif_pcm = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | +diff --git a/sound/soc/meson/aiu-fifo.h b/sound/soc/meson/aiu-fifo.h +index 42ce266677cc..84ab4577815a 100644 +--- a/sound/soc/meson/aiu-fifo.h ++++ b/sound/soc/meson/aiu-fifo.h +@@ -18,7 +18,7 @@ struct snd_pcm_hw_params; + struct platform_device; + + struct aiu_fifo { +- struct snd_pcm_hardware *pcm; ++ const struct snd_pcm_hardware *pcm; + unsigned int mem_offset; + unsigned int fifo_block; + struct clk *pclk; +diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c +index ecb3eb7a9723..23ce75273da4 100644 +--- a/sound/soc/meson/axg-fifo.c ++++ b/sound/soc/meson/axg-fifo.c +@@ -23,7 +23,7 @@ + * These differences are handled in the respective DAI drivers + */ + +-static struct snd_pcm_hardware axg_fifo_hw = { ++static const struct snd_pcm_hardware axg_fifo_hw = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0048-FROMLIST-v1-ASoC-meson-Use-snd_soc_substream_to_rtd-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0048-FROMLIST-v1-ASoC-meson-Use-snd_soc_substream_to_rtd-.patch new file mode 100644 index 0000000000..ec4a842b65 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0048-FROMLIST-v1-ASoC-meson-Use-snd_soc_substream_to_rtd-.patch @@ -0,0 +1,43 @@ +From 6299ce68ab47b2c371cc707402bd1ea6f59e752d Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 30 Apr 2024 16:02:20 +0200 +Subject: [PATCH 48/69] FROMLIST(v1): ASoC: meson: Use + snd_soc_substream_to_rtd() for accessing private_data + +Do not open-code snd_soc_substream_to_rtd(). + +Signed-off-by: Krzysztof Kozlowski +--- + sound/soc/meson/aiu-fifo.c | 2 +- + sound/soc/meson/axg-fifo.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/meson/aiu-fifo.c b/sound/soc/meson/aiu-fifo.c +index 4041ff8e437f..b222bde1f61b 100644 +--- a/sound/soc/meson/aiu-fifo.c ++++ b/sound/soc/meson/aiu-fifo.c +@@ -25,7 +25,7 @@ + + static struct snd_soc_dai *aiu_fifo_dai(struct snd_pcm_substream *ss) + { +- struct snd_soc_pcm_runtime *rtd = ss->private_data; ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(ss); + + return snd_soc_rtd_to_cpu(rtd, 0); + } +diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c +index 23ce75273da4..59abe0b3c59f 100644 +--- a/sound/soc/meson/axg-fifo.c ++++ b/sound/soc/meson/axg-fifo.c +@@ -46,7 +46,7 @@ static const struct snd_pcm_hardware axg_fifo_hw = { + + static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss) + { +- struct snd_soc_pcm_runtime *rtd = ss->private_data; ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(ss); + + return snd_soc_rtd_to_cpu(rtd, 0); + } +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0049-FROMLIST-v1-net-mdio-meson-gxl-set-28th-bit-in-eth_r.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0049-FROMLIST-v1-net-mdio-meson-gxl-set-28th-bit-in-eth_r.patch new file mode 100644 index 0000000000..cf2f8078f7 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0049-FROMLIST-v1-net-mdio-meson-gxl-set-28th-bit-in-eth_r.patch @@ -0,0 +1,43 @@ +From 9bfbedf208542f00d5fcd39d7bee1601c655601b Mon Sep 17 00:00:00 2001 +From: Da Xue +Date: Fri, 24 May 2024 15:17:37 +0000 +Subject: [PATCH 49/69] FROMLIST(v1): net: mdio: meson-gxl set 28th bit in + eth_reg2 + +This bit is necessary to enable packets on the interface. Without this +bit set, ethernet behaves as if it is working but no activity occurs. + +The vendor SDK sets this bit along with the PHY_ID bits. u-boot will set +this bit as well but if u-boot is not compiled with networking, the +interface will not work. + +Fixes: 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support"); +Signed-off-by: Da Xue +--- + drivers/net/mdio/mdio-mux-meson-gxl.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/mdio/mdio-mux-meson-gxl.c b/drivers/net/mdio/mdio-mux-meson-gxl.c +index 89554021b5cc..b2bd57f54034 100644 +--- a/drivers/net/mdio/mdio-mux-meson-gxl.c ++++ b/drivers/net/mdio/mdio-mux-meson-gxl.c +@@ -17,6 +17,7 @@ + #define REG2_LEDACT GENMASK(23, 22) + #define REG2_LEDLINK GENMASK(25, 24) + #define REG2_DIV4SEL BIT(27) ++#define REG2_RESERVED_28 BIT(28) + #define REG2_ADCBYPASS BIT(30) + #define REG2_CLKINSEL BIT(31) + #define ETH_REG3 0x4 +@@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct gxl_mdio_mux *priv) + * The only constraint is that it must match the one in + * drivers/net/phy/meson-gxl.c to properly match the PHY. + */ +- writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), ++ writel(REG2_RESERVED_28 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), + priv->regs + ETH_REG2); + + /* Enable the internal phy */ +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0050-WIP-media-meson-vdec-reintroduce-wiggle-room.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0050-WIP-media-meson-vdec-reintroduce-wiggle-room.patch new file mode 100644 index 0000000000..83be169986 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0050-WIP-media-meson-vdec-reintroduce-wiggle-room.patch @@ -0,0 +1,50 @@ +From 7fc9e86945350fc1be6e6c28274e2da7b7ec01c3 Mon Sep 17 00:00:00 2001 +From: Andreas Baierl +Date: Tue, 2 Apr 2024 14:22:52 +0000 +Subject: [PATCH 50/69] WIP: media: meson: vdec: reintroduce wiggle room + +Without the wiggle room, it happens that matching offsets can't be found. +This results in non-matches and afterwards in frame drops in userspace apps. +Reintroduce this wiggle room again. + +Signed-off-by: Andreas Baierl +--- + drivers/staging/media/meson/vdec/vdec_helpers.c | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c +index fef76142f0c5..fbfdbf3ec19d 100644 +--- a/drivers/staging/media/meson/vdec/vdec_helpers.c ++++ b/drivers/staging/media/meson/vdec/vdec_helpers.c +@@ -378,7 +378,16 @@ void amvdec_dst_buf_done_offset(struct amvdec_session *sess, + + /* Look for our vififo offset to get the corresponding timestamp. */ + list_for_each_entry_safe(tmp, n, &sess->timestamps, list) { +- if (tmp->offset > offset) { ++ s64 delta = (s64)offset - tmp->offset; ++ ++ /* Offsets reported by codecs usually differ slightly, ++ * so we need some wiggle room. ++ * 4KiB being the minimum packet size, there is no risk here. ++ */ ++ if (delta > (-1 * (s32)SZ_4K) && delta < SZ_4K) { ++ match = tmp; ++ break; ++ } else { + /* + * Delete any record that remained unused for 32 match + * checks +@@ -387,10 +396,7 @@ void amvdec_dst_buf_done_offset(struct amvdec_session *sess, + list_del(&tmp->list); + kfree(tmp); + } +- break; + } +- +- match = tmp; + } + + if (!match) { +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0039-WIP-dt-bindings-arm-amlogic-add-support-for-Dreambox.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0051-WIP-dt-bindings-arm-amlogic-add-support-for-Dreambox.patch similarity index 82% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0039-WIP-dt-bindings-arm-amlogic-add-support-for-Dreambox.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0051-WIP-dt-bindings-arm-amlogic-add-support-for-Dreambox.patch index 1b54ea90ba..bd14b137ef 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0039-WIP-dt-bindings-arm-amlogic-add-support-for-Dreambox.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0051-WIP-dt-bindings-arm-amlogic-add-support-for-Dreambox.patch @@ -1,7 +1,7 @@ -From 8d6f4eb8a8a7bd35dd10bb4d942b0e3182042ac1 Mon Sep 17 00:00:00 2001 +From c63dc0d2975b01f94848480801d32ca9501bae32 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 5 Apr 2021 13:48:34 +0000 -Subject: [PATCH 39/53] WIP: dt-bindings: arm: amlogic: add support for +Subject: [PATCH 51/69] WIP: dt-bindings: arm: amlogic: add support for Dreambox One/Two The Dreambox One and Dreambox Two are DVBS/T2 receiver boxes based @@ -13,10 +13,10 @@ Signed-off-by: Christian Hewitt 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml -index caab7ceeda45..922380d6139e 100644 +index 949537cea6be..0cb0721d83e3 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml -@@ -175,6 +175,8 @@ properties: +@@ -168,6 +168,8 @@ properties: - azw,gtking - azw,gtking-pro - bananapi,bpi-m2s diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0040-WIP-arm64-dts-meson-add-initial-device-trees-for-Dre.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0052-WIP-arm64-dts-meson-add-initial-device-trees-for-Dre.patch similarity index 96% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0040-WIP-arm64-dts-meson-add-initial-device-trees-for-Dre.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0052-WIP-arm64-dts-meson-add-initial-device-trees-for-Dre.patch index 39f5c63037..e69cdb763d 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0040-WIP-arm64-dts-meson-add-initial-device-trees-for-Dre.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0052-WIP-arm64-dts-meson-add-initial-device-trees-for-Dre.patch @@ -1,7 +1,7 @@ -From ffbb462ad7261792d8642717b1d17407afe81d94 Mon Sep 17 00:00:00 2001 +From 1dc7d697233d1832d222e6e72afe2dcbc9ef19c9 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 5 Apr 2021 13:51:20 +0000 -Subject: [PATCH 40/53] WIP: arm64: dts: meson: add initial device-trees for +Subject: [PATCH 52/69] WIP: arm64: dts: meson: add initial device-trees for Dreambox One/Two Dreambox One and Dreambox Two are based on the Amlogic W400 reference @@ -40,10 +40,10 @@ Signed-off-by: Christian Hewitt create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile -index cc8b34bd583d..edb22c57f11d 100644 +index 1ab160bf928a..3b2e11a82df2 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile -@@ -15,6 +15,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb +@@ -17,6 +17,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-bananapi-m2s.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-cm4io.dtb diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0053-WIP-arm64-dts-meson-add-p271-support.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0053-WIP-arm64-dts-meson-add-p271-support.patch deleted file mode 100644 index a41d087366..0000000000 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0053-WIP-arm64-dts-meson-add-p271-support.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 75671e34bec14c140e4e81ae742de16b2a29d174 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Mon, 1 Jan 2024 07:40:15 +0000 -Subject: [PATCH 53/53] WIP: arm64: dts: meson: add p271 support - -Add a device-tree for the Amlogic P271 (S905L) reference design board. This is -similar to the P212 (S905X) but with silicon differences to omit the VP9 codec -and use Mali 450-MP2 not MP3. The SoC is marked with S905L and a "2" (believed -to denote the MP2) and is sometimes wrongly described on some distributor stock -lists (and box vendor marketing) as an S905L2 chip. - -Signed-off-by: Christian Hewitt ---- - .../boot/dts/amlogic/meson-gxl-s905l-p271.dts | 47 +++++++++++++++++++ - 1 file changed, 47 insertions(+) - create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts - -diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts -new file mode 100644 -index 000000000000..a902e4af7c15 ---- /dev/null -+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2024 Christian Hewitt -+ */ -+ -+/dts-v1/; -+ -+#include "meson-gxl-s905x.dtsi" -+#include "meson-gx-p23x-q20x.dtsi" -+ -+/ { -+ compatible = "amlogic,p271", "amlogic,s905l", "amlogic,meson-gxl"; -+ model = "Amlogic Meson GXLX (S905L) P271 Development Board"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x40000000>; -+ }; -+ -+ sound { -+ model = "P271"; -+ }; -+}; -+ -+&apb { -+ mali: gpu@c0000 { -+ /* Mali 450-MP2 */ -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "gp", "gpmmu", "pp", "pmu", -+ "pp0", "ppmmu0", "pp1", "ppmmu1"; -+ }; -+}; -+ -+&saradc { -+ compatible = "amlogic,meson-gxlx-saradc", "amlogic,meson-saradc"; -+}; -+ -+&usb { -+ dr_mode = "host"; -+}; --- -2.34.1 - diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0041-WIP-arm64-dts-meson-increase-SD-speeds-on-Minix-Neo-.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0053-WIP-arm64-dts-meson-increase-SD-speeds-on-Minix-Neo-.patch similarity index 87% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0041-WIP-arm64-dts-meson-increase-SD-speeds-on-Minix-Neo-.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0053-WIP-arm64-dts-meson-increase-SD-speeds-on-Minix-Neo-.patch index a837827fc4..825c3bb08e 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0041-WIP-arm64-dts-meson-increase-SD-speeds-on-Minix-Neo-.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0053-WIP-arm64-dts-meson-increase-SD-speeds-on-Minix-Neo-.patch @@ -1,7 +1,7 @@ -From 2fa9dc2253ed3266db28b0a3ebb5d942427ef7a9 Mon Sep 17 00:00:00 2001 +From afb8fdb7130c6d2a31dba2e0a66e4db299bae4ad Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 1 Jan 2024 06:15:40 +0000 -Subject: [PATCH 41/53] WIP: arm64: dts: meson: increase SD speeds on Minix Neo +Subject: [PATCH 53/69] WIP: arm64: dts: meson: increase SD speeds on Minix Neo U9-H Lets see what happens/breaks when all the fancy modes are added diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0042-WIP-arm64-dts-meson-fixup-Minix-U9-H-wifi.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0054-WIP-arm64-dts-meson-fixup-Minix-U9-H-wifi.patch similarity index 86% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0042-WIP-arm64-dts-meson-fixup-Minix-U9-H-wifi.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0054-WIP-arm64-dts-meson-fixup-Minix-U9-H-wifi.patch index fbda4e066e..8552b1b78b 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0042-WIP-arm64-dts-meson-fixup-Minix-U9-H-wifi.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0054-WIP-arm64-dts-meson-fixup-Minix-U9-H-wifi.patch @@ -1,7 +1,7 @@ -From 6302dc4b0ec1ce8d343ca620f1fc82e8fa5e1dda Mon Sep 17 00:00:00 2001 +From df7565c87afd20714c96fbb3f5847ff6c20bd220 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Fri, 5 Jan 2024 03:07:58 +0000 -Subject: [PATCH 42/53] WIP: arm64: dts: meson: fixup Minix U9-H wifi +Subject: [PATCH 54/69] WIP: arm64: dts: meson: fixup Minix U9-H wifi I think the 'drop compatible' change conflicted so remove this too. diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0043-WIP-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0055-WIP-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch similarity index 96% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0043-WIP-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0055-WIP-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch index db4952d89a..522927ce47 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0043-WIP-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0055-WIP-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch @@ -1,7 +1,7 @@ -From 7354c155f1956487683a192e629cda68bcd38bd8 Mon Sep 17 00:00:00 2001 +From 089ad862d61790d7fca3f372762fd53f684299c0 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 18 Jan 2022 15:09:12 +0000 -Subject: [PATCH 43/53] WIP: arm64: dts: meson: set p212/p23x/q20x SDIO to +Subject: [PATCH 55/69] WIP: arm64: dts: meson: set p212/p23x/q20x SDIO to 100MHz Amlogic datasheets describe 50MHz max-frequency for SDIO on GXL/GXM but diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0044-WIP-arm64-dts-meson-add-UHS-SDIO-capabilities-to-p21.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0056-WIP-arm64-dts-meson-add-UHS-SDIO-capabilities-to-p21.patch similarity index 91% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0044-WIP-arm64-dts-meson-add-UHS-SDIO-capabilities-to-p21.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0056-WIP-arm64-dts-meson-add-UHS-SDIO-capabilities-to-p21.patch index 0c69eff32c..f3ff871e50 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0044-WIP-arm64-dts-meson-add-UHS-SDIO-capabilities-to-p21.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0056-WIP-arm64-dts-meson-add-UHS-SDIO-capabilities-to-p21.patch @@ -1,7 +1,7 @@ -From fb6de4d2453abb6e9ff8f0b653eb12e94156958c Mon Sep 17 00:00:00 2001 +From a1afe83c0d099c5fe033d7e4e74aaae5edc874bd Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 19 Jan 2022 06:45:06 +0000 -Subject: [PATCH 44/53] WIP: arm64: dts: meson: add UHS SDIO capabilities to +Subject: [PATCH 56/69] WIP: arm64: dts: meson: add UHS SDIO capabilities to p212/p23x/q20x Add UHS capabilities to the SDIO node to enable 100MHz speeds. diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0045-WIP-arm64-dts-meson-remove-SDIO-node-from-Khadas-VIM.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0057-WIP-arm64-dts-meson-remove-SDIO-node-from-Khadas-VIM.patch similarity index 88% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0045-WIP-arm64-dts-meson-remove-SDIO-node-from-Khadas-VIM.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0057-WIP-arm64-dts-meson-remove-SDIO-node-from-Khadas-VIM.patch index 232c2531d7..914f56e6e2 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0045-WIP-arm64-dts-meson-remove-SDIO-node-from-Khadas-VIM.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0057-WIP-arm64-dts-meson-remove-SDIO-node-from-Khadas-VIM.patch @@ -1,7 +1,7 @@ -From 5661824fa83b4eeb182286aa8ad3b97d1025852c Mon Sep 17 00:00:00 2001 +From 515b6a825199935a85ff27f0778a007f4a582799 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 18 Jan 2022 15:18:32 +0000 -Subject: [PATCH 45/53] WIP: arm64: dts: meson: remove SDIO node from Khadas +Subject: [PATCH 57/69] WIP: arm64: dts: meson: remove SDIO node from Khadas VIM1 Now that SDIO 100MHz max-frequency is inherited from the p212 dtsi we diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0046-WIP-arm64-dts-meson-drop-broadcom-compatible-from-re.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0058-WIP-arm64-dts-meson-drop-broadcom-compatible-from-re.patch similarity index 96% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0046-WIP-arm64-dts-meson-drop-broadcom-compatible-from-re.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0058-WIP-arm64-dts-meson-drop-broadcom-compatible-from-re.patch index 449369e8d7..7cf15380b6 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0046-WIP-arm64-dts-meson-drop-broadcom-compatible-from-re.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0058-WIP-arm64-dts-meson-drop-broadcom-compatible-from-re.patch @@ -1,7 +1,7 @@ -From e77b259c064cd7b8c672c96834fdb1c4d2a98ff4 Mon Sep 17 00:00:00 2001 +From 351dffe709349c9c7eee6700e4f57c1d05f08501 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 3 Jan 2024 03:14:06 +0000 -Subject: [PATCH 46/53] WIP: arm64: dts: meson: drop broadcom compatible from +Subject: [PATCH 58/69] WIP: arm64: dts: meson: drop broadcom compatible from reference board SDIO nodes Remove the Broadcom compatible to allow Android STB boards using Qualcom QCA9377 diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0047-WIP-dt-bindings-arm-amlogic-add-OSMC-Vero-4K.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0059-WIP-dt-bindings-arm-amlogic-add-OSMC-Vero-4K.patch similarity index 79% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0047-WIP-dt-bindings-arm-amlogic-add-OSMC-Vero-4K.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0059-WIP-dt-bindings-arm-amlogic-add-OSMC-Vero-4K.patch index cfa2555cd1..651393b521 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0047-WIP-dt-bindings-arm-amlogic-add-OSMC-Vero-4K.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0059-WIP-dt-bindings-arm-amlogic-add-OSMC-Vero-4K.patch @@ -1,7 +1,7 @@ -From 642e23b3f8a96c89390eb0ff05a6e46e63f9a98f Mon Sep 17 00:00:00 2001 +From 8be562d97c6499157ef7940362abeb62c42b8b51 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 19 Jan 2022 02:40:20 +0000 -Subject: [PATCH 47/53] WIP: dt-bindings: arm: amlogic: add OSMC Vero 4K +Subject: [PATCH 59/69] WIP: dt-bindings: arm: amlogic: add OSMC Vero 4K Add support for the OSMC Vero 4K @@ -11,10 +11,10 @@ Signed-off-by: Christian Hewitt 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml -index 922380d6139e..73598f7992fd 100644 +index 0cb0721d83e3..5d52065abe72 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml -@@ -99,6 +99,7 @@ properties: +@@ -91,6 +91,7 @@ properties: - libretech,aml-s905x-cc - libretech,aml-s905x-cc-v2 - nexbox,a95x diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0048-WIP-arm64-dts-meson-add-support-for-OSMC-Vero-4K.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0060-WIP-arm64-dts-meson-add-support-for-OSMC-Vero-4K.patch similarity index 94% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0048-WIP-arm64-dts-meson-add-support-for-OSMC-Vero-4K.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0060-WIP-arm64-dts-meson-add-support-for-OSMC-Vero-4K.patch index 6dec1cb957..20d3cfd2f9 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0048-WIP-arm64-dts-meson-add-support-for-OSMC-Vero-4K.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0060-WIP-arm64-dts-meson-add-support-for-OSMC-Vero-4K.patch @@ -1,7 +1,7 @@ -From e4062d9479c72b37e7093a424f969829018d5a48 Mon Sep 17 00:00:00 2001 +From f370eaf064a3dd1620d9e47edd6738eff74531fa Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 19 Jan 2022 04:06:17 +0000 -Subject: [PATCH 48/53] WIP: arm64: dts: meson: add support for OSMC Vero 4K +Subject: [PATCH 60/69] WIP: arm64: dts: meson: add support for OSMC Vero 4K The OSMC Vero 4K device is based on the Amlogic S905X (P212) reference design with the following specifications: @@ -22,20 +22,19 @@ design with the following specifications: Signed-off-by: Christian Hewitt --- - arch/arm64/boot/dts/amlogic/Makefile | 8 + + arch/arm64/boot/dts/amlogic/Makefile | 7 + .../dts/amlogic/meson-gxl-s905x-vero4k.dts | 202 ++++++++++++++++++ - 2 files changed, 210 insertions(+) + 2 files changed, 209 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile -index edb22c57f11d..936cd1989463 100644 +index 3b2e11a82df2..ccfac417ca10 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile -@@ -49,6 +49,14 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +@@ -51,6 +51,13 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb -+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905l-p271.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0049-WIP-dt-bindings-arm-amlogic-add-S905L-and-p271-refer.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0061-WIP-dt-bindings-arm-amlogic-add-GXLX-S905L-p271-refe.patch similarity index 51% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0049-WIP-dt-bindings-arm-amlogic-add-S905L-and-p271-refer.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0061-WIP-dt-bindings-arm-amlogic-add-GXLX-S905L-p271-refe.patch index 7a84ad883e..967d653fdc 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0049-WIP-dt-bindings-arm-amlogic-add-S905L-and-p271-refer.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0061-WIP-dt-bindings-arm-amlogic-add-GXLX-S905L-p271-refe.patch @@ -1,12 +1,12 @@ -From 1d5c42d5f84a1b022365b4ae00c3c6325a4b8f16 Mon Sep 17 00:00:00 2001 +From 07f53466522aa22a385caaa7893dc247441d863a Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 1 Jan 2024 07:13:19 +0000 -Subject: [PATCH 49/53] WIP: dt-bindings: arm: amlogic: add S905L and p271 +Subject: [PATCH 61/69] WIP: dt-bindings: arm: amlogic: add GXLX/S905L/p271 reference board -Add bindings for the Amlogic S905L SoC and reference design board. S905L is similar -to P281 (S905W) and derived from P212 (S905X) but with silicon differences to omit -VP9 codec support and using a Mali 450-MP2 (not MP3). +Add bindings for the Amlogic GXLX based S905L SoC and P271 reference design board. The +S905L is a cost engineered design similar to the P281 (S905W) and is derived from P212 +(S905X). S905L omits VP9 codec support and uses Mali 450-MP2 (not MP3). Signed-off-by: Christian Hewitt --- @@ -14,21 +14,21 @@ Signed-off-by: Christian Hewitt 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml -index 73598f7992fd..515d58587f7c 100644 +index 5d52065abe72..79deb7bfe698 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml -@@ -81,6 +81,13 @@ properties: - - const: amlogic,s805x +@@ -108,6 +108,13 @@ properties: + - const: amlogic,s905d - const: amlogic,meson-gxl -+ - description: Boards with the Amlogic Meson GXL S905L SoC ++ - description: Boards with the Amlogic Meson GXLX S905L SoC + items: + - enum: + - amlogic,p271 + - const: amlogic,s905l -+ - const: amlogic,meson-gxl ++ - const: amlogic,meson-gxlx + - - description: Boards with the Amlogic Meson GXL S905W SoC + - description: Boards with the Amlogic Meson GXM S912 SoC items: - enum: -- diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0050-WIP-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0062-WIP-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch similarity index 74% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0050-WIP-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0062-WIP-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch index 4d95643b89..ca894758cb 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0050-WIP-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0062-WIP-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch @@ -1,11 +1,11 @@ -From f5ab209b7240f1251e100f9e7919f165bdb26f96 Mon Sep 17 00:00:00 2001 +From 37c40fe68da65de963064481ce98e1fb08ed9d06 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 1 Jan 2024 07:48:39 +0000 -Subject: [PATCH 50/53] WIP: soc: amlogic: meson-gx-socinfo: Add S905L ID +Subject: [PATCH 62/69] WIP: soc: amlogic: meson-gx-socinfo: Add S905L ID -Add the S905L SoC id observed in several P271 boards: +Add the S905L SoC ID observed in several P271 boards: -LibreELEC kernel: soc soc0: Amlogic Meson GXLX (S905L) Revision 26:a (c1:2) Detected +kernel: soc soc0: Amlogic Meson GXLX (S905L) Revision 26:a (c1:2) Detected Signed-off-by: Christian Hewitt --- diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0051-WIP-dt-bindings-iio-adc-amlogic-meson-saradc-Add-GXL.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0063-WIP-dt-bindings-iio-adc-amlogic-meson-saradc-add-GXL.patch similarity index 77% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0051-WIP-dt-bindings-iio-adc-amlogic-meson-saradc-Add-GXL.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0063-WIP-dt-bindings-iio-adc-amlogic-meson-saradc-add-GXL.patch index 4ed165f218..a2d4c0fad2 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0051-WIP-dt-bindings-iio-adc-amlogic-meson-saradc-Add-GXL.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0063-WIP-dt-bindings-iio-adc-amlogic-meson-saradc-add-GXL.patch @@ -1,12 +1,11 @@ -From b2cbf810a3310389b2691797e487396aa1f621da Mon Sep 17 00:00:00 2001 +From 357f7ec77196b67ef2c467b96b73e3267c9f2b39 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 23 Mar 2024 20:38:59 +0100 -Subject: [PATCH 51/53] WIP: dt-bindings: iio: adc: amlogic,meson-saradc: Add +Subject: [PATCH 63/69] WIP: dt-bindings: iio: adc: amlogic,meson-saradc: add GXLX SoC compatible -Add a compatible string for the GXLX SoC. It's very similar to GXL but -has three additional bits in MESON_SAR_ADC_REG12 for the three MPLL -clocks. +Add a compatible string for the GXLX SoC. GXLX is very similar to GXL but has three +additional bits in MESON_SAR_ADC_REG12 for the three MPLL clocks. Signed-off-by: Martin Blumenstingl --- diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0052-WIP-iio-adc-meson-add-support-for-the-GXLX-SoC.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0064-WIP-iio-adc-meson-add-support-for-the-GXLX-SoC.patch similarity index 87% rename from projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0052-WIP-iio-adc-meson-add-support-for-the-GXLX-SoC.patch rename to projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0064-WIP-iio-adc-meson-add-support-for-the-GXLX-SoC.patch index 3e79ff315e..f24bf1e112 100644 --- a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0052-WIP-iio-adc-meson-add-support-for-the-GXLX-SoC.patch +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0064-WIP-iio-adc-meson-add-support-for-the-GXLX-SoC.patch @@ -1,14 +1,12 @@ -From a3fe76499d3b186e1b964cc24fe49afc0c12eca7 Mon Sep 17 00:00:00 2001 +From e807a7ea1ca1eefcb39eafc9d4bfe88226fd93e6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 23 Mar 2024 20:44:41 +0100 -Subject: [PATCH 52/53] WIP: iio: adc: meson: add support for the GXLX SoC +Subject: [PATCH 64/69] WIP: iio: adc: meson: add support for the GXLX SoC -The SARADC IP on the GXLX SoC itself is identical to the one found on -GXL SoCs. However, GXLX SoCs require poking the first three bits in the -MESON_SAR_ADC_REG12 register to get the three MPLL clocks (used as clock -generators for the audio frequencies) to work. - -WiP: the purpose of these three bits needs to be clarified +The SARADC IP on GXLX is identical to the one found on GXL SoCs: except GXLX requires +poking the first three bits in the MESON_SAR_ADC_REG12 register to get the three MPLL +clocks (used as clock generators for the audio frequencies) to work. Register values +are taken from the vendor kernel. Signed-off-by: Martin Blumenstingl --- diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0065-WIP-dt-bindings-media-amlogic-gx-vdec-add-the-GXLX-S.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0065-WIP-dt-bindings-media-amlogic-gx-vdec-add-the-GXLX-S.patch new file mode 100644 index 0000000000..c2091aede4 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0065-WIP-dt-bindings-media-amlogic-gx-vdec-add-the-GXLX-S.patch @@ -0,0 +1,31 @@ +From da8832786aa94197e7bcf420aa78c5283b055dad Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sat, 1 Jun 2024 15:46:42 +0000 +Subject: [PATCH 65/69] WIP: dt-bindings: media: amlogic,gx-vdec: add the GXLX + SoC family + +The GXLX SoC is a GXL variant that omits VP9 codec support. While we are here, add +S905W and S905Y as GXL chips and sort the GXL comment. + +Signed-off-by: Christian Hewitt +--- + Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml +index 55930f6107c9..47dce75aeae6 100644 +--- a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml ++++ b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml +@@ -31,7 +31,8 @@ properties: + - items: + - enum: + - amlogic,gxbb-vdec # GXBB (S905) +- - amlogic,gxl-vdec # GXL (S905X, S905D) ++ - amlogic,gxl-vdec # GXL (S905D, S905W, S905X, S905Y) ++ - amlogic,gxlx-vdec # GXLX (S905L) + - amlogic,gxm-vdec # GXM (S912) + - const: amlogic,gx-vdec + - enum: +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0066-WIP-media-meson-vdec-add-GXLX-SoC-platform.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0066-WIP-media-meson-vdec-add-GXLX-SoC-platform.patch new file mode 100644 index 0000000000..d464e2a090 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0066-WIP-media-meson-vdec-add-GXLX-SoC-platform.patch @@ -0,0 +1,102 @@ +From 1b994ed915398729aa50c709628176f928b2f0dc Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sat, 1 Jun 2024 15:51:07 +0000 +Subject: [PATCH 66/69] WIP: media: meson: vdec: add GXLX SoC platform + +The GXLX SoC is a GXL variant that omits VP9 codec support. + +Signed-off-by: Christian Hewitt +--- + drivers/staging/media/meson/vdec/vdec.c | 2 ++ + .../staging/media/meson/vdec/vdec_platform.c | 34 +++++++++++++++++++ + .../staging/media/meson/vdec/vdec_platform.h | 2 ++ + 3 files changed, 38 insertions(+) + +diff --git a/drivers/staging/media/meson/vdec/vdec.c b/drivers/staging/media/meson/vdec/vdec.c +index de3e0345ab7c..5e5b296f93ba 100644 +--- a/drivers/staging/media/meson/vdec/vdec.c ++++ b/drivers/staging/media/meson/vdec/vdec.c +@@ -982,6 +982,8 @@ static const struct of_device_id vdec_dt_match[] = { + .data = &vdec_platform_gxm }, + { .compatible = "amlogic,gxl-vdec", + .data = &vdec_platform_gxl }, ++ { .compatible = "amlogic,gxlx-vdec", ++ .data = &vdec_platform_gxlx }, + { .compatible = "amlogic,g12a-vdec", + .data = &vdec_platform_g12a }, + { .compatible = "amlogic,sm1-vdec", +diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c +index 083adf0d07d9..870e61dedd81 100644 +--- a/drivers/staging/media/meson/vdec/vdec_platform.c ++++ b/drivers/staging/media/meson/vdec/vdec_platform.c +@@ -82,6 +82,34 @@ static const struct amvdec_format vdec_formats_gxl[] = { + }, + }; + ++static const struct amvdec_format vdec_formats_gxlx[] = { ++ { ++ .pixfmt = V4L2_PIX_FMT_HEVC, ++ .min_buffers = 4, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_hevc_ops, ++ .codec_ops = &codec_hevc_ops, ++ .firmware_path = "meson/vdec/gxl_hevc.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, ++ }, { ++ .pixfmt = V4L2_PIX_FMT_H264, ++ .min_buffers = 2, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_1_ops, ++ .codec_ops = &codec_h264_ops, ++ .firmware_path = "meson/vdec/gxl_h264.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, ++ }, ++}; ++ + static const struct amvdec_format vdec_formats_gxm[] = { + { + .pixfmt = V4L2_PIX_FMT_VP9, +@@ -190,6 +218,12 @@ const struct vdec_platform vdec_platform_gxl = { + .revision = VDEC_REVISION_GXL, + }; + ++const struct vdec_platform vdec_platform_gxlx = { ++ .formats = vdec_formats_gxlx, ++ .num_formats = ARRAY_SIZE(vdec_formats_gxlx), ++ .revision = VDEC_REVISION_GXLX, ++}; ++ + const struct vdec_platform vdec_platform_gxm = { + .formats = vdec_formats_gxm, + .num_formats = ARRAY_SIZE(vdec_formats_gxm), +diff --git a/drivers/staging/media/meson/vdec/vdec_platform.h b/drivers/staging/media/meson/vdec/vdec_platform.h +index 731877a771f4..88ca4a9db8a8 100644 +--- a/drivers/staging/media/meson/vdec/vdec_platform.h ++++ b/drivers/staging/media/meson/vdec/vdec_platform.h +@@ -14,6 +14,7 @@ struct amvdec_format; + enum vdec_revision { + VDEC_REVISION_GXBB, + VDEC_REVISION_GXL, ++ VDEC_REVISION_GXLX, + VDEC_REVISION_GXM, + VDEC_REVISION_G12A, + VDEC_REVISION_SM1, +@@ -28,6 +29,7 @@ struct vdec_platform { + extern const struct vdec_platform vdec_platform_gxbb; + extern const struct vdec_platform vdec_platform_gxm; + extern const struct vdec_platform vdec_platform_gxl; ++extern const struct vdec_platform vdec_platform_gxlx; + extern const struct vdec_platform vdec_platform_g12a; + extern const struct vdec_platform vdec_platform_sm1; + +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0067-WIP-arm64-dts-meson-add-p271-support.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0067-WIP-arm64-dts-meson-add-p271-support.patch new file mode 100644 index 0000000000..5e5e0cd1a9 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0067-WIP-arm64-dts-meson-add-p271-support.patch @@ -0,0 +1,90 @@ +From 85fd969f38153362aa6859fdd28f71367f4ee53e Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Mon, 1 Jan 2024 07:40:15 +0000 +Subject: [PATCH 67/69] WIP: arm64: dts: meson: add p271 support + +Add a device-tree for the GXLX Amlogic P271 (S905L) reference design board. This +is a low-cost design similar to P281 (S905W) and P212 (S905X) but with silicon +differences to omit VP9 and use Mali 450-MP2 (not MP3). The SoC is marked with +S905L and "2" (believed to denote MP2) resulting in some chip distributor stock +lists (and subsequent box vendor marketing) describing it as an S905L2 chip. + +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/Makefile | 1 + + .../dts/amlogic/meson-gxlx-s905l-p271.dts | 51 +++++++++++++++++++ + 2 files changed, 52 insertions(+) + create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts + +diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile +index ccfac417ca10..d106a18c39a8 100644 +--- a/arch/arm64/boot/dts/amlogic/Makefile ++++ b/arch/arm64/boot/dts/amlogic/Makefile +@@ -67,6 +67,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb ++dtb-$(CONFIG_ARCH_MESON) += meson-gxlx-s905l-p271.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-gxm-gt1-ultimate.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts b/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts +new file mode 100644 +index 000000000000..1221f4545130 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2024 Christian Hewitt ++ */ ++ ++/dts-v1/; ++ ++#include "meson-gxl-s905x.dtsi" ++#include "meson-gx-p23x-q20x.dtsi" ++ ++/ { ++ compatible = "amlogic,p271", "amlogic,s905l", "amlogic,meson-gxlx"; ++ model = "Amlogic Meson GXLX (S905L) P271 Development Board"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ sound { ++ model = "P271"; ++ }; ++}; ++ ++&apb { ++ mali: gpu@c0000 { ++ /* Mali 450-MP2 */ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "gp", "gpmmu", "pp", "pmu", ++ "pp0", "ppmmu0", "pp1", "ppmmu1"; ++ }; ++}; ++ ++&saradc { ++ compatible = "amlogic,meson-gxlx-saradc", "amlogic,meson-saradc"; ++}; ++ ++&usb { ++ dr_mode = "host"; ++}; ++ ++&vdec { ++ compatible = "amlogic,gxlx-vdec", "amlogic,gx-vdec"; ++}; +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0068-WIP-ASoC-Add-support-for-ti-pcm5242-to-the-pcm512x-d.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0068-WIP-ASoC-Add-support-for-ti-pcm5242-to-the-pcm512x-d.patch new file mode 100644 index 0000000000..6465bb7887 --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0068-WIP-ASoC-Add-support-for-ti-pcm5242-to-the-pcm512x-d.patch @@ -0,0 +1,51 @@ +From c502027cafd182fd76467b76c7c271706ceab466 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sun, 26 May 2024 12:08:54 +0000 +Subject: [PATCH 68/69] WIP: ASoC: Add support for ti,pcm5242 to the pcm512x + driver + +Add compatibles to enable support for the ti,pcm5242 DAC chip in the +pcm512x driver. + +Signed-off-by: Christian Hewitt +--- + Documentation/devicetree/bindings/sound/pcm512x.txt | 2 +- + sound/soc/codecs/pcm512x-i2c.c | 2 ++ + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt +index 77006a4aec4a..47878a6df608 100644 +--- a/Documentation/devicetree/bindings/sound/pcm512x.txt ++++ b/Documentation/devicetree/bindings/sound/pcm512x.txt +@@ -6,7 +6,7 @@ on the board). The TAS575x devices only support I2C. + Required properties: + + - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141", +- "ti,pcm5142", "ti,tas5754" or "ti,tas5756" ++ "ti,pcm5142", "ti,pcm5242", "ti,tas5754" or "ti,tas5756" + + - reg : the I2C address of the device for I2C, the chip select + number for SPI. +diff --git a/sound/soc/codecs/pcm512x-i2c.c b/sound/soc/codecs/pcm512x-i2c.c +index 4be476a280e1..92bcf5179779 100644 +--- a/sound/soc/codecs/pcm512x-i2c.c ++++ b/sound/soc/codecs/pcm512x-i2c.c +@@ -39,6 +39,7 @@ static const struct i2c_device_id pcm512x_i2c_id[] = { + { "pcm5122", }, + { "pcm5141", }, + { "pcm5142", }, ++ { "pcm5242", }, + { "tas5754", }, + { "tas5756", }, + { } +@@ -51,6 +52,7 @@ static const struct of_device_id pcm512x_of_match[] = { + { .compatible = "ti,pcm5122", }, + { .compatible = "ti,pcm5141", }, + { .compatible = "ti,pcm5142", }, ++ { .compatible = "ti,pcm5242", }, + { .compatible = "ti,tas5754", }, + { .compatible = "ti,tas5756", }, + { } +-- +2.34.1 + diff --git a/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0069-WIP-arm64-dts-meson-add-Odroid-C2-HiFi-Shield-boards.patch b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0069-WIP-arm64-dts-meson-add-Odroid-C2-HiFi-Shield-boards.patch new file mode 100644 index 0000000000..d7c8d7e4fc --- /dev/null +++ b/projects/Amlogic/devices/AMLGX/patches/linux/amlogic-0069-WIP-arm64-dts-meson-add-Odroid-C2-HiFi-Shield-boards.patch @@ -0,0 +1,935 @@ +From 81f79be44cb62b75eadf9acdb61f877d97ee9f7c Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sun, 26 May 2024 12:53:07 +0000 +Subject: [PATCH 69/69] WIP: arm64: dts: meson: add Odroid-C2 HiFi-Shield + boards + +Add experimental device-tree files for Odroid C2 with HiFi-Shield+ (pcm5102a) +and HiFi-Shield2 (pcm5242) mezzanine boards. + +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/Makefile | 4 + + .../meson-gxbb-odroidc2-hifishield.dts | 443 +++++++++++++++++ + .../meson-gxbb-odroidc2-hifishield2.dts | 447 ++++++++++++++++++ + 3 files changed, 894 insertions(+) + create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts + create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts + +diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile +index d106a18c39a8..e634b37a5af1 100644 +--- a/arch/arm64/boot/dts/amlogic/Makefile ++++ b/arch/arm64/boot/dts/amlogic/Makefile +@@ -96,3 +96,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb + # Overlays + meson-g12a-fbx8am-brcm-dtbs := meson-g12a-fbx8am.dtb meson-g12a-fbx8am-brcm.dtbo + meson-g12a-fbx8am-realtek-dtbs := meson-g12a-fbx8am.dtb meson-g12a-fbx8am-realtek.dtbo ++ ++# Experimental ++dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2-hifishield.dtb ++dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2-hifishield2.dtb +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts +new file mode 100644 +index 000000000000..906adc1f622b +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts +@@ -0,0 +1,443 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016 Andreas Färber ++ * Copyright (c) 2016 BayLibre, Inc. ++ * Author: Kevin Hilman ++ */ ++ ++/dts-v1/; ++ ++#include "meson-gxbb.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; ++ model = "Hardkernel ODROID-C2"; ++ ++ aliases { ++ serial0 = &uart_AO; ++ ethernet0 = ðmac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x80000000>; ++ }; ++ ++ spdif_dit: audio-codec-0 { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ status = "okay"; ++ sound-name-prefix = "DIT"; ++ }; ++ ++ usb_otg_pwr: regulator-usb-pwrs { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "USB_OTG_PWR"; ++ ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ ++ /* ++ * signal name from schematics: PWREN ++ */ ++ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ /* ++ * signal name from schematics: USB_POWER ++ */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led-blue { ++ label = "c2:blue:alive"; ++ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "heartbeat"; ++ default-state = "off"; ++ }; ++ }; ++ ++ p5v0: regulator-p5v0 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "P5V0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ hdmi_p5v0: regulator-hdmi-p5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "HDMI_P5V0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ /* AP2331SA-7 */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ tflash_vdd: regulator-tflash-vdd { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "TFLASH_VDD"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ /* ++ * signal name from schematics: TFLASH_VDD_EN ++ */ ++ gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ /* U16 RT9179GB */ ++ vin-supply = <&vddio_ao3v3>; ++ }; ++ ++ tf_io: gpio-regulator-tf-io { ++ compatible = "regulator-gpio"; ++ ++ regulator-name = "TF_IO"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ /* ++ * signal name from schematics: TF_3V3N_1V8_EN ++ */ ++ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0>; ++ ++ states = <3300000 0>, ++ <1800000 1>; ++ /* U12/U13 RT9179GB */ ++ vin-supply = <&vddio_ao3v3>; ++ }; ++ ++ vcc1v8: regulator-vcc1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ /* U18 RT9179GB */ ++ vin-supply = <&vddio_ao3v3>; ++ }; ++ ++ vcc3v3: regulator-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vddio_ao1v8: regulator-vddio-ao1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ /* U17 RT9179GB */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ vddio_ao3v3: regulator-vddio-ao3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ /* U11 MP2161GJ-C499 */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ ddr3_1v5: regulator-ddr3-1v5 { ++ compatible = "regulator-fixed"; ++ regulator-name = "DDR3_1V5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ /* U15 MP2161GJ-C499 */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_connector_in: endpoint { ++ remote-endpoint = <&hdmi_tx_tmds_out>; ++ }; ++ }; ++ }; ++ ++ sound { ++ compatible = "amlogic,gx-sound-card"; ++ model = "ODROID-C2"; ++ assigned-clocks = <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>, ++ <&clkc CLKID_MPLL2>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ ++ dai-link-0 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; ++ }; ++ }; ++ ++ dai-link-3 { ++ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; ++ ++ codec-0 { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; ++ ++ dai-link-4 { ++ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; ++ ++ codec-0 { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&aiu { ++ status = "okay"; ++ pinctrl-0 = <&spdif_out_ao_6_pins &i2s_am_clk_pins &i2s_out_ao_clk_pins &i2s_out_lr_clk_pins &i2s_out_ch01_ao_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++ðmac { ++ status = "okay"; ++ pinctrl-0 = <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ phy-handle = <ð_phy0>; ++ phy-mode = "rgmii"; ++ ++ amlogic,tx-delay-ns = <2>; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ eth_phy0: ethernet-phy@0 { ++ /* Realtek RTL8211F (0x001cc916) */ ++ reg = <0>; ++ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <80000>; ++ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; ++ ++ interrupt-parent = <&gpio_intc>; ++ /* MAC_INTR on GPIOZ_15 */ ++ interrupts = <29 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ }; ++}; ++ ++&hdmi_tx { ++ status = "okay"; ++ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; ++ pinctrl-names = "default"; ++ hdmi-supply = <&hdmi_p5v0>; ++}; ++ ++&hdmi_tx_tmds_port { ++ hdmi_tx_tmds_out: endpoint { ++ remote-endpoint = <&hdmi_connector_in>; ++ }; ++}; ++ ++&i2c_A { ++ status = "okay"; ++ pinctrl-0 = <&i2c_a_pins>; ++ pinctrl-names = "default"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pcm5102a: pcm5102a@4c { ++ compatible = "ti,pcm5102a"; ++ reg = <0x4c>; ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++&ir { ++ status = "okay"; ++ pinctrl-0 = <&remote_input_ao_pins>; ++ pinctrl-names = "default"; ++ linux,rc-map-name = "rc-odroid"; ++}; ++ ++&gpio_ao { ++ gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", ++ "USB HUB nRESET", "USB OTG Power En", ++ "SPDIF_OUTPUT", "IR In", "I2S_MCLK", ++ "I2S_SCLK", "I2S_LRCLK", "I2S_DATA_OUTPUT", ++ "HDMI CEC", "SYS LED", ++ /* GPIO_TEST_N */ ++ ""; ++}; ++ ++&gpio { ++ gpio-line-names = /* Bank GPIOZ */ ++ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", ++ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", ++ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", ++ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", ++ "Eth PHY nRESET", "Eth PHY Intc", ++ /* Bank GPIOH */ ++ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "", ++ /* Bank BOOT */ ++ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", ++ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", ++ "eMMC Reset", "eMMC CMD", ++ "", "", "", "", "", "", "", ++ /* Bank CARD */ ++ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", ++ "SDCard D3", "SDCard D2", "SDCard Det", ++ /* Bank GPIODV */ ++ "", "", "", "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", "", ++ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", ++ "PWM D", "PWM B", ++ /* Bank GPIOY */ ++ "Revision Bit0", "Revision Bit1", "", ++ "J2 Header Pin35", "", "", "", "J2 Header Pin36", ++ "J2 Header Pin31", "", "", "", "TF VDD En", ++ "J2 Header Pin32", "J2 Header Pin26", "", "", ++ /* Bank GPIOX */ ++ "J2 Header Pin29", "J2 Header Pin24", ++ "J2 Header Pin23", "J2 Header Pin22", ++ "J2 Header Pin21", "J2 Header Pin18", ++ "J2 Header Pin33", "J2 Header Pin19", ++ "J2 Header Pin16", "J2 Header Pin15", ++ "J2 Header Pin12", "J2 Header Pin13", ++ "J2 Header Pin8", "J2 Header Pin10", ++ "", "", "", "", "", ++ "J2 Header Pin11", "", "J2 Header Pin7", "", ++ /* Bank GPIOCLK */ ++ "", "", "", ""; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vcc1v8>; ++}; ++ ++&scpi_clocks { ++ status = "disabled"; ++}; ++ ++/* SD */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-ddr50; ++ max-frequency = <100000000>; ++ disable-wp; ++ ++ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; ++ ++ vmmc-supply = <&tflash_vdd>; ++ vqmmc-supply = <&tf_io>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vcc3v3>; ++ vqmmc-supply = <&vcc1v8>; ++}; ++ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb0_phy { ++ status = "disabled"; ++ phy-supply = <&usb_otg_pwr>; ++}; ++ ++&usb1_phy { ++ status = "okay"; ++ phy-supply = <&usb_otg_pwr>; ++}; ++ ++&usb0 { ++ status = "disabled"; ++}; ++ ++&usb1 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub@1 { ++ /* Genesys Logic GL852G USB 2.0 hub */ ++ compatible = "usb5e3,610"; ++ reg = <1>; ++ vdd-supply = <&p5v0>; ++ reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts +new file mode 100644 +index 000000000000..91697f5b5cd7 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts +@@ -0,0 +1,447 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016 Andreas Färber ++ * Copyright (c) 2016 BayLibre, Inc. ++ * Author: Kevin Hilman ++ */ ++ ++/dts-v1/; ++ ++#include "meson-gxbb.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; ++ model = "Hardkernel ODROID-C2"; ++ ++ aliases { ++ serial0 = &uart_AO; ++ ethernet0 = ðmac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x80000000>; ++ }; ++ ++ spdif_dit: audio-codec-0 { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ status = "okay"; ++ sound-name-prefix = "DIT"; ++ }; ++ ++ usb_otg_pwr: regulator-usb-pwrs { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "USB_OTG_PWR"; ++ ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ ++ /* ++ * signal name from schematics: PWREN ++ */ ++ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ /* ++ * signal name from schematics: USB_POWER ++ */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ led-blue { ++ label = "c2:blue:alive"; ++ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "heartbeat"; ++ default-state = "off"; ++ }; ++ }; ++ ++ p5v0: regulator-p5v0 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "P5V0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ hdmi_p5v0: regulator-hdmi-p5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "HDMI_P5V0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ /* AP2331SA-7 */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ tflash_vdd: regulator-tflash-vdd { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "TFLASH_VDD"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ /* ++ * signal name from schematics: TFLASH_VDD_EN ++ */ ++ gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ /* U16 RT9179GB */ ++ vin-supply = <&vddio_ao3v3>; ++ }; ++ ++ tf_io: gpio-regulator-tf-io { ++ compatible = "regulator-gpio"; ++ ++ regulator-name = "TF_IO"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ /* ++ * signal name from schematics: TF_3V3N_1V8_EN ++ */ ++ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0>; ++ ++ states = <3300000 0>, ++ <1800000 1>; ++ /* U12/U13 RT9179GB */ ++ vin-supply = <&vddio_ao3v3>; ++ }; ++ ++ vcc1v8: regulator-vcc1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ /* U18 RT9179GB */ ++ vin-supply = <&vddio_ao3v3>; ++ }; ++ ++ vcc3v3: regulator-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vddio_ao1v8: regulator-vddio-ao1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ /* U17 RT9179GB */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ vddio_ao3v3: regulator-vddio-ao3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ /* U11 MP2161GJ-C499 */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ ddr3_1v5: regulator-ddr3-1v5 { ++ compatible = "regulator-fixed"; ++ regulator-name = "DDR3_1V5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ /* U15 MP2161GJ-C499 */ ++ vin-supply = <&p5v0>; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_connector_in: endpoint { ++ remote-endpoint = <&hdmi_tx_tmds_out>; ++ }; ++ }; ++ }; ++ ++ sound { ++ compatible = "amlogic,gx-sound-card"; ++ model = "ODROID-C2"; ++ assigned-clocks = <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>, ++ <&clkc CLKID_MPLL2>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ ++ dai-link-0 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; ++ }; ++ }; ++ ++ dai-link-3 { ++ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; ++ ++ codec-0 { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; ++ ++ dai-link-4 { ++ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; ++ ++ codec-0 { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&aiu { ++ status = "okay"; ++ pinctrl-0 = <&spdif_out_ao_6_pins &i2s_am_clk_pins &i2s_out_ao_clk_pins &i2s_out_lr_clk_pins &i2s_out_ch01_ao_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&cec_AO { ++ status = "okay"; ++ pinctrl-0 = <&ao_cec_pins>; ++ pinctrl-names = "default"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++ðmac { ++ status = "okay"; ++ pinctrl-0 = <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ phy-handle = <ð_phy0>; ++ phy-mode = "rgmii"; ++ ++ amlogic,tx-delay-ns = <2>; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ eth_phy0: ethernet-phy@0 { ++ /* Realtek RTL8211F (0x001cc916) */ ++ reg = <0>; ++ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <80000>; ++ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; ++ ++ interrupt-parent = <&gpio_intc>; ++ /* MAC_INTR on GPIOZ_15 */ ++ interrupts = <29 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ }; ++}; ++ ++&hdmi_tx { ++ status = "okay"; ++ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; ++ pinctrl-names = "default"; ++ hdmi-supply = <&hdmi_p5v0>; ++}; ++ ++&hdmi_tx_tmds_port { ++ hdmi_tx_tmds_out: endpoint { ++ remote-endpoint = <&hdmi_connector_in>; ++ }; ++}; ++ ++&i2c_A { ++ status = "okay"; ++ pinctrl-0 = <&i2c_a_pins>; ++ pinctrl-names = "default"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pcm5242: pcm5242@4c { ++ compatible = "ti,pcm5242"; ++ reg = <0x4c>; ++ #sound-dai-cells = <0>; ++ ++ AVDD-supply = <&vddio_ao3v3>; ++ DVDD-supply = <&vddio_ao3v3>; ++ CPVDD-supply = <&vddio_ao3v3>; ++ }; ++}; ++ ++&ir { ++ status = "okay"; ++ pinctrl-0 = <&remote_input_ao_pins>; ++ pinctrl-names = "default"; ++ linux,rc-map-name = "rc-odroid"; ++}; ++ ++&gpio_ao { ++ gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", ++ "USB HUB nRESET", "USB OTG Power En", ++ "SPDIF_OUTPUT", "IR In", "I2S_MCLK", ++ "I2S_SCLK", "I2S_LRCLK", "I2S_DATA_OUTPUT", ++ "HDMI CEC", "SYS LED", ++ /* GPIO_TEST_N */ ++ ""; ++}; ++ ++&gpio { ++ gpio-line-names = /* Bank GPIOZ */ ++ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", ++ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", ++ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", ++ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", ++ "Eth PHY nRESET", "Eth PHY Intc", ++ /* Bank GPIOH */ ++ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "", ++ /* Bank BOOT */ ++ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", ++ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", ++ "eMMC Reset", "eMMC CMD", ++ "", "", "", "", "", "", "", ++ /* Bank CARD */ ++ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", ++ "SDCard D3", "SDCard D2", "SDCard Det", ++ /* Bank GPIODV */ ++ "", "", "", "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", "", ++ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", ++ "PWM D", "PWM B", ++ /* Bank GPIOY */ ++ "Revision Bit0", "Revision Bit1", "", ++ "J2 Header Pin35", "", "", "", "J2 Header Pin36", ++ "J2 Header Pin31", "", "", "", "TF VDD En", ++ "J2 Header Pin32", "J2 Header Pin26", "", "", ++ /* Bank GPIOX */ ++ "J2 Header Pin29", "J2 Header Pin24", ++ "J2 Header Pin23", "J2 Header Pin22", ++ "J2 Header Pin21", "J2 Header Pin18", ++ "J2 Header Pin33", "J2 Header Pin19", ++ "J2 Header Pin16", "J2 Header Pin15", ++ "J2 Header Pin12", "J2 Header Pin13", ++ "J2 Header Pin8", "J2 Header Pin10", ++ "", "", "", "", "", ++ "J2 Header Pin11", "", "J2 Header Pin7", "", ++ /* Bank GPIOCLK */ ++ "", "", "", ""; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vcc1v8>; ++}; ++ ++&scpi_clocks { ++ status = "disabled"; ++}; ++ ++/* SD */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-ddr50; ++ max-frequency = <100000000>; ++ disable-wp; ++ ++ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; ++ ++ vmmc-supply = <&tflash_vdd>; ++ vqmmc-supply = <&tf_io>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vcc3v3>; ++ vqmmc-supply = <&vcc1v8>; ++}; ++ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb0_phy { ++ status = "disabled"; ++ phy-supply = <&usb_otg_pwr>; ++}; ++ ++&usb1_phy { ++ status = "okay"; ++ phy-supply = <&usb_otg_pwr>; ++}; ++ ++&usb0 { ++ status = "disabled"; ++}; ++ ++&usb1 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub@1 { ++ /* Genesys Logic GL852G USB 2.0 hub */ ++ compatible = "usb5e3,610"; ++ reg = <1>; ++ vdd-supply = <&p5v0>; ++ reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; ++ }; ++}; +-- +2.34.1 + diff --git a/projects/Amlogic/linux/linux.aarch64.conf b/projects/Amlogic/linux/linux.aarch64.conf index fc3f856ff3..7d1eccfe8b 100644 --- a/projects/Amlogic/linux/linux.aarch64.conf +++ b/projects/Amlogic/linux/linux.aarch64.conf @@ -1,15 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.8.0 Kernel Configuration +# Linux/arm64 6.9.3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-libreelec-linux-gnu-gcc-13.2.0 (GCC) 13.2.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=130200 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=24100 +CONFIG_AS_VERSION=24200 CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=24100 +CONFIG_LD_VERSION=24200 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -263,7 +263,6 @@ CONFIG_PROFILING=y # # CONFIG_KEXEC is not set # CONFIG_KEXEC_FILE is not set -# CONFIG_CRASH_DUMP is not set # end of Kexec and crash features # end of General setup @@ -271,7 +270,6 @@ CONFIG_ARM64=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_64BIT=y CONFIG_MMU=y -CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_CONT_PTE_SHIFT=4 CONFIG_ARM64_CONT_PMD_SHIFT=4 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 @@ -399,6 +397,7 @@ CONFIG_ARM64_4K_PAGES=y # CONFIG_ARM64_64K_PAGES is not set # CONFIG_ARM64_VA_BITS_39 is not set CONFIG_ARM64_VA_BITS_48=y +# CONFIG_ARM64_VA_BITS_52 is not set CONFIG_ARM64_VA_BITS=48 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PA_BITS=48 @@ -507,6 +506,7 @@ CONFIG_RANDOMIZE_BASE=y CONFIG_RANDOMIZE_MODULE_REGION_FULL=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_ARM64_CONTPTE=y # end of Kernel Features # @@ -589,8 +589,8 @@ CONFIG_ARM_SCPI_CPUFREQ=y # end of CPU Frequency scaling # end of CPU Power Management -CONFIG_HAVE_KVM=y # CONFIG_VIRTUALIZATION is not set +CONFIG_CPU_MITIGATIONS=y # # General architecture-dependent options @@ -623,6 +623,7 @@ CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_EVENTS_NMI=y @@ -673,8 +674,11 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -877,7 +881,6 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 @@ -929,7 +932,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set CONFIG_TLS=y @@ -1151,6 +1153,7 @@ CONFIG_NETFILTER_XT_MATCH_STATE=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV4 is not set # CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set @@ -1173,12 +1176,13 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_IP_NF_TARGET_ECN is not set # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set -# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARPFILTER is not set # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV6 is not set # CONFIG_NF_TPROXY_IPV6 is not set # CONFIG_NF_DUP_IPV6 is not set @@ -1323,7 +1327,6 @@ CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y # CONFIG_BT_BNEP is not set CONFIG_BT_HIDP=m -CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_LE_L2CAP_ECRED=y # CONFIG_BT_LEDS is not set @@ -1430,6 +1433,7 @@ CONFIG_ETHTOOL_NETLINK=y # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y @@ -1655,7 +1659,6 @@ CONFIG_MTD_CFI_I2=y # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # end of Mapping drivers for chip access @@ -2171,6 +2174,9 @@ CONFIG_MICROSEMI_PHY=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y # CONFIG_RENESAS_PHY is not set @@ -2437,11 +2443,13 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192EE=m CONFIG_RTL8821AE=m CONFIG_RTL8192CU=m +CONFIG_RTL8192DU=m CONFIG_RTLWIFI=m CONFIG_RTLWIFI_PCI=m CONFIG_RTLWIFI_USB=m CONFIG_RTLWIFI_DEBUG=y CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8192D_COMMON=m CONFIG_RTL8723_COMMON=m CONFIG_RTLBTCOEXIST=m CONFIG_RTL8XXXU=m @@ -2668,7 +2676,6 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set @@ -2940,6 +2947,7 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -3137,9 +3145,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DRIVETEMP is not set @@ -3176,6 +3186,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -3225,10 +3236,12 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set @@ -3286,7 +3299,6 @@ CONFIG_THERMAL=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -4299,17 +4311,18 @@ CONFIG_DVB_DUMMY_FE=m # Graphics support # CONFIG_APERTURE_HELPERS=y -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y CONFIG_AUXDISPLAY=y # CONFIG_HD44780 is not set -# CONFIG_IMG_ASCII_LCD is not set -# CONFIG_HT16K33 is not set # CONFIG_LCD2S is not set -CONFIG_TM1628=m # CONFIG_CHARLCD_BL_OFF is not set # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_IMG_ASCII_LCD is not set +# CONFIG_HT16K33 is not set +# CONFIG_MAX6959 is not set +# CONFIG_SEG_LED_GPIO is not set +CONFIG_TM1628=m CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set @@ -4367,15 +4380,15 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -# CONFIG_DRM_PANEL_DSI_CM is not set -# CONFIG_DRM_PANEL_LVDS is not set -# CONFIG_DRM_PANEL_SIMPLE is not set -# CONFIG_DRM_PANEL_EDP is not set # CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set @@ -4385,17 +4398,17 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set -# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set # CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set @@ -4404,8 +4417,8 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set @@ -4416,15 +4429,16 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set @@ -4435,19 +4449,21 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels @@ -4602,6 +4618,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set # CONFIG_BACKLIGHT_PWM is not set # CONFIG_BACKLIGHT_QCOM_WLED is not set @@ -4853,7 +4870,7 @@ CONFIG_SND_SOC_MAX98357A=y # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set CONFIG_SND_SOC_PCM5102A=m -# CONFIG_SND_SOC_PCM512x_I2C is not set +CONFIG_SND_SOC_PCM512x_I2C=m # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_PEB2466 is not set # CONFIG_SND_SOC_RK3328 is not set @@ -5122,6 +5139,7 @@ CONFIG_USB_OTG=y # CONFIG_USB_OTG_FSM is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=m # @@ -5382,6 +5400,7 @@ CONFIG_TYPEC_UCSI=m # CONFIG_TYPEC_MUX_FSA4480 is not set # CONFIG_TYPEC_MUX_GPIO_SBU is not set # CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_IT5205 is not set # CONFIG_TYPEC_MUX_NB7VPQ904M is not set # CONFIG_TYPEC_MUX_PTN36502 is not set # CONFIG_TYPEC_MUX_WCD939X_USBSS is not set @@ -5492,6 +5511,7 @@ CONFIG_LEDS_SYSCON=y # # CONFIG_LEDS_GROUP_MULTICOLOR is not set # CONFIG_LEDS_KTD202X is not set +# CONFIG_LEDS_NCP5623 is not set # CONFIG_LEDS_PWM_MULTICOLOR is not set # CONFIG_LEDS_QCOM_LPG is not set @@ -5734,7 +5754,6 @@ CONFIG_VIDEO_MESON_VDEC=m # StarFive media platform drivers # # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set @@ -5911,6 +5930,7 @@ CONFIG_MESON_GX_SOCINFO=y # # Qualcomm SoC drivers # +# CONFIG_QCOM_PBS is not set # end of Qualcomm SoC drivers # CONFIG_SOC_TI is not set @@ -6069,6 +6089,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set +# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set @@ -6095,6 +6116,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MCP3911 is not set CONFIG_MESON_SARADC=y # CONFIG_NAU7802 is not set +# CONFIG_PAC1934 is not set # CONFIG_QCOM_SPMI_IADC is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SPMI_ADC5 is not set @@ -6110,6 +6132,7 @@ CONFIG_MESON_SARADC=y # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set @@ -6259,6 +6282,7 @@ CONFIG_MESON_SARADC=y # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set # CONFIG_ADF4377 is not set +# CONFIG_ADMFM2000 is not set # CONFIG_ADMV1013 is not set # CONFIG_ADMV1014 is not set # CONFIG_ADMV4420 is not set @@ -6395,6 +6419,7 @@ CONFIG_MESON_SARADC=y # # Magnetometer sensors # +# CONFIG_AF8133J is not set # CONFIG_AK8974 is not set # CONFIG_AK8975 is not set # CONFIG_AK09911 is not set @@ -6562,6 +6587,7 @@ CONFIG_MESON_IRQ_GPIO=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_GPIO is not set CONFIG_RESET_MESON=y CONFIG_RESET_MESON_AUDIO_ARB=y # CONFIG_RESET_SIMPLE is not set @@ -6753,6 +6779,7 @@ CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m # CONFIG_CUSE is not set # CONFIG_VIRTIO_FS is not set +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -6792,11 +6819,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set +# CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -7282,7 +7309,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y @@ -7471,7 +7497,7 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y