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Merge pull request #5326 from heitbaum/mesa2
mesa: fix amd vaapi issue - improved
This commit is contained in:
CvH
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commit
6c91b4c624
@ -1,91 +1,6 @@
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diff -Naur mesa-mesa-21.0.2-old/src/amd/common/ac_surface.c mesa-mesa-21.0.2-new/src/amd/common/ac_surface.c
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diff -Naur mesa-mesa-21.0.2-old/src/amd/common/ac_surface.c mesa-mesa-21.0.2-new/src/amd/common/ac_surface.c
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--- mesa-mesa-21.0.2-old/src/amd/common/ac_surface.c 2021-04-07 18:35:30.000000000 +0200
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--- mesa-mesa-21.0.2-old/src/amd/common/ac_surface.c 2021-04-07 18:35:30.000000000 +0200
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+++ mesa-mesa-21.0.2-new/src/amd/common/ac_surface.c 2021-04-11 11:35:23.939998177 +0200
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+++ mesa-mesa-21.0.2-new/src/amd/common/ac_surface.c 2021-04-11 11:35:23.939998177 +0200
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@@ -2502,10 +2502,6 @@
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{
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surf->dcc_offset = 0;
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surf->display_dcc_offset = 0;
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- if (!surf->htile_offset && !surf->fmask_offset && !surf->cmask_offset) {
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- surf->total_size = surf->surf_size;
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- surf->alignment = surf->surf_alignment;
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- }
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}
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static unsigned eg_tile_split(unsigned tile_split)
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@@ -2804,69 +2800,21 @@
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}
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}
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-static uint32_t ac_surface_get_gfx9_pitch_align(struct radeon_surf *surf)
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-{
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- if (surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR)
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- return 256 / surf->bpe;
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-
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- if (surf->u.gfx9.resource_type == RADEON_RESOURCE_3D)
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- return 1; /* TODO */
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-
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- unsigned bpe_shift = util_logbase2(surf->bpe) / 2;
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- switch(surf->u.gfx9.surf.swizzle_mode & ~3) {
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- case ADDR_SW_LINEAR: /* 256B block. */
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- return 16 >> bpe_shift;
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- case ADDR_SW_4KB_Z:
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- case ADDR_SW_4KB_Z_X:
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- return 64 >> bpe_shift;
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- case ADDR_SW_64KB_Z:
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- case ADDR_SW_64KB_Z_T:
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- case ADDR_SW_64KB_Z_X:
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- return 256 >> bpe_shift;
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- case ADDR_SW_VAR_Z_X:
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- default:
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- return 1; /* TODO */
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- }
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-}
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-
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-bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
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+void ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
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unsigned num_mipmap_levels, uint64_t offset, unsigned pitch)
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{
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- /*
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- * GFX10 and newer don't support custom strides. Furthermore, for
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- * multiple miplevels or compression data we'd really need to rerun
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- * addrlib to update all the fields in the surface. That, however, is a
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- * software limitation and could be relaxed later.
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- */
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- bool require_equal_pitch = surf->surf_size != surf->total_size ||
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- num_mipmap_levels != 1 ||
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- info->chip_class >= GFX10;
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-
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if (info->chip_class >= GFX9) {
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if (pitch) {
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- if (surf->u.gfx9.surf_pitch != pitch && require_equal_pitch)
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- return false;
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-
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- if ((ac_surface_get_gfx9_pitch_align(surf) - 1) & pitch)
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- return false;
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-
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- if (pitch != surf->u.gfx9.surf_pitch) {
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- unsigned slices = surf->surf_size / surf->u.gfx9.surf_slice_size;
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-
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- surf->u.gfx9.surf_pitch = pitch;
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+ surf->u.gfx9.surf_pitch = pitch;
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+ if (num_mipmap_levels == 1)
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surf->u.gfx9.surf.epitch = pitch - 1;
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- surf->u.gfx9.surf_slice_size = (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe;
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- surf->total_size = surf->surf_size = surf->u.gfx9.surf_slice_size * slices;
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- }
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+ surf->u.gfx9.surf_slice_size = (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe;
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}
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surf->u.gfx9.surf_offset = offset;
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if (surf->u.gfx9.stencil_offset)
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surf->u.gfx9.stencil_offset += offset;
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} else {
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if (pitch) {
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- if (surf->u.legacy.level[0].nblk_x != pitch && require_equal_pitch)
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- return false;
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-
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surf->u.legacy.level[0].nblk_x = pitch;
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surf->u.legacy.level[0].slice_size_dw =
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((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
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@@ -2878,10 +2826,6 @@
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@@ -2878,10 +2826,6 @@
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}
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}
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}
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}
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@ -97,53 +12,3 @@ diff -Naur mesa-mesa-21.0.2-old/src/amd/common/ac_surface.c mesa-mesa-21.0.2-new
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if (surf->htile_offset)
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if (surf->htile_offset)
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surf->htile_offset += offset;
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surf->htile_offset += offset;
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if (surf->fmask_offset)
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if (surf->fmask_offset)
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@@ -2892,7 +2836,6 @@
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surf->dcc_offset += offset;
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if (surf->display_dcc_offset)
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surf->display_dcc_offset += offset;
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- return true;
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}
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unsigned ac_surface_get_nplanes(const struct radeon_surf *surf)
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diff -Naur mesa-mesa-21.0.2-old/src/amd/common/ac_surface.h mesa-mesa-21.0.2-new/src/amd/common/ac_surface.h
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--- mesa-mesa-21.0.2-old/src/amd/common/ac_surface.h 2021-04-07 18:35:30.000000000 +0200
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+++ mesa-mesa-21.0.2-new/src/amd/common/ac_surface.h 2021-04-11 11:35:23.939998177 +0200
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@@ -336,7 +336,7 @@
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unsigned num_mipmap_levels, uint32_t desc[8],
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unsigned *size_metadata, uint32_t metadata[64]);
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-bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
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+void ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
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unsigned num_mipmap_levels, uint64_t offset, unsigned pitch);
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struct ac_modifier_options {
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diff -Naur mesa-mesa-21.0.2-old/src/gallium/drivers/radeonsi/si_texture.c mesa-mesa-21.0.2-new/src/gallium/drivers/radeonsi/si_texture.c
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--- mesa-mesa-21.0.2-old/src/gallium/drivers/radeonsi/si_texture.c 2021-04-07 18:35:30.000000000 +0200
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+++ mesa-mesa-21.0.2-new/src/gallium/drivers/radeonsi/si_texture.c 2021-04-11 11:35:23.939998177 +0200
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@@ -941,10 +941,9 @@
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*/
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tex->ps_draw_ratio = 0;
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- if (!ac_surface_override_offset_stride(&sscreen->info, &tex->surface,
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+ ac_surface_override_offset_stride(&sscreen->info, &tex->surface,
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tex->buffer.b.b.last_level + 1,
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- offset, pitch_in_bytes / tex->surface.bpe))
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- goto error;
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+ offset, pitch_in_bytes / tex->surface.bpe);
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if (tex->is_depth) {
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if (sscreen->info.chip_class >= GFX9) {
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@@ -1577,13 +1576,6 @@
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si_texture_reference(&tex, NULL);
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return NULL;
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}
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-
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- if (ac_surface_get_plane_offset(sscreen->info.chip_class, &tex->surface, 0, 0) +
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- tex->surface.total_size > buf->size ||
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- buf->alignment < tex->surface.alignment) {
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- si_texture_reference(&tex, NULL);
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- return NULL;
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- }
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/* Displayable DCC requires an explicit flush. */
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if (dedicated && offset == 0 && !(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
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