diff --git a/projects/NXP/devices/iMX8/patches/linux/0005-arm64-dts-fsl-imx8mq-phanbell.dts-enable-PCI.patch b/projects/NXP/devices/iMX8/patches/linux/0005-arm64-dts-fsl-imx8mq-phanbell.dts-enable-PCI.patch deleted file mode 100644 index 4e681909f6..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0005-arm64-dts-fsl-imx8mq-phanbell.dts-enable-PCI.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 352c7ed9d658a793eba747744e5ec330877e7f50 Mon Sep 17 00:00:00 2001 -From: Rudi Heitbaum -Date: Tue, 1 Oct 2024 06:53:51 +0000 -Subject: [PATCH 4/4] arm64: dts: fsl: imx8mq-phanbell.dts: enable PCI - ---- - arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts -index deba4a6f65d5..ed7d3e39af9a 100644 ---- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts -+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts -@@ -510,3 +510,11 @@ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - }; -+ -+&pcie0 { -+ status = "disabled"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; --- -2.43.0 - diff --git a/projects/NXP/devices/iMX8/patches/linux/0009-arm64-pci-add-ext_osc.patch b/projects/NXP/devices/iMX8/patches/linux/0009-arm64-pci-add-ext_osc.patch new file mode 100644 index 0000000000..7dfe3a4bdf --- /dev/null +++ b/projects/NXP/devices/iMX8/patches/linux/0009-arm64-pci-add-ext_osc.patch @@ -0,0 +1,35 @@ +From 4e40d36940e9d5159ba8a72e4ad04580025d5b94 Mon Sep 17 00:00:00 2001 +From: Rudi Heitbaum +Date: Tue, 1 Oct 2024 14:28:57 +0000 +Subject: [PATCH] arm64: pci: add ext_osc + +ext_osc from https://lore.kernel.org/lkml/1552467452-538-2-git-send-email-hongxing.zhu@nxp.com/ +--- + drivers/pci/controller/dwc/pci-imx6.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c +index 74703362aeec..603ca50229ec 100644 +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -90,6 +90,7 @@ struct imx_pcie { + u32 tx_deemph_gen2_6db; + u32 tx_swing_full; + u32 tx_swing_low; ++ u32 ext_osc; + struct regulator *vpcie; + struct regulator *vph; + void __iomem *phy_base; +@@ -1287,6 +1288,9 @@ static int imx_pcie_probe(struct platform_device *pdev) + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + ++ if (of_property_read_u32(node, "ext_osc", &imx_pcie->ext_osc) < 0) ++ imx_pcie->ext_osc = 0; ++ + /* Fetch GPIOs */ + imx_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); + imx_pcie->gpio_active_high = of_property_read_bool(node, +-- +2.43.0 + diff --git a/projects/NXP/devices/iMX8/patches/linux/0012-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch b/projects/NXP/devices/iMX8/patches/linux/0012-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch deleted file mode 100644 index e3dbc7a09e..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0012-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch +++ /dev/null @@ -1,33 +0,0 @@ -From aef5837a50af6adc53de4f907647cfd949912dba Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Tue, 7 Mar 2023 21:13:29 -0800 -Subject: [PATCH 2/4] MLK-15307-2 clk: imx8mq: set the parent clocks of PCIE - -Configure the parent clocks of PCIE. - -Signed-off-by: Richard Zhu -Signed-off-by: Khem Raj ---- - drivers/clk/imx/clk-imx8mq.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c -index bf3100eb59ca..3a5ff7109ff1 100644 ---- a/drivers/clk/imx/clk-imx8mq.c -+++ b/drivers/clk/imx/clk-imx8mq.c -@@ -646,6 +646,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) - /* enable all the clocks just for bringup */ - imx_clk_init_on(np, hws); - -+ /* set pcie root's parent clk source */ -+ clk_set_parent(hws[IMX8MQ_CLK_PCIE1_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_PCIE1_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_PCIE2_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk); -+ clk_set_parent(hws[IMX8MQ_CLK_PCIE2_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk); -+ - clk_set_parent(hws[IMX8MQ_CLK_CSI1_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk); - clk_set_parent(hws[IMX8MQ_CLK_CSI1_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk); - clk_set_parent(hws[IMX8MQ_CLK_CSI1_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk); --- -2.39.2 - diff --git a/projects/NXP/devices/iMX8/patches/linux/0013-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch b/projects/NXP/devices/iMX8/patches/linux/0013-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch index 3c7ca72fe9..5b7122ec50 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0013-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0013-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch @@ -10,35 +10,32 @@ REF_CLK. Signed-off-by: Ryosuke Saito Signed-off-by: Khem Raj --- - drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++-------- - 1 file changed, 7 insertions(+), 8 deletions(-) + drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 3a8350cad812..841af6f55c7d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c -@@ -1569,14 +1569,13 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) - break; - case IMX8MQ: - case IMX8MQ_EP: -- /* -- * TODO: Currently this code assumes external -- * oscillator is being used -- */ -- regmap_update_bits(imx6_pcie->iomuxc_gpr, -- imx6_pcie_grp_offset(imx6_pcie), -- IMX8MQ_GPR_PCIE_REF_USE_PAD, -- IMX8MQ_GPR_PCIE_REF_USE_PAD); -+ if (imx6_pcie->ext_osc) { -+ /* Use the external oscillator as REF clock */ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, -+ imx6_pcie_grp_offset(imx6_pcie), -+ IMX8MQ_GPR_PCIE_REF_USE_PAD, -+ IMX8MQ_GPR_PCIE_REF_USE_PAD); -+ } - /* - * Regarding the datasheet, the PCIE_VPH is suggested - * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the +@@ -370,11 +370,13 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + + static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) + { +- /* TODO: Currently this code assumes external oscillator is being used */ +- regmap_update_bits(imx_pcie->iomuxc_gpr, +- imx_pcie_grp_offset(imx_pcie), +- IMX8MQ_GPR_PCIE_REF_USE_PAD, +- IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ if (imx_pcie->ext_osc) { ++ /* Use the external oscillator as REF clock */ ++ regmap_update_bits(imx_pcie->iomuxc_gpr, ++ imx_pcie_grp_offset(imx_pcie), ++ IMX8MQ_GPR_PCIE_REF_USE_PAD, ++ IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ } + /* + * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is + * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. -- 2.39.2 diff --git a/projects/NXP/devices/iMX8/patches/linux/0014-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch b/projects/NXP/devices/iMX8/patches/linux/0014-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch index ab50273d9e..7731a39cb2 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0014-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0014-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch @@ -17,37 +17,34 @@ diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/ index 841af6f55c7d..ac36c7035460 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c -@@ -275,6 +275,12 @@ struct imx6_pcie { - #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) - #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) - +@@ -43,6 +43,11 @@ struct imx6_pcie { + #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) + #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) + #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 +#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG 0x74 +#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK GENMASK(3, 0) +#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE BIT(4) +#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG 0x7C +#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK GENMASK(2, 0) -+ - static int imx6_pcie_cz_enabled; - static void imx6_pcie_ltssm_disable(struct device *dev); -@@ -1575,6 +1581,35 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) - imx6_pcie_grp_offset(imx6_pcie), - IMX8MQ_GPR_PCIE_REF_USE_PAD, - IMX8MQ_GPR_PCIE_REF_USE_PAD); + #define IMX95_PCIE_PHY_GEN_CTRL 0x0 + #define IMX95_PCIE_REF_USE_PAD BIT(17) +@@ -370,6 +370,34 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + imx_pcie_grp_offset(imx_pcie), + IMX8MQ_GPR_PCIE_REF_USE_PAD, + IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ } else { ++ /* ++ * Use the internal PLL as REF clock and also ++ * provide a clock to the device. ++ */ ++ struct regmap *anatop = ++ syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop"); ++ ++ if (IS_ERR(anatop)) { ++ dev_err(imx_pcie->pci->dev, ++ "Couldn't configure the internal PLL as REF clock\n"); + } else { -+ /* -+ * Use the internal PLL as REF clock and also -+ * provide a clock to the device. -+ */ -+ struct regmap *anatop = -+ syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop"); -+ -+ if (IS_ERR(anatop)) { -+ dev_err(imx6_pcie->pci->dev, -+ "Couldn't configure the internal PLL as REF clock\n"); -+ break; -+ } -+ + /* Select SYSTEM_PLL1_CLK as the clock source */ + regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, + IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb); @@ -63,9 +60,10 @@ index 841af6f55c7d..ac36c7035460 100644 + regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, + IMX8MQ_ANA_PLLOUT_MONITOR_CKE, + IMX8MQ_ANA_PLLOUT_MONITOR_CKE); - } - /* - * Regarding the datasheet, the PCIE_VPH is suggested ++ } + } + /* + * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is -- 2.39.2