From 7c672b5506e3370eef86252c70c0349ca7f8d84b Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 6 Jan 2021 18:20:25 +0100 Subject: [PATCH] Allwinner: H6: Organize U-Boot patches --- ...am-h6-Improve-DDR3-config-detection.patch} | 19 +- ...02-ARM-dts-sunxi-h6-Update-DT-files.patch} | 1461 ++++++++--------- ...0003-sunxi-Add-support-for-Tanix-TX6.patch | 201 +++ ...act-creating-a-unique-sid-into-a-hel.patch | 159 ++ ...config-option-to-fixup-a-Bluetooth-a.patch | 96 ++ ...s-sun50i-Add-support-for-Orange-Pi-3.patch | 424 +++++ ....patch => 0008-orange-pi-3-ethernet.patch} | 17 - ...tch => 0009-tanix-tx6-ethernet-hack.patch} | 8 +- .../patches/u-boot/0010-unreliable-dram.patch | 40 + ...ate-Orange-Pi-One-Plus-for-LibreELEC.patch | 82 - .../patches/u-boot/004-unreliable-dram.patch | 104 -- .../devices/H6/patches/u-boot/006-DDR3.patch | 181 -- 12 files changed, 1662 insertions(+), 1130 deletions(-) rename projects/Allwinner/devices/H6/patches/u-boot/{008-wip-h6-dram-fix.patch => 0001-sunxi-dram-h6-Improve-DDR3-config-detection.patch} (86%) rename projects/Allwinner/devices/H6/patches/u-boot/{001-backports.patch => 0002-ARM-dts-sunxi-h6-Update-DT-files.patch} (52%) create mode 100644 projects/Allwinner/devices/H6/patches/u-boot/0003-sunxi-Add-support-for-Tanix-TX6.patch create mode 100644 projects/Allwinner/devices/H6/patches/u-boot/0004-sunxi-board-extract-creating-a-unique-sid-into-a-hel.patch create mode 100644 projects/Allwinner/devices/H6/patches/u-boot/0005-arm-sunxi-add-a-config-option-to-fixup-a-Bluetooth-a.patch create mode 100644 projects/Allwinner/devices/H6/patches/u-boot/0007-arm64-dts-sun50i-Add-support-for-Orange-Pi-3.patch rename projects/Allwinner/devices/H6/patches/u-boot/{002-orange-pi-3-support.patch => 0008-orange-pi-3-ethernet.patch} (86%) rename projects/Allwinner/devices/H6/patches/u-boot/{007-ethernet-hack.patch => 0009-tanix-tx6-ethernet-hack.patch} (75%) create mode 100644 projects/Allwinner/devices/H6/patches/u-boot/0010-unreliable-dram.patch delete mode 100644 projects/Allwinner/devices/H6/patches/u-boot/003-Update-Orange-Pi-One-Plus-for-LibreELEC.patch delete mode 100644 projects/Allwinner/devices/H6/patches/u-boot/004-unreliable-dram.patch delete mode 100644 projects/Allwinner/devices/H6/patches/u-boot/006-DDR3.patch diff --git a/projects/Allwinner/devices/H6/patches/u-boot/008-wip-h6-dram-fix.patch b/projects/Allwinner/devices/H6/patches/u-boot/0001-sunxi-dram-h6-Improve-DDR3-config-detection.patch similarity index 86% rename from projects/Allwinner/devices/H6/patches/u-boot/008-wip-h6-dram-fix.patch rename to projects/Allwinner/devices/H6/patches/u-boot/0001-sunxi-dram-h6-Improve-DDR3-config-detection.patch index 72ffd34b02..b46cb8bbaa 100644 --- a/projects/Allwinner/devices/H6/patches/u-boot/008-wip-h6-dram-fix.patch +++ b/projects/Allwinner/devices/H6/patches/u-boot/0001-sunxi-dram-h6-Improve-DDR3-config-detection.patch @@ -1,8 +1,21 @@ -From 1de004d4e6830c44a30ffa0abd09c12e69734bb5 Mon Sep 17 00:00:00 2001 +From 4d2be560fe0123536aed35f86184290b0afffccc Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 1 Oct 2020 19:56:38 +0200 -Subject: [PATCH] wip h6 dram fix +Subject: [PATCH] sunxi: dram: h6: Improve DDR3 config detection +It turns out that in rare cases, current analytical approach to detect +correct DRAM bus width and rank on H6 doesn't work. On some TV boxes +with DDR3, incorrect DRAM configuration triggers write leveling error +which immediately stops initialization process. Exact reason why this +error appears isn't known. However, if correct configuration is used, +initalization works without problem. + +In order to fix this issue, simply try another configuration when any +kind of error appears during initialization, not just those related to +rank and bus width. + +Tested-by: Thomas Graichen +Signed-off-by: Jernej Skrabec --- arch/arm/mach-sunxi/dram_sun50i_h6.c | 95 +++++++++++++++------------- 1 file changed, 51 insertions(+), 44 deletions(-) @@ -168,5 +181,5 @@ index 9e34da474798..1cde6132be2c 100644 mctl_core_init(¶); -- -2.28.0 +2.29.2 diff --git a/projects/Allwinner/devices/H6/patches/u-boot/001-backports.patch b/projects/Allwinner/devices/H6/patches/u-boot/0002-ARM-dts-sunxi-h6-Update-DT-files.patch similarity index 52% rename from projects/Allwinner/devices/H6/patches/u-boot/001-backports.patch rename to projects/Allwinner/devices/H6/patches/u-boot/0002-ARM-dts-sunxi-h6-Update-DT-files.patch index 72c954ba7b..42b0517f5f 100644 --- a/projects/Allwinner/devices/H6/patches/u-boot/001-backports.patch +++ b/projects/Allwinner/devices/H6/patches/u-boot/0002-ARM-dts-sunxi-h6-Update-DT-files.patch @@ -1,272 +1,27 @@ -From 506a6889998b34598209e0b9838a606d10aec642 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Tue, 26 Nov 2019 12:38:46 +0100 -Subject: [PATCH 1/4] sunxi: board: extract creating a unique sid into a helper - function +From cec4496355d1c9ff651a049b2ae5f51c7e49bd90 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 3 Jan 2021 10:45:14 +0100 +Subject: [PATCH v3 1/2] ARM: dts: sunxi: h6: Update DT files -Refactor setup_environment() so we can use the created sid for a -Bluetooth address too. +Updated H6 DT files are based on Linux 5.11-rc1 release. -Signed-off-by: Andre Heider -Acked-by: Maxime Ripard +Signed-off-by: Jernej Skrabec --- - board/sunxi/board.c | 105 ++++++++++++++++++++++++-------------------- - 1 file changed, 58 insertions(+), 47 deletions(-) - -diff --git a/board/sunxi/board.c b/board/sunxi/board.c -index 6afea6ef42..e670793479 100644 ---- a/board/sunxi/board.c -+++ b/board/sunxi/board.c -@@ -770,6 +770,38 @@ static void parse_spl_header(const uint32_t spl_addr) - env_set_hex("fel_scriptaddr", spl->fel_script_address); - } - -+static bool get_unique_sid(unsigned int *sid) -+{ -+ if (sunxi_get_sid(sid) != 0) -+ return false; -+ -+ if (!sid[0]) -+ return false; -+ -+ /* -+ * The single words 1 - 3 of the SID have quite a few bits -+ * which are the same on many models, so we take a crc32 -+ * of all 3 words, to get a more unique value. -+ * -+ * Note we only do this on newer SoCs as we cannot change -+ * the algorithm on older SoCs since those have been using -+ * fixed mac-addresses based on only using word 3 for a -+ * long time and changing a fixed mac-address with an -+ * u-boot update is not good. -+ */ -+#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ -+ !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ -+ !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) -+ sid[3] = crc32(0, (unsigned char *)&sid[1], 12); -+#endif -+ -+ /* Ensure the NIC specific bytes of the mac are not all 0 */ -+ if ((sid[3] & 0xffffff) == 0) -+ sid[3] |= 0x800000; -+ -+ return true; -+} -+ - /* - * Note this function gets called multiple times. - * It must not make any changes to env variables which already exist. -@@ -780,61 +812,40 @@ static void setup_environment(const void *fdt) - unsigned int sid[4]; - uint8_t mac_addr[6]; - char ethaddr[16]; -- int i, ret; -+ int i; - -- ret = sunxi_get_sid(sid); -- if (ret == 0 && sid[0] != 0) { -- /* -- * The single words 1 - 3 of the SID have quite a few bits -- * which are the same on many models, so we take a crc32 -- * of all 3 words, to get a more unique value. -- * -- * Note we only do this on newer SoCs as we cannot change -- * the algorithm on older SoCs since those have been using -- * fixed mac-addresses based on only using word 3 for a -- * long time and changing a fixed mac-address with an -- * u-boot update is not good. -- */ --#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ -- !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ -- !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) -- sid[3] = crc32(0, (unsigned char *)&sid[1], 12); --#endif -- -- /* Ensure the NIC specific bytes of the mac are not all 0 */ -- if ((sid[3] & 0xffffff) == 0) -- sid[3] |= 0x800000; -+ if (!get_unique_sid(sid)) -+ return; - -- for (i = 0; i < 4; i++) { -- sprintf(ethaddr, "ethernet%d", i); -- if (!fdt_get_alias(fdt, ethaddr)) -- continue; -+ for (i = 0; i < 4; i++) { -+ sprintf(ethaddr, "ethernet%d", i); -+ if (!fdt_get_alias(fdt, ethaddr)) -+ continue; - -- if (i == 0) -- strcpy(ethaddr, "ethaddr"); -- else -- sprintf(ethaddr, "eth%daddr", i); -+ if (i == 0) -+ strcpy(ethaddr, "ethaddr"); -+ else -+ sprintf(ethaddr, "eth%daddr", i); - -- if (env_get(ethaddr)) -- continue; -+ if (env_get(ethaddr)) -+ continue; - -- /* Non OUI / registered MAC address */ -- mac_addr[0] = (i << 4) | 0x02; -- mac_addr[1] = (sid[0] >> 0) & 0xff; -- mac_addr[2] = (sid[3] >> 24) & 0xff; -- mac_addr[3] = (sid[3] >> 16) & 0xff; -- mac_addr[4] = (sid[3] >> 8) & 0xff; -- mac_addr[5] = (sid[3] >> 0) & 0xff; -+ /* Non OUI / registered MAC address */ -+ mac_addr[0] = (i << 4) | 0x02; -+ mac_addr[1] = (sid[0] >> 0) & 0xff; -+ mac_addr[2] = (sid[3] >> 24) & 0xff; -+ mac_addr[3] = (sid[3] >> 16) & 0xff; -+ mac_addr[4] = (sid[3] >> 8) & 0xff; -+ mac_addr[5] = (sid[3] >> 0) & 0xff; - -- eth_env_set_enetaddr(ethaddr, mac_addr); -- } -+ eth_env_set_enetaddr(ethaddr, mac_addr); -+ } - -- if (!env_get("serial#")) { -- snprintf(serial_string, sizeof(serial_string), -- "%08x%08x", sid[0], sid[3]); -+ if (!env_get("serial#")) { -+ snprintf(serial_string, sizeof(serial_string), -+ "%08x%08x", sid[0], sid[3]); - -- env_set("serial#", serial_string); -- } -+ env_set("serial#", serial_string); - } - } - --- -2.24.1 - -From b032ba7c92543040f11670fe17132d9a2a8a46b5 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Sun, 17 Nov 2019 20:24:43 +0100 -Subject: [PATCH 2/4] arm: sunxi: add a config option to fixup a Bluetooth - address - -Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3, -ship with the controller default address. - -Add a config option to fix it up so it can function properly. - -Signed-off-by: Andre Heider -Tested-by: Ondrej Jirman -Acked-by: Maxime Ripard ---- - arch/arm/mach-sunxi/Kconfig | 11 +++++++++++ - board/sunxi/board.c | 34 ++++++++++++++++++++++++++++++++++ - 2 files changed, 45 insertions(+) - -diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig -index 3a3b673430..4c6977e8fb 100644 ---- a/arch/arm/mach-sunxi/Kconfig -+++ b/arch/arm/mach-sunxi/Kconfig -@@ -1010,4 +1010,15 @@ config PINE64_DT_SELECTION - option, the device tree selection code specific to Pine64 which - utilizes the DRAM size will be enabled. - -+config FIXUP_BDADDR -+ string "Fixup the Bluetooth controller address" -+ default "" -+ help -+ This option specifies the DT compatible name of the Bluetooth -+ controller for which to set the "local-bd-address" property. -+ Set this option if your device ships with the Bluetooth controller -+ default address. -+ The used address is "bdaddr" if set, and "ethaddr" with the LSB -+ flipped elsewise. -+ - endif -diff --git a/board/sunxi/board.c b/board/sunxi/board.c -index e670793479..c05682a331 100644 ---- a/board/sunxi/board.c -+++ b/board/sunxi/board.c -@@ -878,6 +878,38 @@ int misc_init_r(void) - return 0; - } - -+static void fixup_bd_address(void *blob) -+{ -+ /* Some devices ship with a Bluetooth controller default address. -+ * Set a valid address through the device tree. -+ */ -+ uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN]; -+ unsigned int sid[4]; -+ int i; -+ -+ if (!CONFIG_FIXUP_BDADDR[0]) -+ return; -+ -+ if (eth_env_get_enetaddr("bdaddr", tmp)) { -+ /* Convert between the binary formats of the corresponding stacks */ -+ for (i = 0; i < ETH_ALEN; ++i) -+ bdaddr[i] = tmp[ETH_ALEN - i - 1]; -+ } else { -+ if (!get_unique_sid(sid)) -+ return; -+ -+ bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1; -+ bdaddr[1] = (sid[3] >> 8) & 0xff; -+ bdaddr[2] = (sid[3] >> 16) & 0xff; -+ bdaddr[3] = (sid[3] >> 24) & 0xff; -+ bdaddr[4] = (sid[0] >> 0) & 0xff; -+ bdaddr[5] = 0x02; -+ } -+ -+ do_fixup_by_compat(blob, CONFIG_FIXUP_BDADDR, -+ "local-bd-address", bdaddr, ETH_ALEN, 1); -+} -+ - int ft_board_setup(void *blob, struct bd_info *bd) - { - int __maybe_unused r; -@@ -888,6 +920,8 @@ int ft_board_setup(void *blob, bd_t *bd) - */ - setup_environment(blob); - -+ fixup_bd_address(blob); -+ - #ifdef CONFIG_VIDEO_DT_SIMPLEFB - r = sunxi_simplefb_setup(blob); - if (r) --- -2.24.1 - -From 66d40d7dd5fa29aa592590a3b820ebe656707c5d Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 18 Nov 2019 10:52:52 +0100 -Subject: [PATCH 3/4] arm64: dts: sync Allwinner H6 files - -Taken from the linux-next commit: -98d25b0b266d Merge branch 'sunxi/dt-for-5.6' into sunxi/for-next - -Drop the /omit-if-no-ref/ keyword as it's not supported by u-boot. - -Signed-off-by: Andre Heider -Acked-by: Maxime Ripard ---- - arch/arm/dts/sun50i-h6-beelink-gs1.dts | 48 +++- - arch/arm/dts/sun50i-h6-orangepi-lite2.dts | 6 +- - arch/arm/dts/sun50i-h6-orangepi-one-plus.dts | 8 +- - arch/arm/dts/sun50i-h6-orangepi.dtsi | 18 +- - arch/arm/dts/sun50i-h6-pine-h64.dts | 33 ++- - arch/arm/dts/sun50i-h6.dtsi | 262 +++++++++++++++++-- - 6 files changed, 328 insertions(+), 47 deletions(-) + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 70 +++- + arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 117 ++++++ + arch/arm/dts/sun50i-h6-orangepi-lite2.dts | 71 +++- + arch/arm/dts/sun50i-h6-orangepi-one-plus.dts | 41 +- + arch/arm/dts/sun50i-h6-orangepi.dtsi | 72 +++- + arch/arm/dts/sun50i-h6-pine-h64.dts | 102 +++-- + arch/arm/dts/sun50i-h6.dtsi | 394 +++++++++++++++++-- + 7 files changed, 794 insertions(+), 73 deletions(-) + create mode 100644 arch/arm/dts/sun50i-h6-cpu-opp.dtsi diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts -index 0dc33c90dd..df6d872c34 100644 +index 0dc33c90dd60..7c9dbde645b5 100644 --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts -@@ -1,7 +1,5 @@ +@@ -1,11 +1,10 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (C) 2019 Clément Péron @@ -276,7 +31,12 @@ index 0dc33c90dd..df6d872c34 100644 /dts-v1/; -@@ -25,6 +23,7 @@ + #include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" + + #include + +@@ -25,6 +24,7 @@ connector { compatible = "hdmi-connector"; type = "a"; @@ -284,7 +44,21 @@ index 0dc33c90dd..df6d872c34 100644 port { hdmi_con_in: endpoint { -@@ -51,12 +50,34 @@ +@@ -33,6 +33,13 @@ + }; + }; + ++ ext_osc32k: ext_osc32k_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "ext_osc32k"; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -51,12 +58,38 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; @@ -306,6 +80,10 @@ index 0dc33c90dd..df6d872c34 100644 + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdca>; }; &de { @@ -319,7 +97,14 @@ index 0dc33c90dd..df6d872c34 100644 &ehci0 { status = "okay"; }; -@@ -70,6 +91,11 @@ +@@ -64,12 +97,17 @@ + &emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; +- phy-mode = "rgmii"; ++ phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_aldo2>; status = "okay"; }; @@ -331,15 +116,25 @@ index 0dc33c90dd..df6d872c34 100644 &hdmi { status = "okay"; }; -@@ -206,6 +232,7 @@ +@@ -201,13 +239,16 @@ + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; }; reg_dcdcc: dcdcc { + regulator-enable-ramp-delay = <32000>; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; ++ regulator-ramp-delay = <2500>; regulator-name = "vdd-gpu"; -@@ -232,6 +259,11 @@ + }; + +@@ -232,6 +273,11 @@ }; }; @@ -351,10 +146,14 @@ index 0dc33c90dd..df6d872c34 100644 &r_pio { /* * PL0 and PL1 are used for PMIC I2C -@@ -243,6 +275,10 @@ +@@ -243,6 +289,14 @@ vcc-pm-supply = <®_aldo1>; }; ++&rtc { ++ clocks = <&ext_osc32k>; ++}; ++ +&spdif { + status = "okay"; +}; @@ -362,7 +161,7 @@ index 0dc33c90dd..df6d872c34 100644 &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; -@@ -258,3 +294,7 @@ +@@ -258,3 +312,7 @@ usb0_vbus-supply = <®_vcc5v>; status = "okay"; }; @@ -370,11 +169,134 @@ index 0dc33c90dd..df6d872c34 100644 +&usb3phy { + status = "okay"; +}; +diff --git a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi +new file mode 100644 +index 000000000000..1a5eddc5a40f +--- /dev/null ++++ b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi +@@ -0,0 +1,117 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Ondrej Jirman ++// Copyright (C) 2020 Clément Péron ++ ++/ { ++ cpu_opp_table: cpu-opp-table { ++ compatible = "allwinner,sun50i-h6-operating-points"; ++ nvmem-cells = <&cpu_speed_grade>; ++ opp-shared; ++ ++ opp@480000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <480000000>; ++ ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; ++ }; ++ ++ opp@720000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <720000000>; ++ ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; ++ }; ++ ++ opp@816000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <816000000>; ++ ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; ++ }; ++ ++ opp@888000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <888000000>; ++ ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; ++ }; ++ ++ opp@1080000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1080000000>; ++ ++ opp-microvolt-speed0 = <940000 940000 1200000>; ++ opp-microvolt-speed1 = <880000 880000 1200000>; ++ opp-microvolt-speed2 = <880000 880000 1200000>; ++ }; ++ ++ opp@1320000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1320000000>; ++ ++ opp-microvolt-speed0 = <1000000 1000000 1200000>; ++ opp-microvolt-speed1 = <940000 940000 1200000>; ++ opp-microvolt-speed2 = <940000 940000 1200000>; ++ }; ++ ++ opp@1488000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1488000000>; ++ ++ opp-microvolt-speed0 = <1060000 1060000 1200000>; ++ opp-microvolt-speed1 = <1000000 1000000 1200000>; ++ opp-microvolt-speed2 = <1000000 1000000 1200000>; ++ }; ++ ++ opp@1608000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1608000000>; ++ ++ opp-microvolt-speed0 = <1090000 1090000 1200000>; ++ opp-microvolt-speed1 = <1030000 1030000 1200000>; ++ opp-microvolt-speed2 = <1030000 1030000 1200000>; ++ }; ++ ++ opp@1704000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1704000000>; ++ ++ opp-microvolt-speed0 = <1120000 1120000 1200000>; ++ opp-microvolt-speed1 = <1060000 1060000 1200000>; ++ opp-microvolt-speed2 = <1060000 1060000 1200000>; ++ }; ++ ++ opp@1800000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1800000000>; ++ ++ opp-microvolt-speed0 = <1160000 1160000 1200000>; ++ opp-microvolt-speed1 = <1100000 1100000 1200000>; ++ opp-microvolt-speed2 = <1100000 1100000 1200000>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts -index e098a2475f..e7ca75c0d0 100644 +index e098a2475f2d..e8770858b5d0 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts -@@ -1,7 +1,5 @@ +@@ -1,11 +1,74 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (C) 2018 Jagan Teki @@ -384,11 +306,80 @@ index e098a2475f..e7ca75c0d0 100644 #include "sun50i-h6-orangepi.dtsi" + / { + model = "OrangePi Lite2"; + compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial1 = &uart1; /* BT-UART */ ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_cldo2>; ++ vqmmc-supply = <®_bldo3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcm: sdio-wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++®_cldo2 { ++ /* ++ * This regulator is connected with CLDO3. ++ * Before the kernel can support synchronized ++ * enable of coupled regulators, keep them ++ * both always on as a ugly hack. ++ */ ++ regulator-always-on; ++}; ++ ++®_cldo3 { ++ /* ++ * This regulator is connected with CLDO2. ++ * See the comments for CLDO2. ++ */ ++ regulator-always-on; ++}; ++ ++/* There's the BT part of the AP6255 connected to that UART */ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ ++ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ ++ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ ++ max-speed = <1500000>; ++ }; + }; diff --git a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts -index 12e17567ab..83aab73688 100644 +index 12e17567ab56..29a081e72a9b 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts -@@ -1,8 +1,6 @@ +@@ -1,12 +1,43 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (C) 2018 Amarula Solutions @@ -400,8 +391,45 @@ index 12e17567ab..83aab73688 100644 #include "sun50i-h6-orangepi.dtsi" + / { + model = "OrangePi One Plus"; + compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; ++ ++ aliases { ++ ethernet0 = &emac; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ ++ vin-supply = <®_aldo2>; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-supply = <®_gmac_3v3>; ++ allwinner,rx-delay-ps = <200>; ++ allwinner,tx-delay-ps = <200>; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; + }; diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi -index 62e27948a3..37f4c57597 100644 +index 62e27948a3fa..ebc120a9232f 100644 --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi @@ -1,8 +1,6 @@ @@ -416,7 +444,44 @@ index 62e27948a3..37f4c57597 100644 /dts-v1/; -@@ -55,6 +53,11 @@ +@@ -22,6 +20,25 @@ + stdout-path = "serial0:115200n8"; + }; + ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ ext_osc32k: ext_osc32k_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "ext_osc32k"; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -47,6 +64,10 @@ + }; + }; + ++&de { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +@@ -55,6 +76,21 @@ status = "okay"; }; @@ -424,11 +489,34 @@ index 62e27948a3..37f4c57597 100644 + mali-supply = <®_dcdcc>; + status = "okay"; +}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; + &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; -@@ -163,6 +166,7 @@ +@@ -70,6 +106,12 @@ + status = "okay"; + }; + ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_aldo1>; ++}; ++ + &r_i2c { + status = "okay"; + +@@ -163,6 +205,7 @@ }; reg_dcdcc: dcdcc { @@ -436,22 +524,44 @@ index 62e27948a3..37f4c57597 100644 regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; regulator-name = "vdd-gpu"; -@@ -189,6 +193,10 @@ +@@ -189,6 +232,18 @@ }; }; +&r_ir { + status = "okay"; +}; ++ ++&r_pio { ++ vcc-pm-supply = <®_bldo3>; ++}; ++ ++&rtc { ++ clocks = <&ext_osc32k>; ++}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; +@@ -196,7 +251,12 @@ + }; + + &usb2otg { +- dr_mode = "otg"; ++ /* ++ * OrangePi Lite 2 and One Plus, where this DT is used, don't ++ * have a controllable VBUS even though they do have an ID pin. ++ * Using it as anything but a USB host is unsafe. ++ */ ++ dr_mode = "host"; + status = "okay"; + }; + diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts -index 1898345183..d1c2aa5b3a 100644 +index 189834518391..961732c52aa0 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts -@@ -1,7 +1,5 @@ +@@ -1,30 +1,38 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (c) 2017 Icenowy Zheng @@ -461,7 +571,9 @@ index 1898345183..d1c2aa5b3a 100644 /dts-v1/; -@@ -10,7 +8,7 @@ + #include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" + #include / { @@ -470,11 +582,23 @@ index 1898345183..d1c2aa5b3a 100644 compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; aliases { -@@ -22,9 +20,10 @@ + ethernet0 = &emac; + serial0 = &uart0; ++ spi0 = &spi0; + }; + + chosen { stdout-path = "serial0:115200n8"; }; - connector { ++ ext_osc32k: ext_osc32k_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "ext_osc32k"; ++ }; ++ + hdmi_connector: connector { compatible = "hdmi-connector"; type = "a"; @@ -482,7 +606,7 @@ index 1898345183..d1c2aa5b3a 100644 port { hdmi_con_in: endpoint { -@@ -52,6 +51,16 @@ +@@ -52,6 +60,16 @@ }; }; @@ -499,36 +623,89 @@ index 1898345183..d1c2aa5b3a 100644 reg_usb_vbus: vbus { compatible = "regulator-fixed"; regulator-name = "usb-vbus"; -@@ -68,7 +77,7 @@ +@@ -63,25 +81,35 @@ + }; + }; + ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ + &emac { + pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; +- phy-mode = "rgmii"; ++ phy-mode = "rgmii-id"; phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_aldo2>; + phy-supply = <®_gmac_3v3>; allwinner,rx-delay-ps = <200>; allwinner,tx-delay-ps = <200>; status = "okay"; -@@ -85,6 +94,11 @@ + }; + +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&de { ++&gpu { ++ mali-supply = <®_dcdcc>; status = "okay"; }; -+&gpu { -+ mali-supply = <®_dcdcc>; -+ status = "okay"; -+}; -+ - &hdmi { - status = "okay"; +@@ -95,12 +123,11 @@ + }; }; -@@ -221,6 +235,7 @@ + +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; + }; + + &mmc0 { +@@ -216,13 +243,16 @@ + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; }; reg_dcdcc: dcdcc { + regulator-enable-ramp-delay = <32000>; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; ++ regulator-ramp-delay = <2500>; regulator-name = "vdd-gpu"; -@@ -255,6 +270,10 @@ + }; + +@@ -255,10 +285,36 @@ }; }; @@ -539,8 +716,34 @@ index 1898345183..d1c2aa5b3a 100644 &r_pio { vcc-pm-supply = <®_aldo1>; }; + ++&rtc { ++ clocks = <&ext_osc32k>; ++}; ++ ++/* ++ * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI ++ * flash and eMMC at the same time, as one of them would fail probing. ++ * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can ++ * fix this up in no eMMC is connected. ++ */ ++&spi0 { ++ pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ flash@0 { ++ compatible = "winbond,w25q128", "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <4000000>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi -index a117f479ae..148bf0107b 100644 +index a117f479ae55..8a62a9fbe347 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -1,7 +1,5 @@ @@ -561,7 +764,47 @@ index a117f479ae..148bf0107b 100644 / { interrupt-parent = <&gic>; -@@ -56,14 +55,6 @@ +@@ -26,6 +25,9 @@ + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu1: cpu@1 { +@@ -33,6 +35,9 @@ + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu2: cpu@2 { +@@ -40,6 +45,9 @@ + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu3: cpu@3 { +@@ -47,6 +55,9 @@ + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + }; + +@@ -56,14 +67,6 @@ status = "disabled"; }; @@ -576,22 +819,17 @@ index a117f479ae..148bf0107b 100644 osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; -@@ -71,11 +62,21 @@ +@@ -71,11 +74,13 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { -+ ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; - clock-output-names = "osc32k"; -+ clock-output-names = "ext_osc32k"; -+ }; -+ + pmu { -+ compatible = "arm,cortex-a53-pmu", -+ "arm,armv8-pmuv3"; ++ compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , @@ -600,10 +838,29 @@ index a117f479ae..148bf0107b 100644 }; psci { -@@ -157,6 +158,29 @@ - allwinner,sram = <&ve_sram 1>; - }; +@@ -85,6 +90,7 @@ + timer { + compatible = "arm,armv8-timer"; ++ arm,no-tick-in-suspend; + interrupts = , + ; ++ iommus = <&iommu 0>; + + ports { + #address-cells = <1>; +@@ -155,6 +162,30 @@ + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; ++ iommus = <&iommu 3>; ++ }; ++ + gpu: gpu@1800000 { + compatible = "allwinner,sun50i-h6-mali", + "arm,mali-t720"; @@ -625,12 +882,10 @@ index a117f479ae..148bf0107b 100644 + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CE>; -+ }; -+ + }; + syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h6-system-control", - "allwinner,sun50i-a64-system-control"; -@@ -197,7 +221,7 @@ +@@ -197,7 +228,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h6-ccu"; reg = <0x03001000 0x1000>; @@ -639,11 +894,21 @@ index a117f479ae..148bf0107b 100644 clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; -@@ -215,9 +239,15 @@ +@@ -215,9 +246,29 @@ #dma-cells = <1>; }; - sid: sid@3006000 { ++ msgbox: mailbox@3003000 { ++ compatible = "allwinner,sun50i-h6-msgbox", ++ "allwinner,sun6i-a31-msgbox"; ++ reg = <0x03003000 0x1000>; ++ clocks = <&ccu CLK_BUS_MSGBOX>; ++ resets = <&ccu RST_BUS_MSGBOX>; ++ interrupts = ; ++ #mbox-cells = <1>; ++ }; ++ + sid: efuse@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; @@ -652,11 +917,15 @@ index a117f479ae..148bf0107b 100644 + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; ++ }; ++ ++ cpu_speed_grade: cpu-speed-grade@1c { ++ reg = <0x1c 0x4>; + }; }; watchdog: watchdog@30090a0 { -@@ -225,10 +255,21 @@ +@@ -225,10 +276,21 @@ "allwinner,sun6i-a31-wdt"; reg = <0x030090a0 0x20>; interrupts = ; @@ -678,7 +947,7 @@ index a117f479ae..148bf0107b 100644 pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; -@@ -236,7 +277,7 @@ +@@ -236,7 +298,7 @@ , , ; @@ -687,7 +956,7 @@ index a117f479ae..148bf0107b 100644 clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; -@@ -256,6 +297,21 @@ +@@ -256,6 +318,21 @@ function = "hdmi"; }; @@ -709,10 +978,47 @@ index a117f479ae..148bf0107b 100644 mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; -@@ -285,10 +341,25 @@ +@@ -264,10 +341,7 @@ bias-pull-up; }; +- /* +- * /omit-if-no-ref/ isn't supported by U-boot +- * keep this comment to avoid bad sync with Linux +- */ ++ /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; +@@ -285,10 +359,50 @@ + bias-pull-up; + }; + ++ /omit-if-no-ref/ ++ spi0_pins: spi0-pins { ++ pins = "PC0", "PC2", "PC3"; ++ function = "spi0"; ++ }; ++ ++ /* pin shared with MMC2-CMD (eMMC) */ ++ /omit-if-no-ref/ ++ spi0_cs_pin: spi0-cs-pin { ++ pins = "PC5"; ++ function = "spi0"; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1_pins: spi1-pins { ++ pins = "PH4", "PH5", "PH6"; ++ function = "spi1"; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1_cs_pin: spi1-cs-pin { ++ pins = "PH3"; ++ function = "spi1"; ++ }; ++ + spdif_tx_pin: spdif-tx-pin { + pins = "PH7"; + function = "spdif"; @@ -735,7 +1041,23 @@ index a117f479ae..148bf0107b 100644 }; gic: interrupt-controller@3021000 { -@@ -394,6 +465,48 @@ +@@ -302,6 +416,15 @@ + #interrupt-cells = <3>; + }; + ++ iommu: iommu@30f0000 { ++ compatible = "allwinner,sun50i-h6-iommu"; ++ reg = <0x030f0000 0x10000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_IOMMU>; ++ resets = <&ccu RST_BUS_IOMMU>; ++ #iommu-cells = <1>; ++ }; ++ + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-h6-mmc", + "allwinner,sun50i-a64-mmc"; +@@ -394,6 +517,78 @@ status = "disabled"; }; @@ -780,14 +1102,57 @@ index a117f479ae..148bf0107b 100644 + #address-cells = <1>; + #size-cells = <0>; + }; ++ ++ spi0: spi@5010000 { ++ compatible = "allwinner,sun50i-h6-spi", ++ "allwinner,sun8i-h3-spi"; ++ reg = <0x05010000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma 22>, <&dma 22>; ++ dma-names = "rx", "tx"; ++ resets = <&ccu RST_BUS_SPI0>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi1: spi@5011000 { ++ compatible = "allwinner,sun50i-h6-spi", ++ "allwinner,sun8i-h3-spi"; ++ reg = <0x05011000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma 23>, <&dma 23>; ++ dma-names = "rx", "tx"; ++ resets = <&ccu RST_BUS_SPI1>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; + emac: ethernet@5020000 { compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac"; -@@ -414,6 +527,21 @@ +@@ -414,6 +609,34 @@ }; }; ++ i2s1: i2s@5091000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun50i-h6-i2s"; ++ reg = <0x05091000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; ++ clock-names = "apb", "mod"; ++ dmas = <&dma 4>, <&dma 4>; ++ resets = <&ccu RST_BUS_I2S1>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + spdif: spdif@5093000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-spdif"; @@ -806,11 +1171,11 @@ index a117f479ae..148bf0107b 100644 usb2otg: usb@5100000 { compatible = "allwinner,sun50i-h6-musb", "allwinner,sun8i-a33-musb"; -@@ -470,6 +598,38 @@ +@@ -470,6 +693,38 @@ status = "disabled"; }; -+ dwc3: dwc3@5200000 { ++ dwc3: usb@5200000 { + compatible = "snps,dwc3"; + reg = <0x05200000 0x10000>; + interrupts = ; @@ -845,7 +1210,7 @@ index a117f479ae..148bf0107b 100644 ehci3: usb@5311000 { compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; reg = <0x05311000 0x100>; -@@ -480,6 +640,7 @@ +@@ -480,6 +735,7 @@ resets = <&ccu RST_BUS_OHCI3>, <&ccu RST_BUS_EHCI3>; phys = <&usb2phy 3>; @@ -853,7 +1218,7 @@ index a117f479ae..148bf0107b 100644 status = "disabled"; }; -@@ -491,6 +652,7 @@ +@@ -491,6 +747,7 @@ <&ccu CLK_USB_OHCI3>; resets = <&ccu RST_BUS_OHCI3>; phys = <&usb2phy 3>; @@ -861,7 +1226,7 @@ index a117f479ae..148bf0107b 100644 status = "disabled"; }; -@@ -507,7 +669,7 @@ +@@ -507,7 +764,7 @@ resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; reset-names = "ctrl", "hdcp"; phys = <&hdmi_phy>; @@ -870,7 +1235,7 @@ index a117f479ae..148bf0107b 100644 pinctrl-names = "default"; pinctrl-0 = <&hdmi_pins>; status = "disabled"; -@@ -549,7 +711,6 @@ +@@ -549,7 +806,6 @@ "tcon-tv0"; clock-output-names = "tcon-top-tv0"; resets = <&ccu RST_BUS_TCON_TOP>; @@ -878,7 +1243,7 @@ index a117f479ae..148bf0107b 100644 #clock-cells = <1>; ports { -@@ -636,10 +797,20 @@ +@@ -636,10 +892,19 @@ }; }; @@ -888,7 +1253,6 @@ index a117f479ae..148bf0107b 100644 + interrupts = , + ; + clock-output-names = "osc32k", "osc32k-out", "iosc"; -+ clocks = <&ext_osc32k>; + #clock-cells = <1>; + }; + @@ -900,7 +1264,7 @@ index a117f479ae..148bf0107b 100644 <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; -@@ -651,6 +822,7 @@ +@@ -651,6 +916,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x07020400 0x20>; interrupts = ; @@ -908,7 +1272,7 @@ index a117f479ae..148bf0107b 100644 }; r_intc: interrupt-controller@7021000 { -@@ -667,7 +839,7 @@ +@@ -667,7 +933,7 @@ reg = <0x07022000 0x400>; interrupts = , ; @@ -917,7 +1281,7 @@ index a117f479ae..148bf0107b 100644 clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; -@@ -678,10 +850,30 @@ +@@ -678,10 +944,30 @@ pins = "PL0", "PL1"; function = "s_i2c"; }; @@ -949,7 +1313,7 @@ index a117f479ae..148bf0107b 100644 reg = <0x07081400 0x400>; interrupts = ; clocks = <&r_ccu CLK_R_APB2_I2C>; -@@ -692,5 +884,31 @@ +@@ -692,5 +978,55 @@ #address-cells = <1>; #size-cells = <0>; }; @@ -972,6 +1336,30 @@ index a117f479ae..148bf0107b 100644 + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; ++ ++ trips { ++ cpu_alert: cpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu-crit { ++ temperature = <100000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + gpu-thermal { @@ -982,410 +1370,5 @@ index a117f479ae..148bf0107b 100644 }; }; -- -2.24.1 - -From 80ad66ba5e6fbb4e2758643b09d911d8aba6a068 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 18 Nov 2019 09:54:43 +0100 -Subject: [PATCH 4/4] arm64: dts: sun50i: Add support for Orange Pi 3 - -The dts is taken from the linux-next commit: -98d25b0b266d Merge branch 'sunxi/dt-for-5.6' into sunxi/for-next - -The Bluetooth controller of this device ships with a default adress, -use the new CONFIG_FIXUP_BDADDR option to fix it up. - -Signed-off-by: Andre Heider -Acked-by: Maxime Ripard ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/sun50i-h6-orangepi-3.dts | 322 ++++++++++++++++++++++++++ - board/sunxi/MAINTAINERS | 5 + - configs/orangepi_3_defconfig | 18 ++ - 4 files changed, 346 insertions(+) - create mode 100644 arch/arm/dts/sun50i-h6-orangepi-3.dts - create mode 100644 configs/orangepi_3_defconfig - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 6915783d9c..c1b891d06b 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -556,6 +556,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ - sun50i-h5-orangepi-zero-plus2.dtb - dtb-$(CONFIG_MACH_SUN50I_H6) += \ - sun50i-h6-beelink-gs1.dtb \ -+ sun50i-h6-orangepi-3.dtb \ - sun50i-h6-orangepi-lite2.dtb \ - sun50i-h6-orangepi-one-plus.dtb \ - sun50i-h6-pine-h64.dtb -diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts -new file mode 100644 -index 0000000000..c311eee52a ---- /dev/null -+++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts -@@ -0,0 +1,322 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright (C) 2019 Ondřej Jirman -+ -+/dts-v1/; -+ -+#include "sun50i-h6.dtsi" -+ -+#include -+ -+/ { -+ model = "OrangePi 3"; -+ compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; -+ -+ aliases { -+ serial0 = &uart0; -+ serial1 = &uart1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ connector { -+ compatible = "hdmi-connector"; -+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ power { -+ label = "orangepi:red:power"; -+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ -+ default-state = "on"; -+ }; -+ -+ status { -+ label = "orangepi:green:status"; -+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ -+ }; -+ }; -+ -+ reg_vcc5v: vcc5v { -+ /* board wide 5V supply directly from the DC jack */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-5v"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ reg_vcc33_wifi: vcc33-wifi { -+ /* Always on 3.3V regulator for WiFi and BT */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc33-wifi"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_vcc5v>; -+ }; -+ -+ reg_vcc_wifi_io: vcc-wifi-io { -+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-wifi-io"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ vin-supply = <®_vcc33_wifi>; -+ }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; -+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ -+ post-power-on-delay-ms = <200>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <®_dcdca>; -+}; -+ -+&de { -+ status = "okay"; -+}; -+ -+&dwc3 { -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <®_dcdcc>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&mmc0 { -+ vmmc-supply = <®_cldo1>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc33_wifi>; -+ vqmmc-supply = <®_vcc_wifi_io>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ brcm: sdio-wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&r_pio>; -+ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&ohci3 { -+ status = "okay"; -+}; -+ -+&pio { -+ vcc-pc-supply = <®_bldo2>; -+ vcc-pd-supply = <®_cldo1>; -+ vcc-pg-supply = <®_vcc_wifi_io>; -+}; -+ -+&r_i2c { -+ status = "okay"; -+ -+ axp805: pmic@36 { -+ compatible = "x-powers,axp805", "x-powers,axp806"; -+ reg = <0x36>; -+ interrupt-parent = <&r_intc>; -+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ x-powers,self-working-mode; -+ vina-supply = <®_vcc5v>; -+ vinb-supply = <®_vcc5v>; -+ vinc-supply = <®_vcc5v>; -+ vind-supply = <®_vcc5v>; -+ vine-supply = <®_vcc5v>; -+ aldoin-supply = <®_vcc5v>; -+ bldoin-supply = <®_vcc5v>; -+ cldoin-supply = <®_vcc5v>; -+ -+ regulators { -+ reg_aldo1: aldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-pl-led-ir"; -+ }; -+ -+ reg_aldo2: aldo2 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc33-audio-tv-ephy-mac"; -+ }; -+ -+ /* ALDO3 is shorted to CLDO1 */ -+ reg_aldo3: aldo3 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; -+ }; -+ -+ reg_bldo1: bldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc18-dram-bias-pll"; -+ }; -+ -+ reg_bldo2: bldo2 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc-efuse-pcie-hdmi-pc"; -+ }; -+ -+ bldo3 { -+ /* unused */ -+ }; -+ -+ bldo4 { -+ /* unused */ -+ }; -+ -+ reg_cldo1: cldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; -+ }; -+ -+ cldo2 { -+ /* unused */ -+ }; -+ -+ cldo3 { -+ /* unused */ -+ }; -+ -+ reg_dcdca: dcdca { -+ regulator-always-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1160000>; -+ regulator-name = "vdd-cpu"; -+ }; -+ -+ reg_dcdcc: dcdcc { -+ regulator-enable-ramp-delay = <32000>; -+ regulator-min-microvolt = <810000>; -+ regulator-max-microvolt = <1080000>; -+ regulator-name = "vdd-gpu"; -+ }; -+ -+ reg_dcdcd: dcdcd { -+ regulator-always-on; -+ regulator-min-microvolt = <960000>; -+ regulator-max-microvolt = <960000>; -+ regulator-name = "vdd-sys"; -+ }; -+ -+ reg_dcdce: dcdce { -+ regulator-always-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "vcc-dram"; -+ }; -+ -+ sw { -+ /* unused */ -+ }; -+ }; -+ }; -+}; -+ -+&r_ir { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_ph_pins>; -+ status = "okay"; -+}; -+ -+/* There's the BT part of the AP6256 connected to that UART */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rtc 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ -+ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ -+ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ -+ max-speed = <1500000>; -+ }; -+}; -+ -+&usb2otg { -+ /* -+ * This board doesn't have a controllable VBUS even though it -+ * does have an ID pin. Using it as anything but a USB host is -+ * unsafe. -+ */ -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb2phy { -+ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ -+ usb0_vbus-supply = <®_vcc5v>; -+ usb3_vbus-supply = <®_vcc5v>; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS -index 1180b86db3..c725af2046 100644 ---- a/board/sunxi/MAINTAINERS -+++ b/board/sunxi/MAINTAINERS -@@ -385,6 +385,11 @@ M: Icenowy Zheng - S: Maintained - F: configs/teres_i_defconfig - -+ORANGEPI 3 BOARD -+M: Andre Heider -+S: Maintained -+F: configs/orangepi_3_defconfig -+ - ORANGEPI LITE2 BOARD - M: Jagan Teki - S: Maintained -diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig -new file mode 100644 -index 0000000000..c9db0abb77 ---- /dev/null -+++ b/configs/orangepi_3_defconfig -@@ -0,0 +1,18 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SPL=y -+CONFIG_MACH_SUN50I_H6=y -+CONFIG_SUNXI_DRAM_H6_LPDDR3=y -+CONFIG_MMC0_CD_PIN="PF6" -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -+CONFIG_FIXUP_BDADDR="brcm,bcm4345c5" -+# CONFIG_PSCI_RESET is not set -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_USE_PREBOOT=y -+# CONFIG_CMD_FLASH is not set -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_SPL_EFI_PARTITION is not set -+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3" -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y --- -2.24.1 +2.30.0 diff --git a/projects/Allwinner/devices/H6/patches/u-boot/0003-sunxi-Add-support-for-Tanix-TX6.patch b/projects/Allwinner/devices/H6/patches/u-boot/0003-sunxi-Add-support-for-Tanix-TX6.patch new file mode 100644 index 0000000000..dd01738fd8 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/u-boot/0003-sunxi-Add-support-for-Tanix-TX6.patch @@ -0,0 +1,201 @@ +From 6edd6f3d8ee26d37a557a890fa75e0840c6273db Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 3 Jan 2021 10:50:27 +0100 +Subject: [PATCH v3 2/2] sunxi: Add support for Tanix TX6 + +This commit adds support for Tanix TX6 TV box, based on H6. It's low end +H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other +peripherals. + +DT file is taken from Linux 5.11-rc1 release. + +Signed-off-by: Jernej Skrabec +--- + arch/arm/dts/Makefile | 3 +- + arch/arm/dts/sun50i-h6-tanix-tx6.dts | 124 +++++++++++++++++++++++++++ + board/sunxi/MAINTAINERS | 6 ++ + configs/tanix_tx6_defconfig | 10 +++ + 4 files changed, 142 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6.dts + create mode 100644 configs/tanix_tx6_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index fd47e408f826..e00aed1ec207 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -607,7 +607,8 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-beelink-gs1.dtb \ + sun50i-h6-orangepi-lite2.dtb \ + sun50i-h6-orangepi-one-plus.dtb \ +- sun50i-h6-pine-h64.dtb ++ sun50i-h6-pine-h64.dtb \ ++ sun50i-h6-tanix-tx6.dtb + dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-amarula-relic.dtb \ + sun50i-a64-bananapi-m64.dtb \ +diff --git a/arch/arm/dts/sun50i-h6-tanix-tx6.dts b/arch/arm/dts/sun50i-h6-tanix-tx6.dts +new file mode 100644 +index 000000000000..be81330db14f +--- /dev/null ++++ b/arch/arm/dts/sun50i-h6-tanix-tx6.dts +@@ -0,0 +1,124 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (c) 2019 Jernej Skrabec ++ ++/dts-v1/; ++ ++#include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" ++ ++#include ++ ++/ { ++ model = "Tanix TX6"; ++ compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ reg_vdd_cpu_gpu: vdd-cpu-gpu { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd-cpu-gpu"; ++ regulator-min-microvolt = <1135000>; ++ regulator-max-microvolt = <1135000>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vdd_cpu_gpu>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&dwc3 { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <®_vdd_cpu_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&r_ir { ++ linux,rc-map-name = "rc-tanix-tx5max"; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&usb2otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb2phy { ++ status = "okay"; ++}; ++ ++&usb3phy { ++ status = "okay"; ++}; +diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS +index d3755ae41a9d..1b37a9899edd 100644 +--- a/board/sunxi/MAINTAINERS ++++ b/board/sunxi/MAINTAINERS +@@ -489,6 +489,12 @@ S: Maintained + F: configs/Sunchip_CX-A99_defconfig + W: https://linux-sunxi.org/Sunchip_CX-A99 + ++TANIX TX6 BOARD ++M: Jernej Skrabec ++S: Maintained ++F: configs/tanix_tx6_defconfig ++W: https://linux-sunxi.org/Tanix_TX6 ++ + TBS A711 BOARD + M: Maxime Ripard + S: Maintained +diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig +new file mode 100644 +index 000000000000..9ce812ecc35d +--- /dev/null ++++ b/configs/tanix_tx6_defconfig +@@ -0,0 +1,10 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I_H6=y ++CONFIG_SUNXI_DRAM_H6_DDR3_1333=y ++CONFIG_DRAM_CLK=648 ++CONFIG_MMC0_CD_PIN="PF6" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-tanix-tx6" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +-- +2.30.0 + diff --git a/projects/Allwinner/devices/H6/patches/u-boot/0004-sunxi-board-extract-creating-a-unique-sid-into-a-hel.patch b/projects/Allwinner/devices/H6/patches/u-boot/0004-sunxi-board-extract-creating-a-unique-sid-into-a-hel.patch new file mode 100644 index 0000000000..b0aa49881b --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/u-boot/0004-sunxi-board-extract-creating-a-unique-sid-into-a-hel.patch @@ -0,0 +1,159 @@ +From a0770d90e89c03115eaf1c22d74b955f37b8ddbd Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Tue, 26 Nov 2019 12:38:46 +0100 +Subject: [PATCH 1/3] sunxi: board: extract creating a unique sid into a helper + function + +Refactor setup_environment() so we can use the created sid for a +Bluetooth address too. + +Signed-off-by: Andre Heider +Acked-by: Maxime Ripard +[rebased] +Signed-off-by: Jernej Skrabec +--- + board/sunxi/board.c | 121 ++++++++++++++++++++++++-------------------- + 1 file changed, 66 insertions(+), 55 deletions(-) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 708a27ed78e9..4a29e351141b 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -789,6 +789,38 @@ static void parse_spl_header(const uint32_t spl_addr) + env_set_hex("fel_scriptaddr", spl->fel_script_address); + } + ++static bool get_unique_sid(unsigned int *sid) ++{ ++ if (sunxi_get_sid(sid) != 0) ++ return false; ++ ++ if (!sid[0]) ++ return false; ++ ++ /* ++ * The single words 1 - 3 of the SID have quite a few bits ++ * which are the same on many models, so we take a crc32 ++ * of all 3 words, to get a more unique value. ++ * ++ * Note we only do this on newer SoCs as we cannot change ++ * the algorithm on older SoCs since those have been using ++ * fixed mac-addresses based on only using word 3 for a ++ * long time and changing a fixed mac-address with an ++ * u-boot update is not good. ++ */ ++#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ ++ !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ ++ !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) ++ sid[3] = crc32(0, (unsigned char *)&sid[1], 12); ++#endif ++ ++ /* Ensure the NIC specific bytes of the mac are not all 0 */ ++ if ((sid[3] & 0xffffff) == 0) ++ sid[3] |= 0x800000; ++ ++ return true; ++} ++ + /* + * Note this function gets called multiple times. + * It must not make any changes to env variables which already exist. +@@ -799,61 +831,40 @@ static void setup_environment(const void *fdt) + unsigned int sid[4]; + uint8_t mac_addr[6]; + char ethaddr[16]; +- int i, ret; +- +- ret = sunxi_get_sid(sid); +- if (ret == 0 && sid[0] != 0) { +- /* +- * The single words 1 - 3 of the SID have quite a few bits +- * which are the same on many models, so we take a crc32 +- * of all 3 words, to get a more unique value. +- * +- * Note we only do this on newer SoCs as we cannot change +- * the algorithm on older SoCs since those have been using +- * fixed mac-addresses based on only using word 3 for a +- * long time and changing a fixed mac-address with an +- * u-boot update is not good. +- */ +-#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ +- !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ +- !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) +- sid[3] = crc32(0, (unsigned char *)&sid[1], 12); +-#endif +- +- /* Ensure the NIC specific bytes of the mac are not all 0 */ +- if ((sid[3] & 0xffffff) == 0) +- sid[3] |= 0x800000; +- +- for (i = 0; i < 4; i++) { +- sprintf(ethaddr, "ethernet%d", i); +- if (!fdt_get_alias(fdt, ethaddr)) +- continue; +- +- if (i == 0) +- strcpy(ethaddr, "ethaddr"); +- else +- sprintf(ethaddr, "eth%daddr", i); +- +- if (env_get(ethaddr)) +- continue; +- +- /* Non OUI / registered MAC address */ +- mac_addr[0] = (i << 4) | 0x02; +- mac_addr[1] = (sid[0] >> 0) & 0xff; +- mac_addr[2] = (sid[3] >> 24) & 0xff; +- mac_addr[3] = (sid[3] >> 16) & 0xff; +- mac_addr[4] = (sid[3] >> 8) & 0xff; +- mac_addr[5] = (sid[3] >> 0) & 0xff; +- +- eth_env_set_enetaddr(ethaddr, mac_addr); +- } +- +- if (!env_get("serial#")) { +- snprintf(serial_string, sizeof(serial_string), +- "%08x%08x", sid[0], sid[3]); +- +- env_set("serial#", serial_string); +- } ++ int i; ++ ++ if (!get_unique_sid(sid)) ++ return; ++ ++ for (i = 0; i < 4; i++) { ++ sprintf(ethaddr, "ethernet%d", i); ++ if (!fdt_get_alias(fdt, ethaddr)) ++ continue; ++ ++ if (i == 0) ++ strcpy(ethaddr, "ethaddr"); ++ else ++ sprintf(ethaddr, "eth%daddr", i); ++ ++ if (env_get(ethaddr)) ++ continue; ++ ++ /* Non OUI / registered MAC address */ ++ mac_addr[0] = (i << 4) | 0x02; ++ mac_addr[1] = (sid[0] >> 0) & 0xff; ++ mac_addr[2] = (sid[3] >> 24) & 0xff; ++ mac_addr[3] = (sid[3] >> 16) & 0xff; ++ mac_addr[4] = (sid[3] >> 8) & 0xff; ++ mac_addr[5] = (sid[3] >> 0) & 0xff; ++ ++ eth_env_set_enetaddr(ethaddr, mac_addr); ++ } ++ ++ if (!env_get("serial#")) { ++ snprintf(serial_string, sizeof(serial_string), ++ "%08x%08x", sid[0], sid[3]); ++ ++ env_set("serial#", serial_string); + } + } + +-- +2.30.0 + diff --git a/projects/Allwinner/devices/H6/patches/u-boot/0005-arm-sunxi-add-a-config-option-to-fixup-a-Bluetooth-a.patch b/projects/Allwinner/devices/H6/patches/u-boot/0005-arm-sunxi-add-a-config-option-to-fixup-a-Bluetooth-a.patch new file mode 100644 index 0000000000..e9f62fa708 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/u-boot/0005-arm-sunxi-add-a-config-option-to-fixup-a-Bluetooth-a.patch @@ -0,0 +1,96 @@ +From c8216074411efbc484d2e308451477fa9f4e342c Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Sun, 17 Nov 2019 20:24:43 +0100 +Subject: [PATCH 2/3] arm: sunxi: add a config option to fixup a Bluetooth + address + +Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3, +ship with the controller default address. + +Add a config option to fix it up so it can function properly. + +Signed-off-by: Andre Heider +Tested-by: Ondrej Jirman +Acked-by: Maxime Ripard +[rebased] +Signed-off-by: Jernej Skrabec +--- + arch/arm/mach-sunxi/Kconfig | 11 +++++++++++ + board/sunxi/board.c | 34 ++++++++++++++++++++++++++++++++++ + 2 files changed, 45 insertions(+) + +diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig +index 49ef217f08c0..269aef5f01a1 100644 +--- a/arch/arm/mach-sunxi/Kconfig ++++ b/arch/arm/mach-sunxi/Kconfig +@@ -1016,4 +1016,15 @@ config PINEPHONE_DT_SELECTION + Enable this option to automatically select the device tree for the + correct PinePhone hardware revision during boot. + ++config FIXUP_BDADDR ++ string "Fixup the Bluetooth controller address" ++ default "" ++ help ++ This option specifies the DT compatible name of the Bluetooth ++ controller for which to set the "local-bd-address" property. ++ Set this option if your device ships with the Bluetooth controller ++ default address. ++ The used address is "bdaddr" if set, and "ethaddr" with the LSB ++ flipped elsewise. ++ + endif +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 4a29e351141b..d19119b7eb36 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -908,6 +908,38 @@ int misc_init_r(void) + return 0; + } + ++static void fixup_bd_address(void *blob) ++{ ++ /* Some devices ship with a Bluetooth controller default address. ++ * Set a valid address through the device tree. ++ */ ++ uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN]; ++ unsigned int sid[4]; ++ int i; ++ ++ if (!CONFIG_FIXUP_BDADDR[0]) ++ return; ++ ++ if (eth_env_get_enetaddr("bdaddr", tmp)) { ++ /* Convert between the binary formats of the corresponding stacks */ ++ for (i = 0; i < ETH_ALEN; ++i) ++ bdaddr[i] = tmp[ETH_ALEN - i - 1]; ++ } else { ++ if (!get_unique_sid(sid)) ++ return; ++ ++ bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1; ++ bdaddr[1] = (sid[3] >> 8) & 0xff; ++ bdaddr[2] = (sid[3] >> 16) & 0xff; ++ bdaddr[3] = (sid[3] >> 24) & 0xff; ++ bdaddr[4] = (sid[0] >> 0) & 0xff; ++ bdaddr[5] = 0x02; ++ } ++ ++ do_fixup_by_compat(blob, CONFIG_FIXUP_BDADDR, ++ "local-bd-address", bdaddr, ETH_ALEN, 1); ++} ++ + int ft_board_setup(void *blob, struct bd_info *bd) + { + int __maybe_unused r; +@@ -918,6 +950,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) + */ + setup_environment(blob); + ++ fixup_bd_address(blob); ++ + #ifdef CONFIG_VIDEO_DT_SIMPLEFB + r = sunxi_simplefb_setup(blob); + if (r) +-- +2.30.0 + diff --git a/projects/Allwinner/devices/H6/patches/u-boot/0007-arm64-dts-sun50i-Add-support-for-Orange-Pi-3.patch b/projects/Allwinner/devices/H6/patches/u-boot/0007-arm64-dts-sun50i-Add-support-for-Orange-Pi-3.patch new file mode 100644 index 0000000000..8a1331e5e6 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/u-boot/0007-arm64-dts-sun50i-Add-support-for-Orange-Pi-3.patch @@ -0,0 +1,424 @@ +From ebbb185d268f795de19aa4d2934531ec61a8ed84 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Mon, 18 Nov 2019 09:54:43 +0100 +Subject: [PATCH 3/3] arm64: dts: sun50i: Add support for Orange Pi 3 + +dts file is taken from Linux 5.11-rc1 tag. + +The Bluetooth controller of this device ships with a default address, +use the new CONFIG_FIXUP_BDADDR option to fix it up. + +Signed-off-by: Andre Heider +Acked-by: Maxime Ripard +[Updated OrangePi 3 DT, rebase and config update] +Signed-off-by: Jernej Skrabec +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/sun50i-h6-orangepi-3.dts | 345 ++++++++++++++++++++++++++ + board/sunxi/MAINTAINERS | 5 + + configs/orangepi_3_defconfig | 13 + + 4 files changed, 364 insertions(+) + create mode 100644 arch/arm/dts/sun50i-h6-orangepi-3.dts + create mode 100644 configs/orangepi_3_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index e00aed1ec207..607571d04b25 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -605,6 +605,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-orangepi-zero-plus2.dtb + dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-beelink-gs1.dtb \ ++ sun50i-h6-orangepi-3.dtb \ + sun50i-h6-orangepi-lite2.dtb \ + sun50i-h6-orangepi-one-plus.dtb \ + sun50i-h6-pine-h64.dtb \ +diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts +new file mode 100644 +index 000000000000..15c9dd8c4479 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts +@@ -0,0 +1,345 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2019 Ondřej Jirman ++ ++/dts-v1/; ++ ++#include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" ++ ++#include ++ ++/ { ++ model = "OrangePi 3"; ++ compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ ext_osc32k: ext_osc32k_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "ext_osc32k"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power { ++ label = "orangepi:red:power"; ++ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ ++ default-state = "on"; ++ }; ++ ++ status { ++ label = "orangepi:green:status"; ++ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ ++ }; ++ }; ++ ++ reg_vcc5v: vcc5v { ++ /* board wide 5V supply directly from the DC jack */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_vcc33_wifi: vcc33-wifi { ++ /* Always on 3.3V regulator for WiFi and BT */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc33-wifi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc33_wifi>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&dwc3 { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <®_dcdcc>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_cldo1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc33_wifi>; ++ vqmmc-supply = <®_vcc_wifi_io>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcm: sdio-wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ vmmc-supply = <®_cldo1>; ++ vqmmc-supply = <®_bldo2>; ++ cap-mmc-hw-reset; ++ non-removable; ++ bus-width = <8>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_vcc_wifi_io>; ++}; ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp805: pmic@36 { ++ compatible = "x-powers,axp805", "x-powers,axp806"; ++ reg = <0x36>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ x-powers,self-working-mode; ++ vina-supply = <®_vcc5v>; ++ vinb-supply = <®_vcc5v>; ++ vinc-supply = <®_vcc5v>; ++ vind-supply = <®_vcc5v>; ++ vine-supply = <®_vcc5v>; ++ aldoin-supply = <®_vcc5v>; ++ bldoin-supply = <®_vcc5v>; ++ cldoin-supply = <®_vcc5v>; ++ ++ regulators { ++ reg_aldo1: aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl-led-ir"; ++ }; ++ ++ reg_aldo2: aldo2 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-audio-tv-ephy-mac"; ++ }; ++ ++ /* ALDO3 is shorted to CLDO1 */ ++ reg_aldo3: aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; ++ }; ++ ++ reg_bldo1: bldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc18-dram-bias-pll"; ++ }; ++ ++ reg_bldo2: bldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-efuse-pcie-hdmi-pc"; ++ }; ++ ++ bldo3 { ++ /* unused */ ++ }; ++ ++ bldo4 { ++ /* unused */ ++ }; ++ ++ reg_cldo1: cldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; ++ }; ++ ++ cldo2 { ++ /* unused */ ++ }; ++ ++ cldo3 { ++ /* unused */ ++ }; ++ ++ reg_dcdca: dcdca { ++ regulator-always-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-ramp-delay = <2500>; ++ regulator-name = "vdd-cpu"; ++ }; ++ ++ reg_dcdcc: dcdcc { ++ regulator-enable-ramp-delay = <32000>; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <1080000>; ++ regulator-ramp-delay = <2500>; ++ regulator-name = "vdd-gpu"; ++ }; ++ ++ reg_dcdcd: dcdcd { ++ regulator-always-on; ++ regulator-min-microvolt = <960000>; ++ regulator-max-microvolt = <960000>; ++ regulator-name = "vdd-sys"; ++ }; ++ ++ reg_dcdce: dcdce { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++ }; ++ ++ sw { ++ /* unused */ ++ }; ++ }; ++ }; ++}; ++ ++&r_ir { ++ status = "okay"; ++}; ++ ++&rtc { ++ clocks = <&ext_osc32k>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++/* There's the BT part of the AP6256 connected to that UART */ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ ++ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ ++ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ ++ max-speed = <1500000>; ++ }; ++}; ++ ++&usb2otg { ++ /* ++ * This board doesn't have a controllable VBUS even though it ++ * does have an ID pin. Using it as anything but a USB host is ++ * unsafe. ++ */ ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb2phy { ++ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ ++ usb0_vbus-supply = <®_vcc5v>; ++ usb3_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&usb3phy { ++ status = "okay"; ++}; +diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS +index 1b37a9899edd..95b4df83e0a9 100644 +--- a/board/sunxi/MAINTAINERS ++++ b/board/sunxi/MAINTAINERS +@@ -385,6 +385,11 @@ M: Icenowy Zheng + S: Maintained + F: configs/teres_i_defconfig + ++ORANGEPI 3 BOARD ++M: Andre Heider ++S: Maintained ++F: configs/orangepi_3_defconfig ++ + ORANGEPI LITE2 BOARD + M: Jagan Teki + S: Maintained +diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig +new file mode 100644 +index 000000000000..6a4a11739213 +--- /dev/null ++++ b/configs/orangepi_3_defconfig +@@ -0,0 +1,13 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I_H6=y ++CONFIG_SUNXI_DRAM_H6_LPDDR3=y ++CONFIG_MMC0_CD_PIN="PF6" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_FIXUP_BDADDR="brcm,bcm4345c5" ++# CONFIG_PSCI_RESET is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y +-- +2.30.0 + diff --git a/projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch b/projects/Allwinner/devices/H6/patches/u-boot/0008-orange-pi-3-ethernet.patch similarity index 86% rename from projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch rename to projects/Allwinner/devices/H6/patches/u-boot/0008-orange-pi-3-ethernet.patch index 1e17bf7ef9..3dcfa6d6af 100644 --- a/projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch +++ b/projects/Allwinner/devices/H6/patches/u-boot/0008-orange-pi-3-ethernet.patch @@ -72,20 +72,3 @@ &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -@@ -136,6 +180,16 @@ - }; - }; - -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_pins>; -+ vmmc-supply = <®_cldo1>; -+ non-removable; -+ cap-mmc-hw-reset; -+ bus-width = <8>; -+ status = "okay"; -+}; -+ - &ohci0 { - status = "okay"; - }; diff --git a/projects/Allwinner/devices/H6/patches/u-boot/007-ethernet-hack.patch b/projects/Allwinner/devices/H6/patches/u-boot/0009-tanix-tx6-ethernet-hack.patch similarity index 75% rename from projects/Allwinner/devices/H6/patches/u-boot/007-ethernet-hack.patch rename to projects/Allwinner/devices/H6/patches/u-boot/0009-tanix-tx6-ethernet-hack.patch index ba7e838575..88b5421186 100644 --- a/projects/Allwinner/devices/H6/patches/u-boot/007-ethernet-hack.patch +++ b/projects/Allwinner/devices/H6/patches/u-boot/0009-tanix-tx6-ethernet-hack.patch @@ -4,13 +4,13 @@ Date: Thu, 11 Jul 2019 23:28:58 +0200 Subject: [PATCH] ethernet hack --- - arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts | 14 ++++++++++++++ + arch/arm/dts/sun50i-h6-tanix-tx6.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -diff --git a/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts b/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts +diff --git a/arch/arm/dts/sun50i-h6-tanix-tx6.dts b/arch/arm/dts/sun50i-h6-tanix-tx6.dts index c217955a39..5c0099f1a7 100644 ---- a/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts -+++ b/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts +--- a/arch/arm/dts/sun50i-h6-tanix-tx6.dts ++++ b/arch/arm/dts/sun50i-h6-tanix-tx6.dts @@ -16,6 +16,7 @@ compatible = "eachlink,h6-mini", "allwinner,sun50i-h6"; diff --git a/projects/Allwinner/devices/H6/patches/u-boot/0010-unreliable-dram.patch b/projects/Allwinner/devices/H6/patches/u-boot/0010-unreliable-dram.patch new file mode 100644 index 0000000000..222c60b429 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/u-boot/0010-unreliable-dram.patch @@ -0,0 +1,40 @@ +From: megous@megous.com +Date: Mon, 29 Jul 2019 01:39:42 +0200 +Subject: [U-Boot] [PATCH] Fix unreliable detection of DRAM size on Orange Pi 3 + +From: Ondrej Jirman + +Orange Pi 3 has 2 GiB of DRAM, that sometime get misdetected +as 4 GiB, due to false negative result from mctl_mem_matches() +when detecting number of column address bits. This leads to +u-boot detecting more address bits than there are and the +boot process hangs shortly after. + +In mctl_mem_matches() we need to wait for each write to finish, +separately. Without this, the check is not reliable for some +unknown reason, probably having to do with unpredictable memory +access ordering. + +Patch was made with help from André Przywara, who noticed that +my original idea about detection failing due to read-back from +cache without involving DRAM was false, because data cache is +still of at the time of the DRAM size autodetection. + +Signed-off-by: Ondrej Jirman +Cc: André Przywara +--- + arch/arm/mach-sunxi/dram_helpers.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c +index 239ab421a8..6dba448638 100644 +--- a/arch/arm/mach-sunxi/dram_helpers.c ++++ b/arch/arm/mach-sunxi/dram_helpers.c +@@ -30,6 +30,7 @@ bool mctl_mem_matches(u32 offset) + { + /* Try to write different values to RAM at two addresses */ + writel(0, CONFIG_SYS_SDRAM_BASE); ++ dsb(); + writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); + dsb(); + /* Check if the same value is actually observed when reading back */ diff --git a/projects/Allwinner/devices/H6/patches/u-boot/003-Update-Orange-Pi-One-Plus-for-LibreELEC.patch b/projects/Allwinner/devices/H6/patches/u-boot/003-Update-Orange-Pi-One-Plus-for-LibreELEC.patch deleted file mode 100644 index 396da014fb..0000000000 --- a/projects/Allwinner/devices/H6/patches/u-boot/003-Update-Orange-Pi-One-Plus-for-LibreELEC.patch +++ /dev/null @@ -1,82 +0,0 @@ -diff --git a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts -index 12e17567ab..4c3447417f 100644 ---- a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts -+++ b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts -@@ -9,4 +9,77 @@ - / { - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; -+ -+ aliases { -+ ethernet0 = &emac; -+ }; -+ -+ connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ ddc-supply = <®_ddc>; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ reg_ddc: ddc-io { -+ compatible = "regulator-fixed"; -+ regulator-name = "ddc-io"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ -+ }; -+ -+ reg_gmac_2v5: gmac-2v5 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-2v5"; -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ -+ -+ /* The real parent of gmac-2v5 is reg_vcc5v, but we need to -+ * enable two regulators to power the phy. This is one way -+ * to achieve that. -+ */ -+ vin-supply = <®_aldo2>; /* GMAC-3V3 */ -+ }; -+}; -+ -+&de { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ext_rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-supply = <®_gmac_2v5>; -+ allwinner,rx-delay-ps = <1500>; -+ allwinner,tx-delay-ps = <700>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; - }; diff --git a/projects/Allwinner/devices/H6/patches/u-boot/004-unreliable-dram.patch b/projects/Allwinner/devices/H6/patches/u-boot/004-unreliable-dram.patch deleted file mode 100644 index 4851cc205a..0000000000 --- a/projects/Allwinner/devices/H6/patches/u-boot/004-unreliable-dram.patch +++ /dev/null @@ -1,104 +0,0 @@ -From patchwork Sun Jul 28 23:39:42 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= -X-Patchwork-Id: 1138087 -X-Patchwork-Delegate: jagannadh.teki@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=none (mailfrom) smtp.mailfrom=lists.denx.de - (client-ip=81.169.180.215; helo=lists.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=megous.com -Authentication-Results: ozlabs.org; - dkim=fail reason="signature verification failed" (1024-bit key; - unprotected) header.d=megous.com header.i=@megous.com - header.b="CrQpjmRT"; dkim-atps=neutral -Received: from lists.denx.de (dione.denx.de [81.169.180.215]) - by ozlabs.org (Postfix) with ESMTP id 45xfSd39Cgz9sBt - for ; - Mon, 29 Jul 2019 09:40:15 +1000 (AEST) -Received: by lists.denx.de (Postfix, from userid 105) - id B2080C21C6A; Sun, 28 Jul 2019 23:40:01 +0000 (UTC) -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de -X-Spam-Level: -X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID - autolearn=unavailable autolearn_force=no version=3.4.0 -Received: from lists.denx.de (localhost [IPv6:::1]) - by lists.denx.de (Postfix) with ESMTP id 4ADF8C21C2F; - Sun, 28 Jul 2019 23:40:00 +0000 (UTC) -Received: by lists.denx.de (Postfix, from userid 105) - id 6153DC21C2F; Sun, 28 Jul 2019 23:39:58 +0000 (UTC) -Received: from vps.xff.cz (vps.xff.cz [195.181.215.36]) - by lists.denx.de (Postfix) with ESMTPS id 01E68C21C2C - for ; Sun, 28 Jul 2019 23:39:58 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; - t=1564357197; bh=O569bOUuJGqDJElKbA3RSmC4Fo1qMuQYR/PPaLa2AAo=; - h=From:To:Cc:Subject:Date:From; - b=CrQpjmRTeDQh+lZWj24nnowLe5dFPiJtkSEF1vR2ioP52kdNo+KsrhhPYOL5zP4s8 - ty4iCkZUQ2Fov/BIVCPJJEgeBBTEFTWzfXyDxIbvgWya45gG3FlGFjyrh52+e3T4zk - t9n7yy1iXLNInpC9uJRwJPMee3pcSZKVudimC7DY= -From: megous@megous.com -To: u-boot@lists.denx.de -Date: Mon, 29 Jul 2019 01:39:42 +0200 -Message-Id: <20190728233942.9767-1-megous@megous.com> -MIME-Version: 1.0 -Cc: Ondrej Jirman , =?utf-8?q?Andr=C3=A9_Przywara?= - , Maxime Ripard -Subject: [U-Boot] [PATCH] Fix unreliable detection of DRAM size on Orange Pi 3 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.18 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Content-Type: text/plain; charset="utf-8" -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" - -From: Ondrej Jirman - -Orange Pi 3 has 2 GiB of DRAM, that sometime get misdetected -as 4 GiB, due to false negative result from mctl_mem_matches() -when detecting number of column address bits. This leads to -u-boot detecting more address bits than there are and the -boot process hangs shortly after. - -In mctl_mem_matches() we need to wait for each write to finish, -separately. Without this, the check is not reliable for some -unknown reason, probably having to do with unpredictable memory -access ordering. - -Patch was made with help from André Przywara, who noticed that -my original idea about detection failing due to read-back from -cache without involving DRAM was false, because data cache is -still of at the time of the DRAM size autodetection. - -Signed-off-by: Ondrej Jirman -Cc: André Przywara ---- - arch/arm/mach-sunxi/dram_helpers.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c -index 239ab421a8..6dba448638 100644 ---- a/arch/arm/mach-sunxi/dram_helpers.c -+++ b/arch/arm/mach-sunxi/dram_helpers.c -@@ -30,6 +30,7 @@ bool mctl_mem_matches(u32 offset) - { - /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); -+ dsb(); - writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); - dsb(); - /* Check if the same value is actually observed when reading back */ diff --git a/projects/Allwinner/devices/H6/patches/u-boot/006-DDR3.patch b/projects/Allwinner/devices/H6/patches/u-boot/006-DDR3.patch deleted file mode 100644 index 197a9e503c..0000000000 --- a/projects/Allwinner/devices/H6/patches/u-boot/006-DDR3.patch +++ /dev/null @@ -1,181 +0,0 @@ -From ed8d12f7e9b86a20221030ba8609e05308813c5e Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Fri, 16 Nov 2018 01:38:32 +0000 -Subject: [PATCH 7/7] sunxi: H6: Add basic Eachlink H6 Mini support - -The Eachlink H6 Mini is a modestly priced TV box, using the Allwinner H6 -SoC. It comes with 4GB of DRAM (3GB usable) and 32GB of eMMC in the -typical TV box enclosure. -This adds a basic device tree and defconfig for it. - -It contrast to the other supported H6 boards the H6 Mini uses DDR3 DRAM -chips (not LPDDR3), which require a different DRAM controller setup. - -Signed-off-by: Andre Przywara ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts | 116 ++++++++++++++++++++ - configs/eachlink_h6_mini_defconfig | 17 +++ - 3 files changed, 134 insertions(+) - create mode 100644 arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts - create mode 100644 configs/eachlink_h6_mini_defconfig - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 528fb909d5..c463aca190 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -507,6 +507,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ - sun50i-h5-orangepi-prime.dtb \ - sun50i-h5-orangepi-zero-plus2.dtb - dtb-$(CONFIG_MACH_SUN50I_H6) += \ -+ sun50i-h6-eachlink-h6-mini.dtb \ - sun50i-h6-beelink-gs1.dtb \ - sun50i-h6-orangepi-lite2.dtb \ - sun50i-h6-orangepi-one-plus.dtb \ -diff --git a/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts b/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts -new file mode 100644 -index 0000000000..c217955a39 ---- /dev/null -+++ b/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts -@@ -0,0 +1,116 @@ -+// SPDX-License-Identifier: (GPL-2.0+ or MIT) -+/* -+ * Copyright (c) 2018 Arm Ltd. -+ * based on work by: -+ * Copyright (c) 2017 Icenowy Zheng -+ */ -+ -+/dts-v1/; -+ -+#include "sun50i-h6.dtsi" -+ -+#include -+ -+/ { -+ model = "Eachlink H6 Mini"; -+ compatible = "eachlink,h6-mini", "allwinner,sun50i-h6"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ reg_vcc5v: vcc5v { -+ /* board wide 5V supply directly from the DC jack */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-5v"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&de { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&ehci0 { -+ phys = <&usb2phy 0>; -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&mmc0 { -+ vmmc-supply = <®_vcc3v3>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&mmc2 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ non-removable; -+ cap-mmc-hw-reset; -+ bus-width = <8>; -+ status = "okay"; -+}; -+ -+&ohci0 { -+ phys = <&usb2phy 0>; -+ status = "okay"; -+}; -+ -+&ohci3 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_ph_pins>; -+ status = "okay"; -+}; -+ -+&usb2otg { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb2phy { -+ usb0_vbus-supply = <®_vcc5v>; -+ status = "okay"; -+}; -diff --git a/configs/eachlink_h6_mini_defconfig b/configs/eachlink_h6_mini_defconfig -new file mode 100644 -index 0000000000..d471a24dd5 ---- /dev/null -+++ b/configs/eachlink_h6_mini_defconfig -@@ -0,0 +1,16 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_SPL=y -+CONFIG_MACH_SUN50I_H6=y -+CONFIG_DRAM_CLK=648 -+CONFIG_SUNXI_DRAM_H6_DDR3_1333=y -+CONFIG_MMC0_CD_PIN="PF6" -+# CONFIG_PSCI_RESET is not set -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -+CONFIG_NR_DRAM_BANKS=1 -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_SPL_TEXT_BASE=0x20060 -+# CONFIG_CMD_FLASH is not set -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_SPL_EFI_PARTITION is not set -+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-eachlink-h6-mini" --- -2.22.0 -