diff --git a/packages/linux/patches/3.17.7/linux-011-intel-force-cs-stall.patch b/packages/linux/patches/3.17.7/linux-011-intel-force-cs-stall.patch
new file mode 100644
index 0000000000..81649a6626
--- /dev/null
+++ b/packages/linux/patches/3.17.7/linux-011-intel-force-cs-stall.patch
@@ -0,0 +1,37 @@
+From 78e2b1bdd84264d6a9d84759da26547f887552cd Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Tue, 16 Dec 2014 08:44:32 +0000
+Subject: [PATCH] drm/i915: Force the CS stall for invalidate flushes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In order to act as a full command barrier by itself, we need to tell the
+pipecontrol to actually stall the command streamer while the flush runs.
+We require the full command barrier before operations like
+MI_SET_CONTEXT, which currently rely on a prior invalidate flush.
+
+References: https://bugs.freedesktop.org/show_bug.cgi?id=83677
+Cc: Simon Farnsworth <simon@farnz.org.uk>
+Cc: Daniel Vetter <daniel@ffwll.ch>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: stable@vger.kernel.org
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+---
+ drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
+index b02cf69..ae17e77 100644
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
+@@ -369,6 +369,8 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
+ 		flags |= PIPE_CONTROL_QW_WRITE;
+ 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+ 
++		flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
++
+ 		/* Workaround: we must issue a pipe_control with CS-stall bit
+ 		 * set before a pipe_control command that has the state cache
+ 		 * invalidate bit set. */