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u-boot (Allwinner): remove upstreamed patches
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sun, 8 Mar 2020 08:08:03 +0100
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Subject: [PATCH] OrangePi PC2: Update defaults
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---
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configs/orangepi_pc2_defconfig | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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--- a/configs/orangepi_pc2_defconfig
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+++ b/configs/orangepi_pc2_defconfig
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@@ -5,11 +5,13 @@ CONFIG_SPL=y
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CONFIG_MACH_SUN50I_H5=y
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CONFIG_DRAM_CLK=672
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CONFIG_DRAM_ZQ=3881977
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-# CONFIG_DRAM_ODT_EN is not set
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CONFIG_MACPWR="PD6"
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CONFIG_SPL_SPI_SUNXI=y
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+CONFIG_SPL_I2C_SUPPORT=y
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SUN8I_EMAC=y
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+CONFIG_SY8106A_POWER=y
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+CONFIG_SY8106A_VOUT1_VOLT=1100
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_MUSB_GADGET=y
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@ -1,63 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 18 Apr 2021 22:21:41 -0500
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Subject: [PATCH] sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2
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So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure
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monitor code (providing PSCI runtime services). And while those SoCs do
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not have the secure SRAM B like older SoCs, there is enough (secure)
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SRAM A2 to put the monitor code and data in there instead.
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Follow the design of 64-bit SoCs and use the first part for the monitor,
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and the last 16 KiB for the SCP firmware. With this change, the monitor
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no longer needs to reserve a region in DRAM.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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[Andre: amend commit message, fix R40 and V3s build]
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 11 +++++++++++
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include/configs/sun8i.h | 10 ++++++++++
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2 files changed, 21 insertions(+)
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--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
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+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
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@@ -11,7 +11,18 @@
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#define SUNXI_SRAM_A1_BASE 0x00000000
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#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
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+#if defined(CONFIG_SUNXI_GEN_SUN6I) && \
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+ !defined(CONFIG_MACH_SUN8I_R40) && \
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+ !defined(CONFIG_MACH_SUN8I_V3S)
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+#define SUNXI_SRAM_A2_BASE 0x00040000
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+#ifdef CONFIG_MACH_SUN8I_H3
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+#define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */
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+#else
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+#define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */
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+#endif
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+#else
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#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
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+#endif
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#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
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#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
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#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
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--- a/include/configs/sun8i.h
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+++ b/include/configs/sun8i.h
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@@ -12,6 +12,16 @@
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* A23 specific configuration
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*/
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+#ifdef SUNXI_SRAM_A2_SIZE
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+/*
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+ * If the SoC has enough SRAM A2, use that for the secure monitor.
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+ * Skip the first 16 KiB of SRAM A2, which is not usable, as only certain bytes
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+ * are writable. Reserve the last 17 KiB for the resume shim and SCP firmware.
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+ */
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+#define CONFIG_ARMV7_SECURE_BASE (SUNXI_SRAM_A2_BASE + 16 * 1024)
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+#define CONFIG_ARMV7_SECURE_MAX_SIZE (SUNXI_SRAM_A2_SIZE - 33 * 1024)
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+#endif
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+
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/*
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* Include common sunxi configuration where most the settings are
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*/
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