jeans/LibreELEC.tv
jeans/LibreELEC.tv
1
0
Fork 0
mirror of https://github.com/LibreELEC/LibreELEC.tv.git synced 2025-07-24 11:16:51 +00:00
Code Issues Packages Projects Releases Wiki Activity

linux (NXP iMX8): add mendel coral patches

Browse Source
This commit is contained in:
Rudi Heitbaum 2024-10-01 12:12:52 +00:00
parent 71f92e255f
commit 804aba00da
4 changed files with 374 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

226
projects/NXP/devices/iMX8/patches/linux/0011-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch Normal file
View File

@ -0,0 +1,226 @@
From 2806bcdfbe52eeba6d09d3a952e270bdba4b8f19 Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Tue, 7 Mar 2023 21:02:46 -0800
Subject: [PATCH] imx8mq-phanbell.dts: Enable Coral specifics e.g. PCIE
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
.../boot/dts/freescale/imx8mq-phanbell.dts | 155 +++++++++++++++++-
1 file changed, 154 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index a3b9d615a3b4..5ce4fc21443e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -21,6 +21,10 @@ memory@40000000 {
reg = <0x00000000 0x40000000 0 0x40000000>;
};
+ busfreq {
+ status = "disabled";
+ };
+
pmic_osc: clock-pmic {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -46,6 +50,12 @@ fan: gpio-fan {
pinctrl-0 = <&pinctrl_gpio_fan>;
status = "okay";
};
+
+ pcie1_refclk: pcie1-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
};
&A53_0 {
@@ -111,6 +121,17 @@ map4 {
};
};
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+
+ wl-reg-on {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -126,7 +147,7 @@ pmic: pmic@4b {
clocks = <&pmic_osc>;
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
regulators {
buck1: BUCK1 {
@@ -259,6 +280,70 @@ ldo7: LDO7 {
};
};
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio3 10 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ fsl,max-link-speed = <1>;
+ ext_osc = <0>;
+ hard-wired = <1>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie1>;
+ reset-gpio = <&gpio3 18 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&pcie1_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ ext_osc = <1>;
+ hard-wired = <1>;
+ status = "okay";
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>,
+ <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ num-cs = <2>;
+ status = "okay";
+
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+ };
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -333,6 +418,54 @@ &wdog1 {
};
&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x05
+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
+ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x19
+ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
+ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19
+ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19
+ MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x19
+ MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
+ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1_cs_grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x82
+ MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x82
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
@@ -366,6 +499,20 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
+ >;
+ };
+
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
@@ -478,4 +625,10 @@ pinctrl_wdog: wdoggrp {
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
+
+ pinctrl_wifi_reset: wifiresetgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
+ >;
+ };
};
--
2.39.2

33
projects/NXP/devices/iMX8/patches/linux/0012-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch Normal file
View File

@ -0,0 +1,33 @@
From aef5837a50af6adc53de4f907647cfd949912dba Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Tue, 7 Mar 2023 21:13:29 -0800
Subject: [PATCH 2/4] MLK-15307-2 clk: imx8mq: set the parent clocks of PCIE
Configure the parent clocks of PCIE.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
drivers/clk/imx/clk-imx8mq.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index bf3100eb59ca..3a5ff7109ff1 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -646,6 +646,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
/* enable all the clocks just for bringup */
imx_clk_init_on(np, hws);
+ /* set pcie root's parent clk source */
+ clk_set_parent(hws[IMX8MQ_CLK_PCIE1_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk);
+ clk_set_parent(hws[IMX8MQ_CLK_PCIE1_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk);
+ clk_set_parent(hws[IMX8MQ_CLK_PCIE2_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk);
+ clk_set_parent(hws[IMX8MQ_CLK_PCIE2_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk);
+
clk_set_parent(hws[IMX8MQ_CLK_CSI1_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk);
clk_set_parent(hws[IMX8MQ_CLK_CSI1_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk);
clk_set_parent(hws[IMX8MQ_CLK_CSI1_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk);
--
2.39.2

44
projects/NXP/devices/iMX8/patches/linux/0013-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch Normal file
View File

@ -0,0 +1,44 @@
From dd3d8c2c0b77eb742b288cf83e4849f87c8db5c6 Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Tue, 7 Mar 2023 21:19:36 -0800
Subject: [PATCH 3/4] PCI: imx: Use the external clock as REF_CLK when needed
for i.MX8MQ
Do not use the external clock when the internal PLL is used as PCIe
REF_CLK.
Signed-off-by: Ryosuke Saito <rsaito@redhat.com>
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 3a8350cad812..841af6f55c7d 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1569,14 +1569,13 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
break;
case IMX8MQ:
case IMX8MQ_EP:
- /*
- * TODO: Currently this code assumes external
- * oscillator is being used
- */
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
- imx6_pcie_grp_offset(imx6_pcie),
- IMX8MQ_GPR_PCIE_REF_USE_PAD,
- IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ if (imx6_pcie->ext_osc) {
+ /* Use the external oscillator as REF clock */
+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ imx6_pcie_grp_offset(imx6_pcie),
+ IMX8MQ_GPR_PCIE_REF_USE_PAD,
+ IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ }
/*
* Regarding the datasheet, the PCIE_VPH is suggested
* to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
--
2.39.2

71
projects/NXP/devices/iMX8/patches/linux/0014-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch Normal file
View File

@ -0,0 +1,71 @@
From 0845d9b5935ad8b3d450c2dfa62631c9c1df1bea Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Tue, 7 Mar 2023 21:21:57 -0800
Subject: [PATCH 4/4] PCI: imx: Provide a clock to the device for i.MX8MQ
When the internal PLL is configured as PCIe REF_CLK, we also have to
output a clock via CLK2_P/N pin to the connector/device to provide it.
Configure 100 MHz clock as its output.
Signed-off-by: Ryosuke Saito <rsaito@redhat.com>
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 841af6f55c7d..ac36c7035460 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -275,6 +275,12 @@ struct imx6_pcie {
#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
+#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG 0x74
+#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK GENMASK(3, 0)
+#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE BIT(4)
+#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG 0x7C
+#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK GENMASK(2, 0)
+
static int imx6_pcie_cz_enabled;
static void imx6_pcie_ltssm_disable(struct device *dev);
@@ -1575,6 +1581,35 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
imx6_pcie_grp_offset(imx6_pcie),
IMX8MQ_GPR_PCIE_REF_USE_PAD,
IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ } else {
+ /*
+ * Use the internal PLL as REF clock and also
+ * provide a clock to the device.
+ */
+ struct regmap *anatop =
+ syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop");
+
+ if (IS_ERR(anatop)) {
+ dev_err(imx6_pcie->pci->dev,
+ "Couldn't configure the internal PLL as REF clock\n");
+ break;
+ }
+
+ /* Select SYSTEM_PLL1_CLK as the clock source */
+ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG,
+ IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb);
+
+ /*
+ * SYSTEM_PLL1_CLK is 800 MHz, so divided by 8
+ * for generating 100 MHz as output.
+ */
+ regmap_update_bits(anatop, IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG,
+ IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK, 0x7);
+
+ /* Enable CLK2_P/N clock to provide it to the device */
+ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG,
+ IMX8MQ_ANA_PLLOUT_MONITOR_CKE,
+ IMX8MQ_ANA_PLLOUT_MONITOR_CKE);
}
/*
* Regarding the datasheet, the PCIE_VPH is suggested
--
2.39.2