diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch deleted file mode 100644 index aed2c1b577..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch +++ /dev/null @@ -1,5847 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Thu, 21 Jul 2022 10:33:00 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add analog audio output on quartz64-b - -This adds the necessary device tree changes to enable analog -audio output on the PINE64 Quartz64 Model B with its RK809 -codec. - -The headphone detection pin is left out for now because I couldn't -get it to work and am not sure if it even matters, but for future -reference: It's pin GPIO4 RK_PC4, named HP_DET_L_GPIO4_C4 in the -schematic. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20220721083301.3711-1-frattaroli.nicolas@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3566-quartz64-b.dts | 32 ++++++++++++++++++- - 1 file changed, 31 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -index 528bb4e8ac77..c8315d703ad0 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -@@ -42,6 +42,21 @@ led-user { - }; - }; - -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "Analog RK809"; -+ simple-audio-card,mclk-fs = <256>; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1_8ch>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&rk809>; -+ }; -+ }; -+ - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; -@@ -177,11 +192,16 @@ rk809: pmic@20 { - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - pinctrl-names = "default"; -- pinctrl-0 = <&pmic_int>; -+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; - rockchip,system-power-controller; -+ #sound-dai-cells = <0>; - wakeup-source; - #clock-cells = <1>; - -@@ -420,6 +440,16 @@ &i2c5 { - status = "disabled"; - }; - -+&i2s1_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_sclktx -+ &i2s1m0_lrcktx -+ &i2s1m0_sdi0 -+ &i2s1m0_sdo0>; -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ - &mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Tue, 12 Jul 2022 15:32:02 +0200 -Subject: [PATCH] arm64: dts: rockchip: add vcc_cam regulator to rock-3a - -The Radxa ROCK3 Model A features a voltage regulator that provides -a 3V3 supply to the MIPI CSI connector. Add this regulator to the -device tree of the board. - -Signed-off-by: Michael Riesch -Link: https://lore.kernel.org/r/20220712133204.2524942-1-michael.riesch@wolfvision.net -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-rock-3a.dts | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index b2e040dffb59..169d4b1d0a34 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -131,6 +131,22 @@ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; -+ -+ vcc_cam: vcc-cam { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_cam_en>; -+ regulator-name = "vcc_cam"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; - }; - - &combphy0 { -@@ -462,6 +478,12 @@ rgmii_phy1: ethernet-phy@0 { - }; - - &pinctrl { -+ cam { -+ vcc_cam_en: vcc_cam_en { -+ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Tue, 12 Jul 2022 15:32:03 +0200 -Subject: [PATCH] arm64: dts: rockchip: add vcc_mipi regulator to rock-3a - -The Radxa ROCK3 Model A features a voltage regulator that provides -a 3V3 supply to the MIPI DSI connector. Add this regulator to the -device tree of the board. - -Signed-off-by: Michael Riesch -Link: https://lore.kernel.org/r/20220712133204.2524942-2-michael.riesch@wolfvision.net -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-rock-3a.dts | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 169d4b1d0a34..f0f96c72ec51 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -147,6 +147,22 @@ regulator-state-mem { - regulator-off-in-suspend; - }; - }; -+ -+ vcc_mipi: vcc-mipi { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_mipi_en>; -+ regulator-name = "vcc_mipi"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; - }; - - &combphy0 { -@@ -484,6 +500,12 @@ vcc_cam_en: vcc_cam_en { - }; - }; - -+ display { -+ vcc_mipi_en: vcc_mipi_en { -+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Tue, 12 Jul 2022 15:32:04 +0200 -Subject: [PATCH] arm64: dts: rockchip: specify pinctrl for i2c adapters on - rock-3a - -On the Radxa ROCK3 Model A the I2C adapters related to the MIPI DSI -connector and the M.2/NGFF connector use the non-default pins. -Specify the correct pinctrl but leave the adapters disabled (as -they are supposed to be activated by overlays that describe the -external hardware). - -Signed-off-by: Michael Riesch -Link: https://lore.kernel.org/r/20220712133204.2524942-3-michael.riesch@wolfvision.net -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index f0f96c72ec51..52a437f48301 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -472,6 +472,18 @@ codec { - }; - }; - -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3m1_xfer>; -+ status = "disabled"; -+}; -+ -+&i2c4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c4m1_xfer>; -+ status = "disabled"; -+}; -+ - &i2s0_8ch { - status = "okay"; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Thu, 25 Aug 2022 21:38:35 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to rk3568 - -Add nodes to rk356x devicetree to support PCIe v3. - -Signed-off-by: Peter Geis -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220825193836.54262-5-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ - 1 file changed, 122 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -index 2bdf8c7e9765..ba67b58f05b7 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { - reg = <0x0 0xfe190200 0x0 0x20>; - }; - -+ pcie30_phy_grf: syscon@fdcb8000 { -+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; -+ reg = <0x0 0xfdcb8000 0x0 0x10000>; -+ }; -+ -+ pcie30phy: phy@fe8c0000 { -+ compatible = "rockchip,rk3568-pcie3-phy"; -+ reg = <0x0 0xfe8c0000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, -+ <&cru PCLK_PCIE30PHY>; -+ clock-names = "refclk_m", "refclk_n", "pclk"; -+ resets = <&cru SRST_PCIE30PHY>; -+ reset-names = "phy"; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ status = "disabled"; -+ }; -+ -+ pcie3x1: pcie@fe270000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, -+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, -+ <&cru CLK_PCIE30X1_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, -+ <0 0 0 2 &pcie3x1_intc 1>, -+ <0 0 0 3 &pcie3x1_intc 2>, -+ <0 0 0 4 &pcie3x1_intc 3>; -+ linux,pci-domain = <1>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x1000 0x1000>; -+ num-lanes = <1>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0400000 0x0 0x00400000>, -+ <0x0 0xfe270000 0x0 0x00010000>, -+ <0x3 0x7f000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X1_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane1 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x1_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie3x2: pcie@fe280000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, -+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, -+ <&cru CLK_PCIE30X2_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -+ <0 0 0 2 &pcie3x2_intc 1>, -+ <0 0 0 3 &pcie3x2_intc 2>, -+ <0 0 0 4 &pcie3x2_intc 3>; -+ linux,pci-domain = <2>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x2000 0x1000>; -+ num-lanes = <2>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0800000 0x0 0x00400000>, -+ <0x0 0xfe280000 0x0 0x00010000>, -+ <0x3 0xbf000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X2_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane0 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Thu, 25 Aug 2022 21:38:36 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro - -Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and -set PCIe related regulators to always on. - -Suggested-by: Peter Geis -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220825193836.54262-6-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 117 ++++++++++++++++++ - 1 file changed, 117 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index 93d383b8be87..bc34061a421e 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -86,6 +86,66 @@ vcc5v0_sys: vcc5v0-sys { - vin-supply = <&dc_12v>; - }; - -+ pcie30_avdd0v9: pcie30-avdd0v9-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ pcie30_avdd1v8: pcie30-avdd1v8-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ /* pi6c pcie clock generator feeds both ports */ -+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <200000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ -+ vcc3v3_minipcie: vcc3v3-minipcie-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_minipcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&minipcie_enable_h>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc3v3_pi6c_05>; -+ }; -+ -+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ -+ vcc3v3_ngff: vcc3v3-ngff-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_ngff"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ngffpcie_enable_h>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc3v3_pi6c_05>; -+ }; -+ - vcc5v0_usb: vcc5v0_usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; -@@ -513,6 +573,32 @@ rgmii_phy1: ethernet-phy@0 { - }; - }; - -+&pcie30phy { -+ data-lanes = <1 2>; -+ phy-supply = <&vcc3v3_pi6c_05>; -+ status = "okay"; -+}; -+ -+&pcie3x1 { -+ /* M.2 slot */ -+ num-lanes = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ngffpcie_reset_h>; -+ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_ngff>; -+ status = "okay"; -+}; -+ -+&pcie3x2 { -+ /* mPCIe slot */ -+ num-lanes = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&minipcie_reset_h>; -+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_minipcie>; -+ status = "okay"; -+}; -+ - &pinctrl { - leds { - blue_led_pin: blue-led-pin { -@@ -529,6 +615,24 @@ hym8563_int: hym8563-int { - }; - }; - -+ pcie { -+ minipcie_enable_h: minipcie-enable-h { -+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; -+ }; -+ -+ ngffpcie_enable_h: ngffpcie-enable-h { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; -+ }; -+ -+ minipcie_reset_h: minipcie-reset-h { -+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; -+ }; -+ -+ ngffpcie_reset_h: ngffpcie-reset-h { -+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; -+ }; -+ }; -+ - pmic { - pmic_int: pmic_int { - rockchip,pins = -@@ -708,6 +812,19 @@ &usb2phy0_otg { - status = "okay"; - }; - -+&usb2phy1 { -+ /* USB for PCIe/M2 */ -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ status = "okay"; -+}; -+ - &vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Michael Riesch -Date: Wed, 20 Jul 2022 11:15:27 +0200 -Subject: [PATCH] arm64: dts: rockchip: add csi dphy node to rk356x - -Add the MIPI CSI DPHY node to the RK356x device tree. - -Signed-off-by: Michael Riesch -Link: https://lore.kernel.org/r/20220720091527.1270365-4-michael.riesch@wolfvision.net -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 319981c3e9f7..c66b60302803 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -1594,6 +1594,18 @@ combphy2: phy@fe840000 { - status = "disabled"; - }; - -+ csi_dphy: phy@fe870000 { -+ compatible = "rockchip,rk3568-csi-dphy"; -+ reg = <0x0 0xfe870000 0x0 0x10000>; -+ clocks = <&cru PCLK_MIPICSIPHY>; -+ clock-names = "pclk"; -+ #phy-cells = <0>; -+ resets = <&cru SRST_P_MIPICSIPHY>; -+ reset-names = "apb"; -+ rockchip,grf = <&grf>; -+ status = "disabled"; -+ }; -+ - usb2phy0: usb2phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Sat, 9 Jul 2022 18:29:42 +0800 -Subject: [PATCH] dt-bindings: vendor-prefixes: Add OPEN AI LAB - -Add vendor prefixes for OPEN AI LAB. - -Signed-off-by: Andy Yan -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20220709102942.2753939-1-andyshrk@163.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 2f0151e9f6be..dfaff2487b04 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -925,6 +925,8 @@ patternProperties: - description: On Tat Industrial Company - "^opalkelly,.*": - description: Opal Kelly Incorporated -+ "^openailab,.*": -+ description: openailab.com - "^opencores,.*": - description: OpenCores.org - "^openembed,.*": - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Sat, 9 Jul 2022 18:30:01 +0800 -Subject: [PATCH] dt-bindings: arm: rockchip: Add EAIDK-610 - -EAIDK-610 is a rk3399 based board from OPEN AI LAB -and popularly used by university students. - -Specification: -- Rockchip RK3399 -- LPDDR3 4GB -- TF sd scard slot -- eMMC -- AP6255 for WiFi + BT -- Gigabit ethernet -- HDMI out -- 40 pin header -- USB 2.0 x 2 -- USB 3.0 x 1 -- USB 3.0 Type-C x 1 -- 12V DC Power supply - -Signed-off-by: Andy Yan -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20220709103001.2753992-1-andyshrk@163.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 7811ba64149c..adc06522d219 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -470,6 +470,11 @@ properties: - - const: netxeon,r89 - - const: rockchip,rk3288 - -+ - description: OPEN AI LAB EAIDK-610 -+ items: -+ - const: openailab,eaidk-610 -+ - const: rockchip,rk3399 -+ - - description: Orange Pi RK3399 board - items: - - const: rockchip,rk3399-orangepi - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Sat, 9 Jul 2022 18:30:16 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add dts for a rk3399 based board - EAIDK-610 - -EAIDK-610 is from OPEN AI LAB and popularly used by university -students. - -Specification: -- Rockchip RK3399 -- LPDDR3 4GB -- TF sd scard slot -- eMMC -- AP6255 for WiFi + BT -- Gigabit ethernet -- HDMI out -- 40 pin header -- USB 2.0 x 2 -- USB 3.0 x 1 -- USB 3.0 Type-C x 1 -- 12V DC Power supply - -This patch is test on Armbain and Glodroid with -HDMI/GPU/USB HOST/Type-C ADB/WIFI/BT. - -Signed-off-by: Andy Yan -Link: https://lore.kernel.org/r/20220709103016.2754044-1-andyshrk@163.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3399-eaidk-610.dts | 939 ++++++++++++++++++ - 2 files changed, 940 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index ef79a672804a..4ed7d483c864 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-eaidk-610.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts b/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts -new file mode 100644 -index 000000000000..d1f343345f67 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts -@@ -0,0 +1,939 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd. -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "OPEN AI LAB EAIDK-610"; -+ compatible = "openailab,eaidk-610", "rockchip,rk3399"; -+ -+ aliases { -+ mmc0 = &sdio0; -+ mmc1 = &sdmmc; -+ mmc2 = &sdhci; -+ }; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm0 0 25000 0>; -+ brightness-levels = < -+ 0 1 2 3 4 5 6 7 -+ 8 9 10 11 12 13 14 15 -+ 16 17 18 19 20 21 22 23 -+ 24 25 26 27 28 29 30 31 -+ 32 33 34 35 36 37 38 39 -+ 40 41 42 43 44 45 46 47 -+ 48 49 50 51 52 53 54 55 -+ 56 57 58 59 60 61 62 63 -+ 64 65 66 67 68 69 70 71 -+ 72 73 74 75 76 77 78 79 -+ 80 81 82 83 84 85 86 87 -+ 88 89 90 91 92 93 94 95 -+ 96 97 98 99 100 101 102 103 -+ 104 105 106 107 108 109 110 111 -+ 112 113 114 115 116 117 118 119 -+ 120 121 122 123 124 125 126 127 -+ 128 129 130 131 132 133 134 135 -+ 136 137 138 139 140 141 142 143 -+ 144 145 146 147 148 149 150 151 -+ 152 153 154 155 156 157 158 159 -+ 160 161 162 163 164 165 166 167 -+ 168 169 170 171 172 173 174 175 -+ 176 177 178 179 180 181 182 183 -+ 184 185 186 187 188 189 190 191 -+ 192 193 194 195 196 197 198 199 -+ 200 201 202 203 204 205 206 207 -+ 208 209 210 211 212 213 214 215 -+ 216 217 218 219 220 221 222 223 -+ 224 225 226 227 228 229 230 231 -+ 232 233 234 235 236 237 238 239 -+ 240 241 242 243 244 245 246 247 -+ 248 249 250 251 252 253 254 255>; -+ default-brightness-level = <200>; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ dc_12v: dc-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "dc_12v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwrbtn>; -+ -+ key-power { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "GPIO Key Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&work_led_pin>, <&user_led_pin>, -+ <&heartbeat_led_pin>, <&wlan_active_led_pin>, -+ <&bt_active_led_pin>; -+ -+ work_led: led-0 { -+ label = "blue:work"; -+ default-state = "on"; -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ user_led: led-1 { -+ label = "read:user"; -+ default-state = "off"; -+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ heartbeat_led: led-2 { -+ label = "green:heartbeat"; -+ linux,default-trigger = "heartbeat"; -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wlan_active_led: led-3 { -+ label = "yellow:wlan"; -+ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "phy0tx"; -+ default-state = "off"; -+ }; -+ -+ bt_active_led: led-4 { -+ label = "blue:bt"; -+ gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "hci0-power"; -+ default-state = "off"; -+ }; -+ }; -+ -+ rt5651-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "realtek,rt5651-codec"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,widgets = -+ "Microphone", "Mic Jack", -+ "Headphone", "Headphone Jack"; -+ simple-audio-card,routing = -+ "Mic Jack", "MICBIAS1", -+ "IN1P", "Mic Jack", -+ "Headphone Jack", "HPOL", -+ "Headphone Jack", "HPOR"; -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&rt5651>; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ -+ /* -+ * On the module itself this is one of these (depending -+ * on the actual card populated): -+ * - SDIO_RESET_L_WL_REG_ON -+ * - PDN (power down when low) -+ */ -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ /* switched by pmic_sleep */ -+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc_1v8>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ /* For USB3.0 Port1/2 */ -+ vcc5v0_host1: vcc5v0-host1-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host1_en>; -+ regulator-name = "vcc5v0_host1"; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ /* For USB2.0 Port1/2 */ -+ vcc5v0_host3: vcc5v0-host3-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host3_en>; -+ regulator-name = "vcc5v0_host3"; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_typec: vcc5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_typec_en>; -+ regulator-name = "vcc5v0_typec"; -+ regulator-always-on; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ }; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ assigned-clock-parents = <&clkin_gmac>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc_lan>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ vcc10-supply = <&vcc3v3_sys>; -+ vcc11-supply = <&vcc3v3_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG1 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc2v8_dvp: LDO_REG2 { -+ regulator-name = "vcc2v8_dvp"; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_pmu: LDO_REG3 { -+ regulator-name = "vcc1v8_pmu"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-name = "vcc_sdio"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-name = "vcca3v0_codec"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-name = "vcca1v8_codec"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-name = "vcc_3v0"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: vcc_lan: SWITCH_REG1 { -+ regulator-name = "vcc3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-name = "vcc3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_b"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_pin>; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_gpu"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_pin>; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ i2c-scl-rising-time-ns = <300>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+ -+ rt5651: audio-codec@1a { -+ compatible = "rockchip,rt5651"; -+ reg = <0x1a>; -+ clocks = <&cru SCLK_I2S_8CH_OUT>; -+ clock-names = "mclk"; -+ hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; -+ spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ #sound-dai-cells = <0>; -+ }; -+ -+}; -+ -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+&i2c4 { -+ i2c-scl-rising-time-ns = <600>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ vbus-supply = <&vcc5v0_typec>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_role_sw: endpoint@0 { -+ remote-endpoint = <&dwc3_0_role_switch>; -+ }; -+ }; -+ }; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ data-role = "dual"; -+ label = "USB-C"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usbc_hs: endpoint { -+ remote-endpoint = <&u2phy0_typec_hs>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usbc_ss: endpoint { -+ remote-endpoint = <&tcphy0_typec_ss>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2s1 { -+ rockchip,playback-channels = <2>; -+ rockchip,capture-channels = <2>; -+ status = "okay"; -+}; -+ -+&i2s2 { -+ status = "okay"; -+}; -+ -+&io_domains { -+ status = "okay"; -+ -+ audio-supply = <&vcca1v8_codec>; -+ bt656-supply = <&vcc_3v0>; -+ gpio1830-supply = <&vcc_3v0>; -+ sdmmc-supply = <&vcc_sdio>; -+}; -+ -+&pmu_io_domains { -+ status = "okay"; -+ -+ pmu1830-supply = <&vcc_3v0>; -+}; -+ -+&pinctrl { -+ buttons { -+ pwrbtn: pwrbtn { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fusb302x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ lcd-panel { -+ lcd_panel_reset: lcd-panel-reset { -+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ leds { -+ work_led_pin: work-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ user_led_pin: user-led-pin { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ heartbeat_led_pin: heartbeat-led-pin { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wlan_active_led_pin: wlan-led-pin { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_active_led_pin: bt-led-pin { -+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_pin: vsel1-pin { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_pin: vsel2-pin { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ rt5651 { -+ rt5651_hpcon: rt5640-hpcon { -+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb-typec { -+ vcc5v0_typec_en: vcc5v0_typec_en { -+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb2 { -+ vcc5v0_host3_en: vcc5v0-host3-en { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_host1_en: vcc5v0-host1-en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ wifi { -+ wifi_host_wake_l: wifi-host-wake-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdio0 { -+ /* WiFi & BT combo module AMPAK AP6255 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ bus-width = <4>; -+ clock-frequency = <50000000>; -+ cap-sdio-irq; -+ cap-sd-highspeed; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ compatible = "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_host_wake_l>; -+ }; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ max-frequency = <150000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy0_usb3 { -+ orientation-switch; -+ port { -+ tcphy0_typec_ss: endpoint { -+ remote-endpoint = <&usbc_ss>; -+ }; -+ }; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ -+ u2phy0_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy0_host: host-port { -+ phy-supply = <&vcc5v0_host3>; -+ status = "okay"; -+ }; -+ -+ port { -+ u2phy0_typec_hs: endpoint { -+ remote-endpoint = <&usbc_hs>; -+ }; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+ -+ u2phy1_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy1_host: host-port { -+ phy-supply = <&vcc5v0_host3>; -+ status = "okay"; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rk808 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ max-speed = <1500000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_1v8>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+ usb-role-switch; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dwc3_0_role_switch: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_role_sw>; -+ }; -+ }; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Tom Fitzhenry -Date: Mon, 15 Aug 2022 22:30:03 +1000 -Subject: [PATCH] dt-bindings: arm: rockchip: Add PinePhone Pro bindings - -Document board compatible names for Pine64 PinePhonePro. - -https://wiki.pine64.org/wiki/PinePhone_Pro - -Signed-off-by: Tom Fitzhenry -Reviewed-by: Caleb Connolly -Acked-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220815123004.252014-2-tom@tom-fitzhenry.me.uk -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index adc06522d219..7295eecc6de7 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -499,6 +499,11 @@ properties: - - const: pine64,pinenote - - const: rockchip,rk3566 - -+ - description: Pine64 PinePhonePro -+ items: -+ - const: pine64,pinephone-pro -+ - const: rockchip,rk3399 -+ - - description: Pine64 Rock64 - items: - - const: pine64,rock64 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Martijn Braam -Date: Mon, 29 Aug 2022 15:00:40 +1000 -Subject: [PATCH] arm64: dts: rockchip: Add initial support for Pine64 - PinePhone Pro -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This is a basic DT containing regulators and UART, intended to be a -base that myself and others can add additional nodes in future patches. - -Tested to work: booting from eMMC/SD, output over UART. - -https://wiki.pine64.org/wiki/PinePhone_Pro - -This is derived from the community pine64-org repo[0] with fixes from -https://megous.com/git/linux. - -0. https://gitlab.com/pine64-org/linux/-/commit/261d3b5f8ac503f97da810986d1d6422430c8531 - -Signed-off-by: Martijn Braam -Co-developed-by: Kamil Trzciński -[no SoB, but Kamil is happy for this patch to be submitted] -Co-developed-by: Ondrej Jirman -Signed-off-by: Ondrej Jirman -Co-developed-by: Tom Fitzhenry -Signed-off-by: Tom Fitzhenry -Reviewed-by: Caleb Connolly -Reviewed-by: Nícolas F. R. A. Prado -Tested-by: Nícolas F. R. A. Prado -Link: https://lore.kernel.org/r/20220829050040.17330-2-tom@tom-fitzhenry.me.uk -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3399-pinephone-pro.dts | 398 ++++++++++++++++++ - 2 files changed, 399 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 4ed7d483c864..236e8ae52c70 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts -new file mode 100644 -index 000000000000..f00c80361377 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts -@@ -0,0 +1,398 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Martijn Braam -+ * Copyright (c) 2021 Kamil Trzciński -+ */ -+ -+/* -+ * PinePhone Pro datasheet: -+ * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf -+ */ -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Pine64 PinePhonePro"; -+ compatible = "pine64,pinephone-pro", "rockchip,rk3399"; -+ chassis-type = "handset"; -+ -+ aliases { -+ mmc0 = &sdio0; -+ mmc1 = &sdmmc; -+ mmc2 = &sdhci; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwrbtn_pin>; -+ -+ key-power { -+ debounce-interval = <20>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ vcc_sys: vcc-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcca1v8_s3: vcc1v8-s3-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca1v8_s3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vcc1v8_codec: vcc1v8-codec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc1v8_codec_en>; -+ regulator-name = "vcc1v8_codec"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk818: pmic@1c { -+ compatible = "rockchip,rk818"; -+ reg = <0x1c>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ -+ regulators { -+ vdd_cpu_l: DCDC_REG1 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <875000>; -+ regulator-max-microvolt = <975000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_center: DCDC_REG2 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG1 { -+ regulator-name = "vcca3v0_codec"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ }; -+ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-name = "vcc3v0_touch"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ }; -+ -+ vcca1v8_codec: LDO_REG3 { -+ regulator-name = "vcca1v8_codec"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ rk818_pwr_on: LDO_REG4 { -+ regulator-name = "rk818_pwr_on"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG5 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG7 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ vcc3v3_s3: LDO_REG8 { -+ regulator-name = "vcc3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG9 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1710000>; -+ regulator-max-microvolt = <3150000>; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG { -+ regulator-name = "vcc3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_pin>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <875000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_pin>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <875000>; -+ regulator-max-microvolt = <975000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&cluster0_opp { -+ opp04 { -+ status = "disabled"; -+ }; -+ -+ opp05 { -+ status = "disabled"; -+ }; -+}; -+ -+&cluster1_opp { -+ opp06 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <1100000 1100000 1150000>; -+ }; -+ -+ opp07 { -+ status = "disabled"; -+ }; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc1v8_dvp>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vccio_sd>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ buttons { -+ pwrbtn_pin: pwrbtn-pin { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_pin: vsel1-pin { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_pin: vsel2-pin { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ sound { -+ vcc1v8_codec_en: vcc1v8-codec-en { -+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ max-frequency = <150000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v3_sys>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 2 Sep 2022 12:20:55 +0530 -Subject: [PATCH] dt-bindings: arm: rockchip: Document Radxa ROCK 4C+ -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Document the dt-bindings for Radxa ROCK 4C+ SBC. - -Key differences of 4C+ compared to previous ROCK Pi 4. -- Rockchip RK3399-T SoC -- DP from 4C replaced with micro HDMI 2K@60fps -- 4-lane MIPI DSI with 1920*1080 -- RK817 Audio codec - -Also, an official naming convention from Radxa mention to remove -Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not -Radxa ROCK Pi 4C+. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20220902065057.97425-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 7295eecc6de7..5c1b9f0e4cc1 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -547,6 +547,11 @@ properties: - - const: radxa,rockpi4 - - const: rockchip,rk3399 - -+ - description: Radxa ROCK 4C+ -+ items: -+ - const: radxa,rock-4c-plus -+ - const: rockchip,rk3399 -+ - - description: Radxa ROCK Pi E - items: - - const: radxa,rockpi-e - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 2 Sep 2022 12:20:56 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add RK3399-T OPP table - -RK3399-T is down-clocked version of RK3399 SoC operated at 1.5GHz. - -Add CPU operating points table for it. - -Signed-off-by: FUKAUMI Naoki -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20220902065057.97425-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/rk3399-t-opp.dtsi | 114 ++++++++++++++++++ - 1 file changed, 114 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi -new file mode 100644 -index 000000000000..1ababadda9df ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi -@@ -0,0 +1,114 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2022 Radxa Limited -+ */ -+ -+/ { -+ cluster0_opp: opp-table-0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <875000 875000 1250000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <875000 875000 1250000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <900000 900000 1250000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <975000 975000 1250000>; -+ }; -+ }; -+ -+ cluster1_opp: opp-table-1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <875000 875000 1250000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <875000 875000 1250000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <875000 875000 1250000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <925000 925000 1250000>; -+ }; -+ opp04 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1000000 1000000 1250000>; -+ }; -+ opp05 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <1075000 1075000 1250000>; -+ }; -+ opp06 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1150000 1150000 1250000>; -+ }; -+ }; -+ -+ gpu_opp_table: opp-table-2 { -+ compatible = "operating-points-v2"; -+ -+ opp00 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <875000 875000 1150000>; -+ }; -+ opp01 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <875000 875000 1150000>; -+ }; -+ opp02 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <875000 875000 1150000>; -+ }; -+ opp03 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <975000 975000 1150000>; -+ }; -+ }; -+}; -+ -+&cpu_l0 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l1 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l2 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_l3 { -+ operating-points-v2 = <&cluster0_opp>; -+}; -+ -+&cpu_b0 { -+ operating-points-v2 = <&cluster1_opp>; -+}; -+ -+&cpu_b1 { -+ operating-points-v2 = <&cluster1_opp>; -+}; -+ -+&gpu { -+ operating-points-v2 = <&gpu_opp_table>; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 2 Sep 2022 12:20:57 +0530 -Subject: [PATCH] arm64: dts: rockchip: rk3399: Radxa ROCK 4C+ -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add support for Radxa ROCK 4C+ SBC. - -Key differences of 4C+ compared to previous ROCK Pi 4. -- Rockchip RK3399-T SoC -- DP from 4C replaced with micro HDMI 2K@60fps -- 4-lane MIPI DSI with 1920*1080 -- RK817 Audio codec - -Also, an official naming convention from Radxa mention to remove -Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not -Radxa ROCK Pi 4C+. - -Signed-off-by: Stephen Chen -Signed-off-by: Manoj Sai -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20220902065057.97425-3-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 646 ++++++++++++++++++ - 2 files changed, 647 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 236e8ae52c70..cdd1f211496d 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -new file mode 100644 -index 000000000000..a1c4727acfcd ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -@@ -0,0 +1,646 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2019 Radxa Limited -+ * Copyright (c) 2022 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include "rk3399.dtsi" -+#include "rk3399-t-opp.dtsi" -+ -+/ { -+ model = "Radxa ROCK 4C+"; -+ compatible = "radxa,rock-4c-plus", "rockchip,rk3399"; -+ -+ aliases { -+ mmc0 = &sdmmc; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk809 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_host1: vcc5v0-host-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+ regulator-name = "vcc5v0_host1"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_host0_s0>; -+ }; -+ -+ vcc5v0_typec: vcc5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_typec0_en>; -+ regulator-name = "vcc5v0_typec"; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc_lan: vcc3v3-phy-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_lan"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ assigned-clock-parents = <&clkin_gmac>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc_lan>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x2a>; -+ rx_delay = <0x21>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_cec>; -+ status = "okay"; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ i2c-scl-falling-time-ns = <30>; -+ i2c-scl-rising-time-ns = <180>; -+ clock-frequency = <400000>; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ #clock-cells = <1>; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc_buck5>; -+ vcc6-supply = <&vcc_buck5>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vdd_log"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vdd_cpu_l"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc_ddr"; -+ regulator-initial-mode = <0x2>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sys: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vcc3v3_sys"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_buck5: DCDC_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_buck5"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_0v9: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vcca_0v9"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc0v9_soc: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vcc0v9_soc"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca_1v8"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_mipi: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_mipi"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc_1v5"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_3v0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vccio_sd"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_cam: LDO_REG9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_cam"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc5v0_host0_s0: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc5v0_host0_s0"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ lcd_3v3: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "lcd_3v3"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-compatible = "fan53555-reg"; -+ pinctrl-0 = <&vsel1_gpio>; -+ vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-compatible = "fan53555-reg"; -+ pinctrl-0 = <&vsel2_gpio>; -+ vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+&i2s2 { -+ status = "okay"; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc_3v0>; -+ gpio1830-supply = <&vcc_3v0>; -+ sdmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_gpio: vsel1-gpio { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_gpio: vsel2-gpio { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ sdmmc { -+ sdmmc_bus4: sdmmc-bus4 { -+ rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>, -+ <4 9 1 &pcfg_pull_up_8ma>, -+ <4 10 1 &pcfg_pull_up_8ma>, -+ <4 11 1 &pcfg_pull_up_8ma>; -+ }; -+ -+ sdmmc_clk: sdmmc-clk { -+ rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>; -+ }; -+ -+ sdmmc_cmd: sdmmc-cmd { -+ rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>; -+ }; -+ }; -+ -+ usb-typec { -+ vcc5v0_typec0_en: vcc5v0-typec-en { -+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb2 { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ wifi { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_host_wake_l: wifi-host-wake-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&saradc { -+ status = "okay"; -+ vref-supply = <&vcc_1v8>; -+}; -+ -+&sdhci { -+ max-frequency = <150000000>; -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ non-removable; -+ mmc-hs400-enhanced-strobe; -+ status = "okay"; -+}; -+ -+&sdio0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ bus-width = <4>; -+ clock-frequency = <50000000>; -+ cap-sdio-irq; -+ cap-sd-highspeed; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ compatible = "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_host_wake_l>; -+ }; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ card-detect-delay = <800>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ -+ u2phy0_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy0_host: host-port { -+ phy-supply = <&vcc5v0_host1>; -+ status = "okay"; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+ -+ u2phy1_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy1_host: host-port { -+ phy-supply = <&vcc5v0_host1>; -+ status = "okay"; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rk809 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ max-speed = <1500000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_1v8>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ extcon = <&u2phy0>; -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Mon, 5 Sep 2022 01:36:47 +0200 -Subject: [PATCH] arm64: dts: rockchip: Fix SD card controller probe on - Pinephone Pro - -Voltage constraints on vccio_sd are invalid. They don't match the voltages -that LDO9 can generate, and this causes rk808-regulator driver to fail -to probe with -EINVAL when it tries to apply the constraints during boot. - -Fix the constraints to something that LDO9 can be actually configured for. - -Fixes: 78a21c7d5952 ("arm64: dts: rockchip: Add initial support for Pine64 PinePhone Pro") -Signed-off-by: Ondrej Jirman -Reviewed-by: Caleb Connolly -Reviewed-by: Tom Fitzhenry -Tested-by: Tom Fitzhenry -Link: https://lore.kernel.org/r/20220904233652.3197885-1-megi@xff.cz -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts -index f00c80361377..2e058c315025 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts -@@ -253,8 +253,8 @@ regulator-state-mem { - - vccio_sd: LDO_REG9 { - regulator-name = "vccio_sd"; -- regulator-min-microvolt = <1710000>; -- regulator-max-microvolt = <3150000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; - }; - - vcc3v3_s0: SWITCH_REG { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Fri, 26 Aug 2022 21:16:23 -0500 -Subject: [PATCH] arm64: dts: rockchip: add rk817 chg to Odroid Go Advance - -Add the new rk817 charger driver to the Odroid Go Advance. Create a -monitored battery node as well for the charger to use. All values -from monitored battery are gathered from the BSP kernel for the -Odroid Go Advance provided by HardKernel. - -Signed-off-by: Chris Morgan -Signed-off-by: Maya Matuszczyk -Link: https://lore.kernel.org/r/20220827021623.23829-5-macroalpha82@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3326-odroid-go2.dts | 26 +++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -index 415aa9ff8bd4..72899a714310 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -@@ -52,6 +52,25 @@ backlight: backlight { - pwms = <&pwm1 0 25000 0>; - }; - -+ battery: battery { -+ compatible = "simple-battery"; -+ charge-full-design-microamp-hours = <3000000>; -+ charge-term-current-microamp = <300000>; -+ constant-charge-current-max-microamp = <2000000>; -+ constant-charge-voltage-max-microvolt = <4200000>; -+ factory-internal-resistance-micro-ohms = <180000>; -+ voltage-max-design-microvolt = <4100000>; -+ voltage-min-design-microvolt = <3500000>; -+ -+ ocv-capacity-celsius = <20>; -+ ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>, -+ <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>, -+ <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>, -+ <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>, -+ <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>, -+ <3574170 0>; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; -@@ -472,6 +491,13 @@ usb_midu: BOOST { - }; - }; - -+ rk817_charger: charger { -+ monitored-battery = <&battery>; -+ rockchip,resistor-sense-micro-ohms = <10000>; -+ rockchip,sleep-enter-current-microamp = <300000>; -+ rockchip,sleep-filter-current-microamp = <100000>; -+ }; -+ - rk817_codec: codec { - rockchip,mic-in-differential; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Thu, 8 Sep 2022 03:17:25 +0000 -Subject: [PATCH] arm64: dts: rockchip: add LED for ROCK Pi 4A/B/C/A+/B+ - -only user_led2 (blue) is supported. - -user_led1 (green) is not connected to any gpio so it cannot be -controlled. - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20220908031726.1307105-1-naoki@radxa.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 21 +++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 401e1ae9d944..6464a6729729 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -6,6 +6,7 @@ - - /dts-v1/; - #include -+#include - #include - #include "rk3399.dtsi" - #include "rk3399-opp.dtsi" -@@ -27,6 +28,20 @@ clkin_gmac: external-gmac-clock { - #clock-cells = <0>; - }; - -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&user_led2>; -+ -+ /* USER_LED2 */ -+ led-0 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; -@@ -553,6 +568,12 @@ hp_int: hp-int { - }; - }; - -+ leds { -+ user_led2: user-led2 { -+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pcie { - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: FUKAUMI Naoki -Date: Thu, 8 Sep 2022 03:17:26 +0000 -Subject: [PATCH] arm64: dts: rockchip: add LEDs for ROCK 4C+ - -add support for user LEDs on Radxa ROCK 4C+ board. - -Signed-off-by: FUKAUMI Naoki -Link: https://lore.kernel.org/r/20220908031726.1307105-2-naoki@radxa.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 33 +++++++++++++++++++ - 1 file changed, 33 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -index a1c4727acfcd..3f01772c66ad 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts -@@ -6,6 +6,7 @@ - */ - - /dts-v1/; -+#include - #include "rk3399.dtsi" - #include "rk3399-t-opp.dtsi" - -@@ -38,6 +39,28 @@ clkin_gmac: external-gmac-clock { - #clock-cells = <0>; - }; - -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&user_led1 &user_led2>; -+ -+ /* USER_LED1 */ -+ led-0 { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ /* USER_LED2 */ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; -@@ -424,6 +447,16 @@ bt_wake_l: bt-wake-l { - }; - }; - -+ leds { -+ user_led1: user-led1 { -+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ user_led2: user-led2 { -+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Tue, 6 Sep 2022 18:42:12 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add regulator suffix to BPI-R2-Pro - -Add -regulator suffix to regulator names on Banana Pi R2 Pro board as -discussed on Mailinglist - -Signed-off-by: Frank Wunderlich -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220906164212.84835-1-linux@fw-web.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index bc34061a421e..c282f6e79960 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -46,7 +46,7 @@ green_led: led-1 { - }; - }; - -- dc_12v: dc-12v { -+ dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; -@@ -66,7 +66,7 @@ hdmi_con_in: endpoint { - }; - }; - -- vcc3v3_sys: vcc3v3-sys { -+ vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; -@@ -76,7 +76,7 @@ vcc3v3_sys: vcc3v3-sys { - vin-supply = <&dc_12v>; - }; - -- vcc5v0_sys: vcc5v0-sys { -+ vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; -@@ -146,7 +146,7 @@ vcc3v3_ngff: vcc3v3-ngff-regulator { - vin-supply = <&vcc3v3_pi6c_05>; - }; - -- vcc5v0_usb: vcc5v0_usb { -+ vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; -@@ -156,7 +156,7 @@ vcc5v0_usb: vcc5v0_usb { - vin-supply = <&dc_12v>; - }; - -- vcc5v0_usb_host: vcc5v0-usb-host { -+ vcc5v0_usb_host: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -@@ -168,7 +168,7 @@ vcc5v0_usb_host: vcc5v0-usb-host { - vin-supply = <&vcc5v0_usb>; - }; - -- vcc5v0_usb_otg: vcc5v0-usb-otg { -+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Tue, 6 Sep 2022 16:03:22 -0500 -Subject: [PATCH] dt-bindings: vendor-prefixes: add Anbernic - -Anbernic designs and manufactures portable gaming systems. -https://anbernic.com/ - -Signed-off-by: Chris Morgan -Acked-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220906210324.28986-2-macroalpha82@gmail.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index dfaff2487b04..e370ffde0692 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -105,6 +105,8 @@ patternProperties: - description: AMS-Taos Inc. - "^analogix,.*": - description: Analogix Semiconductor, Inc. -+ "^anbernic,.*": -+ description: Anbernic - "^andestech,.*": - description: Andes Technology Corporation - "^anvo,.*": - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Tue, 6 Sep 2022 16:03:23 -0500 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Anbernic RG353P and RG503 - -Add entry for the Anbernic RG353P and RG503 handheld devices. - -Signed-off-by: Chris Morgan -Acked-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220906210324.28986-3-macroalpha82@gmail.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 5c1b9f0e4cc1..ae7fe15a3b89 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -30,6 +30,16 @@ properties: - - const: amarula,vyasa-rk3288 - - const: rockchip,rk3288 - -+ - description: Anbernic RG353P -+ items: -+ - const: anbernic,rg353p -+ - const: rockchip,rk3566 -+ -+ - description: Anbernic RG503 -+ items: -+ - const: anbernic,rg503 -+ - const: rockchip,rk3566 -+ - - description: Asus Tinker board - items: - - const: asus,rk3288-tinker - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Tue, 6 Sep 2022 16:03:24 -0500 -Subject: [PATCH] arm64: dts: rockchip: add Anbernic RG353P and RG503 - -Anbernic RG353P and RG503 are both RK3566 based handheld gaming devices -from Anbernic. - -Both devices have: - - 2 SDMMC slots. - - A Realtek rtl8821cs WiFi/Bluetooth adapter. - - A mini HDMI port. - - A USB C host port and a USB C otg port (currently only working as - device). - - Multiple GPIO buttons and a single ADC button. - - Dual analog joysticks controlled via a GPIO mux. - - A headphone jack with amplified stereo speakers via a SGM4865 amp. - - A PWM based vibrator for force feedback. - -The RG353P has: - - 2GB LPDDR4 RAM. - - A 32GB eMMC. - - A 3.5 inch 640x480 4-lane DSI panel of unknown origin with an i2c - controlled touchscreen (touchscreen is a Hynitron CST340). - -The RG503 has: - - 1GB LPDDR4 RAM. - - A 5 inch 960x544 AMOLED 2-lane DSI/DBI panel manufactured by Samsung - with part number ams495qa04. Data for this panel is provided via the - DSI interface, however commands are sent via a 9-bit 3-wire SPI - interface. The MISO pin of SPI3 of the SOC is wired to the input of - the panel, so it must be bitbanged. - -This devicetree enables the following hardware: - - HDMI (plus audio). - - Analog audio, including speakers. - - All buttons. - - All SDMMC/eMMC/SDIO controllers. - - The ADC joysticks (note a pending patch is required to use them). - - WiFi/Bluetooth (note out of tree drivers are required). - - The PWM based vibrator motor. - -The following hardware is not enabled: - - The display panels (drivers are being written and there are issues - with the upstream DSI and VOP2 subsystems). - - Battery (driver pending). - - Touchscreen on the RG353P (note the i2c2 bus is enabled for it). - -Signed-off-by: Chris Morgan -Link: https://lore.kernel.org/r/20220906210324.28986-4-macroalpha82@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 2 + - .../dts/rockchip/rk3566-anbernic-rg353p.dts | 94 ++ - .../dts/rockchip/rk3566-anbernic-rg503.dts | 87 ++ - .../dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 831 ++++++++++++++++++ - 4 files changed, 1014 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts - create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index cdd1f211496d..94639380ec1e 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -60,6 +60,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts -new file mode 100644 -index 000000000000..7a20e2d6876a ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts -@@ -0,0 +1,94 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3566-anbernic-rgxx3.dtsi" -+ -+/ { -+ model = "RG353P"; -+ compatible = "anbernic,rg353p", "rockchip,rk3566"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc0; -+ mmc2 = &sdmmc1; -+ mmc3 = &sdmmc2; -+ }; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ power-supply = <&vcc_sys>; -+ pwms = <&pwm4 0 25000 0>; -+ }; -+}; -+ -+&gpio_keys_control { -+ button-a { -+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; -+ label = "EAST"; -+ linux,code = ; -+ }; -+ -+ button-left { -+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; -+ label = "DPAD-LEFT"; -+ linux,code = ; -+ }; -+ -+ button-r1 { -+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; -+ label = "TR"; -+ linux,code = ; -+ }; -+ -+ button-r2 { -+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; -+ label = "TR2"; -+ linux,code = ; -+ }; -+ -+ button-right { -+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "DPAD-RIGHT"; -+ linux,code = ; -+ }; -+ -+ button-y { -+ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; -+ label = "WEST"; -+ linux,code = ; -+ }; -+}; -+ -+&i2c0 { -+ /* This hardware is physically present but unused. */ -+ power-monitor@62 { -+ compatible = "cellwise,cw2015"; -+ reg = <0x62>; -+ status = "disabled"; -+ }; -+}; -+ -+&i2c2 { -+ pintctrl-names = "default"; -+ pinctrl-0 = <&i2c2m1_xfer>; -+ status = "okay"; -+}; -+ -+&pwm4 { -+ status = "okay"; -+}; -+ -+&sdhci { -+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>; -+ pinctrl-names = "default"; -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts -new file mode 100644 -index 000000000000..3dc01549a5b4 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts -@@ -0,0 +1,87 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3566-anbernic-rgxx3.dtsi" -+ -+/ { -+ model = "RG503"; -+ compatible = "anbernic,rg503", "rockchip,rk3566"; -+ -+ aliases { -+ mmc0 = &sdmmc0; -+ mmc1 = &sdmmc1; -+ mmc2 = &sdmmc2; -+ }; -+ -+ gpio_spi: spi { -+ compatible = "spi-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sck-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -+ mosi-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -+ num-chipselects = <0>; -+ }; -+}; -+ -+&gpio_keys_control { -+ button-a { -+ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; -+ label = "EAST"; -+ linux,code = ; -+ }; -+ -+ button-left { -+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "DPAD-LEFT"; -+ linux,code = ; -+ }; -+ -+ button-right { -+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; -+ label = "DPAD-RIGHT"; -+ linux,code = ; -+ }; -+ -+ button-r1 { -+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; -+ label = "TR"; -+ linux,code = ; -+ }; -+ -+ button-r2 { -+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; -+ label = "TR2"; -+ linux,code = ; -+ }; -+ -+ button-right { -+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; -+ label = "DPAD-RIGHT"; -+ linux,code = ; -+ }; -+ -+ button-y { -+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; -+ label = "WEST"; -+ linux,code = ; -+ }; -+}; -+ -+&pinctrl { -+ gpio-spi { -+ spi_pins: spi-pins { -+ rockchip,pins = -+ <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, -+ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, -+ <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi -new file mode 100644 -index 000000000000..2b455143b86d ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi -@@ -0,0 +1,831 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include -+#include "rk3566.dtsi" -+ -+/ { -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ adc-joystick { -+ compatible = "adc-joystick"; -+ io-channels = <&adc_mux 0>, -+ <&adc_mux 1>, -+ <&adc_mux 2>, -+ <&adc_mux 3>; -+ pinctrl-0 = <&joy_mux_en>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ axis@0 { -+ reg = <0>; -+ abs-flat = <32>; -+ abs-fuzz = <32>; -+ abs-range = <1023 15>; -+ linux,code = ; -+ }; -+ -+ axis@1 { -+ reg = <1>; -+ abs-flat = <32>; -+ abs-fuzz = <32>; -+ abs-range = <15 1023>; -+ linux,code = ; -+ }; -+ -+ axis@2 { -+ reg = <2>; -+ abs-flat = <32>; -+ abs-fuzz = <32>; -+ abs-range = <15 1023>; -+ linux,code = ; -+ }; -+ -+ axis@3 { -+ reg = <3>; -+ abs-flat = <32>; -+ abs-fuzz = <32>; -+ abs-range = <1023 15>; -+ linux,code = ; -+ }; -+ }; -+ -+ adc_keys: adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 0>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <60>; -+ -+ /* -+ * Button is mapped to F key in BSP kernel, but -+ * according to input guidelines it should be mode. -+ */ -+ button-mode { -+ label = "MODE"; -+ linux,code = ; -+ press-threshold-microvolt = <1750>; -+ }; -+ }; -+ -+ adc_mux: adc-mux { -+ compatible = "io-channel-mux"; -+ channels = "left_x", "right_x", "left_y", "right_y"; -+ #io-channel-cells = <1>; -+ io-channels = <&saradc 3>; -+ io-channel-names = "parent"; -+ mux-controls = <&gpio_mux>; -+ settle-time-us = <100>; -+ }; -+ -+ gpio_keys_control: gpio-keys-control { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&btn_pins_ctrl>; -+ pinctrl-names = "default"; -+ -+ button-b { -+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; -+ label = "SOUTH"; -+ linux,code = ; -+ }; -+ -+ button-down { -+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; -+ label = "DPAD-DOWN"; -+ linux,code = ; -+ }; -+ -+ button-l1 { -+ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; -+ label = "TL"; -+ linux,code = ; -+ }; -+ -+ button-l2 { -+ gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; -+ label = "TL2"; -+ linux,code = ; -+ }; -+ -+ button-select { -+ gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; -+ label = "SELECT"; -+ linux,code = ; -+ }; -+ -+ button-start { -+ gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; -+ label = "START"; -+ linux,code = ; -+ }; -+ -+ button-thumbl { -+ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; -+ label = "THUMBL"; -+ linux,code = ; -+ }; -+ -+ button-thumbr { -+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; -+ label = "THUMBR"; -+ linux,code = ; -+ }; -+ -+ button-up { -+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; -+ label = "DPAD-UP"; -+ linux,code = ; -+ }; -+ -+ button-x { -+ gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; -+ label = "NORTH"; -+ linux,code = ; -+ }; -+ }; -+ -+ gpio_keys_vol: gpio-keys-vol { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-0 = <&btn_pins_vol>; -+ pinctrl-names = "default"; -+ -+ button-vol-down { -+ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; -+ label = "VOLUMEDOWN"; -+ linux,code = ; -+ }; -+ -+ button-vol-up { -+ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; -+ label = "VOLUMEUP"; -+ linux,code = ; -+ }; -+ }; -+ -+ gpio_mux: mux-controller { -+ compatible = "gpio-mux"; -+ mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, -+ <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; -+ #mux-control-cells = <0>; -+ }; -+ -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ ddc-i2c-bus = <&i2c5>; -+ type = "c"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ leds: gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&led_pins>; -+ pinctrl-names = "default"; -+ -+ green_led: led-0 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_POWER; -+ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ amber_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_CHARGING; -+ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ retain-state-suspended; -+ }; -+ -+ red_led: led-2 { -+ color = ; -+ default-state = "off"; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ /* Channels reversed for both headphones and speakers. */ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "anbernic_rk817"; -+ simple-audio-card,aux-devs = <&spk_amp>; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,widgets = -+ "Microphone", "Mic Jack", -+ "Headphone", "Headphones", -+ "Speaker", "Internal Speakers"; -+ simple-audio-card,routing = -+ "MICL", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR", -+ "Internal Speakers", "Speaker Amp OUTL", -+ "Internal Speakers", "Speaker Amp OUTR", -+ "Speaker Amp INL", "HPOL", -+ "Speaker Amp INR", "HPOR"; -+ simple-audio-card,pin-switches = "Internal Speakers"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&rk817>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1_8ch>; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk817 1>; -+ clock-names = "ext_clock"; -+ pinctrl-0 = <&wifi_enable_h>; -+ pinctrl-names = "default"; -+ post-power-on-delay-ms = <200>; -+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ spk_amp: audio-amplifier { -+ compatible = "simple-audio-amplifier"; -+ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&spk_amp_enable_h>; -+ pinctrl-names = "default"; -+ sound-name-prefix = "Speaker Amp"; -+ }; -+ -+ vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ pinctrl-0 = <&vcc_lcd_h>; -+ pinctrl-names = "default"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_lcd0_n"; -+ vin-supply = <&vcc_3v3>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_sys: regulator-vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3800000>; -+ regulator-max-microvolt = <3800000>; -+ regulator-name = "vcc_sys"; -+ }; -+ -+ vcc_wifi: regulator-vcc-wifi { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&vcc_wifi_h>; -+ pinctrl-names = "default"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_wifi"; -+ }; -+ -+ vibrator: pwm-vibrator { -+ compatible = "pwm-vibrator"; -+ pwm-names = "enable"; -+ pwms = <&pwm5 0 1000000000 0>; -+ }; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c5>; -+ pinctrl-0 = <&hdmitxm0_cec>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ rk817: pmic@20 { -+ compatible = "rockchip,rk817"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ #clock-cells = <1>; -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc_sys>; -+ vcc8-supply = <&vcc_sys>; -+ vcc9-supply = <&dcdc_boost>; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-init-microvolt = <900000>; -+ regulator-ramp-delay = <6001>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vdd_logic"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-init-microvolt = <900000>; -+ regulator-ramp-delay = <6001>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vdd_gpu"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vcc_ddr"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vcc_3v3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_pmu"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vdda_0v9"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vdda0v9_pmu"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vccio_acodec"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vccio_sd"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_pmu"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_1v8: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc1v8_dvp"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc2v8_dvp: LDO_REG9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-name = "vcc2v8_dvp"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ dcdc_boost: BOOST { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4700000>; -+ regulator-max-microvolt = <5400000>; -+ regulator-name = "boost"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ otg_switch: OTG_SWITCH { -+ regulator-name = "otg_switch"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu: regulator@40 { -+ compatible = "fcs,fan53555"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1390000>; -+ regulator-init-microvolt = <900000>; -+ regulator-name = "vdd_cpu"; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc_sys>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ /* Unknown/unused device at 0x3c */ -+ status = "disabled"; -+}; -+ -+&i2c5 { -+ pinctrl-0 = <&i2c5m1_xfer>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ -+&i2s0_8ch { -+ status = "okay"; -+}; -+ -+&i2s1_8ch { -+ pinctrl-0 = <&i2s1m0_sclktx -+ &i2s1m0_lrcktx -+ &i2s1m0_sdi0 -+ &i2s1m0_sdo0>; -+ pinctrl-names = "default"; -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ audio-amplifier { -+ spk_amp_enable_h: spk-amp-enable-h { -+ rockchip,pins = -+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ gpio-btns { -+ btn_pins_ctrl: btn-pins-ctrl { -+ rockchip,pins = -+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ btn_pins_vol: btn-pins-vol { -+ rockchip,pins = -+ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, -+ <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ gpio-led { -+ led_pins: led-pins { -+ rockchip,pins = -+ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, -+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, -+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ joy-mux { -+ joy_mux_en: joy-mux-en { -+ rockchip,pins = -+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = -+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = -+ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ vcc3v3-lcd { -+ vcc_lcd_h: vcc-lcd-h { -+ rockchip,pins = -+ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ vcc-wifi { -+ vcc_wifi_h: vcc-wifi-h { -+ rockchip,pins = -+ <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ status = "okay"; -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc1v8_dvp>; -+ vccio7-supply = <&vcc_3v3>; -+}; -+ -+&pwm5 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>; -+ pinctrl-names = "default"; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc1v8_dvp>; -+ status = "okay"; -+}; -+ -+&sdmmc2 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; -+ pinctrl-names = "default"; -+ vmmc-supply = <&vcc_wifi>; -+ vqmmc-supply = <&vcca1v8_pmu>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; -+ pinctrl-names = "default"; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "realtek,rtl8821cs-bt"; -+ device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; -+ enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; -+ host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+/* -+ * Lack the schematics to verify, but port works as a peripheral -+ * (and not a host or OTG port). -+ */ -+&usb_host0_xhci { -+ dr_mode = "peripheral"; -+ phys = <&usb2phy0_otg>; -+ phy-names = "usb2-phy"; -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ phy-names = "usb2-phy", "usb3-phy"; -+ phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>; -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ status = "okay"; -+}; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Mon, 18 Jul 2022 05:31:45 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add PCIe 2 nodes to quartz64-b - -This adds the regulator node to the quartz64-b device tree, -and enables the PCIe 2 controller and combphy for it. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20220718033145.792657-1-frattaroli.nicolas@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3566-quartz64-b.dts | 34 +++++++++++++++++++ - 1 file changed, 34 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -index c8315d703ad0..0f623198970f 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -@@ -69,6 +69,18 @@ sdio_pwrseq: sdio-pwrseq { - power-off-delay-us = <5000000>; - }; - -+ vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_enable_h>; -+ regulator-name = "vcc3v3_pcie_p"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3>; -+ }; -+ - vcc5v0_in: vcc5v0-in-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_in"; -@@ -128,6 +140,10 @@ &combphy1 { - status = "okay"; - }; - -+&combphy2 { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_cpu>; - }; -@@ -457,6 +473,14 @@ rgmii_phy1: ethernet-phy@1 { - }; - }; - -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie_p>; -+ status = "okay"; -+}; -+ - &pinctrl { - bt { - bt_enable_h: bt-enable-h { -@@ -478,6 +502,16 @@ user_led_enable_h: user-led-enable-h { - }; - }; - -+ pcie { -+ pcie_enable_h: pcie-enable-h { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int: pmic_int { - rockchip,pins = - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 26 Jul 2022 10:30:46 +0800 -Subject: [PATCH] arm64: dts: rockchip: add rtc to rock3a - -Add devicetree node for hym8563 rtc to -Radxa ROCK3 Model A board. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20220726023046.5876-1-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-rock-3a.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 52a437f48301..28a1db4958c7 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -484,6 +484,23 @@ &i2c4 { - status = "disabled"; - }; - -+&i2c5 { -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "rtcic_32kout"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ wakeup-source; -+ }; -+}; -+ - &i2s0_8ch { - status = "okay"; - }; -@@ -524,6 +541,12 @@ eth_phy_rst: eth_phy_rst { - }; - }; - -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ - leds { - led_user_en: led_user_en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 26 Jul 2022 10:35:16 +0800 -Subject: [PATCH] arm64: dts: rockchip: Enable PCIe controller on rock3a - -Add the nodes to enable the PCIe controller on the -Radxa ROCK3 Model A board. Run test with the MT7921 -pcie wireless card. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20220726023516.6487-1-amadeus@jmu.edu.cn -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-rock-3a.dts | 34 +++++++++++++++++++ - 1 file changed, 34 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 28a1db4958c7..fb87a168fe96 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -67,6 +67,18 @@ vcc12v_dcin: vcc12v-dcin { - regulator-boot-on; - }; - -+ vcc3v3_pcie: vcc3v3-pcie-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_enable_h>; -+ regulator-name = "vcc3v3_pcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; -@@ -173,6 +185,10 @@ &combphy1 { - status = "okay"; - }; - -+&combphy2 { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_cpu>; - }; -@@ -522,6 +538,14 @@ rgmii_phy1: ethernet-phy@0 { - }; - }; - -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ status = "okay"; -+}; -+ - &pinctrl { - cam { - vcc_cam_en: vcc_cam_en { -@@ -553,6 +577,16 @@ led_user_en: led_user_en { - }; - }; - -+ pcie { -+ pcie_enable_h: pcie-enable-h { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int: pmic_int { - rockchip,pins = - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Piotr Oniszczuk -Date: Mon, 14 Feb 2022 22:29:54 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add VPU support for RK3568/RK3566 - -RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8 -video formats. - -This patch enables RK356x video decoder in RK356x device-tree -include. - -Tested on [1] with FFmpeg v4l2_request code taken from [2] -with MPEG2, H.642 and VP8 samples with results [3]. - -[1] https://github.com/warpme/minimyth2 -[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch -[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt - -Signed-off-by: Piotr Oniszczuk -Reviewed-by: Ezequiel Garcia -Link: https://lore.kernel.org/r/20220214212955.1178947-2-piotr.oniszczuk@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index c66b60302803..351797102a19 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -592,6 +592,26 @@ gpu: gpu@fde60000 { - status = "disabled"; - }; - -+ vpu: video-codec@fdea0400 { -+ compatible = "rockchip,rk3568-vpu"; -+ reg = <0x0 0xfdea0000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vdpu_mmu>; -+ power-domains = <&power RK3568_PD_VPU>; -+ }; -+ -+ vdpu_mmu: iommu@fdea0800 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdea0800 0x0 0x40>; -+ interrupts = ; -+ clock-names = "aclk", "iface"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ power-domains = <&power RK3568_PD_VPU>; -+ #iommu-cells = <0>; -+ }; -+ - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Sun, 12 Jun 2022 17:53:46 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add Hantro encoder node to rk356x - -The RK3566 and RK3568 come with a dedicated Hantro instance solely for -encoding. This patch adds a node for this to the device tree, along with -a node for its MMU. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20220612155346.16288-4-frattaroli.nicolas@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 351797102a19..fd903e697aa2 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -612,6 +612,26 @@ vdpu_mmu: iommu@fdea0800 { - #iommu-cells = <0>; - }; - -+ vepu: video-codec@fdee0000 { -+ compatible = "rockchip,rk3568-vepu"; -+ reg = <0x0 0xfdee0000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu_mmu>; -+ power-domains = <&power RK3568_PD_RGA>; -+ }; -+ -+ vepu_mmu: iommu@fdee0800 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdee0800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3568_PD_RGA>; -+ #iommu-cells = <0>; -+ }; -+ - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Judy Hsiao -Date: Fri, 8 Jul 2022 08:07:26 +0000 -Subject: [PATCH] arm64: dts: rockchip: use BCLK to GPIO switch on rk3399 - -We discoverd that the state of BCLK on, LRCLK off and SD_MODE on -may cause the speaker melting issue. Removing LRCLK while BCLK -is present can cause unexpected output behavior including a large -DC output voltage as described in the Max98357a datasheet. - -In order to: - 1. prevent BCLK from turning on by other component. - 2. keep BCLK and LRCLK being present at the same time - -This patch adjusts the device tree to allow BCLK to switch -to GPIO func before LRCLK output, and switch back during -LRCLK is output. - -Signed-off-by: Judy Hsiao -Reviewed-by: Brian Norris -Link: https://lore.kernel.org/r/20220708080726.4170711-1-judyhsiao@chromium.org -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 10 ++++++++ - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++- - 2 files changed, 34 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -index 40d4053fba80..ed3348b558f8 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -@@ -768,6 +768,16 @@ &i2s0_8ch_bus { - <4 RK_PA0 1 &pcfg_pull_none_6ma>; - }; - -+&i2s0_8ch_bus_bclk_off { -+ rockchip,pins = -+ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>, -+ <3 RK_PD1 1 &pcfg_pull_none_6ma>, -+ <3 RK_PD2 1 &pcfg_pull_none_6ma>, -+ <3 RK_PD3 1 &pcfg_pull_none_6ma>, -+ <3 RK_PD7 1 &pcfg_pull_none_6ma>, -+ <4 RK_PA0 1 &pcfg_pull_none_6ma>; -+}; -+ - /* there is no external pull up, so need to set this pin pull up */ - &sdmmc_cd_pin { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 9d5b0e8c9cca..f4fbd5bece0e 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1664,8 +1664,9 @@ i2s0: i2s@ff880000 { - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; -- pinctrl-names = "default"; -+ pinctrl-names = "bclk_on", "bclk_off"; - pinctrl-0 = <&i2s0_8ch_bus>; -+ pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; -@@ -2409,6 +2410,19 @@ i2s0_8ch_bus: i2s0-8ch-bus { - <3 RK_PD7 1 &pcfg_pull_none>, - <4 RK_PA0 1 &pcfg_pull_none>; - }; -+ -+ i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { -+ rockchip,pins = -+ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, -+ <3 RK_PD1 1 &pcfg_pull_none>, -+ <3 RK_PD2 1 &pcfg_pull_none>, -+ <3 RK_PD3 1 &pcfg_pull_none>, -+ <3 RK_PD4 1 &pcfg_pull_none>, -+ <3 RK_PD5 1 &pcfg_pull_none>, -+ <3 RK_PD6 1 &pcfg_pull_none>, -+ <3 RK_PD7 1 &pcfg_pull_none>, -+ <4 RK_PA0 1 &pcfg_pull_none>; -+ }; - }; - - i2s1 { -@@ -2420,6 +2434,15 @@ i2s1_2ch_bus: i2s1-2ch-bus { - <4 RK_PA6 1 &pcfg_pull_none>, - <4 RK_PA7 1 &pcfg_pull_none>; - }; -+ -+ i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { -+ rockchip,pins = -+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, -+ <4 RK_PA4 1 &pcfg_pull_none>, -+ <4 RK_PA5 1 &pcfg_pull_none>, -+ <4 RK_PA6 1 &pcfg_pull_none>, -+ <4 RK_PA7 1 &pcfg_pull_none>; -+ }; - }; - - sdio0 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Furkan Kardame -Date: Mon, 27 Jun 2022 23:22:08 +0300 -Subject: [PATCH] arm64: dts: rockchip: Enable video output on rk3566-roc-pc - -Add the device tree nodes to enable video output on the Station M2. -Enable the GPU and HDMI nodes and fix the GPU regulator range. - -Signed-off-by: Furkan Kardame -Link: https://lore.kernel.org/r/20220627202208.45770-1-f.kardame@manjaro.org -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 52 +++++++++++++++++++ - 1 file changed, 52 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts -index 57759b66d44d..dba648c2f57e 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3566.dtsi" - - / { -@@ -27,6 +28,17 @@ gmac1_clkin: external-gmac1-clock { - #clock-cells = <0>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -149,6 +161,29 @@ &gmac1m0_clkinout - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -577,3 +612,20 @@ &usb_host0_ehci { - &usb_host0_ohci { - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Hugh Cole-Baker -Date: Tue, 19 Oct 2021 22:58:43 +0100 -Subject: [PATCH] arm64: dts: rockchip: enable gamma control on RK3399 - -Define the memory region on RK3399 VOPs containing the gamma LUT at -base+0x2000. - -Signed-off-by: Hugh Cole-Baker -Tested-by: Linus Heckemann -Link: https://lore.kernel.org/r/20211019215843.42718-4-sigmaris@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index f4fbd5bece0e..92c2207e686c 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1702,7 +1702,7 @@ i2s2: i2s@ff8a0000 { - - vopl: vop@ff8f0000 { - compatible = "rockchip,rk3399-vop-lit"; -- reg = <0x0 0xff8f0000 0x0 0x3efc>; -+ reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; - interrupts = ; - assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - assigned-clock-rates = <400000000>, <100000000>; -@@ -1758,7 +1758,7 @@ vopl_mmu: iommu@ff8f3f00 { - - vopb: vop@ff900000 { - compatible = "rockchip,rk3399-vop-big"; -- reg = <0x0 0xff900000 0x0 0x3efc>; -+ reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - assigned-clock-rates = <400000000>, <100000000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Wed, 17 Aug 2022 12:33:55 -0700 -Subject: [PATCH] dt-bindings: arm: rockchip: Add gru-scarlet sku{2,4} variants - -The Gru-Scarlet family includes a variety of SKU identifiers, using -parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few -different manufacturer names) also use the Innolux display. - -For reference, the original vendor tree source: - -CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility -https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 - -CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree -https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc - -Signed-off-by: Brian Norris -Link: https://lore.kernel.org/r/20220817123350.1.Ibb15bab32dbfa0d89f86321c4eae7adbc8d7ad4a@changeid -Signed-off-by: Heiko Stuebner ---- - .../devicetree/bindings/arm/rockchip.yaml | 27 ++++++++++++++++++- - 1 file changed, 26 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index ae7fe15a3b89..58fc4b677321 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -373,30 +373,55 @@ properties: - - const: google,gru - - const: rockchip,rk3399 - -- - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) -+ - description: | -+ Google Scarlet - Innolux display (Acer Chromebook Tab 10 and more) - items: -+ - const: google,scarlet-rev15-sku2 -+ - const: google,scarlet-rev15-sku4 - - const: google,scarlet-rev15-sku6 - - const: google,scarlet-rev15 -+ - const: google,scarlet-rev14-sku2 -+ - const: google,scarlet-rev14-sku4 - - const: google,scarlet-rev14-sku6 - - const: google,scarlet-rev14 -+ - const: google,scarlet-rev13-sku2 -+ - const: google,scarlet-rev13-sku4 - - const: google,scarlet-rev13-sku6 - - const: google,scarlet-rev13 -+ - const: google,scarlet-rev12-sku2 -+ - const: google,scarlet-rev12-sku4 - - const: google,scarlet-rev12-sku6 - - const: google,scarlet-rev12 -+ - const: google,scarlet-rev11-sku2 -+ - const: google,scarlet-rev11-sku4 - - const: google,scarlet-rev11-sku6 - - const: google,scarlet-rev11 -+ - const: google,scarlet-rev10-sku2 -+ - const: google,scarlet-rev10-sku4 - - const: google,scarlet-rev10-sku6 - - const: google,scarlet-rev10 -+ - const: google,scarlet-rev9-sku2 -+ - const: google,scarlet-rev9-sku4 - - const: google,scarlet-rev9-sku6 - - const: google,scarlet-rev9 -+ - const: google,scarlet-rev8-sku2 -+ - const: google,scarlet-rev8-sku4 - - const: google,scarlet-rev8-sku6 - - const: google,scarlet-rev8 -+ - const: google,scarlet-rev7-sku2 -+ - const: google,scarlet-rev7-sku4 - - const: google,scarlet-rev7-sku6 - - const: google,scarlet-rev7 -+ - const: google,scarlet-rev6-sku2 -+ - const: google,scarlet-rev6-sku4 - - const: google,scarlet-rev6-sku6 - - const: google,scarlet-rev6 -+ - const: google,scarlet-rev5-sku2 -+ - const: google,scarlet-rev5-sku4 - - const: google,scarlet-rev5-sku6 - - const: google,scarlet-rev5 -+ - const: google,scarlet-rev4-sku2 -+ - const: google,scarlet-rev4-sku4 - - const: google,scarlet-rev4-sku6 - - const: google,scarlet-rev4 - - const: google,scarlet - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Wed, 17 Aug 2022 12:33:56 -0700 -Subject: [PATCH] arm64: dts: rockchip: Support gru-scarlet sku{2,4} variants - -The Gru-Scarlet family includes a variety of SKU identifiers, using -parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few -different manufacturer names) also use the Innolux display. - -Without this, a SKU2 device may non-deterministically (depending on the -matching order of DTBs and bootloader behavior) select either one of the -INX DTBs (rk3399-gru-scarlet-dumo.dtb or rk3399-gru-scarlet-inx.dtb) or -the KingDisplay DTB (rk3399-gru-scarlet-kd.dtb), to ill effect. - -For reference, the original vendor tree source: - -CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility -https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 - -CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree -https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc - -Signed-off-by: Brian Norris -Link: https://lore.kernel.org/r/20220817123350.2.I5f4fd0808a927b08e267c189712fb4a85931fd3b@changeid -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-gru-scarlet-inx.dts | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts -index 2d721a974790..5d1879033e7c 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts -@@ -11,17 +11,29 @@ - - / { - model = "Google Scarlet"; -- compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", -+ compatible = "google,scarlet-rev15-sku2", "google,scarlet-rev15-sku4", -+ "google,scarlet-rev15-sku6", "google,scarlet-rev15", -+ "google,scarlet-rev14-sku2", "google,scarlet-rev14-sku4", - "google,scarlet-rev14-sku6", "google,scarlet-rev14", -+ "google,scarlet-rev13-sku2", "google,scarlet-rev13-sku4", - "google,scarlet-rev13-sku6", "google,scarlet-rev13", -+ "google,scarlet-rev12-sku2", "google,scarlet-rev12-sku4", - "google,scarlet-rev12-sku6", "google,scarlet-rev12", -+ "google,scarlet-rev11-sku2", "google,scarlet-rev11-sku4", - "google,scarlet-rev11-sku6", "google,scarlet-rev11", -+ "google,scarlet-rev10-sku2", "google,scarlet-rev10-sku4", - "google,scarlet-rev10-sku6", "google,scarlet-rev10", -+ "google,scarlet-rev9-sku2", "google,scarlet-rev9-sku4", - "google,scarlet-rev9-sku6", "google,scarlet-rev9", -+ "google,scarlet-rev8-sku2", "google,scarlet-rev8-sku4", - "google,scarlet-rev8-sku6", "google,scarlet-rev8", -+ "google,scarlet-rev7-sku2", "google,scarlet-rev7-sku4", - "google,scarlet-rev7-sku6", "google,scarlet-rev7", -+ "google,scarlet-rev6-sku2", "google,scarlet-rev6-sku4", - "google,scarlet-rev6-sku6", "google,scarlet-rev6", -+ "google,scarlet-rev5-sku2", "google,scarlet-rev5-sku4", - "google,scarlet-rev5-sku6", "google,scarlet-rev5", -+ "google,scarlet-rev4-sku2", "google,scarlet-rev4-sku4", - "google,scarlet-rev4-sku6", "google,scarlet-rev4", - "google,scarlet", "google,gru", "rockchip,rk3399"; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Markus Reichl -Date: Thu, 15 Sep 2022 13:11:36 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pc - -Add avdd-0v9-supply and avdd-1v8-supply to hdmi node for -rk3399-roc-pc to silence dmesg warning and match the name -of the 1v8 supply to the circuit sheet. - -Signed-off-by: Markus Reichl -Link: https://lore.kernel.org/r/20220915111138.1108-1-m.reichl@fivetechno.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -index acb174d3a8c5..2f4b1b2e3ac7 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -@@ -271,6 +271,8 @@ &gpu { - }; - - &hdmi { -+ avdd-0v9-supply = <&vcca0v9_hdmi>; -+ avdd-1v8-supply = <&vcca1v8_hdmi>; - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; -@@ -369,8 +371,8 @@ regulator-state-mem { - }; - }; - -- vcc1v8_hdmi: LDO_REG2 { -- regulator-name = "vcc1v8_hdmi"; -+ vcca1v8_hdmi: LDO_REG2 { -+ regulator-name = "vcca1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Quentin Schulz -Date: Fri, 16 Sep 2022 11:17:46 +0200 -Subject: [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to - px30 - -The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are -2-channel I2S/PCM controllers handled by the same controller driver, and -i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller -driver. - -This adds the device tree node required to enable I2S0 on PX30. - -This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX -(rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board. - -Signed-off-by: Quentin Schulz -Link: https://lore.kernel.org/r/20220916091746.35108-1-foss+kernel@0leil.net -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi -index 214f94fea3dc..bfa3580429d1 100644 ---- a/arch/arm64/boot/dts/rockchip/px30.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi -@@ -365,6 +365,28 @@ uart0: serial@ff030000 { - status = "disabled"; - }; - -+ i2s0_8ch: i2s@ff060000 { -+ compatible = "rockchip,px30-i2s-tdm"; -+ reg = <0x0 0xff060000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac 16>, <&dmac 17>; -+ dma-names = "tx", "rx"; -+ rockchip,grf = <&grf>; -+ resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; -+ reset-names = "tx-m", "rx-m"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx -+ &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx -+ &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 -+ &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 -+ &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 -+ &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ - i2s1_2ch: i2s@ff070000 { - compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff070000 0x0 0x1000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Thu, 15 Sep 2022 10:25:10 +0800 -Subject: [PATCH] dt-bindings: Add doc for FriendlyARM NanoPi R4S Enterprise - Edition - -Add devicetree binding documentation for the FriendlyARM NanoPi R4S -Enterprise Edition. - -Signed-off-by: Tianling Shen -Acked-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220915022511.4267-1-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 58fc4b677321..4c64d9ff089c 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -161,6 +161,7 @@ properties: - - friendlyarm,nanopi-m4b - - friendlyarm,nanopi-neo4 - - friendlyarm,nanopi-r4s -+ - friendlyarm,nanopi-r4s-enterprise - - const: rockchip,rk3399 - - - description: GeekBuying GeekBox - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Thu, 15 Sep 2022 10:25:11 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise - Edition - -The only diffrence against the standrard edition is that the enterprise -one has a built-in EEPROM chip which stores a globally unique MAC address. - -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20220915022511.4267-2-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../rockchip/rk3399-nanopi-r4s-enterprise.dts | 29 +++++++++++++++++++ - 2 files changed, 30 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 94639380ec1e..8c15593c0ca4 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts -new file mode 100644 -index 000000000000..a23d11ca0eb6 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3399-nanopi-r4s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S Enterprise Edition"; -+ compatible = "friendlyarm,nanopi-r4s-enterprise", "rockchip,rk3399"; -+}; -+ -+&gmac { -+ nvmem-cells = <&mac_address>; -+ nvmem-cell-names = "mac-address"; -+}; -+ -+&i2c2 { -+ eeprom@51 { -+ compatible = "microchip,24c02", "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ size = <256>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ mac_address: mac-address@fa { -+ reg = <0xfa 0x06>; -+ }; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Tue, 6 Sep 2022 12:48:21 -0500 -Subject: [PATCH] drm/rockchip: dsi: add rk3568 support - -Add the compatible and GRF definitions for the RK3568 soc. - -Signed-off-by: Chris Morgan -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220906174823.28561-4-macroalpha82@gmail.com ---- - .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 ++++++++++++++++++- - 1 file changed, 49 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -index 110e83aad9bb..bf6948125b84 100644 ---- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -@@ -179,6 +179,23 @@ - #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) - #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) - -+#define RK3568_GRF_VO_CON2 0x0368 -+#define RK3568_DSI0_SKEWCALHS (0x1f << 11) -+#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) -+#define RK3568_DSI0_TURNDISABLE BIT(2) -+#define RK3568_DSI0_FORCERXMODE BIT(0) -+ -+/* -+ * Note these registers do not appear in the datasheet, they are -+ * however present in the BSP driver which is where these values -+ * come from. Name GRF_VO_CON3 is assumed. -+ */ -+#define RK3568_GRF_VO_CON3 0x36c -+#define RK3568_DSI1_SKEWCALHS (0x1f << 11) -+#define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4) -+#define RK3568_DSI1_TURNDISABLE BIT(2) -+#define RK3568_DSI1_FORCERXMODE BIT(0) -+ - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - - enum { -@@ -735,8 +752,9 @@ static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) - static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, - int mux) - { -- regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, -- mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); -+ if (dsi->cdata->lcdsel_grf_reg < 0) -+ regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, -+ mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); - } - - static int -@@ -963,6 +981,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, - DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); - goto out_pll_clk; - } -+ rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, -+ dev->of_node, 0, 0); - - ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); - if (ret) { -@@ -1612,6 +1632,30 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { - { /* sentinel */ } - }; - -+static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { -+ { -+ .reg = 0xfe060000, -+ .lcdsel_grf_reg = -1, -+ .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, -+ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS | -+ RK3568_DSI0_FORCETXSTOPMODE | -+ RK3568_DSI0_TURNDISABLE | -+ RK3568_DSI0_FORCERXMODE), -+ .max_data_lanes = 4, -+ }, -+ { -+ .reg = 0xfe070000, -+ .lcdsel_grf_reg = -1, -+ .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, -+ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS | -+ RK3568_DSI1_FORCETXSTOPMODE | -+ RK3568_DSI1_TURNDISABLE | -+ RK3568_DSI1_FORCERXMODE), -+ .max_data_lanes = 4, -+ }, -+ { /* sentinel */ } -+}; -+ - static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { - { - .compatible = "rockchip,px30-mipi-dsi", -@@ -1622,6 +1666,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { - }, { - .compatible = "rockchip,rk3399-mipi-dsi", - .data = &rk3399_chip_data, -+ }, { -+ .compatible = "rockchip,rk3568-mipi-dsi", -+ .data = &rk3568_chip_data, - }, - { /* sentinel */ } - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Hugh Cole-Baker -Date: Tue, 19 Oct 2021 22:58:41 +0100 -Subject: [PATCH] drm/rockchip: define gamma registers for RK3399 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The VOP on RK3399 has a different approach from previous versions for -setting a gamma lookup table, using an update_gamma_lut register. As -this differs from RK3288, give RK3399 its own set of "common" register -definitions. - -Signed-off-by: Hugh Cole-Baker -Tested-by: "Milan P. Stanić" -Tested-by: Linus Heckemann -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20211019215843.42718-2-sigmaris@gmail.com ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++ - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++-- - drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 + - 3 files changed, 25 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index ba88addc1a75..8502849833d9 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -113,6 +113,8 @@ struct vop_common { - struct vop_reg dither_down_en; - struct vop_reg dither_up; - struct vop_reg dsp_lut_en; -+ struct vop_reg update_gamma_lut; -+ struct vop_reg lut_buffer_index; - struct vop_reg gate_en; - struct vop_reg mmu_en; - struct vop_reg out_mode; -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index d03dd0402923..014f99e8928e 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -875,6 +875,24 @@ static const struct vop_output rk3399_output = { - .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), - }; - -+static const struct vop_common rk3399_common = { -+ .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), -+ .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), -+ .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20), -+ .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4), -+ .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3), -+ .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2), -+ .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1), -+ .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), -+ .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0), -+ .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7), -+ .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1), -+ .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), -+ .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), -+ .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), -+ .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), -+}; -+ - static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { - .y2r_coefficients = { - VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), -@@ -957,7 +975,7 @@ static const struct vop_data rk3399_vop_big = { - .version = VOP_VERSION(3, 5), - .feature = VOP_FEATURE_OUTPUT_RGB10, - .intr = &rk3366_vop_intr, -- .common = &rk3288_common, -+ .common = &rk3399_common, - .modeset = &rk3288_modeset, - .output = &rk3399_output, - .afbc = &rk3399_vop_afbc, -@@ -965,6 +983,7 @@ static const struct vop_data rk3399_vop_big = { - .win = rk3399_vop_win_data, - .win_size = ARRAY_SIZE(rk3399_vop_win_data), - .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, -+ .lut_size = 1024, - }; - - static const struct vop_win_data rk3399_vop_lit_win_data[] = { -@@ -983,13 +1002,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { - static const struct vop_data rk3399_vop_lit = { - .version = VOP_VERSION(3, 6), - .intr = &rk3366_vop_intr, -- .common = &rk3288_common, -+ .common = &rk3399_common, - .modeset = &rk3288_modeset, - .output = &rk3399_output, - .misc = &rk3368_misc, - .win = rk3399_vop_lit_win_data, - .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), - .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, -+ .lut_size = 256, - }; - - static const struct vop_win_data rk3228_vop_win_data[] = { -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h -index 0b3cd65ba5c1..406e981c75bd 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h -@@ -628,6 +628,7 @@ - #define RK3399_YUV2YUV_WIN 0x02c0 - #define RK3399_YUV2YUV_POST 0x02c4 - #define RK3399_AUTO_GATING_EN 0x02cc -+#define RK3399_DBG_POST_REG1 0x036c - #define RK3399_WIN0_CSC_COE 0x03a0 - #define RK3399_WIN1_CSC_COE 0x03c0 - #define RK3399_WIN2_CSC_COE 0x03e0 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Hugh Cole-Baker -Date: Tue, 19 Oct 2021 22:58:42 +0100 -Subject: [PATCH] drm/rockchip: support gamma control on RK3399 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its -"big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP. -Compared to the RK3288, it no longer requires disabling gamma while -updating the LUT. On the RK3399, the LUT can be updated at any time as -the hardware has two LUT buffers, one can be written while the other is -in use. A swap of the buffers is triggered by writing 1 to the -update_gamma_lut register. - -Signed-off-by: Hugh Cole-Baker -Tested-by: "Milan P. Stanić" -Tested-by: Linus Heckemann -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20211019215843.42718-3-sigmaris@gmail.com ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 105 +++++++++++++------- - 1 file changed, 71 insertions(+), 34 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index ad3958b6f8bf..d32117633efe 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -68,6 +69,9 @@ - #define VOP_REG_SET(vop, group, name, v) \ - vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) - -+#define VOP_HAS_REG(vop, group, name) \ -+ (!!(vop->data->group->name.mask)) -+ - #define VOP_INTR_SET_TYPE(vop, name, type, v) \ - do { \ - int i, reg = 0, mask = 0; \ -@@ -1224,17 +1228,22 @@ static bool vop_dsp_lut_is_enabled(struct vop *vop) - return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); - } - -+static u32 vop_lut_buffer_index(struct vop *vop) -+{ -+ return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); -+} -+ - static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) - { - struct drm_color_lut *lut = crtc->state->gamma_lut->data; -- unsigned int i; -+ unsigned int i, bpc = ilog2(vop->data->lut_size); - - for (i = 0; i < crtc->gamma_size; i++) { - u32 word; - -- word = (drm_color_lut_extract(lut[i].red, 10) << 20) | -- (drm_color_lut_extract(lut[i].green, 10) << 10) | -- drm_color_lut_extract(lut[i].blue, 10); -+ word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | -+ (drm_color_lut_extract(lut[i].green, bpc) << bpc) | -+ drm_color_lut_extract(lut[i].blue, bpc); - writel(word, vop->lut_regs + i * 4); - } - } -@@ -1244,38 +1253,66 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, - { - struct drm_crtc_state *state = crtc->state; - unsigned int idle; -+ u32 lut_idx, old_idx; - int ret; - - if (!vop->lut_regs) - return; -- /* -- * To disable gamma (gamma_lut is null) or to write -- * an update to the LUT, clear dsp_lut_en. -- */ -- spin_lock(&vop->reg_lock); -- VOP_REG_SET(vop, common, dsp_lut_en, 0); -- vop_cfg_done(vop); -- spin_unlock(&vop->reg_lock); - -- /* -- * In order to write the LUT to the internal memory, -- * we need to first make sure the dsp_lut_en bit is cleared. -- */ -- ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, -- idle, !idle, 5, 30 * 1000); -- if (ret) { -- DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); -- return; -- } -+ if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { -+ /* -+ * To disable gamma (gamma_lut is null) or to write -+ * an update to the LUT, clear dsp_lut_en. -+ */ -+ spin_lock(&vop->reg_lock); -+ VOP_REG_SET(vop, common, dsp_lut_en, 0); -+ vop_cfg_done(vop); -+ spin_unlock(&vop->reg_lock); - -- if (!state->gamma_lut) -- return; -+ /* -+ * In order to write the LUT to the internal memory, -+ * we need to first make sure the dsp_lut_en bit is cleared. -+ */ -+ ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, -+ idle, !idle, 5, 30 * 1000); -+ if (ret) { -+ DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); -+ return; -+ } -+ -+ if (!state->gamma_lut) -+ return; -+ } else { -+ /* -+ * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, -+ * by setting update_gamma_lut then waiting for lut_buffer_index change -+ */ -+ old_idx = vop_lut_buffer_index(vop); -+ } - - spin_lock(&vop->reg_lock); - vop_crtc_write_gamma_lut(vop, crtc); - VOP_REG_SET(vop, common, dsp_lut_en, 1); -+ VOP_REG_SET(vop, common, update_gamma_lut, 1); - vop_cfg_done(vop); - spin_unlock(&vop->reg_lock); -+ -+ if (VOP_HAS_REG(vop, common, update_gamma_lut)) { -+ ret = readx_poll_timeout(vop_lut_buffer_index, vop, -+ lut_idx, lut_idx != old_idx, 5, 30 * 1000); -+ if (ret) { -+ DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); -+ return; -+ } -+ -+ /* -+ * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit -+ * in our backup of the regs. -+ */ -+ spin_lock(&vop->reg_lock); -+ VOP_REG_SET(vop, common, update_gamma_lut, 0); -+ spin_unlock(&vop->reg_lock); -+ } - } - - static void vop_crtc_atomic_begin(struct drm_crtc *crtc, -@@ -1325,14 +1362,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - return; - } - -- /* -- * If we have a GAMMA LUT in the state, then let's make sure -- * it's updated. We might be coming out of suspend, -- * which means the LUT internal memory needs to be re-written. -- */ -- if (crtc->state->gamma_lut) -- vop_crtc_gamma_set(vop, crtc, old_state); -- - mutex_lock(&vop->vop_lock); - - WARN_ON(vop->event); -@@ -1423,6 +1452,14 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, - - VOP_REG_SET(vop, common, standby, 0); - mutex_unlock(&vop->vop_lock); -+ -+ /* -+ * If we have a GAMMA LUT in the state, then let's make sure -+ * it's updated. We might be coming out of suspend, -+ * which means the LUT internal memory needs to be re-written. -+ */ -+ if (crtc->state->gamma_lut) -+ vop_crtc_gamma_set(vop, crtc, old_state); - } - - static bool vop_fs_irq_is_pending(struct vop *vop) -@@ -2148,8 +2185,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data) - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) { -- if (!vop_data->lut_size) { -- DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); -+ if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { -+ DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); - return -EINVAL; - } - vop->lut_regs = devm_ioremap_resource(dev, res); diff --git a/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch index e489f58c87..368f47fa97 100644 --- a/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch @@ -414,13 +414,13 @@ Required to proper decode H.264@4K Signed-off-by: Alex Bee --- - drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 +++++++++++--- + drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c index 8de6fd2e8eef..002b1a600f93 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c ++++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c @@ -15,7 +15,8 @@ #include "rockchip_vpu2_regs.h"