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Allwinner: Add support for R40
This commit is contained in:
Jernej Skrabec
parent
dae53b5ef0
commit
825d0864bc
@ -0,0 +1,36 @@
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#
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# Configuration for H3 analog output
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#
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<confdir:pcm/front.conf>
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H3_Audio_Codec.pcm.front.0 {
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@args [ CARD ]
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@args.CARD {
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type string
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}
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type hooks
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slave.pcm {
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type hw
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card $CARD
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}
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hooks.0 {
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type ctl_elems
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hook_args [
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{
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name "Line Out Playback Volume"
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lock true
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preserve true
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optional false
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value 31
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}
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{
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name "Line Out Playback Switch"
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lock true
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preserve true
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optional false
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value [ on on ]
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}
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]
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}
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}
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50
projects/Allwinner/devices/R40/options
Normal file
50
projects/Allwinner/devices/R40/options
Normal file
@ -0,0 +1,50 @@
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################################################################################
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# setup system defaults
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################################################################################
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# The TARGET_CPU variable controls which processor should be targeted for
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# generated code.
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case $TARGET_ARCH in
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arm)
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# TARGET_CPU:
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# arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm7m arm7d
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# arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710c
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# arm7100 arm720 arm7500 arm7500fe arm7tdmi arm7tdmi-s arm710t
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# arm720t arm740t strongarm strongarm110 strongarm1100
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# strongarm1110 arm8 arm810 arm9 arm9e arm920 arm920t arm922t
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# arm946e-s arm966e-s arm968e-s arm926ej-s arm940t arm9tdmi
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# arm10tdmi arm1020t arm1026ej-s arm10e arm1020e arm1022e
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# arm1136j-s arm1136jf-s mpcore mpcorenovfp arm1156t2-s
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# arm1176jz-s arm1176jzf-s cortex-a8 cortex-a9 cortex-r4
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# cortex-r4f cortex-m3 cortex-m1 xscale iwmmxt iwmmxt2 ep9312.
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TARGET_CPU="cortex-a7"
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# TARGET_FLOAT:
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# Specifies which floating-point ABI to use. Permissible values are:
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# soft hard
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TARGET_FLOAT="hard"
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# TARGET_FPU:
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# This specifies what floating point hardware (or hardware emulation) is
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# available on the target. Permissible names are:
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# fpa fpe2 fpe3 maverick vfp vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16
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# vfpv3xd vfpv3xd-fp16 neon neon-fp16 vfpv4 vfpv4-d16 fpv4-sp-d16
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# neon-vfpv4.
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TARGET_FPU="neon-vfpv4"
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;;
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esac
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# Kernel target
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KERNEL_TARGET="zImage"
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# OpenGL-ES implementation to use (no / bcm2835-driver / gpu-viv-bin-mx6q)
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OPENGLES="mesa"
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# Mali GPU family
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MALI_FAMILY="400"
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# KODI Player implementation to use (default / bcm2835-driver / libfslvpuwrap)
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KODIPLAYER_DRIVER="$OPENGLES"
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# set the addon project
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ADDON_PROJECT="ARMv7"
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@ -0,0 +1,112 @@
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From 7ace610aa8c87a4854c974299f880f168a8b075d Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Mon, 24 Aug 2020 16:35:00 +0200
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Subject: [PATCH 15/17] clk: r40: initialize clocks earlier
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 63 +++++++++++++++++-----------
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1 file changed, 38 insertions(+), 25 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
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index 84153418453f..5c82fed4b4b9 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
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@@ -5,6 +5,7 @@
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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+#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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@@ -1310,14 +1311,46 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
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struct resource *res;
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struct regmap *regmap;
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void __iomem *reg;
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- u32 val;
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- int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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+ regmap = devm_regmap_init_mmio(&pdev->dev, reg,
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+ &sun8i_r40_ccu_regmap_config);
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id sun8i_r40_ccu_ids[] = {
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+ { .compatible = "allwinner,sun8i-r40-ccu" },
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+ { }
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+};
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+
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+static struct platform_driver sun8i_r40_ccu_driver = {
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+ .probe = sun8i_r40_ccu_probe,
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+ .driver = {
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+ .name = "sun8i-r40-ccu",
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+ .of_match_table = sun8i_r40_ccu_ids,
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+ },
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+};
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+builtin_platform_driver(sun8i_r40_ccu_driver);
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+
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+static void __init sun8i_r40_ccu_setup(struct device_node *node)
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+{
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+ void __iomem *reg;
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+ u32 val;
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+ int ret;
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+
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+ reg = of_iomap(node, 0);
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+ if (IS_ERR(reg)) {
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+ pr_err("%pOF: Could not map the clock registers\n", node);
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+ return;
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+ }
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+
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/* Force the PLL-Audio-1x divider to 1 */
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val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
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val &= ~GENMASK(19, 16);
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@@ -1341,14 +1374,7 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
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writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
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reg + SUN8I_R40_SYS_32K_CLK_REG);
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- regmap = devm_regmap_init_mmio(&pdev->dev, reg,
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- &sun8i_r40_ccu_regmap_config);
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- if (IS_ERR(regmap))
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- return PTR_ERR(regmap);
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-
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- ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
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- if (ret)
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- return ret;
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+ sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc);
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/* Gate then ungate PLL CPU after any rate changes */
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ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
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@@ -1357,19 +1383,6 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
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ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
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&sun8i_r40_cpu_nb);
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- return 0;
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}
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-
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-static const struct of_device_id sun8i_r40_ccu_ids[] = {
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- { .compatible = "allwinner,sun8i-r40-ccu" },
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- { }
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-};
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-
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-static struct platform_driver sun8i_r40_ccu_driver = {
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- .probe = sun8i_r40_ccu_probe,
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- .driver = {
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- .name = "sun8i-r40-ccu",
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- .of_match_table = sun8i_r40_ccu_ids,
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- },
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-};
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-builtin_platform_driver(sun8i_r40_ccu_driver);
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+CLK_OF_DECLARE_DRIVER(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu",
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+ sun8i_r40_ccu_setup);
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--
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2.28.0
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@ -0,0 +1,101 @@
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From 958ad802878443a2f5f06f5f3c796d163fd03ca9 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Mon, 24 Aug 2020 16:35:54 +0200
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Subject: [PATCH 16/17] dts: enable various devices
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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.../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 ++++
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arch/arm/boot/dts/sun8i-r40.dtsi | 42 +++++++++++++++++++
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2 files changed, 51 insertions(+)
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diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
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index 2fc62ef0cb3e..dc673826109f 100644
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--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
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+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
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@@ -113,6 +113,15 @@ &ahci {
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status = "okay";
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};
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+&codec {
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+ allwinner,audio-routing =
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+ "Headphone", "HP",
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+ "Headphone", "HPCOM",
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+ "MIC1", "Mic",
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+ "Mic", "MBIAS";
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+ status = "okay";
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+};
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+
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&de {
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status = "okay";
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};
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diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
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index 7907569e7b5c..6dc075de94ae 100644
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--- a/arch/arm/boot/dts/sun8i-r40.dtsi
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+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
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|
@@ -628,6 +628,18 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
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};
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};
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+ timer@1c20c00 {
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+ compatible = "allwinner,sun4i-a10-timer";
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+ reg = <0x01c20c00 0x90>;
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+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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|
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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|
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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|
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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|
+ clocks = <&osc24M>;
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|
+ };
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|
+
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|
wdt: watchdog@1c20c90 {
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|
compatible = "allwinner,sun4i-a10-wdt";
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|
reg = <0x01c20c90 0x10>;
|
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|
@@ -661,6 +673,25 @@ ir1: ir@1c21c00 {
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|
status = "disabled";
|
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|
};
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|
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|
+ codec: codec@01c22c00 {
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|
+ #sound-dai-cells = <0>;
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|
+ compatible = "allwinner,sun8i-h3-codec";
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|
+ reg = <0x01c22c00 0x300>;
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|
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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|
+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>;
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|
+ clock-names = "apb", "codec";
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|
+ resets = <&ccu RST_BUS_CODEC>;
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|
+ dmas = <&dma 19>, <&dma 19>;
|
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|
+ dma-names = "rx", "tx";
|
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|
+ allwinner,codec-analog-controls = <&codec_analog>;
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|
+ status = "disabled";
|
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|
+ };
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|
+
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|
+ codec_analog: codec-analog@01c22f00 {
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|
+ compatible = "allwinner,sun8i-a23-codec-analog";
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|
+ reg = <0x01c22f00 0x4>;
|
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|
+ };
|
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|
+
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|
ths: thermal-sensor@1c24c00 {
|
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|
compatible = "allwinner,sun8i-r40-ths";
|
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|
reg = <0x01c24c00 0x100>;
|
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|
@@ -866,6 +897,17 @@ gmac_mdio: mdio {
|
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|
};
|
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|
};
|
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|
|
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|
+ hstimer@1c60000 {
|
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|
+ compatible = "allwinner,sun7i-a20-hstimer";
|
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|
+ reg = <0x01c60000 0x1000>;
|
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|
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
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|
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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|
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
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|
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
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|
+ clocks = <&ccu CLK_BUS_HSTIMER>;
|
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|
+ resets = <&ccu RST_BUS_HSTIMER>;
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|
+ };
|
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|
+
|
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|
mbus: dram-controller@1c62000 {
|
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|
compatible = "allwinner,sun8i-r40-mbus";
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|
reg = <0x01c62000 0x1000>;
|
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|
--
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|
2.28.0
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|
|
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@ -0,0 +1,70 @@
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|
From 4347f8f825bf0a775ab552ca37eaa2204fb65188 Mon Sep 17 00:00:00 2001
|
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|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
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|
Date: Sun, 16 Aug 2020 11:01:11 +0200
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|
Subject: [PATCH 17/17] r40 hdmi audio wip
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|
|
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|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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|
---
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|
arch/arm/boot/dts/sun8i-r40.dtsi | 32 ++++++++++++++++++++++++++++++++
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|
1 file changed, 32 insertions(+)
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|
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|
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
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|
index 6dc075de94ae..bd8f4495ad7a 100644
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|
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
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|
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
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|
@@ -111,6 +111,24 @@ de: display-engine {
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|
status = "disabled";
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|
};
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|
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|
+ sound_hdmi: sound {
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|
+ compatible = "simple-audio-card";
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|
+ simple-audio-card,format = "i2s";
|
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|
+ simple-audio-card,name = "allwinner-hdmi";
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|
+ simple-audio-card,mclk-fs = <128>;
|
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|
+ simple-audio-card,frame-inversion;
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|
+
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|
+ simple-audio-card,codec {
|
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|
+ sound-dai = <&hdmi>;
|
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|
+ };
|
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|
+
|
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|
+ simple-audio-card,cpu {
|
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|
+ sound-dai = <&i2s2>;
|
||||||
|
+ dai-tdm-slot-num = <2>;
|
||||||
|
+ dai-tdm-slot-width = <32>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
thermal-zones {
|
||||||
|
cpu_thermal: cpu0-thermal {
|
||||||
|
/* milliseconds */
|
||||||
|
@@ -647,6 +665,19 @@ wdt: watchdog@1c20c90 {
|
||||||
|
clocks = <&osc24M>;
|
||||||
|
};
|
||||||
|
|
||||||
|
+ i2s2: i2s@1c22800 {
|
||||||
|
+ #sound-dai-cells = <0>;
|
||||||
|
+ compatible = "allwinner,sun8i-r40-i2s",
|
||||||
|
+ "allwinner,sun8i-h3-i2s";
|
||||||
|
+ reg = <0x01c22800 0x400>;
|
||||||
|
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
|
||||||
|
+ clock-names = "apb", "mod";
|
||||||
|
+ resets = <&ccu RST_BUS_I2S2>;
|
||||||
|
+ dmas = <&dma 6>, <&dma 6>;
|
||||||
|
+ dma-names = "rx", "tx";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
ir0: ir@1c21800 {
|
||||||
|
compatible = "allwinner,sun8i-r40-ir",
|
||||||
|
"allwinner,sun6i-a31-ir";
|
||||||
|
@@ -1134,6 +1165,7 @@ gic: interrupt-controller@1c81000 {
|
||||||
|
};
|
||||||
|
|
||||||
|
hdmi: hdmi@1ee0000 {
|
||||||
|
+ #sound-dai-cells = <0>;
|
||||||
|
compatible = "allwinner,sun8i-r40-dw-hdmi",
|
||||||
|
"allwinner,sun8i-a83t-dw-hdmi";
|
||||||
|
reg = <0x01ee0000 0x10000>;
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
@ -4724,7 +4724,7 @@ CONFIG_SUN4I_A10_CCU=y
|
|||||||
CONFIG_SUN8I_H3_CCU=y
|
CONFIG_SUN8I_H3_CCU=y
|
||||||
# CONFIG_SUN8I_V3S_CCU is not set
|
# CONFIG_SUN8I_V3S_CCU is not set
|
||||||
CONFIG_SUN8I_DE2_CCU=y
|
CONFIG_SUN8I_DE2_CCU=y
|
||||||
# CONFIG_SUN8I_R40_CCU is not set
|
CONFIG_SUN8I_R40_CCU=y
|
||||||
CONFIG_SUN8I_R_CCU=y
|
CONFIG_SUN8I_R_CCU=y
|
||||||
# CONFIG_HWSPINLOCK is not set
|
# CONFIG_HWSPINLOCK is not set
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,524 @@
|
|||||||
|
From 3658a2b7f3e16c7053eb8d70657b94bb62c5a0f4 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Mon, 24 Aug 2020 21:36:49 +0200
|
||||||
|
Subject: [PATCH] ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulator
|
||||||
|
|
||||||
|
DCDC1 regulator powers many different subsystems. While some of them can
|
||||||
|
work at 3.0 V, some of them can not. For example, VCC-HDMI can only work
|
||||||
|
between 3.24 V and 3.36 V. According to OS images provided by the board
|
||||||
|
manufacturer this regulator should be set to 3.3 V.
|
||||||
|
|
||||||
|
Set DCDC1 and DCDC1SW to 3.3 V in order to fix this.
|
||||||
|
|
||||||
|
Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra")
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200824193649.978197-1-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 10 +++++-----
|
||||||
|
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
||||||
|
index 42d62d1ba1dc..ea15073f0c79 100644
|
||||||
|
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
||||||
|
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
||||||
|
@@ -223,16 +223,16 @@ ®_aldo3 {
|
||||||
|
};
|
||||||
|
|
||||||
|
®_dc1sw {
|
||||||
|
- regulator-min-microvolt = <3000000>;
|
||||||
|
- regulator-max-microvolt = <3000000>;
|
||||||
|
+ regulator-min-microvolt = <3300000>;
|
||||||
|
+ regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-name = "vcc-gmac-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_dcdc1 {
|
||||||
|
regulator-always-on;
|
||||||
|
- regulator-min-microvolt = <3000000>;
|
||||||
|
- regulator-max-microvolt = <3000000>;
|
||||||
|
- regulator-name = "vcc-3v0";
|
||||||
|
+ regulator-min-microvolt = <3300000>;
|
||||||
|
+ regulator-max-microvolt = <3300000>;
|
||||||
|
+ regulator-name = "vcc-3v3";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_dcdc2 {
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 12bb1887be9dc8ca88fccd4da4d8d9eaae561239 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Mon, 24 Aug 2020 17:04:34 +0200
|
||||||
|
Subject: [PATCH] ARM: dts: sun8i: r40: Add Mali node
|
||||||
|
|
||||||
|
R40 has Mali400 GP2 GPU. Add a node for it.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200824150434.951693-3-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/sun8i-r40.dtsi | 22 ++++++++++++++++++++++
|
||||||
|
1 file changed, 22 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
index b782041e0e04..b82031b19893 100644
|
||||||
|
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
@@ -743,6 +743,28 @@ i2c4: i2c@1c2c000 {
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
+ mali: gpu@1c40000 {
|
||||||
|
+ compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
|
||||||
|
+ reg = <0x01c40000 0x10000>;
|
||||||
|
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ interrupt-names = "gp",
|
||||||
|
+ "gpmmu",
|
||||||
|
+ "pp0",
|
||||||
|
+ "ppmmu0",
|
||||||
|
+ "pp1",
|
||||||
|
+ "ppmmu1",
|
||||||
|
+ "pmu";
|
||||||
|
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
||||||
|
+ clock-names = "bus", "core";
|
||||||
|
+ resets = <&ccu RST_BUS_GPU>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
gmac: ethernet@1c50000 {
|
||||||
|
compatible = "allwinner,sun8i-r40-gmac";
|
||||||
|
syscon = <&ccu>;
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 2933bf3528007f834fb7f5eab033f9c5b0683f91 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Qiang Yu <yuq825@gmail.com>
|
||||||
|
Date: Sat, 22 Aug 2020 14:27:55 +0800
|
||||||
|
Subject: [PATCH] arm64: dts: allwinner: h5: remove Mali GPU PMU module
|
||||||
|
|
||||||
|
H5's Mali GPU PMU is not present or working corretly although
|
||||||
|
H5 datasheet record its interrupt vector.
|
||||||
|
|
||||||
|
Adding this module will miss lead lima driver try to shutdown
|
||||||
|
it and get waiting timeout. This problem is not exposed before
|
||||||
|
lima runtime PM support is added.
|
||||||
|
|
||||||
|
Fixes: bb39ed07e55b ("arm64: dts: allwinner: h5: Add device node for Mali-450 GPU")
|
||||||
|
Signed-off-by: Qiang Yu <yuq825@gmail.com>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200822062755.534761-1-yuq825@gmail.com
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 6 ++----
|
||||||
|
1 file changed, 2 insertions(+), 4 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
|
||||||
|
index 6735e316a39c..6c6053a18413 100644
|
||||||
|
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
|
||||||
|
@@ -139,8 +139,7 @@ mali: gpu@1e80000 {
|
||||||
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "gp",
|
||||||
|
"gpmmu",
|
||||||
|
"pp",
|
||||||
|
@@ -151,8 +150,7 @@ mali: gpu@1e80000 {
|
||||||
|
"pp2",
|
||||||
|
"ppmmu2",
|
||||||
|
"pp3",
|
||||||
|
- "ppmmu3",
|
||||||
|
- "pmu";
|
||||||
|
+ "ppmmu3";
|
||||||
|
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
||||||
|
clock-names = "bus", "core";
|
||||||
|
resets = <&ccu RST_BUS_GPU>;
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From a3ba99a24b36bc4eee5413a820e2c4f3d81593fa Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 25 Aug 2020 15:10:49 +0200
|
||||||
|
Subject: [PATCH] clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for
|
||||||
|
audio PLL
|
||||||
|
|
||||||
|
Audio cores need specific clock rates which can't be simply obtained by
|
||||||
|
adjusting integer multipliers and dividers. HW for such cases supports
|
||||||
|
delta-sigma modulation which enables fractional multipliers.
|
||||||
|
|
||||||
|
Port H3 delta-sigma table to R40. They have identical audio PLLs.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200825131049.1277596-1-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++++++++++++++++++----------
|
||||||
|
1 file changed, 24 insertions(+), 13 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
|
||||||
|
index 23bfe1d12f21..84153418453f 100644
|
||||||
|
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
|
||||||
|
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
|
||||||
|
@@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = {
|
||||||
|
* the base (2x, 4x and 8x), and one variable divider (the one true
|
||||||
|
* pll audio).
|
||||||
|
*
|
||||||
|
- * We don't have any need for the variable divider for now, so we just
|
||||||
|
- * hardcode it to match with the clock names
|
||||||
|
+ * With sigma-delta modulation for fractional-N on the audio PLL,
|
||||||
|
+ * we have to use specific dividers. This means the variable divider
|
||||||
|
+ * can no longer be used, as the audio codec requests the exact clock
|
||||||
|
+ * rates we support through this mechanism. So we now hard code the
|
||||||
|
+ * variable divider to 1. This means the clock rates will no longer
|
||||||
|
+ * match the clock names.
|
||||||
|
*/
|
||||||
|
#define SUN8I_R40_PLL_AUDIO_REG 0x008
|
||||||
|
|
||||||
|
-static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||||
|
- "osc24M", 0x008,
|
||||||
|
- 8, 7, /* N */
|
||||||
|
- 0, 5, /* M */
|
||||||
|
- BIT(31), /* gate */
|
||||||
|
- BIT(28), /* lock */
|
||||||
|
- CLK_SET_RATE_UNGATE);
|
||||||
|
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
||||||
|
+ { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
|
||||||
|
+ { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||||||
|
+ "osc24M", 0x008,
|
||||||
|
+ 8, 7, /* N */
|
||||||
|
+ 0, 5, /* M */
|
||||||
|
+ pll_audio_sdm_table, BIT(24),
|
||||||
|
+ 0x284, BIT(31),
|
||||||
|
+ BIT(31), /* gate */
|
||||||
|
+ BIT(28), /* lock */
|
||||||
|
+ CLK_SET_RATE_UNGATE);
|
||||||
|
|
||||||
|
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
|
||||||
|
"osc24M", 0x0010,
|
||||||
|
@@ -952,10 +963,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
|
||||||
|
&pll_audio_base_clk.common.hw
|
||||||
|
};
|
||||||
|
|
||||||
|
-/* We hardcode the divider to 4 for now */
|
||||||
|
+/* We hardcode the divider to 1 for now */
|
||||||
|
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
|
||||||
|
clk_parent_pll_audio,
|
||||||
|
- 4, 1, CLK_SET_RATE_PARENT);
|
||||||
|
+ 1, 1, CLK_SET_RATE_PARENT);
|
||||||
|
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
|
||||||
|
clk_parent_pll_audio,
|
||||||
|
2, 1, CLK_SET_RATE_PARENT);
|
||||||
|
@@ -1307,10 +1318,10 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
|
||||||
|
if (IS_ERR(reg))
|
||||||
|
return PTR_ERR(reg);
|
||||||
|
|
||||||
|
- /* Force the PLL-Audio-1x divider to 4 */
|
||||||
|
+ /* Force the PLL-Audio-1x divider to 1 */
|
||||||
|
val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||||
|
val &= ~GENMASK(19, 16);
|
||||||
|
- writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||||
|
+ writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
|
||||||
|
|
||||||
|
/* Force PLL-MIPI to MIPI mode */
|
||||||
|
val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 5822bfed6472340f882b43d5c2f2629091191c9d Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 25 Aug 2020 12:00:30 +0200
|
||||||
|
Subject: [PATCH] ARM: dts: sun8i: r40: Add DMA node
|
||||||
|
|
||||||
|
Allwinner R40 SoC has DMA with 16 channels and 31 request sources.
|
||||||
|
|
||||||
|
Add a node for it.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200825100030.1145356-3-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/sun8i-r40.dtsi | 12 ++++++++++++
|
||||||
|
1 file changed, 12 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
index b82031b19893..d481fe7989b8 100644
|
||||||
|
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
@@ -198,6 +198,18 @@ nmi_intc: interrupt-controller@1c00030 {
|
||||||
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
+ dma: dma-controller@1c02000 {
|
||||||
|
+ compatible = "allwinner,sun8i-r40-dma",
|
||||||
|
+ "allwinner,sun50i-a64-dma";
|
||||||
|
+ reg = <0x01c02000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_DMA>;
|
||||||
|
+ dma-channels = <16>;
|
||||||
|
+ dma-requests = <31>;
|
||||||
|
+ resets = <&ccu RST_BUS_DMA>;
|
||||||
|
+ #dma-cells = <1>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
spi0: spi@1c05000 {
|
||||||
|
compatible = "allwinner,sun8i-r40-spi",
|
||||||
|
"allwinner,sun8i-h3-spi";
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 166405e1f89acf7b24d95b90dbd1f78ec1ab3ec6 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 25 Aug 2020 19:13:57 +0200
|
||||||
|
Subject: [PATCH] ARM: dts: sun8i: r40: Add IR nodes
|
||||||
|
|
||||||
|
Allwinner R40 has two IR cores, add nodes for them.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200825171358.1286902-3-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++
|
||||||
|
1 file changed, 36 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
index d481fe7989b8..dff9a3dc1fba 100644
|
||||||
|
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
@@ -513,6 +513,16 @@ i2c4_pins: i2c4-pins {
|
||||||
|
function = "i2c4";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ ir0_pins: ir0-pins {
|
||||||
|
+ pins = "PB4";
|
||||||
|
+ function = "ir0";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ir1_pins: ir1-pins {
|
||||||
|
+ pins = "PB23";
|
||||||
|
+ function = "ir1";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
mmc0_pins: mmc0-pins {
|
||||||
|
pins = "PF0", "PF1", "PF2",
|
||||||
|
"PF3", "PF4", "PF5";
|
||||||
|
@@ -591,6 +601,32 @@ wdt: watchdog@1c20c90 {
|
||||||
|
clocks = <&osc24M>;
|
||||||
|
};
|
||||||
|
|
||||||
|
+ ir0: ir@1c21800 {
|
||||||
|
+ compatible = "allwinner,sun8i-r40-ir",
|
||||||
|
+ "allwinner,sun6i-a31-ir";
|
||||||
|
+ reg = <0x01c21800 0x400>;
|
||||||
|
+ pinctrl-0 = <&ir0_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
|
||||||
|
+ clock-names = "apb", "ir";
|
||||||
|
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ resets = <&ccu RST_BUS_IR0>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ir1: ir@1c21c00 {
|
||||||
|
+ compatible = "allwinner,sun8i-r40-ir",
|
||||||
|
+ "allwinner,sun6i-a31-ir";
|
||||||
|
+ reg = <0x01c21c00 0x400>;
|
||||||
|
+ pinctrl-0 = <&ir1_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
|
||||||
|
+ clock-names = "apb", "ir";
|
||||||
|
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ resets = <&ccu RST_BUS_IR1>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
ths: thermal-sensor@1c24c00 {
|
||||||
|
compatible = "allwinner,sun8i-r40-ths";
|
||||||
|
reg = <0x01c24c00 0x100>;
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 44406428f5764d7a71be3bafd642c8e02cdd5468 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 25 Aug 2020 19:13:58 +0200
|
||||||
|
Subject: [PATCH] ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable IR
|
||||||
|
|
||||||
|
BananaPi M2 Ultra has IR receiver connected to IR0.
|
||||||
|
|
||||||
|
Enable it.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200825171358.1286902-4-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 4 ++++
|
||||||
|
1 file changed, 4 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
||||||
|
index 42d62d1ba1dc..ca6088c87855 100644
|
||||||
|
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
||||||
|
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
||||||
|
@@ -164,6 +164,10 @@ axp22x: pmic@34 {
|
||||||
|
|
||||||
|
#include "axp22x.dtsi"
|
||||||
|
|
||||||
|
+&ir0 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&mmc0 {
|
||||||
|
vmmc-supply = <®_dcdc1>;
|
||||||
|
bus-width = <4>;
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 3566b0869179779d3abc4b605dcc9d2121d67672 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 25 Aug 2020 19:35:20 +0200
|
||||||
|
Subject: [PATCH] ARM: dts: sun8i: r40: Add node for system controller
|
||||||
|
|
||||||
|
Allwinner R40 has system controller and SRAM C1 region similar to that
|
||||||
|
in A10.
|
||||||
|
|
||||||
|
Add nodes for them.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200825173523.1289379-3-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++++++++++++++++++++++
|
||||||
|
1 file changed, 23 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
index dff9a3dc1fba..0c7526365896 100644
|
||||||
|
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
@@ -190,6 +190,29 @@ mixer1_out_tcon_top: endpoint {
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+ syscon: system-control@1c00000 {
|
||||||
|
+ compatible = "allwinner,sun8i-r40-system-control",
|
||||||
|
+ "allwinner,sun4i-a10-system-control";
|
||||||
|
+ reg = <0x01c00000 0x30>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ ranges;
|
||||||
|
+
|
||||||
|
+ sram_c: sram@1d00000 {
|
||||||
|
+ compatible = "mmio-sram";
|
||||||
|
+ reg = <0x01d00000 0xd0000>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ ranges = <0 0x01d00000 0xd0000>;
|
||||||
|
+
|
||||||
|
+ ve_sram: sram-section@0 {
|
||||||
|
+ compatible = "allwinner,sun8i-r40-sram-c1",
|
||||||
|
+ "allwinner,sun4i-a10-sram-c1";
|
||||||
|
+ reg = <0x000000 0x80000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
nmi_intc: interrupt-controller@1c00030 {
|
||||||
|
compatible = "allwinner,sun7i-a20-sc-nmi";
|
||||||
|
interrupt-controller;
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 343bbfd1652964fb52520c4cc232c5a2c679cb21 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 25 Aug 2020 19:35:22 +0200
|
||||||
|
Subject: [PATCH] media: cedrus: Add support for R40
|
||||||
|
|
||||||
|
Video engine in R40 is very similar to that in A33 but it runs on lower
|
||||||
|
speed, at least according to OS images released by board designer.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200825173523.1289379-5-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++++++++
|
||||||
|
1 file changed, 9 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
|
||||||
|
index bc27f9430eeb..83a654a618be 100644
|
||||||
|
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
|
||||||
|
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
|
||||||
|
@@ -496,6 +496,11 @@ static const struct cedrus_variant sun8i_h3_cedrus_variant = {
|
||||||
|
.mod_rate = 402000000,
|
||||||
|
};
|
||||||
|
|
||||||
|
+static const struct cedrus_variant sun8i_r40_cedrus_variant = {
|
||||||
|
+ .capabilities = CEDRUS_CAPABILITY_UNTILED,
|
||||||
|
+ .mod_rate = 297000000,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const struct cedrus_variant sun50i_a64_cedrus_variant = {
|
||||||
|
.capabilities = CEDRUS_CAPABILITY_UNTILED |
|
||||||
|
CEDRUS_CAPABILITY_H265_DEC,
|
||||||
|
@@ -536,6 +541,10 @@ static const struct of_device_id cedrus_dt_match[] = {
|
||||||
|
.compatible = "allwinner,sun8i-h3-video-engine",
|
||||||
|
.data = &sun8i_h3_cedrus_variant,
|
||||||
|
},
|
||||||
|
+ {
|
||||||
|
+ .compatible = "allwinner,sun8i-r40-video-engine",
|
||||||
|
+ .data = &sun8i_r40_cedrus_variant,
|
||||||
|
+ },
|
||||||
|
{
|
||||||
|
.compatible = "allwinner,sun50i-a64-video-engine",
|
||||||
|
.data = &sun50i_a64_cedrus_variant,
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
|
From 2abed6778f38e2cfb90806994dff01de00ca77a6 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 25 Aug 2020 19:35:23 +0200
|
||||||
|
Subject: [PATCH] ARM: dts: sun8i: r40: Add video engine node
|
||||||
|
|
||||||
|
Allwinner R40 SoC has a video engine.
|
||||||
|
|
||||||
|
Add a node for it.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
||||||
|
Link: https://lore.kernel.org/r/20200825173523.1289379-6-jernej.skrabec@siol.net
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/sun8i-r40.dtsi | 11 +++++++++++
|
||||||
|
1 file changed, 11 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
index 0c7526365896..7907569e7b5c 100644
|
||||||
|
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||||
|
@@ -273,6 +273,17 @@ csi0: csi@1c09000 {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ video-codec@1c0e000 {
|
||||||
|
+ compatible = "allwinner,sun8i-r40-video-engine";
|
||||||
|
+ reg = <0x01c0e000 0x1000>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
|
||||||
|
+ <&ccu CLK_DRAM_VE>;
|
||||||
|
+ clock-names = "ahb", "mod", "ram";
|
||||||
|
+ resets = <&ccu RST_BUS_VE>;
|
||||||
|
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ allwinner,sram = <&ve_sram 1>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
mmc0: mmc@1c0f000 {
|
||||||
|
compatible = "allwinner,sun8i-r40-mmc",
|
||||||
|
"allwinner,sun50i-a64-mmc";
|
||||||
|
--
|
||||||
|
2.28.0
|
||||||
|
|
||||||
@ -165,7 +165,7 @@ index 43643ad31730..d840bc07cba6 100644
|
|||||||
- regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
|
- regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
|
||||||
+ /* manual control of CEC pins */
|
+ /* manual control of CEC pins */
|
||||||
+ regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG,
|
+ regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG,
|
||||||
+ SUN8I_HDMI_PHY_CEC_PIN_CTRL);
|
+ phy->variant->bit_bang_cec ? SUN8I_HDMI_PHY_CEC_PIN_CTRL : 0);
|
||||||
|
|
||||||
/* read calibration data */
|
/* read calibration data */
|
||||||
regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
|
regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
|
||||||
@ -227,14 +227,6 @@ index 43643ad31730..d840bc07cba6 100644
|
|||||||
.has_phy_clk = true,
|
.has_phy_clk = true,
|
||||||
.is_custom_phy = true,
|
.is_custom_phy = true,
|
||||||
.phy_init = &sun8i_hdmi_phy_init_h3,
|
.phy_init = &sun8i_hdmi_phy_init_h3,
|
||||||
@@ -557,6 +600,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
|
|
||||||
+ .bit_bang_cec = true,
|
|
||||||
.has_phy_clk = true,
|
|
||||||
.has_second_pll = true,
|
|
||||||
.is_custom_phy = true,
|
|
||||||
@@ -566,6 +610,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
|
@@ -566,6 +610,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user