From 848c5b5024b61feebbb555af7f142270f4490081 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Sun, 26 Jan 2025 14:26:41 +0000 Subject: [PATCH] linux (Rockchip): drop upstream patches in 6.13 --- .../default/linux-1000-drm-rockchip.patch | 454 ------------------ 1 file changed, 454 deletions(-) diff --git a/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch index 806fc88354..8314867faf 100644 --- a/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch @@ -200,326 +200,6 @@ index 9f7326c5b1f5..30e252ba7184 100644 * Clock craziness. * -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Yakir Yang -Date: Mon, 11 Jul 2016 19:05:39 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: adjust cklvl & txlvl for RF/EMI - -Dut to the high HDMI signal voltage driver, Mickey have meet -a serious RF/EMI problem, so we decided to reduce HDMI signal -voltage to a proper value. - -The default params for phy is cklvl = 20 & txlvl = 13 (RF/EMI failed) - ck: lvl = 13, term=100, vlo = 2.71, vhi=3.14, vswing = 0.43 - tx: lvl = 20, term=100, vlo = 2.81, vhi=3.16, vswing = 0.35 - -1. We decided to reduce voltage value to lower, but VSwing still -keep high, RF/EMI have been improved but still failed. - ck: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50 - tx: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50 - -2. We try to keep voltage value and vswing both lower, then RF/EMI -test all passed ;) - ck: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40 - tx: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40 -When we back to run HDMI different test and single-end test, we see -different test passed, but signle-end test failed. The oscilloscope -show that simgle-end clock's VL value is 1.78v (which remind LowLimit -should not lower then 2.6v). - -3. That's to say there are some different between PHY document and -measure value. And according to experiment 2 results, we need to -higher clock voltage and lower data voltage, then we can keep RF/EMI -satisfied and single-end & differen test passed. - ck: lvl = 9, term=100, vlo = 2.65, vhi=3.12, vswing = 0.47 - tx: lvl = 16, term=100, vlo = 2.75, vhi=3.15, vswing = 0.39 - -Signed-off-by: Yakir Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index c14f88893868..4411ca8fd7ed 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -201,7 +201,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - static const struct dw_hdmi_phy_config rockchip_phy_config[] = { - /*pixelclk symbol term vlev*/ - { 74250000, 0x8009, 0x0004, 0x0272}, -- { 148500000, 0x802b, 0x0004, 0x028d}, -+ { 165000000, 0x802b, 0x0004, 0x0209}, - { 297000000, 0x8039, 0x0005, 0x028d}, - { ~0UL, 0x0000, 0x0000, 0x0000} - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nickey Yang -Date: Mon, 13 Feb 2017 15:40:29 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: add phy_config for 594Mhz pixel clock - -Add phy_config for 594Mhz pixel clock used for 4K@60hz - -Signed-off-by: Nickey Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 4411ca8fd7ed..bec381cde0bc 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -203,6 +203,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { - { 74250000, 0x8009, 0x0004, 0x0272}, - { 165000000, 0x802b, 0x0004, 0x0209}, - { 297000000, 0x8039, 0x0005, 0x028d}, -+ { 594000000, 0x8039, 0x0000, 0x019d}, - { ~0UL, 0x0000, 0x0000, 0x0000} - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Mon, 11 Jul 2016 19:05:36 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always - -Jitter was improved by lowering the MPLL bandwidth to account for high -frequency noise in the rk3288 PLL. In each case MPLL bandwidth was -lowered only enough to get us a comfortable margin. We believe that -lowering the bandwidth like this is safe given sufficient testing. - -Signed-off-by: Douglas Anderson -Signed-off-by: Yakir Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++-------------- - 1 file changed, 2 insertions(+), 14 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index bec381cde0bc..72c1d65c7b75 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -178,20 +178,6 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - /* pixelclk bpp8 bpp10 bpp12 */ - { -- 40000000, { 0x0018, 0x0018, 0x0018 }, -- }, { -- 65000000, { 0x0028, 0x0028, 0x0028 }, -- }, { -- 66000000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 74250000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 83500000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 146250000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 148500000, { 0x0000, 0x0038, 0x0038 }, -- }, { - 600000000, { 0x0000, 0x0000, 0x0000 }, - }, { - ~0UL, { 0x0000, 0x0000, 0x0000}, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Mon, 11 Jul 2016 19:05:42 +0800 -Subject: [PATCH] drm/rockchip: dw_hdmi: Use auto-generated tables - -The previous tables for mpll_cfg and curr_ctrl were created using the -20-pages of example settings provided by the PHY vendor. Those -example settings weren't particularly dense, so there were places -where we were guessing what the settings would be for 10-bit and -12-bit (not that we use those anyway). It was also always a lot of -extra work every time we wanted to add a new clock rate since we had -to cross-reference several tables. - -In I've gone through the work to figure -out how to generate this table automatically. Let's now use the -automatically generated table and then we'll never need to look at it -again. - -We only support 8-bit mode right now and only support a small number -of clock rates and and I've verified that the only 8-bit rate that was -affected was 148.5. That mode appears to have been wrong in the old -table. - -Signed-off-by: Douglas Anderson -Signed-off-by: Yakir Yang -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++--------- - 1 file changed, 69 insertions(+), 61 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 72c1d65c7b75..0370bb247fcb 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -91,86 +91,88 @@ - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -- 27000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 36000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 40000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -- }, -- }, { -- 54000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 65000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 66000000, { -- { 0x013e, 0x0003}, -- { 0x217e, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 74250000, { -- { 0x0072, 0x0001}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 83500000, { -- { 0x0072, 0x0001}, -- }, -- }, { -- 108000000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 106500000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 146250000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 148500000, { -- { 0x0051, 0x0003}, -- { 0x214c, 0x0003}, -- { 0x4064, 0x0003} -+ 30666000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40f3, 0x0000 }, -+ }, -+ }, { -+ 36800000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 46000000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 61333000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, -+ }, -+ }, { -+ 73600000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 92000000, { -+ { 0x0072, 0x0001 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 122666000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, -+ }, -+ }, { -+ 147200000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4064, 0x0003 }, -+ }, -+ }, { -+ 184000000, { -+ { 0x0051, 0x0002 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, - }, -- }, { -+ }, { -+ 226666000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, -+ }, -+ }, { -+ 272000000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { - 340000000, { - { 0x0040, 0x0003 }, - { 0x3b4c, 0x0003 }, - { 0x5a64, 0x0003 }, - }, -- }, { -+ }, { -+ 600000000, { -+ { 0x1a40, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { - ~0UL, { -- { 0x00a0, 0x000a }, -- { 0x2001, 0x000f }, -- { 0x4002, 0x000f }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, - }, - } - }; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 10 Oct 2020 10:16:32 +0000 @@ -2835,137 +2515,3 @@ index 49619f794061..9915bf124374 100644 port = of_get_child_by_name(dev->of_node, "port"); -From 3303a206ae7474b2f8a5d17d8df9de08bac16ca5 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 8 Sep 2024 14:54:58 +0000 -Subject: [PATCH] drm/rockchip: dw_hdmi: Filter modes based on hdmiphy_clk - -RK3228 and RK3328 clock rate is being validated against a mpll config -table intended for a Synopsys phy, and not the used inno-hdmi-phy. - -Instead get a reference to the hdmiphy clk and validate rates against -it to enable use of HDMI2.0 modes, e.g. 4K@60Hz, on RK3228 and RK3328. - -For Synopsis phy the max_tmds_clock validation is sufficient. - -Signed-off-by: Jonas Karlman -Tested-by: Diederik de Haas # Rock64 -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20240908145511.3331451-2-jonas@kwiboo.se ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 35 ++++++++++----------- - 1 file changed, 17 insertions(+), 18 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 240552eb517f7e..36cc700766fd82 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -76,6 +76,7 @@ struct rockchip_hdmi { - struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; - const struct dw_hdmi_plat_data *plat_data; -+ struct clk *hdmiphy_clk; - struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; -@@ -251,10 +252,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, - const struct drm_display_mode *mode) - { - struct rockchip_hdmi *hdmi = data; -- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; - int pclk = mode->clock * 1000; -- bool exact_match = hdmi->plat_data->phy_force_vendor; -- int i; - - if (hdmi->chip_data->max_tmds_clock && - mode->clock > hdmi->chip_data->max_tmds_clock) -@@ -263,26 +261,18 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, - if (hdmi->ref_clk) { - int rpclk = clk_round_rate(hdmi->ref_clk, pclk); - -- if (abs(rpclk - pclk) > pclk / 1000) -+ if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000) - return MODE_NOCLOCK; - } - -- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { -- /* -- * For vendor specific phys force an exact match of the pixelclock -- * to preserve the original behaviour of the driver. -- */ -- if (exact_match && pclk == mpll_cfg[i].mpixelclock) -- return MODE_OK; -- /* -- * The Synopsys phy can work with pixelclocks up to the value given -- * in the corresponding mpll_cfg entry. -- */ -- if (!exact_match && pclk <= mpll_cfg[i].mpixelclock) -- return MODE_OK; -+ if (hdmi->hdmiphy_clk) { -+ int rpclk = clk_round_rate(hdmi->hdmiphy_clk, pclk); -+ -+ if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000) -+ return MODE_NOCLOCK; - } - -- return MODE_BAD; -+ return MODE_OK; - } - - static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) -@@ -607,6 +597,15 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -+ if (hdmi->phy) { -+ struct of_phandle_args clkspec; -+ -+ clkspec.np = hdmi->phy->dev.of_node; -+ hdmi->hdmiphy_clk = of_clk_get_from_provider(&clkspec); -+ if (IS_ERR(hdmi->hdmiphy_clk)) -+ hdmi->hdmiphy_clk = NULL; -+ } -+ - if (hdmi->chip_data == &rk3568_chip_data) { - regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, - HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | - -From 28f0ae48e7fdbd6cdcf3972c8d8686a529ae1ede Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 8 Sep 2024 14:55:03 +0000 -Subject: [PATCH] drm/rockchip: dw_hdmi: Enable 4K@60Hz mode on RK3399 and - RK356x - -Use a maximum TMDS clock rate limit of 594MHz to enable use of HDMI2.0 -modes, e.g. 4K@60Hz, on RK3399 and RK3568. - -Signed-off-by: Jonas Karlman -Tested-by: Diederik de Haas # Quartz64 Model B -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20240908145511.3331451-7-jonas@kwiboo.se ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 090d8c0f306f55..96e1097f993dc1 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -481,7 +481,7 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { - .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, - .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL), - .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL), -- .max_tmds_clock = 340000, -+ .max_tmds_clock = 594000, - }; - - static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { -@@ -495,7 +495,7 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { - - static struct rockchip_hdmi_chip_data rk3568_chip_data = { - .lcdsel_grf_reg = -1, -- .max_tmds_clock = 340000, -+ .max_tmds_clock = 594000, - }; - - static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {