diff --git a/projects/RPi/patches/linux/linux-01-RPi_support-4b3694f.patch b/projects/RPi/patches/linux/linux-01-RPi_support.patch similarity index 98% rename from projects/RPi/patches/linux/linux-01-RPi_support-4b3694f.patch rename to projects/RPi/patches/linux/linux-01-RPi_support.patch index 284fcd50fb..3822310127 100644 --- a/projects/RPi/patches/linux/linux-01-RPi_support-4b3694f.patch +++ b/projects/RPi/patches/linux/linux-01-RPi_support.patch @@ -1,7 +1,7 @@ -From 08a5ef637c08da1a7051ff5ed34ee8fa1da9b6a2 Mon Sep 17 00:00:00 2001 +From da300e34085f2060a181117b41321b4ee0db8620 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 12 May 2013 12:24:19 +0100 -Subject: [PATCH 001/110] Main bcm2708 linux port +Subject: [PATCH 001/101] Main bcm2708 linux port Signed-off-by: popcornmix --- @@ -33,7 +33,7 @@ Signed-off-by: popcornmix arch/arm/mach-bcm2708/include/mach/gpio.h | 17 + arch/arm/mach-bcm2708/include/mach/hardware.h | 28 + arch/arm/mach-bcm2708/include/mach/io.h | 27 + - arch/arm/mach-bcm2708/include/mach/irqs.h | 196 +++ + arch/arm/mach-bcm2708/include/mach/irqs.h | 194 +++ arch/arm/mach-bcm2708/include/mach/memory.h | 57 + arch/arm/mach-bcm2708/include/mach/platform.h | 220 ++++ arch/arm/mach-bcm2708/include/mach/power.h | 26 + @@ -56,7 +56,7 @@ Signed-off-by: popcornmix drivers/mmc/host/sdhci.h | 37 + drivers/tty/serial/amba-pl011.c | 2 +- include/linux/mmc/sdhci.h | 2 + - 51 files changed, 7791 insertions(+), 72 deletions(-) + 51 files changed, 7789 insertions(+), 72 deletions(-) create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig create mode 100644 arch/arm/configs/bcmrpi_defconfig create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig @@ -2806,7 +2806,7 @@ index 0000000..e339a93 +#endif diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c new file mode 100644 -index 0000000..bab8a49 +index 0000000..120929ff --- /dev/null +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c @@ -0,0 +1,361 @@ @@ -2884,7 +2884,7 @@ index 0000000..bab8a49 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; + +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); -+ if (offset >= ARCH_NR_GPIOS) ++ if (offset >= BCM2708_NR_GPIOS) + return -EINVAL; + + spin_lock_irqsave(&lock, flags); @@ -2922,7 +2922,7 @@ index 0000000..bab8a49 + unsigned gpio_field_offset = (offset - 32 * gpio_bank); + unsigned lev; + -+ if (offset >= ARCH_NR_GPIOS) ++ if (offset >= BCM2708_NR_GPIOS) + return 0; + lev = readl(gpio->base + GPIOLEV(gpio_bank)); +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); @@ -2935,7 +2935,7 @@ index 0000000..bab8a49 + unsigned gpio_bank = offset / 32; + unsigned gpio_field_offset = (offset - 32 * gpio_bank); +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); -+ if (offset >= ARCH_NR_GPIOS) ++ if (offset >= BCM2708_NR_GPIOS) + return; + if (value) + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); @@ -3114,7 +3114,7 @@ index 0000000..bab8a49 + + ucb->gc.label = "bcm2708_gpio"; + ucb->gc.base = 0; -+ ucb->gc.ngpio = ARCH_NR_GPIOS; ++ ucb->gc.ngpio = BCM2708_NR_GPIOS; + ucb->gc.owner = THIS_MODULE; + + ucb->gc.direction_input = bcm2708_gpio_dir_in; @@ -4418,7 +4418,7 @@ index 0000000..dd51e07 +#endif diff --git a/arch/arm/mach-bcm2708/include/mach/gpio.h b/arch/arm/mach-bcm2708/include/mach/gpio.h new file mode 100644 -index 0000000..753dc06 +index 0000000..7965a97 --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/gpio.h @@ -0,0 +1,17 @@ @@ -4433,7 +4433,7 @@ index 0000000..753dc06 +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + -+#define ARCH_NR_GPIOS 54 // number of gpio lines ++#define BCM2708_NR_GPIOS 54 // number of gpio lines + +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) @@ -4508,10 +4508,10 @@ index 0000000..e6eb84d +#endif diff --git a/arch/arm/mach-bcm2708/include/mach/irqs.h b/arch/arm/mach-bcm2708/include/mach/irqs.h new file mode 100644 -index 0000000..e8bb068 +index 0000000..faf5d1a --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h -@@ -0,0 +1,196 @@ +@@ -0,0 +1,194 @@ +/* + * arch/arm/mach-bcm2708/include/mach/irqs.h + * @@ -4700,12 +4700,10 @@ index 0000000..e8bb068 +#define FIQ_PENDING2 INT_PENDING2 + +#define HARD_IRQS (64 + 21) -+#define GPIO_IRQ_START HARD_IRQS -+ -+#define GPIO_IRQS 32*5 -+ -+#define NR_IRQS HARD_IRQS+GPIO_IRQS -+ ++#define GPIO_IRQ_START (HARD_IRQS) ++#define GPIO_IRQS (32*5) ++#define SPARE_IRQS (64) ++#define NR_IRQS (HARD_IRQS+GPIO_IRQS+SPARE_IRQS) + +#endif /* _BCM2708_IRQS_H_ */ diff --git a/arch/arm/mach-bcm2708/include/mach/memory.h b/arch/arm/mach-bcm2708/include/mach/memory.h @@ -8593,10 +8591,10 @@ index 362927c4..e23fffb 100644 1.9.1 -From f60a50640d06bb8f93d2dcebaccd9c68743b58e6 Mon Sep 17 00:00:00 2001 +From 629cada1cc7e9408b1a5a0a3ee86ace70c2a96e2 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 7 May 2013 22:20:24 +0100 -Subject: [PATCH 002/110] Add quick config. +Subject: [PATCH 002/101] Add quick config. This is designed for quick compiling when developing. No modules are needed and it includes all Pi specific drivers @@ -8812,10 +8810,10 @@ index 0000000..e5efe75 1.9.1 -From cfc03c6cb10e7bd0113e746217eb199d7b6d9b8d Mon Sep 17 00:00:00 2001 +From f27b7966ca9272014026c8b4dc4448cc044ee371 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:46:17 +0100 -Subject: [PATCH 003/110] Add dwc_otg driver +Subject: [PATCH 003/101] Add dwc_otg driver Signed-off-by: popcornmix --- @@ -65887,10 +65885,10 @@ index 0000000..cdc9963 1.9.1 -From 7734cb5e3a32e567ade48d067a6802898ffdf68b Mon Sep 17 00:00:00 2001 +From 3ec8918c38408c8b4f98e618c47e82fd01600c79 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:54:32 +0100 -Subject: [PATCH 004/110] bcm2708 watchdog driver +Subject: [PATCH 004/101] bcm2708 watchdog driver Signed-off-by: popcornmix --- @@ -66323,10 +66321,10 @@ index 0000000..2f19203 1.9.1 -From 40af82b762b54b620181a75636755bc472c2dc9d Mon Sep 17 00:00:00 2001 +From 3b40e80a5a9cea0ed3240bc9b4b98423db9e2c62 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:55:09 +0100 -Subject: [PATCH 005/110] bcm2708 framebuffer driver +Subject: [PATCH 005/101] bcm2708 framebuffer driver Signed-off-by: popcornmix --- @@ -69373,10 +69371,10 @@ index 3c14e43..7626beb 100644 1.9.1 -From 79c6ee6e0b4d60db199bf1701cbadae32a34571a Mon Sep 17 00:00:00 2001 +From a12e66ad3f5de7fd6dbd48bd0c2f9e37ee719984 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 2 Jul 2013 23:42:01 +0100 -Subject: [PATCH 006/110] bcm2708 vchiq driver +Subject: [PATCH 006/101] bcm2708 vchiq driver Signed-off-by: popcornmix @@ -81927,10 +81925,10 @@ index 0000000..b6bfa21 1.9.1 -From 580927bbe5116aa345c6040b0a6cdab6da53be41 Mon Sep 17 00:00:00 2001 +From 1837642b00389488170bcf3e0de827dbf0593d1c Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:31:47 +0100 -Subject: [PATCH 007/110] cma: Add vc_cma driver to enable use of CMA +Subject: [PATCH 007/101] cma: Add vc_cma driver to enable use of CMA Signed-off-by: popcornmix --- @@ -83221,10 +83219,10 @@ index 0000000..5325832 1.9.1 -From c67803d14570ca5ea3cf69fca8595ce78b50284e Mon Sep 17 00:00:00 2001 +From 7bbbb963c27a1941a8c5ca034a42255418ecdd88 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 26 Mar 2012 22:15:50 +0100 -Subject: [PATCH 008/110] bcm2708: alsa sound driver +Subject: [PATCH 008/101] bcm2708: alsa sound driver Signed-off-by: popcornmix --- @@ -83619,7 +83617,7 @@ index 0000000..8c5334a +} diff --git a/sound/arm/bcm2835-pcm.c b/sound/arm/bcm2835-pcm.c new file mode 100755 -index 0000000..b5435fb +index 0000000..2e7d405 --- /dev/null +++ b/sound/arm/bcm2835-pcm.c @@ -0,0 +1,409 @@ @@ -83760,6 +83758,11 @@ index 0000000..b5435fb + alsa_stream->enable_fifo_irq = 0; + alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq; + ++ err = bcm2835_audio_open(alsa_stream); ++ if (err != 0) { ++ kfree(alsa_stream); ++ return err; ++ } + runtime->private_data = alsa_stream; + runtime->private_free = snd_bcm2835_playback_free; + runtime->hw = snd_bcm2835_playback_hw; @@ -83767,11 +83770,6 @@ index 0000000..b5435fb + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, + 16); + -+ err = bcm2835_audio_open(alsa_stream); -+ if (err != 0) { -+ kfree(alsa_stream); -+ return err; -+ } + chip->alsa_stream[idx] = alsa_stream; + + alsa_stream->open = 1; @@ -85588,10 +85586,10 @@ index 0000000..af3e6eb 1.9.1 -From eed75fd62cc463d81ea517eb26f9ec57b622e316 Mon Sep 17 00:00:00 2001 +From 6dfd897dc1ce769119f88503eca2fd6ff97288a8 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 26 Apr 2013 10:08:31 -0700 -Subject: [PATCH 009/110] Merge pull request #286 from +Subject: [PATCH 009/101] Merge pull request #286 from martinezjavier/rpi-3.6.y-dev add mmap support and some cleanups to bcm2835 ALSA driver @@ -85603,7 +85601,7 @@ add mmap support and some cleanups to bcm2835 ALSA driver 4 files changed, 124 insertions(+), 70 deletions(-) diff --git a/sound/arm/bcm2835-pcm.c b/sound/arm/bcm2835-pcm.c -index b5435fb..7f6d75e 100755 +index 2e7d405..b4084bb 100755 --- a/sound/arm/bcm2835-pcm.c +++ b/sound/arm/bcm2835-pcm.c @@ -19,7 +19,8 @@ @@ -86072,10 +86070,10 @@ index 080bd5c..36afee3 100755 1.9.1 -From 673c36c214d15cd30c9aa8ae75f47c369a045091 Mon Sep 17 00:00:00 2001 +From e9594340a70240f071daf1cd600e08c7208e693e Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:51:55 +0100 -Subject: [PATCH 010/110] Add hwrng (hardware random number generator) driver +Subject: [PATCH 010/101] Add hwrng (hardware random number generator) driver --- arch/arm/mach-bcm2708/include/mach/platform.h | 1 + @@ -86256,10 +86254,10 @@ index 0000000..1ffa7d7 1.9.1 -From 7d24c7cfecc88d01af66719e211f1b9edc272559 Mon Sep 17 00:00:00 2001 +From 335e99d01b8baefdfc4a6e3fa15d6079ea3d4aca Mon Sep 17 00:00:00 2001 From: Aron Szabo Date: Sat, 16 Jun 2012 12:15:55 +0200 -Subject: [PATCH 011/110] lirc: added support for RaspberryPi GPIO +Subject: [PATCH 011/101] lirc: added support for RaspberryPi GPIO --- drivers/staging/media/lirc/Kconfig | 6 + @@ -87000,10 +86998,10 @@ index 0000000..8aee83f 1.9.1 -From 9d38941b1565b436bf5de2e6de99212a285dcabd Mon Sep 17 00:00:00 2001 +From 34ac600e35376dcee117f2d79851223b56a3640c Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 8 May 2012 23:12:13 +0100 -Subject: [PATCH 012/110] Fixes for sdhci-bcm2708 +Subject: [PATCH 012/101] Fixes for sdhci-bcm2708 possible fix for sdcard missing status. Thank naren @@ -88277,10 +88275,10 @@ index e23fffb..b1b6537 100644 1.9.1 -From 9caaecc681b0aa2db81e896b5aa86619d4efdf6b Mon Sep 17 00:00:00 2001 +From 9c11799639037ce87e60d48c5c146c68e6289aab Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:49:20 +0100 -Subject: [PATCH 013/110] Add cpufreq driver +Subject: [PATCH 013/101] Add cpufreq driver --- arch/arm/Kconfig | 1 + @@ -88582,10 +88580,10 @@ index 0000000..7bc55bd 1.9.1 -From b4cdc2917006da38ae182d9202117a4b7404b967 Mon Sep 17 00:00:00 2001 +From 005924e34d5a59b9fe02c89bb31f7e3ec5bc779c Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 19:24:24 +0000 -Subject: [PATCH 014/110] Added hwmon/thermal driver for reporting core +Subject: [PATCH 014/101] Added hwmon/thermal driver for reporting core temperature. Thanks Dorian --- @@ -89110,10 +89108,10 @@ index 0000000..85fceb5 1.9.1 -From c8693b7ca9fde98cfd3dd1046442e499428d9975 Mon Sep 17 00:00:00 2001 +From 34d97daa8bba1cce1b775c6bee3b7d9b0c38d6d8 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 17:26:38 +0000 -Subject: [PATCH 015/110] Allow mac address to be set in smsc95xx +Subject: [PATCH 015/101] Allow mac address to be set in smsc95xx Signed-off-by: popcornmix --- @@ -89207,10 +89205,10 @@ index 424db65e..fc1ef4e 100644 1.9.1 -From 47cd5e75af8d496251a33783b1e6a43c0ea76eea Mon Sep 17 00:00:00 2001 +From 14ebfade47ca20518b2bc473ce8c11c9a0de5310 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 4 Nov 2013 18:56:10 +0000 -Subject: [PATCH 016/110] Add Chris Boot's i2c and spi drivers. +Subject: [PATCH 016/101] Add Chris Boot's i2c and spi drivers. --- arch/arm/configs/bcmrpi_cutdown_defconfig | 9 + @@ -90575,10 +90573,10 @@ index 0000000..180264a 1.9.1 -From ff41fa27a2f855287a252fd217f999477cd3ce72 Mon Sep 17 00:00:00 2001 +From 82b546ca74249907295399826627d4f2ed477bd8 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 8 May 2013 11:46:50 +0100 -Subject: [PATCH 017/110] enabling the realtime clock 1-wire chip DS1307 and +Subject: [PATCH 017/101] enabling the realtime clock 1-wire chip DS1307 and 1-wire on GPIO4 (as a module) 1-wire: Add support for configuring pin for w1-gpio kernel module @@ -90781,10 +90779,10 @@ index e10acc2..667fdd5 100644 1.9.1 -From fde654d01524afd98860bf640104e44eeaf530cc Mon Sep 17 00:00:00 2001 +From 2b0dce510fae400a8928494a8130a607abe9bf86 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:46:42 +0100 -Subject: [PATCH 018/110] Add FIQ patch to dwc_otg driver. Enable with +Subject: [PATCH 018/101] Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance. Thanks to Gordon and Costas @@ -90793,9 +90791,9 @@ Subject: [PATCH 018/110] Add FIQ patch to dwc_otg driver. Enable with arch/arm/include/asm/fiq.h | 1 + arch/arm/kernel/fiq.c | 1 + arch/arm/kernel/fiqasm.S | 7 ++ - arch/arm/mach-bcm2708/armctrl.c | 19 ++- + arch/arm/mach-bcm2708/armctrl.c | 19 +++- arch/arm/mach-bcm2708/bcm2708.c | 29 ++++- - arch/arm/mach-bcm2708/include/mach/irqs.h | 159 +++++++++++++------------- + arch/arm/mach-bcm2708/include/mach/irqs.h | 155 +++++++++++++------------- arch/arm/mach-bcm2708/include/mach/platform.h | 2 + drivers/usb/host/dwc_otg/Makefile | 1 + drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 14 ++- @@ -90807,10 +90805,10 @@ Subject: [PATCH 018/110] Add FIQ patch to dwc_otg driver. Enable with drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 154 ++++++++++++++++++++++--- drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 45 ++++++++ drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 20 +++- - drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c | 113 ++++++++++++++++++ + drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c | 113 +++++++++++++++++++ drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h | 36 ++++++ drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 3 + - 21 files changed, 545 insertions(+), 110 deletions(-) + 21 files changed, 543 insertions(+), 108 deletions(-) create mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c create mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h @@ -90967,10 +90965,10 @@ index d315c19..2b11e9d 100644 bcm_register_device(&bcm2708_uart1_device); bcm_register_device(&bcm2708_powerman_device); diff --git a/arch/arm/mach-bcm2708/include/mach/irqs.h b/arch/arm/mach-bcm2708/include/mach/irqs.h -index e8bb068..9aaedf1 100644 +index faf5d1a..4299054 100644 --- a/arch/arm/mach-bcm2708/include/mach/irqs.h +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h -@@ -106,91 +106,94 @@ +@@ -106,89 +106,92 @@ #define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) #define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) @@ -91129,18 +91127,14 @@ index e8bb068..9aaedf1 100644 +#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) +#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) --#define HARD_IRQS (64 + 21) --#define GPIO_IRQ_START HARD_IRQS -+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) - --#define GPIO_IRQS 32*5 -+#define HARD_IRQS (64 + 21) -+#define FIQ_IRQS (64 + 21) -+#define GPIO_IRQS (32*5) - --#define NR_IRQS HARD_IRQS+GPIO_IRQS -+#define NR_IRQS HARD_IRQS+FIQ_IRQS+GPIO_IRQS - + #define HARD_IRQS (64 + 21) +-#define GPIO_IRQ_START (HARD_IRQS) ++#define FIQ_IRQS (64 + 21) ++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) + #define GPIO_IRQS (32*5) + #define SPARE_IRQS (64) +-#define NR_IRQS (HARD_IRQS+GPIO_IRQS+SPARE_IRQS) ++#define NR_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_IRQS) #endif /* _BCM2708_IRQS_H_ */ diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h @@ -91944,10 +91938,10 @@ index e46d9bb..6b2c7d0 100644 1.9.1 -From 8322f0247034a47891c6863fabae27e93acb3c3f Mon Sep 17 00:00:00 2001 +From 8fc4c133c0774cb3e18ac3db071b84f05e3e6887 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sat, 8 Sep 2012 15:17:53 +0100 -Subject: [PATCH 021/110] Avoid dynamic memory allocation for channel lock in +Subject: [PATCH 021/101] Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005. --- @@ -92054,17 +92048,17 @@ index b7b6b0c..76b5085 100644 1.9.1 -From ae7b6c14dd2f698f9db80e7c8630f975a0400333 Mon Sep 17 00:00:00 2001 +From 12360e62628015e8fe57a504ac9e52404878348a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 12 Apr 2013 23:58:47 +0100 -Subject: [PATCH 022/110] config: add missing options from 3.6.y kernel +Subject: [PATCH 022/101] config: add missing options from 3.6.y kernel --- - arch/arm/configs/bcmrpi_defconfig | 748 ++++++++++++++++++++++++++++++++------ - 1 file changed, 643 insertions(+), 105 deletions(-) + arch/arm/configs/bcmrpi_defconfig | 749 ++++++++++++++++++++++++++++++++------ + 1 file changed, 644 insertions(+), 105 deletions(-) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 31f5afaa..88692be 100644 +index 31f5afaa..bbf3000 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig @@ -1,11 +1,17 @@ @@ -92431,7 +92425,7 @@ index 31f5afaa..88692be 100644 CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m -@@ -89,35 +366,102 @@ CONFIG_BT_HCIVHCI=m +@@ -89,35 +366,103 @@ CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m @@ -92535,6 +92529,7 @@ index 31f5afaa..88692be 100644 +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m @@ -92542,7 +92537,7 @@ index 31f5afaa..88692be 100644 CONFIG_LIBERTAS_THINFIRM=m CONFIG_LIBERTAS_THINFIRM_USB=m CONFIG_AT76C50X_USB=m -@@ -125,14 +469,17 @@ CONFIG_USB_ZD1201=m +@@ -125,14 +470,17 @@ CONFIG_USB_ZD1201=m CONFIG_USB_NET_RNDIS_WLAN=m CONFIG_RTL8187=m CONFIG_MAC80211_HWSIM=m @@ -92562,7 +92557,7 @@ index 31f5afaa..88692be 100644 CONFIG_LIBERTAS=m CONFIG_LIBERTAS_USB=m CONFIG_LIBERTAS_SDIO=m -@@ -142,57 +489,28 @@ CONFIG_RT2X00=m +@@ -142,57 +490,28 @@ CONFIG_RT2X00=m CONFIG_RT2500USB=m CONFIG_RT73USB=m CONFIG_RT2800USB=m @@ -92628,7 +92623,7 @@ index 31f5afaa..88692be 100644 CONFIG_INPUT_ATI_REMOTE2=m CONFIG_INPUT_KEYSPAN_REMOTE=m CONFIG_INPUT_POWERMATE=m -@@ -207,26 +525,191 @@ CONFIG_SERIO_RAW=m +@@ -207,26 +526,191 @@ CONFIG_SERIO_RAW=m CONFIG_GAMEPORT=m CONFIG_GAMEPORT_NS558=m CONFIG_GAMEPORT_L4=m @@ -92824,7 +92819,7 @@ index 31f5afaa..88692be 100644 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set -@@ -249,10 +732,10 @@ CONFIG_SND_BCM2835=m +@@ -249,10 +733,10 @@ CONFIG_SND_BCM2835=m CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_UA101=m CONFIG_SND_USB_CAIAQ=m @@ -92837,7 +92832,7 @@ index 31f5afaa..88692be 100644 CONFIG_HID_A4TECH=m CONFIG_HID_ACRUX=m CONFIG_HID_APPLE=m -@@ -283,7 +766,6 @@ CONFIG_HID_ORTEK=m +@@ -283,7 +767,6 @@ CONFIG_HID_ORTEK=m CONFIG_HID_PANTHERLORD=m CONFIG_HID_PETALYNX=m CONFIG_HID_PICOLCD=m @@ -92845,7 +92840,7 @@ index 31f5afaa..88692be 100644 CONFIG_HID_ROCCAT=m CONFIG_HID_SAMSUNG=m CONFIG_HID_SONY=m -@@ -292,15 +774,19 @@ CONFIG_HID_SUNPLUS=m +@@ -292,15 +775,19 @@ CONFIG_HID_SUNPLUS=m CONFIG_HID_GREENASIA=m CONFIG_HID_SMARTJOYPLUS=m CONFIG_HID_TOPSEED=m @@ -92865,7 +92860,7 @@ index 31f5afaa..88692be 100644 CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_REALTEK=m CONFIG_USB_STORAGE_DATAFAB=m -@@ -315,8 +801,6 @@ CONFIG_USB_STORAGE_ONETOUCH=m +@@ -315,8 +802,6 @@ CONFIG_USB_STORAGE_ONETOUCH=m CONFIG_USB_STORAGE_KARMA=m CONFIG_USB_STORAGE_CYPRESS_ATACB=m CONFIG_USB_STORAGE_ENE_UB6250=m @@ -92874,7 +92869,7 @@ index 31f5afaa..88692be 100644 CONFIG_USB_MDC800=m CONFIG_USB_MICROTEK=m CONFIG_USB_SERIAL=m -@@ -331,12 +815,12 @@ CONFIG_USB_SERIAL_CP210X=m +@@ -331,12 +816,12 @@ CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m @@ -92888,7 +92883,7 @@ index 31f5afaa..88692be 100644 CONFIG_USB_SERIAL_GARMIN=m CONFIG_USB_SERIAL_IPW=m CONFIG_USB_SERIAL_IUU=m -@@ -345,18 +829,16 @@ CONFIG_USB_SERIAL_KEYSPAN=m +@@ -345,18 +830,16 @@ CONFIG_USB_SERIAL_KEYSPAN=m CONFIG_USB_SERIAL_KLSI=m CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m @@ -92908,7 +92903,7 @@ index 31f5afaa..88692be 100644 CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m -@@ -365,9 +847,11 @@ CONFIG_USB_SERIAL_XIRCOM=m +@@ -365,9 +848,11 @@ CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_OPTICON=m @@ -92922,7 +92917,7 @@ index 31f5afaa..88692be 100644 CONFIG_USB_SERIAL_DEBUG=m CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m -@@ -389,17 +873,71 @@ CONFIG_USB_TEST=m +@@ -389,17 +874,71 @@ CONFIG_USB_TEST=m CONFIG_USB_ISIGHTFW=m CONFIG_USB_YUREX=m CONFIG_MMC=y @@ -92999,7 +92994,7 @@ index 31f5afaa..88692be 100644 # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y -@@ -422,6 +960,8 @@ CONFIG_BTRFS_FS=m +@@ -422,6 +961,8 @@ CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_NILFS2_FS=m CONFIG_FANOTIFY=y @@ -93008,7 +93003,7 @@ index 31f5afaa..88692be 100644 CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m -@@ -437,28 +977,32 @@ CONFIG_MSDOS_FS=y +@@ -437,28 +978,32 @@ CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_NTFS_FS=m @@ -93045,7 +93040,7 @@ index 31f5afaa..88692be 100644 CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=m -@@ -497,39 +1041,33 @@ CONFIG_NLS_ISO8859_14=m +@@ -497,39 +1042,33 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m @@ -93101,10 +93096,10 @@ index 31f5afaa..88692be 100644 1.9.1 -From e1a58be97ac48e5f1e25fc6982aa15189afe891a Mon Sep 17 00:00:00 2001 +From 76e3748151860d6fe3e6999affbe2628a4395b51 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 8 Apr 2013 21:12:48 +0100 -Subject: [PATCH 023/110] Add NAK holdoff scheme. Enabled by default, disable +Subject: [PATCH 023/101] Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh --- @@ -93314,10 +93309,10 @@ index a9dea55..ebee73a 100644 1.9.1 -From 53ac4583629170f71d14a4b90457c27845eec915 Mon Sep 17 00:00:00 2001 +From bc9e5a5eb877fc2e7046ecffaaea43975cc573c3 Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Sun, 4 Nov 2012 15:55:01 +0000 -Subject: [PATCH 024/110] Make sure we wait for the reset to finish +Subject: [PATCH 024/101] Make sure we wait for the reset to finish --- drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2 ++ @@ -93340,10 +93335,10 @@ index aff59df..1a23d4b 100644 1.9.1 -From 1fe16629b6031ab9614206da9ed29cb2db4feb57 Mon Sep 17 00:00:00 2001 +From c8855138a145b108a01e1e065a4c42aa0dd08915 Mon Sep 17 00:00:00 2001 From: P33M Date: Wed, 9 Jan 2013 16:12:04 +0000 -Subject: [PATCH 025/110] dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent +Subject: [PATCH 025/101] dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel memory corruption, escalating to OOPS under high USB load. --- @@ -93380,10 +93375,10 @@ index ebee73a..b3efaf4 100644 1.9.1 -From c92794b6856837d0efde95c810cb6483fe5f8709 Mon Sep 17 00:00:00 2001 +From 89c349f53180dab2e81bbad69c979b942531a4ae Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 15 Feb 2013 22:36:47 +0000 -Subject: [PATCH 026/110] dwc_otg: Fix unsafe access of QTD during URB enqueue +Subject: [PATCH 026/101] dwc_otg: Fix unsafe access of QTD during URB enqueue In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the transaction could complete almost immediately after the qtd was assigned @@ -93470,10 +93465,10 @@ index b3efaf4..1554be5 100644 1.9.1 -From e8437427960f9d8cbae7185f1102944e51e31b2f Mon Sep 17 00:00:00 2001 +From 596b9fb216549e37daa3911b6c83e36d0106f10b Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 15 Feb 2013 22:38:40 +0000 -Subject: [PATCH 027/110] dwc_otg: Fix incorrect URB allocation error handling +Subject: [PATCH 027/101] dwc_otg: Fix incorrect URB allocation error handling If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS because for some reason a member of the *unallocated* struct was set to @@ -93514,10 +93509,10 @@ index 35d03d1..6fe30e3 100644 1.9.1 -From 366979eaa87e2b1ad028083c84076be48d44d503 Mon Sep 17 00:00:00 2001 +From 51e291bed0d26025d0a7788ed7b8d422a68837dc Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 28 Feb 2013 16:52:51 +0000 -Subject: [PATCH 028/110] dwc_otg: fix potential use-after-free case in +Subject: [PATCH 028/101] dwc_otg: fix potential use-after-free case in interrupt handler If a transaction had previously aborted, certain interrupts are @@ -93549,10 +93544,10 @@ index 1a23d4b..7af455d 100644 1.9.1 -From db302b24d7d56e66c046327b8637bd1838cc9d8a Mon Sep 17 00:00:00 2001 +From 72ff7437d1de57dbfc2ea82a1293855f991991a3 Mon Sep 17 00:00:00 2001 From: P33M Date: Sun, 3 Mar 2013 14:45:53 +0000 -Subject: [PATCH 029/110] dwc_otg: add handling of SPLIT transaction data +Subject: [PATCH 029/101] dwc_otg: add handling of SPLIT transaction data toggle errors Previously a data toggle error on packets from a USB1.1 device behind @@ -93607,10 +93602,10 @@ index 7af455d..a27dacd 100644 1.9.1 -From 0fe4b7476e4a8cb9e66e4903cc8c493c2756d5ad Mon Sep 17 00:00:00 2001 +From 6349a0d43f0394be158da810fb0a035bb60ce08c Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 21 Mar 2013 19:36:17 +0000 -Subject: [PATCH 030/110] dwc_otg: implement tasklet for returning URBs to +Subject: [PATCH 030/101] dwc_otg: implement tasklet for returning URBs to usbcore hcd layer The dwc_otg driver interrupt handler for transfer completion will spend @@ -93852,10 +93847,10 @@ index 2b4a14e..39787e3 100644 1.9.1 -From 64e8287aa6a4c2114a491d4d08f3e195fe917a72 Mon Sep 17 00:00:00 2001 +From 71ea56aea4588b8f7ccc386e1546f744386d48ce Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 22 Apr 2013 00:08:36 +0100 -Subject: [PATCH 032/110] dwc_otg: fix NAK holdoff and allow on split +Subject: [PATCH 032/101] dwc_otg: fix NAK holdoff and allow on split transactions only This corrects a bug where if a single active non-periodic endpoint @@ -93925,10 +93920,10 @@ index 533b17d..73f7643 100644 1.9.1 -From 4c7ab253073d193859fa27edd719d5f4f622159d Mon Sep 17 00:00:00 2001 +From 9fced3a3133438d1677a2ae4e74a2f3d7188c6f5 Mon Sep 17 00:00:00 2001 From: Harm Hanemaaijer Date: Thu, 20 Jun 2013 20:21:39 +0200 -Subject: [PATCH 033/110] Speed up console framebuffer imageblit function +Subject: [PATCH 033/101] Speed up console framebuffer imageblit function Especially on platforms with a slower CPU but a relatively high framebuffer fill bandwidth, like current ARM devices, the existing @@ -94140,10 +94135,10 @@ index a2bb276..436494f 100644 1.9.1 -From ed2081dbb044577414d0b70386d13644d851d36f Mon Sep 17 00:00:00 2001 +From 5a9f5c575a5971bf1a04e8d9cdd941a4a1cfbba4 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 13:32:11 +0300 -Subject: [PATCH 034/110] fbdev: add FBIOCOPYAREA ioctl +Subject: [PATCH 034/101] fbdev: add FBIOCOPYAREA ioctl Based on the patch authored by Ali Gholami Rudi at https://lkml.org/lkml/2009/7/13/153 @@ -94239,10 +94234,10 @@ index fb795c3..fa72af0 100644 1.9.1 -From 2e34fa8e8ebdc5ac7e86537b23daf0d33987d2ab Mon Sep 17 00:00:00 2001 +From 8e08a8c3b03f7e7caa4be840c4c692db37d2a5ee Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 16:00:25 +0300 -Subject: [PATCH 035/110] bcm2708_fb: DMA acceleration for fb_copyarea +Subject: [PATCH 035/101] bcm2708_fb: DMA acceleration for fb_copyarea Based on http://www.raspberrypi.org/phpBB3/viewtopic.php?p=62425#p62425 Also used Simon's dmaer_master module as a reference for tweaking DMA @@ -94700,10 +94695,10 @@ index 54cd760..798eb52 100644 1.9.1 -From 72f5e10d6f525ea76a0eef8341c61a060e05ed4b Mon Sep 17 00:00:00 2001 +From 5568fb348e2fdedb68e41c41beb3b82e11b36c4c Mon Sep 17 00:00:00 2001 From: Mike Bradley Date: Mon, 17 Jun 2013 11:31:42 -0700 -Subject: [PATCH 036/110] dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock +Subject: [PATCH 036/101] dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler usb_hcd_unlink_urb_from_ep must be called with the HCD lock held. Calling it @@ -94790,10 +94785,10 @@ index 39787e3..5e6a26a 100644 1.9.1 -From 364630952167e3ec065bae195e483891e59554d5 Mon Sep 17 00:00:00 2001 +From d4b538e11c5caaff6682ee98f930e41adc75a3e2 Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Thu, 4 Apr 2013 11:05:21 +0100 -Subject: [PATCH 037/110] USB fix using a FIQ to implement split transactions +Subject: [PATCH 037/101] USB fix using a FIQ to implement split transactions This commit adds a FIQ implementaion that schedules the split transactions using a FIQ so we don't get @@ -96196,10 +96191,10 @@ index 1b1f83c..c8590b5 100644 1.9.1 -From 7e3076271ad27372e4e28d9c6308ccb476bc514c Mon Sep 17 00:00:00 2001 +From 4ffb0d4445f512b96fbc1af3e3ef947b2b293883 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 11:39:46 +0100 -Subject: [PATCH 038/110] dwc_otg: fix device attributes and avoid kernel +Subject: [PATCH 038/101] dwc_otg: fix device attributes and avoid kernel warnings on boot --- @@ -96268,10 +96263,10 @@ index fab2961..af1cd4d 100644 1.9.1 -From e5d5bf4c0dc6f022d52f17eeede11eff798d987d Mon Sep 17 00:00:00 2001 +From 4baa84cbc027d6be0c7d1d7f2b15db6f2dabc86f Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 15 Jul 2013 23:55:52 +0100 -Subject: [PATCH 039/110] dcw_otg: avoid logging function that can cause panics +Subject: [PATCH 039/101] dcw_otg: avoid logging function that can cause panics See: https://github.com/raspberrypi/firmware/issues/21 Thanks to cleverca22 for fix @@ -96296,10 +96291,10 @@ index af1cd4d..9da0c92 100644 1.9.1 -From f59c4eaf4fe413ded09fe4dcf9b80ff6008e58b8 Mon Sep 17 00:00:00 2001 +From 942f6313e30d0a910e496a1a8836bdeb6ec0a662 Mon Sep 17 00:00:00 2001 From: P33M Date: Sat, 13 Jul 2013 20:41:26 +0100 -Subject: [PATCH 040/110] dwc_otg: mask correct interrupts after transaction +Subject: [PATCH 040/101] dwc_otg: mask correct interrupts after transaction error recovery The dwc_otg driver will unmask certain interrupts on a transaction @@ -96366,10 +96361,10 @@ index 8e5789f..fd73e41 100644 1.9.1 -From 10f4be939ca616828b3cd38180d755a7d3022361 Mon Sep 17 00:00:00 2001 +From e7bdf4a9ab86bdc21a521f82136e836cdf6abaa9 Mon Sep 17 00:00:00 2001 From: P33M Date: Sat, 13 Jul 2013 21:48:41 +0100 -Subject: [PATCH 041/110] dwc_otg: fiq: prevent FIQ thrash and incorrect state +Subject: [PATCH 041/101] dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ In the case of a transaction to a device that had previously aborted @@ -96426,10 +96421,10 @@ index fd73e41..2ec0565 100644 1.9.1 -From 3d27b2717df351d512ddad15be310f4358d175be Mon Sep 17 00:00:00 2001 +From 36459b88a91f2f2d86a70f2d0dd2d348ddd8370b Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Mon, 8 Jul 2013 04:12:19 +0100 -Subject: [PATCH 042/110] Fix function tracing +Subject: [PATCH 042/101] Fix function tracing --- drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 12 ++++++------ @@ -96494,10 +96489,10 @@ index 2ec0565..083b1c3 100644 1.9.1 -From 076c9cb29dafe414ee3919a57d95c0f0a9e76832 Mon Sep 17 00:00:00 2001 +From 8c053272f4f99e82928ecdccfe5d5e032012f096 Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 18 Jul 2013 16:32:41 +0100 -Subject: [PATCH 043/110] dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue +Subject: [PATCH 043/101] dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue --- drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 53 ++++++++++++++-------------- @@ -96584,10 +96579,10 @@ index d1c5c2b..315c803 100644 1.9.1 -From 32357806fa63d542ba5c83e8e5367a03a3bf969e Mon Sep 17 00:00:00 2001 +From 1c4619e01b55800ca3460a562830f78222f4bed5 Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 18 Jul 2013 17:07:26 +0100 -Subject: [PATCH 044/110] dwc_otg: prevent OOPSes during device disconnects +Subject: [PATCH 044/101] dwc_otg: prevent OOPSes during device disconnects The dwc_otg_urb_enqueue function is thread-unsafe. In particular the access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and @@ -96728,10 +96723,10 @@ index 7b92025..db95851 100644 1.9.1 -From e156b6a050067fa5bff3b6101ae39a9010e22b7f Mon Sep 17 00:00:00 2001 +From 30520a91ed7c5445216af88a7c1d440ebf79f515 Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 22 Jul 2013 14:08:26 +0100 -Subject: [PATCH 045/110] dwc_otg: prevent BUG() in TT allocation if hub +Subject: [PATCH 045/101] dwc_otg: prevent BUG() in TT allocation if hub address is > 16 A fixed-size array is used to track TT allocation. This was @@ -96821,10 +96816,10 @@ index 083b1c3..c76910d 100644 1.9.1 -From 63531899b0324747ae13d3d06c57a51685ccfc74 Mon Sep 17 00:00:00 2001 +From a12d71649b0b5673a1cb838fbfebf8683a70d7c5 Mon Sep 17 00:00:00 2001 From: P33M Date: Tue, 23 Jul 2013 14:15:32 +0100 -Subject: [PATCH 046/110] dwc_otg: make channel halts with unknown state less +Subject: [PATCH 046/101] dwc_otg: make channel halts with unknown state less damaging If the IRQ received a channel halt interrupt through the FIQ @@ -96869,10 +96864,10 @@ index c76910d..5fd8613 100644 1.9.1 -From d03121de8997082cd2db538f29c8dd8c2acd14eb Mon Sep 17 00:00:00 2001 +From af4105198fc2e467b9ab895f2f5831208b5fee99 Mon Sep 17 00:00:00 2001 From: P33M Date: Tue, 30 Jul 2013 09:58:48 +0100 -Subject: [PATCH 047/110] dwc_otg: fiq_split: use TTs with more granularity +Subject: [PATCH 047/101] dwc_otg: fiq_split: use TTs with more granularity This fixes certain issues with split transaction scheduling. @@ -96992,10 +96987,10 @@ index 5fd8613..a959a49 100644 1.9.1 -From 423256e30c4f532da015524796a8471f60ad1019 Mon Sep 17 00:00:00 2001 +From 23e4f4379254f084da0cd957196eb5e3ecd711e1 Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 2 Aug 2013 10:04:18 +0100 -Subject: [PATCH 048/110] dwc_otg: fix potential sleep while atomic during urb +Subject: [PATCH 048/101] dwc_otg: fix potential sleep while atomic during urb enqueue Fixes a regression introduced with eb1b482a. Kmalloc called from @@ -97024,10 +97019,10 @@ index 87e517d..88c0544 100644 1.9.1 -From 85e017a120568a1433e087acc24fb1f772cd79d9 Mon Sep 17 00:00:00 2001 +From da992dee27fdda797ddb0fd9688717b0ba4c7df4 Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 5 Aug 2013 11:42:12 +0100 -Subject: [PATCH 049/110] dwc_otg: make fiq_split_enable imply fiq_fix_enable +Subject: [PATCH 049/101] dwc_otg: make fiq_split_enable imply fiq_fix_enable Failing to set up the FIQ correctly would result in "IRQ 32: nobody cared" errors in dmesg. @@ -97056,10 +97051,10 @@ index 176dc14..f06c3d22 100644 1.9.1 -From b7bd8df8032bb2cb6e7c83e73fc94b35fe93269e Mon Sep 17 00:00:00 2001 +From 5a7c83124b0e24eb145d56b0ebe24a7e187a09a1 Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 5 Aug 2013 11:47:12 +0100 -Subject: [PATCH 050/110] dwc_otg: prevent crashes on host port disconnects +Subject: [PATCH 050/101] dwc_otg: prevent crashes on host port disconnects Fix several issues resulting in crashes or inconsistent state if a Model A root port was disconnected. @@ -97217,10 +97212,10 @@ index 88c0544..ae4271a 100644 1.9.1 -From abd4de08167f098a7f75700ee17808e102c99e93 Mon Sep 17 00:00:00 2001 +From b3c2b3c771f9b87842088e54745dd62c74d57dab Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 5 Aug 2013 13:17:58 +0100 -Subject: [PATCH 051/110] dwc_otg: prevent leaking URBs during enqueue +Subject: [PATCH 051/101] dwc_otg: prevent leaking URBs during enqueue A dwc_otg_urb would get leaked if the HCD enqueue function failed for any reason. Free the URB at the appropriate points. @@ -97256,10 +97251,10 @@ index ae4271a..ee8eec9 100644 1.9.1 -From 61fd67b8e80ebd8a8a882cbc243924f6180e84fb Mon Sep 17 00:00:00 2001 +From 8c7034b6c60b0832a257a05605bca517dc819a59 Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 20 Sep 2013 16:08:27 +0100 -Subject: [PATCH 052/110] dwc_otg: Enable NAK holdoff for control split +Subject: [PATCH 052/101] dwc_otg: Enable NAK holdoff for control split transactions Certain low-speed devices take a very long time to complete a @@ -97292,10 +97287,10 @@ index 3a549a1..f8dc4be 100644 1.9.1 -From 2fed783de03b5bdedb4bf477837ebb2a9597c913 Mon Sep 17 00:00:00 2001 +From 96e726fc965d4b9c8836ffdd6dae5744d5dcf2cf Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 20 Sep 2013 19:07:56 +0100 -Subject: [PATCH 053/110] dwc_otg: Fix for occasional lockup on boot when doing +Subject: [PATCH 053/101] dwc_otg: Fix for occasional lockup on boot when doing a USB reset --- @@ -97321,10 +97316,10 @@ index f8dc4be..64d33a5 100644 1.9.1 -From 87c894fcb8805a012d6820a07a1acdb4437a8b60 Mon Sep 17 00:00:00 2001 +From 020ecd365efbfc6a6599ef5f0ee2fc34d5dbf14c Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 27 Sep 2013 14:42:24 +0100 -Subject: [PATCH 054/110] dwc_otg: Don't issue traffic to LS devices in FS mode +Subject: [PATCH 054/101] dwc_otg: Don't issue traffic to LS devices in FS mode Issuing low-speed packets when the root port is in full-speed mode causes the root port to stop responding. Explicitly fail when @@ -97366,10 +97361,10 @@ index 1904f6a..22300f0 100644 1.9.1 -From 850ce2ec49c96b8cd1a6b8e51e12ca9daa7652bb Mon Sep 17 00:00:00 2001 +From 9af4ad49abf13e8c65e9271b513128cdca03e24d Mon Sep 17 00:00:00 2001 From: Vincent Sanders Date: Wed, 30 Jan 2013 12:45:18 +0000 -Subject: [PATCH 055/110] bcm2835: add v4l2 camera device +Subject: [PATCH 055/101] bcm2835: add v4l2 camera device - Supports raw YUV capture, preview, JPEG and H264. - Uses videobuf2 for data transfer, using dma_buf. @@ -103357,10 +103352,10 @@ index 0000000..9d1d11e 1.9.1 -From 9c5782d989787bc070abf9c2d558681c6c87ea5f Mon Sep 17 00:00:00 2001 +From e2b93686a82c8cc9834b873b8a8a1f0d4a893445 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 10:58:01 +0000 -Subject: [PATCH 056/110] V4L2: Fix EV values. Add manual shutter speed control +Subject: [PATCH 056/101] V4L2: Fix EV values. Add manual shutter speed control V4L2 EV values should be in units of 1/1000. Corrected. Add support for V4L2_CID_EXPOSURE_ABSOLUTE which should @@ -103553,10 +103548,10 @@ index c611b58..d8aace5 100644 1.9.1 -From bee371e86cf75de45d3a49e2741bb0e99ba18abb Mon Sep 17 00:00:00 2001 +From baf00fde04e94e1ca78bad9535d2f22e59134fdf Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 11:01:53 +0000 -Subject: [PATCH 057/110] V4L2: Correct JPEG Q-factor range +Subject: [PATCH 057/101] V4L2: Correct JPEG Q-factor range Should be 1-100, not 0-100 @@ -103594,10 +103589,10 @@ index 481d1f6..c2e4c64 100644 1.9.1 -From dd9b15163f0a87e1cd151b639e25da83c69adeb4 Mon Sep 17 00:00:00 2001 +From 83f6d13bffa5cf1286c71b77349b452c2e2f6f6f Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 11:05:24 +0000 -Subject: [PATCH 058/110] V4L2: Fix issue of driver jamming if STREAMON failed. +Subject: [PATCH 058/101] V4L2: Fix issue of driver jamming if STREAMON failed. Fix issue where the driver was left in a partially enabled state if STREAMON failed, and would then reject many IOCTLs @@ -103633,10 +103628,10 @@ index 47fe45d..2743074 100644 1.9.1 -From 31a4b623cbe4db51dfd638002ced0ca13330c3fa Mon Sep 17 00:00:00 2001 +From 8511ef1d85f4b7d8e5e626e1eef3e978c2a95f76 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 15:30:48 +0000 -Subject: [PATCH 059/110] V4L2: Fix ISO controls. +Subject: [PATCH 059/101] V4L2: Fix ISO controls. Driver was passing the index to the GPU, and not the desired ISO value. @@ -103689,10 +103684,10 @@ index c2e4c64..92863f7 100644 1.9.1 -From 04076ca535a7e317197c8ca1386d8eb203de76b2 Mon Sep 17 00:00:00 2001 +From 702ba69516cf1f972898eee2006e8cc7fa8a03e7 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 16:40:24 +0000 -Subject: [PATCH 060/110] V4L2: Add flicker avoidance controls +Subject: [PATCH 060/101] V4L2: Add flicker avoidance controls Add support for V4L2_CID_POWER_LINE_FREQUENCY to set flicker avoidance frequencies. @@ -103807,10 +103802,10 @@ index d8aace5..b3d2c39 100644 1.9.1 -From 4f33a3b49081cca656d274b68faa996f2248d63a Mon Sep 17 00:00:00 2001 +From 55f2b34c660430f382f12e7d0c86944f89f98407 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Fri, 13 Dec 2013 15:54:13 +0000 -Subject: [PATCH 061/110] V4L2: Add support for frame rate control. +Subject: [PATCH 061/101] V4L2: Add support for frame rate control. Add support for frame rate (or time per frame as V4L2 inverts it) control via s_parm. @@ -104049,10 +104044,10 @@ index b3d2c39..0f2bd50 100644 1.9.1 -From 7dc835e1b17783d92b53abe0c74ffc2366cc3f0c Mon Sep 17 00:00:00 2001 +From a2ec33f1e07e899058a50832ae1500610ef8c43b Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 17:30:09 +0000 -Subject: [PATCH 062/110] V4L2: Improve G_FBUF handling so we pass conformance +Subject: [PATCH 062/101] V4L2: Improve G_FBUF handling so we pass conformance Return some sane numbers for get framebuffer so that we pass conformance. @@ -104092,10 +104087,10 @@ index 8c38d03..c8d8742 100644 1.9.1 -From 742a92eaa8ba5d2d47868505712f97774df6e37e Mon Sep 17 00:00:00 2001 +From 4089e1c1cb9978a410dedc0fe35d1a0a4f061ba7 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 17:29:39 +0000 -Subject: [PATCH 063/110] V4L2: Fix information advertised through g_vidfmt +Subject: [PATCH 063/101] V4L2: Fix information advertised through g_vidfmt Width and height were being stored based on incorrect values. @@ -104135,10 +104130,10 @@ index c8d8742..4766a9c 100644 1.9.1 -From 02cff92806c6e45650444de836571f8c93343a99 Mon Sep 17 00:00:00 2001 +From d59952191719a5abe3bc4bd685a583e650af6a99 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 11:03:54 +0000 -Subject: [PATCH 064/110] V4L2: Add support for inline H264 headers +Subject: [PATCH 064/101] V4L2: Add support for inline H264 headers Add support for V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER to control H264 inline headers. @@ -104443,10 +104438,10 @@ index 0f2bd50..b08a4b0 100644 1.9.1 -From 64a10ef1b41060cb7cdf03c8ca515604c7324af3 Mon Sep 17 00:00:00 2001 +From 1b1106b4e1e7b43d2046de90ed4b3b98ad7545e5 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Thu, 19 Dec 2013 17:33:02 +0000 -Subject: [PATCH 065/110] V4L2: Fix JPEG timestamp issue +Subject: [PATCH 065/101] V4L2: Fix JPEG timestamp issue JPEG images were coming through from the GPU with timestamp of 0. Detect this and give current system time instead @@ -104484,10 +104479,10 @@ index 4766a9c..9fc90a2 100644 1.9.1 -From 644fc9a620229c29ac037ef173f5bf5ae29ad89b Mon Sep 17 00:00:00 2001 +From 13c1fbe328c91df406d1724c3ffcd7eb584f861f Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 11:24:55 +0000 -Subject: [PATCH 066/110] V4L2: Fix issue when switching down JPEG resolution. +Subject: [PATCH 066/101] V4L2: Fix issue when switching down JPEG resolution. JPEG buffer size calculation is based on input resolution. Input resolution was being configured after output port @@ -104649,10 +104644,10 @@ index 9fc90a2..4780107 100644 1.9.1 -From a0190c30797f5763f1cb6c585d5a5dafe858743b Mon Sep 17 00:00:00 2001 +From 345c6abeb25774c19d9f956ae45b08f0041a0aaf Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 23 Dec 2013 15:42:21 +0000 -Subject: [PATCH 067/110] V4L2: Enable MJPEG encoding +Subject: [PATCH 067/101] V4L2: Enable MJPEG encoding Requires GPU firmware update to support MJPEG encoder. @@ -104696,10 +104691,10 @@ index 856e80e..764bb12 100644 1.9.1 -From bc3b2199d7f4a61856b91e5bf32a95615d8bc2b2 Mon Sep 17 00:00:00 2001 +From 9397547c190a76abaf810a0ab3db75990328198f Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Thu, 2 Jan 2014 15:57:06 +0000 -Subject: [PATCH 068/110] V4L2: Correct flag settings for compressed formats +Subject: [PATCH 068/101] V4L2: Correct flag settings for compressed formats Set flags field correctly on enum_fmt_vid_cap for compressed image formats. @@ -104795,10 +104790,10 @@ index 602b4a7..076f9a8 100644 1.9.1 -From 29f29d1d2b9f30d2e30b6d6408ea012186ee5d8d Mon Sep 17 00:00:00 2001 +From c09ec0e836a8e925e949afdf44660adf8e664862 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Wed, 12 Feb 2014 11:18:20 +0000 -Subject: [PATCH 069/110] V4L2: H264 profile & level ctrls, FPS control and +Subject: [PATCH 069/101] V4L2: H264 profile & level ctrls, FPS control and auto exp pri Several control handling updates. @@ -105487,10 +105482,10 @@ index b08a4b0..ae8fef9 100644 1.9.1 -From 69f469c21a719f2740baad9273a6538a8bb737f1 Mon Sep 17 00:00:00 2001 +From 6b342deff5e9a3496aa8930b5e4344e83012f2fe Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Wed, 12 Feb 2014 11:39:20 +0000 -Subject: [PATCH 070/110] V4L2: Correct BGR24 to RGB24 in format table +Subject: [PATCH 070/101] V4L2: Correct BGR24 to RGB24 in format table Signed-off-by: Dave Stevenson --- @@ -105516,10 +105511,10 @@ index 6d0d77a..8285e6a 100644 1.9.1 -From 0201321b21e505e22db1d8c723f3d42e3fad61b6 Mon Sep 17 00:00:00 2001 +From 253f94a2cb5ad5c348c7d428ba02ad9d327ab3d0 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Wed, 12 Feb 2014 15:35:41 +0000 -Subject: [PATCH 071/110] V4L2: Add additional pixel formats. Correct +Subject: [PATCH 071/101] V4L2: Add additional pixel formats. Correct colourspace Adds the other flavours of YUYV, and NV12. @@ -105588,10 +105583,10 @@ index 8285e6a..3dea993 100644 1.9.1 -From e24842aca01dae87972683605f4cf609b212f4a0 Mon Sep 17 00:00:00 2001 +From 0129c277aeae3b2d73e3125e20ddabb885f1e33f Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Fri, 14 Feb 2014 17:08:18 +0000 -Subject: [PATCH 072/110] V4L2: Drop logging msg from info to debug +Subject: [PATCH 072/101] V4L2: Drop logging msg from info to debug Signed-off-by: Dave Stevenson --- @@ -105615,10 +105610,10 @@ index a06fb44..82752e6 100644 1.9.1 -From 972a1c1c5d8d00179d42292c655910704abcfb5b Mon Sep 17 00:00:00 2001 +From 7d89595cc0d322b494f70efe81b9caddb35a8b07 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Fri, 14 Feb 2014 17:12:08 +0000 -Subject: [PATCH 073/110] V4L2: Initial pass at scene modes. +Subject: [PATCH 073/101] V4L2: Initial pass at scene modes. Only supports exposure mode and metering modes. @@ -105983,10 +105978,10 @@ index 45cf790..b7a7e883 100644 1.9.1 -From a83f569cfd54ebe641597fba37b10dba0a95099c Mon Sep 17 00:00:00 2001 +From d532e0ff679f8aa7f2a4c8b9217e2f0f456deb2b Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Tue, 25 Mar 2014 11:48:01 +0000 -Subject: [PATCH 074/110] V4L2: Add manual white balance control. +Subject: [PATCH 074/101] V4L2: Add manual white balance control. Adds support for V4L2_CID_RED_BALANCE and V4L2_CID_BLUE_BALANCE. Only has an effect if @@ -106114,20 +106109,20 @@ index ae8fef9..089f949 100644 1.9.1 -From 1aea771ba9b7dd2656a2cf9ffd64d0fdd7bcc18f Mon Sep 17 00:00:00 2001 +From 291436c2cf29a2aebe18f470c779b46e894ee45b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 2 Dec 2013 16:57:44 +0000 -Subject: [PATCH 075/110] config: Enable V4L / MMAL driver +Subject: [PATCH 075/101] config: Enable V4L / MMAL driver --- arch/arm/configs/bcmrpi_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 88692be..75a262d 100644 +index bbf3000..058a520 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -692,6 +692,9 @@ CONFIG_DVB_B2C2_FLEXCOP_USB=m +@@ -693,6 +693,9 @@ CONFIG_DVB_B2C2_FLEXCOP_USB=m CONFIG_VIDEO_EM28XX=m CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m @@ -106141,10 +106136,10 @@ index 88692be..75a262d 100644 1.9.1 -From d97b61fab2887a8106ac3a2e0edcada2b2bc5567 Mon Sep 17 00:00:00 2001 +From 7081d21d5a6d11b4e90c6a92517ee9ed86ff694b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Dec 2013 22:16:19 +0000 -Subject: [PATCH 076/110] config: Enable CONFIG_MEMCG, but leave it disabled +Subject: [PATCH 076/101] config: Enable CONFIG_MEMCG, but leave it disabled (due to memory cost). Enable with cgroup_enable=memory. --- @@ -106154,7 +106149,7 @@ Subject: [PATCH 076/110] config: Enable CONFIG_MEMCG, but leave it disabled 3 files changed, 29 insertions(+) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 75a262d..1041f5e 100644 +index 058a520..5100760 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig @@ -18,6 +18,7 @@ CONFIG_CGROUP_FREEZER=y @@ -106219,10 +106214,10 @@ index 5b6b003..56de606 100644 1.9.1 -From 61de85782042d9bfccac1f02be8729d41ef0ccbe Mon Sep 17 00:00:00 2001 +From 24151b1c2a7c4821d3c31737d5b058bba205bc81 Mon Sep 17 00:00:00 2001 From: Julian Scheel Date: Wed, 19 Feb 2014 16:06:59 +0100 -Subject: [PATCH 077/110] snd-bcm2835: Add support for spdif/hdmi passthrough +Subject: [PATCH 077/101] snd-bcm2835: Add support for spdif/hdmi passthrough This adds a dedicated subdevice which can be used for passthrough of non-audio formats (ie encoded a52) through the hdmi audio link. In addition to this @@ -106383,7 +106378,7 @@ index 8c5334a..aad905f 100755 return 0; } diff --git a/sound/arm/bcm2835-pcm.c b/sound/arm/bcm2835-pcm.c -index 7f6d75e..fe27a8f 100755 +index b4084bb..ebd3f62 100755 --- a/sound/arm/bcm2835-pcm.c +++ b/sound/arm/bcm2835-pcm.c @@ -15,6 +15,8 @@ @@ -106441,8 +106436,8 @@ index 7f6d75e..fe27a8f 100755 if (idx > MAX_SUBSTREAMS) { audio_error ("substream(%d) device doesn't exist max(%d) substreams allowed\n", -@@ -138,7 +163,13 @@ static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream) - +@@ -143,13 +168,20 @@ static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream) + } runtime->private_data = alsa_stream; runtime->private_free = snd_bcm2835_playback_free; - runtime->hw = snd_bcm2835_playback_hw; @@ -106456,8 +106451,7 @@ index 7f6d75e..fe27a8f 100755 /* minimum 16 bytes alignment (for vchiq bulk transfers) */ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 16); -@@ -150,6 +181,7 @@ static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream) - } + chip->alsa_stream[idx] = alsa_stream; + chip->opened |= (1 << idx); @@ -106694,4743 +106688,10 @@ index 36afee3..8c2fe26 100755 1.9.1 -From 0b8b181d4f8ce935a5063e7f00fd25eaebd83e47 Mon Sep 17 00:00:00 2001 -From: P33M -Date: Wed, 19 Mar 2014 12:58:23 +0000 -Subject: [PATCH 078/110] dwc_otg: fiq_fsm: Base commit for driver rewrite - -This commit removes the previous FIQ fixes entirely and adds fiq_fsm. - -This rewrite features much more complete support for split transactions -and takes into account several OTG hardware bugs. High-speed -isochronous transactions are also capable of being performed by fiq_fsm. - -All driver options have been removed and replaced with: - - dwc_otg.fiq_enable (bool) - - dwc_otg.fiq_fsm_enable (bool) - - dwc_otg.fiq_fsm_mask (bitmask) - - dwc_otg.nak_holdoff (unsigned int) - -Defaults are specified such that fiq_fsm behaves similarly to the -previously implemented FIQ fixes. ---- - arch/arm/mach-bcm2708/bcm2708.c | 19 - - drivers/usb/host/dwc_otg/Makefile | 3 +- - drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 47 +- - drivers/usb/host/dwc_otg/dwc_otg_driver.c | 47 +- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 1217 ++++++++++++++++++++++++++ - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 349 ++++++++ - drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S | 81 ++ - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 759 +++++++++++++--- - drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 11 + - drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 979 ++++++++++----------- - drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 101 ++- - drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 41 +- - drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c | 113 --- - drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h | 48 - - 14 files changed, 2865 insertions(+), 950 deletions(-) - create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c - create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h - create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S - delete mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c - delete mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h - -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 2b11e9d..91c008f 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -328,20 +328,6 @@ static struct resource bcm2708_usb_resources[] = { - }, - }; - --bool fiq_fix_enable = true; -- --static struct resource bcm2708_usb_resources_no_fiq_fix[] = { -- [0] = { -- .start = USB_BASE, -- .end = USB_BASE + SZ_128K - 1, -- .flags = IORESOURCE_MEM, -- }, -- [1] = { -- .start = IRQ_USB, -- .end = IRQ_USB, -- .flags = IORESOURCE_IRQ, -- }, --}; - - static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); - -@@ -724,11 +710,6 @@ void __init bcm2708_init(void) - #endif - bcm_register_device(&bcm2708_systemtimer_device); - bcm_register_device(&bcm2708_fb_device); -- if (!fiq_fix_enable) -- { -- bcm2708_usb_device.resource = bcm2708_usb_resources_no_fiq_fix; -- bcm2708_usb_device.num_resources = ARRAY_SIZE(bcm2708_usb_resources_no_fiq_fix); -- } - bcm_register_device(&bcm2708_usb_device); - bcm_register_device(&bcm2708_uart1_device); - bcm_register_device(&bcm2708_powerman_device); -diff --git a/drivers/usb/host/dwc_otg/Makefile b/drivers/usb/host/dwc_otg/Makefile -index a56f193..e7bdd12 100644 ---- a/drivers/usb/host/dwc_otg/Makefile -+++ b/drivers/usb/host/dwc_otg/Makefile -@@ -36,7 +36,8 @@ dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o - dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o - dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o - dwc_otg-objs += dwc_otg_adp.o --dwc_otg-objs += dwc_otg_mphi_fix.o -+dwc_otg-objs += dwc_otg_fiq_fsm.o -+dwc_otg-objs += dwc_otg_fiq_stub.o - ifneq ($(CFI),) - dwc_otg-objs += dwc_otg_cfi.o - endif -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c -index 2f8b3bd..065807f 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c -@@ -45,7 +45,6 @@ - #include "dwc_otg_driver.h" - #include "dwc_otg_pcd.h" - #include "dwc_otg_hcd.h" --#include "dwc_otg_mphi_fix.h" - - #ifdef DEBUG - inline const char *op_state_str(dwc_otg_core_if_t * core_if) -@@ -1319,7 +1318,7 @@ static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if) - /** - * This function returns the Core Interrupt register. - */ --static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk) -+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd) - { - gahbcfg_data_t gahbcfg = {.d32 = 0 }; - gintsts_data_t gintsts; -@@ -1345,16 +1344,15 @@ static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gin - } - gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); - gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); -- { -- unsigned long flags; -- -- // Re-enable the saved interrupts -- local_irq_save(flags); -+ if(fiq_enable) { - local_fiq_disable(); -- gintmsk.d32 |= gintmsk_common.d32; -- gintsts_saved.d32 &= ~gintmsk_common.d32; -- reenable_gintmsk->d32 = gintmsk.d32; -- local_irq_restore(flags); -+ /* Pull in the interrupts that the FIQ has masked */ -+ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32); -+ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */ -+ reenable_gintmsk->d32 |= gintmsk.d32; -+ reenable_gintmsk->d32 |= ~(hcd->fiq_state->gintmsk_saved.d32); -+ reenable_gintmsk->d32 &= gintmsk_common.d32; -+ local_fiq_enable(); - } - - gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); -@@ -1366,13 +1364,15 @@ static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gin - gintsts.d32, gintmsk.d32); - } - #endif -- if (!fiq_fix_enable){ -+ if (!fiq_enable){ - if (gahbcfg.b.glblintrmsk) - return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); - else - return 0; -- } -- else { -+ } else { -+ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface. -+ * Can't trust the global interrupt mask bit in this case. -+ */ - return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); - } - -@@ -1406,7 +1406,7 @@ int32_t dwc_otg_handle_common_intr(void *dev) - { - int retval = 0; - gintsts_data_t gintsts; -- gintmsk_data_t reenable_gintmsk; -+ gintmsk_data_t gintmsk_reenable = { .d32 = 0 }; - gpwrdn_data_t gpwrdn = {.d32 = 0 }; - dwc_otg_device_t *otg_dev = dev; - dwc_otg_core_if_t *core_if = otg_dev->core_if; -@@ -1428,7 +1428,10 @@ int32_t dwc_otg_handle_common_intr(void *dev) - } - - if (core_if->hibernation_suspend <= 0) { -- gintsts.d32 = dwc_otg_read_common_intr(core_if, &reenable_gintmsk); -+ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end -+ * of this handler - god only knows why it's done like this -+ */ -+ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd); - - if (gintsts.b.modemismatch) { - retval |= dwc_otg_handle_mode_mismatch_intr(core_if); -@@ -1525,11 +1528,16 @@ int32_t dwc_otg_handle_common_intr(void *dev) - gintsts.b.portintr = 1; - DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); - retval |= 1; -- reenable_gintmsk.b.portintr = 1; -+ gintmsk_reenable.b.portintr = 1; - - } -- -- DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, reenable_gintmsk.d32); -+ /* Did we actually handle anything? if so, unmask the interrupt */ -+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval); -+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32); -+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32); -+ if (retval) { -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32); -+ } - - } else { - DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32); -@@ -1583,6 +1591,5 @@ int32_t dwc_otg_handle_common_intr(void *dev) - } - if (core_if->lock) - DWC_SPINUNLOCK(core_if->lock); -- - return retval; - } -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_driver.c b/drivers/usb/host/dwc_otg/dwc_otg_driver.c -index f06c3d22..d5bd726 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c -@@ -56,6 +56,7 @@ - #include "dwc_otg_core_if.h" - #include "dwc_otg_pcd_if.h" - #include "dwc_otg_hcd_if.h" -+#include "dwc_otg_fiq_fsm.h" - - #define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" - #define DWC_DRIVER_DESC "HS OTG USB Controller driver" -@@ -64,7 +65,6 @@ bool microframe_schedule=true; - - static const char dwc_driver_name[] = "dwc_otg"; - --extern void* dummy_send; - - extern int pcd_init( - #ifdef LM_INTERFACE -@@ -240,13 +240,14 @@ static struct dwc_otg_driver_module_params dwc_otg_module_params = { - .adp_enable = -1, - }; - --//Global variable to switch the fiq fix on or off (declared in bcm2708.c) --extern bool fiq_fix_enable; -+//Global variable to switch the fiq fix on or off -+bool fiq_enable = 1; - // Global variable to enable the split transaction fix --bool fiq_split_enable = true; --//Global variable to switch the nak holdoff on or off --bool nak_holdoff_enable = true; -+bool fiq_fsm_enable = false; -+//Bulk split-transaction NAK holdoff in microframes -+uint16_t nak_holdoff = 8; - -+unsigned short fiq_fsm_mask = 0x01; - - /** - * This function shows the Driver Version. -@@ -800,7 +801,7 @@ static int dwc_otg_driver_probe( - dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start, - _dev->resource[0].end - - _dev->resource[0].start+1); -- if (fiq_fix_enable) -+ if (fiq_enable) - { - if (!request_mem_region(_dev->resource[1].start, - _dev->resource[1].end - _dev->resource[1].start + 1, -@@ -813,7 +814,6 @@ static int dwc_otg_driver_probe( - dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start, - _dev->resource[1].end - - _dev->resource[1].start + 1); -- dummy_send = (void *) kmalloc(16, GFP_ATOMIC); - } - - #else -@@ -1071,9 +1071,9 @@ static int __init dwc_otg_driver_init(void) - int error; - struct device_driver *drv; - -- if(fiq_split_enable && !fiq_fix_enable) { -- printk(KERN_WARNING "dwc_otg: fiq_split_enable was set without fiq_fix_enable! Correcting.\n"); -- fiq_fix_enable = 1; -+ if(fiq_fsm_enable && !fiq_enable) { -+ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n"); -+ fiq_enable = 1; - } - - printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, -@@ -1095,9 +1095,9 @@ static int __init dwc_otg_driver_init(void) - printk(KERN_ERR "%s retval=%d\n", __func__, retval); - return retval; - } -- printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_fix_enable ? "enabled":"disabled"); -- printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff_enable ? "enabled":"disabled"); -- printk(KERN_DEBUG "dwc_otg: FIQ split fix %s\n", fiq_split_enable ? "enabled":"disabled"); -+ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled"); -+ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled"); -+ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled"); - - error = driver_create_file(drv, &driver_attr_version); - #ifdef DEBUG -@@ -1378,12 +1378,19 @@ MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); - module_param(microframe_schedule, bool, 0444); - MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); - --module_param(fiq_fix_enable, bool, 0444); --MODULE_PARM_DESC(fiq_fix_enable, "Enable the fiq fix"); --module_param(nak_holdoff_enable, bool, 0444); --MODULE_PARM_DESC(nak_holdoff_enable, "Enable the NAK holdoff"); --module_param(fiq_split_enable, bool, 0444); --MODULE_PARM_DESC(fiq_split_enable, "Enable the FIQ fix on split transactions"); -+module_param(fiq_enable, bool, 0444); -+MODULE_PARM_DESC(fiq_enable, "Enable the FIQ"); -+module_param(nak_holdoff, ushort, 0644); -+MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8"); -+module_param(fiq_fsm_enable, bool, 0444); -+MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask"); -+module_param(fiq_fsm_mask, ushort, 0444); -+MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n" -+ "Bit 0 : Non-periodic split transactions\n" -+ "Bit 1 : Periodic split transactions\n" -+ "Bit 2 : High-speed multi-transfer isochronous\n" -+ "All other bits should be set 0."); -+ - - /** @page "Module Parameters" - * -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -new file mode 100644 -index 0000000..e286d57 ---- /dev/null -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -@@ -0,0 +1,1217 @@ -+/* -+ * dwc_otg_fiq_fsm.c - The finite state machine FIQ -+ * -+ * Copyright (c) 2013 Raspberry Pi Foundation -+ * -+ * Author: Jonathan Bell -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Raspberry Pi nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This FIQ implements functionality that performs split transactions on -+ * the dwc_otg hardware without any outside intervention. A split transaction -+ * is "queued" by nominating a specific host channel to perform the entirety -+ * of a split transaction. This FIQ will then perform the microframe-precise -+ * scheduling required in each phase of the transaction until completion. -+ * -+ * The FIQ functionality is glued into the Synopsys driver via the entry point -+ * in the FSM enqueue function, and at the exit point in handling a HC interrupt -+ * for a FSM-enabled channel. -+ * -+ * NB: Large parts of this implementation have architecture-specific code. -+ * For porting this functionality to other ARM machines, the minimum is required: -+ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed -+ * to the FIQ -+ * - A method of forcing a software generated interrupt from FIQ mode that then -+ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number) -+ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same -+ * processor core - there is no locking between the FIQ and IRQ (aside from -+ * local_fiq_disable) -+ * -+ */ -+ -+#include "dwc_otg_fiq_fsm.h" -+ -+ -+char buffer[1000*16]; -+int wptr; -+void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...) -+{ -+ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR; -+ va_list args; -+ char text[17]; -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) }; -+ -+ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR) -+ { -+ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7); -+ va_start(args, fmt); -+ vsnprintf(text+8, 9, fmt, args); -+ va_end(args); -+ -+ memcpy(buffer + wptr, text, 16); -+ wptr = (wptr + 16) % sizeof(buffer); -+ } -+} -+ -+/** -+ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction -+ * @channel: channel to re-enable -+ */ -+static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force) -+{ -+ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) }; -+ -+ hcchar.b.chen = 0; -+ if (st->channel[n].hcchar_copy.b.eptype & 0x1) { -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; -+ /* Hardware bug workaround: update the ssplit index */ -+ if (st->channel[n].hcsplt_copy.b.spltena) -+ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; -+ -+ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; -+ } -+ -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); -+ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ hcchar.b.chen = 1; -+ -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); -+ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force); -+} -+ -+/** -+ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage -+ * @st: Pointer to the channel's state -+ * @n : channel number -+ * -+ * Change host channel registers to perform a complete-split transaction. Being mindful of the -+ * endpoint direction, set control regs up correctly. -+ */ -+static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n) -+{ -+ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) }; -+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; -+ -+ hcsplt.b.compsplt = 1; -+ if (st->channel[n].hcchar_copy.b.epdir == 1) { -+ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket. -+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; -+ } else { -+ // If OUT, the CSPLIT result contains handshake only. -+ hctsiz.b.xfersize = 0; -+ } -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); -+ mb(); -+} -+ -+static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n) -+{ -+ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */ -+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; -+ -+ if (st->channel[n].hcchar_copy.b.epdir == 0) { -+ return st->channel[n].hctsiz_copy.b.xfersize; -+ } else { -+ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize; -+ } -+ -+} -+ -+ -+/** -+ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT -+ * -+ * Of use only for IN periodic transfers. -+ */ -+static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n) -+{ -+ hcdma_data_t hcdma; -+ int i = st->channel[n].nrpackets; -+ int len = 254; -+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; -+ -+ len = fiq_get_xfer_len(st, n); -+ fiq_print(FIQDBG_INT, st, "LEN: %03d", len); -+ st->channel[n].dma_info.slot_len[i] = len; -+ i++; -+ if (i > 5) -+ BUG(); -+ -+ st->channel[n].nrpackets++; -+ -+ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0]; -+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); -+ return 0; -+} -+ -+/** -+ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ -+ */ -+static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n) -+{ -+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; -+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; -+ hctsiz.b.pktcnt = 1; -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); -+} -+ -+/** -+ * fiq_iso_out_advance() - update DMA address and split position bits -+ * for isochronous OUT transactions. -+ * -+ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and -+ * Split-BEGIN states are not handled - this is done when the transaction was queued. -+ * -+ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state. -+ */ -+static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n) -+{ -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ hcdma_data_t hcdma; -+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; -+ int last = 0; -+ int i = st->channel[n].dma_info.index; -+ -+ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i); -+ i++; -+ if (i == 4) -+ last = 1; -+ if (st->channel[n].dma_info.slot_len[i+1] == 255) -+ last = 1; -+ -+ /* New DMA address - address of bounce buffer referred to in index */ -+ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0]; -+ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n)); -+ //hcdma.d32 += st->channel[n].dma_info.slot_len[i]; -+ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last); -+ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]); -+ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT); -+ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ); -+ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID; -+ /* Set up new packet length */ -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i]; -+ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32); -+ -+ st->channel[n].dma_info.index++; -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); -+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); -+ return last; -+} -+ -+/** -+ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT -+ * -+ * Despite the limitations of the DWC core, we can force a microframe pipeline of -+ * isochronous OUT start-split transactions while waiting for a corresponding other-type -+ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it -+ * is very unlikely that filling the start-split FIFO will cause data loss. -+ * This allows much better interleaving of transactions in an order-independent way- -+ * there is no requirement to prioritise isochronous, just a state-space search has -+ * to be performed on each periodic start-split complete interrupt. -+ */ -+static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n) -+{ -+ int hub_addr = st->channel[n].hub_addr; -+ int port_addr = st->channel[n].port_addr; -+ int i, poked = 0; -+ for (i = 0; i < num_channels; i++) { -+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) -+ continue; -+ if (st->channel[i].hub_addr == hub_addr && -+ st->channel[i].port_addr == port_addr) { -+ switch (st->channel[i].fsm) { -+ case FIQ_PER_ISO_OUT_PENDING: -+ if (st->channel[i].nrpackets == 1) { -+ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST; -+ } else { -+ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ } -+ fiq_fsm_restart_channel(st, i, 0); -+ poked = 1; -+ break; -+ -+ default: -+ break; -+ } -+ } -+ if (poked) -+ break; -+ } -+ return poked; -+} -+ -+/** -+ * fiq_fsm_tt_in_use() - search for host channels using this TT -+ * @n: Channel to use as reference -+ * -+ */ -+int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n) -+{ -+ int hub_addr = st->channel[n].hub_addr; -+ int port_addr = st->channel[n].port_addr; -+ int i, in_use = 0; -+ for (i = 0; i < num_channels; i++) { -+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) -+ continue; -+ switch (st->channel[i].fsm) { -+ /* TT is reserved for channels that are in the middle of a periodic -+ * split transaction. -+ */ -+ case FIQ_PER_SSPLIT_STARTED: -+ case FIQ_PER_CSPLIT_WAIT: -+ case FIQ_PER_CSPLIT_NYET1: -+ //case FIQ_PER_CSPLIT_POLL: -+ case FIQ_PER_ISO_OUT_ACTIVE: -+ if (st->channel[i].hub_addr == hub_addr && -+ st->channel[i].port_addr == port_addr) { -+ in_use = 1; -+ } -+ break; -+ default: -+ break; -+ } -+ if (in_use) -+ break; -+ } -+ return in_use; -+} -+ -+/** -+ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need -+ * to be issued for this IN transaction. -+ * -+ * We cannot tell the inbound PID of a data packet due to hardware limitations. -+ * we need to make an educated guess as to whether we need to queue another CSPLIT -+ * or not. A no-brainer is when we have received enough data to fill the endpoint -+ * size, but for endpoints that give variable-length data then we have to resort -+ * to heuristics. -+ * -+ * We also return whether this is the last CSPLIT to be queued, again based on -+ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions. -+ */ -+ -+/* -+ * We need some way of guaranteeing if a returned periodic packet of size X -+ * has a DATA0 PID. -+ * The heuristic value of 144 bytes assumes that the received data has maximal -+ * bit-stuffing and the clock frequency of the transmitting device is at the lowest -+ * permissible limit. If the transfer length results in a final packet size -+ * 144 < p <= 188, then an erroneous CSPLIT will be issued. -+ * Also used to ensure that an endpoint will nominally only return a single -+ * complete-split worth of data. -+ */ -+#define DATA0_PID_HEURISTIC 144 -+ -+static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last) -+{ -+ -+ int i; -+ int total_len = 0; -+ int more_needed = 1; -+ struct fiq_channel_state *st = &state->channel[n]; -+ -+ for (i = 0; i < st->nrpackets; i++) { -+ total_len += st->dma_info.slot_len[i]; -+ } -+ -+ *probably_last = 0; -+ -+ if (st->hcchar_copy.b.eptype == 0x3) { -+ /* -+ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data -+ * then this is definitely the last CSPLIT. -+ */ -+ *probably_last = 1; -+ } else { -+ /* Isoc IN. This is a bit risky if we are the first transaction: -+ * we may have been held off slightly. */ -+ if (i > 1 && st->dma_info.slot_len[st->nrpackets-1] <= DATA0_PID_HEURISTIC) { -+ more_needed = 0; -+ } -+ /* If in the next uframe we will receive enough data to fill the endpoint, -+ * then only issue 1 more csplit. -+ */ -+ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC) -+ *probably_last = 1; -+ } -+ -+ if (total_len >= st->hctsiz_copy.b.xfersize || -+ i == 6 || total_len == 0) -+ more_needed = 0; -+ -+ return more_needed; -+} -+ -+/** -+ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline -+ * -+ * Search pending transactions in the start-split pending state and queue them. -+ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4). -+ * Note: we specifically don't do isochronous OUT transactions first because better -+ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT. -+ */ -+static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels) -+{ -+ int n; -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; -+ if ((hfnum.b.frnum & 0x7) == 5) -+ return; -+ for (n = 0; n < num_channels; n++) { -+ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) { -+ /* Check to see if any other transactions are using this TT */ -+ if(!fiq_fsm_tt_in_use(st, num_channels, n)) { -+ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -+ fiq_print(FIQDBG_INT, st, "NEXTPER "); -+ fiq_fsm_restart_channel(st, n, 0); -+ break; -+ } -+ } -+ } -+ for (n = 0; n < num_channels; n++) { -+ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) { -+ if (!fiq_fsm_tt_in_use(st, num_channels, n)) { -+ fiq_print(FIQDBG_INT, st, "NEXTISO "); -+ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ fiq_fsm_restart_channel(st, n, 0); -+ break; -+ } -+ } -+ } -+} -+ -+/** -+ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data -+ * @state: Pointer to fiq_state -+ * @n: Channel transaction is active on -+ * @hcint: Copy of host channel interrupt register -+ * -+ * Returns 0 if there are no more transactions for this HC to do, 1 -+ * otherwise. -+ */ -+static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint) -+{ -+ struct fiq_channel_state *st = &state->channel[n]; -+ int xfer_len = 0, nrpackets = 0; -+ hcdma_data_t hcdma; -+ fiq_print(FIQDBG_INT, state, "HSISO %02d", n); -+ -+ xfer_len = fiq_get_xfer_len(state, n); -+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len; -+ -+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32; -+ -+ st->hs_isoc_info.index++; -+ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) { -+ return 0; -+ } -+ -+ /* grab the next DMA address offset from the array */ -+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset; -+ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); -+ -+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as -+ * the core needs to be told to send the correct number. Caution: for IN transfers, -+ * this is always set to the maximum size of the endpoint. */ -+ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length; -+ /* Integer divide in a FIQ: fun. FIXME: make this not suck */ -+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; -+ if (nrpackets == 0) -+ nrpackets = 1; -+ st->hcchar_copy.b.multicnt = nrpackets; -+ st->hctsiz_copy.b.pktcnt = nrpackets; -+ -+ /* Initial PID also needs to be set */ -+ if (st->hcchar_copy.b.epdir == 0) { -+ st->hctsiz_copy.b.xfersize = xfer_len; -+ switch (st->hcchar_copy.b.multicnt) { -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_MDATA; -+ break; -+ } -+ -+ } else { -+ switch (st->hcchar_copy.b.multicnt) { -+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA1; -+ break; -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA2; -+ break; -+ } -+ } -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32); -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32); -+ /* Channel is enabled on hcint handler exit */ -+ fiq_print(FIQDBG_INT, state, "HSISOOUT"); -+ return 1; -+} -+ -+ -+/** -+ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler -+ * @state: Pointer to the state struct passed from banked FIQ mode registers. -+ * @num_channels: set according to the DWC hardware configuration -+ * -+ * The SOF handler in FSM mode has two functions -+ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's -+ * nothing to do -+ * 2. Advance certain FSM states that require either a microframe delay, or a microframe -+ * of holdoff. -+ * -+ * The second part is architecture-specific to mach-bcm2835 - -+ * a sane interrupt controller would have a mask register for ARM interrupt sources -+ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt -+ * number (USB) can be enabled. This means that certain parts of the USB specification -+ * that require "wait a little while, then issue another packet" cannot be fulfilled with -+ * the timing granularity required to achieve optimal throughout. The workaround is to use -+ * the SOF "timer" (125uS) to perform this task. -+ */ -+static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels) -+{ -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) }; -+ int n; -+ -+ for (n = 0; n < num_channels; n++) { -+ switch (state->channel[n].fsm) { -+ -+ case FIQ_NP_SSPLIT_RETRY: -+ case FIQ_NP_IN_CSPLIT_RETRY: -+ case FIQ_NP_OUT_CSPLIT_RETRY: -+ fiq_fsm_restart_channel(state, n, 0); -+ break; -+ -+ case FIQ_HS_ISOC_SLEEPING: -+ state->channel[n].fsm = FIQ_HS_ISOC_TURBO; -+ fiq_fsm_restart_channel(state, n, 0); -+ break; -+ -+ case FIQ_PER_SSPLIT_QUEUED: -+ if ((hfnum.b.frnum & 0x7) == 5) -+ break; -+ if (!fiq_fsm_tt_in_use(state, num_channels, n)) { -+ fiq_print(FIQDBG_INT, state, "SOF GO %01d", n); -+ fiq_fsm_restart_channel(state, n, 0); -+ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -+ } -+ break; -+ -+ case FIQ_PER_ISO_OUT_PENDING: -+ /* Ordinarily, this should be poked after the SSPLIT -+ * complete interrupt for a competing transfer on the same -+ * TT. Doesn't happen for aborted transactions though. -+ */ -+ if ((hfnum.b.frnum & 0x7) >= 5) -+ break; -+ if (!fiq_fsm_tt_in_use(state, num_channels, n)) { -+ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt -+ * that caused this. -+ */ -+ fiq_fsm_restart_channel(state, n, 0); -+ fiq_print(FIQDBG_INT, state, "SOF ISOC"); -+ if (state->channel[n].nrpackets == 1) { -+ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST; -+ } else { -+ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ } -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_WAIT: -+ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt -+ * occurred when the bus transaction occurred. The SOF interrupt reversal bug -+ * will utterly bugger this up though. -+ */ -+ if (hfnum.b.frnum != state->channel[n].expected_uframe) { -+ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n); -+ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL; -+ fiq_fsm_restart_channel(state, n, 0); -+ fiq_fsm_start_next_periodic(state, num_channels); -+ -+ } -+ break; -+ -+ default: -+ break; -+ } -+ } -+ -+ if ((hfnum.b.frnum & 0x7) == 1) { -+ /* We cannot issue csplits for transactions in the last frame past (n+1).1 -+ * Check to see if there are any transactions that are stale. -+ * Boot them out. -+ */ -+ for (n = 0; n < num_channels; n++) { -+ switch (state->channel[n].fsm) { -+ case FIQ_PER_CSPLIT_WAIT: -+ case FIQ_PER_CSPLIT_NYET1: -+ case FIQ_PER_CSPLIT_POLL: -+ case FIQ_PER_CSPLIT_LAST: -+ /* Check if we are no longer in the same full-speed frame. */ -+ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) < -+ (hfnum.b.frnum & ~0x7)) -+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -+ break; -+ default: -+ break; -+ } -+ } -+ -+ } -+ -+ if (!state->kick_np_queues && -+ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) { -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ -+ -+/** -+ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler -+ * @state: Pointer to the FIQ state struct -+ * @num_channels: Number of channels as per hardware config -+ * @n: channel for which HAINT(i) was raised -+ * -+ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well. -+ */ -+static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n) -+{ -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ hcchar_data_t hcchar; -+ int handled = 0; -+ int restart = 0; -+ int last_csplit = 0; -+ int start_next_periodic = 0; -+ struct fiq_channel_state *st = &state->channel[n]; -+ hfnum_data_t hfnum; -+ -+ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT); -+ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK); -+ -+ if (st->fsm != FIQ_PASSTHROUGH) { -+ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm); -+ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32); -+ } -+ -+ switch (st->fsm) { -+ -+ case FIQ_PASSTHROUGH: -+ case FIQ_DEQUEUE_ISSUED: -+ /* doesn't belong to us, kick it upstairs */ -+ break; -+ -+ /* Non-periodic state groups */ -+ case FIQ_NP_SSPLIT_STARTED: -+ case FIQ_NP_SSPLIT_RETRY: -+ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */ -+ if (hcint.b.ack) { -+ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction -+ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood. -+ */ -+ if(st->hcchar_copy.b.epdir == 1) -+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; -+ else -+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; -+ st->nr_errors = 0; -+ handled = 1; -+ fiq_fsm_setup_csplit(state, n); -+ } else if (hcint.b.nak) { -+ // No buffer space in TT. Retry on a uframe boundary. -+ st->fsm = FIQ_NP_SSPLIT_RETRY; -+ handled = 1; -+ } else if (hcint.b.xacterr) { -+ // The only other one we care about is xacterr. This implies HS bus error - retry. -+ st->nr_errors++; -+ st->fsm = FIQ_NP_SSPLIT_RETRY; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ restart = 1; -+ } -+ } else { -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ handled = 0; -+ restart = 0; -+ } -+ break; -+ -+ case FIQ_NP_IN_CSPLIT_RETRY: -+ /* Received a CSPLIT done interrupt. -+ * Expected Data/NAK/STALL/NYET for IN. -+ */ -+ if (hcint.b.xfercomp) { -+ /* For IN, data is present. */ -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nak) { -+ /* no endpoint data. Punt it upstairs */ -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nyet) { -+ /* CSPLIT NYET - retry on a uframe boundary. */ -+ handled = 1; -+ st->nr_errors = 0; -+ } else if (hcint.b.datatglerr) { -+ /* data toggle errors do not set the xfercomp bit. */ -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ } else if (hcint.b.xacterr) { -+ /* HS error. Retry immediate */ -+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ restart = 1; -+ } -+ } else if (hcint.b.stall) { -+ /* A STALL implies either a LS bus error or a genuine STALL. */ -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ } else { -+ /* Hardware bug. It's possible in some cases to -+ * get a channel halt with nothing else set when -+ * the response was a NYET. Treat as local 3-strikes retry. -+ */ -+ hcint_data_t hcint_test = hcint; -+ hcint_test.b.chhltd = 0; -+ if (!hcint_test.d32) { -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ } -+ } else { -+ /* Bail out if something unexpected happened */ -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } -+ } -+ break; -+ -+ case FIQ_NP_OUT_CSPLIT_RETRY: -+ /* Received a CSPLIT done interrupt. -+ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/ -+ if (hcint.b.xfercomp) { -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nak) { -+ // The HCD will implement the holdoff on frame boundaries. -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nyet) { -+ // Hub still processing. -+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; -+ handled = 1; -+ st->nr_errors = 0; -+ //restart = 1; -+ } else if (hcint.b.xacterr) { -+ /* HS error. retry immediate */ -+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ restart = 1; -+ } -+ } else if (hcint.b.stall) { -+ /* LS bus error or genuine stall */ -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ } else { -+ /* -+ * Hardware bug. It's possible in some cases to get a -+ * channel halt with nothing else set when the response was a NYET. -+ * Treat as local 3-strikes retry. -+ */ -+ hcint_data_t hcint_test = hcint; -+ hcint_test.b.chhltd = 0; -+ if (!hcint_test.d32) { -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ } -+ } else { -+ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it. -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } -+ } -+ break; -+ -+ /* Periodic split states (except isoc out) */ -+ case FIQ_PER_SSPLIT_STARTED: -+ /* Expect an ACK or failure for SSPLIT */ -+ if (hcint.b.ack) { -+ /* -+ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs. -+ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1 -+ * point for microframe n-3, the packet will not appear on the bus until microframe n. -+ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus -+ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1 -+ * coincident with SOF for n+1. -+ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place. -+ * These appear to be caused by timing/clock crossing bugs within the core itself. -+ * State machine workaround. -+ */ -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ fiq_fsm_setup_csplit(state, n); -+ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct -+ * time. If not, then we're in the next SOF. -+ */ -+ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) { -+ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n); -+ st->expected_uframe = hfnum.b.frnum; -+ st->fsm = FIQ_PER_CSPLIT_WAIT; -+ } else { -+ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n); -+ /* For isochronous IN endpoints, -+ * we need to hold off if we are expecting a lot of data */ -+ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) { -+ start_next_periodic = 1; -+ } -+ /* Danger will robinson: we are in a broken state. If our first interrupt after -+ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable -+ * lag. Unmask the NYET interrupt. -+ */ -+ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; -+ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1; -+ restart = 1; -+ } -+ handled = 1; -+ } else if (hcint.b.xacterr) { -+ /* 3-strikes retry is enabled, we have hit our max nr_errors */ -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ start_next_periodic = 1; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ start_next_periodic = 1; -+ } -+ /* We can now queue the next isochronous OUT transaction, if one is pending. */ -+ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) { -+ fiq_print(FIQDBG_INT, state, "NEXTISO "); -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_NYET1: -+ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET, -+ * we are too late and the TT has dropped its CSPLIT fifo. -+ */ -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ start_next_periodic = 1; -+ if (hcint.b.nak) { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } else if (hcint.b.xfercomp) { -+ fiq_increment_dma_buf(state, num_channels, n); -+ st->fsm = FIQ_PER_CSPLIT_POLL; -+ st->nr_errors = 0; -+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { -+ handled = 1; -+ restart = 1; -+ if (!last_csplit) -+ start_next_periodic = 0; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } else if (hcint.b.nyet) { -+ /* Doh. Data lost. */ -+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_BROKEN_NYET1: -+ /* -+ * we got here because our host channel is in the delayed-interrupt -+ * state and we cannot take a NYET interrupt any later than when it -+ * occurred. Disable then re-enable the channel if this happens to force -+ * CSPLITs to occur at the right time. -+ */ -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n); -+ if (hcint.b.nak) { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ start_next_periodic = 1; -+ } else if (hcint.b.xfercomp) { -+ fiq_increment_dma_buf(state, num_channels, n); -+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { -+ st->fsm = FIQ_PER_CSPLIT_POLL; -+ handled = 1; -+ restart = 1; -+ start_next_periodic = 1; -+ /* Reload HCTSIZ for the next transfer */ -+ fiq_fsm_reload_hctsiz(state, n); -+ if (!last_csplit) -+ start_next_periodic = 0; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } else if (hcint.b.nyet) { -+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; -+ start_next_periodic = 1; -+ } else if (hcint.b.xacterr) { -+ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/ -+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; -+ } else { -+ fiq_print(FIQDBG_INT, state, "TOGGLES"); -+ BUG(); -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_POLL: -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ start_next_periodic = 1; -+ if (hcint.b.nak) { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } else if (hcint.b.xfercomp) { -+ fiq_increment_dma_buf(state, num_channels, n); -+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { -+ handled = 1; -+ restart = 1; -+ /* Reload HCTSIZ for the next transfer */ -+ fiq_fsm_reload_hctsiz(state, n); -+ if (!last_csplit) -+ start_next_periodic = 0; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } else if (hcint.b.nyet) { -+ /* Are we a NYET after the first data packet? */ -+ if (st->nrpackets == 0) { -+ st->fsm = FIQ_PER_CSPLIT_NYET1; -+ handled = 1; -+ restart = 1; -+ } else { -+ /* We got a NYET when polling CSPLITs. Can happen -+ * if our heuristic fails, or if someone disables us -+ * for any significant length of time. -+ */ -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } -+ } else if (hcint.b.xacterr) { -+ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/ -+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; -+ } else if (hcint.b.datatglerr) { -+ fiq_print(FIQDBG_INT, state, "TOGGLES"); -+ BUG(); -+ } else { -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ } -+ break; -+ -+ case FIQ_HS_ISOC_TURBO: -+ if (fiq_fsm_update_hs_isoc(state, n, hcint)) { -+ /* more transactions to come */ -+ handled = 1; -+ restart = 1; -+ fiq_print(FIQDBG_INT, state, "HSISO M "); -+ } else { -+ st->fsm = FIQ_HS_ISOC_DONE; -+ fiq_print(FIQDBG_INT, state, "HSISO F "); -+ } -+ break; -+ -+ case FIQ_HS_ISOC_ABORTED: -+ /* This abort is called by the driver rewriting the state mid-transaction -+ * which allows the dequeue mechanism to work more effectively. -+ */ -+ break; -+ -+ case FIQ_PER_ISO_OUT_ACTIVE: -+ if (hcint.b.ack) { -+ if(fiq_iso_out_advance(state, num_channels, n)) { -+ /* last OUT transfer */ -+ st->fsm = FIQ_PER_ISO_OUT_LAST; -+ /* -+ * Assuming the periodic FIFO in the dwc core -+ * actually does its job properly, we can queue -+ * the next ssplit now and in theory, the wire -+ * transactions will be in-order. -+ */ -+ // No it doesn't. It appears to process requests in host channel order. -+ //start_next_periodic = 1; -+ } -+ handled = 1; -+ restart = 1; -+ } else { -+ /* -+ * Isochronous transactions carry on regardless. Log the error -+ * and continue. -+ */ -+ //explode += 1; -+ st->nr_errors++; -+ if(fiq_iso_out_advance(state, num_channels, n)) { -+ st->fsm = FIQ_PER_ISO_OUT_LAST; -+ //start_next_periodic = 1; -+ } -+ handled = 1; -+ restart = 1; -+ } -+ break; -+ -+ case FIQ_PER_ISO_OUT_LAST: -+ if (hcint.b.ack) { -+ /* All done here */ -+ st->fsm = FIQ_PER_ISO_OUT_DONE; -+ } else { -+ st->fsm = FIQ_PER_ISO_OUT_DONE; -+ st->nr_errors++; -+ } -+ start_next_periodic = 1; -+ break; -+ -+ case FIQ_PER_SPLIT_TIMEOUT: -+ /* SOF kicked us because we overran. */ -+ start_next_periodic = 1; -+ break; -+ -+ default: -+ break; -+ } -+ -+ if (handled) { -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32); -+ } else { -+ /* Copy the regs into the state so the IRQ knows what to do */ -+ st->hcint_copy.d32 = hcint.d32; -+ } -+ -+ if (restart) { -+ /* Restart always implies handled. */ -+ if (restart == 2) { -+ /* For complete-split INs, the show must go on. -+ * Force a channel restart */ -+ fiq_fsm_restart_channel(state, n, 1); -+ } else { -+ fiq_fsm_restart_channel(state, n, 0); -+ } -+ } -+ if (start_next_periodic) { -+ fiq_fsm_start_next_periodic(state, num_channels); -+ } -+ if (st->fsm != FIQ_PASSTHROUGH) -+ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm); -+ -+ return handled; -+} -+ -+ -+/** -+ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ -+ * @state: pointer to state struct passed from the banked FIQ mode registers. -+ * @num_channels: set according to the DWC hardware configuration -+ * @dma: pointer to DMA bounce buffers for split transaction slots -+ * -+ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode -+ * inside an EHCI or similar host controller regarding split transactions. The DWC core -+ * interrupts each and every time a split transaction packet is received or sent successfully. -+ * This results in either an interrupt storm when everything is working "properly", or -+ * the interrupt latency of the system in general breaks time-sensitive periodic split -+ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ -+ * solves these problems. -+ * -+ * Return: void -+ */ -+void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels) -+{ -+ gintsts_data_t gintsts, gintsts_handled; -+ gintmsk_data_t gintmsk; -+ //hfnum_data_t hfnum; -+ haint_data_t haint, haint_handled; -+ haintmsk_data_t haintmsk; -+ int kick_irq = 0; -+ -+ gintsts_handled.d32 = 0; -+ haint_handled.d32 = 0; -+ -+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); -+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); -+ gintsts.d32 &= gintmsk.d32; -+ -+ if (gintsts.b.sofintr) { -+ /* For FSM mode, SOF is required to keep the state machine advance for -+ * certain stages of the periodic pipeline. It's death to mask this -+ * interrupt in that case. -+ */ -+ -+ if (!fiq_fsm_do_sof(state, num_channels)) { -+ /* Kick IRQ once. Queue advancement means that all pending transactions -+ * will get serviced when the IRQ finally executes. -+ */ -+ if (state->gintmsk_saved.b.sofintr == 1) -+ kick_irq |= 1; -+ state->gintmsk_saved.b.sofintr = 0; -+ } -+ gintsts_handled.b.sofintr = 1; -+ } -+ -+ if (gintsts.b.hcintr) { -+ int i; -+ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT); -+ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK); -+ haint.d32 &= haintmsk.d32; -+ haint_handled.d32 = 0; -+ for (i=0; ihaintmsk_saved.b2.chint &= ~(1 << i); -+ } else { -+ /* do_hcintr cleaned up after itself, but clear haint */ -+ haint_handled.b2.chint |= (1 << i); -+ } -+ } -+ } -+ -+ if (haint_handled.b2.chint) { -+ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32); -+ } -+ -+ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) { -+ /* -+ * This is necessary to avoid multiple retriggers of the MPHI in the case -+ * where interrupts are held off and HCINTs start to pile up. -+ * Only wake up the IRQ if a new interrupt came in, was not handled and was -+ * masked. -+ */ -+ haintmsk.d32 &= state->haintmsk_saved.d32; -+ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32); -+ kick_irq |= 1; -+ } -+ /* Top-Level interrupt - always handled because it's level-sensitive */ -+ gintsts_handled.b.hcintr = 1; -+ } -+ -+ -+ /* Clear the bits in the saved register that were not handled but were triggered. */ -+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); -+ -+ /* FIQ didn't handle something - mask has changed - write new mask */ -+ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) { -+ gintmsk.d32 &= state->gintmsk_saved.d32; -+ gintmsk.b.sofintr = 1; -+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); -+// fiq_print(FIQDBG_INT, state, "KICKGINT"); -+// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32); -+// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32); -+ kick_irq |= 1; -+ } -+ -+ if (gintsts_handled.d32) { -+ /* Only applies to edge-sensitive bits in GINTSTS */ -+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); -+ } -+ -+ /* We got an interrupt, didn't handle it. */ -+ if (kick_irq) { -+ state->mphi_int_count++; -+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); -+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); -+ -+ } -+ state->fiq_done++; -+ mb(); -+} -+ -+ -+/** -+ * dwc_otg_fiq_nop() - FIQ "lite" -+ * @state: pointer to state struct passed from the banked FIQ mode registers. -+ * -+ * The "nop" handler does not intervene on any interrupts other than SOF. -+ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals -+ * with non-periodic/periodic queues) needs to be kicked. -+ * -+ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second. -+ * -+ * Return: void -+ */ -+void notrace dwc_otg_fiq_nop(struct fiq_state *state) -+{ -+ gintsts_data_t gintsts, gintsts_handled; -+ gintmsk_data_t gintmsk; -+ hfnum_data_t hfnum; -+ -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); -+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); -+ gintsts.d32 &= gintmsk.d32; -+ gintsts_handled.d32 = 0; -+ -+ if (gintsts.b.sofintr) { -+ if (!state->kick_np_queues && -+ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) { -+ /* SOF handled, no work to do, just ACK interrupt */ -+ gintsts_handled.b.sofintr = 1; -+ } else { -+ /* Kick IRQ */ -+ state->gintmsk_saved.b.sofintr = 0; -+ } -+ } -+ -+ /* Reset handled interrupts */ -+ if(gintsts_handled.d32) { -+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); -+ } -+ -+ /* Clear the bits in the saved register that were not handled but were triggered. */ -+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); -+ -+ /* We got an interrupt, didn't handle it and want to mask it */ -+ if (~(state->gintmsk_saved.d32)) { -+ state->mphi_int_count++; -+ gintmsk.d32 &= state->gintmsk_saved.d32; -+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); -+ /* Force a clear before another dummy send */ -+ FIQ_WRITE(state->mphi_regs.intstat, (1<<29)); -+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); -+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); -+ -+ } -+ state->fiq_done++; -+ mb(); -+} -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -new file mode 100644 -index 0000000..716e921 ---- /dev/null -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -@@ -0,0 +1,349 @@ -+/* -+ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions -+ * -+ * Copyright (c) 2013 Raspberry Pi Foundation -+ * -+ * Author: Jonathan Bell -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Raspberry Pi nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This FIQ implements functionality that performs split transactions on -+ * the dwc_otg hardware without any outside intervention. A split transaction -+ * is "queued" by nominating a specific host channel to perform the entirety -+ * of a split transaction. This FIQ will then perform the microframe-precise -+ * scheduling required in each phase of the transaction until completion. -+ * -+ * The FIQ functionality has been surgically implanted into the Synopsys -+ * vendor-provided driver. -+ * -+ */ -+ -+#ifndef DWC_OTG_FIQ_FSM_H_ -+#define DWC_OTG_FIQ_FSM_H_ -+ -+#include "dwc_otg_regs.h" -+#include "dwc_otg_cil.h" -+#include "dwc_otg_hcd.h" -+#include -+#include -+#include -+#include -+ -+#if 0 -+#define FLAME_ON(x) \ -+do { \ -+ int gpioreg; \ -+ \ -+ gpioreg = readl(__io_address(0x20200000+0x8)); \ -+ gpioreg &= ~(7 << (x-20)*3); \ -+ gpioreg |= 0x1 << (x-20)*3; \ -+ writel(gpioreg, __io_address(0x20200000+0x8)); \ -+ \ -+ writel(1< 1, SOF wakes up the isochronous FSM */ -+ FIQ_HS_ISOC_SLEEPING = 24, -+ FIQ_HS_ISOC_DONE = 25, -+ FIQ_HS_ISOC_ABORTED = 26, -+ FIQ_DEQUEUE_ISSUED = 30, -+ FIQ_TEST = 32, -+}; -+ -+struct fiq_stack { -+ int magic1; -+ uint8_t stack[2048]; -+ int magic2; -+}; -+ -+ -+/** -+ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel) -+ * @index: Number of slots reported used for IN transactions / number of slots -+ * transmitted for an OUT transaction -+ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused) -+ * -+ * Split transaction transfers can have variable length depending on other bus -+ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore -+ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers -+ * can happen per-frame. -+ */ -+struct fiq_dma_info { -+ u8 index; -+ u8 slot_len[6]; -+}; -+ -+struct __attribute__((packed)) fiq_split_dma_slot { -+ u8 buf[188]; -+}; -+ -+struct fiq_dma_channel { -+ struct __attribute__((packed)) fiq_split_dma_slot index[6]; -+}; -+ -+struct fiq_dma_blob { -+ struct __attribute__((packed)) fiq_dma_channel channel[0]; -+}; -+ -+/** -+ * struct fiq_hs_isoc_info - USB2.0 isochronous data -+ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs. -+ * @nrframes: Total length of iso_frame_desc array -+ * @index: Current index (FIQ-maintained) -+ * -+ */ -+struct fiq_hs_isoc_info { -+ struct dwc_otg_hcd_iso_packet_desc *iso_desc; -+ unsigned int nrframes; -+ unsigned int index; -+}; -+ -+/** -+ * struct fiq_channel_state - FIQ state machine storage -+ * @fsm: Current state of the channel as understood by the FIQ -+ * @nr_errors: Number of transaction errors on this split-transaction -+ * @hub_addr: SSPLIT/CSPLIT destination hub -+ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub -+ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For -+ * split-IN, number of CSPLIT data packets that were received. -+ * @hcchar_copy: -+ * @hcsplt_copy: -+ * @hcintmsk_copy: -+ * @hctsiz_copy: Copies of the host channel registers. -+ * For use as scratch, or for returning state. -+ * -+ * The fiq_channel_state is state storage between interrupts for a host channel. The -+ * FSM state is stored here. Members of this structure must only be set up by the -+ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ -+ * has updated the state to either a COMPLETE state group or ABORT state group. -+ */ -+ -+struct fiq_channel_state { -+ enum fiq_fsm_state fsm; -+ unsigned int nr_errors; -+ unsigned int hub_addr; -+ unsigned int port_addr; -+ /* Hardware bug workaround: sometimes channel halt interrupts are -+ * delayed until the next SOF. Keep track of when we expected to get interrupted. */ -+ unsigned int expected_uframe; -+ /* in/out for communicating number of dma buffers used, or number of ISOC to do */ -+ unsigned int nrpackets; -+ struct fiq_dma_info dma_info; -+ struct fiq_hs_isoc_info hs_isoc_info; -+ /* Copies of HC registers - in/out communication from/to IRQ handler -+ * and for ease of channel setup. A bit of mungeing is performed - for -+ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint. -+ */ -+ hcchar_data_t hcchar_copy; -+ hcsplt_data_t hcsplt_copy; -+ hcint_data_t hcint_copy; -+ hcintmsk_data_t hcintmsk_copy; -+ hctsiz_data_t hctsiz_copy; -+ hcdma_data_t hcdma_copy; -+}; -+ -+/** -+ * struct fiq_state - top-level FIQ state machine storage -+ * @mphi_regs: virtual address of the MPHI peripheral register file -+ * @dwc_regs_base: virtual address of the base of the DWC core register file -+ * @dma_base: physical address for the base of the DMA bounce buffers -+ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral -+ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled. -+ * Used for determining which interrupts fired to set off the IRQ handler. -+ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally. -+ * @np_count: Non-periodic transactions in the active queue -+ * @np_sent: Count of non-periodic transactions that have completed -+ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism, -+ * this is the next frame on which a SOF interrupt is required. Used to hold off -+ * passing SOF through to the driver until necessary. -+ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host -+ * channels configured into the core logic. -+ * -+ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub. -+ * It contains top-level state information. -+ */ -+struct fiq_state { -+ mphi_regs_t mphi_regs; -+ void *dwc_regs_base; -+ dma_addr_t dma_base; -+ struct fiq_dma_blob *fiq_dmab; -+ void *dummy_send; -+ gintmsk_data_t gintmsk_saved; -+ haintmsk_data_t haintmsk_saved; -+ int mphi_int_count; -+ unsigned int fiq_done; -+ unsigned int kick_np_queues; -+ unsigned int next_sched_frame; -+#ifdef FIQ_DEBUG -+ char * buffer; -+ unsigned int bufsiz; -+#endif -+ struct fiq_channel_state channel[0]; -+}; -+ -+extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n); -+ -+extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels); -+ -+extern void dwc_otg_fiq_nop(struct fiq_state *state); -+ -+#endif /* DWC_OTG_FIQ_FSM_H_ */ -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S -new file mode 100644 -index 0000000..8cfe364 ---- /dev/null -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S -@@ -0,0 +1,81 @@ -+/* -+ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ -+ * -+ * Copyright (c) 2013 Raspberry Pi Foundation -+ * -+ * Author: Jonathan Bell -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Raspberry Pi nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include -+#include -+ -+ -+.text -+ -+.global _dwc_otg_fiq_stub_end; -+ -+/** -+ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow -+ * a C-style function call with arguments from the FIQ banked registers. -+ * r0 = &hcd->fiq_state -+ * r1 = &hcd->num_channels -+ * r2 = &hcd->dma_buffers -+ * Tramples: r0, r1, r2, r4, fp, ip -+ */ -+ -+ENTRY(_dwc_otg_fiq_stub) -+ /* Stash unbanked regs - SP will have been set up for us */ -+ mov ip, sp; -+ stmdb sp!, {r0-r12, lr}; -+#ifdef FIQ_DEBUG -+ // Cycle profiling - read cycle counter at start -+ mrc p15, 0, r5, c15, c12, 1; -+#endif -+ /* r11 = fp, don't trample it */ -+ mov r4, fp; -+ /* set EABI frame size */ -+ sub fp, ip, #512; -+ -+ /* for fiq NOP mode - just need state */ -+ mov r0, r8; -+ /* r9 = num_channels */ -+ mov r1, r9; -+ /* r10 = struct *dma_bufs */ -+// mov r2, r10; -+ -+ /* r4 = &fiq_c_function */ -+ blx r4; -+#ifdef FIQ_DEBUG -+ mrc p15, 0, r4, c15, c12, 1; -+ subs r5, r5, r4; -+ // r5 is now the cycle count time for executing the FIQ. Store it somewhere? -+#endif -+ ldmia sp!, {r0-r12, lr}; -+ subs pc, lr, #4; -+_dwc_otg_fiq_stub_end: -+END(_dwc_otg_fiq_stub) -+ -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index 22300f0..e67437c 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -@@ -45,9 +45,10 @@ - - #include "dwc_otg_hcd.h" - #include "dwc_otg_regs.h" --#include "dwc_otg_mphi_fix.h" -+#include "dwc_otg_fiq_fsm.h" - --extern bool microframe_schedule, nak_holdoff_enable; -+extern bool microframe_schedule; -+extern uint16_t fiq_fsm_mask, nak_holdoff; - - //#define DEBUG_HOST_CHANNELS - #ifdef DEBUG_HOST_CHANNELS -@@ -57,12 +58,6 @@ static int last_sel_trans_num_avail_hc_at_start = 0; - static int last_sel_trans_num_avail_hc_at_end = 0; - #endif /* DEBUG_HOST_CHANNELS */ - --extern int g_next_sched_frame, g_np_count, g_np_sent; -- --extern haint_data_t haint_saved; --extern hcintmsk_data_t hcintmsk_saved[MAX_EPS_CHANNELS]; --extern hcint_data_t hcint_saved[MAX_EPS_CHANNELS]; --extern gintsts_data_t ginsts_saved; - - dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) - { -@@ -295,7 +290,7 @@ static int32_t dwc_otg_hcd_disconnect_cb(void *p) - */ - dwc_otg_hcd->flags.b.port_connect_status_change = 1; - dwc_otg_hcd->flags.b.port_connect_status = 0; -- if(fiq_fix_enable) -+ if(fiq_enable) - local_fiq_disable(); - /* - * Shutdown any transfers in process by clearing the Tx FIFO Empty -@@ -392,20 +387,15 @@ static int32_t dwc_otg_hcd_disconnect_cb(void *p) - channel->qh = NULL; - } - } -- if(fiq_split_enable) { -+ if(fiq_fsm_enable) { - for(i=0; i < 128; i++) { - dwc_otg_hcd->hub_port[i] = 0; - } -- haint_saved.d32 = 0; -- for(i=0; i < MAX_EPS_CHANNELS; i++) { -- hcint_saved[i].d32 = 0; -- hcintmsk_saved[i].d32 = 0; -- } - } - - } - -- if(fiq_fix_enable) -+ if(fiq_enable) - local_fiq_enable(); - - if (dwc_otg_hcd->fops->disconnect) { -@@ -542,7 +532,7 @@ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, - } - #endif - intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk); -- if(!intr_mask.b.sofintr) needs_scheduling = 1; -+ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1; - if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) - /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */ - needs_scheduling = 0; -@@ -613,6 +603,7 @@ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, - if (urb_qtd->in_process && qh->channel) { - /* The QTD is in process (it has been assigned to a channel). */ - if (hcd->flags.b.port_connect_status) { -+ int n = qh->channel->hc_num; - /* - * If still connected (i.e. in host mode), halt the - * channel so it can be used for other transfers. If -@@ -620,10 +611,14 @@ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, - * written to halt the channel since the core is in - * device mode. - */ -+ /* In FIQ FSM mode, we need to shut down carefully. -+ * The FIQ may attempt to restart a disabled channel */ -+ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) { -+ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED; -+ } - dwc_otg_hc_halt(hcd->core_if, qh->channel, - DWC_OTG_HC_XFER_URB_DEQUEUE); - -- dwc_otg_hcd_release_port(hcd, qh); - } - } - -@@ -759,7 +754,6 @@ static void completion_tasklet_func(void *ptr) - - usb_hcd_giveback_urb(hcd->priv, urb, urb->status); - -- fiq_print(FIQDBG_PORTHUB, "COMPLETE"); - - DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); - } -@@ -854,6 +848,34 @@ void dwc_otg_hcd_power_up(void *ptr) - cil_hcd_start(core_if); - } - -+void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num) -+{ -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; -+ struct fiq_dma_blob *blob = hcd->fiq_dmab; -+ int i; -+ -+ st->fsm = FIQ_PASSTHROUGH; -+ st->hcchar_copy.d32 = 0; -+ st->hcsplt_copy.d32 = 0; -+ st->hcint_copy.d32 = 0; -+ st->hcintmsk_copy.d32 = 0; -+ st->hctsiz_copy.d32 = 0; -+ st->hcdma_copy.d32 = 0; -+ st->nr_errors = 0; -+ st->hub_addr = 0; -+ st->port_addr = 0; -+ st->expected_uframe = 0; -+ st->nrpackets = 0; -+ st->dma_info.index = 0; -+ for (i = 0; i < 6; i++) -+ st->dma_info.slot_len[i] = 255; -+ st->hs_isoc_info.index = 0; -+ st->hs_isoc_info.iso_desc = NULL; -+ st->hs_isoc_info.nrframes = 0; -+ -+ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128); -+} -+ - /** - * Frees secondary storage associated with the dwc_otg_hcd structure contained - * in the struct usb_hcd field. -@@ -907,6 +929,7 @@ static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd) - DWC_TIMER_FREE(dwc_otg_hcd->conn_timer); - DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet); - DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet); -+ DWC_FREE(dwc_otg_hcd->fiq_state); - - #ifdef DWC_DEV_SRPCAP - if (dwc_otg_hcd->core_if->power_down == 2 && -@@ -979,6 +1002,59 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) - channel); - } - -+ if (fiq_enable) { -+ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)); -+ if (!hcd->fiq_state) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__); -+ dwc_otg_hcd_free(hcd); -+ goto out; -+ } -+ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels))); -+ -+ for (i = 0; i < num_channels; i++) { -+ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH; -+ } -+ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16); -+ -+ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack)); -+ if (!hcd->fiq_stack) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__); -+ dwc_otg_hcd_free(hcd); -+ goto out; -+ } -+ hcd->fiq_stack->magic1 = 0xDEADBEEF; -+ hcd->fiq_stack->magic2 = 0xD00DFEED; -+ hcd->fiq_state->gintmsk_saved.d32 = ~0; -+ hcd->fiq_state->haintmsk_saved.b2.chint = ~0; -+ -+ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools -+ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels) -+ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some -+ * moderately readable array casts. -+ */ -+ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base); -+ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d", -+ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base, -+ sizeof(struct fiq_dma_channel) * num_channels); -+ -+ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024); -+ -+ /* pointer for debug in fiq_print */ -+ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab; -+ if (fiq_fsm_enable) { -+ int i; -+ for (i=0; i < hcd->core_if->core_params->host_channels; i++) { -+ dwc_otg_cleanup_fiq_channel(hcd, i); -+ } -+ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s", -+ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "", -+ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "", -+ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : ""); -+ } -+ } -+ - /* Initialize the Connection timeout timer. */ - hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", - dwc_otg_hcd_connect_timeout, 0); -@@ -1176,7 +1252,8 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - hc->do_split = 1; - hc->xact_pos = qtd->isoc_split_pos; - /* We don't need to do complete splits anymore */ -- if(fiq_split_enable) -+// if(fiq_fsm_enable) -+ if (0) - hc->complete_split = qtd->complete_split = 0; - else - hc->complete_split = qtd->complete_split; -@@ -1327,62 +1404,487 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - hc->qh = qh; - } - --/* --** Check the transaction to see if the port / hub has already been assigned for --** a split transaction --** --** Return 0 - Port is already in use --*/ --int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh) -+ -+/** -+ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ -+ * @qh: pointer to the endpoint's queue head -+ * -+ * Transaction start/end control flow is grafted onto the existing dwc_otg -+ * mechanisms, to avoid spaghettifying the functions more than they already are. -+ * This function's eligibility check is altered by debug parameter. -+ * -+ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction. -+ */ -+ -+int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh) - { -- uint32_t hub_addr, port_addr; -+ if (qh->do_split) { -+ switch (qh->ep_type) { -+ case UE_CONTROL: -+ case UE_BULK: -+ if (fiq_fsm_mask & (1 << 0)) -+ return 1; -+ break; -+ case UE_INTERRUPT: -+ case UE_ISOCHRONOUS: -+ if (fiq_fsm_mask & (1 << 1)) -+ return 1; -+ break; -+ default: -+ break; -+ } -+ } else if (qh->ep_type == UE_ISOCHRONOUS) { -+ if (fiq_fsm_mask & (1 << 2)) { -+ /* HS ISOCH support. We test for compatibility: -+ * - DWORD aligned buffers -+ * - Must be at least 2 transfers (otherwise pointless to use the FIQ) -+ * If yes, then the fsm enqueue function will handle the state machine setup. -+ */ -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs; -+ int nr_iso_frames = urb->packet_count; -+ int i; -+ uint32_t ptr; -+ -+ if (nr_iso_frames < 2) -+ return 0; -+ for (i = 0; i < nr_iso_frames; i++) { -+ ptr = urb->dma + iso_descs[i]->offset; -+ if (ptr & 0x3) { -+ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset." -+ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n", -+ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num); -+ return 0; -+ } -+ } -+ return 1; -+ } -+ } -+ return 0; -+} - -- if(!fiq_split_enable) -- return 0; -+/** -+ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers -+ * @hcd: Pointer to the dwc_otg_hcd struct -+ * @qh: Pointer to the endpoint's queue head -+ * -+ * Periodic split transactions are transmitted modulo 188 bytes. -+ * This necessitates slicing data up into buckets for isochronous out -+ * and fixing up the DMA address for all IN transfers. -+ * -+ * Returns 1 if the DMA bounce buffers have been used, 0 if the default -+ * HC buffer has been used. -+ */ -+int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh) -+ { -+ int i = 0; -+ uint32_t frame_length, nrslots, last_size; -+ uint8_t *ptr = NULL; -+ dwc_hc_t *hc = qh->channel; -+ struct fiq_dma_blob *blob; -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc; -+ -+ -+ for (i = 0; i < 6; i++) { -+ st->dma_info.slot_len[i] = 255; -+ } -+ st->dma_info.index = 0; -+ i = 0; -+ if (hc->ep_is_in) { -+ /* -+ * Set dma_regs to bounce buffer. FIQ will update the -+ * state depending on transaction progress. -+ */ -+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; -+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; -+ return 1; -+ } else { -+ if (qh->ep_type == UE_ISOCHRONOUS) { - -- hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); - -- if(hcd->hub_port[hub_addr] & (1 << port_addr)) -- { -- fiq_print(FIQDBG_PORTHUB, "H%dP%d:S%02d", hub_addr, port_addr, qh->skip_count); -+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ frame_length = frame_desc->length; - -- qh->skip_count++; -+ /* Virtual address for bounce buffers */ -+ blob = hcd->fiq_dmab; - -- if(qh->skip_count > 40000) -- { -- printk_once(KERN_ERR "Error: Having to skip port allocation"); -- local_fiq_disable(); -- BUG(); -+ ptr = qtd->urb->buf + frame_desc->offset; -+ nrslots = (frame_length + 187) / 188; -+ last_size = frame_length % 188; -+ //printk(KERN_INFO "len = %d nrslots = %d last_size=%d\n", frame_length, nrslots, last_size); -+ if (frame_length == 0) { -+ /* -+ * for isochronous transactions, we must still transmit a packet -+ * even if the length is zero. -+ */ -+ st->dma_info.slot_len[0] = 0; -+ st->nrpackets = 1; -+ } else { -+ do { -+ if (i < nrslots - 1) { -+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188); -+ st->dma_info.slot_len[i] = 188; -+ ptr += 188; -+ } else { -+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, last_size); -+ st->dma_info.slot_len[i] = last_size; -+ ptr += last_size; -+ } -+ i++; -+ } while (i <= nrslots - 1); -+ st->nrpackets = i; -+ } -+ ptr = qtd->urb->buf + frame_desc->offset; -+ if(DWC_MEMCMP(&blob->channel[hc->hc_num].index[0].buf[0], ptr, frame_length)) -+ BUG(); -+ /* Point the HC at the DMA address of the bounce buffers */ -+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; -+ /* Bugette: for some reason, memcpy corrupts the data in the bounce buffers. May be a -+ * cache coherency issue */ -+ //st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; -+ //ptr = qtd->urb->buf + frame_desc->offset; -+ st->hcdma_copy.d32 = (uint32_t) qtd->urb->dma + frame_desc->offset; -+ if (st->hcdma_copy.d32 & 0x3) -+ BUG(); -+ /* fixup xfersize to the actual packet size */ -+ st->hctsiz_copy.b.pid = 0; -+ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0]; -+ return 1; -+ } else { -+ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */ - return 0; - } -- return 1; - } -- else -- { -- qh->skip_count = 0; -- hcd->hub_port[hub_addr] |= 1 << port_addr; -- fiq_print(FIQDBG_PORTHUB, "H%dP%d:A %d", hub_addr, port_addr, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->pipe_info.ep_num); --#ifdef FIQ_DEBUG -- hcd->hub_port_alloc[hub_addr * 16 + port_addr] = dwc_otg_hcd_get_frame_number(hcd); --#endif -+} -+ -+/* -+ * Pushing a periodic request into the queue near the EOF1 point -+ * in a microframe causes erroneous behaviour (frmovrun) interrupt. -+ * Usually, the request goes out on the bus causing a transfer but -+ * the core does not transfer the data to memory. -+ * This guard interval (in number of 60MHz clocks) is required which -+ * must cater for CPU latency between reading the value and enabling -+ * the channel. -+ */ -+#define PERIODIC_FRREM_BACKOFF 1000 -+ -+int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -+{ -+ dwc_hc_t *hc = qh->channel; -+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ int frame; -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; -+ int xfer_len, nrpackets; -+ hcdma_data_t hcdma; -+ hfnum_data_t hfnum; -+ -+ if (st->fsm != FIQ_PASSTHROUGH) - return 0; -+ -+ st->nr_errors = 0; -+ -+ st->hcchar_copy.d32 = 0; -+ st->hcchar_copy.b.mps = hc->max_packet; -+ st->hcchar_copy.b.epdir = hc->ep_is_in; -+ st->hcchar_copy.b.devaddr = hc->dev_addr; -+ st->hcchar_copy.b.epnum = hc->ep_num; -+ st->hcchar_copy.b.eptype = hc->ep_type; -+ -+ st->hcintmsk_copy.b.chhltd = 1; -+ -+ frame = dwc_otg_hcd_get_frame_number(hcd); -+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; -+ -+ st->hcchar_copy.b.lspddev = 0; -+ /* Enable the channel later as a final register write. */ -+ -+ st->hcsplt_copy.d32 = 0; -+ -+ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs; -+ st->hs_isoc_info.nrframes = qtd->urb->packet_count; -+ /* grab the next DMA address offset from the array */ -+ st->hcdma_copy.d32 = qtd->urb->dma; -+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset; -+ -+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as -+ * the core needs to be told to send the correct number. Caution: for IN transfers, -+ * this is always set to the maximum size of the endpoint. */ -+ xfer_len = st->hs_isoc_info.iso_desc[0].length; -+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; -+ if (nrpackets == 0) -+ nrpackets = 1; -+ st->hcchar_copy.b.multicnt = nrpackets; -+ st->hctsiz_copy.b.pktcnt = nrpackets; -+ -+ /* Initial PID also needs to be set */ -+ if (st->hcchar_copy.b.epdir == 0) { -+ st->hctsiz_copy.b.xfersize = xfer_len; -+ switch (st->hcchar_copy.b.multicnt) { -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_MDATA; -+ break; -+ } -+ -+ } else { -+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; -+ switch (st->hcchar_copy.b.multicnt) { -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA1; -+ break; -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA2; -+ break; -+ } - } -+ -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); -+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); -+ local_fiq_disable(); -+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); -+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { -+ /* Prevent queueing near EOF1. Bad things happen if a periodic -+ * split transaction is queued very close to EOF. -+ */ -+ st->fsm = FIQ_HS_ISOC_SLEEPING; -+ } else { -+ st->fsm = FIQ_HS_ISOC_TURBO; -+ st->hcchar_copy.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ } -+ mb(); -+ st->hcchar_copy.b.chen = 0; -+ local_fiq_enable(); -+ return 0; - } --void dwc_otg_hcd_release_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh) -+ -+ -+/** -+ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state -+ * @hcd: Pointer to the dwc_otg_hcd struct -+ * @qh: Pointer to the endpoint's queue head -+ * -+ * This overrides the dwc_otg driver's normal method of queueing a transaction. -+ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup -+ * for the nominated host channel. -+ * -+ * For periodic transfers, it also peeks at the FIQ state to see if an immediate -+ * start is possible. If not, then the FIQ is left to start the transfer. -+ */ -+int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) - { -- uint32_t hub_addr, port_addr; -+ int start_immediate = 1, i; -+ hfnum_data_t hfnum; -+ dwc_hc_t *hc = qh->channel; -+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; -+ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */ -+ int hub_addr, port_addr, frame, uframe; -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; - -- if(!fiq_split_enable) -- return; -+ if (st->fsm != FIQ_PASSTHROUGH) -+ return 0; -+ st->nr_errors = 0; -+ -+ st->hcchar_copy.d32 = 0; -+ st->hcchar_copy.b.mps = hc->max_packet; -+ st->hcchar_copy.b.epdir = hc->ep_is_in; -+ st->hcchar_copy.b.devaddr = hc->dev_addr; -+ st->hcchar_copy.b.epnum = hc->ep_num; -+ st->hcchar_copy.b.eptype = hc->ep_type; -+ if (hc->ep_type & 0x1) { -+ if (hc->ep_is_in) -+ st->hcchar_copy.b.multicnt = 3; -+ else -+ /* Docs say set this to 1, but driver sets to 0! */ -+ st->hcchar_copy.b.multicnt = 0; -+ } else { -+ st->hcchar_copy.b.multicnt = 1; -+ st->hcchar_copy.b.oddfrm = 0; -+ } -+ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0; -+ /* Enable the channel later as a final register write. */ -+ -+ st->hcsplt_copy.d32 = 0; -+ if(qh->do_split) { -+ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); -+ st->hcsplt_copy.b.compsplt = 0; -+ st->hcsplt_copy.b.spltena = 1; -+ // XACTPOS is for isoc-out only but needs initialising anyway. -+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL; -+ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) { -+ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL. -+ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ -+ * will update as necessary. -+ */ -+ if (hc->xfer_len > 188) { -+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN; -+ } -+ } -+ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr; -+ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr; -+ st->hub_addr = hub_addr; -+ st->port_addr = port_addr; -+ } - -- hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); -+ st->hctsiz_copy.d32 = 0; -+ st->hctsiz_copy.b.dopng = 0; -+ st->hctsiz_copy.b.pid = hc->data_pid_start; - -- hcd->hub_port[hub_addr] &= ~(1 << port_addr); --#ifdef FIQ_DEBUG -- hcd->hub_port_alloc[hub_addr * 16 + port_addr] = -1; --#endif -- fiq_print(FIQDBG_PORTHUB, "H%dP%d:RO%d", hub_addr, port_addr, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->pipe_info.ep_num); -+ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { -+ hc->xfer_len = hc->max_packet; -+ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { -+ hc->xfer_len = 188; -+ } -+ st->hctsiz_copy.b.xfersize = hc->xfer_len; -+ -+ st->hctsiz_copy.b.pktcnt = 1; - -+ if (hc->ep_type & 0x1) { -+ /* -+ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers, -+ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array. -+ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt -+ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set -+ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ -+ * must not touch internal driver state. -+ */ -+ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) { -+ if (hc->align_buff) { -+ st->hcdma_copy.d32 = hc->align_buff; -+ } else { -+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); -+ } -+ } -+ } else { -+ if (hc->align_buff) { -+ st->hcdma_copy.d32 = hc->align_buff; -+ } else { -+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); -+ } -+ } -+ /* The FIQ depends upon no other interrupts being enabled except channel halt. -+ * Fixup channel interrupt mask. */ -+ st->hcintmsk_copy.d32 = 0; -+ st->hcintmsk_copy.b.chhltd = 1; -+ st->hcintmsk_copy.b.ahberr = 1; -+ -+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); -+ -+ local_fiq_disable(); -+ mb(); -+ -+ if (hc->ep_type & 0x1) { -+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); -+ frame = (hfnum.b.frnum & ~0x7) >> 3; -+ uframe = hfnum.b.frnum & 0x7; -+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { -+ /* Prevent queueing near EOF1. Bad things happen if a periodic -+ * split transaction is queued very close to EOF. -+ */ -+ start_immediate = 0; -+ } else if (uframe == 5) { -+ start_immediate = 0; -+ } else if (hc->ep_type == UE_ISOCHRONOUS) { -+ start_immediate = 0; -+ } else { -+ /* Search through all host channels to determine if a transaction -+ * is currently in progress */ -+ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) { -+ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH) -+ continue; -+ switch (hcd->fiq_state->channel[i].fsm) { -+ /* TT is reserved for channels that are in the middle of a periodic -+ * split transaction. -+ */ -+ case FIQ_PER_SSPLIT_STARTED: -+ case FIQ_PER_CSPLIT_WAIT: -+ case FIQ_PER_CSPLIT_NYET1: -+ case FIQ_PER_CSPLIT_POLL: -+ case FIQ_PER_ISO_OUT_ACTIVE: -+ case FIQ_PER_ISO_OUT_LAST: -+ if (hcd->fiq_state->channel[i].hub_addr == hub_addr && -+ hcd->fiq_state->channel[i].port_addr == port_addr) { -+ start_immediate = 0; -+ } -+ break; -+ default: -+ break; -+ } -+ if (!start_immediate) -+ break; -+ } -+ } -+ } -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem); -+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr); -+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); -+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); -+ switch (hc->ep_type) { -+ case UE_CONTROL: -+ case UE_BULK: -+ st->fsm = FIQ_NP_SSPLIT_STARTED; -+ break; -+ case UE_ISOCHRONOUS: -+ if (hc->ep_is_in) { -+ if (start_immediate) { -+ st->fsm = FIQ_PER_SSPLIT_STARTED; -+ } else { -+ st->fsm = FIQ_PER_SSPLIT_QUEUED; -+ } -+ } else { -+ if (start_immediate) { -+ /* Single-isoc OUT packets don't require FIQ involvement */ -+ if (st->nrpackets == 1) { -+ st->fsm = FIQ_PER_ISO_OUT_LAST; -+ } else { -+ st->fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ } -+ } else { -+ st->fsm = FIQ_PER_ISO_OUT_PENDING; -+ } -+ } -+ break; -+ case UE_INTERRUPT: -+ if (start_immediate) { -+ st->fsm = FIQ_PER_SSPLIT_STARTED; -+ } else { -+ st->fsm = FIQ_PER_SSPLIT_QUEUED; -+ } -+ default: -+ break; -+ } -+ if (start_immediate) { -+ /* Set the oddfrm bit as close as possible to actual queueing */ -+ frame = dwc_otg_hcd_get_frame_number(hcd); -+ st->expected_uframe = (frame + 1) & 0x3FFF; -+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; -+ st->hcchar_copy.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ } -+ mb(); -+ local_fiq_enable(); -+ return 0; - } - - -@@ -1399,16 +1901,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) - { - dwc_list_link_t *qh_ptr; - dwc_otg_qh_t *qh; -- dwc_otg_qtd_t *qtd; - int num_channels; - dwc_irqflags_t flags; - dwc_spinlock_t *channel_lock = hcd->channel_lock; - dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; - --#ifdef DEBUG_SOF -- DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); --#endif -- - #ifdef DEBUG_HOST_CHANNELS - last_sel_trans_num_per_scheduled = 0; - last_sel_trans_num_nonper_scheduled = 0; -@@ -1423,26 +1920,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) - - qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); - -- if(qh->do_split) { -- qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -- if(!(qh->ep_type == UE_ISOCHRONOUS && -- (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || -- qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END))) { -- if(dwc_otg_hcd_allocate_port(hcd, qh)) -- { -- qh_ptr = DWC_LIST_NEXT(qh_ptr); -- g_next_sched_frame = dwc_frame_num_inc(dwc_otg_hcd_get_frame_number(hcd), 1); -- continue; -- } -- } -- } -- - if (microframe_schedule) { - // Make sure we leave one channel for non periodic transactions. - DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); - if (hcd->available_host_channels <= 1) { - DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -- if(qh->do_split) dwc_otg_hcd_release_port(hcd, qh); - break; - } - hcd->available_host_channels--; -@@ -1478,27 +1960,24 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) - !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { - - qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); -- - /* - * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission - * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed - * cheeky devices that just hold off using NAKs - */ -- if (nak_holdoff_enable && qh->do_split) { -- if (qh->nak_frame != 0xffff && -- dwc_full_frame_num(qh->nak_frame) == -- dwc_full_frame_num(dwc_otg_hcd_get_frame_number(hcd))) { -- /* -- * Revisit: Need to avoid trampling on periodic scheduling. -- * Currently we are safe because g_np_count != g_np_sent whenever we hit this, -- * but if this behaviour is changed then periodic endpoints will get a slower -- * polling rate. -- */ -- g_next_sched_frame = ((qh->nak_frame + 8) & ~7) & DWC_HFNUM_MAX_FRNUM; -- qh_ptr = DWC_LIST_NEXT(qh_ptr); -- continue; -- } else { -- qh->nak_frame = 0xffff; -+ if (nak_holdoff && qh->do_split) { -+ if (qh->nak_frame != 0xffff) { -+ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8); -+ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd); -+ if (dwc_frame_num_le(frame, next_frame)) { -+ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) { -+ hcd->fiq_state->next_sched_frame = next_frame; -+ } -+ qh_ptr = DWC_LIST_NEXT(qh_ptr); -+ continue; -+ } else { -+ qh->nak_frame = 0xFFFF; -+ } - } - } - -@@ -1527,12 +2006,29 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) - &qh->qh_list_entry); - DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); - -- g_np_sent++; - - if (!microframe_schedule) - hcd->non_periodic_channels++; - } -- -+ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty, -+ * stop the FIQ from kicking us. We could potentially still have elements here if we -+ * ran out of host channels. -+ */ -+ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) { -+ hcd->fiq_state->kick_np_queues = 0; -+ } else { -+ /* For each entry remaining in the NP inactive queue, -+ * if this a NAK'd retransmit then don't set the kick flag. -+ */ -+ if(nak_holdoff) { -+ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) { -+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ if (qh->nak_frame == 0xFFFF) { -+ hcd->fiq_state->kick_np_queues = 1; -+ } -+ } -+ } -+ } - if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) - ret_val |= DWC_OTG_TRANSACTION_PERIODIC; - -@@ -1629,7 +2125,7 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) - hptxsts_data_t tx_status; - dwc_list_link_t *qh_ptr; - dwc_otg_qh_t *qh; -- int status; -+ int status = 0; - int no_queue_space = 0; - int no_fifo_space = 0; - -@@ -1658,27 +2154,34 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) - - // Do not send a split start transaction any later than frame .6 - // Note, we have to schedule a periodic in .5 to make it go in .6 -- if(fiq_split_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) -+ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) - { - qh_ptr = qh_ptr->next; -- g_next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; -+ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; - continue; - } - -- /* -- * Set a flag if we're queuing high-bandwidth in slave mode. -- * The flag prevents any halts to get into the request queue in -- * the middle of multiple high-bandwidth packets getting queued. -- */ -- if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { -- hcd->core_if->queuing_high_bandwidth = 1; -- } -- status = -- queue_transaction(hcd, qh->channel, -- tx_status.b.ptxfspcavail); -- if (status < 0) { -- no_fifo_space = 1; -- break; -+ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { -+ if (qh->do_split) -+ fiq_fsm_queue_split_transaction(hcd, qh); -+ else -+ fiq_fsm_queue_isoc_transaction(hcd, qh); -+ } else { -+ -+ /* -+ * Set a flag if we're queueing high-bandwidth in slave mode. -+ * The flag prevents any halts to get into the request queue in -+ * the middle of multiple high-bandwidth packets getting queued. -+ */ -+ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { -+ hcd->core_if->queuing_high_bandwidth = 1; -+ } -+ status = queue_transaction(hcd, qh->channel, -+ tx_status.b.ptxfspcavail); -+ if (status < 0) { -+ no_fifo_space = 1; -+ break; -+ } - } - - /* -@@ -1795,25 +2298,19 @@ static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) - qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, - qh_list_entry); - -- // Do not send a split start transaction any later than frame .5 -- // non periodic transactions will start immediately in this uframe -- if(fiq_split_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) -- { -- g_next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; -- break; -- } -- -- status = -- queue_transaction(hcd, qh->channel, -- tx_status.b.nptxfspcavail); -+ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { -+ fiq_fsm_queue_split_transaction(hcd, qh); -+ } else { -+ status = queue_transaction(hcd, qh->channel, -+ tx_status.b.nptxfspcavail); - -- if (status > 0) { -- more_to_do = 1; -- } else if (status < 0) { -- no_fifo_space = 1; -- break; -+ if (status > 0) { -+ more_to_do = 1; -+ } else if (status < 0) { -+ no_fifo_space = 1; -+ break; -+ } - } -- - /* Advance to next QH, skipping start-of-list entry. */ - hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; - if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.h b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h -index 0007fa1..da2986244 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.h -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h -@@ -40,6 +40,8 @@ - #include "dwc_otg_core_if.h" - #include "dwc_list.h" - #include "dwc_otg_cil.h" -+#include "dwc_otg_fiq_fsm.h" -+ - - /** - * @file -@@ -585,6 +587,12 @@ struct dwc_otg_hcd { - /** Frame List DMA address */ - dma_addr_t frame_list_dma; - -+ struct fiq_stack *fiq_stack; -+ struct fiq_state *fiq_state; -+ -+ /** Virtual address for split transaction DMA bounce buffers */ -+ struct fiq_dma_blob *fiq_dmab; -+ - #ifdef DEBUG - uint32_t frrem_samples; - uint64_t frrem_accum; -@@ -615,6 +623,9 @@ extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, - int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh); - void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh); - -+extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); -+extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh); -+extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num); - - /** @} */ - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -index 64d33a5..e5a27f4 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -@@ -34,7 +34,6 @@ - - #include "dwc_otg_hcd.h" - #include "dwc_otg_regs.h" --#include "dwc_otg_mphi_fix.h" - - #include - #include -@@ -47,33 +46,8 @@ extern bool microframe_schedule; - * This file contains the implementation of the HCD Interrupt handlers. - */ - --/* -- * Some globals to communicate between the FIQ and INTERRUPT -- */ -- --void * dummy_send; --mphi_regs_t c_mphi_regs; --volatile void *dwc_regs_base; - int fiq_done, int_done; - --gintsts_data_t gintsts_saved = {.d32 = 0}; --hcint_data_t hcint_saved[MAX_EPS_CHANNELS]; --hcintmsk_data_t hcintmsk_saved[MAX_EPS_CHANNELS]; --int split_out_xfersize[MAX_EPS_CHANNELS]; --haint_data_t haint_saved; -- --int g_next_sched_frame, g_np_count, g_np_sent; --static int mphi_int_count = 0 ; -- --hcchar_data_t nak_hcchar; --hctsiz_data_t nak_hctsiz; --hcsplt_data_t nak_hcsplt; --int nak_count; -- --int complete_sched[MAX_EPS_CHANNELS] = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}; --int split_start_frame[MAX_EPS_CHANNELS]; --int queued_port[MAX_EPS_CHANNELS]; -- - #ifdef FIQ_DEBUG - char buffer[1000*16]; - int wptr; -@@ -83,12 +57,10 @@ void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...) - va_list args; - char text[17]; - hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) }; -- unsigned long flags; - -- local_irq_save(flags); -- local_fiq_disable(); - if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR) - { -+ local_fiq_disable(); - snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937); - va_start(args, fmt); - vsnprintf(text+8, 9, fmt, args); -@@ -96,410 +68,21 @@ void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...) - - memcpy(buffer + wptr, text, 16); - wptr = (wptr + 16) % sizeof(buffer); -+ local_fiq_enable(); - } -- local_irq_restore(flags); - } - #endif - --void notrace fiq_queue_request(int channel, int odd_frame) --{ -- hcchar_data_t hcchar = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x0) }; -- hcsplt_data_t hcsplt = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x4) }; -- hctsiz_data_t hctsiz = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x10) }; -- -- if(hcsplt.b.spltena == 0) -- { -- fiq_print(FIQDBG_ERR, "SPLTENA "); -- BUG(); -- } -- -- if(hcchar.b.epdir == 1) -- { -- fiq_print(FIQDBG_SCHED, "IN Ch %d", channel); -- } -- else -- { -- hctsiz.b.xfersize = 0; -- fiq_print(FIQDBG_SCHED, "OUT Ch %d", channel); -- } -- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x10), hctsiz.d32); -- -- hcsplt.b.compsplt = 1; -- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x4), hcsplt.d32); -- -- // Send the Split complete -- hcchar.b.chen = 1; -- hcchar.b.oddfrm = odd_frame ? 1 : 0; -- -- // Post this for transmit on the next frame for periodic or this frame for non-periodic -- fiq_print(FIQDBG_SCHED, "SND_%s", odd_frame ? "ODD " : "EVEN"); -- -- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x0), hcchar.d32); --} -- --static int last_sof = -1; -- --/* --** Function to handle the start of frame interrupt, choose whether we need to do anything and --** therefore trigger the main interrupt --** --** returns int != 0 - interrupt has been handled --*/ --int diff; -- --int notrace fiq_sof_handle(hfnum_data_t hfnum) --{ -- int handled = 0; -- int i; -- -- // Just check that once we're running we don't miss a SOF -- /*if(last_sof != -1 && (hfnum.b.frnum != ((last_sof + 1) & 0x3fff))) -- { -- fiq_print(FIQDBG_ERR, "LASTSOF "); -- fiq_print(FIQDBG_ERR, "%4d%d ", last_sof / 8, last_sof & 7); -- fiq_print(FIQDBG_ERR, "%4d%d ", hfnum.b.frnum / 8, hfnum.b.frnum & 7); -- BUG(); -- }*/ -- -- // Only start remembering the last sof when the interrupt has been -- // enabled (we don't check the mask to come in here...) -- if(last_sof != -1 || FIQ_READ(dwc_regs_base + 0x18) & (1<<3)) -- last_sof = hfnum.b.frnum; -- -- for(i = 0; i < MAX_EPS_CHANNELS; i++) -- { -- if(complete_sched[i] != -1) -- { -- if(complete_sched[i] <= hfnum.b.frnum || (complete_sched[i] > 0x3f00 && hfnum.b.frnum < 0xf0)) -- { -- fiq_queue_request(i, hfnum.b.frnum & 1); -- complete_sched[i] = -1; -- } -- } -- -- if(complete_sched[i] != -1) -- { -- // This is because we've seen a split complete occur with no start... -- // most likely because missed the complete 0x3fff frames ago! -- -- diff = (hfnum.b.frnum + 0x3fff - complete_sched[i]) & 0x3fff ; -- if(diff > 32 && diff < 0x3f00) -- { -- fiq_print(FIQDBG_ERR, "SPLTMISS"); -- BUG(); -- } -- } -- } -- -- if(g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum)) -- { -- /* -- * If np_count != np_sent that means we need to queue non-periodic (bulk) packets this packet -- * g_next_sched_frame is the next frame we have periodic packets for -- * -- * if neither of these are required for this frame then just clear the interrupt -- */ -- handled = 1; -- -- } -- -- return handled; --} -- --int notrace port_id(hcsplt_data_t hcsplt) --{ -- return hcsplt.b.prtaddr + (hcsplt.b.hubaddr << 8); --} -- --int notrace fiq_hcintr_handle(int channel, hfnum_data_t hfnum) --{ -- hcchar_data_t hcchar = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x0) }; -- hcsplt_data_t hcsplt = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x4) }; -- hcint_data_t hcint = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x8) }; -- hcintmsk_data_t hcintmsk = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0xc) }; -- hctsiz_data_t hctsiz = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x10)}; -- -- hcint_saved[channel].d32 |= hcint.d32; -- hcintmsk_saved[channel].d32 = hcintmsk.d32; -- -- if(hcsplt.b.spltena) -- { -- fiq_print(FIQDBG_PORTHUB, "ph: %4x", port_id(hcsplt)); -- if(hcint.b.chhltd) -- { -- fiq_print(FIQDBG_SCHED, "CH HLT %d", channel); -- fiq_print(FIQDBG_SCHED, "%08x", hcint_saved[channel]); -- } -- if(hcint.b.stall || hcint.b.xacterr || hcint.b.bblerr || hcint.b.frmovrun || hcint.b.datatglerr) -- { -- queued_port[channel] = 0; -- fiq_print(FIQDBG_ERR, "CHAN ERR"); -- } -- if(hcint.b.xfercomp) -- { -- // Clear the port allocation and transmit anything also on this port -- queued_port[channel] = 0; -- fiq_print(FIQDBG_SCHED, "XFERCOMP"); -- } -- if(hcint.b.nak) -- { -- queued_port[channel] = 0; -- fiq_print(FIQDBG_SCHED, "NAK"); -- } -- if(hcint.b.ack && !hcsplt.b.compsplt) -- { -- int i; -- -- // Do not complete isochronous out transactions -- if(hcchar.b.eptype == 1 && hcchar.b.epdir == 0) -- { -- queued_port[channel] = 0; -- fiq_print(FIQDBG_SCHED, "ISOC_OUT"); -- } -- else -- { -- // Make sure we check the port / hub combination that we sent this split on. -- // Do not queue a second request to the same port -- for(i = 0; i < MAX_EPS_CHANNELS; i++) -- { -- if(port_id(hcsplt) == queued_port[i]) -- { -- fiq_print(FIQDBG_ERR, "PORTERR "); -- //BUG(); -- } -- } -- -- split_start_frame[channel] = (hfnum.b.frnum + 1) & ~7; -- -- // Note, the size of an OUT is in the start split phase, not -- // the complete split -- split_out_xfersize[channel] = hctsiz.b.xfersize; -- -- hcint_saved[channel].b.chhltd = 0; -- hcint_saved[channel].b.ack = 0; -- -- queued_port[channel] = port_id(hcsplt); -- -- if(hcchar.b.eptype & 1) -- { -- // Send the periodic complete in the same oddness frame as the ACK went... -- fiq_queue_request(channel, !(hfnum.b.frnum & 1)); -- // complete_sched[channel] = dwc_frame_num_inc(hfnum.b.frnum, 1); -- } -- else -- { -- // Schedule the split complete to occur later -- complete_sched[channel] = dwc_frame_num_inc(hfnum.b.frnum, 2); -- fiq_print(FIQDBG_SCHED, "ACK%04d%d", complete_sched[channel]/8, complete_sched[channel]%8); -- } -- } -- } -- if(hcint.b.nyet) -- { -- fiq_print(FIQDBG_ERR, "NYETERR1"); -- //BUG(); -- // Can transmit a split complete up to uframe .0 of the next frame -- if(hfnum.b.frnum <= dwc_frame_num_inc(split_start_frame[channel], 8)) -- { -- // Send it next frame -- if(hcchar.b.eptype & 1) // type 1 & 3 are interrupt & isoc -- { -- fiq_print(FIQDBG_SCHED, "NYT:SEND"); -- fiq_queue_request(channel, !(hfnum.b.frnum & 1)); -- } -- else -- { -- // Schedule non-periodic access for next frame (the odd-even bit doesn't effect NP) -- complete_sched[channel] = dwc_frame_num_inc(hfnum.b.frnum, 1); -- fiq_print(FIQDBG_SCHED, "NYT%04d%d", complete_sched[channel]/8, complete_sched[channel]%8); -- } -- hcint_saved[channel].b.chhltd = 0; -- hcint_saved[channel].b.nyet = 0; -- } -- else -- { -- queued_port[channel] = 0; -- fiq_print(FIQDBG_ERR, "NYETERR2"); -- //BUG(); -- } -- } -- } -- else -- { -- /* -- * If we have any of NAK, ACK, Datatlgerr active on a -- * non-split channel, the sole reason is to reset error -- * counts for a previously broken transaction. The FIQ -- * will thrash on NAK IN and ACK OUT in particular so -- * handle it "once" and allow the IRQ to do the rest. -- */ -- hcint.d32 &= hcintmsk.d32; -- if(hcint.b.nak) -- { -- hcintmsk.b.nak = 0; -- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0xc), hcintmsk.d32); -- } -- if (hcint.b.ack) -- { -- hcintmsk.b.ack = 0; -- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0xc), hcintmsk.d32); -- } -- } -- -- // Clear the interrupt, this will also clear the HAINT bit -- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x8), hcint.d32); -- return hcint_saved[channel].d32 == 0; --} -- --gintsts_data_t gintsts; --gintmsk_data_t gintmsk; --// triggered: The set of interrupts that were triggered --// handled: The set of interrupts that have been handled (no IRQ is --// required) --// keep: The set of interrupts we want to keep unmasked even though we --// want to trigger an IRQ to handle it (SOF and HCINTR) --gintsts_data_t triggered, handled, keep; --hfnum_data_t hfnum; -- --void __attribute__ ((naked)) notrace dwc_otg_hcd_handle_fiq(void) --{ -- -- /* entry takes care to store registers we will be treading on here */ -- asm __volatile__ ( -- "mov ip, sp ;" -- /* stash FIQ and normal regs */ -- "stmdb sp!, {r0-r12, lr};" -- /* !! THIS SETS THE FRAME, adjust to > sizeof locals */ -- "sub fp, ip, #512 ;" -- ); -- -- // Cannot put local variables at the beginning of the function -- // because otherwise 'C' will play with the stack pointer. any locals -- // need to be inside the following block -- do -- { -- fiq_done++; -- gintsts.d32 = FIQ_READ(dwc_regs_base + 0x14); -- gintmsk.d32 = FIQ_READ(dwc_regs_base + 0x18); -- hfnum.d32 = FIQ_READ(dwc_regs_base + 0x408); -- triggered.d32 = gintsts.d32 & gintmsk.d32; -- handled.d32 = 0; -- keep.d32 = 0; -- fiq_print(FIQDBG_INT, "FIQ "); -- fiq_print(FIQDBG_INT, "%08x", gintsts.d32); -- fiq_print(FIQDBG_INT, "%08x", gintmsk.d32); -- if(gintsts.d32) -- { -- // If port enabled -- if((FIQ_READ(dwc_regs_base + 0x440) & 0xf) == 0x5) -- { -- if(gintsts.b.sofintr) -- { -- if(fiq_sof_handle(hfnum)) -- { -- handled.b.sofintr = 1; /* Handled in FIQ */ -- } -- else -- { -- /* Keer interrupt unmasked */ -- keep.b.sofintr = 1; -- } -- { -- // Need to make sure the read and clearing of the SOF interrupt is as close as possible to avoid the possibility of missing -- // a start of frame interrupt -- gintsts_data_t gintsts = { .b.sofintr = 1 }; -- FIQ_WRITE((dwc_regs_base + 0x14), gintsts.d32); -- } -- } -- -- if(fiq_split_enable && gintsts.b.hcintr) -- { -- int i; -- haint_data_t haint; -- haintmsk_data_t haintmsk; -- -- haint.d32 = FIQ_READ(dwc_regs_base + 0x414); -- haintmsk.d32 = FIQ_READ(dwc_regs_base + 0x418); -- haint.d32 &= haintmsk.d32; -- haint_saved.d32 |= haint.d32; -- -- fiq_print(FIQDBG_INT, "hcintr"); -- fiq_print(FIQDBG_INT, "%08x", FIQ_READ(dwc_regs_base + 0x414)); -- -- // Go through each channel that has an enabled interrupt -- for(i = 0; i < 16; i++) -- if((haint.d32 >> i) & 1) -- if(fiq_hcintr_handle(i, hfnum)) -- haint_saved.d32 &= ~(1 << i); /* this was handled */ -- -- /* If we've handled all host channel interrupts then don't trigger the interrupt */ -- if(haint_saved.d32 == 0) -- { -- handled.b.hcintr = 1; -- } -- else -- { -- /* Make sure we keep the channel interrupt unmasked when triggering the IRQ */ -- keep.b.hcintr = 1; -- } -- -- { -- gintsts_data_t gintsts = { .b.hcintr = 1 }; -- -- // Always clear the channel interrupt -- FIQ_WRITE((dwc_regs_base + 0x14), gintsts.d32); -- } -- } -- } -- else -- { -- last_sof = -1; -- } -- } -- -- // Mask out the interrupts triggered - those handled - don't mask out the ones we want to keep -- gintmsk.d32 = keep.d32 | (gintmsk.d32 & ~(triggered.d32 & ~handled.d32)); -- // Save those that were triggered but not handled -- gintsts_saved.d32 |= triggered.d32 & ~handled.d32; -- FIQ_WRITE(dwc_regs_base + 0x18, gintmsk.d32); -- -- // Clear and save any unhandled interrupts and trigger the interrupt -- if(gintsts_saved.d32) -- { -- /* To enable the MPHI interrupt (INT 32) -- */ -- FIQ_WRITE( c_mphi_regs.outdda, (int) dummy_send); -- FIQ_WRITE( c_mphi_regs.outddb, (1 << 29)); -- -- mphi_int_count++; -- } -- } -- while(0); -- -- mb(); -- -- /* exit back to normal mode restoring everything */ -- asm __volatile__ ( -- /* return FIQ regs back to pristine state -- * and get normal regs back -- */ -- "ldmia sp!, {r0-r12, lr};" -- -- /* return */ -- "subs pc, lr, #4;" -- ); --} -- - /** This function handles interrupts for the HCD. */ - int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) - { - int retval = 0; - static int last_time; -- - dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; - gintsts_data_t gintsts; - gintmsk_data_t gintmsk; - hfnum_data_t hfnum; -+ haintmsk_data_t haintmsk; - - #ifdef DEBUG - dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -@@ -517,14 +100,25 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) - /* Check if HOST Mode */ - if (dwc_otg_is_host_mode(core_if)) { - local_fiq_disable(); -- gintmsk.d32 |= gintsts_saved.d32; -- gintsts.d32 |= gintsts_saved.d32; -- gintsts_saved.d32 = 0; -+ /* Pull in from the FIQ's disabled mask */ -+ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32); -+ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0; -+ -+ -+ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) { -+ gintsts.b.hcintr = 1; -+ } -+ -+ /* Danger will robinson: fake a SOF if necessary */ -+ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) { -+ gintsts.b.sofintr = 1; -+ } -+ gintsts.d32 &= gintmsk.d32; -+ - local_fiq_enable(); - if (!gintsts.d32) { - goto exit_handler_routine; - } -- gintsts.d32 &= gintmsk.d32; - - #ifdef DEBUG - // We should be OK doing this because the common interrupts should already have been serviced -@@ -544,12 +138,7 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) - gintsts.d32, core_if); - #endif - hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum); -- if (gintsts.b.sofintr && g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum)) -- { -- /* Note, we should never get here if the FIQ is doing it's job properly*/ -- retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); -- } -- else if (gintsts.b.sofintr) { -+ if (gintsts.b.sofintr) { - retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); - } - -@@ -604,37 +193,43 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) - } - - exit_handler_routine: -- -- if (fiq_fix_enable) -- { -+ if (fiq_enable) { -+ gintmsk_data_t gintmsk_new; -+ haintmsk_data_t haintmsk_new; - local_fiq_disable(); -- // Make sure that we don't clear the interrupt if we've still got pending work to do -- if(gintsts_saved.d32 == 0) -- { -- /* Clear the MPHI interrupt */ -- DWC_WRITE_REG32(c_mphi_regs.intstat, (1<<16)); -- if (mphi_int_count >= 60) -- { -- DWC_WRITE_REG32(c_mphi_regs.ctrl, ((1<<31) + (1<<16))); -- while(!(DWC_READ_REG32(c_mphi_regs.ctrl) & (1 << 17))) -- ; -- DWC_WRITE_REG32(c_mphi_regs.ctrl, (1<<31)); -- mphi_int_count = 0; -- } -- int_done++; -+ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32; -+ if(fiq_fsm_enable) -+ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32; -+ else -+ haintmsk_new.d32 = 0x0000FFFF; -+ -+ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */ -+ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) { -+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16)); -+ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) { -+ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR"); -+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16))); -+ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17))) -+ ; -+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31)); -+ dwc_otg_hcd->fiq_state->mphi_int_count = 0; -+ } -+ int_done++; - } -- -- // Unmask handled interrupts -- FIQ_WRITE(dwc_regs_base + 0x18, gintmsk.d32); -- //DWC_MODIFY_REG32((uint32_t *)IO_ADDRESS(USB_BASE + 0x8), 0 , 1); -- -+ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); -+ /* Re-enable interrupts that the FIQ masked (first time round) */ -+ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32); - local_fiq_enable(); - -- if((jiffies / HZ) > last_time) -- { -+ if ((jiffies / HZ) > last_time) { -+ //dwc_otg_qh_t *qh; -+ //dwc_list_link_t *cur; - /* Once a second output the fiq and irq numbers, useful for debug */ - last_time = jiffies / HZ; -- DWC_DEBUGPL(DBG_USER, "int_done = %d fiq_done = %d\n", int_done, fiq_done); -+ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d", -+ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels, -+ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done); -+ //printk(KERN_WARNING "Periodic queues:\n"); - } - } - -@@ -686,6 +281,7 @@ static inline void track_missed_sofs(uint16_t curr_frame_number) - int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) - { - hfnum_data_t hfnum; -+ gintsts_data_t gintsts = { .d32 = 0 }; - dwc_list_link_t *qh_entry; - dwc_otg_qh_t *qh; - dwc_otg_transaction_type_e tr_type; -@@ -733,7 +329,7 @@ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) - } - } - -- g_next_sched_frame = next_sched_frame; -+ hcd->fiq_state->next_sched_frame = next_sched_frame; - - tr_type = dwc_otg_hcd_select_transactions(hcd); - if (tr_type != DWC_OTG_TRANSACTION_NONE) { -@@ -741,10 +337,11 @@ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) - did_something = 1; - } - -- /* Clear interrupt */ -- gintsts.b.sofintr = 1; -- DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); -- -+ /* Clear interrupt - but do not trample on the FIQ sof */ -+ if (!fiq_fsm_enable) { -+ gintsts.b.sofintr = 1; -+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); -+ } - return 1; - } - -@@ -1020,19 +617,21 @@ int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd) - { - int i; - int retval = 0; -- haint_data_t haint; -+ haint_data_t haint = { .d32 = 0 } ; - - /* Clear appropriate bits in HCINTn to clear the interrupt bit in - * GINTSTS */ - -- haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); -+ if (!fiq_fsm_enable) -+ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); - - // Overwrite with saved interrupts from fiq handler -- if(fiq_split_enable) -+ if(fiq_fsm_enable) - { -+ /* check the mask? */ - local_fiq_disable(); -- haint.d32 = haint_saved.d32; -- haint_saved.d32 = 0; -+ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint); -+ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0; - local_fiq_enable(); - } - -@@ -1076,9 +675,7 @@ static uint32_t get_actual_xfer_length(dwc_hc_t * hc, - *short_read = (hctsiz.b.xfersize != 0); - } - } else if (hc->qh->do_split) { -- if(fiq_split_enable) -- length = split_out_xfersize[hc->hc_num]; -- else -+ //length = split_out_xfersize[hc->hc_num]; - length = qtd->ssplit_out_xfer_count; - } else { - length = hc->xfer_len; -@@ -1325,19 +922,17 @@ static void release_channel(dwc_otg_hcd_t * hcd, - int free_qtd; - dwc_irqflags_t flags; - dwc_spinlock_t *channel_lock = hcd->channel_lock; --#ifdef FIQ_DEBUG -- int endp = qtd->urb ? qtd->urb->pipe_info.ep_num : 0; --#endif -+ - int hog_port = 0; - - DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", - __func__, hc->hc_num, halt_status, hc->xfer_len); - -- if(fiq_split_enable && hc->do_split) { -+ if(fiq_fsm_enable && hc->do_split) { - if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) { - if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID || - hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) { -- hog_port = 1; -+ hog_port = 0; - } - } - } -@@ -1394,6 +989,8 @@ static void release_channel(dwc_otg_hcd_t * hcd, - * function clears the channel interrupt enables and conditions, so - * there's no need to clear the Channel Halted interrupt separately. - */ -+ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH) -+ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num); - dwc_otg_hc_cleanup(hcd->core_if, hc); - DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); - -@@ -1416,27 +1013,10 @@ static void release_channel(dwc_otg_hcd_t * hcd, - - DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); - hcd->available_host_channels++; -- fiq_print(FIQDBG_PORTHUB, "AHC = %d ", hcd->available_host_channels); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels); - DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); - } - -- if(fiq_split_enable && hc->do_split) -- { -- if(!(hcd->hub_port[hc->hub_addr] & (1 << hc->port_addr))) -- { -- fiq_print(FIQDBG_ERR, "PRTNOTAL"); -- //BUG(); -- } -- if(!hog_port && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC || -- hc->ep_type == DWC_OTG_EP_TYPE_INTR)) { -- hcd->hub_port[hc->hub_addr] &= ~(1 << hc->port_addr); --#ifdef FIQ_DEBUG -- hcd->hub_port_alloc[hc->hub_addr * 16 + hc->port_addr] = -1; --#endif -- fiq_print(FIQDBG_PORTHUB, "H%dP%d:RR%d", hc->hub_addr, hc->port_addr, endp); -- } -- } -- - /* Try to queue more transfers now that there's a free channel. */ - tr_type = dwc_otg_hcd_select_transactions(hcd); - if (tr_type != DWC_OTG_TRANSACTION_NONE) { -@@ -1858,7 +1438,7 @@ static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd, - switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { - case UE_BULK: - case UE_CONTROL: -- if (nak_holdoff_enable) -+ if (nak_holdoff && qtd->qh->do_split) - hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd); - } - -@@ -2074,7 +1654,7 @@ static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd, - // With the FIQ running we only ever see the failed NYET - if (dwc_full_frame_num(frnum) != - dwc_full_frame_num(hc->qh->sched_frame) || -- fiq_split_enable) { -+ fiq_fsm_enable) { - /* - * No longer in the same full speed frame. - * Treat this as a transaction error. -@@ -2460,12 +2040,11 @@ static inline int halt_status_ok(dwc_otg_hcd_t * hcd, - static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, - dwc_hc_t * hc, - dwc_otg_hc_regs_t * hc_regs, -- dwc_otg_qtd_t * qtd, -- hcint_data_t hcint, -- hcintmsk_data_t hcintmsk) -+ dwc_otg_qtd_t * qtd) - { - int out_nak_enh = 0; -- -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; - /* For core with OUT NAK enhancement, the flow for high- - * speed CONTROL/BULK OUT is handled a little differently. - */ -@@ -2495,11 +2074,9 @@ static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, - } - - /* Read the HCINTn register to determine the cause for the halt. */ -- if(!fiq_split_enable) -- { -- hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -- hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); -- } -+ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); - - if (hcint.b.xfercomp) { - /** @todo This is here because of a possible hardware bug. Spec -@@ -2624,15 +2201,13 @@ static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, - static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, - dwc_hc_t * hc, - dwc_otg_hc_regs_t * hc_regs, -- dwc_otg_qtd_t * qtd, -- hcint_data_t hcint, -- hcintmsk_data_t hcintmsk) -+ dwc_otg_qtd_t * qtd) - { - DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " - "Channel Halted--\n", hc->hc_num); - - if (hcd->core_if->dma_enable) { -- handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd, hcint, hcintmsk); -+ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); - } else { - #ifdef DEBUG - if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { -@@ -2645,11 +2220,370 @@ static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, - return 1; - } - -+ -+/** -+ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on -+ * FIQ transfer completion -+ * @hcd: Pointer to dwc_otg_hcd struct -+ * @num: Host channel number -+ * -+ * 1. Un-mangle the status as recorded in each iso_frame_desc status -+ * 2. Copy it from the dwc_otg_urb into the real URB -+ */ -+void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) -+{ -+ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb; -+ int nr_frames = dwc_urb->packet_count; -+ int i; -+ hcint_data_t frame_hcint; -+ -+ for (i = 0; i < nr_frames; i++) { -+ frame_hcint.d32 = dwc_urb->iso_descs[i].status; -+ if (frame_hcint.b.xfercomp) { -+ dwc_urb->iso_descs[i].status = 0; -+ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length; -+ } else if (frame_hcint.b.frmovrun) { -+ if (qh->ep_is_in) -+ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES; -+ else -+ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION; -+ dwc_urb->error_count++; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ } else if (frame_hcint.b.xacterr) { -+ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL; -+ dwc_urb->error_count++; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ } else if (frame_hcint.b.bblerr) { -+ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW; -+ dwc_urb->error_count++; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ } else { -+ /* Something went wrong */ -+ dwc_urb->iso_descs[i].status = -1; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ dwc_urb->error_count++; -+ } -+ } -+ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n", -+ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count); -+ hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0); -+ release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+} -+ -+/** -+ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions -+ * @hcd: Pointer to dwc_otg_hcd struct -+ * @num: Host channel number -+ * -+ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state. -+ * Returns total length of data or -1 if the buffers were not used. -+ * -+ */ -+int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) -+{ -+ dwc_hc_t *hc = qh->channel; -+ struct fiq_dma_blob *blob = hcd->fiq_dmab; -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; -+ uint8_t *ptr = NULL; -+ int index = 0, len = 0; -+ int i = 0; -+ if (hc->ep_is_in) { -+ /* Copy data out of the DMA bounce buffers to the URB's buffer. -+ * The align_buf is ignored as this is ignored on FSM enqueue. */ -+ ptr = qtd->urb->buf; -+ if (qh->ep_type == UE_ISOCHRONOUS) { -+ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */ -+ index = qtd->isoc_frame_index; -+ ptr += qtd->urb->iso_descs[index].offset; -+ } else { -+ /* Need to increment by actual_length for interrupt IN */ -+ ptr += qtd->urb->actual_length; -+ } -+ -+ for (i = 0; i < st->nrpackets; i++) { -+ len += st->dma_info.slot_len[i]; -+ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]); -+ ptr += st->dma_info.slot_len[i]; -+ } -+ return len; -+ } else { -+ /* OUT endpoints - nothing to do. */ -+ return -1; -+ } -+ -+} -+/** -+ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt -+ * from a channel handled in the FIQ -+ * @hcd: Pointer to dwc_otg_hcd struct -+ * @num: Host channel number -+ * -+ * If a host channel interrupt was received by the IRQ and this was a channel -+ * used by the FIQ, the execution flow for transfer completion is substantially -+ * different from the normal (messy) path. This function and its friends handles -+ * channel cleanup and transaction completion from a FIQ transaction. -+ */ -+int32_t dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) -+{ -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; -+ dwc_hc_t *hc = hcd->hc_ptr_array[num]; -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); -+ dwc_otg_qh_t *qh = hc->qh; -+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num]; -+ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy; -+ int hostchannels = 0; -+ int ret = 0; -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm); -+ -+ hostchannels = hcd->available_host_channels; -+ switch (st->fsm) { -+ case FIQ_TEST: -+ break; -+ -+ case FIQ_DEQUEUE_ISSUED: -+ /* hc_halt was called. QTD no longer exists. */ -+ /* TODO: for a nonperiodic split transaction, need to issue a -+ * CLEAR_TT_BUFFER hub command if we were in the start-split phase. -+ */ -+ release_channel(hcd, hc, NULL, hc->halt_status); -+ ret = 1; -+ break; -+ -+ case FIQ_NP_SPLIT_DONE: -+ /* Nonperiodic transaction complete. */ -+ if (!hc->ep_is_in) { -+ qtd->ssplit_out_xfer_count = hc->xfer_len; -+ } -+ if (hcint.b.xfercomp) { -+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.nak) { -+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); -+ } -+ ret = 1; -+ break; -+ -+ case FIQ_NP_SPLIT_HS_ABORTED: -+ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction. -+ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that -+ * because there's no guarantee which order a non-periodic split happened in. -+ * We could end up clearing a perfectly good transaction out of the buffer. -+ */ -+ if (hcint.b.xacterr) { -+ qtd->error_count += st->nr_errors; -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.ahberr) { -+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ local_fiq_disable(); -+ BUG(); -+ } -+ break; -+ -+ case FIQ_NP_SPLIT_LS_ABORTED: -+ /* A few cases can cause this - either an unknown state on a SSPLIT or -+ * STALL/data toggle error response on a CSPLIT */ -+ if (hcint.b.stall) { -+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.datatglerr) { -+ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.ahberr) { -+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ local_fiq_disable(); -+ BUG(); -+ } -+ break; -+ -+ case FIQ_PER_SPLIT_DONE: -+ /* Isoc IN or Interrupt IN/OUT */ -+ -+ /* Flow control here is different from the normal execution by the driver. -+ * We need to completely ignore most of the driver's method of handling -+ * split transactions and do it ourselves. -+ */ -+ if (hc->ep_type == UE_INTERRUPT) { -+ if (hc->ep_is_in) { -+ if (hcint.b.nak) { -+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ int len; -+ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num); -+ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length); -+ qtd->urb->actual_length += len; -+ if (qtd->urb->actual_length >= qtd->urb->length) { -+ qtd->urb->status = 0; -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ /* Interrupt transfer not complete yet - is it a short read? */ -+ if (len < hc->max_packet) { -+ /* Interrupt transaction complete */ -+ qtd->urb->status = 0; -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ /* Further transactions required */ -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ -+ } -+ -+ } -+ -+ } else { -+ /* Interrupt OUT complete. */ -+ qtd->urb->actual_length += hc->xfer_len; -+ if (qtd->urb->actual_length >= qtd->urb->length) { -+ qtd->urb->status = 0; -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } -+ } else { -+ /* ISOC IN complete. */ -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ int len = 0; -+ /* Record errors, update qtd. */ -+ if (st->nr_errors) { -+ frame_desc->actual_length = 0; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ } else { -+ frame_desc->status = 0; -+ /* Unswizzle dma */ -+ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num); -+ frame_desc->actual_length = len; -+ } -+ qtd->isoc_frame_index++; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } -+ break; -+ -+ case FIQ_PER_ISO_OUT_DONE: { -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ /* Record errors, update qtd. */ -+ if (st->nr_errors) { -+ frame_desc->actual_length = 0; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ } else { -+ frame_desc->status = 0; -+ frame_desc->actual_length = frame_desc->length; -+ } -+ qtd->isoc_frame_index++; -+ qtd->isoc_split_offset = 0; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } -+ break; -+ -+ case FIQ_PER_SPLIT_NYET_ABORTED: -+ /* Doh. lost the data. */ -+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " -+ "- FIQ reported NYET. Data may have been lost.\n", -+ hc->dev_addr, hc->ep_num); -+ if (hc->ep_type == UE_ISOCHRONOUS) { -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ /* Record errors, update qtd. */ -+ frame_desc->actual_length = 0; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ qtd->isoc_frame_index++; -+ qtd->isoc_split_offset = 0; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ break; -+ -+ case FIQ_HS_ISOC_DONE: -+ /* The FIQ has performed a whole pile of isochronous transactions. -+ * The status is recorded as the interrupt state should the transaction -+ * fail. -+ */ -+ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num); -+ break; -+ -+ case FIQ_PER_SPLIT_LS_ABORTED: -+ if (hcint.b.xacterr) { -+ /* Hub has responded with an ERR packet. Device -+ * has been unplugged or the port has been disabled. -+ * TODO: need to issue a reset to the hub port. */ -+ qtd->error_count += 3; -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " -+ "- FIQ reported FSM=%d. Data may have been lost.\n", -+ st->fsm, hc->dev_addr, hc->ep_num); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ break; -+ -+ case FIQ_PER_SPLIT_HS_ABORTED: -+ /* Either the SSPLIT phase suffered transaction errors or something -+ * unexpected happened. -+ */ -+ qtd->error_count += 3; -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ break; -+ -+ case FIQ_PER_SPLIT_TIMEOUT: -+ /* Couldn't complete in the nominated frame */ -+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " -+ "- FIQ timed out. Data may have been lost.\n", -+ hc->dev_addr, hc->ep_num); -+ if (hc->ep_type == UE_ISOCHRONOUS) { -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ /* Record errors, update qtd. */ -+ frame_desc->actual_length = 0; -+ if (hc->ep_is_in) { -+ frame_desc->status = -DWC_E_NO_STREAM_RES; -+ } else { -+ frame_desc->status = -DWC_E_COMMUNICATION; -+ } -+ qtd->isoc_frame_index++; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ break; -+ -+ default: -+ local_fiq_disable(); -+ DWC_WARN("unexpected state received on hc=%d fsm=%d", hc->hc_num, st->fsm); -+ BUG(); -+ } -+ //if (hostchannels != hcd->available_host_channels) { -+ /* should have incremented by now! */ -+ // BUG(); -+// } -+ return ret; -+} -+ - /** Handles interrupt for a specific Host Channel */ - int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) - { - int retval = 0; -- hcint_data_t hcint, hcint_orig; -+ hcint_data_t hcint; - hcintmsk_data_t hcintmsk; - dwc_hc_t *hc; - dwc_otg_hc_regs_t *hc_regs; -@@ -2666,26 +2600,25 @@ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) - release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status); - return 1; - } -+ -+ /* -+ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ. -+ * Execution path is fundamentally different for the channels after a FIQ has completed -+ * a split transaction. -+ */ -+ -+ -+ if (fiq_fsm_enable) { -+ if (*(volatile uint32_t *)&dwc_otg_hcd->fiq_state->channel[num].fsm != FIQ_PASSTHROUGH) { -+ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num); -+ return 1; -+ } -+ } - qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); - - hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -- hcint_orig = hcint; - hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); -- DWC_DEBUGPL(DBG_HCDV, -- " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", -- hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); - hcint.d32 = hcint.d32 & hcintmsk.d32; -- -- if(fiq_split_enable) -- { -- // replace with the saved interrupts from the fiq handler -- local_fiq_disable(); -- hcint_orig.d32 = hcint_saved[num].d32; -- hcint.d32 = hcint_orig.d32 & hcintmsk_saved[num].d32; -- hcint_saved[num].d32 = 0; -- local_fiq_enable(); -- } -- - if (!dwc_otg_hcd->core_if->dma_enable) { - if (hcint.b.chhltd && hcint.d32 != 0x2) { - hcint.b.chhltd = 0; -@@ -2703,7 +2636,7 @@ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) - hcint.b.nyet = 0; - } - if (hcint.b.chhltd) { -- retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd, hcint_orig, hcintmsk_saved[num]); -+ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); - } - if (hcint.b.ahberr) { - retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c -index ee8eec9..5d45062 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c -@@ -58,6 +58,7 @@ - #else - #include - #endif -+#include - - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) - #define USB_URB_EP_LINKING 1 -@@ -69,7 +70,8 @@ - #include "dwc_otg_dbg.h" - #include "dwc_otg_driver.h" - #include "dwc_otg_hcd.h" --#include "dwc_otg_mphi_fix.h" -+ -+extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end; - - /** - * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is -@@ -80,7 +82,7 @@ - - static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; - --extern bool fiq_fix_enable; -+extern bool fiq_enable; - - /** @name Linux HC Driver API Functions */ - /** @{ */ -@@ -351,7 +353,6 @@ static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, - urb); - } - } -- - DWC_FREE(dwc_otg_urb); - if (!new_entry) { - DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n"); -@@ -395,13 +396,9 @@ static struct dwc_otg_hcd_function_ops hcd_fops = { - static struct fiq_handler fh = { - .name = "usb_fiq", - }; --struct fiq_stack_s { -- int magic1; -- uint8_t stack[2048]; -- int magic2; --} fiq_stack; - --extern mphi_regs_t c_mphi_regs; -+ -+ - /** - * Initializes the HCD. This function allocates memory for and initializes the - * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the -@@ -433,20 +430,6 @@ int hcd_init(dwc_bus_dev_t *_dev) - pci_set_consistent_dma_mask(_dev, dmamask); - #endif - -- if (fiq_fix_enable) -- { -- // Set up fiq -- claim_fiq(&fh); -- set_fiq_handler(__FIQ_Branch, 4); -- memset(®s,0,sizeof(regs)); -- regs.ARM_r8 = (long)dwc_otg_hcd_handle_fiq; -- regs.ARM_r9 = (long)0; -- regs.ARM_sp = (long)fiq_stack.stack + sizeof(fiq_stack.stack) - 4; -- set_fiq_regs(®s); -- fiq_stack.magic1 = 0xdeadbeef; -- fiq_stack.magic2 = 0xaa995566; -- } -- - /* - * Allocate memory for the base HCD plus the DWC OTG HCD. - * Initialize the base HCD. -@@ -466,30 +449,7 @@ int hcd_init(dwc_bus_dev_t *_dev) - - hcd->regs = otg_dev->os_dep.base; - -- if (fiq_fix_enable) -- { -- volatile extern void *dwc_regs_base; - -- //Set the mphi periph to the required registers -- c_mphi_regs.base = otg_dev->os_dep.mphi_base; -- c_mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; -- c_mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; -- c_mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; -- c_mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; -- -- dwc_regs_base = otg_dev->os_dep.base; -- -- //Enable mphi peripheral -- writel((1<<31),c_mphi_regs.ctrl); --#ifdef DEBUG -- if (readl(c_mphi_regs.ctrl) & 0x80000000) -- DWC_DEBUGPL(DBG_USER, "MPHI periph has been enabled\n"); -- else -- DWC_DEBUGPL(DBG_USER, "MPHI periph has NOT been enabled\n"); --#endif -- // Enable FIQ interrupt from USB peripheral -- enable_fiq(INTERRUPT_VC_USB); -- } - /* Initialize the DWC OTG HCD. */ - dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); - if (!dwc_otg_hcd) { -@@ -503,6 +463,55 @@ int hcd_init(dwc_bus_dev_t *_dev) - goto error2; - } - -+ if (fiq_enable) -+ { -+ if (claim_fiq(&fh)) { -+ DWC_ERROR("Can't claim FIQ"); -+ goto error2; -+ } -+ -+ DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop)); -+ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub)); -+ -+ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub); -+ memset(®s,0,sizeof(regs)); -+ -+ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state; -+ if (fiq_fsm_enable) { -+ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels; -+ //regs.ARM_r10 = dwc_otg_hcd->dma; -+ regs.ARM_fp = (long) dwc_otg_fiq_fsm; -+ } else { -+ regs.ARM_fp = (long) dwc_otg_fiq_nop; -+ } -+ -+ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4); -+ -+// __show_regs(®s); -+ set_fiq_regs(®s); -+ -+ //Set the mphi periph to the required registers -+ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base; -+ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; -+ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; -+ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; -+ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; -+ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base; -+ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base); -+ //Enable mphi peripheral -+ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl); -+#ifdef DEBUG -+ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000) -+ DWC_WARN("MPHI periph has been enabled"); -+ else -+ DWC_WARN("MPHI periph has NOT been enabled"); -+#endif -+ // Enable FIQ interrupt from USB peripheral -+ enable_fiq(INTERRUPT_VC_USB); -+ local_fiq_enable(); -+ } -+ -+ - otg_dev->hcd->otg_dev = otg_dev; - hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd); - #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel) -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -index db95851..4d5a24c 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -@@ -41,7 +41,6 @@ - - #include "dwc_otg_hcd.h" - #include "dwc_otg_regs.h" --#include "dwc_otg_mphi_fix.h" - - extern bool microframe_schedule; - -@@ -576,7 +575,6 @@ static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - } - - --extern int g_next_sched_frame, g_np_count, g_np_sent; - - /** - * Schedules an interrupt or isochronous transfer in the periodic schedule. -@@ -636,9 +634,9 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); - } - else { -- if(DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, g_next_sched_frame)) -+ if(DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)) - { -- g_next_sched_frame = qh->sched_frame; -+ hcd->fiq_state->next_sched_frame = qh->sched_frame; - - } - /* Always start in the inactive schedule. */ -@@ -679,7 +677,7 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - /* Always start in the inactive schedule. */ - DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, - &qh->qh_list_entry); -- g_np_count++; -+ //hcd->fiq_state->kick_np_queues = 1; - } else { - status = schedule_periodic(hcd, qh); - if ( !hcd->periodic_qh_count ) { -@@ -739,13 +737,12 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - hcd->non_periodic_qh_ptr->next; - } - DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); -- -- // If we've removed the last non-periodic entry then there are none left! -- g_np_count = g_np_sent; -+ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) -+ // hcd->fiq_state->kick_np_queues = 1; - } else { - deschedule_periodic(hcd, qh); - hcd->periodic_qh_count--; -- if( !hcd->periodic_qh_count ) { -+ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) { - intr_mask.b.sofintr = 1; - DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, - intr_mask.d32, 0); -@@ -770,28 +767,11 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, - int sched_next_periodic_split) - { - if (dwc_qh_is_non_per(qh)) { -- -- dwc_otg_qh_t *qh_tmp; -- dwc_list_link_t *qh_list; -- DWC_LIST_FOREACH(qh_list, &hcd->non_periodic_sched_inactive) -- { -- qh_tmp = DWC_LIST_ENTRY(qh_list, struct dwc_otg_qh, qh_list_entry); -- if(qh_tmp == qh) -- { -- /* -- * FIQ is being disabled because this one nevers gets a np_count increment -- * This is still not absolutely correct, but it should fix itself with -- * just an unnecessary extra interrupt -- */ -- g_np_sent = g_np_count; -- } -- } -- -- - dwc_otg_hcd_qh_remove(hcd, qh); - if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { - /* Add back to inactive non-periodic schedule. */ - dwc_otg_hcd_qh_add(hcd, qh); -+ //hcd->fiq_state->kick_np_queues = 1; - } - } else { - uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd); -@@ -850,9 +830,9 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, - DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, - &qh->qh_list_entry); - } else { -- if(!dwc_frame_num_le(g_next_sched_frame, qh->sched_frame)) -+ if(!dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame)) - { -- g_next_sched_frame = qh->sched_frame; -+ hcd->fiq_state->next_sched_frame = qh->sched_frame; - } - - DWC_LIST_MOVE_HEAD -@@ -943,6 +923,9 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, - if (*qh == NULL) { - retval = -DWC_E_NO_MEMORY; - goto done; -+ } else { -+ if (fiq_enable) -+ hcd->fiq_state->kick_np_queues = 1; - } - } - retval = dwc_otg_hcd_qh_add(hcd, *qh); -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c b/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c -deleted file mode 100755 -index 50b94a8..0000000 ---- a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c -+++ /dev/null -@@ -1,113 +0,0 @@ --#include "dwc_otg_regs.h" --#include "dwc_otg_dbg.h" -- --void dwc_debug_print_core_int_reg(gintsts_data_t gintsts, const char* function_name) --{ -- DWC_DEBUGPL(DBG_USER, "*** Debugging from within the %s function: ***\n" -- "curmode: %1i Modemismatch: %1i otgintr: %1i sofintr: %1i\n" -- "rxstsqlvl: %1i nptxfempty : %1i ginnakeff: %1i goutnakeff: %1i\n" -- "ulpickint: %1i i2cintr: %1i erlysuspend:%1i usbsuspend: %1i\n" -- "usbreset: %1i enumdone: %1i isooutdrop: %1i eopframe: %1i\n" -- "restoredone: %1i epmismatch: %1i inepint: %1i outepintr: %1i\n" -- "incomplisoin:%1i incomplisoout:%1i fetsusp: %1i resetdet: %1i\n" -- "portintr: %1i hcintr: %1i ptxfempty: %1i lpmtranrcvd:%1i\n" -- "conidstschng:%1i disconnect: %1i sessreqintr:%1i wkupintr: %1i\n", -- function_name, -- gintsts.b.curmode, -- gintsts.b.modemismatch, -- gintsts.b.otgintr, -- gintsts.b.sofintr, -- gintsts.b.rxstsqlvl, -- gintsts.b.nptxfempty, -- gintsts.b.ginnakeff, -- gintsts.b.goutnakeff, -- gintsts.b.ulpickint, -- gintsts.b.i2cintr, -- gintsts.b.erlysuspend, -- gintsts.b.usbsuspend, -- gintsts.b.usbreset, -- gintsts.b.enumdone, -- gintsts.b.isooutdrop, -- gintsts.b.eopframe, -- gintsts.b.restoredone, -- gintsts.b.epmismatch, -- gintsts.b.inepint, -- gintsts.b.outepintr, -- gintsts.b.incomplisoin, -- gintsts.b.incomplisoout, -- gintsts.b.fetsusp, -- gintsts.b.resetdet, -- gintsts.b.portintr, -- gintsts.b.hcintr, -- gintsts.b.ptxfempty, -- gintsts.b.lpmtranrcvd, -- gintsts.b.conidstschng, -- gintsts.b.disconnect, -- gintsts.b.sessreqintr, -- gintsts.b.wkupintr); -- return; --} -- --void dwc_debug_core_int_mask(gintmsk_data_t gintmsk, const char* function_name) --{ -- DWC_DEBUGPL(DBG_USER, "Interrupt Mask status (called from %s) :\n" -- "modemismatch: %1i otgintr: %1i sofintr: %1i rxstsqlvl: %1i\n" -- "nptxfempty: %1i ginnakeff: %1i goutnakeff: %1i ulpickint: %1i\n" -- "i2cintr: %1i erlysuspend:%1i usbsuspend: %1i usbreset: %1i\n" -- "enumdone: %1i isooutdrop: %1i eopframe: %1i restoredone: %1i\n" -- "epmismatch: %1i inepintr: %1i outepintr: %1i incomplisoin:%1i\n" -- "incomplisoout:%1i fetsusp: %1i resetdet: %1i portintr: %1i\n" -- "hcintr: %1i ptxfempty: %1i lpmtranrcvd:%1i conidstschng:%1i\n" -- "disconnect: %1i sessreqintr:%1i wkupintr: %1i\n", -- function_name, -- gintmsk.b.modemismatch, -- gintmsk.b.otgintr, -- gintmsk.b.sofintr, -- gintmsk.b.rxstsqlvl, -- gintmsk.b.nptxfempty, -- gintmsk.b.ginnakeff, -- gintmsk.b.goutnakeff, -- gintmsk.b.ulpickint, -- gintmsk.b.i2cintr, -- gintmsk.b.erlysuspend, -- gintmsk.b.usbsuspend, -- gintmsk.b.usbreset, -- gintmsk.b.enumdone, -- gintmsk.b.isooutdrop, -- gintmsk.b.eopframe, -- gintmsk.b.restoredone, -- gintmsk.b.epmismatch, -- gintmsk.b.inepintr, -- gintmsk.b.outepintr, -- gintmsk.b.incomplisoin, -- gintmsk.b.incomplisoout, -- gintmsk.b.fetsusp, -- gintmsk.b.resetdet, -- gintmsk.b.portintr, -- gintmsk.b.hcintr, -- gintmsk.b.ptxfempty, -- gintmsk.b.lpmtranrcvd, -- gintmsk.b.conidstschng, -- gintmsk.b.disconnect, -- gintmsk.b.sessreqintr, -- gintmsk.b.wkupintr); -- return; --} -- --void dwc_debug_otg_int(gotgint_data_t gotgint, const char* function_name) --{ -- DWC_DEBUGPL(DBG_USER, "otg int register (from %s function):\n" -- "sesenddet:%1i sesreqsucstschung:%2i hstnegsucstschng:%1i\n" -- "hstnegdet:%1i adevtoutchng: %2i debdone: %1i\n" -- "mvic: %1i\n", -- function_name, -- gotgint.b.sesenddet, -- gotgint.b.sesreqsucstschng, -- gotgint.b.hstnegsucstschng, -- gotgint.b.hstnegdet, -- gotgint.b.adevtoutchng, -- gotgint.b.debdone, -- gotgint.b.mvic); -- -- return; --} -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h b/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h -deleted file mode 100755 -index ca17379..0000000 ---- a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h -+++ /dev/null -@@ -1,48 +0,0 @@ --#ifndef __DWC_OTG_MPHI_FIX_H__ --#define __DWC_OTG_MPHI_FIX_H__ --#define FIQ_WRITE(_addr_,_data_) (*(volatile uint32_t *) (_addr_) = (_data_)) --#define FIQ_READ(_addr_) (*(volatile uint32_t *) (_addr_)) -- --typedef struct { -- volatile void* base; -- volatile void* ctrl; -- volatile void* outdda; -- volatile void* outddb; -- volatile void* intstat; --} mphi_regs_t; -- --void dwc_debug_print_core_int_reg(gintsts_data_t gintsts, const char* function_name); --void dwc_debug_core_int_mask(gintsts_data_t gintmsk, const char* function_name); --void dwc_debug_otg_int(gotgint_data_t gotgint, const char* function_name); -- --extern gintsts_data_t gintsts_saved; -- --#ifdef DEBUG --#define DWC_DBG_PRINT_CORE_INT(_arg_) dwc_debug_print_core_int_reg(_arg_,__func__) --#define DWC_DBG_PRINT_CORE_INT_MASK(_arg_) dwc_debug_core_int_mask(_arg_,__func__) --#define DWC_DBG_PRINT_OTG_INT(_arg_) dwc_debug_otg_int(_arg_,__func__) -- --#else --#define DWC_DBG_PRINT_CORE_INT(_arg_) --#define DWC_DBG_PRINT_CORE_INT_MASK(_arg_) --#define DWC_DBG_PRINT_OTG_INT(_arg_) -- --#endif -- --typedef enum { -- FIQDBG_SCHED = (1 << 0), -- FIQDBG_INT = (1 << 1), -- FIQDBG_ERR = (1 << 2), -- FIQDBG_PORTHUB = (1 << 3), --} FIQDBG_T; -- --void _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...); --#ifdef FIQ_DEBUG --#define fiq_print _fiq_print --#else --#define fiq_print(x, y, ...) --#endif -- --extern bool fiq_fix_enable, nak_holdoff_enable, fiq_split_enable; -- --#endif --- -1.9.1 - - -From 041e8cc178b179966a2f42b1843f821995a10dec Mon Sep 17 00:00:00 2001 -From: P33M -Date: Wed, 19 Mar 2014 15:13:53 +0000 -Subject: [PATCH 079/110] Fix ARM architecture issue with local_irq_restore() - -If local_fiq_enable() is called before a local_irq_restore(flags) where -the flags variable has the F bit set, the FIQ will be erroneously disabled. - -Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR. - -Also fix some of the hacks previously implemented for previous dwc_otg -incarnations. ---- - arch/arm/include/asm/fiq.h | 1 - - arch/arm/include/asm/irqflags.h | 16 +++++++++++++--- - arch/arm/kernel/fiq.c | 1 - - arch/arm/kernel/fiqasm.S | 3 --- - drivers/usb/host/dwc_common_port/dwc_common_linux.c | 1 + - 5 files changed, 14 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/include/asm/fiq.h b/arch/arm/include/asm/fiq.h -index f1a131b..d493d0b 100644 ---- a/arch/arm/include/asm/fiq.h -+++ b/arch/arm/include/asm/fiq.h -@@ -42,7 +42,6 @@ extern void disable_fiq(int fiq); - /* helpers defined in fiqasm.S: */ - extern void __set_fiq_regs(unsigned long const *regs); - extern void __get_fiq_regs(unsigned long *regs); --extern void __FIQ_Branch(unsigned long *regs); - - static inline void set_fiq_regs(struct pt_regs const *regs) - { -diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h -index 3b763d6..5770408 100644 ---- a/arch/arm/include/asm/irqflags.h -+++ b/arch/arm/include/asm/irqflags.h -@@ -145,12 +145,22 @@ static inline unsigned long arch_local_save_flags(void) - } - - /* -- * restore saved IRQ & FIQ state -+ * restore saved IRQ state - */ - static inline void arch_local_irq_restore(unsigned long flags) - { -- asm volatile( -- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" -+ unsigned long temp = 0; -+ flags &= ~(1 << 6); -+ asm volatile ( -+ " mrs %0, cpsr" -+ : "=r" (temp) -+ : -+ : "memory", "cc"); -+ /* Preserve FIQ bit */ -+ temp &= (1 << 6); -+ flags = flags | temp; -+ asm volatile ( -+ " msr cpsr_c, %0 @ local_irq_restore" - : - : "r" (flags) - : "memory", "cc"); -diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c -index aac11f8..918875d 100644 ---- a/arch/arm/kernel/fiq.c -+++ b/arch/arm/kernel/fiq.c -@@ -142,7 +142,6 @@ void disable_fiq(int fiq) - EXPORT_SYMBOL(set_fiq_handler); - EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */ - EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */ --EXPORT_SYMBOL(__FIQ_Branch); /* defined in fiqasm.S */ - EXPORT_SYMBOL(claim_fiq); - EXPORT_SYMBOL(release_fiq); - EXPORT_SYMBOL(enable_fiq); -diff --git a/arch/arm/kernel/fiqasm.S b/arch/arm/kernel/fiqasm.S -index 93eddfe..5233d54 100644 ---- a/arch/arm/kernel/fiqasm.S -+++ b/arch/arm/kernel/fiqasm.S -@@ -25,9 +25,6 @@ - ENTRY(__set_fiq_regs) - mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE - mrs r1, cpsr --@@@@@@@@@@@@@@@ hack: enable the fiq here to keep usb driver happy -- and r1, #~PSR_F_BIT --@@@@@@@@@@@@@@@ endhack: (need to find better place for this to happen) - msr cpsr_c, r2 @ select FIQ mode - mov r0, r0 @ avoid hazard prior to ARMv4 - ldmia r0!, {r8 - r12} -diff --git a/drivers/usb/host/dwc_common_port/dwc_common_linux.c b/drivers/usb/host/dwc_common_port/dwc_common_linux.c -index 0812d3a..6d01261 100644 ---- a/drivers/usb/host/dwc_common_port/dwc_common_linux.c -+++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c -@@ -585,6 +585,7 @@ void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_ - local_irq_save(flags); - local_fiq_disable(); - writel((readl(reg) & ~clear_mask) | set_mask, reg); -+ local_fiq_enable(); - local_irq_restore(flags); - } - --- -1.9.1 - - -From cdce5f507ec6075419425dfeaa8474f6039abc0e Mon Sep 17 00:00:00 2001 +From ae87471ddb02eded727cf6dfd14e227387ea7315 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:22:53 +0100 -Subject: [PATCH 080/110] dmaengine: Add support for BCM2708 +Subject: [PATCH 078/101] dmaengine: Add support for BCM2708 Add support for DMA controller of BCM2708 as used in the Raspberry Pi. Currently it only supports cyclic DMA. @@ -112070,10 +107331,10 @@ index 0000000..b244293 1.9.1 -From c6c50d38e3ae40a3b4bea4282e4bd98293da6ebc Mon Sep 17 00:00:00 2001 +From 60f69e823e9f68c69d84c8ddb9a1d139dab4092b Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:33:38 +0100 -Subject: [PATCH 081/110] ASoC: Add support for BCM2708 +Subject: [PATCH 079/101] ASoC: Add support for BCM2708 This driver adds support for digital audio (I2S) for the BCM2708 SoC that is used by the @@ -113071,10 +108332,10 @@ index 0000000..ebaf3d6 1.9.1 -From 23dee33ecd81425e8a627b8d6f88ed2ec0319d8d Mon Sep 17 00:00:00 2001 +From b099a459b3e112b17f5964f3ca1e2f1b4de186ac Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:37:51 +0100 -Subject: [PATCH 082/110] BCM2708: Extend mach header +Subject: [PATCH 080/101] BCM2708: Extend mach header Extend the headers of the mach-bcm2708 in order to support I2S and DMA engine. @@ -113119,10 +108380,10 @@ index 992a630..2e7e1bb 100644 1.9.1 -From 41a7fd0d5cbe67d0df69d182521d7cba50b8a97c Mon Sep 17 00:00:00 2001 +From 7fb0bf302efc6f9a2bd7965b1fb81f710b05b5a1 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:59:51 +0100 -Subject: [PATCH 083/110] ASoC: Add support for PCM5102A codec +Subject: [PATCH 081/101] ASoC: Add support for PCM5102A codec Some definitions to support the PCM5102A codec by Texas Instruments. @@ -113250,10 +108511,10 @@ index 0000000..126f1e9 1.9.1 -From 2a0ccd132101436fa8f973c65f33cd9f6680b365 Mon Sep 17 00:00:00 2001 +From b80da6a2b65b939a59b4f92737eab5472a5d3abe Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:04:54 +0100 -Subject: [PATCH 084/110] BCM2708: Add I2S support to board file +Subject: [PATCH 082/101] BCM2708: Add I2S support to board file Adds the required initializations for I2S to the board file of mach-bcm2708. @@ -113264,10 +108525,10 @@ Signed-off-by: Florian Meier 1 file changed, 26 insertions(+) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 91c008f..6117a4b 100644 +index 2b11e9d..76d7505 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -606,6 +606,28 @@ static struct platform_device bcm2835_thermal_device = { +@@ -620,6 +620,28 @@ static struct platform_device bcm2835_thermal_device = { .name = "bcm2835_thermal", }; @@ -113296,7 +108557,7 @@ index 91c008f..6117a4b 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -728,6 +750,10 @@ void __init bcm2708_init(void) +@@ -747,6 +769,10 @@ void __init bcm2708_init(void) bcm_register_device(&bcm2835_hwmon_device); bcm_register_device(&bcm2835_thermal_device); @@ -113311,10 +108572,10 @@ index 91c008f..6117a4b 100644 1.9.1 -From ada4ff394947d003e6edaa52af4b50ecbdbcec61 Mon Sep 17 00:00:00 2001 +From 70a008c256ef3ab28ff4cefe31b212d336daa0ca Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:19:08 +0100 -Subject: [PATCH 085/110] ASoC: Add support for HifiBerry DAC +Subject: [PATCH 083/101] ASoC: Add support for HifiBerry DAC This adds a machine driver for the HifiBerry DAC. It is a sound card that can @@ -113466,10 +108727,10 @@ index 0000000..4b70b45 1.9.1 -From 0819c85198ab2717f148aa042fdd4ee8b7fe1e1d Mon Sep 17 00:00:00 2001 +From 5e2d018d9842c30693c0737862b0806d344e1fbb Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:21:34 +0100 -Subject: [PATCH 086/110] BCM2708: Add HifiBerry DAC to board file +Subject: [PATCH 084/101] BCM2708: Add HifiBerry DAC to board file This adds the initalization of the HifiBerry DAC to the mach-bcm2708 board file. @@ -113480,10 +108741,10 @@ Signed-off-by: Florian Meier 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 6117a4b..5056993 100644 +index 76d7505..45d0b4f 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -628,6 +628,20 @@ static struct platform_device bcm2708_i2s_device = { +@@ -642,6 +642,20 @@ static struct platform_device bcm2708_i2s_device = { }; #endif @@ -113504,7 +108765,7 @@ index 6117a4b..5056993 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -754,6 +768,11 @@ void __init bcm2708_init(void) +@@ -773,6 +787,11 @@ void __init bcm2708_init(void) bcm_register_device(&bcm2708_i2s_device); #endif @@ -113520,10 +108781,10 @@ index 6117a4b..5056993 100644 1.9.1 -From 71516ae619c3290e9f38b43167fabe820c9f5202 Mon Sep 17 00:00:00 2001 +From e48f39b687eb642e145636400c824d73ca9176df Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 6 Dec 2013 18:55:53 +0100 -Subject: [PATCH 087/110] ASoC: BCM2708: Add 24 bit support +Subject: [PATCH 085/101] ASoC: BCM2708: Add 24 bit support This adds 24 bit support to the I2S driver of the BCM2708. Besides enabling the 24 bit flags, it includes two bug fixes: @@ -113598,10 +108859,10 @@ index ebaf3d6..a179216 100644 1.9.1 -From 8bb36f06184e62d98d7936366686593259afa8e2 Mon Sep 17 00:00:00 2001 +From 3b862496d772e867f65570e37b097aaa820fba31 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Mon, 2 Dec 2013 20:28:22 +0100 -Subject: [PATCH 088/110] BCM2708: Add I2S and DMA support to default config +Subject: [PATCH 086/101] BCM2708: Add I2S and DMA support to default config This commit adds several modules that are needed for I2S support for the Raspberry Pi to the defconfig. @@ -113612,10 +108873,10 @@ Signed-off-by: Florian Meier 1 file changed, 11 insertions(+) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 1041f5e..0360c86 100644 +index 5100760..cde1233 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -738,6 +738,13 @@ CONFIG_SND_USB_UA101=m +@@ -739,6 +739,13 @@ CONFIG_SND_USB_UA101=m CONFIG_SND_USB_CAIAQ=m CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_USB_6FIRE=m @@ -113629,7 +108890,7 @@ index 1041f5e..0360c86 100644 CONFIG_SOUND_PRIME=m CONFIG_HIDRAW=y CONFIG_HID_A4TECH=m -@@ -925,6 +932,10 @@ CONFIG_RTC_DRV_RS5C348=m +@@ -926,6 +933,10 @@ CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_DS3234=m CONFIG_RTC_DRV_PCF2123=m CONFIG_RTC_DRV_RX4581=m @@ -113644,10 +108905,10 @@ index 1041f5e..0360c86 100644 1.9.1 -From 2efa936670f58dac8628f0016fd083f25e7baac4 Mon Sep 17 00:00:00 2001 +From 248a1f201126cfa236075aa4169a13e1010a82ac Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 6 Dec 2013 20:50:28 +0100 -Subject: [PATCH 089/110] ASoC: BCM2708: Add support for RPi-DAC +Subject: [PATCH 087/101] ASoC: BCM2708: Add support for RPi-DAC This adds a machine driver for the RPi-DAC. @@ -113666,10 +108927,10 @@ Signed-off-by: Florian Meier create mode 100644 sound/soc/codecs/pcm1794a.c diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 0360c86..524ad3e 100644 +index cde1233..b1536f2 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -743,8 +743,10 @@ CONFIG_SND_SOC_DMAENGINE_PCM=y +@@ -744,8 +744,10 @@ CONFIG_SND_SOC_DMAENGINE_PCM=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_BCM2708_SOC_I2S=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m @@ -113681,10 +108942,10 @@ index 0360c86..524ad3e 100644 CONFIG_HIDRAW=y CONFIG_HID_A4TECH=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 5056993..b6348c9 100644 +index 45d0b4f..b5e4272 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -642,6 +642,20 @@ static struct platform_device snd_pcm5102a_codec_device = { +@@ -656,6 +656,20 @@ static struct platform_device snd_pcm5102a_codec_device = { }; #endif @@ -113705,7 +108966,7 @@ index 5056993..b6348c9 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -773,6 +787,11 @@ void __init bcm2708_init(void) +@@ -792,6 +806,11 @@ void __init bcm2708_init(void) bcm_register_device(&snd_pcm5102a_codec_device); #endif @@ -113961,10 +109222,10 @@ index 0000000..b4eaa44 1.9.1 -From c5f238786a77026ad4d6818e004c9b5444d7befd Mon Sep 17 00:00:00 2001 +From 74c99a005cc4541154af37d6cf0f46d1d28e72b1 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:41:23 +0100 -Subject: [PATCH 090/110] ASoC: wm8804: Implement MCLK configuration options, +Subject: [PATCH 088/101] ASoC: wm8804: Implement MCLK configuration options, add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an @@ -114081,10 +109342,10 @@ index 8ec14f5..e72d4f4 100644 1.9.1 -From 42d47e2007ab6c9e932157c5c2278595ae4307e1 Mon Sep 17 00:00:00 2001 +From 9b933935a9fad1c58197bdce75cd6f9c041561bf Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:42:08 +0100 -Subject: [PATCH 091/110] ASoC: BCM:Add support for HiFiBerry Digi. Driver is +Subject: [PATCH 089/101] ASoC: BCM:Add support for HiFiBerry Digi. Driver is based on the patched WM8804 driver. Signed-off-by: Daniel Matuschek @@ -114290,10 +109551,10 @@ index 0000000..e4f769d 1.9.1 -From 18c73b6b45c1b352881af34836b01102c675866c Mon Sep 17 00:00:00 2001 +From 34ea61992e36e6cb8614ddd7aee28af24badc93e Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:26:08 +0100 -Subject: [PATCH 092/110] BCM2708: Added support for HiFiBerry Digi board Board +Subject: [PATCH 090/101] BCM2708: Added support for HiFiBerry Digi board Board initalization by I2C Signed-off-by: Daniel Matuschek @@ -114302,10 +109563,10 @@ Signed-off-by: Daniel Matuschek 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index b6348c9..b5a41c9 100644 +index b5e4272..d7055e1 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -642,6 +642,21 @@ static struct platform_device snd_pcm5102a_codec_device = { +@@ -656,6 +656,21 @@ static struct platform_device snd_pcm5102a_codec_device = { }; #endif @@ -114327,7 +109588,7 @@ index b6348c9..b5a41c9 100644 #if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) static struct platform_device snd_rpi_dac_device = { .name = "snd-rpi-dac", -@@ -787,6 +802,11 @@ void __init bcm2708_init(void) +@@ -806,6 +821,11 @@ void __init bcm2708_init(void) bcm_register_device(&snd_pcm5102a_codec_device); #endif @@ -114343,10 +109604,10 @@ index b6348c9..b5a41c9 100644 1.9.1 -From e6556f37f881746a856809446bb6f1cac973da34 Mon Sep 17 00:00:00 2001 +From 906ff8f28e355166978b23901e30c7de50eac84b Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:27:28 +0100 -Subject: [PATCH 093/110] BCM2708: Added HiFiBerry Digi configuration option It +Subject: [PATCH 091/101] BCM2708: Added HiFiBerry Digi configuration option It will be compiled as a module by default. This also includes the WM8804 driver. @@ -114356,10 +109617,10 @@ Signed-off-by: Daniel Matuschek 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 524ad3e..cefbb24 100644 +index b1536f2..b2b9def 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -741,8 +741,10 @@ CONFIG_SND_USB_6FIRE=m +@@ -742,8 +742,10 @@ CONFIG_SND_USB_6FIRE=m CONFIG_SND_SOC=m CONFIG_SND_SOC_DMAENGINE_PCM=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y @@ -114374,10 +109635,10 @@ index 524ad3e..cefbb24 100644 1.9.1 -From 86771dc68d9edb3a3949246de4be65fd3829f5e3 Mon Sep 17 00:00:00 2001 +From 292a964cd960cf9413440320146b6a8c32f5464b Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:36:35 +0100 -Subject: [PATCH 094/110] ASoC: wm8804: Set idle_bias_off to false Idle bias +Subject: [PATCH 092/101] ASoC: wm8804: Set idle_bias_off to false Idle bias has been change to remove warning on driver startup Signed-off-by: Daniel Matuschek @@ -114402,10 +109663,10 @@ index c35b4f3..8915d08 100644 1.9.1 -From 594139ba84c038f5ca77b9ab5fbf62a01223e415 Mon Sep 17 00:00:00 2001 +From 0a3c30032fb517aebf1cdfa868634e078c2fb252 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 12 Mar 2014 11:46:34 +0000 -Subject: [PATCH 095/110] ASoc: Don't report S24_LE support, it produces white +Subject: [PATCH 093/101] ASoc: Don't report S24_LE support, it produces white noise with xbmc --- @@ -114443,10 +109704,10 @@ index 126f1e9..7812d34 100644 1.9.1 -From a8f1b4612c18f465ec6160666bf2a13d4f19ac45 Mon Sep 17 00:00:00 2001 +From 63cbbd49e0e0c22f88216c74918bacc75290b8ef Mon Sep 17 00:00:00 2001 From: Gordon Garrity Date: Sat, 8 Mar 2014 16:56:57 +0000 -Subject: [PATCH 096/110] Add IQaudIO Sound Card support for Raspberry Pi +Subject: [PATCH 094/101] Add IQaudIO Sound Card support for Raspberry Pi --- arch/arm/configs/bcmrpi_defconfig | 1 + @@ -114464,10 +109725,10 @@ Subject: [PATCH 096/110] Add IQaudIO Sound Card support for Raspberry Pi create mode 100644 sound/soc/codecs/pcm512x.h diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index cefbb24..4407a5d 100644 +index b2b9def..f0a5370 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -749,6 +749,7 @@ CONFIG_SND_BCM2708_SOC_RPI_DAC=m +@@ -750,6 +750,7 @@ CONFIG_SND_BCM2708_SOC_RPI_DAC=m CONFIG_SND_SOC_I2C_AND_SPI=m CONFIG_SND_SOC_PCM5102A=m CONFIG_SND_SOC_PCM1794A=m @@ -114476,10 +109737,10 @@ index cefbb24..4407a5d 100644 CONFIG_HIDRAW=y CONFIG_HID_A4TECH=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index b5a41c9..887f732 100644 +index d7055e1..c6f04df 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -671,6 +671,22 @@ static struct platform_device snd_pcm1794a_codec_device = { +@@ -685,6 +685,22 @@ static struct platform_device snd_pcm1794a_codec_device = { }; #endif @@ -114502,7 +109763,7 @@ index b5a41c9..887f732 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -812,6 +828,12 @@ void __init bcm2708_init(void) +@@ -831,6 +847,12 @@ void __init bcm2708_init(void) bcm_register_device(&snd_pcm1794a_codec_device); #endif @@ -115538,10 +110799,10 @@ index 0000000..b2f518e 1.9.1 -From 71d7fcd652aa5f4ec578495b4f110f5dd20d4d8a Mon Sep 17 00:00:00 2001 +From 62d6b625bef70c81e7534ef2bf71c2ebe2966611 Mon Sep 17 00:00:00 2001 From: Howard Mitchell Date: Fri, 28 Mar 2014 16:27:57 +0000 -Subject: [PATCH 097/110] Fix volsw_range functions so SOC_DOUBLE_R_RANGE_TLV +Subject: [PATCH 095/101] Fix volsw_range functions so SOC_DOUBLE_R_RANGE_TLV works. This is so that the correct rabge of values as specified @@ -115617,10 +110878,10 @@ index fe1df50..c3f41e7 100644 1.9.1 -From ee6bfcc02ec741a755414e6e7409838cab5ba57d Mon Sep 17 00:00:00 2001 +From b8664a86e8ee0c6e6ba76970b6baf634f18af7e8 Mon Sep 17 00:00:00 2001 From: Howard Mitchell Date: Fri, 28 Mar 2014 16:40:31 +0000 -Subject: [PATCH 098/110] Use a range macro for Playback Volume. +Subject: [PATCH 096/101] Use a range macro for Playback Volume. This allows limiting the output gain to avoid clipping in the DAC ouput stages. @@ -115647,10 +110908,10 @@ index 55b6200..2653311 100644 1.9.1 -From 3d3feb5d72210ce1527653de205eb4a682fa7704 Mon Sep 17 00:00:00 2001 +From 1961550498f3f7dd94aabd4ca7a1d3828d13367b Mon Sep 17 00:00:00 2001 From: Gordon Garrity Date: Sun, 30 Mar 2014 13:52:33 +0100 -Subject: [PATCH 099/110] fix soc-core's inverse range and let IQaudIO DAC use +Subject: [PATCH 097/101] fix soc-core's inverse range and let IQaudIO DAC use this fixed SOC_DOUBLE_R_RANGE_TLV support --- @@ -115704,915 +110965,10 @@ index c3f41e7..a8a753f 100644 1.9.1 -From f7528f785c8426d77586a82f1f6e67fe295b1846 Mon Sep 17 00:00:00 2001 -From: P33M -Date: Tue, 15 Apr 2014 17:29:57 +0100 -Subject: [PATCH 100/110] fiq_fsm: Push error recovery into the FIQ when - fiq_fsm is used - -If the transfer associated with a QTD failed due to a bus error, the HCD -would retry the transfer up to 3 times (implementing the USB2.0 -three-strikes retry in software). - -Due to the masking mechanism used by fiq_fsm, it is only possible to pass -a single interrupt through to the HCD per-transfer. - -In this instance host channels would fall off the radar because the error -reset would function, but the subsequent channel halt would be lost. - -Push the error count reset into the FIQ handler. ---- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 28 +++++++++++++++++++++++++++- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 4 +++- - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 6 ++++++ - drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 21 +++++++++++++++------ - 4 files changed, 51 insertions(+), 8 deletions(-) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -index e286d57..c3d64cf 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -@@ -612,6 +612,7 @@ static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_c - { - hcint_data_t hcint; - hcintmsk_data_t hcintmsk; -+ hcint_data_t hcint_probe; - hcchar_data_t hcchar; - int handled = 0; - int restart = 0; -@@ -622,7 +623,8 @@ static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_c - - hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT); - hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK); -- -+ hcint_probe.d32 = hcint.d32 & hcintmsk.d32; -+ - if (st->fsm != FIQ_PASSTHROUGH) { - fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm); - fiq_print(FIQDBG_INT, state, "%08x", hcint.d32); -@@ -635,6 +637,30 @@ static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_c - /* doesn't belong to us, kick it upstairs */ - break; - -+ case FIQ_PASSTHROUGH_ERRORSTATE: -+ /* We are here to emulate the error recovery mechanism of the dwc HCD. -+ * Several interrupts are unmasked if a previous transaction failed - it's -+ * death for the FIQ to attempt to handle them as the channel isn't halted. -+ * Emulate what the HCD does in this situation: mask and continue. -+ * The FSM has no other state setup so this has to be handled out-of-band. -+ */ -+ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n); -+ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) { -+ fiq_print(FIQDBG_ERR, state, "RESET %02d", n); -+ st->nr_errors = 0; -+ hcintmsk.b.nak = 0; -+ hcintmsk.b.ack = 0; -+ hcintmsk.b.datatglerr = 0; -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32); -+ return 1; -+ } -+ if (hcint_probe.b.chhltd) { -+ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n); -+ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32); -+ return 0; -+ } -+ break; -+ - /* Non-periodic state groups */ - case FIQ_NP_SSPLIT_STARTED: - case FIQ_NP_SSPLIT_RETRY: -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -index 716e921..bc808a0 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -@@ -155,7 +155,9 @@ extern ushort nak_holdoff; - enum fiq_fsm_state { - /* FIQ isn't enabled for this host channel */ - FIQ_PASSTHROUGH = 0, -- -+ /* For the first interrupt received for this channel, -+ * the FIQ has to ack any interrupts indicating success. */ -+ FIQ_PASSTHROUGH_ERRORSTATE = 31, - /* Nonperiodic state groups */ - FIQ_NP_SSPLIT_STARTED = 1, - FIQ_NP_SSPLIT_RETRY = 2, -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index e67437c..98f5e84 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -@@ -2073,6 +2073,12 @@ static int queue_transaction(dwc_otg_hcd_t * hcd, - hc->qh->ping_state = 0; - } - } else if (!hc->xfer_started) { -+ if (fiq_fsm_enable && hc->error_state) { -+ hcd->fiq_state->channel[hc->hc_num].nr_errors = -+ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count; -+ hcd->fiq_state->channel[hc->hc_num].fsm = -+ FIQ_PASSTHROUGH_ERRORSTATE; -+ } - dwc_otg_hc_start_transfer(hcd->core_if, hc); - hc->qh->ping_state = 0; - } -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -index e5a27f4..3b8567e 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -@@ -2600,21 +2600,30 @@ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) - release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status); - return 1; - } -+ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); - - /* - * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ. - * Execution path is fundamentally different for the channels after a FIQ has completed - * a split transaction. - */ -- -- - if (fiq_fsm_enable) { -- if (*(volatile uint32_t *)&dwc_otg_hcd->fiq_state->channel[num].fsm != FIQ_PASSTHROUGH) { -- dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num); -- return 1; -+ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) { -+ case FIQ_PASSTHROUGH: -+ break; -+ case FIQ_PASSTHROUGH_ERRORSTATE: -+ /* Hook into the error count */ -+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num); -+ if (dwc_otg_hcd->fiq_state->channel[num].nr_errors) { -+ qtd->error_count = 0; -+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET "); -+ } -+ break; -+ default: -+ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num); -+ return 1; - } - } -- qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); - - hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); - hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); --- -1.9.1 - - -From 0ddcd5604e58018c6bf80fc8e40d2f0818915add Mon Sep 17 00:00:00 2001 -From: P33M -Date: Thu, 17 Apr 2014 13:19:11 +0100 -Subject: [PATCH 101/110] fiq_fsm: Implement timeout mechanism - -For full-speed endpoints with a large packet size, interrupt latency -runs the risk of the FIQ starting a transaction too late in a full-speed -frame. If the device is still transmitting data when EOF2 for the -downstream frame occurs, the hub will disable the port. This change is -not reflected in the hub status endpoint and the device becomes -unresponsive. - -Prevent high-bandwidth transactions from being started too late in a -frame. The mechanism is not guaranteed: a combination of bit stuffing -and hub latency may still result in a device overrunning. ---- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 132 ++++++++++++++++++---------- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 2 + - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 17 +++- - drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 10 +-- - 4 files changed, 109 insertions(+), 52 deletions(-) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -index c3d64cf..161edcf 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -@@ -148,21 +148,20 @@ static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n) - static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n) - { - hcdma_data_t hcdma; -- int i = st->channel[n].nrpackets; -- int len = 254; -+ int i = st->channel[n].dma_info.index; -+ int len; - struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; - - len = fiq_get_xfer_len(st, n); - fiq_print(FIQDBG_INT, st, "LEN: %03d", len); - st->channel[n].dma_info.slot_len[i] = len; - i++; -- if (i > 5) -+ if (i > 6) - BUG(); - -- st->channel[n].nrpackets++; -- - hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0]; - FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); -+ st->channel[n].dma_info.index = i; - return 0; - } - -@@ -313,6 +312,7 @@ int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, i - * - * We also return whether this is the last CSPLIT to be queued, again based on - * heuristics. This is to allow a 1-uframe overlap of periodic split transactions. -+ * Note: requires at least 1 CSPLIT to have been performed prior to being called. - */ - - /* -@@ -335,7 +335,7 @@ static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, - int more_needed = 1; - struct fiq_channel_state *st = &state->channel[n]; - -- for (i = 0; i < st->nrpackets; i++) { -+ for (i = 0; i < st->dma_info.index; i++) { - total_len += st->dma_info.slot_len[i]; - } - -@@ -350,7 +350,7 @@ static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, - } else { - /* Isoc IN. This is a bit risky if we are the first transaction: - * we may have been held off slightly. */ -- if (i > 1 && st->dma_info.slot_len[st->nrpackets-1] <= DATA0_PID_HEURISTIC) { -+ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) { - more_needed = 0; - } - /* If in the next uframe we will receive enough data to fill the endpoint, -@@ -362,12 +362,37 @@ static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, - - if (total_len >= st->hctsiz_copy.b.xfersize || - i == 6 || total_len == 0) -+ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for -+ * a single endpoint. Accepting more would completely break our scheduling mechanism though -+ * - in these extreme cases we will pass through a truncated packet. -+ */ - more_needed = 0; - - return more_needed; - } - - /** -+ * fiq_fsm_too_late() - Test transaction for lateness -+ * -+ * If a SSPLIT for a large IN transaction is issued too late in a frame, -+ * the hub will disable the port to the device and respond with ERR handshakes. -+ * The hub status endpoint will not reflect this change. -+ * Returns 1 if we will issue a SSPLIT that will result in a device babble. -+ */ -+int notrace fiq_fsm_too_late(struct fiq_state *st, int n) -+{ -+ int uframe; -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; -+ uframe = hfnum.b.frnum & 0x7; -+ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) { -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ -+ -+/** - * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline - * - * Search pending transactions in the start-split pending state and queue them. -@@ -385,9 +410,13 @@ static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, i - if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) { - /* Check to see if any other transactions are using this TT */ - if(!fiq_fsm_tt_in_use(st, num_channels, n)) { -- st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -- fiq_print(FIQDBG_INT, st, "NEXTPER "); -- fiq_fsm_restart_channel(st, n, 0); -+ if (!fiq_fsm_too_late(st, n)) { -+ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -+ fiq_print(FIQDBG_INT, st, "NEXTPER "); -+ fiq_fsm_restart_channel(st, n, 0); -+ } else { -+ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -+ } - break; - } - } -@@ -503,7 +532,30 @@ static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_chan - { - hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) }; - int n; -- -+ int kick_irq = 0; -+ -+ if ((hfnum.b.frnum & 0x7) == 1) { -+ /* We cannot issue csplits for transactions in the last frame past (n+1).1 -+ * Check to see if there are any transactions that are stale. -+ * Boot them out. -+ */ -+ for (n = 0; n < num_channels; n++) { -+ switch (state->channel[n].fsm) { -+ case FIQ_PER_CSPLIT_WAIT: -+ case FIQ_PER_CSPLIT_NYET1: -+ case FIQ_PER_CSPLIT_POLL: -+ case FIQ_PER_CSPLIT_LAST: -+ /* Check if we are no longer in the same full-speed frame. */ -+ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) < -+ (hfnum.b.frnum & ~0x7)) -+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ - for (n = 0; n < num_channels; n++) { - switch (state->channel[n].fsm) { - -@@ -521,10 +573,16 @@ static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_chan - case FIQ_PER_SSPLIT_QUEUED: - if ((hfnum.b.frnum & 0x7) == 5) - break; -- if (!fiq_fsm_tt_in_use(state, num_channels, n)) { -- fiq_print(FIQDBG_INT, state, "SOF GO %01d", n); -- fiq_fsm_restart_channel(state, n, 0); -- state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -+ if(!fiq_fsm_tt_in_use(state, num_channels, n)) { -+ if (!fiq_fsm_too_late(state, n)) { -+ fiq_print(FIQDBG_INT, st, "SOF GO %01d", n); -+ fiq_fsm_restart_channel(state, n, 0); -+ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -+ } else { -+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -+ state->haintmsk_saved.b2.chint &= ~(1 << n); -+ kick_irq |= 1; -+ } - } - break; - -@@ -562,41 +620,27 @@ static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_chan - - } - break; -- -+ -+ case FIQ_PER_SPLIT_TIMEOUT: -+ /* Ugly: we have to force a HCD interrupt. -+ * Poke the mask for the channel in question. -+ * We will take a fake SOF because of this, but -+ * that's OK. -+ */ -+ state->haintmsk_saved.b2.chint &= ~(1 << n); -+ kick_irq |= 1; -+ break; -+ - default: - break; - } - } - -- if ((hfnum.b.frnum & 0x7) == 1) { -- /* We cannot issue csplits for transactions in the last frame past (n+1).1 -- * Check to see if there are any transactions that are stale. -- * Boot them out. -- */ -- for (n = 0; n < num_channels; n++) { -- switch (state->channel[n].fsm) { -- case FIQ_PER_CSPLIT_WAIT: -- case FIQ_PER_CSPLIT_NYET1: -- case FIQ_PER_CSPLIT_POLL: -- case FIQ_PER_CSPLIT_LAST: -- /* Check if we are no longer in the same full-speed frame. */ -- if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) < -- (hfnum.b.frnum & ~0x7)) -- state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -- break; -- default: -- break; -- } -- } -- -- } -+ if (state->kick_np_queues || -+ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum)) -+ kick_irq |= 1; - -- if (!state->kick_np_queues && -- dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) { -- return 1; -- } else { -- return 0; -- } -+ return !kick_irq; - } - - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -index bc808a0..7572958 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h -@@ -342,6 +342,8 @@ struct fiq_state { - struct fiq_channel_state channel[0]; - }; - -+extern int fiq_fsm_too_late(struct fiq_state *st, int n); -+ - extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n); - - extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels); -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index 98f5e84..042af09 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -@@ -1478,8 +1478,8 @@ int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh) - */ - int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh) - { -- int i = 0; -- uint32_t frame_length, nrslots, last_size; -+ int frame_length, i = 0; -+ uint32_t nrslots, last_size; - uint8_t *ptr = NULL; - dwc_hc_t *hc = qh->channel; - struct fiq_dma_blob *blob; -@@ -1498,6 +1498,15 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, - */ - blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; - st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; -+ /* Calculate the max number of CSPLITS such that the FIQ can time out -+ * a transaction if it fails. -+ */ -+ frame_length = st->hcchar_copy.b.mps; -+ do { -+ i++; -+ frame_length -= 188; -+ } while (frame_length >= 0); -+ st->nrpackets = i; - return 1; - } else { - if (qh->ep_type == UE_ISOCHRONOUS) { -@@ -1804,7 +1813,9 @@ int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) - start_immediate = 0; - } else if (uframe == 5) { - start_immediate = 0; -- } else if (hc->ep_type == UE_ISOCHRONOUS) { -+ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) { -+ start_immediate = 0; -+ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) { - start_immediate = 0; - } else { - /* Search through all host channels to determine if a transaction -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -index 3b8567e..dda88a3 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -@@ -2300,7 +2300,7 @@ int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qt - ptr += qtd->urb->actual_length; - } - -- for (i = 0; i < st->nrpackets; i++) { -+ for (i = 0; i < st->dma_info.index; i++) { - len += st->dma_info.slot_len[i]; - dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]); - ptr += st->dma_info.slot_len[i]; -@@ -2488,9 +2488,9 @@ int32_t dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) - - case FIQ_PER_SPLIT_NYET_ABORTED: - /* Doh. lost the data. */ -- printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " -+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " - "- FIQ reported NYET. Data may have been lost.\n", -- hc->dev_addr, hc->ep_num); -+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); - if (hc->ep_type == UE_ISOCHRONOUS) { - struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; - /* Record errors, update qtd. */ -@@ -2543,9 +2543,9 @@ int32_t dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) - - case FIQ_PER_SPLIT_TIMEOUT: - /* Couldn't complete in the nominated frame */ -- printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " -+ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " - "- FIQ timed out. Data may have been lost.\n", -- hc->dev_addr, hc->ep_num); -+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); - if (hc->ep_type == UE_ISOCHRONOUS) { - struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; - /* Record errors, update qtd. */ --- -1.9.1 - - -From 46aa9b23eca52ed395ea1e10320e6de9cbeeac39 Mon Sep 17 00:00:00 2001 -From: P33M -Date: Thu, 17 Apr 2014 15:17:48 +0100 -Subject: [PATCH 102/110] fiq_fsm: fix bounce buffer utilisation for - Isochronous OUT - -Multi-packet isochronous OUT transactions were subject to a few bounday -bugs. Fix them. - -Audio playback is now much more robust: however, an issue stands with -devices that have adaptive sinks - ALSA plays samples too fast. ---- - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 29 +++++++++-------------------- - 1 file changed, 9 insertions(+), 20 deletions(-) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index 042af09..e6b4a1e 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -@@ -1479,13 +1479,11 @@ int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh) - int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh) - { - int frame_length, i = 0; -- uint32_t nrslots, last_size; - uint8_t *ptr = NULL; - dwc_hc_t *hc = qh->channel; - struct fiq_dma_blob *blob; - struct dwc_otg_hcd_iso_packet_desc *frame_desc; - -- - for (i = 0; i < 6; i++) { - st->dma_info.slot_len[i] = 255; - } -@@ -1520,9 +1518,6 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, - blob = hcd->fiq_dmab; - - ptr = qtd->urb->buf + frame_desc->offset; -- nrslots = (frame_length + 187) / 188; -- last_size = frame_length % 188; -- //printk(KERN_INFO "len = %d nrslots = %d last_size=%d\n", frame_length, nrslots, last_size); - if (frame_length == 0) { - /* - * for isochronous transactions, we must still transmit a packet -@@ -1532,31 +1527,25 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, - st->nrpackets = 1; - } else { - do { -- if (i < nrslots - 1) { -+ if (frame_length <= 188) { -+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length); -+ st->dma_info.slot_len[i] = frame_length; -+ ptr += frame_length; -+ } else { - dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188); - st->dma_info.slot_len[i] = 188; - ptr += 188; -- } else { -- dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, last_size); -- st->dma_info.slot_len[i] = last_size; -- ptr += last_size; - } - i++; -- } while (i <= nrslots - 1); -+ frame_length -= 188; -+ } while (frame_length > 0); - st->nrpackets = i; - } - ptr = qtd->urb->buf + frame_desc->offset; -- if(DWC_MEMCMP(&blob->channel[hc->hc_num].index[0].buf[0], ptr, frame_length)) -- BUG(); - /* Point the HC at the DMA address of the bounce buffers */ - blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; -- /* Bugette: for some reason, memcpy corrupts the data in the bounce buffers. May be a -- * cache coherency issue */ -- //st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; -- //ptr = qtd->urb->buf + frame_desc->offset; -- st->hcdma_copy.d32 = (uint32_t) qtd->urb->dma + frame_desc->offset; -- if (st->hcdma_copy.d32 & 0x3) -- BUG(); -+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; -+ - /* fixup xfersize to the actual packet size */ - st->hctsiz_copy.b.pid = 0; - st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0]; --- -1.9.1 - - -From f825713b14bc667a2fcf519ff347df84c39807f2 Mon Sep 17 00:00:00 2001 -From: P33M -Date: Mon, 21 Apr 2014 09:58:52 +0100 -Subject: [PATCH 103/110] dwc_otg: Return full-speed frame numbers in HS mode - -The frame counter increments on every *microframe* in high-speed mode. -Most device drivers expect this number to be in full-speed frames - this -caused considerable confusion to e.g. snd_usb_audio which uses the -frame counter to estimate the number of samples played. ---- - drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c -index 5d45062..dc27b24 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c -@@ -626,9 +626,13 @@ void hcd_stop(struct usb_hcd *hcd) - /** Returns the current frame number. */ - static int get_frame_number(struct usb_hcd *hcd) - { -+ hprt0_data_t hprt0; - dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -- -- return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); -+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); -+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) -+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3; -+ else -+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); - } - - #ifdef DEBUG --- -1.9.1 - - -From 628fbe7f45839ea6e5570fccacd3ef14ea826933 Mon Sep 17 00:00:00 2001 -From: P33M -Date: Tue, 22 Apr 2014 14:21:49 +0100 -Subject: [PATCH 104/110] fiq_fsm: save PID on completion of interrupt OUT - transfers - -Also add edge case handling for interrupt transports. - -Note that for periodic split IN, data toggles are unimplemented in the -OTG host hardware - it unconditionally accepts any PID. ---- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 6 +++-- - drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 38 ++++++++++++++--------------- - 2 files changed, 22 insertions(+), 22 deletions(-) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -index 161edcf..e642ea1 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -@@ -920,6 +920,8 @@ static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_c - } else if (hcint.b.nyet) { - /* Doh. Data lost. */ - st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; -+ } else if (hcint.b.xacterr || hcint.b.stall) { -+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; - } else { - st->fsm = FIQ_PER_SPLIT_HS_ABORTED; - } -@@ -999,8 +1001,8 @@ static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_c - st->fsm = FIQ_PER_SPLIT_DONE; - } - } -- } else if (hcint.b.xacterr) { -- /* Local 3-strikes retry is handled by the core. This is a ERR response.*/ -+ } else if (hcint.b.xacterr || hcint.b.stall) { -+ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/ - st->fsm = FIQ_PER_SPLIT_LS_ABORTED; - } else if (hcint.b.datatglerr) { - fiq_print(FIQDBG_INT, state, "TOGGLES"); -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -index dda88a3..be8ef1b 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c -@@ -2402,36 +2402,32 @@ int32_t dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) - * split transactions and do it ourselves. - */ - if (hc->ep_type == UE_INTERRUPT) { -- if (hc->ep_is_in) { -- if (hcint.b.nak) { -+ if (hcint.b.nak) { - handle_hc_nak_intr(hcd, hc, hc_regs, qtd); -+ } else if (hc->ep_is_in) { -+ int len; -+ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num); -+ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length); -+ qtd->urb->actual_length += len; -+ if (qtd->urb->actual_length >= qtd->urb->length) { -+ qtd->urb->status = 0; -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); - } else { -- int len; -- len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num); -- //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length); -- qtd->urb->actual_length += len; -- if (qtd->urb->actual_length >= qtd->urb->length) { -+ /* Interrupt transfer not complete yet - is it a short read? */ -+ if (len < hc->max_packet) { -+ /* Interrupt transaction complete */ - qtd->urb->status = 0; - hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); - release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); - } else { -- /* Interrupt transfer not complete yet - is it a short read? */ -- if (len < hc->max_packet) { -- /* Interrupt transaction complete */ -- qtd->urb->status = 0; -- hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -- release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -- } else { -- /* Further transactions required */ -- release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -- } -- -+ /* Further transactions required */ -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); - } -- - } -- - } else { - /* Interrupt OUT complete. */ -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); - qtd->urb->actual_length += hc->xfer_len; - if (qtd->urb->actual_length >= qtd->urb->length) { - qtd->urb->status = 0; -@@ -2524,6 +2520,8 @@ int32_t dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) - * TODO: need to issue a reset to the hub port. */ - qtd->error_count += 3; - handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.stall) { -+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); - } else { - printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " - "- FIQ reported FSM=%d. Data may have been lost.\n", --- -1.9.1 - - -From c2ef4eb9f3074fafefeec3527c86f6a4b17f0811 Mon Sep 17 00:00:00 2001 -From: notro -Date: Sun, 20 Apr 2014 18:51:40 +0200 -Subject: [PATCH 105/110] mach-bcm2708: Reserve 64 IRQs for peripherals - -The Raspberry Pi does not support dynamic IRQs. Some peripherals, such -as the STMPE, add IRQ controllers. If there aren't any reserved IRQs, then -these peripherals will just fail. - -Signed-off-by: Sean Cross -Signed-off-by: Noralf Tronnes ---- - arch/arm/mach-bcm2708/include/mach/irqs.h | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm2708/include/mach/irqs.h b/arch/arm/mach-bcm2708/include/mach/irqs.h -index 9aaedf1..1947d91 100644 ---- a/arch/arm/mach-bcm2708/include/mach/irqs.h -+++ b/arch/arm/mach-bcm2708/include/mach/irqs.h -@@ -192,8 +192,9 @@ - #define HARD_IRQS (64 + 21) - #define FIQ_IRQS (64 + 21) - #define GPIO_IRQS (32*5) -+#define SPARE_IRQS (64) - --#define NR_IRQS HARD_IRQS+FIQ_IRQS+GPIO_IRQS -+#define NR_IRQS HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_IRQS - - - #endif /* _BCM2708_IRQS_H_ */ --- -1.9.1 - - -From d3add94941ab83a0f08f8d4af9fb8bf465650a41 Mon Sep 17 00:00:00 2001 -From: notro -Date: Sun, 20 Apr 2014 18:55:24 +0200 -Subject: [PATCH 106/110] bcm2708_gpio: make room for additional GPIO chips - -ARCH_NR_GPIOS is set to 54, and all is used by the onboard gpio controller. -This makes no room for additional gpio controllers to be added. - -ARCH_NR_GPIOS limits how many gpios that can be used on a platform. -From gpiolib.c: -static struct gpio_desc gpio_desc[ARCH_NR_GPIOS]; - -Lift this restraint by using the default value for ARCH_NR_GPIOS, which is 256, -and make a new macro for the on-chip number of gpios. - -Signed-off-by: Noralf Tronnes ---- - arch/arm/mach-bcm2708/bcm2708_gpio.c | 8 ++++---- - arch/arm/mach-bcm2708/include/mach/gpio.h | 2 +- - 2 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c -index bab8a49..120929ff 100644 ---- a/arch/arm/mach-bcm2708/bcm2708_gpio.c -+++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c -@@ -72,7 +72,7 @@ static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, - unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; - - //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); -- if (offset >= ARCH_NR_GPIOS) -+ if (offset >= BCM2708_NR_GPIOS) - return -EINVAL; - - spin_lock_irqsave(&lock, flags); -@@ -110,7 +110,7 @@ static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) - unsigned gpio_field_offset = (offset - 32 * gpio_bank); - unsigned lev; - -- if (offset >= ARCH_NR_GPIOS) -+ if (offset >= BCM2708_NR_GPIOS) - return 0; - lev = readl(gpio->base + GPIOLEV(gpio_bank)); - //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); -@@ -123,7 +123,7 @@ static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) - unsigned gpio_bank = offset / 32; - unsigned gpio_field_offset = (offset - 32 * gpio_bank); - //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); -- if (offset >= ARCH_NR_GPIOS) -+ if (offset >= BCM2708_NR_GPIOS) - return; - if (value) - writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); -@@ -302,7 +302,7 @@ static int bcm2708_gpio_probe(struct platform_device *dev) - - ucb->gc.label = "bcm2708_gpio"; - ucb->gc.base = 0; -- ucb->gc.ngpio = ARCH_NR_GPIOS; -+ ucb->gc.ngpio = BCM2708_NR_GPIOS; - ucb->gc.owner = THIS_MODULE; - - ucb->gc.direction_input = bcm2708_gpio_dir_in; -diff --git a/arch/arm/mach-bcm2708/include/mach/gpio.h b/arch/arm/mach-bcm2708/include/mach/gpio.h -index 753dc06..7965a97 100644 ---- a/arch/arm/mach-bcm2708/include/mach/gpio.h -+++ b/arch/arm/mach-bcm2708/include/mach/gpio.h -@@ -9,7 +9,7 @@ - #ifndef __ASM_ARCH_GPIO_H - #define __ASM_ARCH_GPIO_H - --#define ARCH_NR_GPIOS 54 // number of gpio lines -+#define BCM2708_NR_GPIOS 54 // number of gpio lines - - #define gpio_to_irq(x) ((x) + GPIO_IRQ_START) - #define irq_to_gpio(x) ((x) - GPIO_IRQ_START) --- -1.9.1 - - -From f326a174fd0702508a3de99dcdbf346e1fcdfb43 Mon Sep 17 00:00:00 2001 -From: P33M -Date: Wed, 23 Apr 2014 16:01:52 +0100 -Subject: [PATCH 107/110] fiq_fsm: add missing case for fiq_fsm_tt_in_use() - -Certain combinations of bitrate and endpoint activity could -result in a periodic transaction erroneously getting started -while the previous Isochronous OUT was still active. ---- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -index e642ea1..ecb7b14 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -@@ -286,6 +286,7 @@ int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, i - case FIQ_PER_CSPLIT_NYET1: - //case FIQ_PER_CSPLIT_POLL: - case FIQ_PER_ISO_OUT_ACTIVE: -+ case FIQ_PER_ISO_OUT_LAST: - if (st->channel[i].hub_addr == hub_addr && - st->channel[i].port_addr == port_addr) { - in_use = 1; --- -1.9.1 - - -From bab8d459e7156d7f383ce0cc2f6507d27f120175 Mon Sep 17 00:00:00 2001 -From: P33M -Date: Thu, 24 Apr 2014 17:04:30 +0100 -Subject: [PATCH 108/110] fiq_fsm: clear hcintmsk for aborted transactions - -Prevents the FIQ from erroneously handling interrupts -on a timed out channel. ---- - drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -index ecb7b14..61f5534 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c -@@ -580,8 +580,10 @@ static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_chan - fiq_fsm_restart_channel(state, n, 0); - state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; - } else { -+ /* Transaction cannot be started without risking a device babble error */ - state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; - state->haintmsk_saved.b2.chint &= ~(1 << n); -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); - kick_irq |= 1; - } - } -@@ -629,6 +631,7 @@ static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_chan - * that's OK. - */ - state->haintmsk_saved.b2.chint &= ~(1 << n); -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); - kick_irq |= 1; - break; - --- -1.9.1 - - -From 84cee746ceb1f94fe7a777f13a2af9a40d3d88b4 Mon Sep 17 00:00:00 2001 +From cc1bf1bacb9deb46d9ac7cd3700f99880f340373 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 22 Apr 2014 13:58:14 +0100 -Subject: [PATCH 109/110] lirc_rpi: Use read_current_timer to determine +Subject: [PATCH 098/101] lirc_rpi: Use read_current_timer to determine transmitter delay. Thanks to jjmz and others See: https://github.com/raspberrypi/linux/issues/525 @@ -116710,44 +111066,4939 @@ index 8aee83f..57ffacf 100644 1.9.1 -From 4b3694f20b99274c03043ab931095481c9180cd8 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sun, 27 Apr 2014 17:52:12 +0100 -Subject: [PATCH 110/110] snd-bcm2835: Ensure alsa_stream is null on failure to - avoid kernel panic +From c176c12e81f9ebd0fe9c5b0f8b0a4283aae14eed Mon Sep 17 00:00:00 2001 +From: P33M +Date: Wed, 19 Mar 2014 15:13:53 +0000 +Subject: [PATCH 099/101] Fix ARM architecture issue with local_irq_restore() +If local_fiq_enable() is called before a local_irq_restore(flags) where +the flags variable has the F bit set, the FIQ will be erroneously disabled. + +Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR. + +Also fix some of the hacks previously implemented for previous dwc_otg +incarnations. --- - sound/arm/bcm2835-pcm.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) + arch/arm/include/asm/fiq.h | 1 - + arch/arm/include/asm/irqflags.h | 16 +++++++++++++--- + arch/arm/kernel/fiq.c | 1 - + arch/arm/kernel/fiqasm.S | 3 --- + drivers/usb/host/dwc_common_port/dwc_common_linux.c | 1 + + 5 files changed, 14 insertions(+), 8 deletions(-) -diff --git a/sound/arm/bcm2835-pcm.c b/sound/arm/bcm2835-pcm.c -index fe27a8f..ebd3f62 100755 ---- a/sound/arm/bcm2835-pcm.c -+++ b/sound/arm/bcm2835-pcm.c -@@ -161,6 +161,11 @@ static int snd_bcm2835_playback_open_generic( - alsa_stream->enable_fifo_irq = 0; - alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq; +diff --git a/arch/arm/include/asm/fiq.h b/arch/arm/include/asm/fiq.h +index f1a131b..d493d0b 100644 +--- a/arch/arm/include/asm/fiq.h ++++ b/arch/arm/include/asm/fiq.h +@@ -42,7 +42,6 @@ extern void disable_fiq(int fiq); + /* helpers defined in fiqasm.S: */ + extern void __set_fiq_regs(unsigned long const *regs); + extern void __get_fiq_regs(unsigned long *regs); +-extern void __FIQ_Branch(unsigned long *regs); -+ err = bcm2835_audio_open(alsa_stream); -+ if (err != 0) { -+ kfree(alsa_stream); -+ return err; -+ } - runtime->private_data = alsa_stream; - runtime->private_free = snd_bcm2835_playback_free; - if (spdif) { -@@ -174,11 +179,6 @@ static int snd_bcm2835_playback_open_generic( - snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, - 16); + static inline void set_fiq_regs(struct pt_regs const *regs) + { +diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h +index 3b763d6..5770408 100644 +--- a/arch/arm/include/asm/irqflags.h ++++ b/arch/arm/include/asm/irqflags.h +@@ -145,12 +145,22 @@ static inline unsigned long arch_local_save_flags(void) + } -- err = bcm2835_audio_open(alsa_stream); -- if (err != 0) { -- kfree(alsa_stream); -- return err; -- } - chip->alsa_stream[idx] = alsa_stream; + /* +- * restore saved IRQ & FIQ state ++ * restore saved IRQ state + */ + static inline void arch_local_irq_restore(unsigned long flags) + { +- asm volatile( +- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" ++ unsigned long temp = 0; ++ flags &= ~(1 << 6); ++ asm volatile ( ++ " mrs %0, cpsr" ++ : "=r" (temp) ++ : ++ : "memory", "cc"); ++ /* Preserve FIQ bit */ ++ temp &= (1 << 6); ++ flags = flags | temp; ++ asm volatile ( ++ " msr cpsr_c, %0 @ local_irq_restore" + : + : "r" (flags) + : "memory", "cc"); +diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c +index aac11f8..918875d 100644 +--- a/arch/arm/kernel/fiq.c ++++ b/arch/arm/kernel/fiq.c +@@ -142,7 +142,6 @@ void disable_fiq(int fiq) + EXPORT_SYMBOL(set_fiq_handler); + EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */ + EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */ +-EXPORT_SYMBOL(__FIQ_Branch); /* defined in fiqasm.S */ + EXPORT_SYMBOL(claim_fiq); + EXPORT_SYMBOL(release_fiq); + EXPORT_SYMBOL(enable_fiq); +diff --git a/arch/arm/kernel/fiqasm.S b/arch/arm/kernel/fiqasm.S +index 93eddfe..5233d54 100644 +--- a/arch/arm/kernel/fiqasm.S ++++ b/arch/arm/kernel/fiqasm.S +@@ -25,9 +25,6 @@ + ENTRY(__set_fiq_regs) + mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE + mrs r1, cpsr +-@@@@@@@@@@@@@@@ hack: enable the fiq here to keep usb driver happy +- and r1, #~PSR_F_BIT +-@@@@@@@@@@@@@@@ endhack: (need to find better place for this to happen) + msr cpsr_c, r2 @ select FIQ mode + mov r0, r0 @ avoid hazard prior to ARMv4 + ldmia r0!, {r8 - r12} +diff --git a/drivers/usb/host/dwc_common_port/dwc_common_linux.c b/drivers/usb/host/dwc_common_port/dwc_common_linux.c +index 0812d3a..6d01261 100644 +--- a/drivers/usb/host/dwc_common_port/dwc_common_linux.c ++++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c +@@ -585,6 +585,7 @@ void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_ + local_irq_save(flags); + local_fiq_disable(); + writel((readl(reg) & ~clear_mask) | set_mask, reg); ++ local_fiq_enable(); + local_irq_restore(flags); + } - chip->opened |= (1 << idx); +-- +1.9.1 + + +From 5c139e438f3b893b9d2443130c8767653fdf46db Mon Sep 17 00:00:00 2001 +From: P33M +Date: Wed, 19 Mar 2014 12:58:23 +0000 +Subject: [PATCH 100/101] dwc_otg: fiq_fsm: Base commit for driver rewrite + +This commit removes the previous FIQ fixes entirely and adds fiq_fsm. + +This rewrite features much more complete support for split transactions +and takes into account several OTG hardware bugs. High-speed +isochronous transactions are also capable of being performed by fiq_fsm. + +All driver options have been removed and replaced with: + - dwc_otg.fiq_enable (bool) + - dwc_otg.fiq_fsm_enable (bool) + - dwc_otg.fiq_fsm_mask (bitmask) + - dwc_otg.nak_holdoff (unsigned int) + +Defaults are specified such that fiq_fsm behaves similarly to the +previously implemented FIQ fixes. + +fiq_fsm: Push error recovery into the FIQ when fiq_fsm is used + +If the transfer associated with a QTD failed due to a bus error, the HCD +would retry the transfer up to 3 times (implementing the USB2.0 +three-strikes retry in software). + +Due to the masking mechanism used by fiq_fsm, it is only possible to pass +a single interrupt through to the HCD per-transfer. + +In this instance host channels would fall off the radar because the error +reset would function, but the subsequent channel halt would be lost. + +Push the error count reset into the FIQ handler. + +fiq_fsm: Implement timeout mechanism + +For full-speed endpoints with a large packet size, interrupt latency +runs the risk of the FIQ starting a transaction too late in a full-speed +frame. If the device is still transmitting data when EOF2 for the +downstream frame occurs, the hub will disable the port. This change is +not reflected in the hub status endpoint and the device becomes +unresponsive. + +Prevent high-bandwidth transactions from being started too late in a +frame. The mechanism is not guaranteed: a combination of bit stuffing +and hub latency may still result in a device overrunning. + +fiq_fsm: fix bounce buffer utilisation for Isochronous OUT + +Multi-packet isochronous OUT transactions were subject to a few bounday +bugs. Fix them. + +Audio playback is now much more robust: however, an issue stands with +devices that have adaptive sinks - ALSA plays samples too fast. + +dwc_otg: Return full-speed frame numbers in HS mode + +The frame counter increments on every *microframe* in high-speed mode. +Most device drivers expect this number to be in full-speed frames - this +caused considerable confusion to e.g. snd_usb_audio which uses the +frame counter to estimate the number of samples played. + +fiq_fsm: save PID on completion of interrupt OUT transfers + +Also add edge case handling for interrupt transports. + +Note that for periodic split IN, data toggles are unimplemented in the +OTG host hardware - it unconditionally accepts any PID. + +fiq_fsm: add missing case for fiq_fsm_tt_in_use() + +Certain combinations of bitrate and endpoint activity could +result in a periodic transaction erroneously getting started +while the previous Isochronous OUT was still active. + +fiq_fsm: clear hcintmsk for aborted transactions + +Prevents the FIQ from erroneously handling interrupts +on a timed out channel. + +fiq_fsm: enable by default +--- + arch/arm/mach-bcm2708/bcm2708.c | 19 - + drivers/usb/host/dwc_otg/Makefile | 3 +- + drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 47 +- + drivers/usb/host/dwc_otg/dwc_otg_driver.c | 47 +- + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 1293 ++++++++++++++++++++++++++ + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 353 +++++++ + drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S | 81 ++ + drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 765 ++++++++++++--- + drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 11 + + drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 986 +++++++++----------- + drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 109 ++- + drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 41 +- + drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c | 113 --- + drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h | 48 - + 14 files changed, 2964 insertions(+), 952 deletions(-) + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S + delete mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c + delete mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h + +diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c +index c6f04df..887f732 100644 +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -328,20 +328,6 @@ static struct resource bcm2708_usb_resources[] = { + }, + }; + +-bool fiq_fix_enable = true; +- +-static struct resource bcm2708_usb_resources_no_fiq_fix[] = { +- [0] = { +- .start = USB_BASE, +- .end = USB_BASE + SZ_128K - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = IRQ_USB, +- .end = IRQ_USB, +- .flags = IORESOURCE_IRQ, +- }, +-}; + + static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + +@@ -805,11 +791,6 @@ void __init bcm2708_init(void) + #endif + bcm_register_device(&bcm2708_systemtimer_device); + bcm_register_device(&bcm2708_fb_device); +- if (!fiq_fix_enable) +- { +- bcm2708_usb_device.resource = bcm2708_usb_resources_no_fiq_fix; +- bcm2708_usb_device.num_resources = ARRAY_SIZE(bcm2708_usb_resources_no_fiq_fix); +- } + bcm_register_device(&bcm2708_usb_device); + bcm_register_device(&bcm2708_uart1_device); + bcm_register_device(&bcm2708_powerman_device); +diff --git a/drivers/usb/host/dwc_otg/Makefile b/drivers/usb/host/dwc_otg/Makefile +index a56f193..e7bdd12 100644 +--- a/drivers/usb/host/dwc_otg/Makefile ++++ b/drivers/usb/host/dwc_otg/Makefile +@@ -36,7 +36,8 @@ dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o + dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o + dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o + dwc_otg-objs += dwc_otg_adp.o +-dwc_otg-objs += dwc_otg_mphi_fix.o ++dwc_otg-objs += dwc_otg_fiq_fsm.o ++dwc_otg-objs += dwc_otg_fiq_stub.o + ifneq ($(CFI),) + dwc_otg-objs += dwc_otg_cfi.o + endif +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +index 2f8b3bd..065807f 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +@@ -45,7 +45,6 @@ + #include "dwc_otg_driver.h" + #include "dwc_otg_pcd.h" + #include "dwc_otg_hcd.h" +-#include "dwc_otg_mphi_fix.h" + + #ifdef DEBUG + inline const char *op_state_str(dwc_otg_core_if_t * core_if) +@@ -1319,7 +1318,7 @@ static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if) + /** + * This function returns the Core Interrupt register. + */ +-static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk) ++static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd) + { + gahbcfg_data_t gahbcfg = {.d32 = 0 }; + gintsts_data_t gintsts; +@@ -1345,16 +1344,15 @@ static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gin + } + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); + gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); +- { +- unsigned long flags; +- +- // Re-enable the saved interrupts +- local_irq_save(flags); ++ if(fiq_enable) { + local_fiq_disable(); +- gintmsk.d32 |= gintmsk_common.d32; +- gintsts_saved.d32 &= ~gintmsk_common.d32; +- reenable_gintmsk->d32 = gintmsk.d32; +- local_irq_restore(flags); ++ /* Pull in the interrupts that the FIQ has masked */ ++ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32); ++ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */ ++ reenable_gintmsk->d32 |= gintmsk.d32; ++ reenable_gintmsk->d32 |= ~(hcd->fiq_state->gintmsk_saved.d32); ++ reenable_gintmsk->d32 &= gintmsk_common.d32; ++ local_fiq_enable(); + } + + gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); +@@ -1366,13 +1364,15 @@ static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gin + gintsts.d32, gintmsk.d32); + } + #endif +- if (!fiq_fix_enable){ ++ if (!fiq_enable){ + if (gahbcfg.b.glblintrmsk) + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); + else + return 0; +- } +- else { ++ } else { ++ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface. ++ * Can't trust the global interrupt mask bit in this case. ++ */ + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); + } + +@@ -1406,7 +1406,7 @@ int32_t dwc_otg_handle_common_intr(void *dev) + { + int retval = 0; + gintsts_data_t gintsts; +- gintmsk_data_t reenable_gintmsk; ++ gintmsk_data_t gintmsk_reenable = { .d32 = 0 }; + gpwrdn_data_t gpwrdn = {.d32 = 0 }; + dwc_otg_device_t *otg_dev = dev; + dwc_otg_core_if_t *core_if = otg_dev->core_if; +@@ -1428,7 +1428,10 @@ int32_t dwc_otg_handle_common_intr(void *dev) + } + + if (core_if->hibernation_suspend <= 0) { +- gintsts.d32 = dwc_otg_read_common_intr(core_if, &reenable_gintmsk); ++ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end ++ * of this handler - god only knows why it's done like this ++ */ ++ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd); + + if (gintsts.b.modemismatch) { + retval |= dwc_otg_handle_mode_mismatch_intr(core_if); +@@ -1525,11 +1528,16 @@ int32_t dwc_otg_handle_common_intr(void *dev) + gintsts.b.portintr = 1; + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); + retval |= 1; +- reenable_gintmsk.b.portintr = 1; ++ gintmsk_reenable.b.portintr = 1; + + } +- +- DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, reenable_gintmsk.d32); ++ /* Did we actually handle anything? if so, unmask the interrupt */ ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval); ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32); ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32); ++ if (retval) { ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32); ++ } + + } else { + DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32); +@@ -1583,6 +1591,5 @@ int32_t dwc_otg_handle_common_intr(void *dev) + } + if (core_if->lock) + DWC_SPINUNLOCK(core_if->lock); +- + return retval; + } +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_driver.c b/drivers/usb/host/dwc_otg/dwc_otg_driver.c +index f06c3d22..bbf63a4 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c +@@ -56,6 +56,7 @@ + #include "dwc_otg_core_if.h" + #include "dwc_otg_pcd_if.h" + #include "dwc_otg_hcd_if.h" ++#include "dwc_otg_fiq_fsm.h" + + #define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" + #define DWC_DRIVER_DESC "HS OTG USB Controller driver" +@@ -64,7 +65,6 @@ bool microframe_schedule=true; + + static const char dwc_driver_name[] = "dwc_otg"; + +-extern void* dummy_send; + + extern int pcd_init( + #ifdef LM_INTERFACE +@@ -240,13 +240,14 @@ static struct dwc_otg_driver_module_params dwc_otg_module_params = { + .adp_enable = -1, + }; + +-//Global variable to switch the fiq fix on or off (declared in bcm2708.c) +-extern bool fiq_fix_enable; ++//Global variable to switch the fiq fix on or off ++bool fiq_enable = 1; + // Global variable to enable the split transaction fix +-bool fiq_split_enable = true; +-//Global variable to switch the nak holdoff on or off +-bool nak_holdoff_enable = true; ++bool fiq_fsm_enable = true; ++//Bulk split-transaction NAK holdoff in microframes ++uint16_t nak_holdoff = 8; + ++unsigned short fiq_fsm_mask = 0x07; + + /** + * This function shows the Driver Version. +@@ -800,7 +801,7 @@ static int dwc_otg_driver_probe( + dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start, + _dev->resource[0].end - + _dev->resource[0].start+1); +- if (fiq_fix_enable) ++ if (fiq_enable) + { + if (!request_mem_region(_dev->resource[1].start, + _dev->resource[1].end - _dev->resource[1].start + 1, +@@ -813,7 +814,6 @@ static int dwc_otg_driver_probe( + dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start, + _dev->resource[1].end - + _dev->resource[1].start + 1); +- dummy_send = (void *) kmalloc(16, GFP_ATOMIC); + } + + #else +@@ -1071,9 +1071,9 @@ static int __init dwc_otg_driver_init(void) + int error; + struct device_driver *drv; + +- if(fiq_split_enable && !fiq_fix_enable) { +- printk(KERN_WARNING "dwc_otg: fiq_split_enable was set without fiq_fix_enable! Correcting.\n"); +- fiq_fix_enable = 1; ++ if(fiq_fsm_enable && !fiq_enable) { ++ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n"); ++ fiq_enable = 1; + } + + printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, +@@ -1095,9 +1095,9 @@ static int __init dwc_otg_driver_init(void) + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + return retval; + } +- printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_fix_enable ? "enabled":"disabled"); +- printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff_enable ? "enabled":"disabled"); +- printk(KERN_DEBUG "dwc_otg: FIQ split fix %s\n", fiq_split_enable ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled"); + + error = driver_create_file(drv, &driver_attr_version); + #ifdef DEBUG +@@ -1378,12 +1378,19 @@ MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); + module_param(microframe_schedule, bool, 0444); + MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); + +-module_param(fiq_fix_enable, bool, 0444); +-MODULE_PARM_DESC(fiq_fix_enable, "Enable the fiq fix"); +-module_param(nak_holdoff_enable, bool, 0444); +-MODULE_PARM_DESC(nak_holdoff_enable, "Enable the NAK holdoff"); +-module_param(fiq_split_enable, bool, 0444); +-MODULE_PARM_DESC(fiq_split_enable, "Enable the FIQ fix on split transactions"); ++module_param(fiq_enable, bool, 0444); ++MODULE_PARM_DESC(fiq_enable, "Enable the FIQ"); ++module_param(nak_holdoff, ushort, 0644); ++MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8"); ++module_param(fiq_fsm_enable, bool, 0444); ++MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask"); ++module_param(fiq_fsm_mask, ushort, 0444); ++MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n" ++ "Bit 0 : Non-periodic split transactions\n" ++ "Bit 1 : Periodic split transactions\n" ++ "Bit 2 : High-speed multi-transfer isochronous\n" ++ "All other bits should be set 0."); ++ + + /** @page "Module Parameters" + * +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c +new file mode 100644 +index 0000000..61f5534 +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c +@@ -0,0 +1,1293 @@ ++/* ++ * dwc_otg_fiq_fsm.c - The finite state machine FIQ ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This FIQ implements functionality that performs split transactions on ++ * the dwc_otg hardware without any outside intervention. A split transaction ++ * is "queued" by nominating a specific host channel to perform the entirety ++ * of a split transaction. This FIQ will then perform the microframe-precise ++ * scheduling required in each phase of the transaction until completion. ++ * ++ * The FIQ functionality is glued into the Synopsys driver via the entry point ++ * in the FSM enqueue function, and at the exit point in handling a HC interrupt ++ * for a FSM-enabled channel. ++ * ++ * NB: Large parts of this implementation have architecture-specific code. ++ * For porting this functionality to other ARM machines, the minimum is required: ++ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed ++ * to the FIQ ++ * - A method of forcing a software generated interrupt from FIQ mode that then ++ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number) ++ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same ++ * processor core - there is no locking between the FIQ and IRQ (aside from ++ * local_fiq_disable) ++ * ++ */ ++ ++#include "dwc_otg_fiq_fsm.h" ++ ++ ++char buffer[1000*16]; ++int wptr; ++void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...) ++{ ++ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR; ++ va_list args; ++ char text[17]; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) }; ++ ++ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR) ++ { ++ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7); ++ va_start(args, fmt); ++ vsnprintf(text+8, 9, fmt, args); ++ va_end(args); ++ ++ memcpy(buffer + wptr, text, 16); ++ wptr = (wptr + 16) % sizeof(buffer); ++ } ++} ++ ++/** ++ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction ++ * @channel: channel to re-enable ++ */ ++static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force) ++{ ++ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) }; ++ ++ hcchar.b.chen = 0; ++ if (st->channel[n].hcchar_copy.b.eptype & 0x1) { ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ /* Hardware bug workaround: update the ssplit index */ ++ if (st->channel[n].hcsplt_copy.b.spltena) ++ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; ++ ++ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; ++ } ++ ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); ++ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ hcchar.b.chen = 1; ++ ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); ++ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force); ++} ++ ++/** ++ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage ++ * @st: Pointer to the channel's state ++ * @n : channel number ++ * ++ * Change host channel registers to perform a complete-split transaction. Being mindful of the ++ * endpoint direction, set control regs up correctly. ++ */ ++static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n) ++{ ++ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) }; ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ ++ hcsplt.b.compsplt = 1; ++ if (st->channel[n].hcchar_copy.b.epdir == 1) { ++ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket. ++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; ++ } else { ++ // If OUT, the CSPLIT result contains handshake only. ++ hctsiz.b.xfersize = 0; ++ } ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++ mb(); ++} ++ ++static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n) ++{ ++ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */ ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ ++ if (st->channel[n].hcchar_copy.b.epdir == 0) { ++ return st->channel[n].hctsiz_copy.b.xfersize; ++ } else { ++ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize; ++ } ++ ++} ++ ++ ++/** ++ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT ++ * ++ * Of use only for IN periodic transfers. ++ */ ++static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n) ++{ ++ hcdma_data_t hcdma; ++ int i = st->channel[n].dma_info.index; ++ int len; ++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; ++ ++ len = fiq_get_xfer_len(st, n); ++ fiq_print(FIQDBG_INT, st, "LEN: %03d", len); ++ st->channel[n].dma_info.slot_len[i] = len; ++ i++; ++ if (i > 6) ++ BUG(); ++ ++ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0]; ++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ st->channel[n].dma_info.index = i; ++ return 0; ++} ++ ++/** ++ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ ++ */ ++static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n) ++{ ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; ++ hctsiz.b.pktcnt = 1; ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++} ++ ++/** ++ * fiq_iso_out_advance() - update DMA address and split position bits ++ * for isochronous OUT transactions. ++ * ++ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and ++ * Split-BEGIN states are not handled - this is done when the transaction was queued. ++ * ++ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state. ++ */ ++static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n) ++{ ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ hcdma_data_t hcdma; ++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; ++ int last = 0; ++ int i = st->channel[n].dma_info.index; ++ ++ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i); ++ i++; ++ if (i == 4) ++ last = 1; ++ if (st->channel[n].dma_info.slot_len[i+1] == 255) ++ last = 1; ++ ++ /* New DMA address - address of bounce buffer referred to in index */ ++ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0]; ++ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n)); ++ //hcdma.d32 += st->channel[n].dma_info.slot_len[i]; ++ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last); ++ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]); ++ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT); ++ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ); ++ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID; ++ /* Set up new packet length */ ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i]; ++ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32); ++ ++ st->channel[n].dma_info.index++; ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ return last; ++} ++ ++/** ++ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT ++ * ++ * Despite the limitations of the DWC core, we can force a microframe pipeline of ++ * isochronous OUT start-split transactions while waiting for a corresponding other-type ++ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it ++ * is very unlikely that filling the start-split FIFO will cause data loss. ++ * This allows much better interleaving of transactions in an order-independent way- ++ * there is no requirement to prioritise isochronous, just a state-space search has ++ * to be performed on each periodic start-split complete interrupt. ++ */ ++static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n) ++{ ++ int hub_addr = st->channel[n].hub_addr; ++ int port_addr = st->channel[n].port_addr; ++ int i, poked = 0; ++ for (i = 0; i < num_channels; i++) { ++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ if (st->channel[i].hub_addr == hub_addr && ++ st->channel[i].port_addr == port_addr) { ++ switch (st->channel[i].fsm) { ++ case FIQ_PER_ISO_OUT_PENDING: ++ if (st->channel[i].nrpackets == 1) { ++ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ fiq_fsm_restart_channel(st, i, 0); ++ poked = 1; ++ break; ++ ++ default: ++ break; ++ } ++ } ++ if (poked) ++ break; ++ } ++ return poked; ++} ++ ++/** ++ * fiq_fsm_tt_in_use() - search for host channels using this TT ++ * @n: Channel to use as reference ++ * ++ */ ++int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n) ++{ ++ int hub_addr = st->channel[n].hub_addr; ++ int port_addr = st->channel[n].port_addr; ++ int i, in_use = 0; ++ for (i = 0; i < num_channels; i++) { ++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ switch (st->channel[i].fsm) { ++ /* TT is reserved for channels that are in the middle of a periodic ++ * split transaction. ++ */ ++ case FIQ_PER_SSPLIT_STARTED: ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ //case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ case FIQ_PER_ISO_OUT_LAST: ++ if (st->channel[i].hub_addr == hub_addr && ++ st->channel[i].port_addr == port_addr) { ++ in_use = 1; ++ } ++ break; ++ default: ++ break; ++ } ++ if (in_use) ++ break; ++ } ++ return in_use; ++} ++ ++/** ++ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need ++ * to be issued for this IN transaction. ++ * ++ * We cannot tell the inbound PID of a data packet due to hardware limitations. ++ * we need to make an educated guess as to whether we need to queue another CSPLIT ++ * or not. A no-brainer is when we have received enough data to fill the endpoint ++ * size, but for endpoints that give variable-length data then we have to resort ++ * to heuristics. ++ * ++ * We also return whether this is the last CSPLIT to be queued, again based on ++ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions. ++ * Note: requires at least 1 CSPLIT to have been performed prior to being called. ++ */ ++ ++/* ++ * We need some way of guaranteeing if a returned periodic packet of size X ++ * has a DATA0 PID. ++ * The heuristic value of 144 bytes assumes that the received data has maximal ++ * bit-stuffing and the clock frequency of the transmitting device is at the lowest ++ * permissible limit. If the transfer length results in a final packet size ++ * 144 < p <= 188, then an erroneous CSPLIT will be issued. ++ * Also used to ensure that an endpoint will nominally only return a single ++ * complete-split worth of data. ++ */ ++#define DATA0_PID_HEURISTIC 144 ++ ++static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last) ++{ ++ ++ int i; ++ int total_len = 0; ++ int more_needed = 1; ++ struct fiq_channel_state *st = &state->channel[n]; ++ ++ for (i = 0; i < st->dma_info.index; i++) { ++ total_len += st->dma_info.slot_len[i]; ++ } ++ ++ *probably_last = 0; ++ ++ if (st->hcchar_copy.b.eptype == 0x3) { ++ /* ++ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data ++ * then this is definitely the last CSPLIT. ++ */ ++ *probably_last = 1; ++ } else { ++ /* Isoc IN. This is a bit risky if we are the first transaction: ++ * we may have been held off slightly. */ ++ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) { ++ more_needed = 0; ++ } ++ /* If in the next uframe we will receive enough data to fill the endpoint, ++ * then only issue 1 more csplit. ++ */ ++ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC) ++ *probably_last = 1; ++ } ++ ++ if (total_len >= st->hctsiz_copy.b.xfersize || ++ i == 6 || total_len == 0) ++ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for ++ * a single endpoint. Accepting more would completely break our scheduling mechanism though ++ * - in these extreme cases we will pass through a truncated packet. ++ */ ++ more_needed = 0; ++ ++ return more_needed; ++} ++ ++/** ++ * fiq_fsm_too_late() - Test transaction for lateness ++ * ++ * If a SSPLIT for a large IN transaction is issued too late in a frame, ++ * the hub will disable the port to the device and respond with ERR handshakes. ++ * The hub status endpoint will not reflect this change. ++ * Returns 1 if we will issue a SSPLIT that will result in a device babble. ++ */ ++int notrace fiq_fsm_too_late(struct fiq_state *st, int n) ++{ ++ int uframe; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ uframe = hfnum.b.frnum & 0x7; ++ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) { ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++ ++/** ++ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline ++ * ++ * Search pending transactions in the start-split pending state and queue them. ++ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4). ++ * Note: we specifically don't do isochronous OUT transactions first because better ++ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT. ++ */ ++static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels) ++{ ++ int n; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ if ((hfnum.b.frnum & 0x7) == 5) ++ return; ++ for (n = 0; n < num_channels; n++) { ++ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) { ++ /* Check to see if any other transactions are using this TT */ ++ if(!fiq_fsm_tt_in_use(st, num_channels, n)) { ++ if (!fiq_fsm_too_late(st, n)) { ++ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; ++ fiq_print(FIQDBG_INT, st, "NEXTPER "); ++ fiq_fsm_restart_channel(st, n, 0); ++ } else { ++ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ } ++ break; ++ } ++ } ++ } ++ for (n = 0; n < num_channels; n++) { ++ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) { ++ if (!fiq_fsm_tt_in_use(st, num_channels, n)) { ++ fiq_print(FIQDBG_INT, st, "NEXTISO "); ++ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ fiq_fsm_restart_channel(st, n, 0); ++ break; ++ } ++ } ++ } ++} ++ ++/** ++ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data ++ * @state: Pointer to fiq_state ++ * @n: Channel transaction is active on ++ * @hcint: Copy of host channel interrupt register ++ * ++ * Returns 0 if there are no more transactions for this HC to do, 1 ++ * otherwise. ++ */ ++static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint) ++{ ++ struct fiq_channel_state *st = &state->channel[n]; ++ int xfer_len = 0, nrpackets = 0; ++ hcdma_data_t hcdma; ++ fiq_print(FIQDBG_INT, state, "HSISO %02d", n); ++ ++ xfer_len = fiq_get_xfer_len(state, n); ++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len; ++ ++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32; ++ ++ st->hs_isoc_info.index++; ++ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) { ++ return 0; ++ } ++ ++ /* grab the next DMA address offset from the array */ ++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset; ++ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ ++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as ++ * the core needs to be told to send the correct number. Caution: for IN transfers, ++ * this is always set to the maximum size of the endpoint. */ ++ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length; ++ /* Integer divide in a FIQ: fun. FIXME: make this not suck */ ++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; ++ if (nrpackets == 0) ++ nrpackets = 1; ++ st->hcchar_copy.b.multicnt = nrpackets; ++ st->hctsiz_copy.b.pktcnt = nrpackets; ++ ++ /* Initial PID also needs to be set */ ++ if (st->hcchar_copy.b.epdir == 0) { ++ st->hctsiz_copy.b.xfersize = xfer_len; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_MDATA; ++ break; ++ } ++ ++ } else { ++ switch (st->hcchar_copy.b.multicnt) { ++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA1; ++ break; ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA2; ++ break; ++ } ++ } ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32); ++ /* Channel is enabled on hcint handler exit */ ++ fiq_print(FIQDBG_INT, state, "HSISOOUT"); ++ return 1; ++} ++ ++ ++/** ++ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler ++ * @state: Pointer to the state struct passed from banked FIQ mode registers. ++ * @num_channels: set according to the DWC hardware configuration ++ * ++ * The SOF handler in FSM mode has two functions ++ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's ++ * nothing to do ++ * 2. Advance certain FSM states that require either a microframe delay, or a microframe ++ * of holdoff. ++ * ++ * The second part is architecture-specific to mach-bcm2835 - ++ * a sane interrupt controller would have a mask register for ARM interrupt sources ++ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt ++ * number (USB) can be enabled. This means that certain parts of the USB specification ++ * that require "wait a little while, then issue another packet" cannot be fulfilled with ++ * the timing granularity required to achieve optimal throughout. The workaround is to use ++ * the SOF "timer" (125uS) to perform this task. ++ */ ++static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels) ++{ ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) }; ++ int n; ++ int kick_irq = 0; ++ ++ if ((hfnum.b.frnum & 0x7) == 1) { ++ /* We cannot issue csplits for transactions in the last frame past (n+1).1 ++ * Check to see if there are any transactions that are stale. ++ * Boot them out. ++ */ ++ for (n = 0; n < num_channels; n++) { ++ switch (state->channel[n].fsm) { ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_CSPLIT_LAST: ++ /* Check if we are no longer in the same full-speed frame. */ ++ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) < ++ (hfnum.b.frnum & ~0x7)) ++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ ++ for (n = 0; n < num_channels; n++) { ++ switch (state->channel[n].fsm) { ++ ++ case FIQ_NP_SSPLIT_RETRY: ++ case FIQ_NP_IN_CSPLIT_RETRY: ++ case FIQ_NP_OUT_CSPLIT_RETRY: ++ fiq_fsm_restart_channel(state, n, 0); ++ break; ++ ++ case FIQ_HS_ISOC_SLEEPING: ++ state->channel[n].fsm = FIQ_HS_ISOC_TURBO; ++ fiq_fsm_restart_channel(state, n, 0); ++ break; ++ ++ case FIQ_PER_SSPLIT_QUEUED: ++ if ((hfnum.b.frnum & 0x7) == 5) ++ break; ++ if(!fiq_fsm_tt_in_use(state, num_channels, n)) { ++ if (!fiq_fsm_too_late(state, n)) { ++ fiq_print(FIQDBG_INT, st, "SOF GO %01d", n); ++ fiq_fsm_restart_channel(state, n, 0); ++ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ /* Transaction cannot be started without risking a device babble error */ ++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ state->haintmsk_saved.b2.chint &= ~(1 << n); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); ++ kick_irq |= 1; ++ } ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_PENDING: ++ /* Ordinarily, this should be poked after the SSPLIT ++ * complete interrupt for a competing transfer on the same ++ * TT. Doesn't happen for aborted transactions though. ++ */ ++ if ((hfnum.b.frnum & 0x7) >= 5) ++ break; ++ if (!fiq_fsm_tt_in_use(state, num_channels, n)) { ++ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt ++ * that caused this. ++ */ ++ fiq_fsm_restart_channel(state, n, 0); ++ fiq_print(FIQDBG_INT, state, "SOF ISOC"); ++ if (state->channel[n].nrpackets == 1) { ++ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_WAIT: ++ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt ++ * occurred when the bus transaction occurred. The SOF interrupt reversal bug ++ * will utterly bugger this up though. ++ */ ++ if (hfnum.b.frnum != state->channel[n].expected_uframe) { ++ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n); ++ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL; ++ fiq_fsm_restart_channel(state, n, 0); ++ fiq_fsm_start_next_periodic(state, num_channels); ++ ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ /* Ugly: we have to force a HCD interrupt. ++ * Poke the mask for the channel in question. ++ * We will take a fake SOF because of this, but ++ * that's OK. ++ */ ++ state->haintmsk_saved.b2.chint &= ~(1 << n); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); ++ kick_irq |= 1; ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ if (state->kick_np_queues || ++ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum)) ++ kick_irq |= 1; ++ ++ return !kick_irq; ++} ++ ++ ++/** ++ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler ++ * @state: Pointer to the FIQ state struct ++ * @num_channels: Number of channels as per hardware config ++ * @n: channel for which HAINT(i) was raised ++ * ++ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well. ++ */ ++static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n) ++{ ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hcint_data_t hcint_probe; ++ hcchar_data_t hcchar; ++ int handled = 0; ++ int restart = 0; ++ int last_csplit = 0; ++ int start_next_periodic = 0; ++ struct fiq_channel_state *st = &state->channel[n]; ++ hfnum_data_t hfnum; ++ ++ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT); ++ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK); ++ hcint_probe.d32 = hcint.d32 & hcintmsk.d32; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) { ++ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm); ++ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32); ++ } ++ ++ switch (st->fsm) { ++ ++ case FIQ_PASSTHROUGH: ++ case FIQ_DEQUEUE_ISSUED: ++ /* doesn't belong to us, kick it upstairs */ ++ break; ++ ++ case FIQ_PASSTHROUGH_ERRORSTATE: ++ /* We are here to emulate the error recovery mechanism of the dwc HCD. ++ * Several interrupts are unmasked if a previous transaction failed - it's ++ * death for the FIQ to attempt to handle them as the channel isn't halted. ++ * Emulate what the HCD does in this situation: mask and continue. ++ * The FSM has no other state setup so this has to be handled out-of-band. ++ */ ++ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n); ++ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) { ++ fiq_print(FIQDBG_ERR, state, "RESET %02d", n); ++ st->nr_errors = 0; ++ hcintmsk.b.nak = 0; ++ hcintmsk.b.ack = 0; ++ hcintmsk.b.datatglerr = 0; ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32); ++ return 1; ++ } ++ if (hcint_probe.b.chhltd) { ++ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n); ++ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32); ++ return 0; ++ } ++ break; ++ ++ /* Non-periodic state groups */ ++ case FIQ_NP_SSPLIT_STARTED: ++ case FIQ_NP_SSPLIT_RETRY: ++ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */ ++ if (hcint.b.ack) { ++ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction ++ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood. ++ */ ++ if(st->hcchar_copy.b.epdir == 1) ++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; ++ else ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ st->nr_errors = 0; ++ handled = 1; ++ fiq_fsm_setup_csplit(state, n); ++ } else if (hcint.b.nak) { ++ // No buffer space in TT. Retry on a uframe boundary. ++ st->fsm = FIQ_NP_SSPLIT_RETRY; ++ handled = 1; ++ } else if (hcint.b.xacterr) { ++ // The only other one we care about is xacterr. This implies HS bus error - retry. ++ st->nr_errors++; ++ st->fsm = FIQ_NP_SSPLIT_RETRY; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else { ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ handled = 0; ++ restart = 0; ++ } ++ break; ++ ++ case FIQ_NP_IN_CSPLIT_RETRY: ++ /* Received a CSPLIT done interrupt. ++ * Expected Data/NAK/STALL/NYET for IN. ++ */ ++ if (hcint.b.xfercomp) { ++ /* For IN, data is present. */ ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nak) { ++ /* no endpoint data. Punt it upstairs */ ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nyet) { ++ /* CSPLIT NYET - retry on a uframe boundary. */ ++ handled = 1; ++ st->nr_errors = 0; ++ } else if (hcint.b.datatglerr) { ++ /* data toggle errors do not set the xfercomp bit. */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else if (hcint.b.xacterr) { ++ /* HS error. Retry immediate */ ++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else if (hcint.b.stall) { ++ /* A STALL implies either a LS bus error or a genuine STALL. */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else { ++ /* Hardware bug. It's possible in some cases to ++ * get a channel halt with nothing else set when ++ * the response was a NYET. Treat as local 3-strikes retry. ++ */ ++ hcint_data_t hcint_test = hcint; ++ hcint_test.b.chhltd = 0; ++ if (!hcint_test.d32) { ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ } ++ } else { ++ /* Bail out if something unexpected happened */ ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } ++ } ++ break; ++ ++ case FIQ_NP_OUT_CSPLIT_RETRY: ++ /* Received a CSPLIT done interrupt. ++ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/ ++ if (hcint.b.xfercomp) { ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nak) { ++ // The HCD will implement the holdoff on frame boundaries. ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nyet) { ++ // Hub still processing. ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ handled = 1; ++ st->nr_errors = 0; ++ //restart = 1; ++ } else if (hcint.b.xacterr) { ++ /* HS error. retry immediate */ ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else if (hcint.b.stall) { ++ /* LS bus error or genuine stall */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else { ++ /* ++ * Hardware bug. It's possible in some cases to get a ++ * channel halt with nothing else set when the response was a NYET. ++ * Treat as local 3-strikes retry. ++ */ ++ hcint_data_t hcint_test = hcint; ++ hcint_test.b.chhltd = 0; ++ if (!hcint_test.d32) { ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ } ++ } else { ++ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it. ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } ++ } ++ break; ++ ++ /* Periodic split states (except isoc out) */ ++ case FIQ_PER_SSPLIT_STARTED: ++ /* Expect an ACK or failure for SSPLIT */ ++ if (hcint.b.ack) { ++ /* ++ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs. ++ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1 ++ * point for microframe n-3, the packet will not appear on the bus until microframe n. ++ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus ++ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1 ++ * coincident with SOF for n+1. ++ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place. ++ * These appear to be caused by timing/clock crossing bugs within the core itself. ++ * State machine workaround. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ fiq_fsm_setup_csplit(state, n); ++ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct ++ * time. If not, then we're in the next SOF. ++ */ ++ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) { ++ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n); ++ st->expected_uframe = hfnum.b.frnum; ++ st->fsm = FIQ_PER_CSPLIT_WAIT; ++ } else { ++ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n); ++ /* For isochronous IN endpoints, ++ * we need to hold off if we are expecting a lot of data */ ++ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) { ++ start_next_periodic = 1; ++ } ++ /* Danger will robinson: we are in a broken state. If our first interrupt after ++ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable ++ * lag. Unmask the NYET interrupt. ++ */ ++ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; ++ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1; ++ restart = 1; ++ } ++ handled = 1; ++ } else if (hcint.b.xacterr) { ++ /* 3-strikes retry is enabled, we have hit our max nr_errors */ ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ start_next_periodic = 1; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ start_next_periodic = 1; ++ } ++ /* We can now queue the next isochronous OUT transaction, if one is pending. */ ++ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) { ++ fiq_print(FIQDBG_INT, state, "NEXTISO "); ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_NYET1: ++ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET, ++ * we are too late and the TT has dropped its CSPLIT fifo. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ start_next_periodic = 1; ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ st->fsm = FIQ_PER_CSPLIT_POLL; ++ st->nr_errors = 0; ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ handled = 1; ++ restart = 1; ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ /* Doh. Data lost. */ ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ } else if (hcint.b.xacterr || hcint.b.stall) { ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_BROKEN_NYET1: ++ /* ++ * we got here because our host channel is in the delayed-interrupt ++ * state and we cannot take a NYET interrupt any later than when it ++ * occurred. Disable then re-enable the channel if this happens to force ++ * CSPLITs to occur at the right time. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n); ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ start_next_periodic = 1; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ st->fsm = FIQ_PER_CSPLIT_POLL; ++ handled = 1; ++ restart = 1; ++ start_next_periodic = 1; ++ /* Reload HCTSIZ for the next transfer */ ++ fiq_fsm_reload_hctsiz(state, n); ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ start_next_periodic = 1; ++ } else if (hcint.b.xacterr) { ++ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/ ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ fiq_print(FIQDBG_INT, state, "TOGGLES"); ++ BUG(); ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_POLL: ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ start_next_periodic = 1; ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ handled = 1; ++ restart = 1; ++ /* Reload HCTSIZ for the next transfer */ ++ fiq_fsm_reload_hctsiz(state, n); ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ /* Are we a NYET after the first data packet? */ ++ if (st->nrpackets == 0) { ++ st->fsm = FIQ_PER_CSPLIT_NYET1; ++ handled = 1; ++ restart = 1; ++ } else { ++ /* We got a NYET when polling CSPLITs. Can happen ++ * if our heuristic fails, or if someone disables us ++ * for any significant length of time. ++ */ ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } ++ } else if (hcint.b.xacterr || hcint.b.stall) { ++ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/ ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else if (hcint.b.datatglerr) { ++ fiq_print(FIQDBG_INT, state, "TOGGLES"); ++ BUG(); ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_HS_ISOC_TURBO: ++ if (fiq_fsm_update_hs_isoc(state, n, hcint)) { ++ /* more transactions to come */ ++ handled = 1; ++ restart = 1; ++ fiq_print(FIQDBG_INT, state, "HSISO M "); ++ } else { ++ st->fsm = FIQ_HS_ISOC_DONE; ++ fiq_print(FIQDBG_INT, state, "HSISO F "); ++ } ++ break; ++ ++ case FIQ_HS_ISOC_ABORTED: ++ /* This abort is called by the driver rewriting the state mid-transaction ++ * which allows the dequeue mechanism to work more effectively. ++ */ ++ break; ++ ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ if (hcint.b.ack) { ++ if(fiq_iso_out_advance(state, num_channels, n)) { ++ /* last OUT transfer */ ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ /* ++ * Assuming the periodic FIFO in the dwc core ++ * actually does its job properly, we can queue ++ * the next ssplit now and in theory, the wire ++ * transactions will be in-order. ++ */ ++ // No it doesn't. It appears to process requests in host channel order. ++ //start_next_periodic = 1; ++ } ++ handled = 1; ++ restart = 1; ++ } else { ++ /* ++ * Isochronous transactions carry on regardless. Log the error ++ * and continue. ++ */ ++ //explode += 1; ++ st->nr_errors++; ++ if(fiq_iso_out_advance(state, num_channels, n)) { ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ //start_next_periodic = 1; ++ } ++ handled = 1; ++ restart = 1; ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_LAST: ++ if (hcint.b.ack) { ++ /* All done here */ ++ st->fsm = FIQ_PER_ISO_OUT_DONE; ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_DONE; ++ st->nr_errors++; ++ } ++ start_next_periodic = 1; ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ /* SOF kicked us because we overran. */ ++ start_next_periodic = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (handled) { ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32); ++ } else { ++ /* Copy the regs into the state so the IRQ knows what to do */ ++ st->hcint_copy.d32 = hcint.d32; ++ } ++ ++ if (restart) { ++ /* Restart always implies handled. */ ++ if (restart == 2) { ++ /* For complete-split INs, the show must go on. ++ * Force a channel restart */ ++ fiq_fsm_restart_channel(state, n, 1); ++ } else { ++ fiq_fsm_restart_channel(state, n, 0); ++ } ++ } ++ if (start_next_periodic) { ++ fiq_fsm_start_next_periodic(state, num_channels); ++ } ++ if (st->fsm != FIQ_PASSTHROUGH) ++ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm); ++ ++ return handled; ++} ++ ++ ++/** ++ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ ++ * @state: pointer to state struct passed from the banked FIQ mode registers. ++ * @num_channels: set according to the DWC hardware configuration ++ * @dma: pointer to DMA bounce buffers for split transaction slots ++ * ++ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode ++ * inside an EHCI or similar host controller regarding split transactions. The DWC core ++ * interrupts each and every time a split transaction packet is received or sent successfully. ++ * This results in either an interrupt storm when everything is working "properly", or ++ * the interrupt latency of the system in general breaks time-sensitive periodic split ++ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ ++ * solves these problems. ++ * ++ * Return: void ++ */ ++void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels) ++{ ++ gintsts_data_t gintsts, gintsts_handled; ++ gintmsk_data_t gintmsk; ++ //hfnum_data_t hfnum; ++ haint_data_t haint, haint_handled; ++ haintmsk_data_t haintmsk; ++ int kick_irq = 0; ++ ++ gintsts_handled.d32 = 0; ++ haint_handled.d32 = 0; ++ ++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); ++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); ++ gintsts.d32 &= gintmsk.d32; ++ ++ if (gintsts.b.sofintr) { ++ /* For FSM mode, SOF is required to keep the state machine advance for ++ * certain stages of the periodic pipeline. It's death to mask this ++ * interrupt in that case. ++ */ ++ ++ if (!fiq_fsm_do_sof(state, num_channels)) { ++ /* Kick IRQ once. Queue advancement means that all pending transactions ++ * will get serviced when the IRQ finally executes. ++ */ ++ if (state->gintmsk_saved.b.sofintr == 1) ++ kick_irq |= 1; ++ state->gintmsk_saved.b.sofintr = 0; ++ } ++ gintsts_handled.b.sofintr = 1; ++ } ++ ++ if (gintsts.b.hcintr) { ++ int i; ++ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT); ++ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK); ++ haint.d32 &= haintmsk.d32; ++ haint_handled.d32 = 0; ++ for (i=0; ihaintmsk_saved.b2.chint &= ~(1 << i); ++ } else { ++ /* do_hcintr cleaned up after itself, but clear haint */ ++ haint_handled.b2.chint |= (1 << i); ++ } ++ } ++ } ++ ++ if (haint_handled.b2.chint) { ++ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32); ++ } ++ ++ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) { ++ /* ++ * This is necessary to avoid multiple retriggers of the MPHI in the case ++ * where interrupts are held off and HCINTs start to pile up. ++ * Only wake up the IRQ if a new interrupt came in, was not handled and was ++ * masked. ++ */ ++ haintmsk.d32 &= state->haintmsk_saved.d32; ++ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32); ++ kick_irq |= 1; ++ } ++ /* Top-Level interrupt - always handled because it's level-sensitive */ ++ gintsts_handled.b.hcintr = 1; ++ } ++ ++ ++ /* Clear the bits in the saved register that were not handled but were triggered. */ ++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); ++ ++ /* FIQ didn't handle something - mask has changed - write new mask */ ++ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) { ++ gintmsk.d32 &= state->gintmsk_saved.d32; ++ gintmsk.b.sofintr = 1; ++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); ++// fiq_print(FIQDBG_INT, state, "KICKGINT"); ++// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32); ++// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32); ++ kick_irq |= 1; ++ } ++ ++ if (gintsts_handled.d32) { ++ /* Only applies to edge-sensitive bits in GINTSTS */ ++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); ++ } ++ ++ /* We got an interrupt, didn't handle it. */ ++ if (kick_irq) { ++ state->mphi_int_count++; ++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); ++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); ++ ++ } ++ state->fiq_done++; ++ mb(); ++} ++ ++ ++/** ++ * dwc_otg_fiq_nop() - FIQ "lite" ++ * @state: pointer to state struct passed from the banked FIQ mode registers. ++ * ++ * The "nop" handler does not intervene on any interrupts other than SOF. ++ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals ++ * with non-periodic/periodic queues) needs to be kicked. ++ * ++ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second. ++ * ++ * Return: void ++ */ ++void notrace dwc_otg_fiq_nop(struct fiq_state *state) ++{ ++ gintsts_data_t gintsts, gintsts_handled; ++ gintmsk_data_t gintmsk; ++ hfnum_data_t hfnum; ++ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); ++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); ++ gintsts.d32 &= gintmsk.d32; ++ gintsts_handled.d32 = 0; ++ ++ if (gintsts.b.sofintr) { ++ if (!state->kick_np_queues && ++ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) { ++ /* SOF handled, no work to do, just ACK interrupt */ ++ gintsts_handled.b.sofintr = 1; ++ } else { ++ /* Kick IRQ */ ++ state->gintmsk_saved.b.sofintr = 0; ++ } ++ } ++ ++ /* Reset handled interrupts */ ++ if(gintsts_handled.d32) { ++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); ++ } ++ ++ /* Clear the bits in the saved register that were not handled but were triggered. */ ++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); ++ ++ /* We got an interrupt, didn't handle it and want to mask it */ ++ if (~(state->gintmsk_saved.d32)) { ++ state->mphi_int_count++; ++ gintmsk.d32 &= state->gintmsk_saved.d32; ++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); ++ /* Force a clear before another dummy send */ ++ FIQ_WRITE(state->mphi_regs.intstat, (1<<29)); ++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); ++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); ++ ++ } ++ state->fiq_done++; ++ mb(); ++} +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h +new file mode 100644 +index 0000000..7572958 +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h +@@ -0,0 +1,353 @@ ++/* ++ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This FIQ implements functionality that performs split transactions on ++ * the dwc_otg hardware without any outside intervention. A split transaction ++ * is "queued" by nominating a specific host channel to perform the entirety ++ * of a split transaction. This FIQ will then perform the microframe-precise ++ * scheduling required in each phase of the transaction until completion. ++ * ++ * The FIQ functionality has been surgically implanted into the Synopsys ++ * vendor-provided driver. ++ * ++ */ ++ ++#ifndef DWC_OTG_FIQ_FSM_H_ ++#define DWC_OTG_FIQ_FSM_H_ ++ ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_hcd.h" ++#include ++#include ++#include ++#include ++ ++#if 0 ++#define FLAME_ON(x) \ ++do { \ ++ int gpioreg; \ ++ \ ++ gpioreg = readl(__io_address(0x20200000+0x8)); \ ++ gpioreg &= ~(7 << (x-20)*3); \ ++ gpioreg |= 0x1 << (x-20)*3; \ ++ writel(gpioreg, __io_address(0x20200000+0x8)); \ ++ \ ++ writel(1< 1, SOF wakes up the isochronous FSM */ ++ FIQ_HS_ISOC_SLEEPING = 24, ++ FIQ_HS_ISOC_DONE = 25, ++ FIQ_HS_ISOC_ABORTED = 26, ++ FIQ_DEQUEUE_ISSUED = 30, ++ FIQ_TEST = 32, ++}; ++ ++struct fiq_stack { ++ int magic1; ++ uint8_t stack[2048]; ++ int magic2; ++}; ++ ++ ++/** ++ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel) ++ * @index: Number of slots reported used for IN transactions / number of slots ++ * transmitted for an OUT transaction ++ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused) ++ * ++ * Split transaction transfers can have variable length depending on other bus ++ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore ++ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers ++ * can happen per-frame. ++ */ ++struct fiq_dma_info { ++ u8 index; ++ u8 slot_len[6]; ++}; ++ ++struct __attribute__((packed)) fiq_split_dma_slot { ++ u8 buf[188]; ++}; ++ ++struct fiq_dma_channel { ++ struct __attribute__((packed)) fiq_split_dma_slot index[6]; ++}; ++ ++struct fiq_dma_blob { ++ struct __attribute__((packed)) fiq_dma_channel channel[0]; ++}; ++ ++/** ++ * struct fiq_hs_isoc_info - USB2.0 isochronous data ++ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs. ++ * @nrframes: Total length of iso_frame_desc array ++ * @index: Current index (FIQ-maintained) ++ * ++ */ ++struct fiq_hs_isoc_info { ++ struct dwc_otg_hcd_iso_packet_desc *iso_desc; ++ unsigned int nrframes; ++ unsigned int index; ++}; ++ ++/** ++ * struct fiq_channel_state - FIQ state machine storage ++ * @fsm: Current state of the channel as understood by the FIQ ++ * @nr_errors: Number of transaction errors on this split-transaction ++ * @hub_addr: SSPLIT/CSPLIT destination hub ++ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub ++ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For ++ * split-IN, number of CSPLIT data packets that were received. ++ * @hcchar_copy: ++ * @hcsplt_copy: ++ * @hcintmsk_copy: ++ * @hctsiz_copy: Copies of the host channel registers. ++ * For use as scratch, or for returning state. ++ * ++ * The fiq_channel_state is state storage between interrupts for a host channel. The ++ * FSM state is stored here. Members of this structure must only be set up by the ++ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ ++ * has updated the state to either a COMPLETE state group or ABORT state group. ++ */ ++ ++struct fiq_channel_state { ++ enum fiq_fsm_state fsm; ++ unsigned int nr_errors; ++ unsigned int hub_addr; ++ unsigned int port_addr; ++ /* Hardware bug workaround: sometimes channel halt interrupts are ++ * delayed until the next SOF. Keep track of when we expected to get interrupted. */ ++ unsigned int expected_uframe; ++ /* in/out for communicating number of dma buffers used, or number of ISOC to do */ ++ unsigned int nrpackets; ++ struct fiq_dma_info dma_info; ++ struct fiq_hs_isoc_info hs_isoc_info; ++ /* Copies of HC registers - in/out communication from/to IRQ handler ++ * and for ease of channel setup. A bit of mungeing is performed - for ++ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint. ++ */ ++ hcchar_data_t hcchar_copy; ++ hcsplt_data_t hcsplt_copy; ++ hcint_data_t hcint_copy; ++ hcintmsk_data_t hcintmsk_copy; ++ hctsiz_data_t hctsiz_copy; ++ hcdma_data_t hcdma_copy; ++}; ++ ++/** ++ * struct fiq_state - top-level FIQ state machine storage ++ * @mphi_regs: virtual address of the MPHI peripheral register file ++ * @dwc_regs_base: virtual address of the base of the DWC core register file ++ * @dma_base: physical address for the base of the DMA bounce buffers ++ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral ++ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled. ++ * Used for determining which interrupts fired to set off the IRQ handler. ++ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally. ++ * @np_count: Non-periodic transactions in the active queue ++ * @np_sent: Count of non-periodic transactions that have completed ++ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism, ++ * this is the next frame on which a SOF interrupt is required. Used to hold off ++ * passing SOF through to the driver until necessary. ++ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host ++ * channels configured into the core logic. ++ * ++ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub. ++ * It contains top-level state information. ++ */ ++struct fiq_state { ++ mphi_regs_t mphi_regs; ++ void *dwc_regs_base; ++ dma_addr_t dma_base; ++ struct fiq_dma_blob *fiq_dmab; ++ void *dummy_send; ++ gintmsk_data_t gintmsk_saved; ++ haintmsk_data_t haintmsk_saved; ++ int mphi_int_count; ++ unsigned int fiq_done; ++ unsigned int kick_np_queues; ++ unsigned int next_sched_frame; ++#ifdef FIQ_DEBUG ++ char * buffer; ++ unsigned int bufsiz; ++#endif ++ struct fiq_channel_state channel[0]; ++}; ++ ++extern int fiq_fsm_too_late(struct fiq_state *st, int n); ++ ++extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n); ++ ++extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels); ++ ++extern void dwc_otg_fiq_nop(struct fiq_state *state); ++ ++#endif /* DWC_OTG_FIQ_FSM_H_ */ +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S +new file mode 100644 +index 0000000..8cfe364 +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S +@@ -0,0 +1,81 @@ ++/* ++ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++#include ++#include ++ ++ ++.text ++ ++.global _dwc_otg_fiq_stub_end; ++ ++/** ++ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow ++ * a C-style function call with arguments from the FIQ banked registers. ++ * r0 = &hcd->fiq_state ++ * r1 = &hcd->num_channels ++ * r2 = &hcd->dma_buffers ++ * Tramples: r0, r1, r2, r4, fp, ip ++ */ ++ ++ENTRY(_dwc_otg_fiq_stub) ++ /* Stash unbanked regs - SP will have been set up for us */ ++ mov ip, sp; ++ stmdb sp!, {r0-r12, lr}; ++#ifdef FIQ_DEBUG ++ // Cycle profiling - read cycle counter at start ++ mrc p15, 0, r5, c15, c12, 1; ++#endif ++ /* r11 = fp, don't trample it */ ++ mov r4, fp; ++ /* set EABI frame size */ ++ sub fp, ip, #512; ++ ++ /* for fiq NOP mode - just need state */ ++ mov r0, r8; ++ /* r9 = num_channels */ ++ mov r1, r9; ++ /* r10 = struct *dma_bufs */ ++// mov r2, r10; ++ ++ /* r4 = &fiq_c_function */ ++ blx r4; ++#ifdef FIQ_DEBUG ++ mrc p15, 0, r4, c15, c12, 1; ++ subs r5, r5, r4; ++ // r5 is now the cycle count time for executing the FIQ. Store it somewhere? ++#endif ++ ldmia sp!, {r0-r12, lr}; ++ subs pc, lr, #4; ++_dwc_otg_fiq_stub_end: ++END(_dwc_otg_fiq_stub) ++ +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +index 22300f0..e6b4a1e 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +@@ -45,9 +45,10 @@ + + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" +-#include "dwc_otg_mphi_fix.h" ++#include "dwc_otg_fiq_fsm.h" + +-extern bool microframe_schedule, nak_holdoff_enable; ++extern bool microframe_schedule; ++extern uint16_t fiq_fsm_mask, nak_holdoff; + + //#define DEBUG_HOST_CHANNELS + #ifdef DEBUG_HOST_CHANNELS +@@ -57,12 +58,6 @@ static int last_sel_trans_num_avail_hc_at_start = 0; + static int last_sel_trans_num_avail_hc_at_end = 0; + #endif /* DEBUG_HOST_CHANNELS */ + +-extern int g_next_sched_frame, g_np_count, g_np_sent; +- +-extern haint_data_t haint_saved; +-extern hcintmsk_data_t hcintmsk_saved[MAX_EPS_CHANNELS]; +-extern hcint_data_t hcint_saved[MAX_EPS_CHANNELS]; +-extern gintsts_data_t ginsts_saved; + + dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) + { +@@ -295,7 +290,7 @@ static int32_t dwc_otg_hcd_disconnect_cb(void *p) + */ + dwc_otg_hcd->flags.b.port_connect_status_change = 1; + dwc_otg_hcd->flags.b.port_connect_status = 0; +- if(fiq_fix_enable) ++ if(fiq_enable) + local_fiq_disable(); + /* + * Shutdown any transfers in process by clearing the Tx FIFO Empty +@@ -392,20 +387,15 @@ static int32_t dwc_otg_hcd_disconnect_cb(void *p) + channel->qh = NULL; + } + } +- if(fiq_split_enable) { ++ if(fiq_fsm_enable) { + for(i=0; i < 128; i++) { + dwc_otg_hcd->hub_port[i] = 0; + } +- haint_saved.d32 = 0; +- for(i=0; i < MAX_EPS_CHANNELS; i++) { +- hcint_saved[i].d32 = 0; +- hcintmsk_saved[i].d32 = 0; +- } + } + + } + +- if(fiq_fix_enable) ++ if(fiq_enable) + local_fiq_enable(); + + if (dwc_otg_hcd->fops->disconnect) { +@@ -542,7 +532,7 @@ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, + } + #endif + intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk); +- if(!intr_mask.b.sofintr) needs_scheduling = 1; ++ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1; + if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) + /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */ + needs_scheduling = 0; +@@ -613,6 +603,7 @@ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, + if (urb_qtd->in_process && qh->channel) { + /* The QTD is in process (it has been assigned to a channel). */ + if (hcd->flags.b.port_connect_status) { ++ int n = qh->channel->hc_num; + /* + * If still connected (i.e. in host mode), halt the + * channel so it can be used for other transfers. If +@@ -620,10 +611,14 @@ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, + * written to halt the channel since the core is in + * device mode. + */ ++ /* In FIQ FSM mode, we need to shut down carefully. ++ * The FIQ may attempt to restart a disabled channel */ ++ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) { ++ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED; ++ } + dwc_otg_hc_halt(hcd->core_if, qh->channel, + DWC_OTG_HC_XFER_URB_DEQUEUE); + +- dwc_otg_hcd_release_port(hcd, qh); + } + } + +@@ -759,7 +754,6 @@ static void completion_tasklet_func(void *ptr) + + usb_hcd_giveback_urb(hcd->priv, urb, urb->status); + +- fiq_print(FIQDBG_PORTHUB, "COMPLETE"); + + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); + } +@@ -854,6 +848,34 @@ void dwc_otg_hcd_power_up(void *ptr) + cil_hcd_start(core_if); + } + ++void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num) ++{ ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ struct fiq_dma_blob *blob = hcd->fiq_dmab; ++ int i; ++ ++ st->fsm = FIQ_PASSTHROUGH; ++ st->hcchar_copy.d32 = 0; ++ st->hcsplt_copy.d32 = 0; ++ st->hcint_copy.d32 = 0; ++ st->hcintmsk_copy.d32 = 0; ++ st->hctsiz_copy.d32 = 0; ++ st->hcdma_copy.d32 = 0; ++ st->nr_errors = 0; ++ st->hub_addr = 0; ++ st->port_addr = 0; ++ st->expected_uframe = 0; ++ st->nrpackets = 0; ++ st->dma_info.index = 0; ++ for (i = 0; i < 6; i++) ++ st->dma_info.slot_len[i] = 255; ++ st->hs_isoc_info.index = 0; ++ st->hs_isoc_info.iso_desc = NULL; ++ st->hs_isoc_info.nrframes = 0; ++ ++ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128); ++} ++ + /** + * Frees secondary storage associated with the dwc_otg_hcd structure contained + * in the struct usb_hcd field. +@@ -907,6 +929,7 @@ static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd) + DWC_TIMER_FREE(dwc_otg_hcd->conn_timer); + DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet); + DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet); ++ DWC_FREE(dwc_otg_hcd->fiq_state); + + #ifdef DWC_DEV_SRPCAP + if (dwc_otg_hcd->core_if->power_down == 2 && +@@ -979,6 +1002,59 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) + channel); + } + ++ if (fiq_enable) { ++ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)); ++ if (!hcd->fiq_state) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels))); ++ ++ for (i = 0; i < num_channels; i++) { ++ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH; ++ } ++ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16); ++ ++ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack)); ++ if (!hcd->fiq_stack) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ hcd->fiq_stack->magic1 = 0xDEADBEEF; ++ hcd->fiq_stack->magic2 = 0xD00DFEED; ++ hcd->fiq_state->gintmsk_saved.d32 = ~0; ++ hcd->fiq_state->haintmsk_saved.b2.chint = ~0; ++ ++ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools ++ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels) ++ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some ++ * moderately readable array casts. ++ */ ++ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base); ++ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d", ++ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base, ++ sizeof(struct fiq_dma_channel) * num_channels); ++ ++ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024); ++ ++ /* pointer for debug in fiq_print */ ++ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab; ++ if (fiq_fsm_enable) { ++ int i; ++ for (i=0; i < hcd->core_if->core_params->host_channels; i++) { ++ dwc_otg_cleanup_fiq_channel(hcd, i); ++ } ++ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s", ++ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "", ++ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "", ++ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : ""); ++ } ++ } ++ + /* Initialize the Connection timeout timer. */ + hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", + dwc_otg_hcd_connect_timeout, 0); +@@ -1176,7 +1252,8 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + hc->do_split = 1; + hc->xact_pos = qtd->isoc_split_pos; + /* We don't need to do complete splits anymore */ +- if(fiq_split_enable) ++// if(fiq_fsm_enable) ++ if (0) + hc->complete_split = qtd->complete_split = 0; + else + hc->complete_split = qtd->complete_split; +@@ -1327,62 +1404,487 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + hc->qh = qh; + } + +-/* +-** Check the transaction to see if the port / hub has already been assigned for +-** a split transaction +-** +-** Return 0 - Port is already in use +-*/ +-int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh) ++ ++/** ++ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ ++ * @qh: pointer to the endpoint's queue head ++ * ++ * Transaction start/end control flow is grafted onto the existing dwc_otg ++ * mechanisms, to avoid spaghettifying the functions more than they already are. ++ * This function's eligibility check is altered by debug parameter. ++ * ++ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction. ++ */ ++ ++int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh) + { +- uint32_t hub_addr, port_addr; ++ if (qh->do_split) { ++ switch (qh->ep_type) { ++ case UE_CONTROL: ++ case UE_BULK: ++ if (fiq_fsm_mask & (1 << 0)) ++ return 1; ++ break; ++ case UE_INTERRUPT: ++ case UE_ISOCHRONOUS: ++ if (fiq_fsm_mask & (1 << 1)) ++ return 1; ++ break; ++ default: ++ break; ++ } ++ } else if (qh->ep_type == UE_ISOCHRONOUS) { ++ if (fiq_fsm_mask & (1 << 2)) { ++ /* HS ISOCH support. We test for compatibility: ++ * - DWORD aligned buffers ++ * - Must be at least 2 transfers (otherwise pointless to use the FIQ) ++ * If yes, then the fsm enqueue function will handle the state machine setup. ++ */ ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs; ++ int nr_iso_frames = urb->packet_count; ++ int i; ++ uint32_t ptr; ++ ++ if (nr_iso_frames < 2) ++ return 0; ++ for (i = 0; i < nr_iso_frames; i++) { ++ ptr = urb->dma + iso_descs[i]->offset; ++ if (ptr & 0x3) { ++ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset." ++ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n", ++ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num); ++ return 0; ++ } ++ } ++ return 1; ++ } ++ } ++ return 0; ++} + +- if(!fiq_split_enable) +- return 0; ++/** ++ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers ++ * @hcd: Pointer to the dwc_otg_hcd struct ++ * @qh: Pointer to the endpoint's queue head ++ * ++ * Periodic split transactions are transmitted modulo 188 bytes. ++ * This necessitates slicing data up into buckets for isochronous out ++ * and fixing up the DMA address for all IN transfers. ++ * ++ * Returns 1 if the DMA bounce buffers have been used, 0 if the default ++ * HC buffer has been used. ++ */ ++int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh) ++ { ++ int frame_length, i = 0; ++ uint8_t *ptr = NULL; ++ dwc_hc_t *hc = qh->channel; ++ struct fiq_dma_blob *blob; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ for (i = 0; i < 6; i++) { ++ st->dma_info.slot_len[i] = 255; ++ } ++ st->dma_info.index = 0; ++ i = 0; ++ if (hc->ep_is_in) { ++ /* ++ * Set dma_regs to bounce buffer. FIQ will update the ++ * state depending on transaction progress. ++ */ ++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; ++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; ++ /* Calculate the max number of CSPLITS such that the FIQ can time out ++ * a transaction if it fails. ++ */ ++ frame_length = st->hcchar_copy.b.mps; ++ do { ++ i++; ++ frame_length -= 188; ++ } while (frame_length >= 0); ++ st->nrpackets = i; ++ return 1; ++ } else { ++ if (qh->ep_type == UE_ISOCHRONOUS) { + +- hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); + +- if(hcd->hub_port[hub_addr] & (1 << port_addr)) +- { +- fiq_print(FIQDBG_PORTHUB, "H%dP%d:S%02d", hub_addr, port_addr, qh->skip_count); ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ frame_length = frame_desc->length; + +- qh->skip_count++; ++ /* Virtual address for bounce buffers */ ++ blob = hcd->fiq_dmab; + +- if(qh->skip_count > 40000) +- { +- printk_once(KERN_ERR "Error: Having to skip port allocation"); +- local_fiq_disable(); +- BUG(); ++ ptr = qtd->urb->buf + frame_desc->offset; ++ if (frame_length == 0) { ++ /* ++ * for isochronous transactions, we must still transmit a packet ++ * even if the length is zero. ++ */ ++ st->dma_info.slot_len[0] = 0; ++ st->nrpackets = 1; ++ } else { ++ do { ++ if (frame_length <= 188) { ++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length); ++ st->dma_info.slot_len[i] = frame_length; ++ ptr += frame_length; ++ } else { ++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188); ++ st->dma_info.slot_len[i] = 188; ++ ptr += 188; ++ } ++ i++; ++ frame_length -= 188; ++ } while (frame_length > 0); ++ st->nrpackets = i; ++ } ++ ptr = qtd->urb->buf + frame_desc->offset; ++ /* Point the HC at the DMA address of the bounce buffers */ ++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; ++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; ++ ++ /* fixup xfersize to the actual packet size */ ++ st->hctsiz_copy.b.pid = 0; ++ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0]; ++ return 1; ++ } else { ++ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */ + return 0; + } +- return 1; + } +- else +- { +- qh->skip_count = 0; +- hcd->hub_port[hub_addr] |= 1 << port_addr; +- fiq_print(FIQDBG_PORTHUB, "H%dP%d:A %d", hub_addr, port_addr, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->pipe_info.ep_num); +-#ifdef FIQ_DEBUG +- hcd->hub_port_alloc[hub_addr * 16 + port_addr] = dwc_otg_hcd_get_frame_number(hcd); +-#endif ++} ++ ++/* ++ * Pushing a periodic request into the queue near the EOF1 point ++ * in a microframe causes erroneous behaviour (frmovrun) interrupt. ++ * Usually, the request goes out on the bus causing a transfer but ++ * the core does not transfer the data to memory. ++ * This guard interval (in number of 60MHz clocks) is required which ++ * must cater for CPU latency between reading the value and enabling ++ * the channel. ++ */ ++#define PERIODIC_FRREM_BACKOFF 1000 ++ ++int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) ++{ ++ dwc_hc_t *hc = qh->channel; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ int frame; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; ++ int xfer_len, nrpackets; ++ hcdma_data_t hcdma; ++ hfnum_data_t hfnum; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) + return 0; ++ ++ st->nr_errors = 0; ++ ++ st->hcchar_copy.d32 = 0; ++ st->hcchar_copy.b.mps = hc->max_packet; ++ st->hcchar_copy.b.epdir = hc->ep_is_in; ++ st->hcchar_copy.b.devaddr = hc->dev_addr; ++ st->hcchar_copy.b.epnum = hc->ep_num; ++ st->hcchar_copy.b.eptype = hc->ep_type; ++ ++ st->hcintmsk_copy.b.chhltd = 1; ++ ++ frame = dwc_otg_hcd_get_frame_number(hcd); ++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; ++ ++ st->hcchar_copy.b.lspddev = 0; ++ /* Enable the channel later as a final register write. */ ++ ++ st->hcsplt_copy.d32 = 0; ++ ++ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs; ++ st->hs_isoc_info.nrframes = qtd->urb->packet_count; ++ /* grab the next DMA address offset from the array */ ++ st->hcdma_copy.d32 = qtd->urb->dma; ++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset; ++ ++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as ++ * the core needs to be told to send the correct number. Caution: for IN transfers, ++ * this is always set to the maximum size of the endpoint. */ ++ xfer_len = st->hs_isoc_info.iso_desc[0].length; ++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; ++ if (nrpackets == 0) ++ nrpackets = 1; ++ st->hcchar_copy.b.multicnt = nrpackets; ++ st->hctsiz_copy.b.pktcnt = nrpackets; ++ ++ /* Initial PID also needs to be set */ ++ if (st->hcchar_copy.b.epdir == 0) { ++ st->hctsiz_copy.b.xfersize = xfer_len; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_MDATA; ++ break; ++ } ++ ++ } else { ++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA1; ++ break; ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA2; ++ break; ++ } + } ++ ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); ++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ local_fiq_disable(); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); ++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { ++ /* Prevent queueing near EOF1. Bad things happen if a periodic ++ * split transaction is queued very close to EOF. ++ */ ++ st->fsm = FIQ_HS_ISOC_SLEEPING; ++ } else { ++ st->fsm = FIQ_HS_ISOC_TURBO; ++ st->hcchar_copy.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ } ++ mb(); ++ st->hcchar_copy.b.chen = 0; ++ local_fiq_enable(); ++ return 0; + } +-void dwc_otg_hcd_release_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh) ++ ++ ++/** ++ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state ++ * @hcd: Pointer to the dwc_otg_hcd struct ++ * @qh: Pointer to the endpoint's queue head ++ * ++ * This overrides the dwc_otg driver's normal method of queueing a transaction. ++ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup ++ * for the nominated host channel. ++ * ++ * For periodic transfers, it also peeks at the FIQ state to see if an immediate ++ * start is possible. If not, then the FIQ is left to start the transfer. ++ */ ++int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) + { +- uint32_t hub_addr, port_addr; ++ int start_immediate = 1, i; ++ hfnum_data_t hfnum; ++ dwc_hc_t *hc = qh->channel; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */ ++ int hub_addr, port_addr, frame, uframe; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; + +- if(!fiq_split_enable) +- return; ++ if (st->fsm != FIQ_PASSTHROUGH) ++ return 0; ++ st->nr_errors = 0; ++ ++ st->hcchar_copy.d32 = 0; ++ st->hcchar_copy.b.mps = hc->max_packet; ++ st->hcchar_copy.b.epdir = hc->ep_is_in; ++ st->hcchar_copy.b.devaddr = hc->dev_addr; ++ st->hcchar_copy.b.epnum = hc->ep_num; ++ st->hcchar_copy.b.eptype = hc->ep_type; ++ if (hc->ep_type & 0x1) { ++ if (hc->ep_is_in) ++ st->hcchar_copy.b.multicnt = 3; ++ else ++ /* Docs say set this to 1, but driver sets to 0! */ ++ st->hcchar_copy.b.multicnt = 0; ++ } else { ++ st->hcchar_copy.b.multicnt = 1; ++ st->hcchar_copy.b.oddfrm = 0; ++ } ++ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0; ++ /* Enable the channel later as a final register write. */ ++ ++ st->hcsplt_copy.d32 = 0; ++ if(qh->do_split) { ++ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); ++ st->hcsplt_copy.b.compsplt = 0; ++ st->hcsplt_copy.b.spltena = 1; ++ // XACTPOS is for isoc-out only but needs initialising anyway. ++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL; ++ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) { ++ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL. ++ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ ++ * will update as necessary. ++ */ ++ if (hc->xfer_len > 188) { ++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN; ++ } ++ } ++ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr; ++ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr; ++ st->hub_addr = hub_addr; ++ st->port_addr = port_addr; ++ } + +- hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); ++ st->hctsiz_copy.d32 = 0; ++ st->hctsiz_copy.b.dopng = 0; ++ st->hctsiz_copy.b.pid = hc->data_pid_start; + +- hcd->hub_port[hub_addr] &= ~(1 << port_addr); +-#ifdef FIQ_DEBUG +- hcd->hub_port_alloc[hub_addr * 16 + port_addr] = -1; +-#endif +- fiq_print(FIQDBG_PORTHUB, "H%dP%d:RO%d", hub_addr, port_addr, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->pipe_info.ep_num); ++ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { ++ hc->xfer_len = hc->max_packet; ++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { ++ hc->xfer_len = 188; ++ } ++ st->hctsiz_copy.b.xfersize = hc->xfer_len; + ++ st->hctsiz_copy.b.pktcnt = 1; ++ ++ if (hc->ep_type & 0x1) { ++ /* ++ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers, ++ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array. ++ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt ++ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set ++ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ ++ * must not touch internal driver state. ++ */ ++ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) { ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ } else { ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ /* The FIQ depends upon no other interrupts being enabled except channel halt. ++ * Fixup channel interrupt mask. */ ++ st->hcintmsk_copy.d32 = 0; ++ st->hcintmsk_copy.b.chhltd = 1; ++ st->hcintmsk_copy.b.ahberr = 1; ++ ++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); ++ ++ local_fiq_disable(); ++ mb(); ++ ++ if (hc->ep_type & 0x1) { ++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ frame = (hfnum.b.frnum & ~0x7) >> 3; ++ uframe = hfnum.b.frnum & 0x7; ++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { ++ /* Prevent queueing near EOF1. Bad things happen if a periodic ++ * split transaction is queued very close to EOF. ++ */ ++ start_immediate = 0; ++ } else if (uframe == 5) { ++ start_immediate = 0; ++ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) { ++ start_immediate = 0; ++ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) { ++ start_immediate = 0; ++ } else { ++ /* Search through all host channels to determine if a transaction ++ * is currently in progress */ ++ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) { ++ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ switch (hcd->fiq_state->channel[i].fsm) { ++ /* TT is reserved for channels that are in the middle of a periodic ++ * split transaction. ++ */ ++ case FIQ_PER_SSPLIT_STARTED: ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ case FIQ_PER_ISO_OUT_LAST: ++ if (hcd->fiq_state->channel[i].hub_addr == hub_addr && ++ hcd->fiq_state->channel[i].port_addr == port_addr) { ++ start_immediate = 0; ++ } ++ break; ++ default: ++ break; ++ } ++ if (!start_immediate) ++ break; ++ } ++ } ++ } ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); ++ switch (hc->ep_type) { ++ case UE_CONTROL: ++ case UE_BULK: ++ st->fsm = FIQ_NP_SSPLIT_STARTED; ++ break; ++ case UE_ISOCHRONOUS: ++ if (hc->ep_is_in) { ++ if (start_immediate) { ++ st->fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ st->fsm = FIQ_PER_SSPLIT_QUEUED; ++ } ++ } else { ++ if (start_immediate) { ++ /* Single-isoc OUT packets don't require FIQ involvement */ ++ if (st->nrpackets == 1) { ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_PENDING; ++ } ++ } ++ break; ++ case UE_INTERRUPT: ++ if (start_immediate) { ++ st->fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ st->fsm = FIQ_PER_SSPLIT_QUEUED; ++ } ++ default: ++ break; ++ } ++ if (start_immediate) { ++ /* Set the oddfrm bit as close as possible to actual queueing */ ++ frame = dwc_otg_hcd_get_frame_number(hcd); ++ st->expected_uframe = (frame + 1) & 0x3FFF; ++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; ++ st->hcchar_copy.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ } ++ mb(); ++ local_fiq_enable(); ++ return 0; + } + + +@@ -1399,16 +1901,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) + { + dwc_list_link_t *qh_ptr; + dwc_otg_qh_t *qh; +- dwc_otg_qtd_t *qtd; + int num_channels; + dwc_irqflags_t flags; + dwc_spinlock_t *channel_lock = hcd->channel_lock; + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; + +-#ifdef DEBUG_SOF +- DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); +-#endif +- + #ifdef DEBUG_HOST_CHANNELS + last_sel_trans_num_per_scheduled = 0; + last_sel_trans_num_nonper_scheduled = 0; +@@ -1423,26 +1920,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) + + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); + +- if(qh->do_split) { +- qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); +- if(!(qh->ep_type == UE_ISOCHRONOUS && +- (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || +- qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END))) { +- if(dwc_otg_hcd_allocate_port(hcd, qh)) +- { +- qh_ptr = DWC_LIST_NEXT(qh_ptr); +- g_next_sched_frame = dwc_frame_num_inc(dwc_otg_hcd_get_frame_number(hcd), 1); +- continue; +- } +- } +- } +- + if (microframe_schedule) { + // Make sure we leave one channel for non periodic transactions. + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); + if (hcd->available_host_channels <= 1) { + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); +- if(qh->do_split) dwc_otg_hcd_release_port(hcd, qh); + break; + } + hcd->available_host_channels--; +@@ -1478,27 +1960,24 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { + + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); +- + /* + * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission + * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed + * cheeky devices that just hold off using NAKs + */ +- if (nak_holdoff_enable && qh->do_split) { +- if (qh->nak_frame != 0xffff && +- dwc_full_frame_num(qh->nak_frame) == +- dwc_full_frame_num(dwc_otg_hcd_get_frame_number(hcd))) { +- /* +- * Revisit: Need to avoid trampling on periodic scheduling. +- * Currently we are safe because g_np_count != g_np_sent whenever we hit this, +- * but if this behaviour is changed then periodic endpoints will get a slower +- * polling rate. +- */ +- g_next_sched_frame = ((qh->nak_frame + 8) & ~7) & DWC_HFNUM_MAX_FRNUM; +- qh_ptr = DWC_LIST_NEXT(qh_ptr); +- continue; +- } else { +- qh->nak_frame = 0xffff; ++ if (nak_holdoff && qh->do_split) { ++ if (qh->nak_frame != 0xffff) { ++ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8); ++ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd); ++ if (dwc_frame_num_le(frame, next_frame)) { ++ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) { ++ hcd->fiq_state->next_sched_frame = next_frame; ++ } ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ continue; ++ } else { ++ qh->nak_frame = 0xFFFF; ++ } + } + } + +@@ -1527,12 +2006,29 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) + &qh->qh_list_entry); + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); + +- g_np_sent++; + + if (!microframe_schedule) + hcd->non_periodic_channels++; + } +- ++ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty, ++ * stop the FIQ from kicking us. We could potentially still have elements here if we ++ * ran out of host channels. ++ */ ++ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) { ++ hcd->fiq_state->kick_np_queues = 0; ++ } else { ++ /* For each entry remaining in the NP inactive queue, ++ * if this a NAK'd retransmit then don't set the kick flag. ++ */ ++ if(nak_holdoff) { ++ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) { ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ if (qh->nak_frame == 0xFFFF) { ++ hcd->fiq_state->kick_np_queues = 1; ++ } ++ } ++ } ++ } + if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) + ret_val |= DWC_OTG_TRANSACTION_PERIODIC; + +@@ -1577,6 +2073,12 @@ static int queue_transaction(dwc_otg_hcd_t * hcd, + hc->qh->ping_state = 0; + } + } else if (!hc->xfer_started) { ++ if (fiq_fsm_enable && hc->error_state) { ++ hcd->fiq_state->channel[hc->hc_num].nr_errors = ++ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count; ++ hcd->fiq_state->channel[hc->hc_num].fsm = ++ FIQ_PASSTHROUGH_ERRORSTATE; ++ } + dwc_otg_hc_start_transfer(hcd->core_if, hc); + hc->qh->ping_state = 0; + } +@@ -1629,7 +2131,7 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) + hptxsts_data_t tx_status; + dwc_list_link_t *qh_ptr; + dwc_otg_qh_t *qh; +- int status; ++ int status = 0; + int no_queue_space = 0; + int no_fifo_space = 0; + +@@ -1658,27 +2160,34 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) + + // Do not send a split start transaction any later than frame .6 + // Note, we have to schedule a periodic in .5 to make it go in .6 +- if(fiq_split_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) ++ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) + { + qh_ptr = qh_ptr->next; +- g_next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; ++ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; + continue; + } + +- /* +- * Set a flag if we're queuing high-bandwidth in slave mode. +- * The flag prevents any halts to get into the request queue in +- * the middle of multiple high-bandwidth packets getting queued. +- */ +- if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { +- hcd->core_if->queuing_high_bandwidth = 1; +- } +- status = +- queue_transaction(hcd, qh->channel, +- tx_status.b.ptxfspcavail); +- if (status < 0) { +- no_fifo_space = 1; +- break; ++ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { ++ if (qh->do_split) ++ fiq_fsm_queue_split_transaction(hcd, qh); ++ else ++ fiq_fsm_queue_isoc_transaction(hcd, qh); ++ } else { ++ ++ /* ++ * Set a flag if we're queueing high-bandwidth in slave mode. ++ * The flag prevents any halts to get into the request queue in ++ * the middle of multiple high-bandwidth packets getting queued. ++ */ ++ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { ++ hcd->core_if->queuing_high_bandwidth = 1; ++ } ++ status = queue_transaction(hcd, qh->channel, ++ tx_status.b.ptxfspcavail); ++ if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } + } + + /* +@@ -1795,25 +2304,19 @@ static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) + qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, + qh_list_entry); + +- // Do not send a split start transaction any later than frame .5 +- // non periodic transactions will start immediately in this uframe +- if(fiq_split_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) +- { +- g_next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; +- break; +- } +- +- status = +- queue_transaction(hcd, qh->channel, +- tx_status.b.nptxfspcavail); ++ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { ++ fiq_fsm_queue_split_transaction(hcd, qh); ++ } else { ++ status = queue_transaction(hcd, qh->channel, ++ tx_status.b.nptxfspcavail); + +- if (status > 0) { +- more_to_do = 1; +- } else if (status < 0) { +- no_fifo_space = 1; +- break; ++ if (status > 0) { ++ more_to_do = 1; ++ } else if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } + } +- + /* Advance to next QH, skipping start-of-list entry. */ + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.h b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +index 0007fa1..da2986244 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.h ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +@@ -40,6 +40,8 @@ + #include "dwc_otg_core_if.h" + #include "dwc_list.h" + #include "dwc_otg_cil.h" ++#include "dwc_otg_fiq_fsm.h" ++ + + /** + * @file +@@ -585,6 +587,12 @@ struct dwc_otg_hcd { + /** Frame List DMA address */ + dma_addr_t frame_list_dma; + ++ struct fiq_stack *fiq_stack; ++ struct fiq_state *fiq_state; ++ ++ /** Virtual address for split transaction DMA bounce buffers */ ++ struct fiq_dma_blob *fiq_dmab; ++ + #ifdef DEBUG + uint32_t frrem_samples; + uint64_t frrem_accum; +@@ -615,6 +623,9 @@ extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, + int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh); + void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh); + ++extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); ++extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh); ++extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num); + + /** @} */ + +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +index 64d33a5..be8ef1b 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +@@ -34,7 +34,6 @@ + + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" +-#include "dwc_otg_mphi_fix.h" + + #include + #include +@@ -47,33 +46,8 @@ extern bool microframe_schedule; + * This file contains the implementation of the HCD Interrupt handlers. + */ + +-/* +- * Some globals to communicate between the FIQ and INTERRUPT +- */ +- +-void * dummy_send; +-mphi_regs_t c_mphi_regs; +-volatile void *dwc_regs_base; + int fiq_done, int_done; + +-gintsts_data_t gintsts_saved = {.d32 = 0}; +-hcint_data_t hcint_saved[MAX_EPS_CHANNELS]; +-hcintmsk_data_t hcintmsk_saved[MAX_EPS_CHANNELS]; +-int split_out_xfersize[MAX_EPS_CHANNELS]; +-haint_data_t haint_saved; +- +-int g_next_sched_frame, g_np_count, g_np_sent; +-static int mphi_int_count = 0 ; +- +-hcchar_data_t nak_hcchar; +-hctsiz_data_t nak_hctsiz; +-hcsplt_data_t nak_hcsplt; +-int nak_count; +- +-int complete_sched[MAX_EPS_CHANNELS] = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}; +-int split_start_frame[MAX_EPS_CHANNELS]; +-int queued_port[MAX_EPS_CHANNELS]; +- + #ifdef FIQ_DEBUG + char buffer[1000*16]; + int wptr; +@@ -83,12 +57,10 @@ void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...) + va_list args; + char text[17]; + hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) }; +- unsigned long flags; + +- local_irq_save(flags); +- local_fiq_disable(); + if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR) + { ++ local_fiq_disable(); + snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937); + va_start(args, fmt); + vsnprintf(text+8, 9, fmt, args); +@@ -96,410 +68,21 @@ void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...) + + memcpy(buffer + wptr, text, 16); + wptr = (wptr + 16) % sizeof(buffer); ++ local_fiq_enable(); + } +- local_irq_restore(flags); + } + #endif + +-void notrace fiq_queue_request(int channel, int odd_frame) +-{ +- hcchar_data_t hcchar = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x0) }; +- hcsplt_data_t hcsplt = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x4) }; +- hctsiz_data_t hctsiz = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x10) }; +- +- if(hcsplt.b.spltena == 0) +- { +- fiq_print(FIQDBG_ERR, "SPLTENA "); +- BUG(); +- } +- +- if(hcchar.b.epdir == 1) +- { +- fiq_print(FIQDBG_SCHED, "IN Ch %d", channel); +- } +- else +- { +- hctsiz.b.xfersize = 0; +- fiq_print(FIQDBG_SCHED, "OUT Ch %d", channel); +- } +- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x10), hctsiz.d32); +- +- hcsplt.b.compsplt = 1; +- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x4), hcsplt.d32); +- +- // Send the Split complete +- hcchar.b.chen = 1; +- hcchar.b.oddfrm = odd_frame ? 1 : 0; +- +- // Post this for transmit on the next frame for periodic or this frame for non-periodic +- fiq_print(FIQDBG_SCHED, "SND_%s", odd_frame ? "ODD " : "EVEN"); +- +- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x0), hcchar.d32); +-} +- +-static int last_sof = -1; +- +-/* +-** Function to handle the start of frame interrupt, choose whether we need to do anything and +-** therefore trigger the main interrupt +-** +-** returns int != 0 - interrupt has been handled +-*/ +-int diff; +- +-int notrace fiq_sof_handle(hfnum_data_t hfnum) +-{ +- int handled = 0; +- int i; +- +- // Just check that once we're running we don't miss a SOF +- /*if(last_sof != -1 && (hfnum.b.frnum != ((last_sof + 1) & 0x3fff))) +- { +- fiq_print(FIQDBG_ERR, "LASTSOF "); +- fiq_print(FIQDBG_ERR, "%4d%d ", last_sof / 8, last_sof & 7); +- fiq_print(FIQDBG_ERR, "%4d%d ", hfnum.b.frnum / 8, hfnum.b.frnum & 7); +- BUG(); +- }*/ +- +- // Only start remembering the last sof when the interrupt has been +- // enabled (we don't check the mask to come in here...) +- if(last_sof != -1 || FIQ_READ(dwc_regs_base + 0x18) & (1<<3)) +- last_sof = hfnum.b.frnum; +- +- for(i = 0; i < MAX_EPS_CHANNELS; i++) +- { +- if(complete_sched[i] != -1) +- { +- if(complete_sched[i] <= hfnum.b.frnum || (complete_sched[i] > 0x3f00 && hfnum.b.frnum < 0xf0)) +- { +- fiq_queue_request(i, hfnum.b.frnum & 1); +- complete_sched[i] = -1; +- } +- } +- +- if(complete_sched[i] != -1) +- { +- // This is because we've seen a split complete occur with no start... +- // most likely because missed the complete 0x3fff frames ago! +- +- diff = (hfnum.b.frnum + 0x3fff - complete_sched[i]) & 0x3fff ; +- if(diff > 32 && diff < 0x3f00) +- { +- fiq_print(FIQDBG_ERR, "SPLTMISS"); +- BUG(); +- } +- } +- } +- +- if(g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum)) +- { +- /* +- * If np_count != np_sent that means we need to queue non-periodic (bulk) packets this packet +- * g_next_sched_frame is the next frame we have periodic packets for +- * +- * if neither of these are required for this frame then just clear the interrupt +- */ +- handled = 1; +- +- } +- +- return handled; +-} +- +-int notrace port_id(hcsplt_data_t hcsplt) +-{ +- return hcsplt.b.prtaddr + (hcsplt.b.hubaddr << 8); +-} +- +-int notrace fiq_hcintr_handle(int channel, hfnum_data_t hfnum) +-{ +- hcchar_data_t hcchar = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x0) }; +- hcsplt_data_t hcsplt = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x4) }; +- hcint_data_t hcint = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x8) }; +- hcintmsk_data_t hcintmsk = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0xc) }; +- hctsiz_data_t hctsiz = { .d32 = FIQ_READ(dwc_regs_base + 0x500 + (channel * 0x20) + 0x10)}; +- +- hcint_saved[channel].d32 |= hcint.d32; +- hcintmsk_saved[channel].d32 = hcintmsk.d32; +- +- if(hcsplt.b.spltena) +- { +- fiq_print(FIQDBG_PORTHUB, "ph: %4x", port_id(hcsplt)); +- if(hcint.b.chhltd) +- { +- fiq_print(FIQDBG_SCHED, "CH HLT %d", channel); +- fiq_print(FIQDBG_SCHED, "%08x", hcint_saved[channel]); +- } +- if(hcint.b.stall || hcint.b.xacterr || hcint.b.bblerr || hcint.b.frmovrun || hcint.b.datatglerr) +- { +- queued_port[channel] = 0; +- fiq_print(FIQDBG_ERR, "CHAN ERR"); +- } +- if(hcint.b.xfercomp) +- { +- // Clear the port allocation and transmit anything also on this port +- queued_port[channel] = 0; +- fiq_print(FIQDBG_SCHED, "XFERCOMP"); +- } +- if(hcint.b.nak) +- { +- queued_port[channel] = 0; +- fiq_print(FIQDBG_SCHED, "NAK"); +- } +- if(hcint.b.ack && !hcsplt.b.compsplt) +- { +- int i; +- +- // Do not complete isochronous out transactions +- if(hcchar.b.eptype == 1 && hcchar.b.epdir == 0) +- { +- queued_port[channel] = 0; +- fiq_print(FIQDBG_SCHED, "ISOC_OUT"); +- } +- else +- { +- // Make sure we check the port / hub combination that we sent this split on. +- // Do not queue a second request to the same port +- for(i = 0; i < MAX_EPS_CHANNELS; i++) +- { +- if(port_id(hcsplt) == queued_port[i]) +- { +- fiq_print(FIQDBG_ERR, "PORTERR "); +- //BUG(); +- } +- } +- +- split_start_frame[channel] = (hfnum.b.frnum + 1) & ~7; +- +- // Note, the size of an OUT is in the start split phase, not +- // the complete split +- split_out_xfersize[channel] = hctsiz.b.xfersize; +- +- hcint_saved[channel].b.chhltd = 0; +- hcint_saved[channel].b.ack = 0; +- +- queued_port[channel] = port_id(hcsplt); +- +- if(hcchar.b.eptype & 1) +- { +- // Send the periodic complete in the same oddness frame as the ACK went... +- fiq_queue_request(channel, !(hfnum.b.frnum & 1)); +- // complete_sched[channel] = dwc_frame_num_inc(hfnum.b.frnum, 1); +- } +- else +- { +- // Schedule the split complete to occur later +- complete_sched[channel] = dwc_frame_num_inc(hfnum.b.frnum, 2); +- fiq_print(FIQDBG_SCHED, "ACK%04d%d", complete_sched[channel]/8, complete_sched[channel]%8); +- } +- } +- } +- if(hcint.b.nyet) +- { +- fiq_print(FIQDBG_ERR, "NYETERR1"); +- //BUG(); +- // Can transmit a split complete up to uframe .0 of the next frame +- if(hfnum.b.frnum <= dwc_frame_num_inc(split_start_frame[channel], 8)) +- { +- // Send it next frame +- if(hcchar.b.eptype & 1) // type 1 & 3 are interrupt & isoc +- { +- fiq_print(FIQDBG_SCHED, "NYT:SEND"); +- fiq_queue_request(channel, !(hfnum.b.frnum & 1)); +- } +- else +- { +- // Schedule non-periodic access for next frame (the odd-even bit doesn't effect NP) +- complete_sched[channel] = dwc_frame_num_inc(hfnum.b.frnum, 1); +- fiq_print(FIQDBG_SCHED, "NYT%04d%d", complete_sched[channel]/8, complete_sched[channel]%8); +- } +- hcint_saved[channel].b.chhltd = 0; +- hcint_saved[channel].b.nyet = 0; +- } +- else +- { +- queued_port[channel] = 0; +- fiq_print(FIQDBG_ERR, "NYETERR2"); +- //BUG(); +- } +- } +- } +- else +- { +- /* +- * If we have any of NAK, ACK, Datatlgerr active on a +- * non-split channel, the sole reason is to reset error +- * counts for a previously broken transaction. The FIQ +- * will thrash on NAK IN and ACK OUT in particular so +- * handle it "once" and allow the IRQ to do the rest. +- */ +- hcint.d32 &= hcintmsk.d32; +- if(hcint.b.nak) +- { +- hcintmsk.b.nak = 0; +- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0xc), hcintmsk.d32); +- } +- if (hcint.b.ack) +- { +- hcintmsk.b.ack = 0; +- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0xc), hcintmsk.d32); +- } +- } +- +- // Clear the interrupt, this will also clear the HAINT bit +- FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x8), hcint.d32); +- return hcint_saved[channel].d32 == 0; +-} +- +-gintsts_data_t gintsts; +-gintmsk_data_t gintmsk; +-// triggered: The set of interrupts that were triggered +-// handled: The set of interrupts that have been handled (no IRQ is +-// required) +-// keep: The set of interrupts we want to keep unmasked even though we +-// want to trigger an IRQ to handle it (SOF and HCINTR) +-gintsts_data_t triggered, handled, keep; +-hfnum_data_t hfnum; +- +-void __attribute__ ((naked)) notrace dwc_otg_hcd_handle_fiq(void) +-{ +- +- /* entry takes care to store registers we will be treading on here */ +- asm __volatile__ ( +- "mov ip, sp ;" +- /* stash FIQ and normal regs */ +- "stmdb sp!, {r0-r12, lr};" +- /* !! THIS SETS THE FRAME, adjust to > sizeof locals */ +- "sub fp, ip, #512 ;" +- ); +- +- // Cannot put local variables at the beginning of the function +- // because otherwise 'C' will play with the stack pointer. any locals +- // need to be inside the following block +- do +- { +- fiq_done++; +- gintsts.d32 = FIQ_READ(dwc_regs_base + 0x14); +- gintmsk.d32 = FIQ_READ(dwc_regs_base + 0x18); +- hfnum.d32 = FIQ_READ(dwc_regs_base + 0x408); +- triggered.d32 = gintsts.d32 & gintmsk.d32; +- handled.d32 = 0; +- keep.d32 = 0; +- fiq_print(FIQDBG_INT, "FIQ "); +- fiq_print(FIQDBG_INT, "%08x", gintsts.d32); +- fiq_print(FIQDBG_INT, "%08x", gintmsk.d32); +- if(gintsts.d32) +- { +- // If port enabled +- if((FIQ_READ(dwc_regs_base + 0x440) & 0xf) == 0x5) +- { +- if(gintsts.b.sofintr) +- { +- if(fiq_sof_handle(hfnum)) +- { +- handled.b.sofintr = 1; /* Handled in FIQ */ +- } +- else +- { +- /* Keer interrupt unmasked */ +- keep.b.sofintr = 1; +- } +- { +- // Need to make sure the read and clearing of the SOF interrupt is as close as possible to avoid the possibility of missing +- // a start of frame interrupt +- gintsts_data_t gintsts = { .b.sofintr = 1 }; +- FIQ_WRITE((dwc_regs_base + 0x14), gintsts.d32); +- } +- } +- +- if(fiq_split_enable && gintsts.b.hcintr) +- { +- int i; +- haint_data_t haint; +- haintmsk_data_t haintmsk; +- +- haint.d32 = FIQ_READ(dwc_regs_base + 0x414); +- haintmsk.d32 = FIQ_READ(dwc_regs_base + 0x418); +- haint.d32 &= haintmsk.d32; +- haint_saved.d32 |= haint.d32; +- +- fiq_print(FIQDBG_INT, "hcintr"); +- fiq_print(FIQDBG_INT, "%08x", FIQ_READ(dwc_regs_base + 0x414)); +- +- // Go through each channel that has an enabled interrupt +- for(i = 0; i < 16; i++) +- if((haint.d32 >> i) & 1) +- if(fiq_hcintr_handle(i, hfnum)) +- haint_saved.d32 &= ~(1 << i); /* this was handled */ +- +- /* If we've handled all host channel interrupts then don't trigger the interrupt */ +- if(haint_saved.d32 == 0) +- { +- handled.b.hcintr = 1; +- } +- else +- { +- /* Make sure we keep the channel interrupt unmasked when triggering the IRQ */ +- keep.b.hcintr = 1; +- } +- +- { +- gintsts_data_t gintsts = { .b.hcintr = 1 }; +- +- // Always clear the channel interrupt +- FIQ_WRITE((dwc_regs_base + 0x14), gintsts.d32); +- } +- } +- } +- else +- { +- last_sof = -1; +- } +- } +- +- // Mask out the interrupts triggered - those handled - don't mask out the ones we want to keep +- gintmsk.d32 = keep.d32 | (gintmsk.d32 & ~(triggered.d32 & ~handled.d32)); +- // Save those that were triggered but not handled +- gintsts_saved.d32 |= triggered.d32 & ~handled.d32; +- FIQ_WRITE(dwc_regs_base + 0x18, gintmsk.d32); +- +- // Clear and save any unhandled interrupts and trigger the interrupt +- if(gintsts_saved.d32) +- { +- /* To enable the MPHI interrupt (INT 32) +- */ +- FIQ_WRITE( c_mphi_regs.outdda, (int) dummy_send); +- FIQ_WRITE( c_mphi_regs.outddb, (1 << 29)); +- +- mphi_int_count++; +- } +- } +- while(0); +- +- mb(); +- +- /* exit back to normal mode restoring everything */ +- asm __volatile__ ( +- /* return FIQ regs back to pristine state +- * and get normal regs back +- */ +- "ldmia sp!, {r0-r12, lr};" +- +- /* return */ +- "subs pc, lr, #4;" +- ); +-} +- + /** This function handles interrupts for the HCD. */ + int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) + { + int retval = 0; + static int last_time; +- + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + gintsts_data_t gintsts; + gintmsk_data_t gintmsk; + hfnum_data_t hfnum; ++ haintmsk_data_t haintmsk; + + #ifdef DEBUG + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; +@@ -517,14 +100,25 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) + /* Check if HOST Mode */ + if (dwc_otg_is_host_mode(core_if)) { + local_fiq_disable(); +- gintmsk.d32 |= gintsts_saved.d32; +- gintsts.d32 |= gintsts_saved.d32; +- gintsts_saved.d32 = 0; ++ /* Pull in from the FIQ's disabled mask */ ++ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32); ++ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0; ++ ++ ++ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) { ++ gintsts.b.hcintr = 1; ++ } ++ ++ /* Danger will robinson: fake a SOF if necessary */ ++ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) { ++ gintsts.b.sofintr = 1; ++ } ++ gintsts.d32 &= gintmsk.d32; ++ + local_fiq_enable(); + if (!gintsts.d32) { + goto exit_handler_routine; + } +- gintsts.d32 &= gintmsk.d32; + + #ifdef DEBUG + // We should be OK doing this because the common interrupts should already have been serviced +@@ -544,12 +138,7 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) + gintsts.d32, core_if); + #endif + hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum); +- if (gintsts.b.sofintr && g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum)) +- { +- /* Note, we should never get here if the FIQ is doing it's job properly*/ +- retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); +- } +- else if (gintsts.b.sofintr) { ++ if (gintsts.b.sofintr) { + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); + } + +@@ -604,37 +193,43 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) + } + + exit_handler_routine: +- +- if (fiq_fix_enable) +- { ++ if (fiq_enable) { ++ gintmsk_data_t gintmsk_new; ++ haintmsk_data_t haintmsk_new; + local_fiq_disable(); +- // Make sure that we don't clear the interrupt if we've still got pending work to do +- if(gintsts_saved.d32 == 0) +- { +- /* Clear the MPHI interrupt */ +- DWC_WRITE_REG32(c_mphi_regs.intstat, (1<<16)); +- if (mphi_int_count >= 60) +- { +- DWC_WRITE_REG32(c_mphi_regs.ctrl, ((1<<31) + (1<<16))); +- while(!(DWC_READ_REG32(c_mphi_regs.ctrl) & (1 << 17))) +- ; +- DWC_WRITE_REG32(c_mphi_regs.ctrl, (1<<31)); +- mphi_int_count = 0; +- } +- int_done++; ++ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32; ++ if(fiq_fsm_enable) ++ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32; ++ else ++ haintmsk_new.d32 = 0x0000FFFF; ++ ++ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */ ++ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) { ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16)); ++ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) { ++ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR"); ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16))); ++ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17))) ++ ; ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31)); ++ dwc_otg_hcd->fiq_state->mphi_int_count = 0; ++ } ++ int_done++; + } +- +- // Unmask handled interrupts +- FIQ_WRITE(dwc_regs_base + 0x18, gintmsk.d32); +- //DWC_MODIFY_REG32((uint32_t *)IO_ADDRESS(USB_BASE + 0x8), 0 , 1); +- ++ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); ++ /* Re-enable interrupts that the FIQ masked (first time round) */ ++ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32); + local_fiq_enable(); + +- if((jiffies / HZ) > last_time) +- { ++ if ((jiffies / HZ) > last_time) { ++ //dwc_otg_qh_t *qh; ++ //dwc_list_link_t *cur; + /* Once a second output the fiq and irq numbers, useful for debug */ + last_time = jiffies / HZ; +- DWC_DEBUGPL(DBG_USER, "int_done = %d fiq_done = %d\n", int_done, fiq_done); ++ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d", ++ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels, ++ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done); ++ //printk(KERN_WARNING "Periodic queues:\n"); + } + } + +@@ -686,6 +281,7 @@ static inline void track_missed_sofs(uint16_t curr_frame_number) + int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) + { + hfnum_data_t hfnum; ++ gintsts_data_t gintsts = { .d32 = 0 }; + dwc_list_link_t *qh_entry; + dwc_otg_qh_t *qh; + dwc_otg_transaction_type_e tr_type; +@@ -733,7 +329,7 @@ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) + } + } + +- g_next_sched_frame = next_sched_frame; ++ hcd->fiq_state->next_sched_frame = next_sched_frame; + + tr_type = dwc_otg_hcd_select_transactions(hcd); + if (tr_type != DWC_OTG_TRANSACTION_NONE) { +@@ -741,10 +337,11 @@ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) + did_something = 1; + } + +- /* Clear interrupt */ +- gintsts.b.sofintr = 1; +- DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); +- ++ /* Clear interrupt - but do not trample on the FIQ sof */ ++ if (!fiq_fsm_enable) { ++ gintsts.b.sofintr = 1; ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); ++ } + return 1; + } + +@@ -1020,19 +617,21 @@ int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd) + { + int i; + int retval = 0; +- haint_data_t haint; ++ haint_data_t haint = { .d32 = 0 } ; + + /* Clear appropriate bits in HCINTn to clear the interrupt bit in + * GINTSTS */ + +- haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); ++ if (!fiq_fsm_enable) ++ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); + + // Overwrite with saved interrupts from fiq handler +- if(fiq_split_enable) ++ if(fiq_fsm_enable) + { ++ /* check the mask? */ + local_fiq_disable(); +- haint.d32 = haint_saved.d32; +- haint_saved.d32 = 0; ++ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint); ++ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0; + local_fiq_enable(); + } + +@@ -1076,9 +675,7 @@ static uint32_t get_actual_xfer_length(dwc_hc_t * hc, + *short_read = (hctsiz.b.xfersize != 0); + } + } else if (hc->qh->do_split) { +- if(fiq_split_enable) +- length = split_out_xfersize[hc->hc_num]; +- else ++ //length = split_out_xfersize[hc->hc_num]; + length = qtd->ssplit_out_xfer_count; + } else { + length = hc->xfer_len; +@@ -1325,19 +922,17 @@ static void release_channel(dwc_otg_hcd_t * hcd, + int free_qtd; + dwc_irqflags_t flags; + dwc_spinlock_t *channel_lock = hcd->channel_lock; +-#ifdef FIQ_DEBUG +- int endp = qtd->urb ? qtd->urb->pipe_info.ep_num : 0; +-#endif ++ + int hog_port = 0; + + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", + __func__, hc->hc_num, halt_status, hc->xfer_len); + +- if(fiq_split_enable && hc->do_split) { ++ if(fiq_fsm_enable && hc->do_split) { + if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) { + if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID || + hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) { +- hog_port = 1; ++ hog_port = 0; + } + } + } +@@ -1394,6 +989,8 @@ static void release_channel(dwc_otg_hcd_t * hcd, + * function clears the channel interrupt enables and conditions, so + * there's no need to clear the Channel Halted interrupt separately. + */ ++ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH) ++ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num); + dwc_otg_hc_cleanup(hcd->core_if, hc); + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); + +@@ -1416,27 +1013,10 @@ static void release_channel(dwc_otg_hcd_t * hcd, + + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); + hcd->available_host_channels++; +- fiq_print(FIQDBG_PORTHUB, "AHC = %d ", hcd->available_host_channels); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels); + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); + } + +- if(fiq_split_enable && hc->do_split) +- { +- if(!(hcd->hub_port[hc->hub_addr] & (1 << hc->port_addr))) +- { +- fiq_print(FIQDBG_ERR, "PRTNOTAL"); +- //BUG(); +- } +- if(!hog_port && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC || +- hc->ep_type == DWC_OTG_EP_TYPE_INTR)) { +- hcd->hub_port[hc->hub_addr] &= ~(1 << hc->port_addr); +-#ifdef FIQ_DEBUG +- hcd->hub_port_alloc[hc->hub_addr * 16 + hc->port_addr] = -1; +-#endif +- fiq_print(FIQDBG_PORTHUB, "H%dP%d:RR%d", hc->hub_addr, hc->port_addr, endp); +- } +- } +- + /* Try to queue more transfers now that there's a free channel. */ + tr_type = dwc_otg_hcd_select_transactions(hcd); + if (tr_type != DWC_OTG_TRANSACTION_NONE) { +@@ -1858,7 +1438,7 @@ static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd, + switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { + case UE_BULK: + case UE_CONTROL: +- if (nak_holdoff_enable) ++ if (nak_holdoff && qtd->qh->do_split) + hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd); + } + +@@ -2074,7 +1654,7 @@ static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd, + // With the FIQ running we only ever see the failed NYET + if (dwc_full_frame_num(frnum) != + dwc_full_frame_num(hc->qh->sched_frame) || +- fiq_split_enable) { ++ fiq_fsm_enable) { + /* + * No longer in the same full speed frame. + * Treat this as a transaction error. +@@ -2460,12 +2040,11 @@ static inline int halt_status_ok(dwc_otg_hcd_t * hcd, + static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, + dwc_hc_t * hc, + dwc_otg_hc_regs_t * hc_regs, +- dwc_otg_qtd_t * qtd, +- hcint_data_t hcint, +- hcintmsk_data_t hcintmsk) ++ dwc_otg_qtd_t * qtd) + { + int out_nak_enh = 0; +- ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; + /* For core with OUT NAK enhancement, the flow for high- + * speed CONTROL/BULK OUT is handled a little differently. + */ +@@ -2495,11 +2074,9 @@ static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, + } + + /* Read the HCINTn register to determine the cause for the halt. */ +- if(!fiq_split_enable) +- { +- hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); +- hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); +- } ++ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); + + if (hcint.b.xfercomp) { + /** @todo This is here because of a possible hardware bug. Spec +@@ -2624,15 +2201,13 @@ static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, + static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, + dwc_hc_t * hc, + dwc_otg_hc_regs_t * hc_regs, +- dwc_otg_qtd_t * qtd, +- hcint_data_t hcint, +- hcintmsk_data_t hcintmsk) ++ dwc_otg_qtd_t * qtd) + { + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "Channel Halted--\n", hc->hc_num); + + if (hcd->core_if->dma_enable) { +- handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd, hcint, hcintmsk); ++ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); + } else { + #ifdef DEBUG + if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { +@@ -2645,11 +2220,368 @@ static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, + return 1; + } + ++ ++/** ++ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on ++ * FIQ transfer completion ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * 1. Un-mangle the status as recorded in each iso_frame_desc status ++ * 2. Copy it from the dwc_otg_urb into the real URB ++ */ ++void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) ++{ ++ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb; ++ int nr_frames = dwc_urb->packet_count; ++ int i; ++ hcint_data_t frame_hcint; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame_hcint.d32 = dwc_urb->iso_descs[i].status; ++ if (frame_hcint.b.xfercomp) { ++ dwc_urb->iso_descs[i].status = 0; ++ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length; ++ } else if (frame_hcint.b.frmovrun) { ++ if (qh->ep_is_in) ++ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES; ++ else ++ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else if (frame_hcint.b.xacterr) { ++ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else if (frame_hcint.b.bblerr) { ++ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else { ++ /* Something went wrong */ ++ dwc_urb->iso_descs[i].status = -1; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ dwc_urb->error_count++; ++ } ++ } ++ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n", ++ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count); ++ hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0); ++ release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++} ++ ++/** ++ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state. ++ * Returns total length of data or -1 if the buffers were not used. ++ * ++ */ ++int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) ++{ ++ dwc_hc_t *hc = qh->channel; ++ struct fiq_dma_blob *blob = hcd->fiq_dmab; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ uint8_t *ptr = NULL; ++ int index = 0, len = 0; ++ int i = 0; ++ if (hc->ep_is_in) { ++ /* Copy data out of the DMA bounce buffers to the URB's buffer. ++ * The align_buf is ignored as this is ignored on FSM enqueue. */ ++ ptr = qtd->urb->buf; ++ if (qh->ep_type == UE_ISOCHRONOUS) { ++ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */ ++ index = qtd->isoc_frame_index; ++ ptr += qtd->urb->iso_descs[index].offset; ++ } else { ++ /* Need to increment by actual_length for interrupt IN */ ++ ptr += qtd->urb->actual_length; ++ } ++ ++ for (i = 0; i < st->dma_info.index; i++) { ++ len += st->dma_info.slot_len[i]; ++ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]); ++ ptr += st->dma_info.slot_len[i]; ++ } ++ return len; ++ } else { ++ /* OUT endpoints - nothing to do. */ ++ return -1; ++ } ++ ++} ++/** ++ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt ++ * from a channel handled in the FIQ ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * If a host channel interrupt was received by the IRQ and this was a channel ++ * used by the FIQ, the execution flow for transfer completion is substantially ++ * different from the normal (messy) path. This function and its friends handles ++ * channel cleanup and transaction completion from a FIQ transaction. ++ */ ++int32_t dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) ++{ ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ dwc_hc_t *hc = hcd->hc_ptr_array[num]; ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); ++ dwc_otg_qh_t *qh = hc->qh; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num]; ++ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy; ++ int hostchannels = 0; ++ int ret = 0; ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm); ++ ++ hostchannels = hcd->available_host_channels; ++ switch (st->fsm) { ++ case FIQ_TEST: ++ break; ++ ++ case FIQ_DEQUEUE_ISSUED: ++ /* hc_halt was called. QTD no longer exists. */ ++ /* TODO: for a nonperiodic split transaction, need to issue a ++ * CLEAR_TT_BUFFER hub command if we were in the start-split phase. ++ */ ++ release_channel(hcd, hc, NULL, hc->halt_status); ++ ret = 1; ++ break; ++ ++ case FIQ_NP_SPLIT_DONE: ++ /* Nonperiodic transaction complete. */ ++ if (!hc->ep_is_in) { ++ qtd->ssplit_out_xfer_count = hc->xfer_len; ++ } ++ if (hcint.b.xfercomp) { ++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.nak) { ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } ++ ret = 1; ++ break; ++ ++ case FIQ_NP_SPLIT_HS_ABORTED: ++ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction. ++ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that ++ * because there's no guarantee which order a non-periodic split happened in. ++ * We could end up clearing a perfectly good transaction out of the buffer. ++ */ ++ if (hcint.b.xacterr) { ++ qtd->error_count += st->nr_errors; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ local_fiq_disable(); ++ BUG(); ++ } ++ break; ++ ++ case FIQ_NP_SPLIT_LS_ABORTED: ++ /* A few cases can cause this - either an unknown state on a SSPLIT or ++ * STALL/data toggle error response on a CSPLIT */ ++ if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.datatglerr) { ++ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ local_fiq_disable(); ++ BUG(); ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_DONE: ++ /* Isoc IN or Interrupt IN/OUT */ ++ ++ /* Flow control here is different from the normal execution by the driver. ++ * We need to completely ignore most of the driver's method of handling ++ * split transactions and do it ourselves. ++ */ ++ if (hc->ep_type == UE_INTERRUPT) { ++ if (hcint.b.nak) { ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } else if (hc->ep_is_in) { ++ int len; ++ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num); ++ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length); ++ qtd->urb->actual_length += len; ++ if (qtd->urb->actual_length >= qtd->urb->length) { ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ /* Interrupt transfer not complete yet - is it a short read? */ ++ if (len < hc->max_packet) { ++ /* Interrupt transaction complete */ ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ /* Further transactions required */ ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ } else { ++ /* Interrupt OUT complete. */ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ qtd->urb->actual_length += hc->xfer_len; ++ if (qtd->urb->actual_length >= qtd->urb->length) { ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ } else { ++ /* ISOC IN complete. */ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ int len = 0; ++ /* Record errors, update qtd. */ ++ if (st->nr_errors) { ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ frame_desc->status = 0; ++ /* Unswizzle dma */ ++ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num); ++ frame_desc->actual_length = len; ++ } ++ qtd->isoc_frame_index++; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_DONE: { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ if (st->nr_errors) { ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ frame_desc->status = 0; ++ frame_desc->actual_length = frame_desc->length; ++ } ++ qtd->isoc_frame_index++; ++ qtd->isoc_split_offset = 0; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_NYET_ABORTED: ++ /* Doh. lost the data. */ ++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " ++ "- FIQ reported NYET. Data may have been lost.\n", ++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); ++ if (hc->ep_type == UE_ISOCHRONOUS) { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ qtd->isoc_frame_index++; ++ qtd->isoc_split_offset = 0; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ case FIQ_HS_ISOC_DONE: ++ /* The FIQ has performed a whole pile of isochronous transactions. ++ * The status is recorded as the interrupt state should the transaction ++ * fail. ++ */ ++ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num); ++ break; ++ ++ case FIQ_PER_SPLIT_LS_ABORTED: ++ if (hcint.b.xacterr) { ++ /* Hub has responded with an ERR packet. Device ++ * has been unplugged or the port has been disabled. ++ * TODO: need to issue a reset to the hub port. */ ++ qtd->error_count += 3; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " ++ "- FIQ reported FSM=%d. Data may have been lost.\n", ++ st->fsm, hc->dev_addr, hc->ep_num); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_HS_ABORTED: ++ /* Either the SSPLIT phase suffered transaction errors or something ++ * unexpected happened. ++ */ ++ qtd->error_count += 3; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ /* Couldn't complete in the nominated frame */ ++ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " ++ "- FIQ timed out. Data may have been lost.\n", ++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); ++ if (hc->ep_type == UE_ISOCHRONOUS) { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ frame_desc->actual_length = 0; ++ if (hc->ep_is_in) { ++ frame_desc->status = -DWC_E_NO_STREAM_RES; ++ } else { ++ frame_desc->status = -DWC_E_COMMUNICATION; ++ } ++ qtd->isoc_frame_index++; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ default: ++ local_fiq_disable(); ++ DWC_WARN("unexpected state received on hc=%d fsm=%d", hc->hc_num, st->fsm); ++ BUG(); ++ } ++ //if (hostchannels != hcd->available_host_channels) { ++ /* should have incremented by now! */ ++ // BUG(); ++// } ++ return ret; ++} ++ + /** Handles interrupt for a specific Host Channel */ + int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) + { + int retval = 0; +- hcint_data_t hcint, hcint_orig; ++ hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + dwc_hc_t *hc; + dwc_otg_hc_regs_t *hc_regs; +@@ -2668,24 +2600,32 @@ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) + } + qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); + ++ /* ++ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ. ++ * Execution path is fundamentally different for the channels after a FIQ has completed ++ * a split transaction. ++ */ ++ if (fiq_fsm_enable) { ++ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) { ++ case FIQ_PASSTHROUGH: ++ break; ++ case FIQ_PASSTHROUGH_ERRORSTATE: ++ /* Hook into the error count */ ++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num); ++ if (dwc_otg_hcd->fiq_state->channel[num].nr_errors) { ++ qtd->error_count = 0; ++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET "); ++ } ++ break; ++ default: ++ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num); ++ return 1; ++ } ++ } ++ + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); +- hcint_orig = hcint; + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); +- DWC_DEBUGPL(DBG_HCDV, +- " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", +- hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); + hcint.d32 = hcint.d32 & hcintmsk.d32; +- +- if(fiq_split_enable) +- { +- // replace with the saved interrupts from the fiq handler +- local_fiq_disable(); +- hcint_orig.d32 = hcint_saved[num].d32; +- hcint.d32 = hcint_orig.d32 & hcintmsk_saved[num].d32; +- hcint_saved[num].d32 = 0; +- local_fiq_enable(); +- } +- + if (!dwc_otg_hcd->core_if->dma_enable) { + if (hcint.b.chhltd && hcint.d32 != 0x2) { + hcint.b.chhltd = 0; +@@ -2703,7 +2643,7 @@ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) + hcint.b.nyet = 0; + } + if (hcint.b.chhltd) { +- retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd, hcint_orig, hcintmsk_saved[num]); ++ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.ahberr) { + retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +index ee8eec9..dc27b24 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +@@ -58,6 +58,7 @@ + #else + #include + #endif ++#include + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) + #define USB_URB_EP_LINKING 1 +@@ -69,7 +70,8 @@ + #include "dwc_otg_dbg.h" + #include "dwc_otg_driver.h" + #include "dwc_otg_hcd.h" +-#include "dwc_otg_mphi_fix.h" ++ ++extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end; + + /** + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is +@@ -80,7 +82,7 @@ + + static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; + +-extern bool fiq_fix_enable; ++extern bool fiq_enable; + + /** @name Linux HC Driver API Functions */ + /** @{ */ +@@ -351,7 +353,6 @@ static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, + urb); + } + } +- + DWC_FREE(dwc_otg_urb); + if (!new_entry) { + DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n"); +@@ -395,13 +396,9 @@ static struct dwc_otg_hcd_function_ops hcd_fops = { + static struct fiq_handler fh = { + .name = "usb_fiq", + }; +-struct fiq_stack_s { +- int magic1; +- uint8_t stack[2048]; +- int magic2; +-} fiq_stack; + +-extern mphi_regs_t c_mphi_regs; ++ ++ + /** + * Initializes the HCD. This function allocates memory for and initializes the + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the +@@ -433,20 +430,6 @@ int hcd_init(dwc_bus_dev_t *_dev) + pci_set_consistent_dma_mask(_dev, dmamask); + #endif + +- if (fiq_fix_enable) +- { +- // Set up fiq +- claim_fiq(&fh); +- set_fiq_handler(__FIQ_Branch, 4); +- memset(®s,0,sizeof(regs)); +- regs.ARM_r8 = (long)dwc_otg_hcd_handle_fiq; +- regs.ARM_r9 = (long)0; +- regs.ARM_sp = (long)fiq_stack.stack + sizeof(fiq_stack.stack) - 4; +- set_fiq_regs(®s); +- fiq_stack.magic1 = 0xdeadbeef; +- fiq_stack.magic2 = 0xaa995566; +- } +- + /* + * Allocate memory for the base HCD plus the DWC OTG HCD. + * Initialize the base HCD. +@@ -466,30 +449,7 @@ int hcd_init(dwc_bus_dev_t *_dev) + + hcd->regs = otg_dev->os_dep.base; + +- if (fiq_fix_enable) +- { +- volatile extern void *dwc_regs_base; +- +- //Set the mphi periph to the required registers +- c_mphi_regs.base = otg_dev->os_dep.mphi_base; +- c_mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; +- c_mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; +- c_mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; +- c_mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; +- +- dwc_regs_base = otg_dev->os_dep.base; + +- //Enable mphi peripheral +- writel((1<<31),c_mphi_regs.ctrl); +-#ifdef DEBUG +- if (readl(c_mphi_regs.ctrl) & 0x80000000) +- DWC_DEBUGPL(DBG_USER, "MPHI periph has been enabled\n"); +- else +- DWC_DEBUGPL(DBG_USER, "MPHI periph has NOT been enabled\n"); +-#endif +- // Enable FIQ interrupt from USB peripheral +- enable_fiq(INTERRUPT_VC_USB); +- } + /* Initialize the DWC OTG HCD. */ + dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); + if (!dwc_otg_hcd) { +@@ -503,6 +463,55 @@ int hcd_init(dwc_bus_dev_t *_dev) + goto error2; + } + ++ if (fiq_enable) ++ { ++ if (claim_fiq(&fh)) { ++ DWC_ERROR("Can't claim FIQ"); ++ goto error2; ++ } ++ ++ DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop)); ++ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub)); ++ ++ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub); ++ memset(®s,0,sizeof(regs)); ++ ++ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state; ++ if (fiq_fsm_enable) { ++ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels; ++ //regs.ARM_r10 = dwc_otg_hcd->dma; ++ regs.ARM_fp = (long) dwc_otg_fiq_fsm; ++ } else { ++ regs.ARM_fp = (long) dwc_otg_fiq_nop; ++ } ++ ++ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4); ++ ++// __show_regs(®s); ++ set_fiq_regs(®s); ++ ++ //Set the mphi periph to the required registers ++ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base; ++ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; ++ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; ++ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; ++ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; ++ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base; ++ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base); ++ //Enable mphi peripheral ++ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl); ++#ifdef DEBUG ++ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000) ++ DWC_WARN("MPHI periph has been enabled"); ++ else ++ DWC_WARN("MPHI periph has NOT been enabled"); ++#endif ++ // Enable FIQ interrupt from USB peripheral ++ enable_fiq(INTERRUPT_VC_USB); ++ local_fiq_enable(); ++ } ++ ++ + otg_dev->hcd->otg_dev = otg_dev; + hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel) +@@ -617,9 +626,13 @@ void hcd_stop(struct usb_hcd *hcd) + /** Returns the current frame number. */ + static int get_frame_number(struct usb_hcd *hcd) + { ++ hprt0_data_t hprt0; + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); +- +- return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) ++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3; ++ else ++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); + } + + #ifdef DEBUG +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +index db95851..4d5a24c 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +@@ -41,7 +41,6 @@ + + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" +-#include "dwc_otg_mphi_fix.h" + + extern bool microframe_schedule; + +@@ -576,7 +575,6 @@ static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + } + + +-extern int g_next_sched_frame, g_np_count, g_np_sent; + + /** + * Schedules an interrupt or isochronous transfer in the periodic schedule. +@@ -636,9 +634,9 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); + } + else { +- if(DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, g_next_sched_frame)) ++ if(DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)) + { +- g_next_sched_frame = qh->sched_frame; ++ hcd->fiq_state->next_sched_frame = qh->sched_frame; + + } + /* Always start in the inactive schedule. */ +@@ -679,7 +677,7 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + /* Always start in the inactive schedule. */ + DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, + &qh->qh_list_entry); +- g_np_count++; ++ //hcd->fiq_state->kick_np_queues = 1; + } else { + status = schedule_periodic(hcd, qh); + if ( !hcd->periodic_qh_count ) { +@@ -739,13 +737,12 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + hcd->non_periodic_qh_ptr->next; + } + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); +- +- // If we've removed the last non-periodic entry then there are none left! +- g_np_count = g_np_sent; ++ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) ++ // hcd->fiq_state->kick_np_queues = 1; + } else { + deschedule_periodic(hcd, qh); + hcd->periodic_qh_count--; +- if( !hcd->periodic_qh_count ) { ++ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) { + intr_mask.b.sofintr = 1; + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, + intr_mask.d32, 0); +@@ -770,28 +767,11 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, + int sched_next_periodic_split) + { + if (dwc_qh_is_non_per(qh)) { +- +- dwc_otg_qh_t *qh_tmp; +- dwc_list_link_t *qh_list; +- DWC_LIST_FOREACH(qh_list, &hcd->non_periodic_sched_inactive) +- { +- qh_tmp = DWC_LIST_ENTRY(qh_list, struct dwc_otg_qh, qh_list_entry); +- if(qh_tmp == qh) +- { +- /* +- * FIQ is being disabled because this one nevers gets a np_count increment +- * This is still not absolutely correct, but it should fix itself with +- * just an unnecessary extra interrupt +- */ +- g_np_sent = g_np_count; +- } +- } +- +- + dwc_otg_hcd_qh_remove(hcd, qh); + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { + /* Add back to inactive non-periodic schedule. */ + dwc_otg_hcd_qh_add(hcd, qh); ++ //hcd->fiq_state->kick_np_queues = 1; + } + } else { + uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd); +@@ -850,9 +830,9 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, + &qh->qh_list_entry); + } else { +- if(!dwc_frame_num_le(g_next_sched_frame, qh->sched_frame)) ++ if(!dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame)) + { +- g_next_sched_frame = qh->sched_frame; ++ hcd->fiq_state->next_sched_frame = qh->sched_frame; + } + + DWC_LIST_MOVE_HEAD +@@ -943,6 +923,9 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, + if (*qh == NULL) { + retval = -DWC_E_NO_MEMORY; + goto done; ++ } else { ++ if (fiq_enable) ++ hcd->fiq_state->kick_np_queues = 1; + } + } + retval = dwc_otg_hcd_qh_add(hcd, *qh); +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c b/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c +deleted file mode 100755 +index 50b94a8..0000000 +--- a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c ++++ /dev/null +@@ -1,113 +0,0 @@ +-#include "dwc_otg_regs.h" +-#include "dwc_otg_dbg.h" +- +-void dwc_debug_print_core_int_reg(gintsts_data_t gintsts, const char* function_name) +-{ +- DWC_DEBUGPL(DBG_USER, "*** Debugging from within the %s function: ***\n" +- "curmode: %1i Modemismatch: %1i otgintr: %1i sofintr: %1i\n" +- "rxstsqlvl: %1i nptxfempty : %1i ginnakeff: %1i goutnakeff: %1i\n" +- "ulpickint: %1i i2cintr: %1i erlysuspend:%1i usbsuspend: %1i\n" +- "usbreset: %1i enumdone: %1i isooutdrop: %1i eopframe: %1i\n" +- "restoredone: %1i epmismatch: %1i inepint: %1i outepintr: %1i\n" +- "incomplisoin:%1i incomplisoout:%1i fetsusp: %1i resetdet: %1i\n" +- "portintr: %1i hcintr: %1i ptxfempty: %1i lpmtranrcvd:%1i\n" +- "conidstschng:%1i disconnect: %1i sessreqintr:%1i wkupintr: %1i\n", +- function_name, +- gintsts.b.curmode, +- gintsts.b.modemismatch, +- gintsts.b.otgintr, +- gintsts.b.sofintr, +- gintsts.b.rxstsqlvl, +- gintsts.b.nptxfempty, +- gintsts.b.ginnakeff, +- gintsts.b.goutnakeff, +- gintsts.b.ulpickint, +- gintsts.b.i2cintr, +- gintsts.b.erlysuspend, +- gintsts.b.usbsuspend, +- gintsts.b.usbreset, +- gintsts.b.enumdone, +- gintsts.b.isooutdrop, +- gintsts.b.eopframe, +- gintsts.b.restoredone, +- gintsts.b.epmismatch, +- gintsts.b.inepint, +- gintsts.b.outepintr, +- gintsts.b.incomplisoin, +- gintsts.b.incomplisoout, +- gintsts.b.fetsusp, +- gintsts.b.resetdet, +- gintsts.b.portintr, +- gintsts.b.hcintr, +- gintsts.b.ptxfempty, +- gintsts.b.lpmtranrcvd, +- gintsts.b.conidstschng, +- gintsts.b.disconnect, +- gintsts.b.sessreqintr, +- gintsts.b.wkupintr); +- return; +-} +- +-void dwc_debug_core_int_mask(gintmsk_data_t gintmsk, const char* function_name) +-{ +- DWC_DEBUGPL(DBG_USER, "Interrupt Mask status (called from %s) :\n" +- "modemismatch: %1i otgintr: %1i sofintr: %1i rxstsqlvl: %1i\n" +- "nptxfempty: %1i ginnakeff: %1i goutnakeff: %1i ulpickint: %1i\n" +- "i2cintr: %1i erlysuspend:%1i usbsuspend: %1i usbreset: %1i\n" +- "enumdone: %1i isooutdrop: %1i eopframe: %1i restoredone: %1i\n" +- "epmismatch: %1i inepintr: %1i outepintr: %1i incomplisoin:%1i\n" +- "incomplisoout:%1i fetsusp: %1i resetdet: %1i portintr: %1i\n" +- "hcintr: %1i ptxfempty: %1i lpmtranrcvd:%1i conidstschng:%1i\n" +- "disconnect: %1i sessreqintr:%1i wkupintr: %1i\n", +- function_name, +- gintmsk.b.modemismatch, +- gintmsk.b.otgintr, +- gintmsk.b.sofintr, +- gintmsk.b.rxstsqlvl, +- gintmsk.b.nptxfempty, +- gintmsk.b.ginnakeff, +- gintmsk.b.goutnakeff, +- gintmsk.b.ulpickint, +- gintmsk.b.i2cintr, +- gintmsk.b.erlysuspend, +- gintmsk.b.usbsuspend, +- gintmsk.b.usbreset, +- gintmsk.b.enumdone, +- gintmsk.b.isooutdrop, +- gintmsk.b.eopframe, +- gintmsk.b.restoredone, +- gintmsk.b.epmismatch, +- gintmsk.b.inepintr, +- gintmsk.b.outepintr, +- gintmsk.b.incomplisoin, +- gintmsk.b.incomplisoout, +- gintmsk.b.fetsusp, +- gintmsk.b.resetdet, +- gintmsk.b.portintr, +- gintmsk.b.hcintr, +- gintmsk.b.ptxfempty, +- gintmsk.b.lpmtranrcvd, +- gintmsk.b.conidstschng, +- gintmsk.b.disconnect, +- gintmsk.b.sessreqintr, +- gintmsk.b.wkupintr); +- return; +-} +- +-void dwc_debug_otg_int(gotgint_data_t gotgint, const char* function_name) +-{ +- DWC_DEBUGPL(DBG_USER, "otg int register (from %s function):\n" +- "sesenddet:%1i sesreqsucstschung:%2i hstnegsucstschng:%1i\n" +- "hstnegdet:%1i adevtoutchng: %2i debdone: %1i\n" +- "mvic: %1i\n", +- function_name, +- gotgint.b.sesenddet, +- gotgint.b.sesreqsucstschng, +- gotgint.b.hstnegsucstschng, +- gotgint.b.hstnegdet, +- gotgint.b.adevtoutchng, +- gotgint.b.debdone, +- gotgint.b.mvic); +- +- return; +-} +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h b/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h +deleted file mode 100755 +index ca17379..0000000 +--- a/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-#ifndef __DWC_OTG_MPHI_FIX_H__ +-#define __DWC_OTG_MPHI_FIX_H__ +-#define FIQ_WRITE(_addr_,_data_) (*(volatile uint32_t *) (_addr_) = (_data_)) +-#define FIQ_READ(_addr_) (*(volatile uint32_t *) (_addr_)) +- +-typedef struct { +- volatile void* base; +- volatile void* ctrl; +- volatile void* outdda; +- volatile void* outddb; +- volatile void* intstat; +-} mphi_regs_t; +- +-void dwc_debug_print_core_int_reg(gintsts_data_t gintsts, const char* function_name); +-void dwc_debug_core_int_mask(gintsts_data_t gintmsk, const char* function_name); +-void dwc_debug_otg_int(gotgint_data_t gotgint, const char* function_name); +- +-extern gintsts_data_t gintsts_saved; +- +-#ifdef DEBUG +-#define DWC_DBG_PRINT_CORE_INT(_arg_) dwc_debug_print_core_int_reg(_arg_,__func__) +-#define DWC_DBG_PRINT_CORE_INT_MASK(_arg_) dwc_debug_core_int_mask(_arg_,__func__) +-#define DWC_DBG_PRINT_OTG_INT(_arg_) dwc_debug_otg_int(_arg_,__func__) +- +-#else +-#define DWC_DBG_PRINT_CORE_INT(_arg_) +-#define DWC_DBG_PRINT_CORE_INT_MASK(_arg_) +-#define DWC_DBG_PRINT_OTG_INT(_arg_) +- +-#endif +- +-typedef enum { +- FIQDBG_SCHED = (1 << 0), +- FIQDBG_INT = (1 << 1), +- FIQDBG_ERR = (1 << 2), +- FIQDBG_PORTHUB = (1 << 3), +-} FIQDBG_T; +- +-void _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...); +-#ifdef FIQ_DEBUG +-#define fiq_print _fiq_print +-#else +-#define fiq_print(x, y, ...) +-#endif +- +-extern bool fiq_fix_enable, nak_holdoff_enable, fiq_split_enable; +- +-#endif +-- +1.9.1 + + +From a8c3930205d93cfc5812a8c9637aeddb510cbd40 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Thu, 1 May 2014 13:38:17 +0100 +Subject: [PATCH 101/101] config: enable CONFIG_DMA_CMA - it may fix cache + coherency issue in USB driver + +See: https://github.com/raspberrypi/linux/issues/575 +--- + arch/arm/configs/bcmrpi_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig +index f0a5370..0d1cb49 100644 +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -381,6 +381,8 @@ CONFIG_NFC=m + CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_DRBD=m -- 1.9.1