From e9371d2934733b5c15cc37042fa3121081cb15c3 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 14 Oct 2020 21:30:43 +0200 Subject: [PATCH] Allwinner: H6: Temporary disable HS-DDR mode for eMMC and remove GS1 patch --- .../H6/patches/linux/19-Beelink-GS1.patch | 33 ------------ ...C-on-some-H6-boards-by-disabling-DDR.patch | 53 +++++++++++++++++++ 2 files changed, 53 insertions(+), 33 deletions(-) delete mode 100644 projects/Allwinner/devices/H6/patches/linux/19-Beelink-GS1.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/20-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-disabling-DDR.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/19-Beelink-GS1.patch b/projects/Allwinner/devices/H6/patches/linux/19-Beelink-GS1.patch deleted file mode 100644 index f877919437..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/19-Beelink-GS1.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 542b2b42c18564c64e2d89d75ad575c0a79772ba Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sun, 27 Sep 2020 21:50:32 +0200 -Subject: [PATCH] arm64: dts: beelink-gs1: fix eMMC is 1.8V in HS200 mode -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -VQMMC is connected to BLDO2 which provides 1.8V. - -Let's reflect this in the device-tree. - -Fixes: 089bee8dd119 ("arm64: dts: allwinner: h6: Introduce Beelink GS1 board") -Signed-off-by: Clément Péron ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index 049c21718846..3f20d2c9bbbb 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -145,6 +145,7 @@ &mmc2 { - vqmmc-supply = <®_bldo2>; - non-removable; - cap-mmc-hw-reset; -+ mmc-hs200-1_8v; - bus-width = <8>; - status = "okay"; - }; --- -2.25.1 - diff --git a/projects/Allwinner/devices/H6/patches/linux/20-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-disabling-DDR.patch b/projects/Allwinner/devices/H6/patches/linux/20-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-disabling-DDR.patch new file mode 100644 index 0000000000..101a9bd946 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/20-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-disabling-DDR.patch @@ -0,0 +1,53 @@ + +Some Allwinner H6 boards have timing problems when dealing with +DDR-capable eMMC cards. These boards include the Pine H64 and Tanix TX6. + +These timing problems result in out of sync communication between the +driver and the eMMC, which renders the memory unsuable for every +operation but some basic commmands, like reading the status register. + +The cause of these timing problems is not yet well known, but they go +away by disabling DDR mode operation in the driver. Like on some H5 +boards, it might be that the traces are not precise enough to support +these speeds. However, Jernej Skrabec compared the BSP driver with this +driver, and found that the BSP driver configures pinctrl to operate at +1.8 V when entering DDR mode (although 3.3 V operation is supported), while +the mainline kernel lacks any mechanism to switch voltages dynamically. +Finally, other possible cause might be some timing parameter that is +different on the H6 with respect to other SoCs. + +Therefore, as this fix works reliably, the kernel lacks the required +dynamic pinctrl control for now and a slow eMMC is better than a not +working eMMC, just disable DDR operation for now on H6-compatible +devices. + +Signed-off-by: Alejandro González +--- + drivers/mmc/host/sunxi-mmc.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c +index d577a6b0ceae..dac57d76d009 100644 +--- a/drivers/mmc/host/sunxi-mmc.c ++++ b/drivers/mmc/host/sunxi-mmc.c +@@ -1395,14 +1395,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev) + + /* + * Some H5 devices do not have signal traces precise enough to +- * use HS DDR mode for their eMMC chips. ++ * use HS DDR mode for their eMMC chips. Other H6 devices operate ++ * unreliably on HS DDR mode, too. + * + * We still enable HS DDR modes for all the other controller +- * variants that support them. ++ * variants that support them properly. + */ + if ((host->cfg->clk_delays || host->use_new_timings) && + !of_device_is_compatible(pdev->dev.of_node, +- "allwinner,sun50i-h5-emmc")) ++ "allwinner,sun50i-h5-emmc") && ++ !of_device_is_compatible(pdev->dev.of_node, ++ "allwinner,sun50i-h6-emmc")) + mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; + + ret = mmc_of_parse(mmc);