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https://github.com/LibreELEC/LibreELEC.tv.git
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Allwinner: Update upstream patches
This commit is contained in:
Jernej Skrabec
parent
019132b031
commit
9823aed71a
@ -96,37 +96,3 @@ index a669945eb829a..ace1a6340ca9c 100644
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err_restore_page:
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return phy_restore_page(phydev, oldpage, ret);
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}
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From bb0516f4d03ffe9bcc06f840e477ea665af94e9d Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sun, 25 Aug 2019 14:40:10 +0200
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Subject: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator
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delay
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Depending on kernel and bootloader configuration, it's possible that
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Realtek ethernet PHY isn't powered on properly. It needs some time
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before it can be used.
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Fix that by adding 100ms ramp delay to regulator responsible for
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powering PHY.
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Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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index 24f1aac366d6..9612a34c1762 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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@@ -63,3 +63,7 @@
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reg = <1>;
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};
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};
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+
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+®_dc1sw {
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+ regulator-enable-ramp-delay = <100000>;
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+};
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--
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2.23.0
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@ -1,13 +0,0 @@
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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index 8a81f764abd0..46b72f2ed5cd 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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@@ -288,7 +288,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
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0, 3, /* M */
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24, 1, /* mux */
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BIT(31), /* gate */
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- 0);
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+ CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
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0x67c, BIT(0), 0);
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@ -1,77 +0,0 @@
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From ab099efa81230670679a0aa8ad6aa9cb2ac748b4 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sat, 14 Sep 2019 15:33:14 +0200
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Subject: [PATCH] clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
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Audio devices needs exact clock rates in order to correctly reproduce
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the sound. Until now, only integer factors were used to configure H6
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audio PLL which resulted in inexact rates. Fix that by adding support
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for fractional factors using sigma-delta modulation look-up table. It
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contains values for two most commonly used audio base frequencies.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
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1 file changed, 15 insertions(+), 6 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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index d89353a3cdec..ed6338d74474 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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@@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
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* hardcode it to match with the clock names.
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*/
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#define SUN50I_H6_PLL_AUDIO_REG 0x078
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+
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+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
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+ { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
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+ { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
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+};
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+
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static struct ccu_nm pll_audio_base_clk = {
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.enable = BIT(31),
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.lock = BIT(28),
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.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
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.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
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+ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
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+ BIT(24), 0x178, BIT(31)),
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.common = {
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+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
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.reg = 0x078,
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.hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
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&ccu_nm_ops,
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@@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
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};
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/*
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- * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
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- * fixed post-divider 2.
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+ * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
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+ * rates can be set exactly in conjunction with sigma-delta modulation.
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*/
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static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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clk_parent_pll_audio,
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- 8, 1, CLK_SET_RATE_PARENT);
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+ 24, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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clk_parent_pll_audio,
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4, 1, CLK_SET_RATE_PARENT);
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@@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
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}
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/*
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- * Force the post-divider of pll-audio to 8 and the output divider
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- * of it to 1, to make the clock name represents the real frequency.
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+ * Force the post-divider of pll-audio to 12 and the output divider
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+ * of it to 2, so 24576000 and 22579200 rates can be set exactly.
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*/
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val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
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val &= ~(GENMASK(21, 16) | BIT(0));
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- writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
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+ writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
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/*
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* First clock parent (osc32K) is unusable for CEC. But since there
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--
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2.23.0
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@ -5685,3 +5685,91 @@ index ba2876a64cf6..e877bf1d537c 100644
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--
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2.23.0
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From 2511366797fa6ab4a404b4b000ef7cd262aaafe8 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Mon, 9 Sep 2019 20:42:35 +0200
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Subject: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator
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delay
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Depending on kernel and bootloader configuration, it's possible that
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Realtek ethernet PHY isn't powered on properly. According to the
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datasheet, it needs 30ms to power up and then some more time before it
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can be used.
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Fix that by adding 100ms ramp delay to regulator responsible for
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powering PHY.
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Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
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Suggested-by: Ondrej Jirman <megous@megous.com>
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Maxime Ripard <mripard@kernel.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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index 24f1aac366d6..d5b6e8159a33 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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@@ -63,3 +63,12 @@
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reg = <1>;
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};
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};
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+
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+®_dc1sw {
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+ /*
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+ * Ethernet PHY needs 30ms to properly power up and some more
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+ * to initialize. 100ms should be plenty of time to finish
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+ * whole process.
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+ */
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+ regulator-enable-ramp-delay = <100000>;
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+};
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--
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2.23.0
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From ccdf3aaa27ded6db9a93eed3ca7468bb2353b8fe Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sun, 29 Sep 2019 10:52:59 +0200
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Subject: [PATCH] arm64: dts: allwinner: a64: sopine-baseboard: Add PHY
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regulator delay
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It turns out that sopine-baseboard needs same fix as pine64-plus
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for ethernet PHY. Here too Realtek ethernet PHY chip needs additional
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power on delay to properly initialize. Datasheet mentions that chip
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needs 30 ms to be properly powered on and that it needs some more time
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to be initialized.
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Fix that by adding 100ms ramp delay to regulator responsible for
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powering PHY.
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Note that issue was found out and fix tested on pine64-lts, but it's
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basically the same as sopine-baseboard, only layout and connectors
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differ.
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Fixes: bdfe4cebea11 ("arm64: allwinner: a64: add Ethernet PHY regulator for several boards")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Maxime Ripard <mripard@kernel.org>
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---
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.../boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
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index e6fb9683f213..25099202c52c 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
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@@ -159,6 +159,12 @@
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};
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®_dc1sw {
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+ /*
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+ * Ethernet PHY needs 30ms to properly power up and some more
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+ * to initialize. 100ms should be plenty of time to finish
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+ * whole process.
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+ */
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+ regulator-enable-ramp-delay = <100000>;
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regulator-name = "vcc-phy";
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};
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--
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2.23.0
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@ -155,3 +155,114 @@ index cf528c289857..4b3e863c4f8a 100644
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--
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2.23.0
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From 3ee5f8ab5e718afdde9984a089137360bdfc66eb Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sat, 14 Sep 2019 15:51:00 +0200
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Subject: [PATCH] clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
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Audio devices needs exact clock rates in order to correctly reproduce
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the sound. Until now, only integer factors were used to configure H6
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audio PLL which resulted in inexact rates. Fix that by adding support
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for fractional factors using sigma-delta modulation look-up table. It
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contains values for two most commonly used audio base frequencies.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Acked-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <mripard@kernel.org>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
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1 file changed, 15 insertions(+), 6 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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index d89353a3cdec..ed6338d74474 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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@@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
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* hardcode it to match with the clock names.
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*/
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#define SUN50I_H6_PLL_AUDIO_REG 0x078
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+
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+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
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+ { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
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+ { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
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+};
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+
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static struct ccu_nm pll_audio_base_clk = {
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.enable = BIT(31),
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.lock = BIT(28),
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.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
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.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
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+ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
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+ BIT(24), 0x178, BIT(31)),
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.common = {
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+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
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.reg = 0x078,
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.hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
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&ccu_nm_ops,
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@@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
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};
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/*
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- * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
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- * fixed post-divider 2.
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+ * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
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+ * rates can be set exactly in conjunction with sigma-delta modulation.
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*/
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static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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clk_parent_pll_audio,
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- 8, 1, CLK_SET_RATE_PARENT);
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+ 24, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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clk_parent_pll_audio,
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4, 1, CLK_SET_RATE_PARENT);
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@@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
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}
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/*
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- * Force the post-divider of pll-audio to 8 and the output divider
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- * of it to 1, to make the clock name represents the real frequency.
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+ * Force the post-divider of pll-audio to 12 and the output divider
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+ * of it to 2, so 24576000 and 22579200 rates can be set exactly.
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*/
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val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
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val &= ~(GENMASK(21, 16) | BIT(0));
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- writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
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+ writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
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/*
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* First clock parent (osc32K) is unusable for CEC. But since there
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--
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2.23.0
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From 4947913491aa83d760e5710c3290f150eb56847a Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Tue, 1 Oct 2019 21:59:25 +0200
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Subject: [PATCH] clk: sunxi-ng: h6: Allow GPU to change parent rate
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GPU PLL was designed with dynamic frequency switching in mind so driver
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can adjust rate based on the GPU load.
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Allow GPU clock to change parent rate (GPU PLL is the only possible
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parent of GPU clock).
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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index d89353a3cdec..e254c06c8621 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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@@ -290,7 +290,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
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0, 3, /* M */
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24, 1, /* mux */
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BIT(31), /* gate */
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- 0);
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+ CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
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0x67c, BIT(0), 0);
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--
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2.23.0
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