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Merge pull request #9200 from heitbaum/gcc
gcc: 14.2 upstream fix for building libaom on arm64
This commit is contained in:
Jernej Škrabec
GitHub
commit
984e99a0d2
@ -0,0 +1,199 @@
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From 32b21292adb6ad6b5e1d60d923a773e4d0daca7b Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Fri, 16 Aug 2024 07:53:01 +0100
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Subject: [PATCH] aarch64: Fix invalid nested subregs [PR115464]
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The testcase extracts one arm_neon.h vector from a pair (one subreg)
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and then reinterprets the result as an SVE vector (another subreg).
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Each subreg makes sense individually, but we can't fold them together
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into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
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but the interpretation of 32 bytes -> 16*N bytes depends on
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whether N==1 or N>1.
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Since the second subreg makes sense individually, simplify_subreg
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should bail out rather than ICE on it. simplify_gen_subreg will
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then do the same (because it already checks validate_subreg).
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This leaves simplify_gen_subreg returning null, requiring the
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caller to take appropriate action.
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I think this is relatively likely to occur elsewhere, so the patch
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adds a helper for forcing a subreg, allowing a temporary pseudo to
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be created where necessary.
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I'll follow up by using force_subreg in more places. This patch
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is intended to be a minimal backportable fix for the PR.
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gcc/
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PR target/115464
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* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
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to fold two subregs together if their relationship isn't known
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at compile time.
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* explow.h (force_subreg): Declare.
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* explow.cc (force_subreg): New function.
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* config/aarch64/aarch64-sve-builtins-base.cc
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(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
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gcc/testsuite/
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PR target/115464
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* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
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(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
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---
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gcc/config/aarch64/aarch64-sve-builtins-base.cc | 2 +-
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gcc/explow.cc | 15 +++++++++++++++
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gcc/explow.h | 2 ++
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gcc/simplify-rtx.cc | 5 +++++
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.../aarch64/sve/acle/general/pr115464.c | 13 +++++++++++++
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5 files changed, 36 insertions(+), 1 deletion(-)
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create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
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diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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index 0d2edf3f19e..c9182594bc1 100644
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--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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@@ -1174,7 +1174,7 @@ public:
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Advanced SIMD argument as an SVE vector. */
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if (!BYTES_BIG_ENDIAN
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&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
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- return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
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+ return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
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rtx_vector_builder builder (VNx16BImode, 16, 2);
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for (unsigned int i = 0; i < 16; i++)
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diff --git a/gcc/explow.cc b/gcc/explow.cc
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index 8e5f6b8e680..f6843398c4b 100644
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--- a/gcc/explow.cc
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+++ b/gcc/explow.cc
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@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
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return temp;
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}
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+/* Like simplify_gen_subreg, but force OP into a new register if the
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+ subreg cannot be formed directly. */
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+
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+rtx
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+force_subreg (machine_mode outermode, rtx op,
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+ machine_mode innermode, poly_uint64 byte)
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+{
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+ rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
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+ if (x)
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+ return x;
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+
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+ op = copy_to_mode_reg (innermode, op);
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+ return simplify_gen_subreg (outermode, op, innermode, byte);
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+}
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+
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/* If X is a memory ref, copy its contents to a new temp reg and return
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that reg. Otherwise, return X. */
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diff --git a/gcc/explow.h b/gcc/explow.h
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index 16aa02cfb68..cbd1fcb7eb3 100644
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--- a/gcc/explow.h
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+++ b/gcc/explow.h
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@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
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Args are mode (in case value is a constant) and the value. */
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extern rtx force_reg (machine_mode, rtx);
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+extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
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+
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/* Return given rtx, copied into a new temp reg if it was in memory. */
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extern rtx force_not_mem (rtx);
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diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
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index dceaa13333c..729d408aa55 100644
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--- a/gcc/simplify-rtx.cc
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+++ b/gcc/simplify-rtx.cc
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@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
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poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
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rtx newx;
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+ /* Make sure that the relationship between the two subregs is
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+ known at compile time. */
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+ if (!ordered_p (outersize, innermostsize))
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+ return NULL_RTX;
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+
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if (outermode == innermostmode
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&& known_eq (byte, 0U)
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&& known_eq (SUBREG_BYTE (op), 0))
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diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
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new file mode 100644
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index 00000000000..d728d1325ed
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
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@@ -0,0 +1,13 @@
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+/* { dg-options "-O2" } */
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+
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+#include <arm_neon.h>
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+#include <arm_sve.h>
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+#include <arm_neon_sve_bridge.h>
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+
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+svuint16_t
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+convolve4_4_x (uint16x8x2_t permute_tbl)
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+{
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+ return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
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+}
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+
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+/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
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--
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2.43.5
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From 86dacfb06b90371458d58872f461d358a0834305 Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Fri, 16 Aug 2024 07:53:02 +0100
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Subject: [PATCH] aarch64: Add another use of force_subreg [PR115464]
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This patch includes the testcase from r15-1399 plus a miminal
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fix for it, without the other proactive uses of force_subreg.
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We can backport other force_subreg calls later if they're shown
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to be needed.
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gcc/
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PR target/115464
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* config/aarch64/aarch64-sve-builtins-base.cc
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(svset_neonq_impl::expand): Use force_subreg instead of
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lowpart_subreg.
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gcc/testsuite/
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PR target/115464
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* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
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---
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gcc/config/aarch64/aarch64-sve-builtins-base.cc | 4 +++-
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.../gcc.target/aarch64/sve/acle/general/pr115464_2.c | 11 +++++++++++
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2 files changed, 14 insertions(+), 1 deletion(-)
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create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
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diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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index c9182594bc1..241a249503f 100644
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--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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@@ -1185,7 +1185,9 @@ public:
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if (BYTES_BIG_ENDIAN)
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return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
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insn_code icode = code_for_vcond_mask (mode, mode);
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- e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
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+ e.args[1] = force_subreg (mode, e.args[1], GET_MODE (e.args[1]),
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+ subreg_lowpart_offset (mode,
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+ GET_MODE (e.args[1])));
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e.add_output_operand (icode);
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e.add_input_operand (icode, e.args[1]);
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e.add_input_operand (icode, e.args[0]);
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diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
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new file mode 100644
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index 00000000000..f561c34f732
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
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@@ -0,0 +1,11 @@
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+/* { dg-options "-O2" } */
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+
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+#include <arm_neon.h>
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+#include <arm_sve.h>
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+#include <arm_neon_sve_bridge.h>
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+
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+svuint16_t
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+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
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+{
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+ return svset_neonq_u16 (a, permute_tbl.val[1]);
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+}
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--
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2.43.5
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