From 9a24926f9fd16f56f3b57980305f6021963b8677 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sat, 9 Oct 2021 17:01:17 +1100 Subject: [PATCH] linux (Allwinner): patches upstreamed in 5.15 --- ...media-hevc-Add-segment-address-field.patch | 45 ---- ...hevc-Add-support-for-multiple-slices.patch | 92 -------- ...s-allwinner-h6-tanix-tx6-enable-emmc.patch | 55 ----- ...n4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch | 210 ------------------ 4 files changed, 402 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch delete mode 100644 projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch delete mode 100644 projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch delete mode 100644 projects/Allwinner/patches/linux/0056-drm-sun4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch diff --git a/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch b/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch deleted file mode 100644 index 14f14b8070..0000000000 --- a/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 229e5bdcd39ed3ca0a71dc8500ba4ea90d4415db Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 6 Jun 2021 10:23:13 +0200 -Subject: [PATCH] media: hevc: Add segment address field - -If HEVC frame consists of multiple slices, segment address has to be -known in order to properly decode it. - -Add segment address field to slice parameters. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 3 +++ - include/media/hevc-ctrls.h | 3 ++- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -3000,6 +3000,9 @@ enum v4l2_mpeg_video_hevc_size_of_length - * - __u8 - - ``pic_struct`` - - -+ * - __u32 -+ - ``slice_segment_addr`` -+ - - * - __u8 - - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` - - The list of L0 reference elements as indices in the DPB. ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -196,10 +196,11 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 pic_struct; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -- __u8 padding[5]; -+ __u8 padding; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; diff --git a/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch b/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch deleted file mode 100644 index 4a2a85f591..0000000000 --- a/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch +++ /dev/null @@ -1,92 +0,0 @@ -From d92a4a27d983032267b231a32be98a11a9995e5c Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 6 Jun 2021 10:23:14 +0200 -Subject: [PATCH] media: cedrus: hevc: Add support for multiple slices - -Now that segment address is available, support for multi-slice frames -can be easily added. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/sunxi/cedrus/cedrus_h265.c | 26 ++++++++++++------- - .../staging/media/sunxi/cedrus/cedrus_video.c | 1 + - 2 files changed, 17 insertions(+), 10 deletions(-) - ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -247,6 +247,8 @@ static void cedrus_h265_setup(struct ced - const struct v4l2_ctrl_hevc_slice_params *slice_params; - const struct v4l2_ctrl_hevc_decode_params *decode_params; - const struct v4l2_hevc_pred_weight_table *pred_weight_table; -+ unsigned int width_in_ctb_luma, ctb_size_luma; -+ unsigned int log2_max_luma_coding_block_size; - dma_addr_t src_buf_addr; - dma_addr_t src_buf_end_addr; - u32 chroma_log2_weight_denom; -@@ -260,15 +262,17 @@ static void cedrus_h265_setup(struct ced - decode_params = run->h265.decode_params; - pred_weight_table = &slice_params->pred_weight_table; - -+ log2_max_luma_coding_block_size = -+ sps->log2_min_luma_coding_block_size_minus3 + 3 + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_luma = 1UL << log2_max_luma_coding_block_size; -+ width_in_ctb_luma = -+ DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); -+ - /* MV column buffer size and allocation. */ - if (!ctx->codec.h265.mv_col_buf_size) { - unsigned int num_buffers = - run->dst->vb2_buf.vb2_queue->num_buffers; -- unsigned int log2_max_luma_coding_block_size = -- sps->log2_min_luma_coding_block_size_minus3 + 3 + -- sps->log2_diff_max_min_luma_coding_block_size; -- unsigned int ctb_size_luma = -- 1UL << log2_max_luma_coding_block_size; - - /* - * Each CTB requires a MV col buffer with a specific unit size. -@@ -322,15 +326,17 @@ static void cedrus_h265_setup(struct ced - reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); - cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); - -- /* Coding tree block address: start at the beginning. */ -- reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0); -+ /* Coding tree block address */ -+ reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma); -+ reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma); - cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); - - cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); - cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); - - /* Clear the number of correctly-decoded coding tree blocks. */ -- cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); -+ if (ctx->fh.m2m_ctx->new_frame) -+ cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); - - /* Initialize bitstream access. */ - cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); -@@ -482,8 +488,8 @@ static void cedrus_h265_setup(struct ced - V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT, - slice_params->flags); - -- /* FIXME: For multi-slice support. */ -- reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; -+ if (ctx->fh.m2m_ctx->new_frame) -+ reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; - - cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); - ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -340,6 +340,7 @@ static int cedrus_s_fmt_vid_out(struct f - - switch (ctx->src_fmt.pixelformat) { - case V4L2_PIX_FMT_H264_SLICE: -+ case V4L2_PIX_FMT_HEVC_SLICE: - vq->subsystem_flags |= - VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF; - break; diff --git a/projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch b/projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch deleted file mode 100644 index 1d719749c0..0000000000 --- a/projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 15 Jan 2020 18:39:17 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: tanix-tx6: enable emmc - -Tanix TX6 has 32 GiB eMMC. Add a node for it. - -Signed-off-by: Jernej Skrabec ---- - .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 20 +++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -32,6 +32,13 @@ - }; - }; - -+ reg_vcc1v8: regulator-vcc1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; -@@ -91,6 +98,15 @@ - status = "okay"; - }; - -+&mmc2 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc1v8>; -+ non-removable; -+ cap-mmc-hw-reset; -+ bus-width = <8>; -+ status = "okay"; -+}; -+ - &ohci0 { - status = "okay"; - }; -@@ -99,6 +115,10 @@ - status = "okay"; - }; - -+&pio { -+ vcc-pc-supply = <®_vcc1v8>; -+}; -+ - &r_ir { - linux,rc-map-name = "rc-tanix-tx5max"; - status = "okay"; diff --git a/projects/Allwinner/patches/linux/0056-drm-sun4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch b/projects/Allwinner/patches/linux/0056-drm-sun4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch deleted file mode 100644 index 2fbf20dab2..0000000000 --- a/projects/Allwinner/patches/linux/0056-drm-sun4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch +++ /dev/null @@ -1,210 +0,0 @@ -From 887d1018e2c5ab5e81edbd1318bbf4bbd2c739b0 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 12 Sep 2021 20:15:26 +0200 -Subject: [PATCH] drm/sun4i: dw-hdmi: Fix HDMI PHY clock setup - -Recent rework which made HDMI PHY driver a platform device inadvertely -reversed clock setup order. HW is very touch about it. Proper way is to -handle controllers resets and clocks first and HDMI PHYs second. - -Move HDMI PHY reset & clocks handling to sun8i_hdmi_phy_init() which -will assure that code is executed after controllers reset & clocks are -handled. Additionally, add sun8i_hdmi_phy_deinit() which will deinit it -at controllers driver unload. - -Fixes: 9bf3797796f5 ("drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 7 +- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 4 +- - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 97 ++++++++++++++------------ - 3 files changed, 61 insertions(+), 47 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -index f75fb157f2ff..5fa5407ac583 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -216,11 +216,13 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, - goto err_disable_clk_tmds; - } - -+ ret = sun8i_hdmi_phy_init(hdmi->phy); -+ if (ret) -+ return ret; -+ - drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - -- sun8i_hdmi_phy_init(hdmi->phy); -- - plat_data->mode_valid = hdmi->quirks->mode_valid; - plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe; - sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data); -@@ -262,6 +264,7 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, - struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev); - - dw_hdmi_unbind(hdmi->hdmi); -+ sun8i_hdmi_phy_deinit(hdmi->phy); - clk_disable_unprepare(hdmi->clk_tmds); - reset_control_assert(hdmi->rst_ctrl); - gpiod_set_value(hdmi->ddc_en, 0); -diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -index 74f6ed0e2570..bffe1b9cd3dc 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -169,6 +169,7 @@ struct sun8i_hdmi_phy { - struct clk *clk_phy; - struct clk *clk_pll0; - struct clk *clk_pll1; -+ struct device *dev; - unsigned int rcal; - struct regmap *regs; - struct reset_control *rst_phy; -@@ -205,7 +206,8 @@ encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder) - - int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node); - --void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy); -+int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy); -+void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy); - void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, - struct dw_hdmi_plat_data *plat_data); - -diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -index c9239708d398..78b152973957 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -506,9 +506,60 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) - phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2; - } - --void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) -+int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) - { -+ int ret; -+ -+ ret = reset_control_deassert(phy->rst_phy); -+ if (ret) { -+ dev_err(phy->dev, "Cannot deassert phy reset control: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(phy->clk_bus); -+ if (ret) { -+ dev_err(phy->dev, "Cannot enable bus clock: %d\n", ret); -+ goto err_deassert_rst_phy; -+ } -+ -+ ret = clk_prepare_enable(phy->clk_mod); -+ if (ret) { -+ dev_err(phy->dev, "Cannot enable mod clock: %d\n", ret); -+ goto err_disable_clk_bus; -+ } -+ -+ if (phy->variant->has_phy_clk) { -+ ret = sun8i_phy_clk_create(phy, phy->dev, -+ phy->variant->has_second_pll); -+ if (ret) { -+ dev_err(phy->dev, "Couldn't create the PHY clock\n"); -+ goto err_disable_clk_mod; -+ } -+ -+ clk_prepare_enable(phy->clk_phy); -+ } -+ - phy->variant->phy_init(phy); -+ -+ return 0; -+ -+err_disable_clk_mod: -+ clk_disable_unprepare(phy->clk_mod); -+err_disable_clk_bus: -+ clk_disable_unprepare(phy->clk_bus); -+err_deassert_rst_phy: -+ reset_control_assert(phy->rst_phy); -+ -+ return ret; -+} -+ -+void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy) -+{ -+ clk_disable_unprepare(phy->clk_mod); -+ clk_disable_unprepare(phy->clk_bus); -+ clk_disable_unprepare(phy->clk_phy); -+ -+ reset_control_assert(phy->rst_phy); - } - - void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, -@@ -638,6 +689,7 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev) - return -ENOMEM; - - phy->variant = (struct sun8i_hdmi_phy_variant *)match->data; -+ phy->dev = dev; - - ret = of_address_to_resource(node, 0, &res); - if (ret) { -@@ -696,47 +748,10 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev) - goto err_put_clk_pll1; - } - -- ret = reset_control_deassert(phy->rst_phy); -- if (ret) { -- dev_err(dev, "Cannot deassert phy reset control: %d\n", ret); -- goto err_put_rst_phy; -- } -- -- ret = clk_prepare_enable(phy->clk_bus); -- if (ret) { -- dev_err(dev, "Cannot enable bus clock: %d\n", ret); -- goto err_deassert_rst_phy; -- } -- -- ret = clk_prepare_enable(phy->clk_mod); -- if (ret) { -- dev_err(dev, "Cannot enable mod clock: %d\n", ret); -- goto err_disable_clk_bus; -- } -- -- if (phy->variant->has_phy_clk) { -- ret = sun8i_phy_clk_create(phy, dev, -- phy->variant->has_second_pll); -- if (ret) { -- dev_err(dev, "Couldn't create the PHY clock\n"); -- goto err_disable_clk_mod; -- } -- -- clk_prepare_enable(phy->clk_phy); -- } -- - platform_set_drvdata(pdev, phy); - - return 0; - --err_disable_clk_mod: -- clk_disable_unprepare(phy->clk_mod); --err_disable_clk_bus: -- clk_disable_unprepare(phy->clk_bus); --err_deassert_rst_phy: -- reset_control_assert(phy->rst_phy); --err_put_rst_phy: -- reset_control_put(phy->rst_phy); - err_put_clk_pll1: - clk_put(phy->clk_pll1); - err_put_clk_pll0: -@@ -753,12 +768,6 @@ static int sun8i_hdmi_phy_remove(struct platform_device *pdev) - { - struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev); - -- clk_disable_unprepare(phy->clk_mod); -- clk_disable_unprepare(phy->clk_bus); -- clk_disable_unprepare(phy->clk_phy); -- -- reset_control_assert(phy->rst_phy); -- - reset_control_put(phy->rst_phy); - - clk_put(phy->clk_pll0); --- -2.33.0 -