From 9bb5811e5463511881ced4d9459d705d7878d5d4 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Thu, 27 Jan 2022 12:03:05 +0000 Subject: [PATCH] linux (NXP iMX8): media: hantro: Let VPU decoders get controlled by vpu blk ctrl --- ...oders-get-controlled-by-vpu-blk-ctrl.patch | 1579 +++++++++++++++++ ...Introduce-struct-hantro_postproc_ops.patch | 229 +++ 2 files changed, 1808 insertions(+) create mode 100644 projects/NXP/devices/iMX8/patches/linux/0050-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch create mode 100644 projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch diff --git a/projects/NXP/devices/iMX8/patches/linux/0050-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch b/projects/NXP/devices/iMX8/patches/linux/0050-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch new file mode 100644 index 0000000000..47ca7ce65a --- /dev/null +++ b/projects/NXP/devices/iMX8/patches/linux/0050-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch @@ -0,0 +1,1579 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id EA8AFC433EF + for ; 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+ Tue, 25 Jan 2022 09:12:25 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Lucas Stach , + Rob Herring , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains +Date: Tue, 25 Jan 2022 11:11:19 -0600 +Message-Id: <20220125171129.472775-3-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 641 +Lines: 23 + +From: Lucas Stach + +This adds the defines for the power domains provided by the VPU +blk-ctrl on the i.MX8MQ. + +Signed-off-by: Lucas Stach +Acked-by: Rob Herring + +diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h +index 8a513bd9166e..9f7d0f1e7c32 100644 +--- a/include/dt-bindings/power/imx8mq-power.h ++++ b/include/dt-bindings/power/imx8mq-power.h +@@ -18,4 +18,7 @@ + #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 + #define IMX8M_POWER_DOMAIN_PCIE2 10 + ++#define IMX8MQ_VPUBLK_PD_G1 0 ++#define IMX8MQ_VPUBLK_PD_G2 1 ++ + #endif +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 660BCC433F5 + for ; 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+ Tue, 25 Jan 2022 09:12:28 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Lucas Stach , + Adam Ford , Rob Herring , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl +Date: Tue, 25 Jan 2022 11:11:20 -0600 +Message-Id: <20220125171129.472775-4-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 2143 +Lines: 88 + +From: Lucas Stach + +This adds the DT binding for the i.MX8MQ VPU blk-ctrl. + +Signed-off-by: Lucas Stach +Signed-off-by: Adam Ford +Reviewed-by: Rob Herring + +diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml +new file mode 100644 +index 000000000000..7263ebedf09f +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: NXP i.MX8MQ VPU blk-ctrl ++ ++maintainers: ++ - Lucas Stach ++ ++description: ++ The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to ++ the NoC and ensuring proper power sequencing of the VPU peripherals ++ located in the VPU domain of the SoC. ++ ++properties: ++ compatible: ++ items: ++ - const: fsl,imx8mq-vpu-blk-ctrl ++ ++ reg: ++ maxItems: 1 ++ ++ '#power-domain-cells': ++ const: 1 ++ ++ power-domains: ++ minItems: 3 ++ maxItems: 3 ++ ++ power-domain-names: ++ items: ++ - const: bus ++ - const: g1 ++ - const: g2 ++ ++ clocks: ++ minItems: 2 ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: g1 ++ - const: g2 ++ ++required: ++ - compatible ++ - reg ++ - power-domains ++ - power-domain-names ++ - clocks ++ - clock-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ vpu_blk_ctrl: blk-ctrl@38320000 { ++ compatible = "fsl,imx8mq-vpu-blk-ctrl"; ++ reg = <0x38320000 0x100>; ++ power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; ++ power-domain-names = "bus", "g1", "g2"; ++ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, ++ <&clk IMX8MQ_CLK_VPU_G2_ROOT>; ++ clock-names = "g1", "g2"; ++ #power-domain-cells = <1>; ++ }; +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 45478C433FE + for ; Tue, 25 Jan 2022 17:16:04 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1573229AbiAYRQC (ORCPT ); + Tue, 25 Jan 2022 12:16:02 -0500 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47222 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S239868AbiAYRNl (ORCPT + ); + Tue, 25 Jan 2022 12:13:41 -0500 +Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 078DBC061762; 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+ ++static int imx8mq_vpu_power_notifier(struct notifier_block *nb, ++ unsigned long action, void *data) ++{ ++ struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, ++ power_nb); ++ ++ if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) ++ return NOTIFY_OK; ++ ++ /* ++ * The ADB in the VPUMIX domain has no separate reset and clock ++ * enable bits, but is ungated and reset together with the VPUs. The ++ * reset and clock enable inputs to the ADB is a logical OR of the ++ * VPU bits. In order to set the G2 fuse bits, the G2 clock must ++ * also be enabled. ++ */ ++ regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1)); ++ regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1)); ++ ++ if (action == GENPD_NOTIFY_ON) { ++ /* ++ * On power up we have no software backchannel to the GPC to ++ * wait for the ADB handshake to happen, so we just delay for a ++ * bit. On power down the GPC driver waits for the handshake. ++ */ ++ udelay(5); ++ ++ /* set "fuse" bits to enable the VPUs */ ++ regmap_set_bits(bc->regmap, 0x8, 0xffffffff); ++ regmap_set_bits(bc->regmap, 0xc, 0xffffffff); ++ regmap_set_bits(bc->regmap, 0x10, 0xffffffff); ++ } ++ ++ return NOTIFY_OK; ++} ++ ++static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { ++ [IMX8MQ_VPUBLK_PD_G1] = { ++ .name = "vpublk-g1", ++ .clk_names = (const char *[]){ "g1", }, ++ .num_clks = 1, ++ .gpc_name = "g1", ++ .rst_mask = BIT(1), ++ .clk_mask = BIT(1), ++ }, ++ [IMX8MQ_VPUBLK_PD_G2] = { ++ .name = "vpublk-g2", ++ .clk_names = (const char *[]){ "g2", }, ++ .num_clks = 1, ++ .gpc_name = "g2", ++ .rst_mask = BIT(0), ++ .clk_mask = BIT(0), ++ }, ++}; ++ ++static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { ++ .max_reg = 0x14, ++ .power_notifier_fn = imx8mq_vpu_power_notifier, ++ .domains = imx8mq_vpu_blk_ctl_domain_data, ++ .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), ++}; ++ + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { + { + .compatible = "fsl,imx8mm-vpu-blk-ctrl", +@@ -599,6 +662,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { + .compatible = "fsl,imx8mm-disp-blk-ctrl", + .data = &imx8mm_disp_blk_ctl_dev_data + } ,{ ++ .compatible = "fsl,imx8mq-vpu-blk-ctrl", ++ .data = &imx8mq_vpu_blk_ctl_dev_data ++ } ,{ + /* Sentinel */ + } + }; +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 7D22FC433F5 + for ; Tue, 25 Jan 2022 17:16:07 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1356019AbiAYRQD (ORCPT ); + Tue, 25 Jan 2022 12:16:03 -0500 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47224 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S242752AbiAYRNn (ORCPT + ); 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+ Tue, 25 Jan 2022 09:12:34 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Adam Ford , Rob Herring , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + Lucas Stach , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 05/11] dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes +Date: Tue, 25 Jan 2022 11:11:22 -0600 +Message-Id: <20220125171129.472775-6-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 3467 +Lines: 115 + +The G1 and G2 are independent and separate decoder blocks +that are enabled by the vpu-blk-ctrl power-domain controller, +which now has a proper driver. + +Because these blocks only share the power-domain, and can be +independently fused out, update the bindings to support separate +nodes for the G1 and G2 decoders with vpu-blk-ctrl power-domain +support. + +The new DT + old kernel isn't a supported configuration. + +Signed-off-by: Adam Ford +Reviewed-by: Rob Herring +Reviewed-by: Ezequiel Garcia + +diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +index 762be3f96ce9..9c28d562112b 100644 +--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml ++++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +@@ -15,33 +15,20 @@ description: + + properties: + compatible: +- const: nxp,imx8mq-vpu ++ oneOf: ++ - const: nxp,imx8mq-vpu ++ deprecated: true ++ - const: nxp,imx8mq-vpu-g1 ++ - const: nxp,imx8mq-vpu-g2 + + reg: +- maxItems: 3 +- +- reg-names: +- items: +- - const: g1 +- - const: g2 +- - const: ctrl ++ maxItems: 1 + + interrupts: +- maxItems: 2 +- +- interrupt-names: +- items: +- - const: g1 +- - const: g2 ++ maxItems: 1 + + clocks: +- maxItems: 3 +- +- clock-names: +- items: +- - const: g1 +- - const: g2 +- - const: bus ++ maxItems: 1 + + power-domains: + maxItems: 1 +@@ -49,31 +36,33 @@ properties: + required: + - compatible + - reg +- - reg-names + - interrupts +- - interrupt-names + - clocks +- - clock-names + + additionalProperties: false + + examples: + - | + #include ++ #include ++ #include ++ ++ vpu_g1: video-codec@38300000 { ++ compatible = "nxp,imx8mq-vpu-g1"; ++ reg = <0x38300000 0x10000>; ++ interrupts = ; ++ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; ++ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; ++ }; ++ - | ++ #include ++ #include + #include + +- vpu: video-codec@38300000 { +- compatible = "nxp,imx8mq-vpu"; +- reg = <0x38300000 0x10000>, +- <0x38310000 0x10000>, +- <0x38320000 0x10000>; +- reg-names = "g1", "g2", "ctrl"; +- interrupts = , +- ; +- interrupt-names = "g1", "g2"; +- clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, +- <&clk IMX8MQ_CLK_VPU_G2_ROOT>, +- <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; +- clock-names = "g1", "g2", "bus"; +- power-domains = <&pgc_vpu>; ++ vpu_g2: video-codec@38300000 { ++ compatible = "nxp,imx8mq-vpu-g2"; ++ reg = <0x38310000 0x10000>; ++ interrupts = ; ++ clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; ++ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id E04ABC433FE + for ; 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+ Tue, 25 Jan 2022 09:12:36 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Adam Ford , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + Lucas Stach , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 06/11] media: hantro: Allow i.MX8MQ G1 and G2 to run independently +Date: Tue, 25 Jan 2022 11:11:23 -0600 +Message-Id: <20220125171129.472775-7-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 5544 +Lines: 151 + +The VPU in the i.MX8MQ is really the combination of Hantro G1 and +Hantro G2. With the updated vpu-blk-ctrl, the power domains system +can enable and disable them separately as well as pull them out of +reset. This simplifies the code and lets them run independently +while still retaining backwards compatibility with older device +trees for those using G1. + +Signed-off-by: Adam Ford +Reviewed-by: Ezequiel Garcia + +diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c +index 6a51f39dde56..f56e8b3efada 100644 +--- a/drivers/staging/media/hantro/hantro_drv.c ++++ b/drivers/staging/media/hantro/hantro_drv.c +@@ -616,6 +616,7 @@ static const struct of_device_id of_hantro_match[] = { + #endif + #ifdef CONFIG_VIDEO_HANTRO_IMX8M + { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, ++ { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, + { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, + #endif + #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 +@@ -890,6 +891,15 @@ static int hantro_probe(struct platform_device *pdev) + match = of_match_node(of_hantro_match, pdev->dev.of_node); + vpu->variant = match->data; + ++ /* ++ * Support for nxp,imx8mq-vpu is kept for backwards compatibility ++ * but it's deprecated. Please update your DTS file to use ++ * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead. ++ */ ++ if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu")) ++ dev_warn(&pdev->dev, "%s compatible is deprecated\n", ++ match->compatible); ++ + INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog); + + vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks, +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 4a19ae8940b9..f0bd2ffe290b 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -299,6 +299,7 @@ enum hantro_enc_fmt { + ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, + }; + ++extern const struct hantro_variant imx8mq_vpu_g1_variant; + extern const struct hantro_variant imx8mq_vpu_g2_variant; + extern const struct hantro_variant imx8mq_vpu_variant; + extern const struct hantro_variant px30_vpu_variant; +diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c +index f5991b8e553a..849ea7122d47 100644 +--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c ++++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c +@@ -205,13 +205,6 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) + imx8m_soft_reset(vpu, RESET_G1); + } + +-static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx) +-{ +- struct hantro_dev *vpu = ctx->dev; +- +- imx8m_soft_reset(vpu, RESET_G2); +-} +- + /* + * Supported codec ops. + */ +@@ -237,10 +230,27 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { + }, + }; + ++static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = { ++ [HANTRO_MODE_MPEG2_DEC] = { ++ .run = hantro_g1_mpeg2_dec_run, ++ .init = hantro_mpeg2_dec_init, ++ .exit = hantro_mpeg2_dec_exit, ++ }, ++ [HANTRO_MODE_VP8_DEC] = { ++ .run = hantro_g1_vp8_dec_run, ++ .init = hantro_vp8_dec_init, ++ .exit = hantro_vp8_dec_exit, ++ }, ++ [HANTRO_MODE_H264_DEC] = { ++ .run = hantro_g1_h264_dec_run, ++ .init = hantro_h264_dec_init, ++ .exit = hantro_h264_dec_exit, ++ }, ++}; ++ + static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { + [HANTRO_MODE_HEVC_DEC] = { + .run = hantro_g2_hevc_dec_run, +- .reset = imx8m_vpu_g2_reset, + .init = hantro_hevc_dec_init, + .exit = hantro_hevc_dec_exit, + }, +@@ -267,6 +276,8 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { + + static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; + static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; ++static const char * const imx8mq_g1_clk_names[] = { "g1" }; ++static const char * const imx8mq_g2_clk_names[] = { "g2" }; + + const struct hantro_variant imx8mq_vpu_variant = { + .dec_fmts = imx8m_vpu_dec_fmts, +@@ -287,6 +298,21 @@ const struct hantro_variant imx8mq_vpu_variant = { + .num_regs = ARRAY_SIZE(imx8mq_reg_names) + }; + ++const struct hantro_variant imx8mq_vpu_g1_variant = { ++ .dec_fmts = imx8m_vpu_dec_fmts, ++ .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), ++ .postproc_fmts = imx8m_vpu_postproc_fmts, ++ .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), ++ .postproc_ops = &hantro_g1_postproc_ops, ++ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | ++ HANTRO_H264_DECODER, ++ .codec_ops = imx8mq_vpu_g1_codec_ops, ++ .irqs = imx8mq_irqs, ++ .num_irqs = ARRAY_SIZE(imx8mq_irqs), ++ .clk_names = imx8mq_g1_clk_names, ++ .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), ++}; ++ + const struct hantro_variant imx8mq_vpu_g2_variant = { + .dec_offset = 0x0, + .dec_fmts = imx8m_vpu_g2_dec_fmts, +@@ -296,10 +322,8 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { + .postproc_ops = &hantro_g2_postproc_ops, + .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, + .codec_ops = imx8mq_vpu_g2_codec_ops, +- .init = imx8mq_vpu_hw_init, +- .runtime_resume = imx8mq_runtime_resume, + .irqs = imx8mq_g2_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), +- .clk_names = imx8mq_clk_names, +- .num_clocks = ARRAY_SIZE(imx8mq_clk_names), ++ .clk_names = imx8mq_g2_clk_names, ++ .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), + }; +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 5ADA7C4332F + for ; Tue, 25 Jan 2022 17:16:33 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1587263AbiAYRQ2 (ORCPT ); + Tue, 25 Jan 2022 12:16:28 -0500 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47234 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1351081AbiAYRNs (ORCPT + ); + Tue, 25 Jan 2022 12:13:48 -0500 +Received: from mail-io1-xd2e.google.com (mail-io1-xd2e.google.com [IPv6:2607:f8b0:4864:20::d2e]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E059C061798; + Tue, 25 Jan 2022 09:12:41 -0800 (PST) +Received: by mail-io1-xd2e.google.com with SMTP id z199so9995184iof.10; + Tue, 25 Jan 2022 09:12:41 -0800 (PST) +DKIM-Signature: v=1; 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+ Tue, 25 Jan 2022 09:12:40 -0800 (PST) +Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:6592:b6fe:71b1:9f4c]) + by smtp.gmail.com with ESMTPSA id m14sm8090291iov.0.2022.01.25.09.12.38 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Tue, 25 Jan 2022 09:12:39 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Adam Ford , + kernel test robot , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + Lucas Stach , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl +Date: Tue, 25 Jan 2022 11:11:24 -0600 +Message-Id: <20220125171129.472775-8-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 3537 +Lines: 97 + +With the Hantro G1 and G2 now setup to run independently, update +the device tree to allow both to operate. This requires the +vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs +certain clock enabled to handle the gating of the G1 and G2 +fuses, the clock-parents and clock-rates for the various VPU's +to be moved into the pgc_vpu because they cannot get re-parented +once enabled, and the pgc_vpu is the highest in the chain. + +Signed-off-by: Adam Ford +Reported-by: kernel test robot +Reviewed-by: Ezequiel Garcia + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi +index 2df2510d0118..549b2440f55d 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi +@@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 { + pgc_vpu: power-domain@6 { + #power-domain-cells = <0>; + reg = ; +- clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; ++ clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, ++ <&clk IMX8MQ_CLK_VPU_G1_ROOT>, ++ <&clk IMX8MQ_CLK_VPU_G2_ROOT>; ++ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, ++ <&clk IMX8MQ_CLK_VPU_G2>, ++ <&clk IMX8MQ_CLK_VPU_BUS>, ++ <&clk IMX8MQ_VPU_PLL_BYPASS>; ++ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, ++ <&clk IMX8MQ_VPU_PLL_OUT>, ++ <&clk IMX8MQ_SYS1_PLL_800M>, ++ <&clk IMX8MQ_VPU_PLL>; ++ assigned-clock-rates = <600000000>, ++ <600000000>, ++ <800000000>, ++ <0>; + }; + + pgc_disp: power-domain@7 { +@@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 { + status = "disabled"; + }; + +- vpu: video-codec@38300000 { +- compatible = "nxp,imx8mq-vpu"; +- reg = <0x38300000 0x10000>, +- <0x38310000 0x10000>, +- <0x38320000 0x10000>; +- reg-names = "g1", "g2", "ctrl"; +- interrupts = , +- ; +- interrupt-names = "g1", "g2"; ++ vpu_g1: video-codec@38300000 { ++ compatible = "nxp,imx8mq-vpu-g1"; ++ reg = <0x38300000 0x10000>; ++ interrupts = ; ++ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; ++ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; ++ }; ++ ++ vpu_g2: video-codec@38310000 { ++ compatible = "nxp,imx8mq-vpu-g2"; ++ reg = <0x38310000 0x10000>; ++ interrupts = ; ++ clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; ++ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; ++ }; ++ ++ vpu_blk_ctrl: blk-ctrl@38320000 { ++ compatible = "fsl,imx8mq-vpu-blk-ctrl"; ++ reg = <0x38320000 0x100>; ++ power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; ++ power-domain-names = "bus", "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, +- <&clk IMX8MQ_CLK_VPU_G2_ROOT>, +- <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; +- clock-names = "g1", "g2", "bus"; +- assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, +- <&clk IMX8MQ_CLK_VPU_G2>, +- <&clk IMX8MQ_CLK_VPU_BUS>, +- <&clk IMX8MQ_VPU_PLL_BYPASS>; +- assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, +- <&clk IMX8MQ_VPU_PLL_OUT>, +- <&clk IMX8MQ_SYS1_PLL_800M>, +- <&clk IMX8MQ_VPU_PLL>; +- assigned-clock-rates = <600000000>, <600000000>, +- <800000000>, <0>; +- power-domains = <&pgc_vpu>; ++ <&clk IMX8MQ_CLK_VPU_G2_ROOT>; ++ clock-names = "g1", "g2"; ++ #power-domain-cells = <1>; + }; + + pcie0: pcie@33800000 { +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 3EC24C433EF + for ; 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+ Tue, 25 Jan 2022 09:12:42 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Adam Ford , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + Lucas Stach , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging +Date: Tue, 25 Jan 2022 11:11:25 -0600 +Message-Id: <20220125171129.472775-9-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 817 +Lines: 22 + +The vpumix power domain has a reset assigned to it, however +when used, it causes a system hang. Testing has shown that +it does not appear to be needed anywhere. + +Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node") +Signed-off-by: Adam Ford + +diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +index f77f90ed416f..0c7a72c51a31 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +@@ -707,7 +707,6 @@ pgc_vpumix: power-domain@6 { + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; +- resets = <&src IMX8MQ_RESET_VPU_RESET>; + }; + + pgc_vpu_g1: power-domain@7 { +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 4D2BCC4332F + for ; Tue, 25 Jan 2022 17:16:50 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1388214AbiAYRQg (ORCPT ); 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+ Tue, 25 Jan 2022 09:12:44 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Adam Ford , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + Lucas Stach , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm +Date: Tue, 25 Jan 2022 11:11:26 -0600 +Message-Id: <20220125171129.472775-10-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 1181 +Lines: 32 + +The i.MX8M mini appears to have a similar G1 decoder but the +post-processing isn't present, so different compatible flag is required. +Since all the other parameters are the same with imx8mq, just add +the new compatible flag to nxp,imx8mq-vpu.yaml. + +Signed-off-by: Adam Ford +Reviewed-by: Ezequiel Garcia + +diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +index 9c28d562112b..7dc13a4b1805 100644 +--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml ++++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +@@ -5,7 +5,7 @@ + $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#" + $schema: "http://devicetree.org/meta-schemas/core.yaml#" + +-title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs ++title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs + + maintainers: + - Philipp Zabel +@@ -20,6 +20,7 @@ properties: + deprecated: true + - const: nxp,imx8mq-vpu-g1 + - const: nxp,imx8mq-vpu-g2 ++ - const: nxp,imx8mm-vpu-g1 + + reg: + maxItems: 1 +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id AFC9EC433EF + for ; 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+ Tue, 25 Jan 2022 09:12:47 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Adam Ford , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + Lucas Stach , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 10/11] media: hantro: Add support for i.MX8MM Hantro-G1 +Date: Tue, 25 Jan 2022 11:11:27 -0600 +Message-Id: <20220125171129.472775-11-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 2384 +Lines: 55 + +The i.MX8MM has a Hantro G1 video decoder similar to the +imx8mq but lacks the post-processor present in the imx8mq. +Add support in the driver for it with the post-processing +removed. + +Signed-off-by: Adam Ford +Reviewed-by: Ezequiel Garcia + +diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c +index f56e8b3efada..8f020ba15194 100644 +--- a/drivers/staging/media/hantro/hantro_drv.c ++++ b/drivers/staging/media/hantro/hantro_drv.c +@@ -615,6 +615,7 @@ static const struct of_device_id of_hantro_match[] = { + { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, + #endif + #ifdef CONFIG_VIDEO_HANTRO_IMX8M ++ { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, + { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, + { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, + { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index f0bd2ffe290b..c00b46e06055 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -299,6 +299,7 @@ enum hantro_enc_fmt { + ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, + }; + ++extern const struct hantro_variant imx8mm_vpu_g1_variant; + extern const struct hantro_variant imx8mq_vpu_g1_variant; + extern const struct hantro_variant imx8mq_vpu_g2_variant; + extern const struct hantro_variant imx8mq_vpu_variant; +diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c +index 849ea7122d47..9802508bade2 100644 +--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c ++++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c +@@ -327,3 +327,15 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { + .clk_names = imx8mq_g2_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), + }; ++ ++const struct hantro_variant imx8mm_vpu_g1_variant = { ++ .dec_fmts = imx8m_vpu_dec_fmts, ++ .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), ++ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | ++ HANTRO_H264_DECODER, ++ .codec_ops = imx8mq_vpu_g1_codec_ops, ++ .irqs = imx8mq_irqs, ++ .num_irqs = ARRAY_SIZE(imx8mq_irqs), ++ .clk_names = imx8mq_g1_clk_names, ++ .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), ++}; +-- +2.32.0 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 238FFC4167B + for ; Tue, 25 Jan 2022 17:19:55 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1587276AbiAYRT3 (ORCPT ); + Tue, 25 Jan 2022 12:19:29 -0500 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46672 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1381178AbiAYRO3 (ORCPT + ); + Tue, 25 Jan 2022 12:14:29 -0500 +Received: from mail-io1-xd31.google.com (mail-io1-xd31.google.com [IPv6:2607:f8b0:4864:20::d31]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AA7DC0617A8; + Tue, 25 Jan 2022 09:12:52 -0800 (PST) +Received: by mail-io1-xd31.google.com with SMTP id h7so6547462iof.3; + Tue, 25 Jan 2022 09:12:52 -0800 (PST) +DKIM-Signature: v=1; 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+ Tue, 25 Jan 2022 09:12:51 -0800 (PST) +Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:6592:b6fe:71b1:9f4c]) + by smtp.gmail.com with ESMTPSA id m14sm8090291iov.0.2022.01.25.09.12.49 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Tue, 25 Jan 2022 09:12:50 -0800 (PST) +From: Adam Ford +To: linux-media@vger.kernel.org +Cc: aford@beaconembedded.com, cphealy@gmail.com, + Adam Ford , + Ezequiel Garcia , + Philipp Zabel , + Mauro Carvalho Chehab , + Rob Herring , + Shawn Guo , + Sascha Hauer , + Pengutronix Kernel Team , + Fabio Estevam , + NXP Linux Team , + Greg Kroah-Hartman , + Lucas Stach , + linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, + linux-staging@lists.linux.dev +Subject: [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders +Date: Tue, 25 Jan 2022 11:11:28 -0600 +Message-Id: <20220125171129.472775-12-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +Status: O +Content-Length: 1673 +Lines: 50 + +There are two decoders on the i.MX8M Mini controlled by the +vpu-blk-ctrl. The G1 supports H264 and VP8 while the +G2 support HEVC and VP9. + +Signed-off-by: Adam Ford +Reviewed-by: Ezequiel Garcia + +diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +index 0c7a72c51a31..98aec4421713 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +@@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 { + power-domains = <&pgc_gpu>; + }; + ++ vpu_g1: video-codec@38300000 { ++ compatible = "nxp,imx8mm-vpu-g1"; ++ reg = <0x38300000 0x10000>; ++ interrupts = ; ++ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; ++ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; ++ }; ++ ++ vpu_g2: video-codec@38310000 { ++ compatible = "nxp,imx8mq-vpu-g2"; ++ reg = <0x38310000 0x10000>; ++ interrupts = ; ++ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; ++ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; ++ }; ++ + vpu_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; +@@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 { + <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "g1", "g2", "h1"; ++ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, ++ <&clk IMX8MM_CLK_VPU_G2>; ++ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, ++ <&clk IMX8MM_VPU_PLL_OUT>; ++ assigned-clock-rates = <600000000>, ++ <600000000>; + #power-domain-cells = <1>; + }; + +-- +2.32.0 + + diff --git a/projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch b/projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch new file mode 100644 index 0000000000..8466cd8f22 --- /dev/null +++ b/projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch @@ -0,0 +1,229 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Tue, 16 Nov 2021 15:38:32 +0100 +Subject: [PATCH] hantro: postproc: Introduce struct hantro_postproc_ops + +Turns out the post-processor block on the G2 core is substantially +different from the one on the G1 core. Introduce hantro_postproc_ops +with .enable and .disable methods, which will allow to support +the G2 post-processor cleanly. + +Signed-off-by: Ezequiel Garcia +Signed-off-by: Andrzej Pietrasiewicz +Reviewed-by: Benjamin Gaignard +Signed-off-by: Hans Verkuil +--- + drivers/staging/media/hantro/hantro.h | 5 +-- + drivers/staging/media/hantro/hantro_hw.h | 13 ++++++- + .../staging/media/hantro/hantro_postproc.c | 35 +++++++++++++------ + drivers/staging/media/hantro/imx8m_vpu_hw.c | 2 +- + .../staging/media/hantro/rockchip_vpu_hw.c | 6 ++-- + .../staging/media/hantro/sama5d4_vdec_hw.c | 2 +- + 6 files changed, 45 insertions(+), 18 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h +index c2e2dca38628..c2e01959dc00 100644 +--- a/drivers/staging/media/hantro/hantro.h ++++ b/drivers/staging/media/hantro/hantro.h +@@ -28,6 +28,7 @@ + + struct hantro_ctx; + struct hantro_codec_ops; ++struct hantro_postproc_ops; + + #define HANTRO_JPEG_ENCODER BIT(0) + #define HANTRO_ENCODERS 0x0000ffff +@@ -59,6 +60,7 @@ struct hantro_irq { + * @num_dec_fmts: Number of decoder formats. + * @postproc_fmts: Post-processor formats. + * @num_postproc_fmts: Number of post-processor formats. ++ * @postproc_ops: Post-processor ops. + * @codec: Supported codecs + * @codec_ops: Codec ops. + * @init: Initialize hardware, optional. +@@ -69,7 +71,6 @@ struct hantro_irq { + * @num_clocks: number of clocks in the array + * @reg_names: array of register range names + * @num_regs: number of register range names in the array +- * @postproc_regs: &struct hantro_postproc_regs pointer + */ + struct hantro_variant { + unsigned int enc_offset; +@@ -80,6 +81,7 @@ struct hantro_variant { + unsigned int num_dec_fmts; + const struct hantro_fmt *postproc_fmts; + unsigned int num_postproc_fmts; ++ const struct hantro_postproc_ops *postproc_ops; + unsigned int codec; + const struct hantro_codec_ops *codec_ops; + int (*init)(struct hantro_dev *vpu); +@@ -90,7 +92,6 @@ struct hantro_variant { + int num_clocks; + const char * const *reg_names; + int num_regs; +- const struct hantro_postproc_regs *postproc_regs; + }; + + /** +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 267a6d33a47b..2f85430682d8 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -174,6 +174,17 @@ struct hantro_postproc_ctx { + struct hantro_aux_buf dec_q[VB2_MAX_FRAME]; + }; + ++/** ++ * struct hantro_postproc_ops - post-processor operations ++ * ++ * @enable: Enable the post-processor block. Optional. ++ * @disable: Disable the post-processor block. Optional. ++ */ ++struct hantro_postproc_ops { ++ void (*enable)(struct hantro_ctx *ctx); ++ void (*disable)(struct hantro_ctx *ctx); ++}; ++ + /** + * struct hantro_codec_ops - codec mode specific operations + * +@@ -221,7 +232,7 @@ extern const struct hantro_variant rk3328_vpu_variant; + extern const struct hantro_variant rk3399_vpu_variant; + extern const struct hantro_variant sama5d4_vdec_variant; + +-extern const struct hantro_postproc_regs hantro_g1_postproc_regs; ++extern const struct hantro_postproc_ops hantro_g1_postproc_ops; + + extern const u32 hantro_vp8_dec_mc_filter[8][6]; + +diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c +index 07842152003f..882fb8bc5ddd 100644 +--- a/drivers/staging/media/hantro/hantro_postproc.c ++++ b/drivers/staging/media/hantro/hantro_postproc.c +@@ -15,14 +15,14 @@ + #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ + { \ + hantro_reg_write(vpu, \ +- &(vpu)->variant->postproc_regs->reg_name, \ ++ &hantro_g1_postproc_regs.reg_name, \ + val); \ + } + + #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ + { \ + hantro_reg_write_s(vpu, \ +- &(vpu)->variant->postproc_regs->reg_name, \ ++ &hantro_g1_postproc_regs.reg_name, \ + val); \ + } + +@@ -64,16 +64,13 @@ bool hantro_needs_postproc(const struct hantro_ctx *ctx, + return fmt->fourcc != V4L2_PIX_FMT_NV12; + } + +-void hantro_postproc_enable(struct hantro_ctx *ctx) ++static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; + struct vb2_v4l2_buffer *dst_buf; + u32 src_pp_fmt, dst_pp_fmt; + dma_addr_t dst_dma; + +- if (!vpu->variant->postproc_regs) +- return; +- + /* Turn on pipeline mode. Must be done first. */ + HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1); + +@@ -154,12 +151,30 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) + return 0; + } + +-void hantro_postproc_disable(struct hantro_ctx *ctx) ++static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; + +- if (!vpu->variant->postproc_regs) +- return; +- + HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); + } ++ ++void hantro_postproc_disable(struct hantro_ctx *ctx) ++{ ++ struct hantro_dev *vpu = ctx->dev; ++ ++ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable) ++ vpu->variant->postproc_ops->disable(ctx); ++} ++ ++void hantro_postproc_enable(struct hantro_ctx *ctx) ++{ ++ struct hantro_dev *vpu = ctx->dev; ++ ++ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable) ++ vpu->variant->postproc_ops->enable(ctx); ++} ++ ++const struct hantro_postproc_ops hantro_g1_postproc_ops = { ++ .enable = hantro_postproc_g1_enable, ++ .disable = hantro_postproc_g1_disable, ++}; +diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c +index ea919bfb9891..22fa7d2f3b64 100644 +--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c ++++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c +@@ -262,7 +262,7 @@ const struct hantro_variant imx8mq_vpu_variant = { + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), + .postproc_fmts = imx8m_vpu_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), +- .postproc_regs = &hantro_g1_postproc_regs, ++ .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = imx8mq_vpu_codec_ops, +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index d4f52957cc53..6c1ad5534ce5 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -460,7 +460,7 @@ const struct hantro_variant rk3036_vpu_variant = { + .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), + .postproc_fmts = rockchip_vpu1_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), +- .postproc_regs = &hantro_g1_postproc_regs, ++ .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = rk3036_vpu_codec_ops, +@@ -485,7 +485,7 @@ const struct hantro_variant rk3066_vpu_variant = { + .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), + .postproc_fmts = rockchip_vpu1_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), +- .postproc_regs = &hantro_g1_postproc_regs, ++ .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | + HANTRO_VP8_DECODER | HANTRO_H264_DECODER, + .codec_ops = rk3066_vpu_codec_ops, +@@ -505,7 +505,7 @@ const struct hantro_variant rk3288_vpu_variant = { + .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts), + .postproc_fmts = rockchip_vpu1_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), +- .postproc_regs = &hantro_g1_postproc_regs, ++ .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | + HANTRO_VP8_DECODER | HANTRO_H264_DECODER, + .codec_ops = rk3288_vpu_codec_ops, +diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c +index 9c3b8cd0b239..f3fecc7248c4 100644 +--- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c ++++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c +@@ -100,7 +100,7 @@ const struct hantro_variant sama5d4_vdec_variant = { + .num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts), + .postproc_fmts = sama5d4_vdec_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts), +- .postproc_regs = &hantro_g1_postproc_regs, ++ .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = sama5d4_vdec_codec_ops,