From 079b6a3a581063ac3de8157021727302e79997a2 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 25 Aug 2019 15:43:08 +0200 Subject: [PATCH 1/5] Allwinner: Sort upstreamed patches --- .../H6/patches/linux/05-sound-hack.patch | 41 - .../devices/H6/patches/linux/07-opi3.patch | 339 -------- .../H6/patches/linux/10-beelink-gs1.patch | 28 - .../H6/patches/linux/13-Tanix-TX6.patch | 176 ++-- .../linux/0001-hdmi-sound-improvements.patch | 80 -- .../linux/0003-backport-from-5.4.patch | 751 +++++++++++++++++- .../patches/linux/0011-cedrus-h264-4k.patch | 10 - 7 files changed, 807 insertions(+), 618 deletions(-) diff --git a/projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch b/projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch index 242bf577a5..754f87cf50 100644 --- a/projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch +++ b/projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch @@ -6,7 +6,6 @@ Subject: [PATCH] AW H6 I2S WIP Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 31 ++++++++++++++++++++ - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++--- sound/soc/sunxi/sun4i-i2s.c | 12 ++++---- 3 files changed, 41 insertions(+), 10 deletions(-) @@ -66,46 +65,6 @@ index 62a0eae77639..f1c53aec6523 100644 compatible = "allwinner,sun50i-h6-dw-hdmi"; reg = <0x06000000 0x10000>; reg-io-width = <1>; -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index 139e8389615c..bdb33266a3de 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -504,7 +504,7 @@ static struct ccu_div i2s3_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s3", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - -@@ -517,7 +517,7 @@ static struct ccu_div i2s0_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s0", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - -@@ -530,7 +530,7 @@ static struct ccu_div i2s1_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s1", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - -@@ -543,7 +543,7 @@ static struct ccu_div i2s2_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s2", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d5ec1a20499d..f286b8bfcfb3 100644 --- a/sound/soc/sunxi/sun4i-i2s.c diff --git a/projects/Allwinner/devices/H6/patches/linux/07-opi3.patch b/projects/Allwinner/devices/H6/patches/linux/07-opi3.patch index f6f80226ef..370dfdb2d5 100644 --- a/projects/Allwinner/devices/H6/patches/linux/07-opi3.patch +++ b/projects/Allwinner/devices/H6/patches/linux/07-opi3.patch @@ -1,232 +1,3 @@ -From 9ea7a168e5cab7ad820439f1c595360e8c2415db Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Tue, 19 Feb 2019 21:54:24 +0100 -Subject: [PATCH 01/34] rtc: sun6i: Add support for H6 RTC - -It is mostly the same as on H5 and H3, but with slight differences -in features that are not yet supported by this driver, so we need -a different compatible, but we can re-use sun8i_h3_rtc_clk_init. - -Some differences are already stated in the comments in existing code. -One other difference is that H6 has extra bit in LOSC_CTRL_REG, called -EXT_LOSC_EN to enable/disable external low speed crystal oscillator. - -It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether -external low speed oscillator is working correctly. - -Signed-off-by: Ondrej Jirman ---- - drivers/rtc/rtc-sun6i.c | 47 +++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 45 insertions(+), 2 deletions(-) - -diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c -index 11f56de521791..b0fbaa1837dd5 100644 ---- a/drivers/rtc/rtc-sun6i.c -+++ b/drivers/rtc/rtc-sun6i.c -@@ -41,11 +41,15 @@ - /* Control register */ - #define SUN6I_LOSC_CTRL 0x0000 - #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) -+#define SUN6I_LOSC_CTRL_AUTO_SWT_EN BIT(14) -+#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) - #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) - #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) - #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) -+#define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) - #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) - #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) -+#define SUN6I_LOSC_CTRL_EXT_OSC_GSM 0x08 - - #define SUN6I_LOSC_CLK_PRESCAL 0x0008 - -@@ -137,6 +141,8 @@ struct sun6i_rtc_clk_data { - unsigned int has_prescaler : 1; - unsigned int has_out_clk : 1; - unsigned int export_iosc : 1; -+ unsigned int has_losc_en : 1; -+ unsigned int has_auto_swt : 1; - }; - - struct sun6i_rtc_dev { -@@ -199,6 +205,10 @@ static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) - val &= ~SUN6I_LOSC_CTRL_EXT_OSC; - val |= SUN6I_LOSC_CTRL_KEY; - val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; -+ if (rtc->data->has_losc_en) { -+ val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; -+ val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; -+ } - writel(val, rtc->base + SUN6I_LOSC_CTRL); - spin_unlock_irqrestore(&rtc->lock, flags); - -@@ -224,6 +234,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, - const char *iosc_name = "rtc-int-osc"; - const char *clkout_name = "osc32k-out"; - const char *parents[2]; -+ u32 reg; - - rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); - if (!rtc) -@@ -244,9 +255,23 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, - goto err; - } - -+ reg = SUN6I_LOSC_CTRL_KEY; -+ if (rtc->data->has_auto_swt) { -+ /* Bypass auto-switch to int osc, on ext losc failure */ -+ reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; -+ writel(reg, rtc->base + SUN6I_LOSC_CTRL); -+ } -+ - /* Switch to the external, more precise, oscillator */ -- writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC, -- rtc->base + SUN6I_LOSC_CTRL); -+ reg |= SUN6I_LOSC_CTRL_EXT_OSC; -+ if (rtc->data->has_losc_en) -+ reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; -+ writel(reg, rtc->base + SUN6I_LOSC_CTRL); -+ -+ /* Set GSM with some delay, after switching to ext losc. */ -+ udelay(10); -+ reg |= SUN6I_LOSC_CTRL_EXT_OSC_GSM; -+ writel(reg, rtc->base + SUN6I_LOSC_CTRL); - - /* Yes, I know, this is ugly. */ - sun6i_rtc = rtc; -@@ -354,6 +379,23 @@ CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", - CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", - sun8i_h3_rtc_clk_init); - -+static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { -+ .rc_osc_rate = 16000000, -+ .fixed_prescaler = 32, -+ .has_prescaler = 1, -+ .has_out_clk = 1, -+ .export_iosc = 1, -+ .has_losc_en = 1, -+ .has_auto_swt = 1, -+}; -+ -+static void __init sun50i_h6_rtc_clk_init(struct device_node *node) -+{ -+ sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); -+} -+CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", -+ sun50i_h6_rtc_clk_init); -+ - static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { - .rc_osc_rate = 32000, - .has_out_clk = 1, -@@ -683,6 +725,7 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = { - { .compatible = "allwinner,sun8i-h3-rtc" }, - { .compatible = "allwinner,sun8i-v3-rtc" }, - { .compatible = "allwinner,sun50i-h5-rtc" }, -+ { .compatible = "allwinner,sun50i-h6-rtc" }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); - -From 80472652eff72ba5198dc5d678612fb91e411ed1 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 12 Apr 2019 13:32:05 +0200 -Subject: [PATCH 02/34] arm64: dts: sun50i-h6: Add support for RTC and fix the - clock tree - -This patch adds RTC node and fixes the clock properties and nodes -to reflect the real clock tree. - -The device nodes for the internal oscillator and osc32k are removed, -as these clocks are now provided by the RTC device. Clock references -are fixed accordingly, too. - -Signed-off-by: Ondrej Jirman ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++++++--------- - 1 file changed, 16 insertions(+), 14 deletions(-) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index c9e861a50a633..ae7977f3f054c 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -56,14 +56,6 @@ - status = "disabled"; - }; - -- iosc: internal-osc-clk { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <16000000>; -- clock-accuracy = <300000000>; -- clock-output-names = "iosc"; -- }; -- - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; -@@ -71,11 +63,11 @@ - clock-output-names = "osc24M"; - }; - -- osc32k: osc32k_clk { -+ ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; -- clock-output-names = "osc32k"; -+ clock-output-names = "ext_osc32k"; - }; - - psci { -@@ -186,7 +178,7 @@ - ccu: clock@3001000 { - compatible = "allwinner,sun50i-h6-ccu"; - reg = <0x03001000 0x1000>; -- clocks = <&osc24M>, <&osc32k>, <&iosc>; -+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; -@@ -199,7 +191,7 @@ - , - , - ; -- clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; -+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; -@@ -583,10 +575,20 @@ - }; - }; - -+ rtc: rtc@7000000 { -+ compatible = "allwinner,sun50i-h6-rtc"; -+ reg = <0x07000000 0x400>; -+ interrupts = , -+ ; -+ clock-output-names = "osc32k", "osc32k-out", "iosc"; -+ clocks = <&ext_osc32k>; -+ #clock-cells = <1>; -+ }; -+ - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-h6-r-ccu"; - reg = <0x07010000 0x400>; -- clocks = <&osc24M>, <&osc32k>, <&iosc>, -+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; -@@ -607,7 +609,7 @@ - reg = <0x07022000 0x400>; - interrupts = , - ; -- clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; -+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - From ce48f9b105340aa4b66f30266c7d9cd4a71a7ca3 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 24 Jun 2019 12:23:04 +0200 @@ -367,116 +138,6 @@ index 17d4969901086..6d6b1f66796d9 100644 vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -From 200cf18794214700f023440021cb7fd40dcc0f01 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Tue, 9 Apr 2019 00:16:35 +0200 -Subject: [PATCH 19/34] arm64: dts: allwinner: orange-pi-3: Enable WiFi - -Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is called -bcm43356 and can be used with the brcmfmac driver. The module is powered by -the two always on regulators (not AXP805). - -WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be -configured so that it sets up an 1.8V input bias on this port. This is done -by the pio driver by reading the vcc-pg-supply voltage. - -You'll need a fw_bcm43456c5_ag.bin firmware file and nvram.txt -configuration that can be found in the Xulongs's repository for H6: - -https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 - -Mainline brcmfmac driver expects the firmware and nvram at the following -paths relative to the firmware directory: - - brcm/brcmfmac43456-sdio.bin - brcm/brcmfmac43456-sdio.txt - -Signed-off-by: Ondrej Jirman ---- - .../dts/allwinner/sun50i-h6-orangepi-3.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index 58a6635c909e3..f795362f5b77e 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -67,6 +67,26 @@ - regulator-always-on; - }; - -+ reg_vcc33_wifi: vcc33-wifi { -+ /* Always on 3.3V regulator for WiFi and BT */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc33-wifi"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_vcc5v>; -+ }; -+ -+ reg_vcc_wifi_io: vcc-wifi-io { -+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-wifi-io"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ vin-supply = <®_vcc33_wifi>; -+ }; -+ - /* - * The board uses 2.5V RGMII signalling. Power sequence to enable - * the phy is to enable GMAC-2V5 and GMAC-3V3 (aldo2) power rails -@@ -87,6 +107,14 @@ - */ - vin-supply = <®_aldo2>; /* GMAC-3V3 */ - }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; -+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ -+ post-power-on-delay-ms = <200>; -+ }; - }; - - &cpu0 { -@@ -144,6 +172,25 @@ - status = "okay"; - }; - -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_vcc33_wifi>; -+ vqmmc-supply = <®_vcc_wifi_io>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ brcm: sdio-wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&r_pio>; -+ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &ohci0 { - status = "okay"; - }; -@@ -155,6 +202,7 @@ - &pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; -+ vcc-pg-supply = <®_vcc_wifi_io>; - }; - - &r_i2c { - From 5fd2d3bd956cc875d07433454f18dcbc14e120d5 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 26 Mar 2019 15:14:14 +0100 diff --git a/projects/Allwinner/devices/H6/patches/linux/10-beelink-gs1.patch b/projects/Allwinner/devices/H6/patches/linux/10-beelink-gs1.patch index 7caa8d9fd6..683dc3f570 100644 --- a/projects/Allwinner/devices/H6/patches/linux/10-beelink-gs1.patch +++ b/projects/Allwinner/devices/H6/patches/linux/10-beelink-gs1.patch @@ -37,31 +37,3 @@ index 0dc33c90dd60..ef595e6a0cd6 100644 +}; -- 2.20.1 - -From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= -Subject: [PATCH] arm64: dts: allwinner: Enable DDC regulator for Beelink GS1 -Date: Mon, 12 Aug 2019 12:23:55 +0200 -Content-Type: text/plain; charset="utf-8" - -Beelink GS1 has a DDC I2C bus voltage shifter. This is actually missing -and video is limited to 1024x768 due to missing EDID information. - -Add the DDC regulator in the device-tree. - -Signed-off-by: Clément Péron ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index 680dc29cb089..67d7f269c5da 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -25,6 +25,7 @@ - connector { - compatible = "hdmi-connector"; - type = "a"; -+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - - port { - hdmi_con_in: endpoint { diff --git a/projects/Allwinner/devices/H6/patches/linux/13-Tanix-TX6.patch b/projects/Allwinner/devices/H6/patches/linux/13-Tanix-TX6.patch index b5ac1bf8c6..c9fb93fea6 100644 --- a/projects/Allwinner/devices/H6/patches/linux/13-Tanix-TX6.patch +++ b/projects/Allwinner/devices/H6/patches/linux/13-Tanix-TX6.patch @@ -1,83 +1,38 @@ -From 13300ba386795eceeaf47fc199d5e8683dcd2ff8 Mon Sep 17 00:00:00 2001 +From cbf6129cdb69f006f66e22b854d5d544c940fd49 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec -Date: Mon, 24 Jun 2019 12:17:58 +0200 -Subject: [PATCH 1/2] Tanix TX6 DT +Date: Sat, 24 Aug 2019 01:03:05 +0200 +Subject: [PATCH] Tanix TX6 improvements Signed-off-by: Jernej Skrabec --- - arch/arm64/boot/dts/allwinner/Makefile | 1 + - .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 133 ++++++++++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 7 + - 3 files changed, 141 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts + .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 44 +++++++++++++++++++ + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 7 +++ + 2 files changed, 51 insertions(+) -diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile -index f6db0611cb85..395fe76f6819 100644 ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -25,3 +25,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -new file mode 100644 -index 000000000000..c90af0b29f28 ---- /dev/null +index 7e7cb10e3d96..3de430b631f2 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -0,0 +1,136 @@ -+// SPDX-License-Identifier: (GPL-2.0+ or MIT) -+/* -+ * Copyright (c) 2019 Jernej Skrabec -+ */ -+ -+/dts-v1/; -+ -+#include "sun50i-h6.dtsi" -+ -+#include -+ -+/ { -+ model = "Tanix TX6"; -+ compatible = "tanix,tanix-tx6", "allwinner,sun50i-h6"; -+ -+ aliases { +@@ -14,6 +14,7 @@ + compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; + + aliases { + ethernet0 = &emac; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ + serial0 = &uart0; + }; + +@@ -41,10 +42,26 @@ + }; + }; + +&ac200_pwm_clk { + status = "okay"; +}; + -+&de { -+ status = "okay"; -+}; -+ + &de { + status = "okay"; + }; + +&dwc3 { + status = "okay"; +}; @@ -90,24 +45,13 @@ index 000000000000..c90af0b29f28 + status = "okay"; +}; + -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ + &ehci0 { + status = "okay"; + }; +@@ -63,6 +80,17 @@ + }; + }; + +&i2c3 { + status = "okay"; +}; @@ -119,51 +63,45 @@ index 000000000000..c90af0b29f28 + }; +}; + -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins>; + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; +@@ -72,6 +100,14 @@ + status = "okay"; + }; + ++&mmc2 { + vmmc-supply = <®_vcc3v3>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&ohci3 { ++ non-removable; ++ cap-mmc-hw-reset; ++ bus-width = <8>; + status = "okay"; +}; + + &ohci0 { + status = "okay"; + }; +@@ -80,6 +116,10 @@ + status = "okay"; + }; + +&pwm { + status = "okay"; +}; + -+&r_ir { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_ph_pins>; -+ status = "okay"; -+}; -+ -+&usb2otg { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb2phy { -+ status = "okay"; -+}; + &r_ir { + status = "okay"; + }; +@@ -98,3 +138,7 @@ + &usb2phy { + status = "okay"; + }; + +&usb3phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 7628a7c83096..305e093c910f 100644 +index 67b732e34091..e436fc78ac71 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -251,6 +251,13 @@ @@ -181,5 +119,5 @@ index 7628a7c83096..305e093c910f 100644 pins = "PH8", "PH9", "PH10"; function = "hdmi"; -- -2.22.0 +2.23.0 diff --git a/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch index 9fa34d581c..1cfae37641 100644 --- a/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch +++ b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch @@ -518,86 +518,6 @@ index 5cbb71a..a397505 100644 -- 2.14.1 - -From dcdde5c3641e7e92b8ead0624d548f918e126b2f Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Mon, 2 Jul 2018 12:21:55 +0200 -Subject: [PATCH 09/15] drm: bridge: dw-hdmi: Use AUTO CTS setup mode when - non-AHB audio - -Signed-off-by: Neil Armstrong ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 41 ++++++++++++++++++++----------- - 1 file changed, 26 insertions(+), 15 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index a7040c1..3f46522 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -438,8 +438,12 @@ static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, - /* nshift factor = 0 */ - hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); - -- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | -- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); -+ /* Use Auto CTS mode with CTS is unknown */ -+ if (cts) -+ hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | -+ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); -+ else -+ hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); - hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); - hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); - -@@ -509,24 +513,31 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, - { - unsigned long ftdms = pixel_clk; - unsigned int n, cts; -+ u8 config3; - u64 tmp; - - n = hdmi_compute_n(sample_rate, pixel_clk); - -- /* -- * Compute the CTS value from the N value. Note that CTS and N -- * can be up to 20 bits in total, so we need 64-bit math. Also -- * note that our TDMS clock is not fully accurate; it is accurate -- * to kHz. This can introduce an unnecessary remainder in the -- * calculation below, so we don't try to warn about that. -- */ -- tmp = (u64)ftdms * n; -- do_div(tmp, 128 * sample_rate); -- cts = tmp; -+ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); - -- dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", -- __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, -- n, cts); -+ if (config3 & HDMI_CONFIG3_AHBAUDDMA) { -+ /* -+ * Compute the CTS value from the N value. Note that CTS and N -+ * can be up to 20 bits in total, so we need 64-bit math. Also -+ * note that our TDMS clock is not fully accurate; it is -+ * accurate to kHz. This can introduce an unnecessary remainder -+ * in the calculation below, so we don't try to warn about that. -+ */ -+ tmp = (u64)ftdms * n; -+ do_div(tmp, 128 * sample_rate); -+ cts = tmp; -+ -+ dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", -+ __func__, sample_rate, -+ ftdms / 1000000, (ftdms / 1000) % 1000, -+ n, cts); -+ } else -+ cts = 0; - - spin_lock_irq(&hdmi->audio_lock); - hdmi->audio_n = n; --- -2.14.1 - - From e7b2f400507263f12872db06f4cd69bc80f62c2f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Mar 2018 22:17:06 +0200 diff --git a/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch b/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch index 2bfe873bb9..3298ff32cf 100644 --- a/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch +++ b/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch @@ -443,7 +443,7 @@ index c951568994a1..29b92ce521b7 100644 #define AXP803_DCDC6_1120mV_END \ (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS) #define AXP803_DCDC6_NUM_VOLTAGES 72 --- +-- 2.22.0 From: Ondrej Jirman @@ -1222,3 +1222,752 @@ index 189834518391..30102daf83cc 100644 -- 2.22.0 +From fdbdcc83ffd7d00265a531e71f1d166566c09d66 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Wed, 12 Jun 2019 10:51:47 +0200 +Subject: [PATCH] drm/bridge: dw-hdmi: Use automatic CTS generation mode when + using non-AHB audio + +When using an I2S source using a different clock source (usually the I2S +audio HW uses dedicated PLLs, different from the HDMI PHY PLL), fixed +CTS values will cause some frequent audio drop-out and glitches as +reported on Amlogic, Allwinner and Rockchip SoCs setups. + +Setting the CTS in automatic mode will let the HDMI controller generate +automatically the CTS value to match the input audio clock. + +The DesignWare DW-HDMI User Guide explains: + For Automatic CTS generation + Write "0" on the bit field "CTS_manual", Register 0x3205: AUD_CTS3 + +The DesignWare DW-HDMI Databook explains : + If "CTS_manual" bit equals 0b this registers contains "audCTS[19:0]" + generated by the Cycle time counter according to specified timing. + +Cc: Jernej Skrabec +Cc: Maxime Ripard +Cc: Jonas Karlman +Cc: Heiko Stuebner +Cc: Jerome Brunet +Signed-off-by: Neil Armstrong +Tested-by: Jernej Skrabec +Reviewed-by: Jernej Skrabec +Tested-by: Douglas Anderson +Signed-off-by: Andrzej Hajda +Link: https://patchwork.freedesktop.org/patch/msgid/20190612085147.26971-1-narmstrong@baylibre.com +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 45 +++++++++++++++-------- + 1 file changed, 30 insertions(+), 15 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index c6490949d9db..218a7b2308f7 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -508,8 +508,14 @@ static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, + /* nshift factor = 0 */ + hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); + +- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | +- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); ++ /* Use automatic CTS generation mode when CTS is not set */ ++ if (cts) ++ hdmi_writeb(hdmi, ((cts >> 16) & ++ HDMI_AUD_CTS3_AUDCTS19_16_MASK) | ++ HDMI_AUD_CTS3_CTS_MANUAL, ++ HDMI_AUD_CTS3); ++ else ++ hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); + hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); + hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); + +@@ -579,24 +585,33 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, + { + unsigned long ftdms = pixel_clk; + unsigned int n, cts; ++ u8 config3; + u64 tmp; + + n = hdmi_compute_n(sample_rate, pixel_clk); + +- /* +- * Compute the CTS value from the N value. Note that CTS and N +- * can be up to 20 bits in total, so we need 64-bit math. Also +- * note that our TDMS clock is not fully accurate; it is accurate +- * to kHz. This can introduce an unnecessary remainder in the +- * calculation below, so we don't try to warn about that. +- */ +- tmp = (u64)ftdms * n; +- do_div(tmp, 128 * sample_rate); +- cts = tmp; ++ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); + +- dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", +- __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, +- n, cts); ++ /* Only compute CTS when using internal AHB audio */ ++ if (config3 & HDMI_CONFIG3_AHBAUDDMA) { ++ /* ++ * Compute the CTS value from the N value. Note that CTS and N ++ * can be up to 20 bits in total, so we need 64-bit math. Also ++ * note that our TDMS clock is not fully accurate; it is ++ * accurate to kHz. This can introduce an unnecessary remainder ++ * in the calculation below, so we don't try to warn about that. ++ */ ++ tmp = (u64)ftdms * n; ++ do_div(tmp, 128 * sample_rate); ++ cts = tmp; ++ ++ dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", ++ __func__, sample_rate, ++ ftdms / 1000000, (ftdms / 1000) % 1000, ++ n, cts); ++ } else { ++ cts = 0; ++ } + + spin_lock_irq(&hdmi->audio_lock); + hdmi->audio_n = n; +-- +2.23.0 + +From 65818ad0815f3a2ba6a41327cce8b600ee04be32 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Wed, 14 Aug 2019 08:08:48 +0200 +Subject: [PATCH] clk: sunxi-ng: h6: Allow I2S to change parent rate + +I2S doesn't work if parent rate couldn't be change. Difference between +wanted and actual rate is too big. + +Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Marcus Cooper +Signed-off-by: Chen-Yu Tsai +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index aebef4af9861..d89353a3cdec 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -505,7 +505,7 @@ static struct ccu_div i2s3_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s3", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +@@ -518,7 +518,7 @@ static struct ccu_div i2s0_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s0", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +@@ -531,7 +531,7 @@ static struct ccu_div i2s1_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s1", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +@@ -544,7 +544,7 @@ static struct ccu_div i2s2_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s2", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +-- +2.23.0 + +From f46f408c152ac925e56c0f38138ae49ba16bbc23 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Mon, 12 Aug 2019 12:23:55 +0200 +Subject: [PATCH] arm64: dts: allwinner: Enable DDC regulator for Beelink GS1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Beelink GS1 has a DDC I2C bus voltage shifter. This is actually missing +and video is limited to 1024x768 due to missing EDID information. + +Add the DDC regulator in the device-tree. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +index 675c602b0e33..1d05d570142f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +@@ -25,6 +25,7 @@ + connector { + compatible = "hdmi-connector"; + type = "a"; ++ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + + port { + hdmi_con_in: endpoint { +-- +2.23.0 + +From d4cbdbc0f88bc4aa3643063f391559868886d315 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 20 Aug 2019 17:19:33 +0200 +Subject: [PATCH] rtc: sun6i: Add support for H6 RTC + +RTC on H6 is mostly the same as on H5 and H3. It has slight differences +mostly in features that are not yet supported by this driver. + +Some differences are already stated in the comments in existing code. +One other difference is that H6 has extra bit in LOSC_CTRL_REG, called +EXT_LOSC_EN to enable/disable external low speed crystal oscillator. + +It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether +external low speed oscillator is working correctly. + +This patch adds support for enabling LOSC when necessary: + +- during reparenting +- when probing the clock + +H6 also has capacbility to automatically reparent RTC clock from +external crystal oscillator, to internal RC oscillator, if external +oscillator fails. This is enabled by default. Disable it during +probe. + +Signed-off-by: Ondrej Jirman +Reviewed-by: Chen-Yu Tsai +Link: https://lore.kernel.org/r/20190820151934.3860-3-megous@megous.com +Signed-off-by: Alexandre Belloni +--- + drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 38 insertions(+), 2 deletions(-) + +diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c +index dbd676db431e..956c0846201f 100644 +--- a/drivers/rtc/rtc-sun6i.c ++++ b/drivers/rtc/rtc-sun6i.c +@@ -32,9 +32,11 @@ + /* Control register */ + #define SUN6I_LOSC_CTRL 0x0000 + #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) ++#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) + #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) + #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) + #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) ++#define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) + #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) + #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) + +@@ -128,6 +130,8 @@ struct sun6i_rtc_clk_data { + unsigned int has_prescaler : 1; + unsigned int has_out_clk : 1; + unsigned int export_iosc : 1; ++ unsigned int has_losc_en : 1; ++ unsigned int has_auto_swt : 1; + }; + + struct sun6i_rtc_dev { +@@ -190,6 +194,10 @@ static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) + val &= ~SUN6I_LOSC_CTRL_EXT_OSC; + val |= SUN6I_LOSC_CTRL_KEY; + val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; ++ if (rtc->data->has_losc_en) { ++ val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; ++ val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; ++ } + writel(val, rtc->base + SUN6I_LOSC_CTRL); + spin_unlock_irqrestore(&rtc->lock, flags); + +@@ -215,6 +223,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, + const char *iosc_name = "rtc-int-osc"; + const char *clkout_name = "osc32k-out"; + const char *parents[2]; ++ u32 reg; + + rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); + if (!rtc) +@@ -235,9 +244,18 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, + goto err; + } + ++ reg = SUN6I_LOSC_CTRL_KEY; ++ if (rtc->data->has_auto_swt) { ++ /* Bypass auto-switch to int osc, on ext losc failure */ ++ reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; ++ writel(reg, rtc->base + SUN6I_LOSC_CTRL); ++ } ++ + /* Switch to the external, more precise, oscillator */ +- writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC, +- rtc->base + SUN6I_LOSC_CTRL); ++ reg |= SUN6I_LOSC_CTRL_EXT_OSC; ++ if (rtc->data->has_losc_en) ++ reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; ++ writel(reg, rtc->base + SUN6I_LOSC_CTRL); + + /* Yes, I know, this is ugly. */ + sun6i_rtc = rtc; +@@ -345,6 +363,23 @@ CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", + CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", + sun8i_h3_rtc_clk_init); + ++static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { ++ .rc_osc_rate = 16000000, ++ .fixed_prescaler = 32, ++ .has_prescaler = 1, ++ .has_out_clk = 1, ++ .export_iosc = 1, ++ .has_losc_en = 1, ++ .has_auto_swt = 1, ++}; ++ ++static void __init sun50i_h6_rtc_clk_init(struct device_node *node) ++{ ++ sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); ++} ++CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", ++ sun50i_h6_rtc_clk_init); ++ + static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { + .rc_osc_rate = 32000, + .has_out_clk = 1, +@@ -673,6 +708,7 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = { + { .compatible = "allwinner,sun8i-r40-rtc" }, + { .compatible = "allwinner,sun8i-v3-rtc" }, + { .compatible = "allwinner,sun50i-h5-rtc" }, ++ { .compatible = "allwinner,sun50i-h6-rtc" }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); +-- +2.23.0 + +From 4cdc12a3ef424361f81bb30a34a3148b03df640c Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 20 Aug 2019 17:19:34 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Add support for RTC and fix the + clock tree + +This patch adds RTC node and fixes the clock properties and nodes +to reflect the real clock tree. + +The device nodes for the internal oscillator and osc32k are removed, +as these clocks are now provided by the RTC device. Clock references +are fixed accordingly, too. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++++++--------- + 1 file changed, 16 insertions(+), 14 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 67b732e34091..67f920e0fc33 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -56,14 +56,6 @@ + status = "disabled"; + }; + +- iosc: internal-osc-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16000000>; +- clock-accuracy = <300000000>; +- clock-output-names = "iosc"; +- }; +- + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; +@@ -71,11 +63,11 @@ + clock-output-names = "osc24M"; + }; + +- osc32k: osc32k_clk { ++ ext_osc32k: ext_osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; +- clock-output-names = "osc32k"; ++ clock-output-names = "ext_osc32k"; + }; + + psci { +@@ -197,7 +189,7 @@ + ccu: clock@3001000 { + compatible = "allwinner,sun50i-h6-ccu"; + reg = <0x03001000 0x1000>; +- clocks = <&osc24M>, <&osc32k>, <&iosc>; ++ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -236,7 +228,7 @@ + , + , + ; +- clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; ++ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; +@@ -710,10 +702,20 @@ + }; + }; + ++ rtc: rtc@7000000 { ++ compatible = "allwinner,sun50i-h6-rtc"; ++ reg = <0x07000000 0x400>; ++ interrupts = , ++ ; ++ clock-output-names = "osc32k", "osc32k-out", "iosc"; ++ clocks = <&ext_osc32k>; ++ #clock-cells = <1>; ++ }; ++ + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-h6-r-ccu"; + reg = <0x07010000 0x400>; +- clocks = <&osc24M>, <&osc32k>, <&iosc>, ++ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; +@@ -741,7 +743,7 @@ + reg = <0x07022000 0x400>; + interrupts = , + ; +- clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; ++ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; +-- +2.23.0 + +From 15ede97054889c0bec09f1f9b71beffecf06fc67 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Fri, 23 Aug 2019 11:42:28 +0200 +Subject: [PATCH] arm64: dts: allwinner: orange-pi-3: Enable WiFi + +Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is called +bcm43356 and can be used with the brcmfmac driver. The module is powered by +the two always on regulators (not AXP805). + +WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be +configured so that it sets up an 1.8V input bias on this port. This is done +by the pio driver by reading the vcc-pg-supply voltage. + +You'll need a fw_bcm43456c5_ag.bin firmware file and nvram.txt +configuration that can be found in the Xulongs's repository for H6: + +https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 + +Mainline brcmfmac driver expects the firmware and nvram at the following +paths relative to the firmware directory: + + brcm/brcmfmac43456-sdio.bin + brcm/brcmfmac43456-sdio.txt + +Signed-off-by: Ondrej Jirman +Signed-off-by: Maxime Ripard +--- + .../dts/allwinner/sun50i-h6-orangepi-3.dts | 46 +++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index eda9d5f640b9..eb379cd402ac 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -56,6 +56,34 @@ + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ reg_vcc33_wifi: vcc33-wifi { ++ /* Always on 3.3V regulator for WiFi and BT */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc33-wifi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc33_wifi>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; + }; + + &cpu0 { +@@ -91,6 +119,23 @@ + status = "okay"; + }; + ++&mmc1 { ++ vmmc-supply = <®_vcc33_wifi>; ++ vqmmc-supply = <®_vcc_wifi_io>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcm: sdio-wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ + &ohci0 { + status = "okay"; + }; +@@ -102,6 +147,7 @@ + &pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_vcc_wifi_io>; + }; + + &r_i2c { +-- +2.23.0 + +From 652a458eb92018c5126701e721255356fdab94a9 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Fri, 16 Aug 2019 22:53:42 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Introduce Tanix TX6 board + +Tanix TX6 is an Allwinner H6 based TV box, which supports: +- Allwinner H6 Quad-core 64-bit ARM Cortex-A53 +- GPU Mali-T720 +- 4GiB DDR3 RAM (3GiB useable) +- 100Mbps EMAC via AC200 EPHY +- Cdtech 47822BS Wifi/BT +- 2x USB 2.0 Host and 1x USB 3.0 Host +- HDMI port +- IR receiver +- 64GiB eMMC +- 5V/2A DC power supply + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 100 ++++++++++++++++++ + 2 files changed, 101 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index f6db0611cb85..395fe76f6819 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -25,3 +25,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +new file mode 100644 +index 000000000000..7e7cb10e3d96 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +@@ -0,0 +1,100 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (c) 2019 Jernej Skrabec ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h6.dtsi" ++ ++#include ++ ++/ { ++ model = "Tanix TX6"; ++ compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&r_ir { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&usb2otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb2phy { ++ status = "okay"; ++}; +-- +2.23.0 + +From 9e037bdf743cc081858423ad4123824e846b2358 Mon Sep 17 00:00:00 2001 +From: Joe Perches +Date: Wed, 10 Jul 2019 01:04:24 -0400 +Subject: [PATCH] media: staging: media: cedrus: Fix misuse of GENMASK macro + +Arguments are supposed to be ordered high then low. + +Signed-off-by: Joe Perches +Acked-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index 3e9931416e45..ddd29788d685 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -110,7 +110,7 @@ + #define VE_DEC_MPEG_MBADDR (VE_ENGINE_DEC_MPEG + 0x10) + + #define VE_DEC_MPEG_MBADDR_X(w) (((w) << 8) & GENMASK(15, 8)) +-#define VE_DEC_MPEG_MBADDR_Y(h) (((h) << 0) & GENMASK(0, 7)) ++#define VE_DEC_MPEG_MBADDR_Y(h) (((h) << 0) & GENMASK(7, 0)) + + #define VE_DEC_MPEG_CTRL (VE_ENGINE_DEC_MPEG + 0x14) + +-- +2.23.0 + +From b557b5073194d63bcd2850c009f9326250b4bd97 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 30 May 2019 18:15:14 -0300 +Subject: [PATCH] media: cedrus: Don't set chroma size for scale & rotation + +Scale and rotation are currently not implemented, so it makes no sense to +set chroma size for it. + +Signed-off-by: Jernej Skrabec +Acked-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index c34aec7c6e40..fc8579b90dab 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -79,9 +79,6 @@ void cedrus_dst_format_set(struct cedrus_dev *dev, + reg = VE_PRIMARY_OUT_FMT_NV12; + cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); + +- reg = VE_CHROMA_BUF_LEN_SDRT(chroma_size / 2); +- cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); +- + reg = chroma_size / 2; + cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); + +-- +2.23.0 diff --git a/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch b/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch index 2d5ff656c0..e2d18f2679 100644 --- a/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch +++ b/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch @@ -287,16 +287,6 @@ index 7d2f6eedfc28..9503d395855b 100644 cedrus_write(dev, VE_MODE, reg); return 0; -@@ -83,9 +89,6 @@ void cedrus_dst_format_set(struct cedrus_dev *dev, - reg = VE_PRIMARY_OUT_FMT_NV12; - cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); - -- reg = VE_CHROMA_BUF_LEN_SDRT(chroma_size / 2); -- cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); -- - reg = chroma_size / 2; - cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); - diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h index 27d0882397aa..0e67c69812be 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h From 48b85f763e5b93e36cfe04cb7f582f4e0a52ffb8 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 25 Aug 2019 15:44:01 +0200 Subject: [PATCH 2/5] Allwinner: H6: Add eMMC workaround --- .../H6/patches/linux/14-eMMC-workaround.patch | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 projects/Allwinner/devices/H6/patches/linux/14-eMMC-workaround.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/14-eMMC-workaround.patch b/projects/Allwinner/devices/H6/patches/linux/14-eMMC-workaround.patch new file mode 100644 index 0000000000..55b2d4c004 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/14-eMMC-workaround.patch @@ -0,0 +1,38 @@ +From 4d38ab8df68f04cc87eeba065c3d35df71c280e4 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 24 Aug 2019 01:36:44 +0200 +Subject: [PATCH] eMMC workaround + +Signed-off-by: Jernej Skrabec +--- + drivers/mmc/host/sunxi-mmc.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c +index d577a6b0ceae..067d217bde42 100644 +--- a/drivers/mmc/host/sunxi-mmc.c ++++ b/drivers/mmc/host/sunxi-mmc.c +@@ -1394,15 +1394,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev) + MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; + + /* +- * Some H5 devices do not have signal traces precise enough to +- * use HS DDR mode for their eMMC chips. ++ * Some H5 and H6 devices do not have signal traces precise ++ * enough to use HS DDR mode for their eMMC chips. + * + * We still enable HS DDR modes for all the other controller + * variants that support them. + */ + if ((host->cfg->clk_delays || host->use_new_timings) && + !of_device_is_compatible(pdev->dev.of_node, +- "allwinner,sun50i-h5-emmc")) ++ "allwinner,sun50i-h5-emmc") && ++ !of_device_is_compatible(pdev->dev.of_node, ++ "allwinner,sun50i-h6-emmc")) + mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; + + ret = mmc_of_parse(mmc); +-- +2.23.0 + From 6270d8fe088f6d49e4e4f483e1d043db52bb1757 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 25 Aug 2019 15:44:27 +0200 Subject: [PATCH 3/5] Allwinner: H6: Add RTC workaround --- .../H6/patches/linux/15-RTC-workaround.patch | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 projects/Allwinner/devices/H6/patches/linux/15-RTC-workaround.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/15-RTC-workaround.patch b/projects/Allwinner/devices/H6/patches/linux/15-RTC-workaround.patch new file mode 100644 index 0000000000..b4ff3f6fc4 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/15-RTC-workaround.patch @@ -0,0 +1,41 @@ +From 7c8b4644df51ba7ecd68a6898bcb041ab669ddf9 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 25 Aug 2019 00:02:06 +0200 +Subject: [PATCH] RTC workaround + +Signed-off-by: Jernej Skrabec +--- + drivers/rtc/rtc-sun6i.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c +index 4603a91c11be..d8a0817b96f4 100644 +--- a/drivers/rtc/rtc-sun6i.c ++++ b/drivers/rtc/rtc-sun6i.c +@@ -33,6 +33,7 @@ + #define SUN6I_LOSC_CTRL 0x0000 + #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) + #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) ++#define SUN6I_LOSC_CTRL_AUTO_SWT_EN BIT(14) + #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) + #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) + #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) +@@ -253,6 +254,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, + + /* Switch to the external, more precise, oscillator */ + reg |= SUN6I_LOSC_CTRL_EXT_OSC; ++ reg |= SUN6I_LOSC_CTRL_AUTO_SWT_EN; + if (rtc->data->has_losc_en) + reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; + writel(reg, rtc->base + SUN6I_LOSC_CTRL); +@@ -370,7 +372,6 @@ static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { + .has_out_clk = 1, + .export_iosc = 1, + .has_losc_en = 1, +- .has_auto_swt = 1, + }; + + static void __init sun50i_h6_rtc_clk_init(struct device_node *node) +-- +2.23.0 + From 2b8bd4c8122c47e15181ed1b9712176e4527d252 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 25 Aug 2019 15:45:02 +0200 Subject: [PATCH 4/5] Allwinner: Disable U-Boot network driver --- projects/Allwinner/bootloader/config | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/Allwinner/bootloader/config b/projects/Allwinner/bootloader/config index 58d44d1a2e..e875753fe4 100644 --- a/projects/Allwinner/bootloader/config +++ b/projects/Allwinner/bootloader/config @@ -1,4 +1,5 @@ # CONFIG_VIDEO_DE2 is not set # CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_OHCI_HCD is not set +# CONFIG_SUN8I_EMAC is not set CONFIG_BOOTDELAY=0 From fed9a4ab457baab2721ebf514cbd84c7d61bc258 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 25 Aug 2019 15:45:36 +0200 Subject: [PATCH 5/5] Allwinner: A64: Fix Pine64+ Ethernet --- .../linux/03_pine64_plus_ethernet_fixes.patch | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 projects/Allwinner/devices/A64/patches/linux/03_pine64_plus_ethernet_fixes.patch diff --git a/projects/Allwinner/devices/A64/patches/linux/03_pine64_plus_ethernet_fixes.patch b/projects/Allwinner/devices/A64/patches/linux/03_pine64_plus_ethernet_fixes.patch new file mode 100644 index 0000000000..3fe5614aba --- /dev/null +++ b/projects/Allwinner/devices/A64/patches/linux/03_pine64_plus_ethernet_fixes.patch @@ -0,0 +1,132 @@ +From eee4bfe0a8423922948b25a415b110985004f25c Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Mon, 29 Jul 2019 17:29:29 +0800 +Subject: [PATCH] arm64: allwinner: a64: dts: apply hack for RTL8211E on + Pine64+ + +Some of the Pine64+ boards are known to use a batch of broken RTL8211E +PHYs. A magic number that is in an undocumented field of a register is +passed from Realtek via Pine64. + +Add the property to apply the hack to the Pine64+ device tree. + +Signed-off-by: Icenowy Zheng +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +index 24f1aac366d64..4d68f850d03a1 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +@@ -61,5 +61,6 @@ + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; ++ realtek,config-magic-for-pine64; + }; + }; +From f74d56b5dc80440aef4877996a5b6df041625d2b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Mon, 29 Jul 2019 17:27:26 +0800 +Subject: [PATCH] net: phy: realtek: add config hack for broken RTL8211E on + Pine64+ boards + +Some RTL8211E chips have broken GbE function, which needs a hack to +fix. + +Currently only some Pine64+ boards are known to used this broken batch +of RTL8211E chips. + +Enable this hack when a certain device tree property is set. + +As this hack is not documented on the datasheet at all, it contains +magic numbers, and could not be revealed. These magic numbers are +received from Realtek via Pine64. + +Signed-off-by: Icenowy Zheng +--- + drivers/net/phy/realtek.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c +index a669945eb829a..ace1a6340ca9c 100644 +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -9,6 +9,7 @@ + * Copyright (c) 2004 Freescale Semiconductor, Inc. + */ + #include ++#include + #include + #include + +@@ -32,6 +33,13 @@ + #define RTL8211E_TX_DELAY BIT(1) + #define RTL8211E_RX_DELAY BIT(2) + #define RTL8211E_MODE_MII_GMII BIT(3) ++/* ++ * The following number resides in the same register with ++ * the delay bits and mode bit above. However, no known ++ * document can explain this, and this value is directly ++ * received from Realtek via Pine64. ++ */ ++#define RTL8211E_CONF_MAGIC_PINE64 0xb400 + + #define RTL8201F_ISR 0x1e + #define RTL8201F_IER 0x13 +@@ -186,6 +194,7 @@ static int rtl8211e_config_init(struct phy_device *phydev) + { + int ret = 0, oldpage; + u16 val; ++ struct device_node *of_node = phydev->mdio.dev.of_node; + + /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ + switch (phydev->interface) { +@@ -224,6 +233,12 @@ static int rtl8211e_config_init(struct phy_device *phydev) + ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, + val); + ++ if (of_node && ++ of_property_read_bool(of_node, "realtek,config-magic-for-pine64")) { ++ ret = __phy_modify(phydev, 0x1c, GENMASK(15, 9), ++ RTL8211E_CONF_MAGIC_PINE64); ++ } ++ + err_restore_page: + return phy_restore_page(phydev, oldpage, ret); + } +From bb0516f4d03ffe9bcc06f840e477ea665af94e9d Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 25 Aug 2019 14:40:10 +0200 +Subject: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator + delay + +Depending on kernel and bootloader configuration, it's possible that +Realtek ethernet PHY isn't powered on properly. It needs some time +before it can be used. + +Fix that by adding 100ms ramp delay to regulator responsible for +powering PHY. + +Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i") +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +index 24f1aac366d6..9612a34c1762 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +@@ -63,3 +63,7 @@ + reg = <1>; + }; + }; ++ ++®_dc1sw { ++ regulator-enable-ramp-delay = <100000>; ++}; +-- +2.23.0 +