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linux (Rockchip): drop upstreamed patches in 6.9
This commit is contained in:
Rudi Heitbaum
parent
d8ceb86e2f
commit
a21f8fbb35
@ -1,236 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Mon, 6 Jul 2020 22:30:13 +0000
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Subject: [PATCH] drm: drm_fourcc: add NV20 and NV30 YUV formats
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DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
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variant of NV15, a 10-bit 2-plane YUV format that has no padding between
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components. Instead, luminance and chrominance samples are grouped into 4s
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so that each group is packed into an integer number of bytes:
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YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
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The '20' and '30' suffix refers to the optimum effective bits per pixel
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which is achieved when the total number of luminance samples is a multiple
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of 4.
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V2: Added NV30 format
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Reviewed-by: Sandy Huang <hjc@rock-chips.com>
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---
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drivers/gpu/drm/drm_fourcc.c | 8 ++++++++
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include/uapi/drm/drm_fourcc.h | 2 ++
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2 files changed, 10 insertions(+)
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diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
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index 07741b678798..5ec38456dc5d 100644
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--- a/drivers/gpu/drm/drm_fourcc.c
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+++ b/drivers/gpu/drm/drm_fourcc.c
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@@ -261,6 +261,14 @@ const struct drm_format_info *__drm_format_info(u32 format)
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.num_planes = 2, .char_per_block = { 5, 5, 0 },
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.block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
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.vsub = 2, .is_yuv = true },
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+ { .format = DRM_FORMAT_NV20, .depth = 0,
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+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
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+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
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+ .vsub = 1, .is_yuv = true },
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+ { .format = DRM_FORMAT_NV30, .depth = 0,
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+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
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+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
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+ .vsub = 1, .is_yuv = true },
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{ .format = DRM_FORMAT_Q410, .depth = 0,
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.num_planes = 3, .char_per_block = { 2, 2, 2 },
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.block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
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diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
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index 0206f812c569..fa49ee98f275 100644
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--- a/include/uapi/drm/drm_fourcc.h
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+++ b/include/uapi/drm/drm_fourcc.h
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@@ -285,6 +285,8 @@ extern "C" {
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* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
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*/
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#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
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+#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
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+#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
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/*
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* 2 plane YCbCr MSB aligned
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Mon, 6 Jul 2020 22:30:13 +0000
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Subject: [PATCH] drm: rockchip: add NV15, NV20 and NV30 support
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Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the
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Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
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Also add support for 10-bit 4:4:4 format while at it.
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V2: Added NV30 support
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Reviewed-by: Sandy Huang <hjc@rock-chips.com>
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---
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drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++--
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drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
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drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 32 +++++++++++++++++----
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3 files changed, 54 insertions(+), 8 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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index d32117633efe..9e71263ac770 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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@@ -280,6 +280,18 @@ static bool has_uv_swapped(uint32_t format)
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}
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}
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+static bool is_fmt_10(uint32_t format)
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+{
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+ switch (format) {
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+ case DRM_FORMAT_NV15:
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+ case DRM_FORMAT_NV20:
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+ case DRM_FORMAT_NV30:
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+ return true;
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+ default:
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+ return false;
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+ }
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+}
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+
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static enum vop_data_format vop_convert_format(uint32_t format)
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{
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switch (format) {
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@@ -295,12 +307,15 @@ static enum vop_data_format vop_convert_format(uint32_t format)
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case DRM_FORMAT_BGR565:
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return VOP_FMT_RGB565;
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case DRM_FORMAT_NV12:
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+ case DRM_FORMAT_NV15:
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case DRM_FORMAT_NV21:
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return VOP_FMT_YUV420SP;
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case DRM_FORMAT_NV16:
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+ case DRM_FORMAT_NV20:
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case DRM_FORMAT_NV61:
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return VOP_FMT_YUV422SP;
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case DRM_FORMAT_NV24:
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+ case DRM_FORMAT_NV30:
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case DRM_FORMAT_NV42:
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return VOP_FMT_YUV444SP;
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default:
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@@ -954,7 +969,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
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dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
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dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
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- offset = (src->x1 >> 16) * fb->format->cpp[0];
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+ if (fb->format->block_w[0])
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+ offset = (src->x1 >> 16) * fb->format->char_per_block[0] /
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+ fb->format->block_w[0];
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+ else
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+ offset = (src->x1 >> 16) * fb->format->cpp[0];
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+
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offset += (src->y1 >> 16) * fb->pitches[0];
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dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
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@@ -980,6 +1000,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
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}
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VOP_WIN_SET(vop, win, format, format);
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+ VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
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VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
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VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
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VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
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@@ -996,7 +1017,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
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uv_obj = fb->obj[1];
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rk_uv_obj = to_rockchip_obj(uv_obj);
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- offset = (src->x1 >> 16) * bpp / hsub;
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+ if (fb->format->block_w[1])
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+ offset = (src->x1 >> 16) * bpp /
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+ fb->format->block_w[1] / hsub;
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+ else
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+ offset = (src->x1 >> 16) * bpp / hsub;
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offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
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dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
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diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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index 8502849833d9..b6eea31109d5 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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@@ -181,6 +181,7 @@ struct vop_win_phy {
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struct vop_reg enable;
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struct vop_reg gate;
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struct vop_reg format;
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+ struct vop_reg fmt_10;
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struct vop_reg rb_swap;
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struct vop_reg uv_swap;
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struct vop_reg act_info;
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diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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index 014f99e8928e..16e6aa01e400 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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@@ -53,6 +53,23 @@ static const uint32_t formats_win_full[] = {
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DRM_FORMAT_NV42,
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};
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+static const uint32_t formats_win_full_10[] = {
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+ DRM_FORMAT_XRGB8888,
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+ DRM_FORMAT_ARGB8888,
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+ DRM_FORMAT_XBGR8888,
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+ DRM_FORMAT_ABGR8888,
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+ DRM_FORMAT_RGB888,
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+ DRM_FORMAT_BGR888,
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+ DRM_FORMAT_RGB565,
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+ DRM_FORMAT_BGR565,
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+ DRM_FORMAT_NV12,
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+ DRM_FORMAT_NV16,
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+ DRM_FORMAT_NV24,
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+ DRM_FORMAT_NV15,
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+ DRM_FORMAT_NV20,
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+ DRM_FORMAT_NV30,
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+};
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+
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static const uint64_t format_modifiers_win_full[] = {
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID,
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@@ -621,11 +638,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = {
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static const struct vop_win_phy rk3288_win01_data = {
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.scl = &rk3288_win_full_scl,
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- .data_formats = formats_win_full,
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- .nformats = ARRAY_SIZE(formats_win_full),
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+ .data_formats = formats_win_full_10,
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+ .nformats = ARRAY_SIZE(formats_win_full_10),
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.format_modifiers = format_modifiers_win_full,
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.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
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+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
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.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
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.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
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.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
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@@ -756,11 +774,12 @@ static const struct vop_intr rk3368_vop_intr = {
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static const struct vop_win_phy rk3368_win01_data = {
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.scl = &rk3288_win_full_scl,
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- .data_formats = formats_win_full,
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- .nformats = ARRAY_SIZE(formats_win_full),
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+ .data_formats = formats_win_full_10,
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+ .nformats = ARRAY_SIZE(formats_win_full_10),
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.format_modifiers = format_modifiers_win_full,
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.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
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+ .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4),
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.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
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.uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15),
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.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
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@@ -924,11 +943,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
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static const struct vop_win_phy rk3399_win01_data = {
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.scl = &rk3288_win_full_scl,
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- .data_formats = formats_win_full,
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- .nformats = ARRAY_SIZE(formats_win_full),
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+ .data_formats = formats_win_full_10,
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+ .nformats = ARRAY_SIZE(formats_win_full_10),
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.format_modifiers = format_modifiers_win_full_afbc,
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.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
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+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
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.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
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.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
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.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
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@ -2485,23 +2485,6 @@ index 47ad74ef1afb..94a615dca672 100644
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struct vop_reg dsp_data_swap;
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struct vop_reg dsp_out_yuv;
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struct vop_reg dsp_background;
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@@ -286,11 +287,12 @@ struct vop_data {
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/*
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* display output interface supported by rockchip lcdc
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*/
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-#define ROCKCHIP_OUT_MODE_P888 0
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-#define ROCKCHIP_OUT_MODE_P666 1
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-#define ROCKCHIP_OUT_MODE_P565 2
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+#define ROCKCHIP_OUT_MODE_P888 0
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+#define ROCKCHIP_OUT_MODE_P666 1
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+#define ROCKCHIP_OUT_MODE_P565 2
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+#define ROCKCHIP_OUT_MODE_YUV420 14
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/* for use special outface */
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-#define ROCKCHIP_OUT_MODE_AAAA 15
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+#define ROCKCHIP_OUT_MODE_AAAA 15
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/* output flags */
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#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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index b16a4c42773c..5463b04240f7 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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