Merge pull request #6607 from heitbaum/kernel10

linux: update to 5.10.y
This commit is contained in:
CvH 2022-06-19 11:58:53 +02:00 committed by GitHub
commit a77f7b7cc7
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8 changed files with 11 additions and 117 deletions

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@ -2,8 +2,8 @@
# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
PKG_NAME="mali-midgard"
PKG_VERSION="2815552cc83e928d3ca3811f18e2c60d8c9eba0d" # TX011-SW-99002-r28p0-01rel0
PKG_SHA256="3572c819df7afafd99a6af20c9695519b37807487899bb9884f06b2f63f79e17"
PKG_VERSION="055a54556037dce5036cd7470eb9c877c0147f0b" # TX011-SW-99002-r28p0-01rel0
PKG_SHA256="d39e32cfece97084a3a6ef4eb9f494507c36c0b27c39f3dd154eb8eff8666248"
PKG_ARCH="arm aarch64"
PKG_LICENSE="GPL"
PKG_SITE="https://developer.arm.com/products/software/mali-drivers/"

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@ -28,8 +28,8 @@ case "${LINUX}" in
PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
;;
*)
PKG_VERSION="5.10.105"
PKG_SHA256="3ddc0e0ab2b9cadb64df43141e0a1e5432b5963ed50f34d586c065ac8d4fcb85"
PKG_VERSION="5.10.123"
PKG_SHA256="654ab0960b70013e7dad6b3782c25d62e13cbb8c053010daef667d5d74061e52"
PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz"
PKG_PATCH_DIRS="default"
;;

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@ -10,6 +10,7 @@ PKG_URL="https://wayland.freedesktop.org/releases/${PKG_NAME}-${PKG_VERSION}.tar
PKG_DEPENDS_TARGET="toolchain wayland:host libffi expat libxml2"
PKG_DEPENDS_HOST="libffi:host expat:host libxml2:host"
PKG_LONGDESC="a display server protocol"
PKG_TOOLCHAIN="autotools"
PKG_CONFIGURE_OPTS_HOST="--enable-shared \
--disable-static \

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@ -1,32 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Wed, 9 Feb 2022 19:03:06 +0100
Subject: [PATCH] media: cedrus: Fix H265 aux buffer size
Neighbour info buffer size needs to be 794 kiB in size on H6. This is
actually mentioned in comment, but smaller size is used nevertheless.
Increase buffer size to conform H6 needs. Since increase is not that big
in absolute numbers, it doesn't make sense to complicate logic for older
generations.
Bug was discovered using iommu, which reported access error when trying
to play H265 video.
Fixes: 86caab29da78 ("media: cedrus: Add HEVC/H.265 decoding support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
@@ -23,7 +23,7 @@
* Subsequent BSP implementations seem to double the neighbor info buffer size
* for the H6 SoC, which may be related to 10 bit H265 support.
*/
-#define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE (397 * SZ_1K)
+#define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE (794 * SZ_1K)
#define CEDRUS_H265_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K)
#define CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE 160

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@ -1,38 +0,0 @@
From df20a1d7586c8986c986624ca8a9c322f524b515 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Mon, 14 Feb 2022 20:01:26 +0100
Subject: [PATCH] media: cedrus: h264: Fix neighbour info buffer size
According to BSP library source, H264 neighbour info buffer size needs
to be 32 kiB for H6. This is similar to H265 decoding, which also needs
double buffer size in comparison to older Cedrus core generations.
Increase buffer size to cover H6 needs. Since increase is not that big
in absolute numbers, it doesn't make sense to complicate logic for older
generations.
Issue was discovered using iommu and cross checked with BSP library
source.
Fixes: 6eb9b758e307 ("media: cedrus: Add H264 decoding support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
index b4173a8926d6..d8fb93035470 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
@@ -38,7 +38,7 @@ struct cedrus_h264_sram_ref_pic {
#define CEDRUS_H264_FRAME_NUM 18
-#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K)
+#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (32 * SZ_1K)
#define CEDRUS_MIN_PIC_INFO_BUF_SIZE (130 * SZ_1K)
static void cedrus_h264_write_sram(struct cedrus_dev *dev,
--
2.35.1

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@ -128,39 +128,6 @@ index 5622f4c77252..943838d17f54 100644
return 0;
}
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 6 Jul 2020 21:54:35 +0000
Subject: [PATCH] media: rkvdec: h264: Fix bit depth wrap in pps packet
The luma and chroma bit depth fields in the pps packet is 3 bits wide.
8 is wrongly added to the bit depth value written to these 3-bit fields.
Because only the 3 LSB is written the hardware is configured correctly.
Correct this by not adding 8 to the luma and chroma bit depth value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index cbaecdcd3def..bf632d45282b 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
WRITE_PPS(0xff, PROFILE_IDC);
WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
- WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
- WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 6 Jul 2020 21:54:35 +0000

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@ -101,7 +101,7 @@ index c115cd362a7f..d9a2fd9386e2 100644
@@ -763,19 +767,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
u8 dpb_valid = 0;
bool dpb_valid = run->ref_buf_idx[i] >= 0;
- u8 idx = 0;
-
- switch (j) {
@ -143,28 +143,24 @@ index d9a2fd9386e2..d4f27ef7addd 100644
u16 *p = (u16 *)hw_rps;
memset(hw_rps, 0, sizeof(priv_tbl->rps));
@@ -764,18 +764,71 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
@@ -764,16 +764,69 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
p[i] = dpb[i].frame_num - max_frame_num;
}
- for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
- for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
- u8 dpb_valid = 0;
- bool dpb_valid = run->ref_buf_idx[i] >= 0;
- u8 idx = reflists[j][i];
+ if (!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) {
+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
+ for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
+ u8 dpb_valid = 0;
+ bool dpb_valid = run->ref_buf_idx[i] >= 0;
+ u8 idx = reflists[j][i];
- if (idx >= ARRAY_SIZE(dec_params->dpb))
- continue;
- dpb_valid = !!(dpb[idx].flags &
- V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ dpb_valid = !!(dpb[idx].flags &
+ V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
- set_ps_field(hw_rps, DPB_INFO(i, j),
- idx | dpb_valid << 4);

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@ -3429,10 +3429,10 @@ index 957a0eb23241..5a8714ef46b5 100644
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
@@ -1256,6 +1293,7 @@ static int rkvdec_probe(struct platform_device *pdev)
@@ -1256,6 +1293,7 @@
static int rkvdec_probe(struct platform_device *pdev)
{
struct rkvdec_dev *rkvdec;
struct resource *res;
+ const struct rkvdec_variant *variant;
unsigned int i;
int ret, irq;