From a7bef2f823e6f9e7c0535206beef07c0e7b8842a Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 16 May 2019 17:24:04 +0200 Subject: [PATCH] Allwinner: linux: Add HDMI 4K init fix --- .../patches/linux/0011-hdmi-init-fix.patch | 118 ++++++++++++++++++ .../patches/linux/0013-cec-improvements.patch | 10 +- 2 files changed, 123 insertions(+), 5 deletions(-) create mode 100644 projects/Allwinner/patches/linux/0011-hdmi-init-fix.patch diff --git a/projects/Allwinner/patches/linux/0011-hdmi-init-fix.patch b/projects/Allwinner/patches/linux/0011-hdmi-init-fix.patch new file mode 100644 index 0000000000..7022c77884 --- /dev/null +++ b/projects/Allwinner/patches/linux/0011-hdmi-init-fix.patch @@ -0,0 +1,118 @@ +From 4029cb43656ede363011e199e589357b2de95617 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 14 May 2019 22:02:46 +0200 +Subject: [PATCH 1/2] drm/sun4i: Fix sun8i HDMI PHY clock initialization + +Current code initializes HDMI PHY clock driver before reset line is +deasserted and clocks enabled. Because of that, initial readout of +clock divider is incorrect (0 instead of 2). This causes any clock +rate with divider 1 (register value 0) to be set incorrectly. + +Fix this by moving initialization of HDMI PHY clock driver after reset +line is deasserted and clocks enabled. + +Cc: stable@vger.kernel.org # 4.17+ +Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 26 ++++++++++++++------------ + 1 file changed, 14 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +index 66ea3a902e36..afc6d4a9c20b 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -672,22 +672,13 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) + goto err_put_clk_pll0; + } + } +- +- ret = sun8i_phy_clk_create(phy, dev, +- phy->variant->has_second_pll); +- if (ret) { +- dev_err(dev, "Couldn't create the PHY clock\n"); +- goto err_put_clk_pll1; +- } +- +- clk_prepare_enable(phy->clk_phy); + } + + phy->rst_phy = of_reset_control_get_shared(node, "phy"); + if (IS_ERR(phy->rst_phy)) { + dev_err(dev, "Could not get phy reset control\n"); + ret = PTR_ERR(phy->rst_phy); +- goto err_disable_clk_phy; ++ goto err_put_clk_pll1; + } + + ret = reset_control_deassert(phy->rst_phy); +@@ -708,18 +699,29 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) + goto err_disable_clk_bus; + } + ++ if (phy->variant->has_phy_clk) { ++ ret = sun8i_phy_clk_create(phy, dev, ++ phy->variant->has_second_pll); ++ if (ret) { ++ dev_err(dev, "Couldn't create the PHY clock\n"); ++ goto err_disable_clk_mod; ++ } ++ ++ clk_prepare_enable(phy->clk_phy); ++ } ++ + hdmi->phy = phy; + + return 0; + ++err_disable_clk_mod: ++ clk_disable_unprepare(phy->clk_mod); + err_disable_clk_bus: + clk_disable_unprepare(phy->clk_bus); + err_deassert_rst_phy: + reset_control_assert(phy->rst_phy); + err_put_rst_phy: + reset_control_put(phy->rst_phy); +-err_disable_clk_phy: +- clk_disable_unprepare(phy->clk_phy); + err_put_clk_pll1: + clk_put(phy->clk_pll1); + err_put_clk_pll0: +-- +2.21.0 + +From 3ebe28afd2b9250375d38bc1144a4aac74340464 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 14 May 2019 22:26:20 +0200 +Subject: [PATCH 2/2] drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 + MHz + +Vendor provided documentation says that EMP bits should be set to 3 for +pixel clocks greater than 148.5 MHz. + +Fix that. + +Cc: stable@vger.kernel.org # 4.17+ +Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +index afc6d4a9c20b..43643ad31730 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -293,7 +293,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi, + SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | + SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4); + ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) | +- SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13); ++ SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) | ++ SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3); + } + + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0013-cec-improvements.patch b/projects/Allwinner/patches/linux/0013-cec-improvements.patch index a7367c738d..f9360ec979 100644 --- a/projects/Allwinner/patches/linux/0013-cec-improvements.patch +++ b/projects/Allwinner/patches/linux/0013-cec-improvements.patch @@ -166,7 +166,7 @@ index 66ea3a902e36..70e291353569 100644 .is_custom_phy = true, .phy_init = &sun8i_hdmi_phy_init_h3, @@ -708,10 +753,40 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) - goto err_disable_clk_bus; + clk_prepare_enable(phy->clk_phy); } +#ifdef CONFIG_DRM_SUN8I_DW_HDMI_CEC @@ -201,11 +201,11 @@ index 66ea3a902e36..70e291353569 100644 + cec_delete_adapter(phy->cec_adapter); +err_put_cec_notifier: + cec_notifier_put(phy->cec_notifier); -+err_disable_clk_mod: -+ clk_disable_unprepare(phy->clk_mod); ++err_disable_clk_phy: ++ clk_disable_unprepare(phy->clk_phy); + err_disable_clk_mod: + clk_disable_unprepare(phy->clk_mod); err_disable_clk_bus: - clk_disable_unprepare(phy->clk_bus); - err_deassert_rst_phy: @@ -736,6 +811,10 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) { struct sun8i_hdmi_phy *phy = hdmi->phy;