Rockchip: RK3288: fix 2160p@60Hz modes

Has only been observered on a Samsung 4K TV
This commit is contained in:
Alex Bee 2021-03-02 12:58:13 +01:00
parent 73c0ce662b
commit b0cb56556f

View File

@ -3028,3 +3028,32 @@ index 72f34205fd20..9358d302f5e4 100644
<50000000>, <100000000>,
<100000000>, <100000000>,
<50000000>, <50000000>,
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Mon, 1 Mar 2021 20:31:15 +0100
Subject: [PATCH] clk: rockchip: rk3288: use common PLL setting for 594 MHz in
NPLL table
The settings in the NPLL table (which were obviously copied from RK3368) don't
provide a stable signal for 594 MHz, what leads to random short-term black
screen periods (@2160p@60Hz) on some sensetive HDMI sinks when using this PLL
as the source for VOPs dclk.
Using the PLL settings from the common PLL table for this frequency fixes
this.
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index b3247a3a7290..f5617529dbb5 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -122,7 +122,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
};
static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
- RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),