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Rockchip: RK3288: fix 2160p@60Hz modes
Has only been observered on a Samsung 4K TV
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@ -3028,3 +3028,32 @@ index 72f34205fd20..9358d302f5e4 100644
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<50000000>, <100000000>,
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<100000000>, <100000000>,
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<50000000>, <50000000>,
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Mon, 1 Mar 2021 20:31:15 +0100
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Subject: [PATCH] clk: rockchip: rk3288: use common PLL setting for 594 MHz in
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NPLL table
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The settings in the NPLL table (which were obviously copied from RK3368) don't
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provide a stable signal for 594 MHz, what leads to random short-term black
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screen periods (@2160p@60Hz) on some sensetive HDMI sinks when using this PLL
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as the source for VOPs dclk.
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Using the PLL settings from the common PLL table for this frequency fixes
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this.
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---
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drivers/clk/rockchip/clk-rk3288.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index b3247a3a7290..f5617529dbb5 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -122,7 +122,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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};
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static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
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- RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
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+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
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RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
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RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
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RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
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