diff --git a/projects/Rockchip/bootloader/canupdate.sh b/projects/Rockchip/bootloader/canupdate.sh
index b9b32ca914..908179b820 100644
--- a/projects/Rockchip/bootloader/canupdate.sh
+++ b/projects/Rockchip/bootloader/canupdate.sh
@@ -1,6 +1,15 @@
# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+# detect legacy kernel installs and abort to prevent upgrades
+case $(uname -r) in
+ 4.4*)
+ echo "Updates from legacy kernels are not supported!"
+ sleep 10
+ exit 1
+ ;;
+esac
+
# Allow upgrades between arm and aarch64
if [ "$1" = "@PROJECT@.arm" -o "$1" = "@PROJECT@.aarch64" ]; then
exit 0
diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf
index 8cdaa9daa5..ead26a4926 100644
--- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf
+++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf
@@ -1,18 +1,7 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/arm 5.9.0 Kernel Configuration
+# Linux/arm 5.10.4 Kernel Configuration
#
-CONFIG_CC_VERSION_TEXT="arm-none-linux-gnueabihf-gcc-9.2.1 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=90201
-CONFIG_LD_VERSION=233010000
-CONFIG_CLANG_VERSION=0
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
#
# General setup
@@ -57,6 +46,7 @@ CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
@@ -111,6 +101,8 @@ CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem
@@ -177,6 +169,7 @@ CONFIG_INITRAMFS_COMPRESSION_NONE=y
# CONFIG_BOOT_CONFIG is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_BPF=y
@@ -206,6 +199,7 @@ CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_BPF_SYSCALL=y
+# CONFIG_BPF_PRELOAD is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_RSEQ=y
@@ -457,7 +451,6 @@ CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
-CONFIG_SECCOMP=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_XEN is not set
@@ -601,6 +594,7 @@ CONFIG_AS_VFP_VMRS_FPINST=y
#
# General architecture-dependent options
#
+CONFIG_SET_FS=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
# CONFIG_JUMP_LABEL is not set
@@ -627,7 +621,9 @@ CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
@@ -654,6 +650,7 @@ CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
#
# GCOV-based kernel profiling
@@ -663,7 +660,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGINS is not set
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
@@ -1151,6 +1147,11 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set
+
+#
+# ECC engine support
+#
+# end of ECC engine support
# end of NAND
#
@@ -1179,7 +1180,6 @@ CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
-CONFIG_OF_MDIO=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
@@ -1229,6 +1229,7 @@ CONFIG_ISL29003=y
# CONFIG_SRAM is not set
# CONFIG_XILINX_SDFEC is not set
# CONFIG_PVPANIC is not set
+# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_C2PORT is not set
#
@@ -1253,14 +1254,6 @@ CONFIG_EEPROM_93CX6=y
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
-
-#
-# Intel MIC & related support
-#
-CONFIG_VOP_BUS=y
-CONFIG_VOP=y
-# end of Intel MIC & related support
-
# CONFIG_ECHO is not set
# CONFIG_MISC_RTSX_USB is not set
# CONFIG_UACCE is not set
@@ -1407,56 +1400,38 @@ CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
+# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_BCM_UNIMAC=m
-# CONFIG_MDIO_BITBANG is not set
-# CONFIG_MDIO_BUS_MUX_GPIO is not set
-# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
-# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
-# CONFIG_MDIO_HISI_FEMAC is not set
-# CONFIG_MDIO_IPQ4019 is not set
-# CONFIG_MDIO_IPQ8064 is not set
-# CONFIG_MDIO_MSCC_MIIM is not set
-# CONFIG_MDIO_MVUSB is not set
-CONFIG_MDIO_XPCS=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_SFP is not set
#
# MII PHY device drivers
#
-# CONFIG_SFP is not set
-# CONFIG_ADIN_PHY is not set
# CONFIG_AMD_PHY is not set
+# CONFIG_ADIN_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
-CONFIG_BCM7XXX_PHY=m
-# CONFIG_BCM87XX_PHY is not set
-CONFIG_BCM_NET_PHYLIB=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
+CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
-# CONFIG_DP83822_PHY is not set
-# CONFIG_DP83TC811_PHY is not set
-# CONFIG_DP83848_PHY is not set
-# CONFIG_DP83867_PHY is not set
-# CONFIG_DP83869_PHY is not set
-CONFIG_FIXED_PHY=y
# CONFIG_ICPLUS_PHY is not set
+# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
@@ -1470,12 +1445,42 @@ CONFIG_MICROCHIP_PHY=m
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
-# CONFIG_SMSC_PHY is not set
+CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_OF_MDIO=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_MDIO_BCM_UNIMAC=m
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+
+#
+# MDIO Multiplexers
+#
+# CONFIG_MDIO_BUS_MUX_GPIO is not set
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+
+#
+# PCS device drivers
+#
+CONFIG_PCS_XPCS=y
+# end of PCS device drivers
+
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
@@ -1900,6 +1905,7 @@ CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_VIRTIO is not set
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_DEVMEM=y
# CONFIG_DEVKMEM is not set
# CONFIG_RAW_DRIVER is not set
@@ -1974,6 +1980,7 @@ CONFIG_I2C_CROS_EC_TUNNEL=m
# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
@@ -2064,6 +2071,12 @@ CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_PALMAS=y
# CONFIG_PINCTRL_RK805 is not set
# CONFIG_PINCTRL_OCELOT is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
@@ -2071,6 +2084,8 @@ CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
#
@@ -2141,9 +2156,6 @@ CONFIG_GPIO_TPS65910=y
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_W1 is not set
-CONFIG_POWER_AVS=y
-# CONFIG_QCOM_CPR is not set
-CONFIG_ROCKCHIP_IODOMAIN=y
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
@@ -2158,7 +2170,6 @@ CONFIG_BATTERY_CPCAP=y
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_LEGO_EV3 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
@@ -2184,6 +2195,7 @@ CONFIG_BATTERY_CPCAP=y
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_CHARGER_TPS65090 is not set
# CONFIG_CHARGER_TPS65217 is not set
@@ -2192,6 +2204,7 @@ CONFIG_BATTERY_CPCAP=y
# CONFIG_CHARGER_CROS_USBPD is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
+# CONFIG_RN5T618_POWER is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set
@@ -2264,6 +2277,7 @@ CONFIG_SENSORS_IIO_HWMON=y
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
@@ -2522,6 +2536,7 @@ CONFIG_MFD_TPS65910=y
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
# end of Multifunction device drivers
CONFIG_REGULATOR=y
@@ -2581,8 +2596,11 @@ CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_RN5T618=y
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_S2MPA01 is not set
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_S5M8767=y
@@ -2660,7 +2678,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
-# CONFIG_MEDIA_PLATFORM_SUPPORT is not set
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types
@@ -2770,6 +2788,11 @@ CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
+CONFIG_VIDEO_ROCKCHIP_RGA=m
# end of Media drivers
#
@@ -3050,6 +3073,7 @@ CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
@@ -3090,6 +3114,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
@@ -3101,9 +3126,11 @@ CONFIG_DRM_PARADE_PS8622=m
CONFIG_DRM_SII9234=m
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
@@ -3112,6 +3139,7 @@ CONFIG_DRM_SII9234=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_I2C_ADV7511_CEC=y
+# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
@@ -3182,6 +3210,7 @@ CONFIG_FB_MODE_HELPERS=y
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
@@ -3345,6 +3374,7 @@ CONFIG_SND_SOC_CPCAP=m
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
@@ -3407,6 +3437,7 @@ CONFIG_SND_SOC_SPDIF=m
CONFIG_SND_SOC_STI_SAS=m
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
@@ -3507,6 +3538,7 @@ CONFIG_HID_GENERIC=y
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_GOOGLE_HAMMER is not set
+# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
@@ -3533,7 +3565,6 @@ CONFIG_HID_GENERIC=y
# CONFIG_HID_NTI is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
-# CONFIG_HID_OUYA is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PENMOUNT is not set
# CONFIG_HID_PETALYNX is not set
@@ -3597,6 +3628,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
@@ -3693,6 +3725,7 @@ CONFIG_USB_DWC3_DUAL_ROLE=y
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3_ROCKCHIP_INNO=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set
@@ -3929,6 +3962,7 @@ CONFIG_LEDS_CPCAP=m
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
@@ -4045,6 +4079,7 @@ CONFIG_RTC_DRV_RX8581=m
# CONFIG_RTC_DRV_RX8025 is not set
CONFIG_RTC_DRV_EM3027=y
# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
CONFIG_RTC_DRV_S5M=m
# CONFIG_RTC_DRV_SD3078 is not set
@@ -4166,8 +4201,6 @@ CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
# CONFIG_VDPA is not set
-CONFIG_VHOST_IOTLB=y
-CONFIG_VHOST_RING=y
CONFIG_VHOST_MENU=y
# CONFIG_VHOST_NET is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
@@ -4248,7 +4281,6 @@ CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_HANTRO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_VDEC=m
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
#
@@ -4272,8 +4304,9 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_WFX is not set
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_GOLDFISH is not set
-CONFIG_MFD_CROS_EC=m
CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC=m
# CONFIG_CROS_EC_I2C is not set
@@ -4292,7 +4325,6 @@ CONFIG_HAVE_CLK=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
-# CONFIG_CLK_HSDK is not set
CONFIG_COMMON_CLK_MAX77686=y
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
@@ -4313,17 +4345,12 @@ CONFIG_CLK_QORIQ=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_CLK_PX30=y
CONFIG_CLK_RV110X=y
CONFIG_CLK_RK3036=y
CONFIG_CLK_RK312X=y
CONFIG_CLK_RK3188=y
CONFIG_CLK_RK322X=y
CONFIG_CLK_RK3288=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
# CONFIG_HWSPINLOCK is not set
#
@@ -4422,6 +4449,7 @@ CONFIG_RPMSG_VIRTIO=m
# end of Qualcomm SoC drivers
CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_SOC_TI is not set
@@ -4471,6 +4499,8 @@ CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
@@ -4479,6 +4509,7 @@ CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
# CONFIG_IIO_SW_DEVICE is not set
CONFIG_IIO_SW_TRIGGER=y
+# CONFIG_IIO_TRIGGERED_EVENT is not set
#
# Accelerometers
@@ -4695,6 +4726,7 @@ CONFIG_VF610_ADC=m
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
+# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
@@ -4724,6 +4756,7 @@ CONFIG_MPU3050_I2C=y
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
+# CONFIG_HDC2010 is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
@@ -4758,6 +4791,7 @@ CONFIG_MPU3050_I2C=y
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
+# CONFIG_AS73211 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
@@ -4955,6 +4989,7 @@ CONFIG_RESET_SCMI=y
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
+# CONFIG_USB_LGM_PHY is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
@@ -4970,9 +5005,11 @@ CONFIG_GENERIC_PHY=y
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=m
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
CONFIG_PHY_ROCKCHIP_EMMC=m
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=m
+# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
# CONFIG_PHY_ROCKCHIP_PCIE is not set
# CONFIG_PHY_ROCKCHIP_TYPEC is not set
@@ -5214,6 +5251,7 @@ CONFIG_ROOT_NFS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
@@ -5224,7 +5262,15 @@ CONFIG_SUNRPC_GSS=y
CONFIG_SUNRPC_BACKCHANNEL=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
-# CONFIG_CIFS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_ROOT is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_NLS=y
@@ -5323,9 +5369,9 @@ CONFIG_CRYPTO=y
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=m
+CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
@@ -5341,8 +5387,8 @@ CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_PCRYPT is not set
# CONFIG_CRYPTO_CRYPTD is not set
@@ -5358,13 +5404,14 @@ CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
CONFIG_CRYPTO_CURVE25519=m
#
# Authenticated Encryption with Associated Data
#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
CONFIG_CRYPTO_SEQIV=m
@@ -5375,9 +5422,9 @@ CONFIG_CRYPTO_ECHAINIV=m
#
CONFIG_CRYPTO_CBC=m
# CONFIG_CRYPTO_CFB is not set
-CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
@@ -5389,8 +5436,8 @@ CONFIG_CRYPTO_ECB=m
#
# Hash modes
#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
@@ -5403,18 +5450,18 @@ CONFIG_CRYPTO_XXHASH=m
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_BLAKE2S=m
# CONFIG_CRYPTO_CRCT10DIF is not set
-CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_GHASH=y
# CONFIG_CRYPTO_POLY1305 is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=m
-# CONFIG_CRYPTO_SHA512 is not set
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_STREEBOG is not set
@@ -5467,7 +5514,9 @@ CONFIG_CRYPTO_USER_API=m
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# CONFIG_CRYPTO_STATS is not set
CONFIG_CRYPTO_HASH_INFO=y
@@ -5475,19 +5524,19 @@ CONFIG_CRYPTO_HASH_INFO=y
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
CONFIG_CRYPTO_LIB_BLAKE2S=m
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=m
+CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
@@ -5584,6 +5633,7 @@ CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_CMA=y
+# CONFIG_DMA_PERNUMA_CMA is not set
#
# Default contiguous memory area size:
@@ -5740,6 +5790,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)
CONFIG_STACKTRACE=y
@@ -5761,7 +5812,7 @@ CONFIG_STACKTRACE=y
#
# RCU Debugging
#
-# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
@@ -5857,7 +5908,6 @@ CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
-# CONFIG_TEST_BITFIELD is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
@@ -5879,6 +5929,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
+# CONFIG_TEST_FREE_PAGES is not set
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage
# end of Kernel hacking
diff --git a/projects/Rockchip/devices/RK3328/README.md b/projects/Rockchip/devices/RK3328/README.md
index 685eca9b81..c06a8ff691 100644
--- a/projects/Rockchip/devices/RK3328/README.md
+++ b/projects/Rockchip/devices/RK3328/README.md
@@ -4,12 +4,9 @@ This is a SoC device for RK3328
**Build**
-* `PROJECT=Rockchip DEVICE=RK3328 ARCH=arm UBOOT_SYSTEM=box make image`
-* `PROJECT=Rockchip DEVICE=RK3328 ARCH=arm UBOOT_SYSTEM=box-trn9 make image`
-* `PROJECT=Rockchip DEVICE=RK3328 ARCH=arm UBOOT_SYSTEM=box-z28 make image`
+* `PROJECT=Rockchip DEVICE=RK3328 ARCH=arm UBOOT_SYSTEM=a1 make image`
* `PROJECT=Rockchip DEVICE=RK3328 ARCH=arm UBOOT_SYSTEM=roc-cc make image`
* `PROJECT=Rockchip DEVICE=RK3328 ARCH=arm UBOOT_SYSTEM=rock64 make image`
-* `PROJECT=Rockchip DEVICE=RK3328 ARCH=arm UBOOT_SYSTEM=rockbox make image`
**How to use on an Android device**
- Flash image to a sd-card
diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf
index 7dc6d65508..5e6fa3289b 100644
--- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf
+++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf
@@ -1,19 +1,7 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.9.0 Kernel Configuration
+# Linux/arm64 5.10.4 Kernel Configuration
#
-CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc-9.2.1 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=90201
-CONFIG_LD_VERSION=233010000
-CONFIG_CLANG_VERSION=0
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
@@ -48,6 +36,7 @@ CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
@@ -105,6 +94,8 @@ CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem
@@ -177,6 +168,7 @@ CONFIG_INITRAMFS_COMPRESSION_LZ4=y
# CONFIG_BOOT_CONFIG is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
@@ -211,6 +203,7 @@ CONFIG_BPF_SYSCALL=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
+# CONFIG_BPF_PRELOAD is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_RSEQ=y
@@ -242,7 +235,8 @@ CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_CONT_SHIFT=4
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
@@ -305,6 +299,7 @@ CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
@@ -335,6 +330,7 @@ CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
@@ -382,7 +378,6 @@ CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-CONFIG_SECCOMP=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
@@ -391,8 +386,6 @@ CONFIG_SECCOMP=y
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_ARM64_SSBD=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
@@ -444,6 +437,8 @@ CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARCH_RANDOM=y
+CONFIG_ARM64_AS_HAS_MTE=y
+CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features
CONFIG_ARM64_SVE=y
@@ -464,6 +459,7 @@ CONFIG_CMDLINE=""
CONFIG_SYSVIPC_COMPAT=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
#
# Power management options
@@ -548,7 +544,6 @@ CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_GOOGLE_FIRMWARE is not set
-CONFIG_EFI_EARLYCON=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
@@ -585,6 +580,7 @@ CONFIG_CRYPTO_AES_ARM64_BS=m
#
# General architecture-dependent options
#
+CONFIG_SET_FS=y
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
@@ -618,7 +614,9 @@ CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
@@ -627,6 +625,7 @@ CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
@@ -649,9 +648,9 @@ CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
#
# GCOV-based kernel profiling
@@ -661,7 +660,10 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGINS is not set
+CONFIG_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+CONFIG_GCC_PLUGIN_RANDSTRUCT=y
+# CONFIG_GCC_PLUGIN_RANDSTRUCT_PERFORMANCE is not set
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
@@ -670,7 +672,8 @@ CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
+CONFIG_MODVERSIONS=y
+CONFIG_ASM_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
@@ -837,6 +840,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_FRAME_VECTOR=y
+CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
@@ -1392,6 +1396,11 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set
+
+#
+# ECC engine support
+#
+# end of ECC engine support
# end of NAND
#
@@ -1414,7 +1423,6 @@ CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
-CONFIG_OF_MDIO=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
@@ -1458,6 +1466,7 @@ CONFIG_VIRTIO_BLK=y
CONFIG_SRAM=y
# CONFIG_XILINX_SDFEC is not set
# CONFIG_PVPANIC is not set
+# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_C2PORT is not set
#
@@ -1482,14 +1491,6 @@ CONFIG_EEPROM_93CX6=m
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
-
-#
-# Intel MIC & related support
-#
-CONFIG_VOP_BUS=y
-CONFIG_VOP=y
-# end of Intel MIC & related support
-
# CONFIG_ECHO is not set
# CONFIG_MISC_RTSX_USB is not set
# CONFIG_UACCE is not set
@@ -1613,58 +1614,37 @@ CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
+# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_BCM_UNIMAC is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_GPIO=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
-CONFIG_MDIO_GPIO=y
-# CONFIG_MDIO_HISI_FEMAC is not set
-# CONFIG_MDIO_IPQ4019 is not set
-# CONFIG_MDIO_IPQ8064 is not set
-# CONFIG_MDIO_MSCC_MIIM is not set
-# CONFIG_MDIO_MVUSB is not set
-# CONFIG_MDIO_OCTEON is not set
-CONFIG_MDIO_XPCS=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_SFP is not set
#
# MII PHY device drivers
#
-# CONFIG_SFP is not set
-# CONFIG_ADIN_PHY is not set
# CONFIG_AMD_PHY is not set
+# CONFIG_ADIN_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
-# CONFIG_BCM7XXX_PHY is not set
-# CONFIG_BCM87XX_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
-# CONFIG_DP83822_PHY is not set
-# CONFIG_DP83TC811_PHY is not set
-# CONFIG_DP83848_PHY is not set
-# CONFIG_DP83867_PHY is not set
-# CONFIG_DP83869_PHY is not set
-CONFIG_FIXED_PHY=y
# CONFIG_ICPLUS_PHY is not set
+# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
@@ -1678,12 +1658,45 @@ CONFIG_MICROCHIP_PHY=m
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
-# CONFIG_SMSC_PHY is not set
+CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_OF_MDIO=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_BCM_UNIMAC is not set
+CONFIG_MDIO_GPIO=y
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+
+#
+# MDIO Multiplexers
+#
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+
+#
+# PCS device drivers
+#
+CONFIG_PCS_XPCS=y
+# end of PCS device drivers
+
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
@@ -2087,6 +2100,7 @@ CONFIG_HW_RANDOM=m
# CONFIG_HW_RANDOM_VIRTIO is not set
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_DEVMEM=y
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
@@ -2248,12 +2262,20 @@ CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_RK805=y
# CONFIG_PINCTRL_OCELOT is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
#
@@ -2318,9 +2340,6 @@ CONFIG_GPIO_MAX77620=y
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_W1 is not set
-CONFIG_POWER_AVS=y
-# CONFIG_QCOM_CPR is not set
-CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
# CONFIG_POWER_RESET_GPIO is not set
@@ -2344,7 +2363,6 @@ CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_LEGO_EV3 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
@@ -2364,6 +2382,7 @@ CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_CHARGER_RT9455 is not set
@@ -2440,6 +2459,7 @@ CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
@@ -2682,6 +2702,7 @@ CONFIG_MFD_SYSCON=y
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
# end of Multifunction device drivers
CONFIG_REGULATOR=y
@@ -2726,7 +2747,10 @@ CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_S2MPA01 is not set
# CONFIG_REGULATOR_S2MPS11 is not set
# CONFIG_REGULATOR_S5M8767 is not set
@@ -2798,7 +2822,7 @@ CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
-# CONFIG_MEDIA_PLATFORM_SUPPORT is not set
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types
@@ -2895,6 +2919,17 @@ CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
+CONFIG_VIDEO_ROCKCHIP_RGA=m
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+
+#
+# MMC/SDIO DVB adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
# end of Media drivers
CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y
@@ -3113,7 +3148,6 @@ CONFIG_ROCKCHIP_DW_HDMI=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
-CONFIG_DRM_RCAR_WRITEBACK=y
# CONFIG_DRM_VIRTIO_GPU is not set
CONFIG_DRM_PANEL=y
@@ -3151,6 +3185,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
@@ -3162,15 +3197,18 @@ CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
@@ -3236,6 +3274,7 @@ CONFIG_FB_MODE_HELPERS=y
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_PWM is not set
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
@@ -3341,7 +3380,6 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
-# CONFIG_SND_SOC_INTEL_KEEMBAY is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_I2S=y
@@ -3396,6 +3434,7 @@ CONFIG_SND_SOC_AK4613=m
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
@@ -3461,6 +3500,7 @@ CONFIG_SND_SOC_SPDIF=y
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
@@ -3560,6 +3600,7 @@ CONFIG_HID_GENERIC=y
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
@@ -3650,6 +3691,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
@@ -3746,6 +3788,7 @@ CONFIG_USB_DWC3_DUAL_ROLE=y
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3_ROCKCHIP_INNO=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set
@@ -3935,6 +3978,7 @@ CONFIG_LEDS_CLASS_FLASH=m
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
@@ -4043,6 +4087,7 @@ CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
CONFIG_RTC_DRV_S5M=y
# CONFIG_RTC_DRV_SD3078 is not set
@@ -4165,8 +4210,6 @@ CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
# CONFIG_VDPA is not set
-CONFIG_VHOST_IOTLB=y
-CONFIG_VHOST_RING=y
CONFIG_VHOST_MENU=y
# CONFIG_VHOST_NET is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
@@ -4247,9 +4290,7 @@ CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_HANTRO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_VDEC=m
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
-# CONFIG_VIDEO_USBVISION is not set
#
# Android
@@ -4272,8 +4313,9 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_WFX is not set
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_GOLDFISH is not set
-# CONFIG_MFD_CROS_EC is not set
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CROS_EC is not set
# CONFIG_MELLANOX_PLATFORM is not set
@@ -4281,7 +4323,6 @@ CONFIG_HAVE_CLK=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
-# CONFIG_CLK_HSDK is not set
# CONFIG_COMMON_CLK_MAX77686 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
@@ -4302,11 +4343,6 @@ CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
-CONFIG_CLK_RV110X=y
-CONFIG_CLK_RK3036=y
-CONFIG_CLK_RK312X=y
-CONFIG_CLK_RK3188=y
-CONFIG_CLK_RK322X=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
@@ -4358,6 +4394,7 @@ CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
# CONFIG_VIRTIO_IOMMU is not set
#
@@ -4413,6 +4450,7 @@ CONFIG_ARM_SMMU_V3=y
# end of Qualcomm SoC drivers
CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_SOC_TI is not set
@@ -4457,6 +4495,8 @@ CONFIG_EXTCON_USB_GPIO=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
# CONFIG_IIO_BUFFER_CB is not set
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
@@ -4465,6 +4505,7 @@ CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
# CONFIG_IIO_SW_DEVICE is not set
# CONFIG_IIO_SW_TRIGGER is not set
+# CONFIG_IIO_TRIGGERED_EVENT is not set
#
# Accelerometers
@@ -4674,6 +4715,7 @@ CONFIG_ROCKCHIP_SARADC=y
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
+# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
@@ -4702,6 +4744,7 @@ CONFIG_ROCKCHIP_SARADC=y
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
+# CONFIG_HDC2010 is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
@@ -4736,6 +4779,7 @@ CONFIG_ROCKCHIP_SARADC=y
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
+# CONFIG_AS73211 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
@@ -4931,6 +4975,7 @@ CONFIG_RESET_CONTROLLER=y
#
CONFIG_GENERIC_PHY=y
# CONFIG_PHY_XGENE is not set
+# CONFIG_USB_LGM_PHY is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
@@ -4946,9 +4991,11 @@ CONFIG_GENERIC_PHY=y
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_INNO_USB3=y
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
CONFIG_PHY_ROCKCHIP_PCIE=m
CONFIG_PHY_ROCKCHIP_TYPEC=y
@@ -4965,6 +5012,7 @@ CONFIG_PHY_ROCKCHIP_USB=y
#
# CONFIG_ARM_CCI_PMU is not set
# CONFIG_ARM_CCN is not set
+# CONFIG_ARM_CMN is not set
CONFIG_ARM_PMU=y
# CONFIG_ARM_DSU_PMU is not set
# CONFIG_ARM_SPE_PMU is not set
@@ -5204,6 +5252,7 @@ CONFIG_ROOT_NFS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
@@ -5214,7 +5263,15 @@ CONFIG_SUNRPC_GSS=y
CONFIG_SUNRPC_BACKCHANNEL=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
-# CONFIG_CIFS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_ROOT is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_9P_FS=y
@@ -5315,6 +5372,10 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity"
# Memory initialization
#
CONFIG_INIT_STACK_NONE=y
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
+# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
@@ -5365,13 +5426,14 @@ CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
CONFIG_CRYPTO_CURVE25519=m
#
# Authenticated Encryption with Associated Data
#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
CONFIG_CRYPTO_SEQIV=m
@@ -5382,9 +5444,9 @@ CONFIG_CRYPTO_ECHAINIV=y
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CFB is not set
-CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
@@ -5397,7 +5459,7 @@ CONFIG_CRYPTO_NHPOLY1305=m
#
# Hash modes
#
-CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
@@ -5411,10 +5473,10 @@ CONFIG_CRYPTO_XXHASH=m
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_BLAKE2S=m
# CONFIG_CRYPTO_CRCT10DIF is not set
-CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=m
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
@@ -5422,7 +5484,7 @@ CONFIG_CRYPTO_POLY1305=m
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
-# CONFIG_CRYPTO_SHA512 is not set
+CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_STREEBOG is not set
@@ -5476,13 +5538,14 @@ CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_HASH_INFO=y
#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
CONFIG_CRYPTO_LIB_BLAKE2S=m
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
@@ -5490,6 +5553,7 @@ CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
@@ -5604,6 +5668,7 @@ CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
+# CONFIG_DMA_PERNUMA_CMA is not set
#
# Default contiguous memory area size:
@@ -5634,6 +5699,7 @@ CONFIG_FONT_SUPPORT=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
+CONFIG_ARCH_STACKWALK=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set
# end of Library routines
@@ -5665,7 +5731,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_COMPRESSED is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_BTF is not set
# CONFIG_GDB_SCRIPTS is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
@@ -5772,6 +5837,8 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)
# CONFIG_STACKTRACE is not set
@@ -5794,7 +5861,7 @@ CONFIG_HAVE_DEBUG_BUGVERBOSE=y
#
# RCU Debugging
#
-# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
diff --git a/projects/Rockchip/devices/RK3399/README.md b/projects/Rockchip/devices/RK3399/README.md
index 9cc3c7bd4d..72923919c1 100644
--- a/projects/Rockchip/devices/RK3399/README.md
+++ b/projects/Rockchip/devices/RK3399/README.md
@@ -4,10 +4,18 @@ This is a SoC device for RK3399
**Build**
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=firefly make image`
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=hugsun-x99 make image`
* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=khadas-edge make image`
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=khadas-edge-v make image`
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=nanopc-t4 make image`
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=nanopi-m4 make image`
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=nanopi-neo4 make image`
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=orangepi make image`
* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=rock960 make image`
* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=rock-pi-4a make image`
* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=rock-pi-4b make image`
* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=rock-pi-4c make image`
* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=rockpro64 make image`
+* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=roc-pc make image`
* `PROJECT=Rockchip DEVICE=RK3399 ARCH=arm UBOOT_SYSTEM=sapphire make image`
diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf
index a06132a50c..b4e3d85e80 100644
--- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf
+++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf
@@ -1,19 +1,7 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.9.0 Kernel Configuration
+# Linux/arm64 5.10.4 Kernel Configuration
#
-CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc-9.2.1 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=90201
-CONFIG_LD_VERSION=233010000
-CONFIG_CLANG_VERSION=0
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
@@ -48,6 +36,7 @@ CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
@@ -105,6 +94,8 @@ CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem
@@ -177,6 +168,7 @@ CONFIG_INITRAMFS_COMPRESSION_LZ4=y
# CONFIG_BOOT_CONFIG is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
@@ -211,6 +203,7 @@ CONFIG_BPF_SYSCALL=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
+# CONFIG_BPF_PRELOAD is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_RSEQ=y
@@ -242,7 +235,8 @@ CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_CONT_SHIFT=4
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
@@ -305,6 +299,7 @@ CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
@@ -335,6 +330,7 @@ CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
@@ -382,7 +378,6 @@ CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-CONFIG_SECCOMP=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
@@ -391,8 +386,6 @@ CONFIG_SECCOMP=y
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_ARM64_SSBD=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
@@ -444,6 +437,8 @@ CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARCH_RANDOM=y
+CONFIG_ARM64_AS_HAS_MTE=y
+CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features
CONFIG_ARM64_SVE=y
@@ -464,6 +459,7 @@ CONFIG_CMDLINE=""
CONFIG_SYSVIPC_COMPAT=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
#
# Power management options
@@ -548,7 +544,6 @@ CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_GOOGLE_FIRMWARE is not set
-CONFIG_EFI_EARLYCON=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
@@ -585,6 +580,7 @@ CONFIG_CRYPTO_AES_ARM64_BS=m
#
# General architecture-dependent options
#
+CONFIG_SET_FS=y
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
@@ -618,7 +614,9 @@ CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
@@ -627,6 +625,7 @@ CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
@@ -649,9 +648,9 @@ CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
#
# GCOV-based kernel profiling
@@ -661,7 +660,9 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGINS is not set
+CONFIG_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
@@ -837,6 +838,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_FRAME_VECTOR=y
+CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
@@ -1392,6 +1394,11 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set
+
+#
+# ECC engine support
+#
+# end of ECC engine support
# end of NAND
#
@@ -1414,7 +1421,6 @@ CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
-CONFIG_OF_MDIO=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
@@ -1458,6 +1464,7 @@ CONFIG_VIRTIO_BLK=y
CONFIG_SRAM=y
# CONFIG_XILINX_SDFEC is not set
# CONFIG_PVPANIC is not set
+# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_C2PORT is not set
#
@@ -1482,14 +1489,6 @@ CONFIG_EEPROM_93CX6=m
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
-
-#
-# Intel MIC & related support
-#
-CONFIG_VOP_BUS=y
-CONFIG_VOP=y
-# end of Intel MIC & related support
-
# CONFIG_ECHO is not set
# CONFIG_MISC_RTSX_USB is not set
# CONFIG_UACCE is not set
@@ -1613,58 +1612,37 @@ CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
+# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_BCM_UNIMAC is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_GPIO=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
-CONFIG_MDIO_GPIO=y
-# CONFIG_MDIO_HISI_FEMAC is not set
-# CONFIG_MDIO_IPQ4019 is not set
-# CONFIG_MDIO_IPQ8064 is not set
-# CONFIG_MDIO_MSCC_MIIM is not set
-# CONFIG_MDIO_MVUSB is not set
-# CONFIG_MDIO_OCTEON is not set
-CONFIG_MDIO_XPCS=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_SFP is not set
#
# MII PHY device drivers
#
-# CONFIG_SFP is not set
-# CONFIG_ADIN_PHY is not set
# CONFIG_AMD_PHY is not set
+# CONFIG_ADIN_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
-# CONFIG_BCM7XXX_PHY is not set
-# CONFIG_BCM87XX_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
-# CONFIG_DP83822_PHY is not set
-# CONFIG_DP83TC811_PHY is not set
-# CONFIG_DP83848_PHY is not set
-# CONFIG_DP83867_PHY is not set
-# CONFIG_DP83869_PHY is not set
-CONFIG_FIXED_PHY=y
# CONFIG_ICPLUS_PHY is not set
+# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
@@ -1678,12 +1656,45 @@ CONFIG_MICROCHIP_PHY=m
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
-# CONFIG_SMSC_PHY is not set
+CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_OF_MDIO=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_BCM_UNIMAC is not set
+CONFIG_MDIO_GPIO=y
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+
+#
+# MDIO Multiplexers
+#
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+
+#
+# PCS device drivers
+#
+CONFIG_PCS_XPCS=y
+# end of PCS device drivers
+
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
@@ -2087,6 +2098,7 @@ CONFIG_HW_RANDOM=m
# CONFIG_HW_RANDOM_VIRTIO is not set
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_DEVMEM=y
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
@@ -2248,12 +2260,20 @@ CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_RK805=y
# CONFIG_PINCTRL_OCELOT is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
#
@@ -2318,9 +2338,6 @@ CONFIG_GPIO_MAX77620=y
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_W1 is not set
-CONFIG_POWER_AVS=y
-# CONFIG_QCOM_CPR is not set
-CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
# CONFIG_POWER_RESET_GPIO is not set
@@ -2344,7 +2361,6 @@ CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_LEGO_EV3 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
@@ -2364,6 +2380,7 @@ CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_CHARGER_RT9455 is not set
@@ -2440,6 +2457,7 @@ CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
@@ -2682,6 +2700,7 @@ CONFIG_MFD_SYSCON=y
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
# end of Multifunction device drivers
CONFIG_REGULATOR=y
@@ -2726,7 +2745,10 @@ CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_S2MPA01 is not set
# CONFIG_REGULATOR_S2MPS11 is not set
# CONFIG_REGULATOR_S5M8767 is not set
@@ -2798,7 +2820,7 @@ CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
-# CONFIG_MEDIA_PLATFORM_SUPPORT is not set
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types
@@ -2895,6 +2917,17 @@ CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
+CONFIG_VIDEO_ROCKCHIP_RGA=m
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+
+#
+# MMC/SDIO DVB adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
# end of Media drivers
CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y
@@ -3113,7 +3146,6 @@ CONFIG_ROCKCHIP_DW_HDMI=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
-CONFIG_DRM_RCAR_WRITEBACK=y
# CONFIG_DRM_VIRTIO_GPU is not set
CONFIG_DRM_PANEL=y
@@ -3151,6 +3183,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
@@ -3162,15 +3195,18 @@ CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
@@ -3236,6 +3272,7 @@ CONFIG_FB_MODE_HELPERS=y
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_PWM is not set
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
@@ -3341,7 +3378,6 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
-# CONFIG_SND_SOC_INTEL_KEEMBAY is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_I2S=y
@@ -3396,6 +3432,7 @@ CONFIG_SND_SOC_AK4613=m
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
@@ -3461,6 +3498,7 @@ CONFIG_SND_SOC_SPDIF=y
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
@@ -3560,6 +3598,7 @@ CONFIG_HID_GENERIC=y
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
@@ -3650,6 +3689,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
@@ -3746,6 +3786,7 @@ CONFIG_USB_DWC3_DUAL_ROLE=y
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_OF_SIMPLE=y
+# CONFIG_USB_DWC3_ROCKCHIP_INNO is not set
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set
@@ -3935,6 +3976,7 @@ CONFIG_LEDS_CLASS_FLASH=m
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
@@ -4043,6 +4085,7 @@ CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
CONFIG_RTC_DRV_S5M=y
# CONFIG_RTC_DRV_SD3078 is not set
@@ -4165,8 +4208,6 @@ CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
# CONFIG_VDPA is not set
-CONFIG_VHOST_IOTLB=y
-CONFIG_VHOST_RING=y
CONFIG_VHOST_MENU=y
# CONFIG_VHOST_NET is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
@@ -4247,9 +4288,7 @@ CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_HANTRO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_VDEC=m
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
-# CONFIG_VIDEO_USBVISION is not set
#
# Android
@@ -4272,8 +4311,9 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_WFX is not set
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_GOLDFISH is not set
-# CONFIG_MFD_CROS_EC is not set
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CROS_EC is not set
# CONFIG_MELLANOX_PLATFORM is not set
@@ -4281,7 +4321,6 @@ CONFIG_HAVE_CLK=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
-# CONFIG_CLK_HSDK is not set
# CONFIG_COMMON_CLK_MAX77686 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
@@ -4302,11 +4341,6 @@ CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
-CONFIG_CLK_RV110X=y
-CONFIG_CLK_RK3036=y
-CONFIG_CLK_RK312X=y
-CONFIG_CLK_RK3188=y
-CONFIG_CLK_RK322X=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
@@ -4358,6 +4392,7 @@ CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
# CONFIG_VIRTIO_IOMMU is not set
#
@@ -4413,6 +4448,7 @@ CONFIG_ARM_SMMU_V3=y
# end of Qualcomm SoC drivers
CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_SOC_TI is not set
@@ -4457,6 +4493,8 @@ CONFIG_EXTCON_USB_GPIO=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
# CONFIG_IIO_BUFFER_CB is not set
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
@@ -4465,6 +4503,7 @@ CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
# CONFIG_IIO_SW_DEVICE is not set
# CONFIG_IIO_SW_TRIGGER is not set
+# CONFIG_IIO_TRIGGERED_EVENT is not set
#
# Accelerometers
@@ -4674,6 +4713,7 @@ CONFIG_ROCKCHIP_SARADC=y
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
+# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
@@ -4702,6 +4742,7 @@ CONFIG_ROCKCHIP_SARADC=y
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
+# CONFIG_HDC2010 is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
@@ -4736,6 +4777,7 @@ CONFIG_ROCKCHIP_SARADC=y
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
+# CONFIG_AS73211 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
@@ -4931,6 +4973,7 @@ CONFIG_RESET_CONTROLLER=y
#
CONFIG_GENERIC_PHY=y
# CONFIG_PHY_XGENE is not set
+# CONFIG_USB_LGM_PHY is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
@@ -4946,9 +4989,11 @@ CONFIG_GENERIC_PHY=y
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
CONFIG_PHY_ROCKCHIP_PCIE=m
CONFIG_PHY_ROCKCHIP_TYPEC=y
@@ -4965,6 +5010,7 @@ CONFIG_PHY_ROCKCHIP_USB=y
#
# CONFIG_ARM_CCI_PMU is not set
# CONFIG_ARM_CCN is not set
+# CONFIG_ARM_CMN is not set
CONFIG_ARM_PMU=y
# CONFIG_ARM_DSU_PMU is not set
# CONFIG_ARM_SPE_PMU is not set
@@ -5204,6 +5250,7 @@ CONFIG_ROOT_NFS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+CONFIG_NFS_V4_2_READ_PLUS=y
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
@@ -5214,7 +5261,15 @@ CONFIG_SUNRPC_GSS=y
CONFIG_SUNRPC_BACKCHANNEL=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
-# CONFIG_CIFS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_ROOT is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_9P_FS=y
@@ -5315,6 +5370,10 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity"
# Memory initialization
#
CONFIG_INIT_STACK_NONE=y
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
+# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
@@ -5365,13 +5424,14 @@ CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
CONFIG_CRYPTO_CURVE25519=m
#
# Authenticated Encryption with Associated Data
#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
CONFIG_CRYPTO_SEQIV=m
@@ -5382,9 +5442,9 @@ CONFIG_CRYPTO_ECHAINIV=y
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CFB is not set
-CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
@@ -5397,7 +5457,7 @@ CONFIG_CRYPTO_NHPOLY1305=m
#
# Hash modes
#
-CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
@@ -5411,10 +5471,10 @@ CONFIG_CRYPTO_XXHASH=m
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_BLAKE2S=m
# CONFIG_CRYPTO_CRCT10DIF is not set
-CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=m
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
@@ -5422,7 +5482,7 @@ CONFIG_CRYPTO_POLY1305=m
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
-# CONFIG_CRYPTO_SHA512 is not set
+CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_STREEBOG is not set
@@ -5476,13 +5536,14 @@ CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_HASH_INFO=y
#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
CONFIG_CRYPTO_LIB_BLAKE2S=m
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
@@ -5490,6 +5551,7 @@ CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
@@ -5604,6 +5666,7 @@ CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
+# CONFIG_DMA_PERNUMA_CMA is not set
#
# Default contiguous memory area size:
@@ -5634,6 +5697,7 @@ CONFIG_FONT_SUPPORT=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
+CONFIG_ARCH_STACKWALK=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set
# end of Library routines
@@ -5772,6 +5836,8 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)
# CONFIG_STACKTRACE is not set
@@ -5794,7 +5860,7 @@ CONFIG_HAVE_DEBUG_BUGVERBOSE=y
#
# RCU Debugging
#
-# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
diff --git a/projects/Rockchip/kodi/appliance.xml b/projects/Rockchip/kodi/appliance.xml
index 8c37b2d46c..31f6e9f58e 100644
--- a/projects/Rockchip/kodi/appliance.xml
+++ b/projects/Rockchip/kodi/appliance.xml
@@ -3,21 +3,15 @@
-
- 0384002160060.00000pstd,0384002160059.94006pstd,0384002160050.00000pstd,0384002160030.00000pstd,0384002160029.97003pstd,0384002160025.00000pstd,0384002160024.00000pstd,0384002160023.97602pstd,0192001080060.00000pstd,0192001080059.94006pstd,0192001080050.00000pstd,0192001080030.00000pstd,0192001080029.97003pstd,0192001080024.00000pstd,0192001080023.97602pstd,0128000720060.00000pstd,0128000720059.94006pstd,0128000720050.00000pstd
-
false
-
- false
-
3
true
-
+
2
false
@@ -31,21 +25,5 @@
-
-
-
-
-
-
-
diff --git a/projects/Rockchip/patches/ffmpeg/ffmpeg-0001-v4l2-request-rkvdec-hevc.patch b/projects/Rockchip/patches/ffmpeg/ffmpeg-0001-v4l2-request-rkvdec-hevc.patch
new file mode 100644
index 0000000000..6853d41ff6
--- /dev/null
+++ b/projects/Rockchip/patches/ffmpeg/ffmpeg-0001-v4l2-request-rkvdec-hevc.patch
@@ -0,0 +1,123 @@
+From 5e9575a822a94139bdcfe6a7fa78e4ef771ccb39 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman
+Date: Wed, 13 May 2020 22:51:21 +0000
+Subject: [PATCH] WIP: hevc rkvdec fields
+
+Signed-off-by: Jonas Karlman
+---
+ libavcodec/hevc-ctrls.h | 17 +++++++++++++----
+ libavcodec/v4l2_request_hevc.c | 12 ++++++++++++
+ 2 files changed, 25 insertions(+), 4 deletions(-)
+
+diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h
+index d1b094c8aaeb..b33e1a8141e1 100644
+--- a/libavcodec/hevc-ctrls.h
++++ b/libavcodec/hevc-ctrls.h
+@@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code {
+ /* The controls are not stable at the moment and will likely be reworked. */
+ struct v4l2_ctrl_hevc_sps {
+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
++ __u8 video_parameter_set_id;
++ __u8 seq_parameter_set_id;
++ __u8 chroma_format_idc;
+ __u16 pic_width_in_luma_samples;
+ __u16 pic_height_in_luma_samples;
+ __u8 bit_depth_luma_minus8;
+@@ -76,9 +79,9 @@ struct v4l2_ctrl_hevc_sps {
+ __u8 log2_diff_max_min_pcm_luma_coding_block_size;
+ __u8 num_short_term_ref_pic_sets;
+ __u8 num_long_term_ref_pics_sps;
+- __u8 chroma_format_idc;
+
+- __u8 padding;
++ __u8 num_slices;
++ __u8 padding[6];
+
+ __u64 flags;
+ };
+@@ -105,7 +108,10 @@ struct v4l2_ctrl_hevc_sps {
+
+ struct v4l2_ctrl_hevc_pps {
+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
++ __u8 pic_parameter_set_id;
+ __u8 num_extra_slice_header_bits;
++ __u8 num_ref_idx_l0_default_active_minus1;
++ __u8 num_ref_idx_l1_default_active_minus1;
+ __s8 init_qp_minus26;
+ __u8 diff_cu_qp_delta_depth;
+ __s8 pps_cb_qp_offset;
+@@ -118,7 +124,7 @@ struct v4l2_ctrl_hevc_pps {
+ __s8 pps_tc_offset_div2;
+ __u8 log2_parallel_merge_level_minus2;
+
+- __u8 padding[4];
++ __u8 padding;
+ __u64 flags;
+ };
+
+@@ -204,7 +210,10 @@ struct v4l2_ctrl_hevc_slice_params {
+ __u8 num_rps_poc_st_curr_after;
+ __u8 num_rps_poc_lt_curr;
+
+- __u8 padding;
++ __u16 short_term_ref_pic_set_size;
++ __u16 long_term_ref_pic_set_size;
++
++ __u8 padding[5];
+
+ __u32 entry_point_offset_minus1[256];
+
+diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c
+index 7e77c83e4e4b..9c6916bcb453 100644
+--- a/libavcodec/v4l2_request_hevc.c
++++ b/libavcodec/v4l2_request_hevc.c
+@@ -169,6 +169,9 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h,
+ .num_rps_poc_st_curr_before = h->rps[ST_CURR_BEF].nb_refs,
+ .num_rps_poc_st_curr_after = h->rps[ST_CURR_AFT].nb_refs,
+ .num_rps_poc_lt_curr = h->rps[LT_CURR].nb_refs,
++
++ .short_term_ref_pic_set_size = sh->short_term_ref_pic_set_size,
++ .long_term_ref_pic_set_size = sh->long_term_ref_pic_set_size,
+ };
+
+ if (sh->slice_sample_adaptive_offset_flag[0])
+@@ -239,9 +242,12 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h,
+ static void fill_sps(struct v4l2_ctrl_hevc_sps *ctrl, const HEVCContext *h)
+ {
+ const HEVCSPS *sps = h->ps.sps;
++ const HEVCPPS *pps = h->ps.pps;
+
+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
+ *ctrl = (struct v4l2_ctrl_hevc_sps) {
++ .video_parameter_set_id = sps->vps_id,
++ .seq_parameter_set_id = pps->sps_id,
+ .chroma_format_idc = sps->chroma_format_idc,
+ .pic_width_in_luma_samples = sps->width,
+ .pic_height_in_luma_samples = sps->height,
+@@ -300,6 +306,7 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx,
+ const HEVCContext *h = avctx->priv_data;
+ const HEVCSPS *sps = h->ps.sps;
+ const HEVCPPS *pps = h->ps.pps;
++ const SliceHeader *sh = &h->sh;
+ const ScalingList *sl = pps->scaling_list_data_present_flag ?
+ &pps->scaling_list :
+ sps->scaling_list_enable_flag ?
+@@ -326,6 +333,9 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx,
+
+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
+ controls->pps = (struct v4l2_ctrl_hevc_pps) {
++ .pic_parameter_set_id = sh->pps_id,
++ .num_ref_idx_l0_default_active_minus1 = pps->num_ref_idx_l0_default_active - 1,
++ .num_ref_idx_l1_default_active_minus1 = pps->num_ref_idx_l1_default_active - 1,
+ .num_extra_slice_header_bits = pps->num_extra_slice_header_bits,
+ .init_qp_minus26 = pps->pic_init_qp_minus26,
+ .diff_cu_qp_delta_depth = pps->diff_cu_qp_delta_depth,
+@@ -442,6 +452,8 @@ static int v4l2_request_hevc_queue_decode(AVCodecContext *avctx, int last_slice)
+ if (ctx->decode_mode == V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED)
+ return ff_v4l2_request_decode_slice(avctx, h->ref->frame, control, FF_ARRAY_ELEMS(control), controls->first_slice, last_slice);
+
++ controls->sps.num_slices = controls->num_slices;
++
+ return ff_v4l2_request_decode_frame(avctx, h->ref->frame, control, FF_ARRAY_ELEMS(control));
+ }
+
diff --git a/projects/Rockchip/patches/kodi/0001-allow-sw-decoding-on-mali-4xx-gpus.patch b/projects/Rockchip/patches/kodi/0001-allow-sw-decoding-on-mali-4xx-gpus.patch
new file mode 100644
index 0000000000..2bb6b0a8a3
--- /dev/null
+++ b/projects/Rockchip/patches/kodi/0001-allow-sw-decoding-on-mali-4xx-gpus.patch
@@ -0,0 +1,44 @@
+From 7479f183788ad47dc5ab74666808c29b7c272531 Mon Sep 17 00:00:00 2001
+From: Alex Bee
+Date: Thu, 14 Jan 2021 23:51:20 +0100
+Subject: [PATCH] HACKOFF: DRMPRIMEGLES: avoid for lima due to broken
+ YU12->XR24 conversion
+
+Signed-off-by: Alex Bee
+---
+ xbmc/cores/VideoPlayer/VideoRenderers/BaseRenderer.cpp | 2 +-
+ .../VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp | 5 +++++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/BaseRenderer.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/BaseRenderer.cpp
+index 8c78f1beac..241a307351 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/BaseRenderer.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/BaseRenderer.cpp
+@@ -329,7 +329,7 @@ EShaderFormat CBaseRenderer::GetShaderFormat()
+ {
+ EShaderFormat ret = SHADER_NONE;
+
+- if (m_format == AV_PIX_FMT_YUV420P)
++ if (m_format == AV_PIX_FMT_YUV420P || m_format == AV_PIX_FMT_DRM_PRIME)
+ ret = SHADER_YV12;
+ else if (m_format == AV_PIX_FMT_YUV420P9)
+ ret = SHADER_YV12_9;
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp
+index c1d69bf381..d33b58a321 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp
+@@ -59,6 +59,11 @@ CBaseRenderer* CRendererDRMPRIMEGLES::Create(CVideoBuffer* buffer)
+ if (!winSystemEGL)
+ return nullptr;
+
++ if (CServiceBroker::GetRenderSystem()->GetRenderVendor() == "lima")
++ {
++ CLog::LogF(LOGDEBUG, "Not using DRMPRIMEGLES due to broken mesa lima driver.");
++ return nullptr;
++ }
+ CEGLImage image{winSystemEGL->GetEGLDisplay()};
+ if (!image.SupportsFormatAndModifier(format, modifier))
+ return nullptr;
+--
+2.25.1
+
diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.10.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.10.patch
deleted file mode 100644
index e1b9d3fd21..0000000000
--- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.10.patch
+++ /dev/null
@@ -1,2967 +0,0 @@
-From 2e3fedafa307db03549840de3f5e342f09fb5c45 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?=C5=81ukasz=20Stelmach?=
-Date: Thu, 13 Aug 2020 22:41:23 +0200
-Subject: [PATCH] dmaengine: pl330: fix instruction dump formatting
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Instruction dump uses two printk() in a row to print one instruction. Use
-KERN_CONT to prevent breaking the output in the middle.
-
-Signed-off-by: Łukasz Stelmach
-Link: https://lore.kernel.org/r/20200813204123.19044-1-l.stelmach@samsung.com
-Signed-off-by: Vinod Koul
-(cherry picked from commit 112ec61b212200d378963cbafdd736a62e9ddaec)
----
- drivers/dma/pl330.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
-index 5274a0704d96..106f47298f9e 100644
---- a/drivers/dma/pl330.c
-+++ b/drivers/dma/pl330.c
-@@ -255,7 +255,7 @@ enum pl330_byteswap {
- static unsigned cmd_line;
- #define PL330_DBGCMD_DUMP(off, x...) do { \
- printk("%x:", cmd_line); \
-- printk(x); \
-+ printk(KERN_CONT x); \
- cmd_line += off; \
- } while (0)
- #define PL330_DBGMC_START(addr) (cmd_line = addr)
-
-From 3bb4e2c068270e9c910e3a3b7bec8b0225e2d442 Mon Sep 17 00:00:00 2001
-From: Jagan Teki
-Date: Wed, 19 Aug 2020 00:15:05 +0530
-Subject: [PATCH] arm64: dts: rockchip: Fix power routing to support POE on
- rk3399-roc-pc
-
-When POE used, the current power routing is failing to power-up
-the PMIC regulators which cause Linux boot hangs.
-
-This patch is trying to update the power routing in order to
-support Type C0 and POE powering methods.
-
-As per the schematics, sys_12v is a common output power regulator
-when type c and POE power being used. sys_12v is supplied by dc_12v
-which is supplied from MP8859 in type c0 power routing and sys_12v
-is supplied by MP8009 PoE PD in POE power supply routing.
-
-Signed-off-by: Jagan Teki
-Tested-by: Suniel Mahesh
-Link: https://lore.kernel.org/r/20200818184505.30064-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit bd77d0ad7a698f5e04edf02328d11e808a71d87c)
----
- .../boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts | 18 ++++++++++++++++--
- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 12 ++++++++++--
- 2 files changed, 26 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts
-index 2acb3d500fb9..754627d97144 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts
-@@ -11,6 +11,16 @@
- model = "Firefly ROC-RK3399-PC Mezzanine Board";
- compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
-
-+ /* MP8009 PoE PD */
-+ poe_12v: poe-12v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "poe_12v";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <12000000>;
-+ regulator-max-microvolt = <12000000>;
-+ };
-+
- vcc3v3_ngff: vcc3v3-ngff {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_ngff";
-@@ -22,7 +32,7 @@
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-- vin-supply = <&dc_12v>;
-+ vin-supply = <&sys_12v>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie {
-@@ -34,10 +44,14 @@
- pinctrl-0 = <&vcc3v3_pcie_en>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-- vin-supply = <&dc_12v>;
-+ vin-supply = <&sys_12v>;
- };
- };
-
-+&sys_12v {
-+ vin-supply = <&poe_12v>;
-+};
-+
- &pcie_phy {
- status = "okay";
- };
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
-index b85ec31cd283..e7a459fa4322 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
-@@ -110,6 +110,14 @@
- regulator-max-microvolt = <5000000>;
- };
-
-+ sys_12v: sys-12v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "sys_12v";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&dc_12v>;
-+ };
-+
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
-@@ -141,7 +149,7 @@
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-- vin-supply = <&dc_12v>;
-+ vin-supply = <&sys_12v>;
- };
-
- vcca_0v9: vcca-0v9 {
-@@ -186,7 +194,7 @@
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-- vin-supply = <&dc_12v>;
-+ vin-supply = <&sys_12v>;
- };
-
- vdd_log: vdd-log {
-
-From 9d3c764ef494a805ed623e81e7485d5fc3f57a97 Mon Sep 17 00:00:00 2001
-From: Johan Jonker
-Date: Tue, 18 Aug 2020 16:37:27 +0200
-Subject: [PATCH] arm64: dts: rockchip: change spdif fallback compatible on
- rk3308
-
-A test with the command below shows that the compatible string
-
-"rockchip,rk3308-spdif", "rockchip,rk3328-spdif"
-
-is already in use, but is not added to a document.
-The current fallback string "rockchip,rk3328-spdif" points to a data
-set enum RK_SPDIF_RK3366 in rockchip_spdif.c that is not used both
-in the mainline as in the manufacturer kernel.
-(Of the enum only RK_SPDIF_RK3288 is used.)
-So if the properties don't change we might as well use the first SoC
-in line as fallback string and add the description for rk3308 as:
-
-"rockchip,rk3308-spdif", "rockchip,rk3066-spdif"
-
-make ARCH=arm64 dtbs_check
-DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
-
-Signed-off-by: Johan Jonker
-Link: https://lore.kernel.org/r/20200818143727.5882-2-jbx6244@gmail.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit bc1f9bff0629a15e3de1ef106ac03cba930227dd)
----
- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
-index e8b754d415d8..2560b98771ca 100644
---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
-@@ -574,7 +574,7 @@
- };
-
- spdif_tx: spdif-tx@ff3a0000 {
-- compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
-+ compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
- reg = <0x0 0xff3a0000 0x0 0x1000>;
- interrupts = ;
- clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
-
-From a87e7be5beb9646557e70f0b42c558d418ba16ce Mon Sep 17 00:00:00 2001
-From: Jagan Teki
-Date: Fri, 7 Aug 2020 15:18:23 +0530
-Subject: [PATCH] dt-bindings: arm: rockchip: Update ROCKPi 4 binding
-
-ROCKPi 4 has 3 variants of hardware platforms called
-ROCKPi 4A, 4B, and 4C.
-
-- ROCKPi 4A has no Wif/BT.
-- ROCKPi 4B has AP6256 Wifi/BT, PoE.
-- ROCKPi 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled
- GPIO pin change compared to 4B, 4C
-
-So, update the existing ROCKPi 4 binding to support
-ROCKPi 4A/B/C hardware platforms.
-
-Signed-off-by: Jagan Teki
-Acked-by: Rob Herring
-Link: https://lore.kernel.org/r/20200807094826.12019-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 75a0a65a301f557bf0306d7983f8cf31ac91de56)
----
- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
-index db2e35796795..7025d00c06cc 100644
---- a/Documentation/devicetree/bindings/arm/rockchip.yaml
-+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
-@@ -430,8 +430,12 @@ properties:
- - const: radxa,rock
- - const: rockchip,rk3188
-
-- - description: Radxa ROCK Pi 4
-+ - description: Radxa ROCK Pi 4A/B/C
- items:
-+ - enum:
-+ - radxa,rockpi4a
-+ - radxa,rockpi4b
-+ - radxa,rockpi4c
- - const: radxa,rockpi4
- - const: rockchip,rk3399
-
-
-From bb10faf3729a3982ba5a85b39b416116e315f642 Mon Sep 17 00:00:00 2001
-From: Jagan Teki
-Date: Fri, 7 Aug 2020 15:18:24 +0530
-Subject: [PATCH] arm64: dts: rockchip: Mark rock-pi-4 as rock-pi-4a dts
-
-ROCKPi 4 has 3 variants of hardware platforms called
-RockPI 4A, 4B, and 4C.
-
-- ROCKPi 4A has no Wif/BT.
-- ROCKPi 4B has AP6256 Wifi/BT, PoE.
-- ROCKPi 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled
- GPIO pin change compared to 4B, 4C
-
-So move common nodes, properties into dtsi file and include
-on respective variant dts files.
-
-Signed-off-by: Jagan Teki
-Link: https://lore.kernel.org/r/20200807094826.12019-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit b5edb04673700125bfd1d13e6c14747b1ecba522)
----
- arch/arm64/boot/dts/rockchip/Makefile | 2 +-
- .../{rk3399-rock-pi-4.dts => rk3399-rock-pi-4.dtsi} | 3 ---
- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts | 13 +++++++++++++
- 3 files changed, 14 insertions(+), 4 deletions(-)
- rename arch/arm64/boot/dts/rockchip/{rk3399-rock-pi-4.dts => rk3399-rock-pi-4.dtsi} (99%)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index b87b1f773083..42f9e1861461 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -33,7 +33,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
--dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-similarity index 99%
-rename from arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
-rename to arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-index 60f98a3e19d8..e163f438f836 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-@@ -11,9 +11,6 @@
- #include "rk3399-opp.dtsi"
-
- / {
-- model = "Radxa ROCK Pi 4";
-- compatible = "radxa,rockpi4", "rockchip,rk3399";
--
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts
-new file mode 100644
-index 000000000000..89f2af5e111d
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts
-@@ -0,0 +1,13 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2019 Akash Gajjar
-+ * Copyright (c) 2019 Pragnesh Patel
-+ */
-+
-+/dts-v1/;
-+#include "rk3399-rock-pi-4.dtsi"
-+
-+/ {
-+ model = "Radxa ROCK Pi 4A";
-+ compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399";
-+};
-
-From 54123d61cf3af2ae6b27e264a40c058eba9716c2 Mon Sep 17 00:00:00 2001
-From: Jagan Teki
-Date: Fri, 7 Aug 2020 15:18:25 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK Pi 4B support
-
-RockPI 4B has AP6256 Wifi/BT, so enable them in 4B dts
-instead of enable in common dtsi.
-
-Signed-off-by: Jagan Teki
-Link: https://lore.kernel.org/r/20200807094826.12019-3-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit c1075b7fcca81f58ebc5d723f07b23f84ae93daa)
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 23 ------------
- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 42 ++++++++++++++++++++++
- 3 files changed, 43 insertions(+), 23 deletions(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index 42f9e1861461..8832d05c2571 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-index e163f438f836..678a336010bf 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-@@ -584,17 +584,6 @@
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
-- status = "okay";
--
-- brcmf: wifi@1 {
-- compatible = "brcm,bcm4329-fmac";
-- reg = <1>;
-- interrupt-parent = <&gpio0>;
-- interrupts = ;
-- interrupt-names = "host-wake";
-- pinctrl-names = "default";
-- pinctrl-0 = <&wifi_host_wake_l>;
-- };
- };
-
- &sdmmc {
-@@ -663,18 +652,6 @@
- &uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
-- status = "okay";
--
-- bluetooth {
-- compatible = "brcm,bcm43438-bt";
-- clocks = <&rk808 1>;
-- clock-names = "ext_clock";
-- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
-- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
-- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-- };
- };
-
- &uart2 {
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts
-new file mode 100644
-index 000000000000..f0055ce2fda0
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts
-@@ -0,0 +1,42 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2019 Akash Gajjar
-+ * Copyright (c) 2019 Pragnesh Patel
-+ */
-+
-+/dts-v1/;
-+#include "rk3399-rock-pi-4.dtsi"
-+
-+/ {
-+ model = "Radxa ROCK Pi 4B";
-+ compatible = "radxa,rockpi4b", "radxa,rockpi4", "rockchip,rk3399";
-+};
-+
-+&sdio0 {
-+ status = "okay";
-+
-+ brcmf: wifi@1 {
-+ compatible = "brcm,bcm4329-fmac";
-+ reg = <1>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = ;
-+ interrupt-names = "host-wake";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_host_wake_l>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "brcm,bcm43438-bt";
-+ clocks = <&rk808 1>;
-+ clock-names = "ext_clock";
-+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
-+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
-+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-+ };
-+};
-
-From a28e4816e96a5b6f565fbe71e8d333e541a54227 Mon Sep 17 00:00:00 2001
-From: Jagan Teki
-Date: Fri, 7 Aug 2020 15:18:26 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK Pi 4C support
-
-Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled
-GPIO pin change compared to 4B, 4C.
-
-So, add or enable difference nodes/properties in 4C dts
-by including common dtsi.
-
-Signed-off-by: Jagan Teki
-Link: https://lore.kernel.org/r/20200807094826.12019-4-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 93e0e8ce5fdf549f1715dad00bfbb21b2f69ba8e)
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 51 ++++++++++++++++++++++
- 2 files changed, 52 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index 8832d05c2571..02cdb3c4a6c1 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
-new file mode 100644
-index 000000000000..4c7ebb1c5d2d
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
-@@ -0,0 +1,51 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
-+ * Copyright (c) 2019 Radxa Limited
-+ * Copyright (c) 2019 Amarula Solutions(India)
-+ */
-+
-+/dts-v1/;
-+#include "rk3399-rock-pi-4.dtsi"
-+
-+/ {
-+ model = "Radxa ROCK Pi 4C";
-+ compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399";
-+};
-+
-+&sdio0 {
-+ status = "okay";
-+
-+ brcmf: wifi@1 {
-+ compatible = "brcm,bcm4329-fmac";
-+ reg = <1>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = ;
-+ interrupt-names = "host-wake";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_host_wake_l>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "brcm,bcm43438-bt";
-+ clocks = <&rk808 1>;
-+ clock-names = "ext_clock";
-+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
-+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
-+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-+ };
-+};
-+
-+&vcc5v0_host {
-+ gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-+};
-+
-+&vcc5v0_host_en {
-+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+};
-
-From c89d84dcef9b307af733aaaedbf1614b4b266341 Mon Sep 17 00:00:00 2001
-From: Johan Jonker
-Date: Sat, 8 Aug 2020 18:06:17 +0200
-Subject: [PATCH] dt-bindings: arm: rockchip: add Zkmagic A95X Z2 description
-
-Add Zkmagic A95X Z2 description for a board with rk3318 processor.
-
-Signed-off-by: Johan Jonker
-Acked-by: Rob Herring
-Link: https://lore.kernel.org/r/20200808160618.15445-3-jbx6244@gmail.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 0dc8c62c92d4df35a001b613ebe10f95e4ebf776)
----
- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
-index 7025d00c06cc..251c3ca22e1b 100644
---- a/Documentation/devicetree/bindings/arm/rockchip.yaml
-+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
-@@ -559,4 +559,9 @@ properties:
- items:
- - const: tronsmart,orion-r68-meta
- - const: rockchip,rk3368
-+
-+ - description: Zkmagic A95X Z2
-+ items:
-+ - const: zkmagic,a95x-z2
-+ - const: rockchip,rk3318
- ...
-
-From a4d955617bdc633aa291642c54134dd30d0c1187 Mon Sep 17 00:00:00 2001
-From: Johan Jonker
-Date: Sat, 8 Aug 2020 18:06:18 +0200
-Subject: [PATCH] arm64: dts: rockchip: add rk3318 A95X Z2 board
-
-The rk3318 A95X Z2 boards are sold as TV box.
-No further documentation is given, but from the dts files
-extracted it seems that the rk3318 processor is simulair
-to the rk3328. This dts file contains only the basic nodes
-that have support in the mainline kernel.
-
-Features:
-
-CPU: RK3318 Quad-Core Cortex-A53
-GPU: Mali-450
-RAM: 2/4GB DDR3
-ROM: EMMC 16/32/64GB
-HDMI: HDMI 2.0a for 4k@60Hz
-Ethernet: 10/100M standard RJ-45
-WiFi: 2.4G+5G WIFI, 802.11 b/g/n
-Bluetooth: 4.0
-1 x USB 3.0
-1 x USB 2.0
-1 x Micro SD card slot
-1 x SPDIF
-1 x AV
-1 x DC IN
-
-Signed-off-by: Johan Jonker
-Link: https://lore.kernel.org/r/20200808160618.15445-4-jbx6244@gmail.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 964ed0807b5f7b42b8a6ad48531ae9312e19599d)
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 374 ++++++++++++++++++++++++
- 2 files changed, 375 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index 02cdb3c4a6c1..d53efdf4cb5a 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -2,6 +2,7 @@
- dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
-new file mode 100644
-index 000000000000..30c73ef25370
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
-@@ -0,0 +1,374 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include
-+#include "rk3328.dtsi"
-+
-+/ {
-+ model = "A95X Z2";
-+ compatible = "zkmagic,a95x-z2", "rockchip,rk3318";
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ adc-keys {
-+ compatible = "adc-keys";
-+ io-channels = <&saradc 0>;
-+ io-channel-names = "buttons";
-+ keyup-threshold-microvolt = <1800000>;
-+ poll-interval = <100>;
-+
-+ recovery {
-+ label = "recovery";
-+ linux,code = ;
-+ press-threshold-microvolt = <17000>;
-+ };
-+ };
-+
-+ ir-receiver {
-+ compatible = "gpio-ir-receiver";
-+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
-+ pinctrl-0 = <&ir_int>;
-+ pinctrl-names = "default";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-0 = <&cyx_led_pin>;
-+ pinctrl-names = "default";
-+
-+ cyx_led: led-0 {
-+ default-state = "on";
-+ gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_LOW>;
-+ label = "CYX_LED";
-+ };
-+ };
-+
-+ sdio_pwrseq: sdio-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ pinctrl-0 = <&wifi_enable_h>;
-+ pinctrl-names = "default";
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+
-+ spdif-sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,name = "SPDIF";
-+
-+ simple-audio-card,cpu {
-+ sound-dai = <&spdif>;
-+ };
-+
-+ simple-audio-card,codec {
-+ sound-dai = <&spdif_out>;
-+ };
-+ };
-+
-+ spdif_out: spdif-out {
-+ compatible = "linux,spdif-dit";
-+ #sound-dai-cells = <0>;
-+ };
-+
-+ /* Power tree */
-+ vccio_1v8: vccio-1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vccio_1v8";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ };
-+
-+ vccio_3v3: vccio-3v3-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vccio_3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ };
-+
-+ vcc_otg_vbus: otg-vbus-regulator {
-+ compatible = "regulator-fixed";
-+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-0 = <&otg_vbus_drv>;
-+ pinctrl-names = "default";
-+ regulator-name = "vcc_otg_vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ };
-+
-+ vcc_sd: sdmmc-regulator {
-+ compatible = "regulator-fixed";
-+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+ pinctrl-0 = <&sdmmc0m1_pin>;
-+ pinctrl-names = "default";
-+ regulator-name = "vcc_sd";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vccio_3v3>;
-+ };
-+
-+ vdd_arm: vdd-arm {
-+ compatible = "pwm-regulator";
-+ pwms = <&pwm0 0 5000 1>;
-+ regulator-name = "vdd_arm";
-+ regulator-min-microvolt = <950000>;
-+ regulator-max-microvolt = <1400000>;
-+ regulator-settling-time-up-us = <250>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ vdd_log: vdd-log {
-+ compatible = "pwm-regulator";
-+ pwms = <&pwm1 0 5000 1>;
-+ regulator-name = "vdd_log";
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <1300000>;
-+ regulator-settling-time-up-us = <250>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+};
-+
-+&analog_sound {
-+ status = "okay";
-+};
-+
-+&codec {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu0_opp_table {
-+ opp-1200000000 {
-+ status = "disabled";
-+ };
-+
-+ opp-1296000000 {
-+ status = "disabled";
-+ };
-+};
-+
-+&emmc {
-+ bus-width = <8>;
-+ cap-mmc-highspeed;
-+ non-removable;
-+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&gmac2phy {
-+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
-+ assigned-clock-rate = <50000000>;
-+ assigned-clocks = <&cru SCLK_MAC2PHY>;
-+ clock_in_out = "output";
-+ status = "okay";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_log>;
-+};
-+
-+&hdmi {
-+ ddc-i2c-scl-high-time-ns = <9625>;
-+ ddc-i2c-scl-low-time-ns = <10000>;
-+ status = "okay";
-+};
-+
-+&hdmiphy {
-+ status = "okay";
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2s0 {
-+ status = "okay";
-+};
-+
-+&i2s1 {
-+ status = "okay";
-+};
-+
-+&io_domains {
-+ pmuio-supply = <&vccio_3v3>;
-+ vccio1-supply = <&vccio_3v3>;
-+ vccio2-supply = <&vccio_1v8>;
-+ vccio3-supply = <&vccio_3v3>;
-+ vccio4-supply = <&vccio_1v8>;
-+ vccio5-supply = <&vccio_3v3>;
-+ vccio6-supply = <&vccio_3v3>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ ir {
-+ ir_int: ir-int {
-+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ leds {
-+ cyx_led_pin: cyx-led-pin {
-+ rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm0 {
-+ pwm0_pin_pull_up: pwm0-pin-pull-up {
-+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pwm1 {
-+ pwm1_pin_pull_up: pwm1-pin-pull-up {
-+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
-+ };
-+ };
-+
-+ sdio-pwrseq {
-+ wifi_enable_h: wifi-enable-h {
-+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sdmmc1 {
-+ clk_32k_out: clk-32k-out {
-+ rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb {
-+ host_vbus_drv: host-vbus-drv {
-+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ otg_vbus_drv: otg-vbus-drv {
-+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pwm0 {
-+ pinctrl-0 = <&pwm0_pin_pull_up>;
-+ pinctrl-names = "active";
-+ status = "okay";
-+};
-+
-+&pwm1 {
-+ pinctrl-0 = <&pwm1_pin_pull_up>;
-+ pinctrl-names = "active";
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vccio_1v8>;
-+ status = "okay";
-+};
-+
-+&sdio {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ keep-power-in-suspend;
-+ max-frequency = <125000000>;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ non-removable;
-+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &clk_32k_out>;
-+ pinctrl-names = "default";
-+ sd-uhs-sdr104;
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
-+ pinctrl-names = "default";
-+ vmmc-supply = <&vcc_sd>;
-+ status = "okay";
-+};
-+
-+&spdif {
-+ pinctrl-0 = <&spdifm0_tx>;
-+ status = "okay";
-+};
-+
-+&soc_crit {
-+ temperature = <115000>; /* millicelsius */
-+};
-+
-+&target {
-+ temperature = <105000>; /* millicelsius */
-+};
-+
-+&threshold {
-+ temperature = <90000>; /* millicelsius */
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-temp = <120000>;
-+ status = "okay";
-+};
-+
-+&u2phy {
-+ status = "okay";
-+};
-+
-+&u2phy_host {
-+ status = "okay";
-+};
-+
-+&u2phy_otg {
-+ phy-supply = <&vcc_otg_vbus>;
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb20_otg {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&vop {
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-
-From 739bf33933935649816771290e0f7e87ed9dcd44 Mon Sep 17 00:00:00 2001
-From: Johan Jonker
-Date: Thu, 13 Aug 2020 20:17:11 +0200
-Subject: [PATCH] arm64: dts: rockchip: fix cpu-supply for rk3328-evb
-
-The property cpu-supply should be added to each cpu separately,
-so fix that for rk3328-evb.
-
-Signed-off-by: Johan Jonker
-Link: https://lore.kernel.org/r/20200813181711.15906-1-jbx6244@gmail.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 4be8df7b3bcd46a75f7e297ef310234975a437d8)
----
- arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
-index 1969dab84138..a48767931af6 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
-@@ -70,6 +70,18 @@
- cpu-supply = <&vdd_arm>;
- };
-
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
- &emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
-
-From 4a30b39b5d073898b065e24af70688d0572bbacb Mon Sep 17 00:00:00 2001
-From: Johan Jonker
-Date: Thu, 13 Aug 2020 20:02:41 +0200
-Subject: [PATCH] ARM: dts: rockchip: update cpu supplies on rk3288
-
-The use of cpu0-supply for cpu0 alone is deprecated,
-so add cpu-supply to each cpu separately and
-update all existing rk3288 boards that use this property.
-
-Signed-off-by: Johan Jonker
-Link: https://lore.kernel.org/r/20200813180241.14660-1-jbx6244@gmail.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit b282ae0511cdb6f17cb5052de20288245a8ecd00)
----
- arch/arm/boot/dts/rk3288-miqi.dts | 14 +++++++++++++-
- arch/arm/boot/dts/rk3288-popmetal.dts | 14 +++++++++++++-
- arch/arm/boot/dts/rk3288-r89.dts | 14 +++++++++++++-
- arch/arm/boot/dts/rk3288-vyasa.dts | 14 +++++++++++++-
- 4 files changed, 52 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
-index 213c9eb84f76..8a3992105151 100644
---- a/arch/arm/boot/dts/rk3288-miqi.dts
-+++ b/arch/arm/boot/dts/rk3288-miqi.dts
-@@ -81,7 +81,19 @@
- };
-
- &cpu0 {
-- cpu0-supply = <&vdd_cpu>;
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
- };
-
- &emmc {
-diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
-index 6a51940398b5..160ed8b932fb 100644
---- a/arch/arm/boot/dts/rk3288-popmetal.dts
-+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
-@@ -103,7 +103,19 @@
- };
-
- &cpu0 {
-- cpu0-supply = <&vdd_cpu>;
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
- };
-
- &emmc {
-diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
-index a258c7ae5329..e5ba901c7dcb 100644
---- a/arch/arm/boot/dts/rk3288-r89.dts
-+++ b/arch/arm/boot/dts/rk3288-r89.dts
-@@ -91,7 +91,19 @@
- };
-
- &cpu0 {
-- cpu0-supply = <&vdd_cpu>;
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
- };
-
- &gmac {
-diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
-index 1a20854a1317..aa50f8ed4ca0 100644
---- a/arch/arm/boot/dts/rk3288-vyasa.dts
-+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
-@@ -125,7 +125,19 @@
- };
-
- &cpu0 {
-- cpu0-supply = <&vdd_cpu>;
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
- };
-
- &emmc {
-
-From 23f9077620fd1f450589387e5951d0db36d2f6d4 Mon Sep 17 00:00:00 2001
-From: Johan Jonker
-Date: Thu, 13 Aug 2020 19:24:50 +0200
-Subject: [PATCH] ARM: dts: rockchip: rk3066a: add label to cpu@1
-
-Add label to cpu@1 for later use.
-
-Signed-off-by: Johan Jonker
-Link: https://lore.kernel.org/r/20200813172451.13754-1-jbx6244@gmail.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 9ab4a7312bf31611f3a9c95470f15b3f2bcd83e3)
----
- arch/arm/boot/dts/rk3066a.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
-index b599394d149d..252750c97f97 100644
---- a/arch/arm/boot/dts/rk3066a.dtsi
-+++ b/arch/arm/boot/dts/rk3066a.dtsi
-@@ -36,7 +36,7 @@
- clock-latency = <40000>;
- clocks = <&cru ARMCLK>;
- };
-- cpu@1 {
-+ cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <&L2>;
-
-From c9ab5671bc0bceac1179f1566daf964c12c4be03 Mon Sep 17 00:00:00 2001
-From: Johan Jonker
-Date: Thu, 13 Aug 2020 19:24:51 +0200
-Subject: [PATCH] ARM: dts: rockchip: update cpu supplies on rk3066a
-
-The use of cpu0-supply for cpu0 alone is deprecated,
-so add cpu-supply to each cpu separately and
-update all existing rk3066a boards.
-
-Signed-off-by: Johan Jonker
-Link: https://lore.kernel.org/r/20200813172451.13754-2-jbx6244@gmail.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 20e464c0f12a9b1930adb0365326037d5b060cee)
----
- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 6 +++++-
- arch/arm/boot/dts/rk3066a-marsboard.dts | 6 +++++-
- arch/arm/boot/dts/rk3066a-rayeager.dts | 6 +++++-
- 3 files changed, 15 insertions(+), 3 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
-index 0a56a2f1bc4d..eba7a1344976 100644
---- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
-+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
-@@ -63,7 +63,11 @@
- };
-
- &cpu0 {
-- cpu0-supply = <&vdd_arm>;
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
- };
-
- &i2c1 {
-diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
-index 7e01f6406a86..6b121658d93c 100644
---- a/arch/arm/boot/dts/rk3066a-marsboard.dts
-+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
-@@ -47,7 +47,11 @@
- };
-
- &cpu0 {
-- cpu0-supply = <&vdd_arm>;
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
- };
-
- &i2c1 {
-diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
-index f9db6bb9fa11..309518403d86 100644
---- a/arch/arm/boot/dts/rk3066a-rayeager.dts
-+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
-@@ -128,7 +128,11 @@
- };
-
- &cpu0 {
-- cpu0-supply = <&vdd_arm>;
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
- };
-
- &emac {
-
-From 4b163a2456edff104e7c9e8d6852afb5aec99b7c Mon Sep 17 00:00:00 2001
-From: Adrian Schmutzler
-Date: Sun, 30 Aug 2020 21:08:20 +0200
-Subject: [PATCH] ARM: dts: rockchip: replace status value "ok" by "okay"
-
-While the DT parser recognizes "ok" as a valid value for the
-"status" property, it is actually mentioned nowhere. Use the
-proper value "okay" instead, as done in the majority of files
-already.
-
-Signed-off-by: Adrian Schmutzler
-Link: https://lore.kernel.org/r/20200830190820.20583-1-freifunk@adrianschmutzler.de
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 0cf10e6f94335495f90fc62fb75d9569f6a603fb)
----
- arch/arm/boot/dts/rk3288-evb.dtsi | 2 +-
- arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +-
- arch/arm/boot/dts/rk3288-firefly.dtsi | 2 +-
- arch/arm/boot/dts/rk3288-miqi.dts | 2 +-
- arch/arm/boot/dts/rk3288-popmetal.dts | 2 +-
- arch/arm/boot/dts/rk3288-r89.dts | 2 +-
- arch/arm/boot/dts/rk3288-rock2-square.dts | 2 +-
- arch/arm/boot/dts/rk3288-tinker.dtsi | 2 +-
- 8 files changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
-index 018802df4c0e..c4ca73b40d4a 100644
---- a/arch/arm/boot/dts/rk3288-evb.dtsi
-+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
-@@ -247,7 +247,7 @@
- pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &gpu {
-diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
-index 61435d8ee37b..36efa36b7190 100644
---- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
-+++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
-@@ -61,7 +61,7 @@
- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &i2c0 {
-diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
-index e5c4fd4ea67e..7fb582302b32 100644
---- a/arch/arm/boot/dts/rk3288-firefly.dtsi
-+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
-@@ -191,7 +191,7 @@
- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &gpu {
-diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
-index 8a3992105151..cf54d5ffff2f 100644
---- a/arch/arm/boot/dts/rk3288-miqi.dts
-+++ b/arch/arm/boot/dts/rk3288-miqi.dts
-@@ -120,7 +120,7 @@
- snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &hdmi {
-diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
-index 160ed8b932fb..8c7376d64bc4 100644
---- a/arch/arm/boot/dts/rk3288-popmetal.dts
-+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
-@@ -161,7 +161,7 @@
- pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &hdmi {
-diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
-index e5ba901c7dcb..55467bc30fa6 100644
---- a/arch/arm/boot/dts/rk3288-r89.dts
-+++ b/arch/arm/boot/dts/rk3288-r89.dts
-@@ -119,7 +119,7 @@
- pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &hdmi {
-diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
-index 3cca4d0f9b09..c4d1d142d8c6 100644
---- a/arch/arm/boot/dts/rk3288-rock2-square.dts
-+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
-@@ -156,7 +156,7 @@
- };
-
- &gmac {
-- status = "ok";
-+ status = "okay";
- };
-
- &hdmi {
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
-index 90e9be443fe6..9c1e38c54eae 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dtsi
-+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
-@@ -137,7 +137,7 @@
- snps,reset-delays-us = <0 10000 1000000>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &gpu {
-
-From 26f3fea877d88bffe0cfbccafb3109a5b4700de9 Mon Sep 17 00:00:00 2001
-From: Adrian Schmutzler
-Date: Sun, 30 Aug 2020 22:11:12 +0200
-Subject: [PATCH] arm64: dts: rockchip: replace status value "ok" by "okay"
-
-While the DT parser recognizes "ok" as a valid value for the
-"status" property, it is actually mentioned nowhere. Use the
-proper value "okay" instead, as done in the majority of files
-already.
-
-Signed-off-by: Adrian Schmutzler
-Link: https://lore.kernel.org/r/20200830201112.1934-1-freifunk@adrianschmutzler.de
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 9caff35d7eba8e15c996c694a282fd38b2ea345e)
----
- arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 2 +-
- arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 4 ++--
- 3 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
-index 1c52f47c43a6..87fabc64cc39 100644
---- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
-@@ -134,7 +134,7 @@
- pinctrl-0 = <&rmii_pins>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &i2c0 {
-diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
-index b058ce999e3b..ecce16ecc9c3 100644
---- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
-@@ -183,7 +183,7 @@
- snps,reset-delays-us = <0 10000 1000000>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &i2c0 {
-diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
-index 236ab0f1b206..2582fa4b90e2 100644
---- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
-@@ -167,7 +167,7 @@
- pinctrl-0 = <&rmii_pins>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
-- status = "ok";
-+ status = "okay";
- };
-
- &i2c0 {
-@@ -198,7 +198,7 @@
- };
-
- &io_domains {
-- status = "ok";
-+ status = "okay";
-
- audio-supply = <&vcc_io>;
- gpio30-supply = <&vcc_io>;
-
-From 28e7a5de4a188cb33017f93a025b3888bf09a74c Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski
-Date: Fri, 28 Aug 2020 17:26:35 +0200
-Subject: [PATCH] dmaengine: pl330: Simplify with dev_err_probe()
-
-Common pattern of handling deferred probe can be simplified with
-dev_err_probe(). Less code and the error value gets printed.
-
-Signed-off-by: Krzysztof Kozlowski
-Link: https://lore.kernel.org/r/20200828152637.16903-1-krzk@kernel.org
-Signed-off-by: Vinod Koul
-(cherry picked from commit af53bef5636d92e81279f4a16f814f8dccf9bf89)
----
- drivers/dma/pl330.c | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
-index 106f47298f9e..bb27338ec1ae 100644
---- a/drivers/dma/pl330.c
-+++ b/drivers/dma/pl330.c
-@@ -3034,9 +3034,7 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
-
- pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
- if (IS_ERR(pl330->rstc)) {
-- if (PTR_ERR(pl330->rstc) != -EPROBE_DEFER)
-- dev_err(&adev->dev, "Failed to get reset!\n");
-- return PTR_ERR(pl330->rstc);
-+ return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n");
- } else {
- ret = reset_control_deassert(pl330->rstc);
- if (ret) {
-@@ -3047,9 +3045,8 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
-
- pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
- if (IS_ERR(pl330->rstc_ocp)) {
-- if (PTR_ERR(pl330->rstc_ocp) != -EPROBE_DEFER)
-- dev_err(&adev->dev, "Failed to get OCP reset!\n");
-- return PTR_ERR(pl330->rstc_ocp);
-+ return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp),
-+ "Failed to get OCP reset!\n");
- } else {
- ret = reset_control_deassert(pl330->rstc_ocp);
- if (ret) {
-
-From da47d555261d41660af9d1071f22b044079d8aff Mon Sep 17 00:00:00 2001
-From: Robin Murphy
-Date: Thu, 3 Sep 2020 21:25:53 +0100
-Subject: [PATCH] dmaengine: pl330: Drop local dma_parms
-
-Since commit f458488425f1 ("amba: Initialize dma_parms for amba
-devices"), struct amba_device already provides a dma_parms structure,
-so we can save allocating another one.
-
-Signed-off-by: Robin Murphy
-Link: https://lore.kernel.org/r/c9e58882e33f22f9b0a6d65a5507e24004512148.1599164692.git.robin.murphy@arm.com
-Signed-off-by: Vinod Koul
-(cherry picked from commit 2fc3cad287c62c6477ab674e4430662b470c3a22)
----
- drivers/dma/pl330.c | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
-index bb27338ec1ae..000c3c4b4f7a 100644
---- a/drivers/dma/pl330.c
-+++ b/drivers/dma/pl330.c
-@@ -460,9 +460,6 @@ struct pl330_dmac {
- /* DMA-Engine Device */
- struct dma_device ddma;
-
-- /* Holds info about sg limitations */
-- struct device_dma_parameters dma_parms;
--
- /* Pool of descriptors available for the DMAC's channels */
- struct list_head desc_pool;
- /* To protect desc_pool manipulation */
-@@ -3151,8 +3148,6 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
- }
- }
-
-- adev->dev.dma_parms = &pl330->dma_parms;
--
- /*
- * This is the limit for transfers with a buswidth of 1, larger
- * buswidths will have larger limits.
-
-From 86d82ef8547894e41cfded4a7521c7dcb6f3dc54 Mon Sep 17 00:00:00 2001
-From: Tuo Li
-Date: Mon, 7 Sep 2020 21:09:37 +0800
-Subject: [PATCH] ALSA: rockchip_i2s: fix a possible divide-by-zero bug in
- rockchip_i2s_hw_params()
-
-The variable bclk_rate is checked in:
- if (bclk_rate && mclk_rate % bclk_rate)
-
-This indicates that bclk_rate can be zero.
-If so, a divide-by-zero bug will occur:
- div_bclk = mclk_rate / bclk_rate;
-
-To fix this possible bug, the function returns -EINVAL when bclk_rate is
-zero.
-
-Signed-off-by: Tuo Li
-Link: https://lore.kernel.org/r/TY2PR04MB4029799E60A5BCAAD5B7B5BBB8280@TY2PR04MB4029.apcprd04.prod.outlook.com
-Signed-off-by: Mark Brown
-(cherry picked from commit 375e2c352582442783178e6a33c279d6bc9354a2)
----
- sound/soc/rockchip/rockchip_i2s.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
-index d1438753edb4..593299675b8c 100644
---- a/sound/soc/rockchip/rockchip_i2s.c
-+++ b/sound/soc/rockchip/rockchip_i2s.c
-@@ -279,7 +279,7 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
- if (i2s->is_master_mode) {
- mclk_rate = clk_get_rate(i2s->mclk);
- bclk_rate = 2 * 32 * params_rate(params);
-- if (bclk_rate && mclk_rate % bclk_rate)
-+ if (bclk_rate == 0 || mclk_rate % bclk_rate)
- return -EINVAL;
-
- div_bclk = mclk_rate / bclk_rate;
-
-From ddbd68d0a7bc4931238977a1a6b35741c77c550c Mon Sep 17 00:00:00 2001
-From: Allen Pais
-Date: Mon, 31 Aug 2020 16:05:27 +0530
-Subject: [PATCH] dmaengine: pl330: convert tasklets to use new tasklet_setup()
- API
-
-In preparation for unconditionally passing the
-struct tasklet_struct pointer to all tasklet
-callbacks, switch to using the new tasklet_setup()
-and from_tasklet() to pass the tasklet pointer explicitly.
-
-Signed-off-by: Romain Perier
-Signed-off-by: Allen Pais
-Link: https://lore.kernel.org/r/20200831103542.305571-21-allen.lkml@gmail.com
-Signed-off-by: Vinod Koul
-(cherry picked from commit ab2a98ae4105d805383f840c54fabbb6560e2fc7)
----
- drivers/dma/pl330.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
-index 000c3c4b4f7a..d98fb318dd2d 100644
---- a/drivers/dma/pl330.c
-+++ b/drivers/dma/pl330.c
-@@ -1573,9 +1573,9 @@ static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
- tasklet_schedule(&pch->task);
- }
-
--static void pl330_dotask(unsigned long data)
-+static void pl330_dotask(struct tasklet_struct *t)
- {
-- struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
-+ struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks);
- unsigned long flags;
- int i;
-
-@@ -1979,7 +1979,7 @@ static int pl330_add(struct pl330_dmac *pl330)
- return ret;
- }
-
-- tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
-+ tasklet_setup(&pl330->tasks, pl330_dotask);
-
- pl330->state = INIT;
-
-@@ -2062,9 +2062,9 @@ static inline void fill_queue(struct dma_pl330_chan *pch)
- }
- }
-
--static void pl330_tasklet(unsigned long data)
-+static void pl330_tasklet(struct tasklet_struct *t)
- {
-- struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
-+ struct dma_pl330_chan *pch = from_tasklet(pch, t, task);
- struct dma_pl330_desc *desc, *_dt;
- unsigned long flags;
- bool power_down = false;
-@@ -2172,7 +2172,7 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
- return -ENOMEM;
- }
-
-- tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
-+ tasklet_setup(&pch->task, pl330_tasklet);
-
- spin_unlock_irqrestore(&pl330->lock, flags);
-
-
-From 1004f7a89c69a41e05bfb0e50b855192eb13def4 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski
-Date: Wed, 16 Sep 2020 18:17:40 +0200
-Subject: [PATCH] clk: rockchip: rk3308: drop unused mux_timer_src_p
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The parent names 'mux_timer_src_p' is not used:
-
- In file included from drivers/clk/rockchip/clk-rk3308.c:13:0:
- drivers/clk/rockchip/clk-rk3308.c:136:7: warning: ‘mux_timer_src_p’ defined but not used [-Wunused-const-variable=]
-
-Signed-off-by: Krzysztof Kozlowski
-Link: https://lore.kernel.org/r/20200916161740.14173-6-krzk@kernel.org
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 816e87253dec6686d2ef1bc2d84e82f033555046)
----
- drivers/clk/rockchip/clk-rk3308.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c
-index b0baf87a283e..5bf15f2a44b7 100644
---- a/drivers/clk/rockchip/clk-rk3308.c
-+++ b/drivers/clk/rockchip/clk-rk3308.c
-@@ -133,7 +133,6 @@ PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
- PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
- PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
- PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
--PNAME(mux_timer_src_p) = { "xin24m", "clk_rtc32k" };
- PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
- PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
- PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
-
-From 61d1828ae692430d8b032376bae59602398fdb36 Mon Sep 17 00:00:00 2001
-From: Elaine Zhang
-Date: Mon, 14 Sep 2020 10:22:20 +0800
-Subject: [PATCH] clk: rockchip: Use clk_hw_register_composite instead of
- clk_register_composite calls
-
-clk_hw_register_composite it's already exported.
-Preparation for compilation of rK common clock drivers into modules.
-
-Reported-by: kernel test robot
-Signed-off-by: Elaine Zhang
-Reviewed-by: Kever Yang
-Reviewed-by: Heiko Stuebner
-Reviewed-by: Stephen Boyd
-Link: https://lore.kernel.org/r/20200914022225.23613-2-zhangqing@rock-chips.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 63207c37eac4f15fdebac14685a315c259c0a780)
----
- drivers/clk/rockchip/clk-half-divider.c | 18 +++++-----
- drivers/clk/rockchip/clk.c | 61 ++++++++++++++++-----------------
- 2 files changed, 40 insertions(+), 39 deletions(-)
-
-diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
-index b333fc28c94b..e97fd3dfbae7 100644
---- a/drivers/clk/rockchip/clk-half-divider.c
-+++ b/drivers/clk/rockchip/clk-half-divider.c
-@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
- unsigned long flags,
- spinlock_t *lock)
- {
-- struct clk *clk = ERR_PTR(-ENOMEM);
-+ struct clk_hw *hw;
- struct clk_mux *mux = NULL;
- struct clk_gate *gate = NULL;
- struct clk_divider *div = NULL;
-@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
- div_ops = &clk_half_divider_ops;
- }
-
-- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-- mux ? &mux->hw : NULL, mux_ops,
-- div ? &div->hw : NULL, div_ops,
-- gate ? &gate->hw : NULL, gate_ops,
-- flags);
-+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
-+ mux ? &mux->hw : NULL, mux_ops,
-+ div ? &div->hw : NULL, div_ops,
-+ gate ? &gate->hw : NULL, gate_ops,
-+ flags);
-+ if (IS_ERR(hw))
-+ goto err_div;
-
-- return clk;
-+ return hw->clk;
- err_div:
- kfree(gate);
- err_gate:
- kfree(mux);
-- return ERR_PTR(-ENOMEM);
-+ return ERR_CAST(hw);
- }
-diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
-index 546e810c3560..46409972983e 100644
---- a/drivers/clk/rockchip/clk.c
-+++ b/drivers/clk/rockchip/clk.c
-@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
- u8 gate_shift, u8 gate_flags, unsigned long flags,
- spinlock_t *lock)
- {
-- struct clk *clk;
-+ struct clk_hw *hw;
- struct clk_mux *mux = NULL;
- struct clk_gate *gate = NULL;
- struct clk_divider *div = NULL;
-@@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const char *name,
- : &clk_divider_ops;
- }
-
-- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-- mux ? &mux->hw : NULL, mux_ops,
-- div ? &div->hw : NULL, div_ops,
-- gate ? &gate->hw : NULL, gate_ops,
-- flags);
--
-- if (IS_ERR(clk)) {
-- ret = PTR_ERR(clk);
-- goto err_composite;
-+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
-+ mux ? &mux->hw : NULL, mux_ops,
-+ div ? &div->hw : NULL, div_ops,
-+ gate ? &gate->hw : NULL, gate_ops,
-+ flags);
-+ if (IS_ERR(hw)) {
-+ kfree(div);
-+ kfree(gate);
-+ return ERR_CAST(hw);
- }
-
-- return clk;
--err_composite:
-- kfree(div);
-+ return hw->clk;
- err_div:
- kfree(gate);
- err_gate:
-@@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
- unsigned long flags, struct rockchip_clk_branch *child,
- spinlock_t *lock)
- {
-+ struct clk_hw *hw;
- struct rockchip_clk_frac *frac;
-- struct clk *clk;
- struct clk_gate *gate = NULL;
- struct clk_fractional_divider *div = NULL;
- const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
-@@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
- div->approximation = rockchip_fractional_approximation;
- div_ops = &clk_fractional_divider_ops;
-
-- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-- NULL, NULL,
-- &div->hw, div_ops,
-- gate ? &gate->hw : NULL, gate_ops,
-- flags | CLK_SET_RATE_UNGATE);
-- if (IS_ERR(clk)) {
-+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
-+ NULL, NULL,
-+ &div->hw, div_ops,
-+ gate ? &gate->hw : NULL, gate_ops,
-+ flags | CLK_SET_RATE_UNGATE);
-+ if (IS_ERR(hw)) {
- kfree(frac);
-- return clk;
-+ return ERR_CAST(hw);
- }
-
- if (child) {
-@@ -292,7 +290,7 @@ static struct clk *rockchip_clk_register_frac_branch(
- mux_clk = clk_register(NULL, &frac_mux->hw);
- if (IS_ERR(mux_clk)) {
- kfree(frac);
-- return clk;
-+ return mux_clk;
- }
-
- rockchip_clk_add_lookup(ctx, mux_clk, child->id);
-@@ -301,7 +299,7 @@ static struct clk *rockchip_clk_register_frac_branch(
- if (frac->mux_frac_idx >= 0) {
- pr_debug("%s: found fractional parent in mux at pos %d\n",
- __func__, frac->mux_frac_idx);
-- ret = clk_notifier_register(clk, &frac->clk_nb);
-+ ret = clk_notifier_register(hw->clk, &frac->clk_nb);
- if (ret)
- pr_err("%s: failed to register clock notifier for %s\n",
- __func__, name);
-@@ -311,7 +309,7 @@ static struct clk *rockchip_clk_register_frac_branch(
- }
- }
-
-- return clk;
-+ return hw->clk;
- }
-
- static struct clk *rockchip_clk_register_factor_branch(const char *name,
-@@ -320,7 +318,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
- int gate_offset, u8 gate_shift, u8 gate_flags,
- unsigned long flags, spinlock_t *lock)
- {
-- struct clk *clk;
-+ struct clk_hw *hw;
- struct clk_gate *gate = NULL;
- struct clk_fixed_factor *fix = NULL;
-
-@@ -349,16 +347,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
- fix->mult = mult;
- fix->div = div;
-
-- clk = clk_register_composite(NULL, name, parent_names, num_parents,
-- NULL, NULL,
-- &fix->hw, &clk_fixed_factor_ops,
-- &gate->hw, &clk_gate_ops, flags);
-- if (IS_ERR(clk)) {
-+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
-+ NULL, NULL,
-+ &fix->hw, &clk_fixed_factor_ops,
-+ &gate->hw, &clk_gate_ops, flags);
-+ if (IS_ERR(hw)) {
- kfree(fix);
- kfree(gate);
-+ return ERR_CAST(hw);
- }
-
-- return clk;
-+ return hw->clk;
- }
-
- struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
-
-From ec0b48760e3c0efb4522dfedf3a5088e538991c5 Mon Sep 17 00:00:00 2001
-From: Elaine Zhang
-Date: Mon, 14 Sep 2020 10:22:21 +0800
-Subject: [PATCH] clk: rockchip: Export rockchip_clk_register_ddrclk()
-
-This is used by the Rockchip clk driver, export it to allow that
-driver to be compiled as a module..
-
-Signed-off-by: Elaine Zhang
-Reviewed-by: Kever Yang
-Reviewed-by: Stephen Boyd
-Link: https://lore.kernel.org/r/20200914022225.23613-3-zhangqing@rock-chips.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit f73907de3493b94d80af5122bcacc98f0e7b295b)
----
- drivers/clk/rockchip/clk-ddr.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
-index 9273bce4d7b6..86718c54e56b 100644
---- a/drivers/clk/rockchip/clk-ddr.c
-+++ b/drivers/clk/rockchip/clk-ddr.c
-@@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
-
- return clk;
- }
-+EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
-
-From e2b0bd39722ef935b30bacf97a23446297169ac7 Mon Sep 17 00:00:00 2001
-From: Elaine Zhang
-Date: Mon, 14 Sep 2020 10:22:22 +0800
-Subject: [PATCH] clk: rockchip: Export rockchip_register_softrst()
-
-This is used by the Rockchip clk driver, export it to allow that
-driver to be compiled as a module..
-
-Signed-off-by: Elaine Zhang
-Reviewed-by: Kever Yang
-Reviewed-by: Stephen Boyd
-Link: https://lore.kernel.org/r/20200914022225.23613-4-zhangqing@rock-chips.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 37353491d1a8c207685c138c3640bd43864b70d9)
----
- drivers/clk/rockchip/softrst.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
-index 5f1ff5e47c4f..5d07266745b8 100644
---- a/drivers/clk/rockchip/softrst.c
-+++ b/drivers/clk/rockchip/softrst.c
-@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
- .deassert = rockchip_softrst_deassert,
- };
-
--void __init rockchip_register_softrst(struct device_node *np,
-- unsigned int num_regs,
-- void __iomem *base, u8 flags)
-+void rockchip_register_softrst(struct device_node *np,
-+ unsigned int num_regs,
-+ void __iomem *base, u8 flags)
- {
- struct rockchip_softrst *softrst;
- int ret;
-@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np,
- kfree(softrst);
- }
- };
-+EXPORT_SYMBOL_GPL(rockchip_register_softrst);
-
-From 8af53c34ecbf759fccf3769fa03d43db2ac554cb Mon Sep 17 00:00:00 2001
-From: Elaine Zhang
-Date: Mon, 14 Sep 2020 10:22:23 +0800
-Subject: [PATCH] clk: rockchip: Export some clock common APIs for module
- drivers
-
-This is used by the Rockchip clk driver, export it to allow that
-driver to be compiled as a module.
-
-Signed-off-by: Elaine Zhang
-Reviewed-by: Kever Yang
-Reviewed-by: Stephen Boyd
-Link: https://lore.kernel.org/r/20200914022225.23613-5-zhangqing@rock-chips.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit ea650c26611dd61adfcc8647d6144f2c9f453d90)
----
- drivers/clk/rockchip/clk.c | 52 ++++++++++++++++++++++++++--------------------
- 1 file changed, 30 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
-index 46409972983e..b443169dd408 100644
---- a/drivers/clk/rockchip/clk.c
-+++ b/drivers/clk/rockchip/clk.c
-@@ -360,8 +360,9 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
- return hw->clk;
- }
-
--struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
-- void __iomem *base, unsigned long nr_clks)
-+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
-+ void __iomem *base,
-+ unsigned long nr_clks)
- {
- struct rockchip_clk_provider *ctx;
- struct clk **clk_table;
-@@ -393,14 +394,16 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
- kfree(ctx);
- return ERR_PTR(-ENOMEM);
- }
-+EXPORT_SYMBOL_GPL(rockchip_clk_init);
-
--void __init rockchip_clk_of_add_provider(struct device_node *np,
-- struct rockchip_clk_provider *ctx)
-+void rockchip_clk_of_add_provider(struct device_node *np,
-+ struct rockchip_clk_provider *ctx)
- {
- if (of_clk_add_provider(np, of_clk_src_onecell_get,
- &ctx->clk_data))
- pr_err("%s: could not register clk provider\n", __func__);
- }
-+EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
-
- void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
- struct clk *clk, unsigned int id)
-@@ -408,8 +411,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
- if (ctx->clk_data.clks && id)
- ctx->clk_data.clks[id] = clk;
- }
-+EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
-
--void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
-+void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
- struct rockchip_pll_clock *list,
- unsigned int nr_pll, int grf_lock_offset)
- {
-@@ -432,11 +436,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
- rockchip_clk_add_lookup(ctx, clk, list->id);
- }
- }
-+EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
-
--void __init rockchip_clk_register_branches(
-- struct rockchip_clk_provider *ctx,
-- struct rockchip_clk_branch *list,
-- unsigned int nr_clk)
-+void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
-+ struct rockchip_clk_branch *list,
-+ unsigned int nr_clk)
- {
- struct clk *clk = NULL;
- unsigned int idx;
-@@ -565,14 +569,15 @@ void __init rockchip_clk_register_branches(
- rockchip_clk_add_lookup(ctx, clk, list->id);
- }
- }
--
--void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
-- unsigned int lookup_id,
-- const char *name, const char *const *parent_names,
-- u8 num_parents,
-- const struct rockchip_cpuclk_reg_data *reg_data,
-- const struct rockchip_cpuclk_rate_table *rates,
-- int nrates)
-+EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
-+
-+void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
-+ unsigned int lookup_id,
-+ const char *name, const char *const *parent_names,
-+ u8 num_parents,
-+ const struct rockchip_cpuclk_reg_data *reg_data,
-+ const struct rockchip_cpuclk_rate_table *rates,
-+ int nrates)
- {
- struct clk *clk;
-
-@@ -587,9 +592,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
-
- rockchip_clk_add_lookup(ctx, clk, lookup_id);
- }
-+EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
-
--void __init rockchip_clk_protect_critical(const char *const clocks[],
-- int nclocks)
-+void rockchip_clk_protect_critical(const char *const clocks[],
-+ int nclocks)
- {
- int i;
-
-@@ -601,6 +607,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
- clk_prepare_enable(clk);
- }
- }
-+EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
-
- static void __iomem *rst_base;
- static unsigned int reg_restart;
-@@ -620,10 +627,10 @@ static struct notifier_block rockchip_restart_handler = {
- .priority = 128,
- };
-
--void __init
-+void
- rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
-- unsigned int reg,
-- void (*cb)(void))
-+ unsigned int reg,
-+ void (*cb)(void))
- {
- int ret;
-
-@@ -635,3 +642,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
- pr_err("%s: cannot register restart handler, %d\n",
- __func__, ret);
- }
-+EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);
-
-From c71d3c0979104408630b2c540ae383b1ff0d4dd3 Mon Sep 17 00:00:00 2001
-From: Elaine Zhang
-Date: Mon, 14 Sep 2020 10:23:04 +0800
-Subject: [PATCH] clk: rockchip: fix the clk config to support module build
-
-use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
-use CONFIG_CLK_RKXX for Rk soc clk driver.
-Mark CONFIG_CLK_RK3399 to "tristate",
-to support building Rk3399 SoC clock driver as module.
-
-Signed-off-by: Elaine Zhang
-Reviewed-by: Kever Yang
-Reviewed-by: Stephen Boyd
-Link: https://lore.kernel.org/r/20200914022304.23908-1-zhangqing@rock-chips.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 4d98ed1e126495016f2a3ef4db6379855c4aacf2)
----
- drivers/clk/Kconfig | 1 +
- drivers/clk/rockchip/Kconfig | 78 +++++++++++++++++++++++++++++++++++++++++++
- drivers/clk/rockchip/Makefile | 42 ++++++++++++-----------
- 3 files changed, 101 insertions(+), 20 deletions(-)
- create mode 100644 drivers/clk/rockchip/Kconfig
-
-diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
-index 4026fac9fac3..b41aaed9bd51 100644
---- a/drivers/clk/Kconfig
-+++ b/drivers/clk/Kconfig
-@@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig"
- source "drivers/clk/mvebu/Kconfig"
- source "drivers/clk/qcom/Kconfig"
- source "drivers/clk/renesas/Kconfig"
-+source "drivers/clk/rockchip/Kconfig"
- source "drivers/clk/samsung/Kconfig"
- source "drivers/clk/sifive/Kconfig"
- source "drivers/clk/sprd/Kconfig"
-diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
-new file mode 100644
-index 000000000000..524b0e0df0a7
---- /dev/null
-+++ b/drivers/clk/rockchip/Kconfig
-@@ -0,0 +1,78 @@
-+# SPDX-License-Identifier: GPL-2.0
-+# common clock support for ROCKCHIP SoC family.
-+
-+config COMMON_CLK_ROCKCHIP
-+ bool "Rockchip clock controller common support"
-+ depends on ARCH_ROCKCHIP
-+ default ARCH_ROCKCHIP
-+ help
-+ Say y here to enable common clock controller for Rockchip platforms.
-+
-+if COMMON_CLK_ROCKCHIP
-+config CLK_PX30
-+ bool "Rockchip PX30 clock controller support"
-+ default y
-+ help
-+ Build the driver for PX30 Clock Driver.
-+
-+config CLK_RV110X
-+ bool "Rockchip RV110x clock controller support"
-+ default y
-+ help
-+ Build the driver for RV110x Clock Driver.
-+
-+config CLK_RK3036
-+ bool "Rockchip RK3036 clock controller support"
-+ default y
-+ help
-+ Build the driver for RK3036 Clock Driver.
-+
-+config CLK_RK312X
-+ bool "Rockchip RK312x clock controller support"
-+ default y
-+ help
-+ Build the driver for RK312x Clock Driver.
-+
-+config CLK_RK3188
-+ bool "Rockchip RK3188 clock controller support"
-+ default y
-+ help
-+ Build the driver for RK3188 Clock Driver.
-+
-+config CLK_RK322X
-+ bool "Rockchip RK322x clock controller support"
-+ default y
-+ help
-+ Build the driver for RK322x Clock Driver.
-+
-+config CLK_RK3288
-+ bool "Rockchip RK3288 clock controller support"
-+ depends on ARM
-+ default y
-+ help
-+ Build the driver for RK3288 Clock Driver.
-+
-+config CLK_RK3308
-+ bool "Rockchip RK3308 clock controller support"
-+ default y
-+ help
-+ Build the driver for RK3308 Clock Driver.
-+
-+config CLK_RK3328
-+ bool "Rockchip RK3328 clock controller support"
-+ default y
-+ help
-+ Build the driver for RK3328 Clock Driver.
-+
-+config CLK_RK3368
-+ bool "Rockchip RK3368 clock controller support"
-+ default y
-+ help
-+ Build the driver for RK3368 Clock Driver.
-+
-+config CLK_RK3399
-+ bool "Rockchip RK3399 clock controller support"
-+ default y
-+ help
-+ Build the driver for RK3399 Clock Driver.
-+endif
-diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
-index 7c5b5813a87c..a99e4d9bbae1 100644
---- a/drivers/clk/rockchip/Makefile
-+++ b/drivers/clk/rockchip/Makefile
-@@ -3,24 +3,26 @@
- # Rockchip Clock specific Makefile
- #
-
--obj-y += clk.o
--obj-y += clk-pll.o
--obj-y += clk-cpu.o
--obj-y += clk-half-divider.o
--obj-y += clk-inverter.o
--obj-y += clk-mmc-phase.o
--obj-y += clk-muxgrf.o
--obj-y += clk-ddr.o
--obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
-+obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
-
--obj-y += clk-px30.o
--obj-y += clk-rv1108.o
--obj-y += clk-rk3036.o
--obj-y += clk-rk3128.o
--obj-y += clk-rk3188.o
--obj-y += clk-rk3228.o
--obj-y += clk-rk3288.o
--obj-y += clk-rk3308.o
--obj-y += clk-rk3328.o
--obj-y += clk-rk3368.o
--obj-y += clk-rk3399.o
-+clk-rockchip-y += clk.o
-+clk-rockchip-y += clk-pll.o
-+clk-rockchip-y += clk-cpu.o
-+clk-rockchip-y += clk-half-divider.o
-+clk-rockchip-y += clk-inverter.o
-+clk-rockchip-y += clk-mmc-phase.o
-+clk-rockchip-y += clk-muxgrf.o
-+clk-rockchip-y += clk-ddr.o
-+clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
-+
-+obj-$(CONFIG_CLK_PX30) += clk-px30.o
-+obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
-+obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
-+obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
-+obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
-+obj-$(CONFIG_CLK_RK322X) += clk-rk3228.o
-+obj-$(CONFIG_CLK_RK3288) += clk-rk3288.o
-+obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
-+obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
-+obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
-+obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
-
-From 640cf0e121d7879899d26bce21b5c7d954f67b09 Mon Sep 17 00:00:00 2001
-From: Elaine Zhang
-Date: Mon, 14 Sep 2020 10:23:16 +0800
-Subject: [PATCH] clk: rockchip: rk3399: Support module build
-
-support CLK_OF_DECLARE and builtin_platform_driver_probe
-double clk init method.
-add module author, description and license to support building
-Soc Rk3399 clock driver as module.
-
-Signed-off-by: Elaine Zhang
-Reviewed-by: Kever Yang
-Reviewed-by: Stephen Boyd
-Link: https://lore.kernel.org/r/20200914022316.24045-1-zhangqing@rock-chips.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 70d839e2761d22eba6facdb3b65faea4d57f355d)
----
- drivers/clk/rockchip/Kconfig | 2 +-
- drivers/clk/rockchip/clk-rk3399.c | 56 +++++++++++++++++++++++++++++++++++++++
- 2 files changed, 57 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
-index 524b0e0df0a7..47cd6c5de837 100644
---- a/drivers/clk/rockchip/Kconfig
-+++ b/drivers/clk/rockchip/Kconfig
-@@ -71,7 +71,7 @@ config CLK_RK3368
- Build the driver for RK3368 Clock Driver.
-
- config CLK_RK3399
-- bool "Rockchip RK3399 clock controller support"
-+ tristate "Rockchip RK3399 clock controller support"
- default y
- help
- Build the driver for RK3399 Clock Driver.
-diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
-index ce1d2446f142..7df2f1e00347 100644
---- a/drivers/clk/rockchip/clk-rk3399.c
-+++ b/drivers/clk/rockchip/clk-rk3399.c
-@@ -5,9 +5,11 @@
- */
-
- #include
-+#include
- #include
- #include
- #include
-+#include
- #include
- #include
- #include
-@@ -1600,3 +1602,57 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
- rockchip_clk_of_add_provider(np, ctx);
- }
- CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
-+
-+struct clk_rk3399_inits {
-+ void (*inits)(struct device_node *np);
-+};
-+
-+static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
-+ .inits = rk3399_pmu_clk_init,
-+};
-+
-+static const struct clk_rk3399_inits clk_rk3399_cru_init = {
-+ .inits = rk3399_clk_init,
-+};
-+
-+static const struct of_device_id clk_rk3399_match_table[] = {
-+ {
-+ .compatible = "rockchip,rk3399-cru",
-+ .data = &clk_rk3399_cru_init,
-+ }, {
-+ .compatible = "rockchip,rk3399-pmucru",
-+ .data = &clk_rk3399_pmucru_init,
-+ },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
-+
-+static int __init clk_rk3399_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ const struct of_device_id *match;
-+ const struct clk_rk3399_inits *init_data;
-+
-+ match = of_match_device(clk_rk3399_match_table, &pdev->dev);
-+ if (!match || !match->data)
-+ return -EINVAL;
-+
-+ init_data = match->data;
-+ if (init_data->inits)
-+ init_data->inits(np);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver clk_rk3399_driver = {
-+ .driver = {
-+ .name = "clk-rk3399",
-+ .of_match_table = clk_rk3399_match_table,
-+ .suppress_bind_attrs = true,
-+ },
-+};
-+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
-+
-+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:clk-rk3399");
-
-From 2862d98b5f5d3682afe09bab8fc29c982e3ac0fe Mon Sep 17 00:00:00 2001
-From: David Bauer
-Date: Sun, 20 Sep 2020 17:45:27 +0200
-Subject: [PATCH] dt-bindings: Add doc for FriendlyARM NanoPi R2S
-
-Add devicetree binding documentation for the FriendlyARM NanoPi R2S.
-
-Signed-off-by: David Bauer
-Reviewed-by: Rob Herring
-Link: https://lore.kernel.org/r/20200920154528.88185-1-mail@david-bauer.net
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 8cfcf3279419acbf2d2c471262bfb18d9e175fc9)
----
- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
-index 251c3ca22e1b..65b4cc2c63f7 100644
---- a/Documentation/devicetree/bindings/arm/rockchip.yaml
-+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
-@@ -104,6 +104,11 @@ properties:
- - firefly,roc-rk3399-pc-mezzanine
- - const: rockchip,rk3399
-
-+ - description: FriendlyElec NanoPi R2S
-+ items:
-+ - const: friendlyarm,nanopi-r2s
-+ - const: rockchip,rk3328
-+
- - description: FriendlyElec NanoPi4 series boards
- items:
- - enum:
-
-From 6b865e0835b1517ed2e7d44feb819f83ce3bc138 Mon Sep 17 00:00:00 2001
-From: David Bauer
-Date: Sun, 20 Sep 2020 17:45:28 +0200
-Subject: [PATCH] arm64: dts: rockchip: Add support for FriendlyARM NanoPi R2S
-
-This adds support for the NanoPi R2S from FriendlyARM.
-
-Rockchip RK3328 SoC
-1GB DDR4 RAM
-Gigabit Ethernet (WAN)
-Gigabit Ethernet (USB3) (LAN)
-USB 2.0 Host Port
-MicroSD slot
-Reset button
-WAN - LAN - SYS LED
-
-Signed-off-by: David Bauer
-Link: https://lore.kernel.org/r/20200920154528.88185-2-mail@david-bauer.net
-[adapted from sdmmc0m1_gpio to renamed sdmmc0m1_pin]
-Reported-by: kernel test robot
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit f1ec83f880dbeaceb10d33c40c47aa1769b787e8)
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 368 +++++++++++++++++++++
- 2 files changed, 369 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index d53efdf4cb5a..26661c7b736b 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-new file mode 100644
-index 000000000000..be7a31d81632
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -0,0 +1,368 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2020 David Bauer
-+ */
-+
-+/dts-v1/;
-+
-+#include
-+#include
-+#include "rk3328.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R2S";
-+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ gmac_clk: gmac-clock {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac_clk";
-+ #clock-cells = <0>;
-+ };
-+
-+ keys {
-+ compatible = "gpio-keys";
-+ pinctrl-0 = <&reset_button_pin>;
-+ pinctrl-names = "default";
-+
-+ reset {
-+ label = "reset";
-+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
-+ linux,code = ;
-+ debounce-interval = <50>;
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-+ pinctrl-names = "default";
-+
-+ lan_led: led-0 {
-+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ label = "nanopi-r2s:green:lan";
-+ };
-+
-+ sys_led: led-1 {
-+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ label = "nanopi-r2s:red:sys";
-+ };
-+
-+ wan_led: led-2 {
-+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+ label = "nanopi-r2s:green:wan";
-+ };
-+ };
-+
-+ vcc_io_sdio: sdmmcio-regulator {
-+ compatible = "regulator-gpio";
-+ enable-active-high;
-+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
-+ pinctrl-0 = <&sdio_vcc_pin>;
-+ pinctrl-names = "default";
-+ regulator-name = "vcc_io_sdio";
-+ regulator-always-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-settling-time-us = <5000>;
-+ regulator-type = "voltage";
-+ startup-delay-us = <2000>;
-+ states = <1800000 0x1
-+ 3300000 0x0>;
-+ vin-supply = <&vcc_io_33>;
-+ };
-+
-+ vcc_sd: sdmmc-regulator {
-+ compatible = "regulator-fixed";
-+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+ pinctrl-0 = <&sdmmc0m1_pin>;
-+ pinctrl-names = "default";
-+ regulator-name = "vcc_sd";
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc_io_33>;
-+ };
-+
-+ vdd_5v: vdd-5v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd_5v";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&gmac2io {
-+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-+ clock_in_out = "input";
-+ phy-handle = <&rtl8211e>;
-+ phy-mode = "rgmii";
-+ phy-supply = <&vcc_io_33>;
-+ pinctrl-0 = <&rgmiim1_pins>;
-+ pinctrl-names = "default";
-+ rx_delay = <0x18>;
-+ snps,aal;
-+ tx_delay = <0x24>;
-+ status = "okay";
-+
-+ mdio {
-+ compatible = "snps,dwmac-mdio";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rtl8211e: ethernet-phy@1 {
-+ reg = <1>;
-+ pinctrl-0 = <ð_phy_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <10000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
-+
-+&i2c1 {
-+ status = "okay";
-+
-+ rk805: pmic@18 {
-+ compatible = "rockchip,rk805";
-+ reg = <0x18>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ clock-output-names = "xin32k", "rk805-clkout2";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ pinctrl-0 = <&pmic_int_l>;
-+ pinctrl-names = "default";
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vdd_5v>;
-+ vcc2-supply = <&vdd_5v>;
-+ vcc3-supply = <&vdd_5v>;
-+ vcc4-supply = <&vdd_5v>;
-+ vcc5-supply = <&vcc_io_33>;
-+ vcc6-supply = <&vdd_5v>;
-+
-+ regulators {
-+ vdd_log: DCDC_REG1 {
-+ regulator-name = "vdd_log";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1450000>;
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1000000>;
-+ };
-+ };
-+
-+ vdd_arm: DCDC_REG2 {
-+ regulator-name = "vdd_arm";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1450000>;
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <950000>;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_io_33: DCDC_REG4 {
-+ regulator-name = "vcc_io_33";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc_18: LDO_REG1 {
-+ regulator-name = "vcc_18";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc18_emmc: LDO_REG2 {
-+ regulator-name = "vcc18_emmc";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd_10: LDO_REG3 {
-+ regulator-name = "vdd_10";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1000000>;
-+ regulator-max-microvolt = <1000000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1000000>;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&io_domains {
-+ pmuio-supply = <&vcc_io_33>;
-+ vccio1-supply = <&vcc_io_33>;
-+ vccio2-supply = <&vcc18_emmc>;
-+ vccio3-supply = <&vcc_io_sdio>;
-+ vccio4-supply = <&vcc_18>;
-+ vccio5-supply = <&vcc_io_33>;
-+ vccio6-supply = <&vcc_io_33>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ button {
-+ reset_button_pin: reset-button-pin {
-+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ ethernet-phy {
-+ eth_phy_reset_pin: eth-phy-reset-pin {
-+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+
-+ leds {
-+ lan_led_pin: lan-led-pin {
-+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ sys_led_pin: sys-led-pin {
-+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ sd {
-+ sdio_vcc_pin: sdio-vcc-pin {
-+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+ pinctrl-names = "default";
-+ sd-uhs-sdr12;
-+ sd-uhs-sdr25;
-+ sd-uhs-sdr50;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_sd>;
-+ vqmmc-supply = <&vcc_io_sdio>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <0>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&u2phy {
-+ status = "okay";
-+};
-+
-+&u2phy_host {
-+ status = "okay";
-+};
-+
-+&u2phy_otg {
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb20_otg {
-+ status = "okay";
-+ dr_mode = "host";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-
-From f18092b21f3ea3ed7d134b274c64c8edde1fcb30 Mon Sep 17 00:00:00 2001
-From: Artem Lapkin
-Date: Wed, 23 Sep 2020 21:08:22 +0800
-Subject: [PATCH] arm64: dts: rockchip: add spiflash node to rk3399-khadas-edge
-
-The Khadas Edge Boards uses winbond - w25q128 spi flash with 104Mhz
-
-Signed-off-by: Artem Lapkin
-Link: https://lore.kernel.org/r/20200923130823.1612533-2-art@khadas.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 5d71f44569941386b419398463166fdf1785f4e2)
----
- arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
-index e36837c04dc7..c67420578fac 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
-@@ -690,6 +690,16 @@
- status = "okay";
- };
-
-+&spi1 {
-+ status = "okay";
-+
-+ spiflash: flash@0 {
-+ compatible = "winbond,w25q128fw", "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <104000000>;
-+ };
-+};
-+
- &tcphy0 {
- status = "okay";
- };
-
-From e2cad982d40449e0839c6de164a34a1d2e23d694 Mon Sep 17 00:00:00 2001
-From: Artem Lapkin
-Date: Wed, 23 Sep 2020 21:08:23 +0800
-Subject: [PATCH] arm64: dts: rockchip: add ir-receiver node to
- rk3399-khadas-edge
-
-add missed ir-receiver and ir_rx pinctl nodes to rk3399-khadas-edge
-Khadas Edge board uses gpio-ir-receiver on RK_PB6 gpio
-
-Signed-off-by: Artem Lapkin
-Link: https://lore.kernel.org/r/20200923130823.1612533-3-art@khadas.com
-Signed-off-by: Heiko Stuebner
-(cherry picked from commit 30a9a8c16865d37bfc0f1859a398ba1b24eec569)
----
- arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
-index c67420578fac..635afdd99122 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
-@@ -138,6 +138,14 @@
- };
- };
-
-+ ir-receiver {
-+ compatible = "gpio-ir-receiver";
-+ gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
-+ linux,rc-map-name = "rc-khadas";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ir_rx>;
-+ };
-+
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
-@@ -585,6 +593,12 @@
- };
- };
-
-+ ir {
-+ ir_rx: ir-rx {
-+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- leds {
- sys_led_pin: sys-led-pin {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-
-From d9ffbaa89722fee3ef963646ea2423ac84f78854 Mon Sep 17 00:00:00 2001
-From: Stephen Boyd
-Date: Wed, 23 Sep 2020 17:41:44 -0700
-Subject: [PATCH] clk: rockchip: Initialize hw to error to avoid undefined
- behavior
-
-We can get down to this return value from ERR_CAST() without
-initializing hw. Set it to -ENOMEM so that we always return something
-sane.
-
-Fixes the following smatch warning:
-
-drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'.
-drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST'
-
-Cc: Elaine Zhang
-Cc: Heiko Stuebner
-Fixes: 956060a52795 ("clk: rockchip: add support for half divider")
-Signed-off-by: Stephen Boyd
-(cherry picked from commit f8ac4db0e23c15baa3f379d4f7e007589d7710ed)
----
- drivers/clk/rockchip/clk-half-divider.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
-index e97fd3dfbae7..ccd5c270c213 100644
---- a/drivers/clk/rockchip/clk-half-divider.c
-+++ b/drivers/clk/rockchip/clk-half-divider.c
-@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
- unsigned long flags,
- spinlock_t *lock)
- {
-- struct clk_hw *hw;
-+ struct clk_hw *hw = ERR_PTR(-ENOMEM);
- struct clk_mux *mux = NULL;
- struct clk_gate *gate = NULL;
- struct clk_divider *div = NULL;
-
-From aadd7a83a8a1e799653d9df0cc99bb0633515fbf Mon Sep 17 00:00:00 2001
-From: Vinod Koul
-Date: Wed, 30 Sep 2020 17:47:35 +0530
-Subject: [PATCH] dmaengine: pl330: fix argument for tasklet
-
-Commit 59cd818763e8 ("dmaengine: fsl: convert tasklets to use new
-tasklet_setup() API") converted the pl330 driver to use new tasklet
-functions but missed that driver calls the tasklet function directly as
-well, so update it.
-
-Fixes: 59cd818763e8 ("dmaengine: fsl: convert tasklets to use new tasklet_setup() API")
-Reported-by: kernel test robot
-Link: https://lore.kernel.org/r/20200930121735.49699-1-vkoul@kernel.org
-Signed-off-by: Vinod Koul
-(cherry picked from commit 86ae924a91a4a4297ad9f47e131f74b1dab6cb7a)
----
- drivers/dma/pl330.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
-index d98fb318dd2d..e9f0101d92fa 100644
---- a/drivers/dma/pl330.c
-+++ b/drivers/dma/pl330.c
-@@ -2484,7 +2484,7 @@ static void pl330_issue_pending(struct dma_chan *chan)
- list_splice_tail_init(&pch->submitted_list, &pch->work_list);
- spin_unlock_irqrestore(&pch->lock, flags);
-
-- pl330_tasklet((unsigned long)pch);
-+ pl330_tasklet(&pch->task);
- }
-
- /*
diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch
new file mode 100644
index 0000000000..27c10f1ff3
--- /dev/null
+++ b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch
@@ -0,0 +1,3068 @@
+From 7bdda3f24987c034767b0834a63bd0379301553a Mon Sep 17 00:00:00 2001
+From: Robin Murphy
+Date: Mon, 26 Oct 2020 11:17:20 +0000
+Subject: [PATCH] clk: rockchip: Add appropriate arch dependencies
+
+There's no point offering support for 32-bit platforms to users
+configuring a 64-bit kernel - and vice-versa - unless they are
+explicitly interested in compile-testing.
+
+Signed-off-by: Robin Murphy
+Link: https://lore.kernel.org/r/72abb0f794b8ed77e274e8ee21c22e0bd3223dfd.1603710913.git.robin.murphy@arm.com
+Signed-off-by: Heiko Stuebner
+---
+ drivers/clk/rockchip/Kconfig | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
+index 47cd6c5de837..effd05032e85 100644
+--- a/drivers/clk/rockchip/Kconfig
++++ b/drivers/clk/rockchip/Kconfig
+@@ -11,67 +11,77 @@ config COMMON_CLK_ROCKCHIP
+ if COMMON_CLK_ROCKCHIP
+ config CLK_PX30
+ bool "Rockchip PX30 clock controller support"
++ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for PX30 Clock Driver.
+
+ config CLK_RV110X
+ bool "Rockchip RV110x clock controller support"
++ depends on (ARM || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RV110x Clock Driver.
+
+ config CLK_RK3036
+ bool "Rockchip RK3036 clock controller support"
++ depends on (ARM || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3036 Clock Driver.
+
+ config CLK_RK312X
+ bool "Rockchip RK312x clock controller support"
++ depends on (ARM || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK312x Clock Driver.
+
+ config CLK_RK3188
+ bool "Rockchip RK3188 clock controller support"
++ depends on (ARM || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3188 Clock Driver.
+
+ config CLK_RK322X
+ bool "Rockchip RK322x clock controller support"
++ depends on (ARM || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK322x Clock Driver.
+
+ config CLK_RK3288
+ bool "Rockchip RK3288 clock controller support"
+- depends on ARM
++ depends on (ARM || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3288 Clock Driver.
+
+ config CLK_RK3308
+ bool "Rockchip RK3308 clock controller support"
++ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3308 Clock Driver.
+
+ config CLK_RK3328
+ bool "Rockchip RK3328 clock controller support"
++ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3328 Clock Driver.
+
+ config CLK_RK3368
+ bool "Rockchip RK3368 clock controller support"
++ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3368 Clock Driver.
+
+ config CLK_RK3399
+ tristate "Rockchip RK3399 clock controller support"
++ depends on (ARM64 || COMPILE_TEST)
+ default y
+ help
+ Build the driver for RK3399 Clock Driver.
+
+From 7a9ce2f8a4e405c67287b076e07420766c33f1e6 Mon Sep 17 00:00:00 2001
+From: Xu Wang
+Date: Fri, 27 Nov 2020 09:05:51 +0000
+Subject: [PATCH] clk: rockchip: Remove redundant null check before
+ clk_prepare_enable
+
+Because clk_prepare_enable() already checked NULL clock parameter,
+so the additional check is unnecessary, just remove it.
+
+Signed-off-by: Xu Wang
+Acked-by: Stephen Boyd
+Link: https://lore.kernel.org/r/20201127090551.50254-1-vulab@iscas.ac.cn
+Signed-off-by: Heiko Stuebner
+---
+ drivers/clk/rockchip/clk.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
+index b443169dd408..336481bc6cc7 100644
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -603,8 +603,7 @@ void rockchip_clk_protect_critical(const char *const clocks[],
+ for (i = 0; i < nclocks; i++) {
+ struct clk *clk = __clk_lookup(clocks[i]);
+
+- if (clk)
+- clk_prepare_enable(clk);
++ clk_prepare_enable(clk);
+ }
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
+
+From 4e5568fccbf904926141cf11aa5ae5e6870ce1c8 Mon Sep 17 00:00:00 2001
+From: Johan Jonker
+Date: Wed, 18 Nov 2020 14:58:16 +0100
+Subject: [PATCH] clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a
+ i2s and uart clocks
+
+Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks,
+so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX
+also update.
+
+Signed-off-by: Johan Jonker
+Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com
+Signed-off-by: Heiko Stuebner
+---
+ drivers/clk/rockchip/clk-rk3188.c | 28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
+index 730020fcc7fe..db8c588139de 100644
+--- a/drivers/clk/rockchip/clk-rk3188.c
++++ b/drivers/clk/rockchip/clk-rk3188.c
+@@ -255,19 +255,19 @@ static struct rockchip_clk_branch common_spdif_fracmux __initdata =
+ RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch common_uart0_fracmux __initdata =
+- MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
++ MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch common_uart1_fracmux __initdata =
+- MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
++ MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch common_uart2_fracmux __initdata =
+- MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
++ MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch common_uart3_fracmux __initdata =
+- MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
++ MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+@@ -408,28 +408,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+ COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
+ RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 8, GFLAGS),
+- COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
++ COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(17), 0,
+ RK2928_CLKGATE_CON(1), 9, GFLAGS,
+ &common_uart0_fracmux),
+ COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
+ RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 10, GFLAGS),
+- COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
++ COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(18), 0,
+ RK2928_CLKGATE_CON(1), 11, GFLAGS,
+ &common_uart1_fracmux),
+ COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
+ RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 12, GFLAGS),
+- COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
++ COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(19), 0,
+ RK2928_CLKGATE_CON(1), 13, GFLAGS,
+ &common_uart2_fracmux),
+ COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
+ RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 14, GFLAGS),
+- COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
++ COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(20), 0,
+ RK2928_CLKGATE_CON(1), 15, GFLAGS,
+ &common_uart3_fracmux),
+@@ -543,15 +543,15 @@ static struct clk_div_table div_aclk_cpu_t[] = {
+ };
+
+ static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
+- MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
++ MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
+- MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
++ MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
+- MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
++ MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
+
+ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
+@@ -615,21 +615,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
+ COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
+ RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(0), 7, GFLAGS),
+- COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
++ COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(6), 0,
+ RK2928_CLKGATE_CON(0), 8, GFLAGS,
+ &rk3066a_i2s0_fracmux),
+ COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
+ RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(0), 9, GFLAGS),
+- COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
++ COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(7), 0,
+ RK2928_CLKGATE_CON(0), 10, GFLAGS,
+ &rk3066a_i2s1_fracmux),
+ COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
+ RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(0), 11, GFLAGS),
+- COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
++ COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(8), 0,
+ RK2928_CLKGATE_CON(0), 12, GFLAGS,
+ &rk3066a_i2s2_fracmux),
+
+From e09debc09e9dfe38b0347be56d5dc63e1a567f8b Mon Sep 17 00:00:00 2001
+From: Johan Jonker
+Date: Wed, 18 Nov 2020 14:58:17 +0100
+Subject: [PATCH] clk: rockchip: fix i2s gate bits on rk3066 and rk3188
+
+The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON:
+
+hclk_i2s_8ch_gate_en bit 4 (dtsi: i2s0)
+hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1)
+hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2)
+
+The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON:
+
+hclk_i2s_2ch_gate_en bit 2 (dtsi: i2s0)
+
+The bits got somehow mixed up in the clk-rk3188.c file.
+The labels in the dtsi files are not suppose to change.
+The sclk and hclk names should match for
+"trace_event=clk_disable,clk_enable",
+so remove GATE HCLK_I2S0 from the common clock tree and
+fix the bits in the rk3066 and rk3188 clock tree.
+
+Signed-off-by: Johan Jonker
+Link: https://lore.kernel.org/r/20201118135822.9582-3-jbx6244@gmail.com
+Signed-off-by: Heiko Stuebner
+---
+ drivers/clk/rockchip/clk-rk3188.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
+index db8c588139de..0b76ad34de00 100644
+--- a/drivers/clk/rockchip/clk-rk3188.c
++++ b/drivers/clk/rockchip/clk-rk3188.c
+@@ -449,7 +449,6 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
+
+ /* hclk_cpu gates */
+ GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
+- GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
+ GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
+ /* hclk_ahb2apb is part of a clk branch */
+@@ -634,8 +633,9 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
+ RK2928_CLKGATE_CON(0), 12, GFLAGS,
+ &rk3066a_i2s2_fracmux),
+
+- GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
+- GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
++ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
++ GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
++ GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
+ GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
+
+@@ -728,6 +728,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
+ RK2928_CLKGATE_CON(0), 10, GFLAGS,
+ &rk3188_i2s0_fracmux),
+
++ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
+ GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
+ GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
+
+
+From c14cd8d58bb0d1b71a501d20b61752c0115aa1d6 Mon Sep 17 00:00:00 2001
+From: Alexandru Stan
+Date: Wed, 21 Oct 2020 22:04:43 -0700
+Subject: [PATCH] ARM: dts: rockchip: Remove 0 point from brightness-levels on
+ rk3288-veyron
+
+The extra 0 only adds one point in the userspace visible range,
+so this change is almost a noop with the current driver behavior.
+
+We don't need the 0% point, userspace seems to handle this just fine
+because it uses the bl_power property to turn off the display.
+
+Furthermore after adding "backlight: pwm_bl: Fix interpolation" patch,
+the backlight interpolation will work a little differently. So we need
+to preemptively remove the 0-3 segment since otherwise we would have a
+252 long interpolation that would slowly go between 0 and 3, looking
+really bad in userspace. So it's almost a noop/cleanup now, but it will
+be required in the future.
+
+Signed-off-by: Alexandru Stan
+Reviewed-by: Douglas Anderson
+Acked-by: Daniel Thompson
+Link: https://lore.kernel.org/r/20201021220404.v3.1.I96b8d872ec51171f19274e43e96cadc092881271@changeid
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm/boot/dts/rk3288-veyron-jaq.dts | 2 +-
+ arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 +-
+ arch/arm/boot/dts/rk3288-veyron-tiger.dts | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+index af77ab20586d..4a148cf1defc 100644
+--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
++++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+@@ -20,7 +20,7 @@ / {
+
+ &backlight {
+ /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
+- brightness-levels = <0 8 255>;
++ brightness-levels = <8 255>;
+ num-interpolated-steps = <247>;
+ };
+
+diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+index f8b69e0a16a0..82fc6fba9999 100644
+--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
++++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+@@ -39,7 +39,7 @@ volum_up {
+
+ &backlight {
+ /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
+- brightness-levels = <0 3 255>;
++ brightness-levels = <3 255>;
+ num-interpolated-steps = <252>;
+ };
+
+diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts
+index 069f0c2c1fdf..52a84cbe7a90 100644
+--- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts
++++ b/arch/arm/boot/dts/rk3288-veyron-tiger.dts
+@@ -23,7 +23,7 @@ / {
+
+ &backlight {
+ /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */
+- brightness-levels = <0 3 255>;
++ brightness-levels = <3 255>;
+ num-interpolated-steps = <252>;
+ };
+
+
+From f4993c1a24b4ecfc6253cc7e82a759bcc9891b1a Mon Sep 17 00:00:00 2001
+From: Johan Jonker
+Date: Mon, 16 Nov 2020 16:07:56 +0100
+Subject: [PATCH] ARM: dts: rockchip: rename wdt nodename to watchdog on rv1108
+
+A test with the command below gives for example this error:
+
+/arch/arm/boot/dts/rv1108-evb.dt.yaml:
+wdt@10360000: $nodename:0: 'wdt@10360000'
+does not match '^watchdog(@.*|-[0-9a-f])?$'
+
+Fix it by renaming the wdt nodename to watchdog
+in the rv1108.dtsi file.
+
+make ARCH=arm dtbs_check
+DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
+
+Signed-off-by: Johan Jonker
+Link: https://lore.kernel.org/r/20201116150756.14265-1-jbx6244@gmail.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm/boot/dts/rv1108.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
+index a1a08cb9364e..e491964b1c3d 100644
+--- a/arch/arm/boot/dts/rv1108.dtsi
++++ b/arch/arm/boot/dts/rv1108.dtsi
+@@ -299,7 +299,7 @@ timer: timer@10350000 {
+ clock-names = "timer", "pclk";
+ };
+
+- watchdog: wdt@10360000 {
++ watchdog: watchdog@10360000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10360000 0x100>;
+ interrupts = ;
+
+From 4d7bc6b808cb61c7803049b0dc71e93202089e1f Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Mon, 30 Nov 2020 14:28:14 +0100
+Subject: [PATCH] ARM: dts: rockchip: Add rtc node for VMARC SOM
+
+Add the hym8563 rtc found on the rk3288 variant of the VMARC SOM.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com
+[split out of the original patch, as it was a change unrelated
+ to the commit description]
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
+index 4a373f5aa600..da80bfd5f2d5 100644
+--- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
++++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
+@@ -231,6 +231,23 @@ regulator-state-mem {
+ };
+ };
+
++&i2c1 {
++ clock-frequency = <400000>;
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ interrupt-parent = <&gpio5>;
++ interrupts = ;
++ #clock-cells = <0>;
++ clock-frequency = <32768>;
++ clock-output-names = "hym8563";
++ pinctrl-names = "default";
++ pinctrl-0 = <&hym8563_int>;
++ };
++};
++
+ &i2c5 {
+ status = "okay";
+ };
+@@ -245,6 +262,12 @@ &io_domains {
+ };
+
+ &pinctrl {
++ hym8563 {
++ hym8563_int: hym8563-int {
++ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+From 2a67f75ad25fd99946aa142ff63c98bb98b8c11b Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Fri, 23 Oct 2020 23:48:14 +0530
+Subject: [PATCH] ARM: dts: rockchip: Add SDIO0 node for VMARC SOM
+
+Rockchip RK3288 and RK3399Pro based VMARC SOM has sdio0 for
+connecting WiFi/BT devices as a pluggable card via M.2 E-Key.
+
+Add associated sdio0 nodes, properties.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com
+[moved the unrelated rtc addition to a separate patch]
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 17 +++++++++++++++
+ .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 +++++++++++++++++++
+ .../dts/rockchip/rk3399pro-vmarc-som.dtsi | 16 ++++++++++++++
+ 3 files changed, 54 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
+index da80bfd5f2d5..0ae2bd150e37 100644
+--- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
++++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
+@@ -258,6 +258,7 @@ &io_domains {
+ gpio1830-supply = <&vcc_18>;
+ gpio30-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
++ wifi-supply = <&vcc_wl>;
+ status = "okay";
+ };
+
+@@ -283,6 +284,12 @@ pmic_int: pmic-int {
+ };
+ };
+
++ sdio-pwrseq {
++ wifi_enable_h: wifi-enable-h {
++ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ sdmmc {
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+@@ -314,6 +321,16 @@ usb0_en_oc: usb0-en-oc {
+ };
+ };
+
++&sdio_pwrseq {
++ /*
++ * On the module itself this is one of these (depending
++ * on the actual card populated):
++ * - SDIO_RESET_L_WL_REG_ON
++ * - PDN (power down when low)
++ */
++ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */
++};
++
+ &usbphy {
+ status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
+index 26b53eac4706..da1d548b7330 100644
+--- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
++++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
+@@ -15,6 +15,14 @@ clkin_gmac: external-gmac-clock {
+ #clock-cells = <0>;
+ };
+
++ sdio_pwrseq: sdio-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ clocks = <&hym8563>;
++ clock-names = "ext_clock";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_enable_h>;
++ };
++
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+@@ -78,6 +86,19 @@ &pwm2 {
+ status = "okay";
+ };
+
++&sdio0 {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ cap-sdio-irq;
++ keep-power-in-suspend;
++ mmc-pwrseq = <&sdio_pwrseq>;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++ sd-uhs-sdr104;
++ status = "okay";
++};
++
+ &sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+index 5d087be04af8..7257494d2831 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+@@ -353,6 +353,12 @@ pmic_int_l: pmic-int-l {
+ };
+ };
+
++ sdio-pwrseq {
++ wifi_enable_h: wifi-enable-h {
++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ vbus_host {
+ usb1_en_oc: usb1-en-oc {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+@@ -371,6 +377,16 @@ &pmu_io_domains {
+ pmu1830-supply = <&vcc_1v8>;
+ };
+
++&sdio_pwrseq {
++ /*
++ * On the module itself this is one of these (depending
++ * on the actual card populated):
++ * - SDIO_RESET_L_WL_REG_ON
++ * - PDN (power down when low)
++ */
++ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
++};
++
+ &sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+
+From cc4ce3fd56ab4a9a53e00c0b6f6e4b9435982d07 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Mon, 9 Nov 2020 23:40:15 +0530
+Subject: [PATCH] arm64: defconfig: Enable ROCKCHIP_LVDS
+
+Now, some of the rockchip hardware platforms do enable
+lvds in mainline tree.
+
+So, enable Rockchip LVDS driver via default defconfig.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20201109181017.206834-8-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 5cfe3cf6f2ac..3ebba7dcb98f 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -646,6 +646,7 @@ CONFIG_ROCKCHIP_CDN_DP=y
+ CONFIG_ROCKCHIP_DW_HDMI=y
+ CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+ CONFIG_ROCKCHIP_INNO_HDMI=y
++CONFIG_ROCKCHIP_LVDS=y
+ CONFIG_DRM_RCAR_DU=m
+ CONFIG_DRM_RCAR_DW_HDMI=m
+ CONFIG_DRM_SUN4I=m
+
+From e9eefe21625121fff49fdddfa20efb37e654045d Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Mon, 9 Nov 2020 23:40:16 +0530
+Subject: [PATCH] arm64: defconfig: Enable PHY_ROCKCHIP_INNO_DSIDPHY
+
+In order to work LDVS, DSI in mainline tree for Rockchip based
+hardware platforms, the associated PHY driver has to enable
+in default defconfig.
+
+Enable rockchip DSI phy driver.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20201109181017.206834-9-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 3ebba7dcb98f..d50826dd7d68 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -1011,6 +1011,7 @@ CONFIG_PHY_RCAR_GEN3_USB3=m
+ CONFIG_PHY_ROCKCHIP_EMMC=y
+ CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
+ CONFIG_PHY_ROCKCHIP_PCIE=m
+ CONFIG_PHY_ROCKCHIP_TYPEC=y
+ CONFIG_PHY_UNIPHIER_USB2=y
+
+From 4ce70903bef3a7f5d45e4acdf744185ec0a468c6 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Mon, 9 Nov 2020 23:40:17 +0530
+Subject: [PATCH] arm64: defconfig: Enable USB_SERIAL_CP210X
+
+Some hardware platforms required CP20x USB to Serial converter
+in order to work onboard functionalities like Bluetooth.
+
+An example of such a platform is from Engicam's PX30 (ARM64).
+
+Mark it as module in defconfig.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20201109181017.206834-10-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index d50826dd7d68..41a2d489f0a2 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -751,6 +751,7 @@ CONFIG_USB_CHIPIDEA_UDC=y
+ CONFIG_USB_CHIPIDEA_HOST=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_CP210X=m
+ CONFIG_USB_SERIAL_FTDI_SIO=m
+ CONFIG_USB_HSIC_USB3503=y
+ CONFIG_NOP_USB_XCEIV=y
+
+From dba3d86aca8df97ebd24edde2522ab61833619f1 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Fri, 23 Oct 2020 23:48:13 +0530
+Subject: [PATCH] arm64: defconfig: Enable RTC_DRV_HYM8563
+
+RTC HYM8563 used in the ARM64 Rockchip SoC's SDIO power
+sequence enablement.
+
+Enable it as module.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20201023181814.220974-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 41a2d489f0a2..699c204090b8 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -816,6 +816,7 @@ CONFIG_EDAC=y
+ CONFIG_EDAC_GHES=y
+ CONFIG_RTC_CLASS=y
+ CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_HYM8563=m
+ CONFIG_RTC_DRV_MAX77686=y
+ CONFIG_RTC_DRV_RK808=m
+ CONFIG_RTC_DRV_PCF85363=m
+
+From 1df05ffbdb8550fa30547574f785c76e8036beb8 Mon Sep 17 00:00:00 2001
+From: Lee Jones
+Date: Tue, 3 Nov 2020 15:28:18 +0000
+Subject: [PATCH] soc: rockchip: io-domain: Remove incorrect and incomplete
+ comment header
+
+Fixes the following W=1 kernel build warning(s):
+
+ drivers/soc/rockchip/io-domain.c:57: warning: Cannot understand * @supplies: voltage settings matching the register bits.
+
+Signed-off-by: Lee Jones
+Cc: Heiko Stuebner
+Cc: Liam Girdwood
+Cc: Mark Brown
+Cc: "Rafael J. Wysocki"
+Cc: Doug Anderson
+Cc: linux-rockchip@lists.infradead.org
+Link: https://lore.kernel.org/r/20201103152838.1290217-6-lee.jones@linaro.org
+Signed-off-by: Heiko Stuebner
+---
+ drivers/soc/rockchip/io-domain.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c
+index b29e829e815e..cf8182fc3642 100644
+--- a/drivers/soc/rockchip/io-domain.c
++++ b/drivers/soc/rockchip/io-domain.c
+@@ -53,9 +53,6 @@
+
+ struct rockchip_iodomain;
+
+-/**
+- * @supplies: voltage settings matching the register bits.
+- */
+ struct rockchip_iodomain_soc_data {
+ int grf_offset;
+ const char *supply_names[MAX_SUPPLIES];
+
+From 6393923881cab6d3a4abacb56b742d386d24eb63 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=
+Date: Wed, 14 Oct 2020 22:00:29 +0200
+Subject: [PATCH] dt-bindings: vendor-prefixes: Add kobol prefix
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The prefix is already used in arm/armada-388-helios4.dts.
+
+Signed-off-by: Uwe Kleine-König
+Acked-by: Rob Herring
+Link: https://lore.kernel.org/r/20201014200030.845759-2-uwe@kleine-koenig.org
+Signed-off-by: Heiko Stuebner
+---
+ Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
+index 2735be1a8470..259faf1b382c 100644
+--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
+@@ -553,6 +553,8 @@ patternProperties:
+ description: Kionix, Inc.
+ "^kobo,.*":
+ description: Rakuten Kobo Inc.
++ "^kobol,.*":
++ description: Kobol Innovations Pte. Ltd.
+ "^koe,.*":
+ description: Kaohsiung Opto-Electronics Inc.
+ "^kontron,.*":
+
+From e4550a0485dc0f693a28e1280e89f279ced3bcd8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=
+Date: Wed, 14 Oct 2020 22:00:30 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add basic support for Kobol's Helios64
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The hardware is described in detail on Kobol's wiki at
+https://wiki.kobol.io/helios64/intro/.
+
+Up to now the following peripherals are working:
+
+ - UART
+ - Micro-SD card
+ - eMMC
+ - ethernet port 1
+ - status LED
+ - temperature sensor on i2c bus 2
+
+Signed-off-by: Uwe Kleine-König
+Link: https://lore.kernel.org/r/20201014200030.845759-3-uwe@kleine-koenig.org
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../dts/rockchip/rk3399-kobol-helios64.dts | 372 ++++++++++++++++++
+ 2 files changed, 373 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index 26661c7b736b..28b26a874313 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+new file mode 100644
+index 000000000000..2a561be724b2
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+@@ -0,0 +1,372 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 Aditya Prayoga
++ */
++
++/*
++ * The Kobol Helios64 is a board designed to operate as a NAS and optionally
++ * ships with an enclosing that can host five 2.5" hard disks.
++ *
++ * See https://wiki.kobol.io/helios64/intro/ for further details.
++ */
++
++/dts-v1/;
++#include "rk3399.dtsi"
++#include "rk3399-opp.dtsi"
++
++/ {
++ model = "Kobol Helios64";
++ compatible = "kobol,helios64", "rockchip,rk3399";
++
++ avdd_1v8_s0: avdd-1v8-s0 {
++ compatible = "regulator-fixed";
++ regulator-name = "avdd_1v8_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc3v3_sys_s3>;
++ };
++
++ clkin_gmac: external-gmac-clock {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "clkin_gmac";
++ #clock-cells = <0>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>;
++
++ led-0 {
++ label = "helios64:green:status";
++ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++
++ led-1 {
++ label = "helios64:red:fault";
++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
++ default-state = "keep";
++ };
++ };
++
++ vcc1v8_sys_s0: vcc1v8-sys-s0 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc1v8_sys_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc1v8_sys_s3>;
++ };
++
++ vcc3v0_sd: vcc3v0-sd {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++ regulator-name = "vcc3v0_sd";
++ regulator-boot-on;
++ regulator-min-microvolt = <3000000>;
++ regulator-max-microvolt = <3000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_pwr_h>;
++ vin-supply = <&vcc3v3_sys_s3>;
++ };
++
++ vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_sys_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc5v0_sys: vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc12v_dcin_bkup>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc12v_dcin: vcc12v-dcin {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc12v_dcin";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ };
++
++ vcc12v_dcin_bkup: vcc12v-dcin-bkup {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc12v_dcin_bkup";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ vin-supply = <&vcc12v_dcin>;
++ };
++};
++
++/*
++ * The system doesn't run stable with cpu freq enabled, so disallow the lower
++ * frequencies until this problem is properly understood and resolved.
++ */
++&cluster0_opp {
++ /delete-node/ opp00;
++ /delete-node/ opp01;
++ /delete-node/ opp02;
++ /delete-node/ opp03;
++ /delete-node/ opp04;
++};
++
++&cluster1_opp {
++ /delete-node/ opp00;
++ /delete-node/ opp01;
++ /delete-node/ opp02;
++ /delete-node/ opp03;
++ /delete-node/ opp04;
++ /delete-node/ opp05;
++ /delete-node/ opp06;
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_l>;
++};
++
++&emmc_phy {
++ status = "okay";
++};
++
++&gmac {
++ assigned-clock-parents = <&clkin_gmac>;
++ assigned-clocks = <&cru SCLK_RMII_SRC>;
++ clock_in_out = "input";
++ phy-mode = "rgmii";
++ phy-supply = <&vcc_lan>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmii_pins &gphy_reset>;
++ rx_delay = <0x20>;
++ tx_delay = <0x28>;
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 10000 50000>;
++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&i2c0 {
++ clock-frequency = <400000>;
++ i2c-scl-rising-time-ns = <168>;
++ i2c-scl-falling-time-ns = <4>;
++ status = "okay";
++
++ rk808: pmic@1b {
++ compatible = "rockchip,rk808";
++ reg = <0x1b>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
++ clock-output-names = "xin32k", "rk808-clkout2";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int_l>;
++ vcc1-supply = <&vcc5v0_sys>;
++ vcc2-supply = <&vcc5v0_sys>;
++ vcc3-supply = <&vcc5v0_sys>;
++ vcc4-supply = <&vcc5v0_sys>;
++ vcc6-supply = <&vcc5v0_sys>;
++ vcc7-supply = <&vcc5v0_sys>;
++ vcc8-supply = <&vcc3v3_sys_s3>;
++ vcc9-supply = <&vcc5v0_sys>;
++ vcc10-supply = <&vcc5v0_sys>;
++ vcc11-supply = <&vcc5v0_sys>;
++ vcc12-supply = <&vcc3v3_sys_s3>;
++ vddio-supply = <&vcc3v0_s3>;
++ wakeup-source;
++ #clock-cells = <1>;
++
++ regulators {
++ vdd_cpu_l: DCDC_REG2 {
++ regulator-name = "vdd_cpu_l";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc1v8_sys_s3: DCDC_REG4 {
++ regulator-name = "vcc1v8_sys_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc_sdio_s0: LDO_REG4 {
++ regulator-name = "vcc_sdio_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3000000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3000000>;
++ };
++ };
++
++ vcc3v0_s3: LDO_REG8 {
++ regulator-name = "vcc3v0_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3000000>;
++ regulator-max-microvolt = <3000000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3000000>;
++ };
++ };
++ };
++ };
++
++ vdd_cpu_b: regulator@40 {
++ compatible = "silergy,syr827";
++ reg = <0x40>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_b";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1500000>;
++ regulator-ramp-delay = <1000>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++};
++
++&i2c2 {
++ clock-frequency = <400000>;
++ i2c-scl-rising-time-ns = <160>;
++ i2c-scl-falling-time-ns = <30>;
++ status = "okay";
++
++ temp@4c {
++ compatible = "national,lm75";
++ reg = <0x4c>;
++ };
++};
++
++&io_domains {
++ audio-supply = <&vcc1v8_sys_s0>;
++ bt656-supply = <&vcc1v8_sys_s0>;
++ gpio1830-supply = <&vcc3v0_s3>;
++ sdmmc-supply = <&vcc_sdio_s0>;
++ status = "okay";
++};
++
++&pinctrl {
++ gmac {
++ gphy_reset: gphy-reset {
++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
++ };
++ };
++
++ leds {
++ sys_grn_led_on: sys-grn-led-on {
++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++
++ sys_red_led_on: sys-red-led-on {
++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ };
++
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ vcc3v0-sd {
++ sdmmc0_pwr_h: sdmmc0-pwr-h {
++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++};
++
++&pmu_io_domains {
++ pmu1830-supply = <&vcc3v0_s3>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ mmc-hs200-1_8v;
++ non-removable;
++ vqmmc-supply = <&vcc1v8_sys_s0>;
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
++ disable-wp;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
++ vmmc-supply = <&vcc3v0_sd>;
++ vqmmc-supply = <&vcc_sdio_s0>;
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
+
+From 5cdadd99fc57ce819d00a6bcf5720d920c64d9f9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=
+Date: Mon, 2 Nov 2020 16:06:58 +0100
+Subject: [PATCH] dt-bindings: arm: rockchip: Add Kobol Helios64
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Document the new board by Kobol introduced recently in
+rockchip/rk3399-kobol-helios64.dts.
+
+Signed-off-by: Uwe Kleine-König
+Acked-by: Rob Herring
+Link: https://lore.kernel.org/r/20201102150658.167161-1-uwe@kleine-koenig.org
+Signed-off-by: Heiko Stuebner
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
+index b621752aaa65..ad1dbf349c33 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -381,6 +381,11 @@ properties:
+ - khadas,edge-v
+ - const: rockchip,rk3399
+
++ - description: Kobol Helios64
++ items:
++ - const: kobol,helios64
++ - const: rockchip,rk3399
++
+ - description: Mecer Xtreme Mini S6
+ items:
+ - const: mecer,xms6
+
+From e648ff565eca99a4c7f73861d5e00f5999ef1afb Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner
+Date: Sat, 4 Jul 2020 00:14:13 +0200
+Subject: [PATCH] arm64: dts: rockchip: add adc joystick to Odroid Go Advance
+
+Add the now usable adc-joystick node that describes the analog
+joystick connected to two saradc channels from the rk3326 soc.
+
+Signed-off-by: Heiko Stuebner
+Link: https://lore.kernel.org/r/20200703221413.269800-1-heiko@sntech.de
+---
+ .../boot/dts/rockchip/rk3326-odroid-go2.dts | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+index 337681038519..97fb93e1cc00 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+@@ -18,6 +18,30 @@ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
++ adc-joystick {
++ compatible = "adc-joystick";
++ io-channels = <&saradc 1>,
++ <&saradc 2>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ axis@0 {
++ reg = <0>;
++ abs-flat = <10>;
++ abs-fuzz = <10>;
++ abs-range = <172 772>;
++ linux,code = ;
++ };
++
++ axis@1 {
++ reg = <1>;
++ abs-flat = <10>;
++ abs-fuzz = <10>;
++ abs-range = <278 815>;
++ linux,code = ;
++ };
++ };
++
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_bl>;
+
+From ab1d9b1011a0715b1b8e9f7509af5595978c636d Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Tue, 29 Sep 2020 14:02:11 +0530
+Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core EDIMM2.2
+ Starter Kit
+
+PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+
+EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
+Evaluation Board from Engicam.
+
+PX30.Core needs to mount on top of this Evaluation board for
+creating complete PX30.Core EDIMM2.2 Starter Kit.
+
+Add bindings for it.
+
+Signed-off-by: Jagan Teki
+Acked-by: Rob Herring
+Link: https://lore.kernel.org/r/20200929083217.25406-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
+index ad1dbf349c33..cef95eb26ca6 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -70,6 +70,12 @@ properties:
+ - const: elgin,rv1108-r1
+ - const: rockchip,rv1108
+
++ - description: Engicam PX30.Core EDIMM2.2 Starter Kit
++ items:
++ - const: engicam,px30-core-edimm2.2
++ - const: engicam,px30-core
++ - const: rockchip,px30
++
+ - description: Firefly Firefly-RK3288
+ items:
+ - enum:
+
+From 8efa7701f53539842009e63eab1c44d4c25f27a0 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Tue, 29 Sep 2020 14:02:12 +0530
+Subject: [PATCH] arm64: dts: rockchip: Add Engicam EDIMM2.2 Starter Kit
+
+Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
+Evaluation Board.
+
+Genaral features:
+- LCD 7" C.Touch
+- microSD slot
+- Ethernet 1Gb
+- Wifi/BT
+- 2x LVDS Full HD interfaces
+- 3x USB 2.0
+- 1x USB 3.0
+- HDMI Out
+- Mini PCIe
+- MIPI CSI
+- 2x CAN
+- Audio Out
+
+SOM's like PX30.Core needs to mount on top of this Evaluation board
+for creating complete PX30.Core EDIMM2.2 Starter Kit.
+
+Add support for it.
+
+Signed-off-by: Jagan Teki
+Signed-off-by: Michael Trimarchi
+Link: https://lore.kernel.org/r/20200929083217.25406-3-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ .../dts/rockchip/px30-engicam-common.dtsi | 39 +++++++++++++++++++
+ .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 7 ++++
+ 2 files changed, 46 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi
+
+diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+new file mode 100644
+index 000000000000..bd5bde989e8d
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+@@ -0,0 +1,39 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 Engicam srl
++ * Copyright (c) 2020 Amarula Solutions
++ * Copyright (c) 2020 Amarula Solutions(India)
++ */
++
++/ {
++ vcc5v0_sys: vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys"; /* +5V */
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++};
++
++&gmac {
++ clock_in_out = "output";
++ phy-supply = <&vcc_3v3>; /* +3V3_SOM */
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 50000 50000>;
++ snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&sdmmc {
++ cap-sd-highspeed;
++ card-detect-delay = <800>;
++ vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */
++ vqmmc-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-0 = <&uart2m1_xfer>;
++ status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi
+new file mode 100644
+index 000000000000..cb00988953e9
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi
+@@ -0,0 +1,7 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 Engicam srl
++ * Copyright (c) 2020 Amarula Solutions(India)
++ */
++
++#include "px30-engicam-common.dtsi"
+
+From 37f0dd7a1a5ccfdf31502abf3099eb0ba84bc2e0 Mon Sep 17 00:00:00 2001
+From: Michael Trimarchi
+Date: Tue, 29 Sep 2020 14:02:13 +0530
+Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core SOM
+
+PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+
+General features:
+- Rockchip PX30
+- Up to 2GB DDR4
+- eMMC 4 GB expandible
+- rest of PX30 features
+
+PX30.Core needs to mount on top of Engicam baseboards for creating
+complete platform boards.
+
+Possible baseboards are,
+- EDIMM2.2
+- C.TOUCH 2.0
+
+Add support for it.
+
+Signed-off-by: Jagan Teki
+Signed-off-by: Michael Trimarchi
+Link: https://lore.kernel.org/r/20200929083217.25406-4-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ .../dts/rockchip/px30-engicam-px30-core.dtsi | 232 ++++++++++++++++++
+ 1 file changed, 232 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
+
+diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
+new file mode 100644
+index 000000000000..db22f776c68f
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
+@@ -0,0 +1,232 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (c) 2020 Engicam srl
++ * Copyright (c) 2020 Amarula Solutons
++ * Copyright (c) 2020 Amarula Solutons(India)
++ */
++
++#include
++#include
++
++/ {
++ compatible = "engicam,px30-core", "rockchip,px30";
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&emmc {
++ cap-mmc-highspeed;
++ mmc-hs200-1_8v;
++ non-removable;
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ rk809: pmic@20 {
++ compatible = "rockchip,rk809";
++ reg = <0x20>;
++ interrupt-parent = <&gpio0>;
++ interrupts = ;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int>;
++ rockchip,system-power-controller;
++ wakeup-source;
++ #clock-cells = <1>;
++ clock-output-names = "rk808-clkout1", "rk808-clkout2";
++
++ vcc1-supply = <&vcc5v0_sys>;
++ vcc2-supply = <&vcc5v0_sys>;
++ vcc3-supply = <&vcc5v0_sys>;
++ vcc4-supply = <&vcc5v0_sys>;
++ vcc5-supply = <&vcc3v3_sys>;
++ vcc6-supply = <&vcc3v3_sys>;
++ vcc7-supply = <&vcc3v3_sys>;
++ vcc8-supply = <&vcc3v3_sys>;
++ vcc9-supply = <&vcc5v0_sys>;
++
++ regulators {
++ vdd_log: DCDC_REG1 {
++ regulator-name = "vdd_log";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <950000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vdd_arm: DCDC_REG2 {
++ regulator-name = "vdd_arm";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <950000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_3v3: DCDC_REG4 {
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc3v3_sys: DCDC_REG5 {
++ regulator-name = "vcc3v3_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc_1v0: LDO_REG1 {
++ regulator-name = "vcc_1v0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vcc_1v8: LDO_REG2 {
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_1v0: LDO_REG3 {
++ regulator-name = "vdd_1v0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vcc3v0_pmu: LDO_REG4 {
++ regulator-name = "vcc3v0_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++
++ };
++ };
++
++ vccio_sd: LDO_REG5 {
++ regulator-name = "vccio_sd";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc5v0_host: SWITCH_REG2 {
++ regulator-name = "vcc5v0_host";
++ regulator-always-on;
++ regulator-boot-on;
++ };
++ };
++ };
++};
++
++&io_domains {
++ vccio1-supply = <&vcc_3v3>;
++ vccio2-supply = <&vcc_3v3>;
++ vccio3-supply = <&vcc_3v3>;
++ vccio4-supply = <&vcc_3v3>;
++ vccio5-supply = <&vcc_3v3>;
++ vccio6-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&pinctrl {
++ pmic {
++ pmic_int: pmic_int {
++ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++};
++
++&pmu_io_domains {
++ pmuio1-supply = <&vcc_3v3>;
++ pmuio2-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <1>;
++ rockchip,hw-tshut-polarity = <1>;
++ status = "okay";
++};
+
+From d51f542ce24362ea0664a5eb7f5dbda84b577810 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Tue, 29 Sep 2020 14:02:14 +0530
+Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter
+ Kit
+
+PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+
+EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
+Evaluation Board from Engicam.
+
+PX30.Core needs to mount on top of this Evaluation board for
+creating complete PX30.Core EDIMM2.2 Starter Kit.
+
+Add support for it.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20200929083217.25406-5-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../px30-engicam-px30-core-edimm2.2.dts | 21 +++++++++++++++++++
+ 2 files changed, 22 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
+
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index 28b26a874313..abf9dc621314 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
+new file mode 100644
+index 000000000000..e54d1e480daa
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (c) 2020 Engicam srl
++ * Copyright (c) 2020 Amarula Solutions(India)
++ */
++
++/dts-v1/;
++#include "px30.dtsi"
++#include "px30-engicam-edimm2.2.dtsi"
++#include "px30-engicam-px30-core.dtsi"
++
++/ {
++ model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
++ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
++ "rockchip,px30";
++
++ chosen {
++ stdout-path = "serial2:115200n8";
++ };
++};
+
+From 178762dcff60848615f72c18987247416633ad8f Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Tue, 29 Sep 2020 14:02:15 +0530
+Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0
+
+PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+
+C.TOUCH 2.0 is a general purpose carrier board with capacitive
+touch interface support.
+
+PX30.Core needs to mount on top of this Carrier board for creating
+complete PX30.Core C.TOUCH 2.0 board.
+
+Add bindings for it.
+
+Signed-off-by: Jagan Teki
+Acked-by: Rob Herring
+Link: https://lore.kernel.org/r/20200929083217.25406-6-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
+index cef95eb26ca6..37fd456170d2 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -70,6 +70,12 @@ properties:
+ - const: elgin,rv1108-r1
+ - const: rockchip,rv1108
+
++ - description: Engicam PX30.Core C.TOUCH 2.0
++ items:
++ - const: engicam,px30-core-ctouch2
++ - const: engicam,px30-core
++ - const: rockchip,px30
++
+ - description: Engicam PX30.Core EDIMM2.2 Starter Kit
+ items:
+ - const: engicam,px30-core-edimm2.2
+
+From 3a0333a1c43aeda0a7eabd3ce97f93b546fc63e1 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Tue, 29 Sep 2020 14:02:16 +0530
+Subject: [PATCH] arm64: dts: rockchip: Add Engicam C.TOUCH 2.0
+
+Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
+carrier board with capacitive touch interface.
+
+Genaral features:
+- TFT 10.1" industrial, 1280x800 LVDS display
+- Ethernet 10/100
+- Wifi/BT
+- USB Type A/OTG
+- Audio Out
+- CAN
+- LVDS panel connector
+
+SOM's like PX30.Core needs to mount on top of this Carrier board
+for creating complete PX30.Core C.TOUCH 2.0 board.
+
+Add support for it.
+
+Signed-off-by: Jagan Teki
+Signed-off-by: Michael Trimarchi
+Link: https://lore.kernel.org/r/20200929083217.25406-7-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
+
+diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
+new file mode 100644
+index 000000000000..58425b1e559f
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
+@@ -0,0 +1,8 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 Engicam srl
++ * Copyright (c) 2020 Amarula Solutions
++ * Copyright (c) 2020 Amarula Solutions(India)
++ */
++
++#include "px30-engicam-common.dtsi"
+
+From 32a432c01b10885659d2dcd24975e991f1e0cf89 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Tue, 29 Sep 2020 14:02:17 +0530
+Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0
+
+PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+
+C.TOUCH 2.0 is a general purpose carrier board with capacitive
+touch interface support.
+
+PX30.Core needs to mount on top of this Carrier board for creating
+complete PX30.Core C.TOUCH 2.0 board.
+
+Add support for it.
+
+Signed-off-by: Jagan Teki
+Signed-off-by: Michael Trimarchi
+Link: https://lore.kernel.org/r/20200929083217.25406-8-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../px30-engicam-px30-core-ctouch2.dts | 22 +++++++++++++++++++
+ 2 files changed, 23 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts
+
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index abf9dc621314..5a53979b7057 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts
+new file mode 100644
+index 000000000000..5a0ecb8faecf
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts
+@@ -0,0 +1,22 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (c) 2020 Engicam srl
++ * Copyright (c) 2020 Amarula Solutions
++ * Copyright (c) 2020 Amarula Solutions(India)
++ */
++
++/dts-v1/;
++#include "px30.dtsi"
++#include "px30-engicam-ctouch2.dtsi"
++#include "px30-engicam-px30-core.dtsi"
++
++/ {
++ model = "Engicam PX30.Core C.TOUCH 2.0";
++ compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
++ "rockchip,px30";
++
++ chosen {
++ stdout-path = "serial2:115200n8";
++ };
++};
+
+From 4402111ed3efffe40616658af7cd677de5954776 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai
+Date: Thu, 26 Nov 2020 15:33:35 +0800
+Subject: [PATCH] arm64: dts: rockchip: Enable HDMI audio on rk3328-roc-cc
+
+The RK3328-ROC-CC already has HDMI display output enabled. Now that
+audio for the HDMI controller is supported, it can be enabled as well.
+
+Enable the simple-audio-card, and the I2S interface the audio is fed
+from.
+
+Signed-off-by: Chen-Yu Tsai
+Link: https://lore.kernel.org/r/20201126073336.30794-3-wens@kernel.org
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+index b76282e704de..697fce709031 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -161,6 +161,10 @@ &hdmiphy {
+ status = "okay";
+ };
+
++&hdmi_sound {
++ status = "okay";
++};
++
+ &i2c1 {
+ status = "okay";
+
+@@ -270,6 +274,10 @@ regulator-state-mem {
+ };
+ };
+
++&i2s0 {
++ status = "okay";
++};
++
+ &io_domains {
+ status = "okay";
+
+
+From 755eed3a0181ab31177162799c6cbe3ed3c85593 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai
+Date: Thu, 26 Nov 2020 15:33:36 +0800
+Subject: [PATCH] arm64: dts: rockchip: Enable analog audio on rk3328-roc-cc
+
+Now that driver support for the RK3328's audio codec, and the plumbing
+is defined at the SoC level, we can enable analog audio at the board
+level.
+
+Enable analog audio by enabling the codec and the I2S interface
+connected and the simple-audio-card that binds them together.
+
+Signed-off-by: Chen-Yu Tsai
+Link: https://lore.kernel.org/r/20201126073336.30794-4-wens@kernel.org
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+index 697fce709031..19959bfba451 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -104,6 +104,14 @@ user_led: led-1 {
+ };
+ };
+
++&analog_sound {
++ status = "okay";
++};
++
++&codec {
++ status = "okay";
++};
++
+ &cpu0 {
+ cpu-supply = <&vdd_arm>;
+ };
+@@ -278,6 +286,10 @@ &i2s0 {
+ status = "okay";
+ };
+
++&i2s1 {
++ status = "okay";
++};
++
+ &io_domains {
+ status = "okay";
+
+
+From 0ec396b3ae638938f6b138e1555afb1d4b1aebed Mon Sep 17 00:00:00 2001
+From: Johan Jonker
+Date: Mon, 16 Nov 2020 14:23:11 +0100
+Subject: [PATCH] arm64: dts: rockchip: rename sdhci nodename to mmc on rk3399
+
+A test with the command below gives for example this error:
+
+/arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml:
+sdhci@fe330000: $nodename:0: 'sdhci@fe330000'
+does not match '^mmc(@.*)?$'
+
+Fix it by renaming sdhci to mmc.
+
+make ARCH=arm64 dtbs_check
+DT_SCHEMA_FILES=Documentation/devicetree/bindings/
+mmc/arasan,sdhci.yaml
+
+Signed-off-by: Johan Jonker
+Link: https://lore.kernel.org/r/20201116132311.8318-1-jbx6244@gmail.com
+Signed-off-by: Heiko Stuebner
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 7a9a7aca86c6..865729ec867f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -331,7 +331,7 @@ sdmmc: mmc@fe320000 {
+ status = "disabled";
+ };
+
+- sdhci: sdhci@fe330000 {
++ sdhci: mmc@fe330000 {
+ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+ reg = <0x0 0xfe330000 0x0 0x10000>;
+ interrupts = ;
+
+From 788de7c2c761d7d34879de0f31d46a26071318e7 Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Mon, 9 Nov 2020 23:40:09 +0530
+Subject: [PATCH] arm64: dts: rockchip: Enable USB Host, OTG on px30-enagicam
+
+Engicam EDIMM2.2 and C.Touch 2.0 Kits support USB Host
+and OTG ports.
+
+Add support to enable USB on these kits while mounting
+px30-core SOM.
+
+Signed-off-by: Jagan Teki
+Link: https://lore.kernel.org/r/20201109181017.206834-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner
+---
+ .../dts/rockchip/px30-engicam-common.dtsi | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+index bd5bde989e8d..fbbdbb0a40af 100644
+--- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
++++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+@@ -33,7 +33,31 @@ &sdmmc {
+ status = "okay";
+ };
+
++&u2phy {
++ status = "okay";
++
++ u2phy_host: host-port {
++ status = "okay";
++ };
++
++ u2phy_otg: otg-port {
++ status = "okay";
++ };
++};
++
+ &uart2 {
+ pinctrl-0 = <&uart2m1_xfer>;
+ status = "okay";
+ };
++
++&usb20_otg {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
+
+From 2b8ed7f5f189cacd9465e725d80949993a4af67a Mon Sep 17 00:00:00 2001
+From: Jagan Teki
+Date: Mon, 9 Nov 2020 23:40:10 +0530
+Subject: [PATCH] arm64: dts: rockchip: Enable LVDS panel on
+ px30-engicam-edimm2.2
+
+Engicam PX30.Core EDIMM2.2 developement Kit has on board 10" LVDS
+panel from yes-optoelectronics.
+
+This patch adds panel enablement nodes on respective dts(i) files.
+
+Signed-off-by: Jagan Teki