diff --git a/projects/WeTek.Play/filesystem/etc/asound.conf b/projects/WeTek.Play/filesystem/etc/asound.conf
new file mode 100644
index 0000000000..85204e0479
--- /dev/null
+++ b/projects/WeTek.Play/filesystem/etc/asound.conf
@@ -0,0 +1,11 @@
+pcm.!default {
+ type hw
+ card 0
+ device 0
+ format S16_LE
+}
+
+ctl.!default {
+ type hw
+ card 0
+}
diff --git a/projects/WeTek.Play/filesystem/etc/remote.conf b/projects/WeTek.Play/filesystem/etc/remote.conf
new file mode 100644
index 0000000000..e5b75cc07b
--- /dev/null
+++ b/projects/WeTek.Play/filesystem/etc/remote.conf
@@ -0,0 +1,11 @@
+# Amlogic NEC remote
+factory_code = 0xbc430001
+work_mode = 1
+repeat_enable = 1
+release_delay = 150
+debug_enable = 1
+reg_control = 0xfbe40
+
+key_begin
+ 0xca 116 ;POWER
+key_end
diff --git a/projects/WeTek.Play/filesystem/lib/firmware/brcm/ap6210-nvram.txt b/projects/WeTek.Play/filesystem/lib/firmware/brcm/ap6210-nvram.txt
new file mode 100644
index 0000000000..6cb3fd730e
--- /dev/null
+++ b/projects/WeTek.Play/filesystem/lib/firmware/brcm/ap6210-nvram.txt
@@ -0,0 +1,57 @@
+#AP6210_NVRAM_V1.2_03192013
+manfid=0x2d0
+prodid=0x492
+vendid=0x14e4
+devid=0x4343
+boardtype=0x0598
+
+# Board Revision is P307, same nvram file can be used for P304, P305, P306 and P307 as the tssi pa params used are same
+#Please force the automatic RX PER data to the respective board directory if not using P307 board, for e.g. for P305 boards force the data into the following directory /projects/BCM43362/a1_labdata/boardtests/results/sdg_rev0305
+boardrev=0x1307
+boardnum=777
+xtalfreq=26000
+boardflags=0x80201
+boardflags2=0x80
+sromrev=3
+wl0id=0x431b
+macaddr=00:90:4c:07:71:12
+aa2g=1
+ag0=2
+maxp2ga0=74
+cck2gpo=0x2222
+ofdm2gpo=0x44444444
+mcs2gpo0=0x6666
+mcs2gpo1=0x6666
+pa0maxpwr=56
+
+#P207 PA params
+#pa0b0=5447
+#pa0b1=-658
+#pa0b2=-175
+
+#Same PA params for P304,P305, P306, P307
+
+pa0b0=5447
+pa0b1=-607
+pa0b2=-160
+pa0itssit=62
+pa1itssit=62
+
+
+cckPwrOffset=5
+ccode=0
+rssismf2g=0xa
+rssismc2g=0x3
+rssisav2g=0x7
+triso2g=0
+noise_cal_enable_2g=0
+noise_cal_po_2g=0
+swctrlmap_2g=0x04040404,0x02020202,0x02020202,0x010101,0x1ff
+temp_add=29767
+temp_mult=425
+
+btc_flags=0x6
+btc_params0=5000
+btc_params1=1000
+btc_params6=63
+
diff --git a/projects/WeTek.Play/filesystem/lib/firmware/brcm/fw_bcm40181a2.bin b/projects/WeTek.Play/filesystem/lib/firmware/brcm/fw_bcm40181a2.bin
new file mode 100644
index 0000000000..ae76625463
Binary files /dev/null and b/projects/WeTek.Play/filesystem/lib/firmware/brcm/fw_bcm40181a2.bin differ
diff --git a/projects/WeTek.Play/filesystem/usr/lib/modules-load.d/mali.conf b/projects/WeTek.Play/filesystem/usr/lib/modules-load.d/mali.conf
new file mode 100644
index 0000000000..29c66fc8c8
--- /dev/null
+++ b/projects/WeTek.Play/filesystem/usr/lib/modules-load.d/mali.conf
@@ -0,0 +1 @@
+mali
diff --git a/projects/WeTek.Play/filesystem/usr/share/kodi/system/keymaps/wetek-remote.xml b/projects/WeTek.Play/filesystem/usr/share/kodi/system/keymaps/wetek-remote.xml
new file mode 100644
index 0000000000..9f89d88ad4
--- /dev/null
+++ b/projects/WeTek.Play/filesystem/usr/share/kodi/system/keymaps/wetek-remote.xml
@@ -0,0 +1,13 @@
+
+
+
+
+ ContextMenu
+ AspectRatio
+ XBMC.ActivateWindow(Home)
+ ActivateWindowAndFocus(MyPVR, 31,0, 10,0)
+ FullScreen
+ Screenshot
+
+
+
diff --git a/projects/WeTek.Play/initramfs/platform_init b/projects/WeTek.Play/initramfs/platform_init
new file mode 100755
index 0000000000..b95b3e16bf
--- /dev/null
+++ b/projects/WeTek.Play/initramfs/platform_init
@@ -0,0 +1,82 @@
+#!/bin/sh
+
+################################################################################
+# This file is part of OpenELEC - http://www.openelec.tv
+# Copyright (C) 2014 Alex Deryskyba (alex@codesnake.com)
+#
+# OpenELEC is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 2 of the License, or
+# (at your option) any later version.
+#
+# OpenELEC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with OpenELEC. If not, see .
+################################################################################
+
+# Force 720p display mode at startup
+echo 720p > /sys/class/display/mode
+
+# Enable framebuffer device
+echo 0 > /sys/class/graphics/fb0/blank
+
+# Disable framebuffer scaling
+echo 0 > /sys/class/graphics/fb0/free_scale
+
+# Set framebuffer geometry
+fbset -fb /dev/fb0 -g 1280 720 1280 1440 32
+
+# Set framebuffer size in CVBS mode to match the resolution,
+# for splash screen to be shown correctly
+hpd_state=$(cat /sys/class/amhdmitx/amhdmitx0/hpd_state)
+if [ "$hpd_state" != "1" ]; then # HDMI is not connected
+ display_height=480
+ display_mode=$(cat /sys/class/display/mode)
+ if [ "$display_mode" = "576cvbs" ]; then
+ display_height=576
+ fi
+ fbset -fb /dev/fb0 -g 720 "$display_height" 720 "$display_height" 32
+ fbset -fb /dev/fb1 -g 720 "$display_height" 720 "$display_height" 32
+fi
+
+# Include deinterlacer into default VFM map
+echo rm default > /sys/class/vfm/map
+echo add default decoder ppmgr deinterlace amvideo > /sys/class/vfm/map
+
+# Parse command line arguments
+for arg in $(cat /proc/cmdline); do
+ case $arg in
+ scaling_governor=*)
+ scaling_governor="${arg#*=}"
+ ;;
+ scaling_min_freq=*)
+ scaling_min_freq="${arg#*=}"
+ ;;
+ scaling_max_freq=*)
+ scaling_max_freq="${arg#*=}"
+ ;;
+ esac
+done
+
+# Boot with performance governor, then switch to the governor specified in the kernel command line
+cpu_idx=0
+while [ $cpu_idx -lt 128 ]; do
+ cpufreq="/sys/devices/system/cpu/cpu$cpu_idx/cpufreq"
+ if [ ! -d "$cpufreq" ]; then
+ break
+ fi
+ if [ -n "$scaling_governor" ]; then
+ echo "$scaling_governor" > "$cpufreq/scaling_governor"
+ fi
+ if [ -n "$scaling_min_freq" ]; then
+ echo "$scaling_min_freq" > "$cpufreq/scaling_min_freq"
+ fi
+ if [ -n "$scaling_max_freq" ]; then
+ echo "$scaling_max_freq" > "$cpufreq/scaling_max_freq"
+ fi
+ cpu_idx=`expr $cpu_idx + 1`
+done
diff --git a/projects/WeTek.Play/kodi/advancedsettings.xml b/projects/WeTek.Play/kodi/advancedsettings.xml
new file mode 100644
index 0000000000..ab23bdc593
--- /dev/null
+++ b/projects/WeTek.Play/kodi/advancedsettings.xml
@@ -0,0 +1,21 @@
+
+
+ false
+
+
+ 20971520
+
+
+
+ 30
+
+
+
+ 4.0
+
+
+
+ 5
+ 20
+
+
diff --git a/projects/WeTek.Play/linux/linux.arm.conf b/projects/WeTek.Play/linux/linux.arm.conf
new file mode 100644
index 0000000000..f16c41d7da
--- /dev/null
+++ b/projects/WeTek.Play/linux/linux.arm.conf
@@ -0,0 +1,3613 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.10.61 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FIQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_NEED_MACH_MEMORY_H=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_XZ is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="openelec"
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_IRQ_DOMAIN_DEBUG is not set
+CONFIG_KTIME_SCALAR=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_PREEMPT_RCU=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+# CONFIG_RCU_USER_QS is not set
+CONFIG_RCU_FANOUT=32
+CONFIG_RCU_FANOUT_LEAF=16
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+CONFIG_TREE_RCU_TRACE=y
+# CONFIG_RCU_BOOST is not set
+# CONFIG_RCU_NOCB_CPU is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_MEMCG is not set
+CONFIG_CGROUP_SCHED=y
+# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_UIDGID_CONVERTED=y
+# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=" "
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_HAVE_UID16=y
+CONFIG_HOTPLUG=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLD_SIGACTION=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_MULTIPLATFORM is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_PXA is not set
+CONFIG_PLAT_MESON=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C24XX is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP1 is not set
+
+#
+# Amlogic Meson platform
+#
+CONFIG_ARCH_MESON6=y
+# CONFIG_ARCH_MESON6TV is not set
+# CONFIG_ARCH_MESON6TVD is not set
+# CONFIG_ARCH_MESON8 is not set
+# CONFIG_ARCH_MESON8B is not set
+# CONFIG_ARCH_MESON8M2 is not set
+# CONFIG_ARCH_MESONG9TV is not set
+
+#
+# Meson development boards
+#
+CONFIG_MACH_MESON6_COMMON_BOARD=y
+# CONFIG_MESON_IRQ is not set
+CONFIG_MESON_ARM_GIC=y
+CONFIG_MESON_CLOCK_TICK_RATE=25000000
+# CONFIG_MESON_ARM_GIC_FIQ is not set
+CONFIG_MESON_SUSPEND=y
+# CONFIG_SUSPEND_WATCHDOG is not set
+# CONFIG_MESON_SUSPEND_TEST is not set
+# CONFIG_SCREEN_ON_EARLY is not set
+# CONFIG_CLK81_DFS is not set
+CONFIG_MESON_LEGACY_REGISTER_API=y
+# CONFIG_MESON_CPU_EMULATOR is not set
+CONFIG_CLKTREE_DEBUG=y
+
+#
+# Meson Global Timer Setting
+#
+CONFIG_MESON_TIMERA=y
+# CONFIG_MESON_TIMERC is not set
+CONFIG_MESON_LOCAL_TIMER=y
+# CONFIG_MESON_ARM_TWD is not set
+CONFIG_MESON_CPU_TEMP_SENSOR=y
+# CONFIG_CORE_FREQ_TRACK is not set
+CONFIG_MESON6_SMP_HOTPLUG=y
+# CONFIG_SUPPORT_USB_BURNING is not set
+CONFIG_MESON_L2CC_OPTIMIZE=y
+# CONFIG_MESON_L2CC_DLF is not set
+# CONFIG_MESON_L2CC_STANDBY is not set
+CONFIG_MESON_SUSPEND_FIRMWARE_BASE=0x1ff00000
+# CONFIG_MESON_TRUSTZONE is not set
+CONFIG_MESON_CUSTOM_BOARD_SUPPORT=y
+
+#
+# Meson customer board drivers
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_PLAT_SPEAR is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_KUSER_HELPERS=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARM_NR_BANKS=8
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_742230 is not set
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_ARM_ERRATA_643719 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+CONFIG_ARM_ERRATA_751472=y
+# CONFIG_PL310_ERRATA_753970 is not set
+CONFIG_ARM_ERRATA_754322=y
+# CONFIG_ARM_ERRATA_754327 is not set
+CONFIG_ARM_ERRATA_764369=y
+# CONFIG_PL310_ERRATA_769419 is not set
+# CONFIG_ARM_ERRATA_775420 is not set
+# CONFIG_ARM_ERRATA_798181 is not set
+# CONFIG_FIQ_DEBUGGER is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_HAVE_SMP=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+# CONFIG_SCHED_MC is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_HAVE_ARM_SCU=y
+# CONFIG_HAVE_ARM_ARCH_TIMER is not set
+# CONFIG_MCPM is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_ARM_PSCI is not set
+CONFIG_LOCAL_TIMERS=y
+CONFIG_ARCH_NR_GPIO=0
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_NEED_BOUNCE_POOL=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CLEANCACHE is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_XEN is not set
+# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ATAGS=y
+CONFIG_DEPRECATED_PARAM_STRUCT=y
+CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
+CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE_NAMES="meson6_g18"
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_APPEND=y
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_HOTPLUG is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_HOTPLUG=y
+# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+
+#
+# ARM CPU frequency scaling drivers
+#
+# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+CONFIG_AMLOGIC_MESON_CPUFREQ=y
+# CONFIG_CPU_IDLE is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_COREDUMP=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_FORCE_POWER_ON_STATE_AFTER_RESUME is not set
+CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL=y
+# CONFIG_CONSOLE_EARLYSUSPEND is not set
+# CONFIG_FB_EARLYSUSPEND is not set
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_WAKELOCKS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_CLK=y
+CONFIG_CPU_PM=y
+# CONFIG_SUSPEND_TIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_ALGO=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_FIB_TRIE_STATS is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_NET_IP_TUNNEL is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_NET_IPVTI is not set
+# CONFIG_INET_AH is not set
+CONFIG_INET_ESP=y
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NET_ACTIVITY_STATS is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+# CONFIG_BRIDGE_NETFILTER is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+# CONFIG_NETFILTER_NETLINK_ACCT is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CONNTRACK_TIMEOUT is not set
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+CONFIG_NF_CONNTRACK_FTP=m
+# CONFIG_NF_CONNTRACK_H323 is not set
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+CONFIG_NF_CONNTRACK_SIP=m
+# CONFIG_NF_CONNTRACK_TFTP is not set
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NF_CT_NETLINK_TIMEOUT is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+# CONFIG_NF_NAT_AMANDA is not set
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_SIP=m
+# CONFIG_NF_NAT_TFTP is not set
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+# CONFIG_NETFILTER_XT_CONNMARK is not set
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+# CONFIG_NETFILTER_XT_TARGET_LOG is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_BPF is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ECN is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA2 is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_SET is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+# CONFIG_IP_NF_TARGET_REJECT_SKERR is not set
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT_IPV4=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_BRIDGE_VLAN_FILTERING is not set
+CONFIG_HAVE_NET_DSA=y
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_VLAN_8021Q_MVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_MMAP is not set
+# CONFIG_NETLINK_DIAG is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+# CONFIG_CFG80211_WEXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_CFG80211_ALLOW_RECONNECT is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+CONFIG_HAVE_BPF_JIT=y
+
+#
+# Device Drivers
+#
+
+#
+# Amlogic Device Drivers
+#
+
+#
+# Char devices
+#
+CONFIG_EARLY_INIT=y
+
+#
+# Register Debug Support
+#
+# CONFIG_AML_REG_DEBUG is not set
+CONFIG_AM_UART=y
+CONFIG_AM_UART_CONSOLE=y
+CONFIG_OF_LM=y
+CONFIG_AML_RTC=y
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_AML=y
+# CONFIG_I2C_SW_AML is not set
+# CONFIG_BCM2079X_I2C is not set
+CONFIG_AM_INPUT=y
+# CONFIG_SARADC_AM is not set
+CONFIG_MESON_INPUT_REMOTE=y
+CONFIG_AM_REMOTE=y
+# CONFIG_AM_IR_RECEIVER is not set
+# CONFIG_VIRTUAL_REMOTE is not set
+CONFIG_MESON_NEW_INPUT_REMOTE=y
+# CONFIG_NEW_AM_REMOTE is not set
+# CONFIG_NEW_AM_IR_TX is not set
+CONFIG_MESON_INPUT_KEYBOARD=y
+CONFIG_KEY_INPUT_CUSTOM_AM=y
+# CONFIG_TOUCH_KEY_PAD_IT7230 is not set
+# CONFIG_TOUCH_KEY_PAD_SO340010 is not set
+# CONFIG_TOUCH_KEY_PAD_HA2605 is not set
+# CONFIG_MESON_INPUT_TOUCHSCREEN is not set
+# CONFIG_AML_HOLD_KEY is not set
+# CONFIG_AML_CALL_KEY is not set
+# CONFIG_SENSOR_DEVICES is not set
+# CONFIG_AML_GPIO_KEY is not set
+CONFIG_GPIO_AMLOGIC=y
+CONFIG_PINCTRL_AMLOGIC=y
+
+#
+# Power Management Support
+#
+CONFIG_AMLOGIC_BOARD_HAS_PMU=y
+CONFIG_AMLOGIC_PMU_OF=y
+# CONFIG_CW2015 is not set
+# CONFIG_SMBA10XX_BATTERY is not set
+# CONFIG_BQ27x00_BATTERY is not set
+# CONFIG_UBOOT_BATTERY_PARAMETERS is not set
+# CONFIG_AML_PMU_ALGORITHM_SUPPORT is not set
+CONFIG_AML_DVFS=y
+# CONFIG_AW_AXP is not set
+CONFIG_MESON_CS_DCDC_REGULATOR=y
+# CONFIG_AML_PMU is not set
+# CONFIG_RICOH_PMU is not set
+
+#
+# Security key Support
+#
+CONFIG_SECURITYKEY=y
+
+#
+# key management Support
+#
+# CONFIG_UNIFY_KEY_MANAGE is not set
+
+#
+# EFUSE Support
+#
+CONFIG_EFUSE=y
+# CONFIG_EFUSE_WRITE_VERSION_PERMIT is not set
+CONFIG_EFUSE_LAYOUT_VERSION=3
+
+#
+# Smartcard support
+#
+# CONFIG_AM_SMARTCARD is not set
+CONFIG_AML_VIRTUAL_THERMAL=y
+# CONFIG_AMLOGIC_THERMAL is not set
+# CONFIG_AML_WDT is not set
+
+#
+# AMLOGIC SPI Hardware bus support
+#
+# CONFIG_AMLOGIC_SPICC_MASTER is not set
+
+#
+# USB Support
+#
+CONFIG_AMLOGIC_USB=y
+CONFIG_USB_DWC_OTG_HCD=y
+CONFIG_USB_HOST_ELECT_TEST=y
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+
+#
+# Multimedia Card support
+#
+CONFIG_MMC_AML=y
+# CONFIG_MMC_AML_DEBUG is not set
+# CONFIG_AML_MMC_DEBUG_FORCE_SINGLE_BLOCK_RW is not set
+
+#
+# SPI NOR Flash support
+#
+# CONFIG_AMLOGIC_SPI_NOR is not set
+
+#
+# Meson NAND Device Support(For NEXT GEN NAND DRIV)
+#
+# CONFIG_AML_NEXT_GEN_NAND is not set
+CONFIG_AML_NFTL_NEW=y
+CONFIG_AML_NAND_KEY=y
+
+#
+# Meson NAND Device Support
+#
+CONFIG_AM_NAND=y
+CONFIG_AM_NAND_RBPIN=y
+CONFIG_AML_NAND_ENV=y
+CONFIG_NAND_KEY_BLOCK_NUM=8
+# CONFIG_AML_NFTL is not set
+# CONFIG_AML_NEXT_NAND is not set
+
+#
+# Network devices
+#
+
+#
+# Ethernet Support
+#
+CONFIG_AM_ETHERNET=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AML_PHY is not set
+CONFIG_AML_LAN8720=y
+CONFIG_AML_IP101_PHY=y
+CONFIG_AML_KSZ8091=y
+# CONFIG_AML_RTL8211F is not set
+CONFIG_AM_ETHERNET_DEBUG_LEVEL=1
+CONFIG_AM_WIFI=y
+CONFIG_AM_WIFI_SD_MMC=y
+# CONFIG_DHD_USE_STATIC_BUF is not set
+CONFIG_AM_WIFI_USB=y
+# CONFIG_RTL8189ES is not set
+CONFIG_RTL8192EU=m
+CONFIG_RTL8723AU=m
+# CONFIG_RTL8723AS is not set
+# CONFIG_RTL8723BS is not set
+CONFIG_RTL8821AU=m
+CONFIG_RTL8812AU=m
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192DU=m
+CONFIG_RTL8188EU=m
+CONFIG_RTL8188EU_MP=m
+CONFIG_SDIO_DHD_CDC_WIFI_40181_MODULE=y
+CONFIG_BCMDHD_FW_PATH="/lib/firmware/brcm/"
+CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/brcm/ap6210-nvram.txt"
+CONFIG_BCMDHD_CONFIG_PATH="/system/etc/wifi/config.txt"
+CONFIG_BCMDHD_POWER_OFF_IN_SUSPEND=y
+CONFIG_BCMDHD_OOB=y
+# CONFIG_SDIO_HARD_IRQ is not set
+
+#
+# Bluetooth Device Support
+#
+# CONFIG_BT_WAKE_CTRL is not set
+# CONFIG_BT_RTKBTUSB is not set
+# CONFIG_MESON_NFC is not set
+
+#
+# Audio devices
+#
+
+#
+# Audio Interface
+#
+CONFIG_AMAUDIO=y
+
+#
+# Amlogic Audio Interface V2
+#
+# CONFIG_AMAUDIO2 is not set
+
+#
+# Audio dsp process
+#
+CONFIG_AML_AUDIO_DSP=y
+
+#
+# Video devices
+#
+CONFIG_AML_VFM=y
+CONFIG_AM_PTSSERVER=y
+# CONFIG_H264_4K2K_SINGLE_CORE is not set
+# CONFIG_VSYNC_RDMA is not set
+CONFIG_AM_VIDEO=y
+# CONFIG_AM_VIDEO2 is not set
+# CONFIG_KEEP_FRAME_RESERVED is not set
+# CONFIG_SUPPORT_VIDEO_ON_VPP2 is not set
+CONFIG_GE2D_KEEP_FRAME=y
+
+#
+# Video Decoders
+#
+CONFIG_AM_VDEC_MPEG12=y
+CONFIG_AM_VDEC_MPEG4=y
+CONFIG_AM_VDEC_VC1=y
+CONFIG_AM_VDEC_H264=y
+CONFIG_AM_VDEC_H264MVC=y
+CONFIG_AM_VDEC_MJPEG=y
+# CONFIG_AM_ENCODER is not set
+# CONFIG_AM_JPEG_ENCODER is not set
+CONFIG_AM_PIC_DEC=y
+CONFIG_AM_VDEC_REAL=y
+CONFIG_AM_VDEC_AVS=y
+CONFIG_AM_JPEGDEC=y
+CONFIG_AM_TIMESYNC=y
+CONFIG_AM_STREAMING=y
+CONFIG_AM_SUBTITLE=y
+CONFIG_AM_VIDEOCAPTURE=y
+
+#
+# Canvas management driver
+#
+CONFIG_AM_CANVAS=y
+CONFIG_AM_DISPLAY_MODULE=y
+
+#
+# Amlogic video output module
+#
+CONFIG_AM_TV_OUTPUT=y
+# CONFIG_AM_LCD_OUTPUT is not set
+
+#
+# Amlogic video output2 module
+#
+# CONFIG_AM_TV_OUTPUT2 is not set
+
+#
+# Amlogic TV LCD Support
+#
+# CONFIG_AML_TV_LCD is not set
+
+#
+# Amlogic osd module
+#
+CONFIG_FB_AM=y
+CONFIG_FB_OSD2_ENABLE=y
+# CONFIG_FB_OSD2_CURSOR is not set
+CONFIG_FB_OSD2_DEFAULT_BITS_PER_PIXEL=32
+CONFIG_FB_OSD2_DEFAULT_WIDTH=1280
+CONFIG_FB_OSD2_DEFAULT_HEIGHT=720
+CONFIG_FB_OSD2_DEFAULT_WIDTH_VIRTUAL=1280
+CONFIG_FB_OSD2_DEFAULT_HEIGHT_VIRTUAL=1440
+CONFIG_FB_OSD1_DEFAULT_BITS_PER_PIXEL=32
+CONFIG_FB_OSD1_DEFAULT_WIDTH=1280
+CONFIG_FB_OSD1_DEFAULT_HEIGHT=720
+CONFIG_FB_OSD1_DEFAULT_WIDTH_VIRTUAL=1280
+CONFIG_FB_OSD1_DEFAULT_HEIGHT_VIRTUAL=1440
+CONFIG_FB_AMLOGIC_UMP=y
+
+#
+# Amlogic osd_ext module
+#
+
+#
+# Amlogic Backlight Support
+#
+# CONFIG_AMLOGIC_BACKLIGHT is not set
+# CONFIG_AML_BL_PWM_ATTR is not set
+# CONFIG_AML_LOCAL_DIMMING is not set
+# CONFIG_IW7023_BACKLIGHT is not set
+# CONFIG_IW7023_USE_EEPROM is not set
+CONFIG_AM_GE2D=y
+CONFIG_AM_LOGO=y
+CONFIG_AM_HDMI_ONLY=y
+
+#
+# HDMI TX Support
+#
+CONFIG_AML_HDMI_TX=y
+# CONFIG_AML_HDMI_TX_HDCP is not set
+# CONFIG_AML_HDMI_TX_CTS_DVI is not set
+# CONFIG_TVIN is not set
+# CONFIG_AML_EXT_HDMIIN is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Post Process Manager driver
+#
+CONFIG_POST_PROCESS_MANAGER=y
+CONFIG_POST_PROCESS_MANAGER_PPSCALER=y
+CONFIG_POST_PROCESS_MANAGER_3D_PROCESS=y
+
+#
+# Amlogic Camera Support
+#
+# CONFIG_VIDEO_AMLOGIC_CAPTURE is not set
+
+#
+# V4L2 Video Support
+#
+# CONFIG_V4L_AMLOGIC_VIDEO is not set
+# CONFIG_V4L_AMLOGIC_VIDEO2 is not set
+
+#
+# Amlogic ion video support
+#
+# CONFIG_VIDEOBUF2_ION is not set
+# CONFIG_AMLOGIC_IONVIDEO is not set
+
+#
+# Deinterlace driver
+#
+CONFIG_DEINTERLACE=y
+# CONFIG_AM_DEINTERLACE_SD_ONLY is not set
+
+#
+# MIPI Support
+#
+# CONFIG_AMLOGIC_MIPI is not set
+# CONFIG_D2D3_PROCESS is not set
+
+#
+# Amlogic VE & CM
+#
+# CONFIG_AM_VECM is not set
+
+#
+# Amlogic DVB driver
+#
+CONFIG_AM_DVB=y
+
+#
+# AMLOGIC CI Driver
+#
+# CONFIG_AM_CI is not set
+# CONFIG_AM_PCMCIA is not set
+# CONFIG_AM_IOBUS is not set
+# CONFIG_AM_SI2177 is not set
+CONFIG_AM_AVL6211=y
+
+#
+# GPU (ARM Mali)
+#
+
+#
+# Mali 400 UMP device driver
+#
+CONFIG_UMP=y
+# CONFIG_UMP_DEBUG is not set
+
+#
+# Mali GPU OpenGL device driver
+#
+CONFIG_MALI400=m
+# CONFIG_MALI400_DEBUG is not set
+# CONFIG_MALI400_PROFILING is not set
+CONFIG_MALI400_UMP=y
+# CONFIG_MALI400_POWER_PERFORMANCE_POLICY is not set
+CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
+CONFIG_MALI_SHARED_INTERRUPTS=y
+CONFIG_MESON6_GPU_EXTRA=y
+# CONFIG_MALI_PMU_PARALLEL_POWER_UP is not set
+
+#
+# ION support
+#
+# CONFIG_AMLOGIC_ION is not set
+
+#
+# Amlogic Crypto Support
+#
+CONFIG_CRYPTO_AML_HW_CRYPRO=y
+# CONFIG_CRYPTO_DEVICE_DRIVER is not set
+
+#
+# MHL Support
+#
+# CONFIG_PANEL_IT6681 is not set
+
+#
+# Amlogic PMU battery algorithm Support
+#
+
+#
+# Amlogic touch algorithm Support
+#
+# CONFIG_AML_TOUCH_ALGORITHM_SUPPORT is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_FW_LOADER_USER_HELPER=y
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_CMA is not set
+
+#
+# Bus devices
+#
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_DENALI is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_DOCG4 is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_OF_SELFTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_BMP085_I2C is not set
+# CONFIG_BMP085_SPI is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_UFSHCD is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_BCACHE is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
+CONFIG_DM_CRYPT=y
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_MII=y
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
+# CONFIG_NET_DSA_MV88E6131 is not set
+# CONFIG_NET_DSA_MV88E6123_61_65 is not set
+CONFIG_ETHERNET=y
+CONFIG_NET_CADENCE=y
+# CONFIG_ARM_AT91_ETHER is not set
+# CONFIG_MACB is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+CONFIG_NET_VENDOR_CIRRUS=y
+# CONFIG_CS89x0 is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_FARADAY=y
+# CONFIG_FTMAC100 is not set
+# CONFIG_FTGMAC100 is not set
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_MARVELL=y
+# CONFIG_MVMDIO is not set
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_AX88796 is not set
+# CONFIG_ETHOC is not set
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SMSC=y
+# CONFIG_SMC91X is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+CONFIG_NET_VENDOR_STMICRO=y
+# CONFIG_STMMAC_ETH is not set
+CONFIG_NET_VENDOR_WIZNET=y
+# CONFIG_WIZNET_W5100 is not set
+# CONFIG_WIZNET_W5300 is not set
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AT803X_PHY is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_AMLOGIC_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_GPIO is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPPOE is not set
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=y
+# CONFIG_USB_NET_CDC_MBIM is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_QMI_WWAN is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_AT76C50X_USB is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_WIFI_CONTROL_FUNC is not set
+CONFIG_ATH_COMMON=m
+CONFIG_ATH_CARDS=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K=m
+CONFIG_ATH9K_AHB=y
+# CONFIG_ATH9K_DEBUGFS is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+CONFIG_ATH9K_HTC=m
+# CONFIG_ATH9K_HTC_DEBUGFS is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+CONFIG_CARL9170_HWRNG=y
+CONFIG_ATH6KL=m
+# CONFIG_ATH6KL_SDIO is not set
+CONFIG_ATH6KL_USB=m
+# CONFIG_ATH6KL_DEBUG is not set
+CONFIG_AR5523=m
+CONFIG_B43=m
+CONFIG_B43_SSB=y
+# CONFIG_B43_SDIO is not set
+CONFIG_B43_PIO=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_LEDS=y
+CONFIG_B43_HWRNG=y
+# CONFIG_B43_DEBUG is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_BRCMUTIL=m
+CONFIG_BRCMFMAC=m
+# CONFIG_BRCMFMAC_SDIO is not set
+CONFIG_BRCMFMAC_USB=y
+# CONFIG_BRCM_TRACING is not set
+# CONFIG_BRCMDBG is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_LIBERTAS is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+# CONFIG_RT2800USB_RT55XX is not set
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_RTLWIFI is not set
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL_TI is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_ANALOG=y
+CONFIG_JOYSTICK_A3D=y
+CONFIG_JOYSTICK_ADI=y
+CONFIG_JOYSTICK_COBRA=y
+CONFIG_JOYSTICK_GF2K=y
+CONFIG_JOYSTICK_GRIP=y
+CONFIG_JOYSTICK_GRIP_MP=y
+CONFIG_JOYSTICK_GUILLEMOT=y
+CONFIG_JOYSTICK_INTERACT=y
+CONFIG_JOYSTICK_SIDEWINDER=y
+CONFIG_JOYSTICK_TMDC=y
+CONFIG_JOYSTICK_IFORCE=y
+CONFIG_JOYSTICK_IFORCE_USB=y
+CONFIG_JOYSTICK_IFORCE_232=y
+CONFIG_JOYSTICK_WARRIOR=y
+CONFIG_JOYSTICK_MAGELLAN=y
+CONFIG_JOYSTICK_SPACEORB=y
+CONFIG_JOYSTICK_SPACEBALL=y
+CONFIG_JOYSTICK_STINGER=y
+CONFIG_JOYSTICK_TWIDJOY=y
+CONFIG_JOYSTICK_ZHENHUA=y
+CONFIG_JOYSTICK_AS5011=y
+CONFIG_JOYSTICK_JOYDUMP=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_JOYSTICK_XPAD_FF=y
+# CONFIG_JOYSTICK_XPAD_LEDS is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_GP2A is not set
+# CONFIG_INPUT_GPIO_TILT_POLLED is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYCHORD is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_APBPS2 is not set
+CONFIG_GAMEPORT=y
+# CONFIG_GAMEPORT_NS558 is not set
+# CONFIG_GAMEPORT_L4 is not set
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+CONFIG_TTY_PRINTK=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_DCC=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_ATMEL is not set
+# CONFIG_HW_RANDOM_EXYNOS is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# Qualcomm MSM SSBI bus support
+#
+# CONFIG_SSBI is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# CONFIG_PTP_1588_CLOCK_PCH is not set
+CONFIG_PINCTRL=y
+
+#
+# Pin controllers
+#
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_EXYNOS is not set
+# CONFIG_PINCTRL_EXYNOS5440 is not set
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIOLIB=y
+CONFIG_OF_GPIO=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_EM is not set
+# CONFIG_GPIO_RCAR is not set
+# CONFIG_GPIO_TS5500 is not set
+# CONFIG_GPIO_GRGPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_ADNP is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+
+#
+# USB GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_BATTERY_ANDROID is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_POWER_RESET is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_AVS is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB=m
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+# CONFIG_SSB_SDIOHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+# CONFIG_SSB_DRIVER_GPIO is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=m
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_SYSCON is not set
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CAMERA_SUPPORT is not set
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+# CONFIG_MEDIA_RADIO_SUPPORT is not set
+# CONFIG_MEDIA_RC_SUPPORT is not set
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+# CONFIG_TTPCI_EEPROM is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+
+#
+# Media drivers
+#
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Analog/digital TV USB devices
+#
+CONFIG_VIDEO_AU0828=m
+
+#
+# Digital TV USB devices
+#
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+# CONFIG_DVB_USB_AU6610 is not set
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_SMS_USB_DRV=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+
+#
+# Supported MMC/SDIO adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
+CONFIG_MEDIA_COMMON_OPTIONS=y
+
+#
+# common driver options
+#
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_SMS_SIANO_MDTV=m
+# CONFIG_SMS_SIANO_DEBUGFS is not set
+
+#
+# Media ancillary drivers (tuners, sensors, i2c, frontends)
+#
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER_R820T=m
+
+#
+# Multistandard (satellite) frontends
+#
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_CX24116=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_DTV=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_AF9033=m
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+CONFIG_ION=y
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AUO_K190X is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_EXYNOS_VIDEO is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI922X is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_AMS369FG06 is not set
+# CONFIG_LCD_LMS501KF03 is not set
+# CONFIG_LCD_HX8357 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3630 is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+# CONFIG_FB_SSD1307 is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_VERBOSE=y
+CONFIG_SND_PCM_XRUN_DEBUG=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+CONFIG_SND_AML_M6_SOC=y
+# CONFIG_SND_AML_M8_SOC is not set
+# CONFIG_SND_AML_M6_RT5631 is not set
+# CONFIG_SND_AML_M6_RT5616 is not set
+# CONFIG_SND_AML_M6_RT3261 is not set
+# CONFIG_SND_AML_M6_WM8960 is not set
+# CONFIG_SND_AML_M6_PCM2BT is not set
+CONFIG_SND_AML_M_DUMMY_CODEC=y
+# CONFIG_SND_AML_M6TV_AUDIO_CODEC is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_DUMMY_CODEC=y
+# CONFIG_SND_SIMPLE_CARD is not set
+# CONFIG_SOUND_PRIME is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_PRODIKEYS=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+CONFIG_HID_ELECOM=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LENOVO_TPKBD=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_ORTEK=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LCD=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_PS3REMOTE=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_THINGM=m
+CONFIG_HID_THRUSTMASTER=m
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_WACOM=m
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WIIMOTE_EXT=y
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=m
+CONFIG_HID_SENSOR_HUB=m
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_ARCH_HAS_XHCI is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_SSB is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=y
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_CHIPIDEA is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_F81232 is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_METRO is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_WWAN=y
+CONFIG_USB_SERIAL_OPTION=y
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_XSENS_MT is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_WISHBONE is not set
+# CONFIG_USB_SERIAL_ZTE is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_QT2 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_PHY is not set
+# CONFIG_USB_OTG_WAKELOCK is not set
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+# CONFIG_MMC_EMBEDDED_SDIO is not set
+# CONFIG_MMC_PARANOID_SD_INIT is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_EMMC_SECURE_STORAGE is not set
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LP5562 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_RENESAS_TPU is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_OT200 is not set
+# CONFIG_LEDS_BLINKM is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_ONESHOT is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_CPU is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
+# CONFIG_LEDS_TRIGGER_CAMERA is not set
+CONFIG_SWITCH=y
+# CONFIG_SWITCH_GPIO is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SNVS is not set
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=y
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+# CONFIG_VIRT_DRIVERS is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_USBIP_CORE is not set
+# CONFIG_W35UND is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_R8712U is not set
+# CONFIG_RTS5139 is not set
+# CONFIG_TRANZPORT is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_ZSMALLOC is not set
+# CONFIG_USB_ENESTORAGE is not set
+# CONFIG_BCM_WIMAX is not set
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+# CONFIG_STAGING_MEDIA is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ASHMEM=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES=y
+# CONFIG_ANDROID_INTF_ALARM_DEV is not set
+CONFIG_SYNC=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_USB_WPAN_HCD is not set
+# CONFIG_WIMAX_GDM72XX is not set
+# CONFIG_CED1401 is not set
+# CONFIG_DGRP is not set
+CONFIG_CLKDEV_LOOKUP=y
+
+#
+# Hardware Spinlock drivers
+#
+# CONFIG_MAILBOX is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_OF_IOMMU=y
+
+#
+# Remoteproc drivers
+#
+# CONFIG_STE_MODEM_RPROC is not set
+
+#
+# Rpmsg drivers
+#
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_PWM is not set
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+# CONFIG_IPACK_BUS is not set
+# CONFIG_RESET_CONTROLLER is not set
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_DEBUG=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=y
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_XATTR is not set
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_F2FS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=y
+CONFIG_CIFS_STATS=y
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_ACL is not set
+CONFIG_CIFS_DEBUG=y
+CONFIG_CIFS_DEBUG2=y
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_SMB2 is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf-8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_PROVE_RCU_DELAY is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_VERBOSE=y
+# CONFIG_RCU_CPU_STALL_INFO is not set
+CONFIG_RCU_TRACE=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_LKDTM is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+# CONFIG_TRACER_SNAPSHOT is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_PROBE_EVENTS is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_RODATA is not set
+# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
+# CONFIG_PID_IN_CONTEXTIDR is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_CMAC is not set
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA1_ARM is not set
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_ARM is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
+# CONFIG_DDR is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/projects/WeTek.Play/options b/projects/WeTek.Play/options
new file mode 100644
index 0000000000..ccededac29
--- /dev/null
+++ b/projects/WeTek.Play/options
@@ -0,0 +1,158 @@
+################################################################################
+# setup system defaults
+################################################################################
+
+ # The TARGET_CPU variable controls which processor should be targeted for
+ # generated code.
+ case $TARGET_ARCH in
+ arm)
+ # TARGET_CPU:
+ # arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm7m arm7d
+ # arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710c
+ # arm7100 arm720 arm7500 arm7500fe arm7tdmi arm7tdmi-s arm710t
+ # arm720t arm740t strongarm strongarm110 strongarm1100
+ # strongarm1110 arm8 arm810 arm9 arm9e arm920 arm920t arm922t
+ # arm946e-s arm966e-s arm968e-s arm926ej-s arm940t arm9tdmi
+ # arm10tdmi arm1020t arm1026ej-s arm10e arm1020e arm1022e
+ # arm1136j-s arm1136jf-s mpcore mpcorenovfp arm1156t2-s
+ # arm1176jz-s arm1176jzf-s cortex-a8 cortex-a9 cortex-r4
+ # cortex-r4f cortex-m3 cortex-m1 xscale iwmmxt iwmmxt2 ep9312.
+ #
+ TARGET_CPU="cortex-a9"
+
+ # TARGET_FLOAT:
+ # Specifies which floating-point ABI to use. Permissible values are:
+ # soft softfp hard
+ TARGET_FLOAT="hard"
+
+ # TARGET_FPU:
+ # This specifies what floating point hardware (or hardware emulation) is
+ # available on the target. Permissible names are:
+ # fpa fpe2 fpe3 maverick vfp vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16
+ # vfpv3xd vfpv3xd-fp16 neon neon-fp16 vfpv4 vfpv4-d16 fpv4-sp-d16
+ # neon-vfpv4.
+ TARGET_FPU="neon"
+ ;;
+ esac
+
+ # Bootloader to use (syslinux / u-boot / atv-bootloader / bcm2835-bootloader)
+ BOOTLOADER="u-boot"
+
+ # u-boot version to use (default)
+ UBOOT_VERSION=""
+
+ # Configuration for u-boot
+ UBOOT_CONFIG=""
+
+ # Target Configfile for u-boot
+ UBOOT_CONFIGFILE=""
+
+ # Kernel target for u-boot (default 'uImage' if BOOTLOADER=u-boot) (uImage / zImage)
+ KERNEL_UBOOT_TARGET="uImage-dtb"
+
+ # Kernel extra targets to build
+ KERNEL_UBOOT_EXTRA_TARGET="meson6_g18.dtd"
+
+ # Additional kernel make parameters (for example to specify the u-boot loadaddress)
+ KERNEL_MAKE_EXTRACMD=""
+
+ # Kernel to use. values can be:
+ # default: default mainline kernel
+ LINUX="amlogic"
+
+
+################################################################################
+# setup build defaults
+################################################################################
+
+ # Build optimizations (size/normal)
+ OPTIMIZATIONS="size"
+
+ # Project CFLAGS
+ PROJECT_CFLAGS=""
+
+ # LTO (Link Time Optimization) support
+ LTO_SUPPORT="yes"
+
+ # GOLD (Google Linker) support
+ GOLD_SUPPORT="yes"
+
+ # SquashFS compression method (gzip / lzo / xz)
+ SQUASHFS_COMPRESSION="lzo"
+
+################################################################################
+# setup project defaults
+################################################################################
+
+ # build and install ALSA Audio support (yes / no)
+ ALSA_SUPPORT="yes"
+
+ # OpenGL(X) implementation to use (no / Mesa)
+ OPENGL="no"
+
+ # OpenGL-ES implementation to use (no / bcm2835-driver / gpu-viv-bin-mx6q / opengl-meson6)
+ OPENGLES="opengl-meson6"
+
+ # include uvesafb support (yes / no)
+ UVESAFB_SUPPORT="no"
+
+ # Displayserver to use (x11 / no)
+ DISPLAYSERVER="no"
+
+ # Windowmanager to use (ratpoison / fluxbox / none)
+ WINDOWMANAGER="none"
+
+ # Xorg Graphic drivers to use (all / i915,i965,r200,r300,r600,nvidia,nouveau)
+ # Space separated list is supported,
+ # e.g. GRAPHIC_DRIVERS="i915 i965 r300 r600 radeonsi nvidia nouveau"
+ GRAPHIC_DRIVERS=""
+
+ # KODI Player implementation to use (default / bcm2835-driver / libfslvpuwrap / libamcodec)
+ KODIPLAYER_DRIVER="libamcodec"
+
+ # Modules to install in initramfs for early boot
+ INITRAMFS_MODULES="softcursor bitblit font fbcon"
+
+ # additional drivers to install:
+ # for a list of additinoal drivers see packages/linux-drivers
+ # Space separated list is supported,
+ # e.g. ADDITIONAL_DRIVERS="DRIVER1 DRIVER2"
+ ADDITIONAL_DRIVERS=""
+
+ # additional Firmware to use (dvb-firmware, misc-firmware, wlan-firmware)
+ # Space separated list is supported,
+ # e.g. FIRMWARE="dvb-firmware misc-firmware wlan-firmware"
+ FIRMWARE="misc-firmware wlan-firmware dvb-firmware"
+
+ # build and install ATV IR remote support (yes / no)
+ ATVCLIENT_SUPPORT="no"
+
+ # build and install IRServer IR/LCD support (yes / no)
+ IRSERVER_SUPPORT="no"
+
+ # Amlogic IR remote support (yes / no)
+ AMREMOTE_SUPPORT="yes"
+
+ # build with swap support (yes / no)
+ SWAP_SUPPORT="yes"
+
+ # swap support enabled per default (yes / no)
+ SWAP_ENABLED_DEFAULT="no"
+
+ # swapfile size if SWAP_SUPPORT=yes in MB
+ SWAPFILESIZE="128"
+
+ # build with installer (yes / no)
+ INSTALLER_SUPPORT="no"
+
+ # build and install 'RSXS' Screensaver (yes / no)
+ KODI_SCR_RSXS="no"
+
+ # build and install 'ProjectM' Visualization (yes / no)
+ KODI_VIS_PROJECTM="no"
+
+ # build and install 'GOOM' Visualization (yes / no)
+ KODI_VIS_GOOM="no"
+
+ # build and install 'FishBMC' Visualization (yes / no)
+ KODI_VIS_FISHBMC="no"
diff --git a/projects/WeTek.Play/patches/kodi/0001-Fix-ALSA-sound-output-for-Amlogic-based-devices.patch b/projects/WeTek.Play/patches/kodi/0001-Fix-ALSA-sound-output-for-Amlogic-based-devices.patch
new file mode 100644
index 0000000000..d5705a4f69
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0001-Fix-ALSA-sound-output-for-Amlogic-based-devices.patch
@@ -0,0 +1,55 @@
+From 95ea0f29d385bdbd926c5ad13bb6b4f93bb1e3ea Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Wed, 16 Apr 2014 22:02:01 +0300
+Subject: [PATCH 01/16] Fix ALSA sound output for Amlogic-based devices.
+
+---
+ xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp b/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp
+index d30cbab..8679107 100644
+--- a/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp
++++ b/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp
+@@ -83,6 +83,17 @@ static unsigned int ALSASampleRateList[] =
+ 0
+ };
+
++static int CheckNP2(unsigned x)
++{
++ --x;
++ x |= x >> 1;
++ x |= x >> 2;
++ x |= x >> 4;
++ x |= x >> 8;
++ x |= x >> 16;
++ return ++x;
++}
++
+ CAESinkALSA::CAESinkALSA() :
+ m_bufferSize(0),
+ m_formatSampleRateMul(0.0),
+@@ -739,12 +750,20 @@ bool CAESinkALSA::InitializeHW(const ALSAConfig &inconfig, ALSAConfig &outconfig
+ */
+ periodSize = std::min(periodSize, (snd_pcm_uframes_t) sampleRate / 20);
+ bufferSize = std::min(bufferSize, (snd_pcm_uframes_t) sampleRate / 5);
++#if defined(HAS_LIBAMCODEC)
++ // must be pot for pivos.
++ bufferSize = CheckNP2(bufferSize);
++#endif
+
+ /*
+ According to upstream we should set buffer size first - so make sure it is always at least
+ 4x period size to not get underruns (some systems seem to have issues with only 2 periods)
+ */
+ periodSize = std::min(periodSize, bufferSize / 4);
++#if defined(HAS_LIBAMCODEC)
++ // must be pot for pivos.
++ periodSize = CheckNP2(periodSize);
++#endif
+
+ CLog::Log(LOGDEBUG, "CAESinkALSA::InitializeHW - Request: periodSize %lu, bufferSize %lu", periodSize, bufferSize);
+
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0002-Allow-audio-passthrough-for-Amlogic-based-devices.patch b/projects/WeTek.Play/patches/kodi/0002-Allow-audio-passthrough-for-Amlogic-based-devices.patch
new file mode 100644
index 0000000000..a6884e1305
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0002-Allow-audio-passthrough-for-Amlogic-based-devices.patch
@@ -0,0 +1,49 @@
+From 614bc1be8201949036c37b29fd124c0be0f866c6 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Wed, 16 Apr 2014 22:11:51 +0300
+Subject: [PATCH 02/16] Allow audio passthrough for Amlogic-based devices.
+
+---
+ .../AudioEngine/Engines/ActiveAE/ActiveAESink.cpp | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAESink.cpp b/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAESink.cpp
+index b391ff3..a7565f0 100644
+--- a/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAESink.cpp
++++ b/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAESink.cpp
+@@ -91,6 +91,7 @@ AEDeviceType CActiveAESink::GetDeviceType(const std::string &device)
+
+ bool CActiveAESink::HasPassthroughDevice()
+ {
++#ifndef HAS_LIBAMCODEC
+ for (AESinkInfoList::iterator itt = m_sinkInfoList.begin(); itt != m_sinkInfoList.end(); ++itt)
+ {
+ for (AEDeviceInfoList::iterator itt2 = itt->m_deviceInfoList.begin(); itt2 != itt->m_deviceInfoList.end(); ++itt2)
+@@ -101,10 +102,14 @@ bool CActiveAESink::HasPassthroughDevice()
+ }
+ }
+ return false;
++#else
++ return true;
++#endif
+ }
+
+ bool CActiveAESink::SupportsFormat(const std::string &device, AEDataFormat format, int samplerate)
+ {
++#ifndef HAS_LIBAMCODEC
+ std::string dev = device;
+ std::string dri;
+ CAESinkFactory::ParseDevice(dev, dri);
+@@ -135,6 +140,9 @@ bool CActiveAESink::SupportsFormat(const std::string &device, AEDataFormat forma
+ }
+ }
+ return false;
++#else
++ return true;
++#endif
+ }
+
+ enum SINK_STATES
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0003-Enable-true-1920x1080-output-without-upscaling-on-Am.patch b/projects/WeTek.Play/patches/kodi/0003-Enable-true-1920x1080-output-without-upscaling-on-Am.patch
new file mode 100644
index 0000000000..4c729893a8
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0003-Enable-true-1920x1080-output-without-upscaling-on-Am.patch
@@ -0,0 +1,106 @@
+From ee4bbfe929ce547310358c74c83468d514a7e288 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Wed, 16 Apr 2014 23:08:58 +0300
+Subject: [PATCH 03/16] Enable true 1920x1080 output without upscaling on
+ Amlogic-based devices.
+
+---
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp | 48 +++++++++++++++++++++++----
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.h | 3 ++
+ 2 files changed, 44 insertions(+), 7 deletions(-)
+
+diff --git a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+index c19124c..ee17f73 100644
+--- a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
++++ b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+@@ -87,9 +87,12 @@ bool CEGLNativeTypeAmlogic::CreateNativeWindow()
+ if (!nativeWindow)
+ return false;
+
+- nativeWindow->width = 1280;
+- nativeWindow->height = 720;
++ nativeWindow->width = 1920;
++ nativeWindow->height = 1080;
+ m_nativeWindow = nativeWindow;
++
++ SetFramebufferResolution(nativeWindow->width, nativeWindow->height);
++
+ return true;
+ #else
+ return false;
+@@ -134,6 +137,12 @@ bool CEGLNativeTypeAmlogic::GetNativeResolution(RESOLUTION_INFO *res) const
+
+ bool CEGLNativeTypeAmlogic::SetNativeResolution(const RESOLUTION_INFO &res)
+ {
++ if (m_nativeWindow)
++ {
++ ((fbdev_window *)m_nativeWindow)->width = res.iScreenWidth;
++ ((fbdev_window *)m_nativeWindow)->height = res.iScreenHeight;
++ }
++
+ switch((int)(0.5 + res.fRefreshRate))
+ {
+ default:
+@@ -220,12 +229,11 @@ bool CEGLNativeTypeAmlogic::SetDisplayResolution(const char *resolution)
+ // switch display resolution
+ aml_set_sysfs_str("/sys/class/display/mode", modestr.c_str());
+
+- // setup gui freescale depending on display resolution
+ DisableFreeScale();
+- if (StringUtils::StartsWith(modestr, "1080"))
+- {
+- EnableFreeScale();
+- }
++
++ RESOLUTION_INFO res;
++ aml_mode_to_resolution(modestr, &res);
++ SetFramebufferResolution(res);
+
+ return true;
+ }
+@@ -289,3 +297,29 @@ void CEGLNativeTypeAmlogic::DisableFreeScale()
+ close(fd0);
+ }
+ }
++
++void CEGLNativeTypeAmlogic::SetFramebufferResolution(const RESOLUTION_INFO &res) const
++{
++ SetFramebufferResolution(res.iScreenWidth, res.iScreenHeight);
++}
++
++void CEGLNativeTypeAmlogic::SetFramebufferResolution(int width, int height) const
++{
++ int fd0;
++ std::string framebuffer = "/dev/" + m_framebuffer_name;
++
++ if ((fd0 = open(framebuffer.c_str(), O_RDWR)) >= 0)
++ {
++ struct fb_var_screeninfo vinfo;
++ if (ioctl(fd0, FBIOGET_VSCREENINFO, &vinfo) == 0)
++ {
++ vinfo.xres = width;
++ vinfo.yres = height;
++ vinfo.xres_virtual = 1920;
++ vinfo.yres_virtual = 2160;
++ vinfo.bits_per_pixel = 32;
++ ioctl(fd0, FBIOPUT_VSCREENINFO, &vinfo);
++ }
++ close(fd0);
++ }
++}
+diff --git a/xbmc/windowing/egl/EGLNativeTypeAmlogic.h b/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
+index 87be029..69ca00a 100644
+--- a/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
++++ b/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
+@@ -53,5 +53,8 @@ protected:
+ void DisableFreeScale();
+
+ private:
++ void SetFramebufferResolution(const RESOLUTION_INFO &res) const;
++ void SetFramebufferResolution(int width, int height) const;
++
+ std::string m_framebuffer_name;
+ };
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0004-Add-support-for-retrieval-of-CPU-temperature-on-Amlo.patch b/projects/WeTek.Play/patches/kodi/0004-Add-support-for-retrieval-of-CPU-temperature-on-Amlo.patch
new file mode 100644
index 0000000000..14d11c0597
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0004-Add-support-for-retrieval-of-CPU-temperature-on-Amlo.patch
@@ -0,0 +1,59 @@
+From c137ada0da2582c6438ddb2966cc582f8574773e Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Tue, 22 Jul 2014 12:18:29 +0300
+Subject: [PATCH 04/16] Add support for retrieval of CPU temperature on
+ Amlogic
+
+---
+ xbmc/utils/CPUInfo.cpp | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/xbmc/utils/CPUInfo.cpp b/xbmc/utils/CPUInfo.cpp
+index 71aa745..f80e7ba 100644
+--- a/xbmc/utils/CPUInfo.cpp
++++ b/xbmc/utils/CPUInfo.cpp
+@@ -18,6 +18,7 @@
+ *
+ */
+
++#include "system.h"
+ #include "CPUInfo.h"
+ #include "Temperature.h"
+ #include
+@@ -95,6 +96,10 @@
+ #include "settings/AdvancedSettings.h"
+ #include "utils/StringUtils.h"
+
++#ifdef HAS_LIBAMCODEC
++#include "utils/AMLUtils.h"
++#endif
++
+ using namespace std;
+
+ // In milliseconds
+@@ -265,6 +270,10 @@ CCPUInfo::CCPUInfo(void)
+ m_fProcTemperature = fopen("/sys/class/hwmon/hwmon0/temp1_input", "r");
+ if (m_fProcTemperature == NULL)
+ m_fProcTemperature = fopen("/sys/class/thermal/thermal_zone0/temp", "r"); // On Raspberry PIs
++#ifdef HAS_LIBAMCODEC
++ if (m_fProcTemperature == NULL)
++ m_fProcTemperature = fopen("/sys/class/saradc/temperature", "r");
++#endif
+
+ m_fCPUFreq = fopen ("/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq", "r");
+ if (!m_fCPUFreq)
+@@ -607,7 +616,10 @@ bool CCPUInfo::getTemperature(CTemperature& temperature)
+ if (!ret)
+ {
+ ret = fscanf(m_fProcTemperature, "%d", &value);
+- value = value / 1000;
++#ifndef HAS_LIBAMCODEC
++ if (!aml_present())
++ value = value / 1000;
++#endif
+ scale = 'c';
+ ret++;
+ }
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0005-Add-support-for-AV-CVBS-video-output-on-Amlogic.patch b/projects/WeTek.Play/patches/kodi/0005-Add-support-for-AV-CVBS-video-output-on-Amlogic.patch
new file mode 100644
index 0000000000..601d90ce55
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0005-Add-support-for-AV-CVBS-video-output-on-Amlogic.patch
@@ -0,0 +1,131 @@
+From 436e67a7fa4969f41765990566f257ffafae9de6 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Wed, 23 Jul 2014 22:23:34 +0300
+Subject: [PATCH 05/16] Add support for AV (CVBS) video output on Amlogic
+
+Conflicts:
+
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+---
+ xbmc/utils/AMLUtils.cpp | 18 +++++++++++++
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp | 37 +++++++++++++++++++++++----
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.h | 1 +
+ 3 files changed, 51 insertions(+), 5 deletions(-)
+
+diff --git a/xbmc/utils/AMLUtils.cpp b/xbmc/utils/AMLUtils.cpp
+index 9553745..9d5b165 100644
+--- a/xbmc/utils/AMLUtils.cpp
++++ b/xbmc/utils/AMLUtils.cpp
+@@ -328,6 +328,24 @@ bool aml_mode_to_resolution(const char *mode, RESOLUTION_INFO *res)
+ res->fRefreshRate = 60;
+ res->dwFlags = D3DPRESENTFLAG_PROGRESSIVE;
+ }
++ else if (fromMode.Equals("480cvbs"))
++ {
++ res->iWidth = 720;
++ res->iHeight= 480;
++ res->iScreenWidth = 720;
++ res->iScreenHeight= 480;
++ res->fRefreshRate = 60;
++ res->dwFlags = D3DPRESENTFLAG_INTERLACED;
++ }
++ else if (fromMode.Equals("576cvbs"))
++ {
++ res->iWidth = 720;
++ res->iHeight= 576;
++ res->iScreenWidth = 720;
++ res->iScreenHeight= 576;
++ res->fRefreshRate = 50;
++ res->dwFlags = D3DPRESENTFLAG_INTERLACED;
++ }
+ else if (fromMode.Equals("720p"))
+ {
+ res->iWidth = 1280;
+diff --git a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+index ee17f73..ab80343 100644
+--- a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
++++ b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+@@ -159,6 +159,10 @@ bool CEGLNativeTypeAmlogic::SetNativeResolution(const RESOLUTION_INFO &res)
+ else
+ SetDisplayResolution("1080p");
+ break;
++ case 720:
++ if (!IsHdmiConnected())
++ SetDisplayResolution("480cvbs");
++ break;
+ }
+ break;
+ case 50:
+@@ -174,6 +178,10 @@ bool CEGLNativeTypeAmlogic::SetNativeResolution(const RESOLUTION_INFO &res)
+ else
+ SetDisplayResolution("1080p50hz");
+ break;
++ case 720:
++ if (!IsHdmiConnected())
++ SetDisplayResolution("576cvbs");
++ break;
+ }
+ break;
+ case 30:
+@@ -189,9 +197,18 @@ bool CEGLNativeTypeAmlogic::SetNativeResolution(const RESOLUTION_INFO &res)
+
+ bool CEGLNativeTypeAmlogic::ProbeResolutions(std::vector &resolutions)
+ {
+- char valstr[256] = {0};
+- aml_get_sysfs_str("/sys/class/amhdmitx/amhdmitx0/disp_cap", valstr, 255);
+- std::vector probe_str = StringUtils::Split(valstr, "\n");
++ std::vector probe_str;
++ if (IsHdmiConnected())
++ {
++ char valstr[256] = {0};
++ aml_get_sysfs_str("/sys/class/amhdmitx/amhdmitx0/disp_cap", valstr, 255);
++ probe_str = StringUtils::Split(valstr, "\n");
++ }
++ else
++ {
++ probe_str.push_back("480cvbs");
++ probe_str.push_back("576cvbs");
++ }
+
+ resolutions.clear();
+ RESOLUTION_INFO res;
+@@ -209,8 +226,11 @@ bool CEGLNativeTypeAmlogic::GetPreferredResolution(RESOLUTION_INFO *res) const
+ // check display/mode, it gets defaulted at boot
+ if (!GetNativeResolution(res))
+ {
+- // punt to 720p if we get nothing
+- aml_mode_to_resolution("720p", res);
++ // punt to 720p or 576cvbs if we get nothing
++ if (IsHdmiConnected())
++ aml_mode_to_resolution("720p", res);
++ else
++ aml_mode_to_resolution("576cvbs", res);
+ }
+
+ return true;
+@@ -323,3 +343,10 @@ void CEGLNativeTypeAmlogic::SetFramebufferResolution(int width, int height) cons
+ close(fd0);
+ }
+ }
++
++bool CEGLNativeTypeAmlogic::IsHdmiConnected() const
++{
++ char hpd_state[2] = {0};
++ aml_get_sysfs_str("/sys/class/amhdmitx/amhdmitx0/hpd_state", hpd_state, 2);
++ return hpd_state[0] == '1';
++}
+diff --git a/xbmc/windowing/egl/EGLNativeTypeAmlogic.h b/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
+index 69ca00a..adb4d51 100644
+--- a/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
++++ b/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
+@@ -55,6 +55,7 @@ protected:
+ private:
+ void SetFramebufferResolution(const RESOLUTION_INFO &res) const;
+ void SetFramebufferResolution(int width, int height) const;
++ bool IsHdmiConnected() const;
+
+ std::string m_framebuffer_name;
+ };
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0006-Fix-the-issue-when-the-video-display-is-disabled-aft.patch b/projects/WeTek.Play/patches/kodi/0006-Fix-the-issue-when-the-video-display-is-disabled-aft.patch
new file mode 100644
index 0000000000..f671024de1
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0006-Fix-the-issue-when-the-video-display-is-disabled-aft.patch
@@ -0,0 +1,113 @@
+From 8e7abac4cd92434339268123257245086ba37c21 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Tue, 29 Jul 2014 10:31:07 +0300
+Subject: [PATCH 06/16] Fix the issue when the video display is disabled after
+ a resolution change
+
+---
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp | 57 +--------------------------
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.h | 1 -
+ 2 files changed, 1 insertion(+), 57 deletions(-)
+
+diff --git a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+index ab80343..468a99e 100644
+--- a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
++++ b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+@@ -65,7 +65,7 @@ void CEGLNativeTypeAmlogic::Initialize()
+ aml_permissions();
+ aml_cpufreq_min(true);
+ aml_cpufreq_max(true);
+- return;
++ DisableFreeScale();
+ }
+ void CEGLNativeTypeAmlogic::Destroy()
+ {
+@@ -249,8 +249,6 @@ bool CEGLNativeTypeAmlogic::SetDisplayResolution(const char *resolution)
+ // switch display resolution
+ aml_set_sysfs_str("/sys/class/display/mode", modestr.c_str());
+
+- DisableFreeScale();
+-
+ RESOLUTION_INFO res;
+ aml_mode_to_resolution(modestr, &res);
+ SetFramebufferResolution(res);
+@@ -258,64 +256,11 @@ bool CEGLNativeTypeAmlogic::SetDisplayResolution(const char *resolution)
+ return true;
+ }
+
+-void CEGLNativeTypeAmlogic::EnableFreeScale()
+-{
+- // enable OSD free scale using frame buffer size of 720p
+- aml_set_sysfs_int("/sys/class/graphics/fb0/free_scale", 0);
+- aml_set_sysfs_int("/sys/class/graphics/fb1/free_scale", 0);
+- aml_set_sysfs_int("/sys/class/graphics/fb0/scale_width", 1280);
+- aml_set_sysfs_int("/sys/class/graphics/fb0/scale_height", 720);
+- aml_set_sysfs_int("/sys/class/graphics/fb1/scale_width", 1280);
+- aml_set_sysfs_int("/sys/class/graphics/fb1/scale_height", 720);
+-
+- // enable video free scale (scaling to 1920x1080 with frame buffer size 1280x720)
+- aml_set_sysfs_int("/sys/class/ppmgr/ppscaler", 0);
+- aml_set_sysfs_int("/sys/class/video/disable_video", 1);
+- aml_set_sysfs_int("/sys/class/ppmgr/ppscaler", 1);
+- aml_set_sysfs_str("/sys/class/ppmgr/ppscaler_rect", "0 0 1919 1079 0");
+- aml_set_sysfs_str("/sys/class/ppmgr/disp", "1280 720");
+- //
+- aml_set_sysfs_int("/sys/class/graphics/fb0/scale_width", 1280);
+- aml_set_sysfs_int("/sys/class/graphics/fb0/scale_height", 720);
+- aml_set_sysfs_int("/sys/class/graphics/fb1/scale_width", 1280);
+- aml_set_sysfs_int("/sys/class/graphics/fb1/scale_height", 720);
+- //
+- aml_set_sysfs_int("/sys/class/video/disable_video", 2);
+- aml_set_sysfs_str("/sys/class/display/axis", "0 0 1279 719 0 0 0 0");
+- aml_set_sysfs_str("/sys/class/ppmgr/ppscaler_rect", "0 0 1279 719 1");
+- //
+- aml_set_sysfs_int("/sys/class/graphics/fb0/free_scale", 1);
+- aml_set_sysfs_int("/sys/class/graphics/fb1/free_scale", 1);
+- aml_set_sysfs_str("/sys/class/graphics/fb0/free_scale_axis", "0 0 1279 719");
+-}
+-
+ void CEGLNativeTypeAmlogic::DisableFreeScale()
+ {
+ // turn off frame buffer freescale
+ aml_set_sysfs_int("/sys/class/graphics/fb0/free_scale", 0);
+ aml_set_sysfs_int("/sys/class/graphics/fb1/free_scale", 0);
+- aml_set_sysfs_str("/sys/class/graphics/fb0/free_scale_axis", "0 0 1279 719");
+-
+- aml_set_sysfs_int("/sys/class/ppmgr/ppscaler", 0);
+- aml_set_sysfs_int("/sys/class/video/disable_video", 0);
+- // now default video display to off
+- aml_set_sysfs_int("/sys/class/video/disable_video", 1);
+-
+- // revert display axis
+- int fd0;
+- std::string framebuffer = "/dev/" + m_framebuffer_name;
+-
+- if ((fd0 = open(framebuffer.c_str(), O_RDWR)) >= 0)
+- {
+- struct fb_var_screeninfo vinfo;
+- if (ioctl(fd0, FBIOGET_VSCREENINFO, &vinfo) == 0)
+- {
+- char daxis_str[255] = {0};
+- sprintf(daxis_str, "%d %d %d %d 0 0 0 0", 0, 0, vinfo.xres-1, vinfo.yres-1);
+- aml_set_sysfs_str("/sys/class/display/axis", daxis_str);
+- }
+- close(fd0);
+- }
+ }
+
+ void CEGLNativeTypeAmlogic::SetFramebufferResolution(const RESOLUTION_INFO &res) const
+diff --git a/xbmc/windowing/egl/EGLNativeTypeAmlogic.h b/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
+index adb4d51..79e5733 100644
+--- a/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
++++ b/xbmc/windowing/egl/EGLNativeTypeAmlogic.h
+@@ -49,7 +49,6 @@ public:
+
+ protected:
+ bool SetDisplayResolution(const char *resolution);
+- void EnableFreeScale();
+ void DisableFreeScale();
+
+ private:
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0007-aml-Update-all-virtual-consoles-when-changing-frameb.patch b/projects/WeTek.Play/patches/kodi/0007-aml-Update-all-virtual-consoles-when-changing-frameb.patch
new file mode 100644
index 0000000000..49eb84e6f9
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0007-aml-Update-all-virtual-consoles-when-changing-frameb.patch
@@ -0,0 +1,27 @@
+From e6946cdeeb07c7aaabf0665d2ccba802b8dabafd Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Thu, 4 Sep 2014 00:28:23 +0300
+Subject: [PATCH 07/16] [aml] Update all virtual consoles when changing
+ framebuffer geometry after a resolution change
+
+That helps to resolve the issue when framebuffer size is not always correctly change according to the resolution set.
+It seems that the issue appeared after updating to the U-Boot bootloader released 2014-08-24 by Amlogic.
+---
+ xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+index 468a99e..f8ceb3d 100644
+--- a/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
++++ b/xbmc/windowing/egl/EGLNativeTypeAmlogic.cpp
+@@ -283,6 +283,7 @@ void CEGLNativeTypeAmlogic::SetFramebufferResolution(int width, int height) cons
+ vinfo.xres_virtual = 1920;
+ vinfo.yres_virtual = 2160;
+ vinfo.bits_per_pixel = 32;
++ vinfo.activate = FB_ACTIVATE_ALL;
+ ioctl(fd0, FBIOPUT_VSCREENINFO, &vinfo);
+ }
+ close(fd0);
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0008-Reorder-libraries-in-configure-script-to-prevent-lin.patch b/projects/WeTek.Play/patches/kodi/0008-Reorder-libraries-in-configure-script-to-prevent-lin.patch
new file mode 100644
index 0000000000..7bc4867083
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0008-Reorder-libraries-in-configure-script-to-prevent-lin.patch
@@ -0,0 +1,30 @@
+From 8a3d4276a0d42795bad6d46bc30c9490f97592a6 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Mon, 8 Sep 2014 23:29:40 +0300
+Subject: [PATCH 08/16] Reorder libraries in configure script to prevent
+ linker errors when linking with libsmbclient
+
+Place libsmbclient before all other libraries to prevent linker errors when linking
+with libsmbclient if the libc that is currently used doesn't contain some functions
+such as dn_expand (which are often included in libc), but are actually included in
+libresolv.
+---
+ configure.in | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configure.in b/configure.in
+index d7c971d..83545d9 100644
+--- a/configure.in
++++ b/configure.in
+@@ -1468,7 +1468,7 @@ fi
+ # samba
+ if test "x$use_samba" != "xno"; then
+ PKG_CHECK_MODULES([SAMBA], [smbclient],
+- [INCLUDES="$INCLUDES $SAMBA_CFLAGS"; LIBS="$LIBS $SAMBA_LIBS"],
++ [INCLUDES="$INCLUDES $SAMBA_CFLAGS"; LIBS="$SAMBA_LIBS $LIBS"],
+ [AC_CHECK_LIB([smbclient], [main],,
+ use_samba=no;AC_MSG_ERROR($missing_library))
+ USE_LIBSMBCLIENT=0
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0009-aml-Change-the-sample-rates-that-are-supported-by-AL.patch b/projects/WeTek.Play/patches/kodi/0009-aml-Change-the-sample-rates-that-are-supported-by-AL.patch
new file mode 100644
index 0000000000..47515cfa50
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0009-aml-Change-the-sample-rates-that-are-supported-by-AL.patch
@@ -0,0 +1,48 @@
+From 5f06d8bb7e427e43b8a2ed1d3399439f3ad156d1 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Fri, 19 Sep 2014 01:55:12 +0300
+Subject: [PATCH 09/16] [aml] Change the sample rates that are supported by
+ ALSA but unsupported by HDMI to the closest supported
+ value
+
+Conflicts:
+
+ xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp
+---
+ xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp b/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp
+index 8679107..f2b29d4 100644
+--- a/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp
++++ b/xbmc/cores/AudioEngine/Sinks/AESinkALSA.cpp
+@@ -664,6 +664,26 @@ bool CAESinkALSA::InitializeHW(const ALSAConfig &inconfig, ALSAConfig &outconfig
+ snd_pcm_hw_params_set_access(m_pcm, hw_params, SND_PCM_ACCESS_RW_INTERLEAVED);
+
+ unsigned int sampleRate = inconfig.sampleRate;
++#ifdef HAS_LIBAMCODEC
++ // Change the sample rates that are supported by ALSA but unsupported by HDMI to the closest supported value
++ switch (sampleRate)
++ {
++ case 5512:
++ case 8000:
++ case 11025:
++ case 16000:
++ case 22050:
++ sampleRate = 44100;
++ break;
++ case 64000:
++ sampleRate = 88200;
++ break;
++ case 384000:
++ sampleRate = 192000;
++ break;
++ }
++#endif
++
+ snd_pcm_hw_params_set_rate_near (m_pcm, hw_params, &sampleRate, NULL);
+
+ unsigned int channelCount = inconfig.channels;
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0010-aml-Fill-audio-packets-completely-when-resampling-to.patch b/projects/WeTek.Play/patches/kodi/0010-aml-Fill-audio-packets-completely-when-resampling-to.patch
new file mode 100644
index 0000000000..3d63a68cfc
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0010-aml-Fill-audio-packets-completely-when-resampling-to.patch
@@ -0,0 +1,29 @@
+From 23501841efd32b519de4e8924f760354fb703572 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Sat, 20 Sep 2014 04:43:52 +0300
+Subject: [PATCH 10/16] [aml] Fill audio packets completely when resampling to
+ prevent 'audio data unaligned' kernel warnings
+
+---
+ .../Engines/ActiveAE/ActiveAEBuffer.cpp | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAEBuffer.cpp b/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAEBuffer.cpp
+index 3b0a015..ef431a4 100644
+--- a/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAEBuffer.cpp
++++ b/xbmc/cores/AudioEngine/Engines/ActiveAE/ActiveAEBuffer.cpp
+@@ -143,7 +143,11 @@ CActiveAEBufferPoolResample::CActiveAEBufferPoolResample(AEAudioFormat inputForm
+ if (AE_IS_RAW(m_inputFormat.m_dataFormat))
+ m_inputFormat.m_dataFormat = AE_FMT_S16NE;
+ m_resampler = NULL;
++#ifdef HAS_LIBAMCODEC
++ m_fillPackets = true;
++#else
+ m_fillPackets = false;
++#endif
+ m_drain = false;
+ m_empty = true;
+ m_procSample = NULL;
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0011-aml-Use-fpsrate-and-fpsscale-instead-of-rfpsrate-and.patch b/projects/WeTek.Play/patches/kodi/0011-aml-Use-fpsrate-and-fpsscale-instead-of-rfpsrate-and.patch
new file mode 100644
index 0000000000..edd8ef0b07
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0011-aml-Use-fpsrate-and-fpsscale-instead-of-rfpsrate-and.patch
@@ -0,0 +1,120 @@
+From 5091ef4fb995c399087435a0d7efc96318099c70 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Sun, 21 Sep 2014 17:17:14 +0300
+Subject: [PATCH 11/16] [aml] Use fpsrate and fpsscale instead of rfpsrate and
+ rfpsscale to detect framerate
+
+---
+ xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp | 12 ++-----
+ .../DVDCodecs/Video/DVDVideoCodecAmlogic.cpp | 38 +++++++++-----------
+ 2 files changed, 20 insertions(+), 30 deletions(-)
+
+diff --git a/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp b/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
+index 47f6594..e859eaa 100644
+--- a/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
++++ b/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
+@@ -1465,14 +1465,8 @@ bool CAMLCodec::OpenDecoder(CDVDStreamInfo &hints)
+ am_private->video_ratio64 = ((int64_t)video_ratio.num << 32) | video_ratio.den;
+
+ // handle video rate
+- if (hints.rfpsrate > 0 && hints.rfpsscale != 0)
++ if (hints.fpsrate > 0 && hints.fpsscale != 0)
+ {
+- // check ffmpeg r_frame_rate 1st
+- am_private->video_rate = 0.5 + (float)UNIT_FREQ * hints.rfpsscale / hints.rfpsrate;
+- }
+- else if (hints.fpsrate > 0 && hints.fpsscale != 0)
+- {
+- // then ffmpeg avg_frame_rate next
+ am_private->video_rate = 0.5 + (float)UNIT_FREQ * hints.fpsscale / hints.fpsrate;
+ }
+
+@@ -1545,8 +1539,8 @@ bool CAMLCodec::OpenDecoder(CDVDStreamInfo &hints)
+ CLog::Log(LOGDEBUG, "CAMLCodec::OpenDecoder "
+ "hints.width(%d), hints.height(%d), hints.codec(%d), hints.codec_tag(%d), hints.pid(%d)",
+ hints.width, hints.height, hints.codec, hints.codec_tag, hints.pid);
+- CLog::Log(LOGDEBUG, "CAMLCodec::OpenDecoder hints.fpsrate(%d), hints.fpsscale(%d), hints.rfpsrate(%d), hints.rfpsscale(%d), video_rate(%d)",
+- hints.fpsrate, hints.fpsscale, hints.rfpsrate, hints.rfpsscale, am_private->video_rate);
++ CLog::Log(LOGDEBUG, "CAMLCodec::OpenDecoder hints.fpsrate(%d), hints.fpsscale(%d), video_rate(%d)",
++ hints.fpsrate, hints.fpsscale, am_private->video_rate);
+ CLog::Log(LOGDEBUG, "CAMLCodec::OpenDecoder hints.aspect(%f), video_ratio.num(%d), video_ratio.den(%d)",
+ hints.aspect, video_ratio.num, video_ratio.den);
+ CLog::Log(LOGDEBUG, "CAMLCodec::OpenDecoder hints.orientation(%d), hints.forced_aspect(%d), hints.extrasize(%d)",
+diff --git a/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp b/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp
+index 24c1ab9..960aae1 100644
+--- a/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp
++++ b/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp
+@@ -74,9 +74,7 @@ bool CDVDVideoCodecAmlogic::Open(CDVDStreamInfo &hints, CDVDCodecOptions &option
+ m_mpeg2_sequence->width = m_hints.width;
+ m_mpeg2_sequence->height = m_hints.height;
+ m_mpeg2_sequence->ratio = m_hints.aspect;
+- if (m_hints.rfpsrate > 0 && m_hints.rfpsscale != 0)
+- m_mpeg2_sequence->rate = (float)m_hints.rfpsrate / m_hints.rfpsscale;
+- else if (m_hints.fpsrate > 0 && m_hints.fpsscale != 0)
++ if (m_hints.fpsrate > 0 && m_hints.fpsscale != 0)
+ m_mpeg2_sequence->rate = (float)m_hints.fpsrate / m_hints.fpsscale;
+ else
+ m_mpeg2_sequence->rate = 1.0;
+@@ -374,43 +372,41 @@ void CDVDVideoCodecAmlogic::FrameRateTracking(uint8_t *pData, int iSize, double
+ {
+ default:
+ case 0x01:
+- m_hints.rfpsrate = 24000.0;
+- m_hints.rfpsscale = 1001.0;
++ m_hints.fpsrate = 24000.0;
++ m_hints.fpsscale = 1001.0;
+ break;
+ case 0x02:
+- m_hints.rfpsrate = 24000.0;
+- m_hints.rfpsscale = 1000.0;
++ m_hints.fpsrate = 24000.0;
++ m_hints.fpsscale = 1000.0;
+ break;
+ case 0x03:
+- m_hints.rfpsrate = 25000.0;
+- m_hints.rfpsscale = 1000.0;
++ m_hints.fpsrate = 25000.0;
++ m_hints.fpsscale = 1000.0;
+ break;
+ case 0x04:
+- m_hints.rfpsrate = 30000.0;
+- m_hints.rfpsscale = 1001.0;
++ m_hints.fpsrate = 30000.0;
++ m_hints.fpsscale = 1001.0;
+ break;
+ case 0x05:
+- m_hints.rfpsrate = 30000.0;
+- m_hints.rfpsscale = 1000.0;
++ m_hints.fpsrate = 30000.0;
++ m_hints.fpsscale = 1000.0;
+ break;
+ case 0x06:
+- m_hints.rfpsrate = 50000.0;
+- m_hints.rfpsscale = 1000.0;
++ m_hints.fpsrate = 50000.0;
++ m_hints.fpsscale = 1000.0;
+ break;
+ case 0x07:
+- m_hints.rfpsrate = 60000.0;
+- m_hints.rfpsscale = 1001.0;
++ m_hints.fpsrate = 60000.0;
++ m_hints.fpsscale = 1001.0;
+ break;
+ case 0x08:
+- m_hints.rfpsrate = 60000.0;
+- m_hints.rfpsscale = 1000.0;
++ m_hints.fpsrate = 60000.0;
++ m_hints.fpsscale = 1000.0;
+ break;
+ }
+ m_hints.width = m_mpeg2_sequence->width;
+ m_hints.height = m_mpeg2_sequence->height;
+ m_hints.aspect = m_mpeg2_sequence->ratio;
+- m_hints.fpsrate = m_hints.rfpsrate;
+- m_hints.fpsscale = m_hints.rfpsscale;
+ }
+ return;
+ }
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0012-Fix-incorrect-frame-rate-detection-of-some-videos-wi.patch b/projects/WeTek.Play/patches/kodi/0012-Fix-incorrect-frame-rate-detection-of-some-videos-wi.patch
new file mode 100644
index 0000000000..faefb8960b
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0012-Fix-incorrect-frame-rate-detection-of-some-videos-wi.patch
@@ -0,0 +1,143 @@
+From 2e9b3a3a6e7b2055479e110c5cbec0d696af8240 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Sun, 21 Sep 2014 17:20:25 +0300
+Subject: [PATCH 12/16] Fix incorrect frame rate detection of some videos with
+ variable frame rate.
+
+Use FFMPEG's r_frame_rate, if it as valid, as a video stream frame rate, otherwise use avg_frame_rate.
+Also remove CDVDStreamInfo.rfpsscale, CDVDStreamInfo.rfpsrate, CDemuxStreamVideo.irFpsScale and CDemuxStreamVideo.irFpsRate,
+they are not needed anymore.
+---
+ xbmc/cores/dvdplayer/DVDDemuxers/DVDDemux.h | 4 ---
+ .../cores/dvdplayer/DVDDemuxers/DVDDemuxFFmpeg.cpp | 29 +++++++-------------
+ xbmc/cores/dvdplayer/DVDStreamInfo.cpp | 8 ------
+ xbmc/cores/dvdplayer/DVDStreamInfo.h | 2 --
+ 4 files changed, 10 insertions(+), 33 deletions(-)
+
+diff --git a/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemux.h b/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemux.h
+index 40c16c0..98c3513 100644
+--- a/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemux.h
++++ b/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemux.h
+@@ -148,8 +148,6 @@ public:
+ {
+ iFpsScale = 0;
+ iFpsRate = 0;
+- irFpsScale = 0;
+- irFpsRate = 0;
+ iHeight = 0;
+ iWidth = 0;
+ fAspect = 0.0;
+@@ -164,8 +162,6 @@ public:
+ virtual ~CDemuxStreamVideo() {}
+ int iFpsScale; // scale of 1000 and a rate of 29970 will result in 29.97 fps
+ int iFpsRate;
+- int irFpsScale;
+- int irFpsRate;
+ int iHeight; // height of the stream reported by the demuxer
+ int iWidth; // width of the stream reported by the demuxer
+ float fAspect; // display aspect of stream
+diff --git a/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemuxFFmpeg.cpp b/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemuxFFmpeg.cpp
+index 300bff7..9a2db60 100644
+--- a/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemuxFFmpeg.cpp
++++ b/xbmc/cores/dvdplayer/DVDDemuxers/DVDDemuxFFmpeg.cpp
+@@ -1117,34 +1117,25 @@ CDemuxStream* CDVDDemuxFFmpeg::AddStream(int iId)
+ #else
+ AVRational r_frame_rate = pStream->r_frame_rate;
+ #endif
++ int rFrameRate = 0;
++ if (r_frame_rate.den && r_frame_rate.num)
++ rFrameRate = r_frame_rate.num / r_frame_rate.den;
++ bool rFrameRateValid = rFrameRate >= 5 && rFrameRate <= 100;
+
+- //average fps is more accurate for mkv files
+- if (m_bMatroska && pStream->avg_frame_rate.den && pStream->avg_frame_rate.num)
+- {
+- st->iFpsRate = pStream->avg_frame_rate.num;
+- st->iFpsScale = pStream->avg_frame_rate.den;
+- }
+- else if(r_frame_rate.den && r_frame_rate.num)
++ if (rFrameRateValid)
+ {
+ st->iFpsRate = r_frame_rate.num;
+ st->iFpsScale = r_frame_rate.den;
+ }
+- else
+- {
+- st->iFpsRate = 0;
+- st->iFpsScale = 0;
+- }
+-
+- // added for aml hw decoder, mkv frame-rate can be wrong.
+- if (r_frame_rate.den && r_frame_rate.num)
++ else if(pStream->avg_frame_rate.den && pStream->avg_frame_rate.num)
+ {
+- st->irFpsRate = r_frame_rate.num;
+- st->irFpsScale = r_frame_rate.den;
++ st->iFpsRate = pStream->avg_frame_rate.num;
++ st->iFpsScale = pStream->avg_frame_rate.den;
+ }
+ else
+ {
+- st->irFpsRate = 0;
+- st->irFpsScale = 0;
++ st->iFpsRate = 0;
++ st->iFpsScale = 0;
+ }
+
+ if (pStream->codec_info_nb_frames > 0
+diff --git a/xbmc/cores/dvdplayer/DVDStreamInfo.cpp b/xbmc/cores/dvdplayer/DVDStreamInfo.cpp
+index c1dbd85..03facbe 100644
+--- a/xbmc/cores/dvdplayer/DVDStreamInfo.cpp
++++ b/xbmc/cores/dvdplayer/DVDStreamInfo.cpp
+@@ -52,8 +52,6 @@ void CDVDStreamInfo::Clear()
+
+ fpsscale = 0;
+ fpsrate = 0;
+- rfpsscale= 0;
+- rfpsrate = 0;
+ height = 0;
+ width = 0;
+ aspect = 0.0;
+@@ -97,8 +95,6 @@ bool CDVDStreamInfo::Equal(const CDVDStreamInfo& right, bool withextradata)
+ // VIDEO
+ if( fpsscale != right.fpsscale
+ || fpsrate != right.fpsrate
+- || rfpsscale!= right.rfpsscale
+- || rfpsrate != right.rfpsrate
+ || height != right.height
+ || width != right.width
+ || stills != right.stills
+@@ -159,8 +155,6 @@ void CDVDStreamInfo::Assign(const CDVDStreamInfo& right, bool withextradata)
+ // VIDEO
+ fpsscale = right.fpsscale;
+ fpsrate = right.fpsrate;
+- rfpsscale= right.rfpsscale;
+- rfpsrate = right.rfpsrate;
+ height = right.height;
+ width = right.width;
+ aspect = right.aspect;
+@@ -220,8 +214,6 @@ void CDVDStreamInfo::Assign(const CDemuxStream& right, bool withextradata)
+ const CDemuxStreamVideo *stream = static_cast(&right);
+ fpsscale = stream->iFpsScale;
+ fpsrate = stream->iFpsRate;
+- rfpsscale = stream->irFpsScale;
+- rfpsrate = stream->irFpsRate;
+ height = stream->iHeight;
+ width = stream->iWidth;
+ aspect = stream->fAspect;
+diff --git a/xbmc/cores/dvdplayer/DVDStreamInfo.h b/xbmc/cores/dvdplayer/DVDStreamInfo.h
+index de66625..d775d78 100644
+--- a/xbmc/cores/dvdplayer/DVDStreamInfo.h
++++ b/xbmc/cores/dvdplayer/DVDStreamInfo.h
+@@ -58,8 +58,6 @@ public:
+ // VIDEO
+ int fpsscale; // scale of 1000 and a rate of 29970 will result in 29.97 fps
+ int fpsrate;
+- int rfpsscale;
+- int rfpsrate;
+ int height; // height of the stream reported by the demuxer
+ int width; // width of the stream reported by the demuxer
+ float aspect; // display aspect as reported by demuxer
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0013-Save-settings-only-if-they-were-modified-after-the-l.patch b/projects/WeTek.Play/patches/kodi/0013-Save-settings-only-if-they-were-modified-after-the-l.patch
new file mode 100644
index 0000000000..f582834d14
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0013-Save-settings-only-if-they-were-modified-after-the-l.patch
@@ -0,0 +1,46 @@
+From 12685fbccb83b93051d618a2a6192625da673296 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Sun, 19 Oct 2014 16:20:33 +0300
+Subject: [PATCH 13/16] Save settings only if they were modified after the
+ last save
+
+This prevents from multiple saving the same settings and helps to resolve
+the issue on Amlogic G18REF TV-boxes when setiings may be lost after a poweroff.
+
+On G18REF When you press the red button on the remote the system receives a signal that power
+is about to off. XBMC always writes guisettings.xml before exit, and the same settings
+may be written several times from different places in code. But the power gets turned off
+before the system completes all shutdown procedures. There may be the case that guisettings.xml
+is written half-way and couldn't be read upon next boot, so the XBMC creates a new one with
+default settings.
+
+With this fix the settings will be written at exit only once, minimizing the risk of being lost.
+---
+ xbmc/settings/Settings.cpp | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/xbmc/settings/Settings.cpp b/xbmc/settings/Settings.cpp
+index 3c981a4..0850bce 100644
+--- a/xbmc/settings/Settings.cpp
++++ b/xbmc/settings/Settings.cpp
+@@ -207,6 +207,17 @@ bool CSettings::Save(const std::string &file)
+ if (!m_settingsManager->Save(root))
+ return false;
+
++ // Avoid saving if the settings saved earlier are indetical to the current ones
++ if (CFile::Exists(file))
++ {
++ std::string fileMD5 = CUtil::GetFileMD5(file);
++ TiXmlPrinter xmlPrinter;
++ xmlDoc.Accept(&xmlPrinter);
++ std::string settingsMD5 = XBMC::XBMC_MD5::GetMD5(xmlPrinter.CStr());
++ if (fileMD5 == settingsMD5)
++ return true;
++ }
++
+ return xmlDoc.SaveFile(file);
+ }
+
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0014-aml-Fix-periodic-video-stuttering-during-playback-of.patch b/projects/WeTek.Play/patches/kodi/0014-aml-Fix-periodic-video-stuttering-during-playback-of.patch
new file mode 100644
index 0000000000..8539a92ae8
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0014-aml-Fix-periodic-video-stuttering-during-playback-of.patch
@@ -0,0 +1,45 @@
+From 3daad356fe95b304b8ba995dae476ec77664c989 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Fri, 10 Oct 2014 23:56:59 +0300
+Subject: [PATCH 14/16] [aml] Fix periodic video stuttering during playback of
+ some media files and streams
+
+---
+ xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp | 20 ++++++++------------
+ 1 file changed, 8 insertions(+), 12 deletions(-)
+
+diff --git a/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp b/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
+index e859eaa..007f3a6 100644
+--- a/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
++++ b/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
+@@ -1994,19 +1994,15 @@ void CAMLCodec::Process()
+
+ double error = app_pts - (double)pts_video/PTS_FREQ;
+ double abs_error = fabs(error);
+- if (abs_error > 0.125)
++ if (abs_error > 0.150)
+ {
+- //CLog::Log(LOGDEBUG, "CAMLCodec::Process pts diff = %f", error);
+- if (abs_error > 0.150)
+- {
+- // big error so try to reset pts_pcrscr
+- SetVideoPtsSeconds(app_pts);
+- }
+- else
+- {
+- // small error so try to avoid a frame jump
+- SetVideoPtsSeconds((double)pts_video/PTS_FREQ + error/4);
+- }
++ // big error so try to reset pts_pcrscr
++ SetVideoPtsSeconds(app_pts);
++ }
++ else
++ {
++ // small error so try to avoid a frame jump
++ SetVideoPtsSeconds((double)pts_video/PTS_FREQ + error/4);
+ }
+ }
+ }
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0015-aml-Remove-dependency-on-libamplayer-and-amffmpeg.patch b/projects/WeTek.Play/patches/kodi/0015-aml-Remove-dependency-on-libamplayer-and-amffmpeg.patch
new file mode 100644
index 0000000000..78e40d5139
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0015-aml-Remove-dependency-on-libamplayer-and-amffmpeg.patch
@@ -0,0 +1,179 @@
+From ea22621b073bf1c01aeeb3bb3c24468bf11e7e38 Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Thu, 6 Nov 2014 08:14:39 +0200
+Subject: [PATCH 15/16] [aml] Remove dependency on libamplayer and amffmpeg
+
+---
+ xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp | 79 +-------------------
+ .../DVDCodecs/Video/DVDVideoCodecAmlogic.cpp | 3 -
+ 2 files changed, 3 insertions(+), 79 deletions(-)
+
+diff --git a/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp b/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
+index 007f3a6..8422d7d 100644
+--- a/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
++++ b/xbmc/cores/dvdplayer/DVDCodecs/Video/AMLCodec.cpp
+@@ -50,9 +50,9 @@
+ #include
+ #include
+
+-// amcodec include
+ extern "C" {
+ #include
++#include
+ } // extern "C"
+
+ typedef struct {
+@@ -91,19 +91,11 @@ public:
+ virtual int codec_set_cntl_mode(codec_para_t *pcodec, unsigned int mode)=0;
+ virtual int codec_set_cntl_avthresh(codec_para_t *pcodec, unsigned int avthresh)=0;
+ virtual int codec_set_cntl_syncthresh(codec_para_t *pcodec, unsigned int syncthresh)=0;
+-
+- // grab these from libamplayer
+- virtual int h263vld(unsigned char *inbuf, unsigned char *outbuf, int inbuf_len, int s263)=0;
+- virtual int decodeble_h263(unsigned char *buf)=0;
+-
+- // grab this from amffmpeg so we do not have to load DllAvUtil
+- virtual AVRational av_d2q(double d, int max)=0;
+ };
+
+ class DllLibAmCodec : public DllDynamic, DllLibamCodecInterface
+ {
+- // libamcodec is static linked into libamplayer.so
+- DECLARE_DLL_WRAPPER(DllLibAmCodec, "libamplayer.so")
++ DECLARE_DLL_WRAPPER(DllLibAmCodec, "libamcodec.so")
+
+ DEFINE_METHOD1(int, codec_init, (codec_para_t *p1))
+ DEFINE_METHOD1(int, codec_close, (codec_para_t *p1))
+@@ -121,11 +113,6 @@ class DllLibAmCodec : public DllDynamic, DllLibamCodecInterface
+ DEFINE_METHOD2(int, codec_set_cntl_avthresh, (codec_para_t *p1, unsigned int p2))
+ DEFINE_METHOD2(int, codec_set_cntl_syncthresh,(codec_para_t *p1, unsigned int p2))
+
+- DEFINE_METHOD4(int, h263vld, (unsigned char *p1, unsigned char *p2, int p3, int p4))
+- DEFINE_METHOD1(int, decodeble_h263, (unsigned char *p1))
+-
+- DEFINE_METHOD2(AVRational, av_d2q, (double p1, int p2))
+-
+ BEGIN_METHOD_RESOLVE()
+ RESOLVE_METHOD(codec_init)
+ RESOLVE_METHOD(codec_close)
+@@ -142,11 +129,6 @@ class DllLibAmCodec : public DllDynamic, DllLibamCodecInterface
+ RESOLVE_METHOD(codec_set_cntl_mode)
+ RESOLVE_METHOD(codec_set_cntl_avthresh)
+ RESOLVE_METHOD(codec_set_cntl_syncthresh)
+-
+- RESOLVE_METHOD(h263vld)
+- RESOLVE_METHOD(decodeble_h263)
+-
+- RESOLVE_METHOD(av_d2q)
+ END_METHOD_RESOLVE()
+
+ public:
+@@ -345,8 +327,6 @@ typedef struct am_private_t
+ unsigned int video_ratio64;
+ unsigned int video_rate;
+ unsigned int video_rotation_degree;
+- int flv_flag;
+- int h263_decodable;
+ int extrasize;
+ uint8_t *extradata;
+ DllLibAmCodec *m_dll;
+@@ -439,7 +419,6 @@ static vformat_t codecid_to_vformat(enum AVCodecID id)
+ case AV_CODEC_ID_H263I:
+ case AV_CODEC_ID_MSMPEG4V2:
+ case AV_CODEC_ID_MSMPEG4V3:
+- case AV_CODEC_ID_FLV1:
+ format = VFORMAT_MPEG4;
+ break;
+ case AV_CODEC_ID_RV10:
+@@ -1221,51 +1200,6 @@ int set_header_info(am_private_t *para)
+ {
+ return divx3_prefix(pkt);
+ }
+- else if (para->video_codec_type == VIDEO_DEC_FORMAT_H263)
+- {
+- return PLAYER_UNSUPPORT;
+- unsigned char *vld_buf;
+- int vld_len, vld_buf_size = para->video_width * para->video_height * 2;
+-
+- if (!pkt->data_size) {
+- return PLAYER_SUCCESS;
+- }
+-
+- if ((pkt->data[0] == 0) && (pkt->data[1] == 0) && (pkt->data[2] == 1) && (pkt->data[3] == 0xb6)) {
+- return PLAYER_SUCCESS;
+- }
+-
+- vld_buf = (unsigned char*)malloc(vld_buf_size);
+- if (!vld_buf) {
+- return PLAYER_NOMEM;
+- }
+-
+- if (para->flv_flag) {
+- vld_len = para->m_dll->h263vld(pkt->data, vld_buf, pkt->data_size, 1);
+- } else {
+- if (0 == para->h263_decodable) {
+- para->h263_decodable = para->m_dll->decodeble_h263(pkt->data);
+- if (0 == para->h263_decodable) {
+- CLog::Log(LOGDEBUG, "[%s]h263 unsupport video and audio, exit", __FUNCTION__);
+- return PLAYER_UNSUPPORT;
+- }
+- }
+- vld_len = para->m_dll->h263vld(pkt->data, vld_buf, pkt->data_size, 0);
+- }
+-
+- if (vld_len > 0) {
+- if (pkt->buf) {
+- free(pkt->buf);
+- }
+- pkt->buf = vld_buf;
+- pkt->buf_size = vld_buf_size;
+- pkt->data = pkt->buf;
+- pkt->data_size = vld_len;
+- } else {
+- free(vld_buf);
+- pkt->data_size = 0;
+- }
+- }
+ } else if (para->video_format == VFORMAT_VC1) {
+ if (para->video_codec_type == VIDEO_DEC_FORMAT_WMV3) {
+ unsigned i, check_sum = 0, data_len = 0;
+@@ -1458,7 +1392,7 @@ bool CAMLCodec::OpenDecoder(CDVDStreamInfo &hints)
+ am_private->video_pid = hints.pid;
+
+ // handle video ratio
+- AVRational video_ratio = m_dll->av_d2q(1, SHRT_MAX);
++ AVRational video_ratio = av_d2q(1, SHRT_MAX);
+ //if (!hints.forced_aspect)
+ // video_ratio = m_dll->av_d2q(hints.aspect, SHRT_MAX);
+ am_private->video_ratio = ((int32_t)video_ratio.num << 16) | video_ratio.den;
+@@ -1529,13 +1463,6 @@ bool CAMLCodec::OpenDecoder(CDVDStreamInfo &hints)
+ else
+ am_private->video_codec_type = codec_tag_to_vdec_type(am_private->video_codec_id);
+
+- am_private->flv_flag = 0;
+- if (am_private->video_codec_id == AV_CODEC_ID_FLV1)
+- {
+- am_private->video_codec_tag = CODEC_TAG_F263;
+- am_private->flv_flag = 1;
+- }
+-
+ CLog::Log(LOGDEBUG, "CAMLCodec::OpenDecoder "
+ "hints.width(%d), hints.height(%d), hints.codec(%d), hints.codec_tag(%d), hints.pid(%d)",
+ hints.width, hints.height, hints.codec, hints.codec_tag, hints.pid);
+diff --git a/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp b/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp
+index 960aae1..57f8e40 100644
+--- a/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp
++++ b/xbmc/cores/dvdplayer/DVDCodecs/Video/DVDVideoCodecAmlogic.cpp
+@@ -108,9 +108,6 @@ bool CDVDVideoCodecAmlogic::Open(CDVDStreamInfo &hints, CDVDCodecOptions &option
+ // amcodec can't handle h263
+ return false;
+ break;
+- case AV_CODEC_ID_FLV1:
+- m_pFormatName = "am-flv1";
+- break;
+ case AV_CODEC_ID_RV10:
+ case AV_CODEC_ID_RV20:
+ case AV_CODEC_ID_RV30:
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/0016-aml-Add-some-key-mappings-for-HDMI-CEC.patch b/projects/WeTek.Play/patches/kodi/0016-aml-Add-some-key-mappings-for-HDMI-CEC.patch
new file mode 100644
index 0000000000..96af86eaef
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/0016-aml-Add-some-key-mappings-for-HDMI-CEC.patch
@@ -0,0 +1,28 @@
+From ff1b77d929a8ff79fff1b4b9da41ac473523a02c Mon Sep 17 00:00:00 2001
+From: Alex Deryskyba
+Date: Sun, 2 Nov 2014 15:54:29 +0200
+Subject: [PATCH 16/16] [aml] Add some key mappings for HDMI CEC
+
+---
+ xbmc/input/linux/LinuxInputDevices.cpp | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/xbmc/input/linux/LinuxInputDevices.cpp b/xbmc/input/linux/LinuxInputDevices.cpp
+index 0b0f7ae..c84930f 100644
+--- a/xbmc/input/linux/LinuxInputDevices.cpp
++++ b/xbmc/input/linux/LinuxInputDevices.cpp
+@@ -250,6 +250,11 @@ KeyMap keyMap[] = {
+ { KEY_PRINT , XBMCK_PRINT },
+ { KEY_QUESTION , XBMCK_HELP },
+ { KEY_BACK , XBMCK_BACKSPACE },
++ { KEY_SELECT , XBMCK_RETURN },
++ { KEY_RED , XBMCK_TAB },
++ { KEY_GREEN , XBMCK_z },
++ { KEY_YELLOW , XBMCK_i },
++ { KEY_BLUE , XBMCK_c },
+ // The Little Black Box Remote Additions
+ { 384 , XBMCK_LEFT }, // Red
+ { 378 , XBMCK_RIGHT }, // Green
+--
+1.7.9.5
+
diff --git a/projects/WeTek.Play/patches/kodi/add_mapping_for_browser_home_key_on_linux.patch b/projects/WeTek.Play/patches/kodi/add_mapping_for_browser_home_key_on_linux.patch
new file mode 100644
index 0000000000..117f98e6d2
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/add_mapping_for_browser_home_key_on_linux.patch
@@ -0,0 +1,12 @@
+diff --git a/xbmc/input/linux/LinuxInputDevices.cpp b/xbmc/input/linux/LinuxInputDevices.cpp
+index ee21474..5dcaf69 100644
+--- a/xbmc/input/linux/LinuxInputDevices.cpp
++++ b/xbmc/input/linux/LinuxInputDevices.cpp
+@@ -242,6 +242,7 @@ KeyMap keyMap[] = {
+ { KEY_RECORD , XBMCK_RECORD },
+ { KEY_REWIND , XBMCK_REWIND },
+ { KEY_PHONE , XBMCK_PHONE },
++ { KEY_HOMEPAGE , XBMCK_BROWSER_HOME},
+ { KEY_REFRESH , XBMCK_SHUFFLE },
+ { KEY_SCROLLUP , XBMCK_PAGEUP },
+ { KEY_SCROLLDOWN , XBMCK_PAGEDOWN },
diff --git a/projects/WeTek.Play/patches/kodi/enable_remoteaskeyboard_by_default.patch b/projects/WeTek.Play/patches/kodi/enable_remoteaskeyboard_by_default.patch
new file mode 100644
index 0000000000..5cba1cee8e
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/enable_remoteaskeyboard_by_default.patch
@@ -0,0 +1,13 @@
+diff --git a/system/settings/settings.xml b/system/settings/settings.xml
+index f92bd59..387bd3d 100644
+--- a/system/settings/settings.xml
++++ b/system/settings/settings.xml
+@@ -2605,7 +2605,7 @@
+
+
+ 1
+- false
++ true
+
+
+
diff --git a/projects/WeTek.Play/patches/kodi/fix_compiler_badness_when_compiling_with_amcodec.patch b/projects/WeTek.Play/patches/kodi/fix_compiler_badness_when_compiling_with_amcodec.patch
new file mode 100644
index 0000000000..cb2351b790
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/fix_compiler_badness_when_compiling_with_amcodec.patch
@@ -0,0 +1,13 @@
+diff --git a/xbmc/cores/dvdplayer/DVDCodecs/Video/Makefile.in b/xbmc/cores/dvdplayer/DVDCodecs/Video/Makefile.in
+index 8a97889..78506b1 100644
+--- a/xbmc/cores/dvdplayer/DVDCodecs/Video/Makefile.in
++++ b/xbmc/cores/dvdplayer/DVDCodecs/Video/Makefile.in
+@@ -27,8 +27,6 @@ endif
+ ifeq (@USE_LIBAMCODEC@,1)
+ SRCS += AMLCodec.cpp
+ SRCS += DVDVideoCodecAmlogic.cpp
+-INCLUDES += -I$(prefix)/include/amcodec
+-INCLUDES += -I$(prefix)/include/amplayer
+ endif
+
+ ifeq (@USE_ANDROID@,1)
diff --git a/projects/WeTek.Play/patches/kodi/make_esc_key_execute_back_action.patch b/projects/WeTek.Play/patches/kodi/make_esc_key_execute_back_action.patch
new file mode 100644
index 0000000000..c15454cebd
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/make_esc_key_execute_back_action.patch
@@ -0,0 +1,21 @@
+diff --git a/system/keymaps/keyboard.xml b/system/keymaps/keyboard.xml
+index 45682a2..74fbd13 100644
+--- a/system/keymaps/keyboard.xml
++++ b/system/keymaps/keyboard.xml
+@@ -57,7 +57,7 @@
+ Back
+ ActivateWindow(PlayerControls)
+ ActivateWindow(shutdownmenu)
+- PreviousMenu
++ Back
+ Info
+
+ ContextMenu
+@@ -167,6 +167,7 @@
+
+
+ Backspace
++ PreviousMenu
+
+
+
diff --git a/projects/WeTek.Play/patches/kodi/perform_suspend_instead_of_powerdown.patch b/projects/WeTek.Play/patches/kodi/perform_suspend_instead_of_powerdown.patch
new file mode 100644
index 0000000000..07a504fe3d
--- /dev/null
+++ b/projects/WeTek.Play/patches/kodi/perform_suspend_instead_of_powerdown.patch
@@ -0,0 +1,35 @@
+diff --git a/system/keymaps/keyboard.xml b/system/keymaps/keyboard.xml
+index 45682a2..b8ce91b 100644
+--- a/system/keymaps/keyboard.xml
++++ b/system/keymaps/keyboard.xml
+@@ -96,7 +96,7 @@
+ ToggleFullScreen
+ FirstPage
+ LastPage
+- ActivateWindow(shutdownmenu)
++ XBMC.Powerdown()
+ ActivateWindow(shutdownmenu)
+
+ XBMC.ActivateWindowAndFocus(MyPVR, 31,0, 10,0)
+diff --git a/xbmc/powermanagement/linux/LogindUPowerSyscall.cpp b/xbmc/powermanagement/linux/LogindUPowerSyscall.cpp
+index 5a97fe6..369e790 100644
+--- a/xbmc/powermanagement/linux/LogindUPowerSyscall.cpp
++++ b/xbmc/powermanagement/linux/LogindUPowerSyscall.cpp
+@@ -52,7 +52,7 @@ CLogindUPowerSyscall::CLogindUPowerSyscall()
+ m_canPowerdown = LogindCheckCapability("CanPowerOff");
+ m_canReboot = LogindCheckCapability("CanReboot");
+ m_canHibernate = LogindCheckCapability("CanHibernate");
+- m_canSuspend = LogindCheckCapability("CanSuspend");
++ m_canSuspend = false;
+
+ InhibitDelayLock();
+
+@@ -97,7 +97,7 @@ CLogindUPowerSyscall::~CLogindUPowerSyscall()
+
+ bool CLogindUPowerSyscall::Powerdown()
+ {
+- return LogindSetPowerState("PowerOff");
++ return Suspend();
+ }
+
+ bool CLogindUPowerSyscall::Reboot()
diff --git a/projects/WeTek.Play/patches/linux/aml_fe_set_property.patch b/projects/WeTek.Play/patches/linux/aml_fe_set_property.patch
new file mode 100644
index 0000000000..ce08484b2c
--- /dev/null
+++ b/projects/WeTek.Play/patches/linux/aml_fe_set_property.patch
@@ -0,0 +1,13 @@
+diff -Naur a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c
+--- a/drivers/media/dvb-core/dvb_frontend.c 2014-12-08 17:33:43.262657721 +0100
++++ b/drivers/media/dvb-core/dvb_frontend.c 2014-12-08 17:34:37.126207052 +0100
+@@ -2416,6 +2416,9 @@
+ if(cmd == FE_SET_PROPERTY) {
+ tvps = (struct dtv_properties __user *)parg;
+
++ if(fe->ops.set_mode)
++ fe->ops.set_mode(fe, FE_QPSK);
++
+ dev_dbg(fe->dvb->device, "%s: properties.num = %d\n", __func__, tvps->num);
+ dev_dbg(fe->dvb->device, "%s: properties.props = %p\n", __func__, tvps->props);
+
diff --git a/projects/WeTek.Play/patches/linux/dvbwetek.patch b/projects/WeTek.Play/patches/linux/dvbwetek.patch
new file mode 100644
index 0000000000..70d0a92096
--- /dev/null
+++ b/projects/WeTek.Play/patches/linux/dvbwetek.patch
@@ -0,0 +1,9798 @@
+diff -Naur a/drivers/amlogic/dvb_tv/aml_dvb.c b/drivers/amlogic/dvb_tv/aml_dvb.c
+--- a/drivers/amlogic/dvb_tv/aml_dvb.c 2014-12-11 15:40:00.073007604 +0100
++++ b/drivers/amlogic/dvb_tv/aml_dvb.c 2014-12-11 16:07:36.316473946 +0100
+@@ -79,6 +79,10 @@
+ static int aml_tsdemux_set_skipbyte(int skipbyte);
+ static int aml_tsdemux_set_demux(int id);
+
++static void aml_dvb_pinctrl_put (struct aml_dvb *advb);
++static struct pinctrl * __must_check aml_dvb_pinctrl_get_select (
++ struct aml_dvb *advb, const char *name);
++
+ static struct tsdemux_ops aml_tsdemux_ops = {
+ .reset = aml_tsdemux_reset,
+ .set_reset_flag = aml_tsdemux_set_reset_flag,
+@@ -154,8 +158,13 @@
+ dmx->dmx_irq = res->start;
+ }
+ #endif
++ if(id == 0)
++ dmx->source = AM_TS_SRC_TS2;
++ else if(id == 1)
++ dmx->source = AM_TS_SRC_TS0;
++ else
++ dmx->source = -1;
+
+- dmx->source = -1;
+ dmx->dump_ts_select = 0;
+ dmx->dvr_irq = -1;
+
+@@ -999,14 +1008,8 @@
+ }
+
+ if((mode != AM_TS_SERIAL) || (ts->s2p_id != -1)){
+- if(ts->pinctrl){
+- devm_pinctrl_put(ts->pinctrl);
+- ts->pinctrl = NULL;
+- }
+
+- ts->pinctrl = devm_pinctrl_get_select(&dvb->pdev->dev, pname);
+- if(IS_ERR_VALUE(ts->pinctrl))
+- ts->pinctrl = NULL;
++ ts->pinctrl = aml_dvb_pinctrl_get_select(dvb, pname);
+ ts->mode = mode;
+ ts->control = ctrl;
+
+@@ -1109,6 +1112,49 @@
+ extern int aml_regist_dmx_class(void);
+ extern int aml_unregist_dmx_class(void);
+
++static void aml_dvb_pinctrl_put (struct aml_dvb *advb)
++{
++ /*all dvb pinctrls share the ts[0]'s pinctrl.*/
++ if (advb->ts[0].pinctrl) {
++ devm_pinctrl_put(advb->ts[0].pinctrl);
++ advb->ts[0].pinctrl = NULL;
++ }
++}
++
++static struct pinctrl * __must_check aml_dvb_pinctrl_get_select (
++ struct aml_dvb *advb, const char *name)
++{
++ /*all dvb pinctrls share the ts[0]'s pinctrl.*/
++ struct pinctrl *p = advb->ts[0].pinctrl;
++
++ struct pinctrl_state *s;
++ int ret;
++
++ if (!p) {
++ p = devm_pinctrl_get(&advb->pdev->dev);
++ if (IS_ERR(p)) {
++ return p;
++ }
++ advb->ts[0].pinctrl = p;
++ }
++
++ s = pinctrl_lookup_state(p, name);
++ if (IS_ERR(s)) {
++ pr_error("pinctl:lookup %s fail\n", name);
++ devm_pinctrl_put(p);
++ return ERR_CAST(s);
++ }
++
++ ret = pinctrl_select_state(p, s);
++ if (ret < 0) {
++ pr_error("pinctl:select %s fail\n", name);
++ devm_pinctrl_put(p);
++ return ERR_PTR(ret);
++ }
++
++ return p;
++}
++
+ static int aml_dvb_probe(struct platform_device *pdev)
+ {
+ struct aml_dvb *advb;
+@@ -1158,7 +1204,7 @@
+ }else{
+ snprintf(buf, sizeof(buf), "s_ts%d", i);
+ advb->ts[i].mode = AM_TS_SERIAL;
+- advb->ts[i].pinctrl = devm_pinctrl_get_select(&pdev->dev, buf);
++ advb->ts[i].pinctrl = aml_dvb_pinctrl_get_select(advb, buf);
+ advb->ts[i].s2p_id = s2p_id;
+
+ s2p_id++;
+@@ -1167,7 +1213,7 @@
+ pr_dbg("%s: parallel\n", buf);
+ snprintf(buf, sizeof(buf), "p_ts%d", i);
+ advb->ts[i].mode = AM_TS_PARALLEL;
+- advb->ts[i].pinctrl = devm_pinctrl_get_select(&pdev->dev, buf);
++ advb->ts[i].pinctrl = aml_dvb_pinctrl_get_select(advb, buf);
+ }else{
+ advb->ts[i].mode = AM_TS_DISABLE;
+ advb->ts[i].pinctrl = NULL;
+@@ -1229,6 +1275,10 @@
+ if ((ret=aml_dvb_asyncfifo_init(advb, &advb->asyncfifo[i], i))<0) {
+ goto error;
+ }
++ if(i == 0)
++ aml_asyncfifo_hw_set_source(&advb->asyncfifo[i], AM_DMX_0);
++ else if(i == 1)
++ aml_asyncfifo_hw_set_source(&advb->asyncfifo[i], AM_DMX_1);
+ }
+
+ aml_regist_dmx_class();
+@@ -1279,10 +1329,7 @@
+ }
+ dvb_unregister_adapter(&advb->dvb_adapter);
+
+- for (i=0; its[i].pinctrl)
+- devm_pinctrl_put(advb->ts[i].pinctrl);
+- }
++ aml_dvb_pinctrl_put(advb);
+
+ switch_mod_gate_by_name("demux", 0);
+
+diff -Naur a/drivers/amlogic/dvb_tv/aml_dvb.h b/drivers/amlogic/dvb_tv/aml_dvb.h
+--- a/drivers/amlogic/dvb_tv/aml_dvb.h 2014-12-11 15:40:00.085007509 +0100
++++ b/drivers/amlogic/dvb_tv/aml_dvb.h 2014-12-11 15:54:32.910432233 +0100
+@@ -23,14 +23,14 @@
+ #endif
+
+
+-#include "drivers/media/dvb-core/dvbdev.h"
+-#include "drivers/media/dvb-core/demux.h"
+-#include "drivers/media/dvb-core/dvb_demux.h"
+-#include "drivers/media/dvb-core/dmxdev.h"
+-#include "drivers/media/dvb-core/dvb_filter.h"
+-#include "drivers/media/dvb-core/dvb_net.h"
+-#include "drivers/media/dvb-core/dvb_ringbuffer.h"
+-#include "drivers/media/dvb-core/dvb_frontend.h"
++#include "dvbdev.h"
++#include "demux.h"
++#include "dvb_demux.h"
++#include "dmxdev.h"
++#include "dvb_filter.h"
++#include "dvb_net.h"
++#include "dvb_ringbuffer.h"
++#include "dvb_frontend.h"
+
+ #include
+ #include
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.c b/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.c
+--- a/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.c 2014-12-11 16:13:49.957618635 +0100
+@@ -0,0 +1,473 @@
++/*****************************************************************************
++* Tuner sample code
++*
++* History:
++* Date Athor Version Reason
++* ============ ============= ========= =================
++* 1.Apr.29.2010 Version1.0
++*****************************************************************************/
++//#include "Board.h"
++//#include "MsCommon.h"
++//#include "HbCommon.h"
++//#if (FRONTEND_TUNER_TYPE == TUNER_AV2011 && FRONTEND_DEMOD_TYPE == DEMOD_AVL6211)
++#include "ExtAV2011.h"
++#include "IBSP.h"
++#include "IBase.h"
++#include "II2C.h"
++
++#define HB_printf printk
++#define AV2011_R0_PLL_LOCK 0x01
++#define AV2011_Tuner
++
++static AVL_uint16 tuner_crystal = 27; //unit is MHz
++static AVL_uchar auto_scan=0; //0 for normal mode, 1 for Blindscan mode
++static void Time_DELAY_MS(AVL_uint32 ms);
++ //Main function at tuner control
++static AVL_DVBSx_ErrorCode Tuner_control(AVL_uint32 channel_freq,AVL_uint32 bb_sym,struct AVL_Tuner * pTuner);
++// I2C write function ( start register, register array pointer, register length)
++static AVL_DVBSx_ErrorCode AV2011_I2C_write(AVL_uchar reg_start,AVL_uchar* buff,AVL_uchar len,struct AVL_Tuner * pTuner);
++static AVL_DVBSx_ErrorCode AV2011_I2C_Check(struct AVL_Tuner * pTuner);
++AVL_uint16 AVL_DVBSx_AV2011_CalculateLPF(AVL_uint16 uiSymbolRate_10kHz);
++AVL_DVBSx_ErrorCode ExtAV2011_RegInit(struct AVL_Tuner * pTuner);
++static AVL_DVBSx_ErrorCode AV2011_I2C_Read(AVL_uchar regAddr,AVL_uchar* buff,struct AVL_Tuner * pTuner);
++
++
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_ExtAV2011_GetLockStatus(struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar uilock;
++
++ //Send register address
++ r = AVL_DVBSx_II2CRepeater_GetOPStatus(pTuner->m_pAVLChip);
++ if( AVL_DVBSx_EC_OK != r )
++ {
++ return(r);
++ }
++ AVL_DVBSx_IBSP_Delay(1);
++ r = AVL_DVBSx_II2CRepeater_ReadData_Multi( pTuner->m_uiSlaveAddress, &uilock, 0x0B, 1, pTuner->m_pAVLChip );
++ printf("uilock is %x\n",uilock);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ if( 0 == (uilock & AV2011_R0_PLL_LOCK) )
++ {
++ r = AVL_DVBSx_EC_Running;
++ }
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_ExtAV2011_Initialize(struct AVL_Tuner * pTuner) {
++ printf("Javy --- AVL_DVBSx_ExtAV2011_Initialize!!!\n");
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_slave_addr_addr, pTuner->m_uiSlaveAddress);
++ r |= AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_use_internal_control_addr, 0);
++ r |= AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_LPF_margin_100kHz_addr, 0); //clean up the LPF margin for blind scan. for external driver, this must be zero.
++ r |= AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_max_LPF_100kHz_addr, 360); //set up the right LPF for blind scan to regulate the freq_step. This field should corresponding the flat response part of the LPF.
++ r |= AVL_DVBSx_II2CRepeater_Initialize(pTuner->m_uiI2CBusClock_kHz, pTuner->m_pAVLChip);
++
++ AVL_puint16 rsj;
++ AVL_DVBSx_II2C_Read16( pTuner->m_pAVLChip, rc_tuner_slave_addr_addr, &rsj);
++ printf("rsj is (rc_tuner_slave_addr_addr)%x\n",rsj);
++
++ r |= AV2011_I2C_Check(pTuner);
++ r |= ExtAV2011_RegInit(pTuner);
++ return(r);
++}
++
++/********************************************************************************
++* INT32 Tuner_control(AVL_uint32 channel_freq, AVL_uint32 bb_sym)
++*
++* Arguments:
++* Parameter1: AVL_uint32 channel_freq : Channel freqency
++* Parameter2: AVL_uint32 bb_sym : Baseband Symbol Rate
++*
++* Return Value: INT32 : Result
++*****************************************************************************/
++AVL_DVBSx_ErrorCode ExtAV2011_RegInit(struct AVL_Tuner * pTuner)
++{
++ AVL_uchar reg[50];
++ AVL_uchar reg_start;
++ AVL_DVBSx_ErrorCode r;
++ // Register initial flag
++ //when sym is 0 or 45000, means auto-scan channel.
++ // At Power ON, tuner_initial = 0
++ // do the initial if not do yet.
++ //Tuner Initail registers R0~R41
++ reg[0]=(char) (0x38);
++ reg[1]=(char) (0x00);
++ reg[2]=(char) (0x00);
++ reg[3]=(char) (0x50);
++ reg[4]=(char) (0x1f);
++ reg[5]=(char) (0xa3);
++ reg[6]=(char) (0xfd);
++ reg[7]=(char) (0x58);
++ reg[8]=(char) (0x0e);
++ reg[9]=(char) (0xc2);//0x82 change into 0xc2- Fixed crystal issue
++ reg[10]=(char) (0x88);
++ reg[11]=(char) (0xb4);
++ reg[12]=(char) (0xd6); //RFLP=ON at Power on initial
++ reg[13]=(char) (0x40);
++#ifdef AV2011_Tuner
++ reg[14]=(char) (0x94);
++ reg[15]=(char) (0x9a);
++#else
++ reg[14]=(char) (0x5b);
++ reg[15]=(char) (0x6a);
++#endif
++ reg[16]=(char) (0x66);
++ reg[17]=(char) (0x40);
++ reg[18]=(char) (0x80);
++ reg[19]=(char) (0x2b);
++ reg[20]=(char) (0x6a);
++ reg[21]=(char) (0x50);
++ reg[22]=(char) (0x91);
++ reg[23]=(char) (0x27);
++ reg[24]=(char) (0x8f);
++ reg[25]=(char) (0xcc);
++ reg[26]=(char) (0x21);
++ reg[27]=(char) (0x10);
++ reg[28]=(char) (0x80);
++ reg[29]=(char) (0x02);
++ reg[30]=(char) (0xf5);
++ reg[31]=(char) (0x7f);
++ reg[32]=(char) (0x4a);
++ reg[33]=(char) (0x9b);
++ reg[34]=(char) (0xe0);
++ reg[35]=(char) (0xe0);
++ reg[36]=(char) (0x36);
++ //monsen 20080710. Disble FT-function at Power on initial
++ //reg[37]=(char) (0x02);
++ reg[37]=(char) (0x00);
++ reg[38]=(char) (0xab);
++ reg[39]=(char) (0x97);
++ reg[40]=(char) (0xc5);
++ reg[41]=(char) (0xa8);
++ //monsen 20080709. power on initial at first "Tuner_control()" call
++ // Sequence 1
++ // Send Reg0 ->Reg11
++ reg_start = 0;
++ r = AV2011_I2C_write(reg_start,reg,12,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Time delay 1ms
++ Time_DELAY_MS(1);
++ // Sequence 2
++ // Send Reg13 ->Reg24
++ reg_start = 13;
++ r = AV2011_I2C_write(reg_start,reg+13,12,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Send Reg25 ->Reg35
++ reg_start = 25;
++ r = AV2011_I2C_write(reg_start,reg+25,11,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Send Reg36 ->Reg41
++ reg_start = 36;
++ r = AV2011_I2C_write(reg_start, reg+36, 6, pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Time delay 1ms
++ Time_DELAY_MS(1);
++ // Sequence 3
++ // send reg12
++ reg_start = 12;
++ r = AV2011_I2C_write(reg_start,reg+12,1,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++
++
++#if 0
++//rsj for test
++ AVL_uchar buff;
++ AV2011_I2C_Read(reg_start,&buff,pTuner);
++ printf("reg_start is %x,buff is %x \n",reg_start,buff);
++//rsj
++#endif
++
++ //monsen 20081125, Wait 100 ms
++ Time_DELAY_MS(10);
++ //monsen 20081030, Reinitial again
++ {
++ // Sequence 1
++ // Send Reg0 ->Reg11
++ reg_start = 0;
++ r = AV2011_I2C_write(reg_start,reg,12,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Time delay 1ms
++ Time_DELAY_MS(1);
++ // Sequence 2
++ // Send Reg13 ->Reg24
++ reg_start = 13;
++ r = AV2011_I2C_write(reg_start,reg+13,12,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Send Reg25 ->Reg35
++ reg_start = 25;
++ r = AV2011_I2C_write(reg_start,reg+25,11,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Send Reg36 ->Reg41
++ reg_start = 36;
++ r = AV2011_I2C_write(reg_start,reg+36,6,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ // Time delay 1ms
++ Time_DELAY_MS(1);
++ // Sequence 3
++ // send reg12
++ reg_start = 12;
++ r = AV2011_I2C_write(reg_start,reg+12,1,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ Time_DELAY_MS(5);
++ return(r);
++ }
++}
++
++
++//Wake_Up = 0 Power_Down = 1
++void Tuner_Set_PD (AVL_uint32 val, struct AVL_Tuner * pTuner)
++{
++ AVL_uchar reg12 = 0 ;
++
++ reg12 = (0xd6 & 0xDF) | (val << 5);
++
++ printf("Javy Set Reg12 : 0x%x\n",reg12);
++
++ AV2011_I2C_write(12, ®12,1,pTuner);
++ /* Time delay ms*/
++ Time_DELAY_MS(5);
++}
++
++
++AVL_DVBSx_ErrorCode Tuner_control(AVL_uint32 channel_freq, AVL_uint32 bb_sym, struct AVL_Tuner * pTuner)
++{
++ AVL_uchar reg[50];
++ AVL_uint32 fracN;
++ AVL_uint32 BW;
++ AVL_uint32 BF;
++ AVL_DVBSx_ErrorCode r;
++ //AVL_uchar auto_scan = 0;// Add flag for "’ß̨"
++ // Register initial flag;
++ auto_scan = 0;
++ //when sym is 0 or 45000, means auto-scan channel.
++ if (bb_sym == 0 || bb_sym == 45000) //auto-scan mode
++ {
++ auto_scan = 1;
++ }
++ Time_DELAY_MS(50);
++ fracN = (channel_freq + tuner_crystal/2)/tuner_crystal;
++ if(fracN > 0xff)
++ fracN = 0xff;
++ reg[0]=(char) (fracN & 0xff);
++ fracN = (channel_freq<<17)/tuner_crystal;
++ fracN = fracN & 0x1ffff;
++ reg[1]=(char) ((fracN>>9)&0xff);
++ reg[2]=(char) ((fracN>>1)&0xff);
++ // reg[3]_D7 is frac<0>, D6~D0 is 0x50
++ reg[3]=(char) (((fracN<<7)&0x80) | 0x50); // default is 0x50
++ // Channel Filter Bandwidth Setting.
++ //"sym" unit is Hz;
++ if(auto_scan)//’ß̨ requested by BB
++ {
++ reg[5] = 0xA3; //BW=27MHz
++ }
++ else
++ {
++ // rolloff is 35%
++ BW = bb_sym*135/200;
++ // monsen 20080726, BB request low IF when sym < 6.5MHz
++ // add 6M when Rs<6.5M,
++ if(bb_sym<6500)
++ {
++ BW = BW + 6000;
++ }
++ // add 2M for LNB frequency shifting
++ BW = BW + 2000;
++ // add 8% margin since fc is not very accurate
++ BW = BW*108/100;
++ // Bandwidth can be tuned from 4M to 40M
++ if( BW< 4000)
++ {
++ BW = 4000;
++ }
++ if( BW> 40000)
++ {
++ BW = 40000;
++ }
++ BF = (BW*127 + 21100/2) / (21100); // BW(MHz) * 1.27 / 211KHz
++ reg[5] = (AVL_uchar)BF;//145
++ printk("BF is %d,BW is %d\n",BF,BW);
++ }
++ // Sequence 4
++ // Send Reg0 ->Reg4
++ Time_DELAY_MS(5);
++ r = AV2011_I2C_write(0,reg,4,pTuner);
++ if(r!=AVL_DVBSx_EC_OK)
++ {
++ return(r);
++ }
++ Time_DELAY_MS(5);
++ // Sequence 5
++ // Send Reg5
++ r = AV2011_I2C_write(5, reg+5, 1,pTuner);
++ if(r!=AVL_DVBSx_EC_OK)
++ {
++ return(r);
++ }
++ Time_DELAY_MS(5);
++ // Fine-tune Function Control
++ //Tuner fine-tune gain function block. bit2.
++ //not auto-scan case. enable block function. FT_block=1, FT_EN=1
++ if (!auto_scan)
++ {
++ reg[37] = 0x06;
++ r = AV2011_I2C_write(37, reg+37, 1,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ }
++ Time_DELAY_MS(5);
++ //Disable RFLP at Lock Channel sequence after reg[37]
++ //RFLP=OFF at Lock Channel sequence
++ // RFLP can be Turned OFF, only at Receving mode.
++ reg[12] = 0x96 + ((1)<<6); //Loop through MTC_ADD_FIX
++ //reg[12] = 0x96;
++ r = AV2011_I2C_write(12, reg+12, 1,pTuner);
++ if(r!=AVL_DVBSx_EC_OK){
++ return(r);
++ Time_DELAY_MS(5);
++ }
++ }
++ return r;
++}
++static void Time_DELAY_MS(AVL_uint32 ms)
++{
++ AVL_DVBSx_IBSP_Delay(ms);
++}
++
++AVL_uint16 AVL_DVBSx_AV2011_CalculateLPF(AVL_uint16 uiSymbolRate_10kHz) {
++ AVL_int32 lpf = uiSymbolRate_10kHz;
++ //lpf *= 81;
++ //lpf /= 100;
++ //lpf += 500;
++ return((AVL_uint16)lpf);
++}
++
++static AVL_DVBSx_ErrorCode AV2011_I2C_write(AVL_uchar reg_start,AVL_uchar* buff,AVL_uchar len,struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r=0;
++ AVL_uchar ucTemp[50];
++ int i,uiTimeOut=0;
++ AVL_DVBSx_IBSP_Delay(5);
++
++ //for(i = 0; i < len; i ++)
++ {
++ ucTemp[0] = reg_start;
++ r = AVL_DVBSx_II2CRepeater_GetOPStatus( pTuner->m_pAVLChip);
++ // printk("%s r is %d\n",__FUNCTION__,r);
++ while( r != AVL_DVBSx_EC_OK)
++ {
++ if( uiTimeOut++>100)
++ {
++ break;
++ }
++ AVL_DVBSx_IBSP_Delay(1);
++ r = AVL_DVBSx_II2CRepeater_GetOPStatus( pTuner->m_pAVLChip);
++ }
++
++
++ for(i = 1; i < len+1; i ++)
++ {
++ ucTemp[i] = *(buff+i-1);
++ }
++
++ r = AVL_DVBSx_II2CRepeater_SendData(pTuner->m_uiSlaveAddress,ucTemp, len+1, pTuner->m_pAVLChip );
++ if(r != AVL_DVBSx_EC_OK)
++ {
++ return(r);
++ }
++ }
++ AVL_DVBSx_IBSP_Delay(1);
++ return(r);
++}
++
++static AVL_DVBSx_ErrorCode AV2011_I2C_Read(AVL_uchar regAddr,AVL_uchar* buff,struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r=0;
++ int uiTimeOut=0;
++
++ r = AVL_DVBSx_II2CRepeater_GetOPStatus( pTuner->m_pAVLChip );
++ while( r != AVL_DVBSx_EC_OK)
++ {
++ if( uiTimeOut++>200)
++ {
++ break;
++ }
++ AVL_DVBSx_IBSP_Delay(1);
++ r = AVL_DVBSx_II2CRepeater_GetOPStatus( pTuner->m_pAVLChip );
++ }
++ r = AVL_DVBSx_II2CRepeater_ReadData_Multi(pTuner->m_uiSlaveAddress, buff, regAddr/*0x00*/, 1, pTuner->m_pAVLChip);
++ if(r != AVL_DVBSx_EC_OK)
++ {
++ return(r);
++ }
++ return(r);
++}
++
++static AVL_DVBSx_ErrorCode AV2011_I2C_Check(struct AVL_Tuner * pTuner)
++{
++ AVL_uchar regValue,AV2011_address;
++
++ AV2011_address = 0xC0;
++ do
++ {
++ pTuner->m_uiSlaveAddress = AV2011_address;
++ AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_slave_addr_addr, pTuner->m_uiSlaveAddress);
++ regValue=(char) (0x38);
++ if(AV2011_I2C_write(0,®Value,1,pTuner) == AVL_DVBSx_EC_OK)
++ {
++ regValue = 0;
++ if(AV2011_I2C_Read(0,®Value,pTuner) == AVL_DVBSx_EC_OK)
++ {
++ printf("regValue is %x\n",regValue);
++ if(regValue == 0x38)
++ {
++ break;
++ }
++ }
++ }
++ AV2011_address += 0x02;
++ }while(AV2011_address <= 0xC6);
++ if(AV2011_address > 0xC6)
++ {
++ HB_printf("\n Not find tuner slave address");
++ AV2011_address = tuner_slave_address;
++ }
++ pTuner->m_uiSlaveAddress = AV2011_address;
++// pTuner->m_uiSlaveAddress = 0xC0;
++ HB_printf("\n Tuner slave address = 0x%X\n",pTuner->m_uiSlaveAddress);
++ return AVL_DVBSx_EC_OK;
++}
++AVL_DVBSx_ErrorCode AVL_DVBSx_ExtAV2011_Lock(struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r;
++ printf("pTuner->m_uiFrequency_100kHz is %d,pTuner->m_uiLPF_100kHz is %d\n",pTuner->m_uiFrequency_100kHz,pTuner->m_uiLPF_100kHz);
++ r = Tuner_control((AVL_uint32)((pTuner->m_uiFrequency_100kHz)/10), (AVL_uint32)((pTuner->m_uiLPF_100kHz)*100), pTuner);
++ return(r);
++}
++//#endif
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.h b/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.h
+--- a/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/AV2011/ExtAV2011.h 2014-12-11 16:13:49.953618665 +0100
+@@ -0,0 +1,24 @@
++#ifndef AV2011_h_h
++#define AV2011_h_h
++//#include "Board.h"
++#include "avl_dvbsx.h"
++#include "II2CRepeater.h"
++#include "ITuner.h"
++
++#ifdef AVL_CPLUSPLUS
++extern "C" {
++#endif
++
++#define tuner_slave_address 0xC0
++#define tuner_I2Cbus_clock 200 //The clock speed of the tuner dedicated I2C bus, in a unit of kHz.
++#define tuner_LPF 340 //The LPF of the tuner,in a unit of 100kHz.
++
++// time delay function ( minisecond )
++AVL_DVBSx_ErrorCode AVL_DVBSx_ExtAV2011_Initialize(struct AVL_Tuner * pTuner);
++AVL_DVBSx_ErrorCode AVL_DVBSx_ExtAV2011_GetLockStatus(struct AVL_Tuner * pTuner);
++AVL_DVBSx_ErrorCode AVL_DVBSx_ExtAV2011_Lock( struct AVL_Tuner * pTuner);
++
++#ifdef AVL_CPLUSPLUS
++}
++#endif
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/avlfrontend.c b/drivers/amlogic/dvb_tv/avl6211/avlfrontend.c
+--- a/drivers/amlogic/dvb_tv/avl6211/avlfrontend.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/avlfrontend.c 2014-12-11 16:13:50.009618235 +0100
+@@ -0,0 +1,931 @@
++/*****************************************************************
++**
++** Copyright (C) 2009 Amlogic,Inc.
++** All rights reserved
++** Filename : avlfrontend.c
++**
++** comment:
++** Driver for AVL6211 demodulator
++** author :
++** Shijie.Rong@amlogic
++** version :
++** v1.0 12/3/30
++*****************************************************************/
++
++/*
++ Driver for AVL6211 demodulator
++*/
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#ifdef ARC_700
++#include
++#else
++#include
++#endif
++#include
++#include
++#include "avlfrontend.h"
++#include "LockSignal_Api.h"
++#include
++#include
++#include
++
++#include
++
++#include "../aml_fe.h"
++
++#if 1
++#define pr_dbg printk
++//#define pr_dbg(fmt, args...) printk( KERN_DEBUG"DVB: " fmt, ## args)
++#else
++#define pr_dbg(fmt, args...)
++#endif
++
++#define pr_error(fmt, args...) printk( KERN_ERR"DVB: " fmt, ## args)
++
++#define M_TUNERMAXLPF_100KHZ 440
++#define bs_start_freq 950 //The start RF frequency, 950MHz
++#define bs_stop_freq 2150 //The stop RF frequency, 2150MHz
++#define Blindscan_Mode AVL_DVBSx_BS_Slow_Mode //The Blind scan mode. AVL_DVBSx_BS_Fast_Mode = 0,AVL_DVBSx_BS_Slow_Mode = 1
++
++extern struct AVL_Tuner *avl6211pTuner[FE_DEV_COUNT];
++extern struct AVL_DVBSx_Chip * pAVLChip_all[FE_DEV_COUNT];
++AVL_semaphore blindscanSem[FE_DEV_COUNT];
++static int blindstart[FE_DEV_COUNT] = { 0, 0};
++struct dvb_frontend *fe_use[FE_DEV_COUNT] = { NULL, NULL };
++struct aml_fe_dev *cur_dvbdev[FE_DEV_COUNT] = { NULL, NULL };
++static int reset_demods = 0;
++
++
++static char *device_name = "avl6211";
++
++struct aml_fe_dev * avl6211_get_cur_dev(int id)
++{
++ return cur_dvbdev[id];
++}
++
++static int AVL6211_Reset(int reset_gpio)
++{
++ amlogic_gpio_request(reset_gpio,device_name);
++
++ amlogic_gpio_direction_output(reset_gpio, 0, device_name);
++ msleep(300);
++ amlogic_gpio_direction_output(reset_gpio, 1, device_name);
++ return 0;
++}
++
++static int AVL6211_Lnb_Power_Ctrl(int id, int lnb)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ if(1 == lnb) {
++ r=AVL_DVBSx_IDiseqc_SetLNB1Out(1, pAVLChip_all[id]); //set LNB1_PIN60 1: Hight
++/* if(id == 0) {
++ amlogic_gpio_request(PAD_GPIOAO_8 , device_name);
++ amlogic_gpio_direction_output(PAD_GPIOAO_8, 1, device_name);
++ }else if(id == 1) {
++ amlogic_gpio_request(PAD_GPIOAO_9, device_name);
++ amlogic_gpio_direction_output(PAD_GPIOAO_9, 1, device_name);
++
++ }*/
++ }
++ else {
++ r=AVL_DVBSx_IDiseqc_SetLNB1Out(0, pAVLChip_all[id]); //set LNB1_PIN60 1: Low
++ /* if(id == 0) {
++ amlogic_gpio_request(PAD_GPIOAO_8 , device_name);
++ amlogic_gpio_direction_output(PAD_GPIOAO_8, 0, device_name);
++ }else if(id == 1) {
++ amlogic_gpio_request(PAD_GPIOAO_9, device_name);
++ amlogic_gpio_direction_output(PAD_GPIOAO_9, 0, device_name);
++
++ }*/
++
++ }
++
++ return r;
++}
++
++static int AVL6211_Tuner_Power_Ctrl(int id, int tunerpwr)
++{
++ if(1==tunerpwr) AVL_DVBSx_IBase_SetGPIOVal(0, pAVLChip_all[id]);
++ else AVL_DVBSx_IBase_SetGPIOVal(0, pAVLChip_all[id]);
++ return 0;
++}
++
++static int AVL6211_Ant_Overload_Ctrl(void)
++{
++ return 0;//gpio_get_value(frontend_ANT);
++}
++
++static int AVL6211_Diseqc_Reset_Overload(struct dvb_frontend* fe)
++{
++ return 0;
++}
++
++static int AVL6211_Diseqc_Send_Master_Cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uchar ucData[8];
++ int j=100;
++ struct AVL_DVBSx_Diseqc_TxStatus TxStatus;
++ int i;
++ pr_dbg("msg_len is %d,\n data is",cmd->msg_len);
++ for(i=0;imsg_len;i++){
++ ucData[i]=cmd->msg[i];
++ printk("%x ",cmd->msg[i]);
++ }
++
++ r=AVL_DVBSx_IDiseqc_SendModulationData(ucData, cmd->msg_len, pAVLChip_all[id]);
++ if(r != AVL_DVBSx_EC_OK)
++ {
++ pr_dbg("AVL_DVBSx_IDiseqc_SendModulationData failed !\n");
++ }
++ else
++ {
++ do
++ {
++ j--;
++ AVL_DVBSx_IBSP_Delay(1);
++ r= AVL_DVBSx_IDiseqc_GetTxStatus(&TxStatus, pAVLChip_all[id]);
++ }while((TxStatus.m_TxDone != 1)&&j);
++ if(r ==AVL_DVBSx_EC_OK )
++ {
++
++ }
++ else
++ {
++ pr_dbg("AVL_DVBSx_IDiseqc_SendModulationData Err. !\n");
++ }
++ }
++ return r;
++}
++
++static int AVL6211_Diseqc_Recv_Slave_Reply(struct dvb_frontend* fe, struct dvb_diseqc_slave_reply* reply)
++{
++ return 0;
++}
++
++static int AVL6211_Diseqc_Send_Burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_Diseqc_TxStatus sTxStatus;
++ AVL_uchar ucTone = 0;
++ int i=100;
++ #define TONE_COUNT 8
++ if(minicmd == SEC_MINI_A)
++ ucTone = 1;
++ else if(minicmd == SEC_MINI_B)
++ ucTone = 0;
++ else ;
++
++ r = AVL_DVBSx_IDiseqc_SendTone(ucTone, TONE_COUNT, pAVLChip_all[id]);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ pr_dbg("\rSend tone %d --- Fail!\n",ucTone);
++ }
++ else
++ {
++ do
++ {
++ i--;
++ AVL_DVBSx_IBSP_Delay(1);
++ r =AVL_DVBSx_IDiseqc_GetTxStatus(&sTxStatus, pAVLChip_all[id]); //Get current status of the Diseqc transmitter data FIFO.
++ }
++ while((1 != sTxStatus.m_TxDone)&&i); //Wait until operation finished.
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ pr_dbg("\rOutput tone %d --- Fail!\n",ucTone);
++ }
++ }
++ return (r);
++
++}
++
++static int AVL6211_Set_Tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uchar uc22kOn = 0;
++ if(SEC_TONE_ON == tone)
++ uc22kOn = 1;
++ else if(SEC_TONE_OFF == tone)
++ uc22kOn = 0;
++ else ;
++ if(uc22kOn)
++ {
++ r=AVL_DVBSx_IDiseqc_StartContinuous(pAVLChip_all[id]);
++ }else{
++ r=AVL_DVBSx_IDiseqc_StopContinuous(pAVLChip_all[id]);
++ }
++ if(r!=AVL_DVBSx_EC_OK)
++ {
++ pr_dbg("[AVL6211_22K_Control] Err:0x%x\n",r);
++ }
++
++ return r;
++
++}
++
++static int AVL6211_Set_Voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ AVL_DVBSx_ErrorCode r=AVL_DVBSx_EC_OK;
++ AVL_uchar nValue = 1;
++ if(voltage == SEC_VOLTAGE_OFF){
++ AVL6211_Lnb_Power_Ctrl(id, 0);//lnb power off
++ return 0;
++ }
++
++ if(voltage == SEC_VOLTAGE_13)
++ nValue = 0;
++ else if(voltage ==SEC_VOLTAGE_18)
++ nValue = 1;
++ else;
++
++ AVL6211_Lnb_Power_Ctrl(id, 1);//lnb power on
++
++ if(1==nValue)
++ r=AVL_DVBSx_IDiseqc_SetLNBOut(1, pAVLChip_all[id]); //set LNB0_PIN59 1: Hight
++ else
++ r=AVL_DVBSx_IDiseqc_SetLNBOut(0, pAVLChip_all[id]); //set LNB0_PIN59 1: Low
++
++ return r;
++}
++
++static int AVL6211_Enable_High_Lnb_Voltage(struct dvb_frontend* fe, long arg)
++{
++ return 0;
++}
++
++static void AVL6211_DumpSetting(struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting)
++{
++ printk(KERN_INFO "AVL6211_DumpSetting+++\n");
++
++ printk(KERN_INFO "m_uiScan_Min_Symbolrate_MHz %d\n", pBSsetting->m_uiScan_Min_Symbolrate_MHz);
++ printk(KERN_INFO "m_uiScan_Max_Symbolrate_MHz %d\n", pBSsetting->m_uiScan_Max_Symbolrate_MHz);
++ printk(KERN_INFO "m_uiScan_Start_Freq_MHz %d\n", pBSsetting->m_uiScan_Start_Freq_MHz);
++ printk(KERN_INFO "m_uiScan_Stop_Freq_MHz %d\n", pBSsetting->m_uiScan_Stop_Freq_MHz);
++ printk(KERN_INFO "m_uiScan_Next_Freq_100KHz %d\n", pBSsetting->m_uiScan_Next_Freq_100KHz);
++ printk(KERN_INFO "m_uiScan_Progress_Per %d\n", pBSsetting->m_uiScan_Progress_Per);
++ printk(KERN_INFO "m_uiScan_Bind_No %d\n", pBSsetting->m_uiScan_Bind_No);
++ printk(KERN_INFO "m_uiTuner_MaxLPF_100kHz %d\n", pBSsetting->m_uiTuner_MaxLPF_100kHz);
++ printk(KERN_INFO "m_uiScan_Center_Freq_Step_100KHz %d\n", pBSsetting->m_uiScan_Center_Freq_Step_100KHz);
++ printk(KERN_INFO "BS_Mode %d\n", pBSsetting->BS_Mode);
++ printk(KERN_INFO "m_uiScaning %d\n", pBSsetting->m_uiScaning);
++ printk(KERN_INFO "m_uiChannelCount %d\n", pBSsetting->m_uiChannelCount);
++ printk(KERN_INFO "m_eSpectrumMode %d\n", pBSsetting->m_eSpectrumMode);
++
++ printk(KERN_INFO "AVL6211_DumpSetting---\n");
++
++ return;
++}
++
++#if 0
++static int dvbs2_blindscan_task(struct dvbsx_blindscanpara *pbspara)//(struct dvb_frontend* fe, struct dvbsx_blindscanpara *pbspara)
++
++{
++ struct dvbsx_blindscanevent bsevent;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 index = 0;
++ struct AVL_DVBSx_Channel * pChannel;
++ // AVL_uchar HandIndex = 0;
++
++ //struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ //struct AVL_Tuner * pTuner = &g_stTuner[HandIndex];
++ struct AVL_DVBSx_BlindScanAPI_Setting BSsetting;
++ enum AVL_DVBSx_BlindScanAPI_Status BS_Status;
++ struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting = &BSsetting;
++ BS_Status = AVL_DVBSx_BS_Status_Init;
++
++ //This function do all the initialization work.It should be called only once at the beginning.It needn't be recalled when we want to lock a new channel.
++ /* r = Initialize(pAVLChip,pTuner);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Initialization failed !\n");
++ return (r);
++ }
++ printf("Initialization success !\n");*/
++
++ memset(pBSsetting, 0, sizeof(struct AVL_DVBSx_BlindScanAPI_Setting));
++
++ pBSsetting->m_uiScan_Start_Freq_MHz=pbspara->minfrequency/1000;
++ pBSsetting->m_uiScan_Stop_Freq_MHz=pbspara->maxfrequency/1000;
++ pBSsetting->m_uiScan_Max_Symbolrate_MHz=pbspara->maxSymbolRate/(1000 * 1000);
++ pBSsetting->m_uiScan_Min_Symbolrate_MHz=pbspara->minSymbolRate/(1000 * 1000);
++
++ while(BS_Status != AVL_DVBSx_BS_Status_Exit)
++ {
++ if(!blindstart){
++ BS_Status = AVL_DVBSx_BS_Status_Cancel;
++ printf("AVL_DVBSx_BS_Status_Cancel\n");
++ }
++ printk(KERN_INFO "BS_Status %d blindstart %d\n", BS_Status, blindstart);
++ switch(BS_Status)
++ {
++ case AVL_DVBSx_BS_Status_Init: {
++ printk(KERN_INFO "AVL_DVBSx_BS_Status_Init\n");
++ AVL_DVBSx_IBlindScanAPI_Initialize(pBSsetting);//this function set the parameters blind scan process needed.
++
++ AVL_DVBSx_IBlindScanAPI_SetFreqRange(pBSsetting, bs_start_freq, bs_stop_freq); //Default scan rang is from 950 to 2150. User may call this function to change scan frequency rang.
++ AVL_DVBSx_IBlindScanAPI_SetScanMode(pBSsetting, Blindscan_Mode);
++
++ AVL_DVBSx_IBlindScanAPI_SetSpectrumMode(pBSsetting, AVL_DVBSx_Spectrum_Invert); //Default set is AVL_DVBSx_Spectrum_Normal, it must be set correctly according Board HW configuration
++ AVL_DVBSx_IBlindScanAPI_SetMaxLPF(pBSsetting, M_TUNERMAXLPF_100KHZ); //Set Tuner max LPF value, this value will difference according tuner type
++
++ BS_Status = AVL_DVBSx_BS_Status_Start;
++
++ AVL6211_DumpSetting(pBSsetting);
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Start: {
++
++ r = AVL_DVBSx_IBlindScanAPI_Start(pAVLChip_all, avl6211pTuner, pBSsetting);
++ printk(KERN_INFO "AVL_DVBSx_BS_Status_Start %d\n", r);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ }
++ else
++ {
++
++ bsevent.status = BLINDSCAN_UPDATESTARTFREQ;
++ bsevent.u.m_uistartfreq_khz = avl6211pTuner->m_uiFrequency_100kHz * 100;
++ fe_use->ops.blindscan_ops.info.blindscan_callback(fe_use, &bsevent);
++ BS_Status = AVL_DVBSx_BS_Status_Wait;
++ }
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Wait: {
++ r = AVL_DVBSx_IBlindScanAPI_GetCurrentScanStatus(pAVLChip_all, pBSsetting);
++ printk(KERN_INFO "AVL_DVBSx_BS_Status_Wait %d %d\n", r, pBSsetting->bsInfo.m_uiChannelCount);
++ if(AVL_DVBSx_EC_GeneralFail == r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ }
++ if(AVL_DVBSx_EC_OK == r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Adjust;
++ }
++ if(AVL_DVBSx_EC_Running == r)
++ {
++ AVL_DVBSx_IBSP_Delay(100);
++ }
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Adjust: {
++ r = AVL_DVBSx_IBlindScanAPI_Adjust(pAVLChip_all, pBSsetting);
++ printk(KERN_INFO "AVL_DVBSx_BS_Status_Adjust %d\n", r);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ }
++ BS_Status = AVL_DVBSx_BS_Status_User_Process;
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_User_Process: {
++ printk(KERN_INFO "AVL_DVBSx_BS_Status_User_Process\n");
++ //------------Custom code start-------------------
++ //customer can add the callback function here such as adding TP information to TP list or lock the TP for parsing PSI
++ //Add custom code here; Following code is an example
++
++ /*----- example 1: print Blindscan progress ----*/
++ printf(" %2d%% \n", AVL_DVBSx_IBlindscanAPI_GetProgress(pBSsetting)); //display progress Percent of blindscan process
++
++ /*----- example 2: print TP information if found valid TP ----*/
++ while(index < pBSsetting->m_uiChannelCount) //display new TP info found in current stage
++ {
++ pChannel = &pBSsetting->channels[index++];
++ printf(" Ch%2d: RF: %4d SR: %5d ",index, (pChannel->m_uiFrequency_kHz/1000),(pChannel->m_uiSymbolRate_Hz/1000));
++
++ bsevent.status = BLINDSCAN_UPDATERESULTFREQ;
++ bsevent.u.parameters.frequency = pChannel->m_uiFrequency_kHz;
++ bsevent.u.parameters.u.qpsk.symbol_rate = pChannel->m_uiSymbolRate_Hz;
++
++ fe_use->ops.blindscan_ops.info.blindscan_callback(fe_use, &bsevent);
++ }
++
++ bsevent.status = BLINDSCAN_UPDATEPROCESS;
++ bsevent.u.m_uiprogress = AVL_DVBSx_IBlindscanAPI_GetProgress(pBSsetting);
++ fe_use->ops.blindscan_ops.info.blindscan_callback(fe_use, &bsevent);
++ //------------Custom code end -------------------
++
++ if ( (AVL_DVBSx_IBlindscanAPI_GetProgress(pBSsetting) < 100))
++ BS_Status = AVL_DVBSx_BS_Status_Start;
++ else
++ BS_Status = AVL_DVBSx_BS_Status_WaitExit;
++ break;
++ }
++ case AVL_DVBSx_BS_Status_WaitExit:
++ {
++ msleep(50);
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Cancel: {
++ r = AVL_DVBSx_IBlindScanAPI_Exit(pAVLChip_all,pBSsetting);
++ printk(KERN_INFO "AVL_DVBSx_BS_Status_Cancel %d\n", r);
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ blindstart=2;
++ break;
++ }
++
++ default: {
++ BS_Status = AVL_DVBSx_BS_Status_Cancel;
++ break;
++ }
++ }
++ }
++ return 0;
++
++
++}
++
++
++static struct task_struct *dvbs2_task;
++static int AVL6211_Blindscan_Scan(struct dvb_frontend* fe, struct dvbsx_blindscanpara *pbspara)
++{
++ printk(KERN_INFO "AVL6211_Blindscan_Scan printk\n");
++
++ AVL_DVBSx_IBSP_WaitSemaphore(&blindscanSem);
++ fe_use = fe;
++ blindstart=1;
++ AVL_DVBSx_IBSP_ReleaseSemaphore(&blindscanSem);
++ dvbs2_task = kthread_create(dvbs2_blindscan_task, pbspara, "dvbs2_task");
++ if(!dvbs2_task){
++ printk("Unable to start dvbs2 thread.\n");
++ dvbs2_task = NULL;
++ return -1;
++ }
++ wake_up_process(dvbs2_task);
++ return 0;
++}
++
++static int AVL6211_Blindscan_Cancel(struct dvb_frontend* fe)
++{
++ blindstart=0;
++ printk(KERN_INFO "AVL6211_Blindscan_Cancel\n");
++ while(2!=blindstart){
++ pr_dbg("wait for scan exit\n");
++ msleep(100);
++ }
++ /*call do_exit() directly*/
++ dvbs2_task = NULL;
++ fe_use = NULL;
++ return 0;
++}
++#endif
++
++static int initflag[2]= { -1, -1 };
++
++static int AVL6211_Read_Status(struct dvb_frontend *fe, fe_status_t * status)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ unsigned char s=0;
++//printk("Get status blindstart:%d.\n",blindstart);
++ if(1==blindstart[id])
++ s=1;
++ else
++ s=AVL6211_GETLockStatus(id);
++
++ if(s==1)
++ {
++ *status = FE_HAS_LOCK|FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC;
++ }
++ else
++ {
++ *status = 0;
++ }
++
++ return 0;
++}
++
++static int AVL6211_Read_Ber(struct dvb_frontend *fe, u32 * ber)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ if(1==blindstart[id])
++ return 0;
++ *ber=AVL6211_GETBer(id);
++ return 0;
++}
++
++static int AVL6211_Read_Signal_Strength(struct dvb_frontend *fe, u16 *strength)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ if(1==blindstart[id])
++ return 0;
++ *strength=AVL_Get_Level_Percent(pAVLChip_all[id]);
++// *strength=AVL6211_GETSignalLevel();
++ return 0;
++}
++static int AVL6211_Read_Snr(struct dvb_frontend *fe, u16 * snr)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ if(1==blindstart[id])
++ return 0;
++ *snr=AVL_Get_Quality_Percent(pAVLChip_all[id]);
++ //*snr=AVL6211_GETSnr();
++ return 0;
++}
++
++static int AVL6211_Read_Ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
++{
++ ucblocks=NULL;
++ return 0;
++}
++
++static int AVL6211_Set_Frontend(struct dvb_frontend *fe)
++{
++ struct aml_fe *afe = fe->demodulator_priv;
++ struct aml_fe_dev *dev = afe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++
++ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
++
++ int async_ret = 0;
++ pr_dbg("avl6211 set frontend=>frequency=%d,symbol_rate=%d\r\n",c->frequency,c->symbol_rate);
++
++ if(initflag[id]!=0)
++ {
++ pr_dbg("[%s] avl6211 init fail\n",__FUNCTION__);
++ return 0;
++ }
++// printk("[AVL6211_Set_Frontend],blindstart is %d\n",blindstart);
++
++ if(1==blindstart[id])
++ return 0;
++ AVL_DVBSx_IBSP_WaitSemaphore(&blindscanSem[id]);
++ if((850000>c->frequency)||(c->frequency>2300000))
++ {
++ c->frequency =945000;
++ pr_dbg("freq is out of range,force to set 945000khz\n");
++ }
++ struct avl6211_state *state = fe->demodulator_priv;
++ struct AVL_DVBSx_Channel Channel;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ avl6211pTuner[id]->m_uiFrequency_100kHz=c->frequency/100;
++// avl6211pTuner->m_uiFrequency_100kHz=15000;
++// printk("avl6211pTuner m_uiFrequency_100kHz is %d",avl6211pTuner->m_uiFrequency_100kHz);
++
++ /* r = CPU_Halt(pAVLChip_all);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("CPU halt failed !\n");
++ return (r);
++ }*/
++
++ //Change the value defined by macro and go back here when we want to lock a new channel.
++// avl6211pTuner->m_uiFrequency_100kHz = tuner_freq*10;
++ avl6211pTuner[id]->m_uiSymbolRate_Hz = c->symbol_rate;//c->symbol_rate;//30000000; //symbol rate of the channel to be locked.
++ //This function should be called before locking the tuner to adjust the tuner LPF based on channel symbol rate.
++ AVL_Set_LPF(id, avl6211pTuner[id], avl6211pTuner[id]->m_uiSymbolRate_Hz);
++
++ r=avl6211pTuner[id]->m_pLockFunc(avl6211pTuner[id]);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ state->freq=c->frequency;
++ state->mode=c->modulation ;
++ state->symbol_rate=c->symbol_rate;
++ AVL_DVBSx_IBSP_ReleaseSemaphore(&blindscanSem[id]);
++ pr_dbg("Tuner test failed !\n");
++ return (r);
++ }
++ pr_dbg("Tuner test ok !\n");
++ //msleep(50);
++ fe->ops.asyncinfo.set_frontend_asyncpreproc(fe);
++ async_ret = fe->ops.asyncinfo.set_frontend_asyncwait(fe, 50);
++ if(async_ret > 0){
++ fe->ops.asyncinfo.set_frontend_asyncpostproc(fe, async_ret);
++ AVL_DVBSx_IBSP_ReleaseSemaphore(&blindscanSem[id]);
++ return 0;
++ }
++ fe->ops.asyncinfo.set_frontend_asyncpostproc(fe, async_ret);
++ #if 0
++ Channel.m_uiSymbolRate_Hz = c->symbol_rate; //Change the value defined by macro when we want to lock a new channel.
++ Channel.m_Flags = (CI_FLAG_MANUAL_LOCK_MODE) << CI_FLAG_MANUAL_LOCK_MODE_BIT; //Manual lock Flag
++
++ Channel.m_Flags |= (CI_FLAG_IQ_NO_SWAPPED) << CI_FLAG_IQ_BIT; //Auto IQ swap
++ Channel.m_Flags |= (CI_FLAG_IQ_AUTO_BIT_AUTO) << CI_FLAG_IQ_AUTO_BIT; //Auto IQ swap Flag
++ //Support QPSK and 8PSK dvbs2
++ {
++ #define Coderate RX_DVBS2_2_3
++ #define Modulation AVL_DVBSx_MM_QPSK
++
++ if (Coderate > 16 || Coderate < 6 || Modulation > 3)
++ {
++ printf("Configure error !\n");
++ return AVL_DVBSx_EC_GeneralFail;
++ }
++ Channel.m_Flags |= (CI_FLAG_DVBS2) << CI_FLAG_DVBS2_BIT; //Disable automatic standard detection
++ Channel.m_Flags |= (enum AVL_DVBSx_FecRate)(Coderate) << CI_FLAG_CODERATE_BIT; //Manual config FEC code rate
++ Channel.m_Flags |= ((enum AVL_DVBSx_ModulationMode)(Modulation)) << CI_FLAG_MODULATION_BIT; //Manual config Modulation
++ }
++ //This function should be called after tuner locked to lock the channel.
++ #else
++ Channel.m_uiSymbolRate_Hz = c->symbol_rate;
++ Channel.m_Flags = (CI_FLAG_IQ_NO_SWAPPED) << CI_FLAG_IQ_BIT; //Normal IQ
++ Channel.m_Flags |= (CI_FLAG_IQ_AUTO_BIT_AUTO) << CI_FLAG_IQ_AUTO_BIT; //Enable automatic IQ swap detection
++ Channel.m_Flags |= (CI_FLAG_DVBS2_UNDEF) << CI_FLAG_DVBS2_BIT; //Enable automatic standard detection
++ #endif
++ r = AVL_DVBSx_IRx_LockChannel(&Channel, pAVLChip_all[id]);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ state->freq=c->frequency;
++ state->mode=c->modulation ;
++ state->symbol_rate=c->symbol_rate;
++ AVL_DVBSx_IBSP_ReleaseSemaphore(&blindscanSem[id]);
++ pr_dbg("Lock channel failed !\n");
++ return (r);
++ }
++ AVL_DVBSx_IBSP_ReleaseSemaphore(&blindscanSem[id]);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Lock channel failed !\n");
++ return (r);
++ }
++ int waittime=150;//3s
++ //Channel lock time increase while symbol rate decrease.Give the max waiting time for different symbolrates.
++ if(c->symbol_rate<5000000)
++ {
++ waittime = 150;//250; //The max waiting time is 5000ms,considering the IQ swapped status the time should be doubled.
++ }
++ else if(c->symbol_rate<10000000)
++ {
++ waittime = 30; //The max waiting time is 600ms,considering the IQ swapped status the time should be doubled.
++ }
++ else
++ {
++ waittime = 15; //The max waiting time is 300ms,considering the IQ swapped status the time should be doubled.
++ }
++ int lockstatus = 0;
++ fe->ops.asyncinfo.set_frontend_asyncpreproc(fe);
++ while(waittime)
++ {
++ //msleep(20);
++ async_ret = fe->ops.asyncinfo.set_frontend_asyncwait(fe, 20);
++ if(async_ret > 0){
++ break;
++ }
++
++ lockstatus=AVL6211_GETLockStatus(id);
++ if(1==lockstatus){
++ pr_dbg("lock success !\n");
++ break;
++ }
++
++ waittime--;
++ }
++ fe->ops.asyncinfo.set_frontend_asyncpostproc(fe, async_ret);
++
++ if(!AVL6211_GETLockStatus(id))
++ pr_dbg("lock timeout !\n");
++
++ r=AVL_DVBSx_IRx_ResetErrorStat(pAVLChip_all[id]);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ state->freq=c->frequency;
++ state->mode=c->modulation ;
++ state->symbol_rate=c->symbol_rate;
++
++ printf("Reset error status failed !\n");
++ return (r);
++ }
++
++// demod_connect(state, p->frequency,p->u.qam.modulation,p->u.qam.symbol_rate);
++ state->freq=c->frequency;
++ state->mode=c->modulation ;
++ state->symbol_rate=c->symbol_rate; //these data will be writed to eeprom
++
++ pr_dbg("avl6211=>frequency=%d,symbol_rate=%d\r\n",c->frequency,c->symbol_rate);
++ return 0;
++}
++
++static int AVL6211_Get_Frontend(struct dvb_frontend *fe)
++{//these content will be writed into eeprom .
++ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
++ struct avl6211_state *state = fe->demodulator_priv;
++
++ printk("delivery sys: %d\n", c->delivery_system);
++ c->frequency=state->freq;
++ c->symbol_rate=state->symbol_rate;
++
++ return 0;
++}
++
++static ssize_t avl_frontend_show_short_circuit(struct class* class, struct class_attribute* attr, char* buf)
++{
++ int ant_overload_status = AVL6211_Ant_Overload_Ctrl();
++
++ return sprintf(buf, "%d\n", ant_overload_status);
++}
++
++static struct class_attribute avl_frontend_class_attrs[] = {
++ __ATTR(short_circuit, S_IRUGO | S_IWUSR, avl_frontend_show_short_circuit, NULL),
++ __ATTR_NULL
++};
++
++static struct class avl_frontend_class = {
++ .name = "avl_frontend",
++ .class_attrs = avl_frontend_class_attrs,
++};
++
++static int avl6211_fe_get_ops(struct aml_fe_dev *dev, int mode, void *ops)
++{
++ struct dvb_frontend_ops *fe_ops = (struct dvb_frontend_ops*)ops;
++
++ char *fe_name = "AMLOGIC DVB-S2";
++ memcpy(fe_ops->info.name, fe_name, strlen(fe_name));
++ fe_ops->info.type = FE_QPSK;
++ fe_ops->delsys[0] = SYS_DVBS;
++ fe_ops->delsys[1] = SYS_DVBS2;
++ fe_ops->info.frequency_min = 850000;
++ fe_ops->info.frequency_max = 2300000;
++ fe_ops->info.frequency_stepsize = 0;
++ fe_ops->info.frequency_tolerance = 0;
++ fe_ops->info.symbol_rate_min = 1000000;
++ fe_ops->info.symbol_rate_max = 45000000;
++ fe_ops->info.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
++ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
++ FE_CAN_QPSK | FE_CAN_QAM_16 |
++ FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
++ FE_CAN_TRANSMISSION_MODE_AUTO |
++ FE_CAN_GUARD_INTERVAL_AUTO |
++ FE_CAN_HIERARCHY_AUTO |
++ FE_CAN_RECOVER |
++ FE_CAN_MUTE_TS;
++
++ fe_ops->set_frontend = AVL6211_Set_Frontend;
++ fe_ops->get_frontend = AVL6211_Get_Frontend;
++ fe_ops->read_status = AVL6211_Read_Status;
++ fe_ops->read_ber = AVL6211_Read_Ber;
++ fe_ops->read_signal_strength = AVL6211_Read_Signal_Strength;
++ fe_ops->read_snr = AVL6211_Read_Snr;
++ fe_ops->read_ucblocks = AVL6211_Read_Ucblocks;
++
++ fe_ops->diseqc_reset_overload = AVL6211_Diseqc_Reset_Overload;
++ fe_ops->diseqc_send_master_cmd = AVL6211_Diseqc_Send_Master_Cmd;
++ fe_ops->diseqc_recv_slave_reply = AVL6211_Diseqc_Recv_Slave_Reply;
++ fe_ops->diseqc_send_burst = AVL6211_Diseqc_Send_Burst;
++ fe_ops->set_tone = AVL6211_Set_Tone;
++ fe_ops->set_voltage = AVL6211_Set_Voltage;
++ fe_ops->enable_high_lnb_voltage = AVL6211_Enable_High_Lnb_Voltage;
++
++#if 0
++ fe_ops->blindscan_ops.blindscan_scan = AVL6211_Blindscan_Scan;
++ fe_ops->blindscan_ops.blindscan_cancel = AVL6211_Blindscan_Cancel;
++#endif
++ fe_ops->asyncinfo.set_frontend_asyncenable = 1;
++
++ return 0;
++}
++
++static int avl6211_fe_enter_mode(struct aml_fe *fe, int mode)
++{
++ struct aml_fe_dev *dev = fe->dtv_demod;
++ int id = dev->i2c_adap_id - 1;
++ cur_dvbdev[id] = dev;
++ pr_dbg("=========================demod init\r\n");
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ //init sema
++// AVL_DVBSx_IBSP_InitSemaphore( &blindscanSem );
++ //reset
++ if(!reset_demods) {
++ AVL6211_Reset(dev->reset_gpio);
++ msleep(100);
++ reset_demods++;
++ }
++ //init
++ r=AVL6211_LockSignal_Init(id);
++ //LBNON
++// AVL6211_Lnb_Power_Ctrl(1);
++ //tunerpower
++ AVL6211_Tuner_Power_Ctrl(id, 0);
++// r=AVL_DVBSx_IDiseqc_StopContinuous(pAVLChip_all);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ return r;
++ }
++ initflag[id] =0;
++ pr_dbg("0x%x(ptuner),0x%x(pavchip)=========================demod init\r\n",avl6211pTuner[id]->m_uiSlaveAddress,pAVLChip_all[id]->m_SlaveAddr);
++ msleep(200);
++
++ return 0;
++}
++
++
++static int avl6211_fe_resume(struct aml_fe_dev *dev)
++{
++
++ int id = dev->i2c_adap_id - 1;
++ cur_dvbdev[id] = dev;
++
++ pr_dbg("avl6211_fe_resume \n");
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ //init sema
++// AVL_DVBSx_IBSP_InitSemaphore( &blindscanSem );
++ //reset
++// AVL6211_Reset(dev->reset_gpio);
++// msleep(100);
++ //init
++ r=AVL6211_LockSignal_Init(id);
++ //LBNON
++// AVL6211_Lnb_Power_Ctrl(1);
++ //tunerpower
++ AVL6211_Tuner_Power_Ctrl(id, 0);
++// r=AVL_DVBSx_IDiseqc_StopContinuous(pAVLChip_all);
++
++ r=AVL_DVBSx_IBase_SetGPIODir(0, pAVLChip_all[id]);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ return r;
++ }
++ initflag[id] =0;
++ pr_dbg("0x%x(ptuner),0x%x(pavchip)=========================demod init\r\n",avl6211pTuner[id]->m_uiSlaveAddress,pAVLChip_all[id]->m_SlaveAddr);
++ msleep(200);
++ return 0;
++
++}
++
++static int avl6211_fe_suspend(struct aml_fe_dev *dev)
++{
++ return 0;
++}
++
++static struct aml_fe_drv avl6211_0_dtv_demod_drv = {
++.id = AM_DTV_DEMOD_AVL6211,
++.name = "Avl6211_0",
++.capability = AM_FE_QPSK,
++.get_ops = avl6211_fe_get_ops,
++.enter_mode = avl6211_fe_enter_mode,
++.suspend = avl6211_fe_suspend,
++.resume = avl6211_fe_resume
++};
++
++static struct aml_fe_drv avl6211_1_dtv_demod_drv = {
++.id = AM_DTV_DEMOD_AVL6211,
++.name = "Avl6211_1",
++.capability = AM_FE_QPSK,
++.get_ops = avl6211_fe_get_ops,
++.enter_mode = avl6211_fe_enter_mode,
++.suspend = avl6211_fe_suspend,
++.resume = avl6211_fe_resume
++};
++
++static int __init avlfrontend_init(void)
++{
++ AVL_DVBSx_IBSP_InitSemaphore( &blindscanSem[0] );
++ AVL_DVBSx_IBSP_InitSemaphore( &blindscanSem[1] );
++
++ pr_dbg("register avl6211_0 demod driver\n");
++ aml_register_fe_drv(AM_DEV_DTV_DEMOD, &avl6211_0_dtv_demod_drv);
++
++ pr_dbg("register avl6211_1 demod driver\n");
++ return aml_register_fe_drv(AM_DEV_DTV_DEMOD, &avl6211_1_dtv_demod_drv);
++}
++
++
++static void __exit avlfrontend_exit(void)
++{
++ pr_dbg("unregister avl6211_0 demod driver\n");
++ aml_unregister_fe_drv(AM_DEV_DTV_DEMOD, &avl6211_0_dtv_demod_drv);
++ pr_dbg("unregister avl6211_1 demod driver\n");
++ aml_unregister_fe_drv(AM_DEV_DTV_DEMOD, &avl6211_1_dtv_demod_drv);
++}
++
++fs_initcall(avlfrontend_init);
++module_exit(avlfrontend_exit);
++
++
++MODULE_DESCRIPTION("avl6211 DVB-S2 Demodulator driver");
++MODULE_AUTHOR("RSJ");
++MODULE_LICENSE("GPL");
++
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx_globals.h b/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx_globals.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx_globals.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx_globals.h 2014-12-11 16:13:50.153617135 +0100
+@@ -0,0 +1,361 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#ifndef AVL_DVBSX_GLOBALS_H
++#define AVL_DVBSX_GLOBALS_H
++
++#define raptor_status_addr (0x00000860 + 0x0)
++#define rx_rsp_addr (0x00000200 + 0x0)
++#define rx_cmd_addr (0x00000400 + 0x0)
++#define i2cm_cmd_addr (0x00000404 + 0x0)
++#define i2cm_rsp_addr (0x00000418 + 0x0)
++#define error_msg_addr (0x0000042c + 0x0)
++#define core_ready_word_addr (0x00000434 + 0x0)
++#define i2cm_status_addr (0x00000438 + 0x0)
++#define rx_config_addr (0x0000043c + 0x0)
++#define rx_state_addr (0x00000690 + 0x0)
++#define sharemem_addr (0x000008d8 + 0x0)
++#define patchglobalvar_addr (0x00002614 + 0x0)
++#define patchtext_addr (0x00002654 + 0x0)
++#define rom_ver_addr (0x00100000 + 0x0)
++#define rx_config_rom_addr (0x00100004 + 0x0)
++#define rp_sleep_wake_status_addr (0x00002632 + 0x0)
++
++#define rc_rfagc_pol_addr (rx_config_addr + 0x0)
++#define rc_alpha_addr (rx_config_addr + 0x4)
++#define rc_equalizer_addr (rx_config_addr + 0x8)
++#define rc_internal_decode_mode_addr (rx_config_addr + 0xc)
++#define rc_format_addr (rx_config_addr + 0x10)
++#define rc_input_addr (rx_config_addr + 0x14)
++#define rc_interleave_mode_addr (rx_config_addr + 0x18)
++#define rc_pkt_err_pol_addr (rx_config_addr + 0x1c)
++#define rc_mpeg_mode_addr (rx_config_addr + 0x20)
++#define rc_outpin_sel_addr (rx_config_addr + 0x24)
++#define rc_pkt_int_pattern_addr (rx_config_addr + 0x28)
++#define rc_mpeg_seri_seq_addr (rx_config_addr + 0x2c)
++#define rc_alpha_setting_addr (rx_config_addr + 0x30)
++#define rc_specinv_addr (rx_config_addr + 0x34)
++#define rc_stdout_port_addr (rx_config_addr + 0x38)
++#define rc_dvbs_snr_mode_addr (rx_config_addr + 0x3c)
++#define rc_blind_scan_avg_blk_num_addr (rx_config_addr + 0x40)
++#define rc_fec_coderate_addr (rx_config_addr + 0x44)
++#define rc_fec_modulation_addr (rx_config_addr + 0x48)
++#define rc_show_mod_pilot_addr (rx_config_addr + 0x4c)
++#define rc_btr_cd_th_addr (rx_config_addr + 0x50)
++#define rc_int_sym_rate_MHz_addr (rx_config_addr + 0x54)
++#define rc_blind_scan_sweep_range_hz_addr (rx_config_addr + 0x58)
++#define rc_blind_scan_acq_th_addr (rx_config_addr + 0x5c)
++#define rc_blind_scan_cd_th_addr (rx_config_addr + 0x60)
++#define rc_dvbs2_eq_adpt_sw_gain_acq_addr (rx_config_addr + 0x64)
++#define rc_dvbs_dss_eq_adpt_sw_gain_acq_addr (rx_config_addr + 0x68)
++#define rc_old_lwm_addr (rx_config_addr + 0x6c)
++#define rc_residue_addr (rx_config_addr + 0x70)
++#define rc_old_frame_cnt_addr (rx_config_addr + 0x74)
++#define rc_error_addr (rx_config_addr + 0x78)
++#define rc_patch_ver_addr (rx_config_addr + 0x7c)
++#define rc_expected_ROM_CRC_addr (rx_config_addr + 0x80)
++#define rc_ROM_CRC_start_addr_addr (rx_config_addr + 0x84)
++#define rc_ROM_CRC_end_addr_addr (rx_config_addr + 0x88)
++#define rc_modcode_corr_addr (rx_config_addr + 0x8c)
++#define rc_softcode_corr_addr (rx_config_addr + 0x90)
++#define rc_softcode_uw_addr (rx_config_addr + 0x94)
++#define rc_dvbs_ber_addr (rx_config_addr + 0x98)
++#define rc_blind_scan_sym_rate_tol_hz_addr (rx_config_addr + 0x9c)
++#define rc_coarse_num_adjust_factor_addr (rx_config_addr + 0xa0)
++#define rc_num_freq_candidate_addr (rx_config_addr + 0xa4)
++#define rc_rfagc_dcm_addr (rx_config_addr + 0xa6)
++#define rc_dagc_ref_addr (rx_config_addr + 0xa8)
++#define rc_aagc_ref_addr (rx_config_addr + 0xaa)
++#define rc_acq_coincidence_threshold_addr (rx_config_addr + 0xac)
++#define rc_acq_timeout_frames_addr (rx_config_addr + 0xae)
++#define rc_fec_wait_timeout_frames_addr (rx_config_addr + 0xb0)
++#define rc_freq_init_est_frames_addr (rx_config_addr + 0xb2)
++#define rc_freq_est_frames_addr (rx_config_addr + 0xb4)
++#define rc_lfsr_fb_invert_addr (rx_config_addr + 0xb6)
++#define rc_lfsr_mode_addr (rx_config_addr + 0xb8)
++#define rc_pkt_lfsr_en_addr (rx_config_addr + 0xba)
++#define rc_mpeg_posedge_addr (rx_config_addr + 0xbc)
++#define rc_mpeg_serial_addr (rx_config_addr + 0xbe)
++#define rc_seri_rate_frac_n_addr (rx_config_addr + 0xc0)
++#define rc_seri_rate_frac_d_addr (rx_config_addr + 0xc2)
++#define rc_para_rate_adj_n_addr (rx_config_addr + 0xc4)
++#define rc_para_rate_adj_d_addr (rx_config_addr + 0xc6)
++#define rc_show_demod_status_addr (rx_config_addr + 0xc8)
++#define rc_show_per_addr (rx_config_addr + 0xca)
++#define rc_show_ber_addr (rx_config_addr + 0xcc)
++#define rc_show_wer_addr (rx_config_addr + 0xce)
++#define rc_show_detail_addr (rx_config_addr + 0xd0)
++#define rc_show_scatter_addr (rx_config_addr + 0xd2)
++#define rc_show_period_frames_addr (rx_config_addr + 0xd4)
++#define rc_show_coeffs_addr (rx_config_addr + 0xd6)
++#define rc_pkt_err_mode_addr (rx_config_addr + 0xd8)
++#define rc_uw_lock_det_frames_addr (rx_config_addr + 0xda)
++#define rc_uw_lock_det_thresh_addr (rx_config_addr + 0xdc)
++#define rc_ddc_buffer_offset_addr (rx_config_addr + 0xde)
++#define rc_eq_buffer_offset_addr (rx_config_addr + 0xe0)
++#define rc_disable_freq_adj_addr (rx_config_addr + 0xe2)
++#define rc_crc_enabled_addr (rx_config_addr + 0xe4)
++#define rc_interleave_shift_addr (rx_config_addr + 0xe6)
++#define rc_skip_tune_addr (rx_config_addr + 0xe8)
++#define rc_skip_freq_est_addr (rx_config_addr + 0xea)
++#define rc_uw_corr_peak_num_addr (rx_config_addr + 0xec)
++#define rc_lock_detect_frm_num_addr (rx_config_addr + 0xee)
++#define rc_max_demod_reset_num_addr (rx_config_addr + 0xf0)
++#define rc_max_freq_tune_num_addr (rx_config_addr + 0xf2)
++#define rc_dagc_acq_gain_addr (rx_config_addr + 0xf4)
++#define rc_dagc_trk_gain_addr (rx_config_addr + 0xf6)
++#define rc_aagc_acq_gain_addr (rx_config_addr + 0xf8)
++#define rc_aagc_trk_gain_addr (rx_config_addr + 0xfa)
++#define rc_eq_loop_gain_addr (rx_config_addr + 0xfc)
++#define rc_eq_center_tap_position_addr (rx_config_addr + 0xfe)
++#define rc_eq_cnvg_frames_addr (rx_config_addr + 0x100)
++#define rc_dvbs2_eq_adpt_sw_gain_trk_addr (rx_config_addr + 0x102)
++#define rc_dvbs_dss_eq_adpt_sw_gain_trk_addr (rx_config_addr + 0x104)
++#define rc_dvbs2_eq_adpt_sw_symbol_acq_addr (rx_config_addr + 0x106)
++#define rc_dvbs2_eq_adpt_sw_symbol_trk_addr (rx_config_addr + 0x108)
++#define rc_dvbs_dss_eq_adpt_sw_symbol_acq_addr (rx_config_addr + 0x10a)
++#define rc_dvbs_dss_eq_adpt_sw_symbol_trk_addr (rx_config_addr + 0x10c)
++#define rc_pnref_addr (rx_config_addr + 0x10e)
++#define rc_dc_comp_acq_gain_addr (rx_config_addr + 0x110)
++#define rc_dc_comp_trk_gain_addr (rx_config_addr + 0x112)
++#define rc_dc_comp_init_i_addr (rx_config_addr + 0x114)
++#define rc_dc_comp_init_q_addr (rx_config_addr + 0x116)
++#define rc_iq_comp_acq_gain_addr (rx_config_addr + 0x118)
++#define rc_iq_comp_trk_gain_addr (rx_config_addr + 0x11a)
++#define rc_iq_amp_imb_addr (rx_config_addr + 0x11c)
++#define rc_iq_phs_imb_addr (rx_config_addr + 0x11e)
++#define rc_dc_comp_enable_addr (rx_config_addr + 0x120)
++#define rc_iq_comp_enable_addr (rx_config_addr + 0x122)
++#define rc_snr_settle_frames_addr (rx_config_addr + 0x124)
++#define rc_btr_acq_lpbw_addr (rx_config_addr + 0x126)
++#define rc_btr_uw_lpbw_addr (rx_config_addr + 0x128)
++#define rc_cpr_lpbw_addr (rx_config_addr + 0x12a)
++#define rc_cpr_acq_lpbw_addr (rx_config_addr + 0x12c)
++#define rc_cpr_trk_lpbw_addr (rx_config_addr + 0x12e)
++#define rc_cpr_freq_acq_rshft_addr (rx_config_addr + 0x130)
++#define rc_cpr_freq_trk_rshft_np_addr (rx_config_addr + 0x132)
++#define rc_cpr_freq_trk_ini_rshft_np_addr (rx_config_addr + 0x134)
++#define rc_cpr_freq_trk_rshft_p_addr (rx_config_addr + 0x136)
++#define rc_cpr_freq_trk_ini_rshft_p_addr (rx_config_addr + 0x138)
++#define rc_btr_dwell_time_ksym_addr (rx_config_addr + 0x13a)
++#define rc_cpr_output_en_addr (rx_config_addr + 0x13c)
++#define rc_cpr_lck_window_len_addr (rx_config_addr + 0x13e)
++#define rc_cpr_lck_unlock_cnt_addr (rx_config_addr + 0x140)
++#define rc_cpr_lck_thr_cpr_addr (rx_config_addr + 0x142)
++#define rc_cpr_dvbs_cnt_len_addr (rx_config_addr + 0x144)
++#define rc_cpr_freq_swp_upd_rate_addr (rx_config_addr + 0x146)
++#define rc_cpr_freq_swp_step_addr (rx_config_addr + 0x148)
++#define rc_cpr_freq_swp_times_addr (rx_config_addr + 0x14a)
++#define rc_cpr_freq_swp_rng_addr (rx_config_addr + 0x14c)
++#define rc_cpr_dvbs_dss_acq_lpbw_addr (rx_config_addr + 0x14e)
++#define rc_cpr_dvbs_dss_trk_lpbw_addr (rx_config_addr + 0x150)
++#define rc_cpr_freq_swp_init_val_addr (rx_config_addr + 0x152)
++#define rc_dvbs_dss_snr_est_blk_size_addr (rx_config_addr + 0x154)
++#define rc_dvbs_dss_snr_est_lpbw_addr (rx_config_addr + 0x156)
++#define rc_dvbs_dss_fec_init_sel_pkt_number_addr (rx_config_addr + 0x158)
++#define rc_fec_min_indx_repetitions_cm_addr (rx_config_addr + 0x15a)
++#define rc_fec_max_frame_chk_cm_addr (rx_config_addr + 0x15c)
++#define rc_dvbs_bypass_bit_descrambler_addr (rx_config_addr + 0x15e)
++#define rc_int_nom_carrier_freq_MHz_addr (rx_config_addr + 0x160)
++#define rc_int_dmd_clk_MHz_addr (rx_config_addr + 0x162)
++#define rc_int_fec_clk_MHz_addr (rx_config_addr + 0x164)
++#define rc_int_mpeg_clk_MHz_addr (rx_config_addr + 0x166)
++#define rc_int_btr_loop_bandwidth_addr (rx_config_addr + 0x168)
++#define rc_int_cpr_loop_bandwidth_addr (rx_config_addr + 0x16a)
++#define rc_int_carrier_freq_half_range_MHz_addr (rx_config_addr + 0x16c)
++#define rc_int_normalized_freq_step_addr (rx_config_addr + 0x16e)
++#define rc_int_lock_detect_loop_bw_addr (rx_config_addr + 0x170)
++#define rc_int_snr_measurement_tolerance_dB_addr (rx_config_addr + 0x172)
++#define rc_dvbs2_low_power_mode_addr (rx_config_addr + 0x174)
++#define rc_demap_scale_addr (rx_config_addr + 0x176)
++#define rc_fec_lock_num_addr (rx_config_addr + 0x178)
++#define rc_fec_lock_leak_addr (rx_config_addr + 0x17a)
++#define rc_fec_lock_threshold_addr (rx_config_addr + 0x17c)
++#define rc_dvbs_fec_lock_leak_addr (rx_config_addr + 0x17e)
++#define rc_dvbs_fec_lock_threshold_addr (rx_config_addr + 0x180)
++#define rc_modcod_descramble_flag_addr (rx_config_addr + 0x182)
++#define rc_fec_min_indx_repetitions_addr (rx_config_addr + 0x184)
++#define rc_dvbs_fec_fcnt_step_addr (rx_config_addr + 0x186)
++#define rc_fec_only_addr (rx_config_addr + 0x188)
++#define rc_toggle_fec_mode_addr (rx_config_addr + 0x18a)
++#define rc_fec_bypass_depunc_addr (rx_config_addr + 0x18c)
++#define rc_fec_max_frame_chk_addr (rx_config_addr + 0x18e)
++#define rc_dvbs_fec_max_trial_for_same_phase_addr (rx_config_addr + 0x190)
++#define rc_fec_deintrlvr_rs_rst_addr (rx_config_addr + 0x192)
++#define rc_fec_bypass_coderate_addr (rx_config_addr + 0x194)
++#define rc_vtrbi_performance_test_addr (rx_config_addr + 0x196)
++#define rc_fec_pk_thrshld_addr (rx_config_addr + 0x198)
++#define rc_dss_fec_max_trial_for_same_phase_addr (rx_config_addr + 0x19a)
++#define rc_dss_fec_fcnt_step_addr (rx_config_addr + 0x19c)
++#define rc_btr_cd_num_addr (rx_config_addr + 0x19e)
++#define rc_accel_track_addr (rx_config_addr + 0x1a0)
++#define rc_mpeg_sync_byte_addr (rx_config_addr + 0x1a2)
++#define rc_dvbs_equalizer_cnvg_iter_no_addr (rx_config_addr + 0x1a4)
++#define rc_modcod_scrmb_mmsb_addr (rx_config_addr + 0x1a6)
++#define rc_modcod_scrmb_mlsb_addr (rx_config_addr + 0x1a8)
++#define rc_modcod_scrmb_lmsb_addr (rx_config_addr + 0x1aa)
++#define rc_modcod_scrmb_llsb_addr (rx_config_addr + 0x1ac)
++#define rc_i2cm_speed_kHz_addr (rx_config_addr + 0x1ae)
++#define rc_i2cm_time_out_addr (rx_config_addr + 0x1b0)
++#define rc_tuner_frequency_100kHz_addr (rx_config_addr + 0x1b2)
++#define rc_tuner_LPF_100kHz_addr (rx_config_addr + 0x1b4)
++#define rc_tuner_slave_addr_addr (rx_config_addr + 0x1b6)
++#define rc_tuner_max_LPF_100kHz_addr (rx_config_addr + 0x1b8)
++#define rc_tuner_LPF_margin_100kHz_addr (rx_config_addr + 0x1ba)
++#define rc_tuner_use_internal_control_addr (rx_config_addr + 0x1bc)
++#define rc_blind_scan_start_freq_100kHz_addr (rx_config_addr + 0x1be)
++#define rc_blind_scan_end_freq_100kHz_addr (rx_config_addr + 0x1c0)
++#define rc_blind_scan_min_sym_rate_kHz_addr (rx_config_addr + 0x1c2)
++#define rc_blind_scan_max_sym_rate_kHz_addr (rx_config_addr + 0x1c4)
++#define rc_blind_scan_channel_info_offset_addr (rx_config_addr + 0x1c6)
++#define rc_blind_scan_process_range_100kHz_addr (rx_config_addr + 0x1c8)
++#define rc_blind_scan_sweep_scalor_addr (rx_config_addr + 0x1ca)
++#define rc_blind_scan_sweep_max_addr (rx_config_addr + 0x1cc)
++#define rc_blind_scan_low_sym_swp_range_addr (rx_config_addr + 0x1ce)
++#define rc_blind_scan_acq_num_addr (rx_config_addr + 0x1d0)
++#define rc_blind_scan_cd_num_addr (rx_config_addr + 0x1d2)
++#define rc_blind_scan_acq_btr_lbw_addr (rx_config_addr + 0x1d4)
++#define rc_blind_scan_cd_btr_lbw_addr (rx_config_addr + 0x1d6)
++#define rc_blind_scan_uw_en_addr (rx_config_addr + 0x1d8)
++#define rc_blind_scan_ts_retry_addr (rx_config_addr + 0x1da)
++#define rc_blind_scan_freq_step_100kHz_addr (rx_config_addr + 0x1dc)
++#define rc_blind_scan_freq_decimation_addr (rx_config_addr + 0x1de)
++#define rc_blind_scan_mode_addr (rx_config_addr + 0x1e0)
++#define rc_blind_scan_show_detail_addr (rx_config_addr + 0x1e2)
++#define rc_blind_scan_max_left1_100kHz_addr (rx_config_addr + 0x1e4)
++#define rc_blind_scan_max_left2_100kHz_addr (rx_config_addr + 0x1e6)
++#define rc_blind_scan_freq_back_100kHz_addr (rx_config_addr + 0x1e8)
++#define rc_descram_X_init_msb_addr (rx_config_addr + 0x1ea)
++#define rc_descram_X_init_lsb_addr (rx_config_addr + 0x1ec)
++#define rc_descram_Y_init_msb_addr (rx_config_addr + 0x1ee)
++#define rc_descram_Y_init_lsb_addr (rx_config_addr + 0x1f0)
++#define rc_pl_descram_en_addr (rx_config_addr + 0x1f2)
++#define rc_iq_try_times_addr (rx_config_addr + 0x1f4)
++#define rc_iq_retries_addr (rx_config_addr + 0x1f6)
++#define rc_pll_fec_addr (rx_config_addr + 0x1f8)
++#define rc_pll_mpeg_addr (rx_config_addr + 0x1fa)
++#define rc_in_soft_sleep_mode_addr (rx_config_addr + 0x1fc)
++#define rc_in_hard_sleep_mode_addr (rx_config_addr + 0x1fe)
++#define rc_in_sleep_mode_addr (rx_config_addr + 0x200)
++#define rc_decode_mode_addr (rx_config_addr + 0x202)
++#define rc_iq_mode_addr (rx_config_addr + 0x204)
++#define rc_blind_scan_carrier_db_addr (rx_config_addr + 0x206)
++#define rc_dishpoint_mode_addr (rx_config_addr + 0x208)
++#define rc_lock_mode_addr (rx_config_addr + 0x20a)
++#define rc_functional_mode_addr (rx_config_addr + 0x20c)
++#define rc_blind_scan_reset_addr (rx_config_addr + 0x20e)
++#define rc_mpeg_continuous_mode_control_addr (rx_config_addr + 0x210)
++#define rc_hwm_threshold_addr (rx_config_addr + 0x212)
++#define rc_lwm_threshold_addr (rx_config_addr + 0x214)
++#define rc_pll_adust_period_addr (rx_config_addr + 0x216)
++#define rc_time_constant_addr (rx_config_addr + 0x218)
++#define rc_pkt_fifo_hwm_addr (rx_config_addr + 0x21a)
++#define rc_pkt_fifo_lwm_addr (rx_config_addr + 0x21c)
++#define rc_bs_pk_to_avg_threshold_addr (rx_config_addr + 0x21e)
++#define rc_blind_scan_tuner_spectrum_inversion_addr (rx_config_addr + 0x220)
++
++
++#define rs_main_state_addr (rx_state_addr + 0x0)
++#define rs_last_main_state_addr (rx_state_addr + 0x4)
++#define rs_code_rate_addr (rx_state_addr + 0x8)
++#define rs_modulation_addr (rx_state_addr + 0xc)
++#define rs_pilot_addr (rx_state_addr + 0x10)
++#define rs_frame_length_addr (rx_state_addr + 0x14)
++#define rs_frame_count_addr (rx_state_addr + 0x18)
++#define rs_int_decim_samp_rate_MHz_addr (rx_state_addr + 0x1c)
++#define rs_int_freq_MHz_addr (rx_state_addr + 0x20)
++#define rs_int_SNR_dB_addr (rx_state_addr + 0x40)
++#define rs_int_ck_i_addr (rx_state_addr + 0x44)
++#define rs_int_ck_q_addr (rx_state_addr + 0x48)
++#define rs_int_ek_addr (rx_state_addr + 0x4c)
++#define rs_int_snr_addr (rx_state_addr + 0x50)
++#define rs_int_instant_snr_addr (rx_state_addr + 0x54)
++#define rs_eq_loop_gain_scl_addr (rx_state_addr + 0x58)
++#define rs_eq_loop_gain_rshft_addr (rx_state_addr + 0x5c)
++#define rs_eq_i_coeffs_addr (rx_state_addr + 0x60)
++#define rs_eq_q_coeffs_addr (rx_state_addr + 0x90)
++#define rs_corr_val_addr (rx_state_addr + 0xc0)
++#define rs_mode_code_addr (rx_state_addr + 0xe0)
++#define rs_demod_reset_times_addr (rx_state_addr + 0xe4)
++#define rs_uw_clk32cnt_acc_addr (rx_state_addr + 0xe8)
++#define rs_freq_tune_times_addr (rx_state_addr + 0xec)
++#define rs_fec_err_accum_addr (rx_state_addr + 0xf0)
++#define rs_equalizer_control_addr (rx_state_addr + 0xf4)
++#define rs_eq_adpt_sw_gain_addr (rx_state_addr + 0xf8)
++#define rs_int_mer_addr (rx_state_addr + 0xfc)
++#define rs_int_mer_s_addr (rx_state_addr + 0x100)
++#define rs_int_mer_e_addr (rx_state_addr + 0x104)
++#define rs_int_mer_e_i_addr (rx_state_addr + 0x108)
++#define rs_int_mer_e_q_addr (rx_state_addr + 0x10c)
++#define rs_blind_scan_bin_size_Hz_addr (rx_state_addr + 0x110)
++#define rs_calc_ROM_CRC_addr (rx_state_addr + 0x114)
++#define rs_uw_i_ptr_addr (rx_state_addr + 0x118)
++#define rs_uw_q_ptr_addr (rx_state_addr + 0x11c)
++#define rs_uw_i_ref_ptr_addr (rx_state_addr + 0x120)
++#define rs_uw_q_ref_ptr_addr (rx_state_addr + 0x124)
++#define rs_mc_i_ref_ptr_addr (rx_state_addr + 0x128)
++#define rs_mc_q_ref_ptr_addr (rx_state_addr + 0x12c)
++#define rs_mc_ptr_addr (rx_state_addr + 0x130)
++#define rs_xi_ptr_addr (rx_state_addr + 0x134)
++#define rs_xq_ptr_addr (rx_state_addr + 0x138)
++#define rs_int_buf_ptr_addr (rx_state_addr + 0x13c)
++#define rs_eq_adpt_sw_symbol_addr (rx_state_addr + 0x140)
++#define rs_int_carrier_freq_100kHz_addr (rx_state_addr + 0x142)
++#define rs_num_uw_acquisition_addr (rx_state_addr + 0x144)
++#define rs_next_punc_cnt_addr (rx_state_addr + 0x146)
++#define rs_next_punc_cnt_mod_32_addr (rx_state_addr + 0x148)
++#define rs_loop_max_addr (rx_state_addr + 0x14a)
++#define rs_fcnt_step_temp_addr (rx_state_addr + 0x14c)
++#define rs_acq_state_addr (rx_state_addr + 0x14e)
++#define rs_indx_trial_addr (rx_state_addr + 0x150)
++#define rs_min_occurance_addr (rx_state_addr + 0x152)
++#define rs_fcnt_step_addr (rx_state_addr + 0x154)
++#define rs_max_trial_addr (rx_state_addr + 0x156)
++#define rs_loop_addr (rx_state_addr + 0x158)
++#define rs_max_occ_addr (rx_state_addr + 0x15a)
++#define rs_sync_indx_addr (rx_state_addr + 0x15c)
++#define rs_dvbs_dss_fec_lock_addr (rx_state_addr + 0x15e)
++#define rs_sym_offset_addr (rx_state_addr + 0x160)
++#define rs_uw_lock_addr (rx_state_addr + 0x162)
++#define rs_fec_lock_addr (rx_state_addr + 0x164)
++#define rs_snr_count_addr (rx_state_addr + 0x166)
++#define rs_freq_est_frames_addr (rx_state_addr + 0x168)
++#define rs_valid_modcod_addr (rx_state_addr + 0x16a)
++#define rs_eq_cnvg_status_addr (rx_state_addr + 0x16c)
++#define rs_freq_est_status_addr (rx_state_addr + 0x16e)
++#define rs_rx_rsp_ptr_addr (rx_state_addr + 0x170)
++#define rs_demap_table_state_addr (rx_state_addr + 0x172)
++#define rs_ldpc_table_state_addr (rx_state_addr + 0x174)
++#define rs_ROM_CRC_status_addr (rx_state_addr + 0x176)
++#define rs_blind_scan_btr_lock_addr (rx_state_addr + 0x178)
++#define rs_blind_scan_channel_count_addr (rx_state_addr + 0x17a)
++#define rs_blind_scan_progress_addr (rx_state_addr + 0x17c)
++#define rs_blind_scan_error_code_addr (rx_state_addr + 0x17e)
++#define rs_blind_scan_bin_numbers_addr (rx_state_addr + 0x180)
++#define rs_blind_scan_max_left1_bins_addr (rx_state_addr + 0x182)
++#define rs_blind_scan_max_left2_bins_addr (rx_state_addr + 0x184)
++#define rs_tuner_status_addr (rx_state_addr + 0x186)
++#define rs_ScatterData_rdy_addr (rx_state_addr + 0x188)
++
++
++#define rp_uint_BER_addr (raptor_status_addr + 0x0)
++#define rp_uint_PER_addr (raptor_status_addr + 0x4)
++#define rp_uint_WER_addr (raptor_status_addr + 0x8)
++
++
++#define c68k_ready_word_addr core_ready_word_addr
++
++#define rc_s2_modulation (patchglobalvar_addr + 0x1a)
++#define rc_s2_coderate (patchglobalvar_addr + 0x1c)
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx.h b/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/avl_dvbsx.h 2014-12-11 16:13:50.033618053 +0100
+@@ -0,0 +1,333 @@
++
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Defines data structures, enumerations, and global macros for the AVL_DVBSx device.
++///
++#ifndef AVL_DVBSx_h_h
++ #define AVL_DVBSx_h_h
++
++ #include "avl.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ // The CI_FLAG_... macros below pertain to the m_Flags member of the AVL_DVBSx_Channel structure.
++ #define CI_FLAG_IQ_BIT 0x00000000 /// The index of the bit which controls the IQ swap setting
++ #define CI_FLAG_IQ_BIT_MASK 0x00000001 /// A bit mask for accessing the IQ swap bit
++ #define CI_FLAG_IQ_NO_SWAPPED 0x00000000 /// Setting the CI_FLAG_IQ_BIT to this value means that the I and Q signals are not swapped
++ #define CI_FLAG_IQ_SWAPPED 0x00000001 /// Setting the CI_FLAG_IQ_BIT to this value means that the I and Q signals are swapped
++
++ #define CI_FLAG_DVBS2_BIT 0x00000002 /// The start index of the bit which controls the standard setting
++ #define CI_FLAG_DVBS2_BIT_MASK 0x0000001c /// A bit mask for accessing the standard setting
++ #define CI_FLAG_DVBS 0x00000000 /// The value which represents the DVB-S standard
++ #define CI_FLAG_DVBS2 0x00000001 /// The value which represents the DVB-S2 standard
++ #define CI_FLAG_DVBS2_UNDEF 0x00000004 /// The value which indicates that the standard is not known
++
++ #define CI_FLAG_MANUAL_LOCK_MODE_BIT 0x00000001 /// The index of the bit which controls the manual code rate setting
++ #define CI_FLAG_MANUAL_LOCK_MODE_BIT_MASK 0x00000002 /// A bit mask for accessing the manual code rate bit
++ #define CI_FLAG_MANUAL_LOCK_MODE 0x00000001 /// Setting the CI_FLAG_MANUAL_LOCK_MODE_BIT to this value means that the code rate can be manually configured
++ #define CI_FLAG_AUTO_LOCK_MODE 0x00000000 /// Setting the CI_FLAG_MANUAL_LOCK_MODE_BIT to this value means that the code rate will be detected automatically by the hardware
++
++ #define CI_FLAG_CODERATE_BIT 0x00000008 /// The index of the bit which controls the code rate setting
++ #define CI_FLAG_CODERATE_BIT_MASK 0x00001f00 /// A bit mask for accessing the index value of code rate
++
++ #define CI_FLAG_MODULATION_BIT 0x0000000d /// The index of the bit which controls the modulation mode setting
++ #define CI_FLAG_MODULATION_BIT_MASK 0x00006000 /// A bit mask for accessing the index value of modulation mode
++
++ #define CI_FLAG_IQ_AUTO_BIT 0x00000005 /// The index of the bit which controls the automatic IQ swap setting
++ #define CI_FLAG_IQ_AUTO_BIT_MASK 0x00000020 /// A bit mask for accessing the automatic IQ swap bit
++ #define CI_FLAG_IQ_AUTO_BIT_OFF 0x00000000 /// Setting the CI_FLAG_AUTO_BIT to this value disables automatic IQ swap
++ #define CI_FLAG_IQ_AUTO_BIT_AUTO 0x00000001 /// Setting the CI_FLAG_AUTO_BIT to this value enables automatic IQ swap
++
++ #define CI_FLAG_LOCK_MODE_BIT 0x00000006 /// The index of the bit which controls the channel lock mode
++ #define CI_FLAG_LOCK_MODE_BIT_MASK 0x00000040 /// A bit mask for accessing the channel lock mode
++
++ #define CI_FLAG_ADAPTIVE_POWER_SAVE_BIT 0x00000007 /// The index of the bit which controls whether adaptive power save mode is enabled
++ #define CI_FLAG_ADAPTIVE_POWER_SAVE_BIT_MASK 0x00000080 /// A bit mask for accessing the adaptive power save mode bit
++
++ typedef AVL_uint16 AVL_DVBSx_ErrorCode; ///< Defines the return code for Availink device operations. \sa AVL_DVBSx_EC_OK, AVL_DVBSx_EC_GeneralFail, AVL_DVBSx_EC_I2CFail, AVL_DVBSx_EC_TimeOut, AVL_DVBSx_EC_Running, AVL_DVBSx_EC_MemoryRunout, AVL_DVBSx_EC_BSP_ERROR1, AVL_DVBSx_EC_BSP_ERROR2
++
++ #define AVL_DVBSx_EC_OK 0 ///< There is no error.
++ #define AVL_DVBSx_EC_GeneralFail 1 ///< Some general failure happened.
++ #define AVL_DVBSx_EC_I2CFail 2 ///< I2C bus failed.
++ #define AVL_DVBSx_EC_TimeOut 4 ///< Operation failed in a given time period
++ #define AVL_DVBSx_EC_Running 8 ///< The Availink device is still processing a previous command.
++ #define AVL_DVBSx_EC_InSleepMode 16 ///< The requested receiver command could not be sent because the Availink device is in sleep mode.
++ #define AVL_DVBSx_EC_MemoryRunout 32 ///< The Availink device has insufficient memory to complete the current operation.
++ #define AVL_DVBSx_EC_BSP_ERROR1 64 ///< User defined error code for reporting BSP operation failure.
++ #define AVL_DVBSx_EC_BSP_ERROR2 128 ///< User defined error code for reporting BSP operation failure.
++
++ #define AVL_DVBSx_SA_0 0x0C ///< Availink device slave address 0. Up to two Availink devices are supported on one I2C bus.
++ #define AVL_DVBSx_SA_1 0x0D ///< Availink device slave address 1. Up to two Availink devices are supported on one I2C bus.
++
++ ///
++ /// Represents the code rate. The Availink device can automatically detect the code rate of the input signal.
++ enum AVL_DVBSx_FecRate
++ {
++ RX_DVBS_1_2 = 0, ///< = 0 Code rate 1/2
++ RX_DVBS_2_3 = 1, ///< = 1 Code rate 2/3
++ RX_DVBS_3_4 = 2, ///< = 2 Code rate 3/4
++ RX_DVBS_5_6 = 3, ///< = 3 Code rate 5/6
++ RX_DVBS_6_7 = 4, ///< = 4 Code rate 6/7
++ RX_DVBS_7_8 = 5, ///< = 5 Code rate 7/8
++ RX_DVBS2_1_4 = 6, ///< = 6 Code rate 1/4
++ RX_DVBS2_1_3 = 7, ///< = 7 Code rate 1/3
++ RX_DVBS2_2_5 = 8, ///< = 8 Code rate 2/5
++ RX_DVBS2_1_2 = 9, ///< = 9 Code rate 1/2
++ RX_DVBS2_3_5 = 10, ///< = 10 Code rate 3/5
++ RX_DVBS2_2_3 = 11, ///< = 11 Code rate 2/3
++ RX_DVBS2_3_4 = 12, ///< = 12 Code rate 3/4
++ RX_DVBS2_4_5 = 13, ///< = 13 Code rate 4/5
++ RX_DVBS2_5_6 = 14, ///< = 14 Code rate 5/6
++ RX_DVBS2_8_9 = 15, ///< = 15 Code rate 8/9
++ RX_DVBS2_9_10 = 16 ///< = 16 Code rate 9/10
++ };
++
++ ///
++ /// Represents the Pilot mode of the signal. The Availink device can automatically detect the Pilot mode of the received signal.
++ enum AVL_DVBSx_Pilot
++ {
++ RX_Pilot_off = 0, ///< = 0 Pilot off
++ RX_Pilot_on = 1 ///< = 1 Pilot on
++ };
++
++ ///
++ /// Represents the channel lock mode.
++ enum AVL_DVBSx_LockMode
++ {
++ AVL_DVBSx_LOCK_MODE_FIXED = 0, ///< = 0 Fixed lock mode
++ AVL_DVBSx_LOCK_MODE_ADAPTIVE = 1 ///< = 1 Adaptive lock mode
++ };
++
++ ///
++ /// Represents the modulation mode. The Availink device can automatically detect the modulation mode of the received signal.
++ enum AVL_DVBSx_ModulationMode
++ {
++ AVL_DVBSx_MM_QPSK = 0, ///< = 0 QPSK
++ AVL_DVBSx_MM_8PSK = 1, ///< = 1 8-PSK
++ AVL_DVBSx_MM_16APSK = 2, ///< = 2 16-APSK
++ AVL_DVBSx_MM_32APSK = 3 ///< = 3 32-APSK
++ };
++
++ ///
++ /// The roll off of the received signal. The Availink device can automatically detect this value from the received signal.
++ enum AVL_DVBSx_RollOff
++ {
++ AVL_DVBSx_RO_20 = 0, ///< = 0 Rolloff is 0.20
++ AVL_DVBSx_RO_25 = 1, ///< = 1 Rolloff is 0.25
++ AVL_DVBSx_RO_35 = 2 ///< = 2 Rolloff is 0.35
++ };
++
++ ///
++ /// The MPEG output format. The default value in the Availink device is \a AVL_DVBSx_MPF_TS
++ enum AVL_DVBSx_MpegFormat
++ {
++ AVL_DVBSx_MPF_TS = 0, ///< = 0 Transport stream format.
++ AVL_DVBSx_MPF_TSP = 1 ///< = 1 Transport stream plus parity format.
++ };
++
++ ///
++ /// The MPEG output mode. The default value in the Availink device is \a AVL_DVBSx_MPM_Parallel
++ enum AVL_DVBSx_MpegMode
++ {
++ AVL_DVBSx_MPM_Parallel = 0, ///< = 0 Output MPEG data in parallel mode
++ AVL_DVBSx_MPM_Serial = 1 ///< = 0 Output MPEG data in serial mode
++ };
++
++ ///
++ /// The MPEG output clock polarity. The clock polarity should be configured to meet the back end device's requirement.
++ /// The default value in the Availink device is \a AVL_DVBSx_MPCP_Rising
++ enum AVL_DVBSx_MpegClockPolarity
++ {
++ AVL_DVBSx_MPCP_Falling = 0, ///< = 0 The MPEG data is valid on the falling edge of the clock.
++ AVL_DVBSx_MPCP_Rising = 1 ///< = 1 The MPEG data is valid on the rising edge of the clock.
++ };
++
++ ///
++ /// Internal MPEG pull-down resistor control. Used to enable or disable the internal MPEG interface pull-down resistors.
++ /// The default value in AVL_DVBSx is \a AVL_DVBSx_MPPD_Enable
++ enum AVL_DVBSx_MpegPulldown
++ {
++ AVL_DVBSx_MPPD_Disable = 0, ///< = 0 The internal MPEG interface pull-down resistors are disabled.
++ AVL_DVBSx_MPPD_Enable = 1 ///< = 1 The internal MPEG interface pull-down resistors are enabled.
++ };
++
++ ///
++ /// Defines the output bit order of the MPEG data bytes. The meaning differs depending on whether the MPEG interface
++ /// is configured to output data in serial mode or parallel mode as follows:
++ /// Serial Mode: Normal - The device outputs the MSB of each byte first and the LSB of each byte last.
++ // Invert - The device outputs the LSB of each byte first and the MSB of each byte last.
++ /// Parallel Mode: Normal - The device outputs the MSB of each byte on pin MPEG_DATA_7 and the LSB of each byte on pin MPEG_DATA_0.
++ /// Invert - The device outputs the LSB of each byte on pin MPEG_DATA_7 and the MSB of each byte on pin MPEG_DATA_0.
++ enum AVL_DVBSx_MpegBitOrder
++ {
++ AVL_DVBSx_MPBO_Normal = 0, ///< = 0 Normal output bit order
++ AVL_DVBSx_MPBO_Invert = 1 ///< = 1 Inverted output bit order
++ };
++
++ ///
++ /// Defines the pin on which the Availink device outputs the MPEG data when the MPEG interface has been configured to operate
++ /// in serial mode.
++ enum AVL_DVBSx_MpegSerialPin
++ {
++ AVL_DVBSx_MPSP_DATA0 = 0, ///< = 0 Serial data is output on pin MPEG_DATA_0
++ AVL_DVBSx_MPSP_DATA7 = 1 ///< = 1 Serial data is output on pin MPEG_DATA_7
++ };
++
++ ///
++ /// Defines the polarity of the MPEG data valid signal when the MPEG interface is configured to operate in TSP mode.
++ enum AVL_DVBSx_MpegValidPolarity
++ {
++ AVL_DVBSx_MPVP_Normal = 0, ///< = 0 The MPEG data valid signal is high during the payload data and low during the parity bytes.
++ AVL_DVBSx_MPVP_Invert = 1 ///< = 1 The MPEG data valid signal is low during the payload data and high during the parity bytes.
++ };
++
++ ///
++ /// Defines the polarity of the MPEG error signal.
++ enum AVL_DVBSx_MpegErrorPolarity
++ {
++ AVL_DVBSx_MPEP_Normal = 0, ///< = 0 The MPEG error signal is high during the payload of a packet which contains uncorrectable error(s).
++ AVL_DVBSx_MPEP_Invert = 1 ///< = 1 The MPEG error signal is low during the payload of a packet which contains uncorrectable error(s).
++ };
++
++ ///
++ /// Defines the polarity of the RF AGC control signal. The polarity of the RF AGC control signal must be
++ /// configured to match that required by the tuner.
++ /// The default value in the Availink device is \a AVL_DVBSx_RA_Invert
++ enum AVL_DVBSx_RfagcPola
++ {
++ AVL_DVBSx_RA_Normal = 0, ///< = 0 Normal polarization. This setting is used for a tuner whose gain increases with increased AGC voltage.
++ AVL_DVBSx_RA_Invert = 1 ///< = 1 Inverted polarization. The default value. Most tuners fall into this category. This setting is used for a tuner whose gain decreases with increased AGC voltage.
++ };
++
++ ///
++ /// Defines the device functional mode.
++ enum AVL_DVBSx_FunctionalMode
++ {
++ AVL_DVBSx_FunctMode_Demod = 0, ///< = 0 The device is in demod mode.
++ AVL_DVBSx_FunctMode_BlindScan = 1 ///< = 1 The device is in blind scan mode
++ };
++
++ ///
++ /// Defines the device spectrum polarity setting.
++ enum AVL_DVBSx_SpectrumPolarity
++ {
++ AVL_DVBSx_Spectrum_Normal = 0, ///< = 0 The received signal spectrum is not inverted.
++ AVL_DVBSx_Spectrum_Invert = 1 ///< = 1 The received signal spectrum is inverted.
++ };
++
++ ///
++ /// Defines the sleep-wake status of the Availink device
++ enum AVL_DVBSx_Sleep_Wake_Status
++ {
++ AVL_DVBSx_Sleep_Mode = 0,
++ AVL_DVBSx_Wake_Mode = 1
++ };
++
++ ///
++ /// Defines the DiSEqC status
++ enum AVL_DVBSx_Diseqc_OPStatus
++ {
++ AVL_DVBSx_DOS_Uninitialized = 0, ///< = 0 DiSEqC has not been initialized yet.
++ AVL_DVBSx_DOS_Initialized = 1, ///< = 1 DiSEqC has been initialized.
++ AVL_DVBSx_DOS_InContinuous = 2, ///< = 2 DiSEqC is in continuous mode.
++ AVL_DVBSx_DOS_InTone = 3, ///< = 3 DiSEqC is in tone burst mode.
++ AVL_DVBSx_DOS_InModulation = 4 ///< = 4 DiSEqC is in modulation mode.
++ };
++
++ /// Stores the MPEG interface configuration parameters that typically need to be configured for the user application.
++ struct AVL_DVBSx_MpegInfo
++ {
++ enum AVL_DVBSx_MpegFormat m_MpegFormat; ///< The MPEG output format (TS or TSP)
++ enum AVL_DVBSx_MpegMode m_MpegMode; ///< The MPEG output mode (parallel or serial)
++ enum AVL_DVBSx_MpegClockPolarity m_MpegClockPolarity; ///< The polarity of the MPEG clock signal
++ } ;
++
++ /// Stores the properties which characterize the received signal
++ struct AVL_DVBSx_SignalInfo
++ {
++ enum AVL_DVBSx_Pilot m_pilot; ///< The pilot mode. \sa ::AVL_DVBSx_Pilot.
++ enum AVL_DVBSx_FecRate m_coderate; ///< The code rate. \sa ::AVL_DVBSx_FecRate.
++ enum AVL_DVBSx_ModulationMode m_modulation; ///< The modulation mode. \sa ::AVL_DVBSx_ModulationMode.
++ enum AVL_DVBSx_RollOff m_rolloff; ///< The roll-off (excess bandwidth). \sa ::AVL_DVBSx_RollOff.
++ };
++
++ /// Stores the carrier channel parameters.
++ struct AVL_DVBSx_Channel
++ {
++ AVL_uint32 m_uiFrequency_kHz; ///< The channel carrier frequency in units of kHz.
++ AVL_uint32 m_uiSymbolRate_Hz; ///< The symbol rate in units of Hz.
++ AVL_uint32 m_Flags; ///< Contains bit-mapped fields which store additional channel configuration information.
++ };
++
++ /// The structure stores the data and flags associated with the Availink device.
++ struct AVL_DVBSx_Chip
++ {
++ AVL_uint16 m_SlaveAddr; ///< Device I2C slave address.
++ AVL_uint16 m_uiBusId; ///< Bus identifier.
++ AVL_uint16 m_StdBuffIndex; ///< The internal stdout port buffer index.
++ AVL_uint16 m_DemodFrequency_10kHz; ///< The internal demod clock frequency corresponding to the current PLL configuration in units of 10kHz.
++ AVL_uint16 m_FecFrequency_10kHz; ///< The FEC clock frequency corresponding to the current PLL configuration in units of 10kHz.
++ AVL_uint16 m_MpegFrequency_10kHz; ///< The MPEG clock corresponding to the current PLL configuration in units of 10 kHZ.
++ AVL_semaphore m_semRx; ///< A semaphore used to protect the receiver command channel.
++ AVL_semaphore m_semI2CRepeater; ///< A semaphore used to protect the I2C repeater channel.
++ AVL_semaphore m_semI2CRepeater_r; ///< A semaphore used to protect the I2C repeater channel data reading.
++ AVL_semaphore m_semDiseqc; ///< A semaphore used to protect the DiSEqC operations.
++ enum AVL_DVBSx_Diseqc_OPStatus Diseqc_OP_Status; ///< The DiSEqC status. \sa ::AVL_DVBSx_Diseqc_OPStatus.
++ };
++
++ /// Configures the Availink device's PLL. The SDK provides an array of PLL configurations in IBSP.h. The user may remove unused elements in that array to reduce the SDK footprint. Availink advises users to refrain from changing the PLL setup values themselves. Please contact Availink if there is a need to support a PLL configuration not already provided.
++ struct AVL_DVBSx_PllConf
++ {
++ AVL_uint16 m_uiClkf; ///< Feedback clock divider
++ AVL_uint16 m_uiClkr; ///< Reference clock divider
++ AVL_uint16 m_uiPllod; ///< PLL output divider
++ AVL_uint16 m_uiPllod2; ///< PLL output divider 2
++ AVL_uint16 m_uiPllod3; ///< PLL output divider 3
++ AVL_uint16 m_RefFrequency_kHz; ///< Reference clock frequency in units of kHz
++ AVL_uint16 m_DmodFrequency_10kHz; ///< Demod clock frequency in units of 10kHz
++ AVL_uint16 m_FecFrequency_10kHz; ///< FEC clock frequency in units of 10 kHz
++ AVL_uint16 m_MpegFrequency_10kHz; ///< MPEG clock frequency in units of 10 kHz
++ } ;
++
++ /// The structure for storing the version information associated with the Availink device and its associated software. \sa AVL_VerInfo
++ struct AVL_DVBSx_VerInfo
++ {
++ struct AVL_VerInfo m_Chip; ///< Hardware version. Should be 1.0.2.
++ struct AVL_VerInfo m_API; ///< SDK version.
++ struct AVL_VerInfo m_Patch; ///< The version of the firmware patch.
++ } ;
++
++ /// Initializes an ::AVL_DVBSx_Chip object. The user must first define an object of type ::AVL_DVBSx_Chip, and then pass the address of the object to this function. This function initializes semaphores for the object and sets the I2C slave address.
++ ///
++ /// @param pAVL_DVBSx_ChipObject A pointer to the ::AVL_DVBSx_Chip object.
++ /// @param uiSlaveAddress The slave address for the Availink device.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode, Return ::AVL_DVBSx_EC_OK if the initialization is successful.
++ /// @remarks This function initializes the semaphores without any checking. It is the user's responsibility to make sure that each object is initialized only once.
++ AVL_DVBSx_ErrorCode Init_AVL_DVBSx_ChipObject(struct AVL_DVBSx_Chip * pAVL_DVBSx_ChipObject, AVL_uint16 uiSlaveAddress);
++
++ /// Declaration of the global PLL configuration array variable. The variable must be defined in IBSP.c
++ ///
++ extern const struct AVL_DVBSx_PllConf pll_conf[];
++ extern const AVL_uint16 pll_array_size;
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/avlfrontend.h b/drivers/amlogic/dvb_tv/avl6211/include/avlfrontend.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/avlfrontend.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/avlfrontend.h 2014-12-11 16:13:50.149617166 +0100
+@@ -0,0 +1,46 @@
++
++
++
++#ifndef _AVL6211SF_H_
++#define _AVL6211SF_H_
++
++
++
++#include
++#include "../aml_dvb.h"
++
++
++#include "IBSP.h"
++#include "avl_dvbsx.h"
++#include "IBase.h"
++#include "IRx.h"
++#include "II2C.h"
++#include "IDiseqc.h"
++#include "ITuner.h"
++#include "IBlindScan.h"
++#include "IBlindscanAPI.h"
++
++
++#define printf printk
++
++
++struct avl6211_fe_config {
++ int i2c_id;
++ int reset_pin;
++ int demod_addr;
++ int tuner_addr;
++ void *i2c_adapter;
++};
++
++
++struct avl6211_state {
++ struct avl6211_fe_config config;
++ struct i2c_adapter *i2c;
++ u32 freq;
++ fe_modulation_t mode;
++ u32 symbol_rate;
++ struct dvb_frontend fe;
++};
++
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/avl.h b/drivers/amlogic/dvb_tv/avl6211/include/avl.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/avl.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/avl.h 2014-12-11 16:13:50.069617776 +0100
+@@ -0,0 +1,133 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Defines common macros, functions and data structures for all Availink products. This file also declare functions for ensuring the SDK can work in both little endian and big endian target platforms.
++///
++#ifndef avl_h_h
++ #define avl_h_h
++
++ #include "bspdatadef.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ #define AVL_min(x,y) (((x) < (y)) ? (x) : (y))
++ #define AVL_max(x,y) (((x) < (y)) ? (y) : (x))
++ #define AVL_floor(a) (((a) == (int)(a))? ((int)(a)) : (((a) < 0)? ((int)((a)-1)) : ((int)(a))))
++ #define AVL_ceil(a) (((a) == (int)(a))? ((int)(a)) : (((a) < 0)? ((int)(a)) : ((int)((a)+1))))
++ #define AVL_abs(a) (((a)>0) ? (a) : (-(a)))
++ #define AVL_abssub(a,b) ((a>=b)?(a-b):(b-a))
++ #define AVL_CONSTANT_10_TO_THE_9TH 1000000000
++
++ #ifdef AVL_CPLUSPLUS
++ #define AVL_NULL 0
++ #else
++ #define AVL_NULL ((void *)0)
++ #endif
++
++ /// Availink's version structure.
++ struct AVL_VerInfo {
++ AVL_uchar m_Major; ///< The major version
++ AVL_uchar m_Minor; ///< The minor version
++ AVL_uint16 m_Build; ///< The build version
++ };
++
++ /// Stores an unsigned 64-bit integer
++ struct AVL_uint64
++ {
++ AVL_uint32 m_HighWord; ///< The most significant 32-bits of the unsigned 64-bit integer
++ AVL_uint32 m_LowWord; ///< The least significant 32-bits of the unsigned 64-bit integer
++ };
++
++ /// Chunk two bytes \a uidata in to \a pBuff.
++ ///
++ /// @param uidata The input 2 bytes data.
++ /// @param pBuff The destination buffer, at least 2 bytes length.
++ ///
++ /// @remarks This function is used to eliminates the big endian and little endian problem.
++ void Chunk16(AVL_uint16 uidata, AVL_puchar pBuff);
++
++ /// Composes a ::AVL_uint16 from two bytes in a AVL_uchar array.
++ ///
++ /// @param pBuff The buffer has at least 2 bytes data.
++ ///
++ /// @return AVL_uint16
++ /// @remarks This function is used to eliminates the big endian and little endian problem.
++ AVL_uint16 DeChunk16(const AVL_puchar pBuff);
++
++ /// Chunk four bytes \a uidata in to \a pBuff.
++ ///
++ /// @param uidata The input 3 bytes data.
++ /// @param pBuff The destination buffer, at least 3 bytes length.
++ ///
++ /// @remarks This function is used to eliminates the big endian and little endian problem.
++ void Chunk32(AVL_uint32 uidata, AVL_puchar pBuff);
++
++ /// Composes a ::AVL_uint16 from four bytes in a AVL_uchar array.
++ ///
++ /// @param pBuff The buffer has at least 4 bytes data.
++ ///
++ /// @return AVL_uint32
++ /// @remarks This function is used to eliminates the big endian and little endian problem.
++ AVL_uint32 DeChunk32(const AVL_puchar pBuff);
++
++ /// Chunk 3 byte of \a uiaddr into the \a pBuff
++ ///
++ /// @param uiaddr The address. Only the three LSB bytes will be used.
++ /// @param pBuff The destination buffer, at lease three bytes length.
++ ///
++ /// @remarks This function is used to eliminates the big endian and little endian problem.
++ void ChunkAddr(AVL_uint32 uiaddr, AVL_puchar pBuff);
++
++ /// Adds a 32-bit unsigned integer to a 64-bit unsigned integer. Stores the result in a 64-bit unsigned integer.
++ ///
++ /// @param pSum Contains the 64-bit addend. Also carries back the resulting sum.
++ /// @param uiAddend Contains the 32-bit addend.
++ ///
++ /// @remarks This function is an 'internal' function. Availink does not recommend that the user call it directly.
++ void Add32To64(struct AVL_uint64 *pSum, AVL_uint32 uiAddend);
++
++ /// Divides two 64-bit unsigned integers. Stores the result in a 64-bit unsigned integer.
++ ///
++ /// @param divisor Contains the 64-bit divisor.
++ /// @param dividend Contains the 64-bit dividend.
++ ///
++ /// @remarks This function is an 'internal' function. Availink does not recommend that the user call it directly.
++ AVL_uint32 Divide64(struct AVL_uint64 divisor, struct AVL_uint64 dividend);
++
++ /// Multiplies two 32-bit unsigned integers. Stores the result in a 64-bit unsigned integer.
++ ///
++ /// @param pDst Carries back the 64-bit product of the multiplication.
++ /// @param m1 Contains one of the 32-bit factors to be used in the multiplication.
++ /// @param m2 Contains the other 32-bit factor to be used in the multiplication.
++ ///
++ /// @remarks This function is an 'internal' function. Availink does not recommend that the user call it directly.
++ void Multiply32(struct AVL_uint64 *pDst, AVL_uint32 m1, AVL_uint32 m2);
++
++ /// Shifts a 32-bit unsigned integer left by 16 bits and then adds the result to a 64-bit unsigned integer. Stores the sum in a 64-bit unsigned integer.
++ ///
++ /// @param pDst Contains the 64-bit addend. Also carries back the resulting sum.
++ /// @param a Contains the 32-bit input which is shifted and added to the other addend.
++ ///
++ /// @remarks This function is an 'internal' function. Availink does not recommend that the user call it directly.
++ void AddScaled32To64(struct AVL_uint64 *pDst, AVL_uint32 a);
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/BlindScan_source.h b/drivers/amlogic/dvb_tv/avl6211/include/BlindScan_source.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/BlindScan_source.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/BlindScan_source.h 2014-12-11 16:13:50.033618053 +0100
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++
++#ifndef BlindScan_source_h_h
++ #define BlindScan_source_h_h
++
++ #include "avl_dvbsx.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ void AVL_DVBSx_Error_Dispose(AVL_DVBSx_ErrorCode r);
++ AVL_DVBSx_ErrorCode Initialize(struct AVL_DVBSx_Chip * pAVLChip,struct AVL_Tuner * pTuner);
++ AVL_DVBSx_ErrorCode BlindScan(void);
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/bspdatadef.h b/drivers/amlogic/dvb_tv/avl6211/include/bspdatadef.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/bspdatadef.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/bspdatadef.h 2014-12-11 16:13:50.161617073 +0100
+@@ -0,0 +1,52 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Defines the primary data type according the target platform. All data
++/// types defined in this file should be overwritten by Users according to
++/// their own target platform.
++///
++#ifndef bspdatadef_h_h
++#define bspdatadef_h_h
++
++#include
++
++//#define AVL_CPLUSPLUS ///< Used to switch the C++ and C compiler. Comment the macro AVL_CPLUSPLUS if you use C compiler
++
++typedef char AVL_char; ///< 8 bits signed char data type.
++typedef unsigned char AVL_uchar; ///< 8 bits unsigned char data type.
++
++typedef short AVL_int16; ///< 16 bits signed char data type.
++typedef unsigned short AVL_uint16; ///< 16 bits unsigned char data type.
++
++typedef int AVL_int32; ///< 32 bits signed char data type.
++typedef unsigned int AVL_uint32; ///< 32 bits unsigned char data type.
++
++typedef char * AVL_pchar; ///< pointer to a 8 bits signed char data type.
++typedef unsigned char * AVL_puchar; ///< pointer to a 8 bits unsigned char data type.
++
++typedef short * AVL_pint16; ///< pointer to a 16 bits signed char data type.
++typedef unsigned short * AVL_puint16; ///< pointer to a 16 bits unsigned char data type.
++
++typedef int * AVL_pint32; ///< pointer to a 32 bits signed char data type.
++typedef unsigned int * AVL_puint32; ///< pointer to a 32 bits unsigned char data type.
++
++//typedef unsigned char AVL_semaphore; ///< the semaphore data type.
++//typedef unsigned char * AVL_psemaphore; ///< the pointer to a semaphore data type.
++typedef struct semaphore AVL_semaphore;
++typedef struct semaphore *AVL_psemaphore;
++
++#endif
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/DiSEqC_source.h b/drivers/amlogic/dvb_tv/avl6211/include/DiSEqC_source.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/DiSEqC_source.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/DiSEqC_source.h 2014-12-11 16:13:50.061617837 +0100
+@@ -0,0 +1,41 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++
++
++
++#ifndef Diseqc_source_h_h
++ #define Diseqc_source_h_h
++
++ #include "avl_dvbsx.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ void AVL_DVBSx_Error_Dispose(AVL_DVBSx_ErrorCode r);
++ AVL_DVBSx_ErrorCode Initialize(struct AVL_DVBSx_Chip * pAVLChip);
++ AVL_DVBSx_ErrorCode DiSEqC(void);
++ AVL_DVBSx_ErrorCode AVL6211_SetToneOut(AVL_uchar ucTone);
++ void AVL6211_DiseqcSendCmd(AVL_puchar pCmd,AVL_uchar CmdSize);
++ AVL_DVBSx_ErrorCode AVL6211_LNB_PIO_Control(AVL_char nPIN_Index,AVL_char nValue);
++ AVL_DVBSx_ErrorCode AVL6211_22K_Control(AVL_uchar OnOff);
++
++ #define LNB1_PIN_60 60
++ #define LNB0_PIN_59 59
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/ExtSharpBS2S7HZ6306.h b/drivers/amlogic/dvb_tv/avl6211/include/ExtSharpBS2S7HZ6306.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/ExtSharpBS2S7HZ6306.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/ExtSharpBS2S7HZ6306.h 2014-12-11 16:13:50.053617900 +0100
+@@ -0,0 +1,43 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Declare functions for external Sharp BS2S7HZ6306 tuner control
++///
++#ifndef ExtSharpBS2S7HZ6306_h_h
++ #define ExtSharpBS2S7HZ6306_h_h
++
++ #include "avl_dvbsx.h"
++ #include "ITuner.h"
++
++ //Included to support the blind scan fix made to blindscanform.cpp file ae per raptor.
++ #define SHARP_TUNER_FACTOR_VALUE 9
++ #define SHARP_HSYM_ACQ_TH_VALUE 20480
++ #define SHARP_HSYM_CD_TH_VALUE 156
++ //////////////////////////////////////////////////////////////////////////////////////
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_Initialize(struct AVL_Tuner * pTuner);
++ AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_GetLockStatus(struct AVL_Tuner * pTuner );
++ AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_Lock(struct AVL_Tuner * pTuner);
++ AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_Check(struct AVL_Tuner * pTuner);
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/IBase.h b/drivers/amlogic/dvb_tv/avl6211/include/IBase.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/IBase.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/IBase.h 2014-12-11 16:13:50.041617992 +0100
+@@ -0,0 +1,257 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Declares functions for generic device level operations.
++///
++#ifndef IBase_h_h
++ #define IBase_h_h
++
++ #include "avl_dvbsx.h"
++ #include "ITuner.h"
++ #include "avl_dvbsx_globals.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ ///@cond
++ #define core_reset_b_reg 0x600000
++ #define gpio_data_in_to_reg 0x6C0004
++ #define gpio_data_reg_out 0x6C0008
++ #define gpio_reg_enb 0x6C000C
++
++ #define pll_clkr_map_addr 0x6C40C0
++ #define pll_clkf_map_addr 0x6C4100
++ #define pll_od_map_addr 0x6C4080
++ #define pll_od2_map_addr 0x6C4140
++ #define pll_od3_map_addr 0x6C4180
++ #define pll_bwadj_map_addr 0x6C41C0
++ #define pll_softvalue_en_map_addr 0x6C4200
++ #define reset_register_addr 0x6C4000
++
++ #define OP_RX_NOOP 0x00
++ #define OP_RX_LD_DEFAULT 0x01
++ #define OP_RX_INIT_GO 0x02
++ #define OP_RX_RESET_BERPER 0x03
++ #define OP_RX_HALT 0x04
++ #define OP_RX_SLEEP 0x05
++ #define OP_RX_WAKE 0x06
++ #define OP_RX_BLIND_SCAN 0x08
++ #define OP_RX_STDOUT_MODE 0x09
++ ///@endcond
++
++ ///@cond
++ #define AVL_DVBSx_API_VER_MAJOR 0x01
++ #define AVL_DVBSx_API_VER_MINOR 0x00
++ #define AVL_DVBSx_API_VER_BUILD 0x06
++
++ /// @cond
++ /// Configures the PLL.
++ ///
++ /// @param pPLLConf Pointer to the PLL configuration object
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the PLL is being configured.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the PLL configuration has been successfully sent to the Availink device.
++ /// Return ::AVL_DVBSx_I2C_Fail if there is an I2C communication problem
++ /// @remarks This function is an internal SDK function. Availink recommends that users refrain from directly calling this function.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetPLL(const struct AVL_DVBSx_PllConf * pPLLConf, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Downloads the firmware to the Availink device.
++ ///
++ /// @param pInitialData Pointer to the buffer which contains the firmware data.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the firmware is being downloaded.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the firmware download is successful.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function is an internal SDK function. Availink recommends that users refrain from directly calling this function.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_DownloadFirmware(AVL_puchar pFirmwareData, const struct AVL_DVBSx_Chip * pAVLChip);
++
++ ///@endcond
++
++ /// Checks the Availink device status to determine whether initialization is complete.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which initialization status is being checked.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if device initialization is complete.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if device initialization has failed.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetStatus( struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Retrieves the Availink device version information.
++ ///
++ /// @param pVerInfo Pointer to an object in which to store the retrieved version information. Refer to ::AVL_DVBSx_Ver_Info for more details.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the version information is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the version information has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetVersion( struct AVL_DVBSx_VerInfo * pVerInfo, const struct AVL_DVBSx_Chip * pAVLChip ) ;
++
++ /// Initializes the Availink device. This function boots the device.
++ /// The user may call ::AVL_DVBSx_IBase_GetStatus to check the device initialization status.
++ ///
++ /// @param pPLLConf Pointer to the ::AVL_DVBSx_PLLConf object which contains the device PLL settings.
++ /// @param pInitialData Pointer to the buffer which contains the firmware patch data.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object which is being initialized.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the firmware and configuration information has been successfully downloaded to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Initialize( const struct AVL_DVBSx_PllConf * pPLLConf, AVL_puchar pInitialData, struct AVL_DVBSx_Chip * pAVLChip ) ;
++
++ /// Sends an operational command to the Availink device.
++ ///
++ /// @param ucOpCmd The OP_RX_xxx command being sent to the device.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip to which the command is being sent.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the operational command is sent to the device.
++ /// Return ::AVL_DVBSx_EC_Running if the command could not be sent because the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function is an internal SDK function. Availink recommends that users refrain from directly calling this function.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SendRxOP(AVL_uchar ucOpCmd, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Checks if the Availink device has finished processing the last operational command sent to it.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip for which the operational command status is being checked.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has finished processing the last command.
++ /// Return ::AVL_DVBSx_EC_Running if the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function is an internal SDK function. Availink recommends that users refrain from directly calling this function.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetRxOPStatus(const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Halts the Availink device. In halt mode the device does not perform any channel processing.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip which is being halted.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the operational command has been sent to the device.
++ /// Return ::AVL_DVBSx_EC_Running if the command could not be sent because the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Halt( struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Places the Availink device in sleep mode. In sleep mode some device blocks are held in an idle state to reduce power consumption.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip which is being placed in sleep mode.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the operational command has been sent to the device.
++ /// Return ::AVL_DVBSx_EC_Running if the command could not be sent because the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Sleep( struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Wakes the Availink device from sleep mode. Upon waking from sleep, the device enters the halt mode.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip which is being waken from sleep.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the operational command has been sent to the device.
++ /// Return ::AVL_DVBSx_EC_Running if the command could not be sent because the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Wake( struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Sets the device functional mode. The device can be configured for either demod mode or blind scan mode.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip for which the functional mode is being set.
++ /// @param enumFunctionalMode The functional mode into which the device is being placed.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the functional mode has been set.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetFunctionalMode(const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_FunctionalMode enumFunctionalMode);
++
++ /// Checks the current device functional mode. The Availink device can operate in either demodulation mode or blind scan mode.
++ ///
++ /// @param pFunctionalMode Pointer to the ::AVL_DVBSx_FunctionalMode object in which to store the retrieved functional mode.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip for which the functional mode is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the functional mode has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetFunctionalMode(enum AVL_DVBSx_FunctionalMode * pFunctionalMode, const struct AVL_DVBSx_Chip * pAVLChip);
++
++ /// Configures the direction of the GPIO pins.
++ ///
++ /// @param ucDir This is a bitmapped field in which each of the three LSBs controls the direction of a particular GPIO pin. Setting a direction bit to a
++ /// one configures the respective pin as an input, and setting the bit to a zero configures the pin as an output. Bit 0 (the LSB) corresponds to pin CS_0,
++ /// bit 1 corresponds to pin LNB_CNTRL_1, and bit 2 corresponds to pin GPIO_CLK.
++ /// @param pAVLChip A pointer point to the ::AVL_DVBSx_Chip object for which GPIO pin direction is being configured.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the GPIO pin direction is configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetGPIODir( AVL_uchar ucDir, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Sets the voltage level of any GPIO pins that have been configured as outputs.
++ ///
++ /// @param ucVal This is a bitmapped field in which each of the three LSBs controls the voltage level of a particular GPIO pin that has been configured as an
++ /// output. Setting a value bit to a zero drives the corresponding pin low, while setting a value bit to a one, drives the corresponding pin high.
++ /// Bit 0 (the LSB) corresponds to pin CS_0, bit 1 corresponds to pin LNB_CNTRL_1, and bit 2 corresponds to pin GPIO_CLK.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the GPIO pin output voltages are being configured.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the GPIO output pin voltages have been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function only controls the voltage of those GPIO pins that have been configured as outputs. If a GPIO pin has been configured as an input,
++ /// the function has no effect for that pin.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetGPIOVal( AVL_uchar ucVal, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads the voltage level of the GPIO pins.
++ ///
++ /// @param pucVal Pointer to a variable in which to store the GPIO pin voltage levels. This is a bitmapped field in which each of the three LSBs will
++ /// contain the voltage level of a particular GPIO pin. A value bit of zero means that the corresponding pin is low, while a value bit of one, means that
++ /// the corresponding pin is high. Bit 0 (the LSB) corresponds to pin CS_0, bit 1 corresponds to pin LNB_CNTRL_1, and bit 2 corresponds to pin GPIO_CLK.
++ /// The GPIO pin voltage level can be read regardless of whether the pin has been configured as an input or output.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the GPIO pin voltage levels are being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the GPIO pin voltages have been read.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is a I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetGPIOVal( AVL_puchar pucVal, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Checks the Availink device is in sleep status or wake status.
++ ///
++ /// @param pChipStatus Pointer to the AVL_DVBSx_Sleep_Wake_Status object in which to store the retrieved chip status.
++ /// @param pAVLChip Pointer to the AVL_DVBSx_Chip for which the operational command status is being checked.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has finished processing the last command.
++ /// Return ::AVL_DVBSx_EC_Running if the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetChipStatus( enum AVL_DVBSx_Sleep_Wake_Status * pChipStatus, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the device to indicate whether the tuner inverts the received signal spectrum.
++ ///
++ /// @param enumSpectrumPolarity Indicates whether the tuner being used inverts the received signal spectrum.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the spectrum polarity setting is being configured.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the spectrum polarity configuration is successful.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetSpectrumPolarity( enum AVL_DVBSx_SpectrumPolarity enumSpectrumPolarity, const struct AVL_DVBSx_Chip * pAVLChip );
++
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/IBlindscanAPI.h b/drivers/amlogic/dvb_tv/avl6211/include/IBlindscanAPI.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/IBlindscanAPI.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/IBlindscanAPI.h 2014-12-11 16:13:50.161617073 +0100
+@@ -0,0 +1,177 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#ifndef IBlindScanAPI_h_h
++ #define IBlindScanAPI_h_h
++
++ #include "avl_dvbsx.h"
++ #include "ITuner.h"
++ #include "IBlindScan.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ ///
++ /// Defines the status of blind scan process.
++ enum AVL_DVBSx_BlindScanAPI_Status
++ {
++ AVL_DVBSx_BS_Status_Init = 0, ///< = 0 Indicates that the blind scan process is initializing the parameters.
++ AVL_DVBSx_BS_Status_Start = 1, ///< = 1 Indicates that the blind scan process is starting to scan.
++ AVL_DVBSx_BS_Status_Wait = 2, ///< = 2 Indicates that the blind scan process is waiting for the completion of scanning.
++ AVL_DVBSx_BS_Status_Adjust = 3, ///< = 3 Indicates that the blind scan process is reading the channel info which have scanned out.
++ AVL_DVBSx_BS_Status_User_Process = 4, ///< = 4 Indicates that the blind scan process is in custom code. Customer can add the callback function in this stage such as adding TP information to TP list or lock the TP for parsing PSI.
++ AVL_DVBSx_BS_Status_Cancel = 5, ///< = 5 Indicates that the blind scan process is cancelled or the blind scan have completed.
++ AVL_DVBSx_BS_Status_Exit = 6, ///< = 6 Indicates that the blind scan process have ended.
++ AVL_DVBSx_BS_Status_WaitExit = 7
++ };
++
++ ///
++ /// Defines the blind scan mode.
++ enum AVL_DVBSx_BlindScanAPI_Mode
++ {
++ AVL_DVBSx_BS_Fast_Mode = 0, ///< = 0 Indicates that the blind scan frequency step is automatic settings.
++ AVL_DVBSx_BS_Slow_Mode = 1 ///< = 1 Indicates that the blind scan frequency step can be setting by user. The default value is 10MHz.
++ };
++
++ ///
++ /// Stores the blind scan configuration parameters.
++ struct AVL_DVBSx_BlindScanAPI_Setting
++ {
++ AVL_uint16 m_uiScan_Min_Symbolrate_MHz; ///< The minimum symbol rate to be scanned in units of MHz. The minimum value is 1000 kHz.
++ AVL_uint16 m_uiScan_Max_Symbolrate_MHz; ///< The maximum symbol rate to be scanned in units of MHz. The maximum value is 45000 kHz.
++ AVL_uint16 m_uiScan_Start_Freq_MHz; ///< The start scan frequency in units of MHz. The minimum value depends on the tuner specification.
++ AVL_uint16 m_uiScan_Stop_Freq_MHz; ///< The stop scan frequency in units of MHz. The maximum value depends on the tuner specification.
++ AVL_uint16 m_uiScan_Next_Freq_100KHz; ///< The start frequency of the next scan in units of 100kHz.
++ AVL_uint16 m_uiScan_Progress_Per; ///< The percentage completion of the blind scan process. A value of 100 indicates that the blind scan is finished.
++ AVL_uint16 m_uiScan_Bind_No; ///< The number of completion of the blind scan procedure.
++ AVL_uint16 m_uiTuner_MaxLPF_100kHz; ///< The max low pass filter bandwidth of the tuner.
++ AVL_uint16 m_uiScan_Center_Freq_Step_100KHz; ///< The blind scan frequency step. The value is only valid when BS_Mode set to AVL_DVBSx_BS_Slow_Mode and would be ignored when BS_Mode set to AVL_DVBSx_BS_Fast_Mode.
++ enum AVL_DVBSx_BlindScanAPI_Mode BS_Mode; ///< The blind scan mode. \sa ::AVL_DVBSx_IBlindScanAPI_Mode.
++ AVL_uint16 m_uiScaning; ///< whether in blindscan progress.
++
++ AVL_uint16 m_uiChannelCount; ///< The number of channels detected thus far by the blind scan operation. The Availink device can store up to 120 detected channels.
++ struct AVL_DVBSx_Channel channels[128]; ///< Stores the channel information that all scan out results.
++ struct AVL_DVBSx_Channel channels_Temp[16]; ///< Stores the channel information temporarily that scan out results by the blind scan procedure.
++
++ struct AVL_DVBSx_BlindScanPara bsPara; ///< Stores the blind scan parameters each blind scan procedure.
++ struct AVL_DVBSx_BlindScanInfo bsInfo; ///< Stores the blind scan status information each blind scan procedure.
++ enum AVL_DVBSx_SpectrumPolarity m_eSpectrumMode; ///< Defines the device spectrum polarity setting. \sa ::AVL_DVBSx_SpectrumPolarity.
++ };
++
++ /// Initializes the blind scan parameters.
++ ///
++ /// @param pBSsetting A pointer to the blind scan configuration parameters.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK after all the member of the pBSsetting is configured with the default value.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Initialize(struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting );
++
++ /// Configures the device to indicate whether the tuner inverts the received signal spectrum.
++ ///
++ /// @param pBSsetting A pointer to the ::AVL_DVBSx_IBlindScanAPI_Setting object for which the spectrum polarity is being configured.
++ /// @param SpectrumMode Indicates whether the tuner inverts the received signal spectrum.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK after the spectrum polarity is configured with the desired value.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetSpectrumMode(struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting, enum AVL_DVBSx_SpectrumPolarity SpectrumMode);
++
++ /// Sets the blind scan mode.
++ ///
++ /// @param pBSsetting A Pointer to the ::AVL_DVBSx_IBlindScanAPI_Setting for which the blind scan mode is being retrieved.
++ /// @param Scan_Mode The blind scan mode on which the device is being placed.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK after the blind scan mode has been retrieved.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetScanMode(struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting, enum AVL_DVBSx_BlindScanAPI_Mode Scan_Mode);
++
++ /// Sets the start frequency and stop frequency.
++ ///
++ /// @param pBSsetting A Pointer to the ::AVL_DVBSx_IBlindScanAPI_Setting for which the frequency range is being retrieved.
++ /// @param StartFreq_MHz The start scan frequency in units of MHz.
++ /// @param EndFreq_MHz The stop scan frequency in units of MHz.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK after the frequency range has been retrieved.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetFreqRange(struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting, AVL_uint16 StartFreq_MHz, AVL_uint16 EndFreq_MHz );
++
++ /// Sets the max low pass filter bandwidth of the tuner.
++ ///
++ /// @param pBSsetting A Pointer to the ::AVL_DVBSx_IBlindScanAPI_Setting for which the max LPF is being retrieved.
++ /// @param MaxLPF The tuner LPF bandwidth setting in units of 100 kHz.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK after the max LPF has been retrieved.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetMaxLPF(struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting, AVL_uint16 MaxLPF );
++
++ /// Performs a blind scan operation. Call the function ::AVL_DVBSx_IBlindScan_GetScanStatus to check the status of the blind scan operation.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object on which blind scan is being performed.
++ /// @param pTuner A Pointer to the ::AVL_Tuner object on which to lock tuner at a proper frequency point.
++ /// @param pBSsetting A Pointer to blind scan configuration parameters.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the scan command is successfully sent to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the scan command could not be sent because the Availink device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if the device is not in the blind scan functional mode or the parameters are wrong.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Start(struct AVL_DVBSx_Chip *pAVLChip, struct AVL_Tuner *pTuner, struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting );
++
++ /// Queries the blind scan status.
++ ///
++ /// @param pAVLChip A pointer to Pointer to the ::AVL_DVBSx_Chip object for which the blind scan status is being queried.
++ /// @param pBSsetting A Pointer to a variable in which to store the blind scan status.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the blind scan status has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the scan command could not be sent because the Availink device is still processing a previous command.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_GetCurrentScanStatus(struct AVL_DVBSx_Chip *pAVLChip ,struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting );
++
++ /// Reads the channels found during a particular scan from the firmware and stores the new channels found in the scan and filters out the duplicate ones.
++ ///
++ /// @param pAVLChip A pointer to the AVL_DVBSx_Chip object on which read channel operation is being performed.
++ /// @param pBSsetting A pointer to a structure that stores the new channels found in the scan.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the blind scan status has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Adjust(struct AVL_DVBSx_Chip *pAVLChip ,struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting );
++
++ /// Stops blind scan process.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object on which blind scan is being stopped.
++ /// @param pBSsetting A Pointer to blind scan configuration parameters.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the functional mode has been set.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Exit(struct AVL_DVBSx_Chip * pAVLChip, struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting);
++
++ /// Gets the progress of blind scan process based on current scan step's start frequency.
++ ///
++ /// @param pBSsetting A pointer to the ::AVL_DVBSx_IBlindScanAPI_Setting object for which store the blind scan process.
++ ///
++ /// @return ::AVL_uint16,
++ /// Return ::The progress of blind scan process based on current scan step's start frequency.
++ AVL_uint16 AVL_DVBSx_IBlindscanAPI_GetProgress(struct AVL_DVBSx_BlindScanAPI_Setting *pBSsetting );
++
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
++
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/IBlindScan.h b/drivers/amlogic/dvb_tv/avl6211/include/IBlindScan.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/IBlindScan.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/IBlindScan.h 2014-12-11 16:13:50.061617837 +0100
+@@ -0,0 +1,118 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Declares functions for blind scan.
++///
++/// @details The Availink device can store up to 120 detected carrier channels.
++/// If more than 120 channels are detected in the scan range, the function ::AVL_DVBSx_IBlindScan_GetScanStatus will
++/// set ::AVL_DVBSx_BlindScanPara.m_uiResultCode to 1.
++/// The user can read blind scan results with the function ::AVL_DVBSx_IBlindScan_ReadChannelInfo.
++///
++#ifndef IBlindScan_h_h
++ #define IBlindScan_h_h
++
++ #include "avl_dvbsx.h"
++ #include "ITuner.h"
++ #include "avl_dvbsx_globals.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ ///@cond
++
++ /// @endcond
++
++ /// Stores the blind scan parameters which are passed to the ::AVL_DVBSx_IBlindScan_Scan function.
++ struct AVL_DVBSx_BlindScanPara
++ {
++ AVL_uint16 m_uiStartFreq_100kHz; ///< The start scan frequency in units of 100kHz. The minimum value depends on the tuner specification.
++ AVL_uint16 m_uiStopFreq_100kHz; ///< The stop scan frequency in units of 100kHz. The maximum value depends on the tuner specification.
++ AVL_uint16 m_uiMinSymRate_kHz; ///< The minimum symbol rate to be scanned in units of kHz. The minimum value is 1000 kHz.
++ AVL_uint16 m_uiMaxSymRate_kHz; ///< The maximum symbol rate to be scanned in units of kHz. The maximum value is 45000 kHz.
++ };
++
++ /// Stores the blind scan status information.
++ struct AVL_DVBSx_BlindScanInfo
++ {
++ AVL_uint16 m_uiProgress; ///< The percentage completion of the blind scan procedure. A value of 100 indicates that the blind scan is finished.
++ AVL_uint16 m_uiChannelCount; ///< The number of channels detected thus far by the blind scan operation. The Availink device can store up to 120 detected channels.
++ AVL_uint16 m_uiNextStartFreq_100kHz; ///< The start frequency of the next scan in units of 100kHz.
++ AVL_uint16 m_uiResultCode; ///< The result of the blind scan operation. Possible values are: 0 - blind scan operation normal; 1 -- more than 120 channels have been detected.
++ };
++
++ /// Performs a blind scan operation. Call the function ::AVL_DVBSx_IBlindScan_GetScanStatus to check the status of the blind scan operation.
++ ///
++ /// @param pBSPara A pointer to the blind scan configuration parameters.
++ /// @param uiTumerLPF_100kHz The tuner LPF bandwidth setting in units of 100 kHz.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object on which blind scan is being performed.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the scan command is successfully sent to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the scan command could not be sent because the Availink device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if the device is not in the blind scan functional mode or if the parameter \a pBSPara->m_uiStartFreq_100kHz is larger than the parameter \a pBSPara->m_uiStopFreq_100kHz
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_Scan(struct AVL_DVBSx_BlindScanPara * pBSPara, AVL_uint16 uiTunerLPF_100kHz, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Queries the blind scan status.
++ ///
++ /// @param pBSInfo Pointer to the object in which the blind scan status is to be stored.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the blind scan status is being queried.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the blind scan status has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_GetScanStatus(struct AVL_DVBSx_BlindScanInfo * pBSInfo, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Cancels the current blind scan operation.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the blind scan operation is being canceled.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the Availink device has been commanded to cancel the blind scan operation.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the blind scan could not be canceled because the device is still processing a previous command.
++ /// @remarks This function sends a cancel command to the Availink device. The internal scan is not be canceled until the current scan section is finished.
++ /// Call ::AVL_DVBSx_IBase_GetRxOPStatus to determine when the scan cancellation is complete.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_Cancel(struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Retrieves the blind scan results.
++ ///
++ /// @param uiStartIndex The blind scan results are stored in an array internal to the Availink device. This parameter tells the function the array index at which to retrieve the results.
++ /// @param pChannelCount The number of channel results to be retrieved. The function updates this value with the actual number of channel results that are reported.
++ /// @param pChannel Pointer to an object in which the blind scan results are to be stored.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the blind scan results are being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the blind scan results have been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks The scan results internal to the Availink device are overwritten after a subsequent call to the ::AVL_DVBSx_IBlindScan_Reset function. Be sure to read out all of the channel information before calling ::AVL_DVBSx_IBlindScan_Reset.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_ReadChannelInfo(AVL_uint16 uiStartIndex, AVL_puint16 pChannelCount, struct AVL_DVBSx_Channel * pChannel, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Resets the Availink device internal blind scan results.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the internal blind scan results are being reset.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the reset operation is successful.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_Reset( const struct AVL_DVBSx_Chip * pAVLChip );
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/IBSP.h b/drivers/amlogic/dvb_tv/avl6211/include/IBSP.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/IBSP.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/IBSP.h 2014-12-11 16:13:50.045617961 +0100
+@@ -0,0 +1,115 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Defines the BSP functions which the user needs to implement.
++/// @details These BSP functions are called by SDK API functions. This file also defines some hardware related macros which also need to be
++/// customized by the user according to their hardware platform. Most of the functions declared here should
++/// NOT be directly called by the user's applications explicitly. There are two exceptions. These are ::AVL_DVBSx_IBSP_Initialize and ::AVL_DVBSx_IBSP_Dispose.
++///
++#ifndef IBSP_h_h
++ #define IBSP_h_h
++
++ #include "avl_dvbsx.h"
++ #include
++ #include "avlfrontend.h"
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ #define MAX_II2C_READ_SIZE 64 ///< The maximum number of bytes the back end chip can handle in a single I2C read operation. This value must >= 2.
++ #define MAX_II2C_Write_SIZE 64 ///< The maximum number of bytes the back end chip can handle in a single I2C write operation. This value must >= 8.
++
++
++ /// Performs initialization for BSP operations.
++ ///
++ /// @remarks This function should never called inside the SDK. The user can redeclare this function to any prototype.
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK Returned by the function stub provided with the SDK.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_Initialize(void);
++
++ /// Destroys all resources allocated in AVL_DVBSx_IBSP_Initialize and other BSP operations.
++ ///
++ /// @remarks This function should never called inside the SDK. The user can redeclare this function to any prototype.
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK Returned by the function stub provided with the SDK.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_Dispose(void);
++
++ /// Implements a delay in units of milliseconds.
++ ///
++ /// @param uiMS: The delay period in units of milliseconds.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK Returned by the function stub provided with the SDK.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_Delay( AVL_uint32 uiMS );
++
++ /// Performs an I2C read operation.
++ ///
++ /// @param pAVLChip Pointer to the Availink device for which the read operation is being performed.
++ /// @param pucBuff Pointer to a buffer in which to place the read data.
++ /// @param puiSize The number of bytes to be read. The function updates this value with the number of bytes actually read. If there is an error, the function sets this value to 0.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the read operation is successful.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function should perform a direct I2C read operation without first writing the device internal address. The Availink SDK automatically handles writing the device internal address prior to performing the read operation.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_I2CRead( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_puint16 puiSize );
++
++ /// Performs an I2C write operation.
++ ///
++ /// @param pAVLChip Pointer to the Availink device for which the write operation is being performed.
++ /// @param pucBuff Pointer to a buffer which contains the data to be written.
++ /// @param puiSize The number of bytes to be written. The function updates this value with the number of bytes actually written. If there is an error, the function sets this value to 0.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the write operation is successful.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_I2CWrite( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_puint16 puiSize );
++
++ /// Initializes a semaphore object.
++ ///
++ /// @param pSemaphore A pointer to the ::AVL_semaphore object to be initialized.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK Returned by the function stub provided with the SDK.
++ /// @remarks All of the semaphore objects should be initialized with 1 as maximum count and the initialized state should be signaled. In particular, after initialization, the first query should succeed.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_InitSemaphore( AVL_psemaphore pSemaphore );
++
++ /// Queries the semaphore. If the semaphore is held by another thread, the function should be blocked until the semaphore is available.
++ ///
++ /// @param pSemaphore A pointer to the ::AVL_semaphore object being queried.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK Returned by the function stub provided with the SDK.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_WaitSemaphore( AVL_psemaphore pSemaphore );
++
++ /// Releases the semaphore so that it is available.
++ ///
++ /// @param pSemaphore A pointer to the ::AVL_semaphore object which is being released.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK Returned by the function stub provided with the SDK.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_ReleaseSemaphore( AVL_psemaphore pSemaphore );
++
++
++ extern AVL_int32 I2CWrite(AVL_uchar I2CSlaveAddr, AVL_uchar *data, AVL_int32 length,int iDeviceId);
++
++
++ extern AVL_int32 I2CRead(AVL_uchar I2CSlaveAddr, AVL_uchar *data, AVL_int32 length,int iDeviceId);
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/IDiseqc.h b/drivers/amlogic/dvb_tv/avl6211/include/IDiseqc.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/IDiseqc.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/IDiseqc.h 2014-12-11 16:13:50.097617561 +0100
+@@ -0,0 +1,252 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Declares the functions for DiSEqC operations.
++/// @details There are some limitations of the DiSEqC operation. First, it is a half duplex bus. You cannot send and receive data simultaneously. Second, the maximum size of each transmission is 8 bytes.
++/// The DiSEqC interface can operate in different modes such as modulation mode, tone mode and continuous mode. There are functions corresponding to these modes. If the user changes the operating mode by calling functions
++/// which belong to another mode, the previous operation will be cancelled if it has not finished yet.
++///
++#ifndef IDiseqc_h_h
++ #define IDiseqc_h_h
++
++ #include "avl_dvbsx.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ ///@cond
++
++ #define diseqc_tx_cntrl_addr 0x00700000
++ #define diseqc_tone_frac_n_addr 0x00700004
++ #define diseqc_tone_frac_d_addr 0x00700008
++ #define diseqc_tx_st_addr 0x0070000c
++ #define diseqc_rx_parity_addr 0x00700010
++ #define diseqc_rx_msg_tim_addr 0x00700014
++ #define diseqc_rx_st_addr 0x00700018
++ #define diseqc_rx_cntrl_addr 0x0070001c
++ #define diseqc_srst_addr 0x00700020
++ #define diseqc_bit_time_addr 0x00700024
++ #define diseqc_samp_frac_n_addr 0x00700028
++ #define diseqc_samp_frac_d_addr 0x0070002c
++ #define diseqc_bit_decode_range_addr 0x00700030
++ #define diseqc_rx_fifo_map_addr 0x00700040
++ #define diseqc_tx_fifo_map_addr 0x00700080
++
++ ///@endcond
++
++ ///
++ /// When transmitting data in Tone0 or Tone1 mode, there is a gap between two tones. This enumeration defines the gap length.
++ enum AVL_DVBSx_Diseqc_TxGap
++ {
++ AVL_DVBSx_DTXG_15ms = 0, ///< = 0 The gap is 15 ms.
++ AVL_DVBSx_DTXG_20ms = 1, ///< = 1 The gap is 20 ms.
++ AVL_DVBSx_DTXG_25ms = 2, ///< = 2 The gap is 25 ms.
++ AVL_DVBSx_DTXG_30ms = 3 ///< = 3 The gap is 30 ms.
++ };
++
++ ///
++ /// Defines the transmit mode.
++ enum AVL_DVBSx_Diseqc_TxMode
++ {
++ AVL_DVBSx_DTM_Modulation = 0, ///< = 0 Use modulation mode.
++ AVL_DVBSx_DTM_Tone0 = 1, ///< = 1 Send out tone 0.
++ AVL_DVBSx_DTM_Tone1 = 2, ///< = 2 Send out tone 1.
++ AVL_DVBSx_DTM_Continuous = 3 ///< = 3 Continuously send out pulses.
++ };
++
++ ///
++ /// Configures the DiSEqC output waveform mode.
++ enum AVL_DVBSx_Diseqc_WaveFormMode
++ {
++ AVL_DVBSx_DWM_Normal = 0, ///< = 0 Normal waveform mode
++ AVL_DVBSx_DWM_Envelope = 1 ///< = 1 Envelope waveform mode
++ };
++
++ ///
++ /// After data is transmitted to the DiSEqC device, the DiSEqC device may return some data.
++ /// This enumeration controls the amount of time for which the Availink device will open the DiSEqC input FIFO to receive the data. Data that
++ /// is received outside of this time frame is abandoned.
++ enum AVL_DVBSx_Diseqc_RxTime
++ {
++ AVL_DVBSx_DRT_150ms = 0, ///< = 0 Wait 150 ms for receive data and then close the input FIFO.
++ AVL_DVBSx_DRT_170ms = 1, ///< = 1 Wait 170 ms for receive data and then close the input FIFO.
++ AVL_DVBSx_DRT_190ms = 2, ///< = 2 Wait 190 ms for receive data and then close the input FIFO.
++ AVL_DVBSx_DRT_210ms = 3 ///< = 3 Wait 210 ms for receive data and then close the input FIFO.
++ };
++
++ /// Stores the DiSEqC configuration parameters.
++ ///
++ struct AVL_DVBSx_Diseqc_Para
++ {
++ AVL_uint16 m_ToneFrequency_kHz; ///< The DiSEqC bus speed in units of kHz. Normally, it is 22kHz.
++ enum AVL_DVBSx_Diseqc_TxGap m_TXGap; ///< Transmit gap
++ enum AVL_DVBSx_Diseqc_WaveFormMode m_TxWaveForm; ///< Transmit waveform format
++ enum AVL_DVBSx_Diseqc_RxTime m_RxTimeout; ///< Receive time frame window
++ enum AVL_DVBSx_Diseqc_WaveFormMode m_RxWaveForm; ///< Receive waveform format
++ };
++
++ /// Stores the DiSEqC transmitter status.
++ ///
++ struct AVL_DVBSx_Diseqc_TxStatus
++ {
++ AVL_uchar m_TxDone; ///< Indicates whether the transmission is complete (1 - transmission is finished, 0 - transmission is still in progress).
++ AVL_uchar m_TxFifoCount; ///< The number of bytes remaining in the transmit FIFO
++ };
++
++ /// Stores the DiSEqC receiver status
++ ///
++ struct AVL_DVBSx_Diseqc_RxStatus
++ {
++ AVL_uchar m_RxFifoCount; ///< The number of bytes in the DiSEqC receive FIFO.
++ AVL_uchar m_RxFifoParChk; ///< The parity check result of the received data. This is a bit-mapped field in which each bit represents the parity check result for each each byte in the receive FIFO. The upper bits without corresponding data are undefined. If a bit is 1, the corresponding byte in the FIFO has good parity. For example, if three bytes are in the FIFO, and the parity check value is 0x03 (value of bit 2 is zero), then the first and the second bytes in the receive FIFO are good. The third byte had bad parity.
++ AVL_uchar m_RxDone; ///< 1 if the receiver window is turned off, 0 if it is still in receiving state.
++ };
++
++ /// Initializes the DiSEqC component using the configuration parameters in \a pDiseqcPara.
++ ///
++ /// @param pDiseqcPara Pointer to the DiSEqC configuration parameters.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the DiSEqC interface is being initialized.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the DiSEqC interface has been initialized.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_Initialize( const struct AVL_DVBSx_Diseqc_Para * pDiseqcPara, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads data from the DiSEqC input FIFO.
++ ///
++ /// @param pucBuff Pointer to a buffer in which the read data should be stored.
++ /// @param pucSize The number of bytes to read from the FIFO. The maximum value is 8. The function updates this parameter to indicate the number of bytes that have actually been read.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the DiSEqC input FIFO is being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the DiSEqC input FIFO has been read.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if the DiSEqC interface is not in modulation mode or if the DiSEqC interface is still receiving the data.
++ /// @remarks Availink recommends that the user call ::AVL_DVBSx_IDiseqc_GetRxStatus before calling this function.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_ReadModulationData( AVL_puchar pucBuff, AVL_puchar pucSize, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Sends data to the DiSEqC bus.
++ ///
++ /// @param pucBuff Pointer to an array which contains the data to be sent to the DiSEqC bus.
++ /// @param ucSize The number of bytes to be sent. The maximum is 8.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which data is to be sent to the DiSEqC bus.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been sent
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if it is not safe to switch the DiSEqC mode because the last transmission is not complete yet.
++ /// Return ::AVL_DVBSx_EC_MemoryRunout if \aucSize is larger than 8.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SendModulationData( const AVL_puchar pucBuff, AVL_uchar ucSize, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Checks the current status of the DiSEqC transmitter.
++ ///
++ /// @param pTxStatus Pointer to an object in which to store the DiSEqC transmitter status.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the transmit status is being checked.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the transmit status has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetTxStatus( struct AVL_DVBSx_Diseqc_TxStatus * pTxStatus, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Checks the current status of the DiSEqC receiver.
++ ///
++ /// @param pRxStatus Pointer to an object in which to store the DiSEqC receiver status information.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the receiver status is being checked.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the receiver status has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if the DiSEqC component is not in modulation mode.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetRxStatus( struct AVL_DVBSx_Diseqc_RxStatus * pRxStatus, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Sets the output level of pin LNB_CNTRL_0. This pin is typically used to control LNB polarization.
++ ///
++ /// @param uiOut Controls the level of pin LNB_CNTRL_0 (0 - Set output level low, 1 - Set output level high).
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the output level of pin LNB_CNTRL_0 is being set.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the pin level has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SetLNBOut( AVL_uchar uiOut, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Gets the output level of pin LNB_CNTRL_0.
++ ///
++ /// @param puiOut Pointer to a variable in which to store the pin output level (0 - Output level is low, 1 - Output level is high).
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the pin output level is being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the pin level has been read.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetLNBOut( AVL_puchar puiOut, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the device to transmit the DiSEqC Tone.
++ ///
++ /// @param ucTone Configures the tone to be transmitted (0 - Tone_0, 1 - Tone_1).
++ /// @param ucCount The number of tones to be transmitted. The maximum value is 8.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object which is being configured to transmit the tones.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has been configured to transmit the DiSEqC tones.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_MemoryRunout if \aucCount is larger than 8.
++ /// Return ::AVL_DVBSx_EC_Running if it is not safe to switch the DiSEqC mode because the last transmission is not complete.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SendTone( AVL_uchar ucTone, AVL_uchar ucCount, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the device to output a continuous 22kHz DiSEqC waveform.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object which is being configured to output the waveform.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has been configured to transmit the waveform.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if it is not safe to switch the DiSEqC mode because the last transmission is not complete.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_StartContinuous (struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the device to stop outputting a continuous 22kHz DiSEqC waveform.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object which is being configured to stop outputting the waveform.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has been configured to stop transmitting the waveform.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_StopContinuous (struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Sets the output level of pin LNB_CNTRL_1. This pin is also can used to control LNB polarization.
++ ///
++ /// @param uiOut Controls the level of pin LNB_CNTRL_1 (0 - Set output level low, 1 - Set output level high).
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the output level of pin LNB_CNTRL_1 is being set.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the pin level has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SetLNB1Out( AVL_uchar uiOut, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Gets the output level of pin LNB_CNTRL_1.
++ ///
++ /// @param puiOut Pointer to a variable in which to store the pin output level (0 - Output level is low, 1 - Output level is high).
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the pin output level is being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the pin level has been read.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetLNB1Out( AVL_puchar puiOut, struct AVL_DVBSx_Chip * pAVLChip );
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/II2C.h b/drivers/amlogic/dvb_tv/avl6211/include/II2C.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/II2C.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/II2C.h 2014-12-11 16:13:50.125617349 +0100
+@@ -0,0 +1,132 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///@file
++///@brief This interface provides functions for performing atomic I2C operations.
++///@details The user should always use the functions provided in this file to perform I2C operations. These functions provide
++/// multi_thread protection and they automatically break potentially large I2C transactions into smaller I2C transactions to
++/// meet the hardware limitations defined in the BSP.
++/// These functions also eliminate the difference between the big endian and little endian systems. Please note that
++/// these I2C functions can only be used to perform I2C operations with the Availink device. When reading and writing data from and to
++/// the Availink device, all data is treated as unsigned data. The user needs to cast data properly to get desired values.
++///
++#ifndef II2C_h_h
++ #define II2C_h_h
++
++ #include "avl_dvbsx.h"
++ #include "avl_dvbsx_globals.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ /// @cond
++
++ /// Initializes I2C operation.
++ ///
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if I2C functionality has been initialized.
++ /// Return ::AVL_DVBSx_EC_MemoryRunout if the semaphores cannot be initialized.
++ /// @remarks This is an internal SDK function. This function must be called before any I2C operations. The user does not need to worry about calling this function directly because it is called by the SDK function ::InitAVL_DVBSx_ChipObject.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Initialize(void);
++
++ /// @endcond
++
++ /// This function reads one or more bytes from the Availink device. The bytes are read from the device internal address specified by the user.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the read operation is being performed.
++ /// @param uiOffset The Availink device internal address from where the function is to read data.
++ /// @param pucBuff Pointer to a buffer in which to store the read data.
++ /// @param uiSize The number of bytes to read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been read from the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks The function first performs an I2C write operation to send the read address to the Availink device.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Read( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiOffset, AVL_puchar pucBuff, AVL_uint16 uiSize);
++
++ /// Reads one or more bytes from the Availink device at the current address.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the read operation is being performed.
++ /// @param pucBuff Pointer to a buffer in which to store the read data.
++ /// @param uiSize The number of bytes to read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been read from the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks The function will directly performs an I2C read operation.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_ReadDirect( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_uint16 uiSize);
++
++ /// This function writes one or more bytes to the Availink device.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object to which data is to be written.
++ /// @param pucBuff Pointer to a buffer which contains the data to be written.
++ /// @param uiSize The number of bytes to be written. The minimum permissible value is 3.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been written to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if uiSize is less than 3.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Write( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_uint16 uiSize);
++
++ /// Reads a 16-bit unsigned integer from the Availink device.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object from which data is being read.
++ /// @param uiAddr The Availink device internal address from where the data is to be read.
++ /// @param puiData Pointer to a variable in which to store the read data.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been read from the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Read16( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_puint16 puiData );
++
++ /// Reads a 32-bit unsigned integer from the Availink device.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object from which data is being read.
++ /// @param uiAddr The Availink device internal address from where the data is to be read.
++ /// @param puiData Pointer to a variable in which to store the read data.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been read from the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Read32( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_puint32 puiData );
++
++ /// Writes a 16-bit unsigned integer to the Availink device.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object to which data is being written.
++ /// @param uiAddr The Availink device internal address to which the data is to be written.
++ /// @param uiData The data to be written to the Availink device.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been written to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Write16( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_uint16 uiData );
++
++ /// Writes a 32-bit unsigned integer to the Availink device.
++ ///
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object to which the data is being written.
++ /// @param uiAddr The Availink device internal address to which the data is to be written.
++ /// @param uiData The data to be written to the Availink device.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been written to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Write32( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_uint32 uiData );
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/II2CRepeater.h b/drivers/amlogic/dvb_tv/avl6211/include/II2CRepeater.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/II2CRepeater.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/II2CRepeater.h 2014-12-11 16:13:50.077617717 +0100
+@@ -0,0 +1,134 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Defines functions for initializing and controlling the I2C repeater.
++/// @details The I2C repeater provides a dedicated I2C bus for tuner control. It is
++/// recommended that the functions in this interface be used to implement a tuner
++/// driver for the tuner being used. For customer convenience, Availink provides tested
++/// tuner drivers for a variety tuner devices.
++///
++#ifndef II2CRepeater_h_h
++ #define II2CRepeater_h_h
++
++ #include "avl_dvbsx.h"
++ #include "avl_dvbsx_globals.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ ///@cond
++
++ #define I2CM_CMD_LENGTH 0x14
++ #define I2CM_RSP_LENGTH 0x14
++
++ #define OP_I2CM_NOOP 0x00
++ #define OP_I2CM_INIT 0x01
++ #define OP_I2CM_WRITE 0x02
++ #define OP_I2CM_READ 0x03
++
++ ///@endcond
++
++ ///@cond
++
++ /// Sends an I2C repeater operational command to the Availink device.
++ ///
++ /// @param pBuff Pointer to the array which contains the operational command and its parameters.
++ /// @param ucSize The number of command related bytes in the array to which pBuff points.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object to which an I2C repeater operational command is being sent.
++ ///
++ /// Return ::AVL_DVBSx_EC_OK if the I2C repeater operational command has been sent to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the command could not be sent to the Availink device because the device is still processing a previous command.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_SendOP(AVL_puchar pBuff, AVL_uchar ucSize, struct AVL_DVBSx_Chip * pAVLChip );
++
++ ///@endcond
++
++ /// Initializes the I2C repeater.
++ ///
++ /// @param I2CBusClock_kHz The clock speed of the I2C bus between the tuner and the Availink device.
++ /// @param pAVLChip A pointer to a ::AVL_DVBSx_Chip object for which the I2C repeater is being initialized.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the initialize command has been sent to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the initialize command could not be sent to the Availink device because the device is still processing a previous command.
++ /// @remarks This function must be called before any other function in this interface. This is a nonblocking function. Call ::AVL_DVBSx_II2CRepeater_GetOPStatus to determine if the I2C repeater is initialized.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_Initialize( AVL_uint16 I2CBusClock_kHz, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads data back from the tuner via the I2C repeater. This function is used with tuners which insert a stop
++ /// bit between messages.
++ ///
++ /// @param ucSlaveAddr The slave address of the tuner device. Please note that the Availink device only supports a 7 bit slave address.
++ /// @param pucBuff Pointer to a buffer in which to store the data read from the tuner.
++ /// @param uiSize The number of bytes to read from the tuner. The maximum value is 20.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which data is being read from the tuner.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been read from the tuner.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the read command could not be sent to the Availink device because the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if \a uiSize is larger than 20.
++ /// @remarks This function will trigger a I2C read operation. It is used with tuners which insert a stop bit between messages. The read position (or device internal address) can be determined by calling ::AVL_DVBSx_II2CRepeater_SendData.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_ReadData( AVL_uchar ucSlaveAddr, AVL_puchar pucBuff, AVL_uint16 uiSize, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads data back from the tuner via the I2C repeater. This function is used with tuners which do not insert a stop
++ /// bit between messages.
++ ///
++ /// @param ucSlaveAddr The slave address of the tuner device. Please note that the Availink device only supports a 7 bit slave address.
++ /// @param pucBuff Pointer to the buffer in which to store the read data.
++ /// @param ucRegAddr The address of the register being read.
++ /// @param uiSize The number of bytes to read from the tuner. The maximum value is 20.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which data is being read from the tuner.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the data has been read from the tuner.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the read command could not be sent to the Availink device because the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if \a uiSize is larger than 20.
++ /// @remarks This function will trigger a I2C read operation. It is used with tuners which do not insert a stop bit between messages.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_ReadData_Multi( AVL_uchar ucSlaveAddr, AVL_puchar pucBuff, AVL_uchar ucRegAddr, AVL_uint16 uiSize, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Writes data to the tuner via the I2C repeater.
++ ///
++ /// @param ucSlaveAddr The slave address of the tuner device. Please note that the Availink device only supports a 7 bit slave address.
++ /// @param ucBuff Pointer to the buffer which contains the data to be sent to the tuner.
++ /// @param uiSize The number of bytes to be sent to the tuner. The maximum value is 17.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which data is being sent to the tuner.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the send command has been sent to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the send command could not be sent to the Availink device because the device is still processing a previous command.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if \a uiSize is larger than 17.
++ /// @remarks The internal register address is buried in the buffer to which \a ucBuff points. This function is a nonblocking function. Call ::AVL_DVBSx_II2CRepeater_GetOPStatus to determine if the write operation is complete.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_SendData( AVL_uchar ucSlaveAddr, const AVL_puchar ucBuff, AVL_uint16 uiSize, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Checks if the last I2C repeater operation is finished.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which I2C repeater operation status is being queried.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the last I2C repeater operation is complete.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the Availink device is still processing the last I2C repeater operation.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_GetOPStatus(const struct AVL_DVBSx_Chip * pAVLChip );
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/IRx.h b/drivers/amlogic/dvb_tv/avl6211/include/IRx.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/IRx.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/IRx.h 2014-12-11 16:13:50.041617992 +0100
+@@ -0,0 +1,462 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Declares functions for the receiver component.
++/// @details Although the user may call these functions from multiple threads, Availink recommends that all
++/// "control" functions be called from a single thread to avoid confusion.
++///
++#ifndef IRx_h_h
++ #define IRx_h_h
++
++ #include "avl_dvbsx.h"
++ #include "avl_dvbsx_globals.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ /// @cond
++ #define rx_aagc_gain 0x0040004C
++ #define rx_Rolloff_addr 0x00400030
++ #define scatter_data_addr 0x00001AD8
++ #define rc_mpeg_bus_tri_enb 0x006C0028
++ #define rc_mpeg_bus_pe 0x006C0038
++ #define rc_rfagc_tri_enb 0x006C002C
++ #define rc_spare_rw_reg_1 0x006C0044
++ #define rp_mpeg_config_addr 0x2652
++ #define rs_imb_status_addr 0x00400058
++ #define rp_phase_imb_addr 0x2650
++ #define rp_amp_imb_addr 0x264E
++ #define rs_cust_chip_id_addr 0x006C0034
++ #define rc_eq_out_iq_swap_addr 0x00402028
++
++ //raptor merge for blind scan fixes to be able to control the tuner step size
++ #define rp_tuner_factor_addr 0x0000264C
++ #define rp_hsym_acq_th_addr 0x0000264A
++ #define rp_hsym_cd_th_addr 0x00002648
++
++ #define rc_mpeg_bus_cntrl_addr 0x400800
++ #define rc_cntns_pkt_para_rate_frac_n_addr 0x400898
++ #define rc_cntns_pkt_para_rate_frac_d_addr 0x40089C
++ #define rc_pkt_seri_rate_frac_n_addr 0x400818
++ #define rc_pkt_seri_rate_frac_d_addr 0x40081C
++
++
++ #define rc_pkt_err_count_addr 0x400810
++ #define rc_pkt_count_addr 0x400814
++ #define rs_total_words_addr 0x400430
++ #define rs_total_uncorrected_words_addr 0x400434
++
++
++ /// @endcond
++
++ /// Initializes the demodulator.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the demodulator is being initialized.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the demodulator has been initialized.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function must be called first before all other functions declared in this interface.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_Initialize(const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the Availink device with the polarity of the RF AGC. This value should be set according to the tuner's requirement as specified by the tuner datasheet.
++ ///
++ /// @param enumAGCPola The polarity of the RF AGC. Refer to ::AVL_DVBSx_RfagcPola.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object which is being configured with the tuner RF AGC polarity.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the tuner RF AGC polarity has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetRFAGCPola( enum AVL_DVBSx_RfagcPola enumAGCPola, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the MPEG output mode.
++ ///
++ /// @param pMpegMode A pointer to an object which contains the MPEG output mode configuration.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the MPEG output mode is being configured.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the MPEG output mode has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegMode( const struct AVL_DVBSx_MpegInfo * pMpegMode, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Gets the RF signal level.
++ ///
++ /// @param puiRFSignalLevel Pointer to a variable in which to store signal level. The signal level value ranges from 0 to 65535, with zero corresponding to the weakest signal level value and 65535 corresponding to the strongest signal level value.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the signal level is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the signal level has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function actually reads the RF AGC value. The corresponding signal power in dBm varies depending on the tuner. The user can derive the relationship from the Tuner datasheet or through measurement.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetSignalLevel(AVL_puint16 puiRFSignalLevel , const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Sets the carrier frequency sweep range for subsequent LockChannel calls. Use of this function is optional. The default value is 500 (+/-5MHz). This function is typically used to narrow the sweep range in cases where there are multiple narrow bandwidth signals within the default range and there is the possibility that the wrong signal will be locked. If multiple signals are detected within the specified sweep range, the Availink device will lock to the strongest one.
++ ///
++ /// @param uiFreqSweepRange_10kHz Half of the frequency sweep range in units of 10kHz. The maximum value is 500 (sweep from -5MHz to +5MHz).
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the frequency sweep range is being set.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the frequency sweep range is successfully configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks The input parameter uiFreqSweepRange_10kHz specifies half of the actual sweep range. The whole range will be [-uiFreqSweepRange_10kHz, +uiFreqSweepRange_10kHz]. Note that this sweep range must be large enough to accommodate the RF path frequency uncertainty.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetFreqSweepRange(AVL_uint16 uiFreqSweepRange_10kHz, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the m_Flags member of the AVL_DVBSx_Channel object with the desired lock mode. On boot-up the default channel lock mode is AVL_DVBSx_LOCK_MODE_FIXED.
++ ///
++ /// @param psChannel Pointer to the channel object for which to configure the lock mode.
++ /// @param enumChannelLockMode The desired lock mode. Refer to ::AVL_DVBSx_LockMode.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK after the m_Flags member of the psChannel input parameter is configured with the desired lock mode.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetChannelLockMode( struct AVL_DVBSx_Channel * psChannel, enum AVL_DVBSx_LockMode enumChannelLockMode );
++
++ /// Locks to a channel using the parameters specified in \a psChannel.
++ ///
++ /// @param psChannel Holds the channel related parameters needed by the Availink device to lock to the input signal.
++ /// @param pAVLChip A pointer to the AVL_DVBSx_Chip object for which the lock operation is being performed.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the lock parameters and command are successfully sent to the device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the lock command could not be sent to the device because the device is still processing a previous command.
++ /// @remarks Calling this function commands the Availink device to lock to a particular channel. Use the function
++ /// GetLockStatus to determine if the device has successfully locked to the channel. The channel lock operation is
++ /// performed in either fixed mode or adaptive mode depending on how the psChannel input parameter has been configured.
++ /// Please see the function SetChannelLockMode for more details regarding how to configure the channel object for either mode. This function can perform automatic IQ swap if \a psChannel->m_Flags has the CI_FLAG_IQ_AUTO_BIT bit set.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_LockChannel( struct AVL_DVBSx_Channel * psChannel, struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Checks if the Availink device has locked to the channel.
++ ///
++ /// @param puiLockStatus Pointer to a variable in which to store the channel lock status (0 - Not locked 1 - Locked).
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the lock status is being queried.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the channel lock status has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function should be called after the function ::AVL_DVBSx_IRx_LockChannel is called.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetLockStatus( AVL_puint16 puiLockStatus, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Resets the BER and PER accumulation statistics.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the BER and PER statistics are being reset.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if command to reset the BER and PER statistics has been sent to the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the command could not be sent to the Availink device because the device is still processing a previous command.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ResetErrorStat( struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Retrieves the scatter data from the Availink device.
++ ///
++ /// @param ucpData Pointer to an array in which to store the scatter data. The buffer size MUST be >= 2*(*puiSize) because there are two bytes per set of IQ data. The first (*puiSize) bytes in the buffer are I values, and the following (*puiSize) bytes are Q values.
++ /// @param puiSize The number of IQ pairs to be read. The function updates this value with the number of IQ pairs actually retrieved.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the scatter data is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the scatter data has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_Running if the scatter data is not ready for retrieval.
++ /// @remarks Normally, the size of the scatter data will be 132 sets of IQ. i.e. 264 bytes.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetScatterData( AVL_puchar ucpData, AVL_puint16 puiSize, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads the current SNR estimate.
++ ///
++ /// @param puiSNR_db Pointer to a variable in which to store the estimated SNR value. The SNR value is scaled by 100. For example, a reported SNR value of 2578 means the SNR value is 25.78 db.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which estimated SNR is being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the SNR has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks It takes a few seconds for the device to calculate a stable SNR value after FEC lock. The function returns an SNR value of 0 before a stable SNR value is calculated.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetSNR( AVL_puint32 puiSNR_db, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads the current PER calculation result.
++ ///
++ /// @param puiPER Pointer to a variable in which to store the PER value. The value is scaled by 1e+9. For example, if the reported value is 123456, the PER value is 0.000123456.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the PER is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the PER has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks It takes a few seconds for the device to calculates a stable PER value after FEC lock. The function reports a PER of 0 until a stable PER is calculated.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetPER( AVL_puint32 puiPER, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads the current BER calculation result.
++ ///
++ /// @param puiBER Pointer to a variable in which to store the current BER value. The value is scaled by 1e+9. For example, a BER reading of 123456 means the that the BER is 0.000123456.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the BER is being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the BER has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function is provided for laboratory BER testing. The function requires the use of a transmitter which can generate either an LFSR15 or LFSR23 data stream.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetBER( AVL_puint32 puiBER, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads the current DVBS BER estimate.
++ ///
++ /// @param puiBER A pointer to a variable in which to store the estimated DVBS BER value. The value is scaled by 1e+9. For example, a BER reading of 123456 means the estimated BER is 0.000123456.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which estimated DVBS BER is being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the BER has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if the Availink device is not locked to a DVBS signal.
++ /// @remarks This function reports and estimated BER when a DVB-S signal is received. The function does not require the input of a known test pattern to the receiver. It can estimate BER for on-air DVB-S signals.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetDVBSBER( AVL_puint32 puiBER, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Resets the DVB-S BER estimate.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the DVB-S BER estimate is being reset.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the DVB-S BER estimate has been reset.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ResetDVBSBER( const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Gets the RF carrier frequency offset. Typically this is used to adjust the tuner frequency.
++ ///
++ /// @param piRFOffset_100kHz Pointer to a variable in which to store the RF carrier frequency offset in units of 100 kHz.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the RF carrier frequency offset is being read.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the RF carrier frequency offset has been read.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function may be called after the Availink device has locked to the input signal.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetRFOffset( AVL_pint16 piRFOffset_100kHz, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Gets the current locked signal information.
++ ///
++ /// @param pSignalInfo Pointer to an object in which to store the detected signal information.
++ /// @param pAVLChip Pointer to the ::AVL_DVBSx_Chip object for which the signal information is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the signal information has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// @remarks This function may be called after the Availink device has locked to the input signal.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetSignalInfo( struct AVL_DVBSx_SignalInfo * pSignalInfo, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Allows the user to enable or disable dish pointing mode.
++ ///
++ /// @param ucMode Indicates whether dish pointing mode is being enabled or disabled (0 - Disable dish pointing mode, 1 - Enable dish pointing mode).
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which dish pointing mode is being configured.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if dish pointing mode has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ /// Return ::AVL_DVBSx_EC_GeneralFail if the Availink device is not in demodulator mode.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetDishPointingMode( AVL_uchar ucMode, const struct AVL_DVBSx_Chip *pAVLChip );
++
++ /// Configures the Availink device to drive the MPEG output interface.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object which is to drive the MPEG output interface.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has been successfully configured to drive the MPEG output interface.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DriveMpegOutput( const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the Availink device to release the MPEG output interface, placing it in a high impedance state. This allows the MPEG bus to be driven by other devices which may be sharing it with the Availink device.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object which is to release the MPEG output interface.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has been successfully configured to release the MPEG output interface.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ReleaseMpegOutput( const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Enables MPEG persistent clock mode. In this mode, once the Availink device is commanded to lock to a channel, it persistently outputs an MPEG clock signal,
++ /// regardless of whether the demod is locked or not. When the demod is not locked, the MPEG valid and data signals are held low. When the demod is locked, the received data
++ /// is output.
++ ///
++ /// @param uiMpegDataClkFreq_10kHz The desired MPEG output byte clock frequency during periods in which the demod is not locked. Units of 10 kHz.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which MPEG persistent clock mode is being enabled.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if MPEG persistent clock mode is successfully enabled.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_EnableMpegPersistentClockMode( AVL_uint16 uiMpegDataClkFreq_10kHz, const struct AVL_DVBSx_Chip *pAVLChip );
++
++ /// Disables MPEG persistent clock mode. If MPEG persistent clock mode is disabled, then the Availink device outputs an MPEG clock signal only when it is locked to a channel.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which MPEG persistent clock mode is being disabled.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if MPEG persistent clock mode is successfully disabled.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DisableMpegPersistentClockMode( const struct AVL_DVBSx_Chip *pAVLChip );
++
++ /// Enable MPEG manual clock mode. In this mode, the Availink device always outputs an MPEG clock signal.
++ ///
++ /// @param uiMpegDataClkFreq_10kHz The desired MPEG continuous output byte clock frequency.
++ /// @param enumMpegMode The mode in which the MPEG output interface is being operated (parallel or serial).
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which MPEG persistent clock mode is being disabled.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if MPEG persistent clock mode is successfully disabled.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_EnableMpegManualClockFrequency(AVL_uint16 uiMpegDataClkFreq_10kHz, enum AVL_DVBSx_MpegMode enumMpegMode, const struct AVL_DVBSx_Chip * pAVLChip);
++
++ /// Disables MPEG manual clock mode. If MPEG manual clock is disabled, MPEG output clock in automatic mode. Then the Availink device outputs an MPEG clock signal only when it is locked to a channel.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which MPEG persistent clock mode is being disabled.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if MPEG persistent clock mode is successfully disabled.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DisableMpegManualClockFrequency(const struct AVL_DVBSx_Chip * pAVLChip);
++
++ /// Enables or disables the internal MPEG interface pull-down resistors.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the internal MPEG interface resistors are being configured.
++ /// @param enumPulldownState Indicates whether the internal pull-down resistors should be enabled or disabled.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the internal MPEG pull-down resistors have been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegPulldown( const struct AVL_DVBSx_Chip *pAVLChip, enum AVL_DVBSx_MpegPulldown enumPulldownState );
++
++ /// Configures the Availink device to output the RF AGC signal.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object which is to output an RF AGC signal.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has been successfully configured to output an RF AGC signal.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DriveRFAGC( const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Configures the Availink device to release the RF AGC signal output.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object which is to release the RF AGC signal output.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device has been successfully configured to release the RF AGC signal.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ReleaseRFAGC( const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads the IQ imbalance of the received signal.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the IQ imbalance of the received signal is being read.
++ /// @param piAmplitude A pointer to a variable in which to store the amplitude imbalance in units of dB. The value is scaled by 100. For example, a value of 300 means an amplitude imbalance of 3 dB.
++ /// @param piPhase A pointer to a variable in which to store the phase imbalance in units of degrees. The value is scaled by 100. For example, a value of 200 means a phase imbalance of 2 degrees.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the IQ imbalance has been retrieved from the Availink device.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetIQ_Imbalance( const struct AVL_DVBSx_Chip * pAVLChip, AVL_pint16 piAmplitude, AVL_pint16 piPhase );
++
++ /// Reads the Availink device ID. Availink can customize the device ID to meet the needs of individual customers.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the device ID is being read.
++ /// @param puiDeviceID A pointer to a variable in which to store the device ID.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the device ID has been read.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetDeviceID( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puint32 puiDeviceID);
++
++ /// Configures the output bit order of the MPEG data. The user can set the bit order to either normal or invert.
++ /// The meaning differs depending on whether the MPEG interface is configured to output data in serial mode or
++ /// parallel mode as follows:
++ /// Serial mode (Normal - Output the most significant bit of each byte first, Invert - Output the least significant
++ /// bit of each byte first.)
++ /// Parallel mode (Normal - The MSB of each byte is output on pin 7 and the LSB on pin 0, Invert - The MSB of each
++ /// byte is output on pin 0 and the LSB on pin 7.)
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the MPEG bit order is being configured.
++ /// @param enumMpegMode The mode in which the MPEG output interface is being operated (parallel or serial).
++ /// @param enumMpegBitOrder The desired MPEG output bit order.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the MPEG output bit order has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegBitOrder( const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegMode enumMpegMode, enum AVL_DVBSx_MpegBitOrder enumMpegBitOrder );
++
++ /// Selects the pin on which MPEG data is output in serial mode. The serial data can be output on pin MPEG_DATA_7
++ /// or pin MPEG_DATA_0.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the output data pin is being selected.
++ /// @param enumSerialPin The pin on which to output the MPEG data in serial mode.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the MPEG output pin has been configured for serial mode.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegSerialPin( const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegSerialPin enumSerialPin );
++
++ /// Configures the polarity of the MPEG valid signal when the MPEG interface is configured for TSP mode.
++ /// If the MPEG Interface is configured for TS mode, calling this function has no effect.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the polarity of the MPEG valid signal is being configured.
++ /// @param enumValidPolarity The polarity of the MPEG valid signal in TSP mode (Normal - The valid signal is held low during the
++ /// parity bytes, Invert - The valid signal is held high during the parity bytes).
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the polarity of the MPEG valid signal has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegValidPolarity( const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegValidPolarity enumValidPolarity );
++
++ /// Configures the polarity of the MPEG error signal. This function allows the user to configure the Availink device with the
++ /// the error signal polarity that should be used when the demod is not locked to the channel as well as the error signal polarity
++ /// that should be used when the demod is locked to the channel.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the polarity of the MPEG error signal is being configured.
++ /// @param enumErrorLockPolarity The MPEG error signal polarity to be used during periods in which the Availink device is locked to a
++ /// signal (Normal - The MPEG error signal is high when there is an MPEG error, Invert - The MPEG signal is low when there is an MPEG error).
++ /// @param enumErrorUnlockPolarity The MPEG error signal polarity to be used during periods in which the Availink device is not locked to a
++ /// signal (Normal - MPEG error signal is low when the demod is not locked, Invert - MPEG error signal is high when the demod is not locked.)
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the polarity of the MPEG error signal has been configured.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegErrorPolarity(const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegErrorPolarity enumErrorLockPolarity, enum AVL_DVBSx_MpegErrorPolarity enumErrorUnlockPolarity);
++
++ /// Reads the IQ swap status of the received signal. This function is useful if the user enabled automatic IQ swap
++ /// when locking to the channel. After channel lock has been achieved, the user may call the GetIQ_Swap function
++ /// to determine whether the I and Q signals had to be swapped for the received signal.
++ ///
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the IQ swap status status is being retrieved.
++ /// @param puiIQ_Swap Pointer to a variable in which to store the IQ swap status (0 - Not swapped, 1 - Swapped).
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the IQ swap status has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetIQ_Swap( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puint16 uiIQ_Swap );
++
++ /// Reads the current word error rate of Reed-Solomon decoder.
++ ///
++ /// @param puiRSErr Pointer to a variable in which to store the word error rate value.The value is scaled by 1e+9. For example, if the reported value is 123456, the word error rate value is 0.000123456.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the word error rate is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the word error rate has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetRSError( AVL_puint32 puiRSErr, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ /// Reads back the value of total error packets at current time.
++ ///
++ /// @param puiErrPacket Pointer to a variable in which to store the error packets value.
++ /// @param pAVLChip A pointer to the ::AVL_DVBSx_Chip object for which the error packets is being retrieved.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the error packets value has been retrieved.
++ /// Return ::AVL_DVBSx_EC_I2CFail if there is an I2C communication problem.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetErrPacket( AVL_puint32 puiErrPacket, const struct AVL_DVBSx_Chip * pAVLChip );
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/ITuner.h b/drivers/amlogic/dvb_tv/avl6211/include/ITuner.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/ITuner.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/ITuner.h 2014-12-11 16:13:50.061617837 +0100
+@@ -0,0 +1,64 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief The ITuner interface
++/// @details The ITuner interface supports dynamic tuner switch during run time. It is the user's responsibility to to ensure that the function pointers in the tuner data structure are not NULL.
++///
++#ifndef ITuner_h_h
++ #define ITuner_h_h
++
++ #include "avl_dvbsx.h"
++ #include "avl_dvbsx_globals.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ /// @cond
++
++ /// @endcond
++
++ /// The Tuner data structure
++ ///
++ struct AVL_Tuner
++ {
++ AVL_uint16 m_uiSlaveAddress; ///< The Tuner slave address. It is the write address of the tuner device. In particular it is an 8-bit address, with the LSB set to zero. The Availink device does not support 10-bit I2C addresses.
++ AVL_uint16 m_uiI2CBusClock_kHz; ///< The clock speed of the I2C bus that is dedicated to tuner control. The units are kHz.
++ AVL_uint16 m_uiFrequency_100kHz; ///< The tuned frequency in units of 100kHz.
++ AVL_uint16 m_uiLPF_100kHz; ///< The lowpass filter bandwidth of the tuner.
++ AVL_uint32 m_uiSymbolRate_Hz; ///< The symbol rate of the incoming channel.
++ void * m_pParameters; ///< A pointer to the tuner's customized parameters baseband gain, etc.
++ struct AVL_DVBSx_Chip * m_pAVLChip; ///< A pointer to the Availink device connected to the Tuner.
++ AVL_DVBSx_ErrorCode (* m_pInitializeFunc)(struct AVL_Tuner *); ///< A pointer to the tuner initialization function.
++ AVL_DVBSx_ErrorCode (* m_pGetLockStatusFunc)(struct AVL_Tuner *); ///< A pointer to the tuner GetLockStatus function.
++ AVL_DVBSx_ErrorCode (* m_pDumpDataFunc)(AVL_puchar ucpData, AVL_puchar ucpSize, struct AVL_Tuner *); ///< A pointer to the DumpData function. This function is optional; it is used to dump debug information.
++ AVL_DVBSx_ErrorCode (* m_pLockFunc)(struct AVL_Tuner *); ///< A pointer to the tuner Lock function.
++ };
++
++ /// This function calculates the tuner lowpass filter bandwidth based on the symbol rate of the received signal.
++ ///
++ /// @param uiSymbolRate_10kHz The symbol rate of the received signal in units of 10kHz.
++ /// @param pTuner A pointer to the tuner object for which the lowpass filter bandwidth is being computed. The function updates the member m_uiLPF_100kHz of this object.
++ ///
++ /// @return ::AVL_DVBSx_ErrorCode,
++ /// Return ::AVL_DVBSx_EC_OK if the tuner lowpass filter bandwidth member of the tuner object has been updated.
++ /// This function is provided as an example of how to set the lowpass filter bandwidth in a manner that is proportional to the symbol rate. The user may use their own calculation instead.
++ AVL_DVBSx_ErrorCode AVL_DVBSx_ITuner_CalculateLPF(AVL_uint16 uiSymbolRate_10kHz,struct AVL_Tuner * pTuner);
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/LockSignal_Api.h b/drivers/amlogic/dvb_tv/avl6211/include/LockSignal_Api.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/LockSignal_Api.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/LockSignal_Api.h 2014-12-11 16:13:50.141617225 +0100
+@@ -0,0 +1,61 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++
++
++
++#ifndef LockSignal_source_h_h
++ #define LockSignal_source_h_h
++
++ #include "avl_dvbsx.h"
++
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++/*#include"ITuner.h"
++#include "IRx.h"
++#include "DiSEqC_source.h"
++#include "IBlindScan.h"
++#include "IBlindscanAPI.h"
++#include "II2C.h"
++#include "IBase.h"*/
++
++
++
++ struct Signal_Level
++ {
++ AVL_uint16 SignalLevel;
++ AVL_int16 SignalDBM;
++ };
++
++ void AVL_DVBSx_Error_Dispose(AVL_DVBSx_ErrorCode r);
++ AVL_DVBSx_ErrorCode AVL6211_Initialize(struct AVL_DVBSx_Chip * pAVLChip,struct AVL_Tuner * pTuner,int iDeviceIndex);
++ AVL_DVBSx_ErrorCode AVL6211_LockSignal_Init(int iDeviceId);
++ AVL_DVBSx_ErrorCode CPU_Halt(struct AVL_DVBSx_Chip * pAVLChip);
++ void AVL_Set_LPF(int iDeviceId,struct AVL_Tuner * pTuner, AVL_uint32 m_uiSymbolRate_Hz);
++ int AVL_Get_Quality_Percent(struct AVL_DVBSx_Chip * pAVLChip);
++ AVL_int16 AVL_Get_Level_Percent(struct AVL_DVBSx_Chip * pAVLChip);
++
++ AVL_uint32 AVL6211_GETBer(int iDeviceId);
++ AVL_uint32 AVL6211_GETPer(int iDeviceId);
++ AVL_uint32 AVL6211_GETSnr(int iDeviceId);
++ AVL_uint32 AVL6211_GETSignalLevel(int iDeviceId);
++ AVL_uint32 AVL6211_GETLockStatus(int iDeviceId);
++
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/SharpBS2S7HZ6306.h b/drivers/amlogic/dvb_tv/avl6211/include/SharpBS2S7HZ6306.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/SharpBS2S7HZ6306.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/SharpBS2S7HZ6306.h 2014-12-11 16:13:50.161617073 +0100
+@@ -0,0 +1,59 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Declare customized data structure for Sharp BS2S7HZ6306 tuner
++///
++#ifndef SharpBS2S7HZ6306_h_h
++ #define SharpBS2S7HZ6306_h_h
++
++ #include "avl_dvbsx.h"
++
++ #ifdef AVL_CPLUSPLUS
++extern "C" {
++ #endif
++
++ enum SharpBS2S7HZ6306_BBGain
++ {
++ Bbg_0_Sharp,
++ Bbg_1_Sharp,
++ Bbg_2_Sharp,
++ Bbg_4_Sharp
++ };
++
++ enum SharpBS2S7HZ6306_PumpCurrent
++ {
++ PC_78_150_Sharp = 0, ///< = 0 min +/- 78 uA; typical +/- 120 uA; Max +/- 150 uA
++ PC_169_325_Sharp = 1, ///< = 1 min +/- 169 uA; typical +/- 260 uA; Max +/- 325 uA
++ PC_360_694_Sharp = 2, ///< = 2 min +/- 360 uA; typical +/- 555 uA; Max +/- 694 uA
++ PC_780_1500_Sharp = 3 ///< = 3 min +/- 780 uA; typical +/- 1200 uA; Max +/- 1500 uA
++ };
++
++ struct SharpBS2S7HZ6306_TunerPara
++ {
++ enum SharpBS2S7HZ6306_PumpCurrent m_ChargPump;
++ enum SharpBS2S7HZ6306_BBGain m_BBGain;
++ };
++
++ struct SharpBS2S7HZ6306_Registers
++ {
++ AVL_uchar m_ucLPF;
++ AVL_uchar m_ucRegData[4];
++ };
++
++ #ifdef AVL_CPLUSPLUS
++}
++ #endif
++#endif
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/include/ucPatchData.h b/drivers/amlogic/dvb_tv/avl6211/include/ucPatchData.h
+--- a/drivers/amlogic/dvb_tv/avl6211/include/ucPatchData.h 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/include/ucPatchData.h 2014-12-11 16:13:50.141617225 +0100
+@@ -0,0 +1,304 @@
++const unsigned char ucPatchData [] =
++{
++ 0x00, 0x00, 0x12, 0xA8, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x1C, 0xD8, 0x00, 0x00, 0x08, 0xD8,
++ 0x5A, 0x6C, 0x78, 0x87, 0x90, 0x96, 0xA0, 0xA2, 0x3F, 0xFF, 0x5C, 0x29, 0x40, 0x3F, 0x3B, 0x64,
++ 0x3F, 0xF9, 0x37, 0x4C, 0x40, 0x3A, 0xE1, 0x48, 0x41, 0x43, 0x00, 0xD2, 0x41, 0x1F, 0xB3, 0x3E,
++ 0x41, 0x59, 0xF3, 0x4D, 0x41, 0x57, 0xE4, 0x26, 0x41, 0x50, 0x5E, 0x9E, 0x41, 0x52, 0xD3, 0xC3,
++ 0x41, 0x84, 0xB5, 0x74, 0x41, 0x85, 0x82, 0x41, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
++ 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x22, 0x30, 0x4E, 0x71, 0x4E, 0xD0, 0x4E, 0x56, 0x00, 0x00,
++ 0x4A, 0x79, 0x00, 0x00, 0x05, 0xF8, 0x67, 0x3E, 0x41, 0xF9, 0x00, 0x00, 0x08, 0x16, 0x30, 0xBC,
++ 0x00, 0xFF, 0x70, 0x00, 0x30, 0x2E, 0x00, 0x0A, 0x0C, 0x80, 0x00, 0x00, 0x00, 0xC8, 0x67, 0x12,
++ 0x0C, 0x80, 0x00, 0x00, 0x00, 0xC9, 0x67, 0x0C, 0x0C, 0x80, 0x00, 0x00, 0x00, 0xCA, 0x67, 0x12,
++ 0x60, 0x14, 0x60, 0x12, 0x70, 0x0A, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0x0C, 0x46, 0x58, 0x8F,
++ 0x60, 0x04, 0x70, 0x01, 0x30, 0x80, 0x42, 0x01, 0x70, 0x00, 0x10, 0x01, 0x4E, 0x5E, 0x4E, 0x75,
++ 0x00, 0x00, 0x11, 0x9C, 0x00, 0x00, 0x26, 0x54, 0x4E, 0x56, 0x00, 0x00, 0x48, 0xE7, 0x20, 0x30,
++ 0x45, 0xF9, 0x00, 0x00, 0x04, 0x3C, 0x70, 0x00, 0x30, 0x2A, 0x01, 0xC6, 0x41, 0xF9, 0x00, 0x00,
++ 0x08, 0xD8, 0x43, 0xF0, 0x08, 0x00, 0x23, 0xC9, 0x00, 0x00, 0x37, 0x60, 0x72, 0x00, 0x32, 0x2E,
++ 0x00, 0x0A, 0x0C, 0x81, 0x00, 0x00, 0x01, 0xF8, 0x64, 0x00, 0x00, 0xB8, 0x70, 0x10, 0xB0, 0x81,
++ 0x67, 0x00, 0x01, 0x72, 0x70, 0x66, 0xB0, 0x81, 0x67, 0x00, 0x02, 0x7C, 0x70, 0x67, 0xB0, 0x81,
++ 0x67, 0x00, 0x02, 0xE0, 0x70, 0x6D, 0xB0, 0x81, 0x67, 0x00, 0x07, 0x12, 0x70, 0x74, 0xB0, 0x81,
++ 0x67, 0x00, 0x01, 0xE8, 0x70, 0x75, 0xB0, 0x81, 0x67, 0x00, 0x07, 0x48, 0x0C, 0x81, 0x00, 0x00,
++ 0x00, 0xCE, 0x67, 0x00, 0x0B, 0xAE, 0x0C, 0x81, 0x00, 0x00, 0x00, 0xCF, 0x67, 0x00, 0x0B, 0xC2,
++ 0x0C, 0x81, 0x00, 0x00, 0x00, 0xDC, 0x67, 0x00, 0x0B, 0x32, 0x0C, 0x81, 0x00, 0x00, 0x00, 0xDD,
++ 0x67, 0x00, 0x0A, 0x78, 0x0C, 0x81, 0x00, 0x00, 0x00, 0xDE, 0x67, 0x00, 0x01, 0xC6, 0x0C, 0x81,
++ 0x00, 0x00, 0x00, 0xDF, 0x67, 0x00, 0x0B, 0x9A, 0x0C, 0x81, 0x00, 0x00, 0x01, 0x35, 0x67, 0x00,
++ 0x05, 0xBE, 0x0C, 0x81, 0x00, 0x00, 0x01, 0x44, 0x67, 0x00, 0x0B, 0xB0, 0x0C, 0x81, 0x00, 0x00,
++ 0x01, 0x47, 0x67, 0x00, 0x05, 0x8A, 0x0C, 0x81, 0x00, 0x00, 0x01, 0x93, 0x67, 0x00, 0x08, 0x34,
++ 0x0C, 0x81, 0x00, 0x00, 0x01, 0x98, 0x67, 0x00, 0x01, 0x42, 0x0C, 0x81, 0x00, 0x00, 0x01, 0xA2,
++ 0x67, 0x00, 0x04, 0xB8, 0x0C, 0x81, 0x00, 0x00, 0x01, 0xF5, 0x67, 0x00, 0x00, 0xCC, 0x60, 0x00,
++ 0x0F, 0xB6, 0x0C, 0x81, 0x00, 0x00, 0x01, 0xF8, 0x67, 0x00, 0x06, 0xE0, 0x0C, 0x81, 0x00, 0x00,
++ 0x02, 0x02, 0x67, 0x00, 0x0E, 0xDE, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x04, 0x67, 0x00, 0x07, 0xF4,
++ 0x0C, 0x81, 0x00, 0x00, 0x02, 0x0D, 0x67, 0x00, 0x0A, 0x3A, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x10,
++ 0x67, 0x00, 0x03, 0x80, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x22, 0x67, 0x00, 0x0E, 0xE6, 0x0C, 0x81,
++ 0x00, 0x00, 0x02, 0x26, 0x67, 0x00, 0x0B, 0xCE, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x2B, 0x67, 0x00,
++ 0x07, 0xC2, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x2C, 0x67, 0x00, 0x08, 0xB8, 0x0C, 0x81, 0x00, 0x00,
++ 0x02, 0x31, 0x67, 0x00, 0x0F, 0x2A, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x67, 0x67, 0x00, 0x02, 0x4A,
++ 0x0C, 0x81, 0x00, 0x00, 0x02, 0x6A, 0x67, 0x00, 0x05, 0x36, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x78,
++ 0x67, 0x00, 0x0B, 0xD8, 0x0C, 0x81, 0x00, 0x00, 0x02, 0x79, 0x67, 0x00, 0x01, 0xE0, 0x0C, 0x81,
++ 0x00, 0x00, 0x02, 0x82, 0x67, 0x00, 0x0C, 0xE0, 0x0C, 0x81, 0x00, 0x00, 0x02, 0xC2, 0x67, 0x00,
++ 0x0E, 0x9C, 0x0C, 0x81, 0x00, 0x00, 0x03, 0x2E, 0x67, 0x00, 0x05, 0x38, 0x0C, 0x81, 0x00, 0x00,
++ 0x03, 0x2F, 0x67, 0x00, 0x05, 0x8A, 0x0C, 0x81, 0x00, 0x00, 0x03, 0x36, 0x67, 0x00, 0x04, 0xB4,
++ 0x60, 0x00, 0x0E, 0xF4, 0x60, 0x00, 0x01, 0x22, 0x25, 0x7A, 0x0E, 0xFC, 0x02, 0x50, 0x35, 0x7C,
++ 0x01, 0x90, 0x01, 0x26, 0x42, 0x78, 0x26, 0x52, 0x42, 0x78, 0x26, 0x50, 0x42, 0x78, 0x26, 0x4E,
++ 0x25, 0x7C, 0x01, 0x00, 0x00, 0x1D, 0x00, 0x7C, 0x70, 0x09, 0x31, 0xC0, 0x26, 0x4C, 0x31, 0xFC,
++ 0x50, 0x00, 0x26, 0x4A, 0x31, 0xFC, 0x00, 0x9C, 0x26, 0x48, 0x21, 0xFC, 0x00, 0x00, 0x00, 0xC8,
++ 0x26, 0x44, 0x31, 0xFC, 0x01, 0x90, 0x26, 0x42, 0x21, 0xFC, 0x00, 0x4C, 0x4B, 0x40, 0x26, 0x3E,
++ 0x70, 0x01, 0x11, 0xC0, 0x26, 0x3D, 0x31, 0xC0, 0x26, 0x32, 0x42, 0x78, 0x26, 0x30, 0x42, 0x78,
++ 0x26, 0x2E, 0x42, 0xB8, 0x26, 0x2A, 0x60, 0x00, 0x0E, 0x8E, 0x42, 0xA7, 0x42, 0xA7, 0x30, 0x2A,
++ 0x00, 0xA8, 0x48, 0xC0, 0x4E, 0xB9, 0x00, 0x10, 0x03, 0x1E, 0x2F, 0x00, 0x2F, 0x3A, 0x0E, 0x8C,
++ 0x4E, 0xB9, 0x00, 0x10, 0x81, 0x78, 0x70, 0x10, 0xDF, 0xC0, 0x48, 0x78, 0x75, 0x30, 0x4E, 0xB9,
++ 0x00, 0x10, 0x63, 0xA2, 0x58, 0x8F, 0x60, 0x00, 0x0E, 0x5E, 0x35, 0x7C, 0x4E, 0x20, 0x01, 0x9E,
++ 0x25, 0x7C, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x50, 0x70, 0x04, 0x35, 0x40, 0x01, 0x4A, 0x60, 0x00,
++ 0x05, 0x72, 0x4A, 0xB9, 0x00, 0x00, 0x37, 0x64, 0x66, 0x00, 0x0E, 0x3C, 0x41, 0xF9, 0x00, 0x00,
++ 0x06, 0x90, 0x70, 0x05, 0xB0, 0xA8, 0x00, 0x04, 0x66, 0x00, 0x0E, 0x2C, 0x70, 0x06, 0xB0, 0x90,
++ 0x66, 0x00, 0x0E, 0x24, 0x2F, 0x3A, 0x0E, 0x38, 0x20, 0x39, 0x00, 0x40, 0x00, 0x48, 0xE9, 0x80,
++ 0xE8, 0x80, 0x4E, 0xB9, 0x00, 0x10, 0x03, 0x1E, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0xD7, 0xE4,
++ 0x50, 0x8F, 0x2F, 0x00, 0x2F, 0x3A, 0x0E, 0x1C, 0x4E, 0xB9, 0x00, 0x10, 0xDC, 0x40, 0x50, 0x8F,
++ 0x2F, 0x00, 0x2F, 0x39, 0x00, 0x00, 0x37, 0x68, 0x4E, 0xB9, 0x00, 0x10, 0xDA, 0x74, 0x25, 0x40,
++ 0x02, 0x24, 0x60, 0x00, 0x04, 0x08, 0x70, 0x7F, 0x35, 0x40, 0x01, 0x6E, 0x70, 0x10, 0x35, 0x40,
++ 0x00, 0xAE, 0x70, 0x05, 0x35, 0x40, 0x00, 0xAC, 0x23, 0xFC, 0x00, 0x00, 0x26, 0x7F, 0x00, 0x6C,
++ 0x80, 0x00, 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x70, 0x01, 0x23, 0xC0, 0x00, 0x6C, 0x80, 0x04,
++ 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x23, 0xFC, 0x00, 0x00, 0x26, 0x70, 0x00, 0x6C, 0x80, 0x00,
++ 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x23, 0xC0, 0x00, 0x6C, 0x80, 0x04, 0x42, 0xB9, 0x00, 0x6C,
++ 0x80, 0x04, 0x23, 0xFC, 0x00, 0x00, 0x26, 0x7F, 0x00, 0x6C, 0x80, 0x00, 0x42, 0xB9, 0x00, 0x6C,
++ 0x80, 0x04, 0x23, 0xC0, 0x00, 0x6C, 0x80, 0x04, 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x60, 0x00,
++ 0x0D, 0x76, 0x23, 0xEA, 0x02, 0x24, 0x00, 0x00, 0x37, 0x68, 0x70, 0x05, 0x35, 0x40, 0x00, 0xAC,
++ 0x30, 0x2A, 0x02, 0x02, 0x72, 0x0F, 0xC0, 0x81, 0x25, 0x40, 0x00, 0x0C, 0x42, 0x6A, 0x01, 0xF4,
++ 0x70, 0xFF, 0x25, 0x40, 0x00, 0x98, 0x72, 0x01, 0x60, 0x00, 0x0D, 0x4E, 0x72, 0x00, 0x32, 0x38,
++ 0x26, 0x52, 0x70, 0x01, 0xC2, 0x80, 0x24, 0x01, 0x22, 0x3C, 0xFF, 0xFF, 0xEF, 0xFF, 0xC2, 0xB9,
++ 0x00, 0x40, 0x08, 0x00, 0x70, 0x0C, 0xE1, 0xA2, 0x20, 0x3C, 0x00, 0x00, 0x10, 0x00, 0xC0, 0x82,
++ 0x82, 0x80, 0x23, 0xC1, 0x00, 0x40, 0x08, 0x00, 0x70, 0x00, 0x30, 0x38, 0x26, 0x52, 0x74, 0x01,
++ 0xE2, 0x88, 0x72, 0xFE, 0xC2, 0xB9, 0x00, 0x6C, 0x00, 0x44, 0xC4, 0x80, 0x82, 0x82, 0x23, 0xC1,
++ 0x00, 0x6C, 0x00, 0x44, 0x60, 0x00, 0x0D, 0x00, 0x4A, 0x6A, 0x02, 0x0C, 0x66, 0x00, 0x00, 0x92,
++ 0x23, 0xF8, 0x26, 0x3E, 0x00, 0x00, 0x37, 0x6C, 0x33, 0xF8, 0x26, 0x42, 0x00, 0x00, 0x37, 0x70,
++ 0x2F, 0x3A, 0x0D, 0x04, 0x2F, 0x39, 0x00, 0x00, 0x37, 0x6C, 0x4E, 0xB9, 0x00, 0x10, 0xCF, 0x40,
++ 0x58, 0x8F, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0xD7, 0xE4, 0x50, 0x8F, 0x2F, 0x00, 0x2F, 0x2A,
++ 0x02, 0x24, 0x4E, 0xB9, 0x00, 0x10, 0xDE, 0x44, 0x50, 0x8F, 0x6E, 0x4A, 0x35, 0x79, 0x00, 0x00,
++ 0x37, 0x70, 0x01, 0x60, 0x2F, 0x3A, 0x0C, 0xD4, 0x74, 0x00, 0x34, 0x39, 0x00, 0x00, 0x37, 0x70,
++ 0x2F, 0x02, 0x4E, 0xB9, 0x00, 0x10, 0xCF, 0x40, 0x58, 0x8F, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10,
++ 0xD7, 0xE4, 0x25, 0x40, 0x02, 0x28, 0x20, 0x2A, 0x00, 0x34, 0x72, 0x00, 0x32, 0x2A, 0x02, 0x20,
++ 0xB3, 0x80, 0x53, 0x80, 0x50, 0x8F, 0x66, 0x18, 0x20, 0x2A, 0x02, 0x28, 0x08, 0x40, 0x00, 0x1F,
++ 0x25, 0x40, 0x02, 0x28, 0x60, 0x0A, 0x42, 0x6A, 0x01, 0x60, 0x25, 0x7A, 0x0C, 0x92, 0x02, 0x28,
++ 0x23, 0xF9, 0x00, 0x40, 0x08, 0x00, 0x00, 0x00, 0x37, 0x74, 0x30, 0x2A, 0x02, 0x10, 0x02, 0x40,
++ 0x80, 0x00, 0x0C, 0x40, 0x80, 0x00, 0x66, 0x2E, 0x20, 0x39, 0x00, 0x00, 0x37, 0x74, 0x72, 0x0B,
++ 0xE2, 0xA0, 0x08, 0x00, 0x00, 0x00, 0x66, 0x1E, 0x70, 0x00, 0x30, 0x2A, 0x02, 0x10, 0x02, 0x80,
++ 0x00, 0x00, 0x7F, 0xFF, 0xE9, 0x80, 0x23, 0xC0, 0x00, 0x40, 0x08, 0x18, 0x30, 0x6A, 0x01, 0x66,
++ 0x23, 0xC8, 0x00, 0x40, 0x08, 0x1C, 0x72, 0x00, 0x32, 0x38, 0x26, 0x52, 0x70, 0x01, 0xE6, 0x89,
++ 0xC0, 0x81, 0x25, 0x40, 0x00, 0x1C, 0x25, 0x79, 0x00, 0x00, 0x37, 0x68, 0x02, 0x24, 0x60, 0x00,
++ 0x0C, 0x06, 0x23, 0xF9, 0x00, 0x40, 0x00, 0x58, 0x00, 0x00, 0x37, 0x78, 0x20, 0x39, 0x00, 0x00,
++ 0x37, 0x78, 0x74, 0x10, 0xE5, 0xA0, 0x74, 0x18, 0xE4, 0xA0, 0x23, 0xC0, 0x00, 0x00, 0x37, 0x7C,
++ 0x20, 0x39, 0x00, 0x00, 0x37, 0x78, 0xE5, 0xA0, 0xE4, 0xA0, 0x23, 0xC0, 0x00, 0x00, 0x37, 0x80,
++ 0x2F, 0x3A, 0x0B, 0xF0, 0x2F, 0x3A, 0x0B, 0xFC, 0x20, 0x39, 0x00, 0x00, 0x37, 0x7C, 0x4E, 0xB9,
++ 0x00, 0x10, 0x03, 0x1E, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0xD7, 0xE4, 0x50, 0x8F, 0x2F, 0x00,
++ 0x4E, 0xB9, 0x00, 0x10, 0xDC, 0x48, 0x23, 0xC0, 0x00, 0x00, 0x37, 0x84, 0x2F, 0x39, 0x00, 0x00,
++ 0x37, 0x84, 0x2F, 0x3A, 0x0B, 0xD2, 0x4E, 0xB9, 0x00, 0x10, 0xDA, 0x74, 0x50, 0x8F, 0x2F, 0x00,
++ 0x20, 0x39, 0x00, 0x00, 0x37, 0x80, 0x4E, 0xB9, 0x00, 0x10, 0x03, 0x1E, 0x2F, 0x00, 0x4E, 0xB9,
++ 0x00, 0x10, 0xD7, 0xE4, 0x23, 0xC0, 0x00, 0x00, 0x37, 0x88, 0x2F, 0x39, 0x00, 0x00, 0x37, 0x84,
++ 0x4E, 0xB9, 0x00, 0x10, 0x87, 0x74, 0x23, 0xC0, 0x00, 0x00, 0x37, 0x8C, 0x58, 0x8F, 0x2F, 0x3A,
++ 0x0B, 0x9A, 0x2F, 0x39, 0x00, 0x00, 0x37, 0x88, 0x4E, 0xB9, 0x00, 0x10, 0xDA, 0x74, 0x23, 0xC0,
++ 0x00, 0x00, 0x37, 0x88, 0x2F, 0x3A, 0x0B, 0x74, 0x2F, 0x39, 0x00, 0x00, 0x37, 0x88, 0x4E, 0xB9,
++ 0x00, 0x10, 0xDA, 0x74, 0x50, 0x8F, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0xD0, 0xE0, 0x58, 0x8F,
++ 0x31, 0xC0, 0x26, 0x50, 0x2F, 0x3A, 0x0B, 0x68, 0x2F, 0x39, 0x00, 0x00, 0x37, 0x8C, 0x4E, 0xB9,
++ 0x00, 0x10, 0xDA, 0x74, 0x50, 0x8F, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0xD0, 0xE0, 0x58, 0x8F,
++ 0x31, 0xC0, 0x26, 0x4E, 0x70, 0x18, 0x60, 0x00, 0x01, 0x00, 0x70, 0x02, 0x23, 0xC0, 0x00, 0x00,
++ 0x37, 0x90, 0x72, 0x00, 0x32, 0x38, 0x26, 0x52, 0x70, 0x01, 0xE4, 0x89, 0xC0, 0x81, 0x25, 0x40,
++ 0x00, 0x1C, 0x0C, 0x38, 0x00, 0x01, 0x26, 0x3D, 0x66, 0x18, 0x2F, 0x3A, 0x0B, 0x26, 0x2F, 0x2A,
++ 0x02, 0x24, 0x4E, 0xB9, 0x00, 0x10, 0xDE, 0x44, 0x50, 0x8F, 0x6E, 0x06, 0x42, 0xB9, 0x00, 0x00,
++ 0x37, 0x90, 0x25, 0x79, 0x00, 0x00, 0x37, 0x90, 0x00, 0x04, 0x2F, 0x2A, 0x00, 0x04, 0x4E, 0xB9,
++ 0x00, 0x10, 0x8B, 0x72, 0x58, 0x8F, 0x23, 0xF9, 0x00, 0x40, 0x08, 0x00, 0x00, 0x00, 0x37, 0x94,
++ 0x20, 0x39, 0x00, 0x00, 0x37, 0x94, 0x72, 0x0B, 0xE2, 0xA0, 0x08, 0x00, 0x00, 0x00, 0x66, 0x04,
++ 0x42, 0x6A, 0x00, 0xBA, 0x08, 0xB9, 0x00, 0x01, 0x00, 0x00, 0x37, 0x96, 0x23, 0xF9, 0x00, 0x00,
++ 0x37, 0x94, 0x00, 0x40, 0x08, 0x00, 0x45, 0xF9, 0x00, 0x00, 0x06, 0x90, 0x70, 0x01, 0x2F, 0x00,
++ 0x42, 0xA7, 0x42, 0xA7, 0x2F, 0x2A, 0x00, 0x08, 0x4E, 0xB9, 0x00, 0x10, 0x65, 0xE6, 0x70, 0x10,
++ 0xDF, 0xC0, 0x4E, 0xB9, 0x00, 0x10, 0x68, 0x98, 0x42, 0xAA, 0x00, 0x18, 0x70, 0x11, 0x24, 0x80,
++ 0x42, 0xAA, 0x00, 0xF0, 0x70, 0x01, 0x35, 0x40, 0x01, 0x64, 0x60, 0x00, 0xFD, 0x0A, 0x72, 0x00,
++ 0x32, 0x38, 0x26, 0x52, 0x70, 0x01, 0xE4, 0x89, 0xC0, 0x81, 0x25, 0x40, 0x00, 0x1C, 0x60, 0x00,
++ 0x0A, 0x46, 0x23, 0xEA, 0x02, 0x24, 0x00, 0x00, 0x37, 0x68, 0x60, 0x00, 0x0A, 0x3A, 0x70, 0x05,
++ 0xB0, 0xB9, 0x00, 0x00, 0x06, 0x90, 0x66, 0x00, 0x0A, 0x2E, 0x42, 0xA7, 0x42, 0xA7, 0x30, 0x2A,
++ 0x00, 0xA8, 0x48, 0xC0, 0x4E, 0xB9, 0x00, 0x10, 0x03, 0x1E, 0x2F, 0x00, 0x2F, 0x3A, 0x0A, 0x58,
++ 0x4E, 0xB9, 0x00, 0x10, 0x81, 0x78, 0x70, 0x10, 0xDF, 0xC0, 0x60, 0x00, 0x0A, 0x0A, 0x47, 0xF9,
++ 0x00, 0x00, 0x06, 0x90, 0x70, 0x01, 0xB0, 0xAB, 0x00, 0xE4, 0x64, 0x00, 0x09, 0xFA, 0x4E, 0xB9,
++ 0x00, 0x10, 0x8D, 0xB6, 0x42, 0xAB, 0x00, 0xEC, 0x2F, 0x2A, 0x00, 0x50, 0x30, 0x2A, 0x01, 0x9E,
++ 0x48, 0xC0, 0xD0, 0x80, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0x8E, 0xF8, 0x50, 0x8F, 0x60, 0x00,
++ 0x09, 0xD6, 0x20, 0x79, 0x00, 0x00, 0x37, 0x60, 0x72, 0x00, 0x32, 0x39, 0x00, 0x00, 0x08, 0x0A,
++ 0x74, 0x0C, 0x20, 0x01, 0xC2, 0xC2, 0x48, 0x40, 0xC0, 0xC2, 0x48, 0x40, 0x42, 0x40, 0xD2, 0x80,
++ 0x0C, 0xB0, 0x00, 0x00, 0x93, 0xD0, 0x18, 0x04, 0x65, 0x00, 0x09, 0xAC, 0x23, 0xEA, 0x00, 0x5C,
++ 0x00, 0x00, 0x37, 0x98, 0x70, 0x00, 0x30, 0x38, 0x26, 0x4A, 0x25, 0x40, 0x00, 0x5C, 0x23, 0xEA,
++ 0x00, 0x60, 0x00, 0x00, 0x37, 0x9C, 0x30, 0x38, 0x26, 0x48, 0x25, 0x40, 0x00, 0x60, 0x20, 0x2A,
++ 0x00, 0x60, 0x72, 0x0A, 0xE3, 0xA0, 0x25, 0x40, 0x00, 0x60, 0x60, 0x00, 0x09, 0x7A, 0x20, 0x79,
++ 0x00, 0x00, 0x37, 0x60, 0x72, 0x00, 0x32, 0x39, 0x00, 0x00, 0x08, 0x0A, 0x74, 0x0C, 0x20, 0x01,
++ 0xC2, 0xC2, 0x48, 0x40, 0xC0, 0xC2, 0x48, 0x40, 0x42, 0x40, 0xD2, 0x80, 0x0C, 0xB0, 0x00, 0x00,
++ 0x93, 0xD0, 0x18, 0x04, 0x65, 0x00, 0x09, 0x50, 0x25, 0x79, 0x00, 0x00, 0x37, 0x98, 0x00, 0x5C,
++ 0x25, 0x79, 0x00, 0x00, 0x37, 0x9C, 0x00, 0x60, 0x60, 0x00, 0x09, 0x3C, 0x42, 0x6A, 0x01, 0x60,
++ 0x25, 0x7A, 0x09, 0x5C, 0x02, 0x28, 0x42, 0x79, 0x00, 0x00, 0x07, 0xD2, 0x70, 0x00, 0x30, 0x2A,
++ 0x01, 0xB4, 0x72, 0x0A, 0x4E, 0xB9, 0x00, 0x10, 0xE6, 0x86, 0x72, 0x7D, 0x34, 0x00, 0x70, 0x00,
++ 0x30, 0x2A, 0x01, 0xC4, 0xE3, 0x42, 0x04, 0x80, 0x00, 0x00, 0x00, 0xC8, 0xE7, 0x89, 0x4E, 0xB9,
++ 0x00, 0x10, 0xE6, 0x86, 0x94, 0x40, 0xC4, 0xF8, 0x26, 0x4C, 0x35, 0x42, 0x01, 0xDC, 0x60, 0x00,
++ 0x08, 0xF6, 0x0C, 0xAA, 0x00, 0x2D, 0xC6, 0xC0, 0x00, 0x54, 0x6C, 0x00, 0x08, 0xEA, 0x70, 0x02,
++ 0x35, 0x40, 0x01, 0x78, 0x70, 0x20, 0x35, 0x40, 0x01, 0x3A, 0x35, 0x7C, 0x00, 0xC2, 0x01, 0x6E,
++ 0x70, 0x03, 0x35, 0x40, 0x00, 0xAC, 0x60, 0x00, 0x08, 0xCE, 0x0C, 0x6A, 0x00, 0x01, 0x02, 0x0A,
++ 0x66, 0x00, 0x08, 0xC4, 0x70, 0x01, 0xB0, 0xAA, 0x00, 0x0C, 0x66, 0x00, 0x08, 0xBA, 0x4E, 0xB9,
++ 0x00, 0x10, 0x92, 0x8C, 0x20, 0x3C, 0xBF, 0xFF, 0xFF, 0xFF, 0xC0, 0xB9, 0x00, 0x40, 0x00, 0x1C,
++ 0x08, 0xC0, 0x00, 0x1E, 0x23, 0xC0, 0x00, 0x40, 0x00, 0x1C, 0x20, 0x3C, 0xBF, 0xFF, 0xFF, 0xFF,
++ 0xC0, 0xB9, 0x00, 0x40, 0x00, 0x1C, 0x23, 0xC0, 0x00, 0x40, 0x00, 0x1C, 0x47, 0xF9, 0x00, 0x00,
++ 0x06, 0x90, 0x2F, 0x2B, 0x01, 0xC0, 0x4E, 0xB9, 0x00, 0x10, 0x89, 0xE2, 0x58, 0x8F, 0x4E, 0xB9,
++ 0x00, 0x10, 0x92, 0xCA, 0x72, 0xFB, 0xC2, 0xB9, 0x00, 0x40, 0x00, 0x70, 0x70, 0x04, 0x82, 0x80,
++ 0x23, 0xC1, 0x00, 0x40, 0x00, 0x70, 0x70, 0xFB, 0xC0, 0xB9, 0x00, 0x40, 0x00, 0x70, 0x23, 0xC0,
++ 0x00, 0x40, 0x00, 0x70, 0x30, 0x2A, 0x01, 0x3A, 0x72, 0x0A, 0x48, 0xC0, 0xE3, 0xA0, 0x2F, 0x00,
++ 0x4E, 0xB9, 0x00, 0x10, 0x63, 0x32, 0x58, 0x8F, 0x4A, 0x80, 0x67, 0x00, 0xFA, 0xEA, 0x48, 0x78,
++ 0x03, 0xE8, 0x4E, 0xB9, 0x00, 0x10, 0x63, 0xA2, 0x58, 0x8F, 0x4E, 0xB9, 0x00, 0x10, 0x83, 0xE8,
++ 0x20, 0x7C, 0x00, 0x40, 0x30, 0x58, 0x22, 0x10, 0x70, 0x01, 0xC0, 0x41, 0x67, 0xF8, 0x23, 0xF9,
++ 0x00, 0x40, 0x30, 0x20, 0x00, 0x00, 0x37, 0xA0, 0x23, 0xF9, 0x00, 0x40, 0x00, 0x54, 0x00, 0x00,
++ 0x37, 0xA4, 0x20, 0x3C, 0x00, 0x00, 0x0F, 0xFF, 0xC0, 0xB9, 0x00, 0x00, 0x37, 0xA0, 0x72, 0x0E,
++ 0xE3, 0xA0, 0x22, 0x39, 0x00, 0x00, 0x37, 0xA4, 0x4E, 0xB9, 0x00, 0x10, 0xE6, 0x86, 0x23, 0xC0,
++ 0x00, 0x00, 0x37, 0xA0, 0x20, 0x3C, 0xFE, 0xFF, 0xFF, 0xFF, 0xC0, 0xB9, 0x00, 0x40, 0x30, 0x48,
++ 0x08, 0xC0, 0x00, 0x18, 0x23, 0xC0, 0x00, 0x40, 0x30, 0x48, 0x20, 0x3C, 0xFE, 0xFF, 0xFF, 0xFF,
++ 0xC0, 0xB9, 0x00, 0x40, 0x30, 0x48, 0x23, 0xC0, 0x00, 0x40, 0x30, 0x48, 0x2F, 0x39, 0x00, 0x00,
++ 0x37, 0xA0, 0x4E, 0xB9, 0x00, 0x10, 0x35, 0x02, 0x58, 0x8F, 0x42, 0x6B, 0x01, 0x44, 0x60, 0x00,
++ 0xFA, 0x56, 0x70, 0x09, 0x23, 0xC0, 0x00, 0x00, 0x37, 0xA8, 0x70, 0x0A, 0x23, 0xC0, 0x00, 0x00,
++ 0x37, 0xAC, 0x41, 0xF9, 0x00, 0x00, 0x06, 0x90, 0x47, 0xE8, 0x00, 0x0C, 0x70, 0x01, 0xB0, 0x93,
++ 0x66, 0x0E, 0x4A, 0xA8, 0x00, 0x10, 0x66, 0x08, 0x21, 0xFC, 0x00, 0x00, 0x01, 0x90, 0x26, 0x44,
++ 0x23, 0xF8, 0x26, 0x44, 0x00, 0x00, 0x37, 0xB0, 0x2F, 0x3A, 0x07, 0xB0, 0x2F, 0x39, 0x00, 0x00,
++ 0x37, 0xB0, 0x4E, 0xB9, 0x00, 0x10, 0xCF, 0x40, 0x58, 0x8F, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10,
++ 0xDA, 0x74, 0x23, 0xC0, 0x00, 0x00, 0x37, 0xB4, 0x4A, 0xAA, 0x00, 0x0C, 0x50, 0x8F, 0x67, 0x08,
++ 0x70, 0x02, 0xB0, 0xAA, 0x00, 0x0C, 0x66, 0x0A, 0x2F, 0x3A, 0x07, 0x84, 0x30, 0x2A, 0x01, 0x50,
++ 0x60, 0x0E, 0x4E, 0xB9, 0x00, 0x10, 0x96, 0xB4, 0x2F, 0x3A, 0x07, 0x74, 0x30, 0x2A, 0x01, 0x2E,
++ 0x48, 0xC0, 0x4E, 0xB9, 0x00, 0x10, 0x03, 0x1E, 0x2F, 0x00, 0x4E, 0xB9, 0x00, 0x10, 0xDA, 0x74,
++ 0x23, 0xC0, 0x00, 0x00, 0x37, 0xB8, 0x50, 0x8F, 0x48, 0x79, 0x00, 0x00, 0x37, 0xBC, 0x48, 0x79,
++ 0x00, 0x00, 0x37, 0xC0, 0x42, 0xA7, 0x2F, 0x13, 0x2F, 0x39, 0x00, 0x00, 0x37, 0xB4, 0x2F, 0x39,
++ 0x00, 0x00, 0x37, 0xB8, 0x4E, 0xB9, 0x00, 0x10, 0x97, 0x58, 0x70, 0x18, 0xDF, 0xC0, 0x23, 0xF9,
++ 0x00, 0x00, 0x37, 0xC0, 0x00, 0x00, 0x37, 0xC4, 0x23, 0xF9, 0x00, 0x00, 0x37, 0xBC, 0x00, 0x00,
++ 0x37, 0xC8, 0x24, 0x39, 0x00, 0x00, 0x37, 0xC4, 0x70, 0x19, 0xE1, 0xA2, 0x20, 0x39, 0x00, 0x00,
++ 0x37, 0xA8, 0x72, 0x14, 0xE3, 0xA0, 0x84, 0x80, 0x20, 0x39, 0x00, 0x00, 0x37, 0xC8, 0xEB, 0x80,
++ 0x84, 0x80, 0x84, 0xB9, 0x00, 0x00, 0x37, 0xAC, 0x23, 0xC2, 0x00, 0x40, 0x0C, 0x10, 0x60, 0x00,
++ 0x06, 0xA6, 0x0C, 0x6A, 0x00, 0x01, 0x01, 0xFC, 0x67, 0x08, 0x0C, 0x6A, 0x00, 0x01, 0x01, 0xFE,
++ 0x66, 0x62, 0x4A, 0x6A, 0x02, 0x00, 0x66, 0x5C, 0x70, 0x0F, 0x23, 0xC0, 0x00, 0x6C, 0x41, 0x40,
++ 0x23, 0xC0, 0x00, 0x6C, 0x41, 0x80, 0x23, 0xFC, 0x00, 0x00, 0x26, 0x70, 0x00, 0x6C, 0x80, 0x00,
++ 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x70, 0x01, 0x23, 0xC0, 0x00, 0x6C, 0x80, 0x04, 0x42, 0xB9,
++ 0x00, 0x6C, 0x80, 0x04, 0x41, 0xF9, 0x00, 0x00, 0x06, 0x90, 0x42, 0x68, 0x01, 0x64, 0x42, 0xB9,
++ 0x00, 0x60, 0x00, 0x28, 0x42, 0xB9, 0x00, 0x60, 0x00, 0x20, 0x42, 0xB9, 0x00, 0x60, 0x00, 0x5C,
++ 0x70, 0x16, 0x20, 0x80, 0x70, 0x01, 0x35, 0x40, 0x02, 0x00, 0x23, 0xC0, 0x00, 0x60, 0x00, 0x20,
++ 0x42, 0x78, 0x26, 0x32, 0x0C, 0x6A, 0x00, 0x01, 0x02, 0x00, 0x66, 0x00, 0x00, 0x8A, 0x4A, 0x6A,
++ 0x01, 0xFC, 0x66, 0x00, 0x00, 0x82, 0x4A, 0x6A, 0x01, 0xFE, 0x66, 0x7A, 0x23, 0xFC, 0x00, 0x00,
++ 0x26, 0x7F, 0x00, 0x6C, 0x80, 0x00, 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x70, 0x01, 0x23, 0xC0,
++ 0x00, 0x6C, 0x80, 0x04, 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x23, 0xFC, 0x00, 0x00, 0x26, 0x70,
++ 0x00, 0x6C, 0x80, 0x00, 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x23, 0xC0, 0x00, 0x6C, 0x80, 0x04,
++ 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x23, 0xFC, 0x00, 0x00, 0x26, 0x7F, 0x00, 0x6C, 0x80, 0x00,
++ 0x42, 0xB9, 0x00, 0x6C, 0x80, 0x04, 0x23, 0xC0, 0x00, 0x6C, 0x80, 0x04, 0x42, 0xB9, 0x00, 0x6C,
++ 0x80, 0x04, 0x42, 0x6A, 0x02, 0x00, 0x30, 0x2A, 0x01, 0xF8, 0x23, 0xC0, 0x00, 0x6C, 0x41, 0x40,
++ 0x30, 0x2A, 0x01, 0xFA, 0x23, 0xC0, 0x00, 0x6C, 0x41, 0x80, 0x70, 0x01, 0x23, 0xC0, 0x00, 0x60,
++ 0x00, 0x5C, 0x31, 0xC0, 0x26, 0x32, 0x60, 0x00, 0xF8, 0x4E, 0x42, 0xB9, 0x00, 0x00, 0x37, 0x64,
++ 0x4E, 0xB9, 0x00, 0x10, 0x0A, 0xA2, 0x4E, 0xB9, 0x00, 0x10, 0x2C, 0x0E, 0x41, 0xF9, 0x00, 0x00,
++ 0x06, 0x90, 0x70, 0x16, 0xB0, 0x90, 0x26, 0x48, 0x66, 0x0C, 0x70, 0x01, 0x23, 0xC0, 0x00, 0x00,
++ 0x37, 0x64, 0x60, 0x00, 0xF8, 0x22, 0x45, 0xE8, 0x00, 0x04, 0x20, 0x10, 0xB0, 0x92, 0x67, 0x06,
++ 0x4E, 0xB9, 0x00, 0x10, 0x2A, 0xCC, 0x24, 0x93, 0x4E, 0xB9, 0x00, 0x10, 0x35, 0xDA, 0x60, 0x00,
++ 0xF8, 0x06, 0x4A, 0x6A, 0x02, 0x0C, 0x66, 0x00, 0x05, 0x4E, 0x30, 0x2A, 0x01, 0x60, 0x72, 0x0A,
++ 0x48, 0xC0, 0x4E, 0xB9, 0x00, 0x10, 0xE6, 0x86, 0x33, 0xC0, 0x00, 0x00, 0x37, 0xCC, 0x20, 0x2A,
++ 0x00, 0x34, 0x72, 0x00, 0x32, 0x2A, 0x02, 0x20, 0xB3, 0x80, 0x53, 0x80, 0x66, 0x10, 0x30, 0x39,
++ 0x00, 0x00, 0x37, 0xCC, 0x48, 0xC0, 0x44, 0x80, 0x33, 0xC0, 0x00, 0x00, 0x37, 0xCC, 0x41, 0xF9,
++ 0x00, 0x00, 0x07, 0xD2, 0x30, 0x39, 0x00, 0x00, 0x37, 0xCC, 0x91, 0x50, 0x20, 0x2A, 0x00, 0x34,
++ 0x72, 0x00, 0x32, 0x2A, 0x02, 0x20, 0xB3, 0x80, 0x53, 0x80, 0x66, 0x00, 0x04, 0xFA, 0x30, 0x10,
++ 0x48, 0xC0, 0x44, 0x80, 0x30, 0x80, 0x60, 0x00, 0x04, 0xEE, 0x47, 0xF9, 0x00, 0x00, 0x06, 0x90,
++ 0x22, 0x13, 0x70, 0x01, 0xB2, 0x80, 0x67, 0x4C, 0x70, 0x03, 0xB2, 0x80, 0x67, 0x36, 0x70, 0x04,
++ 0xB2, 0x80, 0x67, 0x44, 0x70, 0x05, 0xB2, 0x80, 0x67, 0x3A, 0x70, 0x17, 0xB0, 0x81, 0x66, 0x3E,
++ 0x0C, 0xAA, 0x00, 0x1E, 0x84, 0x80, 0x00, 0x54, 0x6E, 0x18, 0x42, 0x78, 0x1E, 0x84, 0x2F, 0x2A,
++ 0x02, 0x24, 0x2F, 0x2A, 0x02, 0x50, 0x4E, 0xB9, 0x00, 0x10, 0xDA, 0x74, 0x27, 0x40, 0x01, 0xC4,
++ 0x50, 0x8F, 0x60, 0x0A, 0x0C, 0xAA, 0x00, 0x1E, 0x84, 0x80, 0x00, 0x54, 0x6F, 0x06, 0x42, 0xAA,
++ 0x00, 0x0C, 0x60, 0x0A, 0x70, 0x04, 0x60, 0x02, 0x70, 0x01, 0x25, 0x40, 0x00, 0x0C, 0x60, 0x00,
++ 0xF7, 0x36, 0x20, 0x39, 0x00, 0x6C, 0x00, 0x30, 0x33, 0xC0, 0x00, 0x00, 0x37, 0xCE, 0x42, 0x01,
++ 0x0C, 0x79, 0x00, 0x0F, 0x00, 0x00, 0x37, 0xCE, 0x67, 0x00, 0x04, 0x6E, 0x60, 0x00, 0xF7, 0x18,
++ 0x20, 0x39, 0x00, 0x6C, 0x00, 0x30, 0x33, 0xC0, 0x00, 0x00, 0x37, 0xCE, 0x0C, 0x79, 0x00, 0x0F,
++ 0x00, 0x00, 0x37, 0xCE, 0x66, 0x10, 0x72, 0x01, 0x4A, 0xB9, 0x00, 0x00, 0x37, 0x64, 0x66, 0x00,
++ 0x04, 0x48, 0x60, 0x00, 0x04, 0x42, 0x60, 0x00, 0xF6, 0xEE, 0x23, 0xF9, 0x00, 0x40, 0x08, 0x00,
++ 0x00, 0x00, 0x37, 0xD0, 0x08, 0x2A, 0x00, 0x00, 0x02, 0x05, 0x67, 0x00, 0x04, 0x2A, 0x20, 0x39,
++ 0x00, 0x00, 0x37, 0xD0, 0x72, 0x0B, 0xE2, 0xA0, 0x08, 0x00, 0x00, 0x00, 0x66, 0x00, 0x04, 0x18,
++ 0x30, 0x2A, 0x02, 0x10, 0x02, 0x40, 0x80, 0x00, 0x0C, 0x40, 0x80, 0x00, 0x66, 0x00, 0x04, 0x08,
++ 0x23, 0xF9, 0x00, 0x40, 0x08, 0x20, 0x00, 0x00, 0x37, 0xD4, 0x23, 0xF9, 0x00, 0x40, 0x08, 0x24,
++ 0x00, 0x00, 0x37, 0xD8, 0x23, 0xF9, 0x00, 0x40, 0x08, 0x18, 0x00, 0x00, 0x37, 0xDC, 0x23, 0xF9,
++ 0x00, 0x40, 0x08, 0x1C, 0x00, 0x00, 0x37, 0xE0, 0x42, 0x6A, 0x00, 0xBA, 0x42, 0xB9, 0x00, 0x60,
++ 0x00, 0x5C, 0x70, 0x01, 0x23, 0xC0, 0x00, 0x60, 0x00, 0x5C, 0x23, 0xF9, 0x00, 0x00, 0x37, 0xD4,
++ 0x00, 0x40, 0x08, 0x20, 0x23, 0xF9, 0x00, 0x00, 0x37, 0xD8, 0x00, 0x40, 0x08, 0x24, 0x23, 0xF9,
++ 0x00, 0x00, 0x37, 0xDC, 0x00, 0x40, 0x08, 0x18, 0x23, 0xF9, 0x00, 0x00, 0x37, 0xE0, 0x00, 0x40,
++ 0x08, 0x1C, 0x60, 0x3C, 0x23, 0xF9, 0x00, 0x40, 0x08, 0x00, 0x00, 0x00, 0x37, 0xE4, 0x30, 0x2A,
++ 0x02, 0x10, 0x02, 0x40, 0x80, 0x00, 0x0C, 0x40, 0x80, 0x00, 0x66, 0x00, 0x03, 0x8A, 0x08, 0x2A,
++ 0x00, 0x00, 0x02, 0x05, 0x67, 0x00, 0x03, 0x80, 0x20, 0x39, 0x00, 0x00, 0x37, 0xE4, 0x72, 0x0B,
++ 0xE2, 0xA0, 0x08, 0x00, 0x00, 0x00, 0x66, 0x00, 0x03, 0x6E, 0x70, 0x01, 0x35, 0x40, 0x00, 0xBA,
++ 0x4E, 0xB9, 0x00, 0x10, 0x68, 0x98, 0x60, 0x00, 0x03, 0x5E, 0x0C, 0x6A, 0x00, 0x01, 0x01, 0x94,
++ 0x66, 0x78, 0x47, 0xF9, 0x00, 0x00, 0x06, 0x90, 0x42, 0x6B, 0x01, 0x46, 0x42, 0x6B, 0x01, 0x48,
++ 0x22, 0x2A, 0x00, 0x44, 0x70, 0x05, 0xB2, 0x80, 0x62, 0x3A, 0x20, 0x01, 0xD0, 0x80, 0x32, 0x3B,
++ 0x08, 0x06, 0x4E, 0xFB, 0x10, 0x02, 0x00, 0x0C, 0x00, 0x14, 0x00, 0x1E, 0x00, 0x22, 0x00, 0x26,
++ 0x00, 0x2A, 0x42, 0x79, 0x00, 0x00, 0x37, 0xE8, 0x60, 0x38, 0x70, 0x01, 0x33, 0xC0, 0x00, 0x00,
++ 0x37, 0xE8, 0x60, 0x2E, 0x70, 0x05, 0x60, 0xF4, 0x70, 0x08, 0x60, 0xF0, 0x70, 0x0D, 0x60, 0xEC,
++ 0x70, 0x19, 0x60, 0xE8, 0x48, 0x7A, 0x03, 0x4C, 0x48, 0x78, 0x00, 0xA0, 0x48, 0x79, 0x00, 0x00,
++ 0x1D, 0x40, 0x4E, 0xB9, 0x00, 0x10, 0xC4, 0xF6, 0x70, 0x0C, 0xDF, 0xC0, 0x4E, 0xB9, 0x00, 0x10,
++ 0x0C, 0x78, 0x27, 0x6A, 0x00, 0x44, 0x00, 0x08, 0x60, 0x10, 0x70, 0x02, 0xB0, 0xAA, 0x00, 0x0C,
++ 0x66, 0x08, 0x70, 0x01, 0x33, 0xC0, 0x00, 0x00, 0x37, 0xE8, 0x0C, 0x6A, 0x00, 0x01, 0x01, 0x94,
++ 0x67, 0x5C, 0x70, 0x02, 0xB0, 0xAA, 0x00, 0x0C, 0x66, 0x6A, 0x60, 0x52, 0x22, 0x39, 0x00, 0x40,
++ 0x04, 0x00, 0x70, 0x01, 0xC0, 0x41, 0x67, 0x10, 0x70, 0xFE, 0xC0, 0xB9, 0x00, 0x40, 0x04, 0x00,
++ 0x23, 0xC0, 0x00, 0x40, 0x04, 0x00, 0x60, 0x36, 0x4A, 0x79, 0x00, 0x00, 0x37, 0xE8, 0x63, 0x2E,
++ 0x72, 0xFE, 0xC2, 0xB9, 0x00, 0x40, 0x04, 0x00, 0x70, 0x01, 0x82, 0x80, 0x23, 0xC1, 0x00, 0x40,
++ 0x04, 0x00, 0x43, 0xF9, 0x00, 0x00, 0x06, 0x90, 0x41, 0xE9, 0x01, 0x46, 0x52, 0x50, 0x30, 0x10,
++ 0x72, 0x1F, 0xC0, 0x41, 0x33, 0x40, 0x01, 0x48, 0x53, 0x79, 0x00, 0x00, 0x37, 0xE8, 0x4A, 0x79,
++ 0x00, 0x00, 0x37, 0xE8, 0x62, 0xA6, 0x70, 0xFE, 0xC0, 0xB9, 0x00, 0x40, 0x04, 0x00, 0x23, 0xC0,
++ 0x00, 0x40, 0x04, 0x00, 0x33, 0xF9, 0x00, 0x00, 0x37, 0xE8, 0x00, 0x00, 0x37, 0xEA, 0x48, 0x78,
++ 0x06, 0x40, 0x60, 0x00, 0x01, 0x72, 0x4A, 0x6A, 0x01, 0x94, 0x67, 0x00, 0x02, 0x3A, 0x20, 0x39,
++ 0x00, 0x40, 0x04, 0x14, 0xE6, 0x80, 0x08, 0x00, 0x00, 0x00, 0x67, 0x00, 0x01, 0x3E, 0x70, 0x02,
++ 0xB0, 0xAA, 0x00, 0x0C, 0x66, 0x3A, 0x0C, 0x79, 0x00, 0x03, 0x00, 0x00, 0x07, 0xD8, 0x66, 0x0E,
++ 0x47, 0xF9, 0x00, 0x10, 0x6A, 0xD4, 0x74, 0x09, 0x4E, 0x93, 0x53, 0x82, 0x66, 0xFA, 0x0C, 0x79,
++ 0x00, 0x13, 0x00, 0x00, 0x07, 0xD8, 0x66, 0x0E, 0x47, 0xF9, 0x00, 0x10, 0x6A, 0xD4, 0x74, 0x0E,
++ 0x4E, 0x93, 0x53, 0x82, 0x66, 0xFA, 0x4E, 0xB9, 0x00, 0x10, 0x6A, 0xD4, 0x60, 0x00, 0x00, 0xA4,
++ 0x4A, 0xAA, 0x00, 0x0C, 0x66, 0x00, 0x00, 0x9C, 0x22, 0x2A, 0x00, 0x44, 0x70, 0x05, 0xB2, 0x80,
++ 0x62, 0x5A, 0x20, 0x01, 0xD0, 0x80, 0x32, 0x3B, 0x08, 0x06, 0x4E, 0xFB, 0x10, 0x02, 0x00, 0x6C,
++ 0x00, 0x0C, 0x00, 0x1E, 0x00, 0x2A, 0x00, 0x36, 0x00, 0x42, 0x0C, 0x79, 0x00, 0x04, 0x00, 0x00,
++ 0x07, 0xD6, 0x6C, 0x56, 0x4E, 0xB9, 0x00, 0x10, 0x6A, 0xD4, 0x60, 0x4E, 0x0C, 0x79, 0x00, 0x07,
++ 0x00, 0x00, 0x07, 0xD6, 0x6C, 0x44, 0x60, 0xEC, 0x0C, 0x79, 0x00, 0x0C, 0x00, 0x00, 0x07, 0xD6,
++ 0x6C, 0x38, 0x60, 0xE0, 0x0C, 0x79, 0x00, 0x18, 0x00, 0x00, 0x07, 0xD6, 0x6C, 0x2C, 0x60, 0xD4,
++ 0x0C, 0x79, 0x00, 0x1F, 0x00, 0x00, 0x07, 0xD6, 0x6C, 0x20, 0x60, 0xC8, 0x48, 0x7A, 0x01, 0xC4,
++ 0x48, 0x78, 0x00, 0xA0, 0x48, 0x79, 0x00, 0x00, 0x1D, 0x40, 0x4E, 0xB9, 0x00, 0x10, 0xC4, 0xF6,
++ 0x70, 0x0C, 0xDF, 0xC0, 0x4E, 0xB9, 0x00, 0x10, 0x0C, 0x78, 0x0C, 0x79, 0x00, 0x1D, 0x00, 0x00,
++ 0x07, 0xD8, 0x66, 0x0E, 0x47, 0xF9, 0x00, 0x10, 0x6A, 0xD4, 0x74, 0x03, 0x4E, 0x93, 0x53, 0x82,
++ 0x66, 0xFA, 0x08, 0x2A, 0x00, 0x00, 0x02, 0x05, 0x67, 0x40, 0x43, 0xF9, 0x00, 0x00, 0x06, 0x90,
++ 0x41, 0xE9, 0x01, 0x48, 0x0C, 0x50, 0x00, 0x0A, 0x66, 0x08, 0x70, 0x0E, 0xD1, 0x79, 0x00, 0x00,
++ 0x37, 0xEA, 0x52, 0x79, 0x00, 0x00, 0x37, 0xEA, 0x0C, 0x50, 0x00, 0x04, 0x67, 0x06, 0x0C, 0x50,
++ 0x00, 0x07, 0x66, 0x06, 0x52, 0x79, 0x00, 0x00, 0x37, 0xEA, 0x0C, 0x79, 0x00, 0x1C, 0x00, 0x00,
++ 0x37, 0xEA, 0x63, 0x06, 0x70, 0x02, 0x33, 0x40, 0x01, 0x5E, 0x70, 0xF7, 0xC0, 0xB9, 0x00, 0x40,
++ 0x04, 0x14, 0x23, 0xC0, 0x00, 0x40, 0x04, 0x14, 0x60, 0x12, 0x72, 0xF7, 0xC2, 0xB9, 0x00, 0x40,
++ 0x04, 0x14, 0x70, 0x08, 0x82, 0x80, 0x23, 0xC1, 0x00, 0x40, 0x04, 0x14, 0x42, 0x79, 0x00, 0x00,
++ 0x07, 0xE0, 0x48, 0x78, 0x03, 0xE8, 0x4E, 0xB9, 0x00, 0x10, 0x63, 0xA2, 0x58, 0x8F, 0x60, 0x00,
++ 0xF3, 0x76, 0x4A, 0x6A, 0x01, 0x94, 0x67, 0x00, 0x00, 0xBE, 0x41, 0xF9, 0x00, 0x00, 0x06, 0x90,
++ 0x70, 0x00, 0x30, 0x38, 0x26, 0x2E, 0xB0, 0xA8, 0x00, 0x0C, 0x66, 0x0E, 0x70, 0x00, 0x30, 0x38,
++ 0x26, 0x30, 0xB0, 0xA8, 0x00, 0x08, 0x67, 0x00, 0x00, 0x9E, 0x42, 0x68, 0x01, 0x6A, 0x60, 0x00,
++ 0x00, 0x96, 0x4A, 0x6A, 0x01, 0x94, 0x67, 0x00, 0x00, 0x8E, 0x08, 0x2A, 0x00, 0x00, 0x02, 0x05,
++ 0x67, 0x06, 0x4E, 0xB9, 0x00, 0x10, 0x33, 0x9C, 0x60, 0x00, 0xF3, 0x2C, 0x41, 0xF9, 0x00, 0x00,
++ 0x06, 0x90, 0x70, 0x01, 0xB0, 0xA8, 0x00, 0x0C, 0x66, 0x6C, 0x4A, 0xA8, 0x00, 0x10, 0x66, 0x66,
++ 0x50, 0x88, 0x70, 0x0A, 0xB0, 0x90, 0x66, 0x08, 0x70, 0x2D, 0x35, 0x40, 0x01, 0x2E, 0x60, 0x56,
++ 0x70, 0x0B, 0xB0, 0x90, 0x66, 0x04, 0x70, 0x32, 0x60, 0xF0, 0x70, 0x0C, 0xB0, 0x90, 0x67, 0x06,
++ 0x70, 0x0E, 0xB0, 0x90, 0x66, 0x04, 0x70, 0x3C, 0x60, 0xE0, 0x70, 0x0F, 0xB0, 0x90, 0x66, 0x04,
++ 0x70, 0x46, 0x60, 0xD6, 0x70, 0x10, 0xB0, 0x90, 0x66, 0x2C, 0x70, 0x50, 0x60, 0xCC, 0x23, 0xF9,
++ 0x00, 0x40, 0x08, 0x00, 0x00, 0x00, 0x37, 0xEC, 0x20, 0x39, 0x00, 0x00, 0x37, 0xEC, 0x72, 0x0B,
++ 0xE2, 0xA0, 0x08, 0x00, 0x00, 0x00, 0x66, 0x0E, 0x4A, 0xB8, 0x26, 0x2A, 0x63, 0x08, 0x23, 0xF8,
++ 0x26, 0x2A, 0x00, 0x40, 0x08, 0x18, 0x42, 0x01, 0x70, 0x00, 0x10, 0x01, 0x4C, 0xEE, 0x0C, 0x04,
++ 0xFF, 0xF4, 0x4E, 0x5E, 0x4E, 0x75, 0x3E, 0xCC, 0xCC, 0xCD, 0x3B, 0x03, 0x12, 0x6F, 0x4D, 0x80,
++ 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x49, 0x74, 0x24, 0x00, 0x42, 0xC8, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x43, 0x00, 0x00, 0x00, 0x43, 0x80, 0x00, 0x00, 0x42, 0x65, 0x2E, 0xED, 0x43, 0x48,
++ 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x3A, 0xC4, 0x9B, 0xA6, 0x3C, 0x23, 0xD7, 0x0A, 0x37, 0x27,
++ 0xC5, 0xAC, 0x49, 0x6C, 0x6C, 0x65, 0x67, 0x61, 0x6C, 0x20, 0x63, 0x6F, 0x64, 0x65, 0x20, 0x72,
++ 0x61, 0x74, 0x65, 0x20, 0x66, 0x6F, 0x72, 0x20, 0x44, 0x56, 0x42, 0x53, 0x20, 0x73, 0x74, 0x64,
++ 0x20, 0x0A, 0x00, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x14, 0x00, 0x10, 0x03, 0xB2,
++ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x04, 0x28, 0x00, 0x00, 0x00, 0x04,
++ 0x00, 0x00, 0x00, 0x0C, 0x00, 0x10, 0x04, 0x9E, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08,
++ 0x00, 0x10, 0x05, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x10, 0x05, 0x64,
++ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x10, 0x02, 0x58
++
++};
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/Kconfig b/drivers/amlogic/dvb_tv/avl6211/Kconfig
+--- a/drivers/amlogic/dvb_tv/avl6211/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/Kconfig 2014-12-11 16:13:50.473614685 +0100
+@@ -0,0 +1,21 @@
++#
++# Avl6211 driver configuration
++#
++menuconfig AM_AVL6211
++ tristate "AVL6211 demod driver"
++ default n
++ depends on AM_DVB
++ help
++ Select to enable AVL6211 demod driver.
++
++if AM_AVL6211
++
++config AVL6211_OUTPUT_SERIAL
++ bool "Serial Output Mode"
++ depends on AM_AVL6211
++ default n
++ help
++ data default on DATA0
++
++endif
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/Makefile b/drivers/amlogic/dvb_tv/avl6211/Makefile
+--- a/drivers/amlogic/dvb_tv/avl6211/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/Makefile 2014-12-11 16:13:49.913618978 +0100
+@@ -0,0 +1,17 @@
++obj-$(CONFIG_AM_AVL6211) += avl6211_fe.o
++
++avl6211_src = src
++avl6211_fe-objs += avlfrontend.o
++avl6211_fe-objs += $(avl6211_src)/avl.o $(avl6211_src)/avl_dvbsx.o $(avl6211_src)/IBase.o $(avl6211_src)/avl_dvbsx.o $(avl6211_src)/IDiseqc.o $(avl6211_src)/II2C.o \
++ $(avl6211_src)/II2CRepeater.o $(avl6211_src)/IRx.o $(avl6211_src)/IBSP.o $(avl6211_src)/LockSignal_Api.o ##$(avl6211_src)/ExtSharpBS2S7HZ6306.o $(avl6211_src)/DiSEqC_source.o
++
++avl6211_fe-objs += $(avl6211_src)/IBlindscanAPI.o $(avl6211_src)/IBlindScan.o
++
++avl6211_fe-objs += AV2011/ExtAV2011.o
++
++
++EXTRA_CFLAGS += -I.
++EXTRA_CFLAGS += -Idrivers/media/dvb-core
++EXTRA_CFLAGS += -Idrivers/amlogic/dvb_tv/avl6211/include
++EXTRA_CFLAGS += -Idrivers/amlogic/dvb_tv/avl6211
++EXTRA_CFLAGS += -Idrivers/amlogic/dvb_tv/avl6211/AV2011
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/avl.c b/drivers/amlogic/dvb_tv/avl6211/src/avl.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/avl.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/avl.c 2014-12-11 16:13:50.325615817 +0100
+@@ -0,0 +1,162 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "avl.h"
++
++#ifdef AVL_CPLUSPLUS
++extern "C" {
++#endif
++
++ void ChunkAddr(AVL_uint32 uiaddr, AVL_puchar pBuff)
++ {
++ pBuff[0] =(AVL_uchar)(uiaddr>>16);
++ pBuff[1] =(AVL_uchar)(uiaddr>>8);
++ pBuff[2] =(AVL_uchar)(uiaddr);
++ return ;
++ }
++
++ void Chunk16(AVL_uint16 uidata, AVL_puchar pBuff)
++ {
++ pBuff[0] = (AVL_uchar)(uidata>>8);
++ pBuff[1] = (AVL_uchar)(uidata & 0xff);
++ return ;
++ }
++
++ AVL_uint16 DeChunk16(const AVL_puchar pBuff)
++ {
++ AVL_uint16 uiData;
++ uiData = pBuff[0];
++ uiData = (AVL_uint16)(uiData << 8) + pBuff[1];
++ return uiData;
++ }
++
++ void Chunk32(AVL_uint32 uidata, AVL_puchar pBuff)
++ {
++ pBuff[0] = (AVL_uchar)(uidata>>24);
++ pBuff[1] = (AVL_uchar)(uidata>>16);
++ pBuff[2] = (AVL_uchar)(uidata>>8);
++ pBuff[3] = (AVL_uchar)(uidata);
++ return ;
++ }
++
++ AVL_uint32 DeChunk32(const AVL_puchar pBuff)
++ {
++ AVL_uint32 uiData;
++ uiData = pBuff[0];
++ uiData = (uiData << 8) + pBuff[1];
++ uiData = (uiData << 8) + pBuff[2];
++ uiData = (uiData << 8) + pBuff[3];
++ return uiData;
++ }
++
++ void Add32To64(struct AVL_uint64 *pSum, AVL_uint32 uiAddend)
++ {
++ AVL_uint32 uiTemp;
++
++ uiTemp = pSum->m_LowWord;
++ pSum->m_LowWord += uiAddend;
++ pSum->m_LowWord &= 0xFFFFFFFF;
++
++ if (pSum->m_LowWord < uiTemp)
++ {
++ pSum->m_HighWord++;
++ }
++ }
++
++ AVL_uint32 Divide64(struct AVL_uint64 divisor, struct AVL_uint64 dividend)
++ {
++ AVL_uint32 uFlag = 0x0;
++ AVL_uint32 uQuto = 0x0;
++ AVL_uint32 i = 0;
++ AVL_uint32 dividend_H = dividend.m_HighWord;
++ AVL_uint32 dividend_L = dividend.m_LowWord;
++ AVL_uint32 divisor_H = divisor.m_HighWord;
++ AVL_uint32 divisor_L = divisor.m_LowWord;
++
++ if(((divisor_H == 0x0) && (divisor_L == 0x0)) || (dividend_H/divisor_L))
++ {
++ return 0;
++ }
++ else if((divisor_H == 0x0)&&(dividend_H == 0x0))
++ {
++ return dividend_L / divisor_L;
++ }
++ else
++ {
++ if(divisor_H != 0)
++ {
++ while(divisor_H)
++ {
++ dividend_L /= 2;
++ if(dividend_H % 2)
++ {
++ dividend_L += 0x80000000;
++ }
++ dividend_H /= 2;
++
++ divisor_L /= 2;
++ if(divisor_H %2)
++ {
++ divisor_L += 0x80000000;
++ }
++ divisor_H /= 2;
++ }
++ }
++ for (i = 0; i <= 31; i++)
++ {
++
++ uFlag = (AVL_int32)dividend_H >> 31;
++
++ dividend_H = (dividend_H << 1)|(dividend_L >> 31);
++ dividend_L <<= 1;
++
++ uQuto <<= 1;
++ if((dividend_H|uFlag) >= divisor_L)
++ {
++ dividend_H -= divisor_L;
++ uQuto++;
++ }
++ }
++ return uQuto;
++ }
++
++ }
++
++ void Multiply32(struct AVL_uint64 *pDst, AVL_uint32 m1, AVL_uint32 m2)
++ {
++ pDst->m_LowWord = (m1 & 0xFFFF) * (m2 & 0xFFFF);
++ pDst->m_HighWord = 0;
++
++ AddScaled32To64(pDst, (m1 >> 16) * (m2 & 0xFFFF));
++ AddScaled32To64(pDst, (m2 >> 16) * (m1 & 0xFFFF));
++
++ pDst->m_HighWord += (m1 >> 16) * (m2 >> 16);
++ }
++
++ void AddScaled32To64(struct AVL_uint64 *pDst, AVL_uint32 a)
++ {
++ AVL_uint32 saved;
++
++ saved = pDst->m_LowWord;
++ pDst->m_LowWord += (a << 16);
++
++ pDst->m_LowWord &= 0xFFFFFFFF;
++ pDst->m_HighWord += ((pDst->m_LowWord < saved) ? 1 : 0) + (a >> 16);
++ }
++
++
++#ifdef AVL_CPLUSPLUS
++}
++#endif
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/avl_dvbsx.c b/drivers/amlogic/dvb_tv/avl6211/src/avl_dvbsx.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/avl_dvbsx.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/avl_dvbsx.c 2014-12-11 16:13:50.473614685 +0100
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "avl.h"
++#include "avl_dvbsx.h"
++#include "IBSP.h"
++#include "II2C.h"
++
++AVL_DVBSx_ErrorCode Init_AVL_DVBSx_ChipObject(struct AVL_DVBSx_Chip * pAVL_DVBSx_ChipObject, AVL_uint16 uiSlaveAddress)
++{
++ AVL_DVBSx_ErrorCode r;
++ pAVL_DVBSx_ChipObject->m_SlaveAddr = uiSlaveAddress;
++ pAVL_DVBSx_ChipObject->m_StdBuffIndex = 0;
++ pAVL_DVBSx_ChipObject->Diseqc_OP_Status = AVL_DVBSx_DOS_Uninitialized;
++ r = AVL_DVBSx_IBSP_InitSemaphore(&(pAVL_DVBSx_ChipObject->m_semRx));
++ r |= AVL_DVBSx_IBSP_InitSemaphore(&(pAVL_DVBSx_ChipObject->m_semI2CRepeater));
++ r |= AVL_DVBSx_IBSP_InitSemaphore(&(pAVL_DVBSx_ChipObject->m_semI2CRepeater_r));
++ r |= AVL_DVBSx_IBSP_InitSemaphore(&(pAVL_DVBSx_ChipObject->m_semDiseqc));
++ r |= AVL_DVBSx_II2C_Initialize(); // there is a internal protection to assure it will be initialized only once.
++ return (r);
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/BlindScan_source.cpp b/drivers/amlogic/dvb_tv/avl6211/src/BlindScan_source.cpp
+--- a/drivers/amlogic/dvb_tv/avl6211/src/BlindScan_source.cpp 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/BlindScan_source.cpp 2014-12-11 16:13:50.377615419 +0100
+@@ -0,0 +1,610 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include
++#include "stdio.h"
++#include "IBSP.h"
++#include "avl_dvbsx.h"
++#include "IBase.h"
++#include "IRx.h"
++#include "ITuner.h"
++#include "ExtSharpBS2S7HZ6306.h"
++#include "II2C.h"
++#include "IDiseqc.h"
++#include "IBlindScan.h"
++#include "IBlindscanAPI.h"
++#include "BlindScan_source.h"
++
++extern AVL_uchar ucPatchData []; //Defined in AVL6211_patch.dat.cpp.
++
++#define Chip_ID 0x0F //0x01000002 //The Chip ID of AVL6211.
++#define bs_start_freq 950 //The start RF frequency, 950MHz
++#define bs_stop_freq 2150 //The stop RF frequency, 2150MHz
++#define Blindscan_Mode AVL_DVBSx_BS_Slow_Mode //The Blind scan mode. AVL_DVBSx_BS_Fast_Mode = 0,AVL_DVBSx_BS_Slow_Mode = 1
++#define Diseqc_Tone_Frequency 22 //The DiSEqC bus speed in the unit of kHz. Normally, it should be 22kHz.
++
++#define FontEnd_MaxCount 2
++struct AVL_DVBSx_Chip g_stAvlDVBSxChip[FontEnd_MaxCount];
++struct AVL_Tuner g_stTuner[FontEnd_MaxCount];
++enum AVL_Demod_ReferenceClock_Select_t
++{
++ Ref_clock_4M=0,
++ Ref_clock_4M5=1,
++ Ref_clock_10M=2,
++ Ref_clock_16M=3,
++ Ref_clock_27M=4,
++ Ref_clock_Enhance_4M=5,
++ Ref_clock_Enhance_4M5=6,
++ Ref_clock_Enhance_10M=7,
++ Ref_clock_Enhance_16M=8,
++ Ref_clock_Enhance_27M=9,
++};
++
++enum AVL_TunerLPF_Calculation_Flag
++{
++ InputLPF = 0,
++ InputSymbolRate = 1,
++};
++
++struct AVL_Demod_Tuner_Configuration_t
++{
++ ////////////////////////////Demod Configure///////////////////////////////
++
++ AVL_char m_ChannelId; ///< Bus identifier.
++ AVL_uint16 m_uiDemodAddress; ///< Device I2C slave address.
++ enum AVL_Demod_ReferenceClock_Select_t m_DemodReferenceClk; ///< Configures the Availink device's PLL.Refer to enum AVL_Demod_ReferenceClock_Select_t
++
++ ///< The MPEG output mode. The default value in the Availink device is \a AVL_DVBSx_MPM_Parallel
++ enum AVL_DVBSx_MpegMode m_TSOutPutMode; ///< AVL_DVBSx_MPM_Parallel = 0; Output MPEG data in parallel mode
++ ///< AVL_DVBSx_MPM_Serial = 1; Output MPEG data in serial mode
++
++ ///< The MPEG output clock polarity. The clock polarity should be configured to meet the back end device's requirement.The default value in the Availink device is \a AVL_DVBSx_MPCP_Rising.
++ enum AVL_DVBSx_MpegClockPolarity m_TSClockPolarity; ///< AVL_DVBSx_MPCP_Falling = 0; The MPEG data is valid on the falling edge of the clock.
++ ///< AVL_DVBSx_MPCP_Rising = 1; The MPEG data is valid on the rising edge of the clock.
++
++ ///< The MPEG output format. The default value in the Availink device is \a AVL_DVBSx_MPF_TS
++ enum AVL_DVBSx_MpegFormat m_TSFormat; ///< AVL_DVBSx_MPF_TS = 0; Transport stream format.
++ ///< AVL_DVBSx_MPF_TSP = 1; Transport stream plus parity format.
++
++ ///< Defines the pin on which the Availink device outputs the MPEG data when the MPEG interface has been configured to operate in serial mode.
++ enum AVL_DVBSx_MpegSerialPin m_SerDataPin; ///< AVL_DVBSx_MPSP_DATA0 = 0; Serial data is output on pin MPEG_DATA_0
++ ///< AVL_DVBSx_MPSP_DATA7 = 1; Serial data is output on pin MPEG_DATA_7
++
++ ////////////////////////////Tuner Configure///////////////////////////////
++
++ AVL_uint16 m_uiTunerAddress; ///< Tuner I2C slave address.
++ AVL_uint16 m_uiTuner_I2Cbus_clock; ///< The clock speed of the tuner dedicated I2C bus, in a unit of kHz.
++ AVL_uint16 m_uiTunerMaxLPF_100Khz; ///< The max low pass filter bandwidth of the tuner.
++
++ ///< Defines the LPF's forms of computation.
++ enum AVL_TunerLPF_Calculation_Flag m_LPF_Config_flag; ///< InputLPF = 0; The LPF will be calculated by formula which defined by user.
++ ///< InputSymbolRate = 1; The LPF will be calculated in tuner driver according to the SymbolRate.
++
++ ///< Defines the polarity of the RF AGC control signal.The polarity of the RF AGC control signal must be configured to match that required by the tuner.
++ enum AVL_DVBSx_RfagcPola m_TunerRFAGC; ///< AVL_DVBSx_RA_Normal = 0; Normal polarization. This setting is used for a tuner whose gain increases with increased AGC voltage.
++ ///< AVL_DVBSx_RA_Invert = 1; Inverted polarization. The default value. Most tuners fall into this category. This setting is used for a tuner whose gain decreases with increased AGC voltage.
++
++ ///< Defines the device spectrum polarity setting.
++ enum AVL_DVBSx_SpectrumPolarity m_Tuner_IQ_SpectrumMode; ///< AVL_DVBSx_Spectrum_Normal = 0; The received signal spectrum is not inverted.
++ ///< AVL_DVBSx_Spectrum_Invert = 1; The received signal spectrum is inverted.
++
++ AVL_DVBSx_ErrorCode (* m_pInitializeFunc)(struct AVL_Tuner *); ///< A pointer to the tuner initialization function.
++ AVL_DVBSx_ErrorCode (* m_pGetLockStatusFunc)(struct AVL_Tuner *); ///< A pointer to the tuner GetLockStatus function.
++ AVL_DVBSx_ErrorCode (* m_pLockFunc)(struct AVL_Tuner *); ///< A pointer to the tuner Lock function.
++};
++
++
++/*Here please according to customer needs, defining the array index*/
++
++static AVL_char g_nDemodTunerArrayIndex = 0;
++
++struct AVL_Demod_Tuner_Configuration_t g_DemodTuner_Config[]=
++{
++ {
++ 0,
++ AVL_DVBSx_SA_0,
++ Ref_clock_10M,
++ AVL_DVBSx_MPM_Parallel,
++ AVL_DVBSx_MPCP_Rising,
++ AVL_DVBSx_MPF_TSP,
++ AVL_DVBSx_MPSP_DATA0,
++
++ 0xC0,
++ 200,
++ 340,
++ InputLPF,
++ AVL_DVBSx_RA_Invert,
++ AVL_DVBSx_Spectrum_Normal,
++ &ExtSharpBS2S7HZ6306_Initialize,
++ &ExtSharpBS2S7HZ6306_GetLockStatus,
++ &ExtSharpBS2S7HZ6306_Lock,
++ },
++ {
++ 1,
++ AVL_DVBSx_SA_0,
++ Ref_clock_10M,
++ AVL_DVBSx_MPM_Parallel,
++ AVL_DVBSx_MPCP_Rising,
++ AVL_DVBSx_MPF_TSP,
++ AVL_DVBSx_MPSP_DATA0,
++
++ 0xC0,
++ 200,
++ 340,
++ InputLPF,
++ AVL_DVBSx_RA_Invert,
++ AVL_DVBSx_Spectrum_Normal,
++ &ExtSharpBS2S7HZ6306_Initialize,
++ &ExtSharpBS2S7HZ6306_GetLockStatus,
++ &ExtSharpBS2S7HZ6306_Lock,
++ },
++};
++
++void AVL_DVBSx_Error_Dispose(AVL_DVBSx_ErrorCode r)
++{
++ switch(r)
++ {
++ case AVL_DVBSx_EC_OK:
++ printf("AVL_DVBSx_EC_OK !\n");
++ break;
++ case AVL_DVBSx_EC_GeneralFail:
++ printf("AVL_DVBSx_EC_GeneralFail !\n");
++ break;
++ case AVL_DVBSx_EC_I2CFail:
++ printf("AVL_DVBSx_EC_I2CFail !\n");
++ break;
++ case AVL_DVBSx_EC_TimeOut:
++ printf("AVL_DVBSx_EC_TimeOut !\n");
++ break;
++ case AVL_DVBSx_EC_Running:
++ printf("AVL_DVBSx_EC_Running !\n");
++ break;
++ case AVL_DVBSx_EC_InSleepMode:
++ printf("AVL_DVBSx_EC_InSleepMode !\n");
++ break;
++ case AVL_DVBSx_EC_MemoryRunout:
++ printf("AVL_DVBSx_EC_MemoryRunout !\n");
++ break;
++ case AVL_DVBSx_EC_BSP_ERROR1:
++ printf("AVL_DVBSx_EC_BSP_ERROR1 !\n");
++ break;
++ case AVL_DVBSx_EC_BSP_ERROR2:
++ printf("AVL_DVBSx_EC_BSP_ERROR2 !\n");
++ break;
++ }
++}
++
++AVL_DVBSx_ErrorCode CPU_Halt(struct AVL_DVBSx_Chip * pAVLChip)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint16 i= 0;
++
++ r = AVL_DVBSx_IBase_SendRxOP(OP_RX_HALT, pAVLChip );
++
++ if(AVL_DVBSx_EC_OK == r)
++ {
++ while(i++<20)
++ {
++ r = AVL_DVBSx_IBase_GetRxOPStatus(pAVLChip);
++ if(AVL_DVBSx_EC_OK == r)
++ {
++ break;
++ }
++ else
++ {
++ AVL_DVBSx_IBSP_Delay(10);
++ }
++ }
++ }
++ return (r);
++}
++
++static void AVL_Set_LPF(struct AVL_Tuner * pTuner)
++{
++ struct AVL_Demod_Tuner_Configuration_t *pDemodTunerConfig = &g_DemodTuner_Config[g_nDemodTunerArrayIndex];
++
++ if (pDemodTunerConfig->m_LPF_Config_flag == InputSymbolRate)
++ {
++ pTuner->m_uiLPF_100kHz = pTuner->m_uiSymbolRate_Hz;
++ }
++ else
++ {
++ pTuner->m_uiLPF_100kHz = pTuner->m_uiSymbolRate_Hz*75/10000000+40;
++ }
++
++ if(pTuner->m_uiLPF_100kHz > pDemodTunerConfig->m_uiTunerMaxLPF_100Khz)
++ {
++ pTuner->m_uiLPF_100kHz = pDemodTunerConfig->m_uiTunerMaxLPF_100Khz;
++ }
++
++}
++
++AVL_DVBSx_ErrorCode AVL_Lock(struct AVL_DVBSx_Chip * pAVLChip,struct AVL_Tuner * pTuner,struct AVL_DVBSx_Channel * pChannel,AVL_uint16 * uiLockStatus)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_Channel Channel;
++ AVL_uint16 uiCounter;
++
++ pTuner->m_uiFrequency_100kHz = pChannel->m_uiFrequency_kHz/100;
++ pTuner->m_uiSymbolRate_Hz = pChannel->m_uiSymbolRate_Hz;
++ AVL_Set_LPF(pTuner);
++ r = pTuner->m_pLockFunc(pTuner);
++
++ AVL_DVBSx_IBSP_Delay(50); //Wait a while for tuner to lock in certain frequency.
++
++ Channel.m_uiSymbolRate_Hz = pChannel->m_uiSymbolRate_Hz;
++ Channel.m_Flags = (CI_FLAG_IQ_NO_SWAPPED) << CI_FLAG_IQ_BIT; //Normal IQ
++ Channel.m_Flags |= (CI_FLAG_IQ_AUTO_BIT_AUTO) << CI_FLAG_IQ_AUTO_BIT; //Enable automatic IQ swap detection
++ Channel.m_Flags |= (CI_FLAG_DVBS2_UNDEF) << CI_FLAG_DVBS2_BIT; //Enable automatic standard detection
++
++ //This function should be called after tuner locked to lock the channel.
++ r |= AVL_DVBSx_IRx_LockChannel(&Channel, pAVLChip);
++
++ //------------------------Check if Channel was locked-----------------------------
++ if(Channel.m_uiSymbolRate_Hz < 5000000)
++ uiCounter = 25;
++ else if(Channel.m_uiSymbolRate_Hz < 10000000)
++ uiCounter = 12;
++ else
++ uiCounter = 5;
++
++ do
++ {
++ AVL_DVBSx_IBSP_Delay(100); //Wait 100ms for demod to lock the channel.
++
++ r = AVL_DVBSx_IRx_GetLockStatus(uiLockStatus, pAVLChip);
++
++ if ((AVL_DVBSx_EC_OK == r)&&(1 == *uiLockStatus))
++ break;
++ }while(--uiCounter);
++ //--------------------------------------------------------------------------------
++
++ return r;
++}
++
++void AVL_Display_TP_Info(struct AVL_DVBSx_Channel * pChannel, AVL_uint16 Channel_Num)
++{
++ AVL_uint16 i;
++ printf("\n\n");
++ for(i=0; i < Channel_Num; i++)
++ {
++ printf("Ch%2d: RF: %4d SR: %5d ",i+1, (pChannel[i].m_uiFrequency_kHz/1000),(pChannel[i].m_uiSymbolRate_Hz/1000));
++ switch((pChannel[i].m_Flags & CI_FLAG_DVBS2_BIT_MASK) >> CI_FLAG_DVBS2_BIT)
++ {
++ case CI_FLAG_DVBS:
++ printf(" DVBS ");
++ break;
++ case CI_FLAG_DVBS2:
++ printf(" DVBS2 ");
++ break;
++ case CI_FLAG_DVBS2_UNDEF:
++ printf("Unknown ");
++ break;
++ }
++ switch((pChannel[i].m_Flags & CI_FLAG_IQ_BIT_MASK)>>CI_FLAG_IQ_BIT)
++ {
++ case CI_FLAG_IQ_NO_SWAPPED:
++ printf("Normal ");
++ break;
++ case CI_FLAG_IQ_SWAPPED:
++ printf("Invert ");
++ break;
++ }
++ printf("\n");
++ }
++}
++
++AVL_DVBSx_ErrorCode Initialize(struct AVL_DVBSx_Chip * pAVLChip,struct AVL_Tuner * pTuner)
++{
++ struct AVL_DVBSx_Diseqc_Para sDiseqcPara;
++ struct AVL_DVBSx_MpegInfo sMpegMode;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_Demod_Tuner_Configuration_t *pDemodTunerConfig = &g_DemodTuner_Config[g_nDemodTunerArrayIndex];
++ struct AVL_DVBSx_VerInfo VerInfo;
++ //AVL_uint32 uiTemp;
++ AVL_uint32 uiDeviceID=0;
++
++#if 0
++ //This function should be implemented by customer.
++ //This function should be called before all other functions to prepare everything for a BSP operation.
++ r = AVL_DVBSx_IBSP_Initialize();
++
++ if( AVL_DVBSx_EC_OK !=r )
++ {
++ printf("BSP Initialization failed !\n");
++ return (r);
++ }
++#endif
++
++ pAVLChip->m_uiBusId=pDemodTunerConfig->m_ChannelId;
++
++ // This function should be called after bsp initialized to initialize the chip object.
++ r = Init_AVL_DVBSx_ChipObject(pAVLChip, pDemodTunerConfig->m_uiDemodAddress);
++ if( AVL_DVBSx_EC_OK !=r )
++ {
++ printf("Chip Object Initialization failed !\n");
++ return (r);
++ }
++
++ //Judge the chip ID of current chip.
++ r= AVL_DVBSx_IRx_GetDeviceID( pAVLChip, &uiDeviceID);
++ //r = AVL_DVBSx_II2C_Read32(pAVLChip, rom_ver_addr, &uiTemp);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Get Chip ID failed !\n");
++ return (r);
++ }
++ //if ( uiTemp != Chip_ID )
++ if(uiDeviceID != Chip_ID )
++ {
++ printf("Chip ID isn't correct !\n");
++ return AVL_DVBSx_EC_GeneralFail;
++ }
++
++ //This function should be called after chip object initialized to initialize the IBase,using reference clock as 10M. Make sure you pickup the right pll_conf since it may be modified in BSP.
++ r = AVL_DVBSx_IBase_Initialize(&(pll_conf[pDemodTunerConfig->m_DemodReferenceClk]), ucPatchData, pAVLChip);
++ if( AVL_DVBSx_EC_OK !=r )
++ {
++ printf("IBase Initialization failed !\n");
++ return (r);
++ }
++ AVL_DVBSx_IBSP_Delay(100); //Wait 100 ms to assure that the AVL_DVBSx chip boots up.This function should be implemented by customer.
++
++ //This function should be called to verify the AVL_DVBSx chip has completed its initialization procedure.
++ r = AVL_DVBSx_IBase_GetStatus(pAVLChip);
++ if( AVL_DVBSx_EC_OK != r )
++ {
++ printf("Booted failed !\n");
++ return (r);
++ }
++ printf("Booted !\n");
++
++ //Get Chip ID, Patch version and SDK version.
++ AVL_DVBSx_IBase_GetVersion( &VerInfo, pAVLChip);
++ printf("Chip Ver:{%d}.{%d}.{%d} API Ver:{%d}.{%d}.{%d} Patch Ver:{%d}.{%d}.{%d} \n",
++ VerInfo.m_Chip.m_Major, VerInfo.m_Chip.m_Minor, VerInfo.m_Chip.m_Build,
++ VerInfo.m_API.m_Major, VerInfo.m_API.m_Minor, VerInfo.m_API.m_Build,
++ VerInfo.m_Patch.m_Major, VerInfo.m_Patch.m_Minor, VerInfo.m_Patch.m_Build);
++
++ //This function should be called after IBase initialized to initialize the demod.
++ r = AVL_DVBSx_IRx_Initialize(pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Demod Initialization failed !\n");
++ return (r);
++ }
++
++ //This function should be called after demod initialized to set RF AGC polar.
++ //User does not need to setup this for Sharp tuner since it is the default value. But for other tuners, user may need to do it here.
++ r |= AVL_DVBSx_IRx_SetRFAGCPola(pDemodTunerConfig->m_TunerRFAGC, pAVLChip);
++ r |= AVL_DVBSx_IRx_DriveRFAGC(pAVLChip);
++
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set RF AGC Polar failed !\n");
++ return (r);
++ }
++
++ //This function should be called after demod initialized to set spectrum polar.
++ r = AVL_DVBSx_IBase_SetSpectrumPolarity(pDemodTunerConfig->m_Tuner_IQ_SpectrumMode, pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set Spectrum Polar failed !\n");
++ return (r);
++ }
++
++ //Setup MPEG mode parameters.
++ sMpegMode.m_MpegFormat = pDemodTunerConfig->m_TSFormat;
++ sMpegMode.m_MpegMode = pDemodTunerConfig->m_TSOutPutMode;
++ sMpegMode.m_MpegClockPolarity = pDemodTunerConfig->m_TSClockPolarity;
++
++ //This function should be called after demod initialized to set MPEG mode.(These parameters will be valid after call lock channel function)
++ r = AVL_DVBSx_IRx_SetMpegMode(&sMpegMode,pAVLChip );
++
++ if(sMpegMode.m_MpegMode == AVL_DVBSx_MPM_Serial)
++ {
++ AVL_DVBSx_IRx_SetMpegSerialPin(pAVLChip,pDemodTunerConfig->m_SerDataPin);
++ }
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set MPEG output mode failed !\n");
++ return (r);
++ }
++
++ // Enable the MPEG output (this function call has no effect for the AVL_DVBSxLG and AVL_DVBSxLGa devices)
++ r = AVL_DVBSx_IRx_DriveMpegOutput(pAVLChip);
++
++ //Setup tuner parameters for tuner initialization.
++ pTuner->m_uiSlaveAddress = pDemodTunerConfig->m_uiTunerAddress;
++ pTuner->m_uiI2CBusClock_kHz = pDemodTunerConfig->m_uiTuner_I2Cbus_clock;
++ pTuner->m_pParameters = 0;
++ pTuner->m_pAVLChip = pAVLChip;
++ pTuner->m_pInitializeFunc = pDemodTunerConfig->m_pInitializeFunc;
++ pTuner->m_pLockFunc = pDemodTunerConfig->m_pLockFunc;
++ pTuner->m_pGetLockStatusFunc = pDemodTunerConfig->m_pGetLockStatusFunc;
++
++ //This function should be called after IBase initialized to initialize the tuner.
++ r = pTuner->m_pInitializeFunc(pTuner);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Tuner Initialization failed !\n");
++ return (r);
++ }
++
++ //Setup DiSEqC parameters for DiSEqC initialization.
++ sDiseqcPara.m_RxTimeout = AVL_DVBSx_DRT_150ms;
++ sDiseqcPara.m_RxWaveForm = AVL_DVBSx_DWM_Normal;
++ sDiseqcPara.m_ToneFrequency_kHz = Diseqc_Tone_Frequency;
++ sDiseqcPara.m_TXGap = AVL_DVBSx_DTXG_15ms;
++ sDiseqcPara.m_TxWaveForm = AVL_DVBSx_DWM_Normal;
++
++ //The DiSEqC should be initialized if AVL_DVBSx need to supply power to LNB. This function should be called after IBase initialized to initialize the DiSEqC.
++ r = AVL_DVBSx_IDiseqc_Initialize(&sDiseqcPara, pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("DiSEqC Initialization failed !\n");
++ }
++
++ return (r);
++}
++
++AVL_DVBSx_ErrorCode BlindScan(void)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 index = 0;
++ struct AVL_DVBSx_Channel * pChannel;
++ AVL_uchar HandIndex = 0;
++ struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ struct AVL_Tuner * pTuner = &g_stTuner[HandIndex];
++ struct AVL_DVBSx_BlindScanAPI_Setting BSsetting;
++ enum AVL_DVBSx_BlindScanAPI_Status BS_Status;
++ struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting = &BSsetting;
++ struct AVL_Demod_Tuner_Configuration_t *pDemodTunerConfig = &g_DemodTuner_Config[g_nDemodTunerArrayIndex];
++ BS_Status = AVL_DVBSx_BS_Status_Init;
++
++ //This function do all the initialization work.It should be called only once at the beginning.It needn't be recalled when we want to lock a new channel.
++ r = Initialize(pAVLChip,pTuner);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Initialization failed !\n");
++ return (r);
++ }
++ printf("Initialization success !\n");
++
++ while(BS_Status != AVL_DVBSx_BS_Status_Exit)
++ {
++ switch(BS_Status)
++ {
++ case AVL_DVBSx_BS_Status_Init: {
++ AVL_DVBSx_IBlindScanAPI_Initialize(pBSsetting);//this function set the parameters blind scan process needed.
++
++ AVL_DVBSx_IBlindScanAPI_SetFreqRange(pBSsetting, bs_start_freq, bs_stop_freq); //Default scan rang is from 950 to 2150. User may call this function to change scan frequency rang.
++ AVL_DVBSx_IBlindScanAPI_SetScanMode(pBSsetting, Blindscan_Mode);
++
++ AVL_DVBSx_IBlindScanAPI_SetSpectrumMode(pBSsetting, pDemodTunerConfig->m_Tuner_IQ_SpectrumMode); //Default set is AVL_DVBSx_Spectrum_Normal, it must be set correctly according Board HW configuration
++ AVL_DVBSx_IBlindScanAPI_SetMaxLPF(pBSsetting, pDemodTunerConfig->m_uiTunerMaxLPF_100Khz); //Set Tuner max LPF value, this value will difference according tuner type
++
++ BS_Status = AVL_DVBSx_BS_Status_Start;
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Start: {
++ r = AVL_DVBSx_IBlindScanAPI_Start(pAVLChip, pTuner, pBSsetting);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ }
++ BS_Status = AVL_DVBSx_BS_Status_Wait;
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Wait: {
++ r = AVL_DVBSx_IBlindScanAPI_GetCurrentScanStatus(pAVLChip, pBSsetting);
++ if(AVL_DVBSx_EC_GeneralFail == r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ }
++ if(AVL_DVBSx_EC_OK == r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Adjust;
++ }
++ if(AVL_DVBSx_EC_Running == r)
++ {
++ AVL_DVBSx_IBSP_Delay(100);
++ }
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Adjust: {
++ r = AVL_DVBSx_IBlindScanAPI_Adjust(pAVLChip, pBSsetting);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ }
++ BS_Status = AVL_DVBSx_BS_Status_User_Process;
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_User_Process: {
++ //------------Custom code start-------------------
++ //customer can add the callback function here such as adding TP information to TP list or lock the TP for parsing PSI
++ //Add custom code here; Following code is an example
++
++ /*----- example 1: print Blindscan progress ----*/
++ printf(" %2d%% \n", AVL_DVBSx_IBlindscanAPI_GetProgress(pBSsetting)); //display progress Percent of blindscan process
++
++ /*----- example 2: print TP information if found valid TP ----*/
++ while(index < pBSsetting->m_uiChannelCount) //display new TP info found in current stage
++ {
++ pChannel = &pBSsetting->channels[index++];
++ printf(" Ch%2d: RF: %4d SR: %5d ",index, (pChannel->m_uiFrequency_kHz/1000),(pChannel->m_uiSymbolRate_Hz/1000));
++
++ #if 0 //Lock signal for testing
++ AVL_uint16 uiLockStatus = 0;
++ struct AVL_DVBSx_Channel channel;
++
++ channel.m_uiFrequency_kHz = pChannel->m_uiFrequency_kHz;
++ channel.m_uiSymbolRate_Hz = pChannel->m_uiSymbolRate_Hz;
++
++ AVL_Lock(pAVLChip, pTuner, &channel, &uiLockStatus);
++ if(uiLockStatus)
++ printf("Locked!");
++ else
++ printf("Unlock!");
++ #endif
++ printf("\n");
++ }
++ index = pBSsetting->m_uiChannelCount;
++
++ /*----- example 3: Break blindscan process when check key pressed ----*/
++ #if 0
++ if ( _kbhit() ) // demonstrate blindscan exit while process status machine is running
++ {
++ if( _getch() == 'e' )
++ {
++ printf("Exit by user.\n");
++ BS_Status = Blindscan_Status_Cancel;
++ break;
++ }
++ }
++ #endif
++ //------------Custom code end -------------------
++
++ if ( (AVL_DVBSx_IBlindscanAPI_GetProgress(pBSsetting) < 100))
++ BS_Status = AVL_DVBSx_BS_Status_Start;
++ else
++ BS_Status = AVL_DVBSx_BS_Status_Cancel;
++ break;
++ }
++
++ case AVL_DVBSx_BS_Status_Cancel: {
++ r = AVL_DVBSx_IBlindScanAPI_Exit(pAVLChip,pBSsetting);
++ BS_Status = AVL_DVBSx_BS_Status_Exit;
++ break;
++ }
++
++ default: {
++ BS_Status = AVL_DVBSx_BS_Status_Cancel;
++ break;
++ }
++ }
++ }
++
++ //print all of the TP info found in blindscan process. this isn't necessary for the customer
++ AVL_Display_TP_Info(pBSsetting->channels,pBSsetting->m_uiChannelCount);
++
++ //-------------------------Blindscan Band Process End------------------------
++ return (r);
++
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/DiSEqC_source.c b/drivers/amlogic/dvb_tv/avl6211/src/DiSEqC_source.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/DiSEqC_source.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/DiSEqC_source.c 2014-12-11 16:13:50.437614960 +0100
+@@ -0,0 +1,452 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++//#include "stdio.h"
++#include "IBSP.h"
++#include "avl_dvbsx.h"
++#include "IBase.h"
++#include "IRx.h"
++#include "II2C.h"
++#include "IDiseqc.h"
++#include "DiSEqC_source.h"
++
++extern AVL_uchar ucPatchData[]; //defined in AVL6211_patch.dat.cpp
++static struct AVL_DVBSx_Chip AVL_DVBSxChip;
++#define Chip_ID 0x0F //0x01000002 //The Chip ID of AVL6211.
++#define DiSEqC_Tone_Frequency 22 // The DiSEqC bus speed in the unit of kHz. Normally, it should be 22kHz.
++#define EAST 0
++#define WEST 1
++
++/*void AVL_DVBSx_Error_Dispose(AVL_DVBSx_ErrorCode r)
++{
++ switch(r)
++ {
++ case AVL_DVBSx_EC_OK:
++ printf("AVL_DVBSx_EC_OK !\n");
++ break;
++ case AVL_DVBSx_EC_GeneralFail:
++ printf("AVL_DVBSx_EC_GeneralFail !\n");
++ break;
++ case AVL_DVBSx_EC_I2CFail:
++ printf("AVL_DVBSx_EC_I2CFail !\n");
++ break;
++ case AVL_DVBSx_EC_TimeOut:
++ printf("AVL_DVBSx_EC_TimeOut !\n");
++ break;
++ case AVL_DVBSx_EC_Running:
++ printf("AVL_DVBSx_EC_Running !\n");
++ break;
++ case AVL_DVBSx_EC_InSleepMode:
++ printf("AVL_DVBSx_EC_InSleepMode !\n");
++ break;
++ case AVL_DVBSx_EC_MemoryRunout:
++ printf("AVL_DVBSx_EC_MemoryRunout !\n");
++ break;
++ case AVL_DVBSx_EC_BSP_ERROR1:
++ printf("AVL_DVBSx_EC_BSP_ERROR1 !\n");
++ break;
++ case AVL_DVBSx_EC_BSP_ERROR2:
++ printf("AVL_DVBSx_EC_BSP_ERROR2 !\n");
++ break;
++ }
++}*/
++AVL_DVBSx_ErrorCode AVL6211_22K_Control(AVL_uchar OnOff)
++{
++ AVL_DVBSx_ErrorCode r=AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_Chip * pAVLChip = &AVL_DVBSxChip;
++ if(OnOff)
++ {
++ r=AVL_DVBSx_IDiseqc_StartContinuous(pAVLChip);
++ }else{
++ r=AVL_DVBSx_IDiseqc_StopContinuous(pAVLChip);
++ }
++ if(r!=AVL_DVBSx_EC_OK)
++ {
++ printf("[AVL6211_22K_Control] Err:0x%x\n",r);
++ }
++ return r;
++}
++AVL_DVBSx_ErrorCode AVL6211_SetToneOut(AVL_uchar ucTone)
++{
++ AVL_DVBSx_ErrorCode r=AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_Diseqc_TxStatus TxStatus;
++ struct AVL_DVBSx_Chip * pAVLChip = &AVL_DVBSxChip;
++ AVL_DVBSx_IDiseqc_SendTone( ucTone, 1, pAVLChip);
++ if(r != AVL_DVBSx_EC_OK)
++ {
++ printf("AVL_DVBSx_IDiseqc_SendTone failed !\n");
++ }
++ else
++ {
++ do
++ {
++ r= AVL_DVBSx_IDiseqc_GetTxStatus(&TxStatus, pAVLChip);
++ }while(TxStatus.m_TxDone != 1);
++ if(r ==AVL_DVBSx_EC_OK )
++ {
++
++ }
++ else
++ {
++ printf("AVL_DVBSx_IDiseqc_SendTone Err. !\n");
++ }
++ }
++ return r;
++
++}
++void AVL6211_DiseqcSendCmd(AVL_puchar pCmd,AVL_uchar CmdSize)
++{
++ AVL_DVBSx_ErrorCode r=AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_Diseqc_TxStatus TxStatus;
++ struct AVL_DVBSx_Chip * pAVLChip = &AVL_DVBSxChip;
++
++ r=AVL_DVBSx_IDiseqc_SendModulationData(pCmd, CmdSize, pAVLChip);
++ if(r != AVL_DVBSx_EC_OK)
++ {
++ printf("AVL_DVBSx_IDiseqc_SendModulationData failed !\n");
++ }
++ else
++ {
++ do
++ {
++ r= AVL_DVBSx_IDiseqc_GetTxStatus(&TxStatus, pAVLChip);
++ }while(TxStatus.m_TxDone != 1);
++ if(r ==AVL_DVBSx_EC_OK )
++ {
++
++ }
++ else
++ {
++ printf("AVL_DVBSx_IDiseqc_SendModulationData Err. !\n");
++ }
++ }
++}
++
++
++AVL_DVBSx_ErrorCode AVL6211_LNB_PIO_Control(AVL_char nPIN_Index,AVL_char nValue)
++{
++ struct AVL_DVBSx_Chip * pAVLChip = &AVL_DVBSxChip;
++ AVL_DVBSx_ErrorCode r=AVL_DVBSx_EC_OK;
++ if(nPIN_Index == LNB1_PIN_60)
++ {
++ if(nValue)
++ r=AVL_DVBSx_IDiseqc_SetLNB1Out(1,pAVLChip);//set LNB1_PIN60 1: Hight
++ else
++ r=AVL_DVBSx_IDiseqc_SetLNB1Out(0,pAVLChip); //set LNB1_PIN60 1: Low
++ }
++ else if(nPIN_Index == LNB0_PIN_59)
++ {
++ if(nValue)
++ r=AVL_DVBSx_IDiseqc_SetLNBOut(1,pAVLChip);//set LNB0_PIN59 1: Hight
++ else
++ r=AVL_DVBSx_IDiseqc_SetLNBOut(0,pAVLChip); //set LNB0_PIN59 1: Low
++ }
++
++ if(r!=AVL_DVBSx_EC_OK)
++ {
++ printf("[AVL6211_LNB_PIO_Control] set nPIN_Index:0x%x,Err\n",r);
++ }
++ return r;
++}
++#if 0
++AVL_DVBSx_ErrorCode Initialize(struct AVL_DVBSx_Chip * pAVLChip)
++{
++ struct AVL_DVBSx_Diseqc_Para sDiseqcPara;
++ AVL_DVBSx_ErrorCode r=AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_VerInfo VerInfo;
++ //AVL_uint32 uiTemp;
++ AVL_uint32 uiDeviceID=0;
++/*
++ //This function should be implemented by customer.
++ //This function should be called before all other functions to prepare everything for a BSP operation.
++ r = AVL_DVBSx_IBSP_Initialize();
++ if( AVL_DVBSx_EC_OK !=r )
++ {
++ printf("BSP Initialization failed !\n");
++ return (r);
++ }
++*/
++
++ // This function should be called after bsp initialized to initialize the chip object.
++ r = Init_AVL_DVBSx_ChipObject(pAVLChip, AVL_DVBSx_SA_0);
++ if( AVL_DVBSx_EC_OK !=r )
++ {
++ printf("Chip Object Initialization failed !\n");
++ return (r);
++ }
++
++ //Judge the chip ID of current chip.
++ r= AVL_DVBSx_IRx_GetDeviceID( pAVLChip, &uiDeviceID);
++ //r = AVL_DVBSx_II2C_Read32(pAVLChip, rom_ver_addr, &uiTemp);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Get Chip ID failed !\n");
++ return (r);
++ }
++ //if ( uiTemp != Chip_ID )
++ if(uiDeviceID != Chip_ID )
++ {
++ printf("uiDeviceID:0x%x,Chip ID isn't correct!\n",uiDeviceID);
++ return AVL_DVBSx_EC_GeneralFail;
++ }
++
++
++ //This function should be called after chip object initialized to initialize the IBase,using reference clock as 10M. Make sure you pickup the right pll_conf since it may be modified in BSP.
++ r = AVL_DVBSx_IBase_Initialize(const_cast(pll_conf+2), ucPatchData, pAVLChip);
++ if( AVL_DVBSx_EC_OK !=r )
++ {
++ printf("IBase Initialization failed !\n");
++ return (r);
++ }
++ AVL_DVBSx_IBSP_Delay(100); //Wait 100 ms to assure that the AVLDVBSx chip boots up.This function should be implemented by customer.
++
++ //This function should be called to verify the AVLDVBSx chip has completed its initialization procedure.
++ r = AVL_DVBSx_IBase_GetStatus(pAVLChip);
++ if( AVL_DVBSx_EC_OK != r )
++ {
++ printf("Booted failed !\n");
++ return (r);
++ }
++ printf("Booted !\n");
++
++ //Get Chip ID, Patch version and SDK version.
++ AVL_DVBSx_IBase_GetVersion( &VerInfo, pAVLChip);
++ printf("Chip Ver:{%d}.{%d}.{%d} API Ver:{%d}.{%d}.{%d} Patch Ver:{%d}.{%d}.{%d} \n",
++ VerInfo.m_Chip.m_Major, VerInfo.m_Chip.m_Minor, VerInfo.m_Chip.m_Build,
++ VerInfo.m_API.m_Major, VerInfo.m_API.m_Minor, VerInfo.m_API.m_Build,
++ VerInfo.m_Patch.m_Major, VerInfo.m_Patch.m_Minor, VerInfo.m_Patch.m_Build);
++
++ //This function should be called after IBase initialized to initialize the demod.
++ r = AVL_DVBSx_IRx_Initialize(pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Demod Initialization failed !\n");
++ return (r);
++ }
++
++ //This function should be called after demod initialized to set RF AGC polar.
++ //User does not need to setup this for Sharp tuner since it is the default value. But for other tuners, user may need to do it here.
++ r |= AVL_DVBSx_IRx_SetRFAGCPola(AVL_DVBSx_RA_Invert, pAVLChip);
++ r |= AVL_DVBSx_IRx_DriveRFAGC(pAVLChip);
++
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set RF AGC Polar failed !\n");
++ return (r);
++ }
++
++ //This function should be called after demod initialized to set spectrum polar.
++ r = AVL_DVBSx_IBase_SetSpectrumPolarity(AVL_DVBSx_Spectrum_Normal, pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set Spectrum Polar failed !\n");
++ return (r);
++ }
++
++ //Setup DiSEqC parameters for DiSEqC initialization.
++ sDiseqcPara.m_RxTimeout = AVL_DVBSx_DRT_150ms;
++ sDiseqcPara.m_RxWaveForm = AVL_DVBSx_DWM_Normal;
++ sDiseqcPara.m_ToneFrequency_kHz = DiSEqC_Tone_Frequency;
++ sDiseqcPara.m_TXGap = AVL_DVBSx_DTXG_15ms;
++ sDiseqcPara.m_TxWaveForm = AVL_DVBSx_DWM_Normal;
++
++ //This function should be called after IBase initialized to initialize the DiSEqC.
++ r = AVL_DVBSx_IDiseqc_Initialize(&sDiseqcPara, pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("DiSEqC Initialization failed !\n");
++ }
++
++
++ return (r);
++}
++
++AVL_DVBSx_ErrorCode DiSEqC(void)
++{
++ struct AVL_DVBSx_Diseqc_TxStatus sTxStatus;
++ struct AVL_DVBSx_Diseqc_RxStatus sRxStatus;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uchar ucData[8];
++ AVL_uchar i,i1;
++
++ struct AVL_DVBSx_Chip * pAVLChip = &AVL_DVBSxChip;
++
++ //This function do all the initialization work. It should be called only once at the beginning.
++ r = Initialize(pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Initialization failed !\n");
++ return (r);
++ }
++ printf("Initialization success !\n");
++
++/*PIN 59/60 I/O Control exmples*/
++ r=AVL6211_LNB_PIO_Control(LNB0_PIN_59,1);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Set PIO 59 to 1,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(1000);
++ r=AVL6211_LNB_PIO_Control(LNB0_PIN_59,0);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Set PIO 59 to 0,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(1000);
++ r=AVL6211_LNB_PIO_Control(LNB1_PIN_60,1);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Set PIO 60 to 1,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(100);
++ r=AVL6211_LNB_PIO_Control(LNB1_PIN_60,0);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Set PIO 60 to 0,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(1000);
++
++//22K Control examples
++ r=AVL6211_22K_Control(1);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Set 22K On,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(1000);
++ r=AVL6211_22K_Control(0);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Set 22K Off,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(1000);
++//Send the tone burst command
++ r=AVL6211_SetToneOut(1);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Send ToneBurst 1,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(1000);
++ r=AVL6211_SetToneOut(0);
++ if(r== AVL_DVBSx_EC_OK)
++ {
++ printf("Send ToneBurst 0,OK\n");
++ }
++ AVL_DVBSx_IBSP_Delay(1000);
++
++ //LNB switch control
++ ucData[0]=0xE0;
++ ucData[1]=0x10;
++ ucData[2]=0x38;
++ ucData[3]=0xF0;
++
++ AVL_uchar uPortBit=0;
++ AVL_uchar uLNBPort = 1;
++
++ switch(uLNBPort)
++ {
++ case 1:
++ uPortBit=0;
++ break;
++
++ case 2:
++ uPortBit=0x04;
++ break;
++
++ case 3:
++ uPortBit=0x08;
++ break;
++
++ case 4:
++ uPortBit=0x0C;
++ break;
++
++ default:
++ uPortBit=0;
++ break;
++
++ }
++ ucData[3] += uPortBit;
++
++ //This function can be called after initialization to send out 4 modulation bytes to select the LNB port if used the 1/4 LNB switch.
++ AVL6211_DiseqcSendCmd(ucData, 4);
++
++
++ //Positioner control one degree.
++ ucData[0]=0xE0;
++ ucData[1]=0x31;
++ ucData[2]=0x68;
++ ucData[3]=0xFF;
++
++ AVL_uchar uDirection = EAST;
++ AVL_uchar uCommandByte;
++
++ switch(uDirection)
++ {
++ case EAST:
++ uCommandByte=0x68; //Turn east
++ break;
++
++ case WEST:
++ uCommandByte=0x69; //Turn west
++ break;
++
++ default:
++ uCommandByte=0x68;
++ break;
++
++ }
++
++ ucData[2] = uCommandByte;
++ AVL6211_DiseqcSendCmd(ucData, 4);
++
++ //Before receiving modulation data, we should send some request data first.
++ //Read input status.
++ do
++ {
++ r = AVL_DVBSx_IDiseqc_GetRxStatus(&sRxStatus, pAVLChip); //Get current status of the DiSEqC receiver.
++ }
++ while(1 != sRxStatus.m_RxDone); //Wait until operation finished.
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Read modulation bytes --- Fail!\n");
++ }
++ else
++ {
++ if(0 != sRxStatus.m_RxFifoCount) //Data received.
++ {
++ i = sRxStatus.m_RxFifoCount;
++ //This function can be called to read data back from the DiSEqC input FIFO when there are data received.
++ r = AVL_DVBSx_IDiseqc_ReadModulationData(ucData, &i, pAVLChip);
++ if(AVL_DVBSx_EC_OK == r)
++ {
++ printf("Received %u modulation bytes:",i);
++ for(i1=0; i134 )
++ {
++ uiLPF_10kHz = 34;
++ }
++ pTunerRegs->m_ucLPF = (AVL_uchar)((uiLPF_10kHz-10)/2+3);
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode SharpBS2S7HZ6306_SetBBGain( enum SharpBS2S7HZ6306_BBGain BBGain, struct SharpBS2S7HZ6306_Registers * pTunerRegs )
++{
++ pTunerRegs->m_ucRegData[0] &= ~(0x3<<5);
++ pTunerRegs->m_ucRegData[0] |= ((AVL_uchar)(BBGain)<<5);
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode SharpBS2S7HZ6306_SetChargePump( enum SharpBS2S7HZ6306_PumpCurrent Current, struct SharpBS2S7HZ6306_Registers * pTunerRegs )
++{
++ pTunerRegs->m_ucRegData[2] &= ~(0x3<<5);
++ pTunerRegs->m_ucRegData[2] |= ((AVL_uchar)(Current)<<5);
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode SharpBS2S7HZ6306_SetFrequency(AVL_uint16 uiFrequency_100kHz, struct SharpBS2S7HZ6306_Registers * pTunerRegs)
++{
++ AVL_uint16 P, N, A, DIV;
++ if( uiFrequency_100kHz<9500 )
++ {
++ return(AVL_DVBSx_EC_GeneralFail);
++ }
++ else if( uiFrequency_100kHz<9860 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x5<<5);
++ P = 16;
++ DIV = 1;
++ }
++ else if( uiFrequency_100kHz<10730 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x6<<5);
++ P = 16;
++ DIV = 1;
++ }
++ else if( uiFrequency_100kHz<11540 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x7<<5);
++ P = 32;
++ DIV = 1;
++ }
++ else if( uiFrequency_100kHz<12910 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x1<<5);
++ P = 32;
++ DIV = 0;
++ }
++ else if( uiFrequency_100kHz<14470 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x2<<5);
++ P = 32;
++ DIV = 0;
++ }
++ else if( uiFrequency_100kHz<16150 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x3<<5);
++ P = 32;
++ DIV = 0;
++ }
++ else if( uiFrequency_100kHz<17910 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x4<<5);
++ P = 32;
++ DIV = 0;
++ }
++ else if( uiFrequency_100kHz<19720 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x5<<5);
++ P = 32;
++ DIV = 0;
++ }
++ else if( uiFrequency_100kHz<=21540 )
++ {
++ pTunerRegs->m_ucRegData[3] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[3] |= (0x6<<5);
++ P = 32;
++ DIV = 0;
++ }
++ else
++ {
++ return(AVL_DVBSx_EC_GeneralFail);
++ }
++
++ A = (uiFrequency_100kHz/10)%P;
++ N = (uiFrequency_100kHz/10)/P;
++
++ pTunerRegs->m_ucRegData[3] &= ~(0x1<<4);
++ if( P==16 )
++ {
++ pTunerRegs->m_ucRegData[3] |= (0x1<<4);
++ }
++
++ pTunerRegs->m_ucRegData[3] &= ~(0x1<<1);
++ pTunerRegs->m_ucRegData[3] |= (AVL_uchar)(DIV<<1);
++
++ pTunerRegs->m_ucRegData[1] &= ~(0x1f<<0);
++ pTunerRegs->m_ucRegData[1] |= (AVL_uchar)(A<<0);
++
++ pTunerRegs->m_ucRegData[1] &= ~(0x7<<5);
++ pTunerRegs->m_ucRegData[1] |= (AVL_uchar)(N<<5);
++ pTunerRegs->m_ucRegData[0] &= ~(0x1f<<0);
++ pTunerRegs->m_ucRegData[0] |= (AVL_uchar)((N>>3)<<0);
++
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode SharpBS2S7HZ6306_CommitSetting(const struct AVL_Tuner * pTuner , struct SharpBS2S7HZ6306_Registers * pTunerRegs )
++{
++ AVL_DVBSx_ErrorCode r;
++ pTunerRegs->m_ucRegData[0] &= 0x7f;
++ pTunerRegs->m_ucRegData[2] |= 0x80;
++
++ pTunerRegs->m_ucRegData[2] &= ~(0x7<<2);
++ pTunerRegs->m_ucRegData[3] &= ~(0x3<<2);
++
++ r = AVL_DVBSx_II2CRepeater_SendData((AVL_uchar)(pTuner->m_uiSlaveAddress), pTunerRegs->m_ucRegData, 4, pTuner->m_pAVLChip );
++ if( r != AVL_DVBSx_EC_OK )
++ {
++ return(r);
++ }
++ pTunerRegs->m_ucRegData[2] |= (0x1<<2);
++
++ r |= AVL_DVBSx_II2CRepeater_SendData((AVL_uchar)(pTuner->m_uiSlaveAddress), (pTunerRegs->m_ucRegData)+2, 1, pTuner->m_pAVLChip );
++ if( r != AVL_DVBSx_EC_OK )
++ {
++ return(r);
++ }
++ r |= AVL_DVBSx_IBSP_Delay(12);
++
++ r |= SharpBS2S7HZ6306Regs_SetLPF ((AVL_uint16)(pTuner->m_uiLPF_100kHz*10), pTunerRegs);
++ pTunerRegs->m_ucRegData[2] |= ((((pTunerRegs->m_ucLPF)>>1)&0x1)<<3); /* PD4 */
++ pTunerRegs->m_ucRegData[2] |= ((((pTunerRegs->m_ucLPF)>>0)&0x1)<<4); /* PD5 */
++ pTunerRegs->m_ucRegData[3] |= ((((pTunerRegs->m_ucLPF)>>3)&0x1)<<2); /* PD2 */
++ pTunerRegs->m_ucRegData[3] |= ((((pTunerRegs->m_ucLPF)>>2)&0x1)<<3); /* PD3 */
++
++ r |= AVL_DVBSx_II2CRepeater_SendData((AVL_uchar)(pTuner->m_uiSlaveAddress), (pTunerRegs->m_ucRegData)+2, 2, pTuner->m_pAVLChip );
++
++ return(r);
++}
++
++//*******************************************************************************************
++
++AVL_DVBSx_ErrorCode Initialize_Demod_RelatedTunerPart(struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_slave_addr_addr, pTuner->m_uiSlaveAddress);
++ r |= AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_use_internal_control_addr, 0);
++ r |= AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_LPF_margin_100kHz_addr, 0); //clean up the LPF margin for blind scan. for external driver, this must be zero.
++ r |= AVL_DVBSx_II2C_Write16(pTuner->m_pAVLChip, rc_tuner_max_LPF_100kHz_addr, 320); //set up the right LPF for blind scan to regulate the freq_step. This field should corresponding the flat response part of the LPF.
++
++ r |= AVL_DVBSx_II2CRepeater_Initialize(pTuner->m_uiI2CBusClock_kHz, pTuner->m_pAVLChip);
++
++ return r;
++}
++
++AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_Initialize(struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r;
++
++ //Initialize the part of demodulator that related with the tuner.
++ r = Initialize_Demod_RelatedTunerPart(pTuner);
++
++ //Initialize the Tuner.
++ //BS2S7HZ6306 not need initialize, if other tuners need initialize add the initialization code here.
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_GetLockStatus(struct AVL_Tuner * pTuner )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint16 ucTemp;
++ r = AVL_DVBSx_II2CRepeater_ReadData((AVL_uchar)(pTuner->m_uiSlaveAddress), (AVL_puchar)(&ucTemp), 1, pTuner->m_pAVLChip );
++ if( AVL_DVBSx_EC_OK == r )
++ {
++
++ if( 0 == (ucTemp & 0x40) )
++ {
++ r = AVL_DVBSx_EC_GeneralFail ;
++ }
++ }
++ return(r);
++}
++
++static AVL_DVBSx_ErrorCode Frequency_LPF_Adjustment(struct AVL_Tuner * pTuner,AVL_uint16 *uiAdjustFreq)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 uitemp1;
++ AVL_uint16 uitemp2;
++ AVL_uint16 minimum_LPF_100kHz;
++ AVL_uint16 carrierFrequency_100kHz;
++
++ r = AVL_DVBSx_II2C_Read32(pTuner->m_pAVLChip, 0x263E, &uitemp1);
++ r |= AVL_DVBSx_II2C_Read16(pTuner->m_pAVLChip, 0x2642, &uitemp2);
++ if(r != AVL_DVBSx_EC_OK)
++ {
++ *uiAdjustFreq = pTuner->m_uiFrequency_100kHz;
++ return r;
++ }
++
++ if(pTuner->m_uiSymbolRate_Hz <= uitemp1)
++ {
++ carrierFrequency_100kHz =(AVL_uint16 )((uitemp2/10)+ pTuner->m_uiFrequency_100kHz);
++
++ minimum_LPF_100kHz = (pTuner->m_uiSymbolRate_Hz/100000 )*135/200 + (uitemp2/10) + 50;
++ if(pTuner->m_uiLPF_100kHz < minimum_LPF_100kHz)
++ {
++ pTuner->m_uiLPF_100kHz = (AVL_uint16 )(minimum_LPF_100kHz);
++ }
++ }
++ else
++ {
++ carrierFrequency_100kHz = pTuner->m_uiFrequency_100kHz;
++ }
++
++ *uiAdjustFreq = carrierFrequency_100kHz;
++
++ return AVL_DVBSx_EC_OK;
++
++}
++
++
++AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_Lock(struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint16 carrierFrequency_100kHz;
++
++ struct SharpBS2S7HZ6306_Registers TunerRegs;
++ struct SharpBS2S7HZ6306_TunerPara * pPara;
++
++ TunerRegs.m_ucRegData[0] = 0;
++ TunerRegs.m_ucRegData[1] = 0;
++ TunerRegs.m_ucRegData[2] = 0;
++ TunerRegs.m_ucRegData[3] = 0;
++
++
++ Frequency_LPF_Adjustment(pTuner, &carrierFrequency_100kHz);
++
++ r = SharpBS2S7HZ6306_SetFrequency(carrierFrequency_100kHz, &TunerRegs );
++ if( 0 == pTuner->m_pParameters ) //use default values
++ {
++ r |= SharpBS2S7HZ6306_SetChargePump(PC_360_694_Sharp, &TunerRegs);
++ r |= SharpBS2S7HZ6306_SetBBGain(Bbg_4_Sharp, &TunerRegs);
++ }
++ else //use custom value
++ {
++ pPara = (struct SharpBS2S7HZ6306_TunerPara *)(pTuner->m_pParameters);
++ r |= SharpBS2S7HZ6306_SetChargePump(pPara->m_ChargPump, &TunerRegs);
++ r |= SharpBS2S7HZ6306_SetBBGain(pPara->m_BBGain, &TunerRegs);
++ }
++ r |= SharpBS2S7HZ6306_CommitSetting(pTuner, &TunerRegs);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode ExtSharpBS2S7HZ6306_Check(struct AVL_Tuner * pTuner)
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = ExtSharpBS2S7HZ6306_Initialize(pTuner);
++ if (r != AVL_DVBSx_EC_OK)
++ {
++ return r;
++ }
++ AVL_DVBSx_IBSP_Delay(1);
++ r = ExtSharpBS2S7HZ6306_Lock(pTuner);
++ if (r != AVL_DVBSx_EC_OK)
++ {
++ return r;
++ }
++ AVL_DVBSx_IBSP_Delay(50); //Wait a while for tuner to lock in certain frequency.
++ r = ExtSharpBS2S7HZ6306_GetLockStatus(pTuner);
++ if (r != AVL_DVBSx_EC_OK)
++ {
++ return r;
++ }
++ return AVL_DVBSx_EC_OK;
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/IBase.c b/drivers/amlogic/dvb_tv/avl6211/src/IBase.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/IBase.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/IBase.c 2014-12-11 16:13:50.457614809 +0100
+@@ -0,0 +1,335 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "IBase.h"
++#include "II2C.h"
++#include "IBSP.h"
++#include "IRx.h"
++#include "ITuner.h"
++#include "II2CRepeater.h"
++#include "IBlindScan.h"
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetPLL(const struct AVL_DVBSx_PllConf * pPLLConf, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ printk("%s in \n",__FUNCTION__);
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, pll_clkf_map_addr, pPLLConf->m_uiClkf);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, pll_bwadj_map_addr, pPLLConf->m_uiClkf);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, pll_clkr_map_addr, pPLLConf->m_uiClkr);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, pll_od_map_addr, pPLLConf->m_uiPllod);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, pll_od2_map_addr, pPLLConf->m_uiPllod2);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, pll_od3_map_addr, pPLLConf->m_uiPllod3);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, pll_softvalue_en_map_addr, 1);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, reset_register_addr, 0);
++ AVL_DVBSx_II2C_Write32(pAVLChip, reset_register_addr, 1); //this is a reset, do not expect an ACK from the chip.
++ pAVLChip->m_DemodFrequency_10kHz = pPLLConf->m_DmodFrequency_10kHz;
++ pAVLChip->m_FecFrequency_10kHz = pPLLConf->m_FecFrequency_10kHz;
++ pAVLChip->m_MpegFrequency_10kHz = pPLLConf->m_MpegFrequency_10kHz;
++
++ return(r);
++}
++/// @endcond
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_DownloadFirmware(AVL_puchar pFirmwareData, const struct AVL_DVBSx_Chip * pAVLChip)
++{
++ printk("%s in \n",__FUNCTION__);
++ AVL_uint32 uiSize, uiDataSize;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 i1;
++
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, core_reset_b_reg, 0);
++
++ uiDataSize = DeChunk32(pFirmwareData);
++ i1 = 4;
++ while( i1 < uiDataSize )
++ {
++ uiSize = DeChunk32(pFirmwareData+i1);
++ i1 += 4;
++ r |= AVL_DVBSx_II2C_Write(pAVLChip, pFirmwareData+i1+1, (AVL_uint16)(uiSize+3));
++ i1 += 4 + uiSize;
++ }
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, 0x00000000, 0x00003ffc);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, core_ready_word_addr, 0x0000);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, error_msg_addr, 0x00000000);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, error_msg_addr+4, 0x00000000);
++ AVL_DVBSx_II2C_Write32(pAVLChip, core_reset_b_reg, 1);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetStatus( struct AVL_DVBSx_Chip * pAVLChip )
++{
++ printk("%s in \n",__FUNCTION__);
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiReadValue;
++ AVL_uint32 uiTemp;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, core_reset_b_reg, &uiTemp);
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, core_ready_word_addr, &uiReadValue);
++ if( (AVL_DVBSx_EC_OK == r) )
++ {
++ if( (0 == uiTemp) || (uiReadValue != 0xA55A) )
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetVersion( struct AVL_DVBSx_VerInfo * pVerInfo, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_uint32 uiTemp;
++ AVL_uchar ucBuff[4];
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rom_ver_addr, &uiTemp);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ Chunk32(uiTemp, ucBuff);
++ pVerInfo->m_Chip.m_Major = ucBuff[0];
++ pVerInfo->m_Chip.m_Minor = ucBuff[1];
++ pVerInfo->m_Chip.m_Build = ucBuff[2];
++ pVerInfo->m_Chip.m_Build = ((AVL_uint16)((pVerInfo->m_Chip.m_Build)<<8)) + ucBuff[3];
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rc_patch_ver_addr, &uiTemp);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ Chunk32(uiTemp, ucBuff);
++ pVerInfo->m_Patch.m_Major = ucBuff[0];
++ pVerInfo->m_Patch.m_Minor = ucBuff[1];
++ pVerInfo->m_Patch.m_Build = ucBuff[2];
++ pVerInfo->m_Patch.m_Build = ((AVL_uint16)((pVerInfo->m_Patch.m_Build)<<8)) + ucBuff[3];
++
++ pVerInfo->m_API.m_Major = AVL_DVBSx_API_VER_MAJOR;
++ pVerInfo->m_API.m_Minor = AVL_DVBSx_API_VER_MINOR;
++ pVerInfo->m_API.m_Build = AVL_DVBSx_API_VER_BUILD;
++ }
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Initialize( const struct AVL_DVBSx_PllConf * pPLLConf, AVL_puchar pInitialData, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_IBase_SetPLL(pPLLConf, pAVLChip );
++ r |= AVL_DVBSx_IBSP_Delay(100); // this delay is critical
++ r |= AVL_DVBSx_IBase_DownloadFirmware(pInitialData, pAVLChip);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Halt( struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_IBase_SendRxOP(OP_RX_HALT, pAVLChip);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Sleep( struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_IBase_SendRxOP(OP_RX_SLEEP, pAVLChip);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_Wake( struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_IBase_SendRxOP(OP_RX_WAKE, pAVLChip);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetFunctionalMode(const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_FunctionalMode enumFunctionalMode)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r = AVL_DVBSx_II2C_Write16(pAVLChip, rc_functional_mode_addr, (AVL_uint16)enumFunctionalMode);
++ if(enumFunctionalMode == AVL_DVBSx_FunctMode_Demod)
++ {
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, 0x2642, 400);
++
++ }
++ else if(enumFunctionalMode == AVL_DVBSx_FunctMode_BlindScan)
++ {
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, 0x2642, 0);
++ }
++ r |=AVL_DVBSx_II2C_Write16(pAVLChip, rc_iq_mode_addr,0);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetFunctionalMode(enum AVL_DVBSx_FunctionalMode * pFunctionalMode, const struct AVL_DVBSx_Chip * pAVLChip)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiTemp;
++
++ r = AVL_DVBSx_II2C_Read16(pAVLChip, rc_functional_mode_addr, &uiTemp);
++ *pFunctionalMode = (enum AVL_DVBSx_FunctionalMode)(uiTemp & 0x0001);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SendRxOP(AVL_uchar ucOpCmd, struct AVL_DVBSx_Chip * pAVLChip )
++{
++/* AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uchar pucBuff[2];
++ AVL_uint16 uiTemp;
++ enum AVL_DVBSx_Sleep_Wake_Status sleep_wake_status;
++ const AVL_uint16 uiTimeDelay = 10;
++ AVL_uint16 uiMaxRetries = 20;
++
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semRx));
++ r |= AVL_DVBSx_IBase_GetChipStatus(&sleep_wake_status, pAVLChip);
++ if(r == AVL_DVBSx_EC_OK)
++ {
++ if(sleep_wake_status == AVL_DVBSx_Sleep_Mode)
++ {
++ if((ucOpCmd != OP_RX_WAKE) && (ucOpCmd != OP_RX_HALT) && (ucOpCmd != OP_RX_SLEEP))
++ {
++ AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semRx));
++ r = AVL_DVBSx_EC_InSleepMode;
++ return(r);
++ }
++ }
++
++ do
++ {
++ r = AVL_DVBSx_IBase_GetRxOPStatus(pAVLChip);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ break;
++ }
++ AVL_DVBSx_IBSP_Delay(uiTimeDelay);
++ uiMaxRetries--;
++
++ }while(uiMaxRetries != 0);
++
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ pucBuff[0] = 0;
++ pucBuff[1] = ucOpCmd;
++ uiTemp = DeChunk16(pucBuff);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rx_cmd_addr, uiTemp);
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semRx));
++
++ return(r);*/
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ unsigned char pucBuff[2];
++ unsigned short uiTemp;
++
++ r |= AVL_DVBSx_IBase_GetRxOPStatus(pAVLChip);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ pucBuff[0] = 0;
++ pucBuff[1] = ucOpCmd;
++ uiTemp = DeChunk16(pucBuff);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rx_cmd_addr, uiTemp);
++ }
++
++ return(r);
++
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetRxOPStatus(const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uchar pBuff[2] = {0,0};
++
++ r = AVL_DVBSx_II2C_Read(pAVLChip, rx_cmd_addr, pBuff, 2);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ if( 0 != pBuff[1] )
++ {
++ r = AVL_DVBSx_EC_Running;
++ }
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetGPIODir( AVL_uchar ucDir, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiTemp = (AVL_uint32)(ucDir & 0x7);
++
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, gpio_reg_enb, uiTemp);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetGPIOVal( AVL_uchar ucVal, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiTemp;
++
++ uiTemp = (AVL_uint32)(ucVal & 0x7);
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, gpio_data_reg_out, uiTemp);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetGPIOVal( AVL_puchar pucVal, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiTemp;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, gpio_data_in_to_reg, &uiTemp);
++ *pucVal = (AVL_uchar)uiTemp;
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_GetChipStatus( enum AVL_DVBSx_Sleep_Wake_Status * pChipStatus, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiStatus;
++
++ r = AVL_DVBSx_II2C_Read16(pAVLChip, rp_sleep_wake_status_addr, &uiStatus);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ if((enum AVL_DVBSx_Sleep_Wake_Status)(uiStatus) == AVL_DVBSx_Sleep_Mode)
++ {
++ *pChipStatus = AVL_DVBSx_Sleep_Mode;
++
++ }
++ else if((enum AVL_DVBSx_Sleep_Wake_Status)(uiStatus) == AVL_DVBSx_Wake_Mode)
++ {
++ *pChipStatus = AVL_DVBSx_Wake_Mode;
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBase_SetSpectrumPolarity( enum AVL_DVBSx_SpectrumPolarity enumSpectrumPolarity, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Write16(pAVLChip, rc_blind_scan_tuner_spectrum_inversion_addr, (AVL_uint16)enumSpectrumPolarity);
++
++ return(r);
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/IBlindscanAPI.c b/drivers/amlogic/dvb_tv/avl6211/src/IBlindscanAPI.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/IBlindscanAPI.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/IBlindscanAPI.c 2014-12-11 16:13:50.289616089 +0100
+@@ -0,0 +1,237 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "avl_dvbsx.h"
++#include "ITuner.h"
++#include "avl_dvbsx_globals.h"
++#include "IBSP.h"
++#include "IBase.h"
++#include "IRx.h"
++#include "II2C.h"
++#include "IBlindScan.h"
++#include "IBlindscanAPI.h"
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Initialize(struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting)
++{
++ pBSsetting->m_uiScan_Start_Freq_MHz = 950; //Default Set Blind scan start frequency
++ pBSsetting->m_uiScan_Stop_Freq_MHz = 2150; //Default Set Blind scan stop frequency
++ pBSsetting->m_uiScan_Next_Freq_100KHz = 10*pBSsetting->m_uiScan_Start_Freq_MHz;
++
++ pBSsetting->m_uiScan_Max_Symbolrate_MHz = 45; //Set MAX symbol rate
++ pBSsetting->m_uiScan_Min_Symbolrate_MHz = 2; //Set MIN symbol rate
++
++ pBSsetting->m_uiTuner_MaxLPF_100kHz = 340;
++
++ pBSsetting->m_uiScan_Bind_No = 0;
++ pBSsetting->m_uiScan_Progress_Per = 0;
++ pBSsetting->m_uiChannelCount = 0;
++
++ pBSsetting->m_eSpectrumMode = AVL_DVBSx_Spectrum_Normal; //Set spectrum mode
++
++ pBSsetting->BS_Mode = AVL_DVBSx_BS_Fast_Mode; //1: Freq Step forward is 10MHz 0: Freq Step firmware is 20.7MHz
++ pBSsetting->m_uiScaning = 0;
++ pBSsetting->m_uiScan_Center_Freq_Step_100KHz = 100; //only valid when scan_algorithmic set to 1 and would be ignored when scan_algorithmic set to 0.
++ printk("BS_Mode is %d(0-fast,1-slow)\n",pBSsetting->BS_Mode);
++ return AVL_DVBSx_EC_OK;
++}
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetSpectrumMode(struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting, enum AVL_DVBSx_SpectrumPolarity SpectrumMode)
++{
++ pBSsetting->m_eSpectrumMode = SpectrumMode;
++ return AVL_DVBSx_EC_OK;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetScanMode(struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting, enum AVL_DVBSx_BlindScanAPI_Mode Scan_Mode)
++{
++ pBSsetting->BS_Mode = Scan_Mode;
++ return AVL_DVBSx_EC_OK;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetFreqRange(struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting,AVL_uint16 StartFreq_MHz,AVL_uint16 EndFreq_MHz)
++{
++// pBSsetting->m_uiScan_Start_Freq_MHz = StartFreq_MHz; //Change default start frequency
++// pBSsetting->m_uiScan_Stop_Freq_MHz = EndFreq_MHz; //Change default end frequency
++ pBSsetting->m_uiScan_Next_Freq_100KHz = 10*pBSsetting->m_uiScan_Start_Freq_MHz;
++
++ return AVL_DVBSx_EC_OK;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_SetMaxLPF(struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting ,AVL_uint16 MaxLPF)
++{
++ pBSsetting->m_uiTuner_MaxLPF_100kHz = MaxLPF;
++
++ return AVL_DVBSx_EC_OK;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Start(struct AVL_DVBSx_Chip * pAVLChip, struct AVL_Tuner * pTuner, struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_BlindScanPara * pbsPara = &pBSsetting->bsPara;
++
++ r |= AVL_DVBSx_IBase_SetFunctionalMode(pAVLChip, AVL_DVBSx_FunctMode_BlindScan);
++ r |= AVL_DVBSx_IBase_SetSpectrumPolarity(pBSsetting->m_eSpectrumMode,pAVLChip);
++
++ if(pBSsetting->BS_Mode)
++ {
++ pTuner->m_uiFrequency_100kHz = 10*pBSsetting->m_uiScan_Start_Freq_MHz + 320 + (pBSsetting->m_uiScan_Bind_No) * pBSsetting->m_uiScan_Center_Freq_Step_100KHz;
++ pbsPara->m_uiStartFreq_100kHz = pTuner->m_uiFrequency_100kHz - 320;
++ pbsPara->m_uiStopFreq_100kHz = pTuner->m_uiFrequency_100kHz + 320;
++ }
++ else
++ {
++ pbsPara->m_uiStartFreq_100kHz = pBSsetting->m_uiScan_Next_Freq_100KHz;
++ pbsPara->m_uiStopFreq_100kHz = pBSsetting->m_uiScan_Next_Freq_100KHz + 320*2;
++ pTuner->m_uiFrequency_100kHz = (pbsPara->m_uiStartFreq_100kHz + pbsPara->m_uiStopFreq_100kHz)/2;
++ }
++
++ pTuner->m_uiLPF_100kHz = pBSsetting->m_uiTuner_MaxLPF_100kHz;
++
++ r |= pTuner->m_pLockFunc(pTuner); //Lock the tuner.
++
++ AVL_DVBSx_IBSP_Delay(50); //wait a while for tuner to lock in certain frequency.
++
++ r |= pTuner->m_pGetLockStatusFunc(pTuner); //Check the lock status of the tuner.
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ return r;
++ }
++
++ pbsPara->m_uiMaxSymRate_kHz = 1000*pBSsetting->m_uiScan_Max_Symbolrate_MHz;
++ pbsPara->m_uiMinSymRate_kHz = 1000*pBSsetting->m_uiScan_Min_Symbolrate_MHz;
++
++ r |= AVL_DVBSx_IBlindScan_Reset(pAVLChip);
++ r |= AVL_DVBSx_IBlindScan_Scan(pbsPara,340, pAVLChip);
++ pBSsetting->m_uiScaning = 1;
++
++ return r;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_GetCurrentScanStatus(struct AVL_DVBSx_Chip * pAVLChip,struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_BlindScanInfo * pbsInfo = &(pBSsetting->bsInfo);
++ struct AVL_DVBSx_BlindScanPara * pbsPara = &(pBSsetting->bsPara);
++
++ r |= AVL_DVBSx_IBlindScan_GetScanStatus(pbsInfo, pAVLChip); //Query the internal blind scan procedure information.
++
++
++ if(100 == pbsInfo->m_uiProgress)
++ {
++ pBSsetting->m_uiScan_Next_Freq_100KHz = pbsInfo->m_uiNextStartFreq_100kHz;
++ pBSsetting->m_uiScan_Progress_Per = AVL_min(100,((10*(pbsPara->m_uiStopFreq_100kHz - 10*pBSsetting->m_uiScan_Start_Freq_MHz))/(pBSsetting->m_uiScan_Stop_Freq_MHz - pBSsetting->m_uiScan_Start_Freq_MHz)));
++ pBSsetting->m_uiScan_Bind_No++;
++ pBSsetting->m_uiScaning = 0;
++
++ r |= AVL_DVBSx_IBase_SetFunctionalMode(pAVLChip,AVL_DVBSx_FunctMode_Demod);
++ }
++ if( r != AVL_DVBSx_EC_OK
++#if defined(CONFIG_MACH_MESON6_G18_TH7)
++ || pbsInfo->m_uiResultCode > 0
++#endif
++ )
++ return AVL_DVBSx_EC_GeneralFail;
++
++ if(100 == pbsInfo->m_uiProgress)
++ return AVL_DVBSx_EC_OK;
++ else
++ return AVL_DVBSx_EC_Running;
++}
++
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Adjust(struct AVL_DVBSx_Chip * pAVLChip,struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting)
++{
++
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_BlindScanInfo * pbsInfo = &pBSsetting->bsInfo;
++ AVL_uint16 Indext = pBSsetting->m_uiChannelCount;
++ AVL_uint16 i,j,flag;
++ struct AVL_DVBSx_Channel *pTemp;
++ struct AVL_DVBSx_Channel *pValid;
++ AVL_uint32 uiSymbolRate_Hz;
++ AVL_uint32 ui_SR_offset;
++
++ if(pbsInfo->m_uiChannelCount>0)
++ {
++ r |= AVL_DVBSx_IBlindScan_ReadChannelInfo(0, &(pbsInfo->m_uiChannelCount), pBSsetting->channels_Temp, pAVLChip);
++ }
++
++ for(i=0; im_uiChannelCount; i++)
++ {
++ pTemp = &(pBSsetting->channels_Temp[i]);
++ flag =0;
++ for(j=0; jm_uiChannelCount; j++)
++ {
++ pValid = &(pBSsetting->channels[j]);
++ if( (AVL_abssub(pValid->m_uiFrequency_kHz,pTemp->m_uiFrequency_kHz)*833) < AVL_min(pValid->m_uiSymbolRate_Hz,pTemp->m_uiSymbolRate_Hz) )
++ {
++ flag = 1;
++ break;
++ }
++ }
++
++ if(0 == flag)
++ {
++ pBSsetting->channels[Indext].m_Flags = pTemp->m_Flags;
++ pBSsetting->channels[Indext].m_uiSymbolRate_Hz = pTemp->m_uiSymbolRate_Hz;
++ pBSsetting->channels[Indext].m_uiFrequency_kHz = 1000*((pTemp->m_uiFrequency_kHz+500)/1000);
++
++ uiSymbolRate_Hz = pBSsetting->channels[Indext].m_uiSymbolRate_Hz;
++ //----------------------------adjust symbol rate offset------------------------------------------------------------
++ ui_SR_offset = ((uiSymbolRate_Hz%10000)>5000)?(10000-(uiSymbolRate_Hz%10000)):(uiSymbolRate_Hz%10000);
++ if( ((uiSymbolRate_Hz>10000000) && (ui_SR_offset<3500)) || ((uiSymbolRate_Hz>5000000) && (ui_SR_offset<2000)) )
++ uiSymbolRate_Hz = (uiSymbolRate_Hz%10000<5000)?(uiSymbolRate_Hz - ui_SR_offset):(uiSymbolRate_Hz + ui_SR_offset);
++
++ ui_SR_offset = ((uiSymbolRate_Hz%1000)>500)?(1000-(uiSymbolRate_Hz%1000)):(uiSymbolRate_Hz%1000);
++ if( (uiSymbolRate_Hz<5000000) && (ui_SR_offset< 500) )
++ uiSymbolRate_Hz = (uiSymbolRate_Hz%1000<500)?(uiSymbolRate_Hz - ui_SR_offset):(uiSymbolRate_Hz + ui_SR_offset);
++
++ pBSsetting->channels[Indext].m_uiSymbolRate_Hz = 1000*(uiSymbolRate_Hz/1000);
++ //----------------------------------------------------------------------------------------------------------------
++ Indext++;
++ }
++ }
++
++ pBSsetting->m_uiChannelCount = Indext;
++
++ return r;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScanAPI_Exit(struct AVL_DVBSx_Chip * pAVLChip, struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_DVBSx_BlindScanInfo * pbsInfo = &pBSsetting->bsInfo;
++
++ if(pBSsetting->m_uiScaning == 1)
++ {
++ do
++ {
++ AVL_DVBSx_IBSP_Delay(50);
++ r |= AVL_DVBSx_IBlindScan_GetScanStatus(pbsInfo, pAVLChip); //Query the internal blind scan procedure information.
++ if(AVL_DVBSx_EC_OK !=r)
++ {
++ return r;
++ }
++ }while(100 != pbsInfo->m_uiProgress);
++ }
++
++ r |= AVL_DVBSx_IBase_SetFunctionalMode(pAVLChip,AVL_DVBSx_FunctMode_Demod);
++ AVL_DVBSx_IBSP_Delay(10);
++
++ return r;
++}
++
++AVL_uint16 AVL_DVBSx_IBlindscanAPI_GetProgress(struct AVL_DVBSx_BlindScanAPI_Setting * pBSsetting)
++{
++ return pBSsetting->m_uiScan_Progress_Per;
++}
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/IBlindScan.c b/drivers/amlogic/dvb_tv/avl6211/src/IBlindScan.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/IBlindScan.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/IBlindScan.c 2014-12-11 16:13:50.457614809 +0100
+@@ -0,0 +1,163 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "IBlindScan.h"
++#include "IBase.h"
++#include "IRx.h"
++#include "II2C.h"
++#include "ITuner.h"
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_Scan(struct AVL_DVBSx_BlindScanPara * pBSPara, AVL_uint16 uiTunerLPF_100kHz, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint16 uiCarrierFreq_100kHz;
++ AVL_uint16 uiMinSymRate;
++ enum AVL_DVBSx_FunctionalMode enumFunctionalMode;
++
++ r = AVL_DVBSx_IBase_GetFunctionalMode(&enumFunctionalMode, pAVLChip);
++
++ if(enumFunctionalMode == AVL_DVBSx_FunctMode_BlindScan)
++ {
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_tuner_LPF_100kHz_addr, uiTunerLPF_100kHz);
++
++ uiMinSymRate = pBSPara->m_uiMinSymRate_kHz - 200; // give some tolerance
++
++ if( uiMinSymRate < 800 ) //Blind scan doesn't support symbol rate less then 1M, give 200K margin
++ {
++ uiMinSymRate = 800;
++ }
++
++ if( pBSPara->m_uiStartFreq_100kHz < pBSPara->m_uiStopFreq_100kHz )
++ {
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ uiCarrierFreq_100kHz = ((pBSPara->m_uiStopFreq_100kHz)+(pBSPara->m_uiStartFreq_100kHz))>>1;
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_tuner_frequency_100kHz_addr, uiCarrierFreq_100kHz);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_blind_scan_min_sym_rate_kHz_addr, uiMinSymRate);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_blind_scan_max_sym_rate_kHz_addr, (pBSPara->m_uiMaxSymRate_kHz)+200);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_blind_scan_start_freq_100kHz_addr, (pBSPara->m_uiStartFreq_100kHz));
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_blind_scan_end_freq_100kHz_addr, (pBSPara->m_uiStopFreq_100kHz));
++
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ r = AVL_DVBSx_IBase_SendRxOP(OP_RX_BLIND_SCAN, (struct AVL_DVBSx_Chip *)pAVLChip );
++ }
++ }
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_GetScanStatus(struct AVL_DVBSx_BlindScanInfo * pBSInfo, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rs_blind_scan_progress_addr, &(pBSInfo->m_uiProgress));
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rs_blind_scan_channel_count_addr, &(pBSInfo->m_uiChannelCount));
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rc_blind_scan_start_freq_100kHz_addr, &(pBSInfo->m_uiNextStartFreq_100kHz));
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rs_blind_scan_error_code_addr, &(pBSInfo->m_uiResultCode));
++ if( pBSInfo->m_uiProgress > 100 )
++ {
++ pBSInfo->m_uiProgress = 0;
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_Cancel(struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ enum AVL_DVBSx_FunctionalMode enumFunctionalMode;
++
++ r = AVL_DVBSx_IBase_GetFunctionalMode(&enumFunctionalMode, pAVLChip);
++
++ if(enumFunctionalMode == AVL_DVBSx_FunctMode_BlindScan)
++ {
++ r |= AVL_DVBSx_IBase_SendRxOP(OP_RX_HALT, pAVLChip );
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_ReadChannelInfo(AVL_uint16 uiStartIndex, AVL_puint16 pChannelCount, struct AVL_DVBSx_Channel * pChannel, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 channel_addr;
++ AVL_uint16 i1, i2;
++ AVL_uint32 uiMinFreq;
++ int iMinIdx;
++ struct AVL_DVBSx_Channel sTempChannel;
++
++ r = AVL_DVBSx_II2C_Read16(pAVLChip, rs_blind_scan_channel_count_addr, &i1);
++ if( (uiStartIndex + (*pChannelCount)) > (i1) )
++ {
++ *pChannelCount = i1-uiStartIndex;
++ }
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rc_blind_scan_channel_info_offset_addr, &i1);
++ channel_addr = (sharemem_addr + i1) + uiStartIndex*sizeof(struct AVL_DVBSx_Channel);
++ for( i1=0; i1<(*pChannelCount); i1++ )
++ {
++#if 1 //for some processors which can not read 12 bytes
++ //dump the channel information
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, channel_addr, &(pChannel[i1].m_uiFrequency_kHz));
++ channel_addr += 4;
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, channel_addr, &(pChannel[i1].m_uiSymbolRate_Hz));
++ channel_addr += 4;
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, channel_addr, &(pChannel[i1].m_Flags));
++ channel_addr += 4;
++#endif
++ }
++
++ // Sort the results
++ for(i1=0; i1<(*pChannelCount); i1++)
++ {
++ iMinIdx = i1;
++ uiMinFreq = pChannel[i1].m_uiFrequency_kHz;
++ for(i2=(i1+1); i2<(*pChannelCount); i2++)
++ {
++ if(pChannel[i2].m_uiFrequency_kHz < uiMinFreq)
++ {
++ uiMinFreq = pChannel[i2].m_uiFrequency_kHz;
++ iMinIdx = i2;
++ }
++ }
++ sTempChannel = pChannel[iMinIdx];
++ pChannel[iMinIdx] = pChannel[i1];
++ pChannel[i1] = sTempChannel;
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBlindScan_Reset( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Write16(pAVLChip, rc_blind_scan_reset_addr, 1);
++
++ return(r);
++}
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/IBSP.c b/drivers/amlogic/dvb_tv/avl6211/src/IBSP.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/IBSP.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/IBSP.c 2014-12-11 16:13:50.473614685 +0100
+@@ -0,0 +1,234 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++///
++/// @file
++/// @brief Implements the functions declared in IBSP.h.
++///
++#include "IBSP.h"
++#include
++#include
++
++#include "../../aml_fe.h"
++
++#define init_MUTEX(sem) sema_init(sem, 1)
++#define init_MUTEX_LOCKED(sem) sema_init(sem, 0)
++
++/// The following table illustrates a set of PLL configuration values to operate AVL6211 in two modes:
++// Standard performance mode.
++// High performance mode
++
++/// Please refer to the AVL6211 channel receiver datasheet for detailed information on highest symbol rate
++/// supported by the demod in both these modes.
++
++///For more information on other supported clock frequencies and PLL settings for higher symbol rates, please
++///contact Availink.
++
++/// Users can remove unused elements from the following array to reduce the SDK footprint size.
++const struct AVL_DVBSx_PllConf pll_conf[] =
++{
++ // The following set of PLL configuration at different reference clock frequencies refer to demod operation
++ // in standard performance mode.
++ {503, 1, 7, 4, 2, 4000, 11200, 16800, 25200} ///< Reference clock 4 MHz, Demod clock 112 MHz, FEC clock 168 MHz, MPEG clock 252 MHz
++ ,{447, 1, 7, 4, 2, 4500, 11200, 16800, 25200} ///< Reference clock 4.5 MHz, Demod clock 112 MHz, FEC clock 168 MHz, MPEG clock 252 MHz
++ ,{503, 4, 7, 4, 2, 10000, 11200, 16800, 25200} ///< Reference clock 10 MHz, Demod clock 112 MHz, FEC clock 168 MHz, MPEG clock 252 MHz
++ ,{503, 7, 7, 4, 2, 16000, 11200, 16800, 25200} ///< Reference clock 16 MHz, Demod clock 112 MHz, FEC clock 168 MHz, MPEG clock 252 MHz
++ ,{111, 2, 7, 4, 2, 27000, 11200, 16800, 25200} ///< Reference clock 27 MHz, Demod clock 112 MHz, FEC clock 168 MHz, MPEG clock 252 MHz
++
++ // The following set of PLL configuration at different reference clock frequencies refer to demod operation
++ // in high performance mode.
++ ,{566, 1, 7, 4, 2, 4000, 12600, 18900, 28350} /// < Reference clock 4 MHz, Demod clock 126 MHz, FEC clock 189 MHz, MPEG clock 283.5 MHz
++ ,{503, 1, 7, 4, 2, 4500, 12600, 18900, 28350} ///< Reference clock 4.5 MHz, Demod clock 126 MHz, FEC clock 189 MHz, MPEG clock 283.5 MHz
++ ,{566, 4, 7, 4, 2, 10000, 12600, 18900, 28350} ///< Reference clock 10 MHz, Demod clock 126 MHz, FEC clock 189 MHz, MPEG clock 283.5 MHz
++ ,{566, 7, 7, 4, 2, 16000, 12600, 18900, 28350} ///< Reference clock 16 MHz, Demod clock 126 MHz, FEC clock 189 MHz, MPEG clock 283.5 MHz
++ ,{377, 8, 7, 4, 2, 27000, 12600, 18900, 28350} ///< Reference clock 27 MHz, Demod clock 126 MHz, FEC clock 189 MHz, MPEG clock 283.5 MHz
++
++};
++
++const AVL_uint16 pll_array_size = sizeof(pll_conf)/sizeof(struct AVL_DVBSx_PllConf);
++
++AVL_int32 I2CWrite(AVL_uchar I2CSlaveAddr, AVL_uchar *data, AVL_int32 length, int iDeviceID);
++AVL_int32 I2CRead(AVL_uchar I2CSlaveAddr, AVL_uchar *data, AVL_int32 length, int iDeviceID);
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_Initialize(void)
++{
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_Dispose(void)
++{
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_Delay( AVL_uint32 uiMS )
++{
++ msleep(uiMS);
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_I2CRead( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_puint16 puiSize )
++{
++ AVL_uint16 I2CSlaveAddr;
++ AVL_puchar data;
++ AVL_puint16 length;
++ I2CSlaveAddr=pAVLChip->m_SlaveAddr;
++ data = pucBuff;
++ length = *puiSize;
++ if(I2CRead(I2CSlaveAddr,data, length,pAVLChip->m_uiBusId)==0)
++ return AVL_DVBSx_EC_I2CFail;
++ //printk("data is %x,%x\n",data[0],data[1]);
++ return(AVL_DVBSx_EC_OK);
++}
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_I2CWrite( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_puint16 puiSize )
++{
++ AVL_uint16 I2CSlaveAddr;
++ AVL_puchar data;
++ AVL_puint16 length;
++ I2CSlaveAddr=pAVLChip->m_SlaveAddr;
++ data = pucBuff;
++ length = *puiSize;
++ if(I2CWrite(I2CSlaveAddr,data, length,pAVLChip->m_uiBusId)==0)
++ return AVL_DVBSx_EC_I2CFail;
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_InitSemaphore( AVL_psemaphore pSemaphore )
++{
++ init_MUTEX(pSemaphore);
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_WaitSemaphore( AVL_psemaphore pSemaphore )
++{
++ if(down_interruptible(pSemaphore))
++ return -AVL_DVBSx_EC_GeneralFail;
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IBSP_ReleaseSemaphore( AVL_psemaphore pSemaphore )
++{
++ up(pSemaphore);
++ return(AVL_DVBSx_EC_OK);
++}
++
++
++extern struct aml_fe_dev * avl6211_get_cur_dev(int iDeviceId);
++
++
++ AVL_int32 I2CWrite(AVL_uchar I2CSlaveAddr, AVL_uchar *data, AVL_int32 length,int iDeviceId)
++ {
++// printk("\n[I2CWrite] enter I2CSlaveAddr is %x,length is %d,data is %x, %x,%x\n",I2CSlaveAddr,length,data[0],data[1],data[2]);
++// printk("I2CSlaveAddr is %d\n",I2CSlaveAddr);
++ /* I2C write, please port this function*/
++ AVL_int32 ret = 0;
++// unsigned char regbuf[1]; /*8 bytes reg addr, regbuf 1 byte*/
++ struct i2c_msg msg; /*construct 2 msgs, 1 for reg addr, 1 for reg value, send together*/
++
++// regbuf[0] = I2CSlaveAddr & 0xff;
++
++ memset(&msg, 0, sizeof(msg));
++
++ /*write reg address*/
++/* msg[0].addr = (state->config.demod_addr);
++ msg[0].flags = 0;
++ msg[0].buf = regbuf;
++ msg[0].len = 1;*/
++
++
++ /*write value*/
++ msg.addr = I2CSlaveAddr;
++ msg.flags = 0; //I2C_M_NOSTART; /*i2c_transfer will emit a stop flag, so we should send 2 msg together,
++ // * and the second msg's flag=I2C_M_NOSTART, to get the right timing*/
++ msg.buf = data;
++ msg.len = length;
++#if 0
++
++ /*write reg address*/
++ msg[0].addr = 0x80;
++ msg[0].flags = 0;
++ msg[0].buf = 0x7;
++ msg[0].len = 1;
++
++ /*write value*/
++ msg[1].addr = 0x80;
++ msg[1].flags = I2C_M_NOSTART; /*i2c_transfer will emit a stop flag, so we should send 2 msg together,
++ * and the second msg's flag=I2C_M_NOSTART, to get the right timing*/
++ msg[1].buf = 0x8;
++ msg[1].len = 1;
++
++#endif
++
++// int i2c_id = -1;
++ /*cfg->demod_addr=0;
++ cfg->tuner_addr=0;
++ cfg->i2c_id=0;
++ cfg->reset_pin=0;*/
++ struct aml_fe_dev *dev = avl6211_get_cur_dev(iDeviceId);
++ /*i2c_handle = i2c_get_adapter(i2c_id,i2c_handle);
++ if (!i2c_handle) {
++ printk("cannot get i2c adaptor\n");
++ return 0;
++ }*/
++ ret = i2c_transfer((struct i2c_adapter *)dev->i2c_adap, &msg, 1);
++ if(ret<0){
++ printk(" %s: writereg error, errno is %d \n", __FUNCTION__, ret);
++ return 0;
++ }
++ else{
++ //printk(" %s:write success, errno is %d \n", __FUNCTION__, ret);
++ return 1;
++ }
++ return 1;
++ }
++
++ AVL_int32 I2CRead(AVL_uchar I2CSlaveAddr, AVL_uchar *data, AVL_int32 length,int iDeviceId)
++ {
++ /* I2C read, please port this function*/
++ // printk("I2CSlaveAddr is %d,length is %d\n",I2CSlaveAddr,length);
++// printk("I2CSlaveAddr is %d\n",I2CSlaveAddr);
++ AVL_uint32 nRetCode = 0;
++ struct i2c_msg msg[1];
++
++ if(data == 0 || length == 0)
++ {
++ printk("avl6211 read register parameter error !!\n");
++ return 0;
++ }
++
++ //read real data
++ memset(msg, 0, sizeof(msg));
++ msg[0].addr = I2CSlaveAddr;
++ msg[0].flags |= I2C_M_RD; //write I2C_M_RD=0x01
++ msg[0].len = length;
++ msg[0].buf = data;
++
++
++ struct aml_fe_dev *dev = avl6211_get_cur_dev(iDeviceId);
++ // printk("\n[I2CRead] get i2c_adapter");
++ /* i2c_handle = i2c_get_adapter(i2c_id);
++ if (!i2c_handle) {
++ printk("cannot get i2c adaptor\n");
++ }*/
++
++
++ nRetCode = i2c_transfer((struct i2c_adapter *)dev->i2c_adap, msg, 1);
++
++ if(nRetCode != 1)
++ {
++ printk("avl6211_readregister reg failure!\n");
++ return 0;
++ }
++ return 1;
++ }
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/IDiseqc.c b/drivers/amlogic/dvb_tv/avl6211/src/IDiseqc.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/IDiseqc.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/IDiseqc.c 2014-12-11 16:13:50.393615298 +0100
+@@ -0,0 +1,478 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "IDiseqc.h"
++#include "II2C.h"
++#include "IBSP.h"
++#include "IBase.h"
++
++///@cond
++#define Diseqc_delay 20
++
++/// Check if it is safe to switch DiSEqC operation mode.
++///
++/// @param pAVLChip A pointer point to a ::AVL_DVBSx_Chip object which is used to tell function which chip it is working on.
++///
++/// @return ::AVL_DVBSx_ErrorCode,
++/// Return ::AVL_DVBSx_EC_OK if it is OK to switch.
++/// Return ::AVL_DVBSx_EC_Running if it is not safe to switch since the last transmit is not done yet.
++/// Return ::AVL_DVBSx_EC_I2CFail if there is a I2C problem.
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_IsSafeToSwitchMode( struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 i1;
++ switch( pAVLChip->Diseqc_OP_Status )
++ {
++ case AVL_DVBSx_DOS_InModulation:
++ case AVL_DVBSx_DOS_InTone:
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_st_addr, &i1);
++ if( 1 != ((i1 & 0x00000040) >> 6) ) //check if the last transmit is done
++ {
++ r |= AVL_DVBSx_EC_Running;
++ }
++ break;
++ case AVL_DVBSx_DOS_InContinuous:
++ case AVL_DVBSx_DOS_Initialized:
++ break;
++ default:
++ r |= AVL_DVBSx_EC_GeneralFail;
++ break;
++ }
++ return(r);
++}
++
++///@endcond
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_Initialize( const struct AVL_DVBSx_Diseqc_Para * pDiseqcPara, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_srst_addr, 1);
++
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_samp_frac_n_addr, 200); //2M=200*10kHz
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_samp_frac_d_addr, pAVLChip->m_DemodFrequency_10kHz);
++
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tone_frac_n_addr, ((pDiseqcPara->m_ToneFrequency_kHz)<<1));
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tone_frac_d_addr, pAVLChip->m_DemodFrequency_10kHz*10);
++
++ // Initialize the tx_control
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0x00000300;
++ i1 |= 0x20; //reset tx_fifo
++ i1 |= ((AVL_uint32)(pDiseqcPara->m_TXGap) << 6);
++ i1 |= ((AVL_uint32)(pDiseqcPara->m_TxWaveForm) << 4);
++ i1 |= (1<<3); //enable tx gap.
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ i1 &= ~(0x20); //release tx_fifo reset
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++
++ // Initialize the rx_control
++ i1 = ((AVL_uint32)(pDiseqcPara->m_RxWaveForm) << 2);
++ i1 |= (1<<1); //active the receiver
++ i1 |= (1<<3); //envelop high when tone present
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_rx_cntrl_addr, i1);
++ i1 = (AVL_uint32)(pDiseqcPara->m_RxTimeout);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_rx_msg_tim_addr, i1);
++
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_srst_addr, 0);
++
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ pAVLChip->Diseqc_OP_Status = AVL_DVBSx_DOS_Initialized;
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_ReadModulationData( AVL_puchar pucBuff, AVL_puchar pucSize, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1,i2;
++ AVL_uchar pucBuffTemp[4];
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_rx_st_addr, &i1);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i2);
++ if((i2>>8) & 0x01)
++ {
++ pAVLChip->Diseqc_OP_Status = AVL_DVBSx_DOS_InModulation;
++ }
++ if( AVL_DVBSx_DOS_InModulation == pAVLChip->Diseqc_OP_Status )
++ {
++ // In modulation mode
++ if( (!((i2>>8) & 0x01 ) && (0x00000004 == (i1 & 0x00000004))) || (((i2>>8) & 0x01 ) &&(0x00000004 != (i1 & 0x00000004))))
++ {
++ *pucSize = (AVL_uchar)((i1 & 0x00000078)>>3);
++ //Receive data
++ for( i1=0; i1<*pucSize; i1++ )
++ {
++ r |= AVL_DVBSx_II2C_Read(pAVLChip, diseqc_rx_fifo_map_addr, pucBuffTemp, 4);
++ pucBuff[i1] = pucBuffTemp[3];
++ }
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SendModulationData( const AVL_puchar pucBuff, AVL_uchar ucSize, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1, i2;
++ AVL_uchar pucBuffTemp[8];
++ AVL_uchar Continuousflag = 0;
++ AVL_uchar uiTempOutTh = 0;
++
++ if( ucSize>8 )
++ {
++ r = AVL_DVBSx_EC_MemoryRunout;
++ }
++ else
++ {
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_IDiseqc_IsSafeToSwitchMode(pAVLChip);
++ if( AVL_DVBSx_EC_OK == r)
++ {
++ if (pAVLChip->Diseqc_OP_Status == AVL_DVBSx_DOS_InContinuous)
++ {
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ if ((i1>>10) & 0x01)
++ {
++ Continuousflag = 1;
++ i1 &= 0xfffff3ff;
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ r |= AVL_DVBSx_IBSP_Delay(Diseqc_delay);
++ }
++ }
++ //reset rx_fifo
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_rx_cntrl_addr, &i2);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_rx_cntrl_addr, (i2|0x01));
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_rx_cntrl_addr, (i2&0xfffffffe));
++
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0xfffffff8; //set to modulation mode and put it to FIFO load mode
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++
++ //trunk address
++ ChunkAddr(diseqc_tx_fifo_map_addr, pucBuffTemp);
++ pucBuffTemp[3] = 0;
++ pucBuffTemp[4] = 0;
++ pucBuffTemp[5] = 0;
++ for( i2=0; i2Diseqc_OP_Status = AVL_DVBSx_DOS_InModulation;
++ }
++ do
++ {
++ r |= AVL_DVBSx_IBSP_Delay(1);
++ if (++uiTempOutTh > 500)
++ {
++ r |= AVL_DVBSx_EC_TimeOut;
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++ }
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_st_addr, &i1);
++ } while ( 1 != ((i1 & 0x00000040) >> 6) );
++
++ r = AVL_DVBSx_IBSP_Delay(Diseqc_delay); //delay 15ms
++ if (Continuousflag == 1) //resume to send out wave
++ {
++ //No data in FIFO
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0xfffffff8;
++ i1 |= 0x03; //switch to continuous mode
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++
++ //start to send out wave
++ i1 |= (1<<10);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ pAVLChip->Diseqc_OP_Status = AVL_DVBSx_DOS_InContinuous;
++ }
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetTxStatus( struct AVL_DVBSx_Diseqc_TxStatus * pTxStatus, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ if( (AVL_DVBSx_DOS_InModulation == pAVLChip->Diseqc_OP_Status) || (AVL_DVBSx_DOS_InTone == pAVLChip->Diseqc_OP_Status) )
++ {
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_st_addr, &i1);
++ pTxStatus->m_TxDone = (AVL_uchar)((i1 & 0x00000040)>>6);
++ pTxStatus->m_TxFifoCount = (AVL_uchar)((i1 & 0x0000003c)>>2);
++ }
++ else
++ {
++ r |= AVL_DVBSx_EC_GeneralFail;
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetRxStatus( struct AVL_DVBSx_Diseqc_RxStatus * pRxStatus, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ if( AVL_DVBSx_DOS_InModulation == pAVLChip->Diseqc_OP_Status )
++ {
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_rx_st_addr, &i1);
++ pRxStatus->m_RxDone = (AVL_uchar)((i1 & 0x00000004)>>2);
++ pRxStatus->m_RxFifoCount = (AVL_uchar)((i1 & 0x000000078)>>3);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_rx_parity_addr, &i1);
++ pRxStatus->m_RxFifoParChk = (AVL_uchar)(i1 & 0x000000ff);
++ }
++ else
++ {
++ r |= AVL_DVBSx_EC_GeneralFail;
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SetLNBOut( AVL_uchar uiOut, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0xfffffdff;
++ i1 |= ((uiOut & 0x1)<<9);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ r |= AVL_DVBSx_IBSP_Delay(Diseqc_delay);
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetLNBOut( AVL_puchar puiOut, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0x00000200;
++ *puiOut = (AVL_uchar)(i1>>9);
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SendTone( AVL_uchar ucTone, AVL_uchar ucCount, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1, i2;
++ AVL_uchar pucBuffTemp[8];
++ AVL_uchar Continuousflag = 0;
++ AVL_uchar uiTempOutTh = 0;
++
++ if( ucCount>8 )
++ {
++ r = AVL_DVBSx_EC_MemoryRunout;
++ }
++ else
++ {
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_IDiseqc_IsSafeToSwitchMode(pAVLChip);
++
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ if (pAVLChip->Diseqc_OP_Status == AVL_DVBSx_DOS_InContinuous)
++ {
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ if ((i1>>10) & 0x01)
++ {
++ Continuousflag = 1;
++ i1 &= 0xfffff3ff;
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ r |= AVL_DVBSx_IBSP_Delay(Diseqc_delay);
++ }
++ }
++ //No data in the FIFO.
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0xfffffff8; //put it into the FIFO load mode.
++ if( 0 == ucTone )
++ {
++ i1 |= 0x01;
++ }
++ else
++ {
++ i1 |= 0x02;
++ }
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++
++ //trunk address
++ ChunkAddr(diseqc_tx_fifo_map_addr, pucBuffTemp);
++ pucBuffTemp[3] = 0;
++ pucBuffTemp[4] = 0;
++ pucBuffTemp[5] = 0;
++ pucBuffTemp[6] = 1;
++
++ for( i2=0; i2Diseqc_OP_Status = AVL_DVBSx_DOS_InTone;
++ }
++ do
++ {
++ r |= AVL_DVBSx_IBSP_Delay(1);
++ if (++uiTempOutTh > 500)
++ {
++ r |= AVL_DVBSx_EC_TimeOut;
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++ }
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_st_addr, &i1);
++ } while ( 1 != ((i1 & 0x00000040) >> 6) );
++
++ r = AVL_DVBSx_IBSP_Delay(Diseqc_delay); //delay 15ms
++ if (Continuousflag == 1) //resume to send out wave
++ {
++ //No data in FIFO
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0xfffffff8;
++ i1 |= 0x03; //switch to continuous mode
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++
++ //start to send out wave
++ i1 |= (1<<10);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ pAVLChip->Diseqc_OP_Status = AVL_DVBSx_DOS_InContinuous;
++ }
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_StartContinuous (struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_IDiseqc_IsSafeToSwitchMode(pAVLChip);
++
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ //No data in FIFO
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0xfffffff8;
++ i1 |= 0x03; //switch to continuous mode
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++
++ //start to send out wave
++ i1 |= (1<<10);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ pAVLChip->Diseqc_OP_Status = AVL_DVBSx_DOS_InContinuous;
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_StopContinuous (struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 i1;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ if( AVL_DVBSx_DOS_InContinuous == pAVLChip->Diseqc_OP_Status )
++ {
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, diseqc_tx_cntrl_addr, &i1);
++ i1 &= 0xfffff3ff;
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, diseqc_tx_cntrl_addr, i1);
++ }
++
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_SetLNB1Out( AVL_uchar uiOut, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 uiTemp;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, gpio_reg_enb, &uiTemp);
++ uiTemp &= ~(1<<1);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, gpio_reg_enb, uiTemp);
++
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, gpio_data_reg_out, &uiTemp);
++ if(uiOut)
++ {
++ uiTemp |= 1<<1 ;
++ }
++ else
++ {
++ uiTemp &= ~(1<<1) ;
++ }
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, gpio_data_reg_out, uiTemp);
++ r |= AVL_DVBSx_IBSP_Delay(Diseqc_delay);
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IDiseqc_GetLNB1Out( AVL_puchar puiOut, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 uiTemp;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semDiseqc));
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, gpio_data_reg_out, &uiTemp);
++ if(uiTemp & (1<<1))
++ {
++ *puiOut = 1;
++ }
++ else
++ {
++ *puiOut = 0;
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semDiseqc));
++ return(r);
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/II2C.c b/drivers/amlogic/dvb_tv/avl6211/src/II2C.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/II2C.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/II2C.c 2014-12-11 16:13:50.289616089 +0100
+@@ -0,0 +1,258 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "II2C.h"
++#include "IBSP.h"
++
++/// @cond
++AVL_semaphore gI2CSem[2];
++/// @endcond
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Initialize(void)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ static AVL_uchar gI2CSem_inited = 0;
++ if( 0 == gI2CSem_inited )
++ {
++ gI2CSem_inited = 1;
++ r = AVL_DVBSx_IBSP_InitSemaphore(&(gI2CSem[0]));
++ r = AVL_DVBSx_IBSP_InitSemaphore(&(gI2CSem[1]));
++ }
++ return r;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Read( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiOffset, AVL_puchar pucBuff, AVL_uint16 uiSize)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pucBuffTemp[3];
++ AVL_uint16 ui1, ui2;
++ AVL_uint16 iSize;
++
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(gI2CSem[pAVLChip->m_uiBusId]));
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ ChunkAddr(uiOffset, pucBuffTemp);
++ ui1 = 3;
++ r = AVL_DVBSx_IBSP_I2CWrite(pAVLChip, pucBuffTemp, &ui1);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ if( uiSize & 1 )
++ {
++ iSize = uiSize - 1;
++ }
++ else
++ {
++ iSize = uiSize;
++ }
++ ui2 = 0;
++ while( iSize > MAX_II2C_READ_SIZE )
++ {
++ ui1 = MAX_II2C_READ_SIZE;
++ r |= AVL_DVBSx_IBSP_I2CRead(pAVLChip, pucBuff+ui2, &ui1);
++ ui2 += MAX_II2C_READ_SIZE;
++ iSize -= MAX_II2C_READ_SIZE;
++ }
++
++ if( 0 != iSize )
++ {
++ r |= AVL_DVBSx_IBSP_I2CRead(pAVLChip, pucBuff+ui2, &iSize);
++ }
++
++ if( uiSize & 1 )
++ {
++ ui1 = 2;
++ r |= AVL_DVBSx_IBSP_I2CRead(pAVLChip, pucBuffTemp, &ui1);
++ pucBuff[uiSize-1] = pucBuffTemp[0];
++ }
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(gI2CSem[pAVLChip->m_uiBusId]));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_ReadDirect( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_uint16 uiSize)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pucBuffTemp[3];
++ AVL_uint16 ui1, ui2;
++ AVL_uint16 iSize;
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(gI2CSem[pAVLChip->m_uiBusId]));
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ if( uiSize & 1 )
++ {
++ iSize = uiSize - 1;
++ }
++ else
++ {
++ iSize = uiSize;
++ }
++ ui2 = 0;
++ while( iSize > MAX_II2C_READ_SIZE )
++ {
++ ui1 = MAX_II2C_READ_SIZE;
++ r |= AVL_DVBSx_IBSP_I2CRead(pAVLChip, pucBuff+ui2, &ui1);
++ ui2 += MAX_II2C_READ_SIZE;
++ iSize -= MAX_II2C_READ_SIZE;
++ }
++
++ if( 0 != iSize )
++ {
++ r |= AVL_DVBSx_IBSP_I2CRead(pAVLChip, pucBuff+ui2, &iSize);
++ }
++
++ if( uiSize & 1 )
++ {
++ ui1 = 2;
++ r |= AVL_DVBSx_IBSP_I2CRead(pAVLChip, pucBuffTemp, &ui1);
++ pucBuff[uiSize-1] = pucBuffTemp[0];
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(gI2CSem[pAVLChip->m_uiBusId]));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Write( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puchar pucBuff, AVL_uint16 uiSize)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pucBuffTemp[5];
++ AVL_uint16 ui1, ui2, uTemp;
++ AVL_uint16 iSize;
++ AVL_uint32 uAddr;
++ if( uiSize<3 )
++ {
++ return(AVL_DVBSx_EC_GeneralFail); //at least 3 bytes
++ }
++
++ uiSize -= 3; //actual data size
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(gI2CSem[pAVLChip->m_uiBusId]));
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ //dump address
++ uAddr = pucBuff[0];
++ uAddr = uAddr<<8;
++ uAddr += pucBuff[1];
++ uAddr = uAddr<<8;
++ uAddr += pucBuff[2];
++
++ if( uiSize & 1 )
++ {
++ iSize = uiSize -1;
++ }
++ else
++ {
++ iSize = uiSize;
++ }
++
++ uTemp = (MAX_II2C_Write_SIZE-3) & 0xfffe; //how many bytes data we can transfer every time
++
++ ui2 = 0;
++ while( iSize > uTemp )
++ {
++ ui1 = uTemp+3;
++ //save the data
++ pucBuffTemp[0] = pucBuff[ui2];
++ pucBuffTemp[1] = pucBuff[ui2+1];
++ pucBuffTemp[2] = pucBuff[ui2+2];
++ ChunkAddr(uAddr, pucBuff+ui2);
++ r |= AVL_DVBSx_IBSP_I2CWrite(pAVLChip, pucBuff+ui2, &ui1);
++ //restore data
++ pucBuff[ui2] = pucBuffTemp[0];
++ pucBuff[ui2+1] = pucBuffTemp[1];
++ pucBuff[ui2+2] = pucBuffTemp[2];
++ uAddr += uTemp;
++ ui2 += uTemp;
++ iSize -= uTemp;
++ }
++ ui1 = iSize+3;
++ //save the data
++ pucBuffTemp[0] = pucBuff[ui2];
++ pucBuffTemp[1] = pucBuff[ui2+1];
++ pucBuffTemp[2] = pucBuff[ui2+2];
++ ChunkAddr(uAddr, pucBuff+ui2);
++ r |= AVL_DVBSx_IBSP_I2CWrite(pAVLChip, pucBuff+ui2, &ui1);
++ //restore data
++ pucBuff[ui2] = pucBuffTemp[0];
++ pucBuff[ui2+1] = pucBuffTemp[1];
++ pucBuff[ui2+2] = pucBuffTemp[2];
++ uAddr += iSize;
++ ui2 += iSize;
++
++ if( uiSize & 1 )
++ {
++ ChunkAddr(uAddr, pucBuffTemp);
++ ui1 = 3;
++ r |= AVL_DVBSx_IBSP_I2CWrite(pAVLChip, pucBuffTemp, &ui1);
++ ui1 = 2;
++ r |= AVL_DVBSx_IBSP_I2CRead(pAVLChip, pucBuffTemp+3, &ui1);
++ pucBuffTemp[3] = pucBuff[ui2+3];
++ ui1 = 5;
++ r |= AVL_DVBSx_IBSP_I2CWrite(pAVLChip, pucBuffTemp, &ui1);
++ }
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(gI2CSem[pAVLChip->m_uiBusId]));
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Read16( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_puint16 puiData )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pBuff[2];
++
++ r = AVL_DVBSx_II2C_Read(pAVLChip, uiAddr, pBuff, 2);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ *puiData = DeChunk16(pBuff);
++ //printf("puiData is %x\n",*puiData);
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Read32( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_puint32 puiData )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pBuff[4];
++
++ r = AVL_DVBSx_II2C_Read(pAVLChip, uiAddr, pBuff, 4);
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ *puiData = DeChunk32(pBuff);
++ //printf("puiData is %x\n",*puiData);
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Write16( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_uint16 uiData )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pBuff[5];
++
++ ChunkAddr(uiAddr, pBuff);
++ Chunk16(uiData, pBuff+3);
++
++ r = AVL_DVBSx_II2C_Write(pAVLChip, pBuff, 5);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2C_Write32( const struct AVL_DVBSx_Chip * pAVLChip, AVL_uint32 uiAddr, AVL_uint32 uiData )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pBuff[7];
++
++ ChunkAddr(uiAddr, pBuff);
++ Chunk32(uiData, pBuff+3);
++ r = AVL_DVBSx_II2C_Write(pAVLChip, pBuff, 7);
++ return(r);
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/II2CRepeater.c b/drivers/amlogic/dvb_tv/avl6211/src/II2CRepeater.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/II2CRepeater.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/II2CRepeater.c 2014-12-11 16:13:50.213616675 +0100
+@@ -0,0 +1,187 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "II2CRepeater.h"
++#include "IBSP.h"
++#include "II2C.h"
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_SendOP(AVL_puchar pBuff, AVL_uchar ucSize, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ const AVL_uint16 uiTimeDelay = 5;
++ const AVL_uint16 uiMaxRetries = 60;
++ AVL_uint32 i;
++
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semI2CRepeater));
++
++ i = 0;
++ while (AVL_DVBSx_EC_OK != AVL_DVBSx_II2CRepeater_GetOPStatus(pAVLChip)) //Maximum waiting time is 300mS.
++ {
++ if (uiMaxRetries < i++)
++ {
++ r |= AVL_DVBSx_EC_Running;
++ break;
++ }
++ AVL_DVBSx_IBSP_Delay(uiTimeDelay);
++ }
++
++ if ( AVL_DVBSx_EC_OK == r )
++ {
++ r = AVL_DVBSx_II2C_Write(pAVLChip, pBuff, ucSize);
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semI2CRepeater));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_Initialize( AVL_uint16 I2CBusClock_kHz, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_uchar pBuff[5];
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Write16(pAVLChip, rc_i2cm_speed_kHz_addr, I2CBusClock_kHz);
++ ChunkAddr(i2cm_cmd_addr+I2CM_CMD_LENGTH-2, pBuff);
++ pBuff[3] = 0x01;
++ pBuff[4] = OP_I2CM_INIT;
++ r |= AVL_DVBSx_II2CRepeater_SendOP(pBuff, 5, pAVLChip);
++ return r;
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_GetOPStatus( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pBuff[2];
++ r = AVL_DVBSx_II2C_Read(pAVLChip, i2cm_cmd_addr+I2CM_CMD_LENGTH-2, pBuff, 2);
++ if ( AVL_DVBSx_EC_OK == r )
++ {
++ if ( pBuff[1] != 0 )
++ {
++ r = AVL_DVBSx_EC_Running;
++ }
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_ReadData( AVL_uchar ucSlaveAddr, AVL_puchar pucBuff, AVL_uint16 uiSize, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pBuff[I2CM_RSP_LENGTH];
++ AVL_uint16 uiTimeOut;
++ const AVL_uint16 uiTimeOutTh = 500;
++ const AVL_uint32 uiTimeDelay = 1;
++
++ if ( uiSize > I2CM_RSP_LENGTH )
++ {
++ return(AVL_DVBSx_EC_GeneralFail);
++ }
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semI2CRepeater_r));
++
++ ChunkAddr(i2cm_cmd_addr+I2CM_CMD_LENGTH-4, pBuff);
++ pBuff[3] = 0x0;
++ pBuff[4] = (AVL_uchar)uiSize;
++ pBuff[5] = ucSlaveAddr;
++ pBuff[6] = OP_I2CM_READ;
++ r |= AVL_DVBSx_II2CRepeater_SendOP(pBuff, 7, pAVLChip);
++ if ( AVL_DVBSx_EC_OK == r )
++ {
++ uiTimeOut = 0;
++ do
++ {
++ r |= AVL_DVBSx_IBSP_Delay(uiTimeDelay);
++ if ((++uiTimeOut) >= uiTimeOutTh)
++ {
++ r |= AVL_DVBSx_EC_TimeOut;
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semI2CRepeater_r));
++ return(r);
++ }
++ } while ( AVL_DVBSx_EC_OK != AVL_DVBSx_II2CRepeater_GetOPStatus(pAVLChip) );
++
++ r |= AVL_DVBSx_II2C_Read(pAVLChip, i2cm_rsp_addr, pucBuff, uiSize);
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semI2CRepeater_r));
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_ReadData_Multi( AVL_uchar ucSlaveAddr, AVL_puchar pucBuff, AVL_uchar ucRegAddr, AVL_uint16 uiSize, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uchar pBuff[I2CM_RSP_LENGTH];
++ AVL_uint16 uiTimeOut;
++ const AVL_uint16 uiTimeOutTh = 500;
++ const AVL_uint32 uiTimeDelay = 1;
++
++ if ( uiSize > I2CM_RSP_LENGTH )
++ {
++ return(AVL_DVBSx_EC_GeneralFail);
++ }
++
++ r = AVL_DVBSx_IBSP_WaitSemaphore(&(pAVLChip->m_semI2CRepeater_r));
++
++ ChunkAddr(i2cm_cmd_addr+I2CM_CMD_LENGTH-6, pBuff);
++ pBuff[3] = 0;
++ pBuff[4] = ucRegAddr;
++ pBuff[5] = 0x1;
++ pBuff[6] = (AVL_uchar)uiSize;
++ pBuff[7] = ucSlaveAddr;
++ pBuff[8] = OP_I2CM_READ;
++ r |= AVL_DVBSx_II2CRepeater_SendOP(pBuff, 9, pAVLChip);
++ memset(pBuff,0,I2CM_RSP_LENGTH);
++ if ( AVL_DVBSx_EC_OK == r )
++ {
++ uiTimeOut = 0;
++ do
++ {
++ r |= AVL_DVBSx_IBSP_Delay(uiTimeDelay);
++ if ((++uiTimeOut) >= uiTimeOutTh)
++ {
++ r |= AVL_DVBSx_EC_TimeOut;
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semI2CRepeater_r));
++ return(r);
++ }
++ } while ( AVL_DVBSx_EC_OK != AVL_DVBSx_II2CRepeater_GetOPStatus(pAVLChip) );
++
++ r |= AVL_DVBSx_II2C_Read(pAVLChip, i2cm_rsp_addr, pucBuff, uiSize);
++ // printf("pucBuff is %x,%x,%x,%x\n",pucBuff[0],pucBuff[1],pucBuff[2],pucBuff[3]);
++ }
++ r |= AVL_DVBSx_IBSP_ReleaseSemaphore(&(pAVLChip->m_semI2CRepeater_r));
++
++ return(r);
++}
++
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_II2CRepeater_SendData( AVL_uchar ucSlaveAddr, const AVL_puchar pucBuff, AVL_uint16 uiSize, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_uchar pBuff[I2CM_CMD_LENGTH+3];
++ AVL_uint16 i1, i2;
++ AVL_uint16 cmdSize;
++
++ if ( uiSize>I2CM_CMD_LENGTH-3 )
++ {
++ return(AVL_DVBSx_EC_GeneralFail);
++ }
++
++ cmdSize = ((3+uiSize)%2)+3+uiSize; /* How many bytes need send to Availink device through i2c interface */
++ ChunkAddr(i2cm_cmd_addr+I2CM_CMD_LENGTH-cmdSize, pBuff);
++
++ i1 = 3+((3+uiSize)%2); /* skip one byte if the uisize+3 is odd*/
++
++ for ( i2=0; i2m_DemodFrequency_10kHz);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_int_fec_clk_MHz_addr, pAVLChip->m_FecFrequency_10kHz);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_int_mpeg_clk_MHz_addr, pAVLChip->m_MpegFrequency_10kHz);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_format_addr, 1);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetFreqSweepRange( AVL_uint16 uiFreqSweepRange_10kHz, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ if(uiFreqSweepRange_10kHz > 500)
++ {
++ uiFreqSweepRange_10kHz = 500;
++ }
++ return AVL_DVBSx_II2C_Write16(pAVLChip, rc_int_carrier_freq_half_range_MHz_addr, uiFreqSweepRange_10kHz);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetChannelLockMode( struct AVL_DVBSx_Channel * psChannel, enum AVL_DVBSx_LockMode enumChannelLockMode )
++{
++ if(enumChannelLockMode == AVL_DVBSx_LOCK_MODE_FIXED)
++ {
++ psChannel->m_Flags &= ~CI_FLAG_LOCK_MODE_BIT_MASK;
++ }
++ else
++ {
++ psChannel->m_Flags |= CI_FLAG_LOCK_MODE_BIT_MASK;
++ }
++
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_LockChannel( struct AVL_DVBSx_Channel * psChannel, struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 IQ;
++ AVL_uint32 autoIQ_Detect;
++ AVL_uint16 Standard;
++ AVL_uint16 auto_manual_lock;
++ AVL_uint16 Coderate;
++ AVL_uint16 Modulation;
++ enum AVL_DVBSx_LockMode LockMode;
++ enum AVL_DVBSx_FunctionalMode enumFunctionalMode;
++ r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_IBase_GetFunctionalMode(&enumFunctionalMode, pAVLChip);
++ if(enumFunctionalMode == AVL_DVBSx_FunctMode_Demod)
++ {
++ LockMode = (enum AVL_DVBSx_LockMode)((psChannel->m_Flags & CI_FLAG_LOCK_MODE_BIT_MASK) >> CI_FLAG_LOCK_MODE_BIT);
++ if(LockMode == AVL_DVBSx_LOCK_MODE_ADAPTIVE)
++ {
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_lock_mode_addr, 1);
++ if(psChannel->m_uiSymbolRate_Hz < 3000000)
++ {
++ r |= AVL_DVBSx_IRx_SetFreqSweepRange(300, pAVLChip);
++ }
++ else
++ {
++ r |= AVL_DVBSx_IRx_SetFreqSweepRange(500, pAVLChip);
++ }
++ }
++ else
++ {
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_lock_mode_addr, 0);
++ }
++ IQ = ((psChannel->m_Flags) & CI_FLAG_IQ_BIT_MASK)>>CI_FLAG_IQ_BIT;
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_specinv_addr, IQ);
++ Standard = (AVL_uint16)(((psChannel->m_Flags) & CI_FLAG_DVBS2_BIT_MASK)>>CI_FLAG_DVBS2_BIT);
++ autoIQ_Detect = (((psChannel->m_Flags) & CI_FLAG_IQ_AUTO_BIT_MASK)>>CI_FLAG_IQ_AUTO_BIT);
++ auto_manual_lock = (((psChannel->m_Flags) & CI_FLAG_MANUAL_LOCK_MODE_BIT_MASK)>>CI_FLAG_MANUAL_LOCK_MODE_BIT);
++ if(auto_manual_lock == CI_FLAG_MANUAL_LOCK_MODE)
++ {
++ Coderate = ((psChannel->m_Flags) & CI_FLAG_CODERATE_BIT_MASK)>>CI_FLAG_CODERATE_BIT;
++ if(Standard == CI_FLAG_DVBS)
++ {
++ if (Coderate > 5)
++ {
++ return AVL_DVBSx_EC_GeneralFail;
++ }
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_fec_coderate_addr, Coderate);
++ }
++ else if(Standard == CI_FLAG_DVBS2)
++ {
++ Modulation = ((psChannel->m_Flags) & CI_FLAG_MODULATION_BIT_MASK)>>CI_FLAG_MODULATION_BIT;
++ if (Coderate > 16 || Coderate <= 5 || Modulation > 3)
++ {
++ return AVL_DVBSx_EC_GeneralFail;
++ }
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_s2_coderate, Coderate);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_s2_modulation, Modulation);
++ }
++ else
++ return AVL_DVBSx_EC_GeneralFail;
++ }
++ else
++ {
++ if(Standard == CI_FLAG_DVBS2_UNDEF || autoIQ_Detect == 1)
++ {
++ Standard = 0x14;
++ }
++ }
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_fec_bypass_coderate_addr, auto_manual_lock);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_decode_mode_addr, Standard);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_iq_mode_addr, (AVL_uint16)autoIQ_Detect);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_int_sym_rate_MHz_addr, psChannel->m_uiSymbolRate_Hz);
++ r |= AVL_DVBSx_IBase_SendRxOP(OP_RX_INIT_GO, pAVLChip );
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetLockStatus( AVL_puint16 puiLockStatus, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Read16(pAVLChip, rs_fec_lock_addr, puiLockStatus);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ResetErrorStat( struct AVL_DVBSx_Chip * pAVLChip )
++{
++ enum AVL_DVBSx_FunctionalMode enumFunctionalMode;
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_IBase_GetFunctionalMode(&enumFunctionalMode, pAVLChip);
++
++ if(enumFunctionalMode == AVL_DVBSx_FunctMode_Demod)
++ {
++ r |= AVL_DVBSx_IBase_SendRxOP( OP_RX_RESET_BERPER, pAVLChip );
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetRFAGCPola( enum AVL_DVBSx_RfagcPola enumAGCPola, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 uiTemp;
++ uiTemp = (AVL_uint32)enumAGCPola;
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, rc_rfagc_pol_addr, uiTemp);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegMode( const struct AVL_DVBSx_MpegInfo * pMpegMode, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_mode_addr, (AVL_uint32)(pMpegMode->m_MpegFormat));
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_mpeg_serial_addr, (AVL_uint16)(pMpegMode->m_MpegMode));
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_mpeg_posedge_addr, (AVL_uint16)(pMpegMode->m_MpegClockPolarity));
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegValidPolarity( const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegValidPolarity enumValidPolarity )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiTemp;
++
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rp_mpeg_config_addr, &uiTemp);
++ uiTemp &= 0xFFFE;
++ uiTemp |= (AVL_uint16)enumValidPolarity;
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rp_mpeg_config_addr, uiTemp);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegErrorPolarity(const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegErrorPolarity enumErrorLockPolarity, enum AVL_DVBSx_MpegErrorPolarity enumErrorUnlockPolarity)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiTemp;
++
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rp_mpeg_config_addr, &uiTemp);
++ uiTemp &= 0xFFF3;
++ uiTemp |= (enumErrorLockPolarity << 2);
++ uiTemp |= (enumErrorUnlockPolarity << 3);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rp_mpeg_config_addr, uiTemp);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegBitOrder( const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegMode enumMpegMode, enum AVL_DVBSx_MpegBitOrder enumMpegBitOrder )
++{
++ AVL_uint16 uiTemp;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rp_mpeg_config_addr, &uiTemp);
++ uiTemp &= 0xFFFD;
++ if(enumMpegMode == AVL_DVBSx_MPM_Serial)
++ {
++ AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_seri_seq_addr, (AVL_uint32)enumMpegBitOrder);
++ }
++ else
++ {
++ uiTemp |= ((AVL_uint16)enumMpegBitOrder << 1);
++ }
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rp_mpeg_config_addr, uiTemp);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegSerialPin( const struct AVL_DVBSx_Chip * pAVLChip, enum AVL_DVBSx_MpegSerialPin enumSerialPin )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_outpin_sel_addr, enumSerialPin);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetSignalLevel( AVL_puint16 puiRFSignalLevel , const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_uint32 uiData;
++ AVL_uint16 uiSignalLevel;
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, (rx_aagc_gain), &uiData);
++
++ if( AVL_DVBSx_EC_OK == r )
++ {
++ uiData += 0x800000;
++ uiData &= 0xffffff;
++ uiSignalLevel = (AVL_uint16)(uiData>>8);
++ *puiRFSignalLevel = uiSignalLevel;
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetScatterData( AVL_puchar ucpData, AVL_puint16 puiSize, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_uint16 ucTemp1, ucTemp2;
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Read16(pAVLChip, rs_ScatterData_rdy_addr, &ucTemp1);
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, scatter_data_addr, &ucTemp2);
++ if( (AVL_DVBSx_EC_OK != r) || (0 == ucTemp1) )
++ {
++ return(AVL_DVBSx_EC_Running);
++ }
++ if( ucTemp2>(*puiSize) )
++ {
++ ucTemp2 = (*puiSize);
++ }
++ else
++ {
++ (*puiSize) = ucTemp2;
++ }
++
++ r = AVL_DVBSx_II2C_Read(pAVLChip, scatter_data_addr+2, ucpData, (AVL_uint16)(ucTemp2<<1)); //both i and q
++ ucTemp1 = 0;
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rs_ScatterData_rdy_addr, ucTemp1);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetSNR( AVL_puint32 puiSNR_db, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rs_int_SNR_dB_addr, puiSNR_db);
++ if( (*puiSNR_db) > 10000 )
++ {
++ // Not get stable SNR value yet.
++ *puiSNR_db = 0;
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetPER( AVL_puint32 puiPER, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 hw_packets;
++ AVL_uint32 hw_errors;
++ struct AVL_uint64 ui64ErrTemp;
++ struct AVL_uint64 ui64Packets;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rc_pkt_err_count_addr, &hw_errors);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rc_pkt_count_addr, &hw_packets);
++
++ if((hw_packets != 0) && (hw_errors != 0))
++ {
++ Multiply32(&ui64ErrTemp, hw_errors, AVL_CONSTANT_10_TO_THE_9TH);
++ ui64Packets.m_HighWord = 0;
++ ui64Packets.m_LowWord = 0;
++ Add32To64(&ui64Packets, hw_packets);
++ *puiPER = Divide64( ui64Packets, ui64ErrTemp);
++ }
++ else
++ {
++ *puiPER = 0;
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetBER( AVL_puint32 puiBER, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rp_uint_BER_addr, puiBER);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetDVBSBER( AVL_puint32 puiBER, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rc_dvbs_ber_addr, puiBER);
++ if( 0xffffffff == (*puiBER) )
++ {
++ r |= AVL_DVBSx_EC_GeneralFail;
++ }
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ResetDVBSBER( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, rc_dvbs_ber_addr, 0xffffffff);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetRFOffset( AVL_pint16 piRFOffset_100kHz, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ r = AVL_DVBSx_II2C_Read16(pAVLChip, rs_int_carrier_freq_100kHz_addr, (AVL_puint16)piRFOffset_100kHz);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetSignalInfo( struct AVL_DVBSx_SignalInfo * pSignalInfo, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiTemp;
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rs_pilot_addr, &uiTemp);
++ pSignalInfo->m_pilot = (enum AVL_DVBSx_Pilot)(uiTemp);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rs_code_rate_addr, &uiTemp);
++ pSignalInfo->m_coderate = (enum AVL_DVBSx_FecRate)(uiTemp);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rs_modulation_addr, &uiTemp);
++ pSignalInfo->m_modulation = (enum AVL_DVBSx_ModulationMode)(uiTemp);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rx_Rolloff_addr, &uiTemp);
++ pSignalInfo->m_rolloff = (enum AVL_DVBSx_RollOff)((uiTemp>>22) & 0x03);
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetDishPointingMode( AVL_uchar ucMode, const struct AVL_DVBSx_Chip *pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ enum AVL_DVBSx_FunctionalMode enumFunctionalMode;
++
++ r |= AVL_DVBSx_IBase_GetFunctionalMode(&enumFunctionalMode, pAVLChip);
++ if(enumFunctionalMode == AVL_DVBSx_FunctMode_Demod)
++ {
++ if(ucMode == 1)
++ {
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_aagc_acq_gain_addr, 12);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_dishpoint_mode_addr, 1);
++ }
++ else
++ {
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_aagc_acq_gain_addr, 10);
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_dishpoint_mode_addr, 0);
++ }
++ }
++ else
++ {
++ r = AVL_DVBSx_EC_GeneralFail;
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DriveMpegOutput( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_bus_tri_enb, 1);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ReleaseMpegOutput( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_bus_tri_enb, 0);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_EnableMpegPersistentClockMode( AVL_uint16 uiMpegDataClkFreq_10kHz, const struct AVL_DVBSx_Chip *pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ uiMpegDataClkFreq_10kHz |= 0x8000;
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_mpeg_continuous_mode_control_addr, uiMpegDataClkFreq_10kHz);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DisableMpegPersistentClockMode( const struct AVL_DVBSx_Chip *pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_II2C_Write16(pAVLChip, rc_mpeg_continuous_mode_control_addr, 0);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_EnableMpegManualClockFrequency( AVL_uint16 uiMpegDataClkFreq_10kHz, enum AVL_DVBSx_MpegMode enumMpegMode, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiMpegRefClkFreq;
++ AVL_uint32 uiTemp;
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rc_mpeg_bus_cntrl_addr, &uiTemp );
++ uiTemp |= 0x00000800;
++ r |=AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_bus_cntrl_addr, uiTemp );
++
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rc_int_mpeg_clk_MHz_addr, &uiMpegRefClkFreq);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_cntns_pkt_para_rate_frac_n_addr,(AVL_uint32)(uiMpegDataClkFreq_10kHz << 1));
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_cntns_pkt_para_rate_frac_d_addr, (AVL_uint32)uiMpegRefClkFreq);
++ if(enumMpegMode == AVL_DVBSx_MPM_Serial)
++ {
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_pkt_seri_rate_frac_n_addr, (AVL_uint32)((uiMpegDataClkFreq_10kHz/8)<< 4));
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_pkt_seri_rate_frac_d_addr, (AVL_uint32)uiMpegRefClkFreq);
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DisableMpegManualClockFrequency( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_uint32 uiTemp;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rc_mpeg_bus_cntrl_addr, &uiTemp );
++ uiTemp &= 0xFFFFF7FF;
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_bus_cntrl_addr, uiTemp );
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetMpegPulldown( const struct AVL_DVBSx_Chip *pAVLChip, enum AVL_DVBSx_MpegPulldown enumPulldownState )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_EC_OK;
++ if(enumPulldownState == AVL_DVBSx_MPPD_Disable)
++ {
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_bus_pe, 0);
++ }
++ else
++ {
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_mpeg_bus_pe, 0xFFF);
++ }
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_DriveRFAGC( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r = AVL_DVBSx_II2C_Write16(pAVLChip, rc_aagc_ref_addr, 0x30);
++ r |= AVL_DVBSx_II2C_Write32(pAVLChip, rc_rfagc_tri_enb, 1);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_ReleaseRFAGC( const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r = AVL_DVBSx_II2C_Write32(pAVLChip, rc_rfagc_tri_enb, 0);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetIQ_Imbalance( const struct AVL_DVBSx_Chip * pAVLChip, AVL_pint16 piAmplitude, AVL_pint16 piPhase )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rp_amp_imb_addr, (AVL_puint16)piAmplitude);
++ r |= AVL_DVBSx_II2C_Read16(pAVLChip, rp_phase_imb_addr, (AVL_puint16)piPhase);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetDeviceID( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puint32 puiDeviceID)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rs_cust_chip_id_addr, puiDeviceID);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_SetAdaptivePowerSaveMode( struct AVL_DVBSx_Channel * psChannel, AVL_uint16 uiEnable )
++{
++ if(uiEnable == 0)
++ {
++ psChannel->m_Flags &= ~CI_FLAG_ADAPTIVE_POWER_SAVE_BIT_MASK;
++ }
++ else
++ {
++ psChannel->m_Flags |= CI_FLAG_ADAPTIVE_POWER_SAVE_BIT_MASK;
++ }
++
++ return(AVL_DVBSx_EC_OK);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetIQ_Swap( const struct AVL_DVBSx_Chip * pAVLChip, AVL_puint16 puiIQ_Swap )
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiTemp1, uiTemp2;
++
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rc_specinv_addr, &uiTemp1);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rc_eq_out_iq_swap_addr, &uiTemp2);
++ *puiIQ_Swap = (AVL_uint16)(uiTemp1 ^ uiTemp2);
++
++ return(r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetRSError( AVL_puint32 puiRSErr, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint32 rs_total_words, rs_total_errors;
++ struct AVL_uint64 ui64ErrTemp;
++ struct AVL_uint64 ui64Words;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rs_total_words_addr, &rs_total_words);
++ r |= AVL_DVBSx_II2C_Read32(pAVLChip, rs_total_uncorrected_words_addr, &rs_total_errors);
++
++ if((rs_total_words != 0) && (rs_total_errors != 0))
++ {
++ Multiply32(&ui64ErrTemp, rs_total_errors, AVL_CONSTANT_10_TO_THE_9TH);
++ ui64Words.m_HighWord = 0;
++ ui64Words.m_LowWord = 0;
++ Add32To64(&ui64Words, rs_total_words);
++ *puiRSErr = Divide64( ui64Words, ui64ErrTemp);
++ }
++ else
++ {
++ *puiRSErr = 0;
++ }
++
++ return (r);
++}
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_IRx_GetErrPacket( AVL_puint32 puiErrPacket, const struct AVL_DVBSx_Chip * pAVLChip )
++{
++ AVL_DVBSx_ErrorCode r;
++
++ r = AVL_DVBSx_II2C_Read32(pAVLChip, rc_pkt_err_count_addr, puiErrPacket);
++
++ return(r);
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/ITuner.c b/drivers/amlogic/dvb_tv/avl6211/src/ITuner.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/ITuner.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/ITuner.c 2014-12-11 16:13:50.245616432 +0100
+@@ -0,0 +1,27 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++#include "avl_dvbsx.h"
++#include "ITuner.h"
++#include "II2C.h"
++
++AVL_DVBSx_ErrorCode AVL_DVBSx_ITuner_CalculateLPF(AVL_uint16 uiSymbolRate_10kHz, struct AVL_Tuner * pTuner)
++{
++ AVL_uint32 lpf = uiSymbolRate_10kHz;
++ lpf *= 675; //roll off = 0.35
++ lpf /= 10000;
++ lpf += 30;
++ pTuner->m_uiLPF_100kHz = (AVL_uint16)lpf;
++ return(AVL_DVBSx_EC_OK);
++}
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/LockSignal_Api.c b/drivers/amlogic/dvb_tv/avl6211/src/LockSignal_Api.c
+--- a/drivers/amlogic/dvb_tv/avl6211/src/LockSignal_Api.c 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/LockSignal_Api.c 2014-12-11 16:13:50.289616089 +0100
+@@ -0,0 +1,704 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++//#include "stdio.h"
++#include "IBSP.h"
++#include "avl_dvbsx.h"
++#include "IBase.h"
++#include "IRx.h"
++#include "ITuner.h"
++#include "ExtSharpBS2S7HZ6306.h"
++#include "II2C.h"
++#include "IDiseqc.h"
++#include "IBlindScan.h"
++#include "LockSignal_Api.h"
++#include "ExtAV2011.h"
++#include "ucPatchData.h"
++
++
++struct Signal_Level SignalLevel [47]=
++{
++ {8285, -922},{10224, -902},{12538, -882},{14890, -862},{17343, -842},{19767, -822},{22178, -802},{24618, -782},{27006, -762},{29106, -742},
++ {30853, -722},{32289, -702},{33577, -682},{34625, -662},{35632, -642},{36552, -622},{37467, -602},{38520, -582},{39643, -562},{40972, -542},
++ {42351, -522},{43659, -502},{44812, -482},{45811, -462},{46703, -442},{47501, -422},{48331, -402},{49116, -382},{49894, -362},{50684, -342},
++ {51543, -322},{52442, -302},{53407, -282},{54314, -262},{55208, -242},{56000, -222},{56789, -202},{57544, -182},{58253, -162},{58959, -142},
++ {59657, -122},{60404, -102},{61181, -82},{62008, -62},{63032, -42},{65483, -22},{65535, -12}
++
++};
++
++extern const unsigned char ucPatchData [];
++
++
++//extern AVL_uchar ucPatchData []; //Defined in AVL6211_patch.dat.cpp.
++//extern struct Signal_Level SignalLevel [47]; //Defined in SignalLevel.cpp
++
++#define Chip_ID 0x0F //0x01000002 //The Chip ID of AVL6211.
++#define Diseqc_Tone_Frequency 22 //The DiSEqC bus speed in the unit of kHz. Normally, it should be 22kHz.
++#define IQ_Swap Auto //Controls the IQ swap setting enum AVL_DVBS_IQ_Swap
++#define standard DVBS2 //Controls the standard setting enum AVL_DVBS_standard
++
++#define FontEnd_MaxCount 2
++struct AVL_DVBSx_Chip g_stAvlDVBSxChip[FontEnd_MaxCount];
++struct AVL_Tuner g_stTuner[FontEnd_MaxCount];
++
++enum AVL_DVBS_IQ_Swap
++{
++ Normal, //< = 0 The received signal spectrum is not inverted.
++ Invert, //< = 1 The received signal spectrum is inverted.
++ Auto //< = 2 The demodulator will automatically detect the received signal spectrum.
++};
++
++enum AVL_DVBS_standard
++{
++ DVBS,
++ DVBS2,
++};
++
++enum AVL_Demod_ReferenceClock_Select_t
++{
++ Ref_clock_4M=0,
++ Ref_clock_4M5=1,
++ Ref_clock_10M=2,
++ Ref_clock_16M=3,
++ Ref_clock_27M=4,
++ Ref_clock_Enhance_4M=5,
++ Ref_clock_Enhance_4M5=6,
++ Ref_clock_Enhance_10M=7,
++ Ref_clock_Enhance_16M=8,
++ Ref_clock_Enhance_27M=9,
++};
++
++enum AVL_TunerLPF_Calculation_Flag
++{
++ InputLPF = 0,
++ InputSymbolRate = 1,
++};
++
++struct AVL_Demod_Tuner_Configuration_t
++{
++ ////////////////////////////Demod Configure///////////////////////////////
++
++ AVL_char m_ChannelId; ///< Bus identifier.
++ AVL_uint16 m_uiDemodAddress; ///< Device I2C slave address.
++ enum AVL_Demod_ReferenceClock_Select_t m_DemodReferenceClk; ///< Configures the Availink device's PLL.Refer to enum AVL_Demod_ReferenceClock_Select_t
++
++ ///< The MPEG output mode. The default value in the Availink device is \a AVL_DVBSx_MPM_Parallel
++ enum AVL_DVBSx_MpegMode m_TSOutPutMode; ///< AVL_DVBSx_MPM_Parallel = 0; Output MPEG data in parallel mode
++ ///< AVL_DVBSx_MPM_Serial = 1; Output MPEG data in serial mode
++
++ ///< The MPEG output clock polarity. The clock polarity should be configured to meet the back end device's requirement.The default value in the Availink device is \a AVL_DVBSx_MPCP_Rising.
++ enum AVL_DVBSx_MpegClockPolarity m_TSClockPolarity; ///< AVL_DVBSx_MPCP_Falling = 0; The MPEG data is valid on the falling edge of the clock.
++ ///< AVL_DVBSx_MPCP_Rising = 1; The MPEG data is valid on the rising edge of the clock.
++
++ ///< The MPEG output format. The default value in the Availink device is \a AVL_DVBSx_MPF_TS
++ enum AVL_DVBSx_MpegFormat m_TSFormat; ///< AVL_DVBSx_MPF_TS = 0; Transport stream format.
++ ///< AVL_DVBSx_MPF_TSP = 1; Transport stream plus parity format.
++
++ ///< Defines the pin on which the Availink device outputs the MPEG data when the MPEG interface has been configured to operate in serial mode.
++ enum AVL_DVBSx_MpegSerialPin m_SerDataPin; ///< AVL_DVBSx_MPSP_DATA0 = 0; Serial data is output on pin MPEG_DATA_0
++ ///< AVL_DVBSx_MPSP_DATA7 = 1; Serial data is output on pin MPEG_DATA_7
++
++ ////////////////////////////Tuner Configure///////////////////////////////
++
++ AVL_uint16 m_uiTunerAddress; ///< Tuner I2C slave address.
++ AVL_uint16 m_uiTuner_I2Cbus_clock; ///< The clock speed of the tuner dedicated I2C bus, in a unit of kHz.
++ AVL_uint16 m_uiTunerMaxLPF_100Khz; ///< The max low pass filter bandwidth of the tuner.
++
++ ///< Defines the LPF's forms of computation.
++ enum AVL_TunerLPF_Calculation_Flag m_LPF_Config_flag; ///< InputLPF = 0; The LPF will be calculated by formula which defined by user.
++ ///< InputSymbolRate = 1; The LPF will be calculated in tuner driver according to the SymbolRate.
++
++ ///< Defines the polarity of the RF AGC control signal.The polarity of the RF AGC control signal must be configured to match that required by the tuner.
++ enum AVL_DVBSx_RfagcPola m_TunerRFAGC; ///< AVL_DVBSx_RA_Normal = 0; Normal polarization. This setting is used for a tuner whose gain increases with increased AGC voltage.
++ ///< AVL_DVBSx_RA_Invert = 1; Inverted polarization. The default value. Most tuners fall into this category. This setting is used for a tuner whose gain decreases with increased AGC voltage.
++
++ ///< Defines the device spectrum polarity setting.
++ enum AVL_DVBSx_SpectrumPolarity m_Tuner_IQ_SpectrumMode; ///< AVL_DVBSx_Spectrum_Normal = 0; The received signal spectrum is not inverted.
++ ///< AVL_DVBSx_Spectrum_Invert = 1; The received signal spectrum is inverted.
++
++ AVL_DVBSx_ErrorCode (* m_pInitializeFunc)(struct AVL_Tuner *); ///< A pointer to the tuner initialization function.
++ AVL_DVBSx_ErrorCode (* m_pGetLockStatusFunc)(struct AVL_Tuner *); ///< A pointer to the tuner GetLockStatus function.
++ AVL_DVBSx_ErrorCode (* m_pLockFunc)(struct AVL_Tuner *); ///< A pointer to the tuner Lock function.
++};
++
++
++/*Here please according to customer needs, defining the array index*/
++
++static AVL_char g_nDemodTunerArrayIndex = 0;
++
++struct AVL_Demod_Tuner_Configuration_t g_DemodTuner_Config[]=
++{
++ {
++ 0,
++ AVL_DVBSx_SA_0,
++ Ref_clock_27M,
++#ifdef AVL6211_OUTPUT_SERIAL
++ AVL_DVBSx_MPM_Serial,
++#else
++ AVL_DVBSx_MPM_Parallel,
++#endif
++ AVL_DVBSx_MPCP_Rising,//AVL_DVBSx_MPCP_Rising,
++ AVL_DVBSx_MPF_TS,
++ AVL_DVBSx_MPSP_DATA0,
++
++ 0xC0,
++ 200,
++ 440,
++ InputSymbolRate,
++ AVL_DVBSx_RA_Invert,
++ #if defined(CONFIG_AVLINK_SPECTRUM_INVERT)
++ AVL_DVBSx_Spectrum_Invert,
++ #else
++ AVL_DVBSx_Spectrum_Normal,
++ #endif
++ &AVL_DVBSx_ExtAV2011_Initialize,
++ &AVL_DVBSx_ExtAV2011_GetLockStatus,
++ &AVL_DVBSx_ExtAV2011_Lock,
++ },
++ {
++ 1,
++ AVL_DVBSx_SA_0,
++ Ref_clock_27M,
++ AVL_DVBSx_MPM_Parallel,
++ AVL_DVBSx_MPCP_Rising,
++ AVL_DVBSx_MPF_TS,
++ AVL_DVBSx_MPSP_DATA0,
++
++ 0xC0,
++ 200,
++ 440,
++ InputSymbolRate,
++ AVL_DVBSx_RA_Invert,
++ #if defined(CONFIG_AVLINK_SPECTRUM_INVERT)
++ AVL_DVBSx_Spectrum_Invert,
++ #else
++ AVL_DVBSx_Spectrum_Normal,
++ #endif
++ &AVL_DVBSx_ExtAV2011_Initialize,
++ &AVL_DVBSx_ExtAV2011_GetLockStatus,
++ &AVL_DVBSx_ExtAV2011_Lock,
++ },
++};
++
++
++AVL_uchar DVBS_SNR[6] ={12,32,41,52,58,62};
++AVL_uchar DVBS2Qpsk_SNR[8] ={10,24,32,41,47,52,63,65};
++AVL_uchar DVBS28psk_SNR[6] ={57,67,80,95,100,110};
++
++int AVL_Get_Quality_Percent(struct AVL_DVBSx_Chip * pAVLChip)
++{
++ AVL_DVBSx_ErrorCode r=AVL_DVBSx_EC_OK;
++ AVL_uint32 uiSNR;
++ AVL_uint16 uiLockStatus=0;
++ AVL_uchar SNRrefer = 0;;
++ AVL_uchar Quality=5;
++ AVL_uchar i;
++ struct AVL_DVBSx_SignalInfo SignalInfo;
++
++ for(i=0;i<5;i++)
++ {
++ AVL_DVBSx_IBSP_Delay(10);
++ r |= AVL_DVBSx_IRx_GetLockStatus(&uiLockStatus, pAVLChip);
++ if(uiLockStatus!=1) break;
++ }
++ if(i==5)
++ {
++ r |= AVL_DVBSx_IRx_GetSNR(&uiSNR, pAVLChip);
++ r |= AVL_DVBSx_IRx_GetSignalInfo(&SignalInfo, pAVLChip);
++ }
++ else
++ return Quality;
++
++ if (SignalInfo.m_coderate < RX_DVBS2_1_4)
++ {
++ SNRrefer = DVBS_SNR[SignalInfo.m_coderate];
++ }
++ else
++ {
++ if (SignalInfo.m_modulation == AVL_DVBSx_MM_8PSK)
++ SNRrefer = DVBS28psk_SNR[SignalInfo.m_coderate -RX_DVBS2_3_5];
++ else
++ SNRrefer = DVBS2Qpsk_SNR[SignalInfo.m_coderate -RX_DVBS2_1_2];
++ }
++
++ if ((uiSNR/10) > SNRrefer)
++ {
++ uiSNR = uiSNR/10 - SNRrefer;
++ if(uiSNR>=100)
++ Quality = 99;
++ else if(uiSNR>=50) // >5.0dB
++ Quality = 80+ (uiSNR-50)*20/50;
++ else if(uiSNR>=25) // > 2.5dB
++ Quality = 50+ (uiSNR-25)*30/25;
++ else if(uiSNR>=10) // > 1dB
++ Quality = 25+ (uiSNR-10)*25/15;
++ else
++ Quality = 5+ (uiSNR)*20/10;
++ }
++ else
++ {
++ Quality = 5;
++ }
++
++ return Quality;
++}
++
++
++struct Signal_Level AGC_LUT [91]=
++{
++ {63688, 0},{62626, -1},{61840, -2},{61175, -3},{60626, -4},{60120, -5},{59647, -6},{59187, -7},{58741, -8},{58293, -9},
++ {57822,-10},{57387,-11},{56913,-12},{56491,-13},{55755,-14},{55266,-15},{54765,-16},{54221,-17},{53710,-18},{53244,-19},
++ {52625,-20},{52043,-21},{51468,-22},{50904,-23},{50331,-24},{49772,-25},{49260,-26},{48730,-27},{48285,-28},{47804,-29},
++ {47333,-30},{46880,-31},{46460,-32},{46000,-33},{45539,-34},{45066,-35},{44621,-36},{44107,-37},{43611,-38},{43082,-39},
++ {42512,-40},{41947,-41},{41284,-42},{40531,-43},{39813,-44},{38978,-45},{38153,-46},{37294,-47},{36498,-48},{35714,-49},
++ {35010,-50},{34432,-51},{33814,-52},{33315,-53},{32989,-54},{32504,-55},{32039,-56},{31608,-57},{31141,-58},{30675,-59},
++ {30215,-60},{29711,-61},{29218,-62},{28688,-63},{28183,-64},{27593,-65},{26978,-66},{26344,-67},{25680,-68},{24988,-69},
++ {24121,-70},{23285,-71},{22460,-72},{21496,-73},{20495,-74},{19320,-75},{18132,-76},{16926,-77},{15564,-78},{14398,-79},
++ {12875,-80},{11913,-81},{10514,-82},{ 9070,-83},{ 7588,-84},{ 6044,-85},{ 4613,-86},{ 3177,-87},{ 1614,-88},{ 123,-89},
++ { 0,-90}
++};
++
++AVL_int16 AVL_Get_Level_Percent(struct AVL_DVBSx_Chip * pAVLChip)
++{
++
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 Level;
++ AVL_int16 i;
++ AVL_int16 Percent;
++/*
++ #define Level_High_Stage 36
++ #define Level_Low_Stage 70
++
++ #define Percent_Space_High 6
++ #define Percent_Space_Mid 44
++ #define Percent_Space_Low 50 //Percent_Space_High+Percent_Space_Mid+Percent_Space_Low = 100
++
++*/
++ #define Level_High_Stage 36
++ #define Level_Low_Stage 76
++
++ #define Percent_Space_High 10
++ #define Percent_Space_Mid 30
++ #define Percent_Space_Low 60
++
++
++ i = 0;
++ Percent = 0;
++
++ r = AVL_DVBSx_IRx_GetSignalLevel(&Level,pAVLChip);
++
++ while(Level < AGC_LUT[i++].SignalLevel);
++
++ if(i<= Level_High_Stage)
++ Percent = Percent_Space_Low+Percent_Space_Mid+ (Level_High_Stage-i)*Percent_Space_High/Level_High_Stage;
++ else if(i<=Level_Low_Stage)
++ Percent = Percent_Space_Low+ (Level_Low_Stage-i)*Percent_Space_Mid/(Level_Low_Stage-Level_High_Stage);
++ else
++ Percent =(90-i)*Percent_Space_Low/(90-Level_Low_Stage);
++
++ return Percent;
++}
++
++
++
++
++void AVL_DVBSx_Error_Dispose(AVL_DVBSx_ErrorCode r)
++{
++ switch(r)
++ {
++ case AVL_DVBSx_EC_OK:
++ printf("AVL_DVBSx_EC_OK !\n");
++ break;
++ case AVL_DVBSx_EC_GeneralFail:
++ printf("AVL_DVBSx_EC_GeneralFail !\n");
++ break;
++ case AVL_DVBSx_EC_I2CFail:
++ printf("AVL_DVBSx_EC_I2CFail !\n");
++ break;
++ case AVL_DVBSx_EC_TimeOut:
++ printf("AVL_DVBSx_EC_TimeOut !\n");
++ break;
++ case AVL_DVBSx_EC_Running:
++ printf("AVL_DVBSx_EC_Running !\n");
++ break;
++ case AVL_DVBSx_EC_InSleepMode:
++ printf("AVL_DVBSx_EC_InSleepMode !\n");
++ break;
++ case AVL_DVBSx_EC_MemoryRunout:
++ printf("AVL_DVBSx_EC_MemoryRunout !\n");
++ break;
++ case AVL_DVBSx_EC_BSP_ERROR1:
++ printf("AVL_DVBSx_EC_BSP_ERROR1 !\n");
++ break;
++ case AVL_DVBSx_EC_BSP_ERROR2:
++ printf("AVL_DVBSx_EC_BSP_ERROR2 !\n");
++ break;
++ }
++}
++
++AVL_DVBSx_ErrorCode CPU_Halt(struct AVL_DVBSx_Chip * pAVLChip)
++{
++ AVL_DVBSx_ErrorCode r;
++ AVL_uint16 i= 0;
++
++ r = AVL_DVBSx_IBase_SendRxOP(OP_RX_HALT, pAVLChip );
++ printf("%s r is %d",__FUNCTION__,r);
++ if(AVL_DVBSx_EC_OK == r)
++ {
++ while(i++<20)
++ {
++ r = AVL_DVBSx_IBase_GetRxOPStatus(pAVLChip);
++ if(AVL_DVBSx_EC_OK == r)
++ {
++ break;
++ }
++ else
++ {
++ AVL_DVBSx_IBSP_Delay(10);
++ }
++ }
++ }
++ printf("%s r is %d",__FUNCTION__,r);
++ return (r);
++}
++
++void AVL_Set_LPF(int iDeviceId ,struct AVL_Tuner * pTuner, AVL_uint32 m_uiSymbolRate_Hz)
++{
++ struct AVL_Demod_Tuner_Configuration_t *pDemodTunerConfig = &g_DemodTuner_Config[iDeviceId];
++
++ if (pDemodTunerConfig->m_LPF_Config_flag == InputSymbolRate)
++ {
++ pTuner->m_uiLPF_100kHz = m_uiSymbolRate_Hz/(1000*100);
++ }
++ else
++ {
++ pTuner->m_uiLPF_100kHz = (m_uiSymbolRate_Hz*75)/(1000*100*100)+40;
++ }
++
++ if (pTuner->m_uiLPF_100kHz > pDemodTunerConfig->m_uiTunerMaxLPF_100Khz)
++ {
++ pTuner->m_uiLPF_100kHz = pDemodTunerConfig->m_uiTunerMaxLPF_100Khz;
++ }
++}
++
++
++AVL_DVBSx_ErrorCode AVL6211_Initialize(struct AVL_DVBSx_Chip * pAVLChip,struct AVL_Tuner * pTuner,int iDeviceIndex)
++{
++ struct AVL_DVBSx_Diseqc_Para sDiseqcPara;
++ struct AVL_DVBSx_MpegInfo sMpegMode;
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ struct AVL_Demod_Tuner_Configuration_t *pDemodTunerConfig = &g_DemodTuner_Config[iDeviceIndex];
++ struct AVL_DVBSx_VerInfo VerInfo;
++ //AVL_uint32 uiTemp;
++ AVL_uint32 uiDeviceID=0;
++#if 0
++ //This function should be implemented by customer.
++ //This function should be called before all other functions to prepare everything for a BSP operation.
++ r = AVL_DVBSx_IBSP_Initialize();
++
++ if( AVL_DVBSx_EC_OK != r )
++ {
++ printf("BSP Initialization failed !\n");
++ return (r);
++ }
++#endif
++
++ pAVLChip->m_uiBusId=pDemodTunerConfig->m_ChannelId;
++ //pAVLChip->m_uiDeviceId = iDeviceIndex;
++ printk(" (AVL6211_Initialize), iDeviceIndex = %d ,pAVLChip->m_uiBusId = %d \n",iDeviceIndex,pAVLChip->m_uiBusId);
++
++ // This function should be called after bsp initialized to initialize the chip object.
++ r = Init_AVL_DVBSx_ChipObject(pAVLChip, pDemodTunerConfig->m_uiDemodAddress);
++ if( AVL_DVBSx_EC_OK != r )
++ {
++ printf("Chip Object Initialization failed !\n");
++ return (r);
++ }
++
++ //Judge the chip ID of current chip.
++ //r = AVL_DVBSx_II2C_Read32(pAVLChip, rom_ver_addr, &uiTemp);
++
++ r= AVL_DVBSx_IRx_GetDeviceID( pAVLChip, &uiDeviceID);
++ printk("r is %x,uiDeviceID is %x\n",r,uiDeviceID);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Get Chip ID failed !\n");
++ return (r);
++ }
++
++ //if ( uiTemp != Chip_ID )
++ if(uiDeviceID != Chip_ID )
++ {
++ printf("Chip ID isn't correct !\n");
++ return AVL_DVBSx_EC_GeneralFail;
++ }
++
++ //This function should be called after chip object initialized to initialize the IBase,using reference clock as 10M. Make sure you pickup the right pll_conf since it may be modified in BSP.
++ r = AVL_DVBSx_IBase_Initialize(&(pll_conf[pDemodTunerConfig->m_DemodReferenceClk]), ucPatchData, pAVLChip);
++ if( AVL_DVBSx_EC_OK != r )
++ {
++ printf("IBase Initialization failed !\n");
++ return (r);
++ }
++ AVL_DVBSx_IBSP_Delay(100); //Wait 100 ms to assure that the AVL_DVBSx chip boots up.This function should be implemented by customer.
++
++
++ //This function should be called to verify the AVL_DVBSx chip has completed its initialization procedure.
++ r = AVL_DVBSx_IBase_GetStatus(pAVLChip);
++ if( AVL_DVBSx_EC_OK != r )
++ {
++ printf("Booted failed !\n");
++ return (r);
++ }
++ printf("Booted !\n");
++
++ //Get Chip ID, Patch version and SDK version.
++ AVL_DVBSx_IBase_GetVersion( &VerInfo, pAVLChip);
++ printf("Chip Ver:{%d}.{%d}.{%d} API Ver:{%d}.{%d}.{%d} Patch Ver:{%d}.{%d}.{%d} \n",
++ VerInfo.m_Chip.m_Major, VerInfo.m_Chip.m_Minor, VerInfo.m_Chip.m_Build,
++ VerInfo.m_API.m_Major, VerInfo.m_API.m_Minor, VerInfo.m_API.m_Build,
++ VerInfo.m_Patch.m_Major, VerInfo.m_Patch.m_Minor, VerInfo.m_Patch.m_Build);
++
++ //This function should be called after IBase initialized to initialize the demod.
++ r = AVL_DVBSx_IRx_Initialize(pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Demod Initialization failed !\n");
++ return (r);
++ }
++ //This function should be called after demod initialized to set RF AGC polar.
++ //User does not need to setup this for Sharp tuner since it is the default value. But for other tuners, user may need to do it here.
++ r |= AVL_DVBSx_IRx_SetRFAGCPola(pDemodTunerConfig->m_TunerRFAGC, pAVLChip);
++ r |= AVL_DVBSx_IRx_DriveRFAGC(pAVLChip);
++
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set RF AGC Polar failed !\n");
++ return (r);
++ }
++
++ //This function should be called after demod initialized to set spectrum polar.
++ r = AVL_DVBSx_IBase_SetSpectrumPolarity(pDemodTunerConfig->m_Tuner_IQ_SpectrumMode, pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set Spectrum Polar failed !\n");
++ return (r);
++ }
++
++ //Setup MPEG mode parameters.
++ sMpegMode.m_MpegFormat = pDemodTunerConfig->m_TSFormat;
++ sMpegMode.m_MpegMode = pDemodTunerConfig->m_TSOutPutMode;
++ sMpegMode.m_MpegClockPolarity = pDemodTunerConfig->m_TSClockPolarity;
++
++ //This function should be called after demod initialized to set MPEG mode.(These parameters will be valid after call lock channel function)
++ r = AVL_DVBSx_IRx_SetMpegMode(&sMpegMode,pAVLChip );
++
++ if(sMpegMode.m_MpegMode == AVL_DVBSx_MPM_Serial)
++ {
++ AVL_DVBSx_IRx_SetMpegSerialPin(pAVLChip,pDemodTunerConfig->m_SerDataPin);
++ }
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Set MPEG output mode failed !\n");
++ return (r);
++ }
++
++ // Enable the MPEG output (this function call has no effect for the AVL_DVBSxLG and AVL_DVBSxLGa devices)
++ r = AVL_DVBSx_IRx_DriveMpegOutput(pAVLChip);
++
++ //Setup tuner parameters for tuner initialization.
++ pTuner->m_uiSlaveAddress = pDemodTunerConfig->m_uiTunerAddress;
++ pTuner->m_uiI2CBusClock_kHz = pDemodTunerConfig->m_uiTuner_I2Cbus_clock;
++ pTuner->m_pParameters = 0;
++ pTuner->m_pAVLChip = pAVLChip;
++ pTuner->m_pInitializeFunc = pDemodTunerConfig->m_pInitializeFunc;
++ pTuner->m_pLockFunc = pDemodTunerConfig->m_pLockFunc;
++ pTuner->m_pGetLockStatusFunc = pDemodTunerConfig->m_pGetLockStatusFunc;
++
++ //This function should be called after IBase initialized to initialize the tuner.
++ r = pTuner->m_pInitializeFunc(pTuner);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Tuner Initialization failed !\n");
++ return (r);
++ }
++
++ //Setup DiSEqC parameters for DiSEqC initialization.
++ sDiseqcPara.m_RxTimeout = AVL_DVBSx_DRT_150ms;
++ sDiseqcPara.m_RxWaveForm = AVL_DVBSx_DWM_Normal;
++ sDiseqcPara.m_ToneFrequency_kHz = Diseqc_Tone_Frequency;
++ sDiseqcPara.m_TXGap = AVL_DVBSx_DTXG_15ms;
++ sDiseqcPara.m_TxWaveForm = AVL_DVBSx_DWM_Normal;
++
++ //The DiSEqC should be initialized if AVL_DVBSx need to supply power to LNB. This function should be called after IBase initialized to initialize the DiSEqC.
++ r = AVL_DVBSx_IDiseqc_Initialize(&sDiseqcPara, pAVLChip);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("DiSEqC Initialization failed !\n");
++ }
++
++ return (r);
++}
++
++
++struct AVL_Tuner *avl6211pTuner[FE_DEV_COUNT];
++struct AVL_DVBSx_Chip * pAVLChip_all[FE_DEV_COUNT];
++
++
++
++AVL_DVBSx_ErrorCode AVL6211_LockSignal_Init(int iFeId)
++{
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uchar HandIndex = iFeId;
++ struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ struct AVL_Tuner * pTuner = &g_stTuner[HandIndex];
++ avl6211pTuner[iFeId]=pTuner;
++// printk(" johnnyDebug,(AVL6211_LockSignal_Init,start), iFeId = %d pAVLChip_all[iFeId]->m_uiDeviceId = %d,\n",iFeId);
++ //This function do all the initialization work.It should be called only once at the beginning.It needn't be recalled when we want to lock a new channel.
++ r = AVL6211_Initialize(pAVLChip,pTuner,iFeId);
++ pAVLChip_all[iFeId]=pAVLChip;
++ printk(" (AVL6211_LockSignal_Init,end), iFeId = %d ,pAVLChip_all[iFeId]->m_uiDeviceId = %d\n",iFeId,pAVLChip_all[iFeId]->m_uiBusId);
++ if(AVL_DVBSx_EC_OK != r)
++ {
++ printf("Initialization failed !\n");
++ return (r);
++ }
++ printf("Initialization success !\n");
++ return (r);
++}
++
++
++
++AVL_uint32 AVL6211_GETLockStatus(int iDeviceId)
++{
++ AVL_uchar HandIndex = iDeviceId;
++ struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiLockStatus;
++ r = AVL_DVBSx_IRx_GetLockStatus(&uiLockStatus, pAVLChip);
++ //printf("lock status is %d",uiLockStatus);
++ if ((AVL_DVBSx_EC_OK == r)&&(1 == uiLockStatus));
++ return uiLockStatus;
++
++ return uiLockStatus;
++
++}
++
++
++AVL_uint32 AVL6211_GETBer(int iDeviceId)
++{
++ AVL_uchar HandIndex = iDeviceId;
++ struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiBER;
++ //This function can be called to read back the current BER calculation result after function AVL_DVBSx_IDVBSxRx_ResetErrorStat called.
++ r = AVL_DVBSx_IRx_GetDVBSBER(&uiBER, pAVLChip);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Get DVBS BER failed. This function should only be called if the input signal is a DVBS signal.\n");
++ }
++ else
++ {
++ // printf("BER=%.9f\n",(float)(uiBER*1.0e-9));
++ printf("BER=%d*10-9\n",uiBER);
++ }
++ return uiBER;
++}
++
++
++AVL_uint32 AVL6211_GETPer(int iDeviceId)
++{
++ AVL_uchar HandIndex = iDeviceId;
++ struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiPER;
++ //This function can be called to read back the current PER calculation result after function AVL_DVBSx_IDVBSxRx_ResetErrorStat called.
++ r = AVL_DVBSx_IRx_GetPER(&uiPER, pAVLChip);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Get PER --- Fail !\n");
++ }
++ else
++ {
++ // printf("PER=%.9f\n",(float)(uiPER*1.0e-9));
++ printf("PER=%d*10-9\n",uiPER);
++ }
++
++ return uiPER;
++}
++
++
++AVL_uint32 AVL6211_GETSnr(int iDeviceId)
++{
++ AVL_uchar HandIndex = iDeviceId;
++ struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint32 uiSNR;
++ //This function can be called to read back the current SNR estimate after the channel locked and some waiting time.
++ r = AVL_DVBSx_IRx_GetSNR(&uiSNR, pAVLChip);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Get SNR --- Fail !\n");
++ }
++ else
++ {
++ // printf("SNR=%.2fdb\n",(float)(uiSNR/100.0));
++ printf("SNR=%ddb\n",uiSNR/100);
++ }
++ return uiSNR;
++}
++
++
++AVL_uint32 AVL6211_GETSignalLevel(int iDeviceId)
++{
++ AVL_uchar HandIndex = iDeviceId;
++ AVL_uint16 i;
++ struct AVL_DVBSx_Chip * pAVLChip = &g_stAvlDVBSxChip[HandIndex];
++ AVL_DVBSx_ErrorCode r = AVL_DVBSx_EC_OK;
++ AVL_uint16 uiRFSignalLevel;
++ AVL_int16 uiRFSignalDBM;
++ //This function can be called to get the RF signal level after the channel locked.
++ r = AVL_DVBSx_IRx_GetSignalLevel(&uiRFSignalLevel, pAVLChip);
++ if (AVL_DVBSx_EC_OK != r)
++ {
++ printf("Get SignalLevel --- Fail !\n");
++ }
++ else
++ {
++ for(i=0; i<47; i++)
++ {
++ if(uiRFSignalLevel <= SignalLevel[i].SignalLevel)
++ {
++ //Calculate the corresponding DBM value.
++ if((0==i)&&(uiRFSignalLevel < SignalLevel[i].SignalLevel))
++ {
++ printf("RFSignalLevel is too weak !");
++ }
++ else
++ {
++ uiRFSignalDBM = SignalLevel[i].SignalDBM;
++ }
++ break;
++ }
++ }
++ // printf("RFSignalLevel::%.1fdbm\n",(float)(uiRFSignalDBM/10.0));
++ printf("RFSignalLevel::%ddbm\n",uiRFSignalDBM/10);
++ }
++
++ return uiRFSignalDBM;
++}
++
++
++
++
+diff -Naur a/drivers/amlogic/dvb_tv/avl6211/src/SignalLevel.cpp b/drivers/amlogic/dvb_tv/avl6211/src/SignalLevel.cpp
+--- a/drivers/amlogic/dvb_tv/avl6211/src/SignalLevel.cpp 1970-01-01 01:00:00.000000000 +0100
++++ b/drivers/amlogic/dvb_tv/avl6211/src/SignalLevel.cpp 2014-12-11 16:13:50.429615023 +0100
+@@ -0,0 +1,31 @@
++/*
++ * Copyright 2012 Availink, Inc.
++ *
++ * This software contains Availink proprietary information and
++ * its use and disclosure are restricted solely to the terms in
++ * the corresponding written license agreement. It shall not be
++ * disclosed to anyone other than valid licensees without
++ * written permission of Availink, Inc.
++ *
++ */
++
++
++///$Date: 2012-2-9 17:36 $
++///
++
++
++
++#include "LockSignal_Manual_source.h"
++
++struct Signal_Level SignalLevel [47]=
++{
++ {8285, -922},{10224, -902},{12538, -882},{14890, -862},{17343, -842},{19767, -822},{22178, -802},{24618, -782},{27006, -762},{29106, -742},
++ {30853, -722},{32289, -702},{33577, -682},{34625, -662},{35632, -642},{36552, -622},{37467, -602},{38520, -582},{39643, -562},{40972, -542},
++ {42351, -522},{43659, -502},{44812, -482},{45811, -462},{46703, -442},{47501, -422},{48331, -402},{49116, -382},{49894, -362},{50684, -342},
++ {51543, -322},{52442, -302},{53407, -282},{54314, -262},{55208, -242},{56000, -222},{56789, -202},{57544, -182},{58253, -162},{58959, -142},
++ {59657, -122},{60404, -102},{61181, -82},{62008, -62},{63032, -42},{65483, -22},{65535, -12}
++
++};
++
++
++
+diff -Naur a/drivers/amlogic/dvb_tv/Makefile b/drivers/amlogic/dvb_tv/Makefile
+--- a/drivers/amlogic/dvb_tv/Makefile 2014-12-11 15:40:00.089007476 +0100
++++ b/drivers/amlogic/dvb_tv/Makefile 2014-12-11 15:56:35.209504705 +0100
+@@ -12,10 +12,7 @@
+
+ obj-$(CONFIG_AM_M6_DEMOD) += amldemod/
+
+-ifneq ($(wildcard $(srctree)/../hardware/dvb),)
+- obj-$(CONFIG_AM_ATBM8869) += ../../../../hardware/dvb/altobeam/drivers/atbm887x/
+- obj-$(CONFIG_AM_SI2177) += ../../../../hardware/dvb/silabs/drivers/si2177/
+- obj-$(CONFIG_AM_AVL6211) += ../../../../hardware/dvb/availink/drivers/avl6211/
+-endif
++obj-$(CONFIG_AM_AVL6211) += avl6211/
+
++EXTRA_CFLAGS += -Idrivers/media/dvb-core
+ EXTRA_CFLAGS += -I.
diff --git a/projects/WeTek.Play/patches/linux/g18dtd.patch b/projects/WeTek.Play/patches/linux/g18dtd.patch
new file mode 100644
index 0000000000..54495b4d83
--- /dev/null
+++ b/projects/WeTek.Play/patches/linux/g18dtd.patch
@@ -0,0 +1,2675 @@
+diff -Naur a/arch/arm/boot/dts/amlogic/meson6_g18.dtd b/arch/arm/boot/dts/amlogic/meson6_g18.dtd
+--- a/arch/arm/boot/dts/amlogic/meson6_g18.dtd 2014-12-11 15:25:42.771688733 +0100
++++ b/arch/arm/boot/dts/amlogic/meson6_g18.dtd 2014-12-11 15:30:01.493678109 +0100
+@@ -1,761 +1,751 @@
+-/*
+- * Amlogic-MX SKT Device Tree Source
+- *
+- * Copyright Amlogic 2013
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- */
+-
+-/dts-v1/;
+-/// ***************************************************************************************\n
+-//$$ PROJECT="meson6"
+-//$$ REMOVE 1
+-void root_func(){
+-//$$ ADD /{
+- compatible = "AMLOGIC,8726_MX";
+- model = "AMLOGIC";
+- interrupt-parent = <&gic>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+-
+-/// ***************************************************************************************
+-/// - CPU
+-//$$ MODULE="CPU"
+- cpus {
+- #address-cells = <1>;
+- #size-cells = <0>;
+-//$$ DEVICE="cpu0"
+- cpu@0 {
+- device_type = "cpu";
+- compatible = "arm,cortex-a9";
+- reg = <0x200>;
+- };
+-//$$ DEVICE="cpu1"
+- cpu@1 {
+- device_type = "cpu";
+- compatible = "arm,cortex-a9";
+- reg = <0x1>;
+- };
+- };
++/*
++ * Amlogic-MX SKT Device Tree Source
++ *
++ * Copyright Amlogic 2013
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++/dts-v1/;
++/// ***************************************************************************************\n
++//$$ PROJECT="meson6"
++//$$ REMOVE 1
++void root_func(){
++//$$ ADD /{
++ compatible = "AMLOGIC,8726_MX";
++ model = "AMLOGIC";
++ interrupt-parent = <&gic>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ chosen {
++ bootargs = "root=/dev/ram0 rdinit=/init boot=/dev/mmcblk0p1 disk=/dev/mmcblk0p2 BOOT_IMAGE=kernel.img console=tty0 consoleblank=0 scaling_governor=hotplug scaling_min_freq=200000 scaling_max_freq=1500000 systemd.show_status=auto";
++ };
++
++/// ***************************************************************************************
++/// - CPU
++//$$ MODULE="CPU"
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++//$$ DEVICE="cpu0"
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <0x200>;
++ };
++//$$ DEVICE="cpu1"
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <0x1>;
++ };
++ };
+ /// ***************************************************************************************
+ /// - Cache
+ //$$ MODULE="Cache"
+ //$$ DEVICE="cache"
+ cache-controller {
+ compatible = "arm,meson-pl310-cache";
+- reg = <0xc4200000 0x1000>;
++ reg = <0xc4200000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ aux-instruction_prefetch;
+ aux-data_prefetch;
+- aux-ns_lockdown;
+- aux-ns_int_ctrl;
+- aux-share_override;
+- aux-cache_replace_policy_round_robin;
+- prefetch-prefetch_offset = <6>;
+- };
+-
+-/// ***************************************************************************************
+-/// - Memory
+-//$$ MODULE="Memory"
+-//$$ DEVICE="memory"
+-//$$ L2 PROP_U32 = "aml_reserved_start"
+-//$$ L2 PROP_U32 = "aml_reserved_end"
+-//$$ L2 PROP_U32 = "linux,usable-memory"
+- memory{
+- device_type = "memory";
+- aml_reserved_start = <0x85000000>; /**reserved memory start-for kernel */
+- aml_reserved_end = <0x84000000>;/**reserved uImage and dtb memory-for uboot*/
++ aux-ns_lockdown;
++ aux-ns_int_ctrl;
++ aux-share_override;
++ aux-cache_replace_policy_round_robin;
++ prefetch-prefetch_offset = <6>;
++ };
++
++/// ***************************************************************************************
++/// - Memory
++//$$ MODULE="Memory"
++//$$ DEVICE="memory"
++//$$ L2 PROP_U32 = "aml_reserved_start"
++//$$ L2 PROP_U32 = "aml_reserved_end"
++//$$ L2 PROP_U32 = "linux,usable-memory"
++ memory{
++ device_type = "memory";
++ aml_reserved_start = <0x85000000>; /**reserved memory start-for kernel */
++ aml_reserved_end = <0x84000000>;/**reserved uImage and dtb memory-for uboot*/
+ phys_offset = <0x80000000>;
+- linux,total-memory = <0x40000000>;/**0x40000000--1G memory 0x80000000--2G memory*/
+- };
+-
+-/// ***************************************************************************************
+-/// - GIC
+-//$$ MODULE="GIC"
+-//$$ DEVICE="gic"
+- gic:interrupt-controller{
+- compatible = "arm,cortex-a9-gic";
+- reg = <0xc4301000 0x1000
+- 0xc4300100 0x0100>;
+- interrupt-controller;
+- #interrupt-cells = <3>;
+- #address-cells = <0>;
+- };
+-
+-/// ***************************************************************************************
+-/// - ION
+-//$$ MODULE="ION"
+-//$$ DEVICE="ion_dev"
+-//$$ L2 PROP_STR = "status"
+- ion_dev{
+- compatible = "amlogic,ion_dev";
+- dev_name = "ion_dev";
+- status = "ok";
++ linux,total-memory = <0x40000000>;/**0x40000000--1G memory 0x80000000--2G memory*/
++ };
++
++/// ***************************************************************************************
++/// - GIC
++//$$ MODULE="GIC"
++//$$ DEVICE="gic"
++ gic:interrupt-controller{
++ compatible = "arm,cortex-a9-gic";
++ reg = <0xc4301000 0x1000
++ 0xc4300100 0x0100>;
++ interrupt-controller;
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ };
++
++/// ***************************************************************************************
++/// - ION
++//$$ MODULE="ION"
++//$$ DEVICE="ion_dev"
++//$$ L2 PROP_STR = "status"
++ ion_dev{
++ compatible = "amlogic,ion_dev";
++ dev_name = "ion_dev";
++ status = "ok";
+ reserve-memory = <0x02000000>;
+- reserve-iomap = "true";
+- };
+-
+-/// **************************************************************************************
+-/// - DISP&MM-FB
+-//$$ MODULE = "DISP&MM-FB"
+-//$$ DEVICE = "mesonfb"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 2 ="reserve-memory"
+-//$$ L2 PROP_U32 = "vmode"
+-//$$ L2 PROP_U32 5 = "display_size_default"
+- mesonfb{
+- compatible = "amlogic,mesonfb";
+- dev_name = "mesonfb";
+- status = "okay";
+- reserve-memory = <0x01000000 0x00100000>;
+- reserve-iomap = "true";
+- vmode = <0>; /*0:VMODE_720P 1:VMODE_LCD 2:VMODE_LVDS_1080P 3:VMODE_1080P*/
+- scale_mode = <0>; /*0:default 1:new*/
+- display_size_default = <1280 1080 1280 3240 32>; // osd0:16M, osd1:1m 1280*1080*4*3 = 16,588,800
+- };
+-//$$ DEVICE="deinterlace"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_U32 = "reserve-memory"
+- deinterlace{
+- compatible = "amlogic,deinterlace";
+- dev_name = "deinterlace";
+- status = "okay";
+- reserve-memory = <0x01c00000>; // 27M
+- reserve-iomap = "true";
+- };
+-
+-/// ***************************************************************************************
+-/// - DISP&MM-A/V stream
+-//$$ MODULE = "DISP&MM-A/V stream"
+-//$$ DEVICE="mesonstream"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 4 ="reserve-memory"
+- mesonstream{
+- compatible = "amlogic,mesonstream";
+- dev_name = "mesonstream.0";
+- status = "okay";
+- reserve-memory = <0x00a00000>; //10M
+- reserve-iomap = "true";
+- };
+-
+-
+-/// ***************************************************************************************
+-/// - DISP&MM-A/V stream
+-//$$ MODULE = "DISP&MM-A/V video dec"
+-//$$ DEVICE="vdec"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 4 ="reg"
+- vdec{
+- compatible = "amlogic,vdec";
+- dev_name = "vdec.0";
+- status = "okay";
+- reserve-memory = <0x02000000>; //32M
+- reserve-iomap = "true";
+- };
+-
+-/// ***************************************************************************************
+-/// - DISP&MM-PostProcess
+-//$$ MODULE="DISP&MM-PostProcess"
+-//$$ DEVICE="ppmgr"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 ="reserve-memory"
+- ppmgr{
+- compatible = "amlogic,ppmgr";
+- dev_name = "ppmgr";
+- status = "okay";
+- reserve-memory = <0x01300000>; // 1280*732*21 = 19,676,160
+- reserve-iomap = "true";
+- };
+-
+-
+-/// ***************************************************************************************
+-/// - DISP&MM-Vout
+-//$$ MODULE = "DISP&MM-Vout"
+-//$$ DEVICE = "mesonvout"
+-//$$ L2 PROP_STR = "status"
+- mesonvout{
+- compatible = "amlogic,mesonvout";
+- dev_name = "mesonvout";
+- status = "okay";
+- };
+-
+-/// ***************************************************************************************
+-/// - EARLY_INIT
+-//$$ MODULE="early_init"
+-//$$ DEVICE = "early_init"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_STR ="gpio-1"
+-//$$ L2 PROP_STR = "gpio-2"
+- early_init{
+- compatible = "amlogic,early_init";
+- dev_name = "early_init";
+- status = "ok";
+- gpio-1 = "GPIOAO_3";
+- gpio-2 = "GPIOAO_2";
+- };
+-
+-/// ***************************************************************************************
+-/// - RTC
+-//$$ MODULE="RTC"
+-//$$ DEVICE="Rtc"
+-//$$ L2 PROP_STR = "status"
+- rtc{
+- compatible = "amlogic,aml_rtc";
+- status = "okay";
+- };
+-
+-/// ***************************************************************************************
+-/// - UART
+-//$$ MODULE="UART"
+-//$$ DEVICE="uart_ao"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_STR = "pinctrl-names"
+-//$$ L3 PROP_CHOICE "uart_ao_pin_match" = "pinctrl-0"
+- uart_ao{
+- compatible = "amlogic,aml_uart";
+- port_name = "uart_ao";
+- status = "okay";
+- dev_name = "uart_ao";
+- pinctrl-names = "default";
+- pinctrl-0 = <&ao_uart_pins>;
+- };
+-
+-//$$ DEVICE="uart_0"
+-//$$ L2 PROP_STR = "status"
+- uart_0{
+- compatible = "amlogic,aml_uart";
+- port_name = "uart_a";
+- status = "okay";
+- dev_name = "uart_0";
+- };
+-
+-//$$ DEVICE="uart_1"
+-//$$ L2 PROP_STR = "status"
+- uart_1{
+- compatible = "amlogic,aml_uart";
+- port_name = "uart_b";
+- status = "disabled";
+- dev_name = "uart_1";
+- };
+-
+-//$$ DEVICE="uart_2"
+-//$$ L2 PROP_STR = "status"
+- uart_2{
+- compatible = "amlogic,aml_uart";
+- port_name = "uart_c";
+- status = "disabled";
+- dev_name = "uart_2";
+- };
+-
+-//$$ DEVICE="uart_3"
+-//$$ L2 PROP_STR = "status"
+- uart_3{
+- compatible = "amlogic,aml_uart";
+- port_name = "uart_d";
+- status = "ok";
+- dev_name = "uart_3";
+- };
+-
+-/// ***************************************************************************************
+-/// - WiFi
+-//$$ MODULE="WiFi"
+-//$$ DEVICE="wifi_power"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_STR = "power_gpio"
+- wifi_power{
+- compatible = "amlogic,wifi_power";
+- dev_name = "wifi_power";
+- status = "okay";
+- power_gpio = "GPIOE_11";
+- };
+-
+-/// ***************************************************************************************
+-/// - MMC
+-//$$ MODULE="MMC"
+-//$$ DEVICE="aml_sdio"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 2 ="reg"
+-//$$ L2 PROP_STR 7 = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "sdio_pin_0_match" = "pinctrl-0"
+-//$$ L2 PROP_CHOICE "sdio_pin_1_match" = "pinctrl-1"
+-//$$ L2 PROP_CHOICE "sdio_pin_2_match" = "pinctrl-2"
+-//$$ L2 PROP_CHOICE "sdio_pin_3_match" = "pinctrl-3"
+-//$$ L2 PROP_CHOICE "sdio_pin_4_match" = "pinctrl-4"
+-//$$ L2 PROP_CHOICE "sdio_pin_5_match" = "pinctrl-5"
+-// L2 PROP_CHOICE "sdio_pin_6_match" = "pinctrl-6"
+- sdio{
+- compatible = "amlogic,aml_sdio";
+- dev_name = "aml_sdio.0";
+- status = "okay";
+- reg = <0xc1108c20 0x20>;
+- pinctrl-names = "sd_clk_cmd_pins", "sd_all_pins", "emmc_clk_cmd_pins", "emmc_all_pins", "sdio_clk_cmd_pins", "sdio_all_pins"; /*sd:sdio_b, emmc:sdio_c, sdio:sdio_a*/
+- // pinctrl-0 = <&sd_pins>;
+- // pinctrl-1 = <&emmc_pins>;
+- // pinctrl-2 = <&sdio_pins>;
+- pinctrl-0 = <&sd_clk_cmd_pins>;
+- pinctrl-1 = <&sd_all_pins>;
+- pinctrl-2 = <&emmc_clk_cmd_pins>;
+- pinctrl-3 = <&emmc_all_pins>;
+- pinctrl-4 = <&sdio_clk_cmd_pins>;
+- pinctrl-5 = <&sdio_all_pins>;
+-
+-//$$ DEVICE="sd"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 = "port"
+-//$$ L2 PROP_STR = "pinname"
+-//$$ L3 PROP_U32 = "ocr_avail"
+-//$$ L2 PROP_STR 3 = "caps"
+-//$$ L3 PROP_U32 = "f_min"
+-//$$ L3 PROP_U32 = "f_max"
+-//$$ L3 PROP_U32 = "f_max_w"
+-//$$ L3 PROP_U32 = "max_req_size"
+-//$$ L2 PROP_STR = "gpio_dat3"
+-//$$ L2 PROP_STR = "jtag_pin"
+-//$$ L2 PROP_STR = "gpio_cd"
+-//$$ L2 PROP_STR = "gpio_ro"
+-//$$ L2 PROP_U32 = "irq_in"
+-//$$ L2 PROP_U32 = "irq_out"
+-//$$ L2 PROP_U32 = "card_type"
+- sd{
+- status = "okay";
+- port = <1>; /**0:sdio_a, 1:sdio_b, 2:sdio_c, 3:sdhc_a, 4:sdhc_b, 5:sdhc_c */
+- pinname = "sd";
+- ocr_avail = <0x200000>; /**VDD voltage 3.3 ~ 3.4 */
+- caps = "MMC_CAP_4_BIT_DATA","MMC_CAP_MMC_HIGHSPEED","MMC_CAP_SD_HIGHSPEED";
+- f_min = <300000>;
+- f_max = <50000000>;
+- f_max_w = <50000000>;
+- max_req_size = <0x20000>; /**128KB*/
+- gpio_dat3 = "CARD_3";
+- gpio_cd = "CARD_6";
+- gpio_power = "CARD_8";
+- power_level = <0>;
+- irq_in = <5>;
+- #irq_in_edge = "GPIO_IRQ_FALLING";
+- irq_out = <6>;
+- #irq_out_edge = "GPIO_IRQ_RISING";
+- card_type = <5>; /* 0:unknown, 1:mmc card(include eMMC), 2:sd card(include tSD), 3:sdio device(ie:sdio-wifi), 4:SD combo (IO+mem) card, 5:NON sdio device(means sd/mmc card), other:reserved */
+- };
+-
+-//$$ DEVICE="emmc"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 = "port"
+-//$$ L2 PROP_STR = "pinname"
+-//$$ L3 PROP_U32 = "ocr_avail"
+-//$$ L2 PROP_STR 4 = "caps"
+-//$$ L3 PROP_U32 = "f_min"
+-//$$ L3 PROP_U32 = "f_max"
+-//$$ L3 PROP_U32 = "f_max_w"
+-//$$ L3 PROP_U32 = "max_req_size"
+-//$$ L2 PROP_STR = "gpio_dat3"
+-//$$ L2 PROP_U32 = "card_type"
+- // emmc{
+- // port = <2>; /*0:sdio_a, 1:sdio_b, 2:sdio_c, 3:sdhc_a, 4:sdhc_b, 5:sdhc_c */
+- // pinname = "emmc";
+- // ocr_avail = <0x200000>; /*VDD voltage 3.3 ~ 3.4 */
+- // caps = "MMC_CAP_4_BIT_DATA","MMC_CAP_MMC_HIGHSPEED","MMC_CAP_SD_HIGHSPEED", "MMC_CAP_NONREMOVABLE"; // MMC_CAP_NEEDS_POLL -- for detect, MMC_CAP_NONREMOVABLE -- for eMMC/TSD
+- // f_min = <300000>;
+- // f_max = <50000000>;
+- // f_max_w = <50000000>;
+- // max_req_size = <0x20000>; /*128KB*/
+- // gpio_dat3 = "BOOT_3";
+- // #gpio_cd = "CARD_6";
+- // #gpio_power = "CARD_8";
+- // #power_level = <0>;
+- // card_type = <5>; /* 0:unknown, 1:mmc card(include eMMC), 2:sd card(include tSD), 3:sdio device(ie:sdio-wifi), 4:SD combo (IO+mem) card, 5:NON sdio device(means sd/mmc card), other:reserved */
+- // };
+-
+- // sdio{
+- // port = <0>; /*0:sdio_a, 1:sdio_b, 2:sdio_c, 3:sdhc_a, 4:sdhc_b, 5:sdhc_c */
+- // pinname = "sdio";
+- // ocr_avail = <0x200000>; /*VDD voltage 3.3 ~ 3.4 */
+- // caps = "MMC_CAP_4_BIT_DATA","MMC_CAP_MMC_HIGHSPEED","MMC_CAP_SD_HIGHSPEED", "MMC_CAP_NONREMOVABLE";
+- // f_min = <300000>;
+- // f_max = <50000000>;
+- // f_max_w = <50000000>;
+- // max_req_size = <0x20000>; /*128KB*/
+- // card_type = <3>; /* 0:unknown, 1:mmc card(include eMMC), 2:sd card(include tSD), 3:sdio device(ie:sdio-wifi), 4:SD combo (IO+mem) card, 5:NON sdio device(means sd/mmc card), other:reserved */
+- // };
+- };
+-
+- // sdhc{
+- // compatible = "amlogic,aml_sdhc";
+- // dev_name = "aml_sdhc.0";
+- // reg = <0xc1108e00 0x30>;
+- // pinctrl-names = "sd"; /*sd:sdio_b, emmc:sdio_c, sdio:sdio_a*/
+- // pinctrl-0 = <&sdhc_b_pins>;
+-
+- // sd{
+- // port = <4>; /*0:sdio_a, 1:sdio_b, 2:sdio_c, 3:sdhc_a, 4:sdhc_b, 5:sdhc_c */
+- // pinname = "sd";
+- // ocr_avail = <0x200000>; /*VDD voltage 3.3 ~ 3.4 */
+- // caps = "MMC_CAP_4_BIT_DATA","MMC_CAP_MMC_HIGHSPEED","MMC_CAP_SD_HIGHSPEED";
+- // f_min = <300000>;
+- // f_max = <50000000>;
+- // f_max_w = <50000000>;
+- // max_req_size = <0x80000>; /*512KB*/
+- // gpio_cd = "CARD_6";
+- // gpio_power = "CARD_8";
+- // power_level = <0>;
+- // irq_in = <5>;
+- // irq_out = <6>;
+- // };
+- // };
+-
+-
+-/// ***************************************************************************************
+-/// - I2C
+-//$$ MODULE="I2C"
+-//$$ DEVICE="I2C_AO"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 2 ="reg"
+-//$$ L3 PROP_STR = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "I2C_AO_pin_match" = "pinctrl-0"
+- i2c@c8100500{ /*I2C-AO*/
+- compatible = "amlogic,aml_i2c";
+- dev_name = "i2c-AO";
+- status = "ok";
+- reg = <0xc8100500 0x1d>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- device_id = <0>;
+- pinctrl-names="default";
+- pinctrl-0=<&ao_i2c_master>;
+- use_pio = <0>;
+- master_i2c_speed = <100000>;
+- };
+-
+-//$$ DEVICE = "I2C_A"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 2 ="reg"
+-//$$ L3 PROP_STR = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "I2C_A_pin_match" = "pinctrl-0"
+- i2c@c1108500{ /*I2C-A*/
+- compatible = "amlogic,aml_i2c";
+- dev_name = "i2c-A";
+- status = "ok";
+- reg = <0xc1108500 0x20>;
+- device_id = <1>;
+- pinctrl-names="default";
+- pinctrl-0=<&a_i2c_master>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- use_pio = <0>;
+- master_i2c_speed = <300000>;
+- };
+-
+-//$$ DEVICE="I2C_B"
+-//$$ L2 PROP_STR = "status"
+-//$$ L3 PROP_U32 2="reg"
+-//$$ L3 PROP_STR = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "I2C_B_pin_match" = "pinctrl-0"
+- i2c@c11087c0{ /*I2C-B*/
+- compatible = "amlogic,aml_i2c";
+- dev_name = "i2c-B";
+- status = "ok";
+- reg = <0xc11087c0 0x20>;
+- device_id = <2>;
+- pinctrl-names="default";
+- pinctrl-0=<&b_i2c_master>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- use_pio = <0>;
+- master_i2c_speed = <300000>;
+- };
+-
+-/// ***************************************************************************************
+-/// - Power
+-//$$ MODULE="Power"
+-//$$ DEVICE="dvfs"
+-//$$ L2 PROP_STR = "status"
+- dvfs {
+- compatible = "amlogic, amlogic-dvfs"; /** fixed for driver, don't change */
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "ok";
+-
+-//$$ L2 PROP_U32 = "dvfs_id"
+-//$$ L2 PROP_U32 = "table_count"
+-//$$ L2 PROP_U32 11*3 = "dvfs_table"
+- vcck_dvfs {
+- dvfs_id = <1>; /** must be value of (1 << n) */
+- table_count = <11>; /** must be correct count for dvfs_table */
+- dvfs_table = <
+- /* NOTE: frequent in this table must be ascending order */
+- /* frequent(Khz) min_uV max_uV */
+- 200000 1079000 1079000
+- 600000 1079000 1079000
+- 792000 1079000 1079000
+- 816000 1147000 1147000
+- 840000 1147000 1147000
+- 984000 1147000 1147000
+- 1000000 1147000 1147000
+- 1080000 1249000 1249000
+- 1200000 1266000 1266000
+- 1320000 1334000 1334000
+- 1500000 1334000 1334000
+- >;
+- };
+- };
+-//$$ DEVICE="meson_vcck_dvfs_driver"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_STR = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "meson_vcck_dvfs_pin_0_match" = "pinctrl-0"
+-//$$ L2 PROP_U32 = "use_pwm"
+-//$$ L2 PROP_U32 = "table_count"
+-//$$ L2 PROP_U32 16*2 = "cs_voltage_table"
+- meson_vcck_dvfs_driver{
+- compatible = "amlogic, meson_vcck_dvfs";
+- dev_name = "meson_vcck_dvfs_driver";
+- status = "ok";
+- pinctrl-names = "default";
+- pinctrl-0 = <&aml_pwm_pins>;
+- use_pwm = <1>;
+- pmw_controller = "PWM_C";
+- table_count = <16>;
+- cs_voltage_table = <
+- /*
+- * Note: This table is hardware depended, If your hardware use PWM method,
+- * then first line in this table is PWM register value, second line is
+- * voltage of VCCK according this PWM register value. If your platform use
+- * constant-current source to adjust vcck voltage, then the first line should
+- * set to 0, means not valid, member 'use_pwm' in this node should set to 0.
+- *
+- * ---- This table must be in ascending order by voltage ----
+- *
+- * PWM value VCCK voltage
+- */
+- 0x130009 1079000
+- 0x12000a 1096000
+- 0x11000b 1113000
+- 0x10000c 1130000
+- 0x0f000d 1147000
+- 0x0e000e 1164000
+- 0x0d000f 1181000
+- 0x0c0010 1198000
+- 0x0b0011 1215000
+- 0x0a0012 1232000
+- 0x090013 1249000
+- 0x080014 1266000
+- 0x070015 1283000
+- 0x060016 1300000
+- 0x050017 1317000
+- 0x040018 1334000
+- >;
+- };
+-
+-
+-
+-/// ***************************************************************************************
+-/// - USB Controller
+-//$$ MODULE="USB Controller"
+- usb_con {
+- lm-compatible = "logicmodule-bus";
+-
+-//$$ DEVICE="usb_b"
+-//$$ L2 PROP_U32 = "lm-periph-id"
+-//$$ L2 PROP_STR = "clock-src"
+-//$$ L2 PROP_U32 = "port-id"
+-//$$ L2 PROP_U32 = "port-type"
+-//$$ L2 PROP_U32 = "port-speed"
+-//$$ L2 PROP_U32 = "port-config"
+-//$$ L2 PROP_U32 = "port-dma"
+-//$$ L2 PROP_U32 = "port-id-mode"
+-//$$ L2 PROP_STR = "status"
+- usb_b{
+- lm-compatible = "amlogic,usb";
+- lm-periph-id = <1>; /** lm name */
+- clock-src = "usb1"; /** clock src */
+- port-id = <1>; /** ref to mach/usb.h */
+- port-type = <1>; /** 0: otg, 1: host, 2: slave */
+- port-speed = <0>; /** 0: default, 1: high, 2: full */
+- port-config = <0>; /** 0: default */
+- port-dma = <0>; /** 0: default, 1: single, 2: incr, 3: incr4, 4: incr8, 5: incr16, 6: disable*/
+- port-id-mode = <1>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
+- status = "okay";
+- };
+-
+-//$$ DEVICE="usb_a"
+-//$$ L2 PROP_U32 = "lm-periph-id"
+-//$$ L2 PROP_STR = "clock-src"
+-//$$ L2 PROP_U32 = "port-id"
+-//$$ L2 PROP_U32 = "port-type"
+-//$$ L2 PROP_U32 = "port-speed"
+-//$$ L2 PROP_U32 = "port-config"
+-//$$ L2 PROP_U32 = "port-dma"
+-//$$ L2 PROP_U32 = "port-id-mode"
+-//$$ L2 PROP_STR = "gpio-vbus-power"
+-//$$ L2 PROP_U32 = "gpio-work-mask"
+-// L2 PROP_U32 = "charger_detect"
+-//$$ L2 PROP_STR = "status"
+- usb_a{
+- lm-compatible = "amlogic,usb";
+- lm-periph-id = <0>; /** lm name */
+- clock-src = "usb0"; /** clock src */
+- port-id = <0>; /** ref to mach/usb.h */
+- port-type = <0>; /** 0: otg, 1: host, 2: slave */
+- port-speed = <0>; /** 0: default, high, 1: full */
+- port-config = <0>; /** 0: default */
+- port-dma = <0>; /** 0: default, 1: single, 2: incr, 3: incr4, 4: incr8, 5: incr16, 6: disable*/
+- port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
+- gpio-vbus-power = "GPIOD_9";
+- gpio-work-mask = <1>; /**0: work on pulldown,1:work on pullup*/
+- status = "okay";
+- };
+- };
+-
+-
+-
+-/// ***************************************************************************************
+-/// - Audio
+-//$$ MODULE="Audio"
+-//$$ DEVICE="audio"
+-//$$ L2 PROP_STR = "status"
+- audio{
+- compatible = "amlogic,aml-audio";
+- dev_name = "aml-audio.0";
+- status = "okay";
+- };
+-
+-//$$ DEVICE="audio_dai"
+-//$$ L2 PROP_STR = "status"
+- audio_dai{
+- compatible = "amlogic,aml-dai";
+- dev_name = "aml-dai.0";
+- status = "okay";
+- };
+-
+-//$$ DEVICE="dummy_codec_audio"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_STR = "pinctrl-names"
+-//$$ L3 PROP_CHOICE "dummy_codec_audio_0_pin_match" = "pinctrl-0"
+- dummy_codec_audio{
+- status = "okay";
+- compatible = "amlogic,aml_dummy_codec_audio";
+- dev_name = "aml_dummy_codec_audio.0";
+- pinctrl-names = "dummy_codec_audio";
+- pinctrl-0 = <&aml_dummy_codec_pins>;
+- };
+-
+-//$$ DEVICE="dummy_codec"
+-//$$ L2 PROP_STR = "status"
+- dummy_codec{
+- status = "okay";
+- compatible = "amlogic,aml_dummy_codec";
+- dev_name = "dummy_codec.0";
+- };
+-
+-
+-
+-/// ***************************************************************************************
+-/// - Input
+-//$$ MODULE="Input"
+-//$$ DEVICE="saradc"
+-//$$ L2 PROP_STR = "status"
+- saradc{
+- compatible = "amlogic,saradc";
+- status = "okay";
+- };
+-//$$ DEVICE="adc_keypad"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_STR 5 = "key_name"
+-//$$ L2 PROP_U32 = "key_num"
+-//$$ L2 PROP_U32 = "name_len"
+-//$$ L2 PROP_U32 5 = "key_code"
+-//$$ L2 PROP_U32 5 = "key_chan"
+-//$$ L2 PROP_U32 5 = "key_val"
+-//$$ L2 PROP_U32 5 = "key_tolerance"
+- adc_keypad{
+- compatible = "amlogic,adc_keypad";
+- status = "okay";
+- key_num = <6>;
+- name_len = <20>;
+- key_name = "menu","vol-","vol+","back","home","ok";
+- key_code = <139 114 115 158 102 232>;
+- key_chan = <4 4 4 4 4 4>;
+- key_val = <9 150 275 392 513 639>;
+- key_tolerance = <40 40 40 40 40 40>;
+- };
+-//$$ DEVICE="key_input"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_U32 = "scan_period"
+-//$$ L2 PROP_U32 = "fuzz_time"
+-//$$ L2 PROP_U32 = "key_code_list"
+-//$$ L2 PROP_U32 = "key_num"
+-//$$ L2 PROP_U32 = "config"
+- key_input{
+- compatible = "amlogic,key_input";
+- status = "okay";
+- scan_period = <20>;
+- fuzz_time = <60>;
+- key_code_list = <116>;
+- key_num = <1>;
+- config = <0>;
+- };
+-//$$ DEVICE="aml_remote"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_U32 = "ao_baseaddr"
+-//$$ L2 PROP_STR = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "Remote_pin_match" = "pinctrl-0"
+- meson-remote{
+- compatible = "amlogic,aml_remote";
+- dev_name = "meson-remote";
+- status = "okay";
+- ao_baseaddr = <0xf3100480>;
+- pinctrl-names="default";
+- pinctrl-0=<&remote_pins>;
+- };
+-
+-
+-/// ***************************************************************************************
+-/// - Spi
+-//$$ MODULE="Spi"
+-//$$ DEVICE="spi"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_U32 2 = "reg"
+-//$$ L2 PROP_STR = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "Spi_pin_0_match" = "pinctrl-0"
+-//$$ L2 PROP_U32 = "nr-parts"
+-//$$ L2 PROP_CHOICE "Spi_nr-part-0_match" = "nr-part-0"
+-//$$ L2 PROP_CHOICE "Spi_nr-part-1_match" = "nr-part-1"
+- spi@cc000000{
+- compatible = "amlogic,apollo_spi_nor";
+- status = "ok";
+- reg = <0xcc000000 0x04000000>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&aml_spi_nor_pins>;
+-
+- nr-parts = <2>;
+- nr-part-0 = <&bootloader>;
+- nr-part-1 = <&ubootenv>;
+-
+-//$$ MATCH "Spi_nr-part-0_match" = <&bootloader>
+-//$$ L2 PROP_STR = "name"
+-//$$ L2 PROP_U32 = "offset"
+-//$$ L2 PROP_U32 = "size"
+- bootloader:bootloader{
+- name = "bootloader";
+- offset = <0>;
+- size = <0x60000>;
+- };
+-
+-//$$ MATCH "Spi_nr-part-1_match" = <&ubootenv>
+-//$$ L2 PROP_STR = "name"
+-//$$ L2 PROP_U32 = "offset"
+-//$$ L2 PROP_U32 = "size"
+- ubootenv:ubootenv{
+- name = "ubootenv";
+- offset = <0x80000>;
+- size = <0x8000>;
+- };
+- };
+-
+-/// ***************************************************************************************
+-/// - Nand
++ reserve-iomap = "true";
++ };
++
++/// **************************************************************************************
++/// - DISP&MM-FB
++//$$ MODULE = "DISP&MM-FB"
++//$$ DEVICE = "mesonfb"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 2 ="reserve-memory"
++//$$ L2 PROP_U32 = "vmode"
++//$$ L2 PROP_U32 5 = "display_size_default"
++ mesonfb{
++ compatible = "amlogic,mesonfb";
++ dev_name = "mesonfb";
++ status = "okay";
++ reserve-memory = <0x01000000 0x00100000>;
++ reserve-iomap = "true";
++ vmode = <0>; /*0:VMODE_720P 1:VMODE_LCD 2:VMODE_LVDS_1080P 3:VMODE_1080P*/
++ scale_mode = <0>; /*0:default 1:new*/
++ display_size_default = <1280 720 1280 2160 32>; // osd0:8M, osd1:1m 1280*720*4*3 = 11,059,200
++ };
++//$$ DEVICE="deinterlace"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_U32 = "reserve-memory"
++ deinterlace{
++ compatible = "amlogic,deinterlace";
++ dev_name = "deinterlace";
++ status = "okay";
++ reserve-memory = <0x01c00000>; // 27M
++ reserve-iomap = "true";
++ };
++
++/// ***************************************************************************************
++/// - DISP&MM-A/V stream
++//$$ MODULE = "DISP&MM-A/V stream"
++//$$ DEVICE="mesonstream"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 4 ="reserve-memory"
++ mesonstream{
++ compatible = "amlogic,mesonstream";
++ dev_name = "mesonstream.0";
++ status = "okay";
++ reserve-memory = <0x00a00000>; //10M
++ reserve-iomap = "true";
++ };
++
++
++/// ***************************************************************************************
++/// - DISP&MM-A/V stream
++//$$ MODULE = "DISP&MM-A/V video dec"
++//$$ DEVICE="vdec"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 4 ="reg"
++ vdec{
++ compatible = "amlogic,vdec";
++ dev_name = "vdec.0";
++ status = "okay";
++ reserve-memory = <0x02000000>; //32M
++ reserve-iomap = "true";
++ };
++
++/// ***************************************************************************************
++/// - DISP&MM-PostProcess
++//$$ MODULE="DISP&MM-PostProcess"
++//$$ DEVICE="ppmgr"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 ="reserve-memory"
++ ppmgr{
++ compatible = "amlogic,ppmgr";
++ dev_name = "ppmgr";
++ status = "okay";
++ reserve-memory = <0x01300000>; // 1280*732*21 = 19,676,160
++ reserve-iomap = "true";
++ };
++
++
++/// ***************************************************************************************
++/// - DISP&MM-Vout
++//$$ MODULE = "DISP&MM-Vout"
++//$$ DEVICE = "mesonvout"
++//$$ L2 PROP_STR = "status"
++ mesonvout{
++ compatible = "amlogic,mesonvout";
++ dev_name = "mesonvout";
++ status = "okay";
++ };
++
++/// ***************************************************************************************
++/// - EARLY_INIT
++//$$ MODULE="early_init"
++//$$ DEVICE = "early_init"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_STR ="gpio-1"
++//$$ L2 PROP_STR = "gpio-2"
++ early_init{
++ compatible = "amlogic,early_init";
++ dev_name = "early_init";
++ status = "ok";
++ gpio-1 = "GPIOAO_3";
++ gpio-2 = "GPIOAO_2";
++ };
++
++/// ***************************************************************************************
++/// - RTC
++//$$ MODULE="RTC"
++//$$ DEVICE="Rtc"
++//$$ L2 PROP_STR = "status"
++ rtc{
++ compatible = "amlogic,aml_rtc";
++ status = "okay";
++ };
++
++/// ***************************************************************************************
++/// - UART
++//$$ MODULE="UART"
++//$$ DEVICE="uart_ao"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_STR = "pinctrl-names"
++//$$ L3 PROP_CHOICE "uart_ao_pin_match" = "pinctrl-0"
++ uart_ao{
++ compatible = "amlogic,aml_uart";
++ port_name = "uart_ao";
++ status = "okay";
++ dev_name = "uart_ao";
++ pinctrl-names = "default";
++ pinctrl-0 = <&ao_uart_pins>;
++ };
++
++//$$ DEVICE="uart_0"
++//$$ L2 PROP_STR = "status"
++ uart_0{
++ compatible = "amlogic,aml_uart";
++ port_name = "uart_a";
++ status = "okay";
++ dev_name = "uart_0";
++ };
++
++//$$ DEVICE="uart_1"
++//$$ L2 PROP_STR = "status"
++ uart_1{
++ compatible = "amlogic,aml_uart";
++ port_name = "uart_b";
++ status = "disabled";
++ dev_name = "uart_1";
++ };
++
++//$$ DEVICE="uart_2"
++//$$ L2 PROP_STR = "status"
++ uart_2{
++ compatible = "amlogic,aml_uart";
++ port_name = "uart_c";
++ status = "disabled";
++ dev_name = "uart_2";
++ };
++
++//$$ DEVICE="uart_3"
++//$$ L2 PROP_STR = "status"
++ uart_3{
++ compatible = "amlogic,aml_uart";
++ port_name = "uart_d";
++ status = "ok";
++ dev_name = "uart_3";
++ };
++
++/// ***************************************************************************************
++/// - Bluetooth
++//$$ MODULE="Bluetooth"
++
++ bt-dev{
++ compatible = "amlogic,bt-dev";
++ dev_name = "bt-dev";
++ gpio_reset = "GPIOE_11";
++ gpio_en = "GPIOE_11";
++ status = "ok";
++ };
++
++/// ***************************************************************************************
++/// - WiFi
++//$$ MODULE="WiFi"
++//$$ DEVICE="aml_broadcm_wifi"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_STR = "interrupt_pin"
++//$$ L2 PROP_U32 = "irq_num"
++//$$ L2 PROP_STR = "irq_trigger_type"
++//$$ L2 PROP_STR = "power_on_pin"
++//$$ L2 PROP_STR = "clock_32k_pin"
++ wifi{
++ compatible = "amlogic,aml_broadcm_wifi";
++ dev_name = "aml_broadcm_wifi";
++ status = "okay";
++ interrupt_pin = "GPIOX_11";
++ irq_num = <4>;
++ irq_trigger_type = "GPIO_IRQ_HIGH";
++ power_on_pin = "GPIOC_7";
++ clock_32k_pin = "GPIOX_12";
++ };
++
++//$$ DEVICE="wifi_power"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_STR = "power_gpio"
++// wifi_power{
++// compatible = "amlogic,wifi_power";
++// dev_name = "wifi_power";
++// status = "okay";
++// power_gpio = "GPIOC_7";
++// };
++
++/// ***************************************************************************************
++/// - MMC
++//$$ MODULE="MMC"
++//$$ DEVICE="aml_sdio"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 2 ="reg"
++//$$ L2 PROP_STR 7 = "pinctrl-names"
++//$$ L2 PROP_CHOICE "sdio_pin_0_match" = "pinctrl-0"
++//$$ L2 PROP_CHOICE "sdio_pin_1_match" = "pinctrl-1"
++//$$ L2 PROP_CHOICE "sdio_pin_2_match" = "pinctrl-2"
++//$$ L2 PROP_CHOICE "sdio_pin_3_match" = "pinctrl-3"
++//$$ L2 PROP_CHOICE "sdio_pin_4_match" = "pinctrl-4"
++//$$ L2 PROP_CHOICE "sdio_pin_5_match" = "pinctrl-5"
++// L2 PROP_CHOICE "sdio_pin_6_match" = "pinctrl-6"
++ sdio{
++ compatible = "amlogic,aml_sdio";
++ dev_name = "aml_sdio.0";
++ status = "okay";
++ reg = <0xc1108c20 0x20>;
++ pinctrl-names = "sd_clk_cmd_pins", "sd_all_pins", "emmc_clk_cmd_pins", "emmc_all_pins", "sdio_clk_cmd_pins", "sdio_all_pins"; /*sd:sdio_b, emmc:sdio_c, sdio:sdio_a*/
++ // pinctrl-0 = <&sd_pins>;
++ // pinctrl-1 = <&emmc_pins>;
++ // pinctrl-2 = <&sdio_pins>;
++ pinctrl-0 = <&sd_clk_cmd_pins>;
++ pinctrl-1 = <&sd_all_pins>;
++ pinctrl-2 = <&emmc_clk_cmd_pins>;
++ pinctrl-3 = <&emmc_all_pins>;
++ pinctrl-4 = <&sdio_clk_cmd_pins>;
++ pinctrl-5 = <&sdio_all_pins>;
++
++//$$ DEVICE="sd"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 = "port"
++//$$ L2 PROP_STR = "pinname"
++//$$ L3 PROP_U32 = "ocr_avail"
++//$$ L2 PROP_STR 3 = "caps"
++//$$ L3 PROP_U32 = "f_min"
++//$$ L3 PROP_U32 = "f_max"
++//$$ L3 PROP_U32 = "f_max_w"
++//$$ L3 PROP_U32 = "max_req_size"
++//$$ L2 PROP_STR = "gpio_dat3"
++//$$ L2 PROP_STR = "jtag_pin"
++//$$ L2 PROP_STR = "gpio_cd"
++//$$ L2 PROP_STR = "gpio_ro"
++//$$ L2 PROP_U32 = "irq_in"
++//$$ L2 PROP_U32 = "irq_out"
++//$$ L2 PROP_U32 = "card_type"
++ sd{
++ status = "okay";
++ port = <1>; /**0:sdio_a, 1:sdio_b, 2:sdio_c, 3:sdhc_a, 4:sdhc_b, 5:sdhc_c */
++ pinname = "sd";
++ ocr_avail = <0x200000>; /**VDD voltage 3.3 ~ 3.4 */
++ caps = "MMC_CAP_4_BIT_DATA","MMC_CAP_MMC_HIGHSPEED","MMC_CAP_SD_HIGHSPEED";
++ f_min = <300000>;
++ f_max = <50000000>;
++ f_max_w = <50000000>;
++ max_req_size = <0x20000>; /**128KB*/
++ gpio_dat3 = "CARD_3";
++ gpio_cd = "CARD_6";
++ gpio_power = "CARD_8";
++ power_level = <0>;
++ irq_in = <5>;
++ #irq_in_edge = "GPIO_IRQ_FALLING";
++ irq_out = <6>;
++ #irq_out_edge = "GPIO_IRQ_RISING";
++ card_type = <5>; /* 0:unknown, 1:mmc card(include eMMC), 2:sd card(include tSD), 3:sdio device(ie:sdio-wifi), 4:SD combo (IO+mem) card, 5:NON sdio device(means sd/mmc card), other:reserved */
++ };
++
++//$$ L3 PROP_U32 = "port"
++//$$ L2 PROP_STR = "pinname"
++//$$ L3 PROP_U32 = "ocr_avail"
++//$$ L2 PROP_STR 4 = "caps"
++//$$ L3 PROP_U32 = "f_min"
++//$$ L3 PROP_U32 = "f_max"
++//$$ L3 PROP_U32 = "max_req_size"
++//$$ L2 PROP_U32 = "card_type"
++ sdio{
++ status = "okay";
++ port = <0>; /*0:sdio_a, 1:sdio_b, 2:sdio_c, 3:sdhc_a, 4:sdhc_b, 5:sdhc_c */
++ pinname = "sdio";
++ ocr_avail = <0x200000>; /*VDD voltage 3.3 ~ 3.4 */
++ caps = "MMC_CAP_4_BIT_DATA","MMC_CAP_MMC_HIGHSPEED","MMC_CAP_SD_HIGHSPEED", "MMC_CAP_NONREMOVABLE";
++ f_min = <300000>;
++ f_max = <50000000>;
++ f_max_w = <50000000>;
++ max_req_size = <0x20000>; /*128KB*/
++ card_type = <3>; /* 0:unknown, 1:mmc card(include eMMC), 2:sd card(include tSD), 3:sdio device(ie:sdio-wifi), 4:SD combo (IO+mem) card, 5:NON sdio device(means sd/mmc card), other:reserved */
++ };
++ };
++
++/// ***************************************************************************************
++/// - I2C
++//$$ MODULE="I2C"
++//$$ DEVICE="I2C_AO"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 2 ="reg"
++//$$ L3 PROP_STR = "pinctrl-names"
++//$$ L2 PROP_CHOICE "I2C_AO_pin_match" = "pinctrl-0"
++ i2c@c8100500{ /*I2C-AO*/
++ compatible = "amlogic,aml_i2c";
++ dev_name = "i2c-AO";
++ status = "ok";
++ reg = <0xc8100500 0x1d>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ device_id = <0>;
++ pinctrl-names="default";
++ pinctrl-0=<&ao_i2c_master>;
++ use_pio = <0>;
++ master_i2c_speed = <100000>;
++ };
++
++//$$ DEVICE = "I2C_A"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 2 ="reg"
++//$$ L3 PROP_STR = "pinctrl-names"
++//$$ L2 PROP_CHOICE "I2C_A_pin_match" = "pinctrl-0"
++ i2c@c1108500{ /*I2C-A*/
++ compatible = "amlogic,aml_i2c";
++ dev_name = "i2c-A";
++ status = "ok";
++ reg = <0xc1108500 0x20>;
++ device_id = <1>;
++ pinctrl-names="default";
++ pinctrl-0=<&a_i2c_master>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ use_pio = <0>;
++ master_i2c_speed = <300000>;
++ };
++
++//$$ DEVICE="I2C_B"
++//$$ L2 PROP_STR = "status"
++//$$ L3 PROP_U32 2="reg"
++//$$ L3 PROP_STR = "pinctrl-names"
++//$$ L2 PROP_CHOICE "I2C_B_pin_match" = "pinctrl-0"
++ i2c@c11087c0{ /*I2C-B*/
++ compatible = "amlogic,aml_i2c";
++ dev_name = "i2c-B";
++ status = "ok";
++ reg = <0xc11087c0 0x20>;
++ device_id = <2>;
++ pinctrl-names="default";
++ pinctrl-0=<&b_i2c_master>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ use_pio = <0>;
++ master_i2c_speed = <300000>;
++ };
++
++/// ***************************************************************************************
++/// - Power
++//$$ MODULE="Power"
++//$$ DEVICE="dvfs"
++//$$ L2 PROP_STR = "status"
++ dvfs {
++ compatible = "amlogic, amlogic-dvfs"; /** fixed for driver, don't change */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "ok";
++
++//$$ L2 PROP_U32 = "dvfs_id"
++//$$ L2 PROP_U32 = "table_count"
++//$$ L2 PROP_U32 11*3 = "dvfs_table"
++ vcck_dvfs {
++ dvfs_id = <1>; /** must be value of (1 << n) */
++ table_count = <11>; /** must be correct count for dvfs_table */
++ dvfs_table = <
++ /* NOTE: frequent in this table must be ascending order */
++ /* frequent(Khz) min_uV max_uV */
++ 200000 1010000 1010000
++ 600000 1010000 1010000
++ 792000 1010000 1010000
++ 816000 1110000 1110000
++ 840000 1110000 1110000
++ 984000 1110000 1110000
++ 1000000 1110000 1110000
++ 1080000 1220000 1220000
++ 1200000 1240000 1240000
++ 1320000 1320000 1320000
++ 1500000 1320000 1320000
++ >;
++ };
++ };
++//$$ DEVICE="meson_vcck_dvfs_driver"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_STR = "pinctrl-names"
++//$$ L2 PROP_CHOICE "meson_vcck_dvfs_pin_0_match" = "pinctrl-0"
++//$$ L2 PROP_U32 = "use_pwm"
++//$$ L2 PROP_U32 = "table_count"
++//$$ L2 PROP_U32 16*2 = "cs_voltage_table"
++ meson_vcck_dvfs_driver{
++ compatible = "amlogic, meson_vcck_dvfs";
++ dev_name = "meson_vcck_dvfs_driver";
++ status = "ok";
++ pinctrl-names = "default";
++ pinctrl-0 = <&aml_pwm_pins>;
++ use_pwm = <1>;
++ pmw_controller = "PWM_C";
++ table_count = <16>;
++ cs_voltage_table = <
++ /*
++ * Note: This table is hardware depended, If your hardware use PWM method,
++ * then first line in this table is PWM register value, second line is
++ * voltage of VCCK according this PWM register value. If your platform use
++ * constant-current source to adjust vcck voltage, then the first line should
++ * set to 0, means not valid, member 'use_pwm' in this node should set to 0.
++ *
++ * ---- This table must be in ascending order by voltage ----
++ *
++ * PWM value VCCK voltage
++ */
++ 0x130009 1010000
++ 0x12000a 1050000
++ 0x11000b 1070000
++ 0x10000c 1090000
++ 0x0f000d 1110000
++ 0x0e000e 1130000
++ 0x0d000f 1150000
++ 0x0c0010 1170000
++ 0x0b0011 1190000
++ 0x0a0012 1210000
++ 0x090013 1220000
++ 0x080014 1240000
++ 0x070015 1270000
++ 0x060016 1280000
++ 0x050017 1300000
++ 0x040018 1320000
++ >;
++ };
++
++
++
++/// ***************************************************************************************
++/// - USB Controller
++//$$ MODULE="USB Controller"
++ usb_con {
++ lm-compatible = "logicmodule-bus";
++
++//$$ DEVICE="usb_b"
++//$$ L2 PROP_U32 = "lm-periph-id"
++//$$ L2 PROP_STR = "clock-src"
++//$$ L2 PROP_U32 = "port-id"
++//$$ L2 PROP_U32 = "port-type"
++//$$ L2 PROP_U32 = "port-speed"
++//$$ L2 PROP_U32 = "port-config"
++//$$ L2 PROP_U32 = "port-dma"
++//$$ L2 PROP_U32 = "port-id-mode"
++//$$ L2 PROP_STR = "status"
++ usb_b{
++ lm-compatible = "amlogic,usb";
++ lm-periph-id = <1>; /** lm name */
++ clock-src = "usb1"; /** clock src */
++ port-id = <1>; /** ref to mach/usb.h */
++ port-type = <1>; /** 0: otg, 1: host, 2: slave */
++ port-speed = <0>; /** 0: default, 1: high, 2: full */
++ port-config = <0>; /** 0: default */
++ port-dma = <0>; /** 0: default, 1: single, 2: incr, 3: incr4, 4: incr8, 5: incr16, 6: disable*/
++ port-id-mode = <1>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
++ status = "okay";
++ };
++
++//$$ DEVICE="usb_a"
++//$$ L2 PROP_U32 = "lm-periph-id"
++//$$ L2 PROP_STR = "clock-src"
++//$$ L2 PROP_U32 = "port-id"
++//$$ L2 PROP_U32 = "port-type"
++//$$ L2 PROP_U32 = "port-speed"
++//$$ L2 PROP_U32 = "port-config"
++//$$ L2 PROP_U32 = "port-dma"
++//$$ L2 PROP_U32 = "port-id-mode"
++//$$ L2 PROP_STR = "gpio-vbus-power"
++//$$ L2 PROP_U32 = "gpio-work-mask"
++// L2 PROP_U32 = "charger_detect"
++//$$ L2 PROP_STR = "status"
++ usb_a{
++ lm-compatible = "amlogic,usb";
++ lm-periph-id = <0>; /** lm name */
++ clock-src = "usb0"; /** clock src */
++ port-id = <0>; /** ref to mach/usb.h */
++ port-type = <0>; /** 0: otg, 1: host, 2: slave */
++ port-speed = <0>; /** 0: default, high, 1: full */
++ port-config = <0>; /** 0: default */
++ port-dma = <0>; /** 0: default, 1: single, 2: incr, 3: incr4, 4: incr8, 5: incr16, 6: disable*/
++ port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
++ gpio-vbus-power = "GPIOD_9";
++ gpio-work-mask = <1>; /**0: work on pulldown,1:work on pullup*/
++ status = "okay";
++ };
++ };
++
++
++
++/// ***************************************************************************************
++/// - Audio
++//$$ MODULE="Audio"
++//$$ DEVICE="audio"
++//$$ L2 PROP_STR = "status"
++ audio{
++ compatible = "amlogic,aml-audio";
++ dev_name = "aml-audio.0";
++ status = "okay";
++ };
++
++//$$ DEVICE="audio_dai"
++//$$ L2 PROP_STR = "status"
++ audio_dai{
++ compatible = "amlogic,aml-dai";
++ dev_name = "aml-dai.0";
++ status = "okay";
++ };
++
++//$$ DEVICE="dummy_codec_audio"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_STR = "pinctrl-names"
++//$$ L3 PROP_CHOICE "dummy_codec_audio_0_pin_match" = "pinctrl-0"
++ dummy_codec_audio{
++ status = "okay";
++ compatible = "amlogic,aml_dummy_codec_audio";
++ dev_name = "aml_dummy_codec_audio.0";
++ pinctrl-names = "dummy_codec_audio";
++ pinctrl-0 = <&aml_dummy_codec_pins>;
++ };
++
++//$$ DEVICE="dummy_codec"
++//$$ L2 PROP_STR = "status"
++ dummy_codec{
++ status = "okay";
++ compatible = "amlogic,aml_dummy_codec";
++ dev_name = "dummy_codec.0";
++ };
++
++
++
++/// ***************************************************************************************
++/// - Input
++//$$ MODULE="Input"
++//$$ DEVICE="saradc"
++//$$ L2 PROP_STR = "status"
++ saradc{
++ compatible = "amlogic,saradc";
++ status = "okay";
++ };
++//$$ DEVICE="adc_keypad"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_STR 5 = "key_name"
++//$$ L2 PROP_U32 = "key_num"
++//$$ L2 PROP_U32 = "name_len"
++//$$ L2 PROP_U32 5 = "key_code"
++//$$ L2 PROP_U32 5 = "key_chan"
++//$$ L2 PROP_U32 5 = "key_val"
++//$$ L2 PROP_U32 5 = "key_tolerance"
++ adc_keypad{
++ compatible = "amlogic,adc_keypad";
++ status = "okay";
++ key_num = <6>;
++ name_len = <20>;
++ key_name = "menu","vol-","vol+","back","home","ok";
++ key_code = <139 114 115 158 102 232>;
++ key_chan = <4 4 4 4 4 4>;
++ key_val = <9 150 275 392 513 639>;
++ key_tolerance = <40 40 40 40 40 40>;
++ };
++//$$ DEVICE="key_input"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_U32 = "scan_period"
++//$$ L2 PROP_U32 = "fuzz_time"
++//$$ L2 PROP_U32 = "key_code_list"
++//$$ L2 PROP_U32 = "key_num"
++//$$ L2 PROP_U32 = "config"
++ key_input{
++ compatible = "amlogic,key_input";
++ status = "okay";
++ scan_period = <20>;
++ fuzz_time = <60>;
++ key_code_list = <116>;
++ key_num = <1>;
++ config = <0>;
++ };
++//$$ DEVICE="aml_remote"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_U32 = "ao_baseaddr"
++//$$ L2 PROP_STR = "pinctrl-names"
++//$$ L2 PROP_CHOICE "Remote_pin_match" = "pinctrl-0"
++ meson-remote{
++ compatible = "amlogic,aml_remote";
++ dev_name = "meson-remote";
++ status = "okay";
++ ao_baseaddr = <0xf3100480>;
++ pinctrl-names="default";
++ pinctrl-0=<&remote_pins>;
++ };
++
++
++/// ***************************************************************************************
++/// - Spi
++//$$ MODULE="Spi"
++//$$ DEVICE="spi"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_U32 2 = "reg"
++//$$ L2 PROP_STR = "pinctrl-names"
++//$$ L2 PROP_CHOICE "Spi_pin_0_match" = "pinctrl-0"
++//$$ L2 PROP_U32 = "nr-parts"
++//$$ L2 PROP_CHOICE "Spi_nr-part-0_match" = "nr-part-0"
++//$$ L2 PROP_CHOICE "Spi_nr-part-1_match" = "nr-part-1"
++ spi@cc000000{
++ compatible = "amlogic,apollo_spi_nor";
++ status = "ok";
++ reg = <0xcc000000 0x04000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&aml_spi_nor_pins>;
++
++ nr-parts = <2>;
++ nr-part-0 = <&bootloader>;
++ nr-part-1 = <&ubootenv>;
++
++//$$ MATCH "Spi_nr-part-0_match" = <&bootloader>
++//$$ L2 PROP_STR = "name"
++//$$ L2 PROP_U32 = "offset"
++//$$ L2 PROP_U32 = "size"
++ bootloader:bootloader{
++ name = "bootloader";
++ offset = <0>;
++ size = <0x100000>;
++ };
++
++//$$ MATCH "Spi_nr-part-1_match" = <&ubootenv>
++//$$ L2 PROP_STR = "name"
++//$$ L2 PROP_U32 = "offset"
++//$$ L2 PROP_U32 = "size"
++ ubootenv:ubootenv{
++ name = "ubootenv";
++ offset = <0x100000>;
++ size = <0x8000>;
++ };
++ };
++
++/// ***************************************************************************************
++/// - Nand
++//$$ MODULE="Nand"
+ //$$ DEVICE="aml_nand"
+ //$$ L2 PROP_STR = "status"
+ //$$ L3 PROP_U32 2 ="reg"
+@@ -765,7 +755,7 @@
+ //$$ L3 PROP_STR 2 ="plat-names"
+ //$$ L2 PROP_U32 = "plat-num"
+ //$$ L2 PROP_CHOICE "plat-part-0_match" = "plat-part-0"
+-//$$ L2 PROP_CHOICE "plat-part-1_match" = "plat-part-1"
++// L2 PROP_CHOICE "plat-part-1_match" = "plat-part-1"
+ nand{
+ compatible = "amlogic,aml_nand";
+ dev_name = "nand";
+@@ -779,34 +769,11 @@
+ &nand_ce0 &nand_ce1
+ &nand_ce2 &nand_ce3>;
+ device_id = <0>;
+- plat-names = "bootloader","nandnormal";
+- plat-num = <2>;
+- plat-part-0 = <&bootload>;
+- plat-part-1 = <&normal>;
+-
+-//$$ MATCH "plat-part-0_match" = <&bootload>
+-//$$ L2 PROP_STR = "enable_pad"
+-//$$ L2 PROP_STR = "busy_pad"
+-//$$ L2 PROP_STR = "timming_mode"
+-//$$ L2 PROP_STR = "bch_mode"
+-//$$ L2 PROP_U32 = "t_rea"
+-//$$ L2 PROP_U32 = "t_rhoh"
+-//$$ L2 PROP_U32 = "chip_num"
+-//$$ L2 PROP_U32 = "part_num"
+-//$$ L2 PROP_U32 = "rb_detect"
+- bootload: bootload{
+- enable_pad ="ce0";
+- busy_pad = "rb0";
+- timming_mode = "mode5";
+- bch_mode = "bch60_1k";
+- t_rea = <20>;
+- t_rhoh = <15>;
+- chip_num = <1>;
+- part_num = <0>;
+- rb_detect = <1>;
+- };
++ plat-names = "nandnormal";
++ plat-num = <1>;
++ plat-part-0 = <&normal>;
+
+-//$$ MATCH "plat-part-1_match" = <&normal>
++//$$ MATCH "plat-part-0_match" = <&normal>
+ //$$ L2 PROP_STR 2 = "enable_pad"
+ //$$ L2 PROP_STR 2 = "busy_pad"
+ //$$ L2 PROP_STR = "timming_mode"
+@@ -826,7 +793,7 @@
+ t_rea = <20>;
+ t_rhoh = <15>;
+ chip_num = <2>;
+- part_num = <7>;
++ part_num = <9>;
+ partition = <&nand_partitions>;
+ rb_detect = <1>;
+ };
+@@ -856,547 +823,578 @@
+ offset=<0x0 0x4a800000>;
+ size=<0x0 0x20000000>;
+ };
+- backup{
+- offset=<0x0 0x6a800000>;
+- size=<0x0 0x10000000>;
+- };
++ backup{
++ offset=<0x0 0x6a800000>;
++ size=<0x0 0x10000000>;
++ };
+ userdata{
+ offset=<0xffffffff 0xffffffff>;
+ size=<0x0 0x0>;
+ };
+ };
+ };
+-
+-/// ***************************************************************************************
+-/// - Efuse
+-//$$ MODULE="Efuse"
+-//$$ DEVICE="efuse"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_U32 2 = "plat-pos"
+-//$$ L2 PROP_U32 = "plat-count"
+-//$$ L2 PROP_U32 = "usid-min"
+-//$$ L2 PROP_U32 = "usid-max"
+- efuse{
+- compatible = "amlogic,efuse";
+- dev_name = "efuse";
+- status = "okay";
+- plat-pos = <0 454>;
+- plat-count = <58>;
+- usid-min = <8>; /*reserved*/
+- usid-max = <31>; /*reserved*/
+- };
+-
+-/// ***************************************************************************************
+-/// - HDMI
+-//$$ MODULE="HDMI"
+-//$$ DEVICE="amhdmitx"
+-//$$ L2 PROP_STR = "status"
+-//$$ L2 PROP_CHOICE "HDMI_vend-data_match" = "vend-data"
+-//$$ L2 PROP_CHOICE "HDMI_pwr-ctrl_match" = "pwr-ctrl"
+- amhdmitx{
+- compatible = "amlogic,amhdmitx";
+- dev_name = "amhdmitx";
+- status = "ok";
+- vend-data = <&vend_data>;
+- pwr-ctrl = <&pwr_ctrl>;
+- phy-size = <3>;
+- phy-data = <27 0x16 0x30 /* 480i/p 576i/p */
+- 74 0x16 0x40 /* 720p 1080i */
+- 148 0x16 0x40 /* 1080p */
+- >;
+-
+-//$$ MATCH "HDMI_vend-data_match" = <&vend_data>
+-//$$ L2 PROP_STR = "vendor_name"
+-//$$ L2 PROP_U32 = "vendor_id"
+-//$$ L2 PROP_STR = "product_desc"
+-//$$ L2 PROP_STR = "cec_osd_string"
+- vend_data: vend_data{
+- vendor_name = "Amlogic"; /* Max Chars: 8 */
+- vendor_id = <0x000000>; /* Refer to http://standards.ieee.org/develop/regauth/oui/oui.txt */
+- product_desc = "MX MBox G18Ref"; /* Max Chars: 16 */
+- cec_osd_string = "Amlogic MBox"; /* Max Chars: 14 */
+- };
+-
+-//$$ MATCH "HDMI_pwr-ctrl_match" = <&pwr_ctrl>
+-//$$ L2 PROP_STR = "pwr_5v_on"
+-//$$ L2 PROP_STR 3 = "pwr_5v_off"
+-//$$ L2 PROP_STR 3 = "pwr_3v3_on"
+-//$$ L2 PROP_STR = "pwr_3v3_off"
+-//$$ L2 PROP_STR = "pwr_hpll_vdd_on"
+-//$$ L2 PROP_STR = "pwr_hpll_vdd_off"
+- pwr_ctrl: pwr_ctrl{
+- pwr_5v_on = "cpu","GPIOD_5","H";
+- pwr_5v_off = "cpu","GPIOD_5","L";
+- pwr_3v3_on = "";
+- pwr_3v3_off = "";
+- pwr_hpll_vdd_on = "";
+- pwr_hpll_vdd_off = "";
+- };
+- };
+-
+-/// ***************************************************************************************
+-/// - Securitykey
+-//$$ MODULE="Securitykey"
+- securitykey{
+- compatible = "amlogic,aml_keys";
+- };
+-
+-/// ***************************************************************************************
+-/// - PowerManager
+-//$$ MODULE="PowerManager"
+-//$$ DEVICE="amvenc_avc"
+-//$$ L2 PROP_STR = "status"
+- aml_pm{
+- compatible = "amlogic,pm";
+- dev_name = "aml_pm";
+- status = "okay";
+- };
+-
+-/// ***************************************************************************************
+-/// - Cpufreq
+-//$$ MODULE="Cpufreq"
+-//$$ DEVICE="cpufreq-meson"
+-//$$ L2 PROP_STR = "status"
+- cpufreq-meson{
+- compatible = "amlogic,cpufreq-meson";
+- status = "okay";
+- };
+-
+-
+-
+-
+-
+-
+-/// ***************************************************************************************
+-/// - Ethernet
+-//$$ MODULE="Ethernet"
+-//$$ DEVICE="meson-eth"
+-//$$ L2 PROP_STR = "status"
+- meson-eth{
+- compatible = "amlogic,meson-eth";
+- dev_name = "meson-eth";
+- status = "okay";
+- ethbaseaddr = <0xf3610000>;
+- interruptnum = <40>;
+- };
+-
+-
+-
+-
+-
+-
+-/// **************************************************************************************
+-/// - GPIO
+-//$$ MODULE="GPIO"
+-//$$ DEVICE="m6-gpio"
+- gpio:gpio{
+- compatible = "amlogic,m6-gpio";
+- dev_name = "gpio";
+- #gpio-cells=<2>;
+- };
+-
+-/// **************************************************************************************
+-/// - Pinmux
+-//$$ MODULE="Pinmux"
+-//$$ DEVICE="pinmux-m6"
+- pinmux{
+- compatible = "amlogic,pinmux-m6";
+- dev_name = "pinmux";
+- #pinmux-cells=<2>;
+-
+-//$$ MATCH "uart_ao_pin_match" = "&ao_uart_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR 2 = "amlogic,pins"
+- ao_uart_pins:ao_uart{
+- amlogic,setmask=<10 0x1800>;
+- amlogic,pins="GPIOAO_0", "GPIOAO_1";
+- };
+-
+-//$$ MATCH "uart_0_pin_match" = "&a_uart_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR 2 = "amlogic,pins"
+- a_uart_pins:a_uart{
+- amlogic,setmask=<4 0x3c00>;
+- amlogic,pins="GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16";
+- };
+-
+-//$$ MATCH "meson_vcck_dvfs_pin_0_match" = "&aml_pwm_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- aml_pwm_pins:aml_pwm{
+- amlogic,setmask=<2 0x4>;
+- amlogic,clrmask=<1 0x20000000>;
+- amlogic,pins="GPIOD_0";
+- };
+-
+-//$$ MATCH "I2C_AO_pin_match" = "&ao_i2c_master"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 2 = "amlogic,pins"
+- ao_i2c_master:ao_i2c{
+- amlogic,setmask=<10 0x60>;
+- amlogic,clrmask=<10 0x1800006>;
+- amlogic,pins="GPIOAO_4","GPIOAO_5";
+- };
+-
+-//$$ MATCH "I2C_A_pin_match" = "&a_i2c_master"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 2 = "amlogic,pins"
+- a_i2c_master:a_i2c{
+- amlogic,setmask=<5 0xc000000>;
+- amlogic,clrmask=<5 0x3000000>;
+- amlogic,pins="GPIOX_25","GPIOX_26";
+- };
+-
+-//$$ MATCH "I2C_B_pin_match" = "&b_i2c_master"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 2 = "amlogic,pins"
+- b_i2c_master:b_i2c{
+- amlogic,setmask=<5 0xc0000000>;
+- amlogic,clrmask=<5 0x30000000>;
+- amlogic,pins="GPIOX_27","GPIOX_28";
+- };
+-
+-//$$ MATCH "Nand_pin_0_match" = "&nand_input_state"
+-//$$ MATCH "Nand_pin_1_match" = "&nand_input_state"
+-//$$ L2 PROP_STR 17 = "amlogic,pins"
+-//$$ L2 PROP_U32 = "amlogic,enable-output"
+- nand_input_state:nand_input{
+- amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
+- "BOOT_5","BOOT_6","BOOT_7","BOOT_12","BOOT_13",
+- "BOOT_8","BOOT_9","BOOT_10","BOOT_11",
+- "BOOT_14","BOOT_15","BOOT_16";
+- amlogic,enable-output=<1>;
+- };
+-
+-//$$ MATCH "Nand_pin_0_match" = "&conf_nand_state"
+-//$$ MATCH "Nand_pin_1_match" = "&conf_nand_state"
+-//$$ L2 PROP_STR 9 = "amlogic,pins"
+-//$$ L2 PROP_U32 = "amlogic,pullup"
+- conf_nand_state: conf_nand{
+- amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
+- "BOOT_5","BOOT_6","BOOT_7","BOOT_16";
+- amlogic,pullup=<1>;
+- };
+-
+-//$$ MATCH "Nand_pin_0_match" = "&nand_base"
+-//$$ MATCH "Nand_pin_1_match" = "&nand_base"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 4*2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 13 = "amlogic,pins"
+- nand_base: nand{
+- amlogic,setmask=<2 0xc3c0000>;
+- amlogic,clrmask=< 5 0xe
+- 3 0x80000000
+- 6 0x3c000000
+- 4 0x70000000>;
+- amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
+- "BOOT_5","BOOT_6","BOOT_7","BOOT_12","BOOT_13",
+- "BOOT_14","BOOT_15","BOOT_16";
+- };
+-
+-//$$ MATCH "Nand_pin_0_match" = "&nand_ce0"
+-//$$ MATCH "Nand_pin_1_match" = "&nand_ce0"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- nand_ce0: nand_ce0{
+- amlogic,setmask=<2 0x2000000>;
+- amlogic,pins = "BOOT_8";
+- };
+-
+-//$$ MATCH "Nand_pin_0_match" = "&nand_ce1"
+-//$$ MATCH "Nand_pin_1_match" = "&nand_ce1"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- nand_ce1: nand_ce1{
+- amlogic,setmask=<2 0x1000000>;
+- amlogic,pins = "BOOT_9";
+- };
+-
+-//$$ MATCH "Nand_pin_1_match" = "&nand_ce2"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- nand_ce2: nand_ce2{
+- amlogic,setmask=<2 0x800000>;
+- amlogic,pins = "BOOT_10";
+- };
+-
+-//$$ MATCH "Nand_pin_1_match" = "&nand_ce3"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- nand_ce3: nand_ce3{
+- amlogic,setmask=<2 0x400000>;
+- amlogic,pins = "BOOT_11";
+- };
+-
+-//$$ MATCH "Nand_pin_0_match" = "&nand_rb0"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- nand_rb0: nand_rb0{
+- amlogic,setmask=<2 0x20000>;
+- amlogic,clrmask=<2 0x800000>;
+- amlogic,pins = "BOOT_10";
+- };
+-
+-//$$ MATCH "Nand_pin_0_match" = "&nand_rb1"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- nand_rb1: nand_rb1{
+- amlogic,setmask=<2 0x10000>;
+- amlogic,clrmask=<2 0x400000>;
+- amlogic,pins = "BOOT_11";
+- };
+-
+-
+- sdio_all_pins:sdio_all_pins{
+- amlogic,setmask=<8 0x0000003f>; /*sdio a*/
+- amlogic,clrmask=<6 0x3f000000 /*sdio c*/
+- 2 0x0000fc00 /*sdio b*/
+- 5 0x00006c00>; /*sdhc a*/
+- amlogic,pins = "GPIOX_0","GPIOX_1","GPIOX_2","GPIOX_3","GPIOX_8","GPIOX_9";
+- amlogic,enable-output=<1>; /* 0:output, 1:input */
+- amlogic,pullup=<0>;
+- };
+- sdio_clk_cmd_pins:sdio_clk_cmd_pins{
+- amlogic,setmask=<8 0x00000003>; /*sdio a*/
+- amlogic,clrmask=<6 0x3f000000 /*sdio c*/
+- 2 0x0000fc00 /*sdio b*/
+- 5 0x00006c00>; /*sdhc a*/
+- amlogic,pins = "GPIOX_8","GPIOX_9";
+- amlogic,enable-output=<1>; /* 0:output, 1:input */
+- amlogic,pullup=<0>;
+- };
+- sd_all_pins:sd_all_pins{
+- amlogic,setmask=<2 0x0000fc00>; /*sdio b*/
+- amlogic,clrmask=<6 0x3f000000 /*sdio c*/
+- 8 0x0000003f /*sdio a*/
+- 2 0x000000f0>; /*sdhc b*/
+- amlogic,pins = "CARD_0","CARD_1","CARD_2","CARD_3","CARD_4","CARD_5";
+- amlogic,enable-output=<1>; /* 0:output, 1:input */
+- amlogic,pullup=<0>;
+- };
+- sd_clk_cmd_pins:sd_clk_cmd_pins{
+- amlogic,setmask=<2 0x00000c00>; /*sdio b*/
+- amlogic,clrmask=<6 0x3f000000 /*sdio c*/
+- 8 0x0000003f /*sdio a*/
+- 2 0x000000f0>; /*sdhc b*/
+- amlogic,pins = "CARD_4","CARD_5"; /* CARD_4:CLK, CARD_5:CMD */
+- amlogic,enable-output=<1>; /* 0:output, 1:input */
+- amlogic,pullup=<0>;
+- };
+- emmc_all_pins:emmc_all_pins{
+- amlogic,setmask=<6 0x3f000000>; /*sdio c, */
+- amlogic,clrmask=<2 0x04c3fc00 /*sdio b & nand*/
+- 8 0x0000003f /*sdio a*/
+- 4 0x6c000000 /*sdhc c*/
+- 3 0x80000000>; /*I2C*/
+- amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_10","BOOT_11";
+- amlogic,enable-output=<1>; /* 0:output, 1:input */
+- amlogic,pullup=<0>;
+- };
+- emmc_clk_cmd_pins:emmc_clk_cmd_pins{
+- amlogic,setmask=<6 0x03000000>; /*bit[24-25] */
+- amlogic,clrmask=<2 0x04c3fc00 /*sdio b & nand*/
+- 8 0x0000003f /*sdio a*/
+- 4 0x6c000000 /*sdhc c*/
+- 3 0x80000000>; /*I2C*/
+- amlogic,pins = "BOOT_10","BOOT_11";
+- amlogic,enable-output=<1>; /* 0:output, 1:input */
+- amlogic,pullup=<0>;
+- };
+-
+-//$$ MATCH "Remote_pin_match" = "&remote_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR= "amlogic,pins"
+- remote_pins:remote_pin{
+- amlogic,setmask=<10 0x1>;
+- amlogic,pins="GPIOAO_7";
+- };
+-
+-//$$ MATCH "wm8960_pin_match" = "&aml_i2s_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 4 = "amlogic,pins"
+- aml_i2s_pins: aml_i2s_pins{
+- amlogic,setmask=<9 0xAB0>;
+- amlogic,clrmask=<9 0x440>;
+- amlogic,pins = "GPIOE_0","GPIOE_1","GPIOE_2","GPIOE_3";
+- };
+-
+-//$$ MATCH "wm8960_pin_match" = "&config_aml_hp_det_pins"
+-//$$ L2 PROP_STR= "amlogic,pins"
+-//$$ L2 PROP_U32 = "amlogic,pullup"
+- config_aml_hp_det_pins: config_aml_hp_det_pins{
+- amlogic,pins = "GPIOA_19";
+- amlogic,pullup=<1>;
+- };
+-
+-//$$ MATCH "dummy_codec_audio_0_pin_match" = "&aml_dummy_codec_pins"
+-//$$ L2 PROP_U32 2*2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 5 = "amlogic,pins"
+- aml_dummy_codec_pins: aml_dummy_codec_pins{
+- amlogic,setmask=<9 0x2B0
+- 3 0x1000000>;
+- amlogic,clrmask=<9 0x380c4e>;
+- amlogic,pins = "GPIOE_1","GPIOE_2","GPIOE_3","GPIOE_4","GPIOC_9";
+- };
+-//$$ MATCH "Bl_pin_0_match" = "&lcd_backlight_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- lcd_backlight_pins:lcd_backlight{
+- amlogic,setmask=<2 0x8>;
+- amlogic,clrmask=<1 0x10000000>;
+- amlogic,pins = "GPIOD_1";
+- };
+- lcd_ttl_hvsync_pins_on:lcd_ttl_hvsync_on{
+- amlogic,setmask=<1 0xc0000>;
+- amlogic,clrmask=<0 0xc00000>;
+- amlogic,pins = "GPIOD_2","GPIOD_3";
+- };
+- lcd_ttl_hvsync_pins_off:lcd_ttl_hvsync_off{
+- amlogic,clrmask=<0 0xc00000 1 0xc0000>;
+- amlogic,pins = "GPIOD_2","GPIOD_3";
+- amlogic,enable-output=<1>;
+- };
+- lcd_ttl_de_pins_on:lcd_ttl_de_on{
+- amlogic,setmask=<1 0x20000>;
+- amlogic,clrmask=<0 0x1000000>;
+- amlogic,pins = "GPIOD_4";
+- };
+- lcd_ttl_de_pins_off:lcd_ttl_de_off{
+- amlogic,clrmask=<0 0x1000000 1 0x20000>;
+- amlogic,pins = "GPIOD_4";
+- amlogic,enable-output=<1>;
+- };
+- lcd_ttl_clk_pins_on:lcd_ttl_clk_on{
+- amlogic,setmask=<1 0x4000>;
+- amlogic,clrmask=<0 0x8000000 1 0x3800>;
+- amlogic,pins = "GPIOD_7";
+- };
+- lcd_ttl_clk_pins_off:lcd_ttl_clk_off{
+- amlogic,clrmask=<0 0x8000000 1 0x7800>;
+- amlogic,pins = "GPIOD_7";
+- amlogic,enable-output=<1>;
+- };
+- lcd_ttl_rgb_8bit_pins_on:lcd_ttl_rgb_8bit_on{
+- amlogic,setmask=<0 0x3f>;
+- amlogic,clrmask=<5 0xff8000>;
+- amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R0~R7
+- "GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G0~G7
+- "GPIOB_16","GPIOB_17","GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23";//B0~B7
+- };
+- lcd_ttl_rgb_8bit_pins_off:lcd_ttl_rgb_8bit_off{
+- amlogic,clrmask=<0 0x3f 5 0xff8000>;
+- amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R0~R7
+- "GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G0~G7
+- "GPIOB_16","GPIOB_17","GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23";//B0~B7
+- amlogic,enable-output=<1>;
+- };
+- lcd_ttl_rgb_6bit_pins_on:lcd_ttl_rgb_6bit_on{
+- amlogic,setmask=<0 0x15>;
+- amlogic,clrmask=<5 0xf98000>;
+- amlogic,pins = "GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R2~R7
+- "GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G2~G7
+- "GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23"; //B2~B7
+- };
+- lcd_ttl_rgb_6bit_pins_off:lcd_ttl_rgb_6bit_off{
+- amlogic,clrmask=<0 0x15 5 0xf98000>;
+- amlogic,pins = "GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R2~R7
+- "GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G2~G7
+- "GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23"; //B2~B7
+- amlogic,enable-output=<1>;
+- };
+-
+-//$$ MATCH "Camera_pin_match" = "&aml_cam_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_STR = "amlogic,pins"
+- aml_cam_pins: aml_cam_pins{
+- amlogic,setmask=<9 0x1000>;
+- amlogic,pins = "GPIOZ_12";
+- };
+-
+-//$$ MATCH "Spi_pin_0_match" = "&aml_spi_nor_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 2 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 4 = "amlogic,pins"
+- aml_spi_nor_pins: aml_spi_nor_pins{
+- amlogic,setmask=<5 0xf>;
+- amlogic,clrmask=<2 0x380000>;
+- amlogic,pins = "BOOT_12","BOOT_13","BOOT_14","BOOT_17";
+- };
+-//$$ MATCH "dvb_p_ts2_pins_match" = "&dvb_p_ts2_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 8 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 12 = "amlogic,pins"
+- dvb_p_ts2_pins: dvb_p_ts2_pins {
+- amlogic,setmask = <3 0xfc0>;
+- amlogic,clrmask = <0 0xf
+- 5 0xff00>;
+- amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7","GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11";
+- };
+-
+-//$$ MATCH "dvb_s_ts2_pins_match" = "&dvb_s_ts2_pins"
+-//$$ L2 PROP_U32 2 = "amlogic,setmask"
+-//$$ L2 PROP_U32 6 = "amlogic,clrmask"
+-//$$ L2 PROP_STR 5 = "amlogic,pins"
+- dvb_s_ts2_pins: dvb_s_ts2_pins {
+- amlogic,setmask = <3 0xfc0>;
+- amlogic,clrmask = <0 0xf
+- 5 0xff00>;
+- amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7","GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11";
+- };
+- };
+-/// ***************************************************************************************
+-/// - DVB
+-//$$ MODULE="DVB"
+-
+-//$$ DEVICE="dvb"
+-//$$ L2 PROP_STR = "ts2"
+-//$$ L2 PROP_U32 = "ts2_invert"
+-//$$ L2 PROP_U32 = "ts2_control"
+-//$$ L2 PROP_STR 6 = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "dvb_p_ts2_pins_match" = "pinctrl-0"
+-//$$ L2 PROP_CHOICE "dvb_s_ts2_pins_match" = "pinctrl-1"
+- dvb{
+- compatible = "amlogic,dvb";
+- /*"parallel","serial","disable"*/
+- ts2 = "parallel";
+- ts2_control = <0>;
+- ts2_invert = <0>;
+- pinctrl-names = "p_ts2", "s_ts2";
+- pinctrl-0 = <&dvb_p_ts2_pins>;
+- pinctrl-1 = <&dvb_s_ts2_pins>;
+- };
+-
+-//$$ DEVICE="dvbfe"
+-//$$ L2 PROP_STR = "dtv_demod0"
+-//$$ L2 PROP_U32 = "dtv_demod0_i2c_adap_id"
+-//$$ L2 PROP_U32 = "dtv_demod0_i2c_addr"
+-//$$ L2 PROP_U32 = "dtv_demod0_reset_value"
+-//$$ L2 PROP_STR = "dtv_demod0_reset_gpio"
+-//$$ L2 PROP_U32 = "fe0_dtv_demod"
+-//$$ L2 PROP_U32 = "fe0_ts"
+-//$$ L2 PROP_U32 = "fe0_dev"
+-//$$ L2 PROP_STR 6 = "pinctrl-names"
+-//$$ L2 PROP_CHOICE "dvb_fe_pins_match" = "pinctrl-0"
+- dvbfe{
+- compatible = "amlogic,dvbfe";
+- dtv_demod0 = "Avl6211";
+- dtv_demod0_i2c_adap_id = <1>;
+- dtv_demod0_i2c_addr = <0xC0>;
+- dtv_demod0_reset_value = <0>;
+- dtv_demod0_reset_gpio = "GPIOD_8";
+- fe0_dtv_demod = <0>;
+- fe0_ts = <2>;
+- fe0_dev = <0>;
+-
+- };
+-}; /* end of / */
+-
++
++/// ***************************************************************************************
++/// - Efuse
++//$$ MODULE="Efuse"
++//$$ DEVICE="efuse"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_U32 2 = "plat-pos"
++//$$ L2 PROP_U32 = "plat-count"
++//$$ L2 PROP_U32 = "usid-min"
++//$$ L2 PROP_U32 = "usid-max"
++ efuse{
++ compatible = "amlogic,efuse";
++ dev_name = "efuse";
++ status = "okay";
++ plat-pos = <0 454>;
++ plat-count = <58>;
++ usid-min = <8>; /*reserved*/
++ usid-max = <31>; /*reserved*/
++ };
++
++/// ***************************************************************************************
++/// - HDMI
++//$$ MODULE="HDMI"
++//$$ DEVICE="amhdmitx"
++//$$ L2 PROP_STR = "status"
++//$$ L2 PROP_CHOICE "HDMI_vend-data_match" = "vend-data"
++//$$ L2 PROP_CHOICE "HDMI_pwr-ctrl_match" = "pwr-ctrl"
++ amhdmitx{
++ compatible = "amlogic,amhdmitx";
++ dev_name = "amhdmitx";
++ status = "ok";
++ vend-data = <&vend_data>;
++ pwr-ctrl = <&pwr_ctrl>;
++ phy-size = <3>;
++ phy-data = <27 0x16 0x30 /* 480i/p 576i/p */
++ 74 0x16 0x40 /* 720p 1080i */
++ 148 0x16 0x40 /* 1080p */
++ >;
++
++//$$ MATCH "HDMI_vend-data_match" = <&vend_data>
++//$$ L2 PROP_STR = "vendor_name"
++//$$ L2 PROP_U32 = "vendor_id"
++//$$ L2 PROP_STR = "product_desc"
++//$$ L2 PROP_STR = "cec_osd_string"
++ vend_data: vend_data{
++ vendor_name = "Amlogic"; /* Max Chars: 8 */
++ vendor_id = <0x000000>; /* Refer to http://standards.ieee.org/develop/regauth/oui/oui.txt */
++ product_desc = "MX MBox G18Ref"; /* Max Chars: 16 */
++ cec_osd_string = "Amlogic MBox"; /* Max Chars: 14 */
++ };
++
++//$$ MATCH "HDMI_pwr-ctrl_match" = <&pwr_ctrl>
++//$$ L2 PROP_STR = "pwr_5v_on"
++//$$ L2 PROP_STR 3 = "pwr_5v_off"
++//$$ L2 PROP_STR 3 = "pwr_3v3_on"
++//$$ L2 PROP_STR = "pwr_3v3_off"
++//$$ L2 PROP_STR = "pwr_hpll_vdd_on"
++//$$ L2 PROP_STR = "pwr_hpll_vdd_off"
++ pwr_ctrl: pwr_ctrl{
++ pwr_5v_on = "cpu","GPIOD_5","H";
++ pwr_5v_off = "cpu","GPIOD_5","L";
++ pwr_3v3_on = "";
++ pwr_3v3_off = "";
++ pwr_hpll_vdd_on = "";
++ pwr_hpll_vdd_off = "";
++ };
++ };
++
++/// ***************************************************************************************
++/// - Securitykey
++//$$ MODULE="Securitykey"
++ securitykey{
++ compatible = "amlogic,aml_keys";
++ };
++
++/// ***************************************************************************************
++/// - PowerManager
++//$$ MODULE="PowerManager"
++//$$ DEVICE="amvenc_avc"
++//$$ L2 PROP_STR = "status"
++ aml_pm{
++ compatible = "amlogic,pm";
++ dev_name = "aml_pm";
++ status = "okay";
++ };
++
++/// ***************************************************************************************
++/// - Cpufreq
++//$$ MODULE="Cpufreq"
++//$$ DEVICE="cpufreq-meson"
++//$$ L2 PROP_STR = "status"
++ cpufreq-meson{
++ compatible = "amlogic,cpufreq-meson";
++ status = "okay";
++ };
++
++
++
++
++
++
++/// ***************************************************************************************
++/// - Ethernet
++//$$ MODULE="Ethernet"
++//$$ DEVICE="meson-eth"
++//$$ L2 PROP_STR = "status"
++ meson-eth{
++ compatible = "amlogic,meson-eth";
++ dev_name = "meson-eth";
++ status = "okay";
++ ethbaseaddr = <0xf3610000>;
++ interruptnum = <40>;
++ };
++
++
++
++
++
++
++/// **************************************************************************************
++/// - GPIO
++//$$ MODULE="GPIO"
++//$$ DEVICE="m6-gpio"
++ gpio:gpio{
++ compatible = "amlogic,m6-gpio";
++ dev_name = "gpio";
++ #gpio-cells=<2>;
++ };
++
++/// **************************************************************************************
++/// - Pinmux
++//$$ MODULE="Pinmux"
++//$$ DEVICE="pinmux-m6"
++ pinmux{
++ compatible = "amlogic,pinmux-m6";
++ dev_name = "pinmux";
++ #pinmux-cells=<2>;
++
++//$$ MATCH "uart_ao_pin_match" = "&ao_uart_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR 2 = "amlogic,pins"
++ ao_uart_pins:ao_uart{
++ amlogic,setmask=<10 0x1800>;
++ amlogic,pins="GPIOAO_0", "GPIOAO_1";
++ };
++
++//$$ MATCH "uart_0_pin_match" = "&a_uart_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR 2 = "amlogic,pins"
++ a_uart_pins:a_uart{
++ amlogic,setmask=<4 0x3c00>;
++ amlogic,pins="GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16";
++ };
++
++//$$ MATCH "meson_vcck_dvfs_pin_0_match" = "&aml_pwm_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ aml_pwm_pins:aml_pwm{
++ amlogic,setmask=<2 0x4>;
++ amlogic,clrmask=<1 0x20000000>;
++ amlogic,pins="GPIOD_0";
++ };
++
++//$$ MATCH "I2C_AO_pin_match" = "&ao_i2c_master"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR 2 = "amlogic,pins"
++ ao_i2c_master:ao_i2c{
++ amlogic,setmask=<10 0x60>;
++ amlogic,clrmask=<10 0x1800006>;
++ amlogic,pins="GPIOAO_4","GPIOAO_5";
++ };
++
++//$$ MATCH "I2C_A_pin_match" = "&a_i2c_master"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR 2 = "amlogic,pins"
++ a_i2c_master:a_i2c{
++ amlogic,setmask=<5 0xc000000>;
++ amlogic,clrmask=<5 0x3000000>;
++ amlogic,pins="GPIOX_25","GPIOX_26";
++ };
++
++//$$ MATCH "I2C_B_pin_match" = "&b_i2c_master"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR 2 = "amlogic,pins"
++ b_i2c_master:b_i2c{
++ amlogic,setmask=<5 0xc0000000>;
++ amlogic,clrmask=<5 0x30000000>;
++ amlogic,pins="GPIOX_27","GPIOX_28";
++ };
++
++//$$ MATCH "Nand_pin_0_match" = "&nand_input_state"
++//$$ MATCH "Nand_pin_1_match" = "&nand_input_state"
++//$$ L2 PROP_STR 17 = "amlogic,pins"
++//$$ L2 PROP_U32 = "amlogic,enable-output"
++ nand_input_state:nand_input{
++ amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
++ "BOOT_5","BOOT_6","BOOT_7","BOOT_12","BOOT_13",
++ "BOOT_8","BOOT_9","BOOT_10","BOOT_11",
++ "BOOT_14","BOOT_15","BOOT_16";
++ amlogic,enable-output=<1>;
++ };
++
++//$$ MATCH "Nand_pin_0_match" = "&conf_nand_state"
++//$$ MATCH "Nand_pin_1_match" = "&conf_nand_state"
++//$$ L2 PROP_STR 9 = "amlogic,pins"
++//$$ L2 PROP_U32 = "amlogic,pullup"
++ conf_nand_state: conf_nand{
++ amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
++ "BOOT_5","BOOT_6","BOOT_7","BOOT_16";
++ amlogic,pullup=<1>;
++ };
++
++//$$ MATCH "Nand_pin_0_match" = "&nand_base"
++//$$ MATCH "Nand_pin_1_match" = "&nand_base"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 4*2 = "amlogic,clrmask"
++//$$ L2 PROP_STR 13 = "amlogic,pins"
++ nand_base: nand{
++ amlogic,setmask=<2 0xc3c0000>;
++ amlogic,clrmask=< 5 0xe
++ 3 0x80000000
++ 6 0x3c000000
++ 4 0x70000000>;
++ amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_4",
++ "BOOT_5","BOOT_6","BOOT_7","BOOT_12","BOOT_13",
++ "BOOT_14","BOOT_15","BOOT_16";
++ };
++
++//$$ MATCH "Nand_pin_0_match" = "&nand_ce0"
++//$$ MATCH "Nand_pin_1_match" = "&nand_ce0"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ nand_ce0: nand_ce0{
++ amlogic,setmask=<2 0x2000000>;
++ amlogic,pins = "BOOT_8";
++ };
++
++//$$ MATCH "Nand_pin_0_match" = "&nand_ce1"
++//$$ MATCH "Nand_pin_1_match" = "&nand_ce1"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ nand_ce1: nand_ce1{
++ amlogic,setmask=<2 0x1000000>;
++ amlogic,pins = "BOOT_9";
++ };
++
++//$$ MATCH "Nand_pin_1_match" = "&nand_ce2"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ nand_ce2: nand_ce2{
++ amlogic,setmask=<2 0x800000>;
++ amlogic,pins = "BOOT_10";
++ };
++
++//$$ MATCH "Nand_pin_1_match" = "&nand_ce3"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ nand_ce3: nand_ce3{
++ amlogic,setmask=<2 0x400000>;
++ amlogic,pins = "BOOT_11";
++ };
++
++//$$ MATCH "Nand_pin_0_match" = "&nand_rb0"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ nand_rb0: nand_rb0{
++ amlogic,setmask=<2 0x20000>;
++ amlogic,clrmask=<2 0x800000>;
++ amlogic,pins = "BOOT_10";
++ };
++
++//$$ MATCH "Nand_pin_0_match" = "&nand_rb1"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ nand_rb1: nand_rb1{
++ amlogic,setmask=<2 0x10000>;
++ amlogic,clrmask=<2 0x400000>;
++ amlogic,pins = "BOOT_11";
++ };
++
++
++ sdio_all_pins:sdio_all_pins{
++ amlogic,setmask=<8 0x0000003f>; /*sdio a*/
++ amlogic,clrmask=<6 0x3f000000 /*sdio c*/
++ 2 0x0000fc00 /*sdio b*/
++ 5 0x00006c00>; /*sdhc a*/
++ amlogic,pins = "GPIOX_0","GPIOX_1","GPIOX_2","GPIOX_3","GPIOX_8","GPIOX_9";
++ amlogic,enable-output=<1>; /* 0:output, 1:input */
++ amlogic,pullup=<0>;
++ };
++ sdio_clk_cmd_pins:sdio_clk_cmd_pins{
++ amlogic,setmask=<8 0x00000003>; /*sdio a*/
++ amlogic,clrmask=<6 0x3f000000 /*sdio c*/
++ 2 0x0000fc00 /*sdio b*/
++ 5 0x00006c00>; /*sdhc a*/
++ amlogic,pins = "GPIOX_8","GPIOX_9";
++ amlogic,enable-output=<1>; /* 0:output, 1:input */
++ amlogic,pullup=<0>;
++ };
++ sd_all_pins:sd_all_pins{
++ amlogic,setmask=<2 0x0000fc00>; /*sdio b*/
++ amlogic,clrmask=<6 0x3f000000 /*sdio c*/
++ 8 0x0000003f /*sdio a*/
++ 2 0x000000f0>; /*sdhc b*/
++ amlogic,pins = "CARD_0","CARD_1","CARD_2","CARD_3","CARD_4","CARD_5";
++ amlogic,enable-output=<1>; /* 0:output, 1:input */
++ amlogic,pullup=<0>;
++ };
++ sd_clk_cmd_pins:sd_clk_cmd_pins{
++ amlogic,setmask=<2 0x00000c00>; /*sdio b*/
++ amlogic,clrmask=<6 0x3f000000 /*sdio c*/
++ 8 0x0000003f /*sdio a*/
++ 2 0x000000f0>; /*sdhc b*/
++ amlogic,pins = "CARD_4","CARD_5"; /* CARD_4:CLK, CARD_5:CMD */
++ amlogic,enable-output=<1>; /* 0:output, 1:input */
++ amlogic,pullup=<0>;
++ };
++ emmc_all_pins:emmc_all_pins{
++ amlogic,setmask=<6 0x3f000000>; /*sdio c, */
++ amlogic,clrmask=<2 0x04c3fc00 /*sdio b & nand*/
++ 8 0x0000003f /*sdio a*/
++ 4 0x6c000000 /*sdhc c*/
++ 3 0x80000000>; /*I2C*/
++ amlogic,pins = "BOOT_0","BOOT_1","BOOT_2","BOOT_3","BOOT_10","BOOT_11";
++ amlogic,enable-output=<1>; /* 0:output, 1:input */
++ amlogic,pullup=<0>;
++ };
++ emmc_clk_cmd_pins:emmc_clk_cmd_pins{
++ amlogic,setmask=<6 0x03000000>; /*bit[24-25] */
++ amlogic,clrmask=<2 0x04c3fc00 /*sdio b & nand*/
++ 8 0x0000003f /*sdio a*/
++ 4 0x6c000000 /*sdhc c*/
++ 3 0x80000000>; /*I2C*/
++ amlogic,pins = "BOOT_10","BOOT_11";
++ amlogic,enable-output=<1>; /* 0:output, 1:input */
++ amlogic,pullup=<0>;
++ };
++
++//$$ MATCH "Remote_pin_match" = "&remote_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR= "amlogic,pins"
++ remote_pins:remote_pin{
++ amlogic,setmask=<10 0x1>;
++ amlogic,pins="GPIOAO_7";
++ };
++
++//$$ MATCH "wm8960_pin_match" = "&aml_i2s_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR 4 = "amlogic,pins"
++ aml_i2s_pins: aml_i2s_pins{
++ amlogic,setmask=<9 0xAB0>;
++ amlogic,clrmask=<9 0x440>;
++ amlogic,pins = "GPIOE_0","GPIOE_1","GPIOE_2","GPIOE_3";
++ };
++
++//$$ MATCH "wm8960_pin_match" = "&config_aml_hp_det_pins"
++//$$ L2 PROP_STR= "amlogic,pins"
++//$$ L2 PROP_U32 = "amlogic,pullup"
++ config_aml_hp_det_pins: config_aml_hp_det_pins{
++ amlogic,pins = "GPIOA_19";
++ amlogic,pullup=<1>;
++ };
++
++//$$ MATCH "dummy_codec_audio_0_pin_match" = "&aml_dummy_codec_pins"
++//$$ L2 PROP_U32 2*2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR 5 = "amlogic,pins"
++ aml_dummy_codec_pins: aml_dummy_codec_pins{
++ amlogic,setmask=<9 0x2B0
++ 3 0x1000000>;
++ amlogic,clrmask=<9 0x380c4e>;
++ amlogic,pins = "GPIOE_1","GPIOE_2","GPIOE_3","GPIOE_4","GPIOC_9";
++ };
++//$$ MATCH "Bl_pin_0_match" = "&lcd_backlight_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ lcd_backlight_pins:lcd_backlight{
++ amlogic,setmask=<2 0x8>;
++ amlogic,clrmask=<1 0x10000000>;
++ amlogic,pins = "GPIOD_1";
++ };
++ lcd_ttl_hvsync_pins_on:lcd_ttl_hvsync_on{
++ amlogic,setmask=<1 0xc0000>;
++ amlogic,clrmask=<0 0xc00000>;
++ amlogic,pins = "GPIOD_2","GPIOD_3";
++ };
++ lcd_ttl_hvsync_pins_off:lcd_ttl_hvsync_off{
++ amlogic,clrmask=<0 0xc00000 1 0xc0000>;
++ amlogic,pins = "GPIOD_2","GPIOD_3";
++ amlogic,enable-output=<1>;
++ };
++ lcd_ttl_de_pins_on:lcd_ttl_de_on{
++ amlogic,setmask=<1 0x20000>;
++ amlogic,clrmask=<0 0x1000000>;
++ amlogic,pins = "GPIOD_4";
++ };
++ lcd_ttl_de_pins_off:lcd_ttl_de_off{
++ amlogic,clrmask=<0 0x1000000 1 0x20000>;
++ amlogic,pins = "GPIOD_4";
++ amlogic,enable-output=<1>;
++ };
++ lcd_ttl_clk_pins_on:lcd_ttl_clk_on{
++ amlogic,setmask=<1 0x4000>;
++ amlogic,clrmask=<0 0x8000000 1 0x3800>;
++ amlogic,pins = "GPIOD_7";
++ };
++ lcd_ttl_clk_pins_off:lcd_ttl_clk_off{
++ amlogic,clrmask=<0 0x8000000 1 0x7800>;
++ amlogic,pins = "GPIOD_7";
++ amlogic,enable-output=<1>;
++ };
++ lcd_ttl_rgb_8bit_pins_on:lcd_ttl_rgb_8bit_on{
++ amlogic,setmask=<0 0x3f>;
++ amlogic,clrmask=<5 0xff8000>;
++ amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R0~R7
++ "GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G0~G7
++ "GPIOB_16","GPIOB_17","GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23";//B0~B7
++ };
++ lcd_ttl_rgb_8bit_pins_off:lcd_ttl_rgb_8bit_off{
++ amlogic,clrmask=<0 0x3f 5 0xff8000>;
++ amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R0~R7
++ "GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G0~G7
++ "GPIOB_16","GPIOB_17","GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23";//B0~B7
++ amlogic,enable-output=<1>;
++ };
++ lcd_ttl_rgb_6bit_pins_on:lcd_ttl_rgb_6bit_on{
++ amlogic,setmask=<0 0x15>;
++ amlogic,clrmask=<5 0xf98000>;
++ amlogic,pins = "GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R2~R7
++ "GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G2~G7
++ "GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23"; //B2~B7
++ };
++ lcd_ttl_rgb_6bit_pins_off:lcd_ttl_rgb_6bit_off{
++ amlogic,clrmask=<0 0x15 5 0xf98000>;
++ amlogic,pins = "GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7", //R2~R7
++ "GPIOB_10","GPIOB_11","GPIOB_12","GPIOB_13","GPIOB_14","GPIOB_15", //G2~G7
++ "GPIOB_18","GPIOB_19","GPIOB_20","GPIOB_21","GPIOB_22","GPIOB_23"; //B2~B7
++ amlogic,enable-output=<1>;
++ };
++
++//$$ MATCH "Camera_pin_match" = "&aml_cam_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_STR = "amlogic,pins"
++ aml_cam_pins: aml_cam_pins{
++ amlogic,setmask=<9 0x1000>;
++ amlogic,pins = "GPIOZ_12";
++ };
++
++//$$ MATCH "Spi_pin_0_match" = "&aml_spi_nor_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 2 = "amlogic,clrmask"
++//$$ L2 PROP_STR 4 = "amlogic,pins"
++ aml_spi_nor_pins: aml_spi_nor_pins{
++ amlogic,setmask=<5 0xf>;
++ amlogic,clrmask=<2 0x380000>;
++ amlogic,pins = "BOOT_12","BOOT_13","BOOT_14","BOOT_17";
++ };
++//$$ MATCH "dvb_p_ts2_pins_match" = "&dvb_p_ts2_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 8 = "amlogic,clrmask"
++//$$ L2 PROP_STR 12 = "amlogic,pins"
++ dvb_p_ts2_pins: dvb_p_ts2_pins {
++ amlogic,setmask = <3 0xfff>;
++ amlogic,clrmask = <0 0xf 5 0xff00>;
++ amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7","GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11";
++ };
++
++//$$ MATCH "dvb_s_ts2_pins_match" = "&dvb_s_ts2_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 6 = "amlogic,clrmask"
++//$$ L2 PROP_STR 5 = "amlogic,pins"
++ dvb_s_ts2_pins: dvb_s_ts2_pins {
++ amlogic,setmask = <3 0xfff>;
++ amlogic,clrmask = <0 0xf 5 0xff00>;
++ amlogic,pins = "GPIOB_0","GPIOB_1","GPIOB_2","GPIOB_3","GPIOB_4","GPIOB_5","GPIOB_6","GPIOB_7","GPIOB_8","GPIOB_9","GPIOB_10","GPIOB_11";
++ };
++
++//$$ MATCH "dvb_p_ts0_pins_match" = "&dvb_p_ts0_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 8 = "amlogic,clrmask"
++//$$ L2 PROP_STR 12 = "amlogic,pins"
++ dvb_p_ts0_pins: dvb_p_ts0_pins {
++ amlogic,setmask = <3 0xfff>;
++ amlogic,clrmask = <0 0x40 6 0xf80000>;
++ amlogic,pins = "GPIOA_0","GPIOA_1","GPIOA_2","GPIOA_3","GPIOA_4","GPIOA_5","GPIOA_6","GPIOA_7","GPIOA_8","GPIOA_9","GPIOA_10","GPIOA_11";
++ };
++
++//$$ MATCH "dvb_s_ts0_pins_match" = "&dvb_s_ts0_pins"
++//$$ L2 PROP_U32 2 = "amlogic,setmask"
++//$$ L2 PROP_U32 6 = "amlogic,clrmask"
++//$$ L2 PROP_STR 5 = "amlogic,pins"
++ dvb_s_ts0_pins: dvb_s_ts0_pins {
++ amlogic,setmask = <3 0xfff>;
++ amlogic,clrmask = <0 0x40 6 0xF80000>;
++ amlogic,pins = "GPIOA_0","GPIOA_1","GPIOA_2","GPIOA_3","GPIOA_4","GPIOA_5","GPIOA_6","GPIOA_7","GPIOA_8","GPIOA_9","GPIOA_10","GPIOA_11";
++ };
++ };
++/// ***************************************************************************************
++/// - DVB
++//$$ MODULE="DVB"
++
++//$$ DEVICE="dvb"
++//$$ L2 PROP_STR = "ts2"
++//$$ L2 PROP_U32 = "ts2_invert"
++//$$ L2 PROP_U32 = "ts2_control"
++//$$ L2 PROP_STR 6 = "pinctrl-names"
++//$$ L2 PROP_CHOICE "dvb_p_ts2_pins_match" = "pinctrl-0"
++//$$ L2 PROP_CHOICE "dvb_s_ts2_pins_match" = "pinctrl-1"
++ dvb{
++ compatible = "amlogic,dvb";
++ /*"parallel","serial","disable"*/
++ ts2 = "parallel";
++ ts2_control = <0>;
++ ts2_invert = <0>;
++ ts0 = "parallel";
++ ts0_control = <0>;
++ ts0_invert = <0>;
++ pinctrl-names = "p_ts0", "s_ts0","p_ts2", "s_ts2";
++ pinctrl-0 = <&dvb_p_ts0_pins>;
++ pinctrl-1 = <&dvb_s_ts0_pins>;
++ pinctrl-2 = <&dvb_p_ts2_pins>;
++ pinctrl-3 = <&dvb_s_ts2_pins>;
++
++ };
++
++//$$ DEVICE="dvbfe"
++//$$ L2 PROP_STR = "dtv_demod0"
++//$$ L2 PROP_U32 = "dtv_demod0_i2c_adap_id"
++//$$ L2 PROP_U32 = "dtv_demod0_i2c_addr"
++//$$ L2 PROP_U32 = "dtv_demod0_reset_value"
++//$$ L2 PROP_STR = "dtv_demod0_reset_gpio"
++//$$ L2 PROP_U32 = "fe0_dtv_demod"
++//$$ L2 PROP_U32 = "fe0_ts"
++//$$ L2 PROP_U32 = "fe0_dev"
++//$$ L2 PROP_STR 6 = "pinctrl-names"
++//$$ L2 PROP_CHOICE "dvb_fe_pins_match" = "pinctrl-0"
++ dvbfe{
++ compatible = "amlogic,dvbfe";
++ dtv_demod0 = "Avl6211_0";
++ dtv_demod0_i2c_adap_id = <1>;
++ dtv_demod0_i2c_addr = <0xC0>;
++ dtv_demod0_reset_value = <0>;
++ dtv_demod0_reset_gpio = "GPIOD_8";
++ fe0_dtv_demod = <0>;
++ fe0_ts = <2>;
++ fe0_dev = <0>;
++ dtv_demod1 = "Avl6211_1";
++ dtv_demod1_i2c_adap_id = <2>;
++ dtv_demod1_i2c_addr = <0xC0>;
++ dtv_demod1_reset_value = <0>;
++ dtv_demod1_reset_gpio = "GPIOD_8";
++ fe1_dtv_demod = <1>;
++ fe1_ts = <0>;
++ fe1_dev = <1>;
++ };
++}; /* end of / */
++
diff --git a/projects/WeTek.Play/patches/linux/no_dev_console.patch b/projects/WeTek.Play/patches/linux/no_dev_console.patch
new file mode 100644
index 0000000000..df35a7ab9a
--- /dev/null
+++ b/projects/WeTek.Play/patches/linux/no_dev_console.patch
@@ -0,0 +1,21 @@
+diff --git a/init/main.c b/init/main.c
+index 9484f4b..db55edd 100644
+--- a/init/main.c
++++ b/init/main.c
+@@ -880,8 +880,14 @@ static noinline void __init kernel_init_freeable(void)
+ do_basic_setup();
+
+ /* Open the /dev/console on the rootfs, this should never fail */
+- if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0)
+- pr_err("Warning: unable to open an initial console.\n");
++ char *console = "/dev_console";
++
++ if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) {
++ sys_mknod(console, S_IFCHR|0600, (TTYAUX_MAJOR<<8)|1);
++ if (sys_open(console, O_RDWR, 0) < 0)
++ printk(KERN_WARNING "Warning: unable to open an initial console.\n");
++ sys_unlink(console);
++ }
+
+ (void) sys_dup(0);
+ (void) sys_dup(0);
diff --git a/projects/WeTek.Play/patches/linux/turn_power_led_into_standby_mode_after_poweroff.patch b/projects/WeTek.Play/patches/linux/turn_power_led_into_standby_mode_after_poweroff.patch
new file mode 100644
index 0000000000..29392a9d3f
--- /dev/null
+++ b/projects/WeTek.Play/patches/linux/turn_power_led_into_standby_mode_after_poweroff.patch
@@ -0,0 +1,28 @@
+diff --git a/arch/arm/mach-meson6/pm.c b/arch/arm/mach-meson6/pm.c
+index 2c08ec1..9b865e7 100755
+--- a/arch/arm/mach-meson6/pm.c
++++ b/arch/arm/mach-meson6/pm.c
+@@ -1056,7 +1056,22 @@ static void power_off_unused_pll(void)
+ }
+ static void m6ref_set_vccx2(int power_on)
+ {
+-
++ if (power_on) {
++ printk(KERN_INFO "%s() Power ON\n", __FUNCTION__);
++ aml_clr_reg32_mask(P_PREG_PAD_GPIO0_EN_N,(1<<26));
++ aml_clr_reg32_mask(P_PREG_PAD_GPIO0_O,(1<<26));
++
++ aml_set_reg32_bits(SECBUS2_REG_ADDR(0), 1, 0, 1); // set TEST_n output mode
++ aml_set_reg32_bits(AOBUS_REG_ADDR(0x24), 1, 31, 1); // set TEST_n pin H
++ }
++ else {
++ printk(KERN_INFO "%s() Power OFF\n", __FUNCTION__);
++ aml_clr_reg32_mask(P_PREG_PAD_GPIO0_EN_N,(1<<26));
++ aml_set_reg32_mask(P_PREG_PAD_GPIO0_O,(1<<26));
++
++ aml_set_reg32_bits(SECBUS2_REG_ADDR(0), 1, 0, 1); // set TEST_n output mode
++ aml_set_reg32_bits(AOBUS_REG_ADDR(0x24), 0, 31, 1); // set TEST_n pin H
++ }
+ }
+
+ static struct meson_pm_config aml_pm_pdata = {