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u-boot (Rockchip): rebase patches for 2025.04

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- replaced by upstream:
  - 1520e81871
  - 2dfa45a785
  - 4e3c7e89d9
  - 055061dc35
- BACKPORT: roc-3328-cc: increase ddr4 clock rate at 800Mhz
- Revert "u-boot (RK3328): BACKPORT: Set efuse auto mode and timing control"
  - This reverts commit 60530331690fb7173a71eb1704542876d5fe1ce8.
- rebase patches for 2024.04
This commit is contained in:
Rudi Heitbaum 2024-07-04 13:59:25 +00:00
parent cc0cc7c39c
commit bb9b73dd7b
4 changed files with 273 additions and 139 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
projects/Rockchip/patches/u-boot/0001-rockchip-rk3328-BACKPORT-Set-efuse-auto-mode-and-timing-control.patch
View File

@ -1,102 +0,0 @@
From 5708e8eeae53ad8ce605afdf61e5a83162dc5131 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 7 Jan 2024 18:18:33 +0000
Subject: [PATCH] rockchip: rk3328: Set efuse auto mode and timing control
Reading from efuse return zero when mainline TF-A is used.
=> dump_efuse
00000000: 00 00 00 00 ....
00000004: 00 00 00 00 ....
00000008: 00 00 00 00 ....
0000000c: 00 00 00 00 ....
00000010: 00 00 00 00 ....
00000014: 00 00 00 00 ....
00000018: 00 00 00 00 ....
0000001c: 00 00 00 00 ....
However, when vendor TF-A blobs is used reading from efuse works.
Change to use auto mode, enable finish and auto access err interrupts
and set timing control using same values that vendor TF-A blob use to
fix this.
With this efuse can be read when either of mainline TF-A or vendor blob
is used.
=> dump_efuse
00000000: 52 4b 33 82 RK3.
00000004: 00 fe 21 55 ..!U
00000008: 52 4b 57 34 RKW4
0000000c: 35 30 32 39 5029
00000010: 00 00 00 00 ....
00000014: 08 25 0c 0f .%..
00000018: 02 0d 08 00 ....
0000001c: 00 00 f0 00 ....
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/mach-rockchip/rk3328/rk3328.c | 38 ++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index de17b886827..ca623c0d3d0 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -19,6 +19,23 @@ DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xFF100000
#define UART2_BASE 0xFF130000
#define FW_DDR_CON_REG 0xFF7C0040
+#define EFUSE_NS_BASE 0xFF260000
+
+#define EFUSE_MOD 0x0000
+#define EFUSE_INT_CON 0x0014
+#define EFUSE_T_CSB_P 0x0028
+#define EFUSE_T_PGENB_P 0x002C
+#define EFUSE_T_LOAD_P 0x0030
+#define EFUSE_T_ADDR_P 0x0034
+#define EFUSE_T_STROBE_P 0x0038
+#define EFUSE_T_CSB_R 0x003C
+#define EFUSE_T_PGENB_R 0x0040
+#define EFUSE_T_LOAD_R 0x0044
+#define EFUSE_T_ADDR_R 0x0048
+#define EFUSE_T_STROBE_R 0x004C
+
+#define EFUSE_USER_MODE 0x1
+#define EFUSE_TIMING(s, l) (((s) << 16) | (l))
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
@@ -50,10 +67,31 @@ struct mm_region *mem_map = rk3328_mem_map;
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
+ u32 reg;
+
/* We do some SoC one time setting here. */
/* Disable the ddr secure region setting to make it non-secure */
rk_setreg(FW_DDR_CON_REG, 0x200);
+
+ /* Use efuse auto mode */
+ reg = readl(EFUSE_NS_BASE + EFUSE_MOD);
+ writel(reg & ~EFUSE_USER_MODE, EFUSE_NS_BASE + EFUSE_MOD);
+
+ /* Enable efuse finish and auto access err interrupt */
+ writel(0x07, EFUSE_NS_BASE + EFUSE_INT_CON);
+
+ /* Set efuse timing control */
+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_CSB_P);
+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_PGENB_P);
+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_LOAD_P);
+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_ADDR_P);
+ writel(EFUSE_TIMING(2, 240), EFUSE_NS_BASE + EFUSE_T_STROBE_P);
+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_CSB_R);
+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_PGENB_R);
+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R);
+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R);
+ writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R);
#endif
return 0;
}

37
projects/Rockchip/patches/u-boot/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch
View File

@ -1,37 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Mon, 31 Oct 2022 17:16:07 +0100
Subject: [PATCH 6/6] Rockchip: rk3399-evb: Don't initalize i2c bus in SPL
Since we are using this device as fallback for boards which are not supported
by mainline u-boot in combination with vendor TPL/SPL, we need to make sure
that i2c is initalized in BL33 because vendor bootchain doesn't do that in
an earlier level.
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index 5e39b1493d..18733da7f9 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -9,18 +9,10 @@
/ {
chosen {
stdout-path = "serial2:1500000n8";
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
-&i2c0 {
- bootph-all;
-};
-
-&rk808 {
- bootph-all;
-};
-
&tcphy1 {
status = "okay";
};

26
projects/Rockchip/patches/u-boot/0006-rockchip-roc-3328-cc-use-1600-ddr4-timing.patch Normal file
View File

@ -0,0 +1,26 @@
From 2e54840fd3de7a791669bf20fc7b576b806167b8 Mon Sep 17 00:00:00 2001
From: Da Xue <da@libre.computer>
Date: Sun, 19 May 2024 18:48:57 -0400
Subject: [PATCH] arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing
Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.
Signed-off-by: Da Xue <da@libre.computer>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 582d6ba49b4e..c47d29c59de9 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -4,7 +4,7 @@
*/
#include "rk3328-u-boot.dtsi"
-#include "rk3328-sdram-ddr4-666.dtsi"
+#include "rk3328-sdram-ddr4-1600.dtsi"
/ {
smbios {

247
projects/Rockchip/patches/u-boot/0007-rockchip-rk3328-add-ddr4-1600-sdram-timing.patch Normal file
View File

@ -0,0 +1,247 @@
From 825863d08ce323ebcefc03af20fb1e37cdac0eaa Mon Sep 17 00:00:00 2001
From: Da Xue <da@libre.computer>
Date: Mon, 19 Sep 2022 13:40:01 -0400
Subject: [PATCH] ram: rk3328: add ddr4-1600 sdram timing
Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
for the ROC-3328-CC board.
Signed-off-by: Da Xue <da@libre.computer>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi | 226 +++++++++++++++++++++++
1 file changed, 226 insertions(+)
create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
new file mode 100644
index 000000000000..9594bb428399
--- /dev/null
+++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+
+&dmc {
+ rockchip,sdram-params = <
+ 0x1
+ 0xA
+ 0x2
+ 0x1
+ 0x0
+ 0x0
+ 0x11
+ 0x0
+ 0x11
+ 0x0
+ 0
+
+ 0x94496354
+ 0x00000000
+ 0x0000002a
+ 0x000004e2
+ 0x00000015
+ 0x0000034a
+ 0x000000ff
+
+ 800
+ 0
+ 1
+ 0
+ 0
+
+ 0x00000000
+ 0x43041010
+ 0x00000064
+ 0x0061008c
+ 0x000000d0
+ 0x000200c5
+ 0x000000d4
+ 0x00500000
+ 0x000000d8
+ 0x00000100
+ 0x000000dc
+ 0x03140401
+ 0x000000e0
+ 0x00000000
+ 0x000000e4
+ 0x00110000
+ 0x000000e8
+ 0x00000420
+ 0x000000ec
+ 0x00000400
+ 0x000000f4
+ 0x000f011f
+ 0x00000100
+ 0x0c0e1b0e
+ 0x00000104
+ 0x00030314
+ 0x00000108
+ 0x0506050b
+ 0x0000010c
+ 0x0040400c
+ 0x00000110
+ 0x06030307
+ 0x00000114
+ 0x04040302
+ 0x00000120
+ 0x06060b06
+ 0x00000124
+ 0x00020308
+ 0x00000180
+ 0x01000040
+ 0x00000184
+ 0x00000000
+ 0x00000190
+ 0x07040003
+ 0x00000198
+ 0x05001100
+ 0x000001a0
+ 0xc0400003
+ 0x00000240
+ 0x0600060c
+ 0x00000244
+ 0x00000201
+ 0x00000250
+ 0x00000f00
+ 0x00000490
+ 0x00000001
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+
+ 0x00000004
+ 0x0000000c
+ 0x00000028
+ 0x0000000c
+ 0x0000002c
+ 0x00000000
+ 0x00000030
+ 0x00000009
+ 0xffffffff
+ 0xffffffff
+
+ 0x77
+ 0x88
+ 0x79
+ 0x79
+ 0x87
+ 0x97
+ 0x87
+ 0x78
+ 0x77
+ 0x78
+ 0x87
+ 0x88
+ 0x87
+ 0x87
+ 0x77
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+ >;
+};