From 3e696a98edbb382430c571df8d28af53fb21126d Mon Sep 17 00:00:00 2001 From: heitbaum Date: Tue, 13 Jul 2021 13:22:11 +0000 Subject: [PATCH 01/51] linux (Allwinner arm): add config option NVME_TCP and VFIO are not set --- projects/Allwinner/linux/linux.arm.conf | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index a8df716748..1a6c78a78c 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.17 Kernel Configuration +# Linux/arm 5.10.50 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0" CONFIG_CC_IS_GCC=y @@ -1405,6 +1405,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # NVME Support # # CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set # CONFIG_NVME_TARGET is not set # end of NVME Support @@ -4590,6 +4591,7 @@ CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +# CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set # CONFIG_VIRTIO_MENU is not set # CONFIG_VDPA is not set From d4e058a333e7d3ea938bacf63b7b470869d75edd Mon Sep 17 00:00:00 2001 From: heitbaum Date: Tue, 13 Jul 2021 11:16:44 +0000 Subject: [PATCH 02/51] linux (Allwinner): patches upstreamed in 5.10.50 --- ...hevc-Add-support-for-multiple-slices.patch | 2 +- ...media-cedrus-wip-hevc-dependent-flag.patch | 37 ------------------- 2 files changed, 1 insertion(+), 38 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0058-media-cedrus-wip-hevc-dependent-flag.patch diff --git a/projects/Allwinner/patches/linux/0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch b/projects/Allwinner/patches/linux/0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch index 1a49b6f12d..eb22de15b0 100644 --- a/projects/Allwinner/patches/linux/0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch +++ b/projects/Allwinner/patches/linux/0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch @@ -68,7 +68,7 @@ Signed-off-by: Jernej Skrabec /* Initialize bitstream access. */ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); @@ -543,8 +549,8 @@ static void cedrus_h265_setup(struct ced - V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT, + V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT, pps->flags); - /* FIXME: For multi-slice support. */ diff --git a/projects/Allwinner/patches/linux/0058-media-cedrus-wip-hevc-dependent-flag.patch b/projects/Allwinner/patches/linux/0058-media-cedrus-wip-hevc-dependent-flag.patch deleted file mode 100644 index 8508ba14a4..0000000000 --- a/projects/Allwinner/patches/linux/0058-media-cedrus-wip-hevc-dependent-flag.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 11 Apr 2021 10:45:50 +0200 -Subject: [PATCH] media: cedrus: wip: hevc: dependent flag - ---- - drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 4 ++-- - include/media/hevc-ctrls.h | 1 + - 2 files changed, 3 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index 8861e1535886..ab6fc857a477 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -634,8 +634,8 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, - slice_params->flags); - - reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT, -- V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT, -- pps->flags); -+ V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT, -+ slice_params->flags); - - if (ctx->fh.m2m_ctx->new_frame) - reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index eb83c1d61b8d..cd51fb6df1f0 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -162,6 +162,7 @@ struct v4l2_hevc_pred_weight_table { - #define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6) - #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7) - #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 9) - - struct v4l2_ctrl_hevc_slice_params { - __u32 bit_size; From e23a4927baea948db1a58311ef20ddbfbe75db4f Mon Sep 17 00:00:00 2001 From: heitbaum Date: Tue, 13 Jul 2021 11:18:10 +0000 Subject: [PATCH 03/51] linux (Rockchip): patches upstreamed in 5.10.50 --- .../linux-2000-v4l-wip-rkvdec-vp9.patch | 38 ------------------- .../linux-2001-v4l-wip-rkvdec-hevc.patch | 18 +-------- 2 files changed, 2 insertions(+), 54 deletions(-) diff --git a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch index 0cac47555d..d8b5058087 100644 --- a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch +++ b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch @@ -1,41 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Mon, 2 Nov 2020 21:05:49 +0200 -Subject: [PATCH] media: rkvdec: Fix .buf_prepare - -The driver should only set the payload on .buf_prepare if the -buffer is CAPTURE type. If an OUTPUT buffer has a zero bytesused -set by userspace then v4l2-core will set it to buffer length. - -Fixes: cd33c830448ba ("media: rkvdec: Add the rkvdec driver") -Signed-off-by: Ezequiel Garcia -Signed-off-by: Adrian Ratiu ---- - drivers/staging/media/rkvdec/rkvdec.c | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 4111155d62f4..c4e0ec16c285 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -546,7 +546,15 @@ static int rkvdec_buf_prepare(struct vb2_buffer *vb) - if (vb2_plane_size(vb, i) < sizeimage) - return -EINVAL; - } -- vb2_set_plane_payload(vb, 0, f->fmt.pix_mp.plane_fmt[0].sizeimage); -+ -+ /* -+ * Buffer bytesused is written by driver for CAPTURE buffers. -+ * (if userspace passes 0 bytesused for OUTPUT buffers, v4l2-core sets -+ * it to buffer length). -+ */ -+ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) -+ vb2_set_plane_payload(vb, 0, f->fmt.pix_mp.plane_fmt[0].sizeimage); -+ - return 0; - } - - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 2 Nov 2020 21:05:50 +0200 diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index 7fd256b17d..cb746a6920 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -2464,7 +2464,7 @@ index 000000000000..03ba848411c6 + /* write pps */ + WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); + WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT), ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), + DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), + OUTPUT_FLAG_PRESENT_FLAG); @@ -3164,8 +3164,7 @@ Subject: [PATCH] WIP: media: rkvdec: hevc: implement lowdelay Signed-off-by: Alex Bee --- drivers/staging/media/rkvdec/rkvdec-hevc.c | 16 ++++++++++++++-- - include/media/hevc-ctrls.h | 1 + - 2 files changed, 15 insertions(+), 2 deletions(-) + 1 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c index 93b4e09e5bf1..8a94fc04980f 100644 @@ -3208,19 +3207,6 @@ index 93b4e09e5bf1..8a94fc04980f 100644 WRITE_RPS(sl_params->long_term_ref_pic_set_size + sl_params->short_term_ref_pic_set_size, -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index b33e1a8141e1..bda0ea61f331 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -168,6 +168,7 @@ struct v4l2_hevc_pred_weight_table { - #define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6) - #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7) - #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 9) - - struct v4l2_ctrl_hevc_slice_params { - __u32 bit_size; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 30 Jan 2021 18:16:39 +0100 From f775bd5fb3b1a340491381320b0be47972dcbf90 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 18 Jul 2021 03:48:10 +0000 Subject: [PATCH 04/51] linux (Rockchip): 5.10.51 upstreamed rk3328 usb3 Full patch remove: - arm64: dts: rockchip: add rk3328 usb3 and usb3phy nodes - partially included in 5.10.51 --- .../linux-0004-rockchip-from-list.patch | 141 ------------------ .../default/linux-1003-for-libreelec.patch | 76 ---------- 2 files changed, 217 deletions(-) diff --git a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch index 9f6ba3f32c..aeabfcd4cb 100644 --- a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch @@ -1067,147 +1067,6 @@ index 000000000000..7007ddbcbdae +MODULE_DESCRIPTION("DesignWare USB3 Rockchip Innosilicon Glue Layer"); +MODULE_AUTHOR("Peter Geis "); -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 16 Nov 2020 15:17:35 +0000 -Subject: [PATCH] arm64: dts: rockchip: add rk3328 usb3 and usb3phy nodes - -Add the usb3 controller and usb3 phy nodes to the rk3328. - -Signed-off-by: Peter Geis ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 65 ++++++++++++++++++++++++ - 1 file changed, 65 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 17709faf651b..d327fd300116 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -856,6 +856,40 @@ u2phy_host: host-port { - }; - }; - -+ usb3phy: usb3-phy@ff470000 { -+ compatible = "rockchip,rk3328-usb3phy"; -+ reg = <0x0 0xff460000 0x0 0x10000>; -+ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; -+ clock-names = "usb3phy-otg", "usb3phy-pipe"; -+ resets = <&cru SRST_USB3PHY_U2>, -+ <&cru SRST_USB3PHY_U3>, -+ <&cru SRST_USB3PHY_PIPE>, -+ <&cru SRST_USB3OTG_UTMI>, -+ <&cru SRST_USB3PHY_OTG_P>, -+ <&cru SRST_USB3PHY_PIPE_P>; -+ reset-names = "usb3phy-u2-por", "usb3phy-u3-por", -+ "usb3phy-pipe-mac", "usb3phy-utmi-mac", -+ "usb3phy-utmi-apb", "usb3phy-pipe-apb"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ usb3phy_utmi: utmi@ff470000 { -+ compatible = "rockchip,rk3328-usb3phy-utmi"; -+ reg = <0x0 0xff470000 0x0 0x8000>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ usb3phy_pipe: pipe@ff478000 { -+ compatible = "rockchip,rk3328-usb3phy-pipe"; -+ reg = <0x0 0xff478000 0x0 0x8000>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ - sdmmc: mmc@ff500000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff500000 0x0 0x4000>; -@@ -987,6 +1021,37 @@ usb_host0_ohci: usb@ff5d0000 { - status = "disabled"; - }; - -+ usbdrd3: usb@ff600000 { -+ compatible = "rockchip,rk3328-dwc3"; -+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, -+ <&cru SCLK_USB3OTG_SUSPEND>; -+ clock-names = "ref", "bus_early", "suspend"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ usbdrd_dwc3: dwc3@ff600000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0xff600000 0x0 0x100000>; -+ interrupts = ; -+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, -+ <&cru SCLK_USB3OTG_SUSPEND>; -+ clock-names = "ref", "bus_early", "suspend"; -+ dr_mode = "host"; -+ usb-phy = <&usb3phy_utmi>, <&usb3phy_pipe>; -+ phy_type = "utmi_wide"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,xhci-trb-ent-quirk; -+ status = "disabled"; -+ }; -+ }; -+ - gic: interrupt-controller@ff811000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 16 Nov 2020 15:17:36 +0000 -Subject: [PATCH] arm64: dts: rockchip: enable usb3 on rk3328-roc-cc board - -Enable the usb3 controller and usb3 phy nodes on the rk3328-roc-cc board file. - -Signed-off-by: Peter Geis ---- - .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 21 +++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 19959bfba451..3ac876c08d61 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -366,6 +366,27 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -+ -+&usb3phy_utmi { -+ status = "okay"; -+}; -+ -+&usb3phy_pipe { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 17 Feb 2019 22:14:38 +0000 diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch index 58fc60ada5..b49f6b9dc8 100644 --- a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch @@ -1,79 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 16 Jan 2021 12:24:58 +0000 -Subject: [PATCH] arm64: dts: rockchip: enable USB3 for supported RK3328 boards - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 21 +++++++++++++++++++ - .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 21 +++++++++++++++++++ - 2 files changed, 42 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 37f307cfa4cc..4013f16bb368 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -352,6 +352,27 @@ &usb_host0_ehci { - status = "okay"; - }; - -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -+ -+&usb3phy_utmi { -+ status = "okay"; -+}; -+ -+&usb3phy_pipe { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index c984662043da..89fde87f7650 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -384,6 +384,27 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -+ -+&usb3phy_utmi { -+ status = "okay"; -+}; -+ -+&usb3phy_pipe { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Wed, 2 Sep 2020 19:52:02 +0200 From 462357d67bb9edc40026ad11007ed97cc1b18602 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Thu, 24 Jun 2021 12:46:29 +0000 Subject: [PATCH 05/51] linux (Samsung): add config option NVME_TCP is not set --- projects/Samsung/linux/linux.arm.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf index 6bd6f3c5db..3ffbd23343 100644 --- a/projects/Samsung/linux/linux.arm.conf +++ b/projects/Samsung/linux/linux.arm.conf @@ -1125,6 +1125,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # NVME Support # # CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set # CONFIG_NVME_TARGET is not set # end of NVME Support From 48bb4fa14195aebed7052aec9d09c7cf3e2c1d44 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Thu, 24 Jun 2021 12:47:04 +0000 Subject: [PATCH 06/51] linux (Qualcomm): add config option NVME_TCP is not set --- projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index c38c3de71c..d0fdd38d0f 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -1643,6 +1643,7 @@ CONFIG_VIRTIO_BLK=y # # CONFIG_BLK_DEV_NVME is not set # CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set # CONFIG_NVME_TARGET is not set # end of NVME Support From dd38fd1857f38610b82dae6b325e1912577ec76c Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 13:52:45 +0000 Subject: [PATCH 07/51] linux (Allwinner): add config option BATTERY_RT5033 is not set --- projects/Allwinner/linux/linux.aarch64.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index 50451cee6a..ff03df8d47 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.44 Kernel Configuration +# Linux/arm64 5.10.52 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103" CONFIG_CC_IS_GCC=y @@ -2714,6 +2714,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set From 25eb8a928a8a560a764d2936d54798bc70dc76d0 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 13:54:21 +0000 Subject: [PATCH 08/51] linux (Allwinner arm): add config option BATTERY_RT5033 is not set --- projects/Allwinner/linux/linux.arm.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index 1a6c78a78c..ca7b2b741c 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.50 Kernel Configuration +# Linux/arm 5.10.52 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0" CONFIG_CC_IS_GCC=y @@ -2448,6 +2448,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set From 970443c9122bfdaa1c25c585db2c644aa7581e51 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 13:56:23 +0000 Subject: [PATCH 09/51] linux (NXP iMX6): add config option BATTERY_RT5033 is not set --- projects/NXP/devices/iMX6/linux/linux.arm.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/NXP/devices/iMX6/linux/linux.arm.conf b/projects/NXP/devices/iMX6/linux/linux.arm.conf index 6de553f32b..0782954303 100644 --- a/projects/NXP/devices/iMX6/linux/linux.arm.conf +++ b/projects/NXP/devices/iMX6/linux/linux.arm.conf @@ -2707,6 +2707,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set CONFIG_CHARGER_UCS1002=y # CONFIG_CHARGER_BD99954 is not set From 94dfcd893449c2959cbe8591f805c3450b0bcd61 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 13:57:25 +0000 Subject: [PATCH 10/51] linux (Qualcomm): add config option BATTERY_RT5033 is not set --- projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index d0fdd38d0f..cfc725b658 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -2976,6 +2976,7 @@ CONFIG_BATTERY_BQ27XXX_I2C=y # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_UCS1002 is not set From 9555e63561c5f318407b4f80096d497fd5960bc4 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 13:58:19 +0000 Subject: [PATCH 11/51] linux (Rockchip RK3288): add config option BATTERY_RT5033 is not set --- projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index e1741d6606..fdee34267f 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.44 Kernel Configuration +# Linux/arm 5.10.52 Kernel Configuration # # @@ -2263,6 +2263,7 @@ CONFIG_BATTERY_CPCAP=y # CONFIG_CHARGER_TPS65090 is not set # CONFIG_CHARGER_TPS65217 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_UCS1002 is not set From 25cd95e54fdf39f22c8ff0cfe8a03c601a8db1b3 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 13:58:47 +0000 Subject: [PATCH 12/51] linux (Rockchip RK3328): add config option BATTERY_RT5033 is not set --- .../Rockchip/devices/RK3328/linux/default/linux.aarch64.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf index 7d9c813f37..663f8bb4e8 100644 --- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.44 Kernel Configuration +# Linux/arm64 5.10.52 Kernel Configuration # # @@ -2437,6 +2437,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set From 5a50ccaf89723f8b05128bbdd7511d67ea78d255 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 13:59:28 +0000 Subject: [PATCH 13/51] linux (Rockchip RK3399): add config option BATTERY_RT5033 is not set --- .../Rockchip/devices/RK3399/linux/default/linux.aarch64.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index 43df4b3bf4..b170219168 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.41 Kernel Configuration +# Linux/arm64 5.10.52 Kernel Configuration # # @@ -2865,6 +2865,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set From ac77a354f43a2613c5236286362a6852c844d201 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 14:00:25 +0000 Subject: [PATCH 14/51] linux (Samsung): add config option BATTERY_RT5033 is not set --- projects/Samsung/linux/linux.arm.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf index 3ffbd23343..261197fdd3 100644 --- a/projects/Samsung/linux/linux.arm.conf +++ b/projects/Samsung/linux/linux.arm.conf @@ -2067,6 +2067,7 @@ CONFIG_CHARGER_MAX8998=y # CONFIG_CHARGER_SMB347 is not set CONFIG_CHARGER_TPS65090=y # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set CONFIG_HWMON=y From 3e4a08d3b7d578bfaa5048148fa53ae2964f5ca7 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 20:43:24 +0000 Subject: [PATCH 15/51] linux (Allwinner): patches upstreamed in 5.10.52 --- ...-orangepi-plus-Fix-ethernet-phy-mode.patch | 41 ------------------- 1 file changed, 41 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0061-ARM-dts-sun8i-h3-orangepi-plus-Fix-ethernet-phy-mode.patch diff --git a/projects/Allwinner/patches/linux/0061-ARM-dts-sun8i-h3-orangepi-plus-Fix-ethernet-phy-mode.patch b/projects/Allwinner/patches/linux/0061-ARM-dts-sun8i-h3-orangepi-plus-Fix-ethernet-phy-mode.patch deleted file mode 100644 index 58a4b73884..0000000000 --- a/projects/Allwinner/patches/linux/0061-ARM-dts-sun8i-h3-orangepi-plus-Fix-ethernet-phy-mode.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b19d3479f25e8a0ff24df0b46c82e50ef0f900dd Mon Sep 17 00:00:00 2001 -From: Salvatore Bonaccorso -Date: Mon, 24 May 2021 14:21:11 +0200 -Subject: [PATCH] ARM: dts: sun8i: h3: orangepi-plus: Fix ethernet phy-mode - -Commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay -config") sets the RX/TX delay according to the phy-mode property in the -device tree. For the Orange Pi Plus board this is "rgmii", which is the -wrong setting. - -Following the example of a900cac3750b ("ARM: dts: sun7i: a20: bananapro: -Fix ethernet phy-mode") the phy-mode is changed to "rgmii-id" which gets -the Ethernet working again on this board. - -Fixes: bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config") -Reported-by: "B.R. Oake" -Reported-by: Vagrant Cascadian -Link: https://bugs.debian.org/988574 -Signed-off-by: Salvatore Bonaccorso -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/20210524122111.416885-1-carnil@debian.org ---- - arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -index 97f497854e05..d05fa679dcd3 100644 ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts -@@ -85,7 +85,7 @@ &emac { - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; -- phy-mode = "rgmii"; -+ phy-mode = "rgmii-id"; - - status = "okay"; - }; --- -2.31.1 - From 2572c0a15b20576e2d4cdaf6353f89490f412432 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 20:44:07 +0000 Subject: [PATCH 16/51] linux (Rockchip): patches upstreamed in 5.10.52 --- .../default/linux-1003-for-libreelec.patch | 53 ------------------- 1 file changed, 53 deletions(-) diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch index b49f6b9dc8..526a43e8ba 100644 --- a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch @@ -753,33 +753,6 @@ index fb7599f07af4..155f22b53103 100644 mmc-hs400-enhanced-strobe; non-removable; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Tue, 1 Jun 2021 19:37:07 +0200 -Subject: [PATCH] arm64: dts: rockchip: re-add regulator-always-on for vdd_vpu - -Seems to be required by panfrost. - -Fixes: ec7d731d81e7 ("arm64: dts: rockchip: Add node for gpu on rk3399-roc-pc") -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -index 20309076dbac..e4345e5bdfb6 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -@@ -488,6 +488,8 @@ vdd_gpu: regulator@41 { - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 1 Jun 2021 19:42:31 +0200 @@ -910,29 +883,3 @@ index 7257494d2831..9e2994e27d05 100644 }; sdio-pwrseq { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 4 Jun 2021 22:19:32 +0200 -Subject: [PATCH] arm64: dts: rockchip: Re-add regulator-always-on property for - vcc_sdio for RK3399-ROC-PC - -Otherwise the board is not able to reboot. - -Fixes: 04a0077fdb19 ("arm64: dts: rockchip: Remove always-on properties from regulator nodes on rk3399-roc-pc.") -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -index e4345e5bdfb6..03f2dcff8490 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi -@@ -385,6 +385,7 @@ regulator-state-mem { - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-boot-on; -+ regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { From 78fa7be88c11c1d695634c1e9419739c2091cb4e Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 21 Jul 2021 20:49:33 +0000 Subject: [PATCH 17/51] linux (NXP iMX8): add config option BATTERY_RT5033 is not set --- projects/NXP/devices/iMX8/linux/linux.aarch64.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf index c9d0ea5638..841497b4de 100644 --- a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf +++ b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf @@ -2552,6 +2552,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_UCS1002 is not set From 49e32bbf19119f529d8540b6c0659c3a5f56c928 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 23 Jul 2021 12:07:41 +0000 Subject: [PATCH 18/51] linux (Allwinner arm): add config option CONFIG_ARM_SCMI_PROTOCOL is not set --- projects/Allwinner/linux/linux.arm.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index ca7b2b741c..9e8fbbe979 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.52 Kernel Configuration +# Linux/arm 5.10.53 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0" CONFIG_CC_IS_GCC=y @@ -581,6 +581,7 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y # # Firmware Drivers # +# CONFIG_ARM_SCMI_PROTOCOL is not set # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_FW_CFG_SYSFS is not set # CONFIG_TRUSTED_FOUNDATIONS is not set From abbe6a4335692ec0b7c7acda5f88cf07baf2799a Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 23 Jul 2021 12:09:01 +0000 Subject: [PATCH 19/51] linux (NXP iMX6): add config option CONFIG_ARM_SCMI_PROTOCOL is not set --- projects/NXP/devices/iMX6/linux/linux.arm.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/NXP/devices/iMX6/linux/linux.arm.conf b/projects/NXP/devices/iMX6/linux/linux.arm.conf index 0782954303..ce8d282bd6 100644 --- a/projects/NXP/devices/iMX6/linux/linux.arm.conf +++ b/projects/NXP/devices/iMX6/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.47 Kernel Configuration +# Linux/arm 5.10.53 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0" CONFIG_CC_IS_GCC=y @@ -616,6 +616,7 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y # # Firmware Drivers # +# CONFIG_ARM_SCMI_PROTOCOL is not set # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_FW_CFG_SYSFS is not set # CONFIG_TRUSTED_FOUNDATIONS is not set From 73fb454e86849190f9e81a9518af7c6ba3153de6 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 23 Jul 2021 12:10:17 +0000 Subject: [PATCH 20/51] linux (NXP iMX8): add config option CONFIG_BTRFS_FS_POSIX_ACL=y --- projects/NXP/devices/iMX8/linux/linux.aarch64.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf index 841497b4de..baeaf98cb2 100644 --- a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf +++ b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.44 Kernel Configuration +# Linux/arm64 5.10.53 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103" CONFIG_CC_IS_GCC=y @@ -5594,7 +5594,7 @@ CONFIG_XFS_SUPPORT_V4=y # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m -# CONFIG_BTRFS_FS_POSIX_ACL is not set +CONFIG_BTRFS_FS_POSIX_ACL=y # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set From 8f05de8995880f83a2797900b0bb8044053bdff5 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 23 Jul 2021 12:12:01 +0000 Subject: [PATCH 21/51] linux (Generic): add config option BATTERY_RT5033 is not set --- projects/Generic/linux/linux.x86_64.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index 5d22b48592..ee6b35ddda 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.10.20 Kernel Configuration +# Linux/x86 5.10.53 Kernel Configuration # CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.2.0 (GCC) 10.2.0" CONFIG_CC_IS_GCC=y @@ -2991,6 +2991,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y From 394de3f9ada1b01b0a5f8e635d0ee2577d01f2a8 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 23 Jul 2021 12:18:13 +0000 Subject: [PATCH 22/51] linux (Rockchip): update RK3328_PD_GPU patch for 5.10.53 --- .../patches/linux/default/linux-1003-for-libreelec.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch index 526a43e8ba..ed11c9bfea 100644 --- a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch @@ -21,11 +21,11 @@ index bd0ec27cf49b..21e32ddb21a0 100644 #address-cells = <1>; #size-cells = <0>; -+ pd_gpu@RK3328_PD_GPU { ++ power-domain@RK3328_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + }; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = ; }; @@ -546,6 +550,11 @@ map0 { From bc5709f5817410bc90776c1be0cd3a2c1acfcc0f Mon Sep 17 00:00:00 2001 From: heitbaum Date: Wed, 28 Jul 2021 20:00:37 +1000 Subject: [PATCH 23/51] linux (Generic): add config option ACPI_TABLE_OVERRIDE_VIA_BUILTIN_INITRD is not set --- projects/Generic/linux/linux.x86_64.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index ee6b35ddda..84c0efd90e 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.10.53 Kernel Configuration +# Linux/x86 5.10.54 Kernel Configuration # CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.2.0 (GCC) 10.2.0" CONFIG_CC_IS_GCC=y @@ -511,6 +511,7 @@ CONFIG_ACPI_PROCESSOR_AGGREGATOR=y CONFIG_ACPI_THERMAL=y CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_TABLE_OVERRIDE_VIA_BUILTIN_INITRD is not set # CONFIG_ACPI_DEBUG is not set # CONFIG_ACPI_PCI_SLOT is not set CONFIG_ACPI_CONTAINER=y From 5ba329e46c610a127a377f2d9801058a06276489 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sat, 31 Jul 2021 12:27:26 +1000 Subject: [PATCH 24/51] linux (iMX8): fix drm-bridge-mhdp patch for 5.10.55 --- ...p-Add-cdns-mhdp-driver-bridge-driver.patch | 45 +++++++++---------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch index c3ab38d336..855403f61a 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch @@ -3695,9 +3695,9 @@ index a4a45daf93f2..058bc372f02b 100644 if (ret) { - DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); + DRM_DEV_ERROR(dev, "Could not write to GRF: %d\n", ret); + clk_disable_unprepare(dp->grf_clk); return ret; } - @@ -83,24 +83,25 @@ static int cdn_dp_grf_write(struct cdn_dp_device *dp, static int cdn_dp_clk_enable(struct cdn_dp_device *dp) @@ -5156,7 +5156,7 @@ index 9d2163ef4d6e..000000000000 - */ - do { - tu_size_reg += 2; -- symbol = tu_size_reg * mode->clock * bit_per_pix; +- symbol = (u64)tu_size_reg * mode->clock * bit_per_pix; - do_div(symbol, dp->max_lanes * link_rate * 8); - rem = do_div(symbol, 1000); - if (tu_size_reg > 64) { @@ -5648,26 +5648,6 @@ index 441248b7a79e..d76716d4edc6 100644 }; -void cdn_dp_clock_reset(struct cdn_dp_device *dp); -- --void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk); --int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem, -- u32 i_size, const u32 *d_mem, u32 d_size); --int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable); --int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip); --int cdn_dp_event_config(struct cdn_dp_device *dp); --u32 cdn_dp_get_event(struct cdn_dp_device *dp); --int cdn_dp_get_hpd_status(struct cdn_dp_device *dp); --int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value); --int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len); --int cdn_dp_get_edid_block(void *dp, u8 *edid, -- unsigned int block, size_t length); --int cdn_dp_train_link(struct cdn_dp_device *dp); --int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active); --int cdn_dp_config_video(struct cdn_dp_device *dp); --int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio); --int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable); --int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio); --#endif /* _CDN_DP_REG_H */ +enum audio_format { + AFMT_I2S = 0, + AFMT_SPDIF_INT = 1, @@ -5924,7 +5904,26 @@ index 441248b7a79e..d76716d4edc6 100644 +int cdns_mhdp_register_cec_driver(struct device *dev); +int cdns_mhdp_unregister_cec_driver(struct device *dev); +#endif -+ + +-void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk); +-int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem, +- u32 i_size, const u32 *d_mem, u32 d_size); +-int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable); +-int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip); +-int cdn_dp_event_config(struct cdn_dp_device *dp); +-u32 cdn_dp_get_event(struct cdn_dp_device *dp); +-int cdn_dp_get_hpd_status(struct cdn_dp_device *dp); +-int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value); +-int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len); +-int cdn_dp_get_edid_block(void *dp, u8 *edid, +- unsigned int block, size_t length); +-int cdn_dp_train_link(struct cdn_dp_device *dp); +-int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active); +-int cdn_dp_config_video(struct cdn_dp_device *dp); +-int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio); +-int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable); +-int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio); +-#endif /* _CDN_DP_REG_H */ +#endif /* CDNS_MHDP_H_ */ -- 2.29.2 From 5ca0186ba7d6dfd92db45b08fbafae5ded912dd9 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Mon, 19 Jul 2021 12:13:00 +0000 Subject: [PATCH 25/51] linux: update to 5.10.61 --- packages/linux/package.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/linux/package.mk b/packages/linux/package.mk index d8e63753d1..30829f5333 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -28,8 +28,8 @@ case "${LINUX}" in PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" ;; *) - PKG_VERSION="5.10.47" - PKG_SHA256="30b52a2fe6d1e0c1e1dc651d5df9a37eb54b35ea1f7f51b9f23d8903c29ae1c5" + PKG_VERSION="5.10.61" + PKG_SHA256="82eae38cc5cd11dd6aaac91c02ff0d006c7bafd6d4cf5c6a791930820a3a91d1" PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" PKG_PATCH_DIRS="default" ;; From 4f688cbb13d746b30f118c8b0632efd26d5b104a Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 21 Feb 2021 14:13:35 +0000 Subject: [PATCH 26/51] linux (Samsung): update linux.arm.conf for 5.10.20 --- projects/Samsung/linux/linux.arm.conf | 476 +++++++++++++++----------- 1 file changed, 273 insertions(+), 203 deletions(-) diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf index 261197fdd3..91c83777fb 100644 --- a/projects/Samsung/linux/linux.arm.conf +++ b/projects/Samsung/linux/linux.arm.conf @@ -1,16 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.17 Kernel Configuration -# - -# -# Compiler: armv7ve-libreelec-linux-gnueabihf-gcc-10.1.0 (GCC) 10.1.0 +# Linux/arm 5.10.20 Kernel Configuration +# Compiler: armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0 # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=100100 -CONFIG_LD_VERSION=234000000 +CONFIG_GCC_VERSION=100200 +CONFIG_LD_VERSION=236010000 CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y @@ -34,11 +33,13 @@ CONFIG_HAVE_KERNEL_LZ4=y # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set CONFIG_KERNEL_LZ4=y +CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="@DISTRONAME@" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set +# CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set # CONFIG_AUDIT is not set @@ -53,9 +54,9 @@ CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y @@ -92,7 +93,7 @@ CONFIG_PREEMPTION=y CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set -# CONFIG_SCHED_THERMAL_PRESSURE is not set +CONFIG_SCHED_THERMAL_PRESSURE=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_PSI is not set @@ -108,6 +109,7 @@ CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y @@ -157,16 +159,19 @@ CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y # CONFIG_INITRAMFS_COMPRESSION_GZIP is not set # CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set # CONFIG_INITRAMFS_COMPRESSION_LZMA is not set # CONFIG_INITRAMFS_COMPRESSION_XZ is not set # CONFIG_INITRAMFS_COMPRESSION_LZO is not set # CONFIG_INITRAMFS_COMPRESSION_LZ4 is not set +# CONFIG_INITRAMFS_COMPRESSION_ZSTD is not set CONFIG_INITRAMFS_COMPRESSION_NONE=y # CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_BPF=y @@ -198,6 +203,7 @@ CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_BPF_SYSCALL is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y @@ -231,7 +237,6 @@ CONFIG_ARM_DMA_USE_IOMMU=y CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y -CONFIG_NO_IOPORT_MAP=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y @@ -302,21 +307,6 @@ CONFIG_SOC_EXYNOS5420=y CONFIG_SOC_EXYNOS5800=y CONFIG_EXYNOS_MCPM=y CONFIG_EXYNOS_CPU_SUSPEND=y -CONFIG_PLAT_SAMSUNG=y - -# -# Samsung Common options -# - -# -# Boot options -# - -# -# Power management -# -# end of Samsung Common options - # CONFIG_ARCH_HIGHBANK is not set # CONFIG_ARCH_HISI is not set # CONFIG_ARCH_MXC is not set @@ -325,6 +315,7 @@ CONFIG_PLAT_SAMSUNG=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MILBEAUT is not set # CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSTARV7 is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_NPCM is not set @@ -342,6 +333,7 @@ CONFIG_PLAT_SAMSUNG=y # CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set +# CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set @@ -469,6 +461,9 @@ CONFIG_ARM_PATCH_IDIV=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y @@ -479,7 +474,6 @@ CONFIG_ARM_MODULE_PLTS=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_SECCOMP=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_XEN is not set @@ -534,7 +528,6 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y -# CONFIG_QORIQ_CPUFREQ is not set # end of CPU Frequency scaling # @@ -601,9 +594,10 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y # # Firmware Drivers # +# CONFIG_FW_CFG_SYSFS is not set # CONFIG_TRUSTED_FOUNDATIONS is not set -CONFIG_HAVE_ARM_SMCCC=y # CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_HAVE_ARM_SMCCC=y # # Tegra firmware driver @@ -627,10 +621,12 @@ CONFIG_CRYPTO_CHACHA20_NEON=y CONFIG_CRYPTO_POLY1305_ARM=y # CONFIG_CRYPTO_NHPOLY1305_NEON is not set CONFIG_CRYPTO_CURVE25519_NEON=y +CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # +CONFIG_SET_FS=y CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set @@ -652,16 +648,16 @@ CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_CLK=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_CC_HAS_STACKPROTECTOR_NONE=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_CONTEXT_TRACKING=y @@ -674,7 +670,6 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y @@ -687,6 +682,7 @@ CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y # # GCOV-based kernel profiling @@ -726,6 +722,7 @@ CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_WBT is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types @@ -789,6 +786,9 @@ CONFIG_COREDUMP=y # # Memory Management options # +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_ARCH_KEEP_MEMBLOCK=y @@ -920,6 +920,7 @@ CONFIG_DNS_RESOLVER=y # CONFIG_HSR is not set # CONFIG_NET_SWITCHDEV is not set # CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y @@ -952,8 +953,9 @@ CONFIG_BT_HIDP=m CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_LEDS=y -# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_MSFTEXT is not set CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set # # Bluetooth device drivers @@ -1100,7 +1102,6 @@ CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_NET=y -CONFIG_OF_MDIO=y CONFIG_OF_RESERVED_MEM=y CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y @@ -1149,6 +1150,7 @@ CONFIG_SRAM=y CONFIG_SRAM_EXEC=y # CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set +# CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set # @@ -1173,13 +1175,6 @@ CONFIG_EEPROM_93CX6=m # CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_ALTERA_STAPL is not set - -# -# Intel MIC & related support -# -# CONFIG_VOP_BUS is not set -# end of Intel MIC & related support - # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_UACCE is not set @@ -1238,6 +1233,7 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_THIN_PROVISIONING is not set # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set # CONFIG_DM_ERA is not set # CONFIG_DM_CLONE is not set # CONFIG_DM_MIRROR is not set @@ -1328,46 +1324,30 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BUS_MUX_GPIO is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set -# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set -# CONFIG_MDIO_HISI_FEMAC is not set -# CONFIG_MDIO_IPQ8064 is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_XPCS is not set CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y # # MII PHY device drivers # -# CONFIG_ADIN_PHY is not set # CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM87XX_PHY is not set # CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set # CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_DP83869_PHY is not set -CONFIG_FIXED_PHY=y # CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_LXT_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MICREL_PHY is not set @@ -1381,12 +1361,42 @@ CONFIG_MICROCHIP_PHY=m # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set # CONFIG_ROCKCHIP_PHY is not set -# CONFIG_SMSC_PHY is not set +CONFIG_SMSC_PHY=y # CONFIG_STE10XP is not set # CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + # CONFIG_PPP is not set # CONFIG_SLIP is not set CONFIG_USB_NET_DRIVERS=y @@ -1502,6 +1512,11 @@ CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x2_COMMON=m CONFIG_MT76x2U=m +# CONFIG_MT7663U is not set +# CONFIG_MT7663S is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m CONFIG_RT2500USB=m @@ -1611,6 +1626,7 @@ CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_BU21013 is not set # CONFIG_TOUCHSCREEN_BU21029 is not set # CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set @@ -1664,16 +1680,15 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_ZFORCE is not set # CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set # CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ATMEL_CAPTOUCH is not set # CONFIG_INPUT_BMA150 is not set # CONFIG_INPUT_E3X0_BUTTON is not set -# CONFIG_INPUT_MSM_VIBRATOR is not set # CONFIG_INPUT_MAX77693_HAPTIC is not set # CONFIG_INPUT_MAX8997_HAPTIC is not set # CONFIG_INPUT_MMA8450 is not set -# CONFIG_INPUT_GP2A is not set # CONFIG_INPUT_GPIO_BEEPER is not set # CONFIG_INPUT_GPIO_DECODER is not set # CONFIG_INPUT_GPIO_VIBRA is not set @@ -1691,6 +1706,7 @@ CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO_ROTARY_ENCODER=m # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -1792,10 +1808,14 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_TRACE_SINK is not set # CONFIG_HVC_DCC is not set # CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_EXYNOS=y +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y # CONFIG_DEVKMEM is not set # CONFIG_RAW_DRIVER is not set @@ -1806,6 +1826,7 @@ CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_I2C_NUVOTON is not set +# CONFIG_TCG_ATMEL is not set # CONFIG_TCG_VTPM_PROXY is not set # CONFIG_TCG_TIS_ST33ZP24_I2C is not set # CONFIG_TCG_TIS_ST33ZP24_SPI is not set @@ -1896,6 +1917,7 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_AXI_SPI_ENGINE is not set CONFIG_SPI_BITBANG=y # CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=y @@ -1910,6 +1932,7 @@ CONFIG_SPI_S3C64XX=y # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set # CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set # # SPI Multiplexer support @@ -1923,6 +1946,7 @@ CONFIG_SPI_S3C64XX=y # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set +CONFIG_SPI_DYNAMIC=y # CONFIG_SPMI is not set # CONFIG_HSI is not set # CONFIG_PPS is not set @@ -1941,22 +1965,28 @@ CONFIG_PINCTRL=y CONFIG_PINMUX=y CONFIG_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_SINGLE is not set # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_OCELOT is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + CONFIG_PINCTRL_SAMSUNG=y CONFIG_PINCTRL_EXYNOS=y CONFIG_PINCTRL_EXYNOS_ARM=y -# CONFIG_PINCTRL_EQUILIBRIUM is not set CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_DEBUG_GPIO=y # CONFIG_GPIO_SYSFS is not set +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y # # Memory mapped GPIO drivers @@ -1990,6 +2020,7 @@ CONFIG_DEBUG_GPIO=y # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_TPIC2810 is not set # end of I2C GPIO expanders @@ -2017,9 +2048,9 @@ CONFIG_GPIO_WM8994=y # # end of USB GPIO expanders +# CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_W1 is not set -# CONFIG_POWER_AVS is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMKONA is not set # CONFIG_POWER_RESET_BRCMSTB is not set @@ -2039,10 +2070,10 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_LEGO_EV3 is not set CONFIG_BATTERY_SBS=y # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set @@ -2063,13 +2094,16 @@ CONFIG_CHARGER_MAX8998=y # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set # CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set CONFIG_CHARGER_TPS65090=y # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2097,6 +2131,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2139,6 +2174,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM70 is not set @@ -2210,6 +2246,7 @@ CONFIG_SENSORS_INA2XX=y # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y @@ -2225,11 +2262,9 @@ CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set CONFIG_CPU_THERMAL=y CONFIG_CPU_FREQ_THERMAL=y -# CONFIG_CLOCK_THERMAL is not set CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y # CONFIG_THERMAL_MMIO is not set -# CONFIG_QORIQ_THERMAL is not set # # Samsung thermal drivers @@ -2260,10 +2295,10 @@ CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_ARM_SP805_WATCHDOG is not set # CONFIG_CADENCE_WATCHDOG is not set # CONFIG_FTWDT010_WATCHDOG is not set -CONFIG_HAVE_S3C2410_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y # CONFIG_DW_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ARM_SMC_WATCHDOG is not set # CONFIG_MEN_A21_WDT is not set # @@ -2309,8 +2344,10 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_DLN2 is not set # CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_GATEWORKS_GSC is not set # CONFIG_MFD_MC13XXX_SPI is not set # CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set @@ -2329,6 +2366,7 @@ CONFIG_MFD_MAX77693=y # CONFIG_MFD_MAX8925 is not set CONFIG_MFD_MAX8997=y CONFIG_MFD_MAX8998=y +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_EZX_PCAP is not set @@ -2345,7 +2383,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y @@ -2390,6 +2427,7 @@ CONFIG_MFD_WM8994=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -2403,6 +2441,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_ISL9305 is not set # CONFIG_REGULATOR_ISL6271A is not set @@ -2423,23 +2462,29 @@ CONFIG_REGULATOR_MAX8998=y CONFIG_REGULATOR_MAX77686=y CONFIG_REGULATOR_MAX77693=y CONFIG_REGULATOR_MAX77802=y +# CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set # CONFIG_REGULATOR_MP8859 is not set # CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RTMV20 is not set CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -2449,34 +2494,56 @@ CONFIG_REGULATOR_TPS65090=y # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set CONFIG_REGULATOR_WM8994=y -CONFIG_CEC_CORE=y -CONFIG_CEC_NOTIFIER=y # CONFIG_RC_CORE is not set +CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_CEC_CH7322 is not set +# CONFIG_CEC_GPIO is not set +# CONFIG_CEC_SAMSUNG_S5P is not set +# CONFIG_USB_PULSE8_CEC is not set +# CONFIG_USB_RAINSHADOW_CEC is not set CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set # -# Multimedia core support +# Media device types # CONFIG_MEDIA_CAMERA_SUPPORT=y # CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set # CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set # CONFIG_MEDIA_RADIO_SUPPORT is not set # CONFIG_MEDIA_SDR_SUPPORT is not set -CONFIG_MEDIA_CEC_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_PLATFORM_SUPPORT is not set +# CONFIG_MEDIA_TEST_SUPPORT is not set +# end of Media device types + CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_CONTROLLER=y + +# +# Video4Linux options +# CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_V4L2_MEM2MEM_DEV=m # CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=m +# end of Video4Linux options + +# +# Media controller options +# +# end of Media controller options # # Media drivers # + +# +# Drivers filtered as selected at 'Filter media drivers' +# CONFIG_MEDIA_USB_SUPPORT=y # @@ -2545,60 +2612,14 @@ CONFIG_USB_GSPCA=m # Webcam, TV (analog/digital) USB devices # # CONFIG_VIDEO_EM28XX is not set - -# -# USB HDMI CEC adapters -# -# CONFIG_USB_PULSE8_CEC is not set -# CONFIG_USB_RAINSHADOW_CEC is not set -CONFIG_V4L_PLATFORM_DRIVERS=y -# CONFIG_VIDEO_CADENCE is not set -# CONFIG_VIDEO_ASPEED is not set -# CONFIG_VIDEO_MUX is not set -CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m -CONFIG_VIDEO_EXYNOS4_IS_COMMON=m -CONFIG_VIDEO_S5P_FIMC=m -CONFIG_VIDEO_S5P_MIPI_CSIS=m -CONFIG_VIDEO_EXYNOS_FIMC_LITE=m -CONFIG_VIDEO_EXYNOS4_FIMC_IS=m -CONFIG_VIDEO_EXYNOS4_ISP_DMA_CAPTURE=y -# CONFIG_VIDEO_XILINX is not set -CONFIG_V4L_MEM2MEM_DRIVERS=y -# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set -# CONFIG_VIDEO_SAMSUNG_S5P_G2D is not set -CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m -CONFIG_VIDEO_SAMSUNG_S5P_MFC=m -CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m -# CONFIG_VIDEO_SH_VEU is not set -CONFIG_V4L_TEST_DRIVERS=y -# CONFIG_VIDEO_VIMC is not set -CONFIG_VIDEO_VIVID=m -# CONFIG_VIDEO_VIVID_CEC is not set -CONFIG_VIDEO_VIVID_MAX_DEVS=64 -# CONFIG_VIDEO_VIM2M is not set -# CONFIG_VIDEO_VICODEC is not set -CONFIG_CEC_PLATFORM_DRIVERS=y -# CONFIG_CEC_GPIO is not set -CONFIG_VIDEO_SAMSUNG_S5P_CEC=m - -# -# Supported MMC/SDIO adapters -# -# CONFIG_CYPRESS_FIRMWARE is not set CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m CONFIG_VIDEOBUF2_MEMOPS=m -CONFIG_VIDEOBUF2_DMA_CONTIG=m CONFIG_VIDEOBUF2_VMALLOC=m -CONFIG_VIDEO_V4L2_TPG=m +# end of Media drivers # -# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) -# -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set - -# -# I2C Encoders, decoders, sensors and other helper chips +# Media ancillary drivers # # @@ -2620,11 +2641,13 @@ CONFIG_VIDEO_V4L2_TPG=m # CONFIG_VIDEO_WM8739 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers # # RDS decoders # # CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders # # Video decoders @@ -2650,12 +2673,14 @@ CONFIG_VIDEO_V4L2_TPG=m # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set # CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_MAX9286 is not set # # Video and audio decoders # # CONFIG_VIDEO_SAA717X is not set # CONFIG_VIDEO_CX25840 is not set +# end of Video decoders # # Video encoders @@ -2670,6 +2695,34 @@ CONFIG_VIDEO_V4L2_TPG=m # CONFIG_VIDEO_AD9389B is not set # CONFIG_VIDEO_AK881X is not set # CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips # # Camera sensor devices @@ -2715,6 +2768,7 @@ CONFIG_VIDEO_V4L2_TPG=m # CONFIG_VIDEO_SR030PC30 is not set # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set CONFIG_VIDEO_S5K6A3=m @@ -2723,6 +2777,7 @@ CONFIG_VIDEO_S5K6A3=m # CONFIG_VIDEO_SMIAPP is not set # CONFIG_VIDEO_ET8EK8 is not set CONFIG_VIDEO_S5C73M3=m +# end of Camera sensor devices # # Lens drivers @@ -2730,7 +2785,9 @@ CONFIG_VIDEO_S5C73M3=m # CONFIG_VIDEO_AD5820 is not set # CONFIG_VIDEO_AK7375 is not set # CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set # CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers # # Flash devices @@ -2738,30 +2795,7 @@ CONFIG_VIDEO_S5C73M3=m # CONFIG_VIDEO_ADP1653 is not set # CONFIG_VIDEO_LM3560 is not set # CONFIG_VIDEO_LM3646 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set - -# -# Audio/Video compression chips -# -# CONFIG_VIDEO_SAA6752HS is not set - -# -# SDR tuner chips -# - -# -# Miscellaneous helper chips -# -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_I2C is not set -# CONFIG_VIDEO_ST_MIPID02 is not set -# end of I2C Encoders, decoders, sensors and other helper chips +# end of Flash devices # # SPI helper chips @@ -2773,15 +2807,7 @@ CONFIG_VIDEO_S5C73M3=m # Media SPI Adapters # # end of Media SPI Adapters - -# -# Customise DVB Frontends -# - -# -# Tools to develop new frontends -# -# end of Customise DVB Frontends +# end of Media ancillary drivers # # Graphics support @@ -2844,6 +2870,7 @@ CONFIG_DRM_EXYNOS_HDMI=y # CONFIG_DRM_EXYNOS_FIMC is not set # CONFIG_DRM_EXYNOS_ROTATOR is not set # CONFIG_DRM_EXYNOS_SCALER is not set +# CONFIG_DRM_EXYNOS_GSC is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_RCAR_DW_HDMI is not set @@ -2858,6 +2885,7 @@ CONFIG_DRM_PANEL=y # Display Panels # # CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_LVDS is not set @@ -2870,6 +2898,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set CONFIG_DRM_PANEL_SAMSUNG_LD9040=y # CONFIG_DRM_PANEL_LG_LB035Q02 is not set @@ -2877,6 +2906,7 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set # CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set @@ -2884,7 +2914,6 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set -# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set @@ -2897,6 +2926,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set @@ -2904,6 +2934,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels @@ -2914,9 +2945,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set CONFIG_DRM_NXP_PTN3460=y CONFIG_DRM_PARADE_PS8622=y # CONFIG_DRM_PARADE_PS8640 is not set @@ -2925,9 +2959,11 @@ CONFIG_DRM_PARADE_PS8622=y CONFIG_DRM_SII9234=y # CONFIG_DRM_SIMPLE_BRIDGE is not set # CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set CONFIG_DRM_TOSHIBA_TC358764=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set @@ -2935,6 +2971,7 @@ CONFIG_DRM_TOSHIBA_TC358764=y # CONFIG_DRM_ANALOGIX_ANX78XX is not set CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set # end of Display Interface Bridges # CONFIG_DRM_STI is not set @@ -2953,7 +2990,7 @@ CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_PL111 is not set # CONFIG_DRM_TVE200 is not set # CONFIG_DRM_LIMA is not set -CONFIG_DRM_PANFROST=y +# CONFIG_DRM_PANFROST is not set # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_LEGACY is not set @@ -3010,7 +3047,7 @@ CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_HX8357 is not set # CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_KTD253 is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set @@ -3127,6 +3164,8 @@ CONFIG_SND_SOC_SMDK_WM8994_PCM=y # CONFIG_SND_SOC_SNOW is not set CONFIG_SND_SOC_ODROID=y # CONFIG_SND_SOC_ARNDALE is not set +# CONFIG_SND_SOC_SAMSUNG_ARIES_WM8994 is not set +# CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811 is not set # CONFIG_SND_SOC_SOF_TOPLEVEL is not set # @@ -3173,6 +3212,7 @@ CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_CS42L52 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set # CONFIG_SND_SOC_CS4271_I2C is not set @@ -3199,7 +3239,8 @@ CONFIG_SND_SOC_MAX98090=y # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set -# CONFIG_SND_SOC_MAX98373 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98390 is not set # CONFIG_SND_SOC_MAX9860 is not set # CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set # CONFIG_SND_SOC_PCM1681 is not set @@ -3230,6 +3271,7 @@ CONFIG_SND_SOC_RT5631=y # CONFIG_SND_SOC_STI_SAS is not set # CONFIG_SND_SOC_TAS2552 is not set # CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set @@ -3272,6 +3314,7 @@ CONFIG_SND_SOC_RT5631=y # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set CONFIG_SND_SOC_WM8994=y +# CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set @@ -3329,6 +3372,7 @@ CONFIG_HID_EZKEY=y # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set # CONFIG_HID_KYE is not set @@ -3424,9 +3468,10 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set @@ -3437,6 +3482,7 @@ CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_C67X00_HCD is not set CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_DBGCAP is not set +# CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_ROOT_HUB_TT is not set @@ -3659,6 +3705,7 @@ CONFIG_MMC_DW_EXYNOS=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=y +# CONFIG_LEDS_CLASS_MULTICOLOR is not set # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # @@ -3667,6 +3714,7 @@ CONFIG_LEDS_CLASS_FLASH=y CONFIG_LEDS_AAT1290=y # CONFIG_LEDS_AN30259A is not set # CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set # CONFIG_LEDS_CR0014114 is not set @@ -3680,10 +3728,8 @@ CONFIG_LEDS_AAT1290=y CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3710,6 +3756,7 @@ CONFIG_LEDS_MAX8997=y # CONFIG_LEDS_USER is not set # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_SGM3140 is not set # # LED Triggers @@ -3788,6 +3835,7 @@ CONFIG_RTC_DRV_MAX77686=y # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set CONFIG_RTC_DRV_S5M=y # CONFIG_RTC_DRV_SD3078 is not set @@ -3869,6 +3917,7 @@ CONFIG_DMA_OF=y # CONFIG_INTEL_IDMA64 is not set # CONFIG_NBPFAXI_DMA is not set CONFIG_PL330_DMA=y +# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set @@ -3899,7 +3948,6 @@ CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_VIRT_DRIVERS is not set # CONFIG_VIRTIO_MENU is not set # CONFIG_VDPA is not set -CONFIG_VHOST_DPN=y # CONFIG_VHOST_MENU is not set # @@ -3974,12 +4022,6 @@ CONFIG_VT6656=m # end of Resolver to digital converters # end of IIO staging drivers -# -# Speakup console speech -# -# CONFIG_SPEAKUP is not set -# end of Speakup console speech - # CONFIG_STAGING_MEDIA is not set # @@ -3991,10 +4033,7 @@ CONFIG_VT6656=m # CONFIG_LTE_GDM724X is not set # CONFIG_GS_FPGABOOT is not set # CONFIG_UNISYSSPAR is not set -# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set # CONFIG_FB_TFT is not set -# CONFIG_WILC1000_SDIO is not set -# CONFIG_WILC1000_SPI is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set @@ -4007,17 +4046,12 @@ CONFIG_VT6656=m # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set # CONFIG_GOLDFISH is not set -# CONFIG_MFD_CROS_EC is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# -# CONFIG_CLK_HSDK is not set CONFIG_COMMON_CLK_MAX77686=y # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set @@ -4035,8 +4069,6 @@ CONFIG_COMMON_CLK_S2MPS11=y # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_COMMON_CLK_SAMSUNG=y CONFIG_EXYNOS_AUDSS_CLK_CON=y -# end of Common Clock Framework - # CONFIG_HWSPINLOCK is not set # @@ -4129,6 +4161,7 @@ CONFIG_EXYNOS_CHIPID=y CONFIG_EXYNOS_PMU=y CONFIG_EXYNOS_PMU_ARM_DRIVERS=y CONFIG_EXYNOS_PM_DOMAINS=y +CONFIG_EXYNOS_REGULATOR_COUPLER=y # CONFIG_SOC_TI is not set # @@ -4182,6 +4215,8 @@ CONFIG_EXYNOS_SROM=y CONFIG_IIO=y CONFIG_IIO_BUFFER=y # CONFIG_IIO_BUFFER_CB is not set +# CONFIG_IIO_BUFFER_DMA is not set +# CONFIG_IIO_BUFFER_DMAENGINE is not set # CONFIG_IIO_BUFFER_HW_CONSUMER is not set CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y @@ -4190,6 +4225,7 @@ CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IIO_SW_DEVICE is not set # CONFIG_IIO_SW_TRIGGER is not set +# CONFIG_IIO_TRIGGERED_EVENT is not set # # Accelerometers @@ -4248,6 +4284,8 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set +# CONFIG_AD9467 is not set +# CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EXYNOS_ADC=y @@ -4260,6 +4298,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set # CONFIG_MCP320X is not set @@ -4301,9 +4340,11 @@ CONFIG_EXYNOS_ADC=y # Chemical Sensors # # CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATLAS_EZO_SENSOR is not set # CONFIG_BME680 is not set # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set +# CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set # CONFIG_SPS30 is not set # CONFIG_VZ89X is not set @@ -4389,6 +4430,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_ADIS16130 is not set # CONFIG_ADIS16136 is not set # CONFIG_ADIS16260 is not set +# CONFIG_ADXRS290 is not set # CONFIG_ADXRS450 is not set # CONFIG_BMG160 is not set # CONFIG_FXAS21002C is not set @@ -4417,6 +4459,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_AM2315 is not set # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set +# CONFIG_HDC2010 is not set # CONFIG_HTS221 is not set # CONFIG_HTU21 is not set # CONFIG_SI7005 is not set @@ -4428,12 +4471,15 @@ CONFIG_EXYNOS_ADC=y # # CONFIG_ADIS16400 is not set # CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set # CONFIG_FXOS8700_I2C is not set # CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set +# CONFIG_INV_ICM42600_I2C is not set +# CONFIG_INV_ICM42600_SPI is not set # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set @@ -4448,6 +4494,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set +# CONFIG_AS73211 is not set # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set # CONFIG_CM32181 is not set @@ -4584,8 +4631,10 @@ CONFIG_AK8975=y # CONFIG_PING is not set # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set +# CONFIG_SX9310 is not set # CONFIG_SX9500 is not set # CONFIG_SRF08 is not set +# CONFIG_VCNL3020 is not set # CONFIG_VL53L0X_I2C is not set # end of Proximity and distance sensors @@ -4638,6 +4687,7 @@ CONFIG_GENERIC_PHY=y # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -4648,13 +4698,13 @@ CONFIG_GENERIC_PHY=y CONFIG_PHY_EXYNOS_DP_VIDEO=y CONFIG_PHY_EXYNOS_MIPI_VIDEO=y # CONFIG_PHY_EXYNOS_PCIE is not set +# CONFIG_PHY_SAMSUNG_UFS is not set CONFIG_PHY_SAMSUNG_USB2=y CONFIG_PHY_EXYNOS4210_USB2=y CONFIG_PHY_EXYNOS4X12_USB2=y CONFIG_PHY_EXYNOS5250_USB2=y CONFIG_PHY_EXYNOS5_USBDRD=y CONFIG_PHY_EXYNOS5250_SATA=y -# CONFIG_PHY_INTEL_EMMC is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -4724,6 +4774,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set # CONFIG_XFS_RT is not set @@ -4875,6 +4926,7 @@ CONFIG_NFS_FSCACHE=y # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set # CONFIG_NFSD is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -4963,7 +5015,7 @@ CONFIG_KEYS=y # CONFIG_BIG_KEYS is not set # CONFIG_TRUSTED_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set +CONFIG_KEY_DH_OPERATIONS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set CONFIG_SECURITYFS=y @@ -5011,7 +5063,7 @@ CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_KPP=m +CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y @@ -5030,10 +5082,11 @@ CONFIG_CRYPTO_SIMD=m # Public-key cryptography # CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set # @@ -5088,7 +5141,7 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m @@ -5108,7 +5161,7 @@ CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set +CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set CONFIG_CRYPTO_SALSA20=m @@ -5139,11 +5192,13 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_USER_API=m -CONFIG_CRYPTO_USER_API_HASH=m -CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # CONFIG_CRYPTO_STATS is not set CONFIG_CRYPTO_HASH_INFO=y @@ -5176,7 +5231,7 @@ CONFIG_CRYPTO_DEV_S5P=y CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y -# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y # CONFIG_PKCS7_TEST_KEY is not set # CONFIG_SIGNED_PE_FILE_VERIFICATION is not set @@ -5198,6 +5253,7 @@ CONFIG_BINARY_PRINTF=y # CONFIG_RAID6_PQ=m # CONFIG_RAID6_PQ_BENCHMARK is not set +CONFIG_LINEAR_RANGES=y # CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y @@ -5205,6 +5261,7 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y @@ -5248,10 +5305,13 @@ CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y @@ -5260,6 +5320,7 @@ CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_REMAP=y CONFIG_DMA_CMA=y +# CONFIG_DMA_PERNUMA_CMA is not set # # Default contiguous memory area size: @@ -5299,6 +5360,7 @@ CONFIG_FONT_7x14=y # CONFIG_FONT_SUN8x16 is not set # CONFIG_FONT_SUN12x22 is not set # CONFIG_FONT_TER16x32 is not set +# CONFIG_FONT_6x8 is not set CONFIG_SG_POOL=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set @@ -5318,6 +5380,7 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options @@ -5327,6 +5390,7 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_BTF is not set @@ -5349,6 +5413,9 @@ CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_UBSAN is not set @@ -5366,6 +5433,7 @@ CONFIG_DEBUG_MISC=y # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set @@ -5380,7 +5448,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_KASAN_STACK=1 +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -5429,6 +5497,7 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y @@ -5452,8 +5521,9 @@ CONFIG_STACKTRACE=y # RCU Debugging # CONFIG_PROVE_RCU=y -# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_TRACE=y # CONFIG_RCU_EQS_DEBUG is not set @@ -5482,7 +5552,6 @@ CONFIG_FTRACE=y # CONFIG_BOOTTIME_TRACING is not set # CONFIG_FUNCTION_TRACER is not set # CONFIG_STACK_TRACER is not set -# CONFIG_PREEMPTIRQ_EVENTS is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set @@ -5497,6 +5566,7 @@ CONFIG_BRANCH_PROFILE_NONE=y CONFIG_UPROBE_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y +# CONFIG_SYNTH_EVENTS is not set # CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set @@ -5511,7 +5581,6 @@ CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # arm Debugging # # CONFIG_ARM_PTDUMP_DEBUGFS is not set -# CONFIG_DEBUG_WX is not set # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y @@ -5549,7 +5618,6 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set # CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_BITFIELD is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set @@ -5557,6 +5625,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_HASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set # CONFIG_TEST_VMALLOC is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set @@ -5570,6 +5639,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MEMCAT_P is not set # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking From 58f8cd7c81d898f7fa33e012d647dc5462a96c09 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 30 Jul 2021 22:02:29 +1000 Subject: [PATCH 27/51] linux (Qualcomm): update linux.arm.conf for 5.10.20 --- .../Dragonboard/linux/linux.aarch64.conf | 1185 +++++++++++------ 1 file changed, 811 insertions(+), 374 deletions(-) diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index cfc725b658..7911b1b7f9 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -1,18 +1,22 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.17 Kernel Configuration +# Linux/arm64 5.10.20 Kernel Configuration # # -# Compiler: gcc (GCC) 8.2.1 20181215 (Red Hat 8.2.1-6) +# Compiler: aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103" # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=80201 +CONFIG_GCC_VERSION=100201 +CONFIG_LD_VERSION=235010000 CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # @@ -23,12 +27,14 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="@DISTRONAME@" # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set CONFIG_AUDIT=y @@ -44,9 +50,10 @@ CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_IRQ_MSI_IOMMU=y @@ -57,7 +64,6 @@ CONFIG_SPARSE_IRQ=y # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -79,6 +85,7 @@ CONFIG_HIGH_RES_TIMERS=y # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting @@ -86,6 +93,7 @@ CONFIG_PREEMPT_COUNT=y CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_SCHED_THERMAL_PRESSURE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y @@ -100,10 +108,12 @@ CONFIG_CPU_ISOLATION=y # # RCU Subsystem # +CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y @@ -116,14 +126,20 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y -# CONFIG_DEBUG_BLK_CGROUP is not set CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y @@ -142,6 +158,7 @@ CONFIG_CGROUP_PERF=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y +CONFIG_TIME_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y @@ -160,11 +177,14 @@ CONFIG_RD_GZIP=y # CONFIG_RD_XZ is not set # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set -# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_RD_ZSTD=y CONFIG_INITRAMFS_COMPRESSION_GZIP=y -CONFIG_INITRAMFS_COMPRESSION=".gz" +# CONFIG_INITRAMFS_COMPRESSION_ZSTD is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y @@ -182,6 +202,7 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -195,8 +216,11 @@ CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_BPF_SYSCALL is not set +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +CONFIG_BPF_JIT_DEFAULT_ON=y # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y @@ -226,7 +250,8 @@ CONFIG_ARM64=y CONFIG_64BIT=y CONFIG_MMU=y CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARM64_CONT_PTE_SHIFT=4 +CONFIG_ARM64_CONT_PMD_SHIFT=4 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=33 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 @@ -240,9 +265,10 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y -CONFIG_HAVE_GENERIC_GUP=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -263,10 +289,12 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set # CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set # CONFIG_ARCH_K3 is not set # CONFIG_ARCH_LAYERSCAPE is not set # CONFIG_ARCH_LG1K is not set # CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set # CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set @@ -275,6 +303,7 @@ CONFIG_ARCH_QCOM=y # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_STRATIX10 is not set # CONFIG_ARCH_SYNQUACER is not set @@ -284,6 +313,7 @@ CONFIG_ARCH_QCOM=y # CONFIG_ARCH_THUNDER2 is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set # CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set @@ -306,21 +336,27 @@ CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y CONFIG_ARM64_ERRATUM_1024718=y CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y CONFIG_ARM64_ERRATUM_1286807=y CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_1508412=y CONFIG_CAVIUM_ERRATUM_22375=y CONFIG_CAVIUM_ERRATUM_23154=y CONFIG_CAVIUM_ERRATUM_27456=y CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_HISILICON_ERRATUM_161600802=y CONFIG_QCOM_FALKOR_ERRATUM_1003=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y CONFIG_QCOM_FALKOR_ERRATUM_1009=y CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_SOCIONEXT_SYNQUACER_PREITS=y -CONFIG_HISILICON_ERRATUM_161600802=y CONFIG_QCOM_FALKOR_ERRATUM_E1041=y -CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y # end of ARM errata workarounds via the alternatives framework CONFIG_ARM64_4K_PAGES=y @@ -332,6 +368,7 @@ CONFIG_ARM64_VA_BITS=48 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PA_BITS=48 # CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SCHED_MC=y # CONFIG_SCHED_SMT is not set CONFIG_NR_CPUS=64 @@ -355,7 +392,6 @@ CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_SECCOMP=y CONFIG_PARAVIRT=y # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_KEXEC=y @@ -365,11 +401,9 @@ CONFIG_XEN_DOM0=y CONFIG_XEN=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDEN_EL2_VECTORS=y -CONFIG_ARM64_SSBD=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y # CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_COMPAT=y CONFIG_KUSER_HELPERS=y CONFIG_ARMV8_DEPRECATED=y @@ -382,7 +416,8 @@ CONFIG_SETEND_EMULATION=y # CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y -# CONFIG_ARM64_LSE_ATOMICS is not set +CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM64_VHE=y # end of ARMv8.1 architectural features @@ -399,11 +434,39 @@ CONFIG_ARM64_CNP=y # ARMv8.3 architectural features # CONFIG_ARM64_PTR_AUTH=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y +CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # end of ARMv8.3 architectural features +# +# ARMv8.4 architectural features +# +CONFIG_ARM64_AMU_EXTN=y +CONFIG_AS_HAS_ARMV8_4=y +CONFIG_ARM64_TLB_RANGE=y +# end of ARMv8.4 architectural features + +# +# ARMv8.5 architectural features +# +CONFIG_ARM64_BTI=y +CONFIG_ARM64_BTI_KERNEL=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y +CONFIG_ARM64_E0PD=y +CONFIG_ARCH_RANDOM=y +CONFIG_ARM64_AS_HAS_MTE=y +CONFIG_ARM64_MTE=y +# end of ARMv8.5 architectural features + CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_STACKPROTECTOR_PER_TASK=y # end of Kernel Features # @@ -411,7 +474,6 @@ CONFIG_ARM64_MODULE_PLTS=y # # CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set CONFIG_CMDLINE="" -# CONFIG_CMDLINE_FORCE is not set CONFIG_EFI_STUB=y CONFIG_EFI=y CONFIG_DMI=y @@ -419,6 +481,7 @@ CONFIG_DMI=y CONFIG_SYSVIPC_COMPAT=y CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management options @@ -460,6 +523,7 @@ CONFIG_DT_IDLE_STATES=y # ARM CPU Idle Drivers # CONFIG_ARM_CPUIDLE=y +# CONFIG_ARM_PSCI_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle @@ -490,9 +554,8 @@ CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y # CONFIG_ACPI_CPPC_CPUFREQ is not set CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_QCOM_CPUFREQ_KRYO=y +# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set CONFIG_ARM_QCOM_CPUFREQ_HW=y -# CONFIG_QORIQ_CPUFREQ is not set # end of CPU Frequency scaling # end of CPU Power Management @@ -508,28 +571,32 @@ CONFIG_DMIID=y # CONFIG_ISCSI_IBFT is not set # CONFIG_FW_CFG_SYSFS is not set CONFIG_QCOM_SCM=y -CONFIG_QCOM_SCM_64=y # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set # CONFIG_GOOGLE_FIRMWARE is not set # # EFI (Extensible Firmware Interface) Support # -# CONFIG_EFI_VARS is not set CONFIG_EFI_ESRT=y CONFIG_EFI_PARAMS_FROM_FDT=y CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_ARMSTUB=y +CONFIG_EFI_GENERIC_STUB=y CONFIG_EFI_ARMSTUB_DTB_LOADER=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set # CONFIG_EFI_CAPSULE_LOADER is not set # CONFIG_EFI_TEST is not set # CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y # # Tegra firmware driver @@ -544,6 +611,8 @@ CONFIG_ACPI_CCA_REQUIRED=y # CONFIG_ACPI_DEBUGGER is not set CONFIG_ACPI_SPCR_TABLE=y # CONFIG_ACPI_EC_DEBUGFS is not set +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y CONFIG_ACPI_FAN=y # CONFIG_ACPI_TAD is not set @@ -564,16 +633,14 @@ CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y CONFIG_HAVE_ACPI_APEI=y # CONFIG_ACPI_APEI is not set -# CONFIG_PMIC_OPREGION is not set # CONFIG_ACPI_CONFIGFS is not set CONFIG_ACPI_IORT=y CONFIG_ACPI_GTDT=y CONFIG_ACPI_PPTT=y +# CONFIG_PMIC_OPREGION is not set CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_VIRTUALIZATION=y # CONFIG_KVM is not set -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA256_ARM64=y # CONFIG_CRYPTO_SHA512_ARM64 is not set @@ -590,7 +657,8 @@ CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y # CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set -# CONFIG_CRYPTO_CHACHA20_NEON is not set +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_POLY1305_NEON=y # CONFIG_CRYPTO_NHPOLY1305_NEON is not set # CONFIG_CRYPTO_AES_ARM64_BS is not set @@ -599,12 +667,14 @@ CONFIG_CRYPTO_AES_ARM64_CE_BLK=y # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y +CONFIG_SET_FS=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y @@ -613,32 +683,36 @@ CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_CLK=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_CC_HAS_STACKPROTECTOR_NONE=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y @@ -648,10 +722,10 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_64BIT_TIME=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y @@ -659,10 +733,12 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_REFCOUNT_FULL=y +CONFIG_HAVE_ARCH_COMPILER_H=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y # # GCOV-based kernel profiling @@ -671,8 +747,10 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling -CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -685,21 +763,27 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set # CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set # CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOCOST is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types @@ -732,6 +816,7 @@ CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y @@ -740,6 +825,9 @@ CONFIG_FREEZER=y # CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_HAVE_ELF_PROT=y +CONFIG_ARCH_USE_GNU_PROPERTY=y CONFIG_ELFCORE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_SCRIPT=y @@ -754,10 +842,10 @@ CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y -CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y # CONFIG_MEMORY_HOTPLUG is not set @@ -765,9 +853,11 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y +CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 @@ -776,7 +866,6 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TRANSPARENT_HUGE_PAGECACHE=y # CONFIG_CLEANCACHE is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set @@ -788,9 +877,12 @@ CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_FRAME_VECTOR=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_BENCHMARK is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options @@ -861,6 +953,7 @@ CONFIG_IPV6_SIT=y CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_FOU=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y @@ -868,7 +961,9 @@ CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y CONFIG_IPV6_PIMSM_V2=y # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set # CONFIG_NETLABEL is not set +# CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -922,7 +1017,6 @@ CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -# CONFIG_NF_TABLES_SET is not set # CONFIG_NF_TABLES_INET is not set # CONFIG_NF_TABLES_NETDEV is not set # CONFIG_NFT_NUMGEN is not set @@ -943,6 +1037,7 @@ CONFIG_NF_TABLES=m # CONFIG_NFT_SOCKET is not set # CONFIG_NFT_OSF is not set # CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m @@ -1149,6 +1244,7 @@ CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_DEFRAG_IPV6=m # CONFIG_NF_TABLES_BRIDGE is not set +# CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set @@ -1163,6 +1259,7 @@ CONFIG_MRP=y CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BRIDGE_MRP is not set CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y @@ -1229,6 +1326,7 @@ CONFIG_NET_SCHED=y # CONFIG_NET_SCH_HHF is not set # CONFIG_NET_SCH_PIE is not set # CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set # CONFIG_NET_SCH_DEFAULT is not set # @@ -1296,8 +1394,9 @@ CONFIG_BT_HS=y CONFIG_BT_LE=y # CONFIG_BT_6LOWPAN is not set CONFIG_BT_LEDS=y -# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_MSFTEXT is not set CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set # # Bluetooth device drivers @@ -1309,6 +1408,7 @@ CONFIG_BT_QCA=y CONFIG_BT_HCIBTUSB=y # CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set CONFIG_BT_HCIBTUSB_BCM=y +# CONFIG_BT_HCIBTUSB_MTK is not set CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=y CONFIG_BT_HCIUART=y @@ -1317,7 +1417,6 @@ CONFIG_BT_HCIUART_BCSP=y # CONFIG_BT_HCIUART_ATH3K is not set # CONFIG_BT_HCIUART_INTEL is not set # CONFIG_BT_HCIUART_AG6XX is not set -# CONFIG_BT_HCIUART_MRVL is not set # CONFIG_BT_HCIBCM203X is not set # CONFIG_BT_HCIBPA10X is not set # CONFIG_BT_HCIBFUSB is not set @@ -1374,7 +1473,9 @@ CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # @@ -1391,7 +1492,6 @@ CONFIG_PCIEAER=y # CONFIG_PCIEAER_INJECT is not set # CONFIG_PCIE_ECRC is not set CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set @@ -1418,13 +1518,6 @@ CONFIG_PCI_LABEL=y # # PCI controller drivers # - -# -# Cadence PCIe controllers support -# -# CONFIG_PCIE_CADENCE_HOST is not set -# end of Cadence PCIe controllers support - # CONFIG_PCI_FTPCI100 is not set CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=y @@ -1445,7 +1538,21 @@ CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y # CONFIG_PCIE_KIRIN is not set # CONFIG_PCI_MESON is not set +# CONFIG_PCIE_AL is not set # end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence PCIe controllers support # end of PCI controller drivers # @@ -1479,6 +1586,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -1491,6 +1600,7 @@ CONFIG_DEV_COREDUMP=y CONFIG_SYS_HYPERVISOR=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPI=y @@ -1506,22 +1616,24 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # Bus devices # # CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set # CONFIG_QCOM_EBI2 is not set CONFIG_SIMPLE_PM_BUS=y CONFIG_VEXPRESS_CONFIG=y +# CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_OF_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set # # Partition parsers # +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # end of Partition parsers @@ -1568,7 +1680,6 @@ CONFIG_MTD_CFI_I2=y # # CONFIG_MTD_PMC551 is not set # CONFIG_MTD_DATAFLASH is not set -CONFIG_MTD_M25P80=y # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set @@ -1582,10 +1693,19 @@ CONFIG_MTD_M25P80=y # CONFIG_MTD_DOCG3 is not set # end of Self-contained MTD device drivers +# +# NAND +# # CONFIG_MTD_ONENAND is not set # CONFIG_MTD_RAW_NAND is not set # CONFIG_MTD_SPI_NAND is not set +# +# ECC engine support +# +# end of ECC engine support +# end of NAND + # # LPDDR & LPDDR2 PCM memory drivers # @@ -1594,9 +1714,8 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -# CONFIG_SPI_CADENCE_QUADSPI is not set -# CONFIG_SPI_MTK_QUADSPI is not set # CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set @@ -1606,7 +1725,6 @@ CONFIG_OF_KOBJ=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_NET=y -CONFIG_OF_MDIO=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set # CONFIG_PARPORT is not set @@ -1634,7 +1752,6 @@ CONFIG_BLK_DEV_NBD=m CONFIG_XEN_BLKDEV_FRONTEND=y # CONFIG_XEN_BLKDEV_BACKEND is not set CONFIG_VIRTIO_BLK=y -# CONFIG_VIRTIO_BLK_SCSI is not set # CONFIG_BLK_DEV_RBD is not set # CONFIG_BLK_DEV_RSXX is not set @@ -1653,7 +1770,6 @@ CONFIG_VIRTIO_BLK=y # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1668,12 +1784,12 @@ CONFIG_VIRTIO_BLK=y # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y -CONFIG_VEXPRESS_SYSCFG=y # CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set +# CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set # @@ -1699,51 +1815,13 @@ CONFIG_VEXPRESS_SYSCFG=y # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_ALTERA_STAPL is not set - -# -# Intel MIC & related support -# - -# -# Intel MIC Bus Driver -# - -# -# SCIF Bus Driver -# - -# -# VOP Bus Driver -# -# CONFIG_VOP_BUS is not set - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# -# end of Intel MIC & related support - # CONFIG_GENWQE is not set # CONFIG_ECHO is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set # end of Misc devices # @@ -1760,7 +1838,6 @@ CONFIG_SCSI_DMA=y # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set @@ -1824,6 +1901,7 @@ CONFIG_SCSI_UFS_QCOM=y # CONFIG_XEN_SCSI_FRONTEND is not set # CONFIG_SCSI_SNIC is not set # CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set # CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set @@ -1845,7 +1923,10 @@ CONFIG_SCSI_UFS_QCOM=y CONFIG_HAVE_PATA_PLATFORM=y CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y CONFIG_ATA_ACPI=y # CONFIG_SATA_ZPODD is not set CONFIG_SATA_PMP=y @@ -1966,6 +2047,7 @@ CONFIG_WIREGUARD=y # CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set # CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set # CONFIG_GTP is not set # CONFIG_MACSEC is not set # CONFIG_NETCONSOLE is not set @@ -1976,10 +2058,6 @@ CONFIG_TUN=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # @@ -2056,6 +2134,8 @@ CONFIG_NET_VENDOR_EMULEX=y # CONFIG_BE2NET is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HIX5HD2_GMAC is not set # CONFIG_HISI_FEMAC is not set @@ -2065,8 +2145,6 @@ CONFIG_HNS=y CONFIG_HNS_DSAF=y CONFIG_HNS_ENET=y # CONFIG_HNS3 is not set -CONFIG_NET_VENDOR_HP=y -# CONFIG_HP100 is not set CONFIG_NET_VENDOR_HUAWEI=y # CONFIG_HINIC is not set CONFIG_NET_VENDOR_I825XX=y @@ -2091,6 +2169,7 @@ CONFIG_NET_VENDOR_MARVELL=y CONFIG_SKY2=y # CONFIG_SKY2_DEBUG is not set # CONFIG_OCTEONTX2_AF is not set +# CONFIG_OCTEONTX2_PF is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLX4_EN is not set # CONFIG_MLX5_CORE is not set @@ -2128,10 +2207,11 @@ CONFIG_NET_VENDOR_OKI=y CONFIG_NET_VENDOR_PACKET_ENGINES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set CONFIG_NET_VENDOR_QLOGIC=y # CONFIG_QLA3XXX is not set # CONFIG_QLCNIC is not set -# CONFIG_QLGE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_QED is not set CONFIG_NET_VENDOR_QUALCOMM=y @@ -2165,11 +2245,13 @@ CONFIG_SMSC911X=y CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set CONFIG_STMMAC_PLATFORM=m # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=m CONFIG_DWMAC_IPQ806X=m CONFIG_DWMAC_QCOM_ETHQOS=m +# CONFIG_DWMAC_INTEL_PLAT is not set # CONFIG_STMMAC_PCI is not set CONFIG_NET_VENDOR_SUN=y # CONFIG_HAPPYMEAL is not set @@ -2189,47 +2271,38 @@ CONFIG_NET_VENDOR_VIA=y CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5100 is not set # CONFIG_WIZNET_W5300 is not set +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_NET_SB1000 is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -# CONFIG_MDIO_BCM_UNIMAC is not set -CONFIG_MDIO_BITBANG=y -# CONFIG_MDIO_BUS_MUX_GPIO is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set -# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set -# CONFIG_MDIO_GPIO is not set -# CONFIG_MDIO_HISI_FEMAC is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_OCTEON is not set -# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set # # MII PHY device drivers # # CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set -# CONFIG_AT803X_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM87XX_PHY is not set # CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -CONFIG_FIXED_PHY=y # CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_LXT_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set CONFIG_MICREL_PHY=y @@ -2237,16 +2310,50 @@ CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=m # CONFIG_RENESAS_PHY is not set # CONFIG_ROCKCHIP_PHY is not set -# CONFIG_SMSC_PHY is not set +CONFIG_SMSC_PHY=m # CONFIG_STE10XP is not set # CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +# end of PCS device drivers + # CONFIG_PPP is not set # CONFIG_SLIP is not set CONFIG_USB_NET_DRIVERS=y @@ -2309,6 +2416,7 @@ CONFIG_WLAN_VENDOR_ATH=y # CONFIG_ATH10K is not set CONFIG_WCN36XX=y # CONFIG_WCN36XX_DEBUGFS is not set +# CONFIG_ATH11K is not set CONFIG_WLAN_VENDOR_ATMEL=y CONFIG_ATMEL=y # CONFIG_PCI_ATMEL is not set @@ -2319,6 +2427,9 @@ CONFIG_AT76C50X_USB=y # CONFIG_WLAN_VENDOR_INTERSIL is not set # CONFIG_WLAN_VENDOR_MARVELL is not set # CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set # CONFIG_WLAN_VENDOR_RALINK is not set # CONFIG_WLAN_VENDOR_REALTEK is not set # CONFIG_WLAN_VENDOR_RSI is not set @@ -2396,7 +2507,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_TM2_TOUCHKEY is not set # CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_CROS_EC is not set # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_BCM is not set CONFIG_INPUT_MOUSE=y @@ -2437,6 +2547,7 @@ CONFIG_TOUCHSCREEN_PROPERTIES=y # CONFIG_TOUCHSCREEN_BU21029 is not set # CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set # CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set @@ -2508,16 +2619,15 @@ CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y # CONFIG_TOUCHSCREEN_ZFORCE is not set # CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set # CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ATMEL_CAPTOUCH is not set # CONFIG_INPUT_BMA150 is not set # CONFIG_INPUT_E3X0_BUTTON is not set -# CONFIG_INPUT_MSM_VIBRATOR is not set CONFIG_INPUT_PM8941_PWRKEY=y # CONFIG_INPUT_PM8XXX_VIBRATOR is not set # CONFIG_INPUT_MMA8450 is not set -# CONFIG_INPUT_GP2A is not set # CONFIG_INPUT_GPIO_BEEPER is not set # CONFIG_INPUT_GPIO_DECODER is not set # CONFIG_INPUT_GPIO_VIBRA is not set @@ -2535,6 +2645,7 @@ CONFIG_INPUT_PM8941_PWRKEY=y # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set # CONFIG_INPUT_CMA3000 is not set CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y # CONFIG_INPUT_SOC_BUTTON_ARRAY is not set @@ -2575,13 +2686,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_NOZOMI is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -# CONFIG_NULL_TTY is not set CONFIG_LDISC_AUTOLOAD=y -CONFIG_DEVMEM=y # # Serial drivers @@ -2590,6 +2695,7 @@ CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y @@ -2599,10 +2705,10 @@ CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set # CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set -# CONFIG_SERIAL_8250_MOXA is not set CONFIG_SERIAL_OF_PLATFORM=y # @@ -2631,28 +2737,45 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_RP2 is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set # end of Serial drivers -# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y CONFIG_HVC_IRQ=y CONFIG_HVC_XEN=y CONFIG_HVC_XEN_FRONTEND=y # CONFIG_HVC_DCC is not set +# CONFIG_SERIAL_DEV_BUS is not set CONFIG_VIRTIO_CONSOLE=y # CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_HISI_V2=m CONFIG_HW_RANDOM_CAVIUM=m +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_APPLICOM is not set +CONFIG_DEVMEM=y # CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y +# CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # end of Character devices +# CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + # # I2C support # @@ -2716,14 +2839,15 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_CADENCE is not set # CONFIG_I2C_CBUS_GPIO is not set CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y # CONFIG_I2C_DESIGNWARE_SLAVE is not set +CONFIG_I2C_DESIGNWARE_PLATFORM=y # CONFIG_I2C_DESIGNWARE_PCI is not set # CONFIG_I2C_EMEV2 is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_NOMADIK is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_QCOM_CCI is not set CONFIG_I2C_QUP=y # CONFIG_I2C_RK3X is not set # CONFIG_I2C_SIMTEC is not set @@ -2734,7 +2858,6 @@ CONFIG_I2C_QUP=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2742,12 +2865,12 @@ CONFIG_I2C_QUP=y # # Other I2C/SMBus bus drivers # -CONFIG_I2C_CROS_EC_TUNNEL=y # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set CONFIG_I2C_SLAVE=y # CONFIG_I2C_SLAVE_EEPROM is not set +# CONFIG_I2C_SLAVE_TESTUNIT is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -2766,7 +2889,9 @@ CONFIG_SPI_MEM=y # CONFIG_SPI_AXI_SPI_ENGINE is not set # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_HISI_SFC_V3XX is not set # CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set @@ -2783,6 +2908,12 @@ CONFIG_SPI_QUP=y # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set # CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set # # SPI Protocol Masters @@ -2791,6 +2922,7 @@ CONFIG_SPI_SPIDEV=m # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set +CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y CONFIG_SPMI_MSM_PMIC_ARB=y # CONFIG_HSI is not set @@ -2816,6 +2948,8 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2838,11 +2972,14 @@ CONFIG_PINCTRL_APQ8084=y CONFIG_PINCTRL_IPQ4019=y CONFIG_PINCTRL_IPQ8064=y CONFIG_PINCTRL_IPQ8074=y +# CONFIG_PINCTRL_IPQ6018 is not set +# CONFIG_PINCTRL_MSM8226 is not set CONFIG_PINCTRL_MSM8660=y CONFIG_PINCTRL_MSM8960=y CONFIG_PINCTRL_MDM9615=y CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_MSM8916=y +# CONFIG_PINCTRL_MSM8976 is not set CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y # CONFIG_PINCTRL_MSM8998 is not set @@ -2850,8 +2987,17 @@ CONFIG_PINCTRL_MSM8996=y CONFIG_PINCTRL_QDF2XXX=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y +# CONFIG_PINCTRL_SC7180 is not set # CONFIG_PINCTRL_SDM660 is not set # CONFIG_PINCTRL_SDM845 is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PINCTRL_SM8250 is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y @@ -2859,6 +3005,8 @@ CONFIG_GPIO_ACPI=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y # @@ -2874,9 +3022,11 @@ CONFIG_GPIO_DWAPB=y CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_GRGPIO is not set # CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_PL061=y # CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_XGENE=y # CONFIG_GPIO_XILINX is not set @@ -2893,6 +3043,7 @@ CONFIG_GPIO_XGENE=y # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_TPIC2810 is not set # end of I2C GPIO expanders @@ -2928,9 +3079,9 @@ CONFIG_GPIO_MAX77620=y # # end of USB GPIO expanders +# CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_W1 is not set -CONFIG_POWER_AVS=y CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMSTB is not set # CONFIG_POWER_RESET_GPIO is not set @@ -2944,16 +3095,17 @@ CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set # CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_SBS is not set # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set @@ -2973,15 +3125,18 @@ CONFIG_BATTERY_BQ27XXX_I2C=y # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set # CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set -# CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set # CONFIG_HWMON is not set CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_OF=y @@ -2989,19 +3144,16 @@ CONFIG_THERMAL_OF=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set # CONFIG_THERMAL_GOV_USER_SPACE is not set -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y -# CONFIG_CLOCK_THERMAL is not set +CONFIG_CPU_FREQ_THERMAL=y # CONFIG_DEVFREQ_THERMAL is not set CONFIG_THERMAL_EMULATION=y # CONFIG_THERMAL_MMIO is not set # CONFIG_MAX77620_THERMAL is not set -# CONFIG_QORIQ_THERMAL is not set # CONFIG_GENERIC_ADC_THERMAL is not set # @@ -3015,6 +3167,7 @@ CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set # @@ -3036,8 +3189,8 @@ CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y # CONFIG_DW_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_MAX77620_WATCHDOG is not set -# CONFIG_IMX_SC_WDT is not set # CONFIG_QCOM_WDT is not set +# CONFIG_ARM_SMC_WATCHDOG is not set # CONFIG_PM8916_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_I6300ESB_WDT is not set @@ -3073,8 +3226,6 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set -CONFIG_MFD_CROS_EC=y -# CONFIG_MFD_CROS_EC_CHARDEV is not set # CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set @@ -3084,13 +3235,16 @@ CONFIG_MFD_CROS_EC=y # CONFIG_MFD_DA9063 is not set # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set # CONFIG_MFD_MC13XXX_SPI is not set # CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set @@ -3106,6 +3260,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_EZX_PCAP is not set @@ -3124,7 +3279,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y @@ -3164,9 +3318,12 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set CONFIG_MFD_VEXPRESS_SYSREG=y +# CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -3177,10 +3334,10 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ANATOP is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_ISL9305 is not set # CONFIG_REGULATOR_ISL6271A is not set @@ -3196,8 +3353,14 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -3205,10 +3368,17 @@ CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y +# CONFIG_REGULATOR_QCOM_USB_VBUS is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_S5M8767 is not set +# CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -3217,7 +3387,8 @@ CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set # CONFIG_REGULATOR_VEXPRESS is not set -CONFIG_CEC_CORE=y +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +# CONFIG_REGULATOR_QCOM_LABIBB is not set CONFIG_RC_CORE=y CONFIG_RC_MAP=y # CONFIG_LIRC is not set @@ -3234,31 +3405,52 @@ CONFIG_IR_XMP_DECODER=y # CONFIG_IR_IMON_DECODER is not set # CONFIG_IR_RCMM_DECODER is not set # CONFIG_RC_DEVICES is not set +CONFIG_CEC_CORE=y +# CONFIG_MEDIA_CEC_RC is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set # -# Multimedia core support +# Media device types # CONFIG_MEDIA_CAMERA_SUPPORT=y # CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set # CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set # CONFIG_MEDIA_RADIO_SUPPORT is not set # CONFIG_MEDIA_SDR_SUPPORT is not set -# CONFIG_MEDIA_CEC_SUPPORT is not set -# CONFIG_MEDIA_CEC_RC is not set -CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_PLATFORM_SUPPORT is not set +# CONFIG_MEDIA_TEST_SUPPORT is not set +# end of Media device types + CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_CONTROLLER=y + +# +# Video4Linux options +# CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m +# end of Video4Linux options + +# +# Media controller options +# +# end of Media controller options # # Media drivers # + +# +# Drivers filtered as selected at 'Filter media drivers' +# CONFIG_MEDIA_USB_SUPPORT=y # @@ -3330,39 +3522,17 @@ CONFIG_USB_S2255=m # # CONFIG_VIDEO_EM28XX is not set # CONFIG_MEDIA_PCI_SUPPORT is not set -CONFIG_V4L_PLATFORM_DRIVERS=y -# CONFIG_VIDEO_CAFE_CCIC is not set -# CONFIG_VIDEO_CADENCE is not set -# CONFIG_VIDEO_ASPEED is not set -# CONFIG_VIDEO_MUX is not set -# CONFIG_VIDEO_QCOM_CAMSS is not set -# CONFIG_VIDEO_XILINX is not set -CONFIG_V4L_MEM2MEM_DRIVERS=y -# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set -# CONFIG_VIDEO_SH_VEU is not set -CONFIG_VIDEO_QCOM_VENUS=m -# CONFIG_V4L_TEST_DRIVERS is not set - -# -# Supported MMC/SDIO adapters -# -# CONFIG_CYPRESS_FIRMWARE is not set CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m CONFIG_VIDEOBUF2_MEMOPS=m CONFIG_VIDEOBUF2_VMALLOC=m -CONFIG_VIDEOBUF2_DMA_SG=m +# end of Media drivers # -# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# Media ancillary drivers # -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_IR_I2C=y -# -# I2C Encoders, decoders, sensors and other helper chips -# - # # Audio decoders, processors and mixers # @@ -3382,11 +3552,13 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_WM8739 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers # # RDS decoders # # CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders # # Video decoders @@ -3412,12 +3584,14 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set # CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_MAX9286 is not set # # Video and audio decoders # # CONFIG_VIDEO_SAA717X is not set # CONFIG_VIDEO_CX25840 is not set +# end of Video decoders # # Video encoders @@ -3428,27 +3602,60 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set # CONFIG_VIDEO_ADV7393 is not set -# CONFIG_VIDEO_ADV7511 is not set # CONFIG_VIDEO_AD9389B is not set # CONFIG_VIDEO_AK881X is not set # CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips # # Camera sensor devices # +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX355 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set # CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV2740 is not set # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3472,6 +3679,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_SR030PC30 is not set # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set @@ -3480,6 +3688,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_SMIAPP is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set +# end of Camera sensor devices # # Lens drivers @@ -3487,7 +3696,9 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_AD5820 is not set # CONFIG_VIDEO_AK7375 is not set # CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set # CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers # # Flash devices @@ -3495,30 +3706,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_ADP1653 is not set # CONFIG_VIDEO_LM3560 is not set # CONFIG_VIDEO_LM3646 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set - -# -# Audio/Video compression chips -# -# CONFIG_VIDEO_SAA6752HS is not set - -# -# SDR tuner chips -# - -# -# Miscellaneous helper chips -# -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_I2C is not set -# CONFIG_VIDEO_ST_MIPID02 is not set -# end of I2C Encoders, decoders, sensors and other helper chips +# end of Flash devices # # SPI helper chips @@ -3530,15 +3718,7 @@ CONFIG_VIDEO_IR_I2C=y # Media SPI Adapters # # end of Media SPI Adapters - -# -# Customise DVB Frontends -# - -# -# Tools to develop new frontends -# -# end of Customise DVB Frontends +# end of Media ancillary drivers # # Graphics support @@ -3576,22 +3756,14 @@ CONFIG_DRM_I2C_SIL164=m # CONFIG_DRM_RADEON is not set # CONFIG_DRM_AMDGPU is not set - -# -# ACP (Audio CoProcessor) Configuration -# -# end of ACP (Audio CoProcessor) Configuration - # CONFIG_DRM_NOUVEAU is not set # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_RCAR_DW_HDMI is not set # CONFIG_DRM_RCAR_LVDS is not set -CONFIG_DRM_RCAR_WRITEBACK=y # CONFIG_DRM_QXL is not set # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_VIRTIO_GPU is not set @@ -3599,6 +3771,7 @@ CONFIG_DRM_MSM=y CONFIG_DRM_MSM_GPU_STATE=y # CONFIG_DRM_MSM_REGISTER_LOGGING is not set # CONFIG_DRM_MSM_HDMI_HDCP is not set +CONFIG_DRM_MSM_DP=y CONFIG_DRM_MSM_DSI=y CONFIG_DRM_MSM_DSI_PLL=y CONFIG_DRM_MSM_DSI_28NM_PHY=y @@ -3606,40 +3779,64 @@ CONFIG_DRM_MSM_DSI_20NM_PHY=y CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y CONFIG_DRM_MSM_DSI_14NM_PHY=y CONFIG_DRM_MSM_DSI_10NM_PHY=y +CONFIG_DRM_MSM_DSI_7NM_PHY=y CONFIG_DRM_PANEL=y # # Display Panels # # CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set # CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set -# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -3648,25 +3845,35 @@ CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # -# CONFIG_DRM_ANALOGIX_ANX78XX is not set # CONFIG_DRM_CDNS_DSI is not set -# CONFIG_DRM_DUMB_VGA_DAC is not set -# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +# CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set # CONFIG_DRM_SIL_SII8620 is not set # CONFIG_DRM_SII902X is not set # CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set # CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set # CONFIG_DRM_TOSHIBA_TC358764 is not set # CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_I2C_ADV7533=y CONFIG_DRM_I2C_ADV7511_CEC=y +# CONFIG_DRM_CDNS_MHDP8546 is not set # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set @@ -3674,11 +3881,21 @@ CONFIG_DRM_I2C_ADV7511_CEC=y # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set # CONFIG_DRM_XEN is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_TIDSS is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3749,9 +3966,9 @@ CONFIG_XEN_FBDEV_FRONTEND=y # # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_KTD253 is not set # CONFIG_BACKLIGHT_PWM is not set -# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set # CONFIG_BACKLIGHT_LM3630A is not set @@ -3761,6 +3978,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set # CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_LED is not set # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y @@ -3809,12 +4027,15 @@ CONFIG_SND_DRIVERS=y # CONFIG_SND_MPU401 is not set CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set # CONFIG_SND_ATIIXP is not set # CONFIG_SND_ATIIXP_MODEM is not set # CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8830 is not set # CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set # CONFIG_SND_BT87X is not set # CONFIG_SND_CA0106 is not set # CONFIG_SND_CMIPCI is not set @@ -3836,17 +4057,23 @@ CONFIG_SND_PCI=y # CONFIG_SND_INDIGODJ is not set # CONFIG_SND_INDIGOIOX is not set # CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set # CONFIG_SND_ENS1370 is not set # CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set # CONFIG_SND_FM801 is not set # CONFIG_SND_HDSP is not set # CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set # CONFIG_SND_ICE1724 is not set # CONFIG_SND_INTEL8X0 is not set # CONFIG_SND_INTEL8X0M is not set # CONFIG_SND_KORG1212 is not set # CONFIG_SND_LOLA is not set # CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set # CONFIG_SND_MIXART is not set # CONFIG_SND_NM256 is not set # CONFIG_SND_PCXHR is not set @@ -3855,6 +4082,8 @@ CONFIG_SND_PCI=y # CONFIG_SND_RME96 is not set # CONFIG_SND_RME9652 is not set # CONFIG_SND_SE6X is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set # CONFIG_SND_VIA82XX is not set # CONFIG_SND_VIA82XX_MODEM is not set # CONFIG_SND_VIRTUOSO is not set @@ -3884,6 +4113,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y CONFIG_SND_SOC=y # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set # @@ -3912,6 +4142,7 @@ CONFIG_SND_SOC_LPASS_PLATFORM=y CONFIG_SND_SOC_LPASS_APQ8016=y # CONFIG_SND_SOC_STORM is not set CONFIG_SND_SOC_APQ8016_SBC=y +CONFIG_SND_SOC_QCOM_COMMON=y # CONFIG_SND_SOC_SOF_TOPLEVEL is not set # @@ -3934,6 +4165,8 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set # CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set # CONFIG_SND_SOC_AK4458 is not set @@ -3945,7 +4178,6 @@ CONFIG_SND_SOC_AK4613=y # CONFIG_SND_SOC_ALC5623 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set -# CONFIG_SND_SOC_CROS_EC_CODEC is not set # CONFIG_SND_SOC_CS35L32 is not set # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set @@ -3956,6 +4188,7 @@ CONFIG_SND_SOC_AK4613=y # CONFIG_SND_SOC_CS42L52 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set # CONFIG_SND_SOC_CS4271_I2C is not set @@ -3965,6 +4198,8 @@ CONFIG_SND_SOC_AK4613=y # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set # CONFIG_SND_SOC_DMIC is not set CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set @@ -3975,10 +4210,12 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set -# CONFIG_SND_SOC_MAX98373 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98390 is not set # CONFIG_SND_SOC_MAX9860 is not set CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y @@ -4009,6 +4246,9 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_STA350 is not set # CONFIG_SND_SOC_STI_SAS is not set # CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4021,9 +4261,11 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set # CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set # CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8524 is not set @@ -4047,10 +4289,12 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set @@ -4092,6 +4336,7 @@ CONFIG_HID_CHICONY=y # CONFIG_HID_MACALLY is not set # CONFIG_HID_PRODIKEYS is not set # CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set @@ -4101,8 +4346,9 @@ CONFIG_HID_CYPRESS=y CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set -# CONFIG_HID_GOOGLE_HAMMER is not set +# CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set # CONFIG_HID_KYE is not set @@ -4167,6 +4413,7 @@ CONFIG_SONY_FF=y # CONFIG_HID_ZYDACRON is not set # CONFIG_HID_SENSOR_HUB is not set # CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set # end of Special HID drivers # @@ -4187,6 +4434,9 @@ CONFIG_USB_HID=y CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +CONFIG_USB_ULPI_BUS=y +# CONFIG_USB_CONN_GPIO is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y @@ -4196,15 +4446,15 @@ CONFIG_USB_PCI=y # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_OTG_FSM is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -4213,6 +4463,7 @@ CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_DBGCAP is not set CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y @@ -4270,6 +4521,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_ULPI is not set @@ -4296,9 +4548,12 @@ CONFIG_USB_DWC2_DUAL_ROLE=y # CONFIG_USB_DWC2_DEBUG is not set # CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_OF=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_MSM=y +CONFIG_USB_CHIPIDEA_IMX=y +CONFIG_USB_CHIPIDEA_GENERIC=y +CONFIG_USB_CHIPIDEA_TEGRA=y CONFIG_USB_ISP1760=y CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1761_UDC=y @@ -4373,7 +4628,6 @@ CONFIG_USB_SERIAL_QT2=m # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_CYPRESS_CY7C63 is not set @@ -4381,6 +4635,7 @@ CONFIG_USB_SERIAL_QT2=m # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set @@ -4433,6 +4688,7 @@ CONFIG_USB_SNP_UDC_PLAT=y # CONFIG_USB_GOKU is not set # CONFIG_USB_EG20T is not set # CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_MAX3420_UDC is not set # CONFIG_USB_DUMMY_HCD is not set # end of USB Peripheral Controller @@ -4466,6 +4722,10 @@ CONFIG_USB_CONFIGFS=m # CONFIG_USB_CONFIGFS_F_HID is not set # CONFIG_USB_CONFIGFS_F_UVC is not set # CONFIG_USB_CONFIGFS_F_PRINTER is not set + +# +# USB Gadget precomposed configurations +# CONFIG_USB_ZERO=m # CONFIG_USB_ZERO_HNPTEST is not set # CONFIG_USB_AUDIO is not set @@ -4485,11 +4745,11 @@ CONFIG_USB_G_SERIAL=m # CONFIG_USB_G_HID is not set # CONFIG_USB_G_DBGP is not set # CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_RAW_GADGET is not set +# end of USB Gadget precomposed configurations + # CONFIG_TYPEC is not set -# CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_LED_TRIG is not set -CONFIG_USB_ULPI_BUS=y -# CONFIG_UWB is not set +CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y CONFIG_PWRSEQ_SIMPLE=y @@ -4511,10 +4771,12 @@ CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y # CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ASPEED is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set # CONFIG_MMC_SDHCI_OF_DWCMSHC is not set # CONFIG_MMC_SDHCI_CADENCE is not set # CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set CONFIG_MMC_SDHCI_MSM=y # CONFIG_MMC_TIFM_SD is not set CONFIG_MMC_SPI=y @@ -4531,6 +4793,7 @@ CONFIG_MMC_DW_K3=y # CONFIG_MMC_USHC is not set # CONFIG_MMC_USDHI6ROL0 is not set CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set # CONFIG_MMC_TOSHIBA_PCI is not set # CONFIG_MMC_MTK is not set # CONFIG_MMC_SDHCI_XENON is not set @@ -4540,15 +4803,18 @@ CONFIG_MMC_CQHCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # # LED drivers # # CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set # CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set # CONFIG_LEDS_LM3530 is not set # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set @@ -4557,10 +4823,8 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -4582,6 +4846,8 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set # # LED Triggers @@ -4660,6 +4926,7 @@ CONFIG_RTC_DRV_MAX77686=y # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set CONFIG_RTC_DRV_S5M=y # CONFIG_RTC_DRV_SD3078 is not set @@ -4710,7 +4977,6 @@ CONFIG_RTC_DRV_EFI=y # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # CONFIG_RTC_DRV_ZYNQMP is not set -# CONFIG_RTC_DRV_CROS_EC is not set # # on-CPU RTC drivers @@ -4720,7 +4986,6 @@ CONFIG_RTC_DRV_PL031=y # CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_PM8XXX is not set -# CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_R7301 is not set # @@ -4742,16 +5007,22 @@ CONFIG_BCM_SBA_RAID=m # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_QDMA is not set +# CONFIG_HISI_DMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_MV_XOR_V2 is not set CONFIG_PL330_DMA=y +# CONFIG_PLX_DMA is not set # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set CONFIG_QCOM_BAM_DMA=y CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y # CONFIG_DW_DMAC is not set # CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set # # DMA Clients @@ -4766,6 +5037,9 @@ CONFIG_DMA_ENGINE_RAID=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -4788,6 +5062,10 @@ CONFIG_VIRTIO_BALLOON=y # CONFIG_VIRTIO_INPUT is not set CONFIG_VIRTIO_MMIO=y # CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support @@ -4816,30 +5094,22 @@ CONFIG_XEN_EFI=y CONFIG_XEN_AUTO_XLATE=y # end of Xen driver support +# CONFIG_GREYBUS is not set # CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y # CONFIG_CHROMEOS_TBMC is not set -# CONFIG_CROS_EC_I2C is not set -# CONFIG_CROS_EC_RPMSG is not set -# CONFIG_CROS_EC_SPI is not set -CONFIG_CROS_EC_PROTO=y +# CONFIG_CROS_EC is not set # CONFIG_CROS_KBD_LED_BACKLIGHT is not set # CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# -CONFIG_COMMON_CLK_VERSATILE=y -CONFIG_CLK_SP810=y -CONFIG_CLK_VEXPRESS_OSC=y -# CONFIG_CLK_HSDK is not set # CONFIG_COMMON_CLK_MAX77686 is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_SCPI=y +# CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set # CONFIG_COMMON_CLK_SI544 is not set @@ -4857,15 +5127,19 @@ CONFIG_QCOM_GDSC=y CONFIG_QCOM_RPMCC=y CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_A53PLL=y +# CONFIG_QCOM_CLK_APCC_MSM8996 is not set CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_APQ_GCC_8084=y CONFIG_APQ_MMCC_8084=y +# CONFIG_IPQ_APSS_PLL is not set CONFIG_IPQ_GCC_4019=y +# CONFIG_IPQ_GCC_6018 is not set CONFIG_IPQ_GCC_806X=y CONFIG_IPQ_LCC_806X=y CONFIG_IPQ_GCC_8074=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_GCC_8916=y +# CONFIG_MSM_GCC_8939 is not set CONFIG_MSM_GCC_8960=y CONFIG_MSM_LCC_8960=y CONFIG_MDM_GCC_9615=y @@ -4877,20 +5151,33 @@ CONFIG_MSM_GCC_8994=y CONFIG_MSM_GCC_8996=y CONFIG_MSM_MMCC_8996=y # CONFIG_MSM_GCC_8998 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_MMCC_8998 is not set # CONFIG_QCS_GCC_404 is not set +# CONFIG_SC_DISPCC_7180 is not set +# CONFIG_SC_GCC_7180 is not set +# CONFIG_SC_LPASS_CORECC_7180 is not set +# CONFIG_SC_GPUCC_7180 is not set +# CONFIG_SC_MSS_7180 is not set +# CONFIG_SC_VIDEOCC_7180 is not set # CONFIG_SDM_CAMCC_845 is not set # CONFIG_SDM_GCC_660 is not set # CONFIG_QCS_TURING_404 is not set +# CONFIG_QCS_Q6SSTOP_404 is not set # CONFIG_SDM_GCC_845 is not set # CONFIG_SDM_GPUCC_845 is not set # CONFIG_SDM_VIDEOCC_845 is not set # CONFIG_SDM_DISPCC_845 is not set # CONFIG_SDM_LPASSCC_845 is not set +# CONFIG_SM_GCC_8150 is not set +# CONFIG_SM_GCC_8250 is not set +# CONFIG_SM_GPUCC_8150 is not set +# CONFIG_SM_GPUCC_8250 is not set +# CONFIG_SM_VIDEOCC_8150 is not set +# CONFIG_SM_VIDEOCC_8250 is not set # CONFIG_SPMI_PMIC_CLKDIV is not set # CONFIG_QCOM_HFPLL is not set # CONFIG_KPSS_XCC is not set -# end of Common Clock Framework - CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y @@ -4900,14 +5187,13 @@ CONFIG_HWSPINLOCK_QCOM=y CONFIG_TIMER_OF=y CONFIG_TIMER_ACPI=y CONFIG_TIMER_PROBE=y -CONFIG_CLKSRC_MMIO=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y CONFIG_FSL_ERRATUM_A008585=y CONFIG_HISILICON_ERRATUM_161010101=y CONFIG_ARM64_ERRATUM_858921=y -CONFIG_CLKSRC_VERSATILE=y +# CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers CONFIG_MAILBOX=y @@ -4918,6 +5204,7 @@ CONFIG_ARM_MHU=y # CONFIG_ALTERA_MBOX is not set # CONFIG_MAILBOX_TEST is not set # CONFIG_QCOM_APCS_IPC is not set +# CONFIG_QCOM_IPCC is not set CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -4936,14 +5223,18 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y CONFIG_ARM_SMMU=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y # CONFIG_ARM_SMMU_V3 is not set CONFIG_QCOM_IOMMU=y +# CONFIG_VIRTIO_IOMMU is not set # # Remoteproc drivers # CONFIG_REMOTEPROC=y +# CONFIG_REMOTEPROC_CDEV is not set +CONFIG_QCOM_PIL_INFO=m CONFIG_QCOM_RPROC_COMMON=m # CONFIG_QCOM_Q6V5_ADSP is not set # CONFIG_QCOM_Q6V5_MSS is not set @@ -4989,6 +5280,8 @@ CONFIG_RPMSG_QCOM_SMD=y # # NXP/Freescale QorIQ SoC drivers # +# CONFIG_QUICC_ENGINE is not set +# CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers # @@ -4996,22 +5289,17 @@ CONFIG_RPMSG_QCOM_SMD=y # # end of i.MX SoC drivers -# -# IXP4xx SoC drivers -# -# CONFIG_IXP4XX_QMGR is not set -# CONFIG_IXP4XX_NPE is not set -# end of IXP4xx SoC drivers - # # Qualcomm SoC drivers # -# CONFIG_QCOM_COMMAND_DB is not set +# CONFIG_QCOM_AOSS_QMP is not set +CONFIG_QCOM_COMMAND_DB=y +# CONFIG_QCOM_CPR is not set # CONFIG_QCOM_GENI_SE is not set -# CONFIG_QCOM_GLINK_SSR is not set # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_LLCC is not set CONFIG_QCOM_MDT_LOADER=y +# CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_RMTFS_MEM is not set # CONFIG_QCOM_RPMH is not set # CONFIG_QCOM_RPMPD is not set @@ -5020,6 +5308,7 @@ CONFIG_QCOM_SMD_RPM=y CONFIG_QCOM_SMEM_STATE=y CONFIG_QCOM_SMP2P=y CONFIG_QCOM_SMSM=y +# CONFIG_QCOM_SOCINFO is not set CONFIG_QCOM_WCNSS_CTRL=y # CONFIG_QCOM_APR is not set # end of Qualcomm SoC drivers @@ -5054,6 +5343,7 @@ CONFIG_EXTCON=y # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set @@ -5061,7 +5351,6 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y -# CONFIG_EXTCON_USBC_CROS_EC is not set # CONFIG_MEMORY is not set CONFIG_IIO=y # CONFIG_IIO_BUFFER is not set @@ -5069,6 +5358,7 @@ CONFIG_IIO=y # CONFIG_IIO_TRIGGER is not set # CONFIG_IIO_SW_DEVICE is not set # CONFIG_IIO_SW_TRIGGER is not set +# CONFIG_IIO_TRIGGERED_EVENT is not set # # Accelerometers @@ -5081,13 +5371,13 @@ CONFIG_IIO=y # CONFIG_ADXL372_I2C is not set # CONFIG_BMA180 is not set # CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set -# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -5108,9 +5398,12 @@ CONFIG_IIO=y # # Analog to digital converters # +# CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set # CONFIG_AD7266 is not set # CONFIG_AD7291 is not set +# CONFIG_AD7292 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set # CONFIG_AD7606_IFACE_PARALLEL is not set @@ -5124,6 +5417,8 @@ CONFIG_IIO=y # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set +# CONFIG_AD9467 is not set +# CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_HI8435 is not set @@ -5131,10 +5426,12 @@ CONFIG_IIO=y # CONFIG_INA2XX_ADC is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set # CONFIG_LTC2497 is not set # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set # CONFIG_MCP320X is not set @@ -5159,6 +5456,7 @@ CONFIG_IIO=y # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set +# CONFIG_XILINX_XADC is not set # end of Analog to digital converters # @@ -5171,22 +5469,23 @@ CONFIG_IIO=y # Amplifiers # # CONFIG_AD8366 is not set +# CONFIG_HMC425 is not set # end of Amplifiers # # Chemical Sensors # # CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATLAS_EZO_SENSOR is not set # CONFIG_BME680 is not set # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set +# CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set # CONFIG_SPS30 is not set # CONFIG_VZ89X is not set # end of Chemical Sensors -# CONFIG_IIO_CROS_EC_SENSORS_CORE is not set - # # Hid Sensor IIO Common # @@ -5211,19 +5510,20 @@ CONFIG_IIO=y # CONFIG_AD5593R is not set # CONFIG_AD5504 is not set # CONFIG_AD5624R_SPI is not set -# CONFIG_LTC1660 is not set -# CONFIG_LTC2632 is not set # CONFIG_AD5686_SPI is not set # CONFIG_AD5696_I2C is not set # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set # CONFIG_DS4424 is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set # CONFIG_M62332 is not set # CONFIG_MAX517 is not set # CONFIG_MAX5821 is not set @@ -5255,6 +5555,7 @@ CONFIG_IIO=y # Phase-Locked Loop (PLL) frequency synthesizers # # CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5265,6 +5566,7 @@ CONFIG_IIO=y # CONFIG_ADIS16130 is not set # CONFIG_ADIS16136 is not set # CONFIG_ADIS16260 is not set +# CONFIG_ADXRS290 is not set # CONFIG_ADXRS450 is not set # CONFIG_BMG160 is not set # CONFIG_FXAS21002C is not set @@ -5293,6 +5595,7 @@ CONFIG_IIO=y # CONFIG_AM2315 is not set # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set +# CONFIG_HDC2010 is not set # CONFIG_HTS221 is not set # CONFIG_HTU21 is not set # CONFIG_SI7005 is not set @@ -5303,10 +5606,16 @@ CONFIG_IIO=y # Inertial measurement units # # CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set +# CONFIG_INV_ICM42600_I2C is not set +# CONFIG_INV_ICM42600_SPI is not set # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set @@ -5317,9 +5626,12 @@ CONFIG_IIO=y # # CONFIG_ACPI_ALS is not set # CONFIG_ADJD_S311 is not set +# CONFIG_ADUX1020 is not set +# CONFIG_AL3010 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set +# CONFIG_AS73211 is not set # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set # CONFIG_CM32181 is not set @@ -5327,6 +5639,7 @@ CONFIG_IIO=y # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set @@ -5337,6 +5650,7 @@ CONFIG_IIO=y # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set # CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set @@ -5352,6 +5666,7 @@ CONFIG_IIO=y # CONFIG_US5182D is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set # CONFIG_VEML6070 is not set # CONFIG_VL6180 is not set # CONFIG_ZOPT2201 is not set @@ -5385,11 +5700,17 @@ CONFIG_IIO=y # # end of Inclinometer sensors +# +# Linear and angular position sensors +# +# end of Linear and angular position sensors + # # Digital potentiometers # # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set # CONFIG_MAX5481 is not set # CONFIG_MAX5487 is not set # CONFIG_MCP4018 is not set @@ -5410,7 +5731,10 @@ CONFIG_IIO=y # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set +# CONFIG_DPS310 is not set # CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set @@ -5434,10 +5758,13 @@ CONFIG_IIO=y # CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set # CONFIG_MB1232 is not set +# CONFIG_PING is not set # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set +# CONFIG_SX9310 is not set # CONFIG_SX9500 is not set # CONFIG_SRF08 is not set +# CONFIG_VCNL3020 is not set # CONFIG_VL53L0X_I2C is not set # end of Proximity and distance sensors @@ -5451,6 +5778,7 @@ CONFIG_IIO=y # # Temperature sensors # +# CONFIG_LTC2983 is not set # CONFIG_MAXIM_THERMOCOUPLE is not set # CONFIG_MLX90614 is not set # CONFIG_MLX90632 is not set @@ -5465,7 +5793,7 @@ CONFIG_IIO=y # CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y -# CONFIG_PWM_CROS_EC is not set +# CONFIG_PWM_DEBUG is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set @@ -5479,6 +5807,7 @@ CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set CONFIG_PARTITION_PERCPU=y # CONFIG_QCOM_IRQ_COMBINER is not set # CONFIG_QCOM_PDC is not set @@ -5486,10 +5815,11 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_BRCMSTB_RESCAL is not set +# CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_TI_SYSCON is not set -# CONFIG_FMC is not set # # PHY Subsystem @@ -5497,23 +5827,29 @@ CONFIG_RESET_CONTROLLER=y CONFIG_GENERIC_PHY=y CONFIG_PHY_XGENE=y # CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set CONFIG_PHY_QCOM_APQ8064_SATA=y +# CONFIG_PHY_QCOM_IPQ4019_USB is not set CONFIG_PHY_QCOM_IPQ806X_SATA=y +# CONFIG_PHY_QCOM_PCIE2 is not set CONFIG_PHY_QCOM_QMP=y CONFIG_PHY_QCOM_QUSB2=y -CONFIG_PHY_QCOM_UFS=y -CONFIG_PHY_QCOM_UFS_14NM=y CONFIG_PHY_QCOM_USB_HS=y +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set CONFIG_PHY_QCOM_USB_HSIC=y +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SS is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set CONFIG_PHY_SAMSUNG_USB2=y # CONFIG_PHY_TUSB1210 is not set # end of PHY Subsystem @@ -5526,16 +5862,18 @@ CONFIG_PHY_SAMSUNG_USB2=y # # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set +# CONFIG_ARM_CMN is not set CONFIG_ARM_PMU=y CONFIG_ARM_PMU_ACPI=y # CONFIG_ARM_DSU_PMU is not set -# CONFIG_HISI_PMU is not set # CONFIG_QCOM_L2_PMU is not set # CONFIG_QCOM_L3_PMU is not set # CONFIG_ARM_SPE_PMU is not set +# CONFIG_HISI_PMU is not set # end of Performance monitor support CONFIG_RAS=y +# CONFIG_USB4 is not set # # Android @@ -5548,6 +5886,7 @@ CONFIG_RAS=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_QCOM_QFPROM=y +# CONFIG_NVMEM_SPMI_SDAM is not set # # HW tracing support @@ -5564,6 +5903,7 @@ CONFIG_PM_OPP=y # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set +# CONFIG_MOST is not set # end of Device Drivers # @@ -5607,6 +5947,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -5623,6 +5964,7 @@ CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m +# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -5644,7 +5986,7 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y @@ -5652,8 +5994,9 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set -# end of DOS/FAT/NT Filesystems +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -5668,6 +6011,7 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -5715,13 +6059,13 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 CONFIG_UFS_FS=y # CONFIG_UFS_FS_WRITE is not set CONFIG_UFS_DEBUG=y +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -# CONFIG_NFS_SWAP is not set CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y @@ -5732,6 +6076,8 @@ CONFIG_NFS_V4_SECURITY_LABEL=y CONFIG_ROOT_NFS=y # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y @@ -5806,13 +6152,14 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set # CONFIG_UNICODE is not set +CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y -CONFIG_KEYS_COMPAT=y +# CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_BIG_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set @@ -5832,6 +6179,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_SECURITY_LOADPIN is not set # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y @@ -5848,6 +6196,12 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity" # Memory initialization # CONFIG_INIT_STACK_NONE=y +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization # end of Kernel hardening options # end of Security options @@ -5864,8 +6218,8 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y @@ -5884,7 +6238,6 @@ CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set -CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y # CONFIG_CRYPTO_TEST is not set @@ -5899,6 +6252,8 @@ CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y # CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set # # Authenticated Encryption with Associated Data @@ -5907,10 +6262,6 @@ CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set # CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS1280 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y @@ -5928,6 +6279,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -5942,6 +6294,9 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_BLAKE2B=y +# CONFIG_CRYPTO_BLAKE2S is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_GHASH=y # CONFIG_CRYPTO_POLY1305 is not set @@ -6007,21 +6362,49 @@ CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_RNG=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_BLAKE2S=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_CCP is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set # CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set # CONFIG_CRYPTO_DEV_QCE is not set # CONFIG_CRYPTO_DEV_QCOM_RNG is not set CONFIG_CRYPTO_DEV_VIRTIO=m +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set # CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set +# CONFIG_CRYPTO_DEV_HISI_ZIP is not set +# CONFIG_CRYPTO_DEV_HISI_HPRE is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y -CONFIG_PKCS8_PRIVATE_KEY_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y # CONFIG_PKCS7_TEST_KEY is not set # CONFIG_SIGNED_PE_FILE_VERIFICATION is not set @@ -6041,6 +6424,7 @@ CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_RAID6_PQ=y CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y # CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y @@ -6048,10 +6432,12 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y # CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # CONFIG_INDIRECT_PIO is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=y @@ -6090,14 +6476,17 @@ CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m +CONFIG_INTERVAL_TREE=y CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -6107,12 +6496,13 @@ CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y -CONFIG_ARCH_HAS_DMA_MMAP_PGPROT=y CONFIG_SWIOTLB=y +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_REMAP=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_CMA=y +# CONFIG_DMA_PERNUMA_CMA is not set # # Default contiguous memory area size: @@ -6131,17 +6521,20 @@ CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_CLZ_TAB=y -# CONFIG_DDR is not set # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_SG_POOL=y +CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines @@ -6160,6 +6553,9 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options # @@ -6167,6 +6563,7 @@ CONFIG_DYNAMIC_DEBUG=y # CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_BTF is not set @@ -6175,10 +6572,7 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -# CONFIG_OPTIMIZE_INLINING is not set +# CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_ARCH_WANT_FRAME_POINTERS=y @@ -6186,9 +6580,23 @@ CONFIG_FRAME_POINTER=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options +# +# Generic Kernel Debugging Instruments +# CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y @@ -6200,13 +6608,20 @@ CONFIG_DEBUG_MISC=y # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y @@ -6214,33 +6629,35 @@ CONFIG_DEBUG_MEMORY_INIT=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set -CONFIG_KASAN_STACK=1 # end of Memory Debugging -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_DEBUG_SHIRQ is not set # -# Debug Lockups and Hangs +# Debug Oops, Lockups and Hangs # +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 # CONFIG_SOFTLOCKUP_DETECTOR is not set CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 # CONFIG_WQ_WATCHDOG is not set -# end of Debug Lockups and Hangs +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 +# +# Scheduler Debugging +# CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y -# CONFIG_SCHED_STACK_END_CHECK is not set +# end of Scheduler Debugging + # CONFIG_DEBUG_TIMEKEEPING is not set # CONFIG_DEBUG_PREEMPT is not set @@ -6260,24 +6677,33 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # -# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set @@ -6286,66 +6712,24 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set -CONFIG_RUNTIME_TESTING_MENU=y -# CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set -# CONFIG_TEST_SORT is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_RBTREE_TEST is not set -# CONFIG_INTERVAL_TREE_TEST is not set -# CONFIG_PERCPU_TEST is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_STRSCPY is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_PRINTF is not set -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_BITFIELD is not set -# CONFIG_TEST_UUID is not set -# CONFIG_TEST_XARRAY is not set -# CONFIG_TEST_OVERFLOW is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set -# CONFIG_TEST_IDA is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_VMALLOC is not set -# CONFIG_TEST_USER_COPY is not set -# CONFIG_TEST_BPF is not set -# CONFIG_FIND_BIT_BENCHMARK is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_SYSCTL is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_TEST_STATIC_KEYS is not set -# CONFIG_TEST_KMOD is not set -# CONFIG_TEST_MEMCAT_P is not set -# CONFIG_TEST_STACKINIT is not set -CONFIG_MEMTEST=y -# CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set + +# +# arm64 Debugging +# CONFIG_PID_IN_CONTEXTIDR=y -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_DEBUG_ALIGN_RODATA is not set # CONFIG_DEBUG_EFI is not set # CONFIG_ARM64_RELOC_TEST is not set CONFIG_CORESIGHT=y @@ -6357,4 +6741,57 @@ CONFIG_CORESIGHT_SINK_ETBV10=y CONFIG_CORESIGHT_SOURCE_ETM4X=y # CONFIG_CORESIGHT_STM is not set # CONFIG_CORESIGHT_CPU_DEBUG is not set +# CONFIG_CORESIGHT_CTI is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage # end of Kernel hacking From b7bd89b27e95624e14023ba41fa9a562bf5ee5e5 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Tue, 20 Apr 2021 14:49:41 +0000 Subject: [PATCH 28/51] linux (Qualcomm Dragonboard): add 5.10.32 option CONFIG_AS_HAS_LSE_ATOMICS --- projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index 7911b1b7f9..5fd911af90 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.20 Kernel Configuration +# Linux/arm64 5.10.32 Kernel Configuration # # @@ -416,6 +416,7 @@ CONFIG_SETEND_EMULATION=y # CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y +CONFIG_AS_HAS_LSE_ATOMICS=y CONFIG_ARM64_LSE_ATOMICS=y CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM64_VHE=y From 77f67daa68cc0fe643ccc855550a456eff8acfd8 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 20 Aug 2021 07:27:09 +1000 Subject: [PATCH 29/51] linux (Samsung): update dts patch against 5.14 --- ...ARM-dts-exynos5422-HC1-XU3-XU4-model-name-is-ODR.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/projects/Samsung/patches/linux/samsung-0025-WIP-ARM-dts-exynos5422-HC1-XU3-XU4-model-name-is-ODR.patch b/projects/Samsung/patches/linux/samsung-0025-WIP-ARM-dts-exynos5422-HC1-XU3-XU4-model-name-is-ODR.patch index 4db33fa977..fd9a39b4f0 100644 --- a/projects/Samsung/patches/linux/samsung-0025-WIP-ARM-dts-exynos5422-HC1-XU3-XU4-model-name-is-ODR.patch +++ b/projects/Samsung/patches/linux/samsung-0025-WIP-ARM-dts-exynos5422-HC1-XU3-XU4-model-name-is-ODR.patch @@ -58,9 +58,9 @@ index 98feecad5489..d0084033199a 100644 + model = "Hardkernel ODROID XU3 Lite"; + compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", + "samsung,exynos5"; - }; - &arm_a7_pmu { + aliases { + ethernet = ðernet; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index db0bc17a667b..3ff7ec514e20 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -74,9 +74,9 @@ index db0bc17a667b..3ff7ec514e20 100644 + model = "Hardkernel ODROID XU3"; + compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", + "samsung,exynos5"; - }; - &i2c_0 { + aliases { + ethernet = ðernet; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 892d389d6d09..d2061b244537 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts From 46489f599cbec3a74eea4daa03b1b02c5550742c Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 20 Aug 2021 08:05:27 +1000 Subject: [PATCH 30/51] linux (NXP iMX6): patches upstreamed in 5.14 --- ...6qdl-wandboard-dtsi-i2c-bus-recovery.patch | 56 ------------------- 1 file changed, 56 deletions(-) delete mode 100644 projects/NXP/devices/iMX6/patches/linux/linux-002-imx6qdl-wandboard-dtsi-i2c-bus-recovery.patch diff --git a/projects/NXP/devices/iMX6/patches/linux/linux-002-imx6qdl-wandboard-dtsi-i2c-bus-recovery.patch b/projects/NXP/devices/iMX6/patches/linux/linux-002-imx6qdl-wandboard-dtsi-i2c-bus-recovery.patch deleted file mode 100644 index f271e3bd79..0000000000 --- a/projects/NXP/devices/iMX6/patches/linux/linux-002-imx6qdl-wandboard-dtsi-i2c-bus-recovery.patch +++ /dev/null @@ -1,56 +0,0 @@ -Add scl/sda gpios defitions for i2c bus recovery. - ---- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi -@@ -97,15 +97,21 @@ - - &i2c1 { - clock-frequency = <100000>; -- pinctrl-names = "default"; -+ pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; -+ pinctrl-1 = <&pinctrl_i2c1_gpio>; -+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - }; - - &i2c2 { - clock-frequency = <100000>; -- pinctrl-names = "default"; -+ pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; -+ pinctrl-1 = <&pinctrl_i2c2_gpio>; -+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - codec: sgtl5000@a { -@@ -185,6 +191,13 @@ - >; - }; - -+ pinctrl_i2c1_gpio: i2c1gpiogrp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0 -+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0 -+ >; -+ }; -+ - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -@@ -192,6 +205,13 @@ - >; - }; - -+ pinctrl_i2c2_gpio: i2c2gpiogrp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0 -+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0 -+ >; -+ }; -+ - pinctrl_mclk: mclkgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 From 5746c7d9bb18c5ee7e27a647dcf64b029ce97063 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Fri, 20 Aug 2021 20:39:56 +1000 Subject: [PATCH 31/51] linux (NXP iMX8): patches upstreamed in 5.14 --- ...p-Add-cdns-mhdp-driver-bridge-driver.patch | 5 +- ...9-clk-imx8mq-add-27MHz-PHY-ref-clock.patch | 13 +++-- ...dp-dp-hdmi-driver-for-imx8x-platform.patch | 2 +- ...fix-unused-but-set-variable-warnings.patch | 48 ------------------- ...-drm-imx-dcss-fix-coccinelle-warning.patch | 33 ------------- 5 files changed, 10 insertions(+), 91 deletions(-) delete mode 100644 projects/NXP/devices/iMX8/patches/linux/0039-drm-imx-dcss-fix-unused-but-set-variable-warnings.patch delete mode 100644 projects/NXP/devices/iMX8/patches/linux/0042-drm-imx-dcss-fix-coccinelle-warning.patch diff --git a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch index 855403f61a..a61e0b180b 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch @@ -78,9 +78,10 @@ diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/ca index 8f647991b374..618290870ba5 100644 --- a/drivers/gpu/drm/bridge/cadence/Makefile +++ b/drivers/gpu/drm/bridge/cadence/Makefile -@@ -2,3 +2,12 @@ +@@ -1,4 +1,13 @@ + # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o - cdns-mhdp8546-y := cdns-mhdp8546-core.o + cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o + +cdns_mhdp_drmcore-y := cdns-mhdp-common.o cdns-mhdp-dp.o cdns-mhdp-hdmi.o diff --git a/projects/NXP/devices/iMX8/patches/linux/0029-clk-imx8mq-add-27MHz-PHY-ref-clock.patch b/projects/NXP/devices/iMX8/patches/linux/0029-clk-imx8mq-add-27MHz-PHY-ref-clock.patch index fdfa29b214..ee9efc0bad 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0029-clk-imx8mq-add-27MHz-PHY-ref-clock.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0029-clk-imx8mq-add-27MHz-PHY-ref-clock.patch @@ -37,14 +37,13 @@ diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/cloc index 9b8045d75b8b..2a81f96b7c74 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h -@@ -431,6 +431,8 @@ +@@ -431,6 +431,7 @@ + #define IMX8MQ_CLK_MON_SEL 301 + #define IMX8MQ_CLK_MON_CLK2_OUT 302 ++#define IMX8MQ_CLK_PHY_27MHZ 303 - #define IMX8MQ_CLK_A53_CORE 289 - --#define IMX8MQ_CLK_END 290 -+#define IMX8MQ_CLK_PHY_27MHZ 290 -+ -+#define IMX8MQ_CLK_END 291 +-#define IMX8MQ_CLK_END 303 ++#define IMX8MQ_CLK_END 304 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- diff --git a/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch b/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch index 0215193b42..fd980240ef 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch @@ -2038,7 +2038,7 @@ index 000000000000..a3ba3da4b05d + goto out; + + if (!imx_mhdp->fw) { -+ ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_NOHOTPLUG, ++ ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_NOUEVENT, + imx_mhdp->firmware_name, + imx_mhdp->mhdp.dev, GFP_KERNEL, + imx_mhdp, diff --git a/projects/NXP/devices/iMX8/patches/linux/0039-drm-imx-dcss-fix-unused-but-set-variable-warnings.patch b/projects/NXP/devices/iMX8/patches/linux/0039-drm-imx-dcss-fix-unused-but-set-variable-warnings.patch deleted file mode 100644 index 6b7a19f3d5..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0039-drm-imx-dcss-fix-unused-but-set-variable-warnings.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 6b147fc07b475ede9ede99cf381f1706be5de6f9 Mon Sep 17 00:00:00 2001 -From: Wang ShaoBo -Date: Fri, 11 Sep 2020 09:44:14 +0800 -Subject: [PATCH 39/49] drm/imx/dcss: fix unused but set variable warnings -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Fix unused but set variable warning building with `make W=1`: - -drivers/gpu/drm/imx/dcss/dcss-plane.c:270:6: warning: - variable ‘pixel_format’ set but not used [-Wunused-but-set-variable] - u32 pixel_format; - ^~~~~~~~~~~~ - -Fixes: 9021c317b770 ("drm/imx: Add initial support for DCSS on iMX8MQ") -Reported-by: Hulk Robot -Signed-off-by: Wang ShaoBo -Reviewed-by: Laurentiu Palcu -Signed-off-by: Lucas Stach -Link: https://patchwork.freedesktop.org/patch/msgid/20200911014414.4663-1-bobo.shaobowang@huawei.com ---- - drivers/gpu/drm/imx/dcss/dcss-plane.c | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c b/drivers/gpu/drm/imx/dcss/dcss-plane.c -index 961d671f171b..e13652e3a115 100644 ---- a/drivers/gpu/drm/imx/dcss/dcss-plane.c -+++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c -@@ -267,7 +267,6 @@ static void dcss_plane_atomic_update(struct drm_plane *plane, - struct dcss_plane *dcss_plane = to_dcss_plane(plane); - struct dcss_dev *dcss = plane->dev->dev_private; - struct drm_framebuffer *fb = state->fb; -- u32 pixel_format; - struct drm_crtc_state *crtc_state; - bool modifiers_present; - u32 src_w, src_h, dst_w, dst_h; -@@ -277,7 +276,6 @@ static void dcss_plane_atomic_update(struct drm_plane *plane, - if (!fb || !state->crtc || !state->visible) - return; - -- pixel_format = state->fb->format->format; - crtc_state = state->crtc->state; - modifiers_present = !!(fb->flags & DRM_MODE_FB_MODIFIERS); - --- -2.29.2 - diff --git a/projects/NXP/devices/iMX8/patches/linux/0042-drm-imx-dcss-fix-coccinelle-warning.patch b/projects/NXP/devices/iMX8/patches/linux/0042-drm-imx-dcss-fix-coccinelle-warning.patch deleted file mode 100644 index bb636d3299..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0042-drm-imx-dcss-fix-coccinelle-warning.patch +++ /dev/null @@ -1,33 +0,0 @@ -From c869538d2a0e04edf0ad9abf89ef6ff70502ed86 Mon Sep 17 00:00:00 2001 -From: Laurentiu Palcu -Date: Thu, 5 Nov 2020 16:01:26 +0200 -Subject: [PATCH 42/49] drm/imx/dcss: fix coccinelle warning - -This small patch fixes a warning that I got while running coccinelle: - - CHECK drivers/gpu/drm/imx/dcss/dcss-plane.c - drivers/gpu/drm/imx/dcss/dcss-plane.c:107:21-23: WARNING !A || A && B is equivalent to !A || B - -Fixes: 9021c317b770 ("drm/imx: Add initial support for DCSS on iMX8MQ") -Signed-off-by: Laurentiu Palcu ---- - drivers/gpu/drm/imx/dcss/dcss-plane.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c b/drivers/gpu/drm/imx/dcss/dcss-plane.c -index e13652e3a115..c8dc6f4436e1 100644 ---- a/drivers/gpu/drm/imx/dcss/dcss-plane.c -+++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c -@@ -103,8 +103,7 @@ static bool dcss_plane_can_rotate(const struct drm_format_info *format, - bool mod_present, u64 modifier, - unsigned int rotation) - { -- bool linear_format = !mod_present || -- (mod_present && modifier == DRM_FORMAT_MOD_LINEAR); -+ bool linear_format = !mod_present || modifier == DRM_FORMAT_MOD_LINEAR; - u32 supported_rotation = DRM_MODE_ROTATE_0; - - if (!format->is_yuv && linear_format) --- -2.29.2 - From 36bf5aa381769a595926ceeb9171c57d787d9d55 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Tue, 11 May 2021 13:38:11 +0000 Subject: [PATCH 32/51] linux (Rockchip): update patches for 5.12 --- .../linux-0001-rockchip-from-5.11.patch | 3068 ----------------- .../linux-0002-rockchip-from-5.12.patch | 662 ---- .../linux-0004-rockchip-from-list.patch | 3 +- .../default/linux-0010-v4l2-from-list.patch | 13 +- .../default/linux-0020-drm-from-5.11.patch | 465 --- .../default/linux-0021-drm-from-list.patch | 28 - .../default/linux-1003-for-libreelec.patch | 11 +- .../linux-2000-v4l-wip-rkvdec-vp9.patch | 7 +- .../linux-2001-v4l-wip-rkvdec-hevc.patch | 30 +- .../linux-2002-v4l-wip-iep-driver.patch | 2 +- 10 files changed, 19 insertions(+), 4270 deletions(-) delete mode 100644 projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch delete mode 100644 projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch delete mode 100644 projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch deleted file mode 100644 index 0bf1066b21..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch +++ /dev/null @@ -1,3068 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Robin Murphy -Date: Mon, 26 Oct 2020 11:17:20 +0000 -Subject: [PATCH] clk: rockchip: Add appropriate arch dependencies - -There's no point offering support for 32-bit platforms to users -configuring a 64-bit kernel - and vice-versa - unless they are -explicitly interested in compile-testing. - -Signed-off-by: Robin Murphy -Link: https://lore.kernel.org/r/72abb0f794b8ed77e274e8ee21c22e0bd3223dfd.1603710913.git.robin.murphy@arm.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/Kconfig | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig -index 47cd6c5de837..effd05032e85 100644 ---- a/drivers/clk/rockchip/Kconfig -+++ b/drivers/clk/rockchip/Kconfig -@@ -11,67 +11,77 @@ config COMMON_CLK_ROCKCHIP - if COMMON_CLK_ROCKCHIP - config CLK_PX30 - bool "Rockchip PX30 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for PX30 Clock Driver. - - config CLK_RV110X - bool "Rockchip RV110x clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RV110x Clock Driver. - - config CLK_RK3036 - bool "Rockchip RK3036 clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK3036 Clock Driver. - - config CLK_RK312X - bool "Rockchip RK312x clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK312x Clock Driver. - - config CLK_RK3188 - bool "Rockchip RK3188 clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK3188 Clock Driver. - - config CLK_RK322X - bool "Rockchip RK322x clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK322x Clock Driver. - - config CLK_RK3288 - bool "Rockchip RK3288 clock controller support" -- depends on ARM -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK3288 Clock Driver. - - config CLK_RK3308 - bool "Rockchip RK3308 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3308 Clock Driver. - - config CLK_RK3328 - bool "Rockchip RK3328 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3328 Clock Driver. - - config CLK_RK3368 - bool "Rockchip RK3368 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3368 Clock Driver. - - config CLK_RK3399 - tristate "Rockchip RK3399 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3399 Clock Driver. - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Xu Wang -Date: Fri, 27 Nov 2020 09:05:51 +0000 -Subject: [PATCH] clk: rockchip: Remove redundant null check before - clk_prepare_enable - -Because clk_prepare_enable() already checked NULL clock parameter, -so the additional check is unnecessary, just remove it. - -Signed-off-by: Xu Wang -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20201127090551.50254-1-vulab@iscas.ac.cn -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c -index b443169dd408..336481bc6cc7 100644 ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -603,8 +603,7 @@ void rockchip_clk_protect_critical(const char *const clocks[], - for (i = 0; i < nclocks; i++) { - struct clk *clk = __clk_lookup(clocks[i]); - -- if (clk) -- clk_prepare_enable(clk); -+ clk_prepare_enable(clk); - } - } - EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Wed, 18 Nov 2020 14:58:16 +0100 -Subject: [PATCH] clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a - i2s and uart clocks - -Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks, -so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX -also update. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3188.c | 28 ++++++++++++++-------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c -index 730020fcc7fe..db8c588139de 100644 ---- a/drivers/clk/rockchip/clk-rk3188.c -+++ b/drivers/clk/rockchip/clk-rk3188.c -@@ -255,19 +255,19 @@ static struct rockchip_clk_branch common_spdif_fracmux __initdata = - RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart0_fracmux __initdata = -- MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, -+ MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart1_fracmux __initdata = -- MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, -+ MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart2_fracmux __initdata = -- MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, -+ MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart3_fracmux __initdata = -- MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, -+ MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_clk_branches[] __initdata = { -@@ -408,28 +408,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { - COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, - RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 8, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(17), 0, - RK2928_CLKGATE_CON(1), 9, GFLAGS, - &common_uart0_fracmux), - COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, - RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 10, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(18), 0, - RK2928_CLKGATE_CON(1), 11, GFLAGS, - &common_uart1_fracmux), - COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, - RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 12, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(19), 0, - RK2928_CLKGATE_CON(1), 13, GFLAGS, - &common_uart2_fracmux), - COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, - RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 14, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(20), 0, - RK2928_CLKGATE_CON(1), 15, GFLAGS, - &common_uart3_fracmux), -@@ -543,15 +543,15 @@ static struct clk_div_table div_aclk_cpu_t[] = { - }; - - static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata = -- MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, -+ MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(2), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata = -- MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, -+ MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata = -- MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, -+ MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(4), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { -@@ -615,21 +615,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { - COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, - RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(0), 7, GFLAGS), -- COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0, -+ COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(6), 0, - RK2928_CLKGATE_CON(0), 8, GFLAGS, - &rk3066a_i2s0_fracmux), - COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, - RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(0), 9, GFLAGS), -- COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0, -+ COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(7), 0, - RK2928_CLKGATE_CON(0), 10, GFLAGS, - &rk3066a_i2s1_fracmux), - COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, - RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(0), 11, GFLAGS), -- COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0, -+ COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(8), 0, - RK2928_CLKGATE_CON(0), 12, GFLAGS, - &rk3066a_i2s2_fracmux), - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Wed, 18 Nov 2020 14:58:17 +0100 -Subject: [PATCH] clk: rockchip: fix i2s gate bits on rk3066 and rk3188 - -The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON: - -hclk_i2s_8ch_gate_en bit 4 (dtsi: i2s0) -hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1) -hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2) - -The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON: - -hclk_i2s_2ch_gate_en bit 2 (dtsi: i2s0) - -The bits got somehow mixed up in the clk-rk3188.c file. -The labels in the dtsi files are not suppose to change. -The sclk and hclk names should match for -"trace_event=clk_disable,clk_enable", -so remove GATE HCLK_I2S0 from the common clock tree and -fix the bits in the rk3066 and rk3188 clock tree. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201118135822.9582-3-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3188.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c -index db8c588139de..0b76ad34de00 100644 ---- a/drivers/clk/rockchip/clk-rk3188.c -+++ b/drivers/clk/rockchip/clk-rk3188.c -@@ -449,7 +449,6 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { - - /* hclk_cpu gates */ - GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), -- GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), - GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), - GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), - /* hclk_ahb2apb is part of a clk branch */ -@@ -634,8 +633,9 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { - RK2928_CLKGATE_CON(0), 12, GFLAGS, - &rk3066a_i2s2_fracmux), - -- GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), -- GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), -+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), -+ GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), -+ GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), - GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), - GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), - -@@ -728,6 +728,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { - RK2928_CLKGATE_CON(0), 10, GFLAGS, - &rk3188_i2s0_fracmux), - -+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), - GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), - GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexandru Stan -Date: Wed, 21 Oct 2020 22:04:43 -0700 -Subject: [PATCH] ARM: dts: rockchip: Remove 0 point from brightness-levels on - rk3288-veyron - -The extra 0 only adds one point in the userspace visible range, -so this change is almost a noop with the current driver behavior. - -We don't need the 0% point, userspace seems to handle this just fine -because it uses the bl_power property to turn off the display. - -Furthermore after adding "backlight: pwm_bl: Fix interpolation" patch, -the backlight interpolation will work a little differently. So we need -to preemptively remove the 0-3 segment since otherwise we would have a -252 long interpolation that would slowly go between 0 and 3, looking -really bad in userspace. So it's almost a noop/cleanup now, but it will -be required in the future. - -Signed-off-by: Alexandru Stan -Reviewed-by: Douglas Anderson -Acked-by: Daniel Thompson -Link: https://lore.kernel.org/r/20201021220404.v3.1.I96b8d872ec51171f19274e43e96cadc092881271@changeid -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-veyron-jaq.dts | 2 +- - arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 +- - arch/arm/boot/dts/rk3288-veyron-tiger.dts | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts -index af77ab20586d..4a148cf1defc 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts -@@ -20,7 +20,7 @@ / { - - &backlight { - /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ -- brightness-levels = <0 8 255>; -+ brightness-levels = <8 255>; - num-interpolated-steps = <247>; - }; - -diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts -index f8b69e0a16a0..82fc6fba9999 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts -@@ -39,7 +39,7 @@ volum_up { - - &backlight { - /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ -- brightness-levels = <0 3 255>; -+ brightness-levels = <3 255>; - num-interpolated-steps = <252>; - }; - -diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts -index 069f0c2c1fdf..52a84cbe7a90 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-tiger.dts -@@ -23,7 +23,7 @@ / { - - &backlight { - /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ -- brightness-levels = <0 3 255>; -+ brightness-levels = <3 255>; - num-interpolated-steps = <252>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Mon, 16 Nov 2020 16:07:56 +0100 -Subject: [PATCH] ARM: dts: rockchip: rename wdt nodename to watchdog on rv1108 - -A test with the command below gives for example this error: - -/arch/arm/boot/dts/rv1108-evb.dt.yaml: -wdt@10360000: $nodename:0: 'wdt@10360000' -does not match '^watchdog(@.*|-[0-9a-f])?$' - -Fix it by renaming the wdt nodename to watchdog -in the rv1108.dtsi file. - -make ARCH=arm dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201116150756.14265-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rv1108.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi -index a1a08cb9364e..e491964b1c3d 100644 ---- a/arch/arm/boot/dts/rv1108.dtsi -+++ b/arch/arm/boot/dts/rv1108.dtsi -@@ -299,7 +299,7 @@ timer: timer@10350000 { - clock-names = "timer", "pclk"; - }; - -- watchdog: wdt@10360000 { -+ watchdog: watchdog@10360000 { - compatible = "snps,dw-wdt"; - reg = <0x10360000 0x100>; - interrupts = ; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 30 Nov 2020 14:28:14 +0100 -Subject: [PATCH] ARM: dts: rockchip: Add rtc node for VMARC SOM - -Add the hym8563 rtc found on the rk3288 variant of the VMARC SOM. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com -[split out of the original patch, as it was a change unrelated - to the commit description] -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -index 4a373f5aa600..da80bfd5f2d5 100644 ---- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -@@ -231,6 +231,23 @@ regulator-state-mem { - }; - }; - -+&i2c1 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio5>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ }; -+}; -+ - &i2c5 { - status = "okay"; - }; -@@ -245,6 +262,12 @@ &io_domains { - }; - - &pinctrl { -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 23 Oct 2020 23:48:14 +0530 -Subject: [PATCH] ARM: dts: rockchip: Add SDIO0 node for VMARC SOM - -Rockchip RK3288 and RK3399Pro based VMARC SOM has sdio0 for -connecting WiFi/BT devices as a pluggable card via M.2 E-Key. - -Add associated sdio0 nodes, properties. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com -[moved the unrelated rtc addition to a separate patch] -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 17 +++++++++++++++ - .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 +++++++++++++++++++ - .../dts/rockchip/rk3399pro-vmarc-som.dtsi | 16 ++++++++++++++ - 3 files changed, 54 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -index da80bfd5f2d5..0ae2bd150e37 100644 ---- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -@@ -258,6 +258,7 @@ &io_domains { - gpio1830-supply = <&vcc_18>; - gpio30-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; -+ wifi-supply = <&vcc_wl>; - status = "okay"; - }; - -@@ -283,6 +284,12 @@ pmic_int: pmic-int { - }; - }; - -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = -@@ -314,6 +321,16 @@ usb0_en_oc: usb0-en-oc { - }; - }; - -+&sdio_pwrseq { -+ /* -+ * On the module itself this is one of these (depending -+ * on the actual card populated): -+ * - SDIO_RESET_L_WL_REG_ON -+ * - PDN (power down when low) -+ */ -+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ -+}; -+ - &usbphy { - status = "okay"; - }; -diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi -index 26b53eac4706..da1d548b7330 100644 ---- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi -+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi -@@ -15,6 +15,14 @@ clkin_gmac: external-gmac-clock { - #clock-cells = <0>; - }; - -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&hym8563>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ }; -+ - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -78,6 +86,19 @@ &pwm2 { - status = "okay"; - }; - -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ - &sdmmc { - bus-width = <4>; - cap-mmc-highspeed; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -index 5d087be04af8..7257494d2831 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -@@ -353,6 +353,12 @@ pmic_int_l: pmic-int-l { - }; - }; - -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - vbus_host { - usb1_en_oc: usb1-en-oc { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; -@@ -371,6 +377,16 @@ &pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - }; - -+&sdio_pwrseq { -+ /* -+ * On the module itself this is one of these (depending -+ * on the actual card populated): -+ * - SDIO_RESET_L_WL_REG_ON -+ * - PDN (power down when low) -+ */ -+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; -+}; -+ - &sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:15 +0530 -Subject: [PATCH] arm64: defconfig: Enable ROCKCHIP_LVDS - -Now, some of the rockchip hardware platforms do enable -lvds in mainline tree. - -So, enable Rockchip LVDS driver via default defconfig. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-8-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 5cfe3cf6f2ac..3ebba7dcb98f 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -646,6 +646,7 @@ CONFIG_ROCKCHIP_CDN_DP=y - CONFIG_ROCKCHIP_DW_HDMI=y - CONFIG_ROCKCHIP_DW_MIPI_DSI=y - CONFIG_ROCKCHIP_INNO_HDMI=y -+CONFIG_ROCKCHIP_LVDS=y - CONFIG_DRM_RCAR_DU=m - CONFIG_DRM_RCAR_DW_HDMI=m - CONFIG_DRM_SUN4I=m - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:16 +0530 -Subject: [PATCH] arm64: defconfig: Enable PHY_ROCKCHIP_INNO_DSIDPHY - -In order to work LDVS, DSI in mainline tree for Rockchip based -hardware platforms, the associated PHY driver has to enable -in default defconfig. - -Enable rockchip DSI phy driver. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-9-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 3ebba7dcb98f..d50826dd7d68 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -1011,6 +1011,7 @@ CONFIG_PHY_RCAR_GEN3_USB3=m - CONFIG_PHY_ROCKCHIP_EMMC=y - CONFIG_PHY_ROCKCHIP_INNO_HDMI=m - CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m - CONFIG_PHY_ROCKCHIP_PCIE=m - CONFIG_PHY_ROCKCHIP_TYPEC=y - CONFIG_PHY_UNIPHIER_USB2=y - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:17 +0530 -Subject: [PATCH] arm64: defconfig: Enable USB_SERIAL_CP210X - -Some hardware platforms required CP20x USB to Serial converter -in order to work onboard functionalities like Bluetooth. - -An example of such a platform is from Engicam's PX30 (ARM64). - -Mark it as module in defconfig. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-10-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index d50826dd7d68..41a2d489f0a2 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -751,6 +751,7 @@ CONFIG_USB_CHIPIDEA_UDC=y - CONFIG_USB_CHIPIDEA_HOST=y - CONFIG_USB_ISP1760=y - CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_CP210X=m - CONFIG_USB_SERIAL_FTDI_SIO=m - CONFIG_USB_HSIC_USB3503=y - CONFIG_NOP_USB_XCEIV=y - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 23 Oct 2020 23:48:13 +0530 -Subject: [PATCH] arm64: defconfig: Enable RTC_DRV_HYM8563 - -RTC HYM8563 used in the ARM64 Rockchip SoC's SDIO power -sequence enablement. - -Enable it as module. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201023181814.220974-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 41a2d489f0a2..699c204090b8 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -816,6 +816,7 @@ CONFIG_EDAC=y - CONFIG_EDAC_GHES=y - CONFIG_RTC_CLASS=y - CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_HYM8563=m - CONFIG_RTC_DRV_MAX77686=y - CONFIG_RTC_DRV_RK808=m - CONFIG_RTC_DRV_PCF85363=m - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Tue, 3 Nov 2020 15:28:18 +0000 -Subject: [PATCH] soc: rockchip: io-domain: Remove incorrect and incomplete - comment header - -Fixes the following W=1 kernel build warning(s): - - drivers/soc/rockchip/io-domain.c:57: warning: Cannot understand * @supplies: voltage settings matching the register bits. - -Signed-off-by: Lee Jones -Cc: Heiko Stuebner -Cc: Liam Girdwood -Cc: Mark Brown -Cc: "Rafael J. Wysocki" -Cc: Doug Anderson -Cc: linux-rockchip@lists.infradead.org -Link: https://lore.kernel.org/r/20201103152838.1290217-6-lee.jones@linaro.org -Signed-off-by: Heiko Stuebner ---- - drivers/soc/rockchip/io-domain.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c -index b29e829e815e..cf8182fc3642 100644 ---- a/drivers/soc/rockchip/io-domain.c -+++ b/drivers/soc/rockchip/io-domain.c -@@ -53,9 +53,6 @@ - - struct rockchip_iodomain; - --/** -- * @supplies: voltage settings matching the register bits. -- */ - struct rockchip_iodomain_soc_data { - int grf_offset; - const char *supply_names[MAX_SUPPLIES]; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Wed, 14 Oct 2020 22:00:29 +0200 -Subject: [PATCH] dt-bindings: vendor-prefixes: Add kobol prefix -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The prefix is already used in arm/armada-388-helios4.dts. - -Signed-off-by: Uwe Kleine-König -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20201014200030.845759-2-uwe@kleine-koenig.org -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 2735be1a8470..259faf1b382c 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -553,6 +553,8 @@ patternProperties: - description: Kionix, Inc. - "^kobo,.*": - description: Rakuten Kobo Inc. -+ "^kobol,.*": -+ description: Kobol Innovations Pte. Ltd. - "^koe,.*": - description: Kaohsiung Opto-Electronics Inc. - "^kontron,.*": - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Wed, 14 Oct 2020 22:00:30 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add basic support for Kobol's Helios64 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The hardware is described in detail on Kobol's wiki at -https://wiki.kobol.io/helios64/intro/. - -Up to now the following peripherals are working: - - - UART - - Micro-SD card - - eMMC - - ethernet port 1 - - status LED - - temperature sensor on i2c bus 2 - -Signed-off-by: Uwe Kleine-König -Link: https://lore.kernel.org/r/20201014200030.845759-3-uwe@kleine-koenig.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3399-kobol-helios64.dts | 372 ++++++++++++++++++ - 2 files changed, 373 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 26661c7b736b..28b26a874313 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -new file mode 100644 -index 000000000000..2a561be724b2 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Aditya Prayoga -+ */ -+ -+/* -+ * The Kobol Helios64 is a board designed to operate as a NAS and optionally -+ * ships with an enclosing that can host five 2.5" hard disks. -+ * -+ * See https://wiki.kobol.io/helios64/intro/ for further details. -+ */ -+ -+/dts-v1/; -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Kobol Helios64"; -+ compatible = "kobol,helios64", "rockchip,rk3399"; -+ -+ avdd_1v8_s0: avdd-1v8-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "avdd_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; -+ -+ led-0 { -+ label = "helios64:green:status"; -+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ led-1 { -+ label = "helios64:red:fault"; -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ }; -+ -+ vcc1v8_sys_s0: vcc1v8-sys-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v8_sys_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc1v8_sys_s3>; -+ }; -+ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc3v0_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_pwr_h>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc12v_dcin_bkup: vcc12v-dcin-bkup { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin_bkup"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+}; -+ -+/* -+ * The system doesn't run stable with cpu freq enabled, so disallow the lower -+ * frequencies until this problem is properly understood and resolved. -+ */ -+&cluster0_opp { -+ /delete-node/ opp00; -+ /delete-node/ opp01; -+ /delete-node/ opp02; -+ /delete-node/ opp03; -+ /delete-node/ opp04; -+}; -+ -+&cluster1_opp { -+ /delete-node/ opp00; -+ /delete-node/ opp01; -+ /delete-node/ opp02; -+ /delete-node/ opp03; -+ /delete-node/ opp04; -+ /delete-node/ opp05; -+ /delete-node/ opp06; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clock-parents = <&clkin_gmac>; -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ clock_in_out = "input"; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_lan>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins &gphy_reset>; -+ rx_delay = <0x20>; -+ tx_delay = <0x28>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc3v3_sys_s3>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc5v0_sys>; -+ vcc12-supply = <&vcc3v3_sys_s3>; -+ vddio-supply = <&vcc3v0_s3>; -+ wakeup-source; -+ #clock-cells = <1>; -+ -+ regulators { -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_sys_s3: DCDC_REG4 { -+ regulator-name = "vcc1v8_sys_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio_s0: LDO_REG4 { -+ regulator-name = "vcc_sdio_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v0_s3: LDO_REG8 { -+ regulator-name = "vcc3v0_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ temp@4c { -+ compatible = "national,lm75"; -+ reg = <0x4c>; -+ }; -+}; -+ -+&io_domains { -+ audio-supply = <&vcc1v8_sys_s0>; -+ bt656-supply = <&vcc1v8_sys_s0>; -+ gpio1830-supply = <&vcc3v0_s3>; -+ sdmmc-supply = <&vcc_sdio_s0>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gmac { -+ gphy_reset: gphy-reset { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; -+ }; -+ }; -+ -+ leds { -+ sys_grn_led_on: sys-grn-led-on { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ sys_red_led_on: sys-red-led-on { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ vcc3v0-sd { -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc3v0_s3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ vqmmc-supply = <&vcc1v8_sys_s0>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio_s0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Mon, 2 Nov 2020 16:06:58 +0100 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Kobol Helios64 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Document the new board by Kobol introduced recently in -rockchip/rk3399-kobol-helios64.dts. - -Signed-off-by: Uwe Kleine-König -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20201102150658.167161-1-uwe@kleine-koenig.org -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index b621752aaa65..ad1dbf349c33 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -381,6 +381,11 @@ properties: - - khadas,edge-v - - const: rockchip,rk3399 - -+ - description: Kobol Helios64 -+ items: -+ - const: kobol,helios64 -+ - const: rockchip,rk3399 -+ - - description: Mecer Xtreme Mini S6 - items: - - const: mecer,xms6 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Sat, 4 Jul 2020 00:14:13 +0200 -Subject: [PATCH] arm64: dts: rockchip: add adc joystick to Odroid Go Advance - -Add the now usable adc-joystick node that describes the analog -joystick connected to two saradc channels from the rk3326 soc. - -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20200703221413.269800-1-heiko@sntech.de ---- - .../boot/dts/rockchip/rk3326-odroid-go2.dts | 24 +++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -index 337681038519..97fb93e1cc00 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -@@ -18,6 +18,30 @@ chosen { - stdout-path = "serial2:115200n8"; - }; - -+ adc-joystick { -+ compatible = "adc-joystick"; -+ io-channels = <&saradc 1>, -+ <&saradc 2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ axis@0 { -+ reg = <0>; -+ abs-flat = <10>; -+ abs-fuzz = <10>; -+ abs-range = <172 772>; -+ linux,code = ; -+ }; -+ -+ axis@1 { -+ reg = <1>; -+ abs-flat = <10>; -+ abs-fuzz = <10>; -+ abs-range = <278 815>; -+ linux,code = ; -+ }; -+ }; -+ - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_bl>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:11 +0530 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core EDIMM2.2 - Starter Kit - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive -Evaluation Board from Engicam. - -PX30.Core needs to mount on top of this Evaluation board for -creating complete PX30.Core EDIMM2.2 Starter Kit. - -Add bindings for it. - -Signed-off-by: Jagan Teki -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20200929083217.25406-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index ad1dbf349c33..cef95eb26ca6 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -70,6 +70,12 @@ properties: - - const: elgin,rv1108-r1 - - const: rockchip,rv1108 - -+ - description: Engicam PX30.Core EDIMM2.2 Starter Kit -+ items: -+ - const: engicam,px30-core-edimm2.2 -+ - const: engicam,px30-core -+ - const: rockchip,px30 -+ - - description: Firefly Firefly-RK3288 - items: - - enum: - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:12 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam EDIMM2.2 Starter Kit - -Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive -Evaluation Board. - -Genaral features: -- LCD 7" C.Touch -- microSD slot -- Ethernet 1Gb -- Wifi/BT -- 2x LVDS Full HD interfaces -- 3x USB 2.0 -- 1x USB 3.0 -- HDMI Out -- Mini PCIe -- MIPI CSI -- 2x CAN -- Audio Out - -SOM's like PX30.Core needs to mount on top of this Evaluation board -for creating complete PX30.Core EDIMM2.2 Starter Kit. - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-3-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 39 +++++++++++++++++++ - .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 7 ++++ - 2 files changed, 46 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -new file mode 100644 -index 000000000000..bd5bde989e8d ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -0,0 +1,39 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/ { -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; /* +5V */ -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&gmac { -+ clock_in_out = "output"; -+ phy-supply = <&vcc_3v3>; /* +3V3_SOM */ -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 50000 50000>; -+ snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ cap-sd-highspeed; -+ card-detect-delay = <800>; -+ vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ -+ vqmmc-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m1_xfer>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -new file mode 100644 -index 000000000000..cb00988953e9 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+#include "px30-engicam-common.dtsi" - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Michael Trimarchi -Date: Tue, 29 Sep 2020 14:02:13 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core SOM - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -General features: -- Rockchip PX30 -- Up to 2GB DDR4 -- eMMC 4 GB expandible -- rest of PX30 features - -PX30.Core needs to mount on top of Engicam baseboards for creating -complete platform boards. - -Possible baseboards are, -- EDIMM2.2 -- C.TOUCH 2.0 - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-4-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-px30-core.dtsi | 232 ++++++++++++++++++ - 1 file changed, 232 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -new file mode 100644 -index 000000000000..db22f776c68f ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -@@ -0,0 +1,232 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutons -+ * Copyright (c) 2020 Amarula Solutons(India) -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "engicam,px30-core", "rockchip,px30"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&emmc { -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ #clock-cells = <1>; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: DCDC_REG4 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc3v3_sys: DCDC_REG5 { -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_1v0: LDO_REG1 { -+ regulator-name = "vcc_1v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vcc_1v8: LDO_REG2 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_1v0: LDO_REG3 { -+ regulator-name = "vdd_1v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vcc3v0_pmu: LDO_REG4 { -+ regulator-name = "vcc3v0_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc5v0_host: SWITCH_REG2 { -+ regulator-name = "vcc5v0_host"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ vccio1-supply = <&vcc_3v3>; -+ vccio2-supply = <&vcc_3v3>; -+ vccio3-supply = <&vcc_3v3>; -+ vccio4-supply = <&vcc_3v3>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc_3v3>; -+ pmuio2-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:14 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter - Kit - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive -Evaluation Board from Engicam. - -PX30.Core needs to mount on top of this Evaluation board for -creating complete PX30.Core EDIMM2.2 Starter Kit. - -Add support for it. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20200929083217.25406-5-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../px30-engicam-px30-core-edimm2.2.dts | 21 +++++++++++++++++++ - 2 files changed, 22 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 28b26a874313..abf9dc621314 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -new file mode 100644 -index 000000000000..e54d1e480daa ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include "px30.dtsi" -+#include "px30-engicam-edimm2.2.dtsi" -+#include "px30-engicam-px30-core.dtsi" -+ -+/ { -+ model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; -+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", -+ "rockchip,px30"; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:15 +0530 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -PX30.Core needs to mount on top of this Carrier board for creating -complete PX30.Core C.TOUCH 2.0 board. - -Add bindings for it. - -Signed-off-by: Jagan Teki -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20200929083217.25406-6-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index cef95eb26ca6..37fd456170d2 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -70,6 +70,12 @@ properties: - - const: elgin,rv1108-r1 - - const: rockchip,rv1108 - -+ - description: Engicam PX30.Core C.TOUCH 2.0 -+ items: -+ - const: engicam,px30-core-ctouch2 -+ - const: engicam,px30-core -+ - const: rockchip,px30 -+ - - description: Engicam PX30.Core EDIMM2.2 Starter Kit - items: - - const: engicam,px30-core-edimm2.2 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:16 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam C.TOUCH 2.0 - -Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose -carrier board with capacitive touch interface. - -Genaral features: -- TFT 10.1" industrial, 1280x800 LVDS display -- Ethernet 10/100 -- Wifi/BT -- USB Type A/OTG -- Audio Out -- CAN -- LVDS panel connector - -SOM's like PX30.Core needs to mount on top of this Carrier board -for creating complete PX30.Core C.TOUCH 2.0 board. - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-7-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -new file mode 100644 -index 000000000000..58425b1e559f ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+#include "px30-engicam-common.dtsi" - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:17 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -PX30.Core needs to mount on top of this Carrier board for creating -complete PX30.Core C.TOUCH 2.0 board. - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-8-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../px30-engicam-px30-core-ctouch2.dts | 22 +++++++++++++++++++ - 2 files changed, 23 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index abf9dc621314..5a53979b7057 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts -new file mode 100644 -index 000000000000..5a0ecb8faecf ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts -@@ -0,0 +1,22 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include "px30.dtsi" -+#include "px30-engicam-ctouch2.dtsi" -+#include "px30-engicam-px30-core.dtsi" -+ -+/ { -+ model = "Engicam PX30.Core C.TOUCH 2.0"; -+ compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", -+ "rockchip,px30"; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Thu, 26 Nov 2020 15:33:35 +0800 -Subject: [PATCH] arm64: dts: rockchip: Enable HDMI audio on rk3328-roc-cc - -The RK3328-ROC-CC already has HDMI display output enabled. Now that -audio for the HDMI controller is supported, it can be enabled as well. - -Enable the simple-audio-card, and the I2S interface the audio is fed -from. - -Signed-off-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201126073336.30794-3-wens@kernel.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index b76282e704de..697fce709031 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -161,6 +161,10 @@ &hdmiphy { - status = "okay"; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c1 { - status = "okay"; - -@@ -270,6 +274,10 @@ regulator-state-mem { - }; - }; - -+&i2s0 { -+ status = "okay"; -+}; -+ - &io_domains { - status = "okay"; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Thu, 26 Nov 2020 15:33:36 +0800 -Subject: [PATCH] arm64: dts: rockchip: Enable analog audio on rk3328-roc-cc - -Now that driver support for the RK3328's audio codec, and the plumbing -is defined at the SoC level, we can enable analog audio at the board -level. - -Enable analog audio by enabling the codec and the I2S interface -connected and the simple-audio-card that binds them together. - -Signed-off-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201126073336.30794-4-wens@kernel.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 697fce709031..19959bfba451 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -104,6 +104,14 @@ user_led: led-1 { - }; - }; - -+&analog_sound { -+ status = "okay"; -+}; -+ -+&codec { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_arm>; - }; -@@ -278,6 +286,10 @@ &i2s0 { - status = "okay"; - }; - -+&i2s1 { -+ status = "okay"; -+}; -+ - &io_domains { - status = "okay"; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Mon, 16 Nov 2020 14:23:11 +0100 -Subject: [PATCH] arm64: dts: rockchip: rename sdhci nodename to mmc on rk3399 - -A test with the command below gives for example this error: - -/arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: -sdhci@fe330000: $nodename:0: 'sdhci@fe330000' -does not match '^mmc(@.*)?$' - -Fix it by renaming sdhci to mmc. - -make ARCH=arm64 dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/ -mmc/arasan,sdhci.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201116132311.8318-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 7e69603fb41c..4d9a2ea3e6bf 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -331,7 +331,7 @@ sdmmc: mmc@fe320000 { - status = "disabled"; - }; - -- sdhci: sdhci@fe330000 { -+ sdhci: mmc@fe330000 { - compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; - reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:09 +0530 -Subject: [PATCH] arm64: dts: rockchip: Enable USB Host, OTG on px30-enagicam - -Engicam EDIMM2.2 and C.Touch 2.0 Kits support USB Host -and OTG ports. - -Add support to enable USB on these kits while mounting -px30-core SOM. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 24 +++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index bd5bde989e8d..fbbdbb0a40af 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -33,7 +33,31 @@ &sdmmc { - status = "okay"; - }; - -+&u2phy { -+ status = "okay"; -+ -+ u2phy_host: host-port { -+ status = "okay"; -+ }; -+ -+ u2phy_otg: otg-port { -+ status = "okay"; -+ }; -+}; -+ - &uart2 { - pinctrl-0 = <&uart2m1_xfer>; - status = "okay"; - }; -+ -+&usb20_otg { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:10 +0530 -Subject: [PATCH] arm64: dts: rockchip: Enable LVDS panel on - px30-engicam-edimm2.2 - -Engicam PX30.Core EDIMM2.2 developement Kit has on board 10" LVDS -panel from yes-optoelectronics. - -This patch adds panel enablement nodes on respective dts(i) files. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-3-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 4 ++ - .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 59 +++++++++++++++++++ - .../dts/rockchip/px30-engicam-px30-core.dtsi | 5 ++ - 3 files changed, 68 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index fbbdbb0a40af..8fdd7ff2fdf9 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -25,6 +25,10 @@ &gmac { - status = "okay"; - }; - -+&pwm0 { -+ status = "okay"; -+}; -+ - &sdmmc { - cap-sd-highspeed; - card-detect-delay = <800>; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -index cb00988953e9..449b8eb6454e 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -@@ -5,3 +5,62 @@ - */ - - #include "px30-engicam-common.dtsi" -+ -+/ { -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm0 0 25000 0>; -+ }; -+ -+ panel { -+ compatible = "yes-optoelectronics,ytc700tlag-05-201c"; -+ backlight = <&backlight>; -+ data-mapping = "vesa-24"; -+ power-supply = <&vcc3v3_lcd>; -+ -+ port { -+ panel_in_lvds: endpoint { -+ remote-endpoint = <&lvds_out_panel>; -+ }; -+ }; -+ }; -+}; -+ -+&display_subsystem { -+ status = "okay"; -+}; -+ -+&dsi_dphy { -+ status = "okay"; -+}; -+ -+/* LVDS_B(secondary) */ -+&lvds { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ -+ lvds_out_panel: endpoint { -+ remote-endpoint = <&panel_in_lvds>; -+ }; -+ }; -+ }; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -index db22f776c68f..cdacd3483600 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -@@ -192,6 +192,11 @@ regulator-state-mem { - }; - }; - -+ vcc3v3_lcd: SWITCH_REG1 { -+ regulator-boot-on; -+ regulator-name = "vcc3v3_lcd"; -+ }; -+ - vcc5v0_host: SWITCH_REG2 { - regulator-name = "vcc5v0_host"; - regulator-always-on; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:11 +0530 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 - 10.1" OF - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. - -PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged -10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. - -Add bindings for it. - -Acked-by: Rob Herring -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-4-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 37fd456170d2..ef4544ad6f82 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -76,6 +76,12 @@ properties: - - const: engicam,px30-core - - const: rockchip,px30 - -+ - description: Engicam PX30.Core C.TOUCH 2.0 10.1" Open Frame -+ items: -+ - const: engicam,px30-core-ctouch2-of10 -+ - const: engicam,px30-core -+ - const: rockchip,px30 -+ - - description: Engicam PX30.Core EDIMM2.2 Starter Kit - items: - - const: engicam,px30-core-edimm2.2 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:12 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" - OF - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. - -PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged -10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. - -Add support for it. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-5-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../px30-engicam-px30-core-ctouch2-of10.dts | 77 +++++++++++++++++++ - 2 files changed, 78 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 5a53979b7057..1ab55a124a87 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts -new file mode 100644 -index 000000000000..47aa30505a42 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include "px30.dtsi" -+#include "px30-engicam-ctouch2.dtsi" -+#include "px30-engicam-px30-core.dtsi" -+ -+/ { -+ model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; -+ compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", -+ "rockchip,px30"; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm0 0 25000 0>; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+ -+ panel { -+ compatible = "ampire,am-1280800n3tzqw-t00h"; -+ backlight = <&backlight>; -+ power-supply = <&vcc3v3_lcd>; -+ data-mapping = "vesa-24"; -+ -+ port { -+ panel_in_lvds: endpoint { -+ remote-endpoint = <&lvds_out_panel>; -+ }; -+ }; -+ }; -+}; -+ -+&display_subsystem { -+ status = "okay"; -+}; -+ -+&dsi_dphy { -+ status = "okay"; -+}; -+ -+&lvds { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ -+ lvds_out_panel: endpoint { -+ remote-endpoint = <&panel_in_lvds>; -+ }; -+ }; -+ }; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Suniel Mahesh -Date: Mon, 9 Nov 2020 23:40:13 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add WiFi support on px30-engicam - -Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have -an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected -on the SDIO bus. - -The SDIO power sequnce is connacted with exteernal 32KHz oscillator -and it require 3V3 regulator input. - -This patch adds WiFi enablement nodes for these respective boards. - -Signed-off-by: Michael Trimarchi -Signed-off-by: Suniel Mahesh -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-6-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 45 +++++++++++++++++++ - .../dts/rockchip/px30-engicam-ctouch2.dtsi | 12 +++++ - .../px30-engicam-px30-core-edimm2.2.dts | 12 +++++ - 3 files changed, 69 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index 8fdd7ff2fdf9..0e1a93ec3234 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -14,6 +14,51 @@ vcc5v0_sys: vcc5v0-sys { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&xin32k>; -+ clock-names = "ext_clock"; -+ post-power-on-delay-ms = <80>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ }; -+ -+ vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_rf_aux_mod"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ xin32k: xin32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xin32k"; -+ }; -+}; -+ -+&sdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ bus-width = <4>; -+ clock-frequency = <50000000>; -+ cap-sdio-irq; -+ cap-sd-highspeed; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ sd-uhs-sdr104; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ compatible = "brcm,bcm4329-fmac"; -+ reg = <1>; -+ }; - }; - - &gmac { -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -index 58425b1e559f..d5708779c285 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -@@ -6,3 +6,15 @@ - */ - - #include "px30-engicam-common.dtsi" -+ -+&pinctrl { -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdio_pwrseq { -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -index e54d1e480daa..913444548b59 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -@@ -19,3 +19,15 @@ chosen { - stdout-path = "serial2:115200n8"; - }; - }; -+ -+&pinctrl { -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdio_pwrseq { -+ reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Suniel Mahesh -Date: Mon, 9 Nov 2020 23:40:14 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add BT support on px30-engicam - -Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have -an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected -on the UART bus. - -UART bus on the design routed via USB to UART CP20x bridge. This -bridge powered from 3V3 regualtor gpio. - -This patch adds BT enablement nodes for these respective boards. - -Signed-off-by: Michael Trimarchi -Signed-off-by: Suniel Mahesh -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-7-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/px30-engicam-common.dtsi | 12 ++++++++++++ - .../boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 10 ++++++++++ - .../dts/rockchip/px30-engicam-px30-core-edimm2.2.dts | 10 ++++++++++ - 3 files changed, 32 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index 0e1a93ec3234..08b0b9fbcbc9 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -24,6 +24,18 @@ sdio_pwrseq: sdio-pwrseq { - pinctrl-0 = <&wifi_enable_h>; - }; - -+ vcc3v3_btreg: vcc3v3-btreg { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_enable_h>; -+ regulator-name = "btreg-gpio-supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ states = <3300000 0x0>; -+ }; -+ - vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_rf_aux_mod"; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -index d5708779c285..bf10a3d29fca 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -@@ -8,6 +8,12 @@ - #include "px30-engicam-common.dtsi" - - &pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -18,3 +24,7 @@ wifi_enable_h: wifi-enable-h { - &sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; -+ -+&vcc3v3_btreg { -+ enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -index 913444548b59..d759478e1c84 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -@@ -21,6 +21,12 @@ chosen { - }; - - &pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -31,3 +37,7 @@ wifi_enable_h: wifi-enable-h { - &sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; - }; -+ -+&vcc3v3_btreg { -+ enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexis Ballier -Date: Thu, 22 Oct 2020 13:35:32 +0200 -Subject: [PATCH] arm64: dts: rockchip: Properly define the type C connector on - rk3399-orangepi - -Tested: -- USB3 Gigabit adapter -- USB2 mass storage - -The wiring is the same as the pinebook pro according to the schematics, -thus this patch is heavily based on its dts. - -Signed-off-by: Alexis Ballier -Cc: devicetree@vger.kernel.org -Cc: Heiko Stuebner -Cc: linux-arm-kernel@lists.infradead.org -Cc: linux-rockchip@lists.infradead.org -Cc: linux-kernel@vger.kernel.org -Link: https://lore.kernel.org/r/20201022113532.18470-1-aballier@gentoo.org -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-orangepi.dts | 62 ++++++++++++++++++- - 1 file changed, 61 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -index 6163ae8063a7..ad7c4d00888f 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -@@ -7,6 +7,7 @@ - - #include "dt-bindings/pwm/pwm.h" - #include "dt-bindings/input/input.h" -+#include "dt-bindings/usb/pd.h" - #include "rk3399.dtsi" - #include "rk3399-opp.dtsi" - -@@ -531,6 +532,43 @@ fusb302@22 { - pinctrl-names = "default"; - pinctrl-0 = <&chg_cc_int_l>; - vbus-supply = <&vbus_typec>; -+ -+ typec_con: connector { -+ compatible = "usb-c-connector"; -+ data-role = "host"; -+ label = "USB-C"; -+ op-sink-microwatt = <1000000>; -+ power-role = "dual"; -+ sink-pdos = -+ ; -+ source-pdos = -+ ; -+ try-power-role = "sink"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ typec_hs: endpoint { -+ remote-endpoint = <&u2phy0_typec_hs>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ typec_ss: endpoint { -+ remote-endpoint = <&tcphy0_typec_ss>; -+ }; -+ }; -+ port@2 { -+ reg = <2>; -+ typec_dp: endpoint { -+ remote-endpoint = <&tcphy0_typec_dp>; -+ }; -+ }; -+ }; -+ }; - }; - }; - -@@ -717,6 +755,22 @@ &tcphy0 { - status = "okay"; - }; - -+&tcphy0_dp { -+ port { -+ tcphy0_typec_dp: endpoint { -+ remote-endpoint = <&typec_dp>; -+ }; -+ }; -+}; -+ -+&tcphy0_usb3 { -+ port { -+ tcphy0_typec_ss: endpoint { -+ remote-endpoint = <&typec_ss>; -+ }; -+ }; -+}; -+ - &tcphy1 { - status = "okay"; - }; -@@ -739,6 +793,12 @@ u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -+ -+ port { -+ u2phy0_typec_hs: endpoint { -+ remote-endpoint = <&typec_hs>; -+ }; -+ }; - }; - - &u2phy1 { -@@ -799,7 +859,7 @@ &usbdrd3_0 { - - &usbdrd_dwc3_0 { - status = "okay"; -- dr_mode = "otg"; -+ dr_mode = "host"; - }; - - &usbdrd3_1 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Shunqian Zheng -Date: Tue, 20 Oct 2020 16:38:49 -0300 -Subject: [PATCH] arm64: dts: rockchip: add isp0 node for rk3399 - -RK3399 has two ISPs, but only isp0 was tested. -Add isp0 node in rk3399 dtsi - -Verified with: -make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml - -Signed-off-by: Shunqian Zheng -Signed-off-by: Jacob Chen -Signed-off-by: Helen Koike -Link: https://lore.kernel.org/r/20201020193850.1460644-9-helen.koike@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 4d9a2ea3e6bf..2551b238b97c 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1725,6 +1725,32 @@ vopb_mmu: iommu@ff903f00 { - status = "disabled"; - }; - -+ isp0: isp0@ff910000 { -+ compatible = "rockchip,rk3399-cif-isp"; -+ reg = <0x0 0xff910000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_ISP0>, -+ <&cru ACLK_ISP0_WRAPPER>, -+ <&cru HCLK_ISP0_WRAPPER>; -+ clock-names = "isp", "aclk", "hclk"; -+ iommus = <&isp0_mmu>; -+ phys = <&mipi_dphy_rx0>; -+ phy-names = "dphy"; -+ power-domains = <&power RK3399_PD_ISP0>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ - isp0_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Eddie Cai -Date: Tue, 20 Oct 2020 16:38:50 -0300 -Subject: [PATCH] arm64: dts: rockchip: add isp and sensors for Scarlet - -Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook - -Verified with: - make ARCH=arm64 dtbs_check - -Signed-off-by: Shunqian Zheng -Signed-off-by: Eddie Cai -Signed-off-by: Tomasz Figa -Signed-off-by: Helen Koike -Reviewed-by: Tomasz Figa -Link: https://lore.kernel.org/r/20201020193850.1460644-10-helen.koike@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 74 +++++++++++++++++++ - 1 file changed, 74 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -index 60cd1c18cd4e..beee5fbb3443 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -@@ -296,6 +296,52 @@ camera: &i2c7 { - - /* 24M mclk is shared between world and user cameras */ - pinctrl-0 = <&i2c7_xfer &test_clkout1>; -+ -+ /* Rear-facing camera */ -+ wcam: camera@36 { -+ compatible = "ovti,ov5695"; -+ reg = <0x36>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wcam_rst>; -+ -+ clocks = <&cru SCLK_TESTCLKOUT1>; -+ clock-names = "xvclk"; -+ -+ avdd-supply = <&pp2800_cam>; -+ dvdd-supply = <&pp1250_cam>; -+ dovdd-supply = <&pp1800_s0>; -+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; -+ -+ port { -+ wcam_out: endpoint { -+ remote-endpoint = <&mipi_in_wcam>; -+ data-lanes = <1 2>; -+ }; -+ }; -+ }; -+ -+ /* Front-facing camera */ -+ ucam: camera@3c { -+ compatible = "ovti,ov2685"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ucam_rst>; -+ -+ clocks = <&cru SCLK_TESTCLKOUT1>; -+ clock-names = "xvclk"; -+ -+ avdd-supply = <&pp2800_cam>; -+ dovdd-supply = <&pp1800_s0>; -+ dvdd-supply = <&pp1800_s0>; -+ reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; -+ -+ port { -+ ucam_out: endpoint { -+ remote-endpoint = <&mipi_in_ucam>; -+ data-lanes = <1>; -+ }; -+ }; -+ }; - }; - - &cdn_dp { -@@ -353,10 +399,38 @@ &io_domains { - gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ - }; - -+&isp0 { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ mipi_in_wcam: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&wcam_out>; -+ data-lanes = <1 2>; -+ }; -+ -+ mipi_in_ucam: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&ucam_out>; -+ data-lanes = <1>; -+ }; -+ }; -+ }; -+}; -+ -+&isp0_mmu { -+ status = "okay"; -+}; -+ - &max98357a { - sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - }; - -+&mipi_dphy_rx0 { -+ status = "okay"; -+}; -+ - &mipi_dsi { - status = "okay"; - clock-master; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:30 +0100 -Subject: [PATCH] arm64: dts: rockchip: fix supplies on rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 18: -vcc_lan is not controllable by software, it is just an analog LC filter. -Because of this, it can not be turned off-in-suspend. - -and on page 17: -vcc_cam and vcc_mipi are not voltage regulators, they are just switches. -So, the voltage range is not applicable. -This silences an error message about not being able to adjust the voltage. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-2-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 8 -------- - 1 file changed, 8 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 678a336010bf..06df2397bbb4 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -111,10 +111,6 @@ vcc_lan: vcc3v3-phy-regulator { - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; - }; - - vdd_log: vdd-log { -@@ -362,8 +358,6 @@ vcc_cam: SWITCH_REG1 { - regulator-name = "vcc_cam"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; -@@ -373,8 +367,6 @@ vcc_mipi: SWITCH_REG2 { - regulator-name = "vcc_mipi"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:31 +0100 -Subject: [PATCH] arm64: dts: rockchip: fix I2S conflict on rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 14: -Only two channels of I2S are connected and the extra -I2S pins are in conflict with other functions like USB power. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-3-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 06df2397bbb4..63b029a543c1 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -432,8 +432,9 @@ &i2c4 { - }; - - &i2s0 { -- rockchip,playback-channels = <8>; -- rockchip,capture-channels = <8>; -+ pinctrl-0 = <&i2s0_2ch_bus>; -+ rockchip,capture-channels = <2>; -+ rockchip,playback-channels = <2>; - status = "okay"; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:32 +0100 -Subject: [PATCH] arm64: dts: rockchip: use USB host by default on - rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 19 there is an USB Type-A receptacle being used as an USB-OTG port. - -But the Type-A connector is not valid for OTG operation, for this reason -there is a switch to select host or device role. -This is non-compliant and error prone because switching is manual. -So, use host mode as it corresponds for a Type-A receptacle. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 63b029a543c1..fb7599f07af4 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -673,7 +673,7 @@ &usbdrd3_0 { - - &usbdrd_dwc3_0 { - status = "okay"; -- dr_mode = "otg"; -+ dr_mode = "host"; - }; - - &usbdrd3_1 { diff --git a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch deleted file mode 100644 index 00c2e2fa24..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch +++ /dev/null @@ -1,662 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Demetris Ierokipides -Date: Fri, 8 Jan 2021 17:10:35 +0200 -Subject: [PATCH] ARM: dts: rockchip: add gpu node to rk3288-miqi - -Add the Mali GPU node to the MiQi device-tree. - -Signed-off-by: Demetris Ierokipides -Link: https://lore.kernel.org/r/20210108151036.36434-2-ierokipides.dem@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts -index cf54d5ffff2f..713f55e143c6 100644 ---- a/arch/arm/boot/dts/rk3288-miqi.dts -+++ b/arch/arm/boot/dts/rk3288-miqi.dts -@@ -123,6 +123,11 @@ &gmac { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ - &hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sat, 19 Dec 2020 22:05:00 +0100 -Subject: [PATCH] arm64: dts: rockchip: assign a fixed index to mmc devices on - rk3328 boards - -Recently introduced async probe on mmc devices can shuffle block IDs. -Pin them to fixed values to ease booting in environments where UUIDs -are not practical. Use newly introduced aliases for mmcblk devices from [1]. - -[1] https://patchwork.kernel.org/patch/11747669/ - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201219210500.3855-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 93c734d8a46c..17709faf651b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -27,6 +27,9 @@ aliases { - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; -+ mmc0 = &sdmmc; -+ mmc1 = &sdio; -+ mmc2 = &emmc; - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 31 Jul 2020 21:33:24 +0530 -Subject: [PATCH] arm64: defconfig: Enable REGULATOR_MP8859 - -RK3399 boards like ROC-RK3399-PC is using MP8859 DC/DC converter -for 12V supply. - -roc-rk3399-pc initially used 12V fixed regulator for this supply, -but the below commit has switched to use MP8859. - -commit <1fc61ed04d309b0b8b3562acf701ab988eee12de> "arm64: dts: rockchip: -Enable mp8859 regulator on rk3399-roc-pc" - -So, enable by default on the defconfig. - -Signed-off-by: Jagan Teki -Tested-by: Suniel Mahesh -Link: https://lore.kernel.org/r/20200731160324.142097-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 699c204090b8..9365213589bb 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -588,6 +588,7 @@ CONFIG_REGULATOR_HI6421V530=y - CONFIG_REGULATOR_HI655X=y - CONFIG_REGULATOR_MAX77620=y - CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_MP8859=y - CONFIG_REGULATOR_PCA9450=y - CONFIG_REGULATOR_PFUZE100=y - CONFIG_REGULATOR_PWM=y - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 6 Dec 2020 11:37:08 +0100 -Subject: [PATCH] ARM: dts: rockchip: add QoS register compatibles for - rk3066/rk3188 - -With the conversion of syscon.yaml minItems for compatibles -was set to 2. Current Rockchip dtsi files only use "syscon" for -QoS registers. Add Rockchip QoS compatibles for rk3066/rk3188 -to reduce notifications produced with: - -make ARCH=arm dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201206103711.7465-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3xxx.dtsi | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi -index 859a7477909f..49bcdf46d03c 100644 ---- a/arch/arm/boot/dts/rk3xxx.dtsi -+++ b/arch/arm/boot/dts/rk3xxx.dtsi -@@ -151,42 +151,42 @@ uart1: serial@10126000 { - }; - - qos_gpu: qos@1012d000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012d000 0x20>; - }; - - qos_vpu: qos@1012e000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012e000 0x20>; - }; - - qos_lcdc0: qos@1012f000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f000 0x20>; - }; - - qos_cif0: qos@1012f080 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f080 0x20>; - }; - - qos_ipp: qos@1012f100 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f100 0x20>; - }; - - qos_lcdc1: qos@1012f180 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f180 0x20>; - }; - - qos_cif1: qos@1012f200 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f200 0x20>; - }; - - qos_rga: qos@1012f280 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f280 0x20>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 6 Dec 2020 11:37:09 +0100 -Subject: [PATCH] ARM: dts: rockchip: add QoS register compatibles for rk3288 - -With the conversion of syscon.yaml minItems for compatibles -was set to 2. Current Rockchip dtsi files only use "syscon" for -QoS registers. Add Rockchip QoS compatibles for rk3288 -to reduce notifications produced with: - -make ARCH=arm dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201206103711.7465-2-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 28 ++++++++++++++-------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 68d5a58cfe88..01ea1f170f77 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1329,72 +1329,72 @@ opp-600000000 { - }; - - qos_gpu_r: qos@ffaa0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_gpu_w: qos@ffaa0080 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_vio1_vop: qos@ffad0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_vio1_isp_w0: qos@ffad0100 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_vio1_isp_w1: qos@ffad0180 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_vio0_vop: qos@ffad0400 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vio0_vip: qos@ffad0480 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vio0_iep: qos@ffad0500 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0500 0x0 0x20>; - }; - - qos_vio2_rga_r: qos@ffad0800 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0800 0x0 0x20>; - }; - - qos_vio2_rga_w: qos@ffad0880 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0880 0x0 0x20>; - }; - - qos_vio1_isp_r: qos@ffad0900 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0900 0x0 0x20>; - }; - - qos_video: qos@ffae0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_hevc_r: qos@ffaf0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - qos_hevc_w: qos@ffaf0080 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0080 0x0 0x20>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 6 Dec 2020 11:37:11 +0100 -Subject: [PATCH] arm64: dts: rockchip: add QoS register compatibles for px30 - -With the conversion of syscon.yaml minItems for compatibles -was set to 2. Current Rockchip dtsi files only use "syscon" for -QoS registers. Add Rockchip QoS compatibles for px30 -to reduce notifications produced with: - -make ARCH=arm64 dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201206103711.7465-4-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30.dtsi | 40 +++++++++++++------------- - 1 file changed, 20 insertions(+), 20 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi -index 64193292d26c..d8b673b486c9 100644 ---- a/arch/arm64/boot/dts/rockchip/px30.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi -@@ -1107,102 +1107,102 @@ vopl_mmu: iommu@ff470f00 { - }; - - qos_gmac: qos@ff518000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff518000 0x0 0x20>; - }; - - qos_gpu: qos@ff520000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff520000 0x0 0x20>; - }; - - qos_sdmmc: qos@ff52c000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff52c000 0x0 0x20>; - }; - - qos_emmc: qos@ff538000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538000 0x0 0x20>; - }; - - qos_nand: qos@ff538080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538080 0x0 0x20>; - }; - - qos_sdio: qos@ff538100 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538100 0x0 0x20>; - }; - - qos_sfc: qos@ff538180 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538180 0x0 0x20>; - }; - - qos_usb_host: qos@ff540000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff540000 0x0 0x20>; - }; - - qos_usb_otg: qos@ff540080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff540080 0x0 0x20>; - }; - - qos_isp_128: qos@ff548000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548000 0x0 0x20>; - }; - - qos_isp_rd: qos@ff548080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548080 0x0 0x20>; - }; - - qos_isp_wr: qos@ff548100 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548100 0x0 0x20>; - }; - - qos_isp_m1: qos@ff548180 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548180 0x0 0x20>; - }; - - qos_vip: qos@ff548200 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548200 0x0 0x20>; - }; - - qos_rga_rd: qos@ff550000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550000 0x0 0x20>; - }; - - qos_rga_wr: qos@ff550080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550080 0x0 0x20>; - }; - - qos_vop_m0: qos@ff550100 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550100 0x0 0x20>; - }; - - qos_vop_m1: qos@ff550180 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550180 0x0 0x20>; - }; - - qos_vpu: qos@ff558000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff558000 0x0 0x20>; - }; - - qos_vpu_r128: qos@ff558080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff558080 0x0 0x20>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Katsuhiro Suzuki -Date: Mon, 3 Aug 2020 00:42:31 +0900 -Subject: [PATCH] arm64: dts: rockchip: enable HDMI sound nodes for - rk3328-rock64 - -This patch enables HDMI sound (I2S0) and Analog sound (I2S1) which -are defined in rk3328.dtsi, and replace SPDIF nodes. - -We can use SPDIF pass-through with suitable ALSA settings and on -mpv or other media players. - - Settings: https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/filesystem/usr/share/alsa/cards/SPDIF.conf - - Ex.: mpv foo.ac3 --audio-spdif=ac3 --audio-device='alsa/SPDIF.pcm.iec958.0:SPDIF' - -[Why use simple-audio-card for SPDIF?] - -For newly adding nodes, ASoC guys recommend to use audio-graph-card. -But all other sound nodes for rk3328 have already been defined by -simple-audio-card. In this time, I chose for consistent sound nodes. - -[DMA allocation problem] - -After this patch is applied, UART2 will fail to allocate DMA resources -but UART driver can work fine without DMA. - -This error is related to the DMAC of rk3328 (pl330 or compatible). -DMAC connected to 16 DMA sources. Each sources have ID number that is -called 'Req number' in rk3328 TRM. After this patch is applied total 7 -of DMA sources will be activated as follows: - -| Req number | Source | Required | -| | | channels | -|------------+--------+-----------| -| 8, 9 | SPI0 | 2ch | -| 11, 12 | I2S0 | 2ch | -| 14, 15 | I2S1 | 2ch | -| 10 | SPDIF | 1ch | -|------------+--------+-----------| -| | Total | 7ch | -|------------+--------+-----------| -| 6, 7 | UART2 | 2ch | -> cannot get DMA channels - -Due to rk3328 DMAC specification we can use max 8 channels at same -time. If SPI0/I2S0/I2S1/SPDIF will be activated by this patch, -required DMAC channels reach to 7. So the last two channels (for -UART2) cannot get DMA resources. - -Virt-dma mechanism for pl0330 DMAC driver is needed to fix this -problem. - -Signed-off-by: Katsuhiro Suzuki -Link: https://lore.kernel.org/r/20200802154231.2639186-1-katsuhiro@katsuster.net -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 56 ++++++++----------- - 1 file changed, 24 insertions(+), 32 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index 86cfb5c50a94..c984662043da 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -84,34 +84,32 @@ standby_led: led-1 { - }; - }; - -- sound { -- compatible = "audio-graph-card"; -- label = "rockchip,rk3328"; -- dais = <&i2s1_p0 -- &spdif_p0>; -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; - }; - -- spdif-dit { -+ spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; -- -- port { -- dit_p0_0: endpoint { -- remote-endpoint = <&spdif_p0_0>; -- }; -- }; - }; - }; - -+&analog_sound { -+ status = "okay"; -+}; -+ - &codec { - mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; - status = "okay"; -- -- port@0 { -- codec_p0_0: endpoint { -- remote-endpoint = <&i2s1_p0_0>; -- }; -- }; - }; - - &cpu0 { -@@ -163,6 +161,10 @@ &hdmi { - status = "okay"; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &hdmiphy { - status = "okay"; - }; -@@ -278,16 +280,12 @@ regulator-state-mem { - }; - }; - --&i2s1 { -+&i2s0 { - status = "okay"; -+}; - -- i2s1_p0: port { -- i2s1_p0_0: endpoint { -- dai-format = "i2s"; -- mclk-fs = <256>; -- remote-endpoint = <&codec_p0_0>; -- }; -- }; -+&i2s1 { -+ status = "okay"; - }; - - &io_domains { -@@ -337,12 +335,6 @@ &sdmmc { - &spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -- -- spdif_p0: port { -- spdif_p0_0: endpoint { -- remote-endpoint = <&dit_p0_0>; -- }; -- }; - }; - - &spi0 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Katsuhiro Suzuki -Date: Mon, 10 Aug 2020 18:16:19 +0900 -Subject: [PATCH] arm64: dts: rockchip: add SPDIF node for rk3399-rockpro64 - -This patch adds 'disabled' SPDIF sound node and related settings -for rk3399-rockpro64. - -There are 2 reasons: - - All RK3399 dma-bus channels have been already used by I2S0/1/2 - - RockPro64 does not have SPDIF optical nor coaxial connector, - just have 3pins - -Signed-off-by: Katsuhiro Suzuki -Link: https://lore.kernel.org/r/20200810091619.3170534-1-katsuhiro@katsuster.net -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 27 +++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 6e553ff47534..58097245994a 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -76,6 +76,23 @@ sound { - dais = <&i2s1_p0>; - }; - -+ sound-dit { -+ compatible = "audio-graph-card"; -+ label = "rockchip,rk3399"; -+ dais = <&spdif_p0>; -+ }; -+ -+ spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ -+ port { -+ dit_p0_0: endpoint { -+ remote-endpoint = <&spdif_p0_0>; -+ }; -+ }; -+ }; -+ - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -698,6 +715,16 @@ &sdhci { - status = "okay"; - }; - -+&spdif { -+ pinctrl-0 = <&spdif_bus_1>; -+ -+ spdif_p0: port { -+ spdif_p0_0: endpoint { -+ remote-endpoint = <&dit_p0_0>; -+ }; -+ }; -+}; -+ - &spi1 { - status = "okay"; - diff --git a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch index aeabfcd4cb..4fe61149e1 100644 --- a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch @@ -784,10 +784,11 @@ diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index ae86da0dc5bd..f5eb7de10128 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile -@@ -51,3 +51,4 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o +@@ -51,4 +51,5 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o + obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o +obj-$(CONFIG_USB_DWC3_ROCKCHIP_INNO) += dwc3-rockchip-inno.o diff --git a/drivers/usb/dwc3/dwc3-rockchip-inno.c b/drivers/usb/dwc3/dwc3-rockchip-inno.c new file mode 100644 diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch index d1d06c89bd..d12a43215d 100644 --- a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch @@ -107,7 +107,7 @@ index 71a6b7b0b057..f405dd72ad93 100644 { + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + - if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS) { + if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; + unsigned int width, height; /* @@ -567,17 +567,6 @@ index 000000000000..a8123be0baa3 + - Y + - C + - Y -diff --git a/Documentation/userspace-api/media/v4l/yuv-formats.rst b/Documentation/userspace-api/media/v4l/yuv-formats.rst -index 4a05a105a9e6..e08e5dbdacea 100644 ---- a/Documentation/userspace-api/media/v4l/yuv-formats.rst -+++ b/Documentation/userspace-api/media/v4l/yuv-formats.rst -@@ -54,4 +54,6 @@ to brightness information. - pixfmt-nv16 - pixfmt-nv16m - pixfmt-nv24 -+ pixfmt-nv15 -+ pixfmt-nv20 - pixfmt-m420 diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c index 4102c373b48a..0caac755d303 100644 --- a/drivers/media/v4l2-core/v4l2-common.c diff --git a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch deleted file mode 100644 index 3ff851bdf3..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch +++ /dev/null @@ -1,465 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Wed, 23 Sep 2020 12:21:51 +0200 -Subject: [PATCH] drm/rockchip: Convert to drm_gem_object_funcs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -GEM object functions deprecate several similar callback interfaces in -struct drm_driver. This patch replaces the per-driver callbacks with -per-instance callbacks in rockchip. The only exception is gem_prime_mmap, -which is non-trivial to convert. - -v3: - * update documentation - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Daniel Vetter -Acked-by: Christian König -Link: https://patchwork.freedesktop.org/patch/msgid/20200923102159.24084-15-tzimmermann@suse.de -(cherry picked from commit 0d590af3140d0f84c537a9ad252aecc780ed7aa5) ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 5 ----- - drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 12 +++++++++++- - 2 files changed, 11 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 0f3eb392fe39..b7654f5e4225 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -212,15 +212,10 @@ static const struct file_operations rockchip_drm_driver_fops = { - static struct drm_driver rockchip_drm_driver = { - .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, - .lastclose = drm_fb_helper_lastclose, -- .gem_vm_ops = &drm_gem_cma_vm_ops, -- .gem_free_object_unlocked = rockchip_gem_free_object, - .dumb_create = rockchip_gem_dumb_create, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -- .gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table, - .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, -- .gem_prime_vmap = rockchip_gem_prime_vmap, -- .gem_prime_vunmap = rockchip_gem_prime_vunmap, - .gem_prime_mmap = rockchip_gem_mmap_buf, - .fops = &rockchip_drm_driver_fops, - .name = DRIVER_NAME, -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -index 62e5d0970525..1cf4631461c9 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -@@ -295,6 +295,14 @@ static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj) - kfree(rk_obj); - } - -+static const struct drm_gem_object_funcs rockchip_gem_object_funcs = { -+ .free = rockchip_gem_free_object, -+ .get_sg_table = rockchip_gem_prime_get_sg_table, -+ .vmap = rockchip_gem_prime_vmap, -+ .vunmap = rockchip_gem_prime_vunmap, -+ .vm_ops = &drm_gem_cma_vm_ops, -+}; -+ - static struct rockchip_gem_object * - rockchip_gem_alloc_object(struct drm_device *drm, unsigned int size) - { -@@ -309,6 +317,8 @@ static struct rockchip_gem_object * - - obj = &rk_obj->base; - -+ obj->funcs = &rockchip_gem_object_funcs; -+ - drm_gem_object_init(drm, obj, size); - - return rk_obj; -@@ -337,7 +347,7 @@ rockchip_gem_create_object(struct drm_device *drm, unsigned int size, - } - - /* -- * rockchip_gem_free_object - (struct drm_driver)->gem_free_object_unlocked -+ * rockchip_gem_free_object - (struct drm_gem_object_funcs)->free - * callback function - */ - void rockchip_gem_free_object(struct drm_gem_object *obj) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Mon, 28 Sep 2020 10:16:43 +0200 -Subject: [PATCH] drm/rockchip: Include for - drm_gem_cm_vm_ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Include to get drm_gem_cma_vm_ops. Fallout -from the recent conversion to GEM object functions. - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Sam Ravnborg -Reported-by: kernel test robot -Fixes: 0d590af3140d ("drm/rockchip: Convert to drm_gem_object_funcs") -Cc: Thomas Zimmermann -Cc: Daniel Vetter -Cc: Christian König -Cc: Sandy Huang -Cc: "Heiko Stübner" -Cc: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org -Cc: linux-rockchip@lists.infradead.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200928081643.8575-1-tzimmermann@suse.de -(cherry picked from commit 8f7db83e6abf863c6a2cfddbe7086f1e3251fdbf) ---- - drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -index 1cf4631461c9..7d5ebb10323b 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -@@ -10,6 +10,7 @@ - - #include - #include -+#include - #include - #include - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Mon, 21 Sep 2020 21:10:19 +0800 -Subject: [PATCH] drm/panfrost: simplify the return expression of - cz_ih_hw_init() - -Simplify the return expression. - -Signed-off-by: Qinglang Miao -Reviewed-by: Philipp Zabel -Reviewed-by: Steven Price -Signed-off-by: Steven Price -Link: https://patchwork.freedesktop.org/patch/msgid/20200921131019.91558-1-miaoqinglang@huawei.com -(cherry picked from commit 3c4641d4e75618fa1b5501b9ae9c19f765d75725) ---- - drivers/gpu/drm/panfrost/panfrost_device.c | 8 +------- - 1 file changed, 1 insertion(+), 7 deletions(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c -index bf7c34cfb84c..a83b2ff5837a 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_device.c -+++ b/drivers/gpu/drm/panfrost/panfrost_device.c -@@ -18,19 +18,13 @@ - - static int panfrost_reset_init(struct panfrost_device *pfdev) - { -- int err; -- - pfdev->rstc = devm_reset_control_array_get(pfdev->dev, false, true); - if (IS_ERR(pfdev->rstc)) { - dev_err(pfdev->dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc)); - return PTR_ERR(pfdev->rstc); - } - -- err = reset_control_deassert(pfdev->rstc); -- if (err) -- return err; -- -- return 0; -+ return reset_control_deassert(pfdev->rstc); - } - - static void panfrost_reset_fini(struct panfrost_device *pfdev) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Mon, 21 Sep 2020 21:10:21 +0800 -Subject: [PATCH] drm/panfrost: simplify the return expression of - panfrost_devfreq_target() - -Simplify the return expression. - -Signed-off-by: Qinglang Miao -Reviewed-by: Steven Price -Signed-off-by: Steven Price -Link: https://patchwork.freedesktop.org/patch/msgid/20200921131021.91604-1-miaoqinglang@huawei.com -(cherry picked from commit 0c5036590bde1407a6250ea027e836815353820f) ---- - drivers/gpu/drm/panfrost/panfrost_devfreq.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -index 8ab025d0035f..913eaa6d0bc6 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -@@ -29,18 +29,13 @@ static int panfrost_devfreq_target(struct device *dev, unsigned long *freq, - u32 flags) - { - struct dev_pm_opp *opp; -- int err; - - opp = devfreq_recommended_opp(dev, freq, flags); - if (IS_ERR(opp)) - return PTR_ERR(opp); - dev_pm_opp_put(opp); - -- err = dev_pm_opp_set_rate(dev, *freq); -- if (err) -- return err; -- -- return 0; -+ return dev_pm_opp_set_rate(dev, *freq); - } - - static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Rikard Falkeborn -Date: Sun, 4 Oct 2020 22:06:53 +0200 -Subject: [PATCH] drm: bridge: dw-hdmi: Constify dw_hdmi_i2s_ops - -The only usage of dw_hdmi_i2s_ops is to assign its address to the ops -field in the hdmi_codec_pdata struct, which is a const pointer. Make it -const to allow the compiler to put it in read-only memory. - -Signed-off-by: Rikard Falkeborn -Signed-off-by: Daniel Vetter -Link: https://patchwork.freedesktop.org/patch/msgid/20201004200653.14702-1-rikard.falkeborn@gmail.com -(cherry picked from commit f3d52908f6baffc21ba45058103d0226ca5cb073) ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 9fef6413741d..feb04f127b55 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -170,7 +170,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data, - return dw_hdmi_set_plugged_cb(hdmi, fn, codec_dev); - } - --static struct hdmi_codec_ops dw_hdmi_i2s_ops = { -+static const struct hdmi_codec_ops dw_hdmi_i2s_ops = { - .hw_params = dw_hdmi_i2s_hw_params, - .audio_startup = dw_hdmi_i2s_audio_startup, - .audio_shutdown = dw_hdmi_i2s_audio_shutdown, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Liu Shixin -Date: Sat, 19 Sep 2020 18:08:50 +0800 -Subject: [PATCH] drm/lima: simplify the return expression of - lima_devfreq_target - -Simplify the return expression. - -Signed-off-by: Liu Shixin -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/20200919100850.1639111-1-liushixin2@huawei.com ---- - drivers/gpu/drm/lima/lima_devfreq.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c -index bbe02817721b..5914442936ed 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -35,18 +35,13 @@ static int lima_devfreq_target(struct device *dev, unsigned long *freq, - u32 flags) - { - struct dev_pm_opp *opp; -- int err; - - opp = devfreq_recommended_opp(dev, freq, flags); - if (IS_ERR(opp)) - return PTR_ERR(opp); - dev_pm_opp_put(opp); - -- err = dev_pm_opp_set_rate(dev, *freq); -- if (err) -- return err; -- -- return 0; -+ return dev_pm_opp_set_rate(dev, *freq); - } - - static void lima_devfreq_reset(struct lima_devfreq *devfreq) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Fri, 13 Nov 2020 13:49:13 +0000 -Subject: [PATCH] drm/lima/lima_drv: Demote kernel-doc formatting abuse - -Fixes the following W=1 kernel build warning(s): - - drivers/gpu/drm/lima/lima_drv.c:264: warning: cannot understand function prototype: 'const struct drm_driver lima_drm_driver = ' - -Cc: Qiang Yu -Cc: David Airlie -Cc: Daniel Vetter -Cc: dri-devel@lists.freedesktop.org -Cc: lima@lists.freedesktop.org -Signed-off-by: Lee Jones -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/20201113134938.4004947-16-lee.jones@linaro.org ---- - drivers/gpu/drm/lima/lima_drv.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/lima/lima_drv.c b/drivers/gpu/drm/lima/lima_drv.c -index ab460121fd52..065c80c14d10 100644 ---- a/drivers/gpu/drm/lima/lima_drv.c -+++ b/drivers/gpu/drm/lima/lima_drv.c -@@ -255,7 +255,7 @@ static const struct drm_ioctl_desc lima_drm_driver_ioctls[] = { - - DEFINE_DRM_GEM_FOPS(lima_drm_driver_fops); - --/** -+/* - * Changelog: - * - * - 1.1.0 - add heap buffer support - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Fri, 13 Nov 2020 13:49:21 +0000 -Subject: [PATCH] drm/lima/lima_sched: Remove unused and unnecessary variable - 'ret' -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Fixes the following W=1 kernel build warning(s): - - drivers/gpu/drm/lima/lima_sched.c: In function ‘lima_sched_run_job’: - drivers/gpu/drm/lima/lima_sched.c:227:20: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] - -Cc: Qiang Yu -Cc: David Airlie -Cc: Daniel Vetter -Cc: Sumit Semwal -Cc: "Christian König" -Cc: dri-devel@lists.freedesktop.org -Cc: lima@lists.freedesktop.org -Cc: linux-media@vger.kernel.org -Cc: linaro-mm-sig@lists.linaro.org -Signed-off-by: Lee Jones -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/20201113134938.4004947-24-lee.jones@linaro.org ---- - drivers/gpu/drm/lima/lima_sched.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_sched.c b/drivers/gpu/drm/lima/lima_sched.c -index f6e7a88a56f1..040ea27b28ce 100644 ---- a/drivers/gpu/drm/lima/lima_sched.c -+++ b/drivers/gpu/drm/lima/lima_sched.c -@@ -223,7 +223,6 @@ static struct dma_fence *lima_sched_run_job(struct drm_sched_job *job) - struct lima_sched_pipe *pipe = to_lima_pipe(job->sched); - struct lima_device *ldev = pipe->ldev; - struct lima_fence *fence; -- struct dma_fence *ret; - int i, err; - - /* after GPU reset */ -@@ -245,7 +244,7 @@ static struct dma_fence *lima_sched_run_job(struct drm_sched_job *job) - /* for caller usage of the fence, otherwise irq handler - * may consume the fence before caller use it - */ -- ret = dma_fence_get(task->fence); -+ dma_fence_get(task->fence); - - pipe->current_task = task; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Viresh Kumar -Date: Wed, 28 Oct 2020 12:14:21 +0530 -Subject: [PATCH] drm/lima: Unconditionally call dev_pm_opp_of_remove_table() - -dev_pm_opp_of_remove_table() doesn't report any errors when it fails to -find the OPP table with error -ENODEV (i.e. OPP table not present for -the device). And we can call dev_pm_opp_of_remove_table() -unconditionally here. - -Reviewed-by: Qiang Yu -Signed-off-by: Viresh Kumar -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/c995335d16d8b4b4ff47b1273869c33e14782b32.1603867405.git.viresh.kumar@linaro.org ---- - drivers/gpu/drm/lima/lima_devfreq.c | 6 +----- - drivers/gpu/drm/lima/lima_devfreq.h | 1 - - 2 files changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c -index 5914442936ed..da7099d20bd5 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -100,10 +100,7 @@ void lima_devfreq_fini(struct lima_device *ldev) - devfreq->devfreq = NULL; - } - -- if (devfreq->opp_of_table_added) { -- dev_pm_opp_of_remove_table(ldev->dev); -- devfreq->opp_of_table_added = false; -- } -+ dev_pm_opp_of_remove_table(ldev->dev); - - if (devfreq->regulators_opp_table) { - dev_pm_opp_put_regulators(devfreq->regulators_opp_table); -@@ -157,7 +154,6 @@ int lima_devfreq_init(struct lima_device *ldev) - ret = dev_pm_opp_of_add_table(dev); - if (ret) - goto err_fini; -- ldevfreq->opp_of_table_added = true; - - lima_devfreq_reset(ldevfreq); - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.h b/drivers/gpu/drm/lima/lima_devfreq.h -index 5eed2975a375..2d9b3008ce77 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.h -+++ b/drivers/gpu/drm/lima/lima_devfreq.h -@@ -18,7 +18,6 @@ struct lima_devfreq { - struct opp_table *clkname_opp_table; - struct opp_table *regulators_opp_table; - struct thermal_cooling_device *cooling; -- bool opp_of_table_added; - - ktime_t busy_time; - ktime_t idle_time; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Viresh Kumar -Date: Fri, 6 Nov 2020 12:18:39 +0530 -Subject: [PATCH] drm/lima: dev_pm_opp_put_*() accepts NULL argument - -The dev_pm_opp_put_*() APIs now accepts a NULL opp_table pointer and so -there is no need for us to carry the extra check. Drop them. - -Reviewed-by: Qiang Yu -Signed-off-by: Viresh Kumar ---- - drivers/gpu/drm/lima/lima_devfreq.c | 13 ++++--------- - 1 file changed, 4 insertions(+), 9 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c -index da7099d20bd5..5686ad4aaf7c 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -102,15 +102,10 @@ void lima_devfreq_fini(struct lima_device *ldev) - - dev_pm_opp_of_remove_table(ldev->dev); - -- if (devfreq->regulators_opp_table) { -- dev_pm_opp_put_regulators(devfreq->regulators_opp_table); -- devfreq->regulators_opp_table = NULL; -- } -- -- if (devfreq->clkname_opp_table) { -- dev_pm_opp_put_clkname(devfreq->clkname_opp_table); -- devfreq->clkname_opp_table = NULL; -- } -+ dev_pm_opp_put_regulators(devfreq->regulators_opp_table); -+ dev_pm_opp_put_clkname(devfreq->clkname_opp_table); -+ devfreq->regulators_opp_table = NULL; -+ devfreq->clkname_opp_table = NULL; - } - - int lima_devfreq_init(struct lima_device *ldev) diff --git a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch index 244d6f5046..93bc774629 100644 --- a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch @@ -362,34 +362,6 @@ index 41edd0a421b2..4d463d50a63a 100644 DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); return ret; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lukasz Luba -Date: Tue, 5 Jan 2021 16:41:11 +0000 -Subject: [PATCH] drm/panfrost: Use delayed timer as default in devfreq profile - -Devfreq framework supports 2 modes for monitoring devices. -Use delayed timer as default instead of deferrable timer -in order to monitor the GPU status regardless of CPU idle. - -Signed-off-by: Lukasz Luba -Reviewed-by: Steven Price ---- - drivers/gpu/drm/panfrost/panfrost_devfreq.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -index 913eaa6d0bc6..17d5fa6e0b83 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -@@ -76,6 +76,7 @@ static int panfrost_devfreq_get_dev_status(struct device *dev, - } - - static struct devfreq_dev_profile panfrost_devfreq_profile = { -+ .timer = DEVFREQ_TIMER_DELAYED, - .polling_ms = 50, /* ~3 frames */ - .target = panfrost_devfreq_target, - .get_dev_status = panfrost_devfreq_get_dev_status, - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Thu, 21 Jan 2021 17:04:45 +0000 diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch index ed11c9bfea..dbf18c3562 100644 --- a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch @@ -211,15 +211,14 @@ index 69c2c079d803..65fbffc4cbc7 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -1093,7 +1093,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, - drm_gem_object_put(obj); - return ret; - } + ret = obj->funcs->mmap(obj, vma); + if (ret) + goto err_drm_gem_object_put; - WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + //WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); } else { - if (obj->funcs && obj->funcs->vm_ops) - vma->vm_ops = obj->funcs->vm_ops; - + if (!vma->vm_ops) { + ret = -EINVAL; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Mar 2018 22:17:06 +0200 diff --git a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch index d8b5058087..3663de8756 100644 --- a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch +++ b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch @@ -941,8 +941,8 @@ index 000000000000..a14fffb3ad61 + +#define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F') + -+#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(i) (V4L2_CID_MPEG_BASE + 4000 + (i)) -+#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (V4L2_CID_MPEG_BASE + 4004) ++#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(i) (V4L2_CID_CODEC_BASE + 4000 + (i)) ++#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 4004) +#define V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT 0x400 +#define V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS 0x404 + @@ -3026,13 +3026,12 @@ diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvde index c4e0ec16c285..f3578c5ea902 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,40 @@ static const u32 rkvdec_h264_decoded_fmts[] = { +@@ -162,6 +162,39 @@ static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV20, }; +static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS, + }, + { diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index cb746a6920..246dda8da6 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -65,18 +65,6 @@ index 456488f2b5ca..81529b1d8d69 100644 ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)`` Specifies the decoding mode to use. Currently exposes slice-based and frame-based decoding but new modes might be added later on. -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -index d585909bc4e2..f817c643761b 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -@@ -200,6 +200,7 @@ Compressed Formats - * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` - * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` - * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX`` - See the :ref:`associated Codec Control IDs `. - Buffers associated with this pixel format must contain the appropriate - number of macroblocks to decode a full corresponding frame. diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 7ed11f296008..a2609de88d26 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c @@ -124,12 +112,12 @@ index 1009cf0891cc..1592e52c3614 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -19,6 +19,7 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011) - #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_MPEG_BASE + 1015) - #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_MPEG_BASE + 1016) + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) + #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) @@ -26,6 +27,7 @@ #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 @@ -2901,28 +2889,24 @@ diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvde index f3578c5ea902..a44db1aa161e 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,61 @@ static const u32 rkvdec_h264_decoded_fmts[] = { +@@ -162,6 +162,57 @@ static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV20, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, + // HACK: match ffmpeg v4l2 request api hwaccel size, + // we should support variable length up to 600 slices + .cfg.dims = { 16 }, + }, + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, + }, + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, + }, + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, + }, + { diff --git a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch index b62cdf056f..c74198a69a 100644 --- a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch +++ b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch @@ -142,9 +142,9 @@ index 62b6cdc8c730..f99a873818d5 100644 obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/ +obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip/iep/ + obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += rockchip/rkisp1/ obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/ - obj-y += omap/ diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile new file mode 100644 index 000000000000..5c89b3277469 From 55fc867644bdc09497bc03c0aa3c7ad972c20336 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Thu, 13 May 2021 12:35:46 +0000 Subject: [PATCH 33/51] linux (Rockchip): update patches for 5.13 --- .../linux-0003-rockchip-from-5.13.patch | 318 ------------------ .../linux-0003-rockchip-from-next.patch | 42 --- .../linux-0004-rockchip-from-list.patch | 2 +- .../default/linux-0010-v4l2-from-list.patch | 4 +- .../default/linux-0021-drm-from-list.patch | 208 ------------ 5 files changed, 3 insertions(+), 571 deletions(-) delete mode 100644 projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-5.13.patch diff --git a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-5.13.patch b/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-5.13.patch deleted file mode 100644 index 59ab005aef..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-5.13.patch +++ /dev/null @@ -1,318 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Wed, 21 Apr 2021 18:03:36 -0300 -Subject: [PATCH] dt-bindings: vendor-prefixes: Add Tang Cheng (TCS) - -Shenzhen City Tang Cheng Technology (http://www.tctek.cn/) -is a power management IC manufacturer. - -Signed-off-by: Ezequiel Garcia ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 259faf1b382c..0ec33479df3c 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -1055,6 +1055,8 @@ patternProperties: - description: Trusted Computing Group - "^tcl,.*": - description: Toby Churchill Ltd. -+ "^tcs,.*": -+ description: Shenzhen City Tang Cheng Technology Co., Ltd. - "^technexion,.*": - description: TechNexion - "^technologic,.*": - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Wed, 21 Apr 2021 18:03:37 -0300 -Subject: [PATCH] dt-bindings: regulator: Add support for TCS4525 - -Add a compatible string to support TCS4525/TCS4526 devices, -which are compatible with Fairchild FAN53555 regulators. - -Signed-off-by: Ezequiel Garcia ---- - Documentation/devicetree/bindings/regulator/fan53555.txt | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/regulator/fan53555.txt b/Documentation/devicetree/bindings/regulator/fan53555.txt -index e7fc045281d1..013f096ac0aa 100644 ---- a/Documentation/devicetree/bindings/regulator/fan53555.txt -+++ b/Documentation/devicetree/bindings/regulator/fan53555.txt -@@ -1,8 +1,8 @@ - Binding for Fairchild FAN53555 regulators - - Required properties: -- - compatible: one of "fcs,fan53555", "fcs,fan53526", "silergy,syr827" or -- "silergy,syr828" -+ - compatible: one of "fcs,fan53555", "fcs,fan53526", "silergy,syr827", -+ "silergy,syr828" or "tcs,tcs4525". - - reg: I2C address - - Optional properties: - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Joseph Chen -Date: Wed, 21 Apr 2021 18:03:38 -0300 -Subject: [PATCH] regulator: fan53555: Add TCS4525 DCDC support - -TCS4525 main features: - -- 2.7V to 5.5V Input Voltage Range; -- 3MHz Constant Switching Frequency; -- 5A Available Load Current; -- Programmable Output Voltage: 0.6V to 1.4V in 6.25mV Steps; -- PFM/PWM Operation for Optimum Increased Efficiency; - -Signed-off-by: Joseph Chen -[Ezequiel: Forward port] -Signed-off-by: Ezequiel Garcia ---- - drivers/regulator/fan53555.c | 136 +++++++++++++++++++++++++++++++---- - 1 file changed, 122 insertions(+), 14 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index aa426183b6a1..f3918f03aaf3 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -24,6 +24,12 @@ - /* Voltage setting */ - #define FAN53555_VSEL0 0x00 - #define FAN53555_VSEL1 0x01 -+ -+#define TCS4525_VSEL0 0x11 -+#define TCS4525_VSEL1 0x10 -+#define TCS4525_TIME 0x13 -+#define TCS4525_COMMAND 0x14 -+ - /* Control register */ - #define FAN53555_CONTROL 0x02 - /* IC Type */ -@@ -49,11 +55,20 @@ - - #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ - #define FAN53526_NVOLTAGES 128 -+#define TCS4525_NVOLTAGES 127 /* Numbers of voltages */ -+ -+#define TCS_VSEL_NSEL_MASK 0x7f -+#define TCS_VSEL0_MODE (1 << 7) -+#define TCS_VSEL1_MODE (1 << 6) -+ -+#define TCS_SLEW_SHIFT 3 -+#define TCS_SLEW_MASK (0x3 < 3) - - enum fan53555_vendor { - FAN53526_VENDOR_FAIRCHILD = 0, - FAN53555_VENDOR_FAIRCHILD, - FAN53555_VENDOR_SILERGY, -+ FAN53555_VENDOR_TCS, - }; - - enum { -@@ -106,6 +121,11 @@ struct fan53555_device_info { - unsigned int mode_mask; - /* Sleep voltage cache */ - unsigned int sleep_vol_cache; -+ /* Slew rate */ -+ unsigned int slew_reg; -+ unsigned int slew_mask; -+ unsigned int slew_shift; -+ unsigned int slew_rate; - }; - - static int fan53555_set_suspend_voltage(struct regulator_dev *rdev, int uV) -@@ -189,13 +209,37 @@ static const int slew_rates[] = { - 500, - }; - -+static const int tcs_slew_rates[] = { -+ 18700, -+ 9300, -+ 4600, -+ 2300, -+}; -+ - static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) - { - struct fan53555_device_info *di = rdev_get_drvdata(rdev); - int regval = -1, i; -+ const int *slew_rate_t; -+ int slew_rate_n; - -- for (i = 0; i < ARRAY_SIZE(slew_rates); i++) { -- if (ramp <= slew_rates[i]) -+ switch (di->vendor) { -+ case FAN53526_VENDOR_FAIRCHILD: -+ case FAN53555_VENDOR_FAIRCHILD: -+ case FAN53555_VENDOR_SILERGY: -+ slew_rate_t = slew_rates; -+ slew_rate_n = ARRAY_SIZE(slew_rates); -+ break; -+ case FAN53555_VENDOR_TCS: -+ slew_rate_t = tcs_slew_rates; -+ slew_rate_n = ARRAY_SIZE(tcs_slew_rates); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < slew_rate_n; i++) { -+ if (ramp <= slew_rate_t[i]) - regval = i; - else - break; -@@ -206,8 +250,8 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) - return -EINVAL; - } - -- return regmap_update_bits(rdev->regmap, FAN53555_CONTROL, -- CTL_SLEW_MASK, regval << CTL_SLEW_SHIFT); -+ return regmap_update_bits(rdev->regmap, di->slew_reg, -+ di->slew_mask, regval << di->slew_shift); - } - - static const struct regulator_ops fan53555_regulator_ops = { -@@ -292,7 +336,9 @@ static int fan53555_voltages_setup_fairchild(struct fan53555_device_info *di) - "Chip ID %d not supported!\n", di->chip_id); - return -EINVAL; - } -- -+ di->slew_reg = FAN53555_CONTROL; -+ di->slew_mask = CTL_SLEW_MASK; -+ di->slew_shift = CTL_SLEW_SHIFT; - di->vsel_count = FAN53555_NVOLTAGES; - - return 0; -@@ -312,12 +358,29 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) - "Chip ID %d not supported!\n", di->chip_id); - return -EINVAL; - } -- -+ di->slew_reg = FAN53555_CONTROL; -+ di->slew_reg = FAN53555_CONTROL; -+ di->slew_mask = CTL_SLEW_MASK; -+ di->slew_shift = CTL_SLEW_SHIFT; - di->vsel_count = FAN53555_NVOLTAGES; - - return 0; - } - -+static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) -+{ -+ di->slew_reg = TCS4525_TIME; -+ di->slew_mask = TCS_SLEW_MASK; -+ di->slew_shift = TCS_SLEW_MASK; -+ -+ /* Init voltage range and step */ -+ di->vsel_min = 600000; -+ di->vsel_step = 6250; -+ di->vsel_count = TCS4525_NVOLTAGES; -+ -+ return 0; -+} -+ - /* For 00,01,03,05 options: - * VOUT = 0.60V + NSELx * 10mV, from 0.60 to 1.23V. - * For 04 option: -@@ -329,17 +392,41 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - int ret = 0; - - /* Setup voltage control register */ -- switch (pdata->sleep_vsel_id) { -- case FAN53555_VSEL_ID_0: -- di->sleep_reg = FAN53555_VSEL0; -- di->vol_reg = FAN53555_VSEL1; -+ switch (di->vendor) { -+ case FAN53526_VENDOR_FAIRCHILD: -+ case FAN53555_VENDOR_FAIRCHILD: -+ case FAN53555_VENDOR_SILERGY: -+ switch (pdata->sleep_vsel_id) { -+ case FAN53555_VSEL_ID_0: -+ di->sleep_reg = FAN53555_VSEL0; -+ di->vol_reg = FAN53555_VSEL1; -+ break; -+ case FAN53555_VSEL_ID_1: -+ di->sleep_reg = FAN53555_VSEL1; -+ di->vol_reg = FAN53555_VSEL0; -+ break; -+ default: -+ dev_err(di->dev, "Invalid VSEL ID!\n"); -+ return -EINVAL; -+ } - break; -- case FAN53555_VSEL_ID_1: -- di->sleep_reg = FAN53555_VSEL1; -- di->vol_reg = FAN53555_VSEL0; -+ case FAN53555_VENDOR_TCS: -+ switch (pdata->sleep_vsel_id) { -+ case FAN53555_VSEL_ID_0: -+ di->sleep_reg = TCS4525_VSEL0; -+ di->vol_reg = TCS4525_VSEL1; -+ break; -+ case FAN53555_VSEL_ID_1: -+ di->sleep_reg = TCS4525_VSEL1; -+ di->vol_reg = TCS4525_VSEL0; -+ break; -+ default: -+ dev_err(di->dev, "Invalid VSEL ID!\n"); -+ return -EINVAL; -+ } - break; - default: -- dev_err(di->dev, "Invalid VSEL ID!\n"); -+ dev_err(di->dev, "vendor %d not supported!\n", di->vendor); - return -EINVAL; - } - -@@ -362,6 +449,18 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - di->mode_reg = di->vol_reg; - di->mode_mask = VSEL_MODE; - break; -+ case FAN53555_VENDOR_TCS: -+ di->mode_reg = TCS4525_COMMAND; -+ -+ switch (pdata->sleep_vsel_id) { -+ case FAN53555_VSEL_ID_0: -+ di->mode_mask = TCS_VSEL1_MODE; -+ break; -+ case FAN53555_VSEL_ID_1: -+ di->mode_mask = TCS_VSEL0_MODE; -+ break; -+ } -+ break; - default: - dev_err(di->dev, "vendor %d not supported!\n", di->vendor); - return -EINVAL; -@@ -378,6 +477,9 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - case FAN53555_VENDOR_SILERGY: - ret = fan53555_voltages_setup_silergy(di); - break; -+ case FAN53555_VENDOR_TCS: -+ ret = fan53555_voltages_setup_tcs(di); -+ break; - default: - dev_err(di->dev, "vendor %d not supported!\n", di->vendor); - return -EINVAL; -@@ -449,6 +551,9 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { - }, { - .compatible = "silergy,syr828", - .data = (void *)FAN53555_VENDOR_SILERGY, -+ }, { -+ .compatible = "tcs,tcs4525", -+ .data = (void *)FAN53555_VENDOR_TCS - }, - { } - }; -@@ -554,6 +659,9 @@ static const struct i2c_device_id fan53555_id[] = { - }, { - .name = "syr828", - .driver_data = FAN53555_VENDOR_SILERGY -+ }, { -+ .name = "tcs4525", -+ .driver_data = FAN53555_VENDOR_TCS - }, - { }, - }; diff --git a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch b/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch index d505f26bfd..234c257969 100644 --- a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch +++ b/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch @@ -1,45 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 11 May 2021 17:13:33 -0400 -Subject: [PATCH] regulator: fan53555: fix TCS4525 voltage calulation - -The TCS4525 has 128 voltage steps. With the calculation set to 127 the -most significant bit is disregarded which leads to a miscalculation of -the voltage by about 200mv. - -Fix the calculation to end deadlock on the rk3566-quartz64 which uses -this as the cpu regulator. - -Fixes: 914df8faa7d6 ("regulator: fan53555: Add TCS4525 DCDC support") -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210511211335.2935163-2-pgwipeout@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index f3918f03aaf3..26f06f685b1b 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -55,7 +55,6 @@ - - #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ - #define FAN53526_NVOLTAGES 128 --#define TCS4525_NVOLTAGES 127 /* Numbers of voltages */ - - #define TCS_VSEL_NSEL_MASK 0x7f - #define TCS_VSEL0_MODE (1 << 7) -@@ -376,7 +375,7 @@ static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) - /* Init voltage range and step */ - di->vsel_min = 600000; - di->vsel_step = 6250; -- di->vsel_count = TCS4525_NVOLTAGES; -+ di->vsel_count = FAN53526_NVOLTAGES; - - return 0; - } - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Tue, 11 May 2021 17:13:34 -0400 diff --git a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch index 4fe61149e1..2f04777360 100644 --- a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch @@ -785,10 +785,10 @@ index ae86da0dc5bd..f5eb7de10128 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -51,4 +51,5 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o - obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o + obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o +obj-$(CONFIG_USB_DWC3_ROCKCHIP_INNO) += dwc3-rockchip-inno.o diff --git a/drivers/usb/dwc3/dwc3-rockchip-inno.c b/drivers/usb/dwc3/dwc3-rockchip-inno.c new file mode 100644 diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch index d12a43215d..a835cda740 100644 --- a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch @@ -782,7 +782,7 @@ index c81ca5c7e979..a11474214bde 100644 +{ + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + -+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS && !ctx->valid_fmt) { ++ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { + ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); + if (ctx->valid_fmt) { + struct v4l2_pix_format_mplane *pix_mp; @@ -949,7 +949,7 @@ index a11474214bde..b57a39ce4f48 100644 DIV_ROUND_UP(pix_mp->width, 16) * DIV_ROUND_UP(pix_mp->height, 16); @@ -55,19 +55,15 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS) { + if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; unsigned int width, height; - /* diff --git a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch index 93bc774629..46a5a8f046 100644 --- a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch @@ -362,211 +362,3 @@ index 41edd0a421b2..4d463d50a63a 100644 DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); return ret; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lukasz Luba -Date: Thu, 21 Jan 2021 17:04:45 +0000 -Subject: [PATCH] drm/panfrost: Add governor data with pre-defined thresholds - -The simple_ondemand devfreq governor uses two thresholds to decide about -the frequency change: upthreshold, downdifferential. These two tunable -change the behavior of the governor decision, e.g. how fast to increase -the frequency or how rapidly limit the frequency. This patch adds needed -governor data with thresholds values gathered experimentally in different -workloads. - -Signed-off-by: Lukasz Luba ---- - drivers/gpu/drm/panfrost/panfrost_devfreq.c | 10 +++++++++- - drivers/gpu/drm/panfrost/panfrost_devfreq.h | 2 ++ - 2 files changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -index 17d5fa6e0b83..53e0188ce8e8 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -@@ -130,8 +130,16 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev) - panfrost_devfreq_profile.initial_freq = cur_freq; - dev_pm_opp_put(opp); - -+ /* -+ * Setup default thresholds for the simple_ondemand governor. -+ * The values are chosen based on experiments. -+ */ -+ pfdevfreq->gov_data.upthreshold = 45; -+ pfdevfreq->gov_data.downdifferential = 5; -+ - devfreq = devm_devfreq_add_device(dev, &panfrost_devfreq_profile, -- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); -+ DEVFREQ_GOV_SIMPLE_ONDEMAND, -+ &pfdevfreq->gov_data); - if (IS_ERR(devfreq)) { - DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n"); - ret = PTR_ERR(devfreq); -diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h b/drivers/gpu/drm/panfrost/panfrost_devfreq.h -index db6ea48e21f9..1e2a4de941aa 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h -@@ -4,6 +4,7 @@ - #ifndef __PANFROST_DEVFREQ_H__ - #define __PANFROST_DEVFREQ_H__ - -+#include - #include - #include - -@@ -17,6 +18,7 @@ struct panfrost_devfreq { - struct devfreq *devfreq; - struct opp_table *regulators_opp_table; - struct thermal_cooling_device *cooling; -+ struct devfreq_simple_ondemand_data gov_data; - bool opp_of_table_added; - - ktime_t busy_time; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Fri, 5 Feb 2021 12:17:57 +0100 -Subject: [PATCH] drm/panfrost: Stay in the threaded MMU IRQ handler until - we've handled all IRQs - -Doing a hw-irq -> threaded-irq round-trip is counter-productive, stay -in the threaded irq handler as long as we can. - -v2: -* Rework the loop to avoid a goto - -Signed-off-by: Boris Brezillon -Reviewed-by: Steven Price -Reviewed-by: Rob Herring ---- - drivers/gpu/drm/panfrost/panfrost_mmu.c | 26 +++++++++++++------------ - 1 file changed, 14 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c -index 198686216317..5a3d18c05802 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_mmu.c -+++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c -@@ -585,22 +585,20 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) - { - struct panfrost_device *pfdev = data; - u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT); -- int i, ret; -+ int ret; - -- for (i = 0; status; i++) { -- u32 mask = BIT(i) | BIT(i + 16); -+ while (status) { -+ u32 as = ffs(status | (status >> 16)) - 1; -+ u32 mask = BIT(as) | BIT(as + 16); - u64 addr; - u32 fault_status; - u32 exception_type; - u32 access_type; - u32 source_id; - -- if (!(status & mask)) -- continue; -- -- fault_status = mmu_read(pfdev, AS_FAULTSTATUS(i)); -- addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(i)); -- addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(i)) << 32; -+ fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as)); -+ addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as)); -+ addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32; - - /* decode the fault status */ - exception_type = fault_status & 0xFF; -@@ -611,8 +609,8 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) - - /* Page fault only */ - ret = -1; -- if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0) -- ret = panfrost_mmu_map_fault_addr(pfdev, i, addr); -+ if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0) -+ ret = panfrost_mmu_map_fault_addr(pfdev, as, addr); - - if (ret) - /* terminal fault, print info about the fault */ -@@ -624,7 +622,7 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) - "exception type 0x%X: %s\n" - "access type 0x%X: %s\n" - "source id 0x%X\n", -- i, addr, -+ as, addr, - "TODO", - fault_status, - (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"), -@@ -633,6 +631,10 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) - source_id); - - status &= ~mask; -+ -+ /* If we received new MMU interrupts, process them before returning. */ -+ if (!status) -+ status = mmu_read(pfdev, MMU_INT_RAWSTAT); - } - - mmu_write(pfdev, MMU_INT_MASK, ~0); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Wed, 27 Jan 2021 19:40:47 +0000 -Subject: [PATCH] drm/lima: add governor data with pre-defined thresholds - -This patch adapts the panfrost pre-defined thresholds change [0] to the -lima driver to improve real-world performance. The upthreshold value has -been set to ramp GPU frequency to max freq faster (compared to panfrost) -to compensate for the lower overall performance of utgard devices. - -[0] https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1-lukasz.luba@arm.com/ - -Signed-off-by: Christian Hewitt -Reviewed-by: Lukasz Luba -Reviewed-by: Qiang Yu ---- - drivers/gpu/drm/lima/lima_devfreq.c | 10 +++++++++- - drivers/gpu/drm/lima/lima_devfreq.h | 2 ++ - 2 files changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c -index 5686ad4aaf7c..c9854315a0b5 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -163,8 +163,16 @@ int lima_devfreq_init(struct lima_device *ldev) - lima_devfreq_profile.initial_freq = cur_freq; - dev_pm_opp_put(opp); - -+ /* -+ * Setup default thresholds for the simple_ondemand governor. -+ * The values are chosen based on experiments. -+ */ -+ ldevfreq->gov_data.upthreshold = 30; -+ ldevfreq->gov_data.downdifferential = 5; -+ - devfreq = devm_devfreq_add_device(dev, &lima_devfreq_profile, -- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); -+ DEVFREQ_GOV_SIMPLE_ONDEMAND, -+ &ldevfreq->gov_data); - if (IS_ERR(devfreq)) { - dev_err(dev, "Couldn't initialize GPU devfreq\n"); - ret = PTR_ERR(devfreq); -diff --git a/drivers/gpu/drm/lima/lima_devfreq.h b/drivers/gpu/drm/lima/lima_devfreq.h -index 2d9b3008ce77..b0c7c736e81a 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.h -+++ b/drivers/gpu/drm/lima/lima_devfreq.h -@@ -4,6 +4,7 @@ - #ifndef __LIMA_DEVFREQ_H__ - #define __LIMA_DEVFREQ_H__ - -+#include - #include - #include - -@@ -18,6 +19,7 @@ struct lima_devfreq { - struct opp_table *clkname_opp_table; - struct opp_table *regulators_opp_table; - struct thermal_cooling_device *cooling; -+ struct devfreq_simple_ondemand_data gov_data; - - ktime_t busy_time; - ktime_t idle_time; From 62b72db0727c5e14837b3a576e9dd618582100dc Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 18 Jul 2021 02:08:56 +0000 Subject: [PATCH 34/51] Rockchip: linux: update patches for 5.14 --- .../linux-0001-rockchip-from-5.15.patch | 3414 +++++++++++++++++ .../linux-0002-rockchip-from-list.patch | 437 +++ .../linux-0003-rockchip-from-next.patch | 219 -- .../linux-0004-rockchip-from-list.patch | 1184 ------ .../default/linux-0010-v4l2-from-5.15.patch | 1303 +++++++ ....patch => linux-0011-v4l2-from-list.patch} | 326 +- ...t.patch => linux-0020-drm-from-list.patch} | 235 +- ...ip.patch => linux-1000-drm-rockchip.patch} | 263 +- ...p.patch => linux-1001-v4l2-rockchip.patch} | 294 +- ...c.patch => linux-1002-for-libreelec.patch} | 377 +- .../linux-2000-v4l-wip-rkvdec-vp9.patch | 718 +++- .../linux-2001-v4l-wip-rkvdec-hevc.patch | 572 ++- .../linux-2002-v4l-wip-iep-driver.patch | 25 +- 13 files changed, 6759 insertions(+), 2608 deletions(-) create mode 100644 projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch create mode 100644 projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch delete mode 100644 projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch delete mode 100644 projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch create mode 100644 projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch rename projects/Rockchip/patches/linux/default/{linux-0010-v4l2-from-list.patch => linux-0011-v4l2-from-list.patch} (73%) rename projects/Rockchip/patches/linux/default/{linux-0021-drm-from-list.patch => linux-0020-drm-from-list.patch} (60%) rename projects/Rockchip/patches/linux/default/{linux-1001-drm-rockchip.patch => linux-1000-drm-rockchip.patch} (95%) rename projects/Rockchip/patches/linux/default/{linux-1002-v4l2-rockchip.patch => linux-1001-v4l2-rockchip.patch} (86%) rename projects/Rockchip/patches/linux/default/{linux-1003-for-libreelec.patch => linux-1002-for-libreelec.patch} (66%) diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch new file mode 100644 index 0000000000..7a2165e1be --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch @@ -0,0 +1,3414 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 13 Jul 2021 17:47:13 +0800 +Subject: [PATCH] clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036 + +Add dt-binding for hclk_sfc on rk3036 + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20210713094718.1709-1-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + include/dt-bindings/clock/rk3036-cru.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h +index 35a5a01f9697..a96a9870ad59 100644 +--- a/include/dt-bindings/clock/rk3036-cru.h ++++ b/include/dt-bindings/clock/rk3036-cru.h +@@ -81,6 +81,7 @@ + #define HCLK_OTG0 449 + #define HCLK_OTG1 450 + #define HCLK_NANDC 453 ++#define HCLK_SFC 454 + #define HCLK_SDMMC 456 + #define HCLK_SDIO 457 + #define HCLK_EMMC 459 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Tue, 13 Jul 2021 17:44:50 +0800 +Subject: [PATCH] clk: rockchip: rk3036: fix up the sclk_sfc parent error + +Choose the correct pll + +Signed-off-by: Elaine Zhang +Signed-off-by: Jon Lin +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20210713094456.23288-5-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3036.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c +index 614845cc5b4a..c38ad4ec8746 100644 +--- a/drivers/clk/rockchip/clk-rk3036.c ++++ b/drivers/clk/rockchip/clk-rk3036.c +@@ -121,6 +121,7 @@ PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; + PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; + + PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" }; ++PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" }; + + PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; + PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; +@@ -340,7 +341,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { + RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS, + RK2928_CLKGATE_CON(10), 4, GFLAGS), + +- COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, ++ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0, + RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, + RK2928_CLKGATE_CON(10), 5, GFLAGS), + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Tue, 13 Jul 2021 17:47:14 +0800 +Subject: [PATCH] clk: rockchip: Add support for hclk_sfc on rk3036 + +Add support for the bus clock for the serial flash controller on the +rk3036. Taken from the Rockchip BSP kernel but not tested on real +hardware (as I lack a 3036 based SoC to test). + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20210713094718.1709-2-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3036.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c +index c38ad4ec8746..d644bc155ec6 100644 +--- a/drivers/clk/rockchip/clk-rk3036.c ++++ b/drivers/clk/rockchip/clk-rk3036.c +@@ -404,7 +404,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { + GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), + GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), + GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), +- GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), ++ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), + GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), + + /* pclk_peri gates */ + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 10 Jun 2021 14:56:13 -0300 +Subject: [PATCH] dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Convert the rockchip,rk3399-cru binding to DT schema format. +Tested with +ARCH=arm64 make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +ARCH=arm64 make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml + +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Rob Herring +Link: https://lore.kernel.org/r/20210610175613.167601-1-nfraprado@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../bindings/clock/rockchip,rk3399-cru.txt | 68 -------------- + .../bindings/clock/rockchip,rk3399-cru.yaml | 92 +++++++++++++++++++ + 2 files changed, 92 insertions(+), 68 deletions(-) + delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt + create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml + +diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt +deleted file mode 100644 +index 3bc56fae90ac..000000000000 +--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt ++++ /dev/null +@@ -1,68 +0,0 @@ +-* Rockchip RK3399 Clock and Reset Unit +- +-The RK3399 clock controller generates and supplies clock to various +-controllers within the SoC and also implements a reset controller for SoC +-peripherals. +- +-Required Properties: +- +-- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" +-- compatible: CRU should be "rockchip,rk3399-cru" +-- reg: physical base address of the controller and length of memory mapped +- region. +-- #clock-cells: should be 1. +-- #reset-cells: should be 1. +- +-Optional Properties: +- +-- rockchip,grf: phandle to the syscon managing the "general register files". +- It is used for GRF muxes, if missing any muxes present in the GRF will not +- be available. +- +-Each clock is assigned an identifier and client nodes can use this identifier +-to specify the clock which they consume. All available clocks are defined as +-preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be +-used in device tree sources. Similar macros exist for the reset sources in +-these files. +- +-External clocks: +- +-There are several clocks that are generated outside the SoC. It is expected +-that they are defined using standard clock bindings with following +-clock-output-names: +- - "xin24m" - crystal input - required, +- - "xin32k" - rtc clock - optional, +- - "clkin_gmac" - external GMAC clock - optional, +- - "clkin_i2s" - external I2S clock - optional, +- - "pclkin_cif" - external ISP clock - optional, +- - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 +- - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 +- +-Example: Clock controller node: +- +- pmucru: pmu-clock-controller@ff750000 { +- compatible = "rockchip,rk3399-pmucru"; +- reg = <0x0 0xff750000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- cru: clock-controller@ff760000 { +- compatible = "rockchip,rk3399-cru"; +- reg = <0x0 0xff760000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +-Example: UART controller node that consumes the clock generated by the clock +- controller: +- +- uart0: serial@ff1a0000 { +- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff180000 0x0 0x100>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +new file mode 100644 +index 000000000000..72b286a1beba +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +@@ -0,0 +1,92 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip RK3399 Clock and Reset Unit ++ ++maintainers: ++ - Xing Zheng ++ - Heiko Stuebner ++ ++description: | ++ The RK3399 clock controller generates and supplies clock to various ++ controllers within the SoC and also implements a reset controller for SoC ++ peripherals. ++ Each clock is assigned an identifier and client nodes can use this identifier ++ to specify the clock which they consume. All available clocks are defined as ++ preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be ++ used in device tree sources. Similar macros exist for the reset sources in ++ these files. ++ There are several clocks that are generated outside the SoC. It is expected ++ that they are defined using standard clock bindings with following ++ clock-output-names: ++ - "xin24m" - crystal input - required, ++ - "xin32k" - rtc clock - optional, ++ - "clkin_gmac" - external GMAC clock - optional, ++ - "clkin_i2s" - external I2S clock - optional, ++ - "pclkin_cif" - external ISP clock - optional, ++ - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 ++ - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3399-pmucru ++ - rockchip,rk3399-cru ++ ++ reg: ++ maxItems: 1 ++ ++ "#clock-cells": ++ const: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++ clocks: ++ minItems: 1 ++ ++ assigned-clocks: ++ minItems: 1 ++ maxItems: 64 ++ ++ assigned-clock-parents: ++ minItems: 1 ++ maxItems: 64 ++ ++ assigned-clock-rates: ++ minItems: 1 ++ maxItems: 64 ++ ++ rockchip,grf: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: > ++ phandle to the syscon managing the "general register files". It is used ++ for GRF muxes, if missing any muxes present in the GRF will not be ++ available. ++ ++required: ++ - compatible ++ - reg ++ - "#clock-cells" ++ - "#reset-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pmucru: pmu-clock-controller@ff750000 { ++ compatible = "rockchip,rk3399-pmucru"; ++ reg = <0xff750000 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ - | ++ cru: clock-controller@ff760000 { ++ compatible = "rockchip,rk3399-cru"; ++ reg = <0xff760000 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 28 Jul 2021 14:00:28 -0400 +Subject: [PATCH] clk: rockchip: drop GRF dependency for rk3328/rk3036 pll + types + +The rk3036/rk3328 pll types were converted to checking the lock status +via the internal register in january 2020, so don't need the grf +reference since then. + +But it was forgotten to remove grf check when deciding between the +pll rate ops (read-only vs. read-write), so a clock driver without +the needed grf reference might've been put into the read-only mode +just because the grf reference was missing. + +This affected the rk356x that needs to reclock certain plls at boot. + +Fix this by removing the check for the grf for selecting the utilized +operations. + +Suggested-by: Heiko Stuebner +Fixes: 7f6ffbb885d1 ("clk: rockchip: convert rk3036 pll type to use internal lock status") +Signed-off-by: Peter Geis +[adjusted the commit message, adjusted the fixes tag] +Link: https://lore.kernel.org/r/20210728180034.717953-3-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-pll.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c +index fe937bcdb487..f7827b3b7fc1 100644 +--- a/drivers/clk/rockchip/clk-pll.c ++++ b/drivers/clk/rockchip/clk-pll.c +@@ -940,7 +940,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, + switch (pll_type) { + case pll_rk3036: + case pll_rk3328: +- if (!pll->rate_table || IS_ERR(ctx->grf)) ++ if (!pll->rate_table) + init.ops = &rockchip_rk3036_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3036_pll_clk_ops; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Yunhao Tian +Date: Wed, 21 Jul 2021 20:48:16 +0800 +Subject: [PATCH] clk: rockchip: make rk3308 ddrphy4x clock critical + +Currently, no driver support for DDR memory controller (DMC) is present, +as a result, no driver is explicitly consuming the ddrphy clock. This means +that VPLL1 (parent of ddr clock) will be shutdown if we enable +and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX). +If VPLL1 is disabled, the whole system will freeze, because the DDR +controller will lose its clock. So, it's necessary to prevent VPLL1 from +shutting down, by marking the ddrphy4x CLK_IS_CRITICAL. + +This bug was discovered when I was porting rockchip_i2s_tdm driver to +mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip +SoCs without DMC driver may need the same patch. If this applies to +other devices, please let us know. + +Signed-off-by: Yunhao Tian +Link: https://lore.kernel.org/r/BYAPR20MB24886765F888A9705CBEB70789E39@BYAPR20MB2488.namprd20.prod.outlook.com +[adapted subject, changed to add the clock to the critical list] +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3308.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c +index 2c3bd0c749f2..db3396c3e6e9 100644 +--- a/drivers/clk/rockchip/clk-rk3308.c ++++ b/drivers/clk/rockchip/clk-rk3308.c +@@ -911,6 +911,7 @@ static const char *const rk3308_critical_clocks[] __initconst = { + "hclk_audio", + "pclk_audio", + "sclk_ddrc", ++ "clk_ddrphy4x", + }; + + static void __init rk3308_clk_init(struct device_node *np) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Sun, 11 Jul 2021 16:34:30 +0200 +Subject: [PATCH] arm64: dts: rockchip: remove interrupt-names from iommu nodes + +The iommu driver gets the interrupts by platform_get_irq(), +so remove interrupt-names property from iommu nodes. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210711143430.14347-2-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 ----- + arch/arm64/boot/dts/rockchip/rk3368.dtsi | 5 ----- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 -------- + 3 files changed, 18 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 8c821acb21ff..becc1c61b182 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -623,7 +623,6 @@ h265e_mmu: iommu@ff330200 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff330200 0 0x100>; + interrupts = ; +- interrupt-names = "h265e_mmu"; + clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -634,7 +633,6 @@ vepu_mmu: iommu@ff340800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff340800 0x0 0x40>; + interrupts = ; +- interrupt-names = "vepu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -656,7 +654,6 @@ vpu_mmu: iommu@ff350800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff350800 0x0 0x40>; + interrupts = ; +- interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -667,7 +664,6 @@ rkvdec_mmu: iommu@ff360480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; + interrupts = ; +- interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -700,7 +696,6 @@ vop_mmu: iommu@ff373f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff373f00 0x0 0x100>; + interrupts = ; +- interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +index 4c64fbefb483..4217897cd454 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +@@ -709,7 +709,6 @@ iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x100>; + interrupts = ; +- interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -721,7 +720,6 @@ isp_mmu: iommu@ff914000 { + reg = <0x0 0xff914000 0x0 0x100>, + <0x0 0xff915000 0x0 0x100>; + interrupts = ; +- interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -733,7 +731,6 @@ vop_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff930300 0x0 0x100>; + interrupts = ; +- interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -745,7 +742,6 @@ hevc_mmu: iommu@ff9a0440 { + reg = <0x0 0xff9a0440 0x0 0x40>, + <0x0 0xff9a0480 0x0 0x40>; + interrupts = ; +- interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -757,7 +753,6 @@ vpu_mmu: iommu@ff9a0800 { + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = , + ; +- interrupt-names = "vepu_mmu", "vdpu_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 3871c7fd83b0..aa5d7dca3432 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1240,7 +1240,6 @@ vpu: video-codec@ff650000 { + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; +- interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; +@@ -1251,7 +1250,6 @@ vpu_mmu: iommu@ff650800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff650800 0x0 0x40>; + interrupts = ; +- interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -1273,7 +1271,6 @@ vdec_mmu: iommu@ff660480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; + interrupts = ; +- interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VDU>; +@@ -1284,7 +1281,6 @@ iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; +- interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -1666,7 +1662,6 @@ vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = ; +- interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPL>; +@@ -1723,7 +1718,6 @@ vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = ; +- interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPB>; +@@ -1761,7 +1755,6 @@ isp0_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = ; +- interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -1773,7 +1766,6 @@ isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + interrupts = ; +- interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Sun, 11 Jul 2021 16:59:00 +0200 +Subject: [PATCH] arm64: dts: rockchip: rename flash nodenames + +Nodes with compatible "jedec,spi-nor" are now checked with +jedec,spi-nor.yaml and mtd.yaml. The pattern is now +"^flash(@.*)?$", so change that for the boards with a +Rockchip SoC. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210711145900.15443-1-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index 1b0f7e4551ea..f69a38f42d2d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -345,7 +345,7 @@ &spdif { + &spi0 { + status = "okay"; + +- spiflash@0 { ++ flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +index c1bcc8ca3769..e310b51ab578 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +@@ -543,7 +543,7 @@ &spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&spi1_sleep>; + +- spiflash@0 { ++ flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Thu, 1 Jul 2021 16:41:09 +0200 +Subject: [PATCH] arm64: dts: rockchip: remove clock_in_out from gmac2phy node + in rk3318-a95x-z2.dts + +Recently a clock_in_out property was added to the gmac2phy node +in rk3328.dtsi, so now the clock_in_out in rk3318-a95x-z2.dts +can be removed. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210701144110.12333-1-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +index 763cf9b4620e..d41f786b2f4b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +@@ -185,7 +185,6 @@ &gmac2phy { + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; +- clock_in_out = "output"; + status = "okay"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Thu, 1 Jul 2021 16:41:10 +0200 +Subject: [PATCH] arm64: dts: rockchip: remove ddc-i2c-scl-* properties from + rk3318-a95x-z2.dts + +The ddc-i2c-scl-* properties in the hdmi node are +not in use in the mainline kernel, so remove them. + +Reported-by: Alex Bee +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210701144110.12333-2-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +index d41f786b2f4b..43c928ac98f0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +@@ -193,8 +193,6 @@ &gpu { + }; + + &hdmi { +- ddc-i2c-scl-high-time-ns = <9625>; +- ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Liang Chen +Date: Thu, 24 Jun 2021 19:47:17 +0800 +Subject: [PATCH] dt-bindings: arm: rockchip: add rk3568 compatible string to + pmu.yaml + +add "rockchip,rk3568-pmu", "syscon", "simple-mfd" for pmu nodes on a +rk3568 platform to pmu.ymal. + +Signed-off-by: Liang Chen +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210624114719.1685-2-cl@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +index 53115b92d17f..ceb15cea77e2 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +@@ -23,6 +23,7 @@ select: + - rockchip,rk3066-pmu + - rockchip,rk3288-pmu + - rockchip,rk3399-pmu ++ - rockchip,rk3568-pmu + + required: + - compatible +@@ -35,6 +36,7 @@ properties: + - rockchip,rk3066-pmu + - rockchip,rk3288-pmu + - rockchip,rk3399-pmu ++ - rockchip,rk3568-pmu + - const: syscon + - const: simple-mfd + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Liang Chen +Date: Thu, 24 Jun 2021 21:10:27 +0800 +Subject: [PATCH] arm64: dts: rockchip: add pmu and qos nodes for rk3568 + +Add the power-management and QoS nodes to the core rk3568 dtsi. + +Signed-off-by: Liang Chen +Link: https://lore.kernel.org/r/20210624131027.3719-1-cl@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++ + 1 file changed, 229 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +index d225e6a45d5c..618849186c39 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -257,6 +258,99 @@ uart0: serial@fdd50000 { + status = "disabled"; + }; + ++ pmu: power-management@fdd90000 { ++ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; ++ reg = <0x0 0xfdd90000 0x0 0x1000>; ++ ++ power: power-controller { ++ compatible = "rockchip,rk3568-power-controller"; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* These power domains are grouped by VD_GPU */ ++ power-domain@RK3568_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU_PRE>, ++ <&cru PCLK_GPU_PRE>; ++ pm_qos = <&qos_gpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ /* These power domains are grouped by VD_LOGIC */ ++ power-domain@RK3568_PD_VI { ++ reg = ; ++ clocks = <&cru HCLK_VI>, ++ <&cru PCLK_VI>; ++ pm_qos = <&qos_isp>, ++ <&qos_vicap0>, ++ <&qos_vicap1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VO { ++ reg = ; ++ clocks = <&cru HCLK_VO>, ++ <&cru PCLK_VO>, ++ <&cru ACLK_VOP_PRE>; ++ pm_qos = <&qos_hdcp>, ++ <&qos_vop_m0>, ++ <&qos_vop_m1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RGA { ++ reg = ; ++ clocks = <&cru HCLK_RGA_PRE>, ++ <&cru PCLK_RGA_PRE>; ++ pm_qos = <&qos_ebc>, ++ <&qos_iep>, ++ <&qos_jpeg_dec>, ++ <&qos_jpeg_enc>, ++ <&qos_rga_rd>, ++ <&qos_rga_wr>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VPU { ++ reg = ; ++ clocks = <&cru HCLK_VPU_PRE>; ++ pm_qos = <&qos_vpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVDEC { ++ clocks = <&cru HCLK_RKVDEC_PRE>; ++ reg = ; ++ pm_qos = <&qos_rkvdec>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVENC { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC_PRE>; ++ pm_qos = <&qos_rkvenc_rd_m0>, ++ <&qos_rkvenc_rd_m1>, ++ <&qos_rkvenc_wr_m0>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_PIPE { ++ reg = ; ++ clocks = <&cru PCLK_PIPE>; ++ pm_qos = <&qos_pcie2x1>, ++ <&qos_pcie3x1>, ++ <&qos_pcie3x2>, ++ <&qos_sata0>, ++ <&qos_sata1>, ++ <&qos_sata2>, ++ <&qos_usb3_0>, ++ <&qos_usb3_1>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; +@@ -271,6 +365,141 @@ sdmmc2: mmc@fe000000 { + status = "disabled"; + }; + ++ qos_gpu: qos@fe128000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe128000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m0: qos@fe138080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138080 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m1: qos@fe138100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138100 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_wr_m0: qos@fe138180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138180 0x0 0x20>; ++ }; ++ ++ qos_isp: qos@fe148000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148000 0x0 0x20>; ++ }; ++ ++ qos_vicap0: qos@fe148080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148080 0x0 0x20>; ++ }; ++ ++ qos_vicap1: qos@fe148100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148100 0x0 0x20>; ++ }; ++ ++ qos_vpu: qos@fe150000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe150000 0x0 0x20>; ++ }; ++ ++ qos_ebc: qos@fe158000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158000 0x0 0x20>; ++ }; ++ ++ qos_iep: qos@fe158100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158100 0x0 0x20>; ++ }; ++ ++ qos_jpeg_dec: qos@fe158180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158180 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc: qos@fe158200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158200 0x0 0x20>; ++ }; ++ ++ qos_rga_rd: qos@fe158280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158280 0x0 0x20>; ++ }; ++ ++ qos_rga_wr: qos@fe158300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158300 0x0 0x20>; ++ }; ++ ++ qos_npu: qos@fe180000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe180000 0x0 0x20>; ++ }; ++ ++ qos_pcie2x1: qos@fe190000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190000 0x0 0x20>; ++ }; ++ ++ qos_pcie3x1: qos@fe190080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190080 0x0 0x20>; ++ }; ++ ++ qos_pcie3x2: qos@fe190100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190100 0x0 0x20>; ++ }; ++ ++ qos_sata0: qos@fe190200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190200 0x0 0x20>; ++ }; ++ ++ qos_sata1: qos@fe190280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190280 0x0 0x20>; ++ }; ++ ++ qos_sata2: qos@fe190300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190300 0x0 0x20>; ++ }; ++ ++ qos_usb3_0: qos@fe190380 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190380 0x0 0x20>; ++ }; ++ ++ qos_usb3_1: qos@fe190400 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190400 0x0 0x20>; ++ }; ++ ++ qos_rkvdec: qos@fe198000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe198000 0x0 0x20>; ++ }; ++ ++ qos_hdcp: qos@fe1a8000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8000 0x0 0x20>; ++ }; ++ ++ qos_vop_m0: qos@fe1a8080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8080 0x0 0x20>; ++ }; ++ ++ qos_vop_m1: qos@fe1a8100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8100 0x0 0x20>; ++ }; ++ + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Fri, 9 Jul 2021 16:01:25 +0800 +Subject: [PATCH] dt-bindings: add doc for Firefly ROC-RK3328-PC + +Add devicetree binding documentation for the Firefly ROC-RK3328-PC. + +Signed-off-by: Levin Du +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210709080126.17045-2-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 6546b015fc62..7ef902f45b38 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -115,6 +115,11 @@ properties: + - const: firefly,roc-rk3328-cc + - const: rockchip,rk3328 + ++ - description: Firefly ROC-RK3328-PC ++ items: ++ - const: firefly,roc-rk3328-pc ++ - const: rockchip,rk3328 ++ + - description: Firefly ROC-RK3399-PC + items: + - enum: + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Fri, 9 Jul 2021 16:01:26 +0800 +Subject: [PATCH] arm64: dts: rockchip: add support for Firefly ROC-RK3328-PC + +ROC-RK3328-PC is the board inside the portable Firefly Station M1 +Geek PC. As a redesign after the ROC-RK3328-CC, it uses TypeC as +power input and OTG port, embedded with eMMC 5.1 storage and a +SDIO WiFi/BT chip (RTL8723DS). + +- Rockchip RK3328 SoC +- 2/4GB LPDDR3 RAM +- 16/32/64/128GB eMMC 5.1 +- TF card slot +- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 (Power/OTG) +- HDMI +- Gigabit Ethernet +- WiFi: RTL8723DS +- Audio: RK3328 +- Key: Power, Reset, Recovery +- LED: POWER, USER +- IR + +Signed-off-by: Levin Du +Link: https://lore.kernel.org/r/20210709080126.17045-3-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 110 ++++++++++++++++++ + 2 files changed, 111 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 7fdb41de01ec..46652b6d7c4d 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +new file mode 100644 +index 000000000000..e3e3984d01d4 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +@@ -0,0 +1,110 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd ++ ++/dts-v1/; ++ ++#include ++ ++#include "rk3328-roc-cc.dts" ++ ++/ { ++ model = "Firefly ROC-RK3328-PC"; ++ compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1750000>; ++ ++ /* This button is unpopulated out of the factory. */ ++ button-recovery { ++ label = "Recovery"; ++ linux,code = ; ++ press-threshold-microvolt = <10000>; ++ }; ++ }; ++ ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; ++ linux,rc-map-name = "rc-khadas"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_int>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&codec { ++ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ ++&pinctrl { ++ ir { ++ ir_int: ir-int { ++ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmcio { ++ sdio_per_pin: sdio-per-pin { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ wifi { ++ wifi_en: wifi-en { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_host_wake: wifi-host-wake { ++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; ++ }; ++ ++ bt_rst: bt-rst { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_en: bt-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmic_int_l { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++}; ++ ++&rk805 { ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++}; ++ ++&saradc { ++ vref-supply = <&vcc_18>; ++ status = "okay"; ++}; ++ ++&usb20_host_drv { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++}; ++ ++&vcc_host1_5v { ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++}; ++ ++&vcc_sdio { ++ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio_per_pin>; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Mon, 28 Jun 2021 11:54:01 +0800 +Subject: [PATCH] dt-bindings: add doc for Firefly ROC-RK3399-PC-PLUS + +Add devicetree binding documentation for the Firefly ROC-RK3399-PC-PLUS. + +Signed-off-by: Levin Du +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210628035402.16812-2-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 7ef902f45b38..ce7785fe3598 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -127,6 +127,12 @@ properties: + - firefly,roc-rk3399-pc-mezzanine + - const: rockchip,rk3399 + ++ - description: Firefly ROC-RK3399-PC-PLUS ++ items: ++ - enum: ++ - firefly,roc-rk3399-pc-plus ++ - const: rockchip,rk3399 ++ + - description: FriendlyElec NanoPi R2S + items: + - const: friendlyarm,nanopi-r2s + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Mon, 28 Jun 2021 11:54:02 +0800 +Subject: [PATCH] arm64: dts: rockchip: add support for Firefly + ROC-RK3399-PC-PLUS + +ROC-RK3399-PC-PLUS is the board inside the portable Firefly Station P1 Geek +PC. As a redesign after the ROC-RK3399-PC, it uses DC-12V as power input +and spares a USB 3 host port. It is also equipped with a USB WiFi chip and +audio codec without the mezzanine board. + +- Rockchip RK3399 SoC +- 4GB LPDDR4 RAM +- 16MB SPI-Flash +- eMMC slot +- TF card slot +- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 +- HDMI +- Gigabit Ethernet +- WiFi: RTL8723DU +- Audio: ES8388 +- Key: Recovery +- LED: WORK, DIY +- IR + +Signed-off-by: Kongxin Deng +Signed-off-by: Levin Du +Link: https://lore.kernel.org/r/20210628035402.16812-3-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-roc-pc-plus.dts | 218 ++++++++++++++++++ + 2 files changed, 219 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 46652b6d7c4d..2890756c294c 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +new file mode 100644 +index 000000000000..5a2661ae0131 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +@@ -0,0 +1,218 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd ++ */ ++ ++/dts-v1/; ++#include "rk3399-roc-pc.dtsi" ++ ++/* ++ * Notice: ++ * 1. rk3399-roc-pc-plus is powered by dc_12v directly. ++ * 2. rk3399-roc-pc-plus has only vcc_bus_typec0 in schematic, which is coresponding ++ * to vcc_vbus_typec1 in rk3399-roc-pc. ++ * For simplicity, reserve the node name of vcc_vbus_typec1. ++ * 3. vcc5v0_host is actually 2 regulators (host0, 1) controlled by the same gpio. ++ */ ++ ++/delete-node/ &fusb1; ++/delete-node/ &hub_rst; ++/delete-node/ &mp8859; ++/delete-node/ &vcc_sys_en; ++/delete-node/ &vcc_vbus_typec0; ++/delete-node/ &yellow_led; ++ ++/ { ++ model = "Firefly ROC-RK3399-PC-PLUS Board"; ++ compatible = "firefly,roc-rk3399-pc-plus", "rockchip,rk3399"; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ es8388-sound { ++ compatible = "simple-audio-card"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det_pin>; ++ simple-audio-card,name = "rockchip,es8388-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ simple-audio-card,routing = ++ "LINPUT1", "Mic Jack", ++ "Headphone Amp INL", "LOUT2", ++ "Headphone Amp INR", "ROUT2", ++ "Headphones", "Headphone Amp OUTL", ++ "Headphones", "Headphone Amp OUTR"; ++ simple-audio-card,hp-det-gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; ++ simple-audio-card,aux-devs = <&headphones_amp>; ++ simple-audio-card,pin-switches = "Headphones"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&es8388>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ }; ++ }; ++ ++ gpio-fan { ++ #cooling-cells = <2>; ++ compatible = "gpio-fan"; ++ gpio-fan,speed-map = <0 0 3000 1>; ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ /delete-node/ gpio-keys; ++ ++ /* not amplifier, used as switcher only */ ++ headphones_amp: headphones-amp { ++ compatible = "simple-audio-amplifier"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ear_ctl_pin>; ++ enable-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ sound-name-prefix = "Headphone Amp"; ++ VCC-supply = <&vcca3v0_codec>; ++ }; ++ ++ ir-receiver { ++ linux,rc-map-name = "rc-khadas"; ++ }; ++ ++ leds { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; ++ }; ++}; ++ ++&fusb0 { ++ vbus-supply = <&vcc_vbus_typec1>; ++}; ++ ++&i2c0 { ++ hym8563: hym8563@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ }; ++}; ++ ++&i2c1 { ++ es8388: es8388@11 { ++ compatible = "everest,es8388"; ++ reg = <0x11>; ++ clock-names = "mclk"; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++/* <4 RK_PA0 1 &pcfg_pull_none> is used as i2s_8ch_mclk_pin */ ++&i2s0_8ch_bus { ++ rockchip,pins = ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ <3 RK_PD3 1 &pcfg_pull_none>, ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ <3 RK_PD6 1 &pcfg_pull_none>, ++ <3 RK_PD7 1 &pcfg_pull_none>; ++}; ++ ++&i2s1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; ++ rockchip,playback-channels = <2>; ++ rockchip,capture-channels = <2>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ es8388 { ++ ear_ctl_pin: ear-ctl-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; ++ }; ++ ++ hp_det_pin: hp-det-pin { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ i2s1 { ++ i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { ++ rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ phy-supply = <&vcc_vbus_typec1>; ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&vcc_sys { ++ /* vcc_sys is fixed, not controlled by any gpio */ ++ /delete-property/ gpio; ++ /delete-property/ pinctrl-names; ++ /delete-property/ pinctrl-0; ++}; ++ ++&vcc5v0_host { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dennis Gilmore +Date: Wed, 14 Jul 2021 21:56:29 -0500 +Subject: [PATCH] arm64: dts: rockchip: set stdout-path on helios64 + +set the default output path to uart2 + +Signed-off-by: Dennis Gilmore +Link: https://lore.kernel.org/r/20210715025635.70452-2-dgilmore@redhat.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index 738cfd21df3e..d911a9a4f0f0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -43,6 +43,10 @@ avdd_1v8_s0: avdd-1v8-s0 { + vin-supply = <&vcc3v3_sys_s3>; + }; + ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dennis Gilmore +Date: Wed, 14 Jul 2021 21:56:30 -0500 +Subject: [PATCH] arm64: dts: rockchip: add SPI support to helios64 + +add SPI support for the helios64, u-boot can live in spi1, spi2 is user +accessible, spi5 is for the sata controller rom. +https://wiki.kobol.io/helios64/spi/ + +Signed-off-by: Dennis Gilmore +Link: https://lore.kernel.org/r/20210715025635.70452-3-dgilmore@redhat.com +Signed-off-by: Heiko Stuebner +--- + .../dts/rockchip/rk3399-kobol-helios64.dts | 24 +++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index d911a9a4f0f0..b275b4790211 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -21,6 +21,9 @@ / { + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi5 = &spi5; + }; + + avdd_0v9_s0: avdd-0v9-s0 { +@@ -473,6 +476,27 @@ &sdmmc { + status = "okay"; + }; + ++&spi1 { ++ status = "okay"; ++ ++ spiflash: flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <25000000>; ++ status = "okay"; ++ m25p,fast-read; ++ }; ++}; ++ ++/* UEXT connector */ ++&spi2 { ++ status = "okay"; ++}; ++ ++&spi5 { ++ status = "okay"; ++}; ++ + &tcphy1 { + /* phy for &usbdrd_dwc3_1 */ + status = "okay"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dennis Gilmore +Date: Wed, 14 Jul 2021 21:56:31 -0500 +Subject: [PATCH] arm64: dts: rockchip: enable tsadc on helios64 + +Enable the tsadc thermal controller on the helios64 + +Signed-off-by: Dennis Gilmore +Link: https://lore.kernel.org/r/20210715025635.70452-4-dgilmore@redhat.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index b275b4790211..63c7681843da 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -502,6 +502,14 @@ &tcphy1 { + status = "okay"; + }; + ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ + &u2phy1 { + status = "okay"; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Simon Xue +Date: Mon, 5 Jul 2021 09:26:10 +0800 +Subject: [PATCH] arm64: dts: rockchip: add saradc node for rk3568 + +Add the core dt-node for the rk3568's saradc. + +Signed-off-by: Simon Xue +Link: https://lore.kernel.org/r/20210705012610.3831-1-xxm@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +index 618849186c39..11825909c5db 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -754,6 +754,18 @@ uart9: serial@fe6d0000 { + status = "disabled"; + }; + ++ saradc: saradc@fe720000 { ++ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; ++ reg = <0x0 0xfe720000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; ++ clock-names = "saradc", "apb_pclk"; ++ resets = <&cru SRST_P_SARADC>; ++ reset-names = "saradc-apb"; ++ #io-channel-cells = <1>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Matthias Brugger +Date: Thu, 15 Jul 2021 18:41:01 +0200 +Subject: [PATCH] arm64: dts: rockchip: Disable CDN DP on Pinebook Pro + +The CDN DP needs a PHY and a extcon to work correctly. But no extcon is +provided by the device-tree, which leads to an error: +cdn-dp fec00000.dp: [drm:cdn_dp_probe [rockchipdrm]] *ERROR* missing extcon or phy +cdn-dp: probe of fec00000.dp failed with error -22 + +Disable the CDN DP to make graphic work on the Pinebook Pro. + +Reported-by: Guillaume Gardet +Signed-off-by: Matthias Brugger +Link: https://lore.kernel.org/r/20210715164101.11486-1-matthias.bgg@kernel.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 2b5f001ff4a6..9e5d07f5712e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -385,10 +385,6 @@ mains_charger: dc-charger { + }; + }; + +-&cdn_dp { +- status = "okay"; +-}; +- + &cpu_b0 { + cpu-supply = <&vdd_cpu_b>; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:52 +0200 +Subject: [PATCH] dt-bindings: Add doc for ROCK Pi 4 A+ and B+ + +ROCK Pi 4 got 2 more variants called A+ and B+. +Add the dt-bindings documentation for it. + +Signed-off-by: Alex Bee +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210618181256.27992-2-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index ce7785fe3598..f051e3330302 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -471,11 +471,13 @@ properties: + - const: radxa,rock + - const: rockchip,rk3188 + +- - description: Radxa ROCK Pi 4A/B/C ++ - description: Radxa ROCK Pi 4A/A+/B/B+/C + items: + - enum: + - radxa,rockpi4a ++ - radxa,rockpi4a-plus + - radxa,rockpi4b ++ - radxa,rockpi4b-plus + - radxa,rockpi4c + - const: radxa,rockpi4 + - const: rockchip,rk3399 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:53 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399 ROCK Pi 4A+ board + +ROCK Pi 4A+ board is the successor of ROCK Pi 4A board. + +Differences to the original version are +- has RK3399 OP1 SoC revision +- has eMMC (16 or 32 GB) soldered on board (no changes required, + since it is enabled in rk3399-rock-pi-4.dtsi) +- dev boards have SPI flash soldered, but as per manufacturer response, + this won't be the case for mass production boards + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-3-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts | 14 ++++++++++++++ + 2 files changed, 15 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 2890756c294c..5e2e852c5f69 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts +new file mode 100644 +index 000000000000..281a04b2f5e9 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Akash Gajjar ++ * Copyright (c) 2019 Pragnesh Patel ++ */ ++ ++/dts-v1/; ++#include "rk3399-rock-pi-4.dtsi" ++#include "rk3399-op1-opp.dtsi" ++ ++/ { ++ model = "Radxa ROCK Pi 4A+"; ++ compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:54 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399 ROCK Pi 4B+ board + +ROCK Pi 4B+ board is the successor of ROCK Pi 4B board. + +Differences to the original version are +- has RK3399 OP1 SoC revision +- has eMMC (16 or 32 GB) soldered on board (no changes required, + since it is enabled in rk3399-rock-pi-4.dtsi) +- dev boards have SPI flash soldered, but as per manufacturer response, + this won't be the case for mass production boards + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-4-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3399-rock-pi-4b-plus.dts | 47 +++++++++++++++++++ + 2 files changed, 48 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 5e2e852c5f69..b1c3f32ac11a 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +new file mode 100644 +index 000000000000..dfad13d2ab24 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Akash Gajjar ++ * Copyright (c) 2019 Pragnesh Patel ++ */ ++ ++/dts-v1/; ++#include "rk3399-rock-pi-4.dtsi" ++#include "rk3399-op1-opp.dtsi" ++ ++/ { ++ model = "Radxa ROCK Pi 4B+"; ++ compatible = "radxa,rockpi4b-plus", "radxa,rockpi4", "rockchip,rk3399"; ++ ++ aliases { ++ mmc2 = &sdio0; ++ }; ++}; ++ ++&sdio0 { ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ compatible = "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_l>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:55 +0200 +Subject: [PATCH] arm64: dts: rockchip: add ES8316 codec for ROCK Pi 4 + +ROCK Pi 4 boards have the codec connected to i2s0 and it is accessible +via i2c1 address 0x11. +Add an audio-graph-card for it. + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-5-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +index b28888ea9262..b49072af4014 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -36,6 +36,12 @@ sdio_pwrseq: sdio-pwrseq { + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + ++ sound { ++ compatible = "audio-graph-card"; ++ label = "Analog"; ++ dais = <&i2s0_p0>; ++ }; ++ + vcc12v_dcin: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; +@@ -422,6 +428,20 @@ &i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; ++ ++ es8316: codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ clock-names = "mclk"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_p0_0>; ++ }; ++ }; ++ }; + }; + + &i2c3 { +@@ -441,6 +461,14 @@ &i2s0 { + rockchip,capture-channels = <2>; + rockchip,playback-channels = <2>; + status = "okay"; ++ ++ i2s0_p0: port { ++ i2s0_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; + }; + + &i2s1 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:56 +0200 +Subject: [PATCH] arm64: dts: rockchip: add SPDIF node for ROCK Pi 4 + +Add a SPDIF audio-graph-card to ROCK Pi 4 device tree. + +It's not enabled by default since all dma channels are used by +the (already) enabled i2s0/1/2 and the pin is muxed with GPIO4_C5 +which might be in use already. +If enabled SPDIF_TX will be available at pin #15. + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-6-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +index b49072af4014..98136c88fa49 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -42,6 +42,23 @@ sound { + dais = <&i2s0_p0>; + }; + ++ sound-dit { ++ compatible = "audio-graph-card"; ++ label = "SPDIF"; ++ dais = <&spdif_p0>; ++ }; ++ ++ spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ dit_p0_0: endpoint { ++ remote-endpoint = <&spdif_p0_0>; ++ }; ++ }; ++ }; ++ + vcc12v_dcin: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; +@@ -631,6 +648,15 @@ &sdhci { + status = "okay"; + }; + ++&spdif { ++ ++ spdif_p0: port { ++ spdif_p0_0: endpoint { ++ remote-endpoint = <&dit_p0_0>; ++ }; ++ }; ++}; ++ + &tcphy0 { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Thu, 22 Jul 2021 09:39:55 +0200 +Subject: [PATCH] arm64: dts: rockchip: add csi-dphy to px30 + +Add the CSI dphy node to the core px30 devicetree for later use +with the rkisp. + +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20210722073955.1192168-1-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 248ebb61aa79..6e53a4cc75e6 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -864,6 +864,19 @@ dsi_dphy: phy@ff2e0000 { + status = "disabled"; + }; + ++ csi_dphy: phy@ff2f0000 { ++ compatible = "rockchip,px30-csi-dphy"; ++ reg = <0x0 0xff2f0000 0x0 0x4000>; ++ clocks = <&cru PCLK_MIPICSIPHY>; ++ clock-names = "pclk"; ++ #phy-cells = <0>; ++ power-domains = <&power PX30_PD_VI>; ++ resets = <&cru SRST_MIPICSIPHY_P>; ++ reset-names = "apb"; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ + usb20_otg: usb@ff300000 { + compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Wed, 10 Feb 2021 12:10:18 +0100 +Subject: [PATCH] arm64: dts: rockchip: add #phy-cells to mipi-dsi1 on rk3399 + +The dsi controller includes access to the dphy which might be used +not only for dsi output but also for csi input on dsi1, so add the +necessary #phy-cells to allow it to be used as phy. + +Signed-off-by: Heiko Stuebner +Tested-by: Sebastian Fricke +Acked-by: Helen Koike +Link: https://lore.kernel.org/r/20210210111020.2476369-5-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index aa5d7dca3432..8d68775365a3 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1870,6 +1870,7 @@ mipi_dsi1: mipi@ff968000 { + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; ++ #phy-cells = <0>; + status = "disabled"; + + ports { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Wed, 10 Feb 2021 12:10:19 +0100 +Subject: [PATCH] arm64: dts: rockchip: add cif clk-control pinctrl for rk3399 + +This enables variant a of the clkout signal for camera applications +and also the cifclkin pinctrl setting. + +Signed-off-by: Heiko Stuebner +Tested-by: Sebastian Fricke +Acked-by: Helen Koike +Link: https://lore.kernel.org/r/20210210111020.2476369-6-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 8d68775365a3..493042bc20c0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -2107,6 +2107,18 @@ clk_32k: clk-32k { + }; + }; + ++ cif { ++ cif_clkin: cif-clkin { ++ rockchip,pins = ++ <2 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ cif_clkouta: cif-clkouta { ++ rockchip,pins = ++ <2 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ }; ++ + edp { + edp_hpd: edp-hpd { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Wed, 10 Feb 2021 12:10:20 +0100 +Subject: [PATCH] arm64: dts: rockchip: add isp1 node on rk3399 + +ISP1 is supplied by the tx1rx1 dphy, that is controlled from +inside the dsi1 controller, so include the necessary phy-link +for it. + +Signed-off-by: Heiko Stuebner +Tested-by: Sebastian Fricke +Acked-by: Helen Koike +Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 493042bc20c0..9db9484ca38f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1762,6 +1762,32 @@ isp0_mmu: iommu@ff914000 { + rockchip,disable-mmu-reset; + }; + ++ isp1: isp1@ff920000 { ++ compatible = "rockchip,rk3399-cif-isp"; ++ reg = <0x0 0xff920000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_ISP1>, ++ <&cru ACLK_ISP1_WRAPPER>, ++ <&cru HCLK_ISP1_WRAPPER>; ++ clock-names = "isp", "aclk", "hclk"; ++ iommus = <&isp1_mmu>; ++ phys = <&mipi_dsi1>; ++ phy-names = "dphy"; ++ power-domains = <&power RK3399_PD_ISP1>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ }; ++ + isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Wed, 28 Jul 2021 20:00:40 -0300 +Subject: [PATCH] arm64: dts: rockchip: Add VPU support for the PX30 + +The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. +Describe these two entities in device-tree. + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Ezequiel Garcia +Link: https://lore.kernel.org/r/20210728230040.17368-1-ezequiel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 6e53a4cc75e6..185bcc5c16ac 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -1037,6 +1037,28 @@ gpu: gpu@ff400000 { + status = "disabled"; + }; + ++ vpu: video-codec@ff442000 { ++ compatible = "rockchip,px30-vpu"; ++ reg = <0x0 0xff442000 0x0 0x800>; ++ interrupts = , ++ ; ++ interrupt-names = "vepu", "vdpu"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vpu_mmu>; ++ power-domains = <&power PX30_PD_VPU>; ++ }; ++ ++ vpu_mmu: iommu@ff442800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff442800 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ power-domains = <&power PX30_PD_VPU>; ++ }; ++ + dsi: dsi@ff450000 { + compatible = "rockchip,px30-mipi-dsi"; + reg = <0x0 0xff450000 0x0 0x10000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Thu, 12 Aug 2021 17:47:52 +0800 +Subject: [PATCH] dt-bindings: arm: rockchip: Add gru-scarlet-dumo board + +Dumo is another variant of Scarlet, also known as the ASUS Chromebook +Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a +specific calibration variant for the WiFi module. + +Add an entry for the board compatibles. + +Signed-off-by: Chen-Yu Tsai +Link: https://lore.kernel.org/r/20210812094753.2359087-2-wenst@chromium.org +Signed-off-by: Heiko Stuebner +--- + .../devicetree/bindings/arm/rockchip.yaml | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index f051e3330302..517f435cbc6e 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -298,6 +298,34 @@ properties: + - const: google,veyron + - const: rockchip,rk3288 + ++ - description: Google Scarlet - Dumo (ASUS Chromebook Tablet CT100) ++ items: ++ - const: google,scarlet-rev15-sku0 ++ - const: google,scarlet-rev15 ++ - const: google,scarlet-rev14-sku0 ++ - const: google,scarlet-rev14 ++ - const: google,scarlet-rev13-sku0 ++ - const: google,scarlet-rev13 ++ - const: google,scarlet-rev12-sku0 ++ - const: google,scarlet-rev12 ++ - const: google,scarlet-rev11-sku0 ++ - const: google,scarlet-rev11 ++ - const: google,scarlet-rev10-sku0 ++ - const: google,scarlet-rev10 ++ - const: google,scarlet-rev9-sku0 ++ - const: google,scarlet-rev9 ++ - const: google,scarlet-rev8-sku0 ++ - const: google,scarlet-rev8 ++ - const: google,scarlet-rev7-sku0 ++ - const: google,scarlet-rev7 ++ - const: google,scarlet-rev6-sku0 ++ - const: google,scarlet-rev6 ++ - const: google,scarlet-rev5-sku0 ++ - const: google,scarlet-rev5 ++ - const: google,scarlet ++ - const: google,gru ++ - const: rockchip,rk3399 ++ + - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku7 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dan Johansen +Date: Fri, 6 Aug 2021 00:04:27 +0200 +Subject: [PATCH] arm64: dts: rockchip: Setup USB typec port as datarole on for + Pinebook Pro + +Some chargers try to put the charged device into device data +role. Before this commit this condition caused the tcpm state machine to +issue a hard reset due to a capability missmatch. + +Signed-off-by: Dan Johansen +Link: https://lore.kernel.org/r/20210805220426.2693062-1-strit@manjaro.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 9e5d07f5712e..dae8c252bc2b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -707,7 +707,7 @@ fusb0: fusb30x@22 { + + connector { + compatible = "usb-c-connector"; +- data-role = "host"; ++ data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 30 Jul 2021 11:17:27 -0400 +Subject: [PATCH] arm64: dts: rockchip: add thermal fan control to rockpro64 + +The rockpro64 had a fan node since +commit 5882d65c1691 ("arm64: dts: rockchip: Add PWM fan for RockPro64") +however it was never tied into the thermal driver for automatic control. + +Add the links to the thermal node to permit the kernel to handle this +automatically. +Borrowed from the (rk3399-khadas-edge.dtsi). + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210730151727.729822-1-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 29 +++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +index 6bff8db7d33e..83db4ca67334 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +@@ -69,6 +69,7 @@ diy_led: led-1 { + + fan: pwm-fan { + compatible = "pwm-fan"; ++ cooling-levels = <0 100 150 200 255>; + #cooling-cells = <2>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm1 0 50000 0>; +@@ -245,6 +246,34 @@ &cpu_b1 { + cpu-supply = <&vdd_cpu_b>; + }; + ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map2 { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map3 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &emmc_phy { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:45:43 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add SFC to PX30 + +Add a devicetree entry for the Rockchip SFC for the PX30 SOC. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Link: https://lore.kernel.org/r/20210812134546.31340-4-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 185bcc5c16ac..64f643145688 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -987,6 +987,18 @@ emmc: mmc@ff390000 { + status = "disabled"; + }; + ++ sfc: spi@ff3a0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xff3a0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; ++ pinctrl-names = "default"; ++ power-domains = <&power PX30_PD_MMC_NAND>; ++ status = "disabled"; ++ }; ++ + nfc: nand-controller@ff3b0000 { + compatible = "rockchip,px30-nfc"; + reg = <0x0 0xff3b0000 0x0 0x4000>; +@@ -2008,6 +2020,32 @@ flash_bus8: flash-bus8 { + }; + }; + ++ sfc { ++ sfc_bus4: sfc-bus4 { ++ rockchip,pins = ++ <1 RK_PA0 3 &pcfg_pull_none>, ++ <1 RK_PA1 3 &pcfg_pull_none>, ++ <1 RK_PA2 3 &pcfg_pull_none>, ++ <1 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_bus2: sfc-bus2 { ++ rockchip,pins = ++ <1 RK_PA0 3 &pcfg_pull_none>, ++ <1 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_cs0: sfc-cs0 { ++ rockchip,pins = ++ <1 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_clk: sfc-clk { ++ rockchip,pins = ++ <1 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ }; ++ + lcdc { + lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:46:38 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add SFC to RK3308 + +Add a devicetree entry for the Rockchip SFC for the RK3308 SOC. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Link: https://lore.kernel.org/r/20210812134639.31586-1-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 ++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index a185901aba9a..ce6f4a28d169 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -731,6 +731,17 @@ gmac: ethernet@ff4e0000 { + status = "disabled"; + }; + ++ sfc: spi@ff4c0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xff4c0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ + cru: clock-controller@ff500000 { + compatible = "rockchip,rk3308-cru"; + reg = <0x0 0xff500000 0x0 0x1000>; +@@ -1004,6 +1015,32 @@ flash_bus8: flash-bus8 { + }; + }; + ++ sfc { ++ sfc_bus4: sfc-bus4 { ++ rockchip,pins = ++ <3 RK_PA0 3 &pcfg_pull_none>, ++ <3 RK_PA1 3 &pcfg_pull_none>, ++ <3 RK_PA2 3 &pcfg_pull_none>, ++ <3 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_bus2: sfc-bus2 { ++ rockchip,pins = ++ <3 RK_PA0 3 &pcfg_pull_none>, ++ <3 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_cs0: sfc-cs0 { ++ rockchip,pins = ++ <3 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_clk: sfc-clk { ++ rockchip,pins = ++ <3 RK_PA5 3 &pcfg_pull_none>; ++ }; ++ }; ++ + gmac { + rmii_pins: rmii-pins { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:46:39 +0800 +Subject: [PATCH] arm64: dts: rockchip: Enable SFC for Odroid Go Advance + +This enables the Rockchip Serial Flash Controller for the Odroid Go +Advance. Note that while the attached SPI NOR flash and the controller +both support quad read mode, only 2 of the required 4 pins are present. +The rx bus width is set to 2 for this reason, and tx bus width is set +to 1 for compatibility reasons. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Link: https://lore.kernel.org/r/20210812134639.31586-2-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +index 7fc674a99a6c..35218c2771a2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +@@ -517,6 +517,22 @@ &sdmmc { + status = "okay"; + }; + ++&sfc { ++ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <108000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ + &tsadc { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:45:41 +0800 +Subject: [PATCH] spi: rockchip-sfc: Bindings for Rockchip serial flash + controller + +Add bindings for the Rockchip serial flash controller. New device +specific parameter of rockchip,sfc-no-dma included in documentation. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Tested-by: Peter Geis +Link: https://lore.kernel.org/r/20210812134546.31340-2-jon.lin@rock-chips.com +Signed-off-by: Mark Brown +--- + .../devicetree/bindings/spi/rockchip-sfc.yaml | 91 +++++++++++++++++++ + 1 file changed, 91 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml + +diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml +new file mode 100644 +index 000000000000..339fb39529f3 +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml +@@ -0,0 +1,91 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip Serial Flash Controller (SFC) ++ ++maintainers: ++ - Heiko Stuebner ++ - Chris Morgan ++ ++allOf: ++ - $ref: spi-controller.yaml# ++ ++properties: ++ compatible: ++ const: rockchip,sfc ++ description: ++ The rockchip sfc controller is a standalone IP with version register, ++ and the driver can handle all the feature difference inside the IP ++ depending on the version register. ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Bus Clock ++ - description: Module Clock ++ ++ clock-names: ++ items: ++ - const: clk_sfc ++ - const: hclk_sfc ++ ++ power-domains: ++ maxItems: 1 ++ ++ rockchip,sfc-no-dma: ++ description: Disable DMA and utilize FIFO mode only ++ type: boolean ++ ++patternProperties: ++ "^flash@[0-3]$": ++ type: object ++ properties: ++ reg: ++ minimum: 0 ++ maximum: 3 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ sfc: spi@ff3a0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0xff3a0000 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; ++ pinctrl-names = "default"; ++ power-domains = <&power PX30_PD_MMC_NAND>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <108000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <2>; ++ }; ++ }; ++ ++... + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:45:42 +0800 +Subject: [PATCH] spi: rockchip-sfc: add rockchip serial flash controller + +Add the rockchip serial flash controller (SFC) driver. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Tested-by: Peter Geis +Tested-by: Chris Morgan +Link: https://lore.kernel.org/r/20210812134546.31340-3-jon.lin@rock-chips.com +Signed-off-by: Mark Brown +--- + drivers/spi/Kconfig | 12 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-rockchip-sfc.c | 694 +++++++++++++++++++++++++++++++++ + 3 files changed, 707 insertions(+) + create mode 100644 drivers/spi/spi-rockchip-sfc.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index e71a4c514f7b..83e352b0c8f9 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -658,6 +658,18 @@ config SPI_ROCKCHIP + The main usecase of this controller is to use spi flash as boot + device. + ++config SPI_ROCKCHIP_SFC ++ tristate "Rockchip Serial Flash Controller (SFC)" ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ depends on HAS_IOMEM && HAS_DMA ++ help ++ This enables support for Rockchip serial flash controller. This ++ is a specialized controller used to access SPI flash on some ++ Rockchip SOCs. ++ ++ ROCKCHIP SFC supports DMA and PIO modes. When DMA is not available, ++ the driver automatically falls back to PIO mode. ++ + config SPI_RB4XX + tristate "Mikrotik RB4XX SPI master" + depends on SPI_MASTER && ATH79 +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 13e54c45e9df..699db95c8441 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -95,6 +95,7 @@ obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o + obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o + obj-$(CONFIG_SPI_QUP) += spi-qup.o + obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o ++obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o + obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o + obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o + obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o +diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c +new file mode 100644 +index 000000000000..7c4d47fe80c2 +--- /dev/null ++++ b/drivers/spi/spi-rockchip-sfc.c +@@ -0,0 +1,694 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip Serial Flash Controller Driver ++ * ++ * Copyright (c) 2017-2021, Rockchip Inc. ++ * Author: Shawn Lin ++ * Chris Morgan ++ * Jon Lin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* System control */ ++#define SFC_CTRL 0x0 ++#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) ++#define SFC_CTRL_CMD_BITS_SHIFT 8 ++#define SFC_CTRL_ADDR_BITS_SHIFT 10 ++#define SFC_CTRL_DATA_BITS_SHIFT 12 ++ ++/* Interrupt mask */ ++#define SFC_IMR 0x4 ++#define SFC_IMR_RX_FULL BIT(0) ++#define SFC_IMR_RX_UFLOW BIT(1) ++#define SFC_IMR_TX_OFLOW BIT(2) ++#define SFC_IMR_TX_EMPTY BIT(3) ++#define SFC_IMR_TRAN_FINISH BIT(4) ++#define SFC_IMR_BUS_ERR BIT(5) ++#define SFC_IMR_NSPI_ERR BIT(6) ++#define SFC_IMR_DMA BIT(7) ++ ++/* Interrupt clear */ ++#define SFC_ICLR 0x8 ++#define SFC_ICLR_RX_FULL BIT(0) ++#define SFC_ICLR_RX_UFLOW BIT(1) ++#define SFC_ICLR_TX_OFLOW BIT(2) ++#define SFC_ICLR_TX_EMPTY BIT(3) ++#define SFC_ICLR_TRAN_FINISH BIT(4) ++#define SFC_ICLR_BUS_ERR BIT(5) ++#define SFC_ICLR_NSPI_ERR BIT(6) ++#define SFC_ICLR_DMA BIT(7) ++ ++/* FIFO threshold level */ ++#define SFC_FTLR 0xc ++#define SFC_FTLR_TX_SHIFT 0 ++#define SFC_FTLR_TX_MASK 0x1f ++#define SFC_FTLR_RX_SHIFT 8 ++#define SFC_FTLR_RX_MASK 0x1f ++ ++/* Reset FSM and FIFO */ ++#define SFC_RCVR 0x10 ++#define SFC_RCVR_RESET BIT(0) ++ ++/* Enhanced mode */ ++#define SFC_AX 0x14 ++ ++/* Address Bit number */ ++#define SFC_ABIT 0x18 ++ ++/* Interrupt status */ ++#define SFC_ISR 0x1c ++#define SFC_ISR_RX_FULL_SHIFT BIT(0) ++#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) ++#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) ++#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) ++#define SFC_ISR_TX_FINISH_SHIFT BIT(4) ++#define SFC_ISR_BUS_ERR_SHIFT BIT(5) ++#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) ++#define SFC_ISR_DMA_SHIFT BIT(7) ++ ++/* FIFO status */ ++#define SFC_FSR 0x20 ++#define SFC_FSR_TX_IS_FULL BIT(0) ++#define SFC_FSR_TX_IS_EMPTY BIT(1) ++#define SFC_FSR_RX_IS_EMPTY BIT(2) ++#define SFC_FSR_RX_IS_FULL BIT(3) ++#define SFC_FSR_TXLV_MASK GENMASK(12, 8) ++#define SFC_FSR_TXLV_SHIFT 8 ++#define SFC_FSR_RXLV_MASK GENMASK(20, 16) ++#define SFC_FSR_RXLV_SHIFT 16 ++ ++/* FSM status */ ++#define SFC_SR 0x24 ++#define SFC_SR_IS_IDLE 0x0 ++#define SFC_SR_IS_BUSY 0x1 ++ ++/* Raw interrupt status */ ++#define SFC_RISR 0x28 ++#define SFC_RISR_RX_FULL BIT(0) ++#define SFC_RISR_RX_UNDERFLOW BIT(1) ++#define SFC_RISR_TX_OVERFLOW BIT(2) ++#define SFC_RISR_TX_EMPTY BIT(3) ++#define SFC_RISR_TRAN_FINISH BIT(4) ++#define SFC_RISR_BUS_ERR BIT(5) ++#define SFC_RISR_NSPI_ERR BIT(6) ++#define SFC_RISR_DMA BIT(7) ++ ++/* Version */ ++#define SFC_VER 0x2C ++#define SFC_VER_3 0x3 ++#define SFC_VER_4 0x4 ++#define SFC_VER_5 0x5 ++ ++/* Delay line controller resiter */ ++#define SFC_DLL_CTRL0 0x3C ++#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) ++#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU ++#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU ++ ++/* Master trigger */ ++#define SFC_DMA_TRIGGER 0x80 ++#define SFC_DMA_TRIGGER_START 1 ++ ++/* Src or Dst addr for master */ ++#define SFC_DMA_ADDR 0x84 ++ ++/* Length control register extension 32GB */ ++#define SFC_LEN_CTRL 0x88 ++#define SFC_LEN_CTRL_TRB_SEL 1 ++#define SFC_LEN_EXT 0x8C ++ ++/* Command */ ++#define SFC_CMD 0x100 ++#define SFC_CMD_IDX_SHIFT 0 ++#define SFC_CMD_DUMMY_SHIFT 8 ++#define SFC_CMD_DIR_SHIFT 12 ++#define SFC_CMD_DIR_RD 0 ++#define SFC_CMD_DIR_WR 1 ++#define SFC_CMD_ADDR_SHIFT 14 ++#define SFC_CMD_ADDR_0BITS 0 ++#define SFC_CMD_ADDR_24BITS 1 ++#define SFC_CMD_ADDR_32BITS 2 ++#define SFC_CMD_ADDR_XBITS 3 ++#define SFC_CMD_TRAN_BYTES_SHIFT 16 ++#define SFC_CMD_CS_SHIFT 30 ++ ++/* Address */ ++#define SFC_ADDR 0x104 ++ ++/* Data */ ++#define SFC_DATA 0x108 ++ ++/* The controller and documentation reports that it supports up to 4 CS ++ * devices (0-3), however I have only been able to test a single CS (CS 0) ++ * due to the configuration of my device. ++ */ ++#define SFC_MAX_CHIPSELECT_NUM 4 ++ ++/* The SFC can transfer max 16KB - 1 at one time ++ * we set it to 15.5KB here for alignment. ++ */ ++#define SFC_MAX_IOSIZE_VER3 (512 * 31) ++ ++/* DMA is only enabled for large data transmission */ ++#define SFC_DMA_TRANS_THRETHOLD (0x40) ++ ++/* Maximum clock values from datasheet suggest keeping clock value under ++ * 150MHz. No minimum or average value is suggested. ++ */ ++#define SFC_MAX_SPEED (150 * 1000 * 1000) ++ ++struct rockchip_sfc { ++ struct device *dev; ++ void __iomem *regbase; ++ struct clk *hclk; ++ struct clk *clk; ++ u32 frequency; ++ /* virtual mapped addr for dma_buffer */ ++ void *buffer; ++ dma_addr_t dma_buffer; ++ struct completion cp; ++ bool use_dma; ++ u32 max_iosize; ++ u16 version; ++}; ++ ++static int rockchip_sfc_reset(struct rockchip_sfc *sfc) ++{ ++ int err; ++ u32 status; ++ ++ writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); ++ ++ err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, ++ !(status & SFC_RCVR_RESET), 20, ++ jiffies_to_usecs(HZ)); ++ if (err) ++ dev_err(sfc->dev, "SFC reset never finished\n"); ++ ++ /* Still need to clear the masked interrupt from RISR */ ++ writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR); ++ ++ dev_dbg(sfc->dev, "reset\n"); ++ ++ return err; ++} ++ ++static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) ++{ ++ return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); ++} ++ ++static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) ++{ ++ return SFC_MAX_IOSIZE_VER3; ++} ++ ++static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask) ++{ ++ u32 reg; ++ ++ /* Enable transfer complete interrupt */ ++ reg = readl(sfc->regbase + SFC_IMR); ++ reg &= ~mask; ++ writel(reg, sfc->regbase + SFC_IMR); ++} ++ ++static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask) ++{ ++ u32 reg; ++ ++ /* Disable transfer finish interrupt */ ++ reg = readl(sfc->regbase + SFC_IMR); ++ reg |= mask; ++ writel(reg, sfc->regbase + SFC_IMR); ++} ++ ++static int rockchip_sfc_init(struct rockchip_sfc *sfc) ++{ ++ writel(0, sfc->regbase + SFC_CTRL); ++ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); ++ rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF); ++ if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) ++ writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); ++ ++ return 0; ++} ++ ++static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) ++{ ++ int ret = 0; ++ u32 status; ++ ++ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, ++ status & SFC_FSR_TXLV_MASK, 0, ++ timeout_us); ++ if (ret) { ++ dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); ++ ++ ret = -ETIMEDOUT; ++ } ++ ++ return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; ++} ++ ++static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) ++{ ++ int ret = 0; ++ u32 status; ++ ++ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, ++ status & SFC_FSR_RXLV_MASK, 0, ++ timeout_us); ++ if (ret) { ++ dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); ++ ++ ret = -ETIMEDOUT; ++ } ++ ++ return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; ++} ++ ++static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) ++{ ++ if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { ++ /* ++ * SFC not support output DUMMY cycles right after CMD cycles, so ++ * treat it as ADDR cycles. ++ */ ++ op->addr.nbytes = op->dummy.nbytes; ++ op->addr.buswidth = op->dummy.buswidth; ++ op->addr.val = 0xFFFFFFFFF; ++ ++ op->dummy.nbytes = 0; ++ } ++} ++ ++static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, ++ struct spi_mem *mem, ++ const struct spi_mem_op *op, ++ u32 len) ++{ ++ u32 ctrl = 0, cmd = 0; ++ ++ /* set CMD */ ++ cmd = op->cmd.opcode; ++ ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); ++ ++ /* set ADDR */ ++ if (op->addr.nbytes) { ++ if (op->addr.nbytes == 4) { ++ cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; ++ } else if (op->addr.nbytes == 3) { ++ cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; ++ } else { ++ cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; ++ writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); ++ } ++ ++ ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); ++ } ++ ++ /* set DUMMY */ ++ if (op->dummy.nbytes) { ++ if (op->dummy.buswidth == 4) ++ cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; ++ else if (op->dummy.buswidth == 2) ++ cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; ++ else ++ cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; ++ } ++ ++ /* set DATA */ ++ if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ ++ writel(len, sfc->regbase + SFC_LEN_EXT); ++ else ++ cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; ++ if (len) { ++ if (op->data.dir == SPI_MEM_DATA_OUT) ++ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; ++ ++ ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); ++ } ++ if (!len && op->addr.nbytes) ++ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; ++ ++ /* set the Controller */ ++ ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; ++ cmd |= mem->spi->chip_select << SFC_CMD_CS_SHIFT; ++ ++ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", ++ op->addr.nbytes, op->addr.buswidth, ++ op->dummy.nbytes, op->dummy.buswidth); ++ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", ++ ctrl, cmd, op->addr.val, len); ++ ++ writel(ctrl, sfc->regbase + SFC_CTRL); ++ writel(cmd, sfc->regbase + SFC_CMD); ++ if (op->addr.nbytes) ++ writel(op->addr.val, sfc->regbase + SFC_ADDR); ++ ++ return 0; ++} ++ ++static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) ++{ ++ u8 bytes = len & 0x3; ++ u32 dwords; ++ int tx_level; ++ u32 write_words; ++ u32 tmp = 0; ++ ++ dwords = len >> 2; ++ while (dwords) { ++ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); ++ if (tx_level < 0) ++ return tx_level; ++ write_words = min_t(u32, tx_level, dwords); ++ iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words); ++ buf += write_words << 2; ++ dwords -= write_words; ++ } ++ ++ /* write the rest non word aligned bytes */ ++ if (bytes) { ++ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); ++ if (tx_level < 0) ++ return tx_level; ++ memcpy(&tmp, buf, bytes); ++ writel(tmp, sfc->regbase + SFC_DATA); ++ } ++ ++ return len; ++} ++ ++static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) ++{ ++ u8 bytes = len & 0x3; ++ u32 dwords; ++ u8 read_words; ++ int rx_level; ++ int tmp; ++ ++ /* word aligned access only */ ++ dwords = len >> 2; ++ while (dwords) { ++ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); ++ if (rx_level < 0) ++ return rx_level; ++ read_words = min_t(u32, rx_level, dwords); ++ ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words); ++ buf += read_words << 2; ++ dwords -= read_words; ++ } ++ ++ /* read the rest non word aligned bytes */ ++ if (bytes) { ++ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); ++ if (rx_level < 0) ++ return rx_level; ++ tmp = readl(sfc->regbase + SFC_DATA); ++ memcpy(buf, &tmp, bytes); ++ } ++ ++ return len; ++} ++ ++static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) ++{ ++ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); ++ writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); ++ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); ++ ++ return len; ++} ++ ++static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, ++ const struct spi_mem_op *op, u32 len) ++{ ++ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); ++ ++ if (op->data.dir == SPI_MEM_DATA_OUT) ++ return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); ++ else ++ return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); ++} ++ ++static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, ++ const struct spi_mem_op *op, u32 len) ++{ ++ int ret; ++ ++ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); ++ ++ if (op->data.dir == SPI_MEM_DATA_OUT) ++ memcpy_toio(sfc->buffer, op->data.buf.out, len); ++ ++ ret = rockchip_sfc_fifo_transfer_dma(sfc, sfc->dma_buffer, len); ++ if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) { ++ dev_err(sfc->dev, "DMA wait for transfer finish timeout\n"); ++ ret = -ETIMEDOUT; ++ } ++ rockchip_sfc_irq_mask(sfc, SFC_IMR_DMA); ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ memcpy_fromio(op->data.buf.in, sfc->buffer, len); ++ ++ return ret; ++} ++ ++static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) ++{ ++ int ret = 0; ++ u32 status; ++ ++ ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, ++ !(status & SFC_SR_IS_BUSY), ++ 20, timeout_us); ++ if (ret) { ++ dev_err(sfc->dev, "wait sfc idle timeout\n"); ++ rockchip_sfc_reset(sfc); ++ ++ ret = -EIO; ++ } ++ ++ return ret; ++} ++ ++static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) ++{ ++ struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); ++ u32 len = op->data.nbytes; ++ int ret; ++ ++ if (unlikely(mem->spi->max_speed_hz != sfc->frequency)) { ++ ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz); ++ if (ret) ++ return ret; ++ sfc->frequency = mem->spi->max_speed_hz; ++ dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", ++ sfc->frequency, clk_get_rate(sfc->clk)); ++ } ++ ++ rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); ++ rockchip_sfc_xfer_setup(sfc, mem, op, len); ++ if (len) { ++ if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { ++ init_completion(&sfc->cp); ++ rockchip_sfc_irq_unmask(sfc, SFC_IMR_DMA); ++ ret = rockchip_sfc_xfer_data_dma(sfc, op, len); ++ } else { ++ ret = rockchip_sfc_xfer_data_poll(sfc, op, len); ++ } ++ ++ if (ret != len) { ++ dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); ++ ++ return -EIO; ++ } ++ } ++ ++ return rockchip_sfc_xfer_done(sfc, 100000); ++} ++ ++static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) ++{ ++ struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); ++ ++ op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); ++ ++ return 0; ++} ++ ++static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { ++ .exec_op = rockchip_sfc_exec_mem_op, ++ .adjust_op_size = rockchip_sfc_adjust_op_size, ++}; ++ ++static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) ++{ ++ struct rockchip_sfc *sfc = dev_id; ++ u32 reg; ++ ++ reg = readl(sfc->regbase + SFC_RISR); ++ ++ /* Clear interrupt */ ++ writel_relaxed(reg, sfc->regbase + SFC_ICLR); ++ ++ if (reg & SFC_RISR_DMA) { ++ complete(&sfc->cp); ++ ++ return IRQ_HANDLED; ++ } ++ ++ return IRQ_NONE; ++} ++ ++static int rockchip_sfc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct spi_master *master; ++ struct resource *res; ++ struct rockchip_sfc *sfc; ++ int ret; ++ ++ master = devm_spi_alloc_master(&pdev->dev, sizeof(*sfc)); ++ if (!master) ++ return -ENOMEM; ++ ++ master->flags = SPI_MASTER_HALF_DUPLEX; ++ master->mem_ops = &rockchip_sfc_mem_ops; ++ master->dev.of_node = pdev->dev.of_node; ++ master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL; ++ master->max_speed_hz = SFC_MAX_SPEED; ++ master->num_chipselect = SFC_MAX_CHIPSELECT_NUM; ++ ++ sfc = spi_master_get_devdata(master); ++ sfc->dev = dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ sfc->regbase = devm_ioremap_resource(dev, res); ++ if (IS_ERR(sfc->regbase)) ++ return PTR_ERR(sfc->regbase); ++ ++ sfc->clk = devm_clk_get(&pdev->dev, "clk_sfc"); ++ if (IS_ERR(sfc->clk)) { ++ dev_err(&pdev->dev, "Failed to get sfc interface clk\n"); ++ return PTR_ERR(sfc->clk); ++ } ++ ++ sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc"); ++ if (IS_ERR(sfc->hclk)) { ++ dev_err(&pdev->dev, "Failed to get sfc ahb clk\n"); ++ return PTR_ERR(sfc->hclk); ++ } ++ ++ sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, ++ "rockchip,sfc-no-dma"); ++ ++ if (sfc->use_dma) { ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_warn(dev, "Unable to set dma mask\n"); ++ return ret; ++ } ++ ++ sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_IOSIZE_VER3, ++ &sfc->dma_buffer, ++ GFP_KERNEL); ++ if (!sfc->buffer) ++ return -ENOMEM; ++ } ++ ++ ret = clk_prepare_enable(sfc->hclk); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to enable ahb clk\n"); ++ goto err_hclk; ++ } ++ ++ ret = clk_prepare_enable(sfc->clk); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to enable interface clk\n"); ++ goto err_clk; ++ } ++ ++ /* Find the irq */ ++ ret = platform_get_irq(pdev, 0); ++ if (ret < 0) { ++ dev_err(dev, "Failed to get the irq\n"); ++ goto err_irq; ++ } ++ ++ ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler, ++ 0, pdev->name, sfc); ++ if (ret) { ++ dev_err(dev, "Failed to request irq\n"); ++ ++ return ret; ++ } ++ ++ ret = rockchip_sfc_init(sfc); ++ if (ret) ++ goto err_irq; ++ ++ sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); ++ sfc->version = rockchip_sfc_get_version(sfc); ++ ++ ret = spi_register_master(master); ++ if (ret) ++ goto err_irq; ++ ++ return 0; ++ ++err_irq: ++ clk_disable_unprepare(sfc->clk); ++err_clk: ++ clk_disable_unprepare(sfc->hclk); ++err_hclk: ++ return ret; ++} ++ ++static int rockchip_sfc_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct rockchip_sfc *sfc = platform_get_drvdata(pdev); ++ ++ spi_unregister_master(master); ++ ++ clk_disable_unprepare(sfc->clk); ++ clk_disable_unprepare(sfc->hclk); ++ ++ return 0; ++} ++ ++static const struct of_device_id rockchip_sfc_dt_ids[] = { ++ { .compatible = "rockchip,sfc"}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids); ++ ++static struct platform_driver rockchip_sfc_driver = { ++ .driver = { ++ .name = "rockchip-sfc", ++ .of_match_table = rockchip_sfc_dt_ids, ++ }, ++ .probe = rockchip_sfc_probe, ++ .remove = rockchip_sfc_remove, ++}; ++module_platform_driver(rockchip_sfc_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver"); ++MODULE_AUTHOR("Shawn Lin "); ++MODULE_AUTHOR("Chris Morgan "); ++MODULE_AUTHOR("Jon Lin "); diff --git a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch new file mode 100644 index 0000000000..ac822561ca --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch @@ -0,0 +1,437 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 15:32:18 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: use correct vco_div_5 macro on + rk3328 + +inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro +when configuring vco_div_5 on RK3328. + +Fix this by using correct vco_div_5 macro for RK3328. + +Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 80acca4e9e14..15339338aae3 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -790,8 +790,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, + RK3328_PRE_PLL_POWER_DOWN); + + /* Configure pre-pll */ +- inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK, +- RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); ++ inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK, ++ RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); + inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); + + val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Zheng Yang +Date: Sat, 10 Oct 2020 15:32:18 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 + recalc_rate + +inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found +in the pre pll config table when the fractal divider is used. +This can prevent proper power_on because a tmdsclock for the new rate +is not found in the pre pll config table. + +Fix this by saving and returning a rounded pixel rate that exist +in the pre pll config table. + +Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") +Signed-off-by: Zheng Yang +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 15339338aae3..15a008a1ac7b 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, + do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); + } + +- inno->pixclock = vco; +- dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); ++ inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; + +- return vco; ++ dev_dbg(inno->dev, "%s rate %lu vco %llu\n", ++ __func__, inno->pixclock, vco); ++ ++ return inno->pixclock; + } + + static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 15:32:19 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: remove unused no_c from rk3328 + recalc_rate + +no_c is not used in any calculation, lets remove it. + +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 15a008a1ac7b..4b936ca19920 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, + { + struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); + unsigned long frac; +- u8 nd, no_a, no_b, no_c, no_d; ++ u8 nd, no_a, no_b, no_d; + u64 vco; + u16 nf; + +@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, + no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; + no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; + no_b += 2; +- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK; +- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT; +- no_c = 1 << no_c; + no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; + + do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 15:32:19 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on + reg write + +inno_write is used to configure 0xaa reg, that also hold the +POST_PLL_POWER_DOWN bit. +When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not +taken into consideration. + +Fix this by keeping the power down bit until configuration is complete. +Also reorder the reg write order for consistency. + +Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 4b936ca19920..620961fcfc1d 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, + + inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); + if (cfg->postdiv == 1) { +- inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); + inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | + RK3328_POST_PLL_PRE_DIV(cfg->prediv)); ++ inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | ++ RK3328_POST_PLL_POWER_DOWN); + } else { + v = (cfg->postdiv / 2) - 1; + v &= RK3328_POST_PLL_POST_DIV_MASK; +@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, + inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | + RK3328_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | +- RK3328_POST_PLL_REFCLK_SEL_TMDS); ++ RK3328_POST_PLL_REFCLK_SEL_TMDS | ++ RK3328_POST_PLL_POWER_DOWN); + } + + for (v = 0; v < 14; v++) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Huicong Xu +Date: Sat, 10 Oct 2020 15:32:20 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: force set_rate on power_on + +Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and +not in pixel clock rate. +When the hdmiphy clock is configured with the same pixel clock rate using +clk_set_rate() the clock framework do not signal the hdmi phy driver +to set_rate when switching between 8-bit and Deep Color. +This result in pre/post pll not being re-configured when switching between +regular 8-bit and Deep Color video formats. + +Fix this by calling set_rate in power_on to force pre pll re-configuration. + +Signed-off-by: Huicong Xu +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 620961fcfc1d..2f01259823ea 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -245,6 +245,7 @@ struct inno_hdmi_phy { + struct clk_hw hw; + struct clk *phyclk; + unsigned long pixclock; ++ unsigned long tmdsclock; + }; + + struct pre_pll_config { +@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy) + + dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); + ++ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); ++ + ret = clk_prepare_enable(inno->phyclk); + if (ret) + return ret; +@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy) + + clk_disable_unprepare(inno->phyclk); + ++ inno->tmdsclock = 0; ++ + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); + + return 0; +@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", + __func__, rate, tmdsclock); + ++ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) ++ return 0; ++ + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); +@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, + } + + inno->pixclock = rate; ++ inno->tmdsclock = tmdsclock; + + return 0; + } +@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", + __func__, rate, tmdsclock); + ++ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) ++ return 0; ++ + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); +@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, + } + + inno->pixclock = rate; ++ inno->tmdsclock = tmdsclock; + + return 0; + } + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 17 Feb 2019 22:14:38 +0000 +Subject: [PATCH] mmc: core: set initial signal voltage on power off + +Some boards have SD card connectors where the power rail cannot be switched +off by the driver. If the card has not been power cycled, it may still be +using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling +will fail to boot from a UHS card that continue to use 1.8V signaling. + +Set initial signal voltage in mmc_power_off() to allow re-boot to function. + +This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), +same issue have been seen on some Rockchip RK3399 boards. + +I am sending this as a RFC because I have no insights into SD/MMC subsystem, +this change fix a re-boot issue on my boards and does not break emmc/sdio. +Is this an acceptable workaround? Any advice is appreciated. + +Signed-off-by: Jonas Karlman +--- + drivers/mmc/core/core.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c +index 95fedcf56e4a..38e75b275bb6 100644 +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -1355,6 +1355,14 @@ void mmc_power_off(struct mmc_host *host) + if (host->ios.power_mode == MMC_POWER_OFF) + return; + ++ mmc_set_initial_signal_voltage(host); ++ ++ /* ++ * This delay should be sufficient to allow the power supply ++ * to reach the minimum voltage. ++ */ ++ mmc_delay(host->ios.power_delay_ms); ++ + mmc_pwrseq_power_off(host); + + host->ios.clock = 0; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 23 Jun 2021 13:59:26 +0200 +Subject: [PATCH] arm64: dts: rockchip: Fix GPU register width for RK3328 + +As can be seen in RK3328's TRM the register range for the GPU is +0xff300000 to 0xff330000. +It would (and does in vendor kernel) overlap with the registers of +the HEVC encoder (node/driver do not exist yet in upstream kernel). +See already existing h265e_mmu node. + +Fixes: 752fbc0c8da7 ("arm64: dts: rockchip: add rk3328 mali gpu node") +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index becc1c61b182..5b2020590f53 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -599,7 +599,7 @@ saradc: adc@ff280000 { + + gpu: gpu@ff300000 { + compatible = "rockchip,rk3328-mali", "arm,mali-450"; +- reg = <0x0 0xff300000 0x0 0x40000>; ++ reg = <0x0 0xff300000 0x0 0x30000>; + interrupts = , + , + , + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 23 Jun 2021 16:59:18 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add sdmmc_ext for RK3328 + +RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some +boards have sdio wifi connected to it. In order to use it +one would have to add the pinctrls from sdmmc0ext group which +is done on board level. + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 5b2020590f53..df46edbec82c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -975,6 +975,20 @@ usb_host0_ohci: usb@ff5d0000 { + status = "disabled"; + }; + ++ sdmmc_ext: mmc@ff5f0000 { ++ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xff5f0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, ++ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <150000000>; ++ resets = <&cru SRST_SDMMCEXT>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ + usbdrd3: usb@ff600000 { + compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 23 Jun 2021 17:02:08 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add sdmmc/sdio/emmc reset controls for + RK3328 + +The DW MCI controller driver will use them to reset the IP block before +initialisation. + +Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs") +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index df46edbec82c..cfc57be009a6 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -853,6 +853,8 @@ sdmmc: mmc@ff500000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; ++ resets = <&cru SRST_MMC0>; ++ reset-names = "reset"; + status = "disabled"; + }; + +@@ -865,6 +867,8 @@ sdio: mmc@ff510000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; ++ resets = <&cru SRST_SDIO>; ++ reset-names = "reset"; + status = "disabled"; + }; + +@@ -877,6 +881,8 @@ emmc: mmc@ff520000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; ++ resets = <&cru SRST_EMMC>; ++ reset-names = "reset"; + status = "disabled"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 19:13:31 +0200 +Subject: [PATCH] Commit a728c10dd62a ("arm64: dts: rockchip: remove + interrupt-names from iommu nodes") intended to remove the interrupt-names + property for the mmu nodes. It also removed them for the vpu node in + rk3399.dtsi which currently results in a non-working driver. Fix this by + re-adding them. + +Fixes: a728c10dd62a ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 9db9484ca38f..44def886b391 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1240,6 +1240,7 @@ vpu: video-codec@ff650000 { + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; ++ interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; diff --git a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch b/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch deleted file mode 100644 index 234c257969..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch +++ /dev/null @@ -1,219 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 11 May 2021 17:13:34 -0400 -Subject: [PATCH] regulator: fan53555: only bind tcs4525 to correct chip id - -The tcs4525 regulator has a chip id of <12>. -Only allow the driver to bind to the correct chip id for safety, in -accordance with the other supported devices. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210511211335.2935163-3-pgwipeout@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 25 ++++++++++++++++++------- - 1 file changed, 18 insertions(+), 7 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index 26f06f685b1b..16f28f9df6a1 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -89,6 +89,10 @@ enum { - FAN53555_CHIP_ID_08 = 8, - }; - -+enum { -+ TCS4525_CHIP_ID_12 = 12, -+}; -+ - /* IC mask revision */ - enum { - FAN53555_CHIP_REV_00 = 0x3, -@@ -368,14 +372,21 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) - - static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) - { -- di->slew_reg = TCS4525_TIME; -- di->slew_mask = TCS_SLEW_MASK; -- di->slew_shift = TCS_SLEW_MASK; -+ switch (di->chip_id) { -+ case TCS4525_CHIP_ID_12: -+ di->slew_reg = TCS4525_TIME; -+ di->slew_mask = TCS_SLEW_MASK; -+ di->slew_shift = TCS_SLEW_MASK; - -- /* Init voltage range and step */ -- di->vsel_min = 600000; -- di->vsel_step = 6250; -- di->vsel_count = FAN53526_NVOLTAGES; -+ /* Init voltage range and step */ -+ di->vsel_min = 600000; -+ di->vsel_step = 6250; -+ di->vsel_count = FAN53526_NVOLTAGES; -+ break; -+ default: -+ dev_err(di->dev, "Chip ID %d not supported!\n", di->chip_id); -+ return -EINVAL; -+ } - - return 0; - } - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 11 May 2021 17:13:35 -0400 -Subject: [PATCH] regulator: fan53555: fix tcs4525 function names - -The tcs4525 is based off the fan53526. -Rename the tcs4525 functions to align with this. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210511211335.2935163-4-pgwipeout@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 18 +++++++++--------- - 1 file changed, 9 insertions(+), 9 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index 16f28f9df6a1..2695be617373 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -67,7 +67,7 @@ enum fan53555_vendor { - FAN53526_VENDOR_FAIRCHILD = 0, - FAN53555_VENDOR_FAIRCHILD, - FAN53555_VENDOR_SILERGY, -- FAN53555_VENDOR_TCS, -+ FAN53526_VENDOR_TCS, - }; - - enum { -@@ -233,7 +233,7 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) - slew_rate_t = slew_rates; - slew_rate_n = ARRAY_SIZE(slew_rates); - break; -- case FAN53555_VENDOR_TCS: -+ case FAN53526_VENDOR_TCS: - slew_rate_t = tcs_slew_rates; - slew_rate_n = ARRAY_SIZE(tcs_slew_rates); - break; -@@ -370,7 +370,7 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) - return 0; - } - --static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) -+static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) - { - switch (di->chip_id) { - case TCS4525_CHIP_ID_12: -@@ -420,7 +420,7 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - return -EINVAL; - } - break; -- case FAN53555_VENDOR_TCS: -+ case FAN53526_VENDOR_TCS: - switch (pdata->sleep_vsel_id) { - case FAN53555_VSEL_ID_0: - di->sleep_reg = TCS4525_VSEL0; -@@ -459,7 +459,7 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - di->mode_reg = di->vol_reg; - di->mode_mask = VSEL_MODE; - break; -- case FAN53555_VENDOR_TCS: -+ case FAN53526_VENDOR_TCS: - di->mode_reg = TCS4525_COMMAND; - - switch (pdata->sleep_vsel_id) { -@@ -487,8 +487,8 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - case FAN53555_VENDOR_SILERGY: - ret = fan53555_voltages_setup_silergy(di); - break; -- case FAN53555_VENDOR_TCS: -- ret = fan53555_voltages_setup_tcs(di); -+ case FAN53526_VENDOR_TCS: -+ ret = fan53526_voltages_setup_tcs(di); - break; - default: - dev_err(di->dev, "vendor %d not supported!\n", di->vendor); -@@ -563,7 +563,7 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { - .data = (void *)FAN53555_VENDOR_SILERGY, - }, { - .compatible = "tcs,tcs4525", -- .data = (void *)FAN53555_VENDOR_TCS -+ .data = (void *)FAN53526_VENDOR_TCS - }, - { } - }; -@@ -671,7 +671,7 @@ static const struct i2c_device_id fan53555_id[] = { - .driver_data = FAN53555_VENDOR_SILERGY - }, { - .name = "tcs4525", -- .driver_data = FAN53555_VENDOR_TCS -+ .driver_data = FAN53526_VENDOR_TCS - }, - { }, - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Axel Lin -Date: Mon, 17 May 2021 09:03:17 +0800 -Subject: [PATCH] regulator: fan53555: Fix slew_shift setting for tcs4525 - -Fix trivial copy-paste mistake. - -Signed-off-by: Axel Lin -Link: https://lore.kernel.org/r/20210517010318.1027949-1-axel.lin@ingics.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index 2695be617373..d582ef3a3aeb 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -376,7 +376,7 @@ static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) - case TCS4525_CHIP_ID_12: - di->slew_reg = TCS4525_TIME; - di->slew_mask = TCS_SLEW_MASK; -- di->slew_shift = TCS_SLEW_MASK; -+ di->slew_shift = TCS_SLEW_SHIFT; - - /* Init voltage range and step */ - di->vsel_min = 600000; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Axel Lin -Date: Mon, 17 May 2021 09:03:18 +0800 -Subject: [PATCH] regulator: fan53555: Cleanup unused define and redundant - assignment - -TCS_VSEL_NSEL_MASK is not used so remove it. -Also remove redundant assignment for di->slew_reg. - -Signed-off-by: Axel Lin -Link: https://lore.kernel.org/r/20210517010318.1027949-2-axel.lin@ingics.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index d582ef3a3aeb..f3f49cf3731b 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -56,7 +56,6 @@ - #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ - #define FAN53526_NVOLTAGES 128 - --#define TCS_VSEL_NSEL_MASK 0x7f - #define TCS_VSEL0_MODE (1 << 7) - #define TCS_VSEL1_MODE (1 << 6) - -@@ -362,7 +361,6 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) - return -EINVAL; - } - di->slew_reg = FAN53555_CONTROL; -- di->slew_reg = FAN53555_CONTROL; - di->slew_mask = CTL_SLEW_MASK; - di->slew_shift = CTL_SLEW_SHIFT; - di->vsel_count = FAN53555_NVOLTAGES; diff --git a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch deleted file mode 100644 index 2f04777360..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch +++ /dev/null @@ -1,1184 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 15:32:18 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: use correct vco_div_5 macro on - rk3328 - -inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro -when configuring vco_div_5 on RK3328. - -Fix this by using correct vco_div_5 macro for RK3328. - -Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 9ca20c947283..b0ac1d3ee390 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -790,8 +790,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, - RK3328_PRE_PLL_POWER_DOWN); - - /* Configure pre-pll */ -- inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK, -- RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); -+ inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK, -+ RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); - inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); - - val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Zheng Yang -Date: Sat, 10 Oct 2020 15:32:18 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 - recalc_rate - -inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found -in the pre pll config table when the fractal divider is used. -This can prevent proper power_on because a tmdsclock for the new rate -is not found in the pre pll config table. - -Fix this by saving and returning a rounded pixel rate that exist -in the pre pll config table. - -Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") -Signed-off-by: Zheng Yang -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index b0ac1d3ee390..093d2334e8cd 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, - do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); - } - -- inno->pixclock = vco; -- dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); -+ inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; - -- return vco; -+ dev_dbg(inno->dev, "%s rate %lu vco %llu\n", -+ __func__, inno->pixclock, vco); -+ -+ return inno->pixclock; - } - - static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 15:32:19 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: remove unused no_c from rk3328 - recalc_rate - -no_c is not used in any calculation, lets remove it. - -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 093d2334e8cd..06db69c8373e 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, - { - struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); - unsigned long frac; -- u8 nd, no_a, no_b, no_c, no_d; -+ u8 nd, no_a, no_b, no_d; - u64 vco; - u16 nf; - -@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, - no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; - no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; - no_b += 2; -- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK; -- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT; -- no_c = 1 << no_c; - no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; - - do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 15:32:19 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on - reg write - -inno_write is used to configure 0xaa reg, that also hold the -POST_PLL_POWER_DOWN bit. -When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not -taken into consideration. - -Fix this by keeping the power down bit until configuration is complete. -Also reorder the reg write order for consistency. - -Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 06db69c8373e..3a59a6da0440 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, - - inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); - if (cfg->postdiv == 1) { -- inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); - inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | - RK3328_POST_PLL_PRE_DIV(cfg->prediv)); -+ inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | -+ RK3328_POST_PLL_POWER_DOWN); - } else { - v = (cfg->postdiv / 2) - 1; - v &= RK3328_POST_PLL_POST_DIV_MASK; -@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, - inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | - RK3328_POST_PLL_PRE_DIV(cfg->prediv)); - inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | -- RK3328_POST_PLL_REFCLK_SEL_TMDS); -+ RK3328_POST_PLL_REFCLK_SEL_TMDS | -+ RK3328_POST_PLL_POWER_DOWN); - } - - for (v = 0; v < 14; v++) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Huicong Xu -Date: Sat, 10 Oct 2020 15:32:20 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: force set_rate on power_on - -Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and -not in pixel clock rate. -When the hdmiphy clock is configured with the same pixel clock rate using -clk_set_rate() the clock framework do not signal the hdmi phy driver -to set_rate when switching between 8-bit and Deep Color. -This result in pre/post pll not being re-configured when switching between -regular 8-bit and Deep Color video formats. - -Fix this by calling set_rate in power_on to force pre pll re-configuration. - -Signed-off-by: Huicong Xu -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 3a59a6da0440..3719309ad0d0 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -245,6 +245,7 @@ struct inno_hdmi_phy { - struct clk_hw hw; - struct clk *phyclk; - unsigned long pixclock; -+ unsigned long tmdsclock; - }; - - struct pre_pll_config { -@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy) - - dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); - -+ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); -+ - ret = clk_prepare_enable(inno->phyclk); - if (ret) - return ret; -@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy) - - clk_disable_unprepare(inno->phyclk); - -+ inno->tmdsclock = 0; -+ - dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); - - return 0; -@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, - dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", - __func__, rate, tmdsclock); - -+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) -+ return 0; -+ - cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); - if (IS_ERR(cfg)) - return PTR_ERR(cfg); -@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, - } - - inno->pixclock = rate; -+ inno->tmdsclock = tmdsclock; - - return 0; - } -@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, - dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", - __func__, rate, tmdsclock); - -+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) -+ return 0; -+ - cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); - if (IS_ERR(cfg)) - return PTR_ERR(cfg); -@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, - } - - inno->pixclock = rate; -+ inno->tmdsclock = tmdsclock; - - return 0; - } - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 16 Nov 2020 15:17:33 +0000 -Subject: [PATCH] phy: rockchip: add rockchip usb3 innosilicon phy driver - -The innosilicon based usb3 phy used in rockchip devices such as the rk3328 is bugged, requiring special handling. -The following erata have been observed: - - usb3 device disconnect events are not detected by the controller - - usb2 hubs with no devices attached do not trigger disconnect events when removed - - interrupts are not reliable - -To work around these issue we implement polling of the usb2 and usb3 status. -On usb3 disconnection we reset the usb3 phy which triggers the disconnect event. -On usb2 disconnection we have to force reset the whole controller. -This requires a handoff to a special dwc3 device driver. - -This has been tested on the rk3328-roc-cc board with the following devices: - - usb2 only device - - usb3 only device - - usb2 only hub without devices - - usb3 hub without devices - - usb2 hub with devices - - usb3 hub with devices - -Signed-off-by: Peter Geis ---- - drivers/phy/rockchip/Kconfig | 9 + - drivers/phy/rockchip/Makefile | 1 + - drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 425 ++++++++++++++++++ - 3 files changed, 435 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c - -diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig -index c2f22f90736c..ce16e0877354 100644 ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -47,6 +47,15 @@ config PHY_ROCKCHIP_INNO_USB2 - help - Support for Rockchip USB2.0 PHY with Innosilicon IP block. - -+config PHY_ROCKCHIP_INNO_USB3 -+ tristate "Rockchip INNO USB3PHY Driver" -+ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ depends on USB_SUPPORT -+ select USB_COMMON -+ help -+ Support for Rockchip USB3.0 PHY with Innosilicon IP block. -+ - config PHY_ROCKCHIP_INNO_DSIDPHY - tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver" - depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF -diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile -index c3cfc7f0af5c..738e3574a722 100644 ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o -+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb3.c b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c -new file mode 100644 -index 000000000000..6e4aa2f0ba46 ---- /dev/null -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c -@@ -0,0 +1,425 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define USB3_STATUS_REG 0x284 -+#define USB2_STATUS_REG 0x30 -+#define USB3_CONN_BIT BIT(0) -+#define USB2_CONN_BIT BIT(7) -+#define USB2_STATE_SHIFT 6 -+#define REG_WRITE_MASK GENMASK(31, 16) -+ -+struct rockchip_usb3phy_port{ -+ struct device *dev; -+ struct regmap *regmap; -+ struct usb_phy phy; -+ struct rockchip_usb3phy *parent; -+ unsigned char type; -+}; -+ -+enum usb3phy_mode { -+ PHY_IDLE = 0, -+ PHY_USB3, -+ PHY_USB2, -+ PHY_COMBO -+}; -+ -+struct rockchip_usb3phy { -+ struct device *dev; -+ struct regmap *regmap; -+ struct clk *clk_pipe; -+ struct clk *clk_otg; -+ struct reset_control *u3por_rst; -+ struct reset_control *u2por_rst; -+ struct reset_control *pipe_rst; -+ struct reset_control *utmi_rst; -+ struct reset_control *pipe_apb_rst; -+ struct reset_control *utmi_apb_rst; -+ struct rockchip_usb3phy_port port_pipe; -+ struct rockchip_usb3phy_port port_utmi; -+ struct work_struct usb_phy_work; -+ struct notifier_block nb; -+ enum usb3phy_mode mode; -+ struct mutex lock; -+}; -+ -+static int rockchip_usb3phy_reset(struct rockchip_usb3phy *usb3phy, bool reset, enum usb3phy_mode mode) -+{ -+ if (reset == true) { -+ if ((mode == PHY_USB2) | (mode == PHY_COMBO)){ -+ clk_disable_unprepare(usb3phy->clk_otg); -+ reset_control_assert(usb3phy->utmi_rst); -+ reset_control_assert(usb3phy->u2por_rst); -+ } -+ if ((mode == PHY_USB3) | (mode == PHY_COMBO)){ -+ clk_disable_unprepare(usb3phy->clk_pipe); -+ reset_control_assert(usb3phy->pipe_rst); -+ reset_control_assert(usb3phy->u3por_rst); -+ } -+ } -+ -+ if (reset == false) { -+ if ((mode == PHY_USB2) | (mode == PHY_COMBO)){ -+ reset_control_deassert(usb3phy->u2por_rst); -+ udelay(1000); -+ clk_prepare_enable(usb3phy->clk_otg); -+ udelay(500); -+ reset_control_deassert(usb3phy->utmi_rst); -+ } -+ if ((mode == PHY_USB3) | (mode == PHY_COMBO)){ -+ reset_control_deassert(usb3phy->u3por_rst); -+ udelay(500); -+ clk_prepare_enable(usb3phy->clk_pipe); -+ udelay(1000); -+ reset_control_deassert(usb3phy->pipe_rst); -+ } -+ } -+ -+ return 0; -+} -+ -+static void rockchip_usb3phy_work(struct work_struct *work) -+{ -+ struct rockchip_usb3phy *usb3phy = container_of(work, struct rockchip_usb3phy, usb_phy_work); -+ struct rockchip_usb3phy_port *port_pipe = &usb3phy->port_pipe; -+ struct rockchip_usb3phy_port *port_utmi = &usb3phy->port_utmi; -+ int usb2, usb3, tmp, state; -+ -+ mutex_lock(&usb3phy->lock); -+ -+ regmap_read(port_pipe->regmap, USB3_STATUS_REG, &tmp); -+ usb3 = tmp & USB3_CONN_BIT; -+ regmap_read(usb3phy->regmap, USB2_STATUS_REG, &tmp); -+ usb2 = ((tmp & USB2_CONN_BIT) ^ USB2_CONN_BIT ) >> USB2_STATE_SHIFT; -+ state = (usb3 | usb2); -+ dev_dbg(usb3phy->dev, "mode %i, state %i\n", usb3phy->mode, state); -+ -+ if (usb3phy->mode == state) -+ /* not our device */ -+ goto out; -+ -+ if (usb2) { -+ usb3phy->mode = PHY_USB2; -+ dev_dbg(usb3phy->dev, "usb3phy utmi polling started\n"); -+ regmap_read_poll_timeout(usb3phy->regmap, USB2_STATUS_REG, tmp, (tmp & USB2_CONN_BIT), 2000, 0); -+ state = ((tmp & USB2_CONN_BIT) ^ USB2_CONN_BIT ) >> USB2_STATE_SHIFT; -+ dev_dbg(usb3phy->dev, "usb3phy utmi polling completed\n"); -+ -+ atomic_notifier_call_chain(&port_utmi->phy.notifier, 0, NULL); -+ goto out; -+ } -+ -+ if (usb3) { -+ dev_dbg(usb3phy->dev, "usb3phy pipe polling started\n"); -+ regmap_read_poll_timeout(port_pipe->regmap, USB3_STATUS_REG, tmp, !(tmp & USB3_CONN_BIT), 2000, 0); -+ dev_dbg(usb3phy->dev, "usb3phy pipe polling completed\n"); -+ -+ rockchip_usb3phy_reset(usb3phy, true, PHY_USB3); -+ udelay(500); -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB3); -+ udelay(500); -+ -+ goto out; -+ } -+ -+out: -+ usb3phy->mode = PHY_IDLE; -+ mutex_unlock(&usb3phy->lock); -+ return; -+} -+ -+static int rockchip_usb3phy_parse_dt(struct rockchip_usb3phy *usb3phy, struct device *dev) -+{ -+ usb3phy->clk_pipe = devm_clk_get(dev, "usb3phy-pipe"); -+ if (IS_ERR(usb3phy->clk_pipe)) { -+ dev_err(dev, "could not get usb3phy pipe clock\n"); -+ return PTR_ERR(usb3phy->clk_pipe); -+ } -+ -+ usb3phy->clk_otg = devm_clk_get(dev, "usb3phy-otg"); -+ if (IS_ERR(usb3phy->clk_otg)) { -+ dev_err(dev, "could not get usb3phy otg clock\n"); -+ return PTR_ERR(usb3phy->clk_otg); -+ } -+ -+ usb3phy->u2por_rst = devm_reset_control_get(dev, "usb3phy-u2-por"); -+ if (IS_ERR(usb3phy->u2por_rst)) { -+ dev_err(dev, "no usb3phy-u2-por reset control found\n"); -+ return PTR_ERR(usb3phy->u2por_rst); -+ } -+ -+ usb3phy->u3por_rst = devm_reset_control_get(dev, "usb3phy-u3-por"); -+ if (IS_ERR(usb3phy->u3por_rst)) { -+ dev_err(dev, "no usb3phy-u3-por reset control found\n"); -+ return PTR_ERR(usb3phy->u3por_rst); -+ } -+ -+ usb3phy->pipe_rst = devm_reset_control_get(dev, "usb3phy-pipe-mac"); -+ if (IS_ERR(usb3phy->pipe_rst)) { -+ dev_err(dev, "no usb3phy_pipe_mac reset control found\n"); -+ return PTR_ERR(usb3phy->pipe_rst); -+ } -+ -+ usb3phy->utmi_rst = devm_reset_control_get(dev, "usb3phy-utmi-mac"); -+ if (IS_ERR(usb3phy->utmi_rst)) { -+ dev_err(dev, "no usb3phy-utmi-mac reset control found\n"); -+ return PTR_ERR(usb3phy->utmi_rst); -+ } -+ -+ usb3phy->pipe_apb_rst = devm_reset_control_get(dev, "usb3phy-pipe-apb"); -+ if (IS_ERR(usb3phy->pipe_apb_rst)) { -+ dev_err(dev, "no usb3phy-pipe-apb reset control found\n"); -+ return PTR_ERR(usb3phy->pipe_apb_rst); -+ } -+ -+ usb3phy->utmi_apb_rst = devm_reset_control_get(dev, "usb3phy-utmi-apb"); -+ if (IS_ERR(usb3phy->utmi_apb_rst)) { -+ dev_err(dev, "no usb3phy-utmi-apb reset control found\n"); -+ return PTR_ERR(usb3phy->utmi_apb_rst); -+ } -+ -+ return 0; -+} -+ -+static int rockchip_usb3phy_notify(struct notifier_block *nb, unsigned long action, void *data) -+{ -+ struct rockchip_usb3phy *usb3phy = container_of(nb, struct rockchip_usb3phy, nb); -+ switch (action) { -+ case USB_DEVICE_ADD: -+ dev_dbg(usb3phy->dev, "notified of device add\n"); -+ if (!(mutex_is_locked(&usb3phy->lock))) -+ schedule_work(&usb3phy->usb_phy_work); -+ return NOTIFY_OK; -+ } -+ return NOTIFY_DONE; -+} -+ -+static int rockchip_usb3phy_init(struct usb_phy *phy) -+{ -+ struct rockchip_usb3phy_port *usb3phy_port = container_of(phy, struct rockchip_usb3phy_port, phy); -+ struct rockchip_usb3phy *usb3phy = usb3phy_port->parent; -+ -+ dev_warn(usb3phy->dev, "usb3phy_init %s\n", phy->label); -+ if (phy->type == USB_PHY_TYPE_USB3){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB3); -+ udelay(100); /* let it stabilize */ -+ usb3phy->nb.notifier_call = rockchip_usb3phy_notify; -+ usb_register_notify(&usb3phy->nb); -+ } -+ if (phy->type == USB_PHY_TYPE_USB2){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB2); -+ udelay(100); /* let it stabilize */ -+ } -+ -+ return 0; -+} -+ -+static void rockchip_usb3phy_shutdown(struct usb_phy *phy) -+{ -+ struct rockchip_usb3phy_port *usb3phy_port = container_of(phy, struct rockchip_usb3phy_port, phy); -+ struct rockchip_usb3phy *usb3phy = usb3phy_port->parent; -+ -+ dev_dbg(usb3phy->dev, "usb3phy_shutdown\n"); -+ if (phy->type == USB_PHY_TYPE_USB3){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB3); -+ usb_unregister_notify(&usb3phy->nb); -+ } -+ if (phy->type == USB_PHY_TYPE_USB2){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB2); -+ } -+} -+ -+static const struct regmap_config rockchip_usb3phy_port_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = 0x1000, -+}; -+ -+static const struct regmap_config rockchip_usb3phy_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = 0x1000, -+ .write_flag_mask = REG_WRITE_MASK, -+}; -+ -+static int rockchip_usb3phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; -+ struct rockchip_usb3phy *usb3phy; -+ struct rockchip_usb3phy_port *usb3phy_port; -+ struct regmap_config regmap_config = rockchip_usb3phy_regmap_config; -+ struct regmap_config regmap_port_config = rockchip_usb3phy_port_regmap_config; -+ const struct of_device_id *match; -+ void __iomem *base; -+ int ret; -+ -+ match = of_match_device(dev->driver->of_match_table, dev); -+ if (!match) { -+ dev_err(dev, "phy node not assigned\n"); -+ return -EINVAL; -+ } -+ -+ if (of_node_name_eq(np, "usb3-phy")) { -+ dev_dbg(dev, "Probe usb3phy main block\n"); -+ -+ usb3phy = devm_kzalloc(dev, sizeof(*usb3phy), GFP_KERNEL); -+ if (!usb3phy) -+ return -ENOMEM; -+ -+ ret = rockchip_usb3phy_parse_dt(usb3phy, dev); -+ if (ret) { -+ dev_err(dev, "parse dt failed %i\n", ret); -+ return ret; -+ } -+ -+ base = devm_of_iomap(dev, np, 0, NULL); -+ if (IS_ERR(base)) { -+ dev_err(dev, "failed port ioremap\n"); -+ return PTR_ERR(base); -+ } -+ -+ regmap_config.name = np->name; -+ -+ usb3phy->regmap = devm_regmap_init_mmio(dev, base, ®map_config); -+ if (IS_ERR(usb3phy->regmap)) { -+ dev_err(dev, "regmap init failed\n"); -+ return PTR_ERR(usb3phy->regmap); -+ } -+ -+ usb3phy->dev = dev; -+ platform_set_drvdata(pdev, usb3phy); -+ -+ /* place block in reset */ -+ reset_control_assert(usb3phy->pipe_rst); -+ reset_control_assert(usb3phy->utmi_rst); -+ reset_control_assert(usb3phy->u3por_rst); -+ reset_control_assert(usb3phy->u2por_rst); -+ reset_control_assert(usb3phy->pipe_apb_rst); -+ reset_control_assert(usb3phy->utmi_apb_rst); -+ -+ udelay(20); -+ -+ /* take apb interface out of reset */ -+ reset_control_deassert(usb3phy->utmi_apb_rst); -+ reset_control_deassert(usb3phy->pipe_apb_rst); -+ -+ usb3phy->mode = PHY_IDLE; -+ INIT_WORK(&usb3phy->usb_phy_work, rockchip_usb3phy_work); -+ dev_dbg(dev, "Completed usb3phy core probe \n"); -+ -+ return devm_of_platform_populate(&pdev->dev); -+ } -+ -+ /* probe the actual ports */ -+ usb3phy = platform_get_drvdata(of_find_device_by_node(np->parent)); -+ -+ if (of_node_name_eq(np, "utmi")) { -+ usb3phy_port = &usb3phy->port_utmi; -+ usb3phy_port->phy.label = "usb2-phy"; -+ usb3phy_port->phy.type = USB_PHY_TYPE_USB2; -+ } -+ else if (of_node_name_eq(np, "pipe")) { -+ usb3phy_port = &usb3phy->port_pipe; -+ usb3phy_port->phy.label = "usb3-phy"; -+ usb3phy_port->phy.type = USB_PHY_TYPE_USB3; -+ } -+ else { -+ dev_err(dev, "unknown child node port type %s\n", np->name); -+ return -EINVAL; -+ } -+ -+ usb3phy_port->dev = dev; -+ -+ base = devm_of_iomap(dev, np, 0, NULL); -+ if (IS_ERR(base)) { -+ dev_err(dev, "failed port ioremap\n"); -+ return PTR_ERR(base); -+ } -+ -+ regmap_port_config.name = np->name; -+ -+ usb3phy_port->regmap = devm_regmap_init_mmio(dev, base, ®map_port_config); -+ if (IS_ERR(usb3phy_port->regmap)) { -+ dev_err(dev, "regmap init failed\n"); -+ return PTR_ERR(usb3phy_port->regmap); -+ } -+ -+ usb3phy_port->phy.dev = dev; -+ usb3phy_port->phy.init = rockchip_usb3phy_init; -+ usb3phy_port->phy.shutdown = rockchip_usb3phy_shutdown; -+ usb3phy_port->parent = usb3phy; -+ -+ ret = usb_add_phy_dev(&usb3phy_port->phy); -+ if (ret) { -+ dev_err(dev, "add usb phy failed %i\n", ret); -+ return ret; -+ } -+ -+ mutex_init(&usb3phy->lock); -+ -+ dev_info(dev, "Completed usb3phy %s port init\n", usb3phy_port->phy.label); -+ return 0; -+} -+ -+ -+static int rockchip_usb3phy_remove(struct platform_device *pdev) -+{ -+ struct rockchip_usb3phy *usb3phy = platform_get_drvdata(pdev); -+ struct rockchip_usb3phy_port *port_pipe = &usb3phy->port_pipe; -+ struct rockchip_usb3phy_port *port_utmi = &usb3phy->port_utmi; -+ -+ if (&port_pipe->phy.head) -+ usb_remove_phy(&port_pipe->phy); -+ if (&port_utmi->phy.head) -+ usb_remove_phy(&port_utmi->phy); -+ -+ reset_control_assert(usb3phy->pipe_apb_rst); -+ reset_control_assert(usb3phy->utmi_apb_rst); -+ -+ return 0; -+} -+ -+static const struct of_device_id rockchip_usb3phy_dt_ids[] = { -+ { .compatible = "rockchip,rk3328-usb3phy", }, -+ { .compatible = "rockchip,rk3328-usb3phy-utmi", }, -+ { .compatible = "rockchip,rk3328-usb3phy-pipe", }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, rockchip_usb3phy_dt_ids); -+ -+static struct platform_driver rockchip_usb3phy_driver = { -+ .probe = rockchip_usb3phy_probe, -+ .remove = rockchip_usb3phy_remove, -+ .driver = { -+ .name = "rockchip-usb3-phy", -+ .of_match_table = rockchip_usb3phy_dt_ids, -+ }, -+}; -+ -+module_platform_driver(rockchip_usb3phy_driver); -+ -+MODULE_AUTHOR("Peter Geis "); -+MODULE_DESCRIPTION("Rockchip USB 3 PHY driver"); -+MODULE_LICENSE("GPL v2"); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 16 Nov 2020 15:17:34 +0000 -Subject: [PATCH] usb: dwc3: add rockchip innosilicon usb3 glue layer - -This adds the handler glue for the rockchip usb3 innosilicon phy driver. -This driver attaches to the phy driver through the notification system. -When a usb2 disconnect event occurs this driver tears down the hcd and rebuilds it manually. -This is to work around the usb2 controller becoming wedged and not detecting any usb2 devices after a usb2 hub is removed. - -It is based off work originally done by rockchip. - -Signed-off-by: Peter Geis ---- - drivers/usb/dwc3/Kconfig | 10 + - drivers/usb/dwc3/Makefile | 1 + - drivers/usb/dwc3/dwc3-rockchip-inno.c | 271 ++++++++++++++++++++++++++ - 3 files changed, 282 insertions(+) - create mode 100644 drivers/usb/dwc3/dwc3-rockchip-inno.c - -diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig -index 7a2304565a73..2e33a45f55ff 100644 ---- a/drivers/usb/dwc3/Kconfig -+++ b/drivers/usb/dwc3/Kconfig -@@ -139,4 +139,14 @@ config USB_DWC3_QCOM - for peripheral mode support. - Say 'Y' or 'M' if you have one such device. - -+config USB_DWC3_ROCKCHIP_INNO -+ tristate "Rockchip Platforms with INNO PHY" -+ depends on OF && COMMON_CLK && ARCH_ROCKCHIP -+ depends on USB=y || USB=USB_DWC3 -+ default USB_DWC3 -+ help -+ Support of USB2/3 functionality in Rockchip platforms -+ with INNO USB 3.0 PHY IP inside. -+ say 'Y' or 'M' if you have one such device. -+ - endif -diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile -index ae86da0dc5bd..f5eb7de10128 100644 ---- a/drivers/usb/dwc3/Makefile -+++ b/drivers/usb/dwc3/Makefile -@@ -51,4 +51,5 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o - obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o - obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o - obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o - obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o -+obj-$(CONFIG_USB_DWC3_ROCKCHIP_INNO) += dwc3-rockchip-inno.o -diff --git a/drivers/usb/dwc3/dwc3-rockchip-inno.c b/drivers/usb/dwc3/dwc3-rockchip-inno.c -new file mode 100644 -index 000000000000..7007ddbcbdae ---- /dev/null -+++ b/drivers/usb/dwc3/dwc3-rockchip-inno.c -@@ -0,0 +1,271 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * dwc3-rockchip-inno.c - DWC3 glue layer for Rockchip devices with Innosilicon based PHY -+ * -+ * Based on dwc3-of-simple.c -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "core.h" -+#include "../host/xhci.h" -+ -+ -+struct dwc3_rk_inno { -+ struct device *dev; -+ struct clk_bulk_data *clks; -+ struct dwc3 *dwc; -+ struct usb_phy *phy; -+ struct notifier_block reset_nb; -+ struct work_struct reset_work; -+ struct mutex lock; -+ int num_clocks; -+ struct reset_control *resets; -+}; -+ -+static int dwc3_rk_inno_host_reset_notifier(struct notifier_block *nb, unsigned long event, void *data) -+{ -+ struct dwc3_rk_inno *rk_inno = container_of(nb, struct dwc3_rk_inno, reset_nb); -+ -+ schedule_work(&rk_inno->reset_work); -+ -+ return NOTIFY_DONE; -+} -+ -+static void dwc3_rk_inno_host_reset_work(struct work_struct *work) -+{ -+ struct dwc3_rk_inno *rk_inno = container_of(work, struct dwc3_rk_inno, reset_work); -+ struct usb_hcd *hcd = dev_get_drvdata(&rk_inno->dwc->xhci->dev); -+ struct usb_hcd *shared_hcd = hcd->shared_hcd; -+ struct xhci_hcd *xhci = hcd_to_xhci(hcd); -+ unsigned int count = 0; -+ -+ mutex_lock(&rk_inno->lock); -+ -+ if (hcd->state != HC_STATE_HALT) { -+ usb_remove_hcd(shared_hcd); -+ usb_remove_hcd(hcd); -+ } -+ -+ if (rk_inno->phy) -+ usb_phy_shutdown(rk_inno->phy); -+ -+ while (hcd->state != HC_STATE_HALT) { -+ if (++count > 1000) { -+ dev_err(rk_inno->dev, "wait for HCD remove 1s timeout!\n"); -+ break; -+ } -+ usleep_range(1000, 1100); -+ } -+ -+ if (hcd->state == HC_STATE_HALT) { -+ xhci->shared_hcd = shared_hcd; -+ usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); -+ usb_add_hcd(shared_hcd, hcd->irq, IRQF_SHARED); -+ } -+ -+ if (rk_inno->phy) -+ usb_phy_init(rk_inno->phy); -+ -+ mutex_unlock(&rk_inno->lock); -+ dev_dbg(rk_inno->dev, "host reset complete\n"); -+} -+ -+static int dwc3_rk_inno_probe(struct platform_device *pdev) -+{ -+ struct dwc3_rk_inno *rk_inno; -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node, *child, *node; -+ struct platform_device *child_pdev; -+ -+ int ret; -+ -+ rk_inno = devm_kzalloc(dev, sizeof(*rk_inno), GFP_KERNEL); -+ if (!rk_inno) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, rk_inno); -+ rk_inno->dev = dev; -+ -+ rk_inno->resets = of_reset_control_array_get(np, false, true, -+ true); -+ if (IS_ERR(rk_inno->resets)) { -+ ret = PTR_ERR(rk_inno->resets); -+ dev_err(dev, "failed to get device resets, err=%d\n", ret); -+ return ret; -+ } -+ -+ ret = reset_control_deassert(rk_inno->resets); -+ if (ret) -+ goto err_resetc_put; -+ -+ ret = clk_bulk_get_all(rk_inno->dev, &rk_inno->clks); -+ if (ret < 0) -+ goto err_resetc_assert; -+ -+ rk_inno->num_clocks = ret; -+ ret = clk_bulk_prepare_enable(rk_inno->num_clocks, rk_inno->clks); -+ if (ret) -+ goto err_resetc_assert; -+ -+ ret = of_platform_populate(np, NULL, NULL, dev); -+ if (ret) -+ goto err_clk_put; -+ -+ child = of_get_child_by_name(np, "dwc3"); -+ if (!child) { -+ dev_err(dev, "failed to find dwc3 core node\n"); -+ ret = -ENODEV; -+ goto err_plat_depopulate; -+ } -+ -+ child_pdev = of_find_device_by_node(child); -+ if (!child_pdev) { -+ dev_err(dev, "failed to get dwc3 core device\n"); -+ ret = -ENODEV; -+ goto err_plat_depopulate; -+ } -+ -+ rk_inno->dwc = platform_get_drvdata(child_pdev); -+ if (!rk_inno->dwc || !rk_inno->dwc->xhci) { -+ ret = -EPROBE_DEFER; -+ goto err_plat_depopulate; -+ } -+ -+ node = of_parse_phandle(child, "usb-phy", 0); -+ INIT_WORK(&rk_inno->reset_work, dwc3_rk_inno_host_reset_work); -+ rk_inno->reset_nb.notifier_call = dwc3_rk_inno_host_reset_notifier; -+ rk_inno->phy = devm_usb_get_phy_by_node(dev, node, &rk_inno->reset_nb); -+ of_node_put(node); -+ mutex_init(&rk_inno->lock); -+ -+ pm_runtime_set_active(dev); -+ pm_runtime_enable(dev); -+ pm_runtime_get_sync(dev); -+ -+ return 0; -+ -+err_plat_depopulate: -+ of_platform_depopulate(dev); -+ -+err_clk_put: -+ clk_bulk_disable_unprepare(rk_inno->num_clocks, rk_inno->clks); -+ clk_bulk_put_all(rk_inno->num_clocks, rk_inno->clks); -+ -+err_resetc_assert: -+ reset_control_assert(rk_inno->resets); -+ -+err_resetc_put: -+ reset_control_put(rk_inno->resets); -+ return ret; -+} -+ -+static void __dwc3_rk_inno_teardown(struct dwc3_rk_inno *rk_inno) -+{ -+ of_platform_depopulate(rk_inno->dev); -+ -+ clk_bulk_disable_unprepare(rk_inno->num_clocks, rk_inno->clks); -+ clk_bulk_put_all(rk_inno->num_clocks, rk_inno->clks); -+ rk_inno->num_clocks = 0; -+ -+ reset_control_assert(rk_inno->resets); -+ -+ reset_control_put(rk_inno->resets); -+ -+ pm_runtime_disable(rk_inno->dev); -+ pm_runtime_put_noidle(rk_inno->dev); -+ pm_runtime_set_suspended(rk_inno->dev); -+} -+ -+static int dwc3_rk_inno_remove(struct platform_device *pdev) -+{ -+ struct dwc3_rk_inno *rk_inno = platform_get_drvdata(pdev); -+ -+ __dwc3_rk_inno_teardown(rk_inno); -+ -+ return 0; -+} -+ -+static void dwc3_rk_inno_shutdown(struct platform_device *pdev) -+{ -+ struct dwc3_rk_inno *rk_inno = platform_get_drvdata(pdev); -+ -+ __dwc3_rk_inno_teardown(rk_inno); -+} -+ -+static int __maybe_unused dwc3_rk_inno_runtime_suspend(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ clk_bulk_disable(rk_inno->num_clocks, rk_inno->clks); -+ -+ return 0; -+} -+ -+static int __maybe_unused dwc3_rk_inno_runtime_resume(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ return clk_bulk_enable(rk_inno->num_clocks, rk_inno->clks); -+} -+ -+static int __maybe_unused dwc3_rk_inno_suspend(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ reset_control_assert(rk_inno->resets); -+ -+ return 0; -+} -+ -+static int __maybe_unused dwc3_rk_inno_resume(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ reset_control_deassert(rk_inno->resets); -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops dwc3_rk_inno_dev_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(dwc3_rk_inno_suspend, dwc3_rk_inno_resume) -+ SET_RUNTIME_PM_OPS(dwc3_rk_inno_runtime_suspend, -+ dwc3_rk_inno_runtime_resume, NULL) -+}; -+ -+static const struct of_device_id of_dwc3_rk_inno_match[] = { -+ { .compatible = "rockchip,rk3328-dwc3" }, -+ { /* Sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_dwc3_rk_inno_match); -+ -+static struct platform_driver dwc3_rk_inno_driver = { -+ .probe = dwc3_rk_inno_probe, -+ .remove = dwc3_rk_inno_remove, -+ .shutdown = dwc3_rk_inno_shutdown, -+ .driver = { -+ .name = "dwc3-rk-inno", -+ .of_match_table = of_dwc3_rk_inno_match, -+ .pm = &dwc3_rk_inno_dev_pm_ops, -+ }, -+}; -+ -+module_platform_driver(dwc3_rk_inno_driver); -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("DesignWare USB3 Rockchip Innosilicon Glue Layer"); -+MODULE_AUTHOR("Peter Geis "); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 17 Feb 2019 22:14:38 +0000 -Subject: [PATCH] mmc: core: set initial signal voltage on power off - -Some boards have SD card connectors where the power rail cannot be switched -off by the driver. If the card has not been power cycled, it may still be -using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling -will fail to boot from a UHS card that continue to use 1.8V signaling. - -Set initial signal voltage in mmc_power_off() to allow re-boot to function. - -This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), -same issue have been seen on some Rockchip RK3399 boards. - -I am sending this as a RFC because I have no insights into SD/MMC subsystem, -this change fix a re-boot issue on my boards and does not break emmc/sdio. -Is this an acceptable workaround? Any advice is appreciated. - -Signed-off-by: Jonas Karlman ---- - drivers/mmc/core/core.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c -index eaf4810fe656..6f8ea06b187b 100644 ---- a/drivers/mmc/core/core.c -+++ b/drivers/mmc/core/core.c -@@ -1349,6 +1349,14 @@ void mmc_power_off(struct mmc_host *host) - if (host->ios.power_mode == MMC_POWER_OFF) - return; - -+ mmc_set_initial_signal_voltage(host); -+ -+ /* -+ * This delay should be sufficient to allow the power supply -+ * to reach the minimum voltage. -+ */ -+ mmc_delay(host->ios.power_delay_ms); -+ - mmc_pwrseq_power_off(host); - - host->ios.clock = 0; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Rudi Heitbaum -Date: Fri, 28 May 2021 10:19:50 +0000 -Subject: [PATCH] regulator: fan53555: add tcs4526 - -For rk3399pro boards the tcs4526 regulator supports the vdd_gpu -regulator. The tcs4526 regulator has a chip id of <0>. -Add the compatibile tcs,tcs4526 - -without this patch, the dmesg output is: - fan53555-regulator 0-0010: Chip ID 0 not supported! - fan53555-regulator 0-0010: Failed to setup device! - fan53555-regulator: probe of 0-0010 failed with error -22 -with this patch, the dmesg output is: - vdd_gpu: supplied by vcc5v0_sys - -The regulators are described as: -- Dedicated power management IC TCS4525 -- Lithium battery protection chip TCS4526 - -This has been tested with a Radxa Rock Pi N10. - -Signed-off-by: Rudi Heitbaum ---- - drivers/regulator/fan53555.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index f3f49cf3731b..bc8242e1dd0f 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -92,6 +92,10 @@ enum { - TCS4525_CHIP_ID_12 = 12, - }; - -+enum { -+ TCS4526_CHIP_ID_00 = 0, -+}; -+ - /* IC mask revision */ - enum { - FAN53555_CHIP_REV_00 = 0x3, -@@ -372,6 +376,7 @@ static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) - { - switch (di->chip_id) { - case TCS4525_CHIP_ID_12: -+ case TCS4526_CHIP_ID_00: - di->slew_reg = TCS4525_TIME; - di->slew_mask = TCS_SLEW_MASK; - di->slew_shift = TCS_SLEW_SHIFT; -@@ -562,6 +567,9 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { - }, { - .compatible = "tcs,tcs4525", - .data = (void *)FAN53526_VENDOR_TCS -+ }, { -+ .compatible = "tcs,tcs4526", -+ .data = (void *)FAN53526_VENDOR_TCS - }, - { } - }; -@@ -670,6 +678,9 @@ static const struct i2c_device_id fan53555_id[] = { - }, { - .name = "tcs4525", - .driver_data = FAN53526_VENDOR_TCS -+ }, { -+ .name = "tcs4526", -+ .driver_data = FAN53526_VENDOR_TCS - }, - { }, - }; diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch new file mode 100644 index 0000000000..c54e0ae4f6 --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch @@ -0,0 +1,1303 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:33 +0200 +Subject: [PATCH] media: hantro: vp8: Move noisy WARN_ON to vpu_debug + +When the VP8 decoders can't find a reference frame, +the driver falls back to the current output frame. + +This will probably produce some undesirable results, +leading to frame corruption, but shouldn't cause +noisy warnings. + +Signed-off-by: Ezequiel Garcia +Acked-by: Nicolas Dufresne +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro_g1_vp8_dec.c | 13 ++++++++++--- + .../staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c | 13 ++++++++++--- + 2 files changed, 20 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +index 96622a7f8279..2afd5996d75f 100644 +--- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +@@ -376,12 +376,17 @@ static void cfg_ref(struct hantro_ctx *ctx, + vb2_dst = hantro_get_dst_buf(ctx); + + ref = hantro_get_ref(ctx, hdr->last_frame_ts); +- if (!ref) ++ if (!ref) { ++ vpu_debug(0, "failed to find last frame ts=%llu\n", ++ hdr->last_frame_ts); + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); ++ } + vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0)); + + ref = hantro_get_ref(ctx, hdr->golden_frame_ts); +- WARN_ON(!ref && hdr->golden_frame_ts); ++ if (!ref && hdr->golden_frame_ts) ++ vpu_debug(0, "failed to find golden frame ts=%llu\n", ++ hdr->golden_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN) +@@ -389,7 +394,9 @@ static void cfg_ref(struct hantro_ctx *ctx, + vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4)); + + ref = hantro_get_ref(ctx, hdr->alt_frame_ts); +- WARN_ON(!ref && hdr->alt_frame_ts); ++ if (!ref && hdr->alt_frame_ts) ++ vpu_debug(0, "failed to find alt frame ts=%llu\n", ++ hdr->alt_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT) +diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +index 951b55f58a61..704607511b57 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c ++++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +@@ -453,12 +453,17 @@ static void cfg_ref(struct hantro_ctx *ctx, + vb2_dst = hantro_get_dst_buf(ctx); + + ref = hantro_get_ref(ctx, hdr->last_frame_ts); +- if (!ref) ++ if (!ref) { ++ vpu_debug(0, "failed to find last frame ts=%llu\n", ++ hdr->last_frame_ts); + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); ++ } + vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF0); + + ref = hantro_get_ref(ctx, hdr->golden_frame_ts); +- WARN_ON(!ref && hdr->golden_frame_ts); ++ if (!ref && hdr->golden_frame_ts) ++ vpu_debug(0, "failed to find golden frame ts=%llu\n", ++ hdr->golden_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN) +@@ -466,7 +471,9 @@ static void cfg_ref(struct hantro_ctx *ctx, + vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(2)); + + ref = hantro_get_ref(ctx, hdr->alt_frame_ts); +- WARN_ON(!ref && hdr->alt_frame_ts); ++ if (!ref && hdr->alt_frame_ts) ++ vpu_debug(0, "failed to find alt frame ts=%llu\n", ++ hdr->alt_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:34 +0200 +Subject: [PATCH] media: hantro: Make struct hantro_variant.init() optional + +The hantro_variant.init() function is there for platforms +to perform hardware-specific initialization, such as +clock rate bumping. + +Not all platforms require it, so make it optional. + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro.h | 4 ++-- + drivers/staging/media/hantro/hantro_drv.c | 10 ++++++---- + drivers/staging/media/hantro/sama5d4_vdec_hw.c | 6 ------ + 3 files changed, 8 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h +index a70c386de6f1..c2e2dca38628 100644 +--- a/drivers/staging/media/hantro/hantro.h ++++ b/drivers/staging/media/hantro/hantro.h +@@ -61,8 +61,8 @@ struct hantro_irq { + * @num_postproc_fmts: Number of post-processor formats. + * @codec: Supported codecs + * @codec_ops: Codec ops. +- * @init: Initialize hardware. +- * @runtime_resume: reenable hardware after power gating ++ * @init: Initialize hardware, optional. ++ * @runtime_resume: reenable hardware after power gating, optional. + * @irqs: array of irq names and interrupt handlers + * @num_irqs: number of irqs in the array + * @clk_names: array of clock names +diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c +index 31d8449ca1d2..9b5415176bfe 100644 +--- a/drivers/staging/media/hantro/hantro_drv.c ++++ b/drivers/staging/media/hantro/hantro_drv.c +@@ -942,10 +942,12 @@ static int hantro_probe(struct platform_device *pdev) + } + } + +- ret = vpu->variant->init(vpu); +- if (ret) { +- dev_err(&pdev->dev, "Failed to init VPU hardware\n"); +- return ret; ++ if (vpu->variant->init) { ++ ret = vpu->variant->init(vpu); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to init VPU hardware\n"); ++ return ret; ++ } + } + + pm_runtime_set_autosuspend_delay(vpu->dev, 100); +diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c +index 58ae72c2b723..9c3b8cd0b239 100644 +--- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c ++++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c +@@ -64,11 +64,6 @@ static const struct hantro_fmt sama5d4_vdec_fmts[] = { + }, + }; + +-static int sama5d4_hw_init(struct hantro_dev *vpu) +-{ +- return 0; +-} +- + /* + * Supported codec ops. + */ +@@ -109,7 +104,6 @@ const struct hantro_variant sama5d4_vdec_variant = { + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = sama5d4_vdec_codec_ops, +- .init = sama5d4_hw_init, + .irqs = sama5d4_irqs, + .num_irqs = ARRAY_SIZE(sama5d4_irqs), + .clk_names = sama5d4_clk_names, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:35 +0200 +Subject: [PATCH] media: hantro: Avoid redundant hantro_get_{dst,src}_buf() + calls + +Getting the next src/dst buffer is relatively expensive +so avoid doing it multiple times. + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++++++++--------- + .../staging/media/hantro/hantro_g1_vp8_dec.c | 18 +++++++++--------- + .../media/hantro/rockchip_vpu2_hw_vp8_dec.c | 19 +++++++++---------- + 3 files changed, 26 insertions(+), 28 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +index 5c792b7bcb79..2aa37baad0c3 100644 +--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +@@ -19,13 +19,12 @@ + #include "hantro_hw.h" + #include "hantro_v4l2.h" + +-static void set_params(struct hantro_ctx *ctx) ++static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) + { + const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; + const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; + const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; + const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; +- struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx); + struct hantro_dev *vpu = ctx->dev; + u32 reg; + +@@ -226,22 +225,20 @@ static void set_ref(struct hantro_ctx *ctx) + } + } + +-static void set_buffers(struct hantro_ctx *ctx) ++static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) + { + const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; +- struct vb2_v4l2_buffer *src_buf, *dst_buf; ++ struct vb2_v4l2_buffer *dst_buf; + struct hantro_dev *vpu = ctx->dev; + dma_addr_t src_dma, dst_dma; + size_t offset = 0; + +- src_buf = hantro_get_src_buf(ctx); +- dst_buf = hantro_get_dst_buf(ctx); +- + /* Source (stream) buffer. */ + src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR); + + /* Destination (decoded frame) buffer. */ ++ dst_buf = hantro_get_dst_buf(ctx); + dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); + /* Adjust dma addr to start at second line for bottom field */ + if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) +@@ -276,6 +273,7 @@ static void set_buffers(struct hantro_ctx *ctx) + int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *src_buf; + int ret; + + /* Prepare the H264 decoder context. */ +@@ -284,9 +282,10 @@ int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) + return ret; + + /* Configure hardware registers. */ +- set_params(ctx); ++ src_buf = hantro_get_src_buf(ctx); ++ set_params(ctx, src_buf); + set_ref(ctx); +- set_buffers(ctx); ++ set_buffers(ctx, src_buf); + + hantro_end_prepare_run(ctx); + +diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +index 2afd5996d75f..6180b23e7d94 100644 +--- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +@@ -367,13 +367,12 @@ static void cfg_tap(struct hantro_ctx *ctx, + } + + static void cfg_ref(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t ref; + +- vb2_dst = hantro_get_dst_buf(ctx); + + ref = hantro_get_ref(ctx, hdr->last_frame_ts); + if (!ref) { +@@ -405,16 +404,14 @@ static void cfg_ref(struct hantro_ctx *ctx, + } + + static void cfg_buffers(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + const struct v4l2_vp8_segment *seg = &hdr->segment; + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t dst_dma; + u32 reg; + +- vb2_dst = hantro_get_dst_buf(ctx); +- + /* Set probability table buffer address */ + vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, + G1_REG_ADDR_QTABLE); +@@ -436,6 +433,7 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) + { + const struct v4l2_ctrl_vp8_frame *hdr; + struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *vb2_dst; + size_t height = ctx->dst_fmt.height; + size_t width = ctx->dst_fmt.width; + u32 mb_width, mb_height; +@@ -499,8 +497,10 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) + cfg_qp(ctx, hdr); + cfg_parts(ctx, hdr); + cfg_tap(ctx, hdr); +- cfg_ref(ctx, hdr); +- cfg_buffers(ctx, hdr); ++ ++ vb2_dst = hantro_get_dst_buf(ctx); ++ cfg_ref(ctx, hdr, vb2_dst); ++ cfg_buffers(ctx, hdr, vb2_dst); + + hantro_end_prepare_run(ctx); + +diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +index 704607511b57..d079075448c9 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c ++++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +@@ -444,14 +444,12 @@ static void cfg_tap(struct hantro_ctx *ctx, + } + + static void cfg_ref(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t ref; + +- vb2_dst = hantro_get_dst_buf(ctx); +- + ref = hantro_get_ref(ctx, hdr->last_frame_ts); + if (!ref) { + vpu_debug(0, "failed to find last frame ts=%llu\n", +@@ -482,16 +480,14 @@ static void cfg_ref(struct hantro_ctx *ctx, + } + + static void cfg_buffers(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + const struct v4l2_vp8_segment *seg = &hdr->segment; + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t dst_dma; + u32 reg; + +- vb2_dst = hantro_get_dst_buf(ctx); +- + /* Set probability table buffer address */ + vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, + VDPU_REG_ADDR_QTABLE); +@@ -514,6 +510,7 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) + { + const struct v4l2_ctrl_vp8_frame *hdr; + struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *vb2_dst; + size_t height = ctx->dst_fmt.height; + size_t width = ctx->dst_fmt.width; + u32 mb_width, mb_height; +@@ -590,8 +587,10 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) + cfg_qp(ctx, hdr); + cfg_parts(ctx, hdr); + cfg_tap(ctx, hdr); +- cfg_ref(ctx, hdr); +- cfg_buffers(ctx, hdr); ++ ++ vb2_dst = hantro_get_dst_buf(ctx); ++ cfg_ref(ctx, hdr, vb2_dst); ++ cfg_buffers(ctx, hdr, vb2_dst); + + hantro_end_prepare_run(ctx); + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:36 +0200 +Subject: [PATCH] media: hantro: h264: Move DPB valid and long-term bitmaps + +In order to reuse these bitmaps, move this process to +struct hantro_h264_dec_hw_ctx. This will be used by +the Rockchip VDPU2 H.264 driver. + +This idea was originally proposed by Jonas Karlman +in "[RFC 08/12] media: hantro: Fix H264 decoding of field encoded content" +which was posted a while ago. + +Link: https://lore.kernel.org/linux-media/HE1PR06MB4011EA39133818A85768B91FACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++--------------- + drivers/staging/media/hantro/hantro_h264.c | 13 +++++++++++++ + drivers/staging/media/hantro/hantro_hw.h | 4 ++++ + 3 files changed, 19 insertions(+), 15 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +index 2aa37baad0c3..6faacfc44c7c 100644 +--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +@@ -129,25 +129,12 @@ static void set_ref(struct hantro_ctx *ctx) + struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; + const u8 *b0_reflist, *b1_reflist, *p_reflist; + struct hantro_dev *vpu = ctx->dev; +- u32 dpb_longterm = 0; +- u32 dpb_valid = 0; + int reg_num; + u32 reg; + int i; + +- /* +- * Set up bit maps of valid and long term DPBs. +- * NOTE: The bits are reversed, i.e. MSb is DPB 0. +- */ +- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) +- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); +- +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); +- } +- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF); +- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF); ++ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); ++ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); + + /* + * Set up reference frame picture numbers. +diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c +index ed6eaf11d96f..6d72136760e7 100644 +--- a/drivers/staging/media/hantro/hantro_h264.c ++++ b/drivers/staging/media/hantro/hantro_h264.c +@@ -229,12 +229,25 @@ static void prepare_table(struct hantro_ctx *ctx) + const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; + struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; + const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; ++ u32 dpb_longterm = 0; ++ u32 dpb_valid = 0; + int i; + + for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { + tbl->poc[i * 2] = dpb[i].top_field_order_cnt; + tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; ++ ++ /* ++ * Set up bit maps of valid and long term DPBs. ++ * NOTE: The bits are reversed, i.e. MSb is DPB 0. ++ */ ++ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) ++ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); ++ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) ++ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); + } ++ ctx->h264_dec.dpb_valid = dpb_valid << 16; ++ ctx->h264_dec.dpb_longterm = dpb_longterm << 16; + + tbl->poc[32] = dec_param->top_field_order_cnt; + tbl->poc[33] = dec_param->bottom_field_order_cnt; +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 5dcf65805396..ce678fedaad6 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -89,12 +89,16 @@ struct hantro_h264_dec_reflists { + * @dpb: DPB + * @reflists: P/B0/B1 reflists + * @ctrls: V4L2 controls attached to a run ++ * @dpb_longterm: DPB long-term ++ * @dpb_valid: DPB valid + */ + struct hantro_h264_dec_hw_ctx { + struct hantro_aux_buf priv; + struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; + struct hantro_h264_dec_reflists reflists; + struct hantro_h264_dec_ctrls ctrls; ++ u32 dpb_longterm; ++ u32 dpb_valid; + }; + + /** + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:37 +0200 +Subject: [PATCH] media: hantro: h264: Move reference picture number to a + helper + +Add a hantro_h264_get_ref_nbr() helper function to get the reference +picture numbers. This will be used by the Rockchip VDPU2 H.264 driver. + +This idea was originally proposed by Jonas Karlman in +"[RFC 09/12] media: hantro: Refactor G1 H264 code" +posted a while ago. + +Link: https://lore.kernel.org/linux-media/HE1PR06MB401165F2BA0AD8A634FDFAF2ACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro_g1_h264_dec.c | 14 ++------------ + drivers/staging/media/hantro/hantro_h264.c | 11 +++++++++++ + drivers/staging/media/hantro/hantro_hw.h | 2 ++ + 3 files changed, 15 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +index 6faacfc44c7c..236ce24ca00c 100644 +--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +@@ -126,7 +126,6 @@ static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) + + static void set_ref(struct hantro_ctx *ctx) + { +- struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; + const u8 *b0_reflist, *b1_reflist, *p_reflist; + struct hantro_dev *vpu = ctx->dev; + int reg_num; +@@ -143,17 +142,8 @@ static void set_ref(struct hantro_ctx *ctx) + * subsequential reference pictures. + */ + for (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) { +- reg = 0; +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num); +- else +- reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num); +- +- if (dpb[i + 1].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num); +- else +- reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num); +- ++ reg = G1_REG_REF_PIC_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, i)) | ++ G1_REG_REF_PIC_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, i + 1)); + vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2)); + } + +diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c +index 6d72136760e7..0b4d2491be3b 100644 +--- a/drivers/staging/media/hantro/hantro_h264.c ++++ b/drivers/staging/media/hantro/hantro_h264.c +@@ -348,6 +348,17 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, + return dma_addr; + } + ++u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) ++{ ++ const struct v4l2_h264_dpb_entry *dpb = &ctx->h264_dec.dpb[dpb_idx]; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ return 0; ++ if (dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) ++ return dpb->pic_num; ++ return dpb->frame_num; ++} ++ + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) + { + struct hantro_h264_dec_hw_ctx *h264_ctx = &ctx->h264_dec; +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index ce678fedaad6..7a8048afe357 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -238,6 +238,8 @@ void hantro_jpeg_enc_done(struct hantro_ctx *ctx); + + dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, + unsigned int dpb_idx); ++u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, ++ unsigned int dpb_idx); + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); + int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); + int hantro_h264_dec_init(struct hantro_ctx *ctx); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 19 Jul 2021 22:52:38 +0200 +Subject: [PATCH] media: hantro: Add H.264 support for Rockchip VDPU2 + +Rockchip VDPU2 core is present on RK3328, RK3326/PX30, RK3399 +and others. It's similar to Hantro G1, but it's not compatible with it. + +Signed-off-by: Jonas Karlman +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/Makefile | 1 + + drivers/staging/media/hantro/hantro_hw.h | 1 + + .../media/hantro/rockchip_vpu2_hw_h264_dec.c | 491 ++++++++++++++++++ + 3 files changed, 493 insertions(+) + create mode 100644 drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c + +diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile +index 287370188d2a..90036831fec4 100644 +--- a/drivers/staging/media/hantro/Makefile ++++ b/drivers/staging/media/hantro/Makefile +@@ -13,6 +13,7 @@ hantro-vpu-y += \ + hantro_g2_hevc_dec.o \ + hantro_g1_vp8_dec.o \ + rockchip_vpu2_hw_jpeg_enc.o \ ++ rockchip_vpu2_hw_h264_dec.o \ + rockchip_vpu2_hw_mpeg2_dec.o \ + rockchip_vpu2_hw_vp8_dec.o \ + hantro_jpeg.o \ +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 7a8048afe357..9296624654a6 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -241,6 +241,7 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, + u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, + unsigned int dpb_idx); + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); ++int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx); + int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); + int hantro_h264_dec_init(struct hantro_ctx *ctx); + void hantro_h264_dec_exit(struct hantro_ctx *ctx); +diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c +new file mode 100644 +index 000000000000..64a6330475eb +--- /dev/null ++++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c +@@ -0,0 +1,491 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Hantro VPU codec driver ++ * ++ * Copyright (c) 2014 Rockchip Electronics Co., Ltd. ++ * Hertz Wong ++ * Herman Chen ++ * ++ * Copyright (C) 2014 Google, Inc. ++ * Tomasz Figa ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "hantro_hw.h" ++#include "hantro_v4l2.h" ++ ++#define VDPU_SWREG(nr) ((nr) * 4) ++ ++#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63) ++#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64) ++#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61) ++#define VDPU_REG_DIR_MV_BASE VDPU_SWREG(62) ++#define VDPU_REG_REFER_BASE(i) (VDPU_SWREG(84 + (i))) ++#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) ++ ++#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) ++#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) ++#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) ++#define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) ++#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) ++ ++#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) ++#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) ++ ++#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) ++#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) ++#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) ++ ++#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0)) ++ ++#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0) ++#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0) ++#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0) ++#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) ++#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) ++#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) ++ ++#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0) ++#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16)) ++#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8)) ++#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0)) ++ ++#define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0) ++#define VDPU_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(21) : 0) ++#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) ++#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0) ++#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0) ++#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0) ++#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0) ++#define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0) ++#define VDPU_REG_PICORD_COUNT_E(v) ((v) ? BIT(6) : 0) ++#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0) ++#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0) ++ ++#define VDPU_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22)) ++#define VDPU_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12)) ++#define VDPU_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2)) ++ ++#define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0) ++ ++#define VDPU_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_F5(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_F4(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_F11(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_F10(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_F9(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_F8(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_F7(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_F15(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_F14(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_F13(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_B4(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_B3(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_B2(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_B1(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_B0(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_B10(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_B9(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_B8(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_B7(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_B6(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_B15(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_B14(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_B13(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_B12(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_PINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_PINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_PINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_PINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0)) ++ ++#define VDPU_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0)) ++ ++#define VDPU_REG_STRM_START_BIT(v) (((v) << 0) & GENMASK(5, 0)) ++ ++#define VDPU_REG_CH_QP_OFFSET2(v) (((v) << 22) & GENMASK(26, 22)) ++#define VDPU_REG_CH_QP_OFFSET(v) (((v) << 17) & GENMASK(21, 17)) ++#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 9) & GENMASK(16, 9)) ++#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 0) & GENMASK(8, 0)) ++ ++#define VDPU_REG_WEIGHT_BIPR_IDC(v) (((v) << 16) & GENMASK(17, 16)) ++#define VDPU_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_FILT_CTRL_PRES(v) ((v) ? BIT(31) : 0) ++#define VDPU_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(30) : 0) ++#define VDPU_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16)) ++#define VDPU_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFPIC_MK_LEN(v) (((v) << 16) & GENMASK(26, 16)) ++#define VDPU_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24)) ++#define VDPU_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19)) ++#define VDPU_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14)) ++#define VDPU_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0)) ++ ++#define VDPU_REG_IDR_PIC_E(v) ((v) ? BIT(8) : 0) ++#define VDPU_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(7) : 0) ++#define VDPU_REG_BLACKWHITE_E(v) ((v) ? BIT(6) : 0) ++#define VDPU_REG_CABAC_E(v) ((v) ? BIT(5) : 0) ++#define VDPU_REG_WEIGHT_PRED_E(v) ((v) ? BIT(4) : 0) ++#define VDPU_REG_CONST_INTRA_E(v) ((v) ? BIT(3) : 0) ++#define VDPU_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(2) : 0) ++#define VDPU_REG_TYPE1_QUANT_E(v) ((v) ? BIT(1) : 0) ++#define VDPU_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0) ++ ++static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) ++{ ++ const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; ++ const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; ++ const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; ++ const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; ++ struct hantro_dev *vpu = ctx->dev; ++ u32 reg; ++ ++ reg = VDPU_REG_DEC_ADV_PRE_DIS(0) | ++ VDPU_REG_DEC_SCMD_DIS(0) | ++ VDPU_REG_FILTERING_DIS(0) | ++ VDPU_REG_PIC_FIXED_QUANT(0) | ++ VDPU_REG_DEC_LATENCY(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); ++ ++ reg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) | ++ VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); ++ ++ reg = VDPU_REG_APF_THRESHOLD(8) | ++ VDPU_REG_STARTMB_X(0) | ++ VDPU_REG_STARTMB_Y(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); ++ ++ reg = VDPU_REG_DEC_MODE(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); ++ ++ reg = VDPU_REG_DEC_STRENDIAN_E(1) | ++ VDPU_REG_DEC_STRSWAP32_E(1) | ++ VDPU_REG_DEC_OUTSWAP32_E(1) | ++ VDPU_REG_DEC_INSWAP32_E(1) | ++ VDPU_REG_DEC_OUT_ENDIAN(1) | ++ VDPU_REG_DEC_IN_ENDIAN(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); ++ ++ reg = VDPU_REG_DEC_DATA_DISC_E(0) | ++ VDPU_REG_DEC_MAX_BURST(16) | ++ VDPU_REG_DEC_AXI_WR_ID(0) | ++ VDPU_REG_DEC_AXI_RD_ID(0xff); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); ++ ++ reg = VDPU_REG_START_CODE_E(1) | ++ VDPU_REG_CH_8PIX_ILEAV_E(0) | ++ VDPU_REG_RLC_MODE_E(0) | ++ VDPU_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && ++ (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || ++ dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) | ++ VDPU_REG_PIC_FIELDMODE_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) | ++ VDPU_REG_PIC_TOPFIELD_E(!(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)) | ++ VDPU_REG_WRITE_MVS_E((sps->profile_idc > 66) && dec_param->nal_ref_idc) | ++ VDPU_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) | ++ VDPU_REG_PICORD_COUNT_E(sps->profile_idc > 66) | ++ VDPU_REG_DEC_TIMEOUT_E(1) | ++ VDPU_REG_DEC_CLK_GATE_E(1); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); ++ ++ reg = VDPU_REG_PRED_BC_TAP_0_0(1) | ++ VDPU_REG_PRED_BC_TAP_0_1((u32)-5) | ++ VDPU_REG_PRED_BC_TAP_0_2(20); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); ++ ++ reg = VDPU_REG_REFBU_E(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); ++ ++ reg = VDPU_REG_STRM_START_BIT(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109)); ++ ++ reg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) | ++ VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) | ++ VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) | ++ VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110)); ++ ++ reg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) | ++ VDPU_REG_REF_FRAMES(sps->max_num_ref_frames); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111)); ++ ++ reg = VDPU_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) | ++ VDPU_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) | ++ VDPU_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | ++ VDPU_REG_FRAMENUM(dec_param->frame_num); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112)); ++ ++ reg = VDPU_REG_REFPIC_MK_LEN(dec_param->dec_ref_pic_marking_bit_size) | ++ VDPU_REG_IDR_PIC_ID(dec_param->idr_pic_id); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113)); ++ ++ reg = VDPU_REG_PPS_ID(pps->pic_parameter_set_id) | ++ VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | ++ VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | ++ VDPU_REG_POC_LENGTH(dec_param->pic_order_cnt_bit_size); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114)); ++ ++ reg = VDPU_REG_IDR_PIC_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) | ++ VDPU_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) | ++ VDPU_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) | ++ VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) | ++ VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) | ++ VDPU_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) | ++ VDPU_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) | ++ VDPU_REG_TYPE1_QUANT_E(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) | ++ VDPU_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115)); ++} ++ ++static void set_ref(struct hantro_ctx *ctx) ++{ ++ const u8 *b0_reflist, *b1_reflist, *p_reflist; ++ struct hantro_dev *vpu = ctx->dev; ++ u32 reg; ++ int i; ++ ++ b0_reflist = ctx->h264_dec.reflists.b0; ++ b1_reflist = ctx->h264_dec.reflists.b1; ++ p_reflist = ctx->h264_dec.reflists.p; ++ ++ reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9]) | ++ VDPU_REG_PINIT_RLIST_F8(p_reflist[8]) | ++ VDPU_REG_PINIT_RLIST_F7(p_reflist[7]) | ++ VDPU_REG_PINIT_RLIST_F6(p_reflist[6]) | ++ VDPU_REG_PINIT_RLIST_F5(p_reflist[5]) | ++ VDPU_REG_PINIT_RLIST_F4(p_reflist[4]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74)); ++ ++ reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15]) | ++ VDPU_REG_PINIT_RLIST_F14(p_reflist[14]) | ++ VDPU_REG_PINIT_RLIST_F13(p_reflist[13]) | ++ VDPU_REG_PINIT_RLIST_F12(p_reflist[12]) | ++ VDPU_REG_PINIT_RLIST_F11(p_reflist[11]) | ++ VDPU_REG_PINIT_RLIST_F10(p_reflist[10]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75)); ++ ++ reg = VDPU_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) | ++ VDPU_REG_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, 0)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76)); ++ ++ reg = VDPU_REG_REFER3_NBR(hantro_h264_get_ref_nbr(ctx, 3)) | ++ VDPU_REG_REFER2_NBR(hantro_h264_get_ref_nbr(ctx, 2)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77)); ++ ++ reg = VDPU_REG_REFER5_NBR(hantro_h264_get_ref_nbr(ctx, 5)) | ++ VDPU_REG_REFER4_NBR(hantro_h264_get_ref_nbr(ctx, 4)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78)); ++ ++ reg = VDPU_REG_REFER7_NBR(hantro_h264_get_ref_nbr(ctx, 7)) | ++ VDPU_REG_REFER6_NBR(hantro_h264_get_ref_nbr(ctx, 6)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79)); ++ ++ reg = VDPU_REG_REFER9_NBR(hantro_h264_get_ref_nbr(ctx, 9)) | ++ VDPU_REG_REFER8_NBR(hantro_h264_get_ref_nbr(ctx, 8)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80)); ++ ++ reg = VDPU_REG_REFER11_NBR(hantro_h264_get_ref_nbr(ctx, 11)) | ++ VDPU_REG_REFER10_NBR(hantro_h264_get_ref_nbr(ctx, 10)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81)); ++ ++ reg = VDPU_REG_REFER13_NBR(hantro_h264_get_ref_nbr(ctx, 13)) | ++ VDPU_REG_REFER12_NBR(hantro_h264_get_ref_nbr(ctx, 12)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82)); ++ ++ reg = VDPU_REG_REFER15_NBR(hantro_h264_get_ref_nbr(ctx, 15)) | ++ VDPU_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83)); ++ ++ reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5]) | ++ VDPU_REG_BINIT_RLIST_F4(b0_reflist[4]) | ++ VDPU_REG_BINIT_RLIST_F3(b0_reflist[3]) | ++ VDPU_REG_BINIT_RLIST_F2(b0_reflist[2]) | ++ VDPU_REG_BINIT_RLIST_F1(b0_reflist[1]) | ++ VDPU_REG_BINIT_RLIST_F0(b0_reflist[0]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100)); ++ ++ reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11]) | ++ VDPU_REG_BINIT_RLIST_F10(b0_reflist[10]) | ++ VDPU_REG_BINIT_RLIST_F9(b0_reflist[9]) | ++ VDPU_REG_BINIT_RLIST_F8(b0_reflist[8]) | ++ VDPU_REG_BINIT_RLIST_F7(b0_reflist[7]) | ++ VDPU_REG_BINIT_RLIST_F6(b0_reflist[6]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101)); ++ ++ reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15]) | ++ VDPU_REG_BINIT_RLIST_F14(b0_reflist[14]) | ++ VDPU_REG_BINIT_RLIST_F13(b0_reflist[13]) | ++ VDPU_REG_BINIT_RLIST_F12(b0_reflist[12]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102)); ++ ++ reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5]) | ++ VDPU_REG_BINIT_RLIST_B4(b1_reflist[4]) | ++ VDPU_REG_BINIT_RLIST_B3(b1_reflist[3]) | ++ VDPU_REG_BINIT_RLIST_B2(b1_reflist[2]) | ++ VDPU_REG_BINIT_RLIST_B1(b1_reflist[1]) | ++ VDPU_REG_BINIT_RLIST_B0(b1_reflist[0]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103)); ++ ++ reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11]) | ++ VDPU_REG_BINIT_RLIST_B10(b1_reflist[10]) | ++ VDPU_REG_BINIT_RLIST_B9(b1_reflist[9]) | ++ VDPU_REG_BINIT_RLIST_B8(b1_reflist[8]) | ++ VDPU_REG_BINIT_RLIST_B7(b1_reflist[7]) | ++ VDPU_REG_BINIT_RLIST_B6(b1_reflist[6]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104)); ++ ++ reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15]) | ++ VDPU_REG_BINIT_RLIST_B14(b1_reflist[14]) | ++ VDPU_REG_BINIT_RLIST_B13(b1_reflist[13]) | ++ VDPU_REG_BINIT_RLIST_B12(b1_reflist[12]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105)); ++ ++ reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3]) | ++ VDPU_REG_PINIT_RLIST_F2(p_reflist[2]) | ++ VDPU_REG_PINIT_RLIST_F1(p_reflist[1]) | ++ VDPU_REG_PINIT_RLIST_F0(p_reflist[0]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106)); ++ ++ reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107)); ++ ++ reg = VDPU_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108)); ++ ++ /* Set up addresses of DPB buffers. */ ++ for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) { ++ dma_addr_t dma_addr = hantro_h264_get_ref_buf(ctx, i); ++ ++ vdpu_write_relaxed(vpu, dma_addr, VDPU_REG_REFER_BASE(i)); ++ } ++} ++ ++static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) ++{ ++ const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; ++ struct vb2_v4l2_buffer *dst_buf; ++ struct hantro_dev *vpu = ctx->dev; ++ dma_addr_t src_dma, dst_dma; ++ size_t offset = 0; ++ ++ /* Source (stream) buffer. */ ++ src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); ++ vdpu_write_relaxed(vpu, src_dma, VDPU_REG_RLC_VLC_BASE); ++ ++ /* Destination (decoded frame) buffer. */ ++ dst_buf = hantro_get_dst_buf(ctx); ++ dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); ++ /* Adjust dma addr to start at second line for bottom field */ ++ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ++ offset = ALIGN(ctx->src_fmt.width, MB_DIM); ++ vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DEC_OUT_BASE); ++ ++ /* Higher profiles require DMV buffer appended to reference frames. */ ++ if (ctrls->sps->profile_idc > 66 && ctrls->decode->nal_ref_idc) { ++ unsigned int bytes_per_mb = 384; ++ ++ /* DMV buffer for monochrome start directly after Y-plane */ ++ if (ctrls->sps->profile_idc >= 100 && ++ ctrls->sps->chroma_format_idc == 0) ++ bytes_per_mb = 256; ++ offset = bytes_per_mb * MB_WIDTH(ctx->src_fmt.width) * ++ MB_HEIGHT(ctx->src_fmt.height); ++ ++ /* ++ * DMV buffer is split in two for field encoded frames, ++ * adjust offset for bottom field ++ */ ++ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ++ offset += 32 * MB_WIDTH(ctx->src_fmt.width) * ++ MB_HEIGHT(ctx->src_fmt.height); ++ vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DIR_MV_BASE); ++ } ++ ++ /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ ++ vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE); ++} ++ ++int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx) ++{ ++ struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *src_buf; ++ u32 reg; ++ int ret; ++ ++ /* Prepare the H264 decoder context. */ ++ ret = hantro_h264_dec_prepare_run(ctx); ++ if (ret) ++ return ret; ++ ++ src_buf = hantro_get_src_buf(ctx); ++ set_params(ctx, src_buf); ++ set_ref(ctx); ++ set_buffers(ctx, src_buf); ++ ++ hantro_end_prepare_run(ctx); ++ ++ /* Start decoding! */ ++ reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1); ++ vdpu_write(vpu, reg, VDPU_SWREG(57)); ++ ++ return 0; ++} + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:39 +0200 +Subject: [PATCH] media: hantro: Enable H.264 on Rockchip VDPU2 + +Given H.264 support for VDPU2 was just added, let's enable it. +For now, this is only enabled on platform that don't have +an RKVDEC core, such as RK3328. + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index 3ccc16413f42..e4e3b5e7689b 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + }, ++ { ++ .fourcc = V4L2_PIX_FMT_H264_SLICE, ++ .codec_mode = HANTRO_MODE_H264_DEC, ++ .max_depth = 2, ++ .frmsize = { ++ .min_width = 48, ++ .max_width = 1920, ++ .step_width = MB_DIM, ++ .min_height = 48, ++ .max_height = 1088, ++ .step_height = MB_DIM, ++ }, ++ }, + { + .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, + .codec_mode = HANTRO_MODE_MPEG2_DEC, +@@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { + .init = hantro_jpeg_enc_init, + .exit = hantro_jpeg_enc_exit, + }, ++ [HANTRO_MODE_H264_DEC] = { ++ .run = rockchip_vpu2_h264_dec_run, ++ .reset = rockchip_vpu2_dec_reset, ++ .init = hantro_h264_dec_init, ++ .exit = hantro_h264_dec_exit, ++ }, + [HANTRO_MODE_MPEG2_DEC] = { + .run = rockchip_vpu2_mpeg2_dec_run, + .reset = rockchip_vpu2_dec_reset, +@@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = { + "aclk", "hclk" + }; + ++/* VDPU1/VEPU1 */ ++ + const struct hantro_variant rk3036_vpu_variant = { + .dec_offset = 0x400, + .dec_fmts = rk3066_vpu_dec_fmts, +@@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = { + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; + ++/* VDPU2/VEPU2 */ ++ + const struct hantro_variant rk3328_vpu_variant = { + .dec_offset = 0x400, + .dec_fmts = rk3399_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), +- .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER, ++ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | ++ HANTRO_H264_DECODER, + .codec_ops = rk3399_vpu_codec_ops, + .irqs = rockchip_vdpu2_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Mon, 19 Jul 2021 22:52:41 +0200 +Subject: [PATCH] media: dt-bindings: media: rockchip-vpu: Add PX30 compatible + +The Rockchip PX30 SoC has a Hantro VPU that features a decoder (VDPU2) +and an encoder (VEPU2). + +Suggested-by: Alex Bee +Signed-off-by: Paul Kocialkowski +Signed-off-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml +index b88172a59de7..bacb60a34989 100644 +--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml ++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml +@@ -22,6 +22,7 @@ properties: + - rockchip,rk3288-vpu + - rockchip,rk3328-vpu + - rockchip,rk3399-vpu ++ - rockchip,px30-vpu + - items: + - const: rockchip,rk3188-vpu + - const: rockchip,rk3066-vpu + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Mon, 19 Jul 2021 22:52:40 +0200 +Subject: [PATCH] media: hantro: Add support for the Rockchip PX30 + +The PX30 SoC includes both the VDPU2 and VEPU2 blocks which are similar +to the RK3399 (Hantro G1/H1 with shuffled registers). + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro_drv.c | 1 + + drivers/staging/media/hantro/hantro_hw.h | 1 + + drivers/staging/media/hantro/rockchip_vpu_hw.c | 17 +++++++++++++++++ + 3 files changed, 19 insertions(+) + +diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c +index 9b5415176bfe..8a2edd67f2c6 100644 +--- a/drivers/staging/media/hantro/hantro_drv.c ++++ b/drivers/staging/media/hantro/hantro_drv.c +@@ -582,6 +582,7 @@ static const struct v4l2_file_operations hantro_fops = { + + static const struct of_device_id of_hantro_match[] = { + #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP ++ { .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, }, + { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, }, + { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, }, + { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 9296624654a6..df7b5e3a57b9 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -209,6 +209,7 @@ enum hantro_enc_fmt { + + extern const struct hantro_variant imx8mq_vpu_g2_variant; + extern const struct hantro_variant imx8mq_vpu_variant; ++extern const struct hantro_variant px30_vpu_variant; + extern const struct hantro_variant rk3036_vpu_variant; + extern const struct hantro_variant rk3066_vpu_variant; + extern const struct hantro_variant rk3288_vpu_variant; +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index e4e3b5e7689b..d4f52957cc53 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -548,3 +548,20 @@ const struct hantro_variant rk3399_vpu_variant = { + .clk_names = rockchip_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; ++ ++const struct hantro_variant px30_vpu_variant = { ++ .enc_offset = 0x0, ++ .enc_fmts = rockchip_vpu_enc_fmts, ++ .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), ++ .dec_offset = 0x400, ++ .dec_fmts = rk3399_vpu_dec_fmts, ++ .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), ++ .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | ++ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, ++ .codec_ops = rk3399_vpu_codec_ops, ++ .irqs = rockchip_vpu2_irqs, ++ .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), ++ .init = rk3036_vpu_hw_init, ++ .clk_names = rockchip_vpu_clk_names, ++ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) ++}; diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch similarity index 73% rename from projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch rename to projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch index a835cda740..07dc5ef7bf 100644 --- a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch @@ -20,7 +20,7 @@ Reviewed-by: Ezequiel Garcia 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 7cc3b478a5f4..054d2e3eed67 100644 +index 76e97cbe2512..af44a16c0c4a 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -752,7 +752,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -47,10 +47,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 1263991de76f..71a6b7b0b057 100644 +index 7131156c1f2c..65a8334a188b 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -223,6 +223,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -233,6 +233,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, pix_mp->pixelformat = coded_desc->decoded_fmts[0]; /* Always apply the frmsize constraint of the coded end. */ @@ -83,7 +83,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 054d2e3eed67..d46424ba88e8 100644 +index af44a16c0c4a..9852c3519f56 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -671,8 +671,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, @@ -98,7 +98,7 @@ index 054d2e3eed67..d46424ba88e8 100644 FRAME_MBS_ONLY_FLAG); WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD), diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 71a6b7b0b057..f405dd72ad93 100644 +index 65a8334a188b..f4c5ee4a1e26 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -29,8 +29,11 @@ @@ -146,7 +146,7 @@ Reviewed-by: Ezequiel Garcia 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index d46424ba88e8..6536cf0d6054 100644 +index 9852c3519f56..f3ff3e709169 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, @@ -179,7 +179,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 6536cf0d6054..bf632d45282b 100644 +index f3ff3e709169..503ae683d0fd 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -1015,8 +1015,9 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, @@ -214,7 +214,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 3dc17ebe14fa..4102c373b48a 100644 +index 04af03285a20..ae585828c388 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -333,6 +333,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf @@ -345,230 +345,13 @@ of 8 for NV15 and 4 for NV20. Signed-off-by: Jonas Karlman --- - .../userspace-api/media/v4l/pixfmt-nv15.rst | 101 ++++++++++++++++++ - .../userspace-api/media/v4l/pixfmt-nv20.rst | 99 +++++++++++++++++ - .../userspace-api/media/v4l/yuv-formats.rst | 2 + - drivers/media/v4l2-core/v4l2-common.c | 3 + - drivers/media/v4l2-core/v4l2-ioctl.c | 2 + - include/uapi/linux/videodev2.h | 3 + - 6 files changed, 210 insertions(+) - create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-nv15.rst - create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-nv20.rst + drivers/media/v4l2-core/v4l2-common.c | 3 +++ + drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ + include/uapi/linux/videodev2.h | 3 +++ + 3 files changed, 8 insertions(+) -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-nv15.rst b/Documentation/userspace-api/media/v4l/pixfmt-nv15.rst -new file mode 100644 -index 000000000000..d059db58c6e0 ---- /dev/null -+++ b/Documentation/userspace-api/media/v4l/pixfmt-nv15.rst -@@ -0,0 +1,101 @@ -+.. Permission is granted to copy, distribute and/or modify this -+.. document under the terms of the GNU Free Documentation License, -+.. Version 1.1 or any later version published by the Free Software -+.. Foundation, with no Invariant Sections, no Front-Cover Texts -+.. and no Back-Cover Texts. A copy of the license is included at -+.. Documentation/userspace-api/media/fdl-appendix.rst. -+.. -+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections -+ -+.. _V4L2-PIX-FMT-NV15: -+ -+************************** -+V4L2_PIX_FMT_NV15 ('NV15') -+************************** -+ -+Format with ½ horizontal and vertical chroma resolution, also known as -+YUV 4:2:0. One luminance and one chrominance plane with alternating -+chroma samples similar to ``V4L2_PIX_FMT_NV12`` but with 10-bit samples -+that are grouped into four and packed into five bytes. -+ -+The '15' suffix refers to the optimum effective bits per pixel which is -+achieved when the total number of luminance samples is a multiple of 8. -+ -+ -+Description -+=========== -+ -+This is a packed 10-bit two-plane version of the YUV 4:2:0 format. The -+three components are separated into two sub-images or planes. The Y plane -+is first. The Y plane has five bytes per each group of four pixels. A -+combined CbCr plane immediately follows the Y plane in memory. The CbCr -+plane is the same width, in bytes, as the Y plane (and of the image), but -+is half as tall in pixels. Each CbCr pair belongs to four pixels. For -+example, Cb\ :sub:`00`/Cr\ :sub:`00` belongs to Y'\ :sub:`00`, -+Y'\ :sub:`01`, Y'\ :sub:`10`, Y'\ :sub:`11`. -+ -+If the Y plane has pad bytes after each row, then the CbCr plane has as -+many pad bytes after its rows. -+ -+**Byte Order.** -+Little endian. Each cell is one byte. Pixels cross the byte boundary. -+ -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - start + 0: -+ - Y'\ :sub:`00[7:0]` -+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]` -+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]` -+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]` -+ - Y'\ :sub:`03[9:2]` -+ * - start + 5: -+ - Y'\ :sub:`10[7:0]` -+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]` -+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]` -+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]` -+ - Y'\ :sub:`13[9:2]` -+ * - start + 10: -+ - Cb'\ :sub:`00[7:0]` -+ - Cr'\ :sub:`00[5:0]`\ Cb'\ :sub:`00[9:8]` -+ - Cb'\ :sub:`01[3:0]`\ Cr'\ :sub:`00[9:6]` -+ - Cr'\ :sub:`01[1:0]`\ Cb'\ :sub:`01[9:4]` -+ - Cr'\ :sub:`01[9:2]` -+ -+ -+**Color Sample Location:** -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - -+ - 0 -+ - -+ - 1 -+ - 2 -+ - -+ - 3 -+ * - 0 -+ - Y -+ - -+ - Y -+ - Y -+ - -+ - Y -+ * - -+ - -+ - C -+ - -+ - -+ - C -+ - -+ * - 1 -+ - Y -+ - -+ - Y -+ - Y -+ - -+ - Y -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-nv20.rst b/Documentation/userspace-api/media/v4l/pixfmt-nv20.rst -new file mode 100644 -index 000000000000..a8123be0baa3 ---- /dev/null -+++ b/Documentation/userspace-api/media/v4l/pixfmt-nv20.rst -@@ -0,0 +1,99 @@ -+.. Permission is granted to copy, distribute and/or modify this -+.. document under the terms of the GNU Free Documentation License, -+.. Version 1.1 or any later version published by the Free Software -+.. Foundation, with no Invariant Sections, no Front-Cover Texts -+.. and no Back-Cover Texts. A copy of the license is included at -+.. Documentation/userspace-api/media/fdl-appendix.rst. -+.. -+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections -+ -+.. _V4L2-PIX-FMT-NV20: -+ -+************************** -+V4L2_PIX_FMT_NV20 ('NV20') -+************************** -+ -+Format with ½ horizontal chroma resolution, also known as YUV 4:2:2. -+One luminance and one chrominance plane with alternating chroma samples -+similar to ``V4L2_PIX_FMT_NV16`` but with 10-bit samples -+that are grouped into four and packed into five bytes. -+ -+The '20' suffix refers to the optimum effective bits per pixel which is -+achieved when the total number of luminance samples is a multiple of 4. -+ -+ -+Description -+=========== -+ -+This is a packed 10-bit two-plane version of the YUV 4:2:2 format. The -+three components are separated into two sub-images or planes. The Y plane -+is first. The Y plane has five bytes per each group of four pixels. A -+combined CbCr plane immediately follows the Y plane in memory. The CbCr -+plane is the same width and height, in bytes, as the Y plane (and of the -+image). Each CbCr pair belongs to two pixels. For example, -+Cb\ :sub:`00`/Cr\ :sub:`00` belongs to Y'\ :sub:`00`, Y'\ :sub:`01`. -+ -+If the Y plane has pad bytes after each row, then the CbCr plane has as -+many pad bytes after its rows. -+ -+**Byte Order.** -+Little endian. Each cell is one byte. Pixels cross the byte boundary. -+ -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - start + 0: -+ - Y'\ :sub:`00[7:0]` -+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]` -+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]` -+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]` -+ - Y'\ :sub:`03[9:2]` -+ * - start + 5: -+ - Y'\ :sub:`10[7:0]` -+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]` -+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]` -+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]` -+ - Y'\ :sub:`13[9:2]` -+ * - start + 10: -+ - Cb'\ :sub:`00[7:0]` -+ - Cr'\ :sub:`00[5:0]`\ Cb'\ :sub:`00[9:8]` -+ - Cb'\ :sub:`01[3:0]`\ Cr'\ :sub:`00[9:6]` -+ - Cr'\ :sub:`01[1:0]`\ Cb'\ :sub:`01[9:4]` -+ - Cr'\ :sub:`01[9:2]` -+ * - start + 15: -+ - Cb'\ :sub:`10[7:0]` -+ - Cr'\ :sub:`10[5:0]`\ Cb'\ :sub:`10[9:8]` -+ - Cb'\ :sub:`11[3:0]`\ Cr'\ :sub:`10[9:6]` -+ - Cr'\ :sub:`11[1:0]`\ Cb'\ :sub:`11[9:4]` -+ - Cr'\ :sub:`11[9:2]` -+ -+ -+**Color Sample Location:** -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - -+ - 0 -+ - -+ - 1 -+ - 2 -+ - -+ - 3 -+ * - 0 -+ - Y -+ - C -+ - Y -+ - Y -+ - C -+ - Y -+ * - 1 -+ - Y -+ - C -+ - Y -+ - Y -+ - C -+ - Y diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 4102c373b48a..0caac755d303 100644 +index ae585828c388..5bafbdbe30b0 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) @@ -582,10 +365,10 @@ index 4102c373b48a..0caac755d303 100644 { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 9eda8b91d17a..1ff68c1bf14a 100644 +index 05d5db3d85e5..fe43d785414c 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1319,6 +1319,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1282,6 +1282,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break; case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break; case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break; @@ -595,12 +378,12 @@ index 9eda8b91d17a..1ff68c1bf14a 100644 case V4L2_PIX_FMT_NV21M: descr = "Y/CrCb 4:2:0 (N-C)"; break; case V4L2_PIX_FMT_NV16M: descr = "Y/CbCr 4:2:2 (N-C)"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 534eaa4d39bc..f21eba15ceae 100644 +index 9260791b8438..169f8ad6fade 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h -@@ -609,6 +609,9 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ +@@ -603,6 +603,9 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ + #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ +#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */ @@ -626,7 +409,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index bf632d45282b..6f2d41b2e076 100644 +index 503ae683d0fd..88f5f4bb320b 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -893,9 +893,9 @@ static void config_registers(struct rkvdec_ctx *ctx, @@ -671,7 +454,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index f405dd72ad93..c81ca5c7e979 100644 +index f4c5ee4a1e26..d8d0eab9e25d 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -27,6 +27,17 @@ @@ -692,7 +475,7 @@ index f405dd72ad93..c81ca5c7e979 100644 static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -167,13 +178,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) +@@ -177,13 +188,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; @@ -709,7 +492,7 @@ index f405dd72ad93..c81ca5c7e979 100644 } static int rkvdec_enum_framesizes(struct file *file, void *priv, -@@ -239,13 +246,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -249,13 +256,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, &pix_mp->height, &coded_desc->frmsize); @@ -743,7 +526,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index c81ca5c7e979..a11474214bde 100644 +index d8d0eab9e25d..d31344c4acaa 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -38,6 +38,16 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, @@ -802,7 +585,7 @@ index c81ca5c7e979..a11474214bde 100644 }; static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -@@ -176,6 +209,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) +@@ -186,6 +219,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->decoded_fmt; @@ -810,7 +593,7 @@ index c81ca5c7e979..a11474214bde 100644 rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -@@ -231,13 +265,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -241,13 +275,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, if (WARN_ON(!coded_desc)) return -EINVAL; @@ -834,7 +617,7 @@ index c81ca5c7e979..a11474214bde 100644 /* Always apply the frmsize constraint of the coded end. */ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -312,6 +350,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, +@@ -322,6 +360,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, return ret; ctx->decoded_fmt = *f; @@ -842,7 +625,7 @@ index c81ca5c7e979..a11474214bde 100644 return 0; } -@@ -401,6 +440,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, +@@ -411,6 +450,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, if (WARN_ON(!ctx->coded_fmt_desc)) return -EINVAL; @@ -858,10 +641,10 @@ index c81ca5c7e979..a11474214bde 100644 return -EINVAL; diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 77a137cca88e..e95c52e3168a 100644 +index 52ac3874c5e5..7b6f44ee8a1a 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -63,6 +63,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) +@@ -62,6 +62,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); @@ -869,7 +652,7 @@ index 77a137cca88e..e95c52e3168a 100644 int (*start)(struct rkvdec_ctx *ctx); void (*stop)(struct rkvdec_ctx *ctx); int (*run)(struct rkvdec_ctx *ctx); -@@ -96,6 +97,7 @@ struct rkvdec_ctx { +@@ -95,6 +96,7 @@ struct rkvdec_ctx { struct v4l2_fh fh; struct v4l2_format coded_fmt; struct v4l2_format decoded_fmt; @@ -898,7 +681,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 6f2d41b2e076..c115cd362a7f 100644 +index 88f5f4bb320b..c9a551dbd9bc 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -1021,6 +1021,25 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, @@ -936,7 +719,7 @@ index 6f2d41b2e076..c115cd362a7f 100644 .stop = rkvdec_h264_stop, .run = rkvdec_h264_run, diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index a11474214bde..b57a39ce4f48 100644 +index d31344c4acaa..d068383aeea8 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, @@ -973,7 +756,7 @@ index a11474214bde..b57a39ce4f48 100644 return -EINVAL; if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -@@ -145,6 +141,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { +@@ -155,6 +151,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV12, @@ -983,46 +766,3 @@ index a11474214bde..b57a39ce4f48 100644 }; static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:38 +0000 -Subject: [PATCH] media: rkvdec: h264: Support profile and level controls - -The Rockchip Video Decoder used in RK3399 supports H.264 profiles from -Baseline to High 4:2:2 up to Level 5.1, except for the Extended profile. - -Expose the V4L2_CID_MPEG_VIDEO_H264_PROFILE and the -V4L2_CID_MPEG_VIDEO_H264_LEVEL control, so that userspace can query the -driver for the list of supported profiles and level. - -Signed-off-by: Jonas Karlman -Reviewed-by: Ezequiel Garcia ---- - drivers/staging/media/rkvdec/rkvdec.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index b57a39ce4f48..9492822c12ae 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -132,6 +132,19 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - .cfg.def = V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B, - .cfg.max = V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B, - }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE, -+ .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422, -+ .cfg.menu_skip_mask = -+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), -+ .cfg.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, -+ .cfg.max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1, -+ }, - }; - - static const struct rkvdec_ctrls rkvdec_h264_ctrls = { diff --git a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch similarity index 60% rename from projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch rename to projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch index 46a5a8f046..17d13f171f 100644 --- a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch @@ -24,10 +24,10 @@ Reviewed-by: Sandy Huang 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c -index 722c7ebe4e88..2daf8a304b53 100644 +index eda832f9200d..9498e9d466fb 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c -@@ -278,6 +278,14 @@ const struct drm_format_info *__drm_format_info(u32 format) +@@ -258,6 +258,14 @@ const struct drm_format_info *__drm_format_info(u32 format) .num_planes = 2, .char_per_block = { 5, 5, 0 }, .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true }, @@ -43,10 +43,10 @@ index 722c7ebe4e88..2daf8a304b53 100644 .num_planes = 3, .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index 5498d7a6556a..5b5db0381729 100644 +index f7156322aba5..a30bb7ef7632 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h -@@ -242,6 +242,8 @@ extern "C" { +@@ -279,6 +279,8 @@ extern "C" { * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian */ #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ @@ -76,10 +76,10 @@ Reviewed-by: Sandy Huang 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index c80f7d9fd13f..eb663e25ad9e 100644 +index f5b9028a16a3..9df4a271f3aa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -261,6 +261,18 @@ static bool has_rb_swapped(uint32_t format) +@@ -262,6 +262,18 @@ static bool has_rb_swapped(uint32_t format) } } @@ -98,7 +98,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { -@@ -276,10 +288,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) +@@ -277,10 +289,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) case DRM_FORMAT_BGR565: return VOP_FMT_RGB565; case DRM_FORMAT_NV12: @@ -112,7 +112,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 return VOP_FMT_YUV444SP; default: DRM_ERROR("unsupported format[%08x]\n", format); -@@ -922,7 +937,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -931,7 +946,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); @@ -126,7 +126,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 offset += (src->y1 >> 16) * fb->pitches[0]; dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; -@@ -948,6 +968,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -957,6 +977,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } VOP_WIN_SET(vop, win, format, format); @@ -134,7 +134,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); -@@ -964,7 +985,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -973,7 +994,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, uv_obj = fb->obj[1]; rk_uv_obj = to_rockchip_obj(uv_obj); @@ -160,7 +160,7 @@ index 857d97cdc67c..b7169010622a 100644 struct vop_reg act_info; struct vop_reg dsp_info; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 80053d91a301..2c55e1852c3d 100644 +index ca7cc82125cb..fff9c3387b9d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = { @@ -187,7 +187,7 @@ index 80053d91a301..2c55e1852c3d 100644 static const uint64_t format_modifiers_win_full[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID, -@@ -579,11 +596,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { +@@ -613,11 +630,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { static const struct vop_win_phy rk3288_win01_data = { .scl = &rk3288_win_full_scl, @@ -202,7 +202,7 @@ index 80053d91a301..2c55e1852c3d 100644 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), -@@ -713,11 +731,12 @@ static const struct vop_intr rk3368_vop_intr = { +@@ -747,11 +765,12 @@ static const struct vop_intr rk3368_vop_intr = { static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, @@ -217,7 +217,7 @@ index 80053d91a301..2c55e1852c3d 100644 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), -@@ -862,11 +881,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { +@@ -896,11 +915,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { static const struct vop_win_phy rk3399_win01_data = { .scl = &rk3288_win_full_scl, @@ -257,10 +257,10 @@ Signed-off-by: Qinglang Miao 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c -index a4a45daf93f2..9b4406191470 100644 +index 8ab3247dbc4a..8429c6706ec5 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c -@@ -98,7 +98,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) +@@ -100,7 +100,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) goto err_core_clk; } @@ -294,10 +294,10 @@ Signed-off-by: Qinglang Miao 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index eb663e25ad9e..c6c76e8ab66c 100644 +index 9df4a271f3aa..c3c0de25b8e6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -602,7 +602,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) +@@ -603,7 +603,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) struct vop *vop = to_vop(crtc); int ret, i; @@ -306,7 +306,7 @@ index eb663e25ad9e..c6c76e8ab66c 100644 if (ret < 0) { DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); return ret; -@@ -1933,7 +1933,7 @@ static int vop_initial(struct vop *vop) +@@ -1956,7 +1956,7 @@ static int vop_initial(struct vop *vop) return PTR_ERR(vop->dclk); } @@ -340,7 +340,7 @@ Signed-off-by: Qinglang Miao 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c -index 41edd0a421b2..4d463d50a63a 100644 +index 489d63c05c0d..aaf0b6bbcb85 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -145,7 +145,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds) @@ -362,3 +362,198 @@ index 41edd0a421b2..4d463d50a63a 100644 DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); return ret; +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Thomas Zimmermann +Date: Thu, 24 Jun 2021 11:55:02 +0200 +Subject: [PATCH] drm/rockchip: Implement mmap as GEM object function + +Moving the driver-specific mmap code into a GEM object function allows +for using DRM helpers for various mmap callbacks. + +The respective rockchip functions are being removed. The file_operations +structure fops is now being created by the helper macro +DEFINE_DRM_GEM_FOPS(). + +Signed-off-by: Thomas Zimmermann +Tested-by: Heiko Stuebner +--- + drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 13 +----- + drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 3 +- + drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 44 +++++-------------- + drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 7 --- + 4 files changed, 15 insertions(+), 52 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +index b730b8d5d949..2e3ab573a817 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +@@ -208,16 +208,7 @@ static void rockchip_drm_unbind(struct device *dev) + drm_dev_put(drm_dev); + } + +-static const struct file_operations rockchip_drm_driver_fops = { +- .owner = THIS_MODULE, +- .open = drm_open, +- .mmap = rockchip_gem_mmap, +- .poll = drm_poll, +- .read = drm_read, +- .unlocked_ioctl = drm_ioctl, +- .compat_ioctl = drm_compat_ioctl, +- .release = drm_release, +-}; ++DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops); + + static const struct drm_driver rockchip_drm_driver = { + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, +@@ -226,7 +217,7 @@ static const struct drm_driver rockchip_drm_driver = { + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, +- .gem_prime_mmap = rockchip_gem_mmap_buf, ++ .gem_prime_mmap = drm_gem_prime_mmap, + .fops = &rockchip_drm_driver_fops, + .name = DRIVER_NAME, + .desc = DRIVER_DESC, +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +index 2fdc455c4ad7..d8418dd39d0e 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + #include + + #include "rockchip_drm_drv.h" +@@ -24,7 +25,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info, + struct drm_fb_helper *helper = info->par; + struct rockchip_drm_private *private = to_drm_private(helper); + +- return rockchip_gem_mmap_buf(private->fbdev_bo, vma); ++ return drm_gem_prime_mmap(private->fbdev_bo, vma); + } + + static const struct fb_ops rockchip_drm_fbdev_ops = { +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +index 7971f57436dd..63eb73b624aa 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +@@ -240,12 +240,22 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, + int ret; + struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj); + ++ /* ++ * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the ++ * whole buffer from the start. ++ */ ++ vma->vm_pgoff = 0; ++ + /* + * We allocated a struct page table for rk_obj, so clear + * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). + */ ++ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_flags &= ~VM_PFNMAP; + ++ vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); ++ vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); ++ + if (rk_obj->pages) + ret = rockchip_drm_gem_object_mmap_iommu(obj, vma); + else +@@ -257,39 +267,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, + return ret; + } + +-int rockchip_gem_mmap_buf(struct drm_gem_object *obj, +- struct vm_area_struct *vma) +-{ +- int ret; +- +- ret = drm_gem_mmap_obj(obj, obj->size, vma); +- if (ret) +- return ret; +- +- return rockchip_drm_gem_object_mmap(obj, vma); +-} +- +-/* drm driver mmap file operations */ +-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma) +-{ +- struct drm_gem_object *obj; +- int ret; +- +- ret = drm_gem_mmap(filp, vma); +- if (ret) +- return ret; +- +- /* +- * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the +- * whole buffer from the start. +- */ +- vma->vm_pgoff = 0; +- +- obj = vma->vm_private_data; +- +- return rockchip_drm_gem_object_mmap(obj, vma); +-} +- + static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj) + { + drm_gem_object_release(&rk_obj->base); +@@ -301,6 +278,7 @@ static const struct drm_gem_object_funcs rockchip_gem_object_funcs = { + .get_sg_table = rockchip_gem_prime_get_sg_table, + .vmap = rockchip_gem_prime_vmap, + .vunmap = rockchip_gem_prime_vunmap, ++ .mmap = rockchip_drm_gem_object_mmap, + .vm_ops = &drm_gem_cma_vm_ops, + }; + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +index 5a70a56cd406..47c1861eece0 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +@@ -34,13 +34,6 @@ rockchip_gem_prime_import_sg_table(struct drm_device *dev, + int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map); + void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map); + +-/* drm driver mmap file operations */ +-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma); +- +-/* mmap a gem object to userspace. */ +-int rockchip_gem_mmap_buf(struct drm_gem_object *obj, +- struct vm_area_struct *vma); +- + struct rockchip_gem_object * + rockchip_gem_create_object(struct drm_device *drm, unsigned int size, + bool alloc_kmap); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sun, 27 Jun 2021 16:47:37 +0800 +Subject: [PATCH] drm/rockchip: Check iommu itself instead of it's parent for + device_is_available + +When iommu itself is disabled in dts, we should +fallback to non-iommu buffer, check iommu parent +is meanless here. + +Signed-off-by: Andy Yan +--- + drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +index 2e3ab573a817..8161540be6c8 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +@@ -367,7 +367,7 @@ static int rockchip_drm_platform_of_probe(struct device *dev) + } + + iommu = of_parse_phandle(port->parent, "iommus", 0); +- if (!iommu || !of_device_is_available(iommu->parent)) { ++ if (!iommu || !of_device_is_available(iommu)) { + DRM_DEV_DEBUG(dev, + "no iommu attached for %pOF, using non-iommu buffers\n", + port->parent); diff --git a/projects/Rockchip/patches/linux/default/linux-1001-drm-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch similarity index 95% rename from projects/Rockchip/patches/linux/default/linux-1001-drm-rockchip.patch rename to projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch index 5c159a9078..0614779709 100644 --- a/projects/Rockchip/patches/linux/default/linux-1001-drm-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch @@ -13,10 +13,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index c6c76e8ab66c..2f98a5e7dce1 100644 +index c3c0de25b8e6..395b7160a3c5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1554,7 +1554,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) +@@ -1578,7 +1578,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) { struct rockchip_crtc_state *rockchip_state; @@ -47,10 +47,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 2f98a5e7dce1..defa314a8f96 100644 +index 395b7160a3c5..3603bf81b58b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1167,6 +1167,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) +@@ -1181,6 +1181,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -110,7 +110,7 @@ index 2f98a5e7dce1..defa314a8f96 100644 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) -@@ -1537,6 +1590,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, +@@ -1561,6 +1614,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { @@ -133,10 +133,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index defa314a8f96..a9e6e8bdc848 100644 +index 3603bf81b58b..91ed741d09cd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1205,6 +1205,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1219,6 +1219,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (!vop_crtc_is_tmds(crtc)) return MODE_OK; @@ -183,10 +183,10 @@ index b7169010622a..0b1984585082 100644 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) #define VOP_FEATURE_INTERNAL_RGB BIT(1) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 2c55e1852c3d..cf87361108a0 100644 +index fff9c3387b9d..37e623bdf287 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -700,6 +700,7 @@ static const struct vop_intr rk3288_vop_intr = { +@@ -734,6 +734,7 @@ static const struct vop_intr rk3288_vop_intr = { static const struct vop_data rk3288_vop = { .version = VOP_VERSION(3, 1), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -194,7 +194,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3288_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -801,6 +802,7 @@ static const struct vop_misc rk3368_misc = { +@@ -835,6 +836,7 @@ static const struct vop_misc rk3368_misc = { static const struct vop_data rk3368_vop = { .version = VOP_VERSION(3, 2), @@ -202,7 +202,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3368_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -822,6 +824,7 @@ static const struct vop_intr rk3366_vop_intr = { +@@ -856,6 +858,7 @@ static const struct vop_intr rk3366_vop_intr = { static const struct vop_data rk3366_vop = { .version = VOP_VERSION(3, 4), @@ -210,7 +210,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -929,6 +932,7 @@ static const struct vop_afbc rk3399_vop_afbc = { +@@ -963,6 +966,7 @@ static const struct vop_afbc rk3399_vop_afbc = { static const struct vop_data rk3399_vop_big = { .version = VOP_VERSION(3, 5), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -218,7 +218,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -955,6 +959,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { +@@ -989,6 +993,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { static const struct vop_data rk3399_vop_lit = { .version = VOP_VERSION(3, 6), @@ -226,7 +226,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -975,6 +980,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { +@@ -1009,6 +1014,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { static const struct vop_data rk3228_vop = { .version = VOP_VERSION(3, 7), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -234,7 +234,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -1046,6 +1052,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { +@@ -1080,6 +1086,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { static const struct vop_data rk3328_vop = { .version = VOP_VERSION(3, 8), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -256,10 +256,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index a9e6e8bdc848..bf44282409ab 100644 +index 91ed741d09cd..5badaf5a87e7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1199,6 +1199,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1213,6 +1213,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct vop *vop = to_vop(crtc); @@ -267,7 +267,7 @@ index a9e6e8bdc848..bf44282409ab 100644 long rounded_rate; long lowest, highest; -@@ -1220,6 +1221,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1234,6 +1235,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (rounded_rate > highest) return MODE_CLOCK_HIGH; @@ -278,7 +278,7 @@ index a9e6e8bdc848..bf44282409ab 100644 return MODE_OK; } -@@ -1228,8 +1233,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1242,8 +1247,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { struct vop *vop = to_vop(crtc); @@ -340,7 +340,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 23de359a1dec..f78851e7ef16 100644 +index 830bdd5e9b7c..08c4ea2b6bf2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -181,7 +181,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { @@ -367,7 +367,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index f78851e7ef16..a308adb56d2f 100644 +index 08c4ea2b6bf2..546970b36dd2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -183,6 +183,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { @@ -397,7 +397,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a308adb56d2f..5b273f26f177 100644 +index 546970b36dd2..3bbd90e2e40b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -160,20 +160,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { @@ -455,7 +455,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 69 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 5b273f26f177..b5d2cdaa24fa 100644 +index 3bbd90e2e40b..2cdaeb76ab9e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -79,80 +79,88 @@ struct rockchip_hdmi { @@ -628,7 +628,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index b5d2cdaa24fa..5f7ab8e6bb72 100644 +index 2cdaeb76ab9e..279d900e3e51 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -221,19 +221,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -667,7 +667,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 5f7ab8e6bb72..0e7ca368314d 100644 +index 279d900e3e51..20c37b22b3eb 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -225,7 +225,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -693,7 +693,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 0e7ca368314d..6f7641fbe6cc 100644 +index 20c37b22b3eb..f8001dd8dca7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -306,6 +306,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, @@ -721,7 +721,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 6f7641fbe6cc..cc20a83fa9b8 100644 +index f8001dd8dca7..8b957af7c61a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -396,9 +396,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { @@ -756,7 +756,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cc20a83fa9b8..fd614c8a3486 100644 +index 8b957af7c61a..303c6e81ca4f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -516,8 +516,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, @@ -822,10 +822,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c -index 47d6482dda9d..a2b4d5487514 100644 +index a24a35553e13..7343d2d7676b 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c -@@ -408,7 +408,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { +@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), @@ -846,10 +846,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index cf87361108a0..05ade8ea962f 100644 +index 37e623bdf287..28df0bc79812 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -697,7 +697,7 @@ static const struct vop_intr rk3288_vop_intr = { +@@ -731,7 +731,7 @@ static const struct vop_intr rk3288_vop_intr = { .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), }; @@ -858,7 +858,7 @@ index cf87361108a0..05ade8ea962f 100644 .version = VOP_VERSION(3, 1), .feature = VOP_FEATURE_OUTPUT_RGB10, .max_output = { 3840, 2160 }, -@@ -710,6 +710,19 @@ static const struct vop_data rk3288_vop = { +@@ -744,6 +744,19 @@ static const struct vop_data rk3288_vop = { .lut_size = 1024, }; @@ -878,7 +878,7 @@ index cf87361108a0..05ade8ea962f 100644 static const int rk3368_vop_intrs[] = { FS_INTR, 0, 0, -@@ -1075,8 +1088,10 @@ static const struct of_device_id vop_driver_dt_match[] = { +@@ -1109,8 +1122,10 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3066_vop }, { .compatible = "rockchip,rk3188-vop", .data = &rk3188_vop }, @@ -903,10 +903,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 01ea1f170f77..3575dea1ee29 100644 +index 9c5a7791a1ab..b64b8fbe388d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1037,7 +1037,7 @@ rga: rga@ff920000 { +@@ -1018,7 +1018,7 @@ rga: rga@ff920000 { }; vopb: vop@ff930000 { @@ -915,7 +915,7 @@ index 01ea1f170f77..3575dea1ee29 100644 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; -@@ -1087,7 +1087,7 @@ vopb_mmu: iommu@ff930300 { +@@ -1068,7 +1068,7 @@ vopb_mmu: iommu@ff930300 { }; vopl: vop@ff940000 { @@ -939,7 +939,7 @@ Signed-off-by: Jonas Karlman 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 0c79a9ba48bb..50199329ad6f 100644 +index e7c7c9b9c646..ee1968ecaa8f 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -137,7 +137,8 @@ struct dw_hdmi_phy_data { @@ -989,7 +989,7 @@ index 7b8ec8310699..539d86131fd4 100644 const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params; diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index ea34ca146b82..4f61ede6486d 100644 +index 6a5716655619..182c8a8781df 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -152,7 +152,8 @@ struct dw_hdmi_plat_data { @@ -999,9 +999,9 @@ index ea34ca146b82..4f61ede6486d 100644 - unsigned long mpixelclock); + unsigned long mpixelclock, + unsigned long mtmdsclock); - }; - struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, + unsigned int disable_cec : 1; + }; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -1016,7 +1016,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 50199329ad6f..2581789178c7 100644 +index ee1968ecaa8f..8b3ce725b211 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1448,6 +1448,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, @@ -1075,7 +1075,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 2581789178c7..6d319b95b992 100644 +index 8b3ce725b211..473db9629a66 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1450,7 +1450,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, @@ -1090,7 +1090,7 @@ index 2581789178c7..6d319b95b992 100644 /* PLL/MPLL Cfg - always match on final entry */ for (; mpll_config->mpixelclock != ~0UL; mpll_config++) diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 4f61ede6486d..0ebe01835d2a 100644 +index 182c8a8781df..5387d2cd1560 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -149,6 +149,7 @@ struct dw_hdmi_plat_data { @@ -1113,7 +1113,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index fd614c8a3486..c22add144cf4 100644 +index 303c6e81ca4f..73fad678b6ee 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -221,8 +221,15 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -1154,7 +1154,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index c22add144cf4..1e558af2c9b2 100644 +index 73fad678b6ee..6471d601b98b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -165,6 +165,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { @@ -1225,7 +1225,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 1e558af2c9b2..6dbd0e422ca1 100644 +index 6471d601b98b..9af45fdfbd19 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -205,6 +205,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { @@ -1302,7 +1302,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 78 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 6dbd0e422ca1..510ae5d5f133 100644 +index 9af45fdfbd19..134c2db8d0fe 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -68,6 +68,7 @@ struct rockchip_hdmi { @@ -1501,10 +1501,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index bf44282409ab..25b89ddb446d 100644 +index 5badaf5a87e7..af9e40d7f49b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1854,19 +1854,10 @@ static int vop_create_crtc(struct vop *vop) +@@ -1877,19 +1877,10 @@ static int vop_create_crtc(struct vop *vop) int ret; int i; @@ -1524,7 +1524,7 @@ index bf44282409ab..25b89ddb446d 100644 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 0, &vop_plane_funcs, win_data->phy->data_formats, -@@ -1899,32 +1890,13 @@ static int vop_create_crtc(struct vop *vop) +@@ -1922,32 +1913,13 @@ static int vop_create_crtc(struct vop *vop) drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); } @@ -1587,10 +1587,10 @@ index 3aa37e177667..a2b59faa9184 100644 dev->mode_config.helper_private = &rockchip_mode_config_helpers; } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 25b89ddb446d..74d7e474bf89 100644 +index af9e40d7f49b..ab3ae8d03231 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1831,7 +1831,7 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1854,7 +1854,7 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1599,7 +1599,7 @@ index 25b89ddb446d..74d7e474bf89 100644 const struct vop_win_data *win_data) { unsigned int flags = 0; -@@ -1841,6 +1841,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, +@@ -1864,6 +1864,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, if (flags) drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | flags); @@ -1608,7 +1608,7 @@ index 25b89ddb446d..74d7e474bf89 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1872,7 +1874,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1895,7 +1897,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1629,10 +1629,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 74d7e474bf89..d8e0c5a4df01 100644 +index ab3ae8d03231..8c6d1881787c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1831,8 +1831,23 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1854,8 +1854,23 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1657,7 +1657,7 @@ index 74d7e474bf89..d8e0c5a4df01 100644 { unsigned int flags = 0; -@@ -1843,6 +1858,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, +@@ -1866,6 +1881,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, DRM_MODE_ROTATE_0 | flags); drm_plane_create_zpos_immutable_property(plane, zpos); @@ -1677,7 +1677,7 @@ index 74d7e474bf89..d8e0c5a4df01 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1874,7 +1902,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1897,7 +1925,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1703,10 +1703,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 3575dea1ee29..03e86d012edd 100644 +index b64b8fbe388d..38da07f42cd5 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1046,6 +1046,8 @@ vopb: vop@ff930000 { +@@ -1027,6 +1027,8 @@ vopb: vop@ff930000 { resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; reset-names = "axi", "ahb", "dclk"; iommus = <&vopb_mmu>; @@ -1716,10 +1716,10 @@ index 3575dea1ee29..03e86d012edd 100644 vopb_out: port { diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 93c794695c46..db6c8bbb35f4 100644 +index baa5aebd3277..20a3cdbbe909 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -231,7 +231,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -232,7 +232,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1728,7 +1728,7 @@ index 93c794695c46..db6c8bbb35f4 100644 }; static struct clk_div_table div_hclk_cpu_t[] = { -@@ -441,7 +441,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { +@@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 4, GFLAGS), @@ -1752,7 +1752,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index db6c8bbb35f4..426309f5dd44 100644 +index 20a3cdbbe909..47a2527fd238 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -121,6 +121,27 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { @@ -1783,7 +1783,7 @@ index db6c8bbb35f4..426309f5dd44 100644 #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf -@@ -231,7 +252,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -232,7 +253,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1806,7 +1806,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 16 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 426309f5dd44..b3247a3a7290 100644 +index 47a2527fd238..233890555616 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -127,18 +127,34 @@ static struct rockchip_pll_rate_table rk3288_npll_rates[] = { @@ -1857,7 +1857,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 7df2f1e00347..d39d9ea39aca 100644 +index 62a4f2543960..980223c32aba 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -105,6 +105,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { @@ -1926,7 +1926,7 @@ index 7df2f1e00347..d39d9ea39aca 100644 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = -@@ -1160,7 +1180,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { +@@ -1162,7 +1182,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(28), 0, GFLAGS), @@ -1947,10 +1947,10 @@ Subject: [PATCH] HACK: dts: rockchip: do not use vopl for hdmi 2 files changed, 18 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 03e86d012edd..746acfac1e92 100644 +index 38da07f42cd5..831484253e27 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1104,11 +1104,6 @@ vopl_out: port { +@@ -1085,11 +1085,6 @@ vopl_out: port { #address-cells = <1>; #size-cells = <0>; @@ -1962,7 +1962,7 @@ index 03e86d012edd..746acfac1e92 100644 vopl_out_edp: endpoint@1 { reg = <1>; remote-endpoint = <&edp_in_vopl>; -@@ -1249,10 +1244,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1230,10 +1225,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -1974,10 +1974,10 @@ index 03e86d012edd..746acfac1e92 100644 }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 2551b238b97c..ea1ef6c7455a 100644 +index 44def886b391..52a748053a97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1639,11 +1639,6 @@ vopl_out_edp: endpoint@1 { +@@ -1642,11 +1642,6 @@ vopl_out_edp: endpoint@1 { remote-endpoint = <&edp_in_vopl>; }; @@ -1989,7 +1989,7 @@ index 2551b238b97c..ea1ef6c7455a 100644 vopl_out_mipi1: endpoint@3 { reg = <3>; remote-endpoint = <&mipi1_in_vopl>; -@@ -1815,10 +1810,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1840,10 +1835,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -2012,7 +2012,7 @@ Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to 1 file changed, 76 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 6d319b95b992..c2425d7fc465 100644 +index 473db9629a66..53fb6cf26137 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1859,6 +1859,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, @@ -2070,7 +2070,7 @@ index 6d319b95b992..c2425d7fc465 100644 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); /* Set up HDMI_FC_INVIDCONF */ -@@ -2544,8 +2541,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2528,8 +2525,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) * - MEDIA_BUS_FMT_RGB888_1X24, */ @@ -2094,7 +2094,7 @@ index 6d319b95b992..c2425d7fc465 100644 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, -@@ -2557,8 +2567,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2541,8 +2551,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_display_info *info = &conn->display_info; struct drm_display_mode *mode = &crtc_state->mode; u8 max_bpc = conn_state->max_requested_bpc; @@ -2103,7 +2103,7 @@ index 6d319b95b992..c2425d7fc465 100644 u32 *output_fmts; unsigned int i = 0; -@@ -2581,29 +2589,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2565,29 +2573,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, * If the current mode enforces 4:2:0, force the output but format * to 4:2:0 and do not add the YUV422/444/RGB formats */ @@ -2145,7 +2145,7 @@ index 6d319b95b992..c2425d7fc465 100644 } /* -@@ -2612,40 +2624,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2596,40 +2608,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, */ if (max_bpc >= 16 && info->bpc == 16) { @@ -2208,7 +2208,7 @@ index 6d319b95b992..c2425d7fc465 100644 *num_output_fmts = i; -@@ -2825,11 +2848,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, +@@ -2809,11 +2832,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, struct dw_hdmi *hdmi = bridge->driver_private; const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; enum drm_mode_status mode_status = MODE_OK; @@ -2241,7 +2241,7 @@ Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 510ae5d5f133..43ad0278fad1 100644 +index 134c2db8d0fe..cba63dd5e8c8 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -77,6 +77,7 @@ struct rockchip_hdmi { @@ -2359,7 +2359,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index c2425d7fc465..f86b8fa40ab6 100644 +index 53fb6cf26137..df8ff6af9157 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1646,6 +1646,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, @@ -2379,25 +2379,25 @@ index c2425d7fc465..f86b8fa40ab6 100644 /* * The Designware IP uses a different byte format from standard * AVI info frames, though generally the bits are in the correct -@@ -2431,7 +2434,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, +@@ -2416,7 +2419,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, if (!crtc) return 0; -- if (!hdr_metadata_equal(old_state, new_state)) { -+ if (!hdr_metadata_equal(old_state, new_state) || +- if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { ++ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) || + old_state->content_type != new_state->content_type) { crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); -@@ -2499,6 +2503,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2484,6 +2488,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) drm_connector_attach_max_bpc_property(connector, 8, 16); + drm_connector_attach_content_type_property(connector); + if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) - drm_object_attach_property(&connector->base, - connector->dev->mode_config.hdr_output_metadata_property, 0); + drm_connector_attach_hdr_output_metadata_property(connector); + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -2412,7 +2412,7 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv444 support 4 files changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 43ad0278fad1..c8eaeb484672 100644 +index cba63dd5e8c8..6429892ac4df 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -62,6 +62,7 @@ struct rockchip_hdmi_chip_data { @@ -2490,10 +2490,10 @@ index 43ad0278fad1..c8eaeb484672 100644 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index d8e0c5a4df01..9fde1c27072b 100644 +index 8c6d1881787c..abf3442baac0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -325,6 +325,17 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -326,6 +326,17 @@ static int vop_convert_afbc_format(uint32_t format) return -EINVAL; } @@ -2511,7 +2511,7 @@ index d8e0c5a4df01..9fde1c27072b 100644 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t dst, bool is_horizontal, int vsu_mode, int *vskiplines) -@@ -1375,6 +1386,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1395,6 +1406,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; int dither_bpc = s->output_bpc ? s->output_bpc : 10; @@ -2519,7 +2519,7 @@ index d8e0c5a4df01..9fde1c27072b 100644 int ret; if (old_state && old_state->self_refresh_active) { -@@ -1448,6 +1460,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1468,6 +1480,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2528,7 +2528,7 @@ index d8e0c5a4df01..9fde1c27072b 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else -@@ -1463,6 +1477,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1483,6 +1497,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2572,10 +2572,10 @@ index 0b1984585082..72dd670bf2a7 100644 struct vop_intr { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 05ade8ea962f..f276ef4b3f64 100644 +index 28df0bc79812..e64cedf7c7a1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -662,6 +662,11 @@ static const struct vop_common rk3288_common = { +@@ -696,6 +696,11 @@ static const struct vop_common rk3288_common = { .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), @@ -2587,7 +2587,7 @@ index 05ade8ea962f..f276ef4b3f64 100644 }; /* -@@ -1029,6 +1034,10 @@ static const struct vop_output rk3328_output = { +@@ -1063,6 +1068,10 @@ static const struct vop_output rk3328_output = { static const struct vop_misc rk3328_misc = { .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), @@ -2598,7 +2598,7 @@ index 05ade8ea962f..f276ef4b3f64 100644 }; static const struct vop_common rk3328_common = { -@@ -1041,6 +1050,11 @@ static const struct vop_common rk3328_common = { +@@ -1075,6 +1084,11 @@ static const struct vop_common rk3328_common = { .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), @@ -2624,7 +2624,7 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv420 support 4 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index c8eaeb484672..9fe690570e3d 100644 +index 6429892ac4df..257770ea2dc7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -386,9 +386,21 @@ static bool is_yuv444(u32 format) @@ -2688,10 +2688,10 @@ index c8eaeb484672..9fe690570e3d 100644 static struct rockchip_hdmi_chip_data rk3399_chip_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 9fde1c27072b..4d855724e1dd 100644 +index abf3442baac0..5238bcbc7bae 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -326,6 +326,19 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -327,6 +327,19 @@ static int vop_convert_afbc_format(uint32_t format) } static bool is_yuv_output(uint32_t bus_format) @@ -2711,7 +2711,7 @@ index 9fde1c27072b..4d855724e1dd 100644 { switch (bus_format) { case MEDIA_BUS_FMT_YUV8_1X24: -@@ -1460,7 +1473,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1480,7 +1493,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2720,7 +2720,7 @@ index 9fde1c27072b..4d855724e1dd 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); -@@ -1477,6 +1490,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1497,6 +1510,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2760,10 +2760,10 @@ index 72dd670bf2a7..a997578e174a 100644 /* output flags */ #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index f276ef4b3f64..8c99cc2a7eda 100644 +index e64cedf7c7a1..a13059052124 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -664,6 +664,7 @@ static const struct vop_common rk3288_common = { +@@ -698,6 +698,7 @@ static const struct vop_common rk3288_common = { .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), @@ -2771,7 +2771,7 @@ index f276ef4b3f64..8c99cc2a7eda 100644 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), -@@ -1052,6 +1053,7 @@ static const struct vop_common rk3328_common = { +@@ -1086,6 +1087,7 @@ static const struct vop_common rk3328_common = { .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), @@ -2791,7 +2791,7 @@ Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 9fe690570e3d..bccdbb3e0a54 100644 +index 257770ea2dc7..78b77b31436a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -595,6 +595,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { @@ -2826,7 +2826,7 @@ Signed-off-by: Alex Bee 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index bccdbb3e0a54..a612bf3da9ee 100644 +index 78b77b31436a..976dd3c9c26f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -305,16 +305,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -2874,10 +2874,10 @@ Subject: [PATCH] !fixup drm/rockchip: rk3368's vop does not support 10-bit 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 8c99cc2a7eda..9ca9fff0d359 100644 +index a13059052124..11a80117f5bc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -751,8 +751,8 @@ static const struct vop_intr rk3368_vop_intr = { +@@ -785,8 +785,8 @@ static const struct vop_intr rk3368_vop_intr = { static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, @@ -2900,10 +2900,10 @@ Signed-off-by: Alex Bee 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 9ca9fff0d359..e34482c3d2be 100644 +index 11a80117f5bc..43541a042a81 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -1069,12 +1069,36 @@ static const struct vop_intr rk3328_vop_intr = { +@@ -1103,12 +1103,36 @@ static const struct vop_intr rk3328_vop_intr = { .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), }; @@ -2954,10 +2954,10 @@ Subject: [PATCH] rockchip: vop: force skip lines if image too big 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 4d855724e1dd..5622ffd1b587 100644 +index 5238bcbc7bae..20e45a23edf4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -932,6 +932,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -941,6 +941,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, int format; int is_yuv = fb->format->is_yuv; int i; @@ -2965,7 +2965,7 @@ index 4d855724e1dd..5622ffd1b587 100644 /* * can't update plane when vop is disabled. -@@ -950,8 +951,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -959,8 +960,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, obj = fb->obj[0]; rk_obj = to_rockchip_obj(obj); @@ -2981,7 +2981,7 @@ index 4d855724e1dd..5622ffd1b587 100644 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); dsp_info = (drm_rect_height(dest) - 1) << 16; -@@ -993,7 +1000,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1002,7 +1009,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); @@ -2990,7 +2990,7 @@ index 4d855724e1dd..5622ffd1b587 100644 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); VOP_WIN_SET(vop, win, y_mir_en, -@@ -1017,7 +1024,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1026,7 +1033,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, offset += (src->y1 >> 16) * fb->pitches[1] / vsub; dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; @@ -3014,10 +3014,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index d327fd300116..31c48c38c955 100644 +index cfc57be009a6..9c10b6e3b9bc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -805,8 +805,8 @@ cru: clock-controller@ff440000 { +@@ -793,8 +793,8 @@ cru: clock-controller@ff440000 { <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, @@ -3046,7 +3046,7 @@ this. 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index b3247a3a7290..f5617529dbb5 100644 +index 233890555616..676e7c3c6f2b 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -122,7 +122,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { @@ -3085,7 +3085,7 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index f86b8fa40ab6..3340aef73d8d 100644 +index df8ff6af9157..5642a8c9bed5 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -81,15 +81,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { @@ -3131,7 +3131,7 @@ Signed-off-by: Alex Bee 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index d39d9ea39aca..16b0bf173299 100644 +index 980223c32aba..09c6f8020212 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -107,20 +107,34 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { @@ -3213,7 +3213,7 @@ Signed-off-by: Alex Bee 1 file changed, 173 insertions(+), 25 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 3719309ad0d0..00025dcd3bb9 100644 +index 2f01259823ea..1889e78e18ea 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -292,31 +292,179 @@ struct inno_hdmi_phy_drv_data { @@ -3445,7 +3445,7 @@ Signed-off-by: Algea Cao 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 3340aef73d8d..d798846579f5 100644 +index 5642a8c9bed5..84cc52858ffb 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1060,7 +1060,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) @@ -3457,13 +3457,12 @@ index 3340aef73d8d..d798846579f5 100644 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { case 8: - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 1 Jun 2021 19:24:37 +0200 -Subject: [PATCH] drm/rockchip: allow 4096px with modes +Subject: [PATCH] drm/rockchip: allow 4096px width modes -There is no reason to limit to modes up to 3840. +There is not reason to limit vop output to 3840px width modes. Also drop the limitation from dw_hdmi_rockchip_mode_valid, since the max dimenstions of the actual vop version is validated in vop_crtc_mode_valid anyways. @@ -3475,7 +3474,7 @@ Signed-off-by: Alex Bee 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a612bf3da9ee..e4cfa6adbd87 100644 +index 8d1d2b8d038b..07e1327acf5e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -329,7 +329,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -3488,10 +3487,10 @@ index a612bf3da9ee..e4cfa6adbd87 100644 static void diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 5622ffd1b587..a0d27a9a9675 100644 +index 20a73cb3005e..b1473459a579 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -401,8 +401,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, +@@ -402,8 +402,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, if (info->is_yuv) is_yuv = true; @@ -3502,3 +3501,5 @@ index 5622ffd1b587..a0d27a9a9675 100644 return; } + + diff --git a/projects/Rockchip/patches/linux/default/linux-1002-v4l2-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch similarity index 86% rename from projects/Rockchip/patches/linux/default/linux-1002-v4l2-rockchip.patch rename to projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch index b6e8d01e2c..c0f90d8482 100644 --- a/projects/Rockchip/patches/linux/default/linux-1002-v4l2-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch @@ -10,10 +10,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 9492822c12ae..b49541f8ecf5 100644 +index d068383aeea8..5c03fdbd45ec 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1024,7 +1024,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -986,7 +986,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) state = (status & RKVDEC_RDY_STA) ? VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; @@ -23,7 +23,7 @@ index 9492822c12ae..b49541f8ecf5 100644 if (cancel_delayed_work(&rkvdec->watchdog_work)) { struct rkvdec_ctx *ctx; -@@ -1045,7 +1046,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1007,7 +1008,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); @@ -46,10 +46,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index b49541f8ecf5..51e257a0233d 100644 +index 5c03fdbd45ec..ad5e02bbd8d0 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1145,9 +1145,9 @@ static int rkvdec_remove(struct platform_device *pdev) +@@ -1105,9 +1105,9 @@ static int rkvdec_remove(struct platform_device *pdev) { struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev); @@ -77,7 +77,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index c115cd362a7f..d9a2fd9386e2 100644 +index c9a551dbd9bc..6ce11b736363 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -734,6 +734,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -131,7 +131,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 64 insertions(+), 15 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index d9a2fd9386e2..d4f27ef7addd 100644 +index 6ce11b736363..9c3f08c94800 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -737,7 +737,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -247,58 +247,27 @@ This still need code cleanup and formatting Signed-off-by: Jonas Karlman --- - .../staging/media/hantro/hantro_g1_h264_dec.c | 17 +--- - drivers/staging/media/hantro/hantro_h264.c | 81 ++++++++++++++++--- - drivers/staging/media/hantro/hantro_hw.h | 2 + - 3 files changed, 74 insertions(+), 26 deletions(-) + drivers/staging/media/hantro/hantro_h264.c | 91 ++++++++++++++++------ + 1 file changed, 69 insertions(+), 22 deletions(-) -diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -index 845bef73d218..869ee261a5db 100644 ---- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c -+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -@@ -130,25 +130,12 @@ static void set_ref(struct hantro_ctx *ctx) - struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; - const u8 *b0_reflist, *b1_reflist, *p_reflist; - struct hantro_dev *vpu = ctx->dev; -- u32 dpb_longterm = 0; -- u32 dpb_valid = 0; - int reg_num; - u32 reg; - int i; - -- /* -- * Set up bit maps of valid and long term DPBs. -- * NOTE: The bits are reversed, i.e. MSb is DPB 0. -- */ -- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) -- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -- -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -- } -- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF); -- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF); -+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); -+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); - - /* - * Set up reference frame picture numbers. diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index b1bdc00ac262..bc2af450a94c 100644 +index 0b4d2491be3b..7b56a68c176c 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -227,17 +227,67 @@ static void prepare_table(struct hantro_ctx *ctx) +@@ -227,30 +227,67 @@ static void prepare_table(struct hantro_ctx *ctx) { const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; + const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; -+ u32 dpb_longterm = 0; -+ u32 dpb_valid = 0; + u32 dpb_longterm = 0; + u32 dpb_valid = 0; int i; +- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { +- tbl->poc[i * 2] = dpb[i].top_field_order_cnt; +- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; + /* + * Set up bit maps of valid and long term DPBs. + * NOTE: The bits are reversed, i.e. MSb is DPB 0. @@ -315,7 +284,15 @@ index b1bdc00ac262..bc2af450a94c 100644 + if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) + dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i); + } -+ + +- /* +- * Set up bit maps of valid and long term DPBs. +- * NOTE: The bits are reversed, i.e. MSb is DPB 0. +- */ +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) +- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); + ctx->h264_dec.dpb_valid = dpb_valid; + ctx->h264_dec.dpb_longterm = dpb_longterm; + } else { @@ -329,11 +306,13 @@ index b1bdc00ac262..bc2af450a94c 100644 + + ctx->h264_dec.dpb_valid = dpb_valid << 16; + ctx->h264_dec.dpb_longterm = dpb_longterm << 16; -+ } -+ - for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -- tbl->poc[i * 2] = dpb[i].top_field_order_cnt; -- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; + } +- ctx->h264_dec.dpb_valid = dpb_valid << 16; +- ctx->h264_dec.dpb_longterm = dpb_longterm << 16; + +- tbl->poc[32] = dec_param->top_field_order_cnt; +- tbl->poc[33] = dec_param->bottom_field_order_cnt; ++ for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { + tbl->poc[i * 2] = dpb[i].top_field_order_cnt; + tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; @@ -341,10 +320,8 @@ index b1bdc00ac262..bc2af450a94c 100644 + tbl->poc[i * 2] = 0; + tbl->poc[i * 2 + 1] = 0; + } - } - -- tbl->poc[32] = dec_param->top_field_order_cnt; -- tbl->poc[33] = dec_param->bottom_field_order_cnt; ++ } ++ + if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || !(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { + if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) + tbl->poc[32] = (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ? @@ -356,11 +333,11 @@ index b1bdc00ac262..bc2af450a94c 100644 + } else { + tbl->poc[32] = dec_param->top_field_order_cnt; + tbl->poc[33] = dec_param->bottom_field_order_cnt; -+ } ++ }; assemble_scaling_list(ctx); } -@@ -245,8 +295,7 @@ static void prepare_table(struct hantro_ctx *ctx) +@@ -258,8 +295,7 @@ static void prepare_table(struct hantro_ctx *ctx) static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, const struct v4l2_h264_dpb_entry *b) { @@ -370,7 +347,7 @@ index b1bdc00ac262..bc2af450a94c 100644 } static void update_dpb(struct hantro_ctx *ctx) -@@ -260,13 +309,13 @@ static void update_dpb(struct hantro_ctx *ctx) +@@ -273,13 +309,13 @@ static void update_dpb(struct hantro_ctx *ctx) /* Disable all entries by default. */ for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) @@ -386,7 +363,7 @@ index b1bdc00ac262..bc2af450a94c 100644 continue; /* -@@ -277,8 +326,7 @@ static void update_dpb(struct hantro_ctx *ctx) +@@ -290,8 +326,7 @@ static void update_dpb(struct hantro_ctx *ctx) struct v4l2_h264_dpb_entry *cdpb; cdpb = &ctx->h264_dec.dpb[j]; @@ -396,7 +373,7 @@ index b1bdc00ac262..bc2af450a94c 100644 continue; *cdpb = *ndpb; -@@ -314,7 +362,10 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, +@@ -327,7 +362,10 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, unsigned int dpb_idx) { struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; @@ -407,7 +384,7 @@ index b1bdc00ac262..bc2af450a94c 100644 if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts); -@@ -332,7 +383,15 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, +@@ -345,7 +383,16 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, dma_addr = hantro_get_dec_buf_addr(ctx, buf); } @@ -421,22 +398,10 @@ index b1bdc00ac262..bc2af450a94c 100644 + 0x1 : 0; + + return dma_addr | flags; ++ } - int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 219283a06f52..7e35140a4f22 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -90,6 +90,8 @@ struct hantro_h264_dec_hw_ctx { - struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; - struct hantro_h264_dec_reflists reflists; - struct hantro_h264_dec_ctrls ctrls; -+ u32 dpb_longterm; -+ u32 dpb_valid; - }; - - /** + u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -449,7 +414,7 @@ Signed-off-by: Alex Bee 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index bc2af450a94c..7bdefcc2fc77 100644 +index 7b56a68c176c..befa69d5c855 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -241,10 +241,10 @@ static void prepare_table(struct hantro_ctx *ctx) @@ -477,7 +442,7 @@ Signed-off-by: Alex Bee 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index d4f27ef7addd..627cd4efabef 100644 +index 9c3f08c94800..7238117b6cf4 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -783,10 +783,10 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -512,32 +477,6 @@ index d4f27ef7addd..627cd4efabef 100644 set_ps_field(hw_rps, DPB_INFO(i, j), idx | (1 << 4)); -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 31 May 2020 18:22:01 +0200 -Subject: [PATCH] media: hantro: rk3288: increase max ACLK - -as per vendor source - -Signed-off-by: Alex Bee ---- - drivers/staging/media/hantro/rk3288_vpu_hw.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/rk3288_vpu_hw.c b/drivers/staging/media/hantro/rk3288_vpu_hw.c -index 7b299ee3e93d..23f793e73941 100644 ---- a/drivers/staging/media/hantro/rk3288_vpu_hw.c -+++ b/drivers/staging/media/hantro/rk3288_vpu_hw.c -@@ -13,7 +13,7 @@ - #include "hantro_g1_regs.h" - #include "hantro_h1_regs.h" - --#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) -+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) - - /* - * Supported formats. - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Sun, 6 Jan 2019 01:48:37 +0800 @@ -560,10 +499,10 @@ Signed-off-by: Randy Li create mode 100644 include/soc/rockchip/pm_domains.h diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c -index 54eb6cfc5d5b..727af107e6d3 100644 +index 0868b7d406fb..fddb4022c376 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c -@@ -196,6 +196,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, +@@ -204,6 +204,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, return 0; } @@ -652,10 +591,10 @@ Subject: [PATCH] WIP: media: rkvdec: implement reset controls 4 files changed, 87 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 8d35c327018b..dfafdb671798 100644 +index 089f11d21b25..3f4772c8d095 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -43,6 +43,18 @@ properties: +@@ -51,6 +51,18 @@ properties: iommus: maxItems: 1 @@ -674,7 +613,7 @@ index 8d35c327018b..dfafdb671798 100644 required: - compatible - reg -@@ -50,6 +62,8 @@ required: +@@ -58,6 +70,8 @@ required: - clocks - clock-names - power-domains @@ -683,7 +622,7 @@ index 8d35c327018b..dfafdb671798 100644 additionalProperties: false -@@ -68,6 +82,11 @@ examples: +@@ -76,6 +90,11 @@ examples: clock-names = "axi", "ahb", "cabac", "core"; power-domains = <&power RK3399_PD_VDU>; iommus = <&vdec_mmu>; @@ -712,7 +651,7 @@ index 15b9bee92016..3acc914888f6 100644 #define RKVDEC_REG_SYSCTRL 0x008 #define RKVDEC_IN_ENDIAN BIT(0) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 51e257a0233d..c05ba31ed656 100644 +index ad5e02bbd8d0..6abce36eee7f 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -10,12 +10,15 @@ @@ -731,7 +670,7 @@ index 51e257a0233d..c05ba31ed656 100644 #include #include #include -@@ -725,6 +728,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, +@@ -687,6 +690,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, pm_runtime_mark_last_busy(rkvdec->dev); pm_runtime_put_autosuspend(rkvdec->dev); @@ -743,7 +682,7 @@ index 51e257a0233d..c05ba31ed656 100644 rkvdec_job_finish_no_pm(ctx, result); } -@@ -762,6 +770,33 @@ static void rkvdec_device_run(void *priv) +@@ -724,6 +732,33 @@ static void rkvdec_device_run(void *priv) if (WARN_ON(!desc)) return; @@ -775,9 +714,9 @@ index 51e257a0233d..c05ba31ed656 100644 + pm_runtime_suspend(rkvdec->dev); + } - ret = pm_runtime_get_sync(rkvdec->dev); + ret = pm_runtime_resume_and_get(rkvdec->dev); if (ret < 0) { -@@ -1029,6 +1064,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -991,6 +1026,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) if (cancel_delayed_work(&rkvdec->watchdog_work)) { struct rkvdec_ctx *ctx; @@ -789,7 +728,7 @@ index 51e257a0233d..c05ba31ed656 100644 ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); rkvdec_job_finish(ctx, state); } -@@ -1046,6 +1086,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1008,6 +1048,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); @@ -797,7 +736,7 @@ index 51e257a0233d..c05ba31ed656 100644 writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); -@@ -1125,6 +1166,18 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1085,6 +1126,18 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; } @@ -817,7 +756,7 @@ index 51e257a0233d..c05ba31ed656 100644 pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index e95c52e3168a..c14cd2571bfc 100644 +index 7b6f44ee8a1a..fa24bcb6ff42 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -11,10 +11,11 @@ @@ -846,7 +785,7 @@ index e95c52e3168a..c14cd2571bfc 100644 struct rkvdec_ctx; struct rkvdec_ctrl_desc { -@@ -91,6 +98,8 @@ struct rkvdec_dev { +@@ -90,6 +97,8 @@ struct rkvdec_dev { void __iomem *regs; struct mutex vdev_lock; /* serializes ioctls */ struct delayed_work watchdog_work; @@ -866,11 +805,11 @@ Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index ea1ef6c7455a..92e3f6da0297 100644 +index 52a748053a97..2c7b263a82cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1022,7 +1022,10 @@ pd_vcodec@RK3399_PD_VCODEC { - pd_vdu@RK3399_PD_VDU { +@@ -993,7 +993,10 @@ power-domain@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VDU { reg = ; clocks = <&cru ACLK_VDU>, - <&cru HCLK_VDU>; @@ -880,8 +819,8 @@ index ea1ef6c7455a..92e3f6da0297 100644 + pm_qos = <&qos_video_m1_r>, <&qos_video_m1_w>; - }; -@@ -1283,6 +1286,11 @@ vdec: video-codec@ff660000 { + #power-domain-cells = <0>; +@@ -1266,6 +1269,11 @@ vdec: video-codec@ff660000 { clock-names = "axi", "ahb", "cabac", "core"; iommus = <&vdec_mmu>; power-domains = <&power RK3399_PD_VDU>; @@ -905,10 +844,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 92e3f6da0297..03c6737ca0ea 100644 +index 2c7b263a82cd..ec3561d147d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1279,7 +1279,7 @@ vpu_mmu: iommu@ff650800 { +@@ -1262,7 +1262,7 @@ vpu_mmu: iommu@ff650800 { vdec: video-codec@ff660000 { compatible = "rockchip,rk3399-vdec"; @@ -925,42 +864,40 @@ Subject: [PATCH] arm64: dts: rockchip: add rkvdec node for RK3328 Signed-off-by: Alex Bee --- - .../bindings/media/rockchip,vdec.yaml | 5 ++++ - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 26 ++++++++++++++++++- - 2 files changed, 30 insertions(+), 1 deletion(-) + .../bindings/media/rockchip,vdec.yaml | 3 +++ + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++++++++++- + 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index dfafdb671798..360b750e5514 100644 +index 3f4772c8d095..21a78372dae6 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -16,6 +16,11 @@ description: |- - properties: - compatible: - const: rockchip,rk3399-vdec -+ - items: -+ - enum: -+ - rockchip,rk3328-vdec -+ - const: rockchip,rk3399-vdec -+ +@@ -20,6 +20,9 @@ properties: + - items: + - const: rockchip,rk3228-vdec + - const: rockchip,rk3399-vdec ++ - items: ++ - const: rockchip,rk3328-vdec ++ - const: rockchip,rk3399-vdec reg: maxItems: 1 diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 31c48c38c955..bd0ec27cf49b 100644 +index 9c10b6e3b9bc..23021373e15b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -326,6 +326,10 @@ pd_hevc@RK3328_PD_HEVC { +@@ -306,6 +306,10 @@ power-domain@RK3328_PD_HEVC { }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + #power-domain-cells = <0>; }; - pd_vpu@RK3328_PD_VPU { - reg = ; -@@ -670,6 +674,26 @@ vpu_mmu: iommu@ff350800 { + power-domain@RK3328_PD_VPU { +@@ -660,6 +664,25 @@ vpu_mmu: iommu@ff350800 { power-domains = <&power RK3328_PD_VPU>; }; @@ -968,7 +905,6 @@ index 31c48c38c955..bd0ec27cf49b 100644 + compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; + reg = <0x0 0xff360000 0x0 0x480>; + interrupts = ; -+ interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; @@ -987,7 +923,7 @@ index 31c48c38c955..bd0ec27cf49b 100644 rkvdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; -@@ -678,7 +702,7 @@ rkvdec_mmu: iommu@ff360480 { +@@ -667,7 +690,7 @@ rkvdec_mmu: iommu@ff360480 { clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -1008,10 +944,10 @@ Signed-off-by: Alex Bee 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index c05ba31ed656..4111155d62f4 100644 +index 6abce36eee7f..fbaf0303f7c2 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1134,10 +1134,12 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1096,10 +1096,12 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; /* @@ -1027,3 +963,61 @@ index c05ba31ed656..4111155d62f4 100644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); rkvdec->regs = devm_ioremap_resource(&pdev->dev, res); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 16:12:36 +0200 +Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK + +Required to proper decode H.264@4K + +Signed-off-by: Alex Bee +--- + drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index d4f52957cc53..3d98e2251ea5 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -15,7 +15,8 @@ + #include "rockchip_vpu2_regs.h" + + #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) +-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) ++#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) ++#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) + + /* + * Supported formats. +@@ -272,13 +273,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) + return 0; + } + +-static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++static int rk3288_vpu_hw_init(struct hantro_dev *vpu) + { + /* Bump ACLK to max. possible freq. to improve performance. */ + clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); + return 0; + } + ++static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++{ ++ /* Bump ACLK to max. possible freq. to improve performance. */ ++ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); ++ return 0; ++} ++ + static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; +@@ -511,7 +519,7 @@ const struct hantro_variant rk3288_vpu_variant = { + .codec_ops = rk3288_vpu_codec_ops, + .irqs = rockchip_vpu1_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), +- .init = rockchip_vpu_hw_init, ++ .init = rk3288_vpu_hw_init, + .clk_names = rockchip_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch similarity index 66% rename from projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch rename to projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch index dbf18c3562..474a2b40bc 100644 --- a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch @@ -10,25 +10,26 @@ other SoC components, we have to make sure voltage is never lower then Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 33 ++++++++++++++++++++++++ - 1 file changed, 33 insertions(+) + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 34 ++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index bd0ec27cf49b..21e32ddb21a0 100644 +index 23021373e15b..ca03c8ed9708 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -321,6 +321,10 @@ power: power-controller { +@@ -300,6 +300,11 @@ power: power-controller { #address-cells = <1>; #size-cells = <0>; + power-domain@RK3328_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; ++ #power-domain-cells = <0>; + }; power-domain@RK3328_PD_HEVC { reg = ; - }; -@@ -546,6 +550,11 @@ map0 { + #power-domain-cells = <0>; +@@ -539,6 +544,11 @@ map0 { <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; @@ -40,7 +41,7 @@ index bd0ec27cf49b..21e32ddb21a0 100644 }; }; -@@ -627,7 +636,31 @@ gpu: gpu@ff300000 { +@@ -620,7 +630,31 @@ gpu: gpu@ff300000 { "ppmmu1"; clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; @@ -73,42 +74,6 @@ index bd0ec27cf49b..21e32ddb21a0 100644 h265e_mmu: iommu@ff330200 { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Mon, 10 Feb 2020 19:22:41 +0100 -Subject: [PATCH] arm64: dts: rockchip: add sdmmc ext node for RK3328 - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 21e32ddb21a0..18d663aacd07 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -1109,6 +1109,20 @@ usbdrd_dwc3: dwc3@ff600000 { - }; - }; - -+ sdmmc_ext: dwmmc@ff5f0000 { -+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xff5f0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, -+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <150000000>; -+ resets = <&cru SRST_SDMMCEXT>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ - gic: interrupt-controller@ff811000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 2 Feb 2021 17:22:21 +0200 @@ -183,10 +148,10 @@ index 9c1e38c54eae..ee332fc9cf1f 100644 simple-audio-card,codec { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 03c6737ca0ea..9c2ac03c154b 100644 +index ec3561d147d5..b2ed593a229c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1782,7 +1782,7 @@ hdmi_sound: hdmi-sound { +@@ -1807,7 +1807,7 @@ hdmi_sound: hdmi-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <256>; @@ -207,10 +172,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c -index 69c2c079d803..65fbffc4cbc7 100644 +index d62fb1a3c916..e46165bed006 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c -@@ -1093,7 +1093,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, +@@ -1073,7 +1073,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, ret = obj->funcs->mmap(obj, vma); if (ret) goto err_drm_gem_object_put; @@ -219,6 +184,7 @@ index 69c2c079d803..65fbffc4cbc7 100644 } else { if (!vma->vm_ops) { ret = -EINVAL; + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Mar 2018 22:17:06 +0200 @@ -229,10 +195,10 @@ Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation 1 file changed, 52 insertions(+), 61 deletions(-) diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c -index 403d4c6a49a8..7505c3eee4c1 100644 +index b61f980cabdc..3ad50ae8c93d 100644 --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c -@@ -195,78 +195,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { +@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { */ static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { { .ca_id = 0x00, .n_ch = 2, @@ -364,63 +330,6 @@ index 403d4c6a49a8..7505c3eee4c1 100644 struct hdmi_codec_priv { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 27 Feb 2021 17:41:48 +0100 -Subject: [PATCH] arm64: dts: rockchip: fix GPU register width and supplies for - RK3328 - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- - 3 files changed, 9 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 3ac876c08d61..8607514437f5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -161,6 +161,10 @@ &gmac2io { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index 89fde87f7650..bd62349a9390 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -157,6 +157,10 @@ &gmac2io { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 18d663aacd07..0e5e492db9c7 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -619,7 +619,7 @@ saradc: adc@ff280000 { - - gpu: gpu@ff300000 { - compatible = "rockchip,rk3328-mali", "arm,mali-450"; -- reg = <0x0 0xff300000 0x0 0x40000>; -+ reg = <0x0 0xff300000 0x0 0x30000>; - interrupts = , - , - , - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 2 May 2021 20:44:21 +0200 @@ -434,10 +343,10 @@ Signed-off-by: Alex Bee 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 58097245994a..c7c515c6c5cb 100644 +index 83db4ca67334..06d2a1e3e340 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -247,8 +247,8 @@ &gmac { +@@ -289,8 +289,8 @@ &gmac { snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; @@ -452,20 +361,18 @@ index 58097245994a..c7c515c6c5cb 100644 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 27 Feb 2021 17:52:02 +0100 -Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1/ROC CC - boards +Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 +++++++++++++++++++ - .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 23 +++++++++++++++++++ - 2 files changed, 46 insertions(+) + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++ + 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 4013f16bb368..1bb3f4a6e496 100644 +index de2d3e88e27f..68b74ed080f3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -52,6 +52,24 @@ ir-receiver { +@@ -57,6 +57,24 @@ ir-receiver { gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; linux,rc-map-name = "rc-beelink-gs1"; }; @@ -490,7 +397,7 @@ index 4013f16bb368..1bb3f4a6e496 100644 }; &analog_sound { -@@ -319,6 +337,11 @@ &sdmmc { +@@ -324,6 +342,11 @@ &sdmmc { status = "okay"; }; @@ -502,47 +409,6 @@ index 4013f16bb368..1bb3f4a6e496 100644 &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 8607514437f5..6ca08854aef3 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -102,6 +102,24 @@ user_led: led-1 { - mode = <0x05>; - }; - }; -+ -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; -+ }; -+ -+ spdif_dit: spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ }; - }; - - &analog_sound { -@@ -337,6 +355,11 @@ &sdmmc { - status = "okay"; - }; - -+&spdif { -+ pinctrl-0 = <&spdifm0_tx>; -+ status = "okay"; -+}; -+ - &tsadc { - status = "okay"; - }; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -555,10 +421,10 @@ Signed-off-by: Alex Bee 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 6ca08854aef3..fb21ad1324bc 100644 +index aa22a0c22265..a78fbddd21df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -83,6 +83,13 @@ vcc_phy: vcc-phy-regulator { +@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator { regulator-boot-on; }; @@ -572,7 +438,7 @@ index 6ca08854aef3..fb21ad1324bc 100644 leds { compatible = "gpio-leds"; -@@ -325,6 +332,13 @@ &io_domains { +@@ -308,6 +315,13 @@ &io_domains { }; &pinctrl { @@ -620,10 +486,10 @@ Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 1bb3f4a6e496..99f28dac0791 100644 +index 68b74ed080f3..6736b5dc53e4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -142,6 +142,14 @@ rtl8211f: ethernet-phy@0 { +@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 { }; }; @@ -713,10 +579,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 9c2ac03c154b..b1c7ee80d255 100644 +index b2ed593a229c..27938ff0d208 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1390,7 +1390,7 @@ cru: clock-controller@ff760000 { +@@ -1393,7 +1393,7 @@ cru: clock-controller@ff760000 { <1000000000>, <150000000>, <75000000>, <37500000>, @@ -728,157 +594,52 @@ index 9c2ac03c154b..b1c7ee80d255 100644 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee -Date: Wed, 5 May 2021 22:09:44 +0200 -Subject: [PATCH] arm64: dts: rockchip: limit emmc clockrate to 150 MHz for - Rock Pi4 board - -as per https://github.com/radxa/kernel/commit/db9dfc2cdd25103c553845d24967e4cb31852b61 +Date: Sat, 21 Aug 2021 17:04:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1 Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 1 + - 1 file changed, 1 insertion(+) + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++ + 1 file changed, 5 insertions(+) -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index fb7599f07af4..155f22b53103 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -593,6 +593,7 @@ &sdmmc { +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 6736b5dc53e4..9000fae2a5ee 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -388,6 +388,11 @@ &usb_host0_ehci { + status = "okay"; + }; - &sdhci { - bus-width = <8>; -+ max-frequency = <150000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Rudi Heitbaum -Date: Tue, 1 Jun 2021 19:42:31 +0200 -Subject: [PATCH] arm64: dts: rockchip: dts additions for Rock Pi N10 +From: Alex Bee +Date: Sat, 21 Aug 2021 14:03:25 +0200 +Subject: [PATCH] HACK: media: hantro: rockchip: disable H264 for RK3328 +Signed-off-by: Alex Bee --- - .../dts/rockchip/rk3399pro-rock-pi-n10.dts | 4 + - .../dts/rockchip/rk3399pro-vmarc-som.dtsi | 83 +++++++++++++++++++ - 2 files changed, 87 insertions(+) + drivers/staging/media/hantro/rockchip_vpu_hw.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) -diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts -index 369de5dc0ebd..48ac0cfa93c0 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts -@@ -20,3 +20,7 @@ chosen { - stdout-path = "serial2:1500000n8"; - }; - }; -+ -+&uart2 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -index 7257494d2831..9e2994e27d05 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -@@ -57,6 +57,22 @@ &hdmi { - pinctrl-0 = <&hdmi_cec>; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ assigned-clocks = <&cru ACLK_GPU>; -+ assigned-clock-rates = <200000000>; -+ status = "okay"; -+ /delete-property/ operating-points-v2; -+}; -+ -+&vopl { -+ status = "disabled"; -+}; -+ - &i2c0 { - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <30>; -@@ -280,6 +296,50 @@ regulator-state-mem { - }; - }; - }; -+ -+ vdd_cpu_b: tcs4525@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-compatible = "fan53555-reg"; -+ pinctrl-0 = <&vsel1_gpio>; -+ vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <2300>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-state = <3>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: tcs4526@10 { -+ compatible = "tcs,tcs4526"; -+ reg = <0x10>; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-compatible = "fan53555-reg"; -+ pinctrl-0 = <&vsel2_gpio>; -+ vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <735000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-ramp-delay = <1000>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-state = <3>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2s2 { -+ status = "okay"; - }; - - &i2c1 { -@@ -351,6 +411,29 @@ pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; - }; -+ vsel1_gpio: vsel1-gpio { -+ rockchip,pins = -+ <1 RK_PC1 0 &pcfg_pull_down>; -+ }; -+ vsel2_gpio: vsel2-gpio { -+ rockchip,pins = -+ <1 RK_PB6 0 &pcfg_pull_down>; -+ }; -+ -+ soc_slppin_gpio: soc-slppin-gpio { -+ rockchip,pins = -+ <1 RK_PA5 0 &pcfg_output_low>; -+ }; -+ -+ soc_slppin_slp: soc-slppin-slp { -+ rockchip,pins = -+ <1 RK_PA5 1 &pcfg_pull_down>; -+ }; -+ -+ soc_slppin_rst: soc-slppin-rst { -+ rockchip,pins = -+ <1 RK_PA5 2 &pcfg_pull_none>; -+ }; - }; - - sdio-pwrseq { +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index 3d98e2251ea5..b201700ccc8a 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -530,8 +530,7 @@ const struct hantro_variant rk3328_vpu_variant = { + .dec_offset = 0x400, + .dec_fmts = rk3399_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), +- .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | +- HANTRO_H264_DECODER, ++ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER, + .codec_ops = rk3399_vpu_codec_ops, + .irqs = rockchip_vdpu2_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), diff --git a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch index 3663de8756..0c30dd7bad 100644 --- a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch +++ b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch @@ -10,20 +10,21 @@ Signed-off-by: Boris Brezillon Signed-off-by: Ezequiel Garcia Signed-off-by: Adrian Ratiu --- - .../userspace-api/media/v4l/biblio.rst | 10 + - .../media/v4l/ext-ctrls-codec.rst | 550 ++++++++++++++++++ - drivers/media/v4l2-core/v4l2-ctrls.c | 239 ++++++++ - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/v4l2-ctrls.h | 5 + - include/media/vp9-ctrls.h | 486 ++++++++++++++++ - 6 files changed, 1291 insertions(+) + .../userspace-api/media/v4l/biblio.rst | 10 + + .../media/v4l/ext-ctrls-codec.rst | 1100 +++++++++++++++++ + drivers/media/v4l2-core/v4l2-ctrls-core.c | 225 ++++ + drivers/media/v4l2-core/v4l2-ctrls-defs.c | 14 + + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/media/v4l2-ctrls.h | 5 + + include/media/vp9-ctrls.h | 486 ++++++++ + 7 files changed, 1841 insertions(+) create mode 100644 include/media/vp9-ctrls.h diff --git a/Documentation/userspace-api/media/v4l/biblio.rst b/Documentation/userspace-api/media/v4l/biblio.rst -index 7869b6f6ff72..6b4a83b053f5 100644 +index 7b8e6738ff9e..9cd18c153d19 100644 --- a/Documentation/userspace-api/media/v4l/biblio.rst +++ b/Documentation/userspace-api/media/v4l/biblio.rst -@@ -407,3 +407,13 @@ VP8 +@@ -417,3 +417,13 @@ VP8 :title: RFC 6386: "VP8 Data Format and Decoding Guide" :author: J. Bankoski et al. @@ -38,11 +39,11 @@ index 7869b6f6ff72..6b4a83b053f5 100644 + +:author: Adrian Grange (Google), Peter de Rivaz (Argon Design), Jonathan Hunt (Argon Design) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index ce728c757eaf..456488f2b5ca 100644 +index 8c6e2a11ed95..5dd4afc5f1fe 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -2730,6 +2730,556 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - - ``padding[3]`` +@@ -3106,6 +3106,556 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + - ``padding[2]`` - Applications and drivers must set this to zero. +.. _v4l2-mpeg-vp9: @@ -598,41 +599,570 @@ index ce728c757eaf..456488f2b5ca 100644 .. raw:: latex \normalsize -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 41f8410d08d6..7ed11f296008 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -971,6 +971,11 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: return "VP9 Profile"; - case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: return "VP9 Level"; - case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: return "VP8 Frame Header"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: return "VP9 Frame Decode Parameters"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): return "VP9 Frame Context 0"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): return "VP9 Frame Context 1"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): return "VP9 Frame Context 2"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): return "VP9 Frame Context 3"; +@@ -3157,6 +3707,556 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + - ``padding[6]`` + - Applications and drivers must set this to zero. - /* HEVC controls */ - case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: return "HEVC I-Frame QP Value"; -@@ -1452,6 +1457,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: - *type = V4L2_CTRL_TYPE_VP8_FRAME_HEADER; - break; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: -+ *type = V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): -+ *type = V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT; -+ break; - case V4L2_CID_MPEG_VIDEO_HEVC_SPS: - *type = V4L2_CTRL_TYPE_HEVC_SPS; - break; -@@ -1754,6 +1768,219 @@ static void std_log(const struct v4l2_ctrl *ctrl) - 0; \ - }) ++.. _v4l2-mpeg-vp9: ++ ++``V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0..3) (struct)`` ++ Stores VP9 probabilities attached to a specific frame context. The VP9 ++ specification allows using a maximum of 4 contexts. Each frame being ++ decoded refers to one of those context. See section '7.1.2 Refresh ++ probs semantics' section of :ref:`vp9` for more details about these ++ contexts. ++ ++ This control is bi-directional: ++ ++ * all 4 contexts must be initialized by userspace just after the ++ stream is started and before the first decoding request is submitted. ++ * the referenced context might be read by the kernel when a decoding ++ request is submitted, and will be updated after the decoder is done ++ decoding the frame if the `V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX` flag ++ is set. ++ * contexts will be read back by user space before each decoding request ++ to retrieve the updated probabilities. ++ * userspace will re-initialize the context to their default values when ++ a reset context is required. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_vp9_frame_ctx ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{5.8cm}|p{4.8cm}|p{6.6cm}| ++ ++.. flat-table:: struct v4l2_ctrl_vp9_frame_ctx ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - struct :c:type:`v4l2_vp9_probabilities` ++ - ``probs`` ++ - Structure with VP9 probabilities attached to the context. ++ ++.. c:type:: v4l2_vp9_probabilities ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_probabilities ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``tx8[2][1]`` ++ - TX 8x8 probabilities. ++ * - __u8 ++ - ``tx16[2][2]`` ++ - TX 16x16 probabilities. ++ * - __u8 ++ - ``tx32[2][3]`` ++ - TX 32x32 probabilities. ++ * - __u8 ++ - ``coef[4][2][2][6][6][3]`` ++ - Coefficient probabilities. ++ * - __u8 ++ - ``skip[3]`` ++ - Skip probabilities. ++ * - __u8 ++ - ``inter_mode[7][3]`` ++ - Inter prediction mode probabilities. ++ * - __u8 ++ - ``interp_filter[4][2]`` ++ - Interpolation filter probabilities. ++ * - __u8 ++ - ``is_inter[4]`` ++ - Is inter-block probabilities. ++ * - __u8 ++ - ``comp_mode[5]`` ++ - Compound prediction mode probabilities. ++ * - __u8 ++ - ``single_ref[5][2]`` ++ - Single reference probabilities. ++ * - __u8 ++ - ``comp_mode[5]`` ++ - Compound reference probabilities. ++ * - __u8 ++ - ``y_mode[4][9]`` ++ - Y prediction mode probabilities. ++ * - __u8 ++ - ``uv_mode[10][9]`` ++ - UV prediction mode probabilities. ++ * - __u8 ++ - ``partition[16][3]`` ++ - Partition probabilities. ++ * - __u8 ++ - ``mv.joint[3]`` ++ - Motion vector joint probabilities. ++ * - __u8 ++ - ``mv.sign[2]`` ++ - Motion vector sign probabilities. ++ * - __u8 ++ - ``mv.class[2][10]`` ++ - Motion vector class probabilities. ++ * - __u8 ++ - ``mv.class0_bit[2]`` ++ - Motion vector class0 bit probabilities. ++ * - __u8 ++ - ``mv.bits[2][10]`` ++ - Motion vector bits probabilities. ++ * - __u8 ++ - ``mv.class0_fr[2][2][3]`` ++ - Motion vector class0 fractional bit probabilities. ++ * - __u8 ++ - ``mv.fr[2][3]`` ++ - Motion vector fractional bit probabilities. ++ * - __u8 ++ - ``mv.class0_hp[2]`` ++ - Motion vector class0 high precision fractional bit probabilities. ++ * - __u8 ++ - ``mv.hp[2]`` ++ - Motion vector high precision fractional bit probabilities. ++ ++``V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (struct)`` ++ Specifies the frame parameters for the associated VP9 frame decode request. ++ This includes the necessary parameters for configuring a stateless hardware ++ decoding pipeline for VP9. The bitstream parameters are defined according ++ to :ref:`vp9`. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_vp9_frame_decode_params ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_ctrl_vp9_frame_decode_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``flags`` ++ - Combination of V4L2_VP9_FRAME_FLAG_* flags. See ++ :c:type:`v4l2_vp9_frame_flags`. ++ * - __u16 ++ - ``compressed_header_size`` ++ - Compressed header size in bytes. ++ * - __u16 ++ - ``uncompressed_header_size`` ++ - Uncompressed header size in bytes. ++ * - __u8 ++ - ``profile`` ++ - VP9 profile. Can be 0, 1, 2 or 3. ++ * - __u8 ++ - ``reset_frame_context`` ++ - Frame context that should be used/updated when decoding the frame. ++ * - __u8 ++ - ``bit_depth`` ++ - Component depth in bits. Must be 8 for profile 0 and 1. Must 10 or 12 ++ for profile 2 and 3. ++ * - __u8 ++ - ``interpolation_filter`` ++ - Specifies the filter selection used for performing inter prediction. See ++ :c:type:`v4l2_vp9_interpolation_filter`. ++ * - __u8 ++ - ``tile_cols_log2`` ++ - Specifies the base 2 logarithm of the width of each tile (where the ++ width is measured in units of 8x8 blocks). Shall be less than or equal ++ to 6. ++ * - __u8 ++ - ``tile_rows_log2`` ++ - Specifies the base 2 logarithm of the height of each tile (where the ++ height is measured in units of 8x8 blocks) ++ * - __u8 ++ - ``tx_mode`` ++ - Specifies the TX mode. See :c:type:`v4l2_vp9_tx_mode`. ++ * - __u8 ++ - ``reference_mode`` ++ - Specifies the type of inter prediction to be used. See ++ :c:type:`v4l2_vp9_reference_mode`. ++ * - __u8 ++ - ``padding[7]`` ++ - Needed to make this struct 64 bit aligned. Shall be filled with zeroes. ++ * - __u16 ++ - ``frame_width_minus_1`` ++ - Add 1 to get the frame width expressed in pixels. ++ * - __u16 ++ - ``frame_height_minus_1`` ++ - Add 1 to get the frame height expressed in pixels. ++ * - __u16 ++ - ``frame_width_minus_1`` ++ - Add 1 to get the expected render width expressed in pixels. This is ++ not used during the decoding process but might be used by HW scalers to ++ prepare a frame that's ready for scanout. ++ * - __u16 ++ - frame_height_minus_1 ++ - Add 1 to get the expected render height expressed in pixels. This is ++ not used during the decoding process but might be used by HW scalers to ++ prepare a frame that's ready for scanout. ++ * - __u64 ++ - ``refs[3]`` ++ - Array of reference frame timestamps. ++ * - struct :c:type:`v4l2_vp9_loop_filter` ++ - ``lf`` ++ - Loop filter parameters. See struct :c:type:`v4l2_vp9_loop_filter`. ++ * - struct :c:type:`v4l2_vp9_quantization` ++ - ``quant`` ++ - Quantization parameters. See :c:type:`v4l2_vp9_quantization`. ++ * - struct :c:type:`v4l2_vp9_segmentation` ++ - ``seg`` ++ - Segmentation parameters. See :c:type:`v4l2_vp9_segmentation`. ++ * - struct :c:type:`v4l2_vp9_probabilities` ++ - ``probs`` ++ - Probabilities. See :c:type:`v4l2_vp9_probabilities`. ++ ++.. c:type:: v4l2_vp9_frame_flags ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_frame_flags ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_FRAME_FLAG_KEY_FRAME`` ++ - The frame is a key frame. ++ * - ``V4L2_VP9_FRAME_FLAG_SHOW_FRAME`` ++ - The frame should be displayed. ++ * - ``V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT`` ++ - The decoding should be error resilient. ++ * - ``V4L2_VP9_FRAME_FLAG_INTRA_ONLY`` ++ - The frame does not reference other frames. ++ * - ``V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV`` ++ - the frame might can high precision motion vectors. ++ * - ``V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX`` ++ - Frame context should be updated after decoding. ++ * - ``V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE`` ++ - Parallel decoding is used. ++ * - ``V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING`` ++ - Vertical subsampling is enabled. ++ * - ``V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING`` ++ - Horizontal subsampling is enabled. ++ * - ``V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING`` ++ - The full UV range is used. ++ ++.. c:type:: v4l2_vp9_ref_id ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_ref_id ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_REF_ID_LAST`` ++ - Last reference frame. ++ * - ``V4L2_REF_ID_GOLDEN`` ++ - Golden reference frame. ++ * - ``V4L2_REF_ID_ALTREF`` ++ - Alternative reference frame. ++ * - ``V4L2_REF_ID_CNT`` ++ - Number of reference frames. ++ ++.. c:type:: v4l2_vp9_tx_mode ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_tx_mode ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_TX_MODE_ONLY_4X4`` ++ - Transform size is 4x4. ++ * - ``V4L2_VP9_TX_MODE_ALLOW_8X8`` ++ - Transform size can be up to 8x8. ++ * - ``V4L2_VP9_TX_MODE_ALLOW_16X16`` ++ - Transform size can be up to 16x16. ++ * - ``V4L2_VP9_TX_MODE_ALLOW_32X32`` ++ - transform size can be up to 32x32. ++ * - ``V4L2_VP9_TX_MODE_SELECT`` ++ - Bitstream contains transform size for each block. ++ ++.. c:type:: v4l2_vp9_reference_mode ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_reference_mode ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_REF_MODE_SINGLE`` ++ - Indicates that all the inter blocks use only a single reference frame ++ to generate motion compensated prediction. ++ * - ``V4L2_VP9_REF_MODE_COMPOUND`` ++ - Requires all the inter blocks to use compound mode. Single reference ++ frame prediction is not allowed. ++ * - ``V4L2_VP9_REF_MODE_SELECT`` ++ - Allows each individual inter block to select between single and ++ compound prediction modes. ++ ++.. c:type:: v4l2_vp9_interpolation_filter ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_interpolation_filter ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_INTERP_FILTER_8TAP`` ++ - Height tap filter. ++ * - ``V4L2_VP9_INTERP_FILTER_8TAP_SMOOTH`` ++ - Height tap smooth filter. ++ * - ``V4L2_VP9_INTERP_FILTER_8TAP_SHARP`` ++ - Height tap sharp filter. ++ * - ``V4L2_VP9_INTERP_FILTER_BILINEAR`` ++ - Bilinear filter. ++ * - ``V4L2_VP9_INTERP_FILTER_SWITCHABLE`` ++ - Filter selection is signaled at the block level. ++ ++.. c:type:: v4l2_vp9_reset_frame_context ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_reset_frame_context ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_RESET_FRAME_CTX_NONE`` ++ - Do not reset any frame context. ++ * - ``V4L2_VP9_RESET_FRAME_CTX_SPEC`` ++ - Reset the frame context pointed by ++ :c:type:`v4l2_ctrl_vp9_frame_decode_params`.frame_context_idx. ++ * - ``V4L2_VP9_RESET_FRAME_CTX_ALL`` ++ - Reset all frame contexts. ++ ++.. c:type:: v4l2_vp9_intra_prediction_mode ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_intra_prediction_mode ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_INTRA_PRED_DC`` ++ - DC intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_V`` ++ - Vertical intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_H`` ++ - Horizontal intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D45`` ++ - D45 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D135`` ++ - D135 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D117`` ++ - D117 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D153`` ++ - D153 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D207`` ++ - D207 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D63`` ++ - D63 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_TM`` ++ - True motion intra prediction. ++ ++.. c:type:: v4l2_vp9_segmentation ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_segmentation ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``flags`` ++ - Combination of V4L2_VP9_SEGMENTATION_FLAG_* flags. See ++ :c:type:`v4l2_vp9_segmentation_flags`. ++ * - __u8 ++ - ``tree_probs[7]`` ++ - Specifies the probability values to be used when decoding a Segment-ID. ++ See '5.15. Segmentation map' section of :ref:`vp9` for more details. ++ * - __u8 ++ - ``pred_prob[3]`` ++ - Specifies the probability values to be used when decoding a ++ Predicted-Segment-ID. See '6.4.14. Get segment id syntax' ++ section of :ref:`vp9` for more details. ++ * - __u8 ++ - ``padding[5]`` ++ - Used to align this struct on 64 bit. Shall be filled with zeroes. ++ * - __u8 ++ - ``feature_enabled[8]`` ++ - Bitmask defining which features are enabled in each segment. ++ * - __u8 ++ - ``feature_data[8][4]`` ++ - Data attached to each feature. Data entry is only valid if the feature ++ is enabled. ++ ++.. c:type:: v4l2_vp9_segment_feature ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_segment_feature ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_SEGMENT_FEATURE_QP_DELTA`` ++ - QP delta segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_LF`` ++ - Loop filter segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_REF_FRAME`` ++ - Reference frame segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_SKIP`` ++ - Skip segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_CNT`` ++ - Number of segment features. ++ ++.. c:type:: v4l2_vp9_segmentation_flags ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_segmentation_flags ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_ENABLED`` ++ - Indicates that this frame makes use of the segmentation tool. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP`` ++ - Indicates that the segmentation map should be updated during the ++ decoding of this frame. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE`` ++ - Indicates that the updates to the segmentation map are coded ++ relative to the existing segmentation map. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA`` ++ - Indicates that new parameters are about to be specified for each ++ segment. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE`` ++ - Indicates that the segmentation parameters represent the actual values ++ to be used. ++ ++.. c:type:: v4l2_vp9_quantization ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_quantization ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``base_q_idx`` ++ - Indicates the base frame qindex. ++ * - __s8 ++ - ``delta_q_y_dc`` ++ - Indicates the Y DC quantizer relative to base_q_idx. ++ * - __s8 ++ - ``delta_q_uv_dc`` ++ - Indicates the UV DC quantizer relative to base_q_idx. ++ * - __s8 ++ - ``delta_q_uv_ac`` ++ - Indicates the UV AC quantizer relative to base_q_idx. ++ * - __u8 ++ - ``padding[4]`` ++ - Padding bytes used to align this struct on 64 bit. Must be set to 0. ++ ++.. c:type:: v4l2_vp9_loop_filter ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_loop_filter ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``flags`` ++ - Combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags. ++ See :c:type:`v4l2_vp9_loop_filter_flags`. ++ * - __u8 ++ - ``level`` ++ - Indicates the loop filter strength. ++ * - __u8 ++ - ``sharpness`` ++ - Indicates the sharpness level. ++ * - __s8 ++ - ``ref_deltas[4]`` ++ - Contains the adjustment needed for the filter level based on the chosen ++ reference frame. ++ * - __s8 ++ - ``mode_deltas[2]`` ++ - Contains the adjustment needed for the filter level based on the chosen ++ mode ++ * - __u8 ++ - ``level_lookup[8][4][2]`` ++ - Level lookup table. ++ ++ ++.. c:type:: v4l2_vp9_loop_filter_flags ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_loop_filter_flags ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED`` ++ - When set, the filter level depends on the mode and reference frame used ++ to predict a block. ++ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE`` ++ - When set, the bitstream contains additional syntax elements that ++ specify which mode and reference frame deltas are to be updated. ++ + .. raw:: latex + + \normalsize +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c +index c4b5082849b6..b4802c9989fd 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c +@@ -289,6 +289,219 @@ static void std_log(const struct v4l2_ctrl *ctrl) + } + } +static int +validate_vp9_lf_params(struct v4l2_vp9_loop_filter *lf) @@ -847,11 +1377,11 @@ index 41f8410d08d6..7ed11f296008 100644 + return 0; +} + - /* Validate a new control */ - - #define zero_padding(s) \ -@@ -1871,6 +2098,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - zero_padding(p_vp8_frame_header->coder_state); + /* + * Round towards the closest legal value. Be careful when we are + * close to the maximum range of the control type to prevent +@@ -574,6 +787,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, + zero_padding(p_vp8_frame->coder_state); break; + case V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS: @@ -863,9 +1393,9 @@ index 41f8410d08d6..7ed11f296008 100644 case V4L2_CTRL_TYPE_HEVC_SPS: p_hevc_sps = p; -@@ -2635,6 +2868,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_VP8_FRAME_HEADER: - elem_size = sizeof(struct v4l2_ctrl_vp8_frame_header); +@@ -1231,6 +1450,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_VP8_FRAME: + elem_size = sizeof(struct v4l2_ctrl_vp8_frame); break; + case V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT: + elem_size = sizeof(struct v4l2_ctrl_vp9_frame_ctx); @@ -876,11 +1406,43 @@ index 41f8410d08d6..7ed11f296008 100644 case V4L2_CTRL_TYPE_HEVC_SPS: elem_size = sizeof(struct v4l2_ctrl_hevc_sps); break; +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +index b6344bbf1e00..22a031e25499 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +@@ -940,6 +940,11 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_VP8_PROFILE: return "VP8 Profile"; + case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: return "VP9 Profile"; + case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: return "VP9 Level"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: return "VP9 Frame Decode Parameters"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): return "VP9 Frame Context 0"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): return "VP9 Frame Context 1"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): return "VP9 Frame Context 2"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): return "VP9 Frame Context 3"; + + /* HEVC controls */ + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: return "HEVC I-Frame QP Value"; +@@ -1479,6 +1484,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_STATELESS_VP8_FRAME: + *type = V4L2_CTRL_TYPE_VP8_FRAME; + break; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: ++ *type = V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): ++ *type = V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT; ++ break; + case V4L2_CID_MPEG_VIDEO_HEVC_SPS: + *type = V4L2_CTRL_TYPE_HEVC_SPS; + break; diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 1ff68c1bf14a..783733bef2da 100644 +index fe43d785414c..47f812a081ca 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1429,6 +1429,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1394,6 +1394,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_VP8: descr = "VP8"; break; case V4L2_PIX_FMT_VP8_FRAME: descr = "VP8 Frame"; break; case V4L2_PIX_FMT_VP9: descr = "VP9"; break; @@ -889,30 +1451,30 @@ index 1ff68c1bf14a..783733bef2da 100644 case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 9ecbb98908f0..ebcb34759ad8 100644 +index 575b59fbac77..f62c529b6a70 100644 --- a/include/media/v4l2-ctrls.h +++ b/include/media/v4l2-ctrls.h -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include +@@ -18,6 +18,7 @@ + * This will move to the public headers once this API is fully stable. + */ #include ++#include /* forward references */ -@@ -53,6 +54,8 @@ struct video_device; + struct file; +@@ -50,6 +51,8 @@ struct video_device; * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. * @p_h264_pred_weights: Pointer to a struct v4l2_ctrl_h264_pred_weights. - * @p_vp8_frame_header: Pointer to a VP8 frame header structure. + * @p_vp8_frame: Pointer to a VP8 frame params structure. + * @p_vp9_frame_ctx: Pointer to a VP9 frame context structure. + * @p_vp9_frame_decode_params: Pointer to a VP9 frame params structure. * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. * @p_hevc_slice_params: Pointer to an HEVC slice parameters structure. -@@ -80,6 +83,8 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_hevc_sps *p_hevc_sps; - struct v4l2_ctrl_hevc_pps *p_hevc_pps; +@@ -82,6 +85,8 @@ union v4l2_ctrl_ptr { struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; + struct v4l2_ctrl_hdr10_cll_info *p_hdr10_cll; + struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering; + struct v4l2_ctrl_vp9_frame_ctx *p_vp9_frame_ctx; + struct v4l2_ctrl_vp9_frame_decode_params *p_vp9_frame_decode_params; struct v4l2_area *p_area; @@ -920,7 +1482,7 @@ index 9ecbb98908f0..ebcb34759ad8 100644 const void *p_const; diff --git a/include/media/vp9-ctrls.h b/include/media/vp9-ctrls.h new file mode 100644 -index 000000000000..a14fffb3ad61 +index 000000000000..f62f528d4b39 --- /dev/null +++ b/include/media/vp9-ctrls.h @@ -0,0 +1,486 @@ @@ -1425,9 +1987,9 @@ Signed-off-by: Adrian Ratiu --- drivers/staging/media/rkvdec/Makefile | 2 +- drivers/staging/media/rkvdec/rkvdec-vp9.c | 1577 +++++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec.c | 60 +- + drivers/staging/media/rkvdec/rkvdec.c | 59 +- drivers/staging/media/rkvdec/rkvdec.h | 6 + - 4 files changed, 1643 insertions(+), 2 deletions(-) + 4 files changed, 1642 insertions(+), 2 deletions(-) create mode 100644 drivers/staging/media/rkvdec/rkvdec-vp9.c diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile @@ -3023,10 +3585,10 @@ index 000000000000..8b443ed511c9 + .done = rkvdec_vp9_done, +}; diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index c4e0ec16c285..f3578c5ea902 100644 +index fbaf0303f7c2..2c0c6dcbd066 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,39 @@ static const u32 rkvdec_h264_decoded_fmts[] = { +@@ -159,6 +159,39 @@ static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV20, }; @@ -3066,7 +3628,7 @@ index c4e0ec16c285..f3578c5ea902 100644 static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { { .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -177,6 +211,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -174,6 +207,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .ops = &rkvdec_h264_fmt_ops, .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), .decoded_fmts = rkvdec_h264_decoded_fmts, @@ -3088,7 +3650,7 @@ index c4e0ec16c285..f3578c5ea902 100644 } }; -@@ -376,7 +425,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, +@@ -373,7 +421,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; const struct rkvdec_coded_fmt_desc *desc; struct v4l2_format *cap_fmt; @@ -3097,7 +3659,7 @@ index c4e0ec16c285..f3578c5ea902 100644 int ret; /* -@@ -388,6 +437,15 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, +@@ -385,6 +433,15 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, if (vb2_is_busy(peer_vq)) return -EBUSY; @@ -3114,10 +3676,10 @@ index c4e0ec16c285..f3578c5ea902 100644 if (ret) return ret; diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index c14cd2571bfc..d760c3609e2c 100644 +index fa24bcb6ff42..18dd721172d8 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -58,6 +58,10 @@ struct rkvdec_vp9_decoded_buffer_info { +@@ -57,6 +57,10 @@ struct rkvdec_vp9_decoded_buffer_info { struct rkvdec_decoded_buffer { /* Must be the first field in this struct. */ struct v4l2_m2m_buffer base; @@ -3128,7 +3690,7 @@ index c14cd2571bfc..d760c3609e2c 100644 }; static inline struct rkvdec_decoded_buffer * -@@ -128,4 +132,6 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); +@@ -127,4 +131,6 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index 246dda8da6..bd7b255037 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -1,41 +1,49 @@ From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 13:55:15 +0200 -Subject: [PATCH] media: uapi: hevc: Add scaling matrix control +From: Benjamin Gaignard +Date: Thu, 15 Jul 2021 17:12:22 +0200 +Subject: [PATCH] media: hevc: Add scaling matrix control -HEVC has a scaling matrix concept. Add support for it. +HEVC scaling lists are used for the scaling process for transform +coefficients. +V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED has to set when they are +encoded in the bitstream. -Signed-off-by: Jernej Skrabec +Signed-off-by: Benjamin Gaignard +Reviewed-by: Jernej Skrabec +Reviewed-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab --- - .../media/v4l/ext-ctrls-codec.rst | 41 +++++++++++++++++++ - .../media/v4l/pixfmt-compressed.rst | 1 + - drivers/media/v4l2-core/v4l2-ctrls.c | 10 +++++ - include/media/hevc-ctrls.h | 11 +++++ - 4 files changed, 63 insertions(+) + .../media/v4l/ext-ctrls-codec.rst | 57 +++++++++++++++++++ + .../media/v4l/vidioc-queryctrl.rst | 6 ++ + drivers/media/v4l2-core/v4l2-ctrls-core.c | 6 ++ + drivers/media/v4l2-core/v4l2-ctrls-defs.c | 4 ++ + include/media/hevc-ctrls.h | 11 ++++ + 5 files changed, 84 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index 456488f2b5ca..81529b1d8d69 100644 +index 5dd4afc5f1fe..dc08368d62fe 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -4866,6 +4866,47 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - - ``padding[6]`` - - Applications and drivers must set this to zero. +@@ -3068,6 +3068,63 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + + \normalsize +``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)`` -+ Specifies the scaling matrix (as extracted from the bitstream) for -+ the associated HEVC slice data. The bitstream parameters are -+ defined according to :ref:`hevc`, section 7.4.5 "Scaling list -+ data semantics". For further documentation, refer to the above -+ specification, unless there is an explicit comment stating -+ otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. ++ Specifies the HEVC scaling matrix parameters used for the scaling process ++ for transform coefficients. ++ These matrix and parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.5 "Scaling list data semantics" of ++ the specification. + +.. c:type:: v4l2_ctrl_hevc_scaling_matrix + ++.. raw:: latex ++ ++ \scriptsize ++ ++.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}| ++ +.. cssclass:: longtable + +.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix @@ -45,50 +53,65 @@ index 456488f2b5ca..81529b1d8d69 100644 + + * - __u8 + - ``scaling_list_4x4[6][16]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_8x8[6][64]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_16x16[6][64]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_32x32[2][64]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_dc_coef_16x16[6]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_dc_coef_32x32[2]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + - ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)`` - Specifies the decoding mode to use. Currently exposes slice-based and - frame-based decoding but new modes might be added later on. -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 7ed11f296008..a2609de88d26 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1026,6 +1026,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; - case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; ++.. raw:: latex ++ ++ \normalsize ++ + .. c:type:: v4l2_hevc_dpb_entry + + .. raw:: latex +diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst +index f9ecf6276129..2f491c17dd5d 100644 +--- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst ++++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst +@@ -495,6 +495,12 @@ See also the examples in :ref:`control`. + - n/a + - A struct :c:type:`v4l2_ctrl_hevc_slice_params`, containing HEVC + slice parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_hevc_scaling_matrix`, containing HEVC ++ scaling matrix for stateless video decoders. + * - ``V4L2_CTRL_TYPE_VP8_FRAME`` + - n/a + - n/a +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c +index b4802c9989fd..f557aca9d966 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c +@@ -906,6 +906,9 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, -@@ -1475,6 +1476,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: -+ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; -+ break; - case V4L2_CID_UNIT_CELL_SIZE: - *type = V4L2_CTRL_TYPE_AREA; - *flags |= V4L2_CTRL_FLAG_READ_ONLY; -@@ -2167,6 +2171,9 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - zero_padding(*p_hevc_slice_params); break; + case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: @@ -97,18 +120,40 @@ index 7ed11f296008..a2609de88d26 100644 case V4L2_CTRL_TYPE_AREA: area = p; if (!area->width || !area->height) -@@ -2883,6 +2890,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, +@@ -1465,6 +1468,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); break; + case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: + elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); + break; - case V4L2_CTRL_TYPE_AREA: - elem_size = sizeof(struct v4l2_area); + case V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_hevc_decode_params); + break; +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +index 22a031e25499..bca21812e216 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +@@ -1001,6 +1001,7 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: return "HEVC Decode Parameters"; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; + case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; +@@ -1502,6 +1503,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: + *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: ++ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; ++ break; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: + *type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS; break; diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 1009cf0891cc..1592e52c3614 100644 +index 53c0038c792b..0e5c4a2eecff 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -19,6 +19,7 @@ @@ -116,18 +161,18 @@ index 1009cf0891cc..1592e52c3614 100644 #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) +#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012) #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) - -@@ -26,6 +27,7 @@ +@@ -27,6 +28,7 @@ #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 +#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 + #define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124 enum v4l2_mpeg_video_hevc_decode_mode { - V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -@@ -209,4 +211,13 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -224,6 +226,15 @@ struct v4l2_ctrl_hevc_decode_params { __u64 flags; }; @@ -140,70 +185,59 @@ index 1009cf0891cc..1592e52c3614 100644 + __u8 scaling_list_dc_coef_32x32[2]; +}; + - #endif + /* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */ + #define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) + /* From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 15:42:28 +0200 -Subject: [PATCH] media: uapi: hevc: Add segment address field +From: Jernej Skrabec +Date: Sun, 6 Jun 2021 10:23:13 +0200 +Subject: [PATCH] media: hevc: Add segment address field If HEVC frame consists of multiple slices, segment address has to be known in order to properly decode it. Add segment address field to slice parameters. -Signed-off-by: Jernej Skrabec +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab --- - Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 5 ++++- - include/media/hevc-ctrls.h | 5 ++++- - 2 files changed, 8 insertions(+), 2 deletions(-) + Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 3 +++ + include/media/hevc-ctrls.h | 3 ++- + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index 81529b1d8d69..817773791888 100644 +index dc08368d62fe..9b25674fcd40 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -4661,6 +4661,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - * - __u32 - - ``data_bit_offset`` - - Offset (in bits) to the video data in the current slice data. +@@ -3000,6 +3000,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + * - __u8 + - ``pic_struct`` + - + * - __u32 + - ``slice_segment_addr`` + - * - __u8 - - ``nal_unit_type`` - - -@@ -4738,7 +4741,7 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - - ``num_rps_poc_lt_curr`` - - The number of reference pictures in the long-term set. - * - __u8 -- - ``padding[7]`` -+ - ``padding[5]`` - - Applications and drivers must set this to zero. - * - struct :c:type:`v4l2_hevc_dpb_entry` - - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` + - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` + - The list of L0 reference elements as indices in the DPB. diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 1592e52c3614..3e2e32098312 100644 +index 0e5c4a2eecff..ef63bc205756 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -167,6 +167,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u32 bit_size; - __u32 data_bit_offset; - -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; -+ - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; - __u8 nuh_temporal_id_plus1; -@@ -200,7 +203,7 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; - -- __u8 padding; -+ __u8 padding[5]; +@@ -198,10 +198,11 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 pic_struct; /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u32 slice_segment_addr; + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + +- __u8 padding[5]; ++ __u8 padding; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -214,46 +248,40 @@ NOTE: these fields are used by rkvdec hevc backend Signed-off-by: Jonas Karlman --- - include/media/hevc-ctrls.h | 16 ++++++++++++---- - 1 file changed, 12 insertions(+), 4 deletions(-) + include/media/hevc-ctrls.h | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 3e2e32098312..3cc3b47e1417 100644 +index ef63bc205756..a808894e8c76 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code { +@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { /* The controls are not stable at the moment and will likely be reworked. */ struct v4l2_ctrl_hevc_sps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + __u8 video_parameter_set_id; + __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; __u16 pic_width_in_luma_samples; __u16 pic_height_in_luma_samples; __u8 bit_depth_luma_minus8; -@@ -76,9 +79,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 log2_diff_max_min_pcm_luma_coding_block_size; - __u8 num_short_term_ref_pic_sets; - __u8 num_long_term_ref_pics_sps; -- __u8 chroma_format_idc; - -- __u8 padding; -+ __u8 padding[7]; +@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; ++ __u8 padding[6]; ++ __u64 flags; }; -@@ -105,7 +107,10 @@ struct v4l2_ctrl_hevc_sps { + +@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps { struct v4l2_ctrl_hevc_pps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ + __u8 pic_parameter_set_id; __u8 num_extra_slice_header_bits; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; - __s8 init_qp_minus26; - __u8 diff_cu_qp_delta_depth; - __s8 pps_cb_qp_offset; -@@ -118,7 +123,7 @@ struct v4l2_ctrl_hevc_pps { + __u8 num_ref_idx_l0_default_active_minus1; + __u8 num_ref_idx_l1_default_active_minus1; +@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps { __s8 pps_tc_offset_div2; __u8 log2_parallel_merge_level_minus2; @@ -262,18 +290,18 @@ index 3e2e32098312..3cc3b47e1417 100644 __u64 flags; }; -@@ -203,7 +208,10 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; +@@ -202,7 +207,10 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -- __u8 padding[5]; +- __u8 padding; + __u16 short_term_ref_pic_set_size; + __u16 long_term_ref_pic_set_size; + -+ __u8 padding; ++ __u8 padding[4]; - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -281,42 +309,34 @@ Date: Sat, 23 May 2020 15:07:15 +0000 Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices --- - include/media/hevc-ctrls.h | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) + include/media/hevc-ctrls.h | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 3cc3b47e1417..b33e1a8141e1 100644 +index a808894e8c76..f1b8756521b9 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -80,7 +80,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 num_short_term_ref_pic_sets; - __u8 num_long_term_ref_pics_sps; +@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; -- __u8 padding[7]; +- __u8 padding[6]; + __u8 num_slices; -+ __u8 padding[6]; ++ __u8 padding[5]; __u64 flags; }; -@@ -174,6 +175,7 @@ struct v4l2_ctrl_hevc_slice_params { - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - __u32 slice_segment_addr; -+ __u32 num_entry_point_offsets; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; -@@ -211,7 +213,9 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -210,7 +211,9 @@ struct v4l2_ctrl_hevc_slice_params { __u16 short_term_ref_pic_set_size; __u16 long_term_ref_pic_set_size; -- __u8 padding; -+ __u8 padding[5]; -+ +- __u8 padding[4]; ++ __u32 num_entry_point_offsets; + __u32 entry_point_offset_minus1[256]; ++ __u8 padding[8]; - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -331,9 +351,9 @@ Signed-off-by: Jonas Karlman drivers/staging/media/rkvdec/Makefile | 2 +- drivers/staging/media/rkvdec/rkvdec-hevc.c | 2522 ++++++++++++++++++++ drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 70 + + drivers/staging/media/rkvdec/rkvdec.c | 67 + drivers/staging/media/rkvdec/rkvdec.h | 1 + - 5 files changed, 2595 insertions(+), 1 deletion(-) + 5 files changed, 2592 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile @@ -347,7 +367,7 @@ index cb86b429cfaa..a77122641d14 100644 +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c new file mode 100644 -index 000000000000..03ba848411c6 +index 000000000000..c3cceba837c2 --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -0,0 +1,2522 @@ @@ -2886,11 +2906,11 @@ index 3acc914888f6..4addfaefdfb4 100644 #define RKVDEC_MODE_VP9 2 #define RKVDEC_RPS_MODE BIT(24) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index f3578c5ea902..a44db1aa161e 100644 +index 2c0c6dcbd066..c269e4a21a29 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,57 @@ static const u32 rkvdec_h264_decoded_fmts[] = { - V4L2_PIX_FMT_NV20, +@@ -147,6 +147,58 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { + }, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { @@ -2944,10 +2964,11 @@ index f3578c5ea902..a44db1aa161e 100644 + V4L2_PIX_FMT_NV15, +}; + - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { - { - .mandatory = true, -@@ -212,6 +267,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { ++ + static const struct rkvdec_ctrls rkvdec_h264_ctrls = { + .ctrls = rkvdec_h264_ctrl_descs, + .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), +@@ -208,6 +260,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), .decoded_fmts = rkvdec_h264_decoded_fmts, }, @@ -2970,10 +2991,10 @@ index f3578c5ea902..a44db1aa161e 100644 .fourcc = V4L2_PIX_FMT_VP9_FRAME, .frmsize = { diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index d760c3609e2c..975fe4b5dd68 100644 +index 18dd721172d8..d60840c179a4 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -132,6 +132,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); +@@ -131,6 +131,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; @@ -2982,6 +3003,132 @@ index d760c3609e2c..975fe4b5dd68 100644 #endif /* RKVDEC_H_ */ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 16:01:43 +0200 +Subject: [PATCH] media: rkvdec: hevc: adapt for 5.14 uAPI + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 29 +++++++++++++--------- + drivers/staging/media/rkvdec/rkvdec.c | 3 +++ + 2 files changed, 20 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +index c3cceba837c2..5c341b5fa534 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -116,6 +116,7 @@ struct rkvdec_hevc_priv_tbl { + struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params; + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; +@@ -2179,6 +2180,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, + static void assemble_hw_rps(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; +@@ -2200,7 +2202,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + for (j = 0; j < run->num_slices; j++) { + sl_params = &run->slices_params[j]; +- dpb = sl_params->dpb; ++ dpb = decode_params->dpb; + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); +@@ -2228,9 +2230,9 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + WRITE_RPS(sl_params->long_term_ref_pic_set_size, + LONG_TERM_REF_PIC_SET_SIZE); + +- WRITE_RPS(sl_params->num_rps_poc_st_curr_before + +- sl_params->num_rps_poc_st_curr_after + +- sl_params->num_rps_poc_lt_curr, ++ WRITE_RPS(decode_params->num_poc_st_curr_before + ++ decode_params->num_poc_st_curr_after + ++ decode_params->num_poc_lt_curr, + NUM_RPS_POC); + + //WRITE_RPS(0x3ffff, PS_FIELD(206, 18)); +@@ -2280,12 +2282,12 @@ get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, + unsigned int dpb_idx) + { + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; +- const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; +- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; + int buf_idx = -1; + +- if (dpb_idx < sl_params->num_active_dpb_entries) ++ if (dpb_idx < decode_params->num_active_dpb_entries) + buf_idx = vb2_find_timestamp(cap_q, + dpb[dpb_idx].timestamp, 0); + +@@ -2303,8 +2305,9 @@ static void config_registers(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { + struct rkvdec_dev *rkvdec = ctx->dev; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; +- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; + const struct v4l2_pix_format_mplane *dst_fmt; +@@ -2366,8 +2369,8 @@ static void config_registers(struct rkvdec_ctx *ctx, + for (i = 0; i < 15; i++) { + struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); + +- if (i < 4 && sl_params->num_active_dpb_entries) { +- reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0); ++ if (i < 4 && decode_params->num_active_dpb_entries) { ++ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); + reg = (reg >> (i * 4)) & 0xf; + } else + reg = 0; +@@ -2376,7 +2379,7 @@ static void config_registers(struct rkvdec_ctx *ctx, + writel_relaxed(refer_addr | reg, + rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); + +- reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); ++ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); + writel_relaxed(reg, + rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); + } +@@ -2461,7 +2464,9 @@ static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { + struct v4l2_ctrl *ctrl; +- ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS); ++ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, + V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); + run->slices_params = ctrl ? ctrl->p_cur.p : NULL; +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index c269e4a21a29..e91c2b3e9fd9 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -163,6 +163,9 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, + }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS, ++ }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, + .cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 1 Aug 2020 12:24:58 +0000 @@ -2993,10 +3140,10 @@ Subject: [PATCH] WIP: media: rkvdec: add HEVC format validation 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 03ba848411c6..b8ad7fc2271c 100644 +index 5c341b5fa534..8ea2ad9f4f3a 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2415,6 +2415,16 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, +@@ -2418,6 +2418,16 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, return 0; } @@ -3013,7 +3160,7 @@ index 03ba848411c6..b8ad7fc2271c 100644 static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) { struct rkvdec_dev *rkvdec = ctx->dev; -@@ -2516,6 +2526,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) +@@ -2521,6 +2531,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { .adjust_fmt = rkvdec_hevc_adjust_fmt, @@ -3022,7 +3169,7 @@ index 03ba848411c6..b8ad7fc2271c 100644 .stop = rkvdec_hevc_stop, .run = rkvdec_hevc_run, diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index a44db1aa161e..7419ae7027ab 100644 +index e91c2b3e9fd9..da32a6350344 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -79,6 +79,26 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) @@ -3056,19 +3203,19 @@ index a44db1aa161e..7419ae7027ab 100644 { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -- if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS && !ctx->valid_fmt) { +- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { + if (!ctx->valid_fmt) { ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); if (ctx->valid_fmt) { struct v4l2_pix_format_mplane *pix_mp; -@@ -173,6 +193,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { +@@ -156,6 +176,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + }, { - .mandatory = true, .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, + .cfg.ops = &rkvdec_ctrl_ops, }, { - .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -3082,10 +3229,10 @@ Signed-off-by: Alex Bee 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index b8ad7fc2271c..943f3f4a644a 100644 +index 8ea2ad9f4f3a..58ae8a1a4ff3 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2164,9 +2164,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, +@@ -2165,9 +2165,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, for (i = 0; i <= pps->num_tile_rows_minus1; i++) WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); } else { @@ -3109,10 +3256,10 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 943f3f4a644a..93b4e09e5bf1 100644 +index 58ae8a1a4ff3..55bf61a84165 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2194,8 +2194,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2196,8 +2196,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, #define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) #define LOWDELAY PS_FIELD(182, 1) @@ -3123,7 +3270,7 @@ index 943f3f4a644a..93b4e09e5bf1 100644 #define NUM_RPS_POC PS_FIELD(202, 4) for (j = 0; j < run->num_slices; j++) { -@@ -2222,11 +2222,11 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2224,11 +2224,11 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, // TODO: lowdelay WRITE_RPS(0, LOWDELAY); @@ -3137,8 +3284,8 @@ index 943f3f4a644a..93b4e09e5bf1 100644 - LONG_TERM_REF_PIC_SET_SIZE); + SHORT_TERM_RPS_BIT_OFFSET); - WRITE_RPS(sl_params->num_rps_poc_st_curr_before + - sl_params->num_rps_poc_st_curr_after + + WRITE_RPS(decode_params->num_poc_st_curr_before + + decode_params->num_poc_st_curr_after + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -3148,13 +3295,13 @@ Subject: [PATCH] WIP: media: rkvdec: hevc: implement lowdelay Signed-off-by: Alex Bee --- drivers/staging/media/rkvdec/rkvdec-hevc.c | 16 ++++++++++++++-- - 1 files changed, 14 insertions(+), 2 deletions(-) + 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 93b4e09e5bf1..8a94fc04980f 100644 +index 55bf61a84165..3cca79282111 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2185,6 +2185,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2187,6 +2187,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; struct rkvdec_rps_packet *hw_ps; int i, j; @@ -3162,15 +3309,15 @@ index 93b4e09e5bf1..8a94fc04980f 100644 #define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -@@ -2201,6 +2202,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2203,6 +2204,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, for (j = 0; j < run->num_slices; j++) { sl_params = &run->slices_params[j]; - dpb = sl_params->dpb; + dpb = decode_params->dpb; + lowdelay = 0; hw_ps = &priv_tbl->rps[j]; memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2219,8 +2221,18 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2221,8 +2223,18 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, //WRITE_RPS(0xffffffff, PS_FIELD(96, 32)); @@ -3179,7 +3326,7 @@ index 93b4e09e5bf1..8a94fc04980f 100644 + if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I && + !(!!(sl_params->flags & V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT))) { + lowdelay = 1; -+ for (i = 0; i < sl_params->num_active_dpb_entries; i++) { ++ for (i = 0; i < decode_params->num_active_dpb_entries; i++) { + if (dpb[i].pic_order_cnt[0] > sl_params->slice_pic_order_cnt) { + lowdelay = 0; + break; @@ -3191,6 +3338,7 @@ index 93b4e09e5bf1..8a94fc04980f 100644 WRITE_RPS(sl_params->long_term_ref_pic_set_size + sl_params->short_term_ref_pic_set_size, + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 30 Jan 2021 18:16:39 +0100 @@ -3213,7 +3361,7 @@ Signed-off-by: Alex Bee 2 files changed, 84 insertions(+), 30 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 7419ae7027ab..ab8b42f4f98c 100644 +index da32a6350344..4fb05e8b5a54 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -14,6 +14,7 @@ @@ -3224,7 +3372,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 #include #include #include -@@ -273,21 +274,6 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { +@@ -269,21 +270,6 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { }; static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { @@ -3246,7 +3394,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 { .fourcc = V4L2_PIX_FMT_HEVC_SLICE, .frmsize = { -@@ -302,6 +288,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -298,6 +284,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .ops = &rkvdec_hevc_fmt_ops, .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), .decoded_fmts = rkvdec_hevc_decoded_fmts, @@ -3270,7 +3418,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 }, { .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -317,16 +320,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -313,16 +316,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .ops = &rkvdec_vp9_fmt_ops, .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), .decoded_fmts = rkvdec_vp9_decoded_fmts, @@ -3305,7 +3453,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 return &rkvdec_coded_fmts[i]; } -@@ -349,7 +367,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) +@@ -345,7 +363,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->coded_fmt; @@ -3314,7 +3462,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -376,11 +394,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, +@@ -372,11 +390,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, struct v4l2_frmsizeenum *fsize) { const struct rkvdec_coded_fmt_desc *fmt; @@ -3329,7 +3477,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 if (!fmt) return -EINVAL; -@@ -451,10 +471,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, +@@ -447,10 +467,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); const struct rkvdec_coded_fmt_desc *desc; @@ -3344,7 +3492,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 } v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -541,7 +562,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, +@@ -537,7 +558,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, if (ret) return ret; @@ -3354,7 +3502,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 if (!desc) return -EINVAL; ctx->coded_fmt_desc = desc; -@@ -589,7 +611,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, +@@ -585,7 +607,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, static int rkvdec_enum_output_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f) { @@ -3366,7 +3514,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 return -EINVAL; f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -@@ -1040,14 +1065,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) +@@ -993,14 +1018,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) int ret; for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) @@ -3388,7 +3536,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 } ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1251,8 +1279,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1204,8 +1232,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) } } @@ -3407,7 +3555,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1265,6 +1302,7 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1218,6 +1255,7 @@ static int rkvdec_probe(struct platform_device *pdev) { struct rkvdec_dev *rkvdec; struct resource *res; @@ -3415,7 +3563,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 unsigned int i; int ret, irq; -@@ -1290,6 +1328,12 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1243,6 +1281,12 @@ static int rkvdec_probe(struct platform_device *pdev) if (ret) return ret; @@ -3429,7 +3577,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 * Don't bump ACLK to max. possible freq. (500 MHz) to improve performance, * since it will lead to non-recoverable decoder lockups in case of decoding diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 975fe4b5dd68..cc505bc4a042 100644 +index d60840c179a4..ac1e7d053f62 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -29,6 +29,10 @@ @@ -3443,7 +3591,7 @@ index 975fe4b5dd68..cc505bc4a042 100644 struct rkvdec_ctx; struct rkvdec_ctrl_desc { -@@ -71,6 +75,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) +@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) base.vb.vb2_buf); } @@ -3454,7 +3602,7 @@ index 975fe4b5dd68..cc505bc4a042 100644 struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); -@@ -90,6 +98,7 @@ struct rkvdec_coded_fmt_desc { +@@ -89,6 +97,7 @@ struct rkvdec_coded_fmt_desc { const struct rkvdec_coded_fmt_ops *ops; unsigned int num_decoded_fmts; const u32 *decoded_fmts; @@ -3462,7 +3610,7 @@ index 975fe4b5dd68..cc505bc4a042 100644 }; struct rkvdec_dev { -@@ -104,6 +113,7 @@ struct rkvdec_dev { +@@ -103,6 +112,7 @@ struct rkvdec_dev { struct delayed_work watchdog_work; struct reset_control *rstc; u8 reset_mask; @@ -3485,10 +3633,10 @@ Signed-off-by: Alex Bee 1 file changed, 8 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index ab8b42f4f98c..162623567a1d 100644 +index 4fb05e8b5a54..8767b1149009 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1285,11 +1285,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { +@@ -1238,11 +1238,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { RKVDEC_CAPABILITY_VP9 }; @@ -3520,10 +3668,10 @@ Signed-off-by: Alex Bee 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 746acfac1e92..32e141a3955b 100644 +index 831484253e27..64b36cc8ef94 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1271,6 +1271,25 @@ vpu_mmu: iommu@ff9a0800 { +@@ -1252,6 +1252,25 @@ vpu_mmu: iommu@ff9a0800 { power-domains = <&power RK3288_PD_VIDEO>; }; @@ -3549,7 +3697,7 @@ index 746acfac1e92..32e141a3955b 100644 hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1279,7 +1298,7 @@ hevc_mmu: iommu@ff9c0440 { +@@ -1260,7 +1279,7 @@ hevc_mmu: iommu@ff9c0440 { clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; diff --git a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch index c74198a69a..c5a382818e 100644 --- a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch +++ b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch @@ -109,10 +109,10 @@ Signed-off-by: Alex Bee create mode 100644 drivers/media/platform/rockchip/iep/iep.h diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig -index 7e152bbb4fa6..eee78b20c791 100644 +index 157c924686e4..d77056060c7f 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig -@@ -462,6 +462,20 @@ config VIDEO_RENESAS_VSP1 +@@ -527,6 +527,20 @@ config VIDEO_RENESAS_VSP1 To compile this driver as a module, choose M here: the module will be called vsp1. @@ -134,10 +134,10 @@ index 7e152bbb4fa6..eee78b20c791 100644 tristate "Rockchip Raster 2d Graphic Acceleration Unit" depends on VIDEO_DEV && VIDEO_V4L2 diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile -index 62b6cdc8c730..f99a873818d5 100644 +index 73ce083c2fc6..d1cf1cf99027 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile -@@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o +@@ -54,6 +54,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o obj-$(CONFIG_VIDEO_RENESAS_JPU) += rcar_jpu.o obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/ @@ -1680,10 +1680,10 @@ Signed-off-by: Alex Bee 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 0e5e492db9c7..f014b87c48f0 100644 +index ca03c8ed9708..ef0d04afc1b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -771,6 +771,28 @@ vop_mmu: iommu@ff373f00 { +@@ -759,6 +759,28 @@ vop_mmu: iommu@ff373f00 { status = "disabled"; }; @@ -1724,10 +1724,10 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index b1c7ee80d255..be839c1a7692 100644 +index 27938ff0d208..9adfc422ae90 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1304,6 +1304,17 @@ vdec_mmu: iommu@ff660480 { +@@ -1286,14 +1286,25 @@ vdec_mmu: iommu@ff660480 { #iommu-cells = <0>; }; @@ -1745,8 +1745,7 @@ index b1c7ee80d255..be839c1a7692 100644 iep_mmu: iommu@ff670800 { compatible = "rockchip,iommu"; reg = <0x0 0xff670800 0x0 0x40>; -@@ -1311,8 +1322,8 @@ iep_mmu: iommu@ff670800 { - interrupt-names = "iep_mmu"; + interrupts = ; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_IEP>; @@ -1767,10 +1766,10 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 32e141a3955b..6b1523b38e53 100644 +index 64b36cc8ef94..159c22805d03 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1002,6 +1002,17 @@ crypto: cypto-controller@ff8a0000 { +@@ -983,6 +983,17 @@ crypto: cypto-controller@ff8a0000 { status = "okay"; }; @@ -1788,7 +1787,7 @@ index 32e141a3955b..6b1523b38e53 100644 iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; reg = <0x0 0xff900800 0x0 0x40>; -@@ -1009,8 +1020,8 @@ iep_mmu: iommu@ff900800 { +@@ -990,8 +1001,8 @@ iep_mmu: iommu@ff900800 { interrupt-names = "iep_mmu"; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; From a2ade7655fde4d688bc2576f5ca502274879ce6c Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 2 May 2021 10:46:25 +0200 Subject: [PATCH 35/51] RTL8812AU: Fix building with 5.12 --- ...Fix-GRO_DROP-deprecation-kernel-5-12.patch | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 packages/linux-drivers/RTL8812AU/patches/Fix-GRO_DROP-deprecation-kernel-5-12.patch diff --git a/packages/linux-drivers/RTL8812AU/patches/Fix-GRO_DROP-deprecation-kernel-5-12.patch b/packages/linux-drivers/RTL8812AU/patches/Fix-GRO_DROP-deprecation-kernel-5-12.patch new file mode 100644 index 0000000000..c544a07ec7 --- /dev/null +++ b/packages/linux-drivers/RTL8812AU/patches/Fix-GRO_DROP-deprecation-kernel-5-12.patch @@ -0,0 +1,26 @@ +From e7e83f2593c9e67e3ee50d032f1ad39fe47ea81d Mon Sep 17 00:00:00 2001 +From: Carlos +Date: Sat, 3 Apr 2021 14:38:14 +0000 +Subject: [PATCH] Fix GRO_DROP deprecation kernel 5.12 + +--- + os_dep/linux/recv_linux.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/os_dep/linux/recv_linux.c b/os_dep/linux/recv_linux.c +index 2f7b3e37..7fecc843 100644 +--- a/os_dep/linux/recv_linux.c ++++ b/os_dep/linux/recv_linux.c +@@ -355,8 +355,12 @@ static int napi_recv(_adapter *padapter, int budget) + + #ifdef CONFIG_RTW_GRO + if (pregistrypriv->en_gro) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0) + if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP) + rx_ok = _TRUE; ++#else ++ rx_ok = _TRUE; ++#endif + goto next; + } + #endif /* CONFIG_RTW_GRO */ From fce55b7e34f898c8db8cb63b93e066f3be5caa01 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sat, 17 Apr 2021 14:27:42 +0000 Subject: [PATCH 36/51] linux: 5.13: remove nop-gcc-plugin patch --- .../default/linux-0000-nop-gcc-plugin.patch | 24 ------------------- 1 file changed, 24 deletions(-) delete mode 100644 packages/linux/patches/default/linux-0000-nop-gcc-plugin.patch diff --git a/packages/linux/patches/default/linux-0000-nop-gcc-plugin.patch b/packages/linux/patches/default/linux-0000-nop-gcc-plugin.patch deleted file mode 100644 index 29819e5ca9..0000000000 --- a/packages/linux/patches/default/linux-0000-nop-gcc-plugin.patch +++ /dev/null @@ -1,24 +0,0 @@ -From a7163ecab9b2a395e809e41255f3567d7a188a5d Mon Sep 17 00:00:00 2001 -From: MilhouseVH -Date: Fri, 14 Feb 2020 00:34:00 +0000 -Subject: [PATCH] gcc-plugin.sh: use CONFIG_PLUGIN_HOSTCC="" on all distros - ---- - scripts/gcc-plugin.sh | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/scripts/gcc-plugin.sh b/scripts/gcc-plugin.sh -index d3caefe..6ba7f13 100755 ---- a/scripts/gcc-plugin.sh -+++ b/scripts/gcc-plugin.sh -@@ -1,6 +1,6 @@ - #!/bin/sh - # SPDX-License-Identifier: GPL-2.0 -- -+exit 0 - set -e - - srctree=$(dirname "$0") --- -2.20.1 - From 1bfef8cc233a0852c46b46d6a5030e38351d9423 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 1 Jul 2021 11:50:26 +0200 Subject: [PATCH 37/51] ffmpeg: update v4l2-request patch 5.13 Patch created using revisions e2ee55c..6a200d3 from branch v4l2-request-hwaccel-4.3.2 of https://github.com/jernejsk/FFmpeg --- .../ffmpeg-001-v4l2-request.patch | 3008 ++++++----------- 1 file changed, 988 insertions(+), 2020 deletions(-) diff --git a/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch b/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch index dd82b28dff..6bd75c0343 100644 --- a/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch +++ b/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch @@ -1,7 +1,9 @@ -From 785728e72dbd513b58d97af2590fafba0f8a24bb Mon Sep 17 00:00:00 2001 +From 2c839cfe011862b06bf986a7999caf21c4d54d6e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 3 Dec 2018 23:48:04 +0100 -Subject: [PATCH 01/22] avutil: add av_buffer_pool_flush() +Subject: [PATCH 01/19] avutil: add av_buffer_pool_flush() + +Used by V4L2 request API hwaccel Signed-off-by: Jonas Karlman --- @@ -50,10 +52,10 @@ index c0f3f6cc9abe..998beec9ac5b 100644 * Mark the pool as being available for freeing. It will actually be freed only * once all the allocated buffers associated with the pool are released. Thus it -From abd5308771a71ba582155a1665a1c40878232040 Mon Sep 17 00:00:00 2001 +From adcd1a0731d769828bb88e4637452a8ad84a30d3 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 02/22] Add common V4L2 request API code +Subject: [PATCH 02/19] Add common V4L2 request API code Signed-off-by: Jonas Karlman --- @@ -67,7 +69,7 @@ Signed-off-by: Jonas Karlman create mode 100644 libavcodec/v4l2_request.h diff --git a/configure b/configure -index 8569a60bf827..9f9909a23696 100755 +index 36713ab658f9..81ee0e740498 100755 --- a/configure +++ b/configure @@ -274,6 +274,7 @@ External library support: @@ -1237,10 +1239,688 @@ index 000000000000..58d2aa70af80 + +#endif /* AVCODEC_V4L2_REQUEST_H */ -From e1ae7e32ce4798f3032a04ccb20a1f76834c3bea Mon Sep 17 00:00:00 2001 +From bfb39057e0ba9a8b1e81c799d09730a70af1fa28 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Wed, 20 Feb 2019 11:18:00 -0300 +Subject: [PATCH 03/19] h264dec: add idr_pic_id to slice context + +Used by V4L2 request API h264 hwaccel + +Signed-off-by: Ezequiel Garcia +Signed-off-by: Jonas Karlman +--- + libavcodec/h264_slice.c | 2 +- + libavcodec/h264dec.h | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/libavcodec/h264_slice.c b/libavcodec/h264_slice.c +index 111e1dfe7fa1..81f9a74cb629 100644 +--- a/libavcodec/h264_slice.c ++++ b/libavcodec/h264_slice.c +@@ -1818,7 +1818,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, + } + + if (nal->type == H264_NAL_IDR_SLICE) +- get_ue_golomb_long(&sl->gb); /* idr_pic_id */ ++ sl->idr_pic_id = get_ue_golomb_long(&sl->gb); + + if (sps->poc_type == 0) { + sl->poc_lsb = get_bits(&sl->gb, sps->log2_max_poc_lsb); +diff --git a/libavcodec/h264dec.h b/libavcodec/h264dec.h +index a419615124b2..316dc6a2c890 100644 +--- a/libavcodec/h264dec.h ++++ b/libavcodec/h264dec.h +@@ -335,6 +335,7 @@ typedef struct H264SliceContext { + int delta_poc[2]; + int curr_pic_num; + int max_pic_num; ++ int idr_pic_id; + } H264SliceContext; + + /** + +From 34c532ae4ff98c49ae4517699acecd491661a4f0 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Wed, 22 May 2019 14:44:22 +0200 +Subject: [PATCH 04/19] h264dec: add ref_pic_marking and pic_order_cnt bit_size + to slice context + +Used by V4L2 request API h264 hwaccel + +Signed-off-by: Boris Brezillon +Signed-off-by: Jonas Karlman +--- + libavcodec/h264_slice.c | 6 +++++- + libavcodec/h264dec.h | 2 ++ + 2 files changed, 7 insertions(+), 1 deletion(-) + +diff --git a/libavcodec/h264_slice.c b/libavcodec/h264_slice.c +index 81f9a74cb629..2b370d18e82d 100644 +--- a/libavcodec/h264_slice.c ++++ b/libavcodec/h264_slice.c +@@ -1736,7 +1736,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, + unsigned int slice_type, tmp, i; + int field_pic_flag, bottom_field_flag; + int first_slice = sl == h->slice_ctx && !h->current_slice; +- int picture_structure; ++ int picture_structure, pos; + + if (first_slice) + av_assert0(!h->setup_finished); +@@ -1820,6 +1820,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, + if (nal->type == H264_NAL_IDR_SLICE) + sl->idr_pic_id = get_ue_golomb_long(&sl->gb); + ++ pos = sl->gb.index; + if (sps->poc_type == 0) { + sl->poc_lsb = get_bits(&sl->gb, sps->log2_max_poc_lsb); + +@@ -1833,6 +1834,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, + if (pps->pic_order_present == 1 && picture_structure == PICT_FRAME) + sl->delta_poc[1] = get_se_golomb(&sl->gb); + } ++ sl->pic_order_cnt_bit_size = sl->gb.index - pos; + + sl->redundant_pic_count = 0; + if (pps->redundant_pic_cnt_present) +@@ -1872,9 +1874,11 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, + + sl->explicit_ref_marking = 0; + if (nal->ref_idc) { ++ pos = sl->gb.index; + ret = ff_h264_decode_ref_pic_marking(sl, &sl->gb, nal, h->avctx); + if (ret < 0 && (h->avctx->err_recognition & AV_EF_EXPLODE)) + return AVERROR_INVALIDDATA; ++ sl->ref_pic_marking_bit_size = sl->gb.index - pos; + } + + if (sl->slice_type_nos != AV_PICTURE_TYPE_I && pps->cabac) { +diff --git a/libavcodec/h264dec.h b/libavcodec/h264dec.h +index 316dc6a2c890..f2cabac468d0 100644 +--- a/libavcodec/h264dec.h ++++ b/libavcodec/h264dec.h +@@ -328,6 +328,7 @@ typedef struct H264SliceContext { + MMCO mmco[MAX_MMCO_COUNT]; + int nb_mmco; + int explicit_ref_marking; ++ int ref_pic_marking_bit_size; + + int frame_num; + int poc_lsb; +@@ -336,6 +337,7 @@ typedef struct H264SliceContext { + int curr_pic_num; + int max_pic_num; + int idr_pic_id; ++ int pic_order_cnt_bit_size; + } H264SliceContext; + + /** + +From 67d7c840cdd1b687272e5c482af6688916843a52 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 15 Dec 2018 22:32:16 +0100 +Subject: [PATCH 05/19] Add V4L2 request API h264 hwaccel + +Signed-off-by: Jernej Skrabec +Signed-off-by: Jonas Karlman +--- + configure | 3 + + libavcodec/Makefile | 1 + + libavcodec/h264_slice.c | 4 + + libavcodec/h264dec.c | 3 + + libavcodec/hwaccels.h | 1 + + libavcodec/v4l2_request_h264.c | 456 +++++++++++++++++++++++++++++++++ + 6 files changed, 468 insertions(+) + create mode 100644 libavcodec/v4l2_request_h264.c + +diff --git a/configure b/configure +index 81ee0e740498..0f5b8e355950 100755 +--- a/configure ++++ b/configure +@@ -2925,6 +2925,8 @@ h264_dxva2_hwaccel_deps="dxva2" + h264_dxva2_hwaccel_select="h264_decoder" + h264_nvdec_hwaccel_deps="nvdec" + h264_nvdec_hwaccel_select="h264_decoder" ++h264_v4l2request_hwaccel_deps="v4l2_request h264_v4l2_request" ++h264_v4l2request_hwaccel_select="h264_decoder" + h264_vaapi_hwaccel_deps="vaapi" + h264_vaapi_hwaccel_select="h264_decoder" + h264_vdpau_hwaccel_deps="vdpau" +@@ -6567,6 +6569,7 @@ if enabled v4l2_m2m; then + fi + + check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns ++check_cc h264_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_H264_SLICE;" + + check_headers sys/videoio.h + test_code cc sys/videoio.h "struct v4l2_frmsizeenum vfse; vfse.discrete.width = 0;" && enable_sanitized struct_v4l2_frmivalenum_discrete +diff --git a/libavcodec/Makefile b/libavcodec/Makefile +index d74220516826..4f6e7fc2515c 100644 +--- a/libavcodec/Makefile ++++ b/libavcodec/Makefile +@@ -903,6 +903,7 @@ OBJS-$(CONFIG_H264_D3D11VA_HWACCEL) += dxva2_h264.o + OBJS-$(CONFIG_H264_DXVA2_HWACCEL) += dxva2_h264.o + OBJS-$(CONFIG_H264_NVDEC_HWACCEL) += nvdec_h264.o + OBJS-$(CONFIG_H264_QSV_HWACCEL) += qsvdec_h2645.o ++OBJS-$(CONFIG_H264_V4L2REQUEST_HWACCEL) += v4l2_request_h264.o + OBJS-$(CONFIG_H264_VAAPI_HWACCEL) += vaapi_h264.o + OBJS-$(CONFIG_H264_VDPAU_HWACCEL) += vdpau_h264.o + OBJS-$(CONFIG_H264_VIDEOTOOLBOX_HWACCEL) += videotoolbox.o +diff --git a/libavcodec/h264_slice.c b/libavcodec/h264_slice.c +index 2b370d18e82d..dd5ba98a02cb 100644 +--- a/libavcodec/h264_slice.c ++++ b/libavcodec/h264_slice.c +@@ -759,6 +759,7 @@ static enum AVPixelFormat get_pixel_format(H264Context *h, int force_callback) + #define HWACCEL_MAX (CONFIG_H264_DXVA2_HWACCEL + \ + (CONFIG_H264_D3D11VA_HWACCEL * 2) + \ + CONFIG_H264_NVDEC_HWACCEL + \ ++ CONFIG_H264_V4L2REQUEST_HWACCEL + \ + CONFIG_H264_VAAPI_HWACCEL + \ + CONFIG_H264_VIDEOTOOLBOX_HWACCEL + \ + CONFIG_H264_VDPAU_HWACCEL) +@@ -843,6 +844,9 @@ static enum AVPixelFormat get_pixel_format(H264Context *h, int force_callback) + #endif + #if CONFIG_H264_VIDEOTOOLBOX_HWACCEL + *fmt++ = AV_PIX_FMT_VIDEOTOOLBOX; ++#endif ++#if CONFIG_H264_V4L2REQUEST_HWACCEL ++ *fmt++ = AV_PIX_FMT_DRM_PRIME; + #endif + if (h->avctx->codec->pix_fmts) + choices = h->avctx->codec->pix_fmts; +diff --git a/libavcodec/h264dec.c b/libavcodec/h264dec.c +index 5eedeb3c275d..a504c89565c7 100644 +--- a/libavcodec/h264dec.c ++++ b/libavcodec/h264dec.c +@@ -1102,6 +1102,9 @@ AVCodec ff_h264_decoder = { + #endif + #if CONFIG_H264_VIDEOTOOLBOX_HWACCEL + HWACCEL_VIDEOTOOLBOX(h264), ++#endif ++#if CONFIG_H264_V4L2REQUEST_HWACCEL ++ HWACCEL_V4L2REQUEST(h264), + #endif + NULL + }, +diff --git a/libavcodec/hwaccels.h b/libavcodec/hwaccels.h +index 6109c89bd63c..f758c34ddcf9 100644 +--- a/libavcodec/hwaccels.h ++++ b/libavcodec/hwaccels.h +@@ -27,6 +27,7 @@ extern const AVHWAccel ff_h264_d3d11va_hwaccel; + extern const AVHWAccel ff_h264_d3d11va2_hwaccel; + extern const AVHWAccel ff_h264_dxva2_hwaccel; + extern const AVHWAccel ff_h264_nvdec_hwaccel; ++extern const AVHWAccel ff_h264_v4l2request_hwaccel; + extern const AVHWAccel ff_h264_vaapi_hwaccel; + extern const AVHWAccel ff_h264_vdpau_hwaccel; + extern const AVHWAccel ff_h264_videotoolbox_hwaccel; +diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c +new file mode 100644 +index 000000000000..88da8f0a2db0 +--- /dev/null ++++ b/libavcodec/v4l2_request_h264.c +@@ -0,0 +1,456 @@ ++/* ++ * This file is part of FFmpeg. ++ * ++ * FFmpeg is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU Lesser General Public ++ * License as published by the Free Software Foundation; either ++ * version 2.1 of the License, or (at your option) any later version. ++ * ++ * FFmpeg is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * Lesser General Public License for more details. ++ * ++ * You should have received a copy of the GNU Lesser General Public ++ * License along with FFmpeg; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include "h264dec.h" ++#include "hwconfig.h" ++#include "v4l2_request.h" ++ ++typedef struct V4L2RequestControlsH264 { ++ struct v4l2_ctrl_h264_sps sps; ++ struct v4l2_ctrl_h264_pps pps; ++ struct v4l2_ctrl_h264_scaling_matrix scaling_matrix; ++ struct v4l2_ctrl_h264_decode_params decode_params; ++ struct v4l2_ctrl_h264_slice_params slice_params; ++ struct v4l2_ctrl_h264_pred_weights pred_weights; ++ int pred_weights_required; ++ int first_slice; ++ int num_slices; ++} V4L2RequestControlsH264; ++ ++typedef struct V4L2RequestContextH264 { ++ V4L2RequestContext base; ++ int decode_mode; ++ int start_code; ++} V4L2RequestContextH264; ++ ++static uint8_t nalu_slice_start_code[] = { 0x00, 0x00, 0x01 }; ++ ++static void fill_weight_factors(struct v4l2_h264_weight_factors *factors, int list, const H264SliceContext *sl) ++{ ++ for (int i = 0; i < sl->ref_count[list]; i++) { ++ if (sl->pwt.luma_weight_flag[list]) { ++ factors->luma_weight[i] = sl->pwt.luma_weight[i][list][0]; ++ factors->luma_offset[i] = sl->pwt.luma_weight[i][list][1]; ++ } else { ++ factors->luma_weight[i] = 1 << sl->pwt.luma_log2_weight_denom; ++ factors->luma_offset[i] = 0; ++ } ++ for (int j = 0; j < 2; j++) { ++ if (sl->pwt.chroma_weight_flag[list]) { ++ factors->chroma_weight[i][j] = sl->pwt.chroma_weight[i][list][j][0]; ++ factors->chroma_offset[i][j] = sl->pwt.chroma_weight[i][list][j][1]; ++ } else { ++ factors->chroma_weight[i][j] = 1 << sl->pwt.chroma_log2_weight_denom; ++ factors->chroma_offset[i][j] = 0; ++ } ++ } ++ } ++} ++ ++static void fill_dpb_entry(struct v4l2_h264_dpb_entry *entry, const H264Picture *pic) ++{ ++ entry->reference_ts = ff_v4l2_request_get_capture_timestamp(pic->f); ++ entry->pic_num = pic->pic_id; ++ entry->frame_num = pic->frame_num; ++ entry->fields = pic->reference & V4L2_H264_FRAME_REF; ++ entry->flags = V4L2_H264_DPB_ENTRY_FLAG_VALID; ++ if (entry->fields) ++ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; ++ if (pic->long_ref) ++ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM; ++ if (pic->field_picture) ++ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_FIELD; ++ if (pic->field_poc[0] != INT_MAX) ++ entry->top_field_order_cnt = pic->field_poc[0]; ++ if (pic->field_poc[1] != INT_MAX) ++ entry->bottom_field_order_cnt = pic->field_poc[1]; ++} ++ ++static void fill_dpb(struct v4l2_ctrl_h264_decode_params *decode, const H264Context *h) ++{ ++ int entries = 0; ++ ++ for (int i = 0; i < h->short_ref_count; i++) { ++ const H264Picture *pic = h->short_ref[i]; ++ if (pic && (pic->field_poc[0] != INT_MAX || pic->field_poc[1] != INT_MAX)) ++ fill_dpb_entry(&decode->dpb[entries++], pic); ++ } ++ ++ if (!h->long_ref_count) ++ return; ++ ++ for (int i = 0; i < FF_ARRAY_ELEMS(h->long_ref); i++) { ++ const H264Picture *pic = h->long_ref[i]; ++ if (pic && (pic->field_poc[0] != INT_MAX || pic->field_poc[1] != INT_MAX)) ++ fill_dpb_entry(&decode->dpb[entries++], pic); ++ } ++} ++ ++static void fill_ref_list(struct v4l2_h264_reference *reference, struct v4l2_ctrl_h264_decode_params *decode, const H264Ref *ref) ++{ ++ uint64_t timestamp; ++ ++ if (!ref->parent) ++ return; ++ ++ timestamp = ff_v4l2_request_get_capture_timestamp(ref->parent->f); ++ ++ for (uint8_t i = 0; i < FF_ARRAY_ELEMS(decode->dpb); i++) { ++ struct v4l2_h264_dpb_entry *entry = &decode->dpb[i]; ++ if ((entry->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID) && ++ entry->reference_ts == timestamp) { ++ reference->fields = ref->reference & V4L2_H264_FRAME_REF; ++ reference->index = i; ++ return; ++ } ++ } ++} ++ ++static void fill_sps(struct v4l2_ctrl_h264_sps *ctrl, const H264Context *h) ++{ ++ const SPS *sps = h->ps.sps; ++ ++ *ctrl = (struct v4l2_ctrl_h264_sps) { ++ .profile_idc = sps->profile_idc, ++ .constraint_set_flags = sps->constraint_set_flags, ++ .level_idc = sps->level_idc, ++ .seq_parameter_set_id = sps->sps_id, ++ .chroma_format_idc = sps->chroma_format_idc, ++ .bit_depth_luma_minus8 = sps->bit_depth_luma - 8, ++ .bit_depth_chroma_minus8 = sps->bit_depth_chroma - 8, ++ .log2_max_frame_num_minus4 = sps->log2_max_frame_num - 4, ++ .pic_order_cnt_type = sps->poc_type, ++ .log2_max_pic_order_cnt_lsb_minus4 = sps->log2_max_poc_lsb - 4, ++ .max_num_ref_frames = sps->ref_frame_count, ++ .num_ref_frames_in_pic_order_cnt_cycle = sps->poc_cycle_length, ++ .offset_for_non_ref_pic = sps->offset_for_non_ref_pic, ++ .offset_for_top_to_bottom_field = sps->offset_for_top_to_bottom_field, ++ .pic_width_in_mbs_minus1 = h->mb_width - 1, ++ .pic_height_in_map_units_minus1 = sps->frame_mbs_only_flag ? h->mb_height - 1 : h->mb_height / 2 - 1, ++ }; ++ ++ if (sps->poc_cycle_length > 0 && sps->poc_cycle_length <= 255) ++ memcpy(ctrl->offset_for_ref_frame, sps->offset_for_ref_frame, sps->poc_cycle_length * sizeof(ctrl->offset_for_ref_frame[0])); ++ ++ if (sps->residual_color_transform_flag) ++ ctrl->flags |= V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE; ++ if (sps->transform_bypass) ++ ctrl->flags |= V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS; ++ if (sps->delta_pic_order_always_zero_flag) ++ ctrl->flags |= V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO; ++ if (sps->gaps_in_frame_num_allowed_flag) ++ ctrl->flags |= V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED; ++ if (sps->frame_mbs_only_flag) ++ ctrl->flags |= V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY; ++ if (sps->mb_aff) ++ ctrl->flags |= V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD; ++ if (sps->direct_8x8_inference_flag) ++ ctrl->flags |= V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE; ++} ++ ++static void fill_pps(struct v4l2_ctrl_h264_pps *ctrl, const H264Context *h) ++{ ++ const SPS *sps = h->ps.sps; ++ const PPS *pps = h->ps.pps; ++ const H264SliceContext *sl = &h->slice_ctx[0]; ++ int qp_bd_offset = 6 * (sps->bit_depth_luma - 8); ++ ++ *ctrl = (struct v4l2_ctrl_h264_pps) { ++ .pic_parameter_set_id = sl->pps_id, ++ .seq_parameter_set_id = pps->sps_id, ++ .num_slice_groups_minus1 = pps->slice_group_count - 1, ++ .num_ref_idx_l0_default_active_minus1 = pps->ref_count[0] - 1, ++ .num_ref_idx_l1_default_active_minus1 = pps->ref_count[1] - 1, ++ .weighted_bipred_idc = pps->weighted_bipred_idc, ++ .pic_init_qp_minus26 = pps->init_qp - 26 - qp_bd_offset, ++ .pic_init_qs_minus26 = pps->init_qs - 26 - qp_bd_offset, ++ .chroma_qp_index_offset = pps->chroma_qp_index_offset[0], ++ .second_chroma_qp_index_offset = pps->chroma_qp_index_offset[1], ++ }; ++ ++ if (pps->cabac) ++ ctrl->flags |= V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE; ++ if (pps->pic_order_present) ++ ctrl->flags |= V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT; ++ if (pps->weighted_pred) ++ ctrl->flags |= V4L2_H264_PPS_FLAG_WEIGHTED_PRED; ++ if (pps->deblocking_filter_parameters_present) ++ ctrl->flags |= V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT; ++ if (pps->constrained_intra_pred) ++ ctrl->flags |= V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED; ++ if (pps->redundant_pic_cnt_present) ++ ctrl->flags |= V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT; ++ if (pps->transform_8x8_mode) ++ ctrl->flags |= V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE; ++ ++ /* FFmpeg always provide a scaling matrix */ ++ ctrl->flags |= V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT; ++} ++ ++static int v4l2_request_h264_start_frame(AVCodecContext *avctx, ++ av_unused const uint8_t *buffer, ++ av_unused uint32_t size) ++{ ++ const H264Context *h = avctx->priv_data; ++ const PPS *pps = h->ps.pps; ++ const SPS *sps = h->ps.sps; ++ const H264SliceContext *sl = &h->slice_ctx[0]; ++ V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; ++ ++ fill_sps(&controls->sps, h); ++ fill_pps(&controls->pps, h); ++ ++ memcpy(controls->scaling_matrix.scaling_list_4x4, pps->scaling_matrix4, sizeof(controls->scaling_matrix.scaling_list_4x4)); ++ memcpy(controls->scaling_matrix.scaling_list_8x8[0], pps->scaling_matrix8[0], sizeof(controls->scaling_matrix.scaling_list_8x8[0])); ++ memcpy(controls->scaling_matrix.scaling_list_8x8[1], pps->scaling_matrix8[3], sizeof(controls->scaling_matrix.scaling_list_8x8[1])); ++ ++ if (sps->chroma_format_idc == 3) { ++ memcpy(controls->scaling_matrix.scaling_list_8x8[2], pps->scaling_matrix8[1], sizeof(controls->scaling_matrix.scaling_list_8x8[2])); ++ memcpy(controls->scaling_matrix.scaling_list_8x8[3], pps->scaling_matrix8[4], sizeof(controls->scaling_matrix.scaling_list_8x8[3])); ++ memcpy(controls->scaling_matrix.scaling_list_8x8[4], pps->scaling_matrix8[2], sizeof(controls->scaling_matrix.scaling_list_8x8[4])); ++ memcpy(controls->scaling_matrix.scaling_list_8x8[5], pps->scaling_matrix8[5], sizeof(controls->scaling_matrix.scaling_list_8x8[5])); ++ } ++ ++ controls->decode_params = (struct v4l2_ctrl_h264_decode_params) { ++ .nal_ref_idc = h->nal_ref_idc, ++ .frame_num = h->poc.frame_num, ++ .top_field_order_cnt = h->cur_pic_ptr->field_poc[0] != INT_MAX ? h->cur_pic_ptr->field_poc[0] : 0, ++ .bottom_field_order_cnt = h->cur_pic_ptr->field_poc[1] != INT_MAX ? h->cur_pic_ptr->field_poc[1] : 0, ++ .idr_pic_id = sl->idr_pic_id, ++ .pic_order_cnt_lsb = sl->poc_lsb, ++ .delta_pic_order_cnt_bottom = sl->delta_poc_bottom, ++ .delta_pic_order_cnt0 = sl->delta_poc[0], ++ .delta_pic_order_cnt1 = sl->delta_poc[1], ++ /* Size in bits of dec_ref_pic_marking() syntax element. */ ++ .dec_ref_pic_marking_bit_size = sl->ref_pic_marking_bit_size, ++ /* Size in bits of pic order count syntax. */ ++ .pic_order_cnt_bit_size = sl->pic_order_cnt_bit_size, ++ .slice_group_change_cycle = 0, /* slice group not supported by FFmpeg */ ++ }; ++ ++ if (h->picture_idr) ++ controls->decode_params.flags |= V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC; ++ if (FIELD_PICTURE(h)) ++ controls->decode_params.flags |= V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC; ++ if (h->picture_structure == PICT_BOTTOM_FIELD) ++ controls->decode_params.flags |= V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD; ++ ++ fill_dpb(&controls->decode_params, h); ++ ++ controls->first_slice = !FIELD_PICTURE(h) || h->first_field; ++ controls->num_slices = 0; ++ ++ return ff_v4l2_request_reset_frame(avctx, h->cur_pic_ptr->f); ++} ++ ++static int v4l2_request_h264_queue_decode(AVCodecContext *avctx, int last_slice) ++{ ++ const H264Context *h = avctx->priv_data; ++ V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; ++ V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; ++ ++ struct v4l2_ext_control control[] = { ++ { ++ .id = V4L2_CID_STATELESS_H264_SPS, ++ .ptr = &controls->sps, ++ .size = sizeof(controls->sps), ++ }, ++ { ++ .id = V4L2_CID_STATELESS_H264_PPS, ++ .ptr = &controls->pps, ++ .size = sizeof(controls->pps), ++ }, ++ { ++ .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX, ++ .ptr = &controls->scaling_matrix, ++ .size = sizeof(controls->scaling_matrix), ++ }, ++ { ++ .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, ++ .ptr = &controls->decode_params, ++ .size = sizeof(controls->decode_params), ++ }, ++ { ++ .id = V4L2_CID_STATELESS_H264_SLICE_PARAMS, ++ .ptr = &controls->slice_params, ++ .size = sizeof(controls->slice_params), ++ }, ++ { ++ .id = V4L2_CID_STATELESS_H264_PRED_WEIGHTS, ++ .ptr = &controls->pred_weights, ++ .size = sizeof(controls->pred_weights), ++ }, ++ }; ++ ++ if (ctx->decode_mode == V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED) { ++ int count = FF_ARRAY_ELEMS(control) - (controls->pred_weights_required ? 0 : 1); ++ return ff_v4l2_request_decode_slice(avctx, h->cur_pic_ptr->f, control, count, controls->first_slice, last_slice); ++ } ++ ++ return ff_v4l2_request_decode_frame(avctx, h->cur_pic_ptr->f, control, FF_ARRAY_ELEMS(control) - 2); ++} ++ ++static int v4l2_request_h264_decode_slice(AVCodecContext *avctx, const uint8_t *buffer, uint32_t size) ++{ ++ const H264Context *h = avctx->priv_data; ++ const PPS *pps = h->ps.pps; ++ const H264SliceContext *sl = &h->slice_ctx[0]; ++ V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; ++ V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; ++ int i, ret, count; ++ ++ if (ctx->decode_mode == V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED && controls->num_slices) { ++ ret = v4l2_request_h264_queue_decode(avctx, 0); ++ if (ret) ++ return ret; ++ ++ ff_v4l2_request_reset_frame(avctx, h->cur_pic_ptr->f); ++ controls->first_slice = 0; ++ } ++ ++ if (ctx->start_code == V4L2_STATELESS_H264_START_CODE_ANNEX_B) { ++ ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, nalu_slice_start_code, 3); ++ if (ret) ++ return ret; ++ } ++ ++ ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, buffer, size); ++ if (ret) ++ return ret; ++ ++ if (ctx->decode_mode != V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED) ++ return 0; ++ ++ controls->slice_params = (struct v4l2_ctrl_h264_slice_params) { ++ /* Offset in bits to slice_data() from the beginning of this slice. */ ++ .header_bit_size = get_bits_count(&sl->gb), ++ ++ .first_mb_in_slice = sl->first_mb_addr, ++ ++ .slice_type = ff_h264_get_slice_type(sl), ++ .colour_plane_id = 0, /* separate colour plane not supported by FFmpeg */ ++ .redundant_pic_cnt = sl->redundant_pic_count, ++ .cabac_init_idc = sl->cabac_init_idc, ++ .slice_qp_delta = sl->qscale - pps->init_qp, ++ .slice_qs_delta = 0, /* not implemented by FFmpeg */ ++ .disable_deblocking_filter_idc = sl->deblocking_filter < 2 ? !sl->deblocking_filter : sl->deblocking_filter, ++ .slice_alpha_c0_offset_div2 = sl->slice_alpha_c0_offset / 2, ++ .slice_beta_offset_div2 = sl->slice_beta_offset / 2, ++ .num_ref_idx_l0_active_minus1 = sl->list_count > 0 ? sl->ref_count[0] - 1 : 0, ++ .num_ref_idx_l1_active_minus1 = sl->list_count > 1 ? sl->ref_count[1] - 1 : 0, ++ }; ++ ++ if (sl->slice_type == AV_PICTURE_TYPE_B && sl->direct_spatial_mv_pred) ++ controls->slice_params.flags |= V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED; ++ /* V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH: not implemented by FFmpeg */ ++ ++ controls->pred_weights_required = V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(&controls->pps, &controls->slice_params); ++ if (controls->pred_weights_required) { ++ controls->pred_weights.chroma_log2_weight_denom = sl->pwt.chroma_log2_weight_denom; ++ controls->pred_weights.luma_log2_weight_denom = sl->pwt.luma_log2_weight_denom; ++ } ++ ++ count = sl->list_count > 0 ? sl->ref_count[0] : 0; ++ for (i = 0; i < count; i++) ++ fill_ref_list(&controls->slice_params.ref_pic_list0[i], &controls->decode_params, &sl->ref_list[0][i]); ++ if (count && controls->pred_weights_required) ++ fill_weight_factors(&controls->pred_weights.weight_factors[0], 0, sl); ++ ++ count = sl->list_count > 1 ? sl->ref_count[1] : 0; ++ for (i = 0; i < count; i++) ++ fill_ref_list(&controls->slice_params.ref_pic_list1[i], &controls->decode_params, &sl->ref_list[1][i]); ++ if (count && controls->pred_weights_required) ++ fill_weight_factors(&controls->pred_weights.weight_factors[1], 1, sl); ++ ++ controls->num_slices++; ++ return 0; ++} ++ ++static int v4l2_request_h264_end_frame(AVCodecContext *avctx) ++{ ++ const H264Context *h = avctx->priv_data; ++ return v4l2_request_h264_queue_decode(avctx, !FIELD_PICTURE(h) || !h->first_field); ++} ++ ++static int v4l2_request_h264_set_controls(AVCodecContext *avctx) ++{ ++ V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; ++ ++ struct v4l2_ext_control control[] = { ++ { .id = V4L2_CID_STATELESS_H264_DECODE_MODE, }, ++ { .id = V4L2_CID_STATELESS_H264_START_CODE, }, ++ }; ++ ++ ctx->decode_mode = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_STATELESS_H264_DECODE_MODE); ++ if (ctx->decode_mode != V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED && ++ ctx->decode_mode != V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED) { ++ av_log(avctx, AV_LOG_ERROR, "%s: unsupported decode mode, %d\n", __func__, ctx->decode_mode); ++ return AVERROR(EINVAL); ++ } ++ ++ ctx->start_code = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_STATELESS_H264_START_CODE); ++ if (ctx->start_code != V4L2_STATELESS_H264_START_CODE_NONE && ++ ctx->start_code != V4L2_STATELESS_H264_START_CODE_ANNEX_B) { ++ av_log(avctx, AV_LOG_ERROR, "%s: unsupported start code, %d\n", __func__, ctx->start_code); ++ return AVERROR(EINVAL); ++ } ++ ++ control[0].value = ctx->decode_mode; ++ control[1].value = ctx->start_code; ++ ++ return ff_v4l2_request_set_controls(avctx, control, FF_ARRAY_ELEMS(control)); ++} ++ ++static int v4l2_request_h264_init(AVCodecContext *avctx) ++{ ++ const H264Context *h = avctx->priv_data; ++ struct v4l2_ctrl_h264_sps sps; ++ int ret; ++ ++ struct v4l2_ext_control control[] = { ++ { ++ .id = V4L2_CID_STATELESS_H264_SPS, ++ .ptr = &sps, ++ .size = sizeof(sps), ++ }, ++ }; ++ ++ fill_sps(&sps, h); ++ ++ ret = ff_v4l2_request_init(avctx, V4L2_PIX_FMT_H264_SLICE, 4 * 1024 * 1024, control, FF_ARRAY_ELEMS(control)); ++ if (ret) ++ return ret; ++ ++ return v4l2_request_h264_set_controls(avctx); ++} ++ ++const AVHWAccel ff_h264_v4l2request_hwaccel = { ++ .name = "h264_v4l2request", ++ .type = AVMEDIA_TYPE_VIDEO, ++ .id = AV_CODEC_ID_H264, ++ .pix_fmt = AV_PIX_FMT_DRM_PRIME, ++ .start_frame = v4l2_request_h264_start_frame, ++ .decode_slice = v4l2_request_h264_decode_slice, ++ .end_frame = v4l2_request_h264_end_frame, ++ .frame_priv_data_size = sizeof(V4L2RequestControlsH264), ++ .init = v4l2_request_h264_init, ++ .uninit = ff_v4l2_request_uninit, ++ .priv_data_size = sizeof(V4L2RequestContextH264), ++ .frame_params = ff_v4l2_request_frame_params, ++ .caps_internal = HWACCEL_CAP_ASYNC_SAFE, ++}; + +From d23614d6e368e796019db46b5330c76323bcc49e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 03/22] Add V4L2 request API mpeg2 hwaccel +Subject: [PATCH 06/19] Add V4L2 request API mpeg2 hwaccel Signed-off-by: Jonas Karlman --- @@ -1253,10 +1933,10 @@ Signed-off-by: Jonas Karlman create mode 100644 libavcodec/v4l2_request_mpeg2.c diff --git a/configure b/configure -index 9f9909a23696..6b157d6d3ef0 100755 +index 0f5b8e355950..6ed48234dd25 100755 --- a/configure +++ b/configure -@@ -2967,6 +2967,8 @@ mpeg2_dxva2_hwaccel_deps="dxva2" +@@ -2969,6 +2969,8 @@ mpeg2_dxva2_hwaccel_deps="dxva2" mpeg2_dxva2_hwaccel_select="mpeg2video_decoder" mpeg2_nvdec_hwaccel_deps="nvdec" mpeg2_nvdec_hwaccel_select="mpeg2video_decoder" @@ -1265,19 +1945,19 @@ index 9f9909a23696..6b157d6d3ef0 100755 mpeg2_vaapi_hwaccel_deps="vaapi" mpeg2_vaapi_hwaccel_select="mpeg2video_decoder" mpeg2_vdpau_hwaccel_deps="vdpau" -@@ -6567,6 +6569,7 @@ if enabled v4l2_m2m; then - fi +@@ -6570,6 +6572,7 @@ fi check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns + check_cc h264_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_H264_SLICE;" +check_cc mpeg2_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_MPEG2_SLICE;" check_headers sys/videoio.h test_code cc sys/videoio.h "struct v4l2_frmsizeenum vfse; vfse.discrete.width = 0;" && enable_sanitized struct_v4l2_frmivalenum_discrete diff --git a/libavcodec/Makefile b/libavcodec/Makefile -index d74220516826..8963bd3e91cf 100644 +index 4f6e7fc2515c..9a10a292e377 100644 --- a/libavcodec/Makefile +++ b/libavcodec/Makefile -@@ -922,6 +922,7 @@ OBJS-$(CONFIG_MPEG2_D3D11VA_HWACCEL) += dxva2_mpeg2.o +@@ -923,6 +923,7 @@ OBJS-$(CONFIG_MPEG2_D3D11VA_HWACCEL) += dxva2_mpeg2.o OBJS-$(CONFIG_MPEG2_DXVA2_HWACCEL) += dxva2_mpeg2.o OBJS-$(CONFIG_MPEG2_NVDEC_HWACCEL) += nvdec_mpeg12.o OBJS-$(CONFIG_MPEG2_QSV_HWACCEL) += qsvdec_other.o @@ -1286,10 +1966,10 @@ index d74220516826..8963bd3e91cf 100644 OBJS-$(CONFIG_MPEG2_VDPAU_HWACCEL) += vdpau_mpeg12.o OBJS-$(CONFIG_MPEG2_VIDEOTOOLBOX_HWACCEL) += videotoolbox.o diff --git a/libavcodec/hwaccels.h b/libavcodec/hwaccels.h -index 6109c89bd63c..172a546bb283 100644 +index f758c34ddcf9..44e00e79b515 100644 --- a/libavcodec/hwaccels.h +++ b/libavcodec/hwaccels.h -@@ -47,6 +47,7 @@ extern const AVHWAccel ff_mpeg2_d3d11va_hwaccel; +@@ -48,6 +48,7 @@ extern const AVHWAccel ff_mpeg2_d3d11va_hwaccel; extern const AVHWAccel ff_mpeg2_d3d11va2_hwaccel; extern const AVHWAccel ff_mpeg2_nvdec_hwaccel; extern const AVHWAccel ff_mpeg2_dxva2_hwaccel; @@ -1482,110 +2162,74 @@ index 000000000000..88d86cc4c23f + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From 8a728ea300aee2fab7a181cab06c2c3cfdd0b705 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 04/22] Add V4L2 request API h264 hwaccel +From d09f7dc15ca0d889dcd112a66d2ebc88046fc271 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Wed, 22 May 2019 14:46:58 +0200 +Subject: [PATCH 07/19] Add V4L2 request API vp8 hwaccel -Signed-off-by: Jernej Skrabec +Signed-off-by: Boris Brezillon +Signed-off-by: Ezequiel Garcia Signed-off-by: Jonas Karlman --- - configure | 3 + - libavcodec/Makefile | 1 + - libavcodec/h264_slice.c | 4 + - libavcodec/h264dec.c | 3 + - libavcodec/hwaccels.h | 1 + - libavcodec/v4l2_request_h264.c | 460 +++++++++++++++++++++++++++++++++ - 6 files changed, 472 insertions(+) - create mode 100644 libavcodec/v4l2_request_h264.c + configure | 3 + + libavcodec/Makefile | 1 + + libavcodec/hwaccels.h | 1 + + libavcodec/v4l2_request_vp8.c | 180 ++++++++++++++++++++++++++++++++++ + libavcodec/vp8.c | 8 +- + 5 files changed, 192 insertions(+), 1 deletion(-) + create mode 100644 libavcodec/v4l2_request_vp8.c diff --git a/configure b/configure -index 6b157d6d3ef0..1a7720ebe3be 100755 +index 6ed48234dd25..a3c724861caa 100755 --- a/configure +++ b/configure -@@ -2925,6 +2925,8 @@ h264_dxva2_hwaccel_deps="dxva2" - h264_dxva2_hwaccel_select="h264_decoder" - h264_nvdec_hwaccel_deps="nvdec" - h264_nvdec_hwaccel_select="h264_decoder" -+h264_v4l2request_hwaccel_deps="v4l2_request h264_v4l2_request" -+h264_v4l2request_hwaccel_select="h264_decoder" - h264_vaapi_hwaccel_deps="vaapi" - h264_vaapi_hwaccel_select="h264_decoder" - h264_vdpau_hwaccel_deps="vdpau" -@@ -6569,6 +6571,7 @@ if enabled v4l2_m2m; then - fi - +@@ -3001,6 +3001,8 @@ vc1_vdpau_hwaccel_deps="vdpau" + vc1_vdpau_hwaccel_select="vc1_decoder" + vp8_nvdec_hwaccel_deps="nvdec" + vp8_nvdec_hwaccel_select="vp8_decoder" ++vp8_v4l2request_hwaccel_deps="v4l2_request vp8_v4l2_request" ++vp8_v4l2request_hwaccel_select="vp8_decoder" + vp8_vaapi_hwaccel_deps="vaapi" + vp8_vaapi_hwaccel_select="vp8_decoder" + vp9_d3d11va_hwaccel_deps="d3d11va DXVA_PicParams_VP9" +@@ -6573,6 +6575,7 @@ fi check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns -+check_cc h264_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_H264_SLICE;" + check_cc h264_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_H264_SLICE;" check_cc mpeg2_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_MPEG2_SLICE;" ++check_cc vp8_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_VP8_FRAME;" check_headers sys/videoio.h + test_code cc sys/videoio.h "struct v4l2_frmsizeenum vfse; vfse.discrete.width = 0;" && enable_sanitized struct_v4l2_frmivalenum_discrete diff --git a/libavcodec/Makefile b/libavcodec/Makefile -index 8963bd3e91cf..9a10a292e377 100644 +index 9a10a292e377..c74d2ebfdd23 100644 --- a/libavcodec/Makefile +++ b/libavcodec/Makefile -@@ -903,6 +903,7 @@ OBJS-$(CONFIG_H264_D3D11VA_HWACCEL) += dxva2_h264.o - OBJS-$(CONFIG_H264_DXVA2_HWACCEL) += dxva2_h264.o - OBJS-$(CONFIG_H264_NVDEC_HWACCEL) += nvdec_h264.o - OBJS-$(CONFIG_H264_QSV_HWACCEL) += qsvdec_h2645.o -+OBJS-$(CONFIG_H264_V4L2REQUEST_HWACCEL) += v4l2_request_h264.o - OBJS-$(CONFIG_H264_VAAPI_HWACCEL) += vaapi_h264.o - OBJS-$(CONFIG_H264_VDPAU_HWACCEL) += vdpau_h264.o - OBJS-$(CONFIG_H264_VIDEOTOOLBOX_HWACCEL) += videotoolbox.o -diff --git a/libavcodec/h264_slice.c b/libavcodec/h264_slice.c -index db8363e4cc98..3ae11ac8a711 100644 ---- a/libavcodec/h264_slice.c -+++ b/libavcodec/h264_slice.c -@@ -759,6 +759,7 @@ static enum AVPixelFormat get_pixel_format(H264Context *h, int force_callback) - #define HWACCEL_MAX (CONFIG_H264_DXVA2_HWACCEL + \ - (CONFIG_H264_D3D11VA_HWACCEL * 2) + \ - CONFIG_H264_NVDEC_HWACCEL + \ -+ CONFIG_H264_V4L2REQUEST_HWACCEL + \ - CONFIG_H264_VAAPI_HWACCEL + \ - CONFIG_H264_VIDEOTOOLBOX_HWACCEL + \ - CONFIG_H264_VDPAU_HWACCEL) -@@ -843,6 +844,9 @@ static enum AVPixelFormat get_pixel_format(H264Context *h, int force_callback) - #endif - #if CONFIG_H264_VIDEOTOOLBOX_HWACCEL - *fmt++ = AV_PIX_FMT_VIDEOTOOLBOX; -+#endif -+#if CONFIG_H264_V4L2REQUEST_HWACCEL -+ *fmt++ = AV_PIX_FMT_DRM_PRIME; - #endif - if (h->avctx->codec->pix_fmts) - choices = h->avctx->codec->pix_fmts; -diff --git a/libavcodec/h264dec.c b/libavcodec/h264dec.c -index 5eedeb3c275d..a504c89565c7 100644 ---- a/libavcodec/h264dec.c -+++ b/libavcodec/h264dec.c -@@ -1102,6 +1102,9 @@ AVCodec ff_h264_decoder = { - #endif - #if CONFIG_H264_VIDEOTOOLBOX_HWACCEL - HWACCEL_VIDEOTOOLBOX(h264), -+#endif -+#if CONFIG_H264_V4L2REQUEST_HWACCEL -+ HWACCEL_V4L2REQUEST(h264), - #endif - NULL - }, +@@ -939,6 +939,7 @@ OBJS-$(CONFIG_VC1_QSV_HWACCEL) += qsvdec_other.o + OBJS-$(CONFIG_VC1_VAAPI_HWACCEL) += vaapi_vc1.o + OBJS-$(CONFIG_VC1_VDPAU_HWACCEL) += vdpau_vc1.o + OBJS-$(CONFIG_VP8_NVDEC_HWACCEL) += nvdec_vp8.o ++OBJS-$(CONFIG_VP8_V4L2REQUEST_HWACCEL) += v4l2_request_vp8.o + OBJS-$(CONFIG_VP8_VAAPI_HWACCEL) += vaapi_vp8.o + OBJS-$(CONFIG_VP9_D3D11VA_HWACCEL) += dxva2_vp9.o + OBJS-$(CONFIG_VP9_DXVA2_HWACCEL) += dxva2_vp9.o diff --git a/libavcodec/hwaccels.h b/libavcodec/hwaccels.h -index 172a546bb283..44e00e79b515 100644 +index 44e00e79b515..14838083ec36 100644 --- a/libavcodec/hwaccels.h +++ b/libavcodec/hwaccels.h -@@ -27,6 +27,7 @@ extern const AVHWAccel ff_h264_d3d11va_hwaccel; - extern const AVHWAccel ff_h264_d3d11va2_hwaccel; - extern const AVHWAccel ff_h264_dxva2_hwaccel; - extern const AVHWAccel ff_h264_nvdec_hwaccel; -+extern const AVHWAccel ff_h264_v4l2request_hwaccel; - extern const AVHWAccel ff_h264_vaapi_hwaccel; - extern const AVHWAccel ff_h264_vdpau_hwaccel; - extern const AVHWAccel ff_h264_videotoolbox_hwaccel; -diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c +@@ -64,6 +64,7 @@ extern const AVHWAccel ff_vc1_nvdec_hwaccel; + extern const AVHWAccel ff_vc1_vaapi_hwaccel; + extern const AVHWAccel ff_vc1_vdpau_hwaccel; + extern const AVHWAccel ff_vp8_nvdec_hwaccel; ++extern const AVHWAccel ff_vp8_v4l2request_hwaccel; + extern const AVHWAccel ff_vp8_vaapi_hwaccel; + extern const AVHWAccel ff_vp9_d3d11va_hwaccel; + extern const AVHWAccel ff_vp9_d3d11va2_hwaccel; +diff --git a/libavcodec/v4l2_request_vp8.c b/libavcodec/v4l2_request_vp8.c new file mode 100644 -index 000000000000..94b9aca8ad45 +index 000000000000..bc0fc400727a --- /dev/null -+++ b/libavcodec/v4l2_request_h264.c -@@ -0,0 +1,460 @@ ++++ b/libavcodec/v4l2_request_vp8.c +@@ -0,0 +1,180 @@ +/* + * This file is part of FFmpeg. + * @@ -1604,453 +2248,206 @@ index 000000000000..94b9aca8ad45 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + -+#include "h264dec.h" +#include "hwconfig.h" +#include "v4l2_request.h" ++#include "vp8.h" + -+typedef struct V4L2RequestControlsH264 { -+ struct v4l2_ctrl_h264_sps sps; -+ struct v4l2_ctrl_h264_pps pps; -+ struct v4l2_ctrl_h264_scaling_matrix scaling_matrix; -+ struct v4l2_ctrl_h264_decode_params decode_params; -+ struct v4l2_ctrl_h264_slice_params slice_params[MAX_SLICES]; -+ int first_slice; -+} V4L2RequestControlsH264; ++typedef struct V4L2RequestControlsVP8 { ++ struct v4l2_ctrl_vp8_frame ctrl; ++} V4L2RequestControlsVP8; + -+typedef struct V4L2RequestContextH264 { -+ V4L2RequestContext base; -+ int decode_mode; -+ int start_code; -+ int max_slices; -+} V4L2RequestContextH264; -+ -+static uint8_t nalu_slice_start_code[] = { 0x00, 0x00, 0x01 }; -+ -+static void fill_weight_factors(struct v4l2_h264_weight_factors *factors, int list, const H264SliceContext *sl) ++static int v4l2_request_vp8_start_frame(AVCodecContext *avctx, ++ av_unused const uint8_t *buffer, ++ av_unused uint32_t size) +{ -+ for (int i = 0; i < sl->ref_count[list]; i++) { -+ if (sl->pwt.luma_weight_flag[list]) { -+ factors->luma_weight[i] = sl->pwt.luma_weight[i][list][0]; -+ factors->luma_offset[i] = sl->pwt.luma_weight[i][list][1]; -+ } else { -+ factors->luma_weight[i] = 1 << sl->pwt.luma_log2_weight_denom; -+ factors->luma_offset[i] = 0; -+ } -+ for (int j = 0; j < 2; j++) { -+ if (sl->pwt.chroma_weight_flag[list]) { -+ factors->chroma_weight[i][j] = sl->pwt.chroma_weight[i][list][j][0]; -+ factors->chroma_offset[i][j] = sl->pwt.chroma_weight[i][list][j][1]; -+ } else { -+ factors->chroma_weight[i][j] = 1 << sl->pwt.chroma_log2_weight_denom; -+ factors->chroma_offset[i][j] = 0; ++ const VP8Context *s = avctx->priv_data; ++ V4L2RequestControlsVP8 *controls = s->framep[VP56_FRAME_CURRENT]->hwaccel_picture_private; ++ ++ memset(&controls->ctrl, 0, sizeof(controls->ctrl)); ++ return ff_v4l2_request_reset_frame(avctx, s->framep[VP56_FRAME_CURRENT]->tf.f); ++} ++ ++static int v4l2_request_vp8_end_frame(AVCodecContext *avctx) ++{ ++ const VP8Context *s = avctx->priv_data; ++ V4L2RequestControlsVP8 *controls = s->framep[VP56_FRAME_CURRENT]->hwaccel_picture_private; ++ struct v4l2_ext_control control[] = { ++ { ++ .id = V4L2_CID_STATELESS_VP8_FRAME, ++ .ptr = &controls->ctrl, ++ .size = sizeof(controls->ctrl), ++ }, ++ }; ++ ++ return ff_v4l2_request_decode_frame(avctx, s->framep[VP56_FRAME_CURRENT]->tf.f, ++ control, FF_ARRAY_ELEMS(control)); ++} ++ ++static int v4l2_request_vp8_decode_slice(AVCodecContext *avctx, ++ const uint8_t *buffer, ++ uint32_t size) ++{ ++ const VP8Context *s = avctx->priv_data; ++ V4L2RequestControlsVP8 *controls = s->framep[VP56_FRAME_CURRENT]->hwaccel_picture_private; ++ struct v4l2_ctrl_vp8_frame *frame = &controls->ctrl; ++ const uint8_t *data = buffer + 3 + 7 * s->keyframe; ++ unsigned int i, j, k; ++ ++ frame->version = s->profile & 0x3; ++ frame->width = avctx->width; ++ frame->height = avctx->height; ++ /* FIXME: set ->xx_scale */ ++ frame->prob_skip_false = s->prob->mbskip; ++ frame->prob_intra = s->prob->intra; ++ frame->prob_gf = s->prob->golden; ++ frame->prob_last = s->prob->last; ++ frame->first_part_size = s->header_partition_size; ++ frame->first_part_header_bits = (8 * (s->coder_state_at_header_end.input - data) - ++ s->coder_state_at_header_end.bit_count - 8); ++ frame->num_dct_parts = s->num_coeff_partitions; ++ for (i = 0; i < 8; i++) ++ frame->dct_part_sizes[i] = s->coeff_partition_size[i]; ++ ++ frame->coder_state.range = s->coder_state_at_header_end.range; ++ frame->coder_state.value = s->coder_state_at_header_end.value; ++ frame->coder_state.bit_count = s->coder_state_at_header_end.bit_count; ++ if (s->framep[VP56_FRAME_PREVIOUS]) ++ frame->last_frame_ts = ff_v4l2_request_get_capture_timestamp(s->framep[VP56_FRAME_PREVIOUS]->tf.f); ++ if (s->framep[VP56_FRAME_GOLDEN]) ++ frame->golden_frame_ts = ff_v4l2_request_get_capture_timestamp(s->framep[VP56_FRAME_GOLDEN]->tf.f); ++ if (s->framep[VP56_FRAME_GOLDEN2]) ++ frame->alt_frame_ts = ff_v4l2_request_get_capture_timestamp(s->framep[VP56_FRAME_GOLDEN2]->tf.f); ++ frame->flags |= s->invisible ? 0 : V4L2_VP8_FRAME_FLAG_SHOW_FRAME; ++ frame->flags |= s->mbskip_enabled ? V4L2_VP8_FRAME_FLAG_MB_NO_SKIP_COEFF : 0; ++ frame->flags |= (s->profile & 0x4) ? V4L2_VP8_FRAME_FLAG_EXPERIMENTAL : 0; ++ frame->flags |= s->keyframe ? V4L2_VP8_FRAME_FLAG_KEY_FRAME : 0; ++ frame->flags |= s->sign_bias[VP56_FRAME_GOLDEN] ? V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN : 0; ++ frame->flags |= s->sign_bias[VP56_FRAME_GOLDEN2] ? V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT : 0; ++ frame->segment.flags |= s->segmentation.enabled ? V4L2_VP8_SEGMENT_FLAG_ENABLED : 0; ++ frame->segment.flags |= s->segmentation.update_map ? V4L2_VP8_SEGMENT_FLAG_UPDATE_MAP : 0; ++ frame->segment.flags |= s->segmentation.update_feature_data ? V4L2_VP8_SEGMENT_FLAG_UPDATE_FEATURE_DATA : 0; ++ frame->segment.flags |= s->segmentation.absolute_vals ? 0 : V4L2_VP8_SEGMENT_FLAG_DELTA_VALUE_MODE; ++ for (i = 0; i < 4; i++) { ++ frame->segment.quant_update[i] = s->segmentation.base_quant[i]; ++ frame->segment.lf_update[i] = s->segmentation.filter_level[i]; ++ } ++ ++ for (i = 0; i < 3; i++) ++ frame->segment.segment_probs[i] = s->prob->segmentid[i]; ++ ++ frame->lf.level = s->filter.level; ++ frame->lf.sharpness_level = s->filter.sharpness; ++ frame->lf.flags |= s->lf_delta.enabled ? V4L2_VP8_LF_ADJ_ENABLE : 0; ++ frame->lf.flags |= s->lf_delta.update ? V4L2_VP8_LF_DELTA_UPDATE : 0; ++ frame->lf.flags |= s->filter.simple ? V4L2_VP8_LF_FILTER_TYPE_SIMPLE : 0; ++ for (i = 0; i < 4; i++) { ++ frame->lf.ref_frm_delta[i] = s->lf_delta.ref[i]; ++ frame->lf.mb_mode_delta[i] = s->lf_delta.mode[i + MODE_I4x4]; ++ } ++ ++ // Probabilites ++ if (s->keyframe) { ++ static const uint8_t keyframe_y_mode_probs[4] = { ++ 145, 156, 163, 128 ++ }; ++ static const uint8_t keyframe_uv_mode_probs[3] = { ++ 142, 114, 183 ++ }; ++ ++ memcpy(frame->entropy.y_mode_probs, keyframe_y_mode_probs, 4); ++ memcpy(frame->entropy.uv_mode_probs, keyframe_uv_mode_probs, 3); ++ } else { ++ for (i = 0; i < 4; i++) ++ frame->entropy.y_mode_probs[i] = s->prob->pred16x16[i]; ++ for (i = 0; i < 3; i++) ++ frame->entropy.uv_mode_probs[i] = s->prob->pred8x8c[i]; ++ } ++ for (i = 0; i < 2; i++) ++ for (j = 0; j < 19; j++) ++ frame->entropy.mv_probs[i][j] = s->prob->mvc[i][j]; ++ ++ for (i = 0; i < 4; i++) { ++ for (j = 0; j < 8; j++) { ++ static const int coeff_bands_inverse[8] = { ++ 0, 1, 2, 3, 5, 6, 4, 15 ++ }; ++ int coeff_pos = coeff_bands_inverse[j]; ++ ++ for (k = 0; k < 3; k++) { ++ memcpy(frame->entropy.coeff_probs[i][j][k], ++ s->prob->token[i][coeff_pos][k], 11); + } + } + } ++ ++ frame->quant.y_ac_qi = s->quant.yac_qi; ++ frame->quant.y_dc_delta = s->quant.ydc_delta; ++ frame->quant.y2_dc_delta = s->quant.y2dc_delta; ++ frame->quant.y2_ac_delta = s->quant.y2ac_delta; ++ frame->quant.uv_dc_delta = s->quant.uvdc_delta; ++ frame->quant.uv_ac_delta = s->quant.uvac_delta; ++ ++ return ff_v4l2_request_append_output_buffer(avctx, s->framep[VP56_FRAME_CURRENT]->tf.f, buffer, size); +} + -+static void fill_dpb_entry(struct v4l2_h264_dpb_entry *entry, const H264Picture *pic) ++static int v4l2_request_vp8_init(AVCodecContext *avctx) +{ -+ entry->reference_ts = ff_v4l2_request_get_capture_timestamp(pic->f); -+ entry->frame_num = pic->frame_num; -+ entry->pic_num = pic->pic_id; -+ entry->flags = V4L2_H264_DPB_ENTRY_FLAG_VALID; -+ if (pic->reference) -+ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; -+ if (pic->long_ref) -+ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM; -+ if (pic->field_poc[0] != INT_MAX) -+ entry->top_field_order_cnt = pic->field_poc[0]; -+ if (pic->field_poc[1] != INT_MAX) -+ entry->bottom_field_order_cnt = pic->field_poc[1]; ++ return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_VP8_FRAME, 2 * 1024 * 1024, NULL, 0); +} + -+static void fill_dpb(struct v4l2_ctrl_h264_decode_params *decode, const H264Context *h) -+{ -+ int entries = 0; -+ -+ for (int i = 0; i < h->short_ref_count; i++) { -+ const H264Picture *pic = h->short_ref[i]; -+ if (pic && (pic->field_poc[0] != INT_MAX || pic->field_poc[1] != INT_MAX)) -+ fill_dpb_entry(&decode->dpb[entries++], pic); -+ } -+ -+ if (!h->long_ref_count) -+ return; -+ -+ for (int i = 0; i < FF_ARRAY_ELEMS(h->long_ref); i++) { -+ const H264Picture *pic = h->long_ref[i]; -+ if (pic && (pic->field_poc[0] != INT_MAX || pic->field_poc[1] != INT_MAX)) -+ fill_dpb_entry(&decode->dpb[entries++], pic); -+ } -+} -+ -+static uint8_t get_dpb_index(struct v4l2_ctrl_h264_decode_params *decode, const H264Ref *ref) -+{ -+ uint64_t timestamp; -+ -+ if (!ref->parent) -+ return 0; -+ -+ timestamp = ff_v4l2_request_get_capture_timestamp(ref->parent->f); -+ -+ for (uint8_t i = 0; i < FF_ARRAY_ELEMS(decode->dpb); i++) { -+ struct v4l2_h264_dpb_entry *entry = &decode->dpb[i]; -+ if ((entry->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID) && -+ entry->reference_ts == timestamp) -+ return i; -+ } -+ -+ return 0; -+} -+ -+static void fill_sps(struct v4l2_ctrl_h264_sps *ctrl, const H264Context *h) -+{ -+ const SPS *sps = h->ps.sps; -+ -+ *ctrl = (struct v4l2_ctrl_h264_sps) { -+ .profile_idc = sps->profile_idc, -+ .constraint_set_flags = sps->constraint_set_flags, -+ .level_idc = sps->level_idc, -+ .seq_parameter_set_id = sps->sps_id, -+ .chroma_format_idc = sps->chroma_format_idc, -+ .bit_depth_luma_minus8 = sps->bit_depth_luma - 8, -+ .bit_depth_chroma_minus8 = sps->bit_depth_chroma - 8, -+ .log2_max_frame_num_minus4 = sps->log2_max_frame_num - 4, -+ .pic_order_cnt_type = sps->poc_type, -+ .log2_max_pic_order_cnt_lsb_minus4 = sps->log2_max_poc_lsb - 4, -+ .max_num_ref_frames = sps->ref_frame_count, -+ .num_ref_frames_in_pic_order_cnt_cycle = sps->poc_cycle_length, -+ //.offset_for_ref_frame[255] - not required? not set by libva-v4l2-request - copy sps->offset_for_ref_frame -+ .offset_for_non_ref_pic = sps->offset_for_non_ref_pic, -+ .offset_for_top_to_bottom_field = sps->offset_for_top_to_bottom_field, -+ .pic_width_in_mbs_minus1 = h->mb_width - 1, -+ .pic_height_in_map_units_minus1 = sps->frame_mbs_only_flag ? h->mb_height - 1 : h->mb_height / 2 - 1, -+ }; -+ -+ if (sps->residual_color_transform_flag) -+ ctrl->flags |= V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE; -+ if (sps->transform_bypass) -+ ctrl->flags |= V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS; -+ if (sps->delta_pic_order_always_zero_flag) -+ ctrl->flags |= V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO; -+ if (sps->gaps_in_frame_num_allowed_flag) -+ ctrl->flags |= V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED; -+ if (sps->frame_mbs_only_flag) -+ ctrl->flags |= V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY; -+ if (sps->mb_aff) -+ ctrl->flags |= V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD; -+ if (sps->direct_8x8_inference_flag) -+ ctrl->flags |= V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE; -+} -+ -+static void fill_pps(struct v4l2_ctrl_h264_pps *ctrl, const H264Context *h) -+{ -+ const SPS *sps = h->ps.sps; -+ const PPS *pps = h->ps.pps; -+ const H264SliceContext *sl = &h->slice_ctx[0]; -+ int qp_bd_offset = 6 * (sps->bit_depth_luma - 8); -+ -+ *ctrl = (struct v4l2_ctrl_h264_pps) { -+ .pic_parameter_set_id = sl->pps_id, -+ .seq_parameter_set_id = pps->sps_id, -+ .num_slice_groups_minus1 = pps->slice_group_count - 1, -+ .num_ref_idx_l0_default_active_minus1 = pps->ref_count[0] - 1, -+ .num_ref_idx_l1_default_active_minus1 = pps->ref_count[1] - 1, -+ .weighted_bipred_idc = pps->weighted_bipred_idc, -+ .pic_init_qp_minus26 = pps->init_qp - 26 - qp_bd_offset, -+ .pic_init_qs_minus26 = pps->init_qs - 26 - qp_bd_offset, -+ .chroma_qp_index_offset = pps->chroma_qp_index_offset[0], -+ .second_chroma_qp_index_offset = pps->chroma_qp_index_offset[1], -+ }; -+ -+ if (pps->cabac) -+ ctrl->flags |= V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE; -+ if (pps->pic_order_present) -+ ctrl->flags |= V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT; -+ if (pps->weighted_pred) -+ ctrl->flags |= V4L2_H264_PPS_FLAG_WEIGHTED_PRED; -+ if (pps->deblocking_filter_parameters_present) -+ ctrl->flags |= V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT; -+ if (pps->constrained_intra_pred) -+ ctrl->flags |= V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED; -+ if (pps->redundant_pic_cnt_present) -+ ctrl->flags |= V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT; -+ if (pps->transform_8x8_mode) -+ ctrl->flags |= V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE; -+} -+ -+static int v4l2_request_h264_start_frame(AVCodecContext *avctx, -+ av_unused const uint8_t *buffer, -+ av_unused uint32_t size) -+{ -+ const H264Context *h = avctx->priv_data; -+ const PPS *pps = h->ps.pps; -+ const SPS *sps = h->ps.sps; -+ V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; -+ -+ fill_sps(&controls->sps, h); -+ fill_pps(&controls->pps, h); -+ -+ memcpy(controls->scaling_matrix.scaling_list_4x4, pps->scaling_matrix4, sizeof(controls->scaling_matrix.scaling_list_4x4)); -+ memcpy(controls->scaling_matrix.scaling_list_8x8[0], pps->scaling_matrix8[0], sizeof(controls->scaling_matrix.scaling_list_8x8[0])); -+ memcpy(controls->scaling_matrix.scaling_list_8x8[1], pps->scaling_matrix8[3], sizeof(controls->scaling_matrix.scaling_list_8x8[1])); -+ -+ if (sps->chroma_format_idc == 3) { -+ memcpy(controls->scaling_matrix.scaling_list_8x8[2], pps->scaling_matrix8[1], sizeof(controls->scaling_matrix.scaling_list_8x8[2])); -+ memcpy(controls->scaling_matrix.scaling_list_8x8[3], pps->scaling_matrix8[4], sizeof(controls->scaling_matrix.scaling_list_8x8[3])); -+ memcpy(controls->scaling_matrix.scaling_list_8x8[4], pps->scaling_matrix8[2], sizeof(controls->scaling_matrix.scaling_list_8x8[4])); -+ memcpy(controls->scaling_matrix.scaling_list_8x8[5], pps->scaling_matrix8[5], sizeof(controls->scaling_matrix.scaling_list_8x8[5])); -+ } -+ -+ controls->decode_params = (struct v4l2_ctrl_h264_decode_params) { -+ .num_slices = 0, -+ .nal_ref_idc = h->nal_ref_idc, -+ .top_field_order_cnt = h->cur_pic_ptr->field_poc[0] != INT_MAX ? h->cur_pic_ptr->field_poc[0] : 0, -+ .bottom_field_order_cnt = h->cur_pic_ptr->field_poc[1] != INT_MAX ? h->cur_pic_ptr->field_poc[1] : 0, -+ }; -+ -+ if (h->picture_idr) -+ controls->decode_params.flags |= V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC; -+ -+ fill_dpb(&controls->decode_params, h); -+ -+ controls->first_slice = !FIELD_PICTURE(h) || h->first_field; -+ -+ return ff_v4l2_request_reset_frame(avctx, h->cur_pic_ptr->f); -+} -+ -+static int v4l2_request_h264_queue_decode(AVCodecContext *avctx, int last_slice) -+{ -+ const H264Context *h = avctx->priv_data; -+ V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; -+ V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; -+ -+ struct v4l2_ext_control control[] = { -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, -+ .ptr = &controls->sps, -+ .size = sizeof(controls->sps), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -+ .ptr = &controls->pps, -+ .size = sizeof(controls->pps), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, -+ .ptr = &controls->scaling_matrix, -+ .size = sizeof(controls->scaling_matrix), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -+ .ptr = &controls->slice_params, -+ .size = sizeof(controls->slice_params[0]) * FFMAX(FFMIN(controls->decode_params.num_slices, MAX_SLICES), ctx->max_slices), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, -+ .ptr = &controls->decode_params, -+ .size = sizeof(controls->decode_params), -+ }, -+ }; -+ -+ if (ctx->decode_mode == V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED) -+ return ff_v4l2_request_decode_slice(avctx, h->cur_pic_ptr->f, control, FF_ARRAY_ELEMS(control), controls->first_slice, last_slice); -+ -+ return ff_v4l2_request_decode_frame(avctx, h->cur_pic_ptr->f, control, FF_ARRAY_ELEMS(control)); -+} -+ -+static int v4l2_request_h264_decode_slice(AVCodecContext *avctx, const uint8_t *buffer, uint32_t size) -+{ -+ const H264Context *h = avctx->priv_data; -+ const PPS *pps = h->ps.pps; -+ const H264SliceContext *sl = &h->slice_ctx[0]; -+ V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; -+ V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; -+ V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)h->cur_pic_ptr->f->data[0]; -+ int i, ret, count, slice = FFMIN(controls->decode_params.num_slices, MAX_SLICES - 1); -+ -+ if (ctx->decode_mode == V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED && slice) { -+ ret = v4l2_request_h264_queue_decode(avctx, 0); -+ if (ret) -+ return ret; -+ -+ ff_v4l2_request_reset_frame(avctx, h->cur_pic_ptr->f); -+ slice = controls->decode_params.num_slices = 0; -+ controls->first_slice = 0; -+ } -+ -+ controls->slice_params[slice] = (struct v4l2_ctrl_h264_slice_params) { -+ /* Size in bytes, including header */ -+ .size = 0, -+ .start_byte_offset = req->output.used, -+ /* Offset in bits to slice_data() from the beginning of this slice. */ -+ .header_bit_size = get_bits_count(&sl->gb), -+ -+ .first_mb_in_slice = sl->first_mb_addr, -+ .slice_type = ff_h264_get_slice_type(sl), -+ .pic_parameter_set_id = sl->pps_id, -+ .colour_plane_id = 0, /* what is this? */ -+ .frame_num = h->poc.frame_num, -+ .idr_pic_id = 0, /* what is this? */ -+ .pic_order_cnt_lsb = sl->poc_lsb, -+ .delta_pic_order_cnt_bottom = sl->delta_poc_bottom, -+ .delta_pic_order_cnt0 = sl->delta_poc[0], -+ .delta_pic_order_cnt1 = sl->delta_poc[1], -+ .redundant_pic_cnt = sl->redundant_pic_count, -+ -+ /* Size in bits of dec_ref_pic_marking() syntax element. */ -+ .dec_ref_pic_marking_bit_size = 0, -+ /* Size in bits of pic order count syntax. */ -+ .pic_order_cnt_bit_size = 0, -+ -+ .cabac_init_idc = sl->cabac_init_idc, -+ .slice_qp_delta = sl->qscale - pps->init_qp, -+ .slice_qs_delta = 0, /* XXX not implemented by FFmpeg */ -+ .disable_deblocking_filter_idc = sl->deblocking_filter < 2 ? !sl->deblocking_filter : sl->deblocking_filter, -+ .slice_alpha_c0_offset_div2 = sl->slice_alpha_c0_offset / 2, -+ .slice_beta_offset_div2 = sl->slice_beta_offset / 2, -+ .slice_group_change_cycle = 0, /* what is this? */ -+ -+ .num_ref_idx_l0_active_minus1 = sl->list_count > 0 ? sl->ref_count[0] - 1 : 0, -+ .num_ref_idx_l1_active_minus1 = sl->list_count > 1 ? sl->ref_count[1] - 1 : 0, -+ }; -+ -+ if (FIELD_PICTURE(h)) -+ controls->slice_params[slice].flags |= V4L2_H264_SLICE_FLAG_FIELD_PIC; -+ if (h->picture_structure == PICT_BOTTOM_FIELD) -+ controls->slice_params[slice].flags |= V4L2_H264_SLICE_FLAG_BOTTOM_FIELD; -+ if (sl->slice_type == AV_PICTURE_TYPE_B && sl->direct_spatial_mv_pred) -+ controls->slice_params[slice].flags |= V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED; -+ -+ controls->slice_params[slice].pred_weight_table.chroma_log2_weight_denom = sl->pwt.chroma_log2_weight_denom; -+ controls->slice_params[slice].pred_weight_table.luma_log2_weight_denom = sl->pwt.luma_log2_weight_denom; -+ -+ count = sl->list_count > 0 ? sl->ref_count[0] : 0; -+ for (i = 0; i < count; i++) -+ controls->slice_params[slice].ref_pic_list0[i] = get_dpb_index(&controls->decode_params, &sl->ref_list[0][i]); -+ if (count) -+ fill_weight_factors(&controls->slice_params[slice].pred_weight_table.weight_factors[0], 0, sl); -+ -+ count = sl->list_count > 1 ? sl->ref_count[1] : 0; -+ for (i = 0; i < count; i++) -+ controls->slice_params[slice].ref_pic_list1[i] = get_dpb_index(&controls->decode_params, &sl->ref_list[1][i]); -+ if (count) -+ fill_weight_factors(&controls->slice_params[slice].pred_weight_table.weight_factors[1], 1, sl); -+ -+ if (ctx->start_code == V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B) { -+ ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, nalu_slice_start_code, 3); -+ if (ret) -+ return ret; -+ } -+ -+ ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, buffer, size); -+ if (ret) -+ return ret; -+ -+ controls->slice_params[slice].size = req->output.used - controls->slice_params[slice].start_byte_offset; -+ controls->decode_params.num_slices++; -+ return 0; -+} -+ -+static int v4l2_request_h264_end_frame(AVCodecContext *avctx) -+{ -+ const H264Context *h = avctx->priv_data; -+ return v4l2_request_h264_queue_decode(avctx, !FIELD_PICTURE(h) || !h->first_field); -+} -+ -+static int v4l2_request_h264_set_controls(AVCodecContext *avctx) -+{ -+ V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; -+ int ret; -+ -+ struct v4l2_ext_control control[] = { -+ { .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE, }, -+ { .id = V4L2_CID_MPEG_VIDEO_H264_START_CODE, }, -+ }; -+ struct v4l2_query_ext_ctrl slice_params = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -+ }; -+ -+ ctx->decode_mode = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE); -+ if (ctx->decode_mode != V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED && -+ ctx->decode_mode != V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED) { -+ av_log(avctx, AV_LOG_ERROR, "%s: unsupported decode mode, %d\n", __func__, ctx->decode_mode); -+ return AVERROR(EINVAL); -+ } -+ -+ ctx->start_code = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_MPEG_VIDEO_H264_START_CODE); -+ if (ctx->start_code != V4L2_MPEG_VIDEO_H264_START_CODE_NONE && -+ ctx->start_code != V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B) { -+ av_log(avctx, AV_LOG_ERROR, "%s: unsupported start code, %d\n", __func__, ctx->start_code); -+ return AVERROR(EINVAL); -+ } -+ -+ ret = ff_v4l2_request_query_control(avctx, &slice_params); -+ if (ret) -+ return ret; -+ -+ ctx->max_slices = slice_params.elems; -+ if (ctx->max_slices > MAX_SLICES) { -+ av_log(avctx, AV_LOG_ERROR, "%s: unsupported max slices, %d\n", __func__, ctx->max_slices); -+ return AVERROR(EINVAL); -+ } -+ -+ control[0].value = ctx->decode_mode; -+ control[1].value = ctx->start_code; -+ -+ return ff_v4l2_request_set_controls(avctx, control, FF_ARRAY_ELEMS(control)); -+} -+ -+static int v4l2_request_h264_init(AVCodecContext *avctx) -+{ -+ const H264Context *h = avctx->priv_data; -+ struct v4l2_ctrl_h264_sps sps; -+ struct v4l2_ctrl_h264_pps pps; -+ int ret; -+ -+ struct v4l2_ext_control control[] = { -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, -+ .ptr = &sps, -+ .size = sizeof(sps), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -+ .ptr = &pps, -+ .size = sizeof(pps), -+ }, -+ }; -+ -+ fill_sps(&sps, h); -+ fill_pps(&pps, h); -+ -+ ret = ff_v4l2_request_init(avctx, V4L2_PIX_FMT_H264_SLICE, 4 * 1024 * 1024, control, FF_ARRAY_ELEMS(control)); -+ if (ret) -+ return ret; -+ -+ return v4l2_request_h264_set_controls(avctx); -+} -+ -+const AVHWAccel ff_h264_v4l2request_hwaccel = { -+ .name = "h264_v4l2request", ++const AVHWAccel ff_vp8_v4l2request_hwaccel = { ++ .name = "vp8_v4l2request", + .type = AVMEDIA_TYPE_VIDEO, -+ .id = AV_CODEC_ID_H264, ++ .id = AV_CODEC_ID_VP8, + .pix_fmt = AV_PIX_FMT_DRM_PRIME, -+ .start_frame = v4l2_request_h264_start_frame, -+ .decode_slice = v4l2_request_h264_decode_slice, -+ .end_frame = v4l2_request_h264_end_frame, -+ .frame_priv_data_size = sizeof(V4L2RequestControlsH264), -+ .init = v4l2_request_h264_init, ++ .start_frame = v4l2_request_vp8_start_frame, ++ .decode_slice = v4l2_request_vp8_decode_slice, ++ .end_frame = v4l2_request_vp8_end_frame, ++ .frame_priv_data_size = sizeof(V4L2RequestControlsVP8), ++ .init = v4l2_request_vp8_init, + .uninit = ff_v4l2_request_uninit, -+ .priv_data_size = sizeof(V4L2RequestContextH264), ++ .priv_data_size = sizeof(V4L2RequestContext), + .frame_params = ff_v4l2_request_frame_params, + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; +diff --git a/libavcodec/vp8.c b/libavcodec/vp8.c +index e84fcdeaa1e7..0608d9e4e165 100644 +--- a/libavcodec/vp8.c ++++ b/libavcodec/vp8.c +@@ -175,6 +175,9 @@ static enum AVPixelFormat get_pixel_format(VP8Context *s) + #endif + #if CONFIG_VP8_NVDEC_HWACCEL + AV_PIX_FMT_CUDA, ++#endif ++#if CONFIG_VP8_V4L2REQUEST_HWACCEL ++ AV_PIX_FMT_DRM_PRIME, + #endif + AV_PIX_FMT_YUV420P, + AV_PIX_FMT_NONE, +@@ -198,7 +201,7 @@ int update_dimensions(VP8Context *s, int width, int height, int is_vp7) + return ret; + } + +- if (!s->actually_webp && !is_vp7) { ++ if (!s->actually_webp && !is_vp7 && s->pix_fmt == AV_PIX_FMT_NONE) { + s->pix_fmt = get_pixel_format(s); + if (s->pix_fmt < 0) + return AVERROR(EINVAL); +@@ -2968,6 +2971,9 @@ AVCodec ff_vp8_decoder = { + #endif + #if CONFIG_VP8_NVDEC_HWACCEL + HWACCEL_NVDEC(vp8), ++#endif ++#if CONFIG_VP8_V4L2REQUEST_HWACCEL ++ HWACCEL_V4L2REQUEST(vp8), + #endif + NULL + }, -From 72758190a3d062b64db756c60761187a2b9ce1c9 Mon Sep 17 00:00:00 2001 +From 81d6e95b5f2753737791a8a9561850d4a028ad86 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 05/22] Add V4L2 request API hevc hwaccel +Subject: [PATCH 08/19] Add V4L2 request API hevc hwaccel Signed-off-by: Jernej Skrabec Signed-off-by: Jonas Karlman @@ -2064,7 +2461,7 @@ Signed-off-by: Jonas Karlman create mode 100644 libavcodec/v4l2_request_hevc.c diff --git a/configure b/configure -index 1a7720ebe3be..58abd99335b5 100755 +index a3c724861caa..94476afd5df1 100755 --- a/configure +++ b/configure @@ -2941,6 +2941,8 @@ hevc_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_HEVC" @@ -2076,16 +2473,16 @@ index 1a7720ebe3be..58abd99335b5 100755 hevc_vaapi_hwaccel_deps="vaapi VAPictureParameterBufferHEVC" hevc_vaapi_hwaccel_select="hevc_decoder" hevc_vdpau_hwaccel_deps="vdpau VdpPictureInfoHEVC" -@@ -6572,6 +6574,7 @@ fi +@@ -6574,6 +6576,7 @@ fi check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns check_cc h264_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_H264_SLICE;" +check_cc hevc_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_HEVC_SLICE;" check_cc mpeg2_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_MPEG2_SLICE;" + check_cc vp8_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_VP8_FRAME;" - check_headers sys/videoio.h diff --git a/libavcodec/Makefile b/libavcodec/Makefile -index 9a10a292e377..5d0e1d7dae77 100644 +index c74d2ebfdd23..d6af854daaa6 100644 --- a/libavcodec/Makefile +++ b/libavcodec/Makefile @@ -911,6 +911,7 @@ OBJS-$(CONFIG_HEVC_D3D11VA_HWACCEL) += dxva2_hevc.o @@ -2097,7 +2494,7 @@ index 9a10a292e377..5d0e1d7dae77 100644 OBJS-$(CONFIG_HEVC_VDPAU_HWACCEL) += vdpau_hevc.o OBJS-$(CONFIG_MJPEG_NVDEC_HWACCEL) += nvdec_mjpeg.o diff --git a/libavcodec/hevcdec.c b/libavcodec/hevcdec.c -index 0772608a30e0..d01b7b34bcee 100644 +index 1eaeaf72f145..7e47bd7177e1 100644 --- a/libavcodec/hevcdec.c +++ b/libavcodec/hevcdec.c @@ -372,6 +372,7 @@ static enum AVPixelFormat get_format(HEVCContext *s, const HEVCSPS *sps) @@ -2128,7 +2525,7 @@ index 0772608a30e0..d01b7b34bcee 100644 #endif break; case AV_PIX_FMT_YUV444P: -@@ -3588,6 +3595,9 @@ AVCodec ff_hevc_decoder = { +@@ -3593,6 +3600,9 @@ AVCodec ff_hevc_decoder = { #endif #if CONFIG_HEVC_VIDEOTOOLBOX_HWACCEL HWACCEL_VIDEOTOOLBOX(hevc), @@ -2139,7 +2536,7 @@ index 0772608a30e0..d01b7b34bcee 100644 NULL }, diff --git a/libavcodec/hwaccels.h b/libavcodec/hwaccels.h -index 44e00e79b515..e2f90a5fdd58 100644 +index 14838083ec36..bd75e94f4cae 100644 --- a/libavcodec/hwaccels.h +++ b/libavcodec/hwaccels.h @@ -35,6 +35,7 @@ extern const AVHWAccel ff_hevc_d3d11va_hwaccel; @@ -2690,466 +3087,28 @@ index 000000000000..f72490954653 + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From ebc06b180bfc3c4c6e02cfe2f559e140ce0020e8 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Wed, 22 May 2019 14:46:58 +0200 -Subject: [PATCH 06/22] Add V4L2 request API vp8 hwaccel - -Need to fix the STREAMOFF/STREAMON issue in a proper way. - -Signed-off-by: Boris Brezillon -Signed-off-by: Ezequiel Garcia ---- - configure | 3 + - libavcodec/Makefile | 1 + - libavcodec/hwaccels.h | 1 + - libavcodec/v4l2_request_vp8.c | 180 ++++++++++++++++++++++++++++++++++ - libavcodec/vp8.c | 8 +- - 5 files changed, 192 insertions(+), 1 deletion(-) - create mode 100644 libavcodec/v4l2_request_vp8.c - -diff --git a/configure b/configure -index 58abd99335b5..cbb91c2bca43 100755 ---- a/configure -+++ b/configure -@@ -3003,6 +3003,8 @@ vc1_vdpau_hwaccel_deps="vdpau" - vc1_vdpau_hwaccel_select="vc1_decoder" - vp8_nvdec_hwaccel_deps="nvdec" - vp8_nvdec_hwaccel_select="vp8_decoder" -+vp8_v4l2request_hwaccel_deps="v4l2_request vp8_v4l2_request" -+vp8_v4l2request_hwaccel_select="vp8_decoder" - vp8_vaapi_hwaccel_deps="vaapi" - vp8_vaapi_hwaccel_select="vp8_decoder" - vp9_d3d11va_hwaccel_deps="d3d11va DXVA_PicParams_VP9" -@@ -6576,6 +6578,7 @@ check_func_headers "linux/media.h linux/videodev2.h" v4l2_timeval_to_ns - check_cc h264_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_H264_SLICE;" - check_cc hevc_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_HEVC_SLICE;" - check_cc mpeg2_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_MPEG2_SLICE;" -+check_cc vp8_v4l2_request linux/videodev2.h "int i = V4L2_PIX_FMT_VP8_FRAME;" - - check_headers sys/videoio.h - test_code cc sys/videoio.h "struct v4l2_frmsizeenum vfse; vfse.discrete.width = 0;" && enable_sanitized struct_v4l2_frmivalenum_discrete -diff --git a/libavcodec/Makefile b/libavcodec/Makefile -index 5d0e1d7dae77..d6af854daaa6 100644 ---- a/libavcodec/Makefile -+++ b/libavcodec/Makefile -@@ -940,6 +940,7 @@ OBJS-$(CONFIG_VC1_QSV_HWACCEL) += qsvdec_other.o - OBJS-$(CONFIG_VC1_VAAPI_HWACCEL) += vaapi_vc1.o - OBJS-$(CONFIG_VC1_VDPAU_HWACCEL) += vdpau_vc1.o - OBJS-$(CONFIG_VP8_NVDEC_HWACCEL) += nvdec_vp8.o -+OBJS-$(CONFIG_VP8_V4L2REQUEST_HWACCEL) += v4l2_request_vp8.o - OBJS-$(CONFIG_VP8_VAAPI_HWACCEL) += vaapi_vp8.o - OBJS-$(CONFIG_VP9_D3D11VA_HWACCEL) += dxva2_vp9.o - OBJS-$(CONFIG_VP9_DXVA2_HWACCEL) += dxva2_vp9.o -diff --git a/libavcodec/hwaccels.h b/libavcodec/hwaccels.h -index e2f90a5fdd58..bd75e94f4cae 100644 ---- a/libavcodec/hwaccels.h -+++ b/libavcodec/hwaccels.h -@@ -65,6 +65,7 @@ extern const AVHWAccel ff_vc1_nvdec_hwaccel; - extern const AVHWAccel ff_vc1_vaapi_hwaccel; - extern const AVHWAccel ff_vc1_vdpau_hwaccel; - extern const AVHWAccel ff_vp8_nvdec_hwaccel; -+extern const AVHWAccel ff_vp8_v4l2request_hwaccel; - extern const AVHWAccel ff_vp8_vaapi_hwaccel; - extern const AVHWAccel ff_vp9_d3d11va_hwaccel; - extern const AVHWAccel ff_vp9_d3d11va2_hwaccel; -diff --git a/libavcodec/v4l2_request_vp8.c b/libavcodec/v4l2_request_vp8.c -new file mode 100644 -index 000000000000..7e75ee398a2e ---- /dev/null -+++ b/libavcodec/v4l2_request_vp8.c -@@ -0,0 +1,180 @@ -+/* -+ * This file is part of FFmpeg. -+ * -+ * FFmpeg is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * FFmpeg is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with FFmpeg; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+#include "hwconfig.h" -+#include "v4l2_request.h" -+#include "vp8.h" -+ -+typedef struct V4L2RequestControlsVP8 { -+ struct v4l2_ctrl_vp8_frame_header ctrl; -+} V4L2RequestControlsVP8; -+ -+static int v4l2_request_vp8_start_frame(AVCodecContext *avctx, -+ av_unused const uint8_t *buffer, -+ av_unused uint32_t size) -+{ -+ const VP8Context *s = avctx->priv_data; -+ V4L2RequestControlsVP8 *controls = s->framep[VP56_FRAME_CURRENT]->hwaccel_picture_private; -+ -+ memset(&controls->ctrl, 0, sizeof(controls->ctrl)); -+ return ff_v4l2_request_reset_frame(avctx, s->framep[VP56_FRAME_CURRENT]->tf.f); -+} -+ -+static int v4l2_request_vp8_end_frame(AVCodecContext *avctx) -+{ -+ const VP8Context *s = avctx->priv_data; -+ V4L2RequestControlsVP8 *controls = s->framep[VP56_FRAME_CURRENT]->hwaccel_picture_private; -+ struct v4l2_ext_control control[] = { -+ { -+ .id = V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER, -+ .ptr = &controls->ctrl, -+ .size = sizeof(controls->ctrl), -+ }, -+ }; -+ -+ return ff_v4l2_request_decode_frame(avctx, s->framep[VP56_FRAME_CURRENT]->tf.f, -+ control, FF_ARRAY_ELEMS(control)); -+} -+ -+static int v4l2_request_vp8_decode_slice(AVCodecContext *avctx, -+ const uint8_t *buffer, -+ uint32_t size) -+{ -+ const VP8Context *s = avctx->priv_data; -+ V4L2RequestControlsVP8 *controls = s->framep[VP56_FRAME_CURRENT]->hwaccel_picture_private; -+ struct v4l2_ctrl_vp8_frame_header *hdr = &controls->ctrl; -+ const uint8_t *data = buffer + 3 + 7 * s->keyframe; -+ unsigned int i, j, k; -+ -+ hdr->version = s->profile & 0x3; -+ hdr->width = avctx->width; -+ hdr->height = avctx->height; -+ /* FIXME: set ->xx_scale */ -+ hdr->prob_skip_false = s->prob->mbskip; -+ hdr->prob_intra = s->prob->intra; -+ hdr->prob_gf = s->prob->golden; -+ hdr->prob_last = s->prob->last; -+ hdr->first_part_size = s->header_partition_size; -+ hdr->first_part_header_bits = (8 * (s->coder_state_at_header_end.input - data) - -+ s->coder_state_at_header_end.bit_count - 8); -+ hdr->num_dct_parts = s->num_coeff_partitions; -+ for (i = 0; i < 8; i++) -+ hdr->dct_part_sizes[i] = s->coeff_partition_size[i]; -+ -+ hdr->coder_state.range = s->coder_state_at_header_end.range; -+ hdr->coder_state.value = s->coder_state_at_header_end.value; -+ hdr->coder_state.bit_count = s->coder_state_at_header_end.bit_count; -+ if (s->framep[VP56_FRAME_PREVIOUS]) -+ hdr->last_frame_ts = ff_v4l2_request_get_capture_timestamp(s->framep[VP56_FRAME_PREVIOUS]->tf.f); -+ if (s->framep[VP56_FRAME_GOLDEN]) -+ hdr->golden_frame_ts = ff_v4l2_request_get_capture_timestamp(s->framep[VP56_FRAME_GOLDEN]->tf.f); -+ if (s->framep[VP56_FRAME_GOLDEN2]) -+ hdr->alt_frame_ts = ff_v4l2_request_get_capture_timestamp(s->framep[VP56_FRAME_GOLDEN2]->tf.f); -+ hdr->flags |= s->invisible ? 0 : V4L2_VP8_FRAME_HEADER_FLAG_SHOW_FRAME; -+ hdr->flags |= s->mbskip_enabled ? V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF : 0; -+ hdr->flags |= (s->profile & 0x4) ? V4L2_VP8_FRAME_HEADER_FLAG_EXPERIMENTAL : 0; -+ hdr->flags |= s->keyframe ? V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME : 0; -+ hdr->flags |= s->sign_bias[VP56_FRAME_GOLDEN] ? V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN : 0; -+ hdr->flags |= s->sign_bias[VP56_FRAME_GOLDEN2] ? V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT : 0; -+ hdr->segment_header.flags |= s->segmentation.enabled ? V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED : 0; -+ hdr->segment_header.flags |= s->segmentation.update_map ? V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP : 0; -+ hdr->segment_header.flags |= s->segmentation.update_feature_data ? V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_FEATURE_DATA : 0; -+ hdr->segment_header.flags |= s->segmentation.absolute_vals ? 0 : V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE; -+ for (i = 0; i < 4; i++) { -+ hdr->segment_header.quant_update[i] = s->segmentation.base_quant[i]; -+ hdr->segment_header.lf_update[i] = s->segmentation.filter_level[i]; -+ } -+ -+ for (i = 0; i < 3; i++) -+ hdr->segment_header.segment_probs[i] = s->prob->segmentid[i]; -+ -+ hdr->lf_header.level = s->filter.level; -+ hdr->lf_header.sharpness_level = s->filter.sharpness; -+ hdr->lf_header.flags |= s->lf_delta.enabled ? V4L2_VP8_LF_HEADER_ADJ_ENABLE : 0; -+ hdr->lf_header.flags |= s->lf_delta.update ? V4L2_VP8_LF_HEADER_DELTA_UPDATE : 0; -+ hdr->lf_header.flags |= s->filter.simple ? V4L2_VP8_LF_FILTER_TYPE_SIMPLE : 0; -+ for (i = 0; i < 4; i++) { -+ hdr->lf_header.ref_frm_delta[i] = s->lf_delta.ref[i]; -+ hdr->lf_header.mb_mode_delta[i] = s->lf_delta.mode[i + MODE_I4x4]; -+ } -+ -+ // Probabilites -+ if (s->keyframe) { -+ static const uint8_t keyframe_y_mode_probs[4] = { -+ 145, 156, 163, 128 -+ }; -+ static const uint8_t keyframe_uv_mode_probs[3] = { -+ 142, 114, 183 -+ }; -+ -+ memcpy(hdr->entropy_header.y_mode_probs, keyframe_y_mode_probs, 4); -+ memcpy(hdr->entropy_header.uv_mode_probs, keyframe_uv_mode_probs, 3); -+ } else { -+ for (i = 0; i < 4; i++) -+ hdr->entropy_header.y_mode_probs[i] = s->prob->pred16x16[i]; -+ for (i = 0; i < 3; i++) -+ hdr->entropy_header.uv_mode_probs[i] = s->prob->pred8x8c[i]; -+ } -+ for (i = 0; i < 2; i++) -+ for (j = 0; j < 19; j++) -+ hdr->entropy_header.mv_probs[i][j] = s->prob->mvc[i][j]; -+ -+ for (i = 0; i < 4; i++) { -+ for (j = 0; j < 8; j++) { -+ static const int coeff_bands_inverse[8] = { -+ 0, 1, 2, 3, 5, 6, 4, 15 -+ }; -+ int coeff_pos = coeff_bands_inverse[j]; -+ -+ for (k = 0; k < 3; k++) { -+ memcpy(hdr->entropy_header.coeff_probs[i][j][k], -+ s->prob->token[i][coeff_pos][k], 11); -+ } -+ } -+ } -+ -+ hdr->quant_header.y_ac_qi = s->quant.yac_qi; -+ hdr->quant_header.y_dc_delta = s->quant.ydc_delta; -+ hdr->quant_header.y2_dc_delta = s->quant.y2dc_delta; -+ hdr->quant_header.y2_ac_delta = s->quant.y2ac_delta; -+ hdr->quant_header.uv_dc_delta = s->quant.uvdc_delta; -+ hdr->quant_header.uv_ac_delta = s->quant.uvac_delta; -+ -+ return ff_v4l2_request_append_output_buffer(avctx, s->framep[VP56_FRAME_CURRENT]->tf.f, buffer, size); -+} -+ -+static int v4l2_request_vp8_init(AVCodecContext *avctx) -+{ -+ return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_VP8_FRAME, 2 * 1024 * 1024, NULL, 0); -+} -+ -+const AVHWAccel ff_vp8_v4l2request_hwaccel = { -+ .name = "vp8_v4l2request", -+ .type = AVMEDIA_TYPE_VIDEO, -+ .id = AV_CODEC_ID_VP8, -+ .pix_fmt = AV_PIX_FMT_DRM_PRIME, -+ .start_frame = v4l2_request_vp8_start_frame, -+ .decode_slice = v4l2_request_vp8_decode_slice, -+ .end_frame = v4l2_request_vp8_end_frame, -+ .frame_priv_data_size = sizeof(V4L2RequestControlsVP8), -+ .init = v4l2_request_vp8_init, -+ .uninit = ff_v4l2_request_uninit, -+ .priv_data_size = sizeof(V4L2RequestContext), -+ .frame_params = ff_v4l2_request_frame_params, -+ .caps_internal = HWACCEL_CAP_ASYNC_SAFE, -+}; -diff --git a/libavcodec/vp8.c b/libavcodec/vp8.c -index bab4223aca11..0e1edb46fb20 100644 ---- a/libavcodec/vp8.c -+++ b/libavcodec/vp8.c -@@ -175,6 +175,9 @@ static enum AVPixelFormat get_pixel_format(VP8Context *s) - #endif - #if CONFIG_VP8_NVDEC_HWACCEL - AV_PIX_FMT_CUDA, -+#endif -+#if CONFIG_VP8_V4L2REQUEST_HWACCEL -+ AV_PIX_FMT_DRM_PRIME, - #endif - AV_PIX_FMT_YUV420P, - AV_PIX_FMT_NONE, -@@ -198,7 +201,7 @@ int update_dimensions(VP8Context *s, int width, int height, int is_vp7) - return ret; - } - -- if (!s->actually_webp && !is_vp7) { -+ if (!s->actually_webp && !is_vp7 && s->pix_fmt == AV_PIX_FMT_NONE) { - s->pix_fmt = get_pixel_format(s); - if (s->pix_fmt < 0) - return AVERROR(EINVAL); -@@ -2968,6 +2971,9 @@ AVCodec ff_vp8_decoder = { - #endif - #if CONFIG_VP8_NVDEC_HWACCEL - HWACCEL_NVDEC(vp8), -+#endif -+#if CONFIG_VP8_V4L2REQUEST_HWACCEL -+ HWACCEL_V4L2REQUEST(vp8), - #endif - NULL - }, - -From cf21ba63945bf6a0a60616ceb0a000e42d02f044 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Wed, 20 Feb 2019 11:18:00 -0300 -Subject: [PATCH 07/22] avcodec/h264: parse idr_pic_id - -Signed-off-by: Ezequiel Garcia ---- - libavcodec/h264_slice.c | 2 +- - libavcodec/h264dec.h | 2 ++ - libavcodec/v4l2_request_h264.c | 2 +- - 3 files changed, 4 insertions(+), 2 deletions(-) - -diff --git a/libavcodec/h264_slice.c b/libavcodec/h264_slice.c -index 3ae11ac8a711..96e8edd10289 100644 ---- a/libavcodec/h264_slice.c -+++ b/libavcodec/h264_slice.c -@@ -1822,7 +1822,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, - } - - if (nal->type == H264_NAL_IDR_SLICE) -- get_ue_golomb_long(&sl->gb); /* idr_pic_id */ -+ sl->idr_pic_id = get_ue_golomb_long(&sl->gb); - - if (sps->poc_type == 0) { - sl->poc_lsb = get_bits(&sl->gb, sps->log2_max_poc_lsb); -diff --git a/libavcodec/h264dec.h b/libavcodec/h264dec.h -index a419615124b2..aebc5ed2f613 100644 ---- a/libavcodec/h264dec.h -+++ b/libavcodec/h264dec.h -@@ -190,6 +190,8 @@ typedef struct H264SliceContext { - int slice_type_nos; ///< S free slice type (SI/SP are remapped to I/P) - int slice_type_fixed; - -+ int idr_pic_id; -+ - int qscale; - int chroma_qp[2]; // QPc - int qp_thresh; ///< QP threshold to skip loopfilter -diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c -index 94b9aca8ad45..9382e573b40b 100644 ---- a/libavcodec/v4l2_request_h264.c -+++ b/libavcodec/v4l2_request_h264.c -@@ -303,7 +303,7 @@ static int v4l2_request_h264_decode_slice(AVCodecContext *avctx, const uint8_t * - .pic_parameter_set_id = sl->pps_id, - .colour_plane_id = 0, /* what is this? */ - .frame_num = h->poc.frame_num, -- .idr_pic_id = 0, /* what is this? */ -+ .idr_pic_id = sl->idr_pic_id, - .pic_order_cnt_lsb = sl->poc_lsb, - .delta_pic_order_cnt_bottom = sl->delta_poc_bottom, - .delta_pic_order_cnt0 = sl->delta_poc[0], - -From 13d2f3430db4d83ce30c921bf2b3ee44e1d6ec55 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Wed, 22 May 2019 14:44:22 +0200 -Subject: [PATCH 08/22] avcodec/h264: parse ref_pic_marking_size_in_bits and - pic_order_cnt_bit_size - -Signed-off-by: Boris Brezillon ---- - libavcodec/h264_slice.c | 6 +++++- - libavcodec/h264dec.h | 2 ++ - libavcodec/v4l2_request_h264.c | 4 ++-- - 3 files changed, 9 insertions(+), 3 deletions(-) - -diff --git a/libavcodec/h264_slice.c b/libavcodec/h264_slice.c -index 96e8edd10289..c3896cfd90ab 100644 ---- a/libavcodec/h264_slice.c -+++ b/libavcodec/h264_slice.c -@@ -1740,7 +1740,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, - unsigned int slice_type, tmp, i; - int field_pic_flag, bottom_field_flag; - int first_slice = sl == h->slice_ctx && !h->current_slice; -- int picture_structure; -+ int picture_structure, pos; - - if (first_slice) - av_assert0(!h->setup_finished); -@@ -1824,6 +1824,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, - if (nal->type == H264_NAL_IDR_SLICE) - sl->idr_pic_id = get_ue_golomb_long(&sl->gb); - -+ pos = sl->gb.index; - if (sps->poc_type == 0) { - sl->poc_lsb = get_bits(&sl->gb, sps->log2_max_poc_lsb); - -@@ -1837,6 +1838,7 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, - if (pps->pic_order_present == 1 && picture_structure == PICT_FRAME) - sl->delta_poc[1] = get_se_golomb(&sl->gb); - } -+ sl->pic_order_cnt_bit_size = sl->gb.index - pos; - - sl->redundant_pic_count = 0; - if (pps->redundant_pic_cnt_present) -@@ -1876,9 +1878,11 @@ static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl, - - sl->explicit_ref_marking = 0; - if (nal->ref_idc) { -+ int bit_pos = sl->gb.index; - ret = ff_h264_decode_ref_pic_marking(sl, &sl->gb, nal, h->avctx); - if (ret < 0 && (h->avctx->err_recognition & AV_EF_EXPLODE)) - return AVERROR_INVALIDDATA; -+ sl->ref_pic_marking_size_in_bits = sl->gb.index - bit_pos; - } - - if (sl->slice_type_nos != AV_PICTURE_TYPE_I && pps->cabac) { -diff --git a/libavcodec/h264dec.h b/libavcodec/h264dec.h -index aebc5ed2f613..b3dcd6e7da30 100644 ---- a/libavcodec/h264dec.h -+++ b/libavcodec/h264dec.h -@@ -330,11 +330,13 @@ typedef struct H264SliceContext { - MMCO mmco[MAX_MMCO_COUNT]; - int nb_mmco; - int explicit_ref_marking; -+ int ref_pic_marking_size_in_bits; - - int frame_num; - int poc_lsb; - int delta_poc_bottom; - int delta_poc[2]; -+ int pic_order_cnt_bit_size; - int curr_pic_num; - int max_pic_num; - } H264SliceContext; -diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c -index 9382e573b40b..bdaeb67d2618 100644 ---- a/libavcodec/v4l2_request_h264.c -+++ b/libavcodec/v4l2_request_h264.c -@@ -311,9 +311,9 @@ static int v4l2_request_h264_decode_slice(AVCodecContext *avctx, const uint8_t * - .redundant_pic_cnt = sl->redundant_pic_count, - - /* Size in bits of dec_ref_pic_marking() syntax element. */ -- .dec_ref_pic_marking_bit_size = 0, -+ .dec_ref_pic_marking_bit_size = sl->ref_pic_marking_size_in_bits, - /* Size in bits of pic order count syntax. */ -- .pic_order_cnt_bit_size = 0, -+ .pic_order_cnt_bit_size = sl->pic_order_cnt_bit_size, - - .cabac_init_idc = sl->cabac_init_idc, - .slice_qp_delta = sl->qscale - pps->init_qp, - -From 5ba945f011277dee7b4fb36af60810fd9b401f79 Mon Sep 17 00:00:00 2001 +From 298f65eb9d5d1bae35e5940e27641b1674af884d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 14 Feb 2019 23:20:05 +0100 -Subject: [PATCH 09/22] Add and use private linux headers for V4L2 request API - ctrls +Subject: [PATCH 09/19] Add and use private linux v5.13 headers for V4L2 + request API ctrls Signed-off-by: Jernej Skrabec +Signed-off-by: Jonas Karlman --- - configure | 6 +- - libavcodec/h264-ctrls.h | 210 +++++++++++++++++++++++++++++++ + configure | 4 +- libavcodec/hevc-ctrls.h | 212 ++++++++++++++++++++++++++++++++ libavcodec/mpeg2-ctrls.h | 82 ++++++++++++ - libavcodec/v4l2_request_h264.c | 1 + libavcodec/v4l2_request_hevc.c | 1 + libavcodec/v4l2_request_mpeg2.c | 1 + - libavcodec/v4l2_request_vp8.c | 1 + - libavcodec/vp8-ctrls.h | 112 +++++++++++++++++ - 9 files changed, 623 insertions(+), 3 deletions(-) - create mode 100644 libavcodec/h264-ctrls.h + 5 files changed, 298 insertions(+), 2 deletions(-) create mode 100644 libavcodec/hevc-ctrls.h create mode 100644 libavcodec/mpeg2-ctrls.h - create mode 100644 libavcodec/vp8-ctrls.h diff --git a/configure b/configure -index cbb91c2bca43..623012757c60 100755 +index 94476afd5df1..b24fb36a26c7 100755 --- a/configure +++ b/configure -@@ -2925,7 +2925,7 @@ h264_dxva2_hwaccel_deps="dxva2" - h264_dxva2_hwaccel_select="h264_decoder" - h264_nvdec_hwaccel_deps="nvdec" - h264_nvdec_hwaccel_select="h264_decoder" --h264_v4l2request_hwaccel_deps="v4l2_request h264_v4l2_request" -+h264_v4l2request_hwaccel_deps="v4l2_request" - h264_v4l2request_hwaccel_select="h264_decoder" - h264_vaapi_hwaccel_deps="vaapi" - h264_vaapi_hwaccel_select="h264_decoder" @@ -2941,7 +2941,7 @@ hevc_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_HEVC" hevc_dxva2_hwaccel_select="hevc_decoder" hevc_nvdec_hwaccel_deps="nvdec" @@ -3159,234 +3118,18 @@ index cbb91c2bca43..623012757c60 100755 hevc_v4l2request_hwaccel_select="hevc_decoder" hevc_vaapi_hwaccel_deps="vaapi VAPictureParameterBufferHEVC" hevc_vaapi_hwaccel_select="hevc_decoder" -@@ -3003,7 +3003,7 @@ vc1_vdpau_hwaccel_deps="vdpau" - vc1_vdpau_hwaccel_select="vc1_decoder" - vp8_nvdec_hwaccel_deps="nvdec" - vp8_nvdec_hwaccel_select="vp8_decoder" --vp8_v4l2request_hwaccel_deps="v4l2_request vp8_v4l2_request" -+vp8_v4l2request_hwaccel_deps="v4l2_request" - vp8_v4l2request_hwaccel_select="vp8_decoder" - vp8_vaapi_hwaccel_deps="vaapi" - vp8_vaapi_hwaccel_select="vp8_decoder" -diff --git a/libavcodec/h264-ctrls.h b/libavcodec/h264-ctrls.h -new file mode 100644 -index 000000000000..e877bf1d537c ---- /dev/null -+++ b/libavcodec/h264-ctrls.h -@@ -0,0 +1,210 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the H.264 state controls for use with stateless H.264 -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _H264_CTRLS_H_ -+#define _H264_CTRLS_H_ -+ -+#include -+ -+/* Our pixel format isn't stable at the moment */ -+#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ -+ -+/* -+ * This is put insanely high to avoid conflicting with controls that -+ * would be added during the phase where those controls are not -+ * stable. It should be fixed eventually. -+ */ -+#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) -+#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) -+#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) -+#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) -+#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) -+#define V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (V4L2_CID_MPEG_BASE+1005) -+#define V4L2_CID_MPEG_VIDEO_H264_START_CODE (V4L2_CID_MPEG_BASE+1006) -+ -+/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_H264_SPS 0x0110 -+#define V4L2_CTRL_TYPE_H264_PPS 0x0111 -+#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 -+#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 -+#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 -+ -+enum v4l2_mpeg_video_h264_decode_mode { -+ V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED, -+ V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED, -+}; -+ -+enum v4l2_mpeg_video_h264_start_code { -+ V4L2_MPEG_VIDEO_H264_START_CODE_NONE, -+ V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B, -+}; -+ -+#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 -+#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 -+#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 -+#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 -+#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 -+#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 -+ -+#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 -+#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 -+#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 -+#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 -+#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 -+#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 -+#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 -+ -+struct v4l2_ctrl_h264_sps { -+ __u8 profile_idc; -+ __u8 constraint_set_flags; -+ __u8 level_idc; -+ __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; -+ __u8 bit_depth_luma_minus8; -+ __u8 bit_depth_chroma_minus8; -+ __u8 log2_max_frame_num_minus4; -+ __u8 pic_order_cnt_type; -+ __u8 log2_max_pic_order_cnt_lsb_minus4; -+ __u8 max_num_ref_frames; -+ __u8 num_ref_frames_in_pic_order_cnt_cycle; -+ __s32 offset_for_ref_frame[255]; -+ __s32 offset_for_non_ref_pic; -+ __s32 offset_for_top_to_bottom_field; -+ __u16 pic_width_in_mbs_minus1; -+ __u16 pic_height_in_map_units_minus1; -+ __u32 flags; -+}; -+ -+#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 -+#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 -+#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 -+#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 -+#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 -+#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 -+#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 -+#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 -+ -+struct v4l2_ctrl_h264_pps { -+ __u8 pic_parameter_set_id; -+ __u8 seq_parameter_set_id; -+ __u8 num_slice_groups_minus1; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; -+ __u8 weighted_bipred_idc; -+ __s8 pic_init_qp_minus26; -+ __s8 pic_init_qs_minus26; -+ __s8 chroma_qp_index_offset; -+ __s8 second_chroma_qp_index_offset; -+ __u16 flags; -+}; -+ -+struct v4l2_ctrl_h264_scaling_matrix { -+ __u8 scaling_list_4x4[6][16]; -+ __u8 scaling_list_8x8[6][64]; -+}; -+ -+struct v4l2_h264_weight_factors { -+ __s16 luma_weight[32]; -+ __s16 luma_offset[32]; -+ __s16 chroma_weight[32][2]; -+ __s16 chroma_offset[32][2]; -+}; -+ -+struct v4l2_h264_pred_weight_table { -+ __u16 luma_log2_weight_denom; -+ __u16 chroma_log2_weight_denom; -+ struct v4l2_h264_weight_factors weight_factors[2]; -+}; -+ -+#define V4L2_H264_SLICE_TYPE_P 0 -+#define V4L2_H264_SLICE_TYPE_B 1 -+#define V4L2_H264_SLICE_TYPE_I 2 -+#define V4L2_H264_SLICE_TYPE_SP 3 -+#define V4L2_H264_SLICE_TYPE_SI 4 -+ -+#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 -+#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 -+#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 -+#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 -+ -+struct v4l2_ctrl_h264_slice_params { -+ /* Size in bytes, including header */ -+ __u32 size; -+ -+ /* Offset in bytes to the start of slice in the OUTPUT buffer. */ -+ __u32 start_byte_offset; -+ -+ /* Offset in bits to slice_data() from the beginning of this slice. */ -+ __u32 header_bit_size; -+ -+ __u16 first_mb_in_slice; -+ __u8 slice_type; -+ __u8 pic_parameter_set_id; -+ __u8 colour_plane_id; -+ __u8 redundant_pic_cnt; -+ __u16 frame_num; -+ __u16 idr_pic_id; -+ __u16 pic_order_cnt_lsb; -+ __s32 delta_pic_order_cnt_bottom; -+ __s32 delta_pic_order_cnt0; -+ __s32 delta_pic_order_cnt1; -+ -+ struct v4l2_h264_pred_weight_table pred_weight_table; -+ /* Size in bits of dec_ref_pic_marking() syntax element. */ -+ __u32 dec_ref_pic_marking_bit_size; -+ /* Size in bits of pic order count syntax. */ -+ __u32 pic_order_cnt_bit_size; -+ -+ __u8 cabac_init_idc; -+ __s8 slice_qp_delta; -+ __s8 slice_qs_delta; -+ __u8 disable_deblocking_filter_idc; -+ __s8 slice_alpha_c0_offset_div2; -+ __s8 slice_beta_offset_div2; -+ __u8 num_ref_idx_l0_active_minus1; -+ __u8 num_ref_idx_l1_active_minus1; -+ __u32 slice_group_change_cycle; -+ -+ /* -+ * Entries on each list are indices into -+ * v4l2_ctrl_h264_decode_params.dpb[]. -+ */ -+ __u8 ref_pic_list0[32]; -+ __u8 ref_pic_list1[32]; -+ -+ __u32 flags; -+}; -+ -+#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 -+#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 -+#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 -+ -+struct v4l2_h264_dpb_entry { -+ __u64 reference_ts; -+ __u16 frame_num; -+ __u16 pic_num; -+ /* Note that field is indicated by v4l2_buffer.field */ -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ -+}; -+ -+#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 -+ -+struct v4l2_ctrl_h264_decode_params { -+ struct v4l2_h264_dpb_entry dpb[16]; -+ __u16 num_slices; -+ __u16 nal_ref_idc; -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ -+}; -+ -+#endif +@@ -2971,7 +2971,7 @@ mpeg2_dxva2_hwaccel_deps="dxva2" + mpeg2_dxva2_hwaccel_select="mpeg2video_decoder" + mpeg2_nvdec_hwaccel_deps="nvdec" + mpeg2_nvdec_hwaccel_select="mpeg2video_decoder" +-mpeg2_v4l2request_hwaccel_deps="v4l2_request mpeg2_v4l2_request" ++mpeg2_v4l2request_hwaccel_deps="v4l2_request" + mpeg2_v4l2request_hwaccel_select="mpeg2video_decoder" + mpeg2_vaapi_hwaccel_deps="vaapi" + mpeg2_vaapi_hwaccel_select="mpeg2video_decoder" diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h new file mode 100644 -index 000000000000..1009cf0891cc +index 000000000000..b4cb2ef02f17 --- /dev/null +++ b/libavcodec/hevc-ctrls.h @@ -0,0 +1,212 @@ @@ -3408,11 +3151,11 @@ index 000000000000..1009cf0891cc +/* The pixel format isn't stable at the moment and will likely be renamed. */ +#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ + -+#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) -+#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_MPEG_BASE + 1015) -+#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_MPEG_BASE + 1016) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) ++#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) ++#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) + +/* enum v4l2_ctrl_type type values */ +#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 @@ -3604,7 +3347,7 @@ index 000000000000..1009cf0891cc +#endif diff --git a/libavcodec/mpeg2-ctrls.h b/libavcodec/mpeg2-ctrls.h new file mode 100644 -index 000000000000..6601455b3d5e +index 000000000000..2a4ae6701166 --- /dev/null +++ b/libavcodec/mpeg2-ctrls.h @@ -0,0 +1,82 @@ @@ -3621,8 +3364,8 @@ index 000000000000..6601455b3d5e +#ifndef _MPEG2_CTRLS_H_ +#define _MPEG2_CTRLS_H_ + -+#define V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS (V4L2_CID_MPEG_BASE+250) -+#define V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION (V4L2_CID_MPEG_BASE+251) ++#define V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS (V4L2_CID_CODEC_BASE+250) ++#define V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION (V4L2_CID_CODEC_BASE+251) + +/* enum v4l2_ctrl_type type values */ +#define V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS 0x0103 @@ -3690,18 +3433,6 @@ index 000000000000..6601455b3d5e +}; + +#endif -diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c -index bdaeb67d2618..0254716e5239 100644 ---- a/libavcodec/v4l2_request_h264.c -+++ b/libavcodec/v4l2_request_h264.c -@@ -19,6 +19,7 @@ - #include "h264dec.h" - #include "hwconfig.h" - #include "v4l2_request.h" -+#include "h264-ctrls.h" - - typedef struct V4L2RequestControlsH264 { - struct v4l2_ctrl_h264_sps sps; diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c index f72490954653..c16f8a868e38 100644 --- a/libavcodec/v4l2_request_hevc.c @@ -3726,774 +3457,11 @@ index 88d86cc4c23f..bc251a6fd2c4 100644 typedef struct V4L2RequestControlsMPEG2 { struct v4l2_ctrl_mpeg2_slice_params slice_params; -diff --git a/libavcodec/v4l2_request_vp8.c b/libavcodec/v4l2_request_vp8.c -index 7e75ee398a2e..ea2c55fa2f53 100644 ---- a/libavcodec/v4l2_request_vp8.c -+++ b/libavcodec/v4l2_request_vp8.c -@@ -19,6 +19,7 @@ - #include "hwconfig.h" - #include "v4l2_request.h" - #include "vp8.h" -+#include "vp8-ctrls.h" - - typedef struct V4L2RequestControlsVP8 { - struct v4l2_ctrl_vp8_frame_header ctrl; -diff --git a/libavcodec/vp8-ctrls.h b/libavcodec/vp8-ctrls.h -new file mode 100644 -index 000000000000..53cba826e482 ---- /dev/null -+++ b/libavcodec/vp8-ctrls.h -@@ -0,0 +1,112 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the VP8 state controls for use with stateless VP8 -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _VP8_CTRLS_H_ -+#define _VP8_CTRLS_H_ -+ -+#include -+ -+#define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') -+ -+#define V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER (V4L2_CID_MPEG_BASE + 2000) -+#define V4L2_CTRL_TYPE_VP8_FRAME_HEADER 0x301 -+ -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED 0x01 -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP 0x02 -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_FEATURE_DATA 0x04 -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE 0x08 -+ -+struct v4l2_vp8_segment_header { -+ __s8 quant_update[4]; -+ __s8 lf_update[4]; -+ __u8 segment_probs[3]; -+ __u8 padding; -+ __u32 flags; -+}; -+ -+#define V4L2_VP8_LF_HEADER_ADJ_ENABLE 0x01 -+#define V4L2_VP8_LF_HEADER_DELTA_UPDATE 0x02 -+#define V4L2_VP8_LF_FILTER_TYPE_SIMPLE 0x04 -+struct v4l2_vp8_loopfilter_header { -+ __s8 ref_frm_delta[4]; -+ __s8 mb_mode_delta[4]; -+ __u8 sharpness_level; -+ __u8 level; -+ __u16 padding; -+ __u32 flags; -+}; -+ -+struct v4l2_vp8_quantization_header { -+ __u8 y_ac_qi; -+ __s8 y_dc_delta; -+ __s8 y2_dc_delta; -+ __s8 y2_ac_delta; -+ __s8 uv_dc_delta; -+ __s8 uv_ac_delta; -+ __u16 padding; -+}; -+ -+struct v4l2_vp8_entropy_header { -+ __u8 coeff_probs[4][8][3][11]; -+ __u8 y_mode_probs[4]; -+ __u8 uv_mode_probs[3]; -+ __u8 mv_probs[2][19]; -+ __u8 padding[3]; -+}; -+ -+struct v4l2_vp8_entropy_coder_state { -+ __u8 range; -+ __u8 value; -+ __u8 bit_count; -+ __u8 padding; -+}; -+ -+#define V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME 0x01 -+#define V4L2_VP8_FRAME_HEADER_FLAG_EXPERIMENTAL 0x02 -+#define V4L2_VP8_FRAME_HEADER_FLAG_SHOW_FRAME 0x04 -+#define V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF 0x08 -+#define V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN 0x10 -+#define V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT 0x20 -+ -+#define VP8_FRAME_IS_KEY_FRAME(hdr) \ -+ (!!((hdr)->flags & V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME)) -+ -+struct v4l2_ctrl_vp8_frame_header { -+ struct v4l2_vp8_segment_header segment_header; -+ struct v4l2_vp8_loopfilter_header lf_header; -+ struct v4l2_vp8_quantization_header quant_header; -+ struct v4l2_vp8_entropy_header entropy_header; -+ struct v4l2_vp8_entropy_coder_state coder_state; -+ -+ __u16 width; -+ __u16 height; -+ -+ __u8 horizontal_scale; -+ __u8 vertical_scale; -+ -+ __u8 version; -+ __u8 prob_skip_false; -+ __u8 prob_intra; -+ __u8 prob_last; -+ __u8 prob_gf; -+ __u8 num_dct_parts; -+ -+ __u32 first_part_size; -+ __u32 first_part_header_bits; -+ __u32 dct_part_sizes[8]; -+ -+ __u64 last_frame_ts; -+ __u64 golden_frame_ts; -+ __u64 alt_frame_ts; -+ -+ __u64 flags; -+}; -+ -+#endif -From 77c91a97c87424c1d6bff888bc8562a9b6697aa2 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 2 May 2020 11:00:26 +0000 -Subject: [PATCH 10/22] Update to v5.7 private linux headers - ---- - libavcodec/h264-ctrls.h | 2 ++ - libavcodec/v4l2_request_h264.c | 8 +++++++- - 2 files changed, 9 insertions(+), 1 deletion(-) - -diff --git a/libavcodec/h264-ctrls.h b/libavcodec/h264-ctrls.h -index e877bf1d537c..1c6ff7d63bca 100644 ---- a/libavcodec/h264-ctrls.h -+++ b/libavcodec/h264-ctrls.h -@@ -185,6 +185,8 @@ struct v4l2_ctrl_h264_slice_params { - #define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 - #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 - #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 -+#define V4L2_H264_DPB_ENTRY_FLAG_FIELD 0x08 -+#define V4L2_H264_DPB_ENTRY_FLAG_BOTTOM_FIELD 0x10 - - struct v4l2_h264_dpb_entry { - __u64 reference_ts; -diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c -index 0254716e5239..d28ed07da3b4 100644 ---- a/libavcodec/v4l2_request_h264.c -+++ b/libavcodec/v4l2_request_h264.c -@@ -67,8 +67,14 @@ static void fill_dpb_entry(struct v4l2_h264_dpb_entry *entry, const H264Picture - entry->frame_num = pic->frame_num; - entry->pic_num = pic->pic_id; - entry->flags = V4L2_H264_DPB_ENTRY_FLAG_VALID; -- if (pic->reference) -+ if (pic->reference) { - entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; -+ if (pic->reference != PICT_FRAME) { -+ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_FIELD; -+ if (pic->reference == PICT_BOTTOM_FIELD) -+ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_BOTTOM_FIELD; -+ } -+ } - if (pic->long_ref) - entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM; - if (pic->field_poc[0] != INT_MAX) - -From 40407184ac1cd48d35acc6b0d8bdec48a98c74fb Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 2 May 2020 22:03:42 +0000 -Subject: [PATCH 11/22] Update to v5.8 private linux headers - ---- - libavcodec/h264-ctrls.h | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/libavcodec/h264-ctrls.h b/libavcodec/h264-ctrls.h -index 1c6ff7d63bca..080fd1293c42 100644 ---- a/libavcodec/h264-ctrls.h -+++ b/libavcodec/h264-ctrls.h -@@ -13,6 +13,12 @@ - - #include - -+/* -+ * Maximum DPB size, as specified by section 'A.3.1 Level limits -+ * common to the Baseline, Main, and Extended profiles'. -+ */ -+#define V4L2_H264_NUM_DPB_ENTRIES 16 -+ - /* Our pixel format isn't stable at the moment */ - #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ - -@@ -201,7 +207,7 @@ struct v4l2_h264_dpb_entry { - #define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 - - struct v4l2_ctrl_h264_decode_params { -- struct v4l2_h264_dpb_entry dpb[16]; -+ struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]; - __u16 num_slices; - __u16 nal_ref_idc; - __s32 top_field_order_cnt; - -From 6a151e35d99c430030709b49a6abd36349a65887 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 6 Sep 2020 16:07:13 +0000 -Subject: [PATCH 12/22] Update to v5.10 private linux headers - ---- - libavcodec/h264-ctrls.h | 89 +++++++++------- - libavcodec/v4l2_request_h264.c | 184 ++++++++++++++++----------------- - 2 files changed, 138 insertions(+), 135 deletions(-) - -diff --git a/libavcodec/h264-ctrls.h b/libavcodec/h264-ctrls.h -index 080fd1293c42..ec4799154438 100644 ---- a/libavcodec/h264-ctrls.h -+++ b/libavcodec/h264-ctrls.h -@@ -19,6 +19,8 @@ - */ - #define V4L2_H264_NUM_DPB_ENTRIES 16 - -+#define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES) -+ - /* Our pixel format isn't stable at the moment */ - #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ - -@@ -34,6 +36,7 @@ - #define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) - #define V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (V4L2_CID_MPEG_BASE+1005) - #define V4L2_CID_MPEG_VIDEO_H264_START_CODE (V4L2_CID_MPEG_BASE+1006) -+#define V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS (V4L2_CID_MPEG_BASE+1007) - - /* enum v4l2_ctrl_type type values */ - #define V4L2_CTRL_TYPE_H264_SPS 0x0110 -@@ -41,6 +44,7 @@ - #define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 - #define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 - #define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 -+#define V4L2_CTRL_TYPE_H264_PRED_WEIGHTS 0x0115 - - enum v4l2_mpeg_video_h264_decode_mode { - V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED, -@@ -95,7 +99,7 @@ struct v4l2_ctrl_h264_sps { - #define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 - #define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 - #define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 --#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 -+#define V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT 0x0080 - - struct v4l2_ctrl_h264_pps { - __u8 pic_parameter_set_id; -@@ -123,7 +127,14 @@ struct v4l2_h264_weight_factors { - __s16 chroma_offset[32][2]; - }; - --struct v4l2_h264_pred_weight_table { -+#define V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice) \ -+ ((((pps)->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && \ -+ ((slice)->slice_type == V4L2_H264_SLICE_TYPE_P || \ -+ (slice)->slice_type == V4L2_H264_SLICE_TYPE_SP)) || \ -+ ((pps)->weighted_bipred_idc == 1 && \ -+ (slice)->slice_type == V4L2_H264_SLICE_TYPE_B)) -+ -+struct v4l2_ctrl_h264_pred_weights { - __u16 luma_log2_weight_denom; - __u16 chroma_log2_weight_denom; - struct v4l2_h264_weight_factors weight_factors[2]; -@@ -135,39 +146,29 @@ struct v4l2_h264_pred_weight_table { - #define V4L2_H264_SLICE_TYPE_SP 3 - #define V4L2_H264_SLICE_TYPE_SI 4 - --#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 --#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 --#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 --#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 -+#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x01 -+#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x02 -+ -+#define V4L2_H264_TOP_FIELD_REF 0x1 -+#define V4L2_H264_BOTTOM_FIELD_REF 0x2 -+#define V4L2_H264_FRAME_REF 0x3 -+ -+struct v4l2_h264_reference { -+ __u8 fields; -+ -+ /* Index into v4l2_ctrl_h264_decode_params.dpb[] */ -+ __u8 index; -+}; - - struct v4l2_ctrl_h264_slice_params { -- /* Size in bytes, including header */ -- __u32 size; -- -- /* Offset in bytes to the start of slice in the OUTPUT buffer. */ -- __u32 start_byte_offset; -- - /* Offset in bits to slice_data() from the beginning of this slice. */ - __u32 header_bit_size; - -- __u16 first_mb_in_slice; -+ __u32 first_mb_in_slice; -+ - __u8 slice_type; -- __u8 pic_parameter_set_id; - __u8 colour_plane_id; - __u8 redundant_pic_cnt; -- __u16 frame_num; -- __u16 idr_pic_id; -- __u16 pic_order_cnt_lsb; -- __s32 delta_pic_order_cnt_bottom; -- __s32 delta_pic_order_cnt0; -- __s32 delta_pic_order_cnt1; -- -- struct v4l2_h264_pred_weight_table pred_weight_table; -- /* Size in bits of dec_ref_pic_marking() syntax element. */ -- __u32 dec_ref_pic_marking_bit_size; -- /* Size in bits of pic order count syntax. */ -- __u32 pic_order_cnt_bit_size; -- - __u8 cabac_init_idc; - __s8 slice_qp_delta; - __s8 slice_qs_delta; -@@ -176,14 +177,11 @@ struct v4l2_ctrl_h264_slice_params { - __s8 slice_beta_offset_div2; - __u8 num_ref_idx_l0_active_minus1; - __u8 num_ref_idx_l1_active_minus1; -- __u32 slice_group_change_cycle; - -- /* -- * Entries on each list are indices into -- * v4l2_ctrl_h264_decode_params.dpb[]. -- */ -- __u8 ref_pic_list0[32]; -- __u8 ref_pic_list1[32]; -+ __u8 reserved; -+ -+ struct v4l2_h264_reference ref_pic_list0[V4L2_H264_REF_LIST_LEN]; -+ struct v4l2_h264_reference ref_pic_list1[V4L2_H264_REF_LIST_LEN]; - - __u32 flags; - }; -@@ -192,26 +190,41 @@ struct v4l2_ctrl_h264_slice_params { - #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 - #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 - #define V4L2_H264_DPB_ENTRY_FLAG_FIELD 0x08 --#define V4L2_H264_DPB_ENTRY_FLAG_BOTTOM_FIELD 0x10 - - struct v4l2_h264_dpb_entry { - __u64 reference_ts; -+ __u32 pic_num; - __u16 frame_num; -- __u16 pic_num; -+ __u8 fields; -+ __u8 reserved[5]; - /* Note that field is indicated by v4l2_buffer.field */ - __s32 top_field_order_cnt; - __s32 bottom_field_order_cnt; - __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ - }; - --#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 -+#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 -+#define V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC 0x02 -+#define V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD 0x04 - - struct v4l2_ctrl_h264_decode_params { - struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]; -- __u16 num_slices; - __u16 nal_ref_idc; -+ __u16 frame_num; - __s32 top_field_order_cnt; - __s32 bottom_field_order_cnt; -+ __u16 idr_pic_id; -+ __u16 pic_order_cnt_lsb; -+ __s32 delta_pic_order_cnt_bottom; -+ __s32 delta_pic_order_cnt0; -+ __s32 delta_pic_order_cnt1; -+ /* Size in bits of dec_ref_pic_marking() syntax element. */ -+ __u32 dec_ref_pic_marking_bit_size; -+ /* Size in bits of pic order count syntax. */ -+ __u32 pic_order_cnt_bit_size; -+ __u32 slice_group_change_cycle; -+ -+ __u32 reserved; - __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ - }; - -diff --git a/libavcodec/v4l2_request_h264.c b/libavcodec/v4l2_request_h264.c -index d28ed07da3b4..c9dbaf8c3e34 100644 ---- a/libavcodec/v4l2_request_h264.c -+++ b/libavcodec/v4l2_request_h264.c -@@ -26,15 +26,17 @@ typedef struct V4L2RequestControlsH264 { - struct v4l2_ctrl_h264_pps pps; - struct v4l2_ctrl_h264_scaling_matrix scaling_matrix; - struct v4l2_ctrl_h264_decode_params decode_params; -- struct v4l2_ctrl_h264_slice_params slice_params[MAX_SLICES]; -+ struct v4l2_ctrl_h264_slice_params slice_params; -+ struct v4l2_ctrl_h264_pred_weights pred_weights; -+ int pred_weights_required; - int first_slice; -+ int num_slices; - } V4L2RequestControlsH264; - - typedef struct V4L2RequestContextH264 { - V4L2RequestContext base; - int decode_mode; - int start_code; -- int max_slices; - } V4L2RequestContextH264; - - static uint8_t nalu_slice_start_code[] = { 0x00, 0x00, 0x01 }; -@@ -64,19 +66,16 @@ static void fill_weight_factors(struct v4l2_h264_weight_factors *factors, int li - static void fill_dpb_entry(struct v4l2_h264_dpb_entry *entry, const H264Picture *pic) - { - entry->reference_ts = ff_v4l2_request_get_capture_timestamp(pic->f); -- entry->frame_num = pic->frame_num; - entry->pic_num = pic->pic_id; -+ entry->frame_num = pic->frame_num; -+ entry->fields = pic->reference & V4L2_H264_FRAME_REF; - entry->flags = V4L2_H264_DPB_ENTRY_FLAG_VALID; -- if (pic->reference) { -+ if (entry->fields) - entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; -- if (pic->reference != PICT_FRAME) { -- entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_FIELD; -- if (pic->reference == PICT_BOTTOM_FIELD) -- entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_BOTTOM_FIELD; -- } -- } - if (pic->long_ref) - entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM; -+ if (pic->field_picture) -+ entry->flags |= V4L2_H264_DPB_ENTRY_FLAG_FIELD; - if (pic->field_poc[0] != INT_MAX) - entry->top_field_order_cnt = pic->field_poc[0]; - if (pic->field_poc[1] != INT_MAX) -@@ -103,23 +102,24 @@ static void fill_dpb(struct v4l2_ctrl_h264_decode_params *decode, const H264Cont - } - } - --static uint8_t get_dpb_index(struct v4l2_ctrl_h264_decode_params *decode, const H264Ref *ref) -+static void fill_ref_list(struct v4l2_h264_reference *reference, struct v4l2_ctrl_h264_decode_params *decode, const H264Ref *ref) - { - uint64_t timestamp; - - if (!ref->parent) -- return 0; -+ return; - - timestamp = ff_v4l2_request_get_capture_timestamp(ref->parent->f); - - for (uint8_t i = 0; i < FF_ARRAY_ELEMS(decode->dpb); i++) { - struct v4l2_h264_dpb_entry *entry = &decode->dpb[i]; - if ((entry->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID) && -- entry->reference_ts == timestamp) -- return i; -+ entry->reference_ts == timestamp) { -+ reference->fields = ref->reference & V4L2_H264_FRAME_REF; -+ reference->index = i; -+ return; -+ } - } -- -- return 0; - } - - static void fill_sps(struct v4l2_ctrl_h264_sps *ctrl, const H264Context *h) -@@ -139,13 +139,15 @@ static void fill_sps(struct v4l2_ctrl_h264_sps *ctrl, const H264Context *h) - .log2_max_pic_order_cnt_lsb_minus4 = sps->log2_max_poc_lsb - 4, - .max_num_ref_frames = sps->ref_frame_count, - .num_ref_frames_in_pic_order_cnt_cycle = sps->poc_cycle_length, -- //.offset_for_ref_frame[255] - not required? not set by libva-v4l2-request - copy sps->offset_for_ref_frame - .offset_for_non_ref_pic = sps->offset_for_non_ref_pic, - .offset_for_top_to_bottom_field = sps->offset_for_top_to_bottom_field, - .pic_width_in_mbs_minus1 = h->mb_width - 1, - .pic_height_in_map_units_minus1 = sps->frame_mbs_only_flag ? h->mb_height - 1 : h->mb_height / 2 - 1, - }; - -+ if (sps->poc_cycle_length > 0 && sps->poc_cycle_length <= 255) -+ memcpy(ctrl->offset_for_ref_frame, sps->offset_for_ref_frame, sps->poc_cycle_length * sizeof(ctrl->offset_for_ref_frame[0])); -+ - if (sps->residual_color_transform_flag) - ctrl->flags |= V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE; - if (sps->transform_bypass) -@@ -196,6 +198,9 @@ static void fill_pps(struct v4l2_ctrl_h264_pps *ctrl, const H264Context *h) - ctrl->flags |= V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT; - if (pps->transform_8x8_mode) - ctrl->flags |= V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE; -+ -+ /* FFmpeg always provide a scaling matrix */ -+ ctrl->flags |= V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT; - } - - static int v4l2_request_h264_start_frame(AVCodecContext *avctx, -@@ -205,6 +210,7 @@ static int v4l2_request_h264_start_frame(AVCodecContext *avctx, - const H264Context *h = avctx->priv_data; - const PPS *pps = h->ps.pps; - const SPS *sps = h->ps.sps; -+ const H264SliceContext *sl = &h->slice_ctx[0]; - V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; - - fill_sps(&controls->sps, h); -@@ -222,18 +228,33 @@ static int v4l2_request_h264_start_frame(AVCodecContext *avctx, - } - - controls->decode_params = (struct v4l2_ctrl_h264_decode_params) { -- .num_slices = 0, - .nal_ref_idc = h->nal_ref_idc, -+ .frame_num = h->poc.frame_num, - .top_field_order_cnt = h->cur_pic_ptr->field_poc[0] != INT_MAX ? h->cur_pic_ptr->field_poc[0] : 0, - .bottom_field_order_cnt = h->cur_pic_ptr->field_poc[1] != INT_MAX ? h->cur_pic_ptr->field_poc[1] : 0, -+ .idr_pic_id = sl->idr_pic_id, -+ .pic_order_cnt_lsb = sl->poc_lsb, -+ .delta_pic_order_cnt_bottom = sl->delta_poc_bottom, -+ .delta_pic_order_cnt0 = sl->delta_poc[0], -+ .delta_pic_order_cnt1 = sl->delta_poc[1], -+ /* Size in bits of dec_ref_pic_marking() syntax element. */ -+ .dec_ref_pic_marking_bit_size = sl->ref_pic_marking_size_in_bits, -+ /* Size in bits of pic order count syntax. */ -+ .pic_order_cnt_bit_size = sl->pic_order_cnt_bit_size, -+ .slice_group_change_cycle = 0, /* slice group not supported by FFmpeg */ - }; - - if (h->picture_idr) - controls->decode_params.flags |= V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC; -+ if (FIELD_PICTURE(h)) -+ controls->decode_params.flags |= V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC; -+ if (h->picture_structure == PICT_BOTTOM_FIELD) -+ controls->decode_params.flags |= V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD; - - fill_dpb(&controls->decode_params, h); - - controls->first_slice = !FIELD_PICTURE(h) || h->first_field; -+ controls->num_slices = 0; - - return ff_v4l2_request_reset_frame(avctx, h->cur_pic_ptr->f); - } -@@ -260,22 +281,29 @@ static int v4l2_request_h264_queue_decode(AVCodecContext *avctx, int last_slice) - .ptr = &controls->scaling_matrix, - .size = sizeof(controls->scaling_matrix), - }, -- { -- .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -- .ptr = &controls->slice_params, -- .size = sizeof(controls->slice_params[0]) * FFMAX(FFMIN(controls->decode_params.num_slices, MAX_SLICES), ctx->max_slices), -- }, - { - .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, - .ptr = &controls->decode_params, - .size = sizeof(controls->decode_params), - }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -+ .ptr = &controls->slice_params, -+ .size = sizeof(controls->slice_params), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS, -+ .ptr = &controls->pred_weights, -+ .size = sizeof(controls->pred_weights), -+ }, - }; - -- if (ctx->decode_mode == V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED) -- return ff_v4l2_request_decode_slice(avctx, h->cur_pic_ptr->f, control, FF_ARRAY_ELEMS(control), controls->first_slice, last_slice); -+ if (ctx->decode_mode == V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED) { -+ int count = FF_ARRAY_ELEMS(control) - (controls->pred_weights_required ? 0 : 1); -+ return ff_v4l2_request_decode_slice(avctx, h->cur_pic_ptr->f, control, count, controls->first_slice, last_slice); -+ } - -- return ff_v4l2_request_decode_frame(avctx, h->cur_pic_ptr->f, control, FF_ARRAY_ELEMS(control)); -+ return ff_v4l2_request_decode_frame(avctx, h->cur_pic_ptr->f, control, FF_ARRAY_ELEMS(control) - 2); - } - - static int v4l2_request_h264_decode_slice(AVCodecContext *avctx, const uint8_t *buffer, uint32_t size) -@@ -285,89 +313,72 @@ static int v4l2_request_h264_decode_slice(AVCodecContext *avctx, const uint8_t * - const H264SliceContext *sl = &h->slice_ctx[0]; - V4L2RequestControlsH264 *controls = h->cur_pic_ptr->hwaccel_picture_private; - V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; -- V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)h->cur_pic_ptr->f->data[0]; -- int i, ret, count, slice = FFMIN(controls->decode_params.num_slices, MAX_SLICES - 1); -+ int i, ret, count; - -- if (ctx->decode_mode == V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED && slice) { -+ if (ctx->decode_mode == V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED && controls->num_slices) { - ret = v4l2_request_h264_queue_decode(avctx, 0); - if (ret) - return ret; - - ff_v4l2_request_reset_frame(avctx, h->cur_pic_ptr->f); -- slice = controls->decode_params.num_slices = 0; - controls->first_slice = 0; - } - -- controls->slice_params[slice] = (struct v4l2_ctrl_h264_slice_params) { -- /* Size in bytes, including header */ -- .size = 0, -- .start_byte_offset = req->output.used, -+ if (ctx->start_code == V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B) { -+ ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, nalu_slice_start_code, 3); -+ if (ret) -+ return ret; -+ } -+ -+ ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, buffer, size); -+ if (ret) -+ return ret; -+ -+ if (ctx->decode_mode != V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED) -+ return 0; -+ -+ controls->slice_params = (struct v4l2_ctrl_h264_slice_params) { - /* Offset in bits to slice_data() from the beginning of this slice. */ - .header_bit_size = get_bits_count(&sl->gb), - - .first_mb_in_slice = sl->first_mb_addr, -+ - .slice_type = ff_h264_get_slice_type(sl), -- .pic_parameter_set_id = sl->pps_id, -- .colour_plane_id = 0, /* what is this? */ -- .frame_num = h->poc.frame_num, -- .idr_pic_id = sl->idr_pic_id, -- .pic_order_cnt_lsb = sl->poc_lsb, -- .delta_pic_order_cnt_bottom = sl->delta_poc_bottom, -- .delta_pic_order_cnt0 = sl->delta_poc[0], -- .delta_pic_order_cnt1 = sl->delta_poc[1], -+ .colour_plane_id = 0, /* separate colour plane not supported by FFmpeg */ - .redundant_pic_cnt = sl->redundant_pic_count, -- -- /* Size in bits of dec_ref_pic_marking() syntax element. */ -- .dec_ref_pic_marking_bit_size = sl->ref_pic_marking_size_in_bits, -- /* Size in bits of pic order count syntax. */ -- .pic_order_cnt_bit_size = sl->pic_order_cnt_bit_size, -- - .cabac_init_idc = sl->cabac_init_idc, - .slice_qp_delta = sl->qscale - pps->init_qp, -- .slice_qs_delta = 0, /* XXX not implemented by FFmpeg */ -+ .slice_qs_delta = 0, /* not implemented by FFmpeg */ - .disable_deblocking_filter_idc = sl->deblocking_filter < 2 ? !sl->deblocking_filter : sl->deblocking_filter, - .slice_alpha_c0_offset_div2 = sl->slice_alpha_c0_offset / 2, - .slice_beta_offset_div2 = sl->slice_beta_offset / 2, -- .slice_group_change_cycle = 0, /* what is this? */ -- - .num_ref_idx_l0_active_minus1 = sl->list_count > 0 ? sl->ref_count[0] - 1 : 0, - .num_ref_idx_l1_active_minus1 = sl->list_count > 1 ? sl->ref_count[1] - 1 : 0, - }; - -- if (FIELD_PICTURE(h)) -- controls->slice_params[slice].flags |= V4L2_H264_SLICE_FLAG_FIELD_PIC; -- if (h->picture_structure == PICT_BOTTOM_FIELD) -- controls->slice_params[slice].flags |= V4L2_H264_SLICE_FLAG_BOTTOM_FIELD; - if (sl->slice_type == AV_PICTURE_TYPE_B && sl->direct_spatial_mv_pred) -- controls->slice_params[slice].flags |= V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED; -+ controls->slice_params.flags |= V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED; -+ /* V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH: not implemented by FFmpeg */ - -- controls->slice_params[slice].pred_weight_table.chroma_log2_weight_denom = sl->pwt.chroma_log2_weight_denom; -- controls->slice_params[slice].pred_weight_table.luma_log2_weight_denom = sl->pwt.luma_log2_weight_denom; -+ controls->pred_weights_required = V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(&controls->pps, &controls->slice_params); -+ if (controls->pred_weights_required) { -+ controls->pred_weights.chroma_log2_weight_denom = sl->pwt.chroma_log2_weight_denom; -+ controls->pred_weights.luma_log2_weight_denom = sl->pwt.luma_log2_weight_denom; -+ } - - count = sl->list_count > 0 ? sl->ref_count[0] : 0; - for (i = 0; i < count; i++) -- controls->slice_params[slice].ref_pic_list0[i] = get_dpb_index(&controls->decode_params, &sl->ref_list[0][i]); -- if (count) -- fill_weight_factors(&controls->slice_params[slice].pred_weight_table.weight_factors[0], 0, sl); -+ fill_ref_list(&controls->slice_params.ref_pic_list0[i], &controls->decode_params, &sl->ref_list[0][i]); -+ if (count && controls->pred_weights_required) -+ fill_weight_factors(&controls->pred_weights.weight_factors[0], 0, sl); - - count = sl->list_count > 1 ? sl->ref_count[1] : 0; - for (i = 0; i < count; i++) -- controls->slice_params[slice].ref_pic_list1[i] = get_dpb_index(&controls->decode_params, &sl->ref_list[1][i]); -- if (count) -- fill_weight_factors(&controls->slice_params[slice].pred_weight_table.weight_factors[1], 1, sl); -+ fill_ref_list(&controls->slice_params.ref_pic_list1[i], &controls->decode_params, &sl->ref_list[1][i]); -+ if (count && controls->pred_weights_required) -+ fill_weight_factors(&controls->pred_weights.weight_factors[1], 1, sl); - -- if (ctx->start_code == V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B) { -- ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, nalu_slice_start_code, 3); -- if (ret) -- return ret; -- } -- -- ret = ff_v4l2_request_append_output_buffer(avctx, h->cur_pic_ptr->f, buffer, size); -- if (ret) -- return ret; -- -- controls->slice_params[slice].size = req->output.used - controls->slice_params[slice].start_byte_offset; -- controls->decode_params.num_slices++; -+ controls->num_slices++; - return 0; - } - -@@ -380,15 +391,11 @@ static int v4l2_request_h264_end_frame(AVCodecContext *avctx) - static int v4l2_request_h264_set_controls(AVCodecContext *avctx) - { - V4L2RequestContextH264 *ctx = avctx->internal->hwaccel_priv_data; -- int ret; - - struct v4l2_ext_control control[] = { - { .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE, }, - { .id = V4L2_CID_MPEG_VIDEO_H264_START_CODE, }, - }; -- struct v4l2_query_ext_ctrl slice_params = { -- .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -- }; - - ctx->decode_mode = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE); - if (ctx->decode_mode != V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED && -@@ -404,16 +411,6 @@ static int v4l2_request_h264_set_controls(AVCodecContext *avctx) - return AVERROR(EINVAL); - } - -- ret = ff_v4l2_request_query_control(avctx, &slice_params); -- if (ret) -- return ret; -- -- ctx->max_slices = slice_params.elems; -- if (ctx->max_slices > MAX_SLICES) { -- av_log(avctx, AV_LOG_ERROR, "%s: unsupported max slices, %d\n", __func__, ctx->max_slices); -- return AVERROR(EINVAL); -- } -- - control[0].value = ctx->decode_mode; - control[1].value = ctx->start_code; - -@@ -424,7 +421,6 @@ static int v4l2_request_h264_init(AVCodecContext *avctx) - { - const H264Context *h = avctx->priv_data; - struct v4l2_ctrl_h264_sps sps; -- struct v4l2_ctrl_h264_pps pps; - int ret; - - struct v4l2_ext_control control[] = { -@@ -433,15 +429,9 @@ static int v4l2_request_h264_init(AVCodecContext *avctx) - .ptr = &sps, - .size = sizeof(sps), - }, -- { -- .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -- .ptr = &pps, -- .size = sizeof(pps), -- }, - }; - - fill_sps(&sps, h); -- fill_pps(&pps, h); - - ret = ff_v4l2_request_init(avctx, V4L2_PIX_FMT_H264_SLICE, 4 * 1024 * 1024, control, FF_ARRAY_ELEMS(control)); - if (ret) - -From f9f4a89058a6fac25712cc385eab72f70e9ac4c8 Mon Sep 17 00:00:00 2001 +From dc55fcd8644515c6986b73ce340ceff4856acc3f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 29 Apr 2019 22:08:59 +0000 -Subject: [PATCH 13/22] HACK: hwcontext_drm: do not require drm device +Subject: [PATCH 10/19] HACK: hwcontext_drm: do not require drm device Signed-off-by: Jonas Karlman --- @@ -4517,10 +3485,10 @@ index 32cbde82ebfa..aa4794c5e665 100644 if (hwctx->fd < 0) return AVERROR(errno); -From 027f8c90ec25c42899b24d96b434e6ed1a1a8c40 Mon Sep 17 00:00:00 2001 +From 5793e491ca4057fa9baa797e354439c9e67b129a Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 14/22] WIP: hevc scaling matrix +Subject: [PATCH 11/19] WIP: hevc scaling matrix Signed-off-by: Jernej Skrabec --- @@ -4529,16 +3497,16 @@ Signed-off-by: Jernej Skrabec 2 files changed, 33 insertions(+) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index 1009cf0891cc..1592e52c3614 100644 +index b4cb2ef02f17..2dc250edaa2f 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h @@ -19,6 +19,7 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011) - #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_MPEG_BASE + 1015) - #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_MPEG_BASE + 1016) + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) + #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) @@ -26,6 +27,7 @@ #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 @@ -4610,10 +3578,10 @@ index c16f8a868e38..f400bf4f3c82 100644 .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, .ptr = &controls->slice_params, -From 9c4a66cca0df6fd0976f907f1e315a715e5ffd87 Mon Sep 17 00:00:00 2001 +From 1b22861c6aebebcc404da0192a1b17bec4e0365d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 15/22] WIP: hevc segment address +Subject: [PATCH 12/19] WIP: hevc segment address Signed-off-by: Jernej Skrabec --- @@ -4622,7 +3590,7 @@ Signed-off-by: Jernej Skrabec 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index 1592e52c3614..3e2e32098312 100644 +index 2dc250edaa2f..f252286f7d9a 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h @@ -167,6 +167,9 @@ struct v4l2_ctrl_hevc_slice_params { @@ -4659,10 +3627,10 @@ index f400bf4f3c82..98222fc74c36 100644 .nal_unit_type = h->nal_unit_type, .nuh_temporal_id_plus1 = h->temporal_id + 1, -From 62795e555cfcccfc29c144f0ed5acae5336479c7 Mon Sep 17 00:00:00 2001 +From 19d9b2cf64743085edf06be00a3924384f13f4dc Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 16/22] WIP: hevc entry point offsets +Subject: [PATCH 13/19] WIP: hevc entry point offsets Signed-off-by: Jernej Skrabec --- @@ -4671,7 +3639,7 @@ Signed-off-by: Jernej Skrabec 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index 3e2e32098312..d1b094c8aaeb 100644 +index f252286f7d9a..eb83c1d61b8d 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h @@ -169,6 +169,7 @@ struct v4l2_ctrl_hevc_slice_params { @@ -4714,10 +3682,10 @@ index 98222fc74c36..7e77c83e4e4b 100644 static void fill_sps(struct v4l2_ctrl_hevc_sps *ctrl, const HEVCContext *h) -From edaaede001e7fbae26a0a668ea1db2b642896322 Mon Sep 17 00:00:00 2001 +From 0aab6ac62a36c7f2c439e3182abc501aa70b19ea Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 12 Dec 2019 16:13:55 +0100 -Subject: [PATCH 17/22] WIP: Add V4L2 request API vp9 hwaccel +Subject: [PATCH 14/19] WIP: Add V4L2 request API vp9 hwaccel Signed-off-by: Boris Brezillon --- @@ -4731,7 +3699,7 @@ Signed-off-by: Boris Brezillon create mode 100644 libavcodec/v4l2_request_vp9.c diff --git a/configure b/configure -index 623012757c60..2b723df55aed 100755 +index b24fb36a26c7..9acb9235ef7b 100755 --- a/configure +++ b/configure @@ -3015,6 +3015,8 @@ vp9_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_VP9" @@ -5198,10 +4166,10 @@ index 54726df742f9..fee3568736f7 100644 uint8_t pred_prob[3]; struct { -From ef82ae9fffba44e88d59a3fa4b958a38d1b5cd9e Mon Sep 17 00:00:00 2001 +From 324ec7647aa25c85b1dae47b86e11fbc4637ceac Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 12 Dec 2019 16:13:55 +0100 -Subject: [PATCH 18/22] WIP: Add and use vp9 private linux header +Subject: [PATCH 15/19] WIP: Add and use vp9 private linux header Signed-off-by: Boris Brezillon --- @@ -5212,7 +4180,7 @@ Signed-off-by: Boris Brezillon create mode 100644 libavcodec/vp9-ctrls.h diff --git a/configure b/configure -index 2b723df55aed..87c6836af275 100755 +index 9acb9235ef7b..9942d74f1f09 100755 --- a/configure +++ b/configure @@ -3015,7 +3015,7 @@ vp9_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_VP9" @@ -5728,10 +4696,10 @@ index 000000000000..0cdea8a18b72 + +#endif /* _VP9_CTRLS_H_ */ -From 4b268a93e5945dc7863a8dc953a12fa157b4f8e6 Mon Sep 17 00:00:00 2001 +From a787b57927be77f29178de8fb00afef0b7468c25 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 15 May 2020 16:54:05 +0000 -Subject: [PATCH 19/22] WIP: add NV15 and NV20 support +Subject: [PATCH 16/19] WIP: add NV15 and NV20 support Signed-off-by: Jonas Karlman --- @@ -5740,7 +4708,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/libavcodec/h264_slice.c b/libavcodec/h264_slice.c -index c3896cfd90ab..39ae8fabfd3b 100644 +index dd5ba98a02cb..c952997d685d 100644 --- a/libavcodec/h264_slice.c +++ b/libavcodec/h264_slice.c @@ -785,10 +785,17 @@ static enum AVPixelFormat get_pixel_format(H264Context *h, int force_callback) @@ -5815,10 +4783,10 @@ index 5234b5049b0d..0b294feff2eb 100644 default: return -1; -From fa7165e391287bf970569e36b0b19bff947b084f Mon Sep 17 00:00:00 2001 +From 8de8b20b540b68355e54a6e97b5543d0ae67cda3 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 27 Jul 2020 23:15:45 +0000 -Subject: [PATCH 20/22] HACK: define drm NV15 and NV20 format +Subject: [PATCH 17/19] HACK: define drm NV15 and NV20 format --- libavcodec/v4l2_request.c | 8 ++++++++ @@ -5844,10 +4812,10 @@ index 0b294feff2eb..a8f0ee79eeef 100644 { V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)frame->data[0]; -From 4ee9ede28d912637e64a7472acd3e8ab5272f41b Mon Sep 17 00:00:00 2001 +From b4ef09e9b03a4cdb442d87f5c3951ea406ff09e0 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 11 Apr 2021 08:40:57 +0000 -Subject: [PATCH 21/22] WIP: hevc: slice dependent flag +Subject: [PATCH 18/19] WIP: hevc: slice dependent flag --- libavcodec/hevc-ctrls.h | 1 + @@ -5855,7 +4823,7 @@ Subject: [PATCH 21/22] WIP: hevc: slice dependent flag 2 files changed, 4 insertions(+) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index d1b094c8aaeb..9c976b3cf092 100644 +index eb83c1d61b8d..cd51fb6df1f0 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h @@ -162,6 +162,7 @@ struct v4l2_hevc_pred_weight_table { @@ -5881,10 +4849,10 @@ index 7e77c83e4e4b..116a69340af3 100644 const HEVCFrame *frame = &h->DPB[i]; if (frame != pic && (frame->flags & (HEVC_FRAME_FLAG_LONG_REF | HEVC_FRAME_FLAG_SHORT_REF))) { -From a327aa791645517b031ac8d89a720b1907cfb96a Mon Sep 17 00:00:00 2001 +From 6a200d38c3ff00cfdecd92bb7b7083b590403017 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 13 May 2020 22:51:21 +0000 -Subject: [PATCH 22/22] WIP: hevc rkvdec fields +Subject: [PATCH 19/19] WIP: hevc rkvdec fields Signed-off-by: Jonas Karlman --- @@ -5893,7 +4861,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index 9c976b3cf092..c54687bfe658 100644 +index cd51fb6df1f0..4d51c148d0ba 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h @@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code { From e198af10b68e2819d98287c5531531975f6da0b3 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 2 May 2021 10:47:46 +0200 Subject: [PATCH 38/51] linux (Allwinner): update patches for 5.13 --- packages/linux/package.mk | 4 - ...-plus-bananapi-m2-zero-Increase-BT-U.patch | 26 - ...2-plus-bananapi-m2-zero-Add-HDMI-out.patch | 51 - ...nanapi-m2-plus-Increase-BT-UART-spee.patch | 25 - .../0001-HACK-h6-Add-HDMI-sound-card.patch | 4 +- ...-Use-devm_regulator_get-for-PHY-regu.patch | 6 +- ...-Rename-PHY-regulator-variable-to-re.patch | 8 +- ...-Add-support-for-enabling-a-regulato.patch | 8 +- ...llwinner-orange-pi-3-Enable-ethernet.patch | 2 +- ...-dts-h6-enable-USB3-port-on-Pine-H64.patch | 2 +- ...nner-h6-Add-AC200-EPHY-related-nodes.patch | 2 +- ...usuable-eMMC-on-some-H6-boards-by-di.patch | 2 +- .../0012-pineh64-model-b-bluetooth-wip.patch | 45 - ...ner-h6-tanix-tx6-add-bt-enable-rtw88.patch | 11 +- projects/Allwinner/linux/linux.aarch64.conf | 328 ++++-- projects/Allwinner/linux/linux.arm.conf | 263 +++-- ...p20x-pek-allow-wakeup-after-shutdown.patch | 0 ...001-media-cedrus-Add-support-for-R40.patch | 40 - ...tected-clocks-for-all-OF-clock-prov.patch} | 4 +- ...r-allow-timeout-to-be-set-at-runtime.patch | 99 -- ...sun4i-i2s-Change-set_chan_cfg-params.patch | 118 --- ...m-Support-protected-clocks-property.patch} | 0 ...SoC-sun4i-i2s-Add-support-for-H6-I2S.patch | 295 ------ ...-dts-sunxi-h3-h5-Protect-SCP-clocks.patch} | 4 +- ...hange-get_sr-and-get_wss-to-be-more-.patch | 134 --- ...4-dts-allwinner-a64-Protect-SCP-clo.patch} | 4 +- ...SoC-sun4i-i2s-Set-sign-extend-sample.patch | 86 -- ...4-dts-allwinner-h6-Protect-SCP-cloc.patch} | 4 +- ...-sun4i-i2s-Add-20-and-24-bit-support.patch | 61 -- ...n6i-Allow-RTC-wakeup-after-shutdown.patch} | 10 +- ...oC-sun4i-i2s-Fix-sun8i-volatile-regs.patch | 49 - ...-sun4i-lradc-keys-Add-wakup-support.patch} | 0 ...-sun4i-i2s-Fix-setting-of-FIFO-modes.patch | 53 - ...-Support-unidirectional-mailbox-cha.patch} | 8 +- ...M-dts-sunxi-h3-h5-Add-SCPI-protocol.patch} | 2 +- ...ix-coding-style-for-callback-definit.patch | 44 - ...M-dts-sun8i-r40-Add-deinterlace-node.patch | 45 - ...dts-allwinner-a64-Add-SCPI-protocol.patch} | 0 ...ts-allwinner-h5-Add-deinterlace-node.patch | 38 - ...-dts-allwinner-h6-Add-SCPI-protocol.patch} | 2 +- ...C-hdmi-codec-fix-channel-allocation.patch} | 2 +- ...-drm-sun4i-csc-Rework-DE3-CSC-macros.patch | 40 - ...e2-de3-Remove-redundant-CSC-matrices.patch | 163 --- ...api-hevc-Add-scaling-matrix-control.patch} | 26 +- ...-sun4i-Add-support-for-BT2020-to-DE3.patch | 62 -- ...hevc-Add-support-for-scaling-matrix.patch} | 11 +- ...uapi-hevc-Add-segment-address-field.patch} | 0 ...sure-host-is-suspended-during-system.patch | 27 - ...arm64-dts-allwinner-h6-Add-I2S1-node.patch | 42 - ...evc-Add-support-for-multiple-slices.patch} | 2 +- ...rm64-dts-allwinner-a64-Add-I2S2-node.patch | 43 - ...> 0018-media-cedrus-hevc-tiles-hack.patch} | 6 +- ...19-arm-dts-sunxi-h3-h5-Add-I2S2-node.patch | 42 - ...rus-Add-callback-for-buffer-cleanup.patch} | 6 +- ...llwinner-h6-PineH64-model-B-Add-wifi.patch | 47 - ...drus-hevc-Improve-buffer-management.patch} | 4 +- ...drus-h264-Improve-buffer-management.patch} | 2 +- ...tch => 0022-WIp-10-bit-HEVC-support.patch} | 16 +- ...check-for-H264-and-HEVC-limitations.patch} | 38 +- ...IP-dw-hdmi-cec-sleep-100ms-on-error.patch} | 0 ...ment-plane-z-position-setting-logic.patch} | 36 +- ...se-update-regmap-variant-for-blend-.patch} | 0 ...drm-sun4i-mixer-Add-caching-support.patch} | 0 ...h => 0028-mfd-Add-support-for-AC200.patch} | 0 ...-net-phy-Add-support-for-AC200-EPHY.patch} | 0 ...ce.patch => 0030-wip-H6-deinterlace.patch} | 2 +- ...ch => 0031-arm64-dts-h6-deinterlace.patch} | 2 +- ...d-parenthesis-around-macro-argument.patch} | 0 ...patch => 0033-WIP-I2S-multi-channel.patch} | 8 +- ...-cedrus-Add-support-for-VP8-decoding.patch | 985 ------------------ ...0034-HACK-h3-h5-Add-HDMI-sound-card.patch} | 4 +- ...0035-h3-h5-power-key-wake-up-source.patch} | 43 +- ...5-cvbs.patch => 0036-wip-h3-h5-cvbs.patch} | 78 +- ...i-hevc-add-fields-needed-for-rkvdec.patch} | 2 - ...edia-uapi-hevc-tiles-and-num_slices.patch} | 2 - ...nor-data-with-pre-defined-thresholds.patch | 57 - ...-timer-as-default-in-devfreq-profile.patch | 24 - ...-governor-data-with-pre-defined-thre.patch | 59 -- ...-delayed-timer-as-default-in-devfreq.patch | 27 - ...c-sun8i-Return-void-from-PHY-unpower.patch | 34 - ...-sun8i-Remove-unnecessary-PHY-power-.patch | 29 - ...-dwmac-sun8i-Use-reset_control_reset.patch | 30 - ...c-sun8i-Minor-probe-function-cleanup.patch | 34 - ...-dwmac-sun8i-Add-a-shutdown-callback.patch | 41 - ...1-i2c-mv64xxx-Add-runtime-PM-support.patch | 237 ----- ...r-Skip-register-writes-during-remove.patch | 38 - ...unxi-cir-Remove-unnecessary-spinlock.patch | 69 -- ...r-Factor-out-hardware-initialization.patch | 223 ---- ...Implement-suspend-resume-shutdown-ca.patch | 60 -- ...sun6i-r-Use-a-stacked-irqchip-driver.patch | 437 -------- ...7-irqchip-sun6i-r-Add-wakeup-support.patch | 210 ---- ...-dts-sunxi-Rename-nmi_intc-to-r_intc.patch | 194 ---- ...dts-sunxi-Use-the-new-r_intc-binding.patch | 291 ------ ...-ARM-dts-sunxi-h3-h5-Add-r_intc-node.patch | 33 - ...i-Move-wakeup-capable-IRQs-to-r_intc.patch | 139 --- ...allwinner-Use-the-new-r_intc-binding.patch | 232 ----- ...ner-Move-wakeup-capable-IRQs-to-r_in.patch | 77 -- ...RM-dts-sunxi-a83t-Protect-SCP-clocks.patch | 28 - ...30-bus-sunxi-rsb-Move-OF-match-table.patch | 43 - ...lit-out-controller-init-exit-functio.patch | 210 ---- ...plement-suspend-resume-shutdown-call.patch | 81 -- ...b-Implement-runtime-power-management.patch | 129 --- 102 files changed, 559 insertions(+), 6135 deletions(-) delete mode 100644 projects/Allwinner/devices/H2-plus/patches/linux/0001-ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Increase-BT-U.patch delete mode 100644 projects/Allwinner/devices/H2-plus/patches/linux/0002-ARM-dts-sunxi-h2-plus-bananapi-m2-zero-Add-HDMI-out.patch delete mode 100644 projects/Allwinner/devices/H3/patches/linux/0002-ARM-dts-sunxi-bananapi-m2-plus-Increase-BT-UART-spee.patch delete mode 100644 projects/Allwinner/devices/H6/patches/linux/0012-pineh64-model-b-bluetooth-wip.patch rename projects/Allwinner/patches/linux/{crust => }/0001-Input-axp20x-pek-allow-wakeup-after-shutdown.patch (100%) delete mode 100644 projects/Allwinner/patches/linux/0001-media-cedrus-Add-support-for-R40.patch rename projects/Allwinner/patches/linux/{crust/0024-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch => 0002-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch} (98%) delete mode 100644 projects/Allwinner/patches/linux/0002-media-sunxi-cir-allow-timeout-to-be-set-at-runtime.patch delete mode 100644 projects/Allwinner/patches/linux/0003-ASoC-sun4i-i2s-Change-set_chan_cfg-params.patch rename projects/Allwinner/patches/linux/{crust/0025-Revert-clk-qcom-Support-protected-clocks-property.patch => 0003-Revert-clk-qcom-Support-protected-clocks-property.patch} (100%) delete mode 100644 projects/Allwinner/patches/linux/0004-ASoC-sun4i-i2s-Add-support-for-H6-I2S.patch rename projects/Allwinner/patches/linux/{crust/0027-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch => 0004-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch} (95%) delete mode 100644 projects/Allwinner/patches/linux/0005-ASoC-sun4i-i2s-Change-get_sr-and-get_wss-to-be-more-.patch rename projects/Allwinner/patches/linux/{crust/0028-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch => 0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch} (95%) delete mode 100644 projects/Allwinner/patches/linux/0006-ASoC-sun4i-i2s-Set-sign-extend-sample.patch rename projects/Allwinner/patches/linux/{crust/0029-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch => 0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch} (95%) delete mode 100644 projects/Allwinner/patches/linux/0007-ASoC-sun4i-i2s-Add-20-and-24-bit-support.patch rename projects/Allwinner/patches/linux/{crust/0034-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch => 0007-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch} (84%) delete mode 100644 projects/Allwinner/patches/linux/0008-ASoC-sun4i-i2s-Fix-sun8i-volatile-regs.patch rename projects/Allwinner/patches/linux/{crust/0035-input-sun4i-lradc-keys-Add-wakup-support.patch => 0008-input-sun4i-lradc-keys-Add-wakup-support.patch} (100%) delete mode 100644 projects/Allwinner/patches/linux/0009-ASoC-sun4i-i2s-Fix-setting-of-FIFO-modes.patch rename projects/Allwinner/patches/linux/{crust/0036-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch => 0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch} (93%) rename projects/Allwinner/patches/linux/{crust/0037-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch => 0010-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch} (98%) delete mode 100644 projects/Allwinner/patches/linux/0010-ASoC-sun4i-i2s-fix-coding-style-for-callback-definit.patch delete mode 100644 projects/Allwinner/patches/linux/0011-ARM-dts-sun8i-r40-Add-deinterlace-node.patch rename projects/Allwinner/patches/linux/{crust/0038-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch => 0011-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch} (100%) delete mode 100644 projects/Allwinner/patches/linux/0012-arm64-dts-allwinner-h5-Add-deinterlace-node.patch rename projects/Allwinner/patches/linux/{crust/0039-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch => 0012-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch} (98%) rename projects/Allwinner/patches/linux/{0022-ASoC-hdmi-codec-fix-channel-allocation.patch => 0013-ASoC-hdmi-codec-fix-channel-allocation.patch} (98%) delete mode 100644 projects/Allwinner/patches/linux/0013-drm-sun4i-csc-Rework-DE3-CSC-macros.patch delete mode 100644 projects/Allwinner/patches/linux/0014-drm-sun4i-de2-de3-Remove-redundant-CSC-matrices.patch rename projects/Allwinner/patches/linux/{0023-media-uapi-hevc-Add-scaling-matrix-control.patch => 0014-media-uapi-hevc-Add-scaling-matrix-control.patch} (74%) delete mode 100644 projects/Allwinner/patches/linux/0015-drm-sun4i-Add-support-for-BT2020-to-DE3.patch rename projects/Allwinner/patches/linux/{0024-media-cedrus-hevc-Add-support-for-scaling-matrix.patch => 0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch} (96%) rename projects/Allwinner/patches/linux/{0025-media-uapi-hevc-Add-segment-address-field.patch => 0016-media-uapi-hevc-Add-segment-address-field.patch} (100%) delete mode 100644 projects/Allwinner/patches/linux/0016-mmc-sunxi-mmc-Ensure-host-is-suspended-during-system.patch delete mode 100644 projects/Allwinner/patches/linux/0017-arm64-dts-allwinner-h6-Add-I2S1-node.patch rename projects/Allwinner/patches/linux/{0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch => 0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch} (98%) delete mode 100644 projects/Allwinner/patches/linux/0018-arm64-dts-allwinner-a64-Add-I2S2-node.patch rename projects/Allwinner/patches/linux/{0027-media-cedrus-hevc-tiles-hack.patch => 0018-media-cedrus-hevc-tiles-hack.patch} (98%) delete mode 100644 projects/Allwinner/patches/linux/0019-arm-dts-sunxi-h3-h5-Add-I2S2-node.patch rename projects/Allwinner/patches/linux/{0028-media-cedrus-Add-callback-for-buffer-cleanup.patch => 0019-media-cedrus-Add-callback-for-buffer-cleanup.patch} (91%) delete mode 100644 projects/Allwinner/patches/linux/0020-arm64-dts-allwinner-h6-PineH64-model-B-Add-wifi.patch rename projects/Allwinner/patches/linux/{0029-media-cedrus-hevc-Improve-buffer-management.patch => 0020-media-cedrus-hevc-Improve-buffer-management.patch} (98%) rename projects/Allwinner/patches/linux/{0030-media-cedrus-h264-Improve-buffer-management.patch => 0021-media-cedrus-h264-Improve-buffer-management.patch} (99%) rename projects/Allwinner/patches/linux/{0031-WIp-10-bit-HEVC-support.patch => 0022-WIp-10-bit-HEVC-support.patch} (91%) rename projects/Allwinner/patches/linux/{0032-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch => 0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch} (77%) rename projects/Allwinner/patches/linux/{0034-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch => 0024-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch} (100%) rename projects/Allwinner/patches/linux/{0035-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch => 0025-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch} (89%) rename projects/Allwinner/patches/linux/{0036-drm-sun4i-Don-t-use-update-regmap-variant-for-blend-.patch => 0026-drm-sun4i-Don-t-use-update-regmap-variant-for-blend-.patch} (100%) rename projects/Allwinner/patches/linux/{0037-drm-sun4i-mixer-Add-caching-support.patch => 0027-drm-sun4i-mixer-Add-caching-support.patch} (100%) rename projects/Allwinner/patches/linux/{0038-mfd-Add-support-for-AC200.patch => 0028-mfd-Add-support-for-AC200.patch} (100%) rename projects/Allwinner/patches/linux/{0039-net-phy-Add-support-for-AC200-EPHY.patch => 0029-net-phy-Add-support-for-AC200-EPHY.patch} (100%) rename projects/Allwinner/patches/linux/{0040-wip-H6-deinterlace.patch => 0030-wip-H6-deinterlace.patch} (99%) rename projects/Allwinner/patches/linux/{0041-arm64-dts-h6-deinterlace.patch => 0031-arm64-dts-h6-deinterlace.patch} (97%) rename projects/Allwinner/patches/linux/{0042-ASoC-sun4i-i2s-Add-parenthesis-around-macro-argument.patch => 0032-ASoC-sun4i-i2s-Add-parenthesis-around-macro-argument.patch} (100%) rename projects/Allwinner/patches/linux/{0043-WIP-I2S-multi-channel.patch => 0033-WIP-I2S-multi-channel.patch} (97%) delete mode 100644 projects/Allwinner/patches/linux/0033-media-cedrus-Add-support-for-VP8-decoding.patch rename projects/Allwinner/patches/linux/{0044-HACK-h3-h5-Add-HDMI-sound-card.patch => 0034-HACK-h3-h5-Add-HDMI-sound-card.patch} (96%) rename projects/Allwinner/patches/linux/{0045-h3-h5-power-key-wake-up-source.patch => 0035-h3-h5-power-key-wake-up-source.patch} (55%) rename projects/Allwinner/patches/linux/{0055-wip-h3-h5-cvbs.patch => 0036-wip-h3-h5-cvbs.patch} (84%) rename projects/Allwinner/patches/linux/{0059-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch => 0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch} (95%) rename projects/Allwinner/patches/linux/{0060-HACK-media-uapi-hevc-tiles-and-num_slices.patch => 0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch} (91%) delete mode 100644 projects/Allwinner/patches/linux/0046-drm-lima-add-governor-data-with-pre-defined-thresholds.patch delete mode 100644 projects/Allwinner/patches/linux/0047-drm-lima-Use-delayed-timer-as-default-in-devfreq-profile.patch delete mode 100644 projects/Allwinner/patches/linux/0048-drm-panfrost-Add-governor-data-with-pre-defined-thre.patch delete mode 100644 projects/Allwinner/patches/linux/0049-drm-panfrost-Use-delayed-timer-as-default-in-devfreq.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0006-net-stmmac-dwmac-sun8i-Return-void-from-PHY-unpower.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0007-net-stmmac-dwmac-sun8i-Remove-unnecessary-PHY-power-.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0008-net-stmmac-dwmac-sun8i-Use-reset_control_reset.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0009-net-stmmac-dwmac-sun8i-Minor-probe-function-cleanup.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0010-net-stmmac-dwmac-sun8i-Add-a-shutdown-callback.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0011-i2c-mv64xxx-Add-runtime-PM-support.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0012-media-sunxi-cir-Skip-register-writes-during-remove.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0013-media-sunxi-cir-Remove-unnecessary-spinlock.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0014-media-sunxi-cir-Factor-out-hardware-initialization.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0015-media-sunxi-cir-Implement-suspend-resume-shutdown-ca.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0016-irqchip-sun6i-r-Use-a-stacked-irqchip-driver.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0017-irqchip-sun6i-r-Add-wakeup-support.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0018-ARM-dts-sunxi-Rename-nmi_intc-to-r_intc.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0019-ARM-dts-sunxi-Use-the-new-r_intc-binding.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0020-ARM-dts-sunxi-h3-h5-Add-r_intc-node.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0021-ARM-dts-sunxi-Move-wakeup-capable-IRQs-to-r_intc.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0022-arm64-dts-allwinner-Use-the-new-r_intc-binding.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0023-arm64-dts-allwinner-Move-wakeup-capable-IRQs-to-r_in.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0026-DO-NOT-MERGE-ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0030-bus-sunxi-rsb-Move-OF-match-table.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0031-bus-sunxi-rsb-Split-out-controller-init-exit-functio.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0032-bus-sunxi-rsb-Implement-suspend-resume-shutdown-call.patch delete mode 100644 projects/Allwinner/patches/linux/crust/0033-bus-sunxi-rsb-Implement-runtime-power-management.patch diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 30829f5333..60b1984a8f 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -37,10 +37,6 @@ esac PKG_KERNEL_CFG_FILE=$(kernel_config_path) || die -if listcontains "${UBOOT_FIRMWARE}" "crust"; then - PKG_PATCH_DIRS+=" crust" -fi - if [ -n "${KERNEL_TOOLCHAIN}" ]; then PKG_DEPENDS_HOST+=" gcc-arm-${KERNEL_TOOLCHAIN}:host" PKG_DEPENDS_TARGET+=" gcc-arm-${KERNEL_TOOLCHAIN}:host" diff --git a/projects/Allwinner/devices/H2-plus/patches/linux/0001-ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Increase-BT-U.patch b/projects/Allwinner/devices/H2-plus/patches/linux/0001-ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Increase-BT-U.patch deleted file mode 100644 index 21047f5b7a..0000000000 --- a/projects/Allwinner/devices/H2-plus/patches/linux/0001-ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Increase-BT-U.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 4cc652f2c660bd01bd0d8cefde272400cbe82fbe Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 16 Jan 2021 11:32:04 +0100 -Subject: [PATCH 1/2] ARM: dts: sun8i: h2-plus: bananapi-m2-zero: Increase BT - UART speed - -Bluetooth module on BananaPi M2 Zero can also be used for streaming -audio. However, for that case higher UART speed is required. - -Add a max-speed property. - -Signed-off-by: Jernej Skrabec ---- - arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts -+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts -@@ -125,6 +125,7 @@ - - bluetooth { - compatible = "brcm,bcm43438-bt"; -+ max-speed = <1500000>; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; diff --git a/projects/Allwinner/devices/H2-plus/patches/linux/0002-ARM-dts-sunxi-h2-plus-bananapi-m2-zero-Add-HDMI-out.patch b/projects/Allwinner/devices/H2-plus/patches/linux/0002-ARM-dts-sunxi-h2-plus-bananapi-m2-zero-Add-HDMI-out.patch deleted file mode 100644 index daeef7f63f..0000000000 --- a/projects/Allwinner/devices/H2-plus/patches/linux/0002-ARM-dts-sunxi-h2-plus-bananapi-m2-zero-Add-HDMI-out.patch +++ /dev/null @@ -1,51 +0,0 @@ -From aa47c3b292cb0ffcf2c00b2a12c477ec3027a729 Mon Sep 17 00:00:00 2001 -From: PJBrs -Date: Sat, 16 Jan 2021 11:39:45 +0100 -Subject: [PATCH 2/2] ARM: dts: sunxi: h2-plus-bananapi-m2-zero: Add HDMI out - -Add HDMI out, including the display engine, to the BananaPi M2 Zero. ---- - .../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 25 +++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts -+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts -@@ -26,6 +26,17 @@ - stdout-path = "serial0:115200n8"; - }; - -+ connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -107,6 +118,20 @@ - }; - }; - -+&de { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &ohci0 { - status = "okay"; - }; diff --git a/projects/Allwinner/devices/H3/patches/linux/0002-ARM-dts-sunxi-bananapi-m2-plus-Increase-BT-UART-spee.patch b/projects/Allwinner/devices/H3/patches/linux/0002-ARM-dts-sunxi-bananapi-m2-plus-Increase-BT-UART-spee.patch deleted file mode 100644 index 12059e3a72..0000000000 --- a/projects/Allwinner/devices/H3/patches/linux/0002-ARM-dts-sunxi-bananapi-m2-plus-Increase-BT-UART-spee.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 54b5c2cb4fc87ca72daa662423d4d969f3b5edb8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 16 Jan 2021 11:49:57 +0100 -Subject: [PATCH] ARM: dts: sunxi: bananapi-m2-plus: Increase BT UART speed - -Bluetooth module on BananaPi M2 Plus can also be used for streaming -audio. However, for that case higher UART speed is required. - -Add a max-speed property. - -Signed-off-by: Jernej Skrabec ---- - arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi -+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi -@@ -219,6 +219,7 @@ - - bluetooth { - compatible = "brcm,bcm43438-bt"; -+ max-speed = <1500000>; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; diff --git a/projects/Allwinner/devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch b/projects/Allwinner/devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch index 71663f441c..390a82e54a 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch @@ -35,7 +35,7 @@ Signed-off-by: Jernej Skrabec soc { compatible = "simple-bus"; #address-cells = <1>; -@@ -652,7 +670,6 @@ +@@ -655,7 +673,6 @@ dmas = <&dma 4>, <&dma 4>; resets = <&ccu RST_BUS_I2S1>; dma-names = "rx", "tx"; @@ -43,7 +43,7 @@ Signed-off-by: Jernej Skrabec }; spdif: spdif@5093000 { -@@ -785,6 +802,7 @@ +@@ -792,6 +809,7 @@ }; hdmi: hdmi@6000000 { diff --git a/projects/Allwinner/devices/H6/patches/linux/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch b/projects/Allwinner/devices/H6/patches/linux/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch index 50e7cc4d46..803c9fe408 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch @@ -22,7 +22,7 @@ Signed-off-by: Ondrej Jirman --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -549,12 +549,10 @@ static int sun8i_dwmac_init(struct platf +@@ -571,12 +571,10 @@ static int sun8i_dwmac_init(struct platf struct sunxi_priv_data *gmac = priv; int ret; @@ -39,7 +39,7 @@ Signed-off-by: Ondrej Jirman } ret = clk_prepare_enable(gmac->tx_clk); -@@ -1021,8 +1019,7 @@ static void sun8i_dwmac_exit(struct plat +@@ -1045,8 +1043,7 @@ static void sun8i_dwmac_exit(struct plat clk_disable_unprepare(gmac->tx_clk); @@ -49,7 +49,7 @@ Signed-off-by: Ondrej Jirman } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) -@@ -1150,12 +1147,12 @@ static int sun8i_dwmac_probe(struct plat +@@ -1174,12 +1171,12 @@ static int sun8i_dwmac_probe(struct plat } /* Optional regulator for PHY */ diff --git a/projects/Allwinner/devices/H6/patches/linux/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch b/projects/Allwinner/devices/H6/patches/linux/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch index 81132eb2b0..2d84ecb115 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch @@ -47,7 +47,7 @@ Signed-off-by: Ondrej Jirman struct reset_control *rst_ephy; const struct emac_variant *variant; struct regmap_field *regmap_field; -@@ -549,9 +551,9 @@ static int sun8i_dwmac_init(struct platf +@@ -571,9 +573,9 @@ static int sun8i_dwmac_init(struct platf struct sunxi_priv_data *gmac = priv; int ret; @@ -59,7 +59,7 @@ Signed-off-by: Ondrej Jirman return ret; } -@@ -572,8 +574,7 @@ static int sun8i_dwmac_init(struct platf +@@ -594,8 +596,7 @@ static int sun8i_dwmac_init(struct platf err_disable_clk: clk_disable_unprepare(gmac->tx_clk); err_disable_regulator: @@ -69,7 +69,7 @@ Signed-off-by: Ondrej Jirman return ret; } -@@ -1019,7 +1020,7 @@ static void sun8i_dwmac_exit(struct plat +@@ -1043,7 +1044,7 @@ static void sun8i_dwmac_exit(struct plat clk_disable_unprepare(gmac->tx_clk); @@ -78,7 +78,7 @@ Signed-off-by: Ondrej Jirman } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) -@@ -1147,11 +1148,9 @@ static int sun8i_dwmac_probe(struct plat +@@ -1171,11 +1172,9 @@ static int sun8i_dwmac_probe(struct plat } /* Optional regulator for PHY */ diff --git a/projects/Allwinner/devices/H6/patches/linux/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch b/projects/Allwinner/devices/H6/patches/linux/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch index a38543d319..adc32db17e 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch @@ -34,7 +34,7 @@ Signed-off-by: Ondrej Jirman struct reset_control *rst_ephy; const struct emac_variant *variant; struct regmap_field *regmap_field; -@@ -551,10 +554,16 @@ static int sun8i_dwmac_init(struct platf +@@ -573,10 +576,16 @@ static int sun8i_dwmac_init(struct platf struct sunxi_priv_data *gmac = priv; int ret; @@ -52,7 +52,7 @@ Signed-off-by: Ondrej Jirman } ret = clk_prepare_enable(gmac->tx_clk); -@@ -575,6 +584,8 @@ err_disable_clk: +@@ -597,6 +606,8 @@ err_disable_clk: clk_disable_unprepare(gmac->tx_clk); err_disable_regulator: regulator_disable(gmac->regulator_phy); @@ -61,7 +61,7 @@ Signed-off-by: Ondrej Jirman return ret; } -@@ -1021,6 +1032,7 @@ static void sun8i_dwmac_exit(struct plat +@@ -1045,6 +1056,7 @@ static void sun8i_dwmac_exit(struct plat clk_disable_unprepare(gmac->tx_clk); regulator_disable(gmac->regulator_phy); @@ -69,7 +69,7 @@ Signed-off-by: Ondrej Jirman } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) -@@ -1154,6 +1166,15 @@ static int sun8i_dwmac_probe(struct plat +@@ -1178,6 +1190,15 @@ static int sun8i_dwmac_probe(struct plat return ret; } diff --git a/projects/Allwinner/devices/H6/patches/linux/0005-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch b/projects/Allwinner/devices/H6/patches/linux/0005-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch index 82baa0f4d0..4c6a1d00b2 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0005-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0005-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch @@ -90,7 +90,7 @@ Signed-off-by: Ondrej Jirman &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -@@ -207,6 +246,7 @@ +@@ -211,6 +250,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc33-audio-tv-ephy-mac"; diff --git a/projects/Allwinner/devices/H6/patches/linux/0006-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch b/projects/Allwinner/devices/H6/patches/linux/0006-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch index 7178bfbf23..91235b742f 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0006-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0006-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch @@ -28,7 +28,7 @@ Reviewed-by: Chen-Yu Tsai &emac { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; -@@ -331,3 +335,8 @@ +@@ -332,3 +336,8 @@ usb3_vbus-supply = <®_usb_vbus>; status = "okay"; }; diff --git a/projects/Allwinner/devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch b/projects/Allwinner/devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch index fd11bccf83..ba637b82ee 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch @@ -76,7 +76,7 @@ Signed-off-by: Jernej Skrabec /omit-if-no-ref/ spi0_pins: spi0-pins { pins = "PC0", "PC2", "PC3"; -@@ -640,6 +671,31 @@ +@@ -643,6 +674,31 @@ #size-cells = <0>; }; diff --git a/projects/Allwinner/devices/H6/patches/linux/0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch b/projects/Allwinner/devices/H6/patches/linux/0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch index 5770fa769d..bf3b0c5ff6 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch @@ -37,7 +37,7 @@ Signed-off-by: Alejandro González --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c -@@ -1398,14 +1398,17 @@ static int sunxi_mmc_probe(struct platfo +@@ -1421,14 +1421,17 @@ static int sunxi_mmc_probe(struct platfo /* * Some H5 devices do not have signal traces precise enough to diff --git a/projects/Allwinner/devices/H6/patches/linux/0012-pineh64-model-b-bluetooth-wip.patch b/projects/Allwinner/devices/H6/patches/linux/0012-pineh64-model-b-bluetooth-wip.patch deleted file mode 100644 index 0b76f232ae..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/0012-pineh64-model-b-bluetooth-wip.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 29 Oct 2020 21:04:24 +0100 -Subject: [PATCH] pineh64 model b - bluetooth wip - -Signed-off-by: Jernej Skrabec ---- - .../dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 16 ++++++++++++++++ - drivers/bluetooth/hci_h5.c | 3 +++ - 2 files changed, 19 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts -@@ -34,3 +34,19 @@ - non-removable; - status = "okay"; - }; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "realtek,rtl8723bs-bt"; -+ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ -+ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ -+ enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ -+ firmware-postfix = "OBDA8723"; -+ max-speed = <1500000>; -+ }; -+}; ---- a/drivers/bluetooth/hci_h5.c -+++ b/drivers/bluetooth/hci_h5.c -@@ -820,6 +820,9 @@ static int h5_serdev_probe(struct serdev - if (!data) - return -ENODEV; - -+ of_property_read_string(dev->of_node, -+ "firmware-postfix", &h5->id); -+ - h5->vnd = (const struct h5_vnd *)data; - } - diff --git a/projects/Allwinner/devices/H6/patches/linux/0020-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch b/projects/Allwinner/devices/H6/patches/linux/0020-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch index 7adac809ec..2feb40b5be 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0020-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch +++ b/projects/Allwinner/devices/H6/patches/linux/0020-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch @@ -29,11 +29,9 @@ Bluetooth: hci0: RTL: loading rtl_bt/rtl8822cs_config.bin .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 32 +++++++++++++++++++ 1 file changed, 48 insertions(+) -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -index 5233ad1488..06e7820fd9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -47,12 +47,29 @@ reg_vcc3v3: vcc3v3 { +@@ -47,12 +47,29 @@ regulator-max-microvolt = <3300000>; }; @@ -63,7 +61,7 @@ index 5233ad1488..06e7820fd9 100644 }; &ac200_pwm_clk { -@@ -122,6 +139,22 @@ &mmc0 { +@@ -122,6 +139,22 @@ status = "okay"; }; @@ -86,7 +84,7 @@ index 5233ad1488..06e7820fd9 100644 &mmc2 { vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc1v8>; -@@ -158,6 +191,21 @@ &uart0 { +@@ -158,6 +191,21 @@ status = "okay"; }; @@ -108,6 +106,3 @@ index 5233ad1488..06e7820fd9 100644 &usb2otg { dr_mode = "host"; status = "okay"; --- -2.29.2 - diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index ff03df8d47..c2d05e73c1 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,12 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.52 Kernel Configuration +# Linux/arm64 5.13.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=100201 -CONFIG_LD_VERSION=235010000 CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23501 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23501 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -60,7 +63,6 @@ CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -78,6 +80,21 @@ CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_JIT_ALWAYS_ON is not set +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y @@ -158,6 +175,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -192,7 +210,6 @@ CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -219,11 +236,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_JIT_ALWAYS_ON is not set -CONFIG_BPF_JIT_DEFAULT_ON=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -274,8 +286,7 @@ CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -287,10 +298,11 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # Platform selection # # CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_AGILEX is not set CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set # CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set @@ -312,7 +324,7 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set @@ -322,7 +334,6 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set # end of Platform selection @@ -341,6 +352,7 @@ CONFIG_ARM64_ERRATUM_819472=y CONFIG_ARM64_ERRATUM_832075=y CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y CONFIG_ARM64_ERRATUM_1024718=y CONFIG_ARM64_ERRATUM_1418040=y CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y @@ -364,6 +376,7 @@ CONFIG_QCOM_FALKOR_ERRATUM_1003=y CONFIG_QCOM_FALKOR_ERRATUM_1009=y CONFIG_QCOM_QDF2400_ERRATUM_0065=y CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set CONFIG_SOCIONEXT_SYNQUACER_PREITS=y # end of ARM errata workarounds via the alternatives framework @@ -393,21 +406,15 @@ CONFIG_HZ_250=y # CONFIG_HZ_1000 is not set CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HW_PERF_EVENTS=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_KEXEC=y # CONFIG_KEXEC_FILE is not set CONFIG_CRASH_DUMP=y +CONFIG_TRANS_TABLE=y # CONFIG_XEN is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_UNMAP_KERNEL_AT_EL0=y @@ -423,16 +430,15 @@ CONFIG_KUSER_HELPERS=y # CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y +CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y CONFIG_ARM64_LSE_ATOMICS=y CONFIG_ARM64_USE_LSE_ATOMICS=y -CONFIG_ARM64_VHE=y # end of ARMv8.1 architectural features # # ARMv8.2 architectural features # -CONFIG_ARM64_UAO=y # CONFIG_ARM64_PMEM is not set CONFIG_ARM64_RAS_EXTN=y CONFIG_ARM64_CNP=y @@ -459,6 +465,7 @@ CONFIG_ARM64_TLB_RANGE=y # # ARMv8.5 architectural features # +CONFIG_AS_HAS_ARMV8_5=y CONFIG_ARM64_BTI=y CONFIG_ARM64_BTI_KERNEL=y CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y @@ -468,6 +475,12 @@ CONFIG_ARM64_AS_HAS_MTE=y CONFIG_ARM64_MTE=y # end of ARMv8.5 architectural features +# +# ARMv8.7 architectural features +# +CONFIG_ARM64_EPAN=y +# end of ARMv8.7 architectural features + CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set @@ -485,8 +498,6 @@ CONFIG_CMDLINE="" # end of Boot options CONFIG_SYSVIPC_COMPAT=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management options @@ -614,7 +625,6 @@ CONFIG_CRYPTO_AES_ARM64_BS=m # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y -CONFIG_SET_FS=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -652,16 +662,23 @@ CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y @@ -676,6 +693,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -685,6 +704,8 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -706,10 +727,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y @@ -780,8 +803,6 @@ CONFIG_COREDUMP=y # # Memory Management options # -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_NEED_MULTIPLE_NODES=y CONFIG_SPARSEMEM_EXTREME=y @@ -790,14 +811,18 @@ CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_COMPACTION=y # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y @@ -811,6 +836,7 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set # CONFIG_ZBUD is not set @@ -818,11 +844,11 @@ CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y -CONFIG_FRAME_VECTOR=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options @@ -864,7 +890,7 @@ CONFIG_NET_IP_TUNNEL=y # CONFIG_IP_MROUTE is not set # CONFIG_SYN_COOKIES is not set # CONFIG_NET_IPVTI is not set -CONFIG_NET_UDP_TUNNEL=y +CONFIG_NET_UDP_TUNNEL=m CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set @@ -921,8 +947,7 @@ CONFIG_NETFILTER_FAMILY_BRIDGE=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_LOG_SYSLOG=m # CONFIG_NF_CONNTRACK_MARK is not set # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y @@ -951,6 +976,7 @@ CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1065,6 +1091,7 @@ CONFIG_IP_VS_RR=m # CONFIG_IP_VS_MH is not set # CONFIG_IP_VS_SED is not set # CONFIG_IP_VS_NQ is not set +# CONFIG_IP_VS_TWOS is not set # # IPVS SH scheduler @@ -1161,7 +1188,7 @@ CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y @@ -1243,14 +1270,15 @@ CONFIG_DNS_RESOLVER=y CONFIG_NET_L3_MASTER_DEV=y # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -CONFIG_BPF_JIT=y # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1275,6 +1303,7 @@ CONFIG_BT_HIDP=m CONFIG_BT_LE=y CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set # CONFIG_BT_SELFTEST is not set # CONFIG_BT_FEATURE_DEBUG is not set @@ -1347,7 +1376,6 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1362,10 +1390,11 @@ CONFIG_NET_9P=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1378,8 +1407,7 @@ CONFIG_HAVE_PCI=y # # Generic Driver Options # -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y @@ -1413,6 +1441,7 @@ CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_ARCH_NUMA=y # end of Generic Driver Options # @@ -1506,6 +1535,8 @@ CONFIG_MTD_CFI_I2=y # # ECC engine support # +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -1517,6 +1548,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_MTD_UBI is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y @@ -1573,7 +1607,6 @@ CONFIG_BLK_DEV_NBD=y # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1602,6 +1635,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1642,6 +1676,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_BOOT_SYSFS is not set CONFIG_SCSI_HISI_SAS=y +# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set CONFIG_SCSI_UFSHCD=m CONFIG_SCSI_UFSHCD_PLATFORM=m # CONFIG_SCSI_UFS_CDNS_PLATFORM is not set @@ -1728,7 +1763,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set CONFIG_DUMMY=m -CONFIG_WIREGUARD=y +CONFIG_WIREGUARD=m # CONFIG_WIREGUARD_DEBUG is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set @@ -1748,12 +1783,6 @@ CONFIG_TAP=m # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m # CONFIG_NLMON is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_NET_VENDOR_ALACRITECH=y CONFIG_NET_VENDOR_ALLWINNER=y @@ -1764,8 +1793,6 @@ CONFIG_NET_VENDOR_AMD=y CONFIG_AMD_XGBE=y CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_NET_VENDOR_ARC=y -CONFIG_NET_VENDOR_AURORA=y -# CONFIG_AURORA_NB8800 is not set CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_B44 is not set # CONFIG_BCMGENET is not set @@ -1791,6 +1818,7 @@ CONFIG_HNS_ENET=y CONFIG_NET_VENDOR_HUAWEI=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y +# CONFIG_NET_VENDOR_MICROSOFT is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_MVMDIO=y CONFIG_NET_VENDOR_MELLANOX=y @@ -1872,11 +1900,13 @@ CONFIG_AC200_PHY=y # CONFIG_LSI_ET1011C_PHY is not set CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m +# CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set CONFIG_AT803X_PHY=m # CONFIG_QSEMI_PHY is not set @@ -1969,6 +1999,7 @@ CONFIG_USB_NET_ZAURUS=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ATH_COMMON=m @@ -2035,6 +2066,7 @@ CONFIG_MT76_LEDS=y CONFIG_MT76_USB=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x2_COMMON=m @@ -2080,11 +2112,8 @@ CONFIG_ZD1211RW=m # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set +# CONFIG_WWAN is not set # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set @@ -2096,7 +2125,6 @@ CONFIG_NET_FAILOVER=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y @@ -2174,7 +2202,6 @@ CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_PROPERTIES=y # CONFIG_TOUCHSCREEN_ADS7846 is not set # CONFIG_TOUCHSCREEN_AD7877 is not set # CONFIG_TOUCHSCREEN_AD7879 is not set @@ -2199,7 +2226,9 @@ CONFIG_TOUCHSCREEN_ATMEL_MXT=m # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_EKTF2127 is not set @@ -2211,6 +2240,7 @@ CONFIG_TOUCHSCREEN_ATMEL_MXT=m # CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set # CONFIG_TOUCHSCREEN_INEXIO is not set @@ -2265,9 +2295,11 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_RK805_PWRKEY is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -2360,9 +2392,9 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set @@ -2376,7 +2408,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y @@ -2394,6 +2425,7 @@ CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set # CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C_CR50 is not set # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_I2C_NUVOTON is not set @@ -2459,6 +2491,7 @@ CONFIG_I2C_RK3X=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2545,6 +2578,7 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +CONFIG_PTP_1588_CLOCK_KVM=y # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support @@ -2564,6 +2598,7 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y # CONFIG_PINCTRL_RK805 is not set # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # # Renesas pinctrl drivers @@ -2592,6 +2627,8 @@ CONFIG_PINCTRL_SUN50I_A64_R=y CONFIG_PINCTRL_SUN50I_H5=y CONFIG_PINCTRL_SUN50I_H6=y CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_PINCTRL_SUN50I_H616=y +CONFIG_PINCTRL_SUN50I_H616_R=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y @@ -2661,14 +2698,20 @@ CONFIG_GPIO_MAX77620=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set CONFIG_POWER_RESET=y CONFIG_POWER_RESET_BRCMSTB=y # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set # CONFIG_POWER_RESET_RESTART is not set CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_RESET_XGENE=y @@ -2704,6 +2747,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set @@ -2712,9 +2756,10 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_BATTERY_RT5033 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set @@ -2740,6 +2785,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2747,6 +2793,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set @@ -2769,6 +2816,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2776,6 +2824,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2790,6 +2839,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2816,10 +2866,12 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2978,6 +3030,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_RT5033 is not set @@ -2988,7 +3041,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set # CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y @@ -3028,8 +3080,10 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set CONFIG_MFD_VEXPRESS_SYSREG=y # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set @@ -3044,6 +3098,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_AXP20X=y +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set CONFIG_REGULATOR_FAN53555=y @@ -3073,6 +3128,7 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -3400,7 +3456,9 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3408,6 +3466,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3418,6 +3477,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3435,12 +3495,13 @@ CONFIG_VIDEO_MT9V011=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3601,6 +3662,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m # # ISDB-T (terrestrial) frontends @@ -3694,6 +3756,7 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set @@ -3723,9 +3786,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_DISPLAY_CONNECTOR=y +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3748,6 +3814,7 @@ CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_ANALOGIX_ANX6345=m # CONFIG_DRM_ANALOGIX_ANX78XX is not set CONFIG_DRM_ANALOGIX_DP=m +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y @@ -3757,9 +3824,9 @@ CONFIG_DRM_DW_HDMI_CEC=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set @@ -3773,6 +3840,7 @@ CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3909,6 +3977,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -3928,6 +3997,8 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -3957,13 +4028,14 @@ CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -4031,14 +4103,16 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set # CONFIG_SND_SOC_SPDIF is not set # CONFIG_SND_SOC_SSM2305 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set @@ -4062,7 +4136,8 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set @@ -4097,11 +4172,16 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y @@ -4147,6 +4227,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set CONFIG_HID_GLORIOUS=m @@ -4191,11 +4272,13 @@ CONFIG_HID_PENMOUNT=m CONFIG_HID_PETALYNX=m # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set CONFIG_HID_SAMSUNG=m +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=m CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -4233,7 +4316,8 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -CONFIG_I2C_HID=m +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4322,7 +4406,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -4437,10 +4521,6 @@ CONFIG_USB_SNP_CORE=y CONFIG_USB_SNP_UDC_PLAT=y # CONFIG_USB_M66592 is not set CONFIG_USB_BDC_UDC=y - -# -# Platform Support -# # CONFIG_USB_NET2272 is not set # CONFIG_USB_GADGET_XILINX is not set # CONFIG_USB_MAX3420_UDC is not set @@ -4564,6 +4644,10 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set +# +# Flash and Torch LED drivers +# + # # LED Triggers # @@ -4588,6 +4672,7 @@ CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -4660,7 +4745,6 @@ CONFIG_RTC_DRV_S5M=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -4674,6 +4758,7 @@ CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232_HWMON=y # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -4707,6 +4792,7 @@ CONFIG_RTC_DRV_SUN6I=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -4749,6 +4835,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -4769,9 +4856,9 @@ CONFIG_DMABUF_HEAPS_CMA=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m # CONFIG_R8712U is not set @@ -4805,7 +4892,6 @@ CONFIG_RTL8723BS=m # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -4851,12 +4937,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set @@ -4880,7 +4960,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_COMMON_CLK_S2MPS11 is not set -# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_XGENE is not set CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_VC5 is not set @@ -4891,11 +4971,13 @@ CONFIG_SUN50I_A64_CCU=y # CONFIG_SUN50I_A100_CCU is not set # CONFIG_SUN50I_A100_R_CCU is not set CONFIG_SUN50I_H6_CCU=y +CONFIG_SUN50I_H616_CCU=y CONFIG_SUN50I_H6_R_CCU=y # CONFIG_SUN8I_A83T_CCU is not set CONFIG_SUN8I_H3_CCU=y CONFIG_SUN8I_DE2_CCU=y CONFIG_SUN8I_R_CCU=y +# CONFIG_XILINX_VCU is not set CONFIG_HWSPINLOCK=y # @@ -4915,6 +4997,7 @@ CONFIG_SUN50I_ERRATUM_UNKNOWN1=y CONFIG_MAILBOX=y CONFIG_ARM_MHU=y +# CONFIG_ARM_MHU_V2 is not set CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set # CONFIG_ALTERA_MBOX is not set @@ -4952,6 +5035,7 @@ CONFIG_IOMMU_DMA=y # CONFIG_RPMSG=y # CONFIG_RPMSG_CHAR is not set +# CONFIG_RPMSG_NS is not set CONFIG_RPMSG_QCOM_GLINK=y CONFIG_RPMSG_QCOM_GLINK_RPM=y # CONFIG_RPMSG_VIRTIO is not set @@ -4968,11 +5052,6 @@ CONFIG_RPMSG_QCOM_GLINK_RPM=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -4991,18 +5070,24 @@ CONFIG_SOC_BRCMSTB=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # # end of Qualcomm SoC drivers +CONFIG_SUNXI_MBUS=y CONFIG_SUNXI_SRAM=y CONFIG_SOC_TI=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5034,6 +5119,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y +# CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set CONFIG_IIO=y @@ -5064,6 +5150,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set @@ -5108,7 +5195,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set -# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_AXP20X_ADC is not set # CONFIG_AXP288_ADC is not set @@ -5144,6 +5230,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set @@ -5162,6 +5249,12 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -5182,6 +5275,11 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -5207,6 +5305,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5377,6 +5476,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5489,6 +5589,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SUN4I=y @@ -5568,6 +5669,7 @@ CONFIG_RAS=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_SUNXI_SID=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -5633,6 +5735,7 @@ CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_FS_LZORLE=y # CONFIG_FS_DAX is not set @@ -5709,9 +5812,10 @@ CONFIG_PROC_PAGE_MONITOR=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_TMPFS_XATTR is not set +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_INODE64 is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -5754,6 +5858,7 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -5781,7 +5886,7 @@ CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y CONFIG_PNFS_BLOCK=m -CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" # CONFIG_NFS_V4_1_MIGRATION is not set CONFIG_NFS_V4_SECURITY_LABEL=y @@ -5795,6 +5900,7 @@ CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -5808,6 +5914,7 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set @@ -5896,6 +6003,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set # CONFIG_IMA is not set @@ -5962,6 +6070,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -6014,17 +6123,13 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -6041,7 +6146,6 @@ CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set CONFIG_CRYPTO_CHACHA20=m # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -6132,6 +6236,8 @@ CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking +CONFIG_BINARY_PRINTF=y + # # Library routines # @@ -6144,6 +6250,7 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6174,9 +6281,10 @@ CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_COMPRESS=m CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y @@ -6222,6 +6330,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -6246,6 +6355,8 @@ CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -6272,10 +6383,12 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set # CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set # CONFIG_DEBUG_INFO_BTF is not set +CONFIG_PAHOLE_HAS_SPLIT_BTF=y # CONFIG_GDB_SCRIPTS is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -6335,9 +6448,13 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6385,10 +6502,10 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y # # Debug kernel data structures @@ -6427,7 +6544,6 @@ CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y # CONFIG_IO_STRICT_DEVMEM is not set @@ -6453,6 +6569,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set +# CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set @@ -6487,6 +6604,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index 9e8fbbe979..e97659544e 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,12 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.53 Kernel Configuration +# Linux/arm 5.13.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=100200 -CONFIG_LD_VERSION=235010000 CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23501 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23501 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -84,6 +87,18 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -149,6 +164,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -182,7 +198,6 @@ CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -209,10 +224,9 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set @@ -229,7 +243,6 @@ CONFIG_PERF_EVENTS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -265,7 +278,6 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_IOP32X is not set @@ -322,7 +334,6 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_SOC_DRA7XX is not set # end of TI OMAP/AM/DM/DRA Family -# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set @@ -330,7 +341,7 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set @@ -342,13 +353,11 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN8I=y # CONFIG_MACH_SUN9I is not set CONFIG_ARCH_SUNXI_MC_SMP=y -# CONFIG_ARCH_TANGO is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQ is not set # @@ -458,7 +467,6 @@ CONFIG_AEABI=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y @@ -602,8 +610,9 @@ CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=y CONFIG_CRYPTO_SHA256_ARM=y CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_BLAKE2S_ARM=y CONFIG_CRYPTO_AES_ARM=y -# CONFIG_CRYPTO_CHACHA20_NEON is not set +CONFIG_CRYPTO_CHACHA20_NEON=y CONFIG_CRYPTO_POLY1305_ARM=y CONFIG_AS_VFP_VMRS_FPINST=y @@ -611,7 +620,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y # General architecture-dependent options # CONFIG_SET_FS=y -CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y @@ -635,13 +643,16 @@ CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_STACKPROTECTOR=y # CONFIG_STACKPROTECTOR is not set +CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -665,6 +676,7 @@ CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling @@ -686,9 +698,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -795,6 +810,7 @@ CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 # CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set @@ -802,9 +818,9 @@ CONFIG_CMA_AREAS=7 # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +CONFIG_KMAP_LOCAL=y # end of Memory Management options CONFIG_NET=y @@ -846,7 +862,7 @@ CONFIG_IP_MROUTE=y # CONFIG_IP_PIMSM_V2 is not set # CONFIG_SYN_COOKIES is not set # CONFIG_NET_IPVTI is not set -CONFIG_NET_UDP_TUNNEL=y +CONFIG_NET_UDP_TUNNEL=m CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set @@ -898,7 +914,7 @@ CONFIG_NETFILTER_FAMILY_BRIDGE=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m -# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_LOG_SYSLOG is not set # CONFIG_NF_CONNTRACK_MARK is not set # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y @@ -1036,6 +1052,7 @@ CONFIG_IP_VS_RR=m # CONFIG_IP_VS_MH is not set # CONFIG_IP_VS_SED is not set # CONFIG_IP_VS_NQ is not set +# CONFIG_IP_VS_TWOS is not set # # IPVS SH scheduler @@ -1105,7 +1122,7 @@ CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set @@ -1187,14 +1204,15 @@ CONFIG_DNS_RESOLVER=y CONFIG_NET_L3_MASTER_DEV=y # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1219,6 +1237,7 @@ CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set # CONFIG_BT_SELFTEST is not set # CONFIG_BT_FEATURE_DEBUG is not set @@ -1292,7 +1311,6 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # CONFIG_CAIF is not set @@ -1303,10 +1321,11 @@ CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y # CONFIG_FAILOVER is not set CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1318,8 +1337,7 @@ CONFIG_HAVE_PCI=y # # Generic Driver Options # -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y @@ -1428,7 +1446,6 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set # @@ -1455,6 +1472,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_ALTERA_STAPL is not set # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1571,7 +1589,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set CONFIG_DUMMY=m -CONFIG_WIREGUARD=y +CONFIG_WIREGUARD=m # CONFIG_WIREGUARD_DEBUG is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set @@ -1593,12 +1611,6 @@ CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m # CONFIG_NLMON is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_NET_VENDOR_ALACRITECH=y CONFIG_NET_VENDOR_ALLWINNER=y @@ -1607,7 +1619,6 @@ CONFIG_SUN4I_EMAC=y CONFIG_NET_VENDOR_AMAZON=y CONFIG_NET_VENDOR_AQUANTIA=y # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set @@ -1628,6 +1639,7 @@ CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HNS_ENET is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1694,11 +1706,13 @@ CONFIG_FIXED_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_MICROCHIP_T1_PHY=y # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set @@ -1797,8 +1811,8 @@ CONFIG_USB_IPHETH=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ATH_COMMON=m CONFIG_WLAN_VENDOR_ATH=y @@ -1877,6 +1891,7 @@ CONFIG_MT76_LEDS=y CONFIG_MT76_USB=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x2_COMMON=m @@ -1924,11 +1939,8 @@ CONFIG_ZD1211RW=m # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set +# CONFIG_WWAN is not set # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set @@ -1940,7 +1952,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set @@ -2040,9 +2051,11 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -2131,7 +2144,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set @@ -2145,7 +2157,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y @@ -2158,7 +2169,6 @@ CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set @@ -2215,6 +2225,7 @@ CONFIG_I2C_MV64XXX=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2298,6 +2309,7 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +CONFIG_PTP_1588_CLOCK_KVM=y # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support @@ -2313,6 +2325,7 @@ CONFIG_PINCTRL_AXP209=y # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # # Renesas pinctrl drivers @@ -2341,6 +2354,8 @@ CONFIG_PINCTRL_SUN8I_H3_R=y # CONFIG_PINCTRL_SUN50I_H5 is not set # CONFIG_PINCTRL_SUN50I_H6 is not set # CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 @@ -2408,8 +2423,13 @@ CONFIG_GPIO_CDEV_V1=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y @@ -2439,6 +2459,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set @@ -2447,9 +2468,10 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_BATTERY_RT5033 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set @@ -2475,12 +2497,14 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set @@ -2503,6 +2527,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2510,6 +2535,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2524,6 +2550,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2550,10 +2577,12 @@ CONFIG_HWMON=y # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2718,6 +2747,7 @@ CONFIG_MFD_AXP20X_RSB=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set @@ -2729,7 +2759,6 @@ CONFIG_MFD_AXP20X_RSB=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SUN6I_PRCM=y CONFIG_MFD_SYSCON=y @@ -2772,8 +2801,10 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -2787,6 +2818,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_AXP20X=y +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set @@ -2813,6 +2845,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -3224,7 +3257,9 @@ CONFIG_VIDEO_ST_MIPID02=m # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3232,6 +3267,7 @@ CONFIG_VIDEO_ST_MIPID02=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3242,6 +3278,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3259,12 +3296,13 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3457,6 +3495,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +# CONFIG_DVB_MXL692 is not set # # ISDB-T (terrestrial) frontends @@ -3577,6 +3616,7 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set @@ -3600,9 +3640,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3624,6 +3667,7 @@ CONFIG_DRM_SIMPLE_BRIDGE=m # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y @@ -3634,8 +3678,8 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_STI is not set # CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set @@ -3651,6 +3695,7 @@ CONFIG_DRM_LIMA=m # CONFIG_DRM_PANFROST is not set # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3760,6 +3805,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -3779,6 +3825,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -3807,13 +3854,14 @@ CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -3881,14 +3929,16 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SSM2305 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set @@ -3912,7 +3962,8 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set @@ -3947,11 +3998,16 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y @@ -3997,6 +4053,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set CONFIG_HID_GLORIOUS=m @@ -4041,11 +4098,13 @@ CONFIG_HID_PENMOUNT=m CONFIG_HID_PETALYNX=m # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set CONFIG_HID_SAMSUNG=m +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=m CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -4083,7 +4142,8 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4170,7 +4230,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -4236,7 +4296,6 @@ CONFIG_USB_SERIAL=m # CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_SERIAL_OPTICON is not set @@ -4245,6 +4304,7 @@ CONFIG_USB_SERIAL=m # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -4413,6 +4473,10 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set +# +# Flash and Torch LED drivers +# + # # LED Triggers # @@ -4436,6 +4500,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -4505,7 +4570,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -4518,6 +4582,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -4550,6 +4615,7 @@ CONFIG_RTC_DRV_SUN6I=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -4585,6 +4651,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -4605,9 +4672,9 @@ CONFIG_DMABUF_HEAPS_CMA=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTLLIB is not set # CONFIG_RTL8723BS is not set # CONFIG_R8712U is not set @@ -4641,7 +4708,6 @@ CONFIG_STAGING=y # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -4687,12 +4753,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set @@ -4712,7 +4772,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set @@ -4730,6 +4790,7 @@ CONFIG_SUN8I_H3_CCU=y CONFIG_SUN8I_DE2_CCU=y CONFIG_SUN8I_R40_CCU=y CONFIG_SUN8I_R_CCU=y +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -4770,11 +4831,6 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -4793,18 +4849,24 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # # end of Qualcomm SoC drivers +CONFIG_SUNXI_MBUS=y CONFIG_SUNXI_SRAM=y # CONFIG_SOC_TI is not set # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -4836,6 +4898,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y @@ -4864,6 +4927,7 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set @@ -4908,7 +4972,6 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set -# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set CONFIG_AXP20X_ADC=y # CONFIG_AXP288_ADC is not set @@ -4945,6 +5008,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set @@ -4963,6 +5027,12 @@ CONFIG_SUN4I_GPADC=y # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -4983,6 +5053,11 @@ CONFIG_SUN4I_GPADC=y # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -5008,6 +5083,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5178,6 +5254,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5283,6 +5360,7 @@ CONFIG_SUN4I_GPADC=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SUN4I=y @@ -5310,7 +5388,6 @@ CONFIG_RESET_SUNXI=y # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y -# CONFIG_USB_LGM_PHY is not set CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN6I_MIPI_DPHY=y CONFIG_PHY_SUN9I_USB=y @@ -5352,6 +5429,7 @@ CONFIG_ARM_PMU=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_SUNXI_SID=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -5424,6 +5502,7 @@ CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_FS_LZORLE=y CONFIG_FS_POSIX_ACL=y @@ -5438,8 +5517,8 @@ CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m # CONFIG_CUSE is not set # CONFIG_VIRTIO_FS is not set @@ -5542,7 +5621,7 @@ CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y CONFIG_PNFS_BLOCK=m -CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_NFS_V4_1_MIGRATION=y CONFIG_ROOT_NFS=y @@ -5556,6 +5635,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -5570,6 +5650,7 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set @@ -5704,6 +5785,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -5756,17 +5838,13 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -5783,7 +5861,6 @@ CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -5824,9 +5901,9 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y CONFIG_CRYPTO_LIB_CHACHA=y CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y CONFIG_CRYPTO_LIB_CURVE25519=y @@ -5840,6 +5917,7 @@ CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ALLWINNER=y CONFIG_CRYPTO_DEV_SUN4I_SS=m # CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG is not set +# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set CONFIG_CRYPTO_DEV_SUN8I_CE=m # CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y @@ -5872,6 +5950,8 @@ CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking +CONFIG_BINARY_PRINTF=y + # # Library routines # @@ -5908,11 +5988,12 @@ CONFIG_XXHASH=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_LZO_COMPRESS=y +CONFIG_LZO_COMPRESS=m CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_COMPRESS=m CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y @@ -5950,6 +6031,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -5973,6 +6055,8 @@ CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -5996,7 +6080,6 @@ CONFIG_SYMBOLIC_ERRNAME=y # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -6004,6 +6087,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -6047,9 +6131,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set +CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6094,6 +6181,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -6135,7 +6223,6 @@ CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # @@ -6167,6 +6254,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set +# CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set @@ -6201,6 +6289,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking diff --git a/projects/Allwinner/patches/linux/crust/0001-Input-axp20x-pek-allow-wakeup-after-shutdown.patch b/projects/Allwinner/patches/linux/0001-Input-axp20x-pek-allow-wakeup-after-shutdown.patch similarity index 100% rename from projects/Allwinner/patches/linux/crust/0001-Input-axp20x-pek-allow-wakeup-after-shutdown.patch rename to projects/Allwinner/patches/linux/0001-Input-axp20x-pek-allow-wakeup-after-shutdown.patch diff --git a/projects/Allwinner/patches/linux/0001-media-cedrus-Add-support-for-R40.patch b/projects/Allwinner/patches/linux/0001-media-cedrus-Add-support-for-R40.patch deleted file mode 100644 index 37665933e4..0000000000 --- a/projects/Allwinner/patches/linux/0001-media-cedrus-Add-support-for-R40.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 9a7e6c2d8a18a24b013c1ad165ed04bb7d2c7716 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 25 Aug 2020 19:35:22 +0200 -Subject: [PATCH 01/44] media: cedrus: Add support for R40 - -Video engine in R40 is very similar to that in A33 but it runs on lower -speed, at least according to OS images released by board designer. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/20200825173523.1289379-5-jernej.skrabec@siol.net ---- - drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -508,6 +508,11 @@ static const struct cedrus_variant sun8i - .mod_rate = 402000000, - }; - -+static const struct cedrus_variant sun8i_r40_cedrus_variant = { -+ .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .mod_rate = 297000000, -+}; -+ - static const struct cedrus_variant sun50i_a64_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED | - CEDRUS_CAPABILITY_H265_DEC, -@@ -549,6 +554,10 @@ static const struct of_device_id cedrus_ - .data = &sun8i_h3_cedrus_variant, - }, - { -+ .compatible = "allwinner,sun8i-r40-video-engine", -+ .data = &sun8i_r40_cedrus_variant, -+ }, -+ { - .compatible = "allwinner,sun50i-a64-video-engine", - .data = &sun50i_a64_cedrus_variant, - }, diff --git a/projects/Allwinner/patches/linux/crust/0024-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch b/projects/Allwinner/patches/linux/0002-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch similarity index 98% rename from projects/Allwinner/patches/linux/crust/0024-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch rename to projects/Allwinner/patches/linux/0002-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch index 34eb616053..8ac83e1b33 100644 --- a/projects/Allwinner/patches/linux/crust/0024-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch +++ b/projects/Allwinner/patches/linux/0002-clk-Implement-protected-clocks-for-all-OF-clock-prov.patch @@ -139,8 +139,8 @@ Signed-off-by: Samuel Holland return rc; --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c -@@ -4188,6 +4188,37 @@ void devm_clk_hw_unregister(struct devic - EXPORT_SYMBOL_GPL(devm_clk_hw_unregister); +@@ -4271,6 +4271,37 @@ struct clk *devm_clk_hw_get_clk(struct d + EXPORT_SYMBOL_GPL(devm_clk_hw_get_clk); /* + * clk-conf helpers diff --git a/projects/Allwinner/patches/linux/0002-media-sunxi-cir-allow-timeout-to-be-set-at-runtime.patch b/projects/Allwinner/patches/linux/0002-media-sunxi-cir-allow-timeout-to-be-set-at-runtime.patch deleted file mode 100644 index 602c26a462..0000000000 --- a/projects/Allwinner/patches/linux/0002-media-sunxi-cir-allow-timeout-to-be-set-at-runtime.patch +++ /dev/null @@ -1,99 +0,0 @@ -From f710d6403b7716d7a5319e51c4cb3c217ec85b73 Mon Sep 17 00:00:00 2001 -From: Sean Young -Date: Tue, 10 Nov 2020 09:30:38 +0100 -Subject: [PATCH 02/44] media: sunxi-cir: allow timeout to be set at runtime - -This allows the timeout to be set with the LIRC_SET_REC_TIMEOUT ioctl. - -The timeout was hardcoded at just over 20ms, but returned 120ms when -queried with the LIRC_GET_REC_TIMEOUT ioctl. - -This also ensures the idle threshold is set correctly with a base clock -other than 8Mhz. - -Acked-by: Maxime Ripard -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/rc/sunxi-cir.c | 48 ++++++++++++++++++++++++++++++------ - 1 file changed, 40 insertions(+), 8 deletions(-) - ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -73,10 +73,6 @@ - #define SUNXI_IR_BASE_CLK 8000000 - /* Noise threshold in samples */ - #define SUNXI_IR_RXNOISE 1 --/* Idle Threshold in samples */ --#define SUNXI_IR_RXIDLE 20 --/* Time after which device stops sending data in ms */ --#define SUNXI_IR_TIMEOUT 120 - - /** - * struct sunxi_ir_quirks - Differences between SoC variants. -@@ -146,6 +142,41 @@ static irqreturn_t sunxi_ir_irq(int irqn - return IRQ_HANDLED; - } - -+/* Convert idle threshold to usec */ -+static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr) -+{ -+ return DIV_ROUND_CLOSEST(USEC_PER_SEC * (ithr + 1), -+ base_clk / (128 * 64)); -+} -+ -+/* Convert usec to idle threshold */ -+static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec) -+{ -+ /* make sure we don't end up with a timeout less than requested */ -+ return DIV_ROUND_UP((base_clk / (128 * 64)) * usec, USEC_PER_SEC) - 1; -+} -+ -+static int sunxi_ir_set_timeout(struct rc_dev *rc_dev, unsigned int timeout) -+{ -+ struct sunxi_ir *ir = rc_dev->priv; -+ unsigned int base_clk = clk_get_rate(ir->clk); -+ unsigned long flags; -+ -+ unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout); -+ -+ dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr); -+ -+ spin_lock_irqsave(&ir->ir_lock, flags); -+ /* Set noise threshold and idle threshold */ -+ writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr), -+ ir->base + SUNXI_IR_CIR_REG); -+ spin_unlock_irqrestore(&ir->ir_lock, flags); -+ -+ rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr); -+ -+ return 0; -+} -+ - static int sunxi_ir_probe(struct platform_device *pdev) - { - int ret = 0; -@@ -242,9 +273,11 @@ static int sunxi_ir_probe(struct platfor - ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY; - ir->rc->dev.parent = dev; - ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; -- /* Frequency after IR internal divider with sample period in ns */ -+ /* Frequency after IR internal divider with sample period in us */ - ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64)); -- ir->rc->timeout = MS_TO_US(SUNXI_IR_TIMEOUT); -+ ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0); -+ ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255); -+ ir->rc->s_timeout = sunxi_ir_set_timeout; - ir->rc->driver_name = SUNXI_IR_DEV; - - ret = rc_register_device(ir->rc); -@@ -272,8 +305,7 @@ static int sunxi_ir_probe(struct platfor - writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); - - /* Set noise threshold and idle threshold */ -- writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE), -- ir->base + SUNXI_IR_CIR_REG); -+ sunxi_ir_set_timeout(ir->rc, IR_DEFAULT_TIMEOUT); - - /* Invert Input Signal */ - writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); diff --git a/projects/Allwinner/patches/linux/0003-ASoC-sun4i-i2s-Change-set_chan_cfg-params.patch b/projects/Allwinner/patches/linux/0003-ASoC-sun4i-i2s-Change-set_chan_cfg-params.patch deleted file mode 100644 index 5cb7c89a06..0000000000 --- a/projects/Allwinner/patches/linux/0003-ASoC-sun4i-i2s-Change-set_chan_cfg-params.patch +++ /dev/null @@ -1,118 +0,0 @@ -From a8bdfe3893f9b226492dac4b4e0d37a27dbee201 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Fri, 30 Oct 2020 15:46:35 +0100 -Subject: [PATCH 03/44] ASoC: sun4i-i2s: Change set_chan_cfg() params -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -As slots and slot_width can be set manually using set_tdm(). -These values are then kept in sun4i_i2s struct. -So we need to check if these values are set or not. - -This is not done actually and will trigger a bug. -For example, if we set to the simple soundcard in the device-tree -dai-tdm-slot-width = <32> and then start a stream using S16_LE, -currently we would calculate BCLK for 32-bit slots, but program -lrck_period for 16-bit slots, making the sample rate double what we -expected. - -To fix this, we need to check if these values are set or not but as -this logic is already done by the caller. Avoid duplicating this -logic and just pass the required values as params to set_chan_cfg(). - -Suggested-by: Samuel Holland -Acked-by: Maxime Ripard -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-3-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 32 ++++++++++++++++++-------------- - 1 file changed, 18 insertions(+), 14 deletions(-) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -162,8 +162,15 @@ struct sun4i_i2s_quirks { - unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *); - s8 (*get_sr)(const struct sun4i_i2s *, int); - s8 (*get_wss)(const struct sun4i_i2s *, int); -- int (*set_chan_cfg)(const struct sun4i_i2s *, -- const struct snd_pcm_hw_params *); -+ -+ /* -+ * In the set_chan_cfg() function pointer: -+ * @slots: channels per frame + padding slots, regardless of format -+ * @slot_width: bits per sample + padding bits, regardless of format -+ */ -+ int (*set_chan_cfg)(const struct sun4i_i2s *i2s, -+ unsigned int channels, unsigned int slots, -+ unsigned int slot_width); - int (*set_fmt)(const struct sun4i_i2s *, unsigned int); - }; - -@@ -399,10 +406,9 @@ static s8 sun8i_i2s_get_sr_wss(const str - } - - static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, -- const struct snd_pcm_hw_params *params) -+ unsigned int channels, unsigned int slots, -+ unsigned int slot_width) - { -- unsigned int channels = params_channels(params); -- - /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); - regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); -@@ -419,15 +425,11 @@ static int sun4i_i2s_set_chan_cfg(const - } - - static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, -- const struct snd_pcm_hw_params *params) -+ unsigned int channels, unsigned int slots, -+ unsigned int slot_width) - { -- unsigned int channels = params_channels(params); -- unsigned int slots = channels; - unsigned int lrck_period; - -- if (i2s->slots) -- slots = i2s->slots; -- - /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); - regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); -@@ -450,13 +452,13 @@ static int sun8i_i2s_set_chan_cfg(const - switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_DSP_A: - case SND_SOC_DAIFMT_DSP_B: -- lrck_period = params_physical_width(params) * slots; -+ lrck_period = slot_width * slots; - break; - - case SND_SOC_DAIFMT_LEFT_J: - case SND_SOC_DAIFMT_RIGHT_J: - case SND_SOC_DAIFMT_I2S: -- lrck_period = params_physical_width(params); -+ lrck_period = slot_width; - break; - - default: -@@ -482,7 +484,9 @@ static int sun4i_i2s_hw_params(struct sn - unsigned int word_size = params_width(params); - unsigned int slot_width = params_physical_width(params); - unsigned int channels = params_channels(params); -+ - unsigned int slots = channels; -+ - int ret, sr, wss; - u32 width; - -@@ -492,7 +496,7 @@ static int sun4i_i2s_hw_params(struct sn - if (i2s->slot_width) - slot_width = i2s->slot_width; - -- ret = i2s->variant->set_chan_cfg(i2s, params); -+ ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width); - if (ret < 0) { - dev_err(dai->dev, "Invalid channel configuration\n"); - return ret; diff --git a/projects/Allwinner/patches/linux/crust/0025-Revert-clk-qcom-Support-protected-clocks-property.patch b/projects/Allwinner/patches/linux/0003-Revert-clk-qcom-Support-protected-clocks-property.patch similarity index 100% rename from projects/Allwinner/patches/linux/crust/0025-Revert-clk-qcom-Support-protected-clocks-property.patch rename to projects/Allwinner/patches/linux/0003-Revert-clk-qcom-Support-protected-clocks-property.patch diff --git a/projects/Allwinner/patches/linux/0004-ASoC-sun4i-i2s-Add-support-for-H6-I2S.patch b/projects/Allwinner/patches/linux/0004-ASoC-sun4i-i2s-Add-support-for-H6-I2S.patch deleted file mode 100644 index a1c67052ce..0000000000 --- a/projects/Allwinner/patches/linux/0004-ASoC-sun4i-i2s-Add-support-for-H6-I2S.patch +++ /dev/null @@ -1,295 +0,0 @@ -From 8ff0df5dffe58a2d1595a6e59ccd5ce63d6bf0e5 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 30 Oct 2020 15:46:36 +0100 -Subject: [PATCH 04/44] ASoC: sun4i-i2s: Add support for H6 I2S -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 I2S is very similar to that in H3, except it supports up to 16 -channels. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Marcus Cooper -Reviewed-by: Chen-Yu Tsai -Acked-by: Maxime Ripard -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-4-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 222 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 222 insertions(+) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -124,6 +124,21 @@ - #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 - #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 - -+/* Defines required for sun50i-h6 support */ -+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20) -+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20) -+#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16) -+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16) -+#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0) -+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1)) -+ -+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44 -+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48 -+ -+#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64 -+#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68 -+#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C -+ - struct sun4i_i2s; - - /** -@@ -476,6 +491,60 @@ static int sun8i_i2s_set_chan_cfg(const - return 0; - } - -+static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, -+ unsigned int channels, unsigned int slots, -+ unsigned int slot_width) -+{ -+ unsigned int lrck_period; -+ -+ /* Map the channels for playback and capture */ -+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98); -+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210); -+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); -+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); -+ -+ /* Configure the channels */ -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK, -+ SUN50I_H6_I2S_TX_CHAN_SEL(channels)); -+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, -+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK, -+ SUN50I_H6_I2S_TX_CHAN_SEL(channels)); -+ -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, -+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, -+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, -+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, -+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); -+ -+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_DSP_A: -+ case SND_SOC_DAIFMT_DSP_B: -+ lrck_period = slot_width * slots; -+ break; -+ -+ case SND_SOC_DAIFMT_LEFT_J: -+ case SND_SOC_DAIFMT_RIGHT_J: -+ case SND_SOC_DAIFMT_I2S: -+ lrck_period = slot_width; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, -+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, -+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period)); -+ -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -+ SUN50I_H6_I2S_TX_CHAN_EN_MASK, -+ SUN50I_H6_I2S_TX_CHAN_EN(channels)); -+ -+ return 0; -+} -+ - static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) -@@ -703,6 +772,108 @@ static int sun8i_i2s_set_soc_fmt(const s - return 0; - } - -+static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, -+ unsigned int fmt) -+{ -+ u32 mode, val; -+ u8 offset; -+ -+ /* -+ * DAI clock polarity -+ * -+ * The setup for LRCK contradicts the datasheet, but under a -+ * scope it's clear that the LRCK polarity is reversed -+ * compared to the expected polarity on the bus. -+ */ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_IB_IF: -+ /* Invert both clocks */ -+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_IB_NF: -+ /* Invert bit clock */ -+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | -+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_NB_IF: -+ /* Invert frame clock */ -+ val = 0; -+ break; -+ case SND_SOC_DAIFMT_NB_NF: -+ val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, -+ SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK | -+ SUN8I_I2S_FMT0_BCLK_POLARITY_MASK, -+ val); -+ -+ /* DAI Mode */ -+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_DSP_A: -+ mode = SUN8I_I2S_CTRL_MODE_PCM; -+ offset = 1; -+ break; -+ -+ case SND_SOC_DAIFMT_DSP_B: -+ mode = SUN8I_I2S_CTRL_MODE_PCM; -+ offset = 0; -+ break; -+ -+ case SND_SOC_DAIFMT_I2S: -+ mode = SUN8I_I2S_CTRL_MODE_LEFT; -+ offset = 1; -+ break; -+ -+ case SND_SOC_DAIFMT_LEFT_J: -+ mode = SUN8I_I2S_CTRL_MODE_LEFT; -+ offset = 0; -+ break; -+ -+ case SND_SOC_DAIFMT_RIGHT_J: -+ mode = SUN8I_I2S_CTRL_MODE_RIGHT; -+ offset = 0; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, -+ SUN8I_I2S_CTRL_MODE_MASK, mode); -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK, -+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset)); -+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, -+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK, -+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset)); -+ -+ /* DAI clock master masks */ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBS_CFS: -+ /* BCLK and LRCLK master */ -+ val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT; -+ break; -+ -+ case SND_SOC_DAIFMT_CBM_CFM: -+ /* BCLK and LRCLK slave */ -+ val = 0; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, -+ SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, -+ val); -+ -+ return 0; -+} -+ - static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -@@ -983,6 +1154,22 @@ static const struct reg_default sun8i_i2 - { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, - }; - -+static const struct reg_default sun50i_h6_i2s_reg_defaults[] = { -+ { SUN4I_I2S_CTRL_REG, 0x00060000 }, -+ { SUN4I_I2S_FMT0_REG, 0x00000033 }, -+ { SUN4I_I2S_FMT1_REG, 0x00000030 }, -+ { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, -+ { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, -+ { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, -+ { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, -+ { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, -+ { SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0x00000000 }, -+ { SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x00000000 }, -+ { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 }, -+ { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 }, -+ { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 }, -+}; -+ - static const struct regmap_config sun4i_i2s_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -1010,6 +1197,19 @@ static const struct regmap_config sun8i_ - .volatile_reg = sun8i_i2s_volatile_reg, - }; - -+static const struct regmap_config sun50i_h6_i2s_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = SUN50I_H6_I2S_RX_CHAN_MAP1_REG, -+ .cache_type = REGCACHE_FLAT, -+ .reg_defaults = sun50i_h6_i2s_reg_defaults, -+ .num_reg_defaults = ARRAY_SIZE(sun50i_h6_i2s_reg_defaults), -+ .writeable_reg = sun4i_i2s_wr_reg, -+ .readable_reg = sun8i_i2s_rd_reg, -+ .volatile_reg = sun8i_i2s_volatile_reg, -+}; -+ - static int sun4i_i2s_runtime_resume(struct device *dev) - { - struct sun4i_i2s *i2s = dev_get_drvdata(dev); -@@ -1168,6 +1368,24 @@ static const struct sun4i_i2s_quirks sun - .set_fmt = sun4i_i2s_set_soc_fmt, - }; - -+static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = { -+ .has_reset = true, -+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, -+ .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config, -+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), -+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), -+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), -+ .bclk_dividers = sun8i_i2s_clk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -+ .mclk_dividers = sun8i_i2s_clk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, -+ .get_sr = sun8i_i2s_get_sr_wss, -+ .get_wss = sun8i_i2s_get_sr_wss, -+ .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg, -+ .set_fmt = sun50i_h6_i2s_set_soc_fmt, -+}; -+ - static int sun4i_i2s_init_regmap_fields(struct device *dev, - struct sun4i_i2s *i2s) - { -@@ -1337,6 +1555,10 @@ static const struct of_device_id sun4i_i - .compatible = "allwinner,sun50i-a64-codec-i2s", - .data = &sun50i_a64_codec_i2s_quirks, - }, -+ { -+ .compatible = "allwinner,sun50i-h6-i2s", -+ .data = &sun50i_h6_i2s_quirks, -+ }, - {} - }; - MODULE_DEVICE_TABLE(of, sun4i_i2s_match); diff --git a/projects/Allwinner/patches/linux/crust/0027-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch b/projects/Allwinner/patches/linux/0004-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch similarity index 95% rename from projects/Allwinner/patches/linux/crust/0027-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch rename to projects/Allwinner/patches/linux/0004-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch index 7bf2916963..f37cf9417f 100644 --- a/projects/Allwinner/patches/linux/crust/0027-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch +++ b/projects/Allwinner/patches/linux/0004-DO-NOT-MERGE-ARM-dts-sunxi-h3-h5-Protect-SCP-clocks.patch @@ -10,7 +10,7 @@ Signed-off-by: Samuel Holland --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -406,6 +406,7 @@ +@@ -388,6 +388,7 @@ reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; @@ -18,7 +18,7 @@ Signed-off-by: Samuel Holland #clock-cells = <1>; #reset-cells = <1>; }; -@@ -894,6 +895,7 @@ +@@ -876,6 +877,7 @@ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; diff --git a/projects/Allwinner/patches/linux/0005-ASoC-sun4i-i2s-Change-get_sr-and-get_wss-to-be-more-.patch b/projects/Allwinner/patches/linux/0005-ASoC-sun4i-i2s-Change-get_sr-and-get_wss-to-be-more-.patch deleted file mode 100644 index 731610a0f7..0000000000 --- a/projects/Allwinner/patches/linux/0005-ASoC-sun4i-i2s-Change-get_sr-and-get_wss-to-be-more-.patch +++ /dev/null @@ -1,134 +0,0 @@ -From aec30a56043a890b75440bb8c9673a07166cf104 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Fri, 30 Oct 2020 15:46:37 +0100 -Subject: [PATCH 05/44] ASoC: sun4i-i2s: Change get_sr() and get_wss() to be - more explicit -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We are actually using a complex formula to just return a bunch of -simple values. Also this formula is wrong for sun4i when calling -get_wss() the function return 4 instead of 3. - -Replace this with a simpler switch case. - -Also drop the i2s params which is unused and return a simple int as -returning an error code could be out of range for an s8 and there is -no optim to return a s8 here. - -Fixes: 619c15f7fac9 ("ASoC: sun4i-i2s: Change SR and WSS computation") -Reviewed-by: Chen-Yu Tsai -Acked-by: Maxime Ripard -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-5-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 75 +++++++++++++++++++++++-------------- - 1 file changed, 47 insertions(+), 28 deletions(-) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -175,8 +175,8 @@ struct sun4i_i2s_quirks { - unsigned int num_mclk_dividers; - - unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *); -- s8 (*get_sr)(const struct sun4i_i2s *, int); -- s8 (*get_wss)(const struct sun4i_i2s *, int); -+ int (*get_sr)(unsigned int width); -+ int (*get_wss)(unsigned int width); - - /* - * In the set_chan_cfg() function pointer: -@@ -387,37 +387,56 @@ static int sun4i_i2s_set_clk_rate(struct - return 0; - } - --static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width) -+static int sun4i_i2s_get_sr(unsigned int width) - { -- if (width < 16 || width > 24) -- return -EINVAL; -- -- if (width % 4) -- return -EINVAL; -+ switch (width) { -+ case 16: -+ return 0; -+ case 20: -+ return 1; -+ case 24: -+ return 2; -+ } - -- return (width - 16) / 4; -+ return -EINVAL; - } - --static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width) -+static int sun4i_i2s_get_wss(unsigned int width) - { -- if (width < 16 || width > 32) -- return -EINVAL; -- -- if (width % 4) -- return -EINVAL; -+ switch (width) { -+ case 16: -+ return 0; -+ case 20: -+ return 1; -+ case 24: -+ return 2; -+ case 32: -+ return 3; -+ } - -- return (width - 16) / 4; -+ return -EINVAL; - } - --static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width) -+static int sun8i_i2s_get_sr_wss(unsigned int width) - { -- if (width % 4) -- return -EINVAL; -- -- if (width < 8 || width > 32) -- return -EINVAL; -+ switch (width) { -+ case 8: -+ return 1; -+ case 12: -+ return 2; -+ case 16: -+ return 3; -+ case 20: -+ return 4; -+ case 24: -+ return 5; -+ case 28: -+ return 6; -+ case 32: -+ return 7; -+ } - -- return (width - 8) / 4 + 1; -+ return -EINVAL; - } - - static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, -@@ -582,11 +601,11 @@ static int sun4i_i2s_hw_params(struct sn - } - i2s->playback_dma_data.addr_width = width; - -- sr = i2s->variant->get_sr(i2s, word_size); -+ sr = i2s->variant->get_sr(word_size); - if (sr < 0) - return -EINVAL; - -- wss = i2s->variant->get_wss(i2s, slot_width); -+ wss = i2s->variant->get_wss(slot_width); - if (wss < 0) - return -EINVAL; - diff --git a/projects/Allwinner/patches/linux/crust/0028-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch b/projects/Allwinner/patches/linux/0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch similarity index 95% rename from projects/Allwinner/patches/linux/crust/0028-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch rename to projects/Allwinner/patches/linux/0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch index 66d37bd47b..60d4395dab 100644 --- a/projects/Allwinner/patches/linux/crust/0028-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch +++ b/projects/Allwinner/patches/linux/0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch @@ -10,7 +10,7 @@ Signed-off-by: Samuel Holland --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -637,6 +637,7 @@ +@@ -641,6 +641,7 @@ reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; @@ -18,7 +18,7 @@ Signed-off-by: Samuel Holland #clock-cells = <1>; #reset-cells = <1>; }; -@@ -1229,6 +1230,7 @@ +@@ -1233,6 +1234,7 @@ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; diff --git a/projects/Allwinner/patches/linux/0006-ASoC-sun4i-i2s-Set-sign-extend-sample.patch b/projects/Allwinner/patches/linux/0006-ASoC-sun4i-i2s-Set-sign-extend-sample.patch deleted file mode 100644 index b4e6c89dec..0000000000 --- a/projects/Allwinner/patches/linux/0006-ASoC-sun4i-i2s-Set-sign-extend-sample.patch +++ /dev/null @@ -1,86 +0,0 @@ -From fe1ae019879d51633d8dcd705117c70b701b77e9 Mon Sep 17 00:00:00 2001 -From: Marcus Cooper -Date: Fri, 30 Oct 2020 15:46:38 +0100 -Subject: [PATCH 06/44] ASoC: sun4i-i2s: Set sign extend sample -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On the newer SoCs such as the H3 and A64 this is set by default -to transfer a 0 after each sample in each slot. However the A10 -and A20 SoCs that this driver was developed on had a default -setting where it padded the audio gain with zeros. - -This isn't a problem while we have only support for 16bit audio -but with larger sample resolution rates in the pipeline then SEXT -bits should be cleared so that they also pad at the LSB. Without -this the audio gets distorted. - -Set sign extend sample for all the sunxi generations even if they -are not affected. This will keep consistency and avoid relying on -default. - -Signed-off-by: Marcus Cooper -Reviewed-by: Chen-Yu Tsai -Acked-by: Maxime Ripard -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-6-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -48,6 +48,9 @@ - #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) - - #define SUN4I_I2S_FMT1_REG 0x08 -+#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) -+#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) -+ - #define SUN4I_I2S_FIFO_TX_REG 0x0c - #define SUN4I_I2S_FIFO_RX_REG 0x10 - -@@ -105,6 +108,9 @@ - #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) - #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7) - -+#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4) -+#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) -+ - #define SUN8I_I2S_INT_STA_REG 0x0c - #define SUN8I_I2S_FIFO_TX_REG 0x20 - -@@ -686,6 +692,7 @@ static int sun4i_i2s_set_soc_fmt(const s - } - regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, - SUN4I_I2S_CTRL_MODE_MASK, val); -+ - return 0; - } - -@@ -788,6 +795,11 @@ static int sun8i_i2s_set_soc_fmt(const s - SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, - val); - -+ /* Set sign extension to pad out LSB with 0 */ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, -+ SUN8I_I2S_FMT1_REG_SEXT_MASK, -+ SUN8I_I2S_FMT1_REG_SEXT(0)); -+ - return 0; - } - -@@ -890,6 +902,11 @@ static int sun50i_h6_i2s_set_soc_fmt(con - SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, - val); - -+ /* Set sign extension to pad out LSB with 0 */ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, -+ SUN8I_I2S_FMT1_REG_SEXT_MASK, -+ SUN8I_I2S_FMT1_REG_SEXT(0)); -+ - return 0; - } - diff --git a/projects/Allwinner/patches/linux/crust/0029-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch b/projects/Allwinner/patches/linux/0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch similarity index 95% rename from projects/Allwinner/patches/linux/crust/0029-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch rename to projects/Allwinner/patches/linux/0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch index a33dd3ce4d..7a05d092e9 100644 --- a/projects/Allwinner/patches/linux/crust/0029-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch +++ b/projects/Allwinner/patches/linux/0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch @@ -10,7 +10,7 @@ Signed-off-by: Samuel Holland --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -241,6 +241,7 @@ +@@ -230,6 +230,7 @@ reg = <0x03001000 0x1000>; clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; clock-names = "hosc", "losc", "iosc"; @@ -18,7 +18,7 @@ Signed-off-by: Samuel Holland #clock-cells = <1>; #reset-cells = <1>; }; -@@ -920,6 +921,7 @@ +@@ -916,6 +917,7 @@ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; diff --git a/projects/Allwinner/patches/linux/0007-ASoC-sun4i-i2s-Add-20-and-24-bit-support.patch b/projects/Allwinner/patches/linux/0007-ASoC-sun4i-i2s-Add-20-and-24-bit-support.patch deleted file mode 100644 index 0205308b31..0000000000 --- a/projects/Allwinner/patches/linux/0007-ASoC-sun4i-i2s-Add-20-and-24-bit-support.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 9c2121fe514f12c830bceea7b33872fa67af3e97 Mon Sep 17 00:00:00 2001 -From: Marcus Cooper -Date: Fri, 30 Oct 2020 15:46:39 +0100 -Subject: [PATCH 07/44] ASoC: sun4i-i2s: Add 20 and 24 bit support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Extend the functionality of the driver to include support of 20 and -24 bits per sample. - -Signed-off-by: Marcus Cooper -Acked-by: Maxime Ripard -Reviewed-by: Chen-Yu Tsai -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-7-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -600,6 +600,9 @@ static int sun4i_i2s_hw_params(struct sn - case 16: - width = DMA_SLAVE_BUSWIDTH_2_BYTES; - break; -+ case 32: -+ width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ break; - default: - dev_err(dai->dev, "Unsupported physical sample width: %d\n", - params_physical_width(params)); -@@ -1081,6 +1084,10 @@ static int sun4i_i2s_dai_probe(struct sn - return 0; - } - -+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ -+ SNDRV_PCM_FMTBIT_S20_LE | \ -+ SNDRV_PCM_FMTBIT_S24_LE) -+ - static struct snd_soc_dai_driver sun4i_i2s_dai = { - .probe = sun4i_i2s_dai_probe, - .capture = { -@@ -1088,14 +1095,14 @@ static struct snd_soc_dai_driver sun4i_i - .channels_min = 1, - .channels_max = 8, - .rates = SNDRV_PCM_RATE_8000_192000, -- .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ .formats = SUN4I_FORMATS, - }, - .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 8, - .rates = SNDRV_PCM_RATE_8000_192000, -- .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ .formats = SUN4I_FORMATS, - }, - .ops = &sun4i_i2s_dai_ops, - .symmetric_rates = 1, diff --git a/projects/Allwinner/patches/linux/crust/0034-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch b/projects/Allwinner/patches/linux/0007-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch similarity index 84% rename from projects/Allwinner/patches/linux/crust/0034-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch rename to projects/Allwinner/patches/linux/0007-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch index 9edaa6fe85..3abf3b50b2 100644 --- a/projects/Allwinner/patches/linux/crust/0034-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch +++ b/projects/Allwinner/patches/linux/0007-rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch @@ -15,7 +15,7 @@ Signed-off-by: Samuel Holland --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c -@@ -639,7 +639,6 @@ static const struct rtc_class_ops sun6i_ +@@ -641,7 +641,6 @@ static const struct rtc_class_ops sun6i_ .alarm_irq_enable = sun6i_rtc_alarm_irq_enable }; @@ -23,7 +23,7 @@ Signed-off-by: Samuel Holland /* Enable IRQ wake on suspend, to wake up from RTC. */ static int sun6i_rtc_suspend(struct device *dev) { -@@ -652,7 +651,7 @@ static int sun6i_rtc_suspend(struct devi +@@ -654,7 +653,7 @@ static int sun6i_rtc_suspend(struct devi } /* Disable IRQ wake on resume. */ @@ -32,7 +32,7 @@ Signed-off-by: Samuel Holland { struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); -@@ -661,7 +660,6 @@ static int sun6i_rtc_resume(struct devic +@@ -663,7 +662,6 @@ static int sun6i_rtc_resume(struct devic return 0; } @@ -40,7 +40,7 @@ Signed-off-by: Samuel Holland static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, sun6i_rtc_suspend, sun6i_rtc_resume); -@@ -733,6 +731,11 @@ static int sun6i_rtc_probe(struct platfo +@@ -735,6 +733,11 @@ static int sun6i_rtc_probe(struct platfo return 0; } @@ -52,7 +52,7 @@ Signed-off-by: Samuel Holland /* * As far as RTC functionality goes, all models are the same. The * datasheets claim that different models have different number of -@@ -753,6 +756,7 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids +@@ -755,6 +758,7 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids static struct platform_driver sun6i_rtc_driver = { .probe = sun6i_rtc_probe, diff --git a/projects/Allwinner/patches/linux/0008-ASoC-sun4i-i2s-Fix-sun8i-volatile-regs.patch b/projects/Allwinner/patches/linux/0008-ASoC-sun4i-i2s-Fix-sun8i-volatile-regs.patch deleted file mode 100644 index 8c4dd63320..0000000000 --- a/projects/Allwinner/patches/linux/0008-ASoC-sun4i-i2s-Fix-sun8i-volatile-regs.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 9f0cbed8e957216d58a2dd5c9c8e795ec39004ad Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Fri, 30 Oct 2020 15:46:40 +0100 -Subject: [PATCH 08/44] ASoC: sun4i-i2s: Fix sun8i volatile regs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The FIFO TX reg is volatile and sun8i i2s register -mapping is different from sun4i. - -Even if in this case it's doesn't create an issue, -Avoid setting some regs that are undefined in sun8i. - -Acked-by: Maxime Ripard -Reviewed-by: Chen-Yu Tsai -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-8-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 15 +++++++++++---- - 1 file changed, 11 insertions(+), 4 deletions(-) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1162,12 +1162,19 @@ static bool sun8i_i2s_rd_reg(struct devi - - static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) - { -- if (reg == SUN8I_I2S_INT_STA_REG) -+ switch (reg) { -+ case SUN4I_I2S_FIFO_CTRL_REG: -+ case SUN4I_I2S_FIFO_RX_REG: -+ case SUN4I_I2S_FIFO_STA_REG: -+ case SUN4I_I2S_RX_CNT_REG: -+ case SUN4I_I2S_TX_CNT_REG: -+ case SUN8I_I2S_FIFO_TX_REG: -+ case SUN8I_I2S_INT_STA_REG: - return true; -- if (reg == SUN8I_I2S_FIFO_TX_REG) -- return false; - -- return sun4i_i2s_volatile_reg(dev, reg); -+ default: -+ return false; -+ } - } - - static const struct reg_default sun4i_i2s_reg_defaults[] = { diff --git a/projects/Allwinner/patches/linux/crust/0035-input-sun4i-lradc-keys-Add-wakup-support.patch b/projects/Allwinner/patches/linux/0008-input-sun4i-lradc-keys-Add-wakup-support.patch similarity index 100% rename from projects/Allwinner/patches/linux/crust/0035-input-sun4i-lradc-keys-Add-wakup-support.patch rename to projects/Allwinner/patches/linux/0008-input-sun4i-lradc-keys-Add-wakup-support.patch diff --git a/projects/Allwinner/patches/linux/0009-ASoC-sun4i-i2s-Fix-setting-of-FIFO-modes.patch b/projects/Allwinner/patches/linux/0009-ASoC-sun4i-i2s-Fix-setting-of-FIFO-modes.patch deleted file mode 100644 index 14cc889b76..0000000000 --- a/projects/Allwinner/patches/linux/0009-ASoC-sun4i-i2s-Fix-setting-of-FIFO-modes.patch +++ /dev/null @@ -1,53 +0,0 @@ -From de8ff7b3ac4736f5aa0c55968170bd449e46c88f Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 30 Oct 2020 15:46:41 +0100 -Subject: [PATCH 09/44] ASoC: sun4i-i2s: Fix setting of FIFO modes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the -regmap is cache-only are ignored. To work around this, move the -configuration to a callback that runs while the ASoC core has a -runtime PM reference to the device. - -Signed-off-by: Samuel Holland -Reviewed-by: Chen-Yu Tsai -Acked-by: Maxime Ripard -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-9-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -596,6 +596,13 @@ static int sun4i_i2s_hw_params(struct sn - return ret; - } - -+ /* Set significant bits in our FIFOs */ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, -+ SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | -+ SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, -+ SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | -+ SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); -+ - switch (params_physical_width(params)) { - case 16: - width = DMA_SLAVE_BUSWIDTH_2_BYTES; -@@ -924,13 +931,6 @@ static int sun4i_i2s_set_fmt(struct snd_ - return ret; - } - -- /* Set significant bits in our FIFOs */ -- regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, -- SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | -- SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, -- SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | -- SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); -- - i2s->format = fmt; - - return 0; diff --git a/projects/Allwinner/patches/linux/crust/0036-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch b/projects/Allwinner/patches/linux/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch similarity index 93% rename from projects/Allwinner/patches/linux/crust/0036-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch rename to projects/Allwinner/patches/linux/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch index 74ee6fb06c..cbf3f66f77 100644 --- a/projects/Allwinner/patches/linux/crust/0036-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch +++ b/projects/Allwinner/patches/linux/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch @@ -38,7 +38,7 @@ Signed-off-by: Samuel Holland if (ret < 0 || !rx_buf) goto out; -@@ -854,8 +855,13 @@ static void scpi_free_channels(void *dat +@@ -856,8 +857,13 @@ static void scpi_free_channels(void *dat struct scpi_drvinfo *info = data; int i; @@ -54,7 +54,7 @@ Signed-off-by: Samuel Holland } static int scpi_remove(struct platform_device *pdev) -@@ -903,6 +909,7 @@ static int scpi_probe(struct platform_de +@@ -905,6 +911,7 @@ static int scpi_probe(struct platform_de struct resource res; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -62,7 +62,7 @@ Signed-off-by: Samuel Holland scpi_info = devm_kzalloc(dev, sizeof(*scpi_info), GFP_KERNEL); if (!scpi_info) -@@ -916,6 +923,14 @@ static int scpi_probe(struct platform_de +@@ -918,6 +925,14 @@ static int scpi_probe(struct platform_de dev_err(dev, "no mboxes property in '%pOF'\n", np); return -ENODEV; } @@ -77,7 +77,7 @@ Signed-off-by: Samuel Holland scpi_info->channels = devm_kcalloc(dev, count, sizeof(struct scpi_chan), GFP_KERNEL); -@@ -961,15 +976,34 @@ static int scpi_probe(struct platform_de +@@ -963,15 +978,34 @@ static int scpi_probe(struct platform_de mutex_init(&pchan->xfers_lock); ret = scpi_alloc_xfer_list(dev, pchan); diff --git a/projects/Allwinner/patches/linux/crust/0037-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch b/projects/Allwinner/patches/linux/0010-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch similarity index 98% rename from projects/Allwinner/patches/linux/crust/0037-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch rename to projects/Allwinner/patches/linux/0010-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch index 26be20b79e..47f073405a 100644 --- a/projects/Allwinner/patches/linux/crust/0037-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch +++ b/projects/Allwinner/patches/linux/0010-ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch @@ -34,7 +34,7 @@ Signed-off-by: Samuel Holland reg = <0x01d00000 0x80000>; --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -123,6 +123,13 @@ +@@ -105,6 +105,13 @@ status = "disabled"; }; diff --git a/projects/Allwinner/patches/linux/0010-ASoC-sun4i-i2s-fix-coding-style-for-callback-definit.patch b/projects/Allwinner/patches/linux/0010-ASoC-sun4i-i2s-fix-coding-style-for-callback-definit.patch deleted file mode 100644 index 15899dd1e6..0000000000 --- a/projects/Allwinner/patches/linux/0010-ASoC-sun4i-i2s-fix-coding-style-for-callback-definit.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 82b0eb24d554180fdea8a254553dcce22085cc74 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Fri, 30 Oct 2020 15:46:42 +0100 -Subject: [PATCH 10/44] ASoC: sun4i-i2s: fix coding-style for callback - definition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Checkpatch script produces warning: -WARNING: function definition argument 'const struct sun4i_i2s *' -should also have an identifier name. - -Let's fix this by adding identifier name to get_bclk_parent_rate() -and set_fmt() callback definition. - -Acked-by: Maxime Ripard -Signed-off-by: Clément Péron -Link: https://lore.kernel.org/r/20201030144648.397824-10-peron.clem@gmail.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -180,7 +180,7 @@ struct sun4i_i2s_quirks { - const struct sun4i_i2s_clk_div *mclk_dividers; - unsigned int num_mclk_dividers; - -- unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *); -+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s); - int (*get_sr)(unsigned int width); - int (*get_wss)(unsigned int width); - -@@ -192,7 +192,7 @@ struct sun4i_i2s_quirks { - int (*set_chan_cfg)(const struct sun4i_i2s *i2s, - unsigned int channels, unsigned int slots, - unsigned int slot_width); -- int (*set_fmt)(const struct sun4i_i2s *, unsigned int); -+ int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt); - }; - - struct sun4i_i2s { diff --git a/projects/Allwinner/patches/linux/0011-ARM-dts-sun8i-r40-Add-deinterlace-node.patch b/projects/Allwinner/patches/linux/0011-ARM-dts-sun8i-r40-Add-deinterlace-node.patch deleted file mode 100644 index ee4b752ba2..0000000000 --- a/projects/Allwinner/patches/linux/0011-ARM-dts-sun8i-r40-Add-deinterlace-node.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 51ebc019df15b46d109bafe7068ebb6fe0b266b5 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 6 Jan 2021 19:19:01 +0100 -Subject: [PATCH 11/44] ARM: dts: sun8i: r40: Add deinterlace node - -R40 contains deinterlace core compatible to that in H3. One peculiarity -is that RAM gate is shared with CSI1. User manual states it's separate -but that's not true. Shared gate was verified with BSP Linux code check -and with runtime tests (CPU crashed if CSI1 gate was not ungated). - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/20210106181901.1324075-3-jernej.skrabec@siol.net ---- - arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/arch/arm/boot/dts/sun8i-r40.dtsi -+++ b/arch/arm/boot/dts/sun8i-r40.dtsi -@@ -190,6 +190,25 @@ - }; - }; - -+ deinterlace: deinterlace@1400000 { -+ compatible = "allwinner,sun8i-r40-deinterlace", -+ "allwinner,sun8i-h3-deinterlace"; -+ reg = <0x01400000 0x20000>; -+ clocks = <&ccu CLK_BUS_DEINTERLACE>, -+ <&ccu CLK_DEINTERLACE>, -+ /* -+ * NOTE: Contrary to what datasheet claims, -+ * DRAM deinterlace gate doesn't exist and -+ * it's shared with CSI1. -+ */ -+ <&ccu CLK_DRAM_CSI1>; -+ clock-names = "bus", "mod", "ram"; -+ resets = <&ccu RST_BUS_DEINTERLACE>; -+ interrupts = ; -+ interconnects = <&mbus 9>; -+ interconnect-names = "dma-mem"; -+ }; -+ - syscon: system-control@1c00000 { - compatible = "allwinner,sun8i-r40-system-control", - "allwinner,sun4i-a10-system-control"; diff --git a/projects/Allwinner/patches/linux/crust/0038-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch b/projects/Allwinner/patches/linux/0011-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch similarity index 100% rename from projects/Allwinner/patches/linux/crust/0038-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch rename to projects/Allwinner/patches/linux/0011-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch diff --git a/projects/Allwinner/patches/linux/0012-arm64-dts-allwinner-h5-Add-deinterlace-node.patch b/projects/Allwinner/patches/linux/0012-arm64-dts-allwinner-h5-Add-deinterlace-node.patch deleted file mode 100644 index 5bcbc7e9c5..0000000000 --- a/projects/Allwinner/patches/linux/0012-arm64-dts-allwinner-h5-Add-deinterlace-node.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 7166a5b6ab1f3d9ba0f5236b738525e828138c8e Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 6 Jan 2021 19:25:23 +0100 -Subject: [PATCH 12/44] arm64: dts: allwinner: h5: Add deinterlace node - -Deinterlace core is completely compatible to H3. - -Add a node for it. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/20210106182523.1325796-1-jernej.skrabec@siol.net ---- - arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi -@@ -121,6 +121,19 @@ - resets = <&ccu RST_BUS_CE>; - }; - -+ deinterlace: deinterlace@1e00000 { -+ compatible = "allwinner,sun8i-h3-deinterlace"; -+ reg = <0x01e00000 0x20000>; -+ clocks = <&ccu CLK_BUS_DEINTERLACE>, -+ <&ccu CLK_DEINTERLACE>, -+ <&ccu CLK_DRAM_DEINTERLACE>; -+ clock-names = "bus", "mod", "ram"; -+ resets = <&ccu RST_BUS_DEINTERLACE>; -+ interrupts = ; -+ interconnects = <&mbus 9>; -+ interconnect-names = "dma-mem"; -+ }; -+ - mali: gpu@1e80000 { - compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; - reg = <0x01e80000 0x30000>; diff --git a/projects/Allwinner/patches/linux/crust/0039-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch b/projects/Allwinner/patches/linux/0012-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch similarity index 98% rename from projects/Allwinner/patches/linux/crust/0039-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch rename to projects/Allwinner/patches/linux/0012-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch index 896b32aeae..0971c9d7ed 100644 --- a/projects/Allwinner/patches/linux/crust/0039-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch +++ b/projects/Allwinner/patches/linux/0012-arm64-dts-allwinner-h6-Add-SCPI-protocol.patch @@ -24,7 +24,7 @@ Signed-off-by: Samuel Holland timer { compatible = "arm,armv8-timer"; arm,no-tick-in-suspend; -@@ -207,6 +214,19 @@ +@@ -196,6 +203,19 @@ #size-cells = <1>; ranges; diff --git a/projects/Allwinner/patches/linux/0022-ASoC-hdmi-codec-fix-channel-allocation.patch b/projects/Allwinner/patches/linux/0013-ASoC-hdmi-codec-fix-channel-allocation.patch similarity index 98% rename from projects/Allwinner/patches/linux/0022-ASoC-hdmi-codec-fix-channel-allocation.patch rename to projects/Allwinner/patches/linux/0013-ASoC-hdmi-codec-fix-channel-allocation.patch index b5a73b1af7..83cb49cd9b 100644 --- a/projects/Allwinner/patches/linux/0022-ASoC-hdmi-codec-fix-channel-allocation.patch +++ b/projects/Allwinner/patches/linux/0013-ASoC-hdmi-codec-fix-channel-allocation.patch @@ -9,7 +9,7 @@ Subject: [PATCH 22/44] ASoC: hdmi-codec: fix channel allocation --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c -@@ -195,78 +195,69 @@ static const struct snd_pcm_chmap_elem h +@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem h */ static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { { .ca_id = 0x00, .n_ch = 2, diff --git a/projects/Allwinner/patches/linux/0013-drm-sun4i-csc-Rework-DE3-CSC-macros.patch b/projects/Allwinner/patches/linux/0013-drm-sun4i-csc-Rework-DE3-CSC-macros.patch deleted file mode 100644 index f8fdf0b2ff..0000000000 --- a/projects/Allwinner/patches/linux/0013-drm-sun4i-csc-Rework-DE3-CSC-macros.patch +++ /dev/null @@ -1,40 +0,0 @@ -From dcd9635dc6027b04a64e19ebb3dc15aaae082400 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 18 Feb 2020 19:24:29 +0100 -Subject: [PATCH 13/44] drm/sun4i: csc: Rework DE3 CSC macros - -Rework DE3 CSC macros to take just one coordinate instead of two. This -will make its usage easier in subsequent commit. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_csc.c | 2 +- - drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 ++---- - 2 files changed, 3 insertions(+), 5 deletions(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_csc.c -+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c -@@ -194,7 +194,7 @@ static void sun8i_de3_ccsc_set_coefficie - return; - } - -- base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0); -+ base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); - regmap_bulk_write(map, base_reg, table, 12); - } - ---- a/drivers/gpu/drm/sun4i/sun8i_mixer.h -+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h -@@ -50,10 +50,8 @@ - #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x)) - #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc) - #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100) --#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \ -- ((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y)) --#define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \ -- ((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c) -+#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \ -+ ((base) + 0x110 + (layer) * 0x30 + (x) * 4) - - #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8) - #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe) diff --git a/projects/Allwinner/patches/linux/0014-drm-sun4i-de2-de3-Remove-redundant-CSC-matrices.patch b/projects/Allwinner/patches/linux/0014-drm-sun4i-de2-de3-Remove-redundant-CSC-matrices.patch deleted file mode 100644 index de6c92f2bf..0000000000 --- a/projects/Allwinner/patches/linux/0014-drm-sun4i-de2-de3-Remove-redundant-CSC-matrices.patch +++ /dev/null @@ -1,163 +0,0 @@ -From acdfa534d3fe6759f43c1fe0bcd2fd40f31d3797 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 18 Feb 2020 19:44:33 +0100 -Subject: [PATCH 14/44] drm/sun4i: de2/de3: Remove redundant CSC matrices - -YUV to RGB matrices are almost identical to YVU to RGB matrices. They -only have second and third column reversed. Do that reversion in code in -order to lower amount of static data and redundancy. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_csc.c | 99 +++++++++++-------------------- - 1 file changed, 34 insertions(+), 65 deletions(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_csc.c -+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c -@@ -46,33 +46,6 @@ static const u32 yuv2rgb[2][2][12] = { - }, - }; - --static const u32 yvu2rgb[2][2][12] = { -- [DRM_COLOR_YCBCR_LIMITED_RANGE] = { -- [DRM_COLOR_YCBCR_BT601] = { -- 0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451, -- 0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D, -- 0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9, -- }, -- [DRM_COLOR_YCBCR_BT709] = { -- 0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99, -- 0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383, -- 0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF, -- } -- }, -- [DRM_COLOR_YCBCR_FULL_RANGE] = { -- [DRM_COLOR_YCBCR_BT601] = { -- 0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E, -- 0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5, -- 0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD, -- }, -- [DRM_COLOR_YCBCR_BT709] = { -- 0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4, -- 0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96, -- 0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF, -- } -- }, --}; -- - /* - * DE3 has a bit different CSC units. Factors are in two's complement format. - * First three factors in a row are multiplication factors which have 17 bits -@@ -123,33 +96,6 @@ static const u32 yuv2rgb_de3[2][2][12] = - }, - }; - --static const u32 yvu2rgb_de3[2][2][12] = { -- [DRM_COLOR_YCBCR_LIMITED_RANGE] = { -- [DRM_COLOR_YCBCR_BT601] = { -- 0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000, -- 0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000, -- 0x0002542A, 0x00000000, 0x000408D2, 0xFE000000, -- }, -- [DRM_COLOR_YCBCR_BT709] = { -- 0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000, -- 0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000, -- 0x0002542A, 0x00000000, 0x0004398C, 0xFE000000, -- } -- }, -- [DRM_COLOR_YCBCR_FULL_RANGE] = { -- [DRM_COLOR_YCBCR_BT601] = { -- 0x00020000, 0x0002CDD2, 0x00000000, 0x00000000, -- 0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000, -- 0x00020000, 0x00000000, 0x00038B43, 0xFE000000, -- }, -- [DRM_COLOR_YCBCR_BT709] = { -- 0x00020000, 0x0003264C, 0x00000000, 0x00000000, -- 0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000, -- 0x00020000, 0x00000000, 0x0003B611, 0xFE000000, -- } -- }, --}; -- - static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, - enum sun8i_csc_mode mode, - enum drm_color_encoding encoding, -@@ -157,21 +103,30 @@ static void sun8i_csc_set_coefficients(s - { - const u32 *table; - u32 base_reg; -+ int i; -+ -+ table = yuv2rgb[range][encoding]; - - switch (mode) { - case SUN8I_CSC_MODE_YUV2RGB: -- table = yuv2rgb[range][encoding]; -+ base_reg = SUN8I_CSC_COEFF(base, 0); -+ regmap_bulk_write(map, base_reg, table, 12); - break; - case SUN8I_CSC_MODE_YVU2RGB: -- table = yvu2rgb[range][encoding]; -+ for (i = 0; i < 12; i++) { -+ if ((i & 3) == 1) -+ base_reg = SUN8I_CSC_COEFF(base, i + 1); -+ else if ((i & 3) == 2) -+ base_reg = SUN8I_CSC_COEFF(base, i - 1); -+ else -+ base_reg = SUN8I_CSC_COEFF(base, i); -+ regmap_write(map, base_reg, table[i]); -+ } - break; - default: - DRM_WARN("Wrong CSC mode specified.\n"); - return; - } -- -- base_reg = SUN8I_CSC_COEFF(base, 0); -- regmap_bulk_write(map, base_reg, table, 12); - } - - static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, -@@ -180,22 +135,36 @@ static void sun8i_de3_ccsc_set_coefficie - enum drm_color_range range) - { - const u32 *table; -- u32 base_reg; -+ u32 addr; -+ int i; -+ -+ table = yuv2rgb_de3[range][encoding]; - - switch (mode) { - case SUN8I_CSC_MODE_YUV2RGB: -- table = yuv2rgb_de3[range][encoding]; -+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); -+ regmap_bulk_write(map, addr, table, 12); - break; - case SUN8I_CSC_MODE_YVU2RGB: -- table = yvu2rgb_de3[range][encoding]; -+ for (i = 0; i < 12; i++) { -+ if ((i & 3) == 1) -+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, -+ layer, -+ i + 1); -+ else if ((i & 3) == 2) -+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, -+ layer, -+ i - 1); -+ else -+ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, -+ layer, i); -+ regmap_write(map, addr, table[i]); -+ } - break; - default: - DRM_WARN("Wrong CSC mode specified.\n"); - return; - } -- -- base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); -- regmap_bulk_write(map, base_reg, table, 12); - } - - static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable) diff --git a/projects/Allwinner/patches/linux/0023-media-uapi-hevc-Add-scaling-matrix-control.patch b/projects/Allwinner/patches/linux/0014-media-uapi-hevc-Add-scaling-matrix-control.patch similarity index 74% rename from projects/Allwinner/patches/linux/0023-media-uapi-hevc-Add-scaling-matrix-control.patch rename to projects/Allwinner/patches/linux/0014-media-uapi-hevc-Add-scaling-matrix-control.patch index 8add1ecf3a..1acd9d90f6 100644 --- a/projects/Allwinner/patches/linux/0023-media-uapi-hevc-Add-scaling-matrix-control.patch +++ b/projects/Allwinner/patches/linux/0014-media-uapi-hevc-Add-scaling-matrix-control.patch @@ -13,7 +13,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1021,6 +1021,7 @@ const char *v4l2_ctrl_get_name(u32 id) +@@ -1041,6 +1041,7 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; @@ -21,7 +21,7 @@ Signed-off-by: Jernej Skrabec case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; -@@ -1461,6 +1462,9 @@ void v4l2_ctrl_fill(u32 id, const char * +@@ -1526,6 +1527,9 @@ void v4l2_ctrl_fill(u32 id, const char * case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; break; @@ -31,8 +31,8 @@ Signed-off-by: Jernej Skrabec case V4L2_CID_UNIT_CELL_SIZE: *type = V4L2_CTRL_TYPE_AREA; *flags |= V4L2_CTRL_FLAG_READ_ONLY; -@@ -1934,6 +1938,9 @@ static int std_validate_compound(const s - zero_padding(*p_hevc_slice_params); +@@ -2237,6 +2241,9 @@ static int std_validate_compound(const s + break; + case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: @@ -41,9 +41,9 @@ Signed-off-by: Jernej Skrabec case V4L2_CTRL_TYPE_AREA: area = p; if (!area->width || !area->height) -@@ -2626,6 +2633,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(s - case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); +@@ -2953,6 +2960,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(s + case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY: + elem_size = sizeof(struct v4l2_ctrl_hdr10_mastering_display); break; + case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: + elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); @@ -54,12 +54,12 @@ Signed-off-by: Jernej Skrabec --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -19,6 +19,7 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011) - #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_MPEG_BASE + 1015) - #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_MPEG_BASE + 1016) + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) + #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) @@ -26,6 +27,7 @@ #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 diff --git a/projects/Allwinner/patches/linux/0015-drm-sun4i-Add-support-for-BT2020-to-DE3.patch b/projects/Allwinner/patches/linux/0015-drm-sun4i-Add-support-for-BT2020-to-DE3.patch deleted file mode 100644 index f94f13d1b8..0000000000 --- a/projects/Allwinner/patches/linux/0015-drm-sun4i-Add-support-for-BT2020-to-DE3.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 2c9a7a5a71d5ed6db9ee28a5ccd11f0db45f574d Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 15 Apr 2020 10:24:05 +0200 -Subject: [PATCH 15/44] drm/sun4i: Add support for BT2020 to DE3 - -DE3 supports 10-bit formats, so it's only naturally to also support -BT2020 encoding. - -Add support for it. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_csc.c | 12 +++++++++++- - drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 2 ++ - 2 files changed, 13 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_csc.c -+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c -@@ -69,7 +69,7 @@ static const u32 yuv2rgb[2][2][12] = { - * c20 c21 c22 [d2 const2] - */ - --static const u32 yuv2rgb_de3[2][2][12] = { -+static const u32 yuv2rgb_de3[2][3][12] = { - [DRM_COLOR_YCBCR_LIMITED_RANGE] = { - [DRM_COLOR_YCBCR_BT601] = { - 0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000, -@@ -80,6 +80,11 @@ static const u32 yuv2rgb_de3[2][2][12] = - 0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000, - 0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000, - 0x0002542A, 0x0004398C, 0x00000000, 0xFE000000, -+ }, -+ [DRM_COLOR_YCBCR_BT2020] = { -+ 0x0002542A, 0x00000000, 0x00035B7B, 0xFFC00000, -+ 0x0002542A, 0xFFFFA017, 0xFFFEB2FC, 0xFE000000, -+ 0x0002542A, 0x00044896, 0x00000000, 0xFE000000, - } - }, - [DRM_COLOR_YCBCR_FULL_RANGE] = { -@@ -92,6 +97,11 @@ static const u32 yuv2rgb_de3[2][2][12] = - 0x00020000, 0x00000000, 0x0003264C, 0x00000000, - 0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000, - 0x00020000, 0x0003B611, 0x00000000, 0xFE000000, -+ }, -+ [DRM_COLOR_YCBCR_BT2020] = { -+ 0x00020000, 0x00000000, 0x0002F2FE, 0x00000000, -+ 0x00020000, 0xFFFFABC0, 0xFFFEDB78, 0xFE000000, -+ 0x00020000, 0x0003C346, 0x00000000, 0xFE000000, - } - }, - }; ---- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -@@ -543,6 +543,8 @@ struct sun8i_vi_layer *sun8i_vi_layer_in - - supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) | - BIT(DRM_COLOR_YCBCR_BT709); -+ if (mixer->cfg->is_de3) -+ supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020); - - supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | - BIT(DRM_COLOR_YCBCR_FULL_RANGE); diff --git a/projects/Allwinner/patches/linux/0024-media-cedrus-hevc-Add-support-for-scaling-matrix.patch b/projects/Allwinner/patches/linux/0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch similarity index 96% rename from projects/Allwinner/patches/linux/0024-media-cedrus-hevc-Add-support-for-scaling-matrix.patch rename to projects/Allwinner/patches/linux/0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch index ddf6ff9f6b..2be33c242a 100644 --- a/projects/Allwinner/patches/linux/0024-media-cedrus-hevc-Add-support-for-scaling-matrix.patch +++ b/projects/Allwinner/patches/linux/0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch @@ -16,14 +16,13 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -126,6 +126,13 @@ static const struct cedrus_control cedru +@@ -131,6 +131,12 @@ static const struct cedrus_control cedru }, { .cfg = { + .id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, + }, + .codec = CEDRUS_CODEC_H265, -+ .required = true, + }, + { + .cfg = { @@ -32,14 +31,14 @@ Signed-off-by: Jernej Skrabec .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -74,6 +74,7 @@ struct cedrus_h265_run { +@@ -76,6 +76,7 @@ struct cedrus_h265_run { const struct v4l2_ctrl_hevc_sps *sps; const struct v4l2_ctrl_hevc_pps *pps; const struct v4l2_ctrl_hevc_slice_params *slice_params; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; }; - struct cedrus_run { + struct cedrus_vp8_run { --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c @@ -68,6 +68,8 @@ void cedrus_device_run(void *priv) @@ -50,7 +49,7 @@ Signed-off-by: Jernej Skrabec + V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX); break; - default: + case V4L2_PIX_FMT_VP8_FRAME: --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -238,6 +238,69 @@ static void cedrus_h265_skip_bits(struct @@ -139,7 +138,7 @@ Signed-off-by: Jernej Skrabec /* Neightbor information address. */ --- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -493,6 +493,8 @@ +@@ -494,6 +494,8 @@ #define VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR (VE_ENGINE_DEC_H265 + 0x64) #define VE_DEC_H265_TILE_START_CTB (VE_ENGINE_DEC_H265 + 0x68) #define VE_DEC_H265_TILE_END_CTB (VE_ENGINE_DEC_H265 + 0x6c) diff --git a/projects/Allwinner/patches/linux/0025-media-uapi-hevc-Add-segment-address-field.patch b/projects/Allwinner/patches/linux/0016-media-uapi-hevc-Add-segment-address-field.patch similarity index 100% rename from projects/Allwinner/patches/linux/0025-media-uapi-hevc-Add-segment-address-field.patch rename to projects/Allwinner/patches/linux/0016-media-uapi-hevc-Add-segment-address-field.patch diff --git a/projects/Allwinner/patches/linux/0016-mmc-sunxi-mmc-Ensure-host-is-suspended-during-system.patch b/projects/Allwinner/patches/linux/0016-mmc-sunxi-mmc-Ensure-host-is-suspended-during-system.patch deleted file mode 100644 index 1a4b75baa0..0000000000 --- a/projects/Allwinner/patches/linux/0016-mmc-sunxi-mmc-Ensure-host-is-suspended-during-system.patch +++ /dev/null @@ -1,27 +0,0 @@ -From e689f3536e632e26166e66eac88728c6653a18b6 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Tue, 12 Jan 2021 23:24:21 -0600 -Subject: [PATCH 16/44] mmc: sunxi-mmc: Ensure host is suspended during system - sleep - -If the device suspend process begins before the mmc host's autosuspend -timeout, the host will continue running during system sleep. Avoid -this by forcing runtime suspend during a global suspend transition. - -Signed-off-by: Samuel Holland -Acked-by: Maxime Ripard ---- - drivers/mmc/host/sunxi-mmc.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mmc/host/sunxi-mmc.c -+++ b/drivers/mmc/host/sunxi-mmc.c -@@ -1506,6 +1506,8 @@ static int sunxi_mmc_runtime_suspend(str - #endif - - static const struct dev_pm_ops sunxi_mmc_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend, - sunxi_mmc_runtime_resume, - NULL) diff --git a/projects/Allwinner/patches/linux/0017-arm64-dts-allwinner-h6-Add-I2S1-node.patch b/projects/Allwinner/patches/linux/0017-arm64-dts-allwinner-h6-Add-I2S1-node.patch deleted file mode 100644 index 58c540517a..0000000000 --- a/projects/Allwinner/patches/linux/0017-arm64-dts-allwinner-h6-Add-I2S1-node.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e019a54d084020e6acc2869da341b376700bfe4c Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 30 Oct 2020 15:46:44 +0100 -Subject: [PATCH 17/44] arm64: dts: allwinner: h6: Add I2S1 node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add Allwinner H6 I2S1 node connected to HDMI interface. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Marcus Cooper -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard -Acked-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201030144648.397824-12-peron.clem@gmail.com ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -609,6 +609,19 @@ - }; - }; - -+ i2s1: i2s@5091000 { -+ #sound-dai-cells = <0>; -+ compatible = "allwinner,sun50i-h6-i2s"; -+ reg = <0x05091000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; -+ clock-names = "apb", "mod"; -+ dmas = <&dma 4>, <&dma 4>; -+ resets = <&ccu RST_BUS_I2S1>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ - spdif: spdif@5093000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-h6-spdif"; diff --git a/projects/Allwinner/patches/linux/0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch b/projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch similarity index 98% rename from projects/Allwinner/patches/linux/0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch rename to projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch index eb22de15b0..85b39b62d6 100644 --- a/projects/Allwinner/patches/linux/0026-media-cedrus-hevc-Add-support-for-multiple-slices.patch +++ b/projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch @@ -80,7 +80,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -332,6 +332,7 @@ static int cedrus_s_fmt_vid_out(struct f +@@ -340,6 +340,7 @@ static int cedrus_s_fmt_vid_out(struct f switch (ctx->src_fmt.pixelformat) { case V4L2_PIX_FMT_H264_SLICE: diff --git a/projects/Allwinner/patches/linux/0018-arm64-dts-allwinner-a64-Add-I2S2-node.patch b/projects/Allwinner/patches/linux/0018-arm64-dts-allwinner-a64-Add-I2S2-node.patch deleted file mode 100644 index e47e95c9fb..0000000000 --- a/projects/Allwinner/patches/linux/0018-arm64-dts-allwinner-a64-Add-I2S2-node.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 0175a3d5680924d3d64ee8181b50c8b06ee715d1 Mon Sep 17 00:00:00 2001 -From: Marcus Cooper -Date: Fri, 30 Oct 2020 15:46:45 +0100 -Subject: [PATCH 18/44] arm64: dts: allwinner: a64: Add I2S2 node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add the I2S2 node connected to the HDMI interface. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Marcus Cooper -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard -Acked-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201030144648.397824-13-peron.clem@gmail.com ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -846,6 +846,20 @@ - status = "disabled"; - }; - -+ i2s2: i2s@1c22800 { -+ #sound-dai-cells = <0>; -+ compatible = "allwinner,sun50i-a64-i2s", -+ "allwinner,sun8i-h3-i2s"; -+ reg = <0x01c22800 0x400>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; -+ clock-names = "apb", "mod"; -+ resets = <&ccu RST_BUS_I2S2>; -+ dma-names = "rx", "tx"; -+ dmas = <&dma 27>, <&dma 27>; -+ status = "disabled"; -+ }; -+ - dai: dai@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-codec-i2s"; diff --git a/projects/Allwinner/patches/linux/0027-media-cedrus-hevc-tiles-hack.patch b/projects/Allwinner/patches/linux/0018-media-cedrus-hevc-tiles-hack.patch similarity index 98% rename from projects/Allwinner/patches/linux/0027-media-cedrus-hevc-tiles-hack.patch rename to projects/Allwinner/patches/linux/0018-media-cedrus-hevc-tiles-hack.patch index e1eb4ebb84..670f87b6d3 100644 --- a/projects/Allwinner/patches/linux/0027-media-cedrus-hevc-tiles-hack.patch +++ b/projects/Allwinner/patches/linux/0018-media-cedrus-hevc-tiles-hack.patch @@ -12,15 +12,15 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -135,6 +135,8 @@ struct cedrus_ctx { +@@ -142,6 +142,8 @@ struct cedrus_ctx { ssize_t mv_col_buf_unit_size; void *neighbor_info_buf; dma_addr_t neighbor_info_buf_addr; + void *entry_points_buf; + dma_addr_t entry_points_buf_addr; } h265; - } codec; - }; + struct { + unsigned int last_frame_p_type; --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -301,6 +301,61 @@ static void cedrus_h265_write_scaling_li diff --git a/projects/Allwinner/patches/linux/0019-arm-dts-sunxi-h3-h5-Add-I2S2-node.patch b/projects/Allwinner/patches/linux/0019-arm-dts-sunxi-h3-h5-Add-I2S2-node.patch deleted file mode 100644 index dfd107a942..0000000000 --- a/projects/Allwinner/patches/linux/0019-arm-dts-sunxi-h3-h5-Add-I2S2-node.patch +++ /dev/null @@ -1,42 +0,0 @@ -From fd67e65487b4e5e2a93df2868043302a99f93098 Mon Sep 17 00:00:00 2001 -From: Marcus Cooper -Date: Fri, 30 Oct 2020 15:46:48 +0100 -Subject: [PATCH 19/44] arm: dts: sunxi: h3/h5: Add I2S2 node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add H3/H5 I2S2 node connected to the HDMI interface. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Marcus Cooper -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard -Acked-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201030144648.397824-16-peron.clem@gmail.com ---- - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi -+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -662,6 +662,19 @@ - status = "disabled"; - }; - -+ i2s2: i2s@1c22800 { -+ #sound-dai-cells = <0>; -+ compatible = "allwinner,sun8i-h3-i2s"; -+ reg = <0x01c22800 0x400>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; -+ clock-names = "apb", "mod"; -+ dmas = <&dma 27>; -+ resets = <&ccu RST_BUS_I2S2>; -+ dma-names = "tx"; -+ status = "disabled"; -+ }; -+ - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-codec"; diff --git a/projects/Allwinner/patches/linux/0028-media-cedrus-Add-callback-for-buffer-cleanup.patch b/projects/Allwinner/patches/linux/0019-media-cedrus-Add-callback-for-buffer-cleanup.patch similarity index 91% rename from projects/Allwinner/patches/linux/0028-media-cedrus-Add-callback-for-buffer-cleanup.patch rename to projects/Allwinner/patches/linux/0019-media-cedrus-Add-callback-for-buffer-cleanup.patch index b8006ee8a9..f8ebf3ad21 100644 --- a/projects/Allwinner/patches/linux/0028-media-cedrus-Add-callback-for-buffer-cleanup.patch +++ b/projects/Allwinner/patches/linux/0019-media-cedrus-Add-callback-for-buffer-cleanup.patch @@ -11,7 +11,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -149,6 +149,7 @@ struct cedrus_dec_ops { +@@ -164,6 +164,7 @@ struct cedrus_dec_ops { int (*start)(struct cedrus_ctx *ctx); void (*stop)(struct cedrus_ctx *ctx); void (*trigger)(struct cedrus_ctx *ctx); @@ -21,7 +21,7 @@ Signed-off-by: Jernej Skrabec struct cedrus_variant { --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -455,6 +455,18 @@ static int cedrus_buf_prepare(struct vb2 +@@ -463,6 +463,18 @@ static int cedrus_buf_prepare(struct vb2 return 0; } @@ -40,7 +40,7 @@ Signed-off-by: Jernej Skrabec static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) { struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); -@@ -535,6 +547,7 @@ static void cedrus_buf_request_complete( +@@ -547,6 +559,7 @@ static void cedrus_buf_request_complete( static struct vb2_ops cedrus_qops = { .queue_setup = cedrus_queue_setup, .buf_prepare = cedrus_buf_prepare, diff --git a/projects/Allwinner/patches/linux/0020-arm64-dts-allwinner-h6-PineH64-model-B-Add-wifi.patch b/projects/Allwinner/patches/linux/0020-arm64-dts-allwinner-h6-PineH64-model-B-Add-wifi.patch deleted file mode 100644 index 12fd8d08a8..0000000000 --- a/projects/Allwinner/patches/linux/0020-arm64-dts-allwinner-h6-PineH64-model-B-Add-wifi.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 3c970c9e87e403b190407dec5c6e4745aef78e6a Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 30 Oct 2020 18:25:30 +0100 -Subject: [PATCH 20/44] arm64: dts: allwinner: h6: PineH64 model B: Add wifi - -PineH64 model B contains RTL8723CS wifi+bt combo module. - -Since bluetooth support is not yet squared away, only wifi is enabled -for now. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard -Tested-by: -Acked-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201030172530.1096394-1-jernej.skrabec@siol.net ---- - .../dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts -@@ -10,6 +10,12 @@ - compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; - - /delete-node/ reg_gmac_3v3; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ -+ post-power-on-delay-ms = <200>; -+ }; - }; - - &hdmi_connector { -@@ -19,3 +25,12 @@ - &emac { - phy-supply = <®_aldo2>; - }; -+ -+&mmc1 { -+ vmmc-supply = <®_cldo3>; -+ vqmmc-supply = <®_aldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+}; diff --git a/projects/Allwinner/patches/linux/0029-media-cedrus-hevc-Improve-buffer-management.patch b/projects/Allwinner/patches/linux/0020-media-cedrus-hevc-Improve-buffer-management.patch similarity index 98% rename from projects/Allwinner/patches/linux/0029-media-cedrus-hevc-Improve-buffer-management.patch rename to projects/Allwinner/patches/linux/0020-media-cedrus-hevc-Improve-buffer-management.patch index fa357267c3..7c5ac09327 100644 --- a/projects/Allwinner/patches/linux/0029-media-cedrus-hevc-Improve-buffer-management.patch +++ b/projects/Allwinner/patches/linux/0020-media-cedrus-hevc-Improve-buffer-management.patch @@ -11,7 +11,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -96,6 +96,11 @@ struct cedrus_buffer { +@@ -103,6 +103,11 @@ struct cedrus_buffer { unsigned int position; enum cedrus_h264_pic_type pic_type; } h264; @@ -23,7 +23,7 @@ Signed-off-by: Jernej Skrabec } codec; }; -@@ -129,10 +134,6 @@ struct cedrus_ctx { +@@ -136,10 +141,6 @@ struct cedrus_ctx { ssize_t intra_pred_buf_size; } h264; struct { diff --git a/projects/Allwinner/patches/linux/0030-media-cedrus-h264-Improve-buffer-management.patch b/projects/Allwinner/patches/linux/0021-media-cedrus-h264-Improve-buffer-management.patch similarity index 99% rename from projects/Allwinner/patches/linux/0030-media-cedrus-h264-Improve-buffer-management.patch rename to projects/Allwinner/patches/linux/0021-media-cedrus-h264-Improve-buffer-management.patch index 648ade8589..72f2887df5 100644 --- a/projects/Allwinner/patches/linux/0030-media-cedrus-h264-Improve-buffer-management.patch +++ b/projects/Allwinner/patches/linux/0021-media-cedrus-h264-Improve-buffer-management.patch @@ -11,7 +11,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -95,6 +95,9 @@ struct cedrus_buffer { +@@ -102,6 +102,9 @@ struct cedrus_buffer { struct { unsigned int position; enum cedrus_h264_pic_type pic_type; diff --git a/projects/Allwinner/patches/linux/0031-WIp-10-bit-HEVC-support.patch b/projects/Allwinner/patches/linux/0022-WIp-10-bit-HEVC-support.patch similarity index 91% rename from projects/Allwinner/patches/linux/0031-WIp-10-bit-HEVC-support.patch rename to projects/Allwinner/patches/linux/0022-WIp-10-bit-HEVC-support.patch index 85477ccf2b..8d1ee5fde0 100644 --- a/projects/Allwinner/patches/linux/0031-WIp-10-bit-HEVC-support.patch +++ b/projects/Allwinner/patches/linux/0022-WIp-10-bit-HEVC-support.patch @@ -14,7 +14,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -301,7 +301,7 @@ static int cedrus_open(struct file *file +@@ -277,7 +277,7 @@ static int cedrus_open(struct file *file goto err_ctrls; } ctx->dst_fmt.pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12; @@ -23,7 +23,7 @@ Signed-off-by: Jernej Skrabec ctx->src_fmt.pixelformat = V4L2_PIX_FMT_MPEG2_SLICE; /* * TILED_NV12 has more strict requirements, so copy the width and -@@ -309,7 +309,7 @@ static int cedrus_open(struct file *file +@@ -285,7 +285,7 @@ static int cedrus_open(struct file *file */ ctx->src_fmt.width = ctx->dst_fmt.width; ctx->src_fmt.height = ctx->dst_fmt.height; @@ -55,7 +55,7 @@ Signed-off-by: Jernej Skrabec reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | --- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -498,6 +498,10 @@ +@@ -499,6 +499,10 @@ #define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) @@ -68,7 +68,7 @@ Signed-off-by: Jernej Skrabec #define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \ --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -93,7 +93,7 @@ static struct cedrus_format *cedrus_find +@@ -100,7 +100,7 @@ static struct cedrus_format *cedrus_find return &cedrus_formats[i]; } @@ -77,7 +77,7 @@ Signed-off-by: Jernej Skrabec { unsigned int width = pix_fmt->width; unsigned int height = pix_fmt->height; -@@ -147,6 +147,17 @@ void cedrus_prepare_format(struct v4l2_p +@@ -155,6 +155,17 @@ void cedrus_prepare_format(struct v4l2_p break; } @@ -95,7 +95,7 @@ Signed-off-by: Jernej Skrabec pix_fmt->width = width; pix_fmt->height = height; -@@ -239,17 +250,27 @@ static int cedrus_try_fmt_vid_cap(struct +@@ -247,17 +258,27 @@ static int cedrus_try_fmt_vid_cap(struct struct cedrus_ctx *ctx = cedrus_file2ctx(file); struct cedrus_dev *dev = ctx->dev; struct v4l2_pix_format *pix_fmt = &f->fmt.pix; @@ -124,7 +124,7 @@ Signed-off-by: Jernej Skrabec return 0; } -@@ -267,8 +288,7 @@ static int cedrus_try_fmt_vid_out(struct +@@ -275,8 +296,7 @@ static int cedrus_try_fmt_vid_out(struct if (!fmt) return -EINVAL; @@ -134,7 +134,7 @@ Signed-off-by: Jernej Skrabec return 0; } -@@ -349,7 +369,7 @@ static int cedrus_s_fmt_vid_out(struct f +@@ -357,7 +377,7 @@ static int cedrus_s_fmt_vid_out(struct f ctx->dst_fmt.quantization = f->fmt.pix.quantization; ctx->dst_fmt.width = ctx->src_fmt.width; ctx->dst_fmt.height = ctx->src_fmt.height; diff --git a/projects/Allwinner/patches/linux/0032-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch b/projects/Allwinner/patches/linux/0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch similarity index 77% rename from projects/Allwinner/patches/linux/0032-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch rename to projects/Allwinner/patches/linux/0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch index e16c2ce89e..c9e25a8c1c 100644 --- a/projects/Allwinner/patches/linux/0032-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch +++ b/projects/Allwinner/patches/linux/0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch @@ -17,7 +17,7 @@ Signed-off-by: Jernej Skrabec +static int cedrus_try_ctrl(struct v4l2_ctrl *ctrl) +{ -+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS) { ++ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { + const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; + + if (sps->chroma_format_idc != 1) @@ -62,39 +62,39 @@ Signed-off-by: Jernej Skrabec static const struct cedrus_control cedrus_controls[] = { { .cfg = { -@@ -60,6 +104,7 @@ static const struct cedrus_control cedru +@@ -56,6 +100,7 @@ static const struct cedrus_control cedru { .cfg = { - .id = V4L2_CID_MPEG_VIDEO_H264_SPS, + .id = V4L2_CID_STATELESS_H264_SPS, + .ops = &cedrus_ctrl_ops, }, .codec = CEDRUS_CODEC_H264, - .required = true, -@@ -106,6 +151,7 @@ static const struct cedrus_control cedru + }, +@@ -114,6 +159,7 @@ static const struct cedrus_control cedru { .cfg = { .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, + .ops = &cedrus_ctrl_ops, }, .codec = CEDRUS_CODEC_H265, - .required = true, -@@ -534,7 +580,8 @@ static const struct cedrus_variant sun50 - - static const struct cedrus_variant sun50i_h6_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED | -- CEDRUS_CAPABILITY_H265_DEC, + }, +@@ -544,7 +590,8 @@ static const struct cedrus_variant sun50 + CEDRUS_CAPABILITY_MPEG2_DEC | + CEDRUS_CAPABILITY_H264_DEC | + CEDRUS_CAPABILITY_H265_DEC | +- CEDRUS_CAPABILITY_VP8_DEC, + CEDRUS_CAPABILITY_H265_DEC | + CEDRUS_CAPABILITY_H265_10_DEC, - .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, .mod_rate = 600000000, }; + --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -28,6 +28,7 @@ - - #define CEDRUS_CAPABILITY_UNTILED BIT(0) - #define CEDRUS_CAPABILITY_H265_DEC BIT(1) -+#define CEDRUS_CAPABILITY_H265_10_DEC BIT(2) - - #define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) +@@ -32,6 +32,7 @@ + #define CEDRUS_CAPABILITY_H264_DEC BIT(2) + #define CEDRUS_CAPABILITY_MPEG2_DEC BIT(3) + #define CEDRUS_CAPABILITY_VP8_DEC BIT(4) ++#define CEDRUS_CAPABILITY_H265_10_DEC BIT(5) + enum cedrus_codec { + CEDRUS_CODEC_MPEG2, diff --git a/projects/Allwinner/patches/linux/0034-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch b/projects/Allwinner/patches/linux/0024-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch similarity index 100% rename from projects/Allwinner/patches/linux/0034-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch rename to projects/Allwinner/patches/linux/0024-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch diff --git a/projects/Allwinner/patches/linux/0035-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch b/projects/Allwinner/patches/linux/0025-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch similarity index 89% rename from projects/Allwinner/patches/linux/0035-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch rename to projects/Allwinner/patches/linux/0025-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch index 1f8eab64dd..89011ed4c1 100644 --- a/projects/Allwinner/patches/linux/0035-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch +++ b/projects/Allwinner/patches/linux/0025-drm-sun4i-Reimplement-plane-z-position-setting-logic.patch @@ -152,10 +152,10 @@ Signed-off-by: Jernej Skrabec + mixer->channel_zpos[channel] = enable ? zpos : -1; } - static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, -@@ -267,11 +240,9 @@ static void sun8i_ui_layer_atomic_disabl - struct drm_plane_state *old_state) - { + static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel, +@@ -294,11 +267,9 @@ static void sun8i_ui_layer_atomic_disabl + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; @@ -166,21 +166,21 @@ Signed-off-by: Jernej Skrabec } static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, -@@ -279,12 +250,11 @@ static void sun8i_ui_layer_atomic_update - { +@@ -310,12 +281,11 @@ static void sun8i_ui_layer_atomic_update + plane); struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); - unsigned int zpos = plane->state->normalized_zpos; + unsigned int zpos = new_state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; - if (!plane->state->visible) { + if (!new_state->visible) { sun8i_ui_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + layer->overlay, false, 0); return; } -@@ -295,7 +265,7 @@ static void sun8i_ui_layer_atomic_update +@@ -328,7 +298,7 @@ static void sun8i_ui_layer_atomic_update sun8i_ui_layer_update_buffer(mixer, layer->channel, layer->overlay, plane); sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, @@ -234,10 +234,10 @@ Signed-off-by: Jernej Skrabec + mixer->channel_zpos[channel] = enable ? zpos : -1; } - static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, -@@ -370,11 +344,9 @@ static void sun8i_vi_layer_atomic_disabl - struct drm_plane_state *old_state) - { + static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, +@@ -398,11 +372,9 @@ static void sun8i_vi_layer_atomic_disabl + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, + plane); struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; @@ -248,21 +248,21 @@ Signed-off-by: Jernej Skrabec } static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, -@@ -382,12 +354,11 @@ static void sun8i_vi_layer_atomic_update - { +@@ -414,12 +386,11 @@ static void sun8i_vi_layer_atomic_update + plane); struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); - unsigned int zpos = plane->state->normalized_zpos; + unsigned int zpos = new_state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; - if (!plane->state->visible) { + if (!new_state->visible) { sun8i_vi_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + layer->overlay, false, 0); return; } -@@ -398,7 +369,7 @@ static void sun8i_vi_layer_atomic_update +@@ -432,7 +403,7 @@ static void sun8i_vi_layer_atomic_update sun8i_vi_layer_update_buffer(mixer, layer->channel, layer->overlay, plane); sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, diff --git a/projects/Allwinner/patches/linux/0036-drm-sun4i-Don-t-use-update-regmap-variant-for-blend-.patch b/projects/Allwinner/patches/linux/0026-drm-sun4i-Don-t-use-update-regmap-variant-for-blend-.patch similarity index 100% rename from projects/Allwinner/patches/linux/0036-drm-sun4i-Don-t-use-update-regmap-variant-for-blend-.patch rename to projects/Allwinner/patches/linux/0026-drm-sun4i-Don-t-use-update-regmap-variant-for-blend-.patch diff --git a/projects/Allwinner/patches/linux/0037-drm-sun4i-mixer-Add-caching-support.patch b/projects/Allwinner/patches/linux/0027-drm-sun4i-mixer-Add-caching-support.patch similarity index 100% rename from projects/Allwinner/patches/linux/0037-drm-sun4i-mixer-Add-caching-support.patch rename to projects/Allwinner/patches/linux/0027-drm-sun4i-mixer-Add-caching-support.patch diff --git a/projects/Allwinner/patches/linux/0038-mfd-Add-support-for-AC200.patch b/projects/Allwinner/patches/linux/0028-mfd-Add-support-for-AC200.patch similarity index 100% rename from projects/Allwinner/patches/linux/0038-mfd-Add-support-for-AC200.patch rename to projects/Allwinner/patches/linux/0028-mfd-Add-support-for-AC200.patch diff --git a/projects/Allwinner/patches/linux/0039-net-phy-Add-support-for-AC200-EPHY.patch b/projects/Allwinner/patches/linux/0029-net-phy-Add-support-for-AC200-EPHY.patch similarity index 100% rename from projects/Allwinner/patches/linux/0039-net-phy-Add-support-for-AC200-EPHY.patch rename to projects/Allwinner/patches/linux/0029-net-phy-Add-support-for-AC200-EPHY.patch diff --git a/projects/Allwinner/patches/linux/0040-wip-H6-deinterlace.patch b/projects/Allwinner/patches/linux/0030-wip-H6-deinterlace.patch similarity index 99% rename from projects/Allwinner/patches/linux/0040-wip-H6-deinterlace.patch rename to projects/Allwinner/patches/linux/0030-wip-H6-deinterlace.patch index b5bb79679e..7c5eec8a1c 100644 --- a/projects/Allwinner/patches/linux/0040-wip-H6-deinterlace.patch +++ b/projects/Allwinner/patches/linux/0030-wip-H6-deinterlace.patch @@ -17,7 +17,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig -@@ -510,6 +510,19 @@ config VIDEO_QCOM_VENUS +@@ -574,6 +574,19 @@ config VIDEO_QCOM_VENUS on various Qualcomm SoCs. To compile this driver as a module choose m here. diff --git a/projects/Allwinner/patches/linux/0041-arm64-dts-h6-deinterlace.patch b/projects/Allwinner/patches/linux/0031-arm64-dts-h6-deinterlace.patch similarity index 97% rename from projects/Allwinner/patches/linux/0041-arm64-dts-h6-deinterlace.patch rename to projects/Allwinner/patches/linux/0031-arm64-dts-h6-deinterlace.patch index 87ec6f74f5..5d18560bb7 100644 --- a/projects/Allwinner/patches/linux/0041-arm64-dts-h6-deinterlace.patch +++ b/projects/Allwinner/patches/linux/0031-arm64-dts-h6-deinterlace.patch @@ -10,7 +10,7 @@ Signed-off-by: Jernej Skrabec --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -153,6 +153,17 @@ +@@ -160,6 +160,17 @@ }; }; diff --git a/projects/Allwinner/patches/linux/0042-ASoC-sun4i-i2s-Add-parenthesis-around-macro-argument.patch b/projects/Allwinner/patches/linux/0032-ASoC-sun4i-i2s-Add-parenthesis-around-macro-argument.patch similarity index 100% rename from projects/Allwinner/patches/linux/0042-ASoC-sun4i-i2s-Add-parenthesis-around-macro-argument.patch rename to projects/Allwinner/patches/linux/0032-ASoC-sun4i-i2s-Add-parenthesis-around-macro-argument.patch diff --git a/projects/Allwinner/patches/linux/0043-WIP-I2S-multi-channel.patch b/projects/Allwinner/patches/linux/0033-WIP-I2S-multi-channel.patch similarity index 97% rename from projects/Allwinner/patches/linux/0043-WIP-I2S-multi-channel.patch rename to projects/Allwinner/patches/linux/0033-WIP-I2S-multi-channel.patch index 520eca52ee..3dfb5efe03 100644 --- a/projects/Allwinner/patches/linux/0043-WIP-I2S-multi-channel.patch +++ b/projects/Allwinner/patches/linux/0033-WIP-I2S-multi-channel.patch @@ -230,7 +230,7 @@ Signed-off-by: Jernej Skrabec regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK, SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset)); -@@ -1198,8 +1239,14 @@ static const struct reg_default sun8i_i2 +@@ -1196,8 +1237,14 @@ static const struct reg_default sun8i_i2 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, @@ -247,7 +247,7 @@ Signed-off-by: Jernej Skrabec { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 }, { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, }; -@@ -1212,9 +1259,18 @@ static const struct reg_default sun50i_h +@@ -1210,9 +1257,18 @@ static const struct reg_default sun50i_h { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, @@ -269,7 +269,7 @@ Signed-off-by: Jernej Skrabec { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 }, { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 }, { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 }, -@@ -1287,7 +1343,7 @@ static int sun4i_i2s_runtime_resume(stru +@@ -1285,7 +1341,7 @@ static int sun4i_i2s_runtime_resume(stru /* Enable the first output line */ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_SDO_EN_MASK, @@ -278,7 +278,7 @@ Signed-off-by: Jernej Skrabec ret = clk_prepare_enable(i2s->mod_clk); if (ret) { -@@ -1529,6 +1585,7 @@ static int sun4i_i2s_probe(struct platfo +@@ -1527,6 +1583,7 @@ static int sun4i_i2s_probe(struct platfo i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; i2s->capture_dma_data.maxburst = 8; diff --git a/projects/Allwinner/patches/linux/0033-media-cedrus-Add-support-for-VP8-decoding.patch b/projects/Allwinner/patches/linux/0033-media-cedrus-Add-support-for-VP8-decoding.patch deleted file mode 100644 index 6c4320868b..0000000000 --- a/projects/Allwinner/patches/linux/0033-media-cedrus-Add-support-for-VP8-decoding.patch +++ /dev/null @@ -1,985 +0,0 @@ -From 574ba48fa87225fbf3e39ffd2b11a6fb93cb6c98 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 20 May 2020 23:01:29 +0200 -Subject: [PATCH 33/44] media: cedrus: Add support for VP8 decoding - -VP8 in Cedrus shares same engine as H264. - -Note that it seems necessary to call bitstream parsing functions, -to parse frame header, otherwise decoded image is garbage. This is -contrary to what is driver supposed to do. However, values are not -really used, so this might be acceptable. It's possible that bitstream -parsing functions set some internal VPU state, which is later necessary -for proper decoding. Biggest suspect is "VP8 probs update" trigger. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/Makefile | 3 +- - drivers/staging/media/sunxi/cedrus/cedrus.c | 8 + - drivers/staging/media/sunxi/cedrus/cedrus.h | 15 + - .../staging/media/sunxi/cedrus/cedrus_dec.c | 5 + - .../staging/media/sunxi/cedrus/cedrus_hw.c | 1 + - .../staging/media/sunxi/cedrus/cedrus_regs.h | 80 ++ - .../staging/media/sunxi/cedrus/cedrus_video.c | 9 + - .../staging/media/sunxi/cedrus/cedrus_vp8.c | 699 ++++++++++++++++++ - 8 files changed, 819 insertions(+), 1 deletion(-) - create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_vp8.c - ---- a/drivers/staging/media/sunxi/cedrus/Makefile -+++ b/drivers/staging/media/sunxi/cedrus/Makefile -@@ -2,4 +2,5 @@ - obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o - - sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ -- cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o -+ cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o \ -+ cedrus_vp8.o ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -195,6 +195,13 @@ static const struct cedrus_control cedru - .codec = CEDRUS_CODEC_H265, - .required = false, - }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER, -+ }, -+ .codec = CEDRUS_CODEC_VP8, -+ .required = true, -+ }, - }; - - #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) -@@ -446,6 +453,7 @@ static int cedrus_probe(struct platform_ - dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; - dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; - dev->dec_ops[CEDRUS_CODEC_H265] = &cedrus_dec_ops_h265; -+ dev->dec_ops[CEDRUS_CODEC_VP8] = &cedrus_dec_ops_vp8; - - mutex_init(&dev->dev_mutex); - ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -36,6 +36,7 @@ enum cedrus_codec { - CEDRUS_CODEC_MPEG2, - CEDRUS_CODEC_H264, - CEDRUS_CODEC_H265, -+ CEDRUS_CODEC_VP8, - CEDRUS_CODEC_LAST, - }; - -@@ -78,6 +79,10 @@ struct cedrus_h265_run { - const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; - }; - -+struct cedrus_vp8_run { -+ const struct v4l2_ctrl_vp8_frame_header *slice_params; -+}; -+ - struct cedrus_run { - struct vb2_v4l2_buffer *src; - struct vb2_v4l2_buffer *dst; -@@ -86,6 +91,7 @@ struct cedrus_run { - struct cedrus_h264_run h264; - struct cedrus_mpeg2_run mpeg2; - struct cedrus_h265_run h265; -+ struct cedrus_vp8_run vp8; - }; - }; - -@@ -143,6 +149,14 @@ struct cedrus_ctx { - void *entry_points_buf; - dma_addr_t entry_points_buf_addr; - } h265; -+ struct { -+ unsigned int last_frame_p_type; -+ unsigned int last_filter_type; -+ unsigned int last_sharpness_level; -+ -+ u8 *entropy_probs_buf; -+ dma_addr_t entropy_probs_buf_dma; -+ } vp8; - } codec; - }; - -@@ -190,6 +204,7 @@ struct cedrus_dev { - extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; - extern struct cedrus_dec_ops cedrus_dec_ops_h264; - extern struct cedrus_dec_ops cedrus_dec_ops_h265; -+extern struct cedrus_dec_ops cedrus_dec_ops_vp8; - - static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) - { ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -72,6 +72,11 @@ void cedrus_device_run(void *priv) - V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX); - break; - -+ case V4L2_PIX_FMT_VP8_FRAME: -+ run.vp8.slice_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER); -+ break; -+ - default: - break; - } ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -48,6 +48,7 @@ int cedrus_engine_enable(struct cedrus_c - break; - - case CEDRUS_CODEC_H264: -+ case CEDRUS_CODEC_VP8: - reg |= VE_MODE_DEC_H264; - break; - ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -552,6 +552,7 @@ - #define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) - - #define VE_H264_CTRL 0x220 -+#define VE_H264_CTRL_VP8 BIT(29) - #define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) - #define VE_H264_CTRL_DECODE_ERR_INT BIT(1) - #define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) -@@ -561,7 +562,12 @@ - VE_H264_CTRL_SLICE_DECODE_INT) - - #define VE_H264_TRIGGER_TYPE 0x224 -+#define VE_H264_TRIGGER_TYPE_PROBABILITY(x) SHIFT_AND_MASK_BITS(x, 31, 24) -+#define VE_H264_TRIGGER_TYPE_BIN_LENS(x) SHIFT_AND_MASK_BITS((x) - 1, 18, 16) - #define VE_H264_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8) -+#define VE_H264_TRIGGER_TYPE_VP8_GET_BITS (15 << 0) -+#define VE_H264_TRIGGER_TYPE_VP8_UPDATE_COEF (14 << 0) -+#define VE_H264_TRIGGER_TYPE_VP8_SLICE_DECODE (10 << 0) - #define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) - #define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) - #define VE_H264_TRIGGER_TYPE_FLUSH_BITS (3 << 0) -@@ -571,6 +577,7 @@ - #define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT - #define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT - #define VE_H264_STATUS_VLD_BUSY BIT(8) -+#define VE_H264_STATUS_VP8_UPPROB_BUSY BIT(17) - - #define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK - -@@ -589,10 +596,83 @@ - #define VE_H264_OUTPUT_FRAME_IDX 0x24c - #define VE_H264_EXTRA_BUFFER1 0x250 - #define VE_H264_EXTRA_BUFFER2 0x254 -+#define VE_H264_MB_ADDR 0x260 -+#define VE_H264_ERROR_CASE 0x2b8 - #define VE_H264_BASIC_BITS 0x2dc - #define VE_AVC_SRAM_PORT_OFFSET 0x2e0 - #define VE_AVC_SRAM_PORT_DATA 0x2e4 - -+#define VE_VP8_PPS 0x214 -+#define VE_VP8_PPS_PIC_TYPE_P_FRAME BIT(31) -+#define VE_VP8_PPS_LAST_SHARPNESS_LEVEL(v) SHIFT_AND_MASK_BITS(v, 30, 28) -+#define VE_VP8_PPS_LAST_PIC_TYPE_P_FRAME BIT(27) -+#define VE_VP8_PPS_ALTREF_SIGN_BIAS BIT(26) -+#define VE_VP8_PPS_GOLDEN_SIGN_BIAS BIT(25) -+#define VE_VP8_PPS_RELOAD_ENTROPY_PROBS BIT(24) -+#define VE_VP8_PPS_REFRESH_ENTROPY_PROBS BIT(23) -+#define VE_VP8_PPS_MB_NO_COEFF_SKIP BIT(22) -+#define VE_VP8_PPS_TOKEN_PARTITION(v) SHIFT_AND_MASK_BITS(v, 21, 20) -+#define VE_VP8_PPS_MODE_REF_LF_DELTA_UPDATE BIT(19) -+#define VE_VP8_PPS_MODE_REF_LF_DELTA_ENABLE BIT(18) -+#define VE_VP8_PPS_LOOP_FILTER_LEVEL(v) SHIFT_AND_MASK_BITS(v, 17, 12) -+#define VE_VP8_PPS_LOOP_FILTER_SIMPLE BIT(11) -+#define VE_VP8_PPS_SHARPNESS_LEVEL(v) SHIFT_AND_MASK_BITS(v, 10, 8) -+#define VE_VP8_PPS_LAST_LOOP_FILTER_SIMPLE BIT(7) -+#define VE_VP8_PPS_SEGMENTATION_ENABLE BIT(6) -+#define VE_VP8_PPS_MB_SEGMENT_ABS_DELTA BIT(5) -+#define VE_VP8_PPS_UPDATE_MB_SEGMENTATION_MAP BIT(4) -+#define VE_VP8_PPS_FULL_PIXEL BIT(3) -+#define VE_VP8_PPS_BILINEAR_MC_FILTER BIT(2) -+#define VE_VP8_PPS_FILTER_TYPE_SIMPLE BIT(1) -+#define VE_VP8_PPS_LPF_DISABLE BIT(0) -+ -+#define VE_VP8_QP_INDEX_DELTA 0x218 -+#define VE_VP8_QP_INDEX_DELTA_UVAC(v) SHIFT_AND_MASK_BITS(v, 31, 27) -+#define VE_VP8_QP_INDEX_DELTA_UVDC(v) SHIFT_AND_MASK_BITS(v, 26, 22) -+#define VE_VP8_QP_INDEX_DELTA_Y2AC(v) SHIFT_AND_MASK_BITS(v, 21, 17) -+#define VE_VP8_QP_INDEX_DELTA_Y2DC(v) SHIFT_AND_MASK_BITS(v, 16, 12) -+#define VE_VP8_QP_INDEX_DELTA_Y1DC(v) SHIFT_AND_MASK_BITS(v, 11, 7) -+#define VE_VP8_QP_INDEX_DELTA_BASE_QINDEX(v) SHIFT_AND_MASK_BITS(v, 6, 0) -+ -+#define VE_VP8_PART_SIZE_OFFSET 0x21c -+#define VE_VP8_ENTROPY_PROBS_ADDR 0x250 -+#define VE_VP8_FIRST_DATA_PART_LEN 0x254 -+ -+#define VE_VP8_FSIZE 0x258 -+#define VE_VP8_FSIZE_WIDTH(w) \ -+ SHIFT_AND_MASK_BITS(DIV_ROUND_UP(w, 16), 15, 8) -+#define VE_VP8_FSIZE_HEIGHT(h) \ -+ SHIFT_AND_MASK_BITS(DIV_ROUND_UP(h, 16), 7, 0) -+ -+#define VE_VP8_PICSIZE 0x25c -+#define VE_VP8_PICSIZE_WIDTH(w) SHIFT_AND_MASK_BITS(w, 27, 16) -+#define VE_VP8_PICSIZE_HEIGHT(h) SHIFT_AND_MASK_BITS(h, 11, 0) -+ -+#define VE_VP8_REC_LUMA 0x2ac -+#define VE_VP8_FWD_LUMA 0x2b0 -+#define VE_VP8_BWD_LUMA 0x2b4 -+#define VE_VP8_REC_CHROMA 0x2d0 -+#define VE_VP8_FWD_CHROMA 0x2d4 -+#define VE_VP8_BWD_CHROMA 0x2d8 -+#define VE_VP8_ALT_LUMA 0x2e8 -+#define VE_VP8_ALT_CHROMA 0x2ec -+ -+#define VE_VP8_SEGMENT_FEAT_MB_LV0 0x2f0 -+#define VE_VP8_SEGMENT_FEAT_MB_LV1 0x2f4 -+ -+#define VE_VP8_SEGMENT3(v) SHIFT_AND_MASK_BITS(v, 31, 24) -+#define VE_VP8_SEGMENT2(v) SHIFT_AND_MASK_BITS(v, 23, 16) -+#define VE_VP8_SEGMENT1(v) SHIFT_AND_MASK_BITS(v, 15, 8) -+#define VE_VP8_SEGMENT0(v) SHIFT_AND_MASK_BITS(v, 7, 0) -+ -+#define VE_VP8_REF_LF_DELTA 0x2f8 -+#define VE_VP8_MODE_LF_DELTA 0x2fc -+ -+#define VE_VP8_LF_DELTA3(v) SHIFT_AND_MASK_BITS(v, 30, 24) -+#define VE_VP8_LF_DELTA2(v) SHIFT_AND_MASK_BITS(v, 22, 16) -+#define VE_VP8_LF_DELTA1(v) SHIFT_AND_MASK_BITS(v, 14, 8) -+#define VE_VP8_LF_DELTA0(v) SHIFT_AND_MASK_BITS(v, 6, 0) -+ - #define VE_ISP_INPUT_SIZE 0xa00 - #define VE_ISP_INPUT_STRIDE 0xa04 - #define VE_ISP_CTRL 0xa08 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -49,6 +49,10 @@ static struct cedrus_format cedrus_forma - .capabilities = CEDRUS_CAPABILITY_H265_DEC, - }, - { -+ .pixelformat = V4L2_PIX_FMT_VP8_FRAME, -+ .directions = CEDRUS_DECODE_SRC, -+ }, -+ { - .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, - .directions = CEDRUS_DECODE_DST, - }, -@@ -110,6 +114,7 @@ void cedrus_prepare_format(struct v4l2_p - case V4L2_PIX_FMT_MPEG2_SLICE: - case V4L2_PIX_FMT_H264_SLICE: - case V4L2_PIX_FMT_HEVC_SLICE: -+ case V4L2_PIX_FMT_VP8_FRAME: - /* Zero bytes per line for encoded source. */ - bytesperline = 0; - /* Choose some minimum size since this can't be 0 */ -@@ -506,6 +511,10 @@ static int cedrus_start_streaming(struct - ctx->current_codec = CEDRUS_CODEC_H265; - break; - -+ case V4L2_PIX_FMT_VP8_FRAME: -+ ctx->current_codec = CEDRUS_CODEC_VP8; -+ break; -+ - default: - return -EINVAL; - } ---- /dev/null -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_vp8.c -@@ -0,0 +1,699 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Cedrus VPU driver -+ * -+ * Copyright (c) 2019 Jernej Skrabec -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "cedrus.h" -+#include "cedrus_hw.h" -+#include "cedrus_regs.h" -+ -+#define CEDRUS_ENTROPY_PROBS_SIZE 0x2400 -+#define VP8_PROB_HALF 128 -+ -+static const u8 prob_table_init[] = { -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xB0, 0xF6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDF, 0xF1, 0xFC, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF9, 0xFD, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0xFC, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xEA, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xF6, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xEF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFE, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF8, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFB, 0xFF, 0xFE, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFD, 0xFE, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFB, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFE, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFA, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD9, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xE1, 0xFC, 0xF1, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xEA, 0xFA, 0xF1, 0xFA, 0xFD, 0xFF, 0xFD, 0xFE, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xDF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEE, 0xFD, 0xFE, 0xFE, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF8, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF9, 0xFE, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFD, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF7, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFD, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xFD, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xBA, 0xFB, 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEA, 0xFB, 0xF4, 0xFE, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFB, 0xFB, 0xF3, 0xFD, 0xFE, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFD, 0xFE, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xEC, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFB, 0xFD, 0xFD, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFA, 0xFE, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFE, 0xF9, 0xFD, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFD, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF6, 0xFD, 0xFD, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFC, 0xFE, 0xFB, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xFC, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF8, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFD, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFB, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xF5, 0xFB, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFD, 0xFD, 0xFE, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFB, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFD, 0xFE, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF9, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91, 0x9C, 0xA3, 0x80, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6E, 0x6F, 0x96, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x78, 0x5A, 0x4F, 0x85, 0x57, 0x55, 0x50, 0x6F, -+ 0x97, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x93, 0x88, 0x12, 0x00, 0x6A, 0x91, 0x01, 0x00, 0xB3, 0x79, 0x01, 0x00, -+ 0xDF, 0x01, 0x22, 0x00, 0xD0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x01, 0x01, 0x8F, -+ 0x0E, 0x12, 0x0E, 0x6B, 0x87, 0x40, 0x39, 0x44, 0x3C, 0x38, 0x80, 0x41, -+ 0x9F, 0x86, 0x80, 0x22, 0xEA, 0xBC, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x84, 0x02, 0x04, 0x06, 0x80, 0x81, 0x82, 0x83, 0x80, 0x02, 0x04, 0x06, -+ 0x81, 0x82, 0x83, 0x84, 0x80, 0x02, 0x81, 0x04, 0x82, 0x83, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x08, -+ 0x04, 0x06, 0x80, 0x81, 0x82, 0x83, 0x0A, 0x0C, 0x84, 0x85, 0x86, 0x87, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x08, 0x04, 0x06, 0x80, 0x81, -+ 0x82, 0x83, 0x0A, 0x0C, 0x84, 0x85, 0x86, 0x87, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x83, 0x02, 0x82, 0x04, 0x80, 0x81, 0x00, 0x00, 0x80, 0x02, 0x81, 0x04, -+ 0x82, 0x06, 0x08, 0x0C, 0x83, 0x0A, 0x85, 0x86, 0x84, 0x0E, 0x87, 0x10, -+ 0x88, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x8A, 0x02, 0x8B, 0x04, 0x8C, 0x8D, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x87, 0x02, 0x85, 0x04, 0x86, 0x06, 0x88, 0x89, -+}; -+ -+static const u8 vp8_mv_update_prob[2][19] = { -+ { 237, 246, 253, 253, 254, 254, 254, 254, 254, -+ 254, 254, 254, 254, 254, 250, 250, 252, 254, 254 }, -+ { 231, 243, 245, 253, 254, 254, 254, 254, 254, -+ 254, 254, 254, 254, 254, 251, 251, 254, 254, 254 } -+}; -+ -+static uint8_t read_bits(struct cedrus_dev *dev, unsigned int bits_count, -+ unsigned int probability) -+{ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_VP8_GET_BITS | -+ VE_H264_TRIGGER_TYPE_BIN_LENS(bits_count) | -+ VE_H264_TRIGGER_TYPE_PROBABILITY(probability)); -+ -+ while (cedrus_read(dev, VE_H264_STATUS) & VE_H264_STATUS_VLD_BUSY) -+ ; -+ -+ return cedrus_read(dev, VE_H264_BASIC_BITS); -+} -+ -+static void get_delta_q(struct cedrus_dev *dev) -+{ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 4, VP8_PROB_HALF); -+ read_bits(dev, 1, VP8_PROB_HALF); -+ } -+} -+ -+static void process_segmentation_info(struct cedrus_dev *dev) -+{ -+ int update = read_bits(dev, 1, VP8_PROB_HALF); -+ int i; -+ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 1, VP8_PROB_HALF); -+ -+ for (i = 0; i < 4; i++) -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 7, VP8_PROB_HALF); -+ read_bits(dev, 1, VP8_PROB_HALF); -+ } -+ -+ for (i = 0; i < 4; i++) -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 6, VP8_PROB_HALF); -+ read_bits(dev, 1, VP8_PROB_HALF); -+ } -+ } -+ -+ if (update) -+ for (i = 0; i < 3; i++) -+ if (read_bits(dev, 1, VP8_PROB_HALF)) -+ read_bits(dev, 8, VP8_PROB_HALF); -+} -+ -+static void process_ref_lf_delta_info(struct cedrus_dev *dev) -+{ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ int i; -+ -+ for (i = 0; i < 4; i++) -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 6, VP8_PROB_HALF); -+ read_bits(dev, 1, VP8_PROB_HALF); -+ } -+ -+ for (i = 0; i < 4; i++) -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 6, VP8_PROB_HALF); -+ read_bits(dev, 1, VP8_PROB_HALF); -+ } -+ } -+} -+ -+static void process_ref_frame_info(struct cedrus_dev *dev) -+{ -+ u8 refresh_golden_frame = read_bits(dev, 1, VP8_PROB_HALF); -+ u8 refresh_alt_ref_frame = read_bits(dev, 1, VP8_PROB_HALF); -+ -+ if (!refresh_golden_frame) -+ read_bits(dev, 2, VP8_PROB_HALF); -+ -+ if (!refresh_alt_ref_frame) -+ read_bits(dev, 2, VP8_PROB_HALF); -+ -+ read_bits(dev, 1, VP8_PROB_HALF); -+ read_bits(dev, 1, VP8_PROB_HALF); -+} -+ -+static void cedrus_read_header(struct cedrus_dev *dev, -+ const struct v4l2_ctrl_vp8_frame_header *slice) -+{ -+ int i, j; -+ -+ if (VP8_FRAME_IS_KEY_FRAME(slice)) { -+ read_bits(dev, 1, VP8_PROB_HALF); -+ read_bits(dev, 1, VP8_PROB_HALF); -+ } -+ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) -+ process_segmentation_info(dev); -+ -+ read_bits(dev, 1, VP8_PROB_HALF); -+ read_bits(dev, 6, VP8_PROB_HALF); -+ read_bits(dev, 3, VP8_PROB_HALF); -+ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) -+ process_ref_lf_delta_info(dev); -+ -+ read_bits(dev, 2, VP8_PROB_HALF); -+ read_bits(dev, 7, VP8_PROB_HALF); -+ -+ get_delta_q(dev); -+ get_delta_q(dev); -+ get_delta_q(dev); -+ get_delta_q(dev); -+ get_delta_q(dev); -+ -+ if (!VP8_FRAME_IS_KEY_FRAME(slice)) -+ process_ref_frame_info(dev); -+ -+ read_bits(dev, 1, VP8_PROB_HALF); -+ -+ if (!VP8_FRAME_IS_KEY_FRAME(slice)) -+ read_bits(dev, 1, VP8_PROB_HALF); -+ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, VE_H264_TRIGGER_TYPE_VP8_UPDATE_COEF); -+ while (cedrus_read(dev, VE_H264_STATUS) & VE_H264_STATUS_VP8_UPPROB_BUSY) -+ ; -+ -+ cedrus_write(dev, VE_H264_STATUS, VE_H264_CTRL_INT_MASK); -+ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) -+ read_bits(dev, 8, VP8_PROB_HALF); -+ -+ if (!VP8_FRAME_IS_KEY_FRAME(slice)) { -+ read_bits(dev, 8, VP8_PROB_HALF); -+ read_bits(dev, 8, VP8_PROB_HALF); -+ read_bits(dev, 8, VP8_PROB_HALF); -+ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 8, VP8_PROB_HALF); -+ read_bits(dev, 8, VP8_PROB_HALF); -+ read_bits(dev, 8, VP8_PROB_HALF); -+ read_bits(dev, 8, VP8_PROB_HALF); -+ } -+ -+ if (read_bits(dev, 1, VP8_PROB_HALF)) { -+ read_bits(dev, 8, VP8_PROB_HALF); -+ read_bits(dev, 8, VP8_PROB_HALF); -+ read_bits(dev, 8, VP8_PROB_HALF); -+ } -+ -+ for (i = 0; i < 2; i++) -+ for (j = 0; j < 19; j++) -+ if (read_bits(dev, 1, vp8_mv_update_prob[i][j])) -+ read_bits(dev, 7, VP8_PROB_HALF); -+ } -+} -+ -+static void cedrus_vp8_update_probs(const struct v4l2_ctrl_vp8_frame_header *slice, -+ u8 *prob_table) -+{ -+ int i, j, k; -+ -+ memcpy(&prob_table[0x1008], slice->entropy_header.y_mode_probs, 4); -+ memcpy(&prob_table[0x1010], slice->entropy_header.uv_mode_probs, 3); -+ -+ memcpy(&prob_table[0x1018], slice->segment_header.segment_probs, 3); -+ -+ prob_table[0x101c] = slice->prob_skip_false; -+ prob_table[0x101d] = slice->prob_intra; -+ prob_table[0x101e] = slice->prob_last; -+ prob_table[0x101f] = slice->prob_gf; -+ -+ memcpy(&prob_table[0x1020], slice->entropy_header.mv_probs[0], 19); -+ memcpy(&prob_table[0x1040], slice->entropy_header.mv_probs[1], 19); -+ -+ for (i = 0; i < 4; ++i) -+ for (j = 0; j < 8; ++j) -+ for (k = 0; k < 3; ++k) -+ memcpy(&prob_table[i * 512 + j * 64 + k * 16], -+ slice->entropy_header.coeff_probs[i][j][k], 11); -+} -+ -+static enum cedrus_irq_status -+cedrus_vp8_irq_status(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_STATUS); -+ -+ if (reg & (VE_H264_STATUS_DECODE_ERR_INT | -+ VE_H264_STATUS_VLD_DATA_REQ_INT)) -+ return CEDRUS_IRQ_ERROR; -+ -+ if (reg & VE_H264_CTRL_SLICE_DECODE_INT) -+ return CEDRUS_IRQ_OK; -+ -+ return CEDRUS_IRQ_NONE; -+} -+ -+static void cedrus_vp8_irq_clear(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_STATUS, -+ VE_H264_STATUS_INT_MASK); -+} -+ -+static void cedrus_vp8_irq_disable(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_CTRL); -+ -+ cedrus_write(dev, VE_H264_CTRL, -+ reg & ~VE_H264_CTRL_INT_MASK); -+} -+ -+static void cedrus_vp8_setup(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_vp8_frame_header *slice = run->vp8.slice_params; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *src_buf = &run->src->vb2_buf; -+ struct cedrus_dev *dev = ctx->dev; -+ dma_addr_t luma_addr, chroma_addr; -+ dma_addr_t src_buf_addr; -+ int header_size; -+ int qindex; -+ u32 reg; -+ -+ cedrus_engine_enable(ctx, CEDRUS_CODEC_VP8); -+ -+ cedrus_write(dev, VE_H264_CTRL, VE_H264_CTRL_VP8); -+ -+ cedrus_vp8_update_probs(slice, ctx->codec.vp8.entropy_probs_buf); -+ -+ reg = slice->first_part_size * 8; -+ cedrus_write(dev, VE_VP8_FIRST_DATA_PART_LEN, reg); -+ -+ header_size = VP8_FRAME_IS_KEY_FRAME(slice) ? 10 : 3; -+ -+ reg = slice->first_part_size + header_size; -+ cedrus_write(dev, VE_VP8_PART_SIZE_OFFSET, reg); -+ -+ reg = vb2_plane_size(src_buf, 0) * 8; -+ cedrus_write(dev, VE_H264_VLD_LEN, reg); -+ -+ /* -+ * FIXME: There is a problem if frame header is skipped (adding -+ * first_part_header_bits to offset). It seems that functions -+ * for parsing bitstreams change internal state of VPU in some -+ * way that can't be otherwise set. Maybe this can be bypassed -+ * by somehow fixing probability table buffer? -+ */ -+ reg = header_size * 8; -+ cedrus_write(dev, VE_H264_VLD_OFFSET, reg); -+ -+ src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); -+ cedrus_write(dev, VE_H264_VLD_END, -+ src_buf_addr + vb2_get_plane_payload(src_buf, 0)); -+ cedrus_write(dev, VE_H264_VLD_ADDR, -+ VE_H264_VLD_ADDR_VAL(src_buf_addr) | -+ VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | -+ VE_H264_VLD_ADDR_LAST); -+ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_INIT_SWDEC); -+ -+ cedrus_write(dev, VE_VP8_ENTROPY_PROBS_ADDR, -+ ctx->codec.vp8.entropy_probs_buf_dma); -+ -+ reg = 0; -+ switch (slice->version) { -+ case 1: -+ reg |= VE_VP8_PPS_FILTER_TYPE_SIMPLE; -+ reg |= VE_VP8_PPS_BILINEAR_MC_FILTER; -+ break; -+ case 2: -+ reg |= VE_VP8_PPS_LPF_DISABLE; -+ reg |= VE_VP8_PPS_BILINEAR_MC_FILTER; -+ break; -+ case 3: -+ reg |= VE_VP8_PPS_LPF_DISABLE; -+ reg |= VE_VP8_PPS_FULL_PIXEL; -+ break; -+ } -+ if (slice->segment_header.flags & V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP) -+ reg |= VE_VP8_PPS_UPDATE_MB_SEGMENTATION_MAP; -+ if (!(slice->segment_header.flags & V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE)) -+ reg |= VE_VP8_PPS_MB_SEGMENT_ABS_DELTA; -+ if (slice->segment_header.flags & V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED) -+ reg |= VE_VP8_PPS_SEGMENTATION_ENABLE; -+ if (ctx->codec.vp8.last_filter_type) -+ reg |= VE_VP8_PPS_LAST_LOOP_FILTER_SIMPLE; -+ reg |= VE_VP8_PPS_SHARPNESS_LEVEL(slice->lf_header.sharpness_level); -+ if (slice->lf_header.flags & V4L2_VP8_LF_FILTER_TYPE_SIMPLE) -+ reg |= VE_VP8_PPS_LOOP_FILTER_SIMPLE; -+ reg |= VE_VP8_PPS_LOOP_FILTER_LEVEL(slice->lf_header.level); -+ if (slice->lf_header.flags & V4L2_VP8_LF_HEADER_ADJ_ENABLE) -+ reg |= VE_VP8_PPS_MODE_REF_LF_DELTA_ENABLE; -+ if (slice->lf_header.flags & V4L2_VP8_LF_HEADER_DELTA_UPDATE) -+ reg |= VE_VP8_PPS_MODE_REF_LF_DELTA_UPDATE; -+ reg |= VE_VP8_PPS_TOKEN_PARTITION(ilog2(slice->num_dct_parts)); -+ if (slice->flags & V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF) -+ reg |= VE_VP8_PPS_MB_NO_COEFF_SKIP; -+ reg |= VE_VP8_PPS_RELOAD_ENTROPY_PROBS; -+ if (slice->flags & V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN) -+ reg |= VE_VP8_PPS_GOLDEN_SIGN_BIAS; -+ if (slice->flags & V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT) -+ reg |= VE_VP8_PPS_ALTREF_SIGN_BIAS; -+ if (ctx->codec.vp8.last_frame_p_type) -+ reg |= VE_VP8_PPS_LAST_PIC_TYPE_P_FRAME; -+ reg |= VE_VP8_PPS_LAST_SHARPNESS_LEVEL(ctx->codec.vp8.last_sharpness_level); -+ if (!(slice->flags & V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME)) -+ reg |= VE_VP8_PPS_PIC_TYPE_P_FRAME; -+ cedrus_write(dev, VE_VP8_PPS, reg); -+ -+ cedrus_read_header(dev, slice); -+ -+ /* reset registers changed by HW */ -+ cedrus_write(dev, VE_H264_CUR_MB_NUM, 0); -+ cedrus_write(dev, VE_H264_MB_ADDR, 0); -+ cedrus_write(dev, VE_H264_ERROR_CASE, 0); -+ -+ reg = 0; -+ reg |= VE_VP8_QP_INDEX_DELTA_UVAC(slice->quant_header.uv_ac_delta); -+ reg |= VE_VP8_QP_INDEX_DELTA_UVDC(slice->quant_header.uv_dc_delta); -+ reg |= VE_VP8_QP_INDEX_DELTA_Y2AC(slice->quant_header.y2_ac_delta); -+ reg |= VE_VP8_QP_INDEX_DELTA_Y2DC(slice->quant_header.y2_dc_delta); -+ reg |= VE_VP8_QP_INDEX_DELTA_Y1DC(slice->quant_header.y_dc_delta); -+ reg |= VE_VP8_QP_INDEX_DELTA_BASE_QINDEX(slice->quant_header.y_ac_qi); -+ cedrus_write(dev, VE_VP8_QP_INDEX_DELTA, reg); -+ -+ reg = 0; -+ reg |= VE_VP8_FSIZE_WIDTH(slice->width); -+ reg |= VE_VP8_FSIZE_HEIGHT(slice->height); -+ cedrus_write(dev, VE_VP8_FSIZE, reg); -+ -+ reg = 0; -+ reg |= VE_VP8_PICSIZE_WIDTH(slice->width); -+ reg |= VE_VP8_PICSIZE_HEIGHT(slice->height); -+ cedrus_write(dev, VE_VP8_PICSIZE, reg); -+ -+ reg = 0; -+ reg |= VE_VP8_SEGMENT3(slice->segment_header.quant_update[3]); -+ reg |= VE_VP8_SEGMENT2(slice->segment_header.quant_update[2]); -+ reg |= VE_VP8_SEGMENT1(slice->segment_header.quant_update[1]); -+ reg |= VE_VP8_SEGMENT0(slice->segment_header.quant_update[0]); -+ cedrus_write(dev, VE_VP8_SEGMENT_FEAT_MB_LV0, reg); -+ -+ reg = 0; -+ reg |= VE_VP8_SEGMENT3(slice->segment_header.lf_update[3]); -+ reg |= VE_VP8_SEGMENT2(slice->segment_header.lf_update[2]); -+ reg |= VE_VP8_SEGMENT1(slice->segment_header.lf_update[1]); -+ reg |= VE_VP8_SEGMENT0(slice->segment_header.lf_update[0]); -+ cedrus_write(dev, VE_VP8_SEGMENT_FEAT_MB_LV1, reg); -+ -+ reg = 0; -+ reg |= VE_VP8_LF_DELTA3(slice->lf_header.ref_frm_delta[3]); -+ reg |= VE_VP8_LF_DELTA2(slice->lf_header.ref_frm_delta[2]); -+ reg |= VE_VP8_LF_DELTA1(slice->lf_header.ref_frm_delta[1]); -+ reg |= VE_VP8_LF_DELTA0(slice->lf_header.ref_frm_delta[0]); -+ cedrus_write(dev, VE_VP8_REF_LF_DELTA, reg); -+ -+ reg = 0; -+ reg |= VE_VP8_LF_DELTA3(slice->lf_header.mb_mode_delta[3]); -+ reg |= VE_VP8_LF_DELTA2(slice->lf_header.mb_mode_delta[2]); -+ reg |= VE_VP8_LF_DELTA1(slice->lf_header.mb_mode_delta[1]); -+ reg |= VE_VP8_LF_DELTA0(slice->lf_header.mb_mode_delta[0]); -+ cedrus_write(dev, VE_VP8_MODE_LF_DELTA, reg); -+ -+ luma_addr = cedrus_dst_buf_addr(ctx, run->dst->vb2_buf.index, 0); -+ chroma_addr = cedrus_dst_buf_addr(ctx, run->dst->vb2_buf.index, 1); -+ cedrus_write(dev, VE_VP8_REC_LUMA, luma_addr); -+ cedrus_write(dev, VE_VP8_REC_CHROMA, chroma_addr); -+ -+ qindex = vb2_find_timestamp(cap_q, slice->last_frame_ts, 0); -+ if (qindex >= 0) { -+ luma_addr = cedrus_dst_buf_addr(ctx, qindex, 0); -+ chroma_addr = cedrus_dst_buf_addr(ctx, qindex, 1); -+ cedrus_write(dev, VE_VP8_FWD_LUMA, luma_addr); -+ cedrus_write(dev, VE_VP8_FWD_CHROMA, chroma_addr); -+ } else { -+ cedrus_write(dev, VE_VP8_FWD_LUMA, 0); -+ cedrus_write(dev, VE_VP8_FWD_CHROMA, 0); -+ } -+ -+ qindex = vb2_find_timestamp(cap_q, slice->golden_frame_ts, 0); -+ if (qindex >= 0) { -+ luma_addr = cedrus_dst_buf_addr(ctx, qindex, 0); -+ chroma_addr = cedrus_dst_buf_addr(ctx, qindex, 1); -+ cedrus_write(dev, VE_VP8_BWD_LUMA, luma_addr); -+ cedrus_write(dev, VE_VP8_BWD_CHROMA, chroma_addr); -+ } else { -+ cedrus_write(dev, VE_VP8_BWD_LUMA, 0); -+ cedrus_write(dev, VE_VP8_BWD_CHROMA, 0); -+ } -+ -+ qindex = vb2_find_timestamp(cap_q, slice->alt_frame_ts, 0); -+ if (qindex >= 0) { -+ luma_addr = cedrus_dst_buf_addr(ctx, qindex, 0); -+ chroma_addr = cedrus_dst_buf_addr(ctx, qindex, 1); -+ cedrus_write(dev, VE_VP8_ALT_LUMA, luma_addr); -+ cedrus_write(dev, VE_VP8_ALT_CHROMA, chroma_addr); -+ } else { -+ cedrus_write(dev, VE_VP8_ALT_LUMA, 0); -+ cedrus_write(dev, VE_VP8_ALT_CHROMA, 0); -+ } -+ -+ cedrus_write(dev, VE_H264_CTRL, VE_H264_CTRL_VP8 | -+ VE_H264_CTRL_DECODE_ERR_INT | -+ VE_H264_CTRL_SLICE_DECODE_INT); -+ -+ if (slice->lf_header.level) { -+ ctx->codec.vp8.last_filter_type = -+ !!(slice->lf_header.flags & V4L2_VP8_LF_FILTER_TYPE_SIMPLE); -+ ctx->codec.vp8.last_frame_p_type = -+ !VP8_FRAME_IS_KEY_FRAME(slice); -+ ctx->codec.vp8.last_sharpness_level = -+ slice->lf_header.sharpness_level; -+ } -+} -+ -+static int cedrus_vp8_start(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ ctx->codec.vp8.entropy_probs_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_ENTROPY_PROBS_SIZE, -+ &ctx->codec.vp8.entropy_probs_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.vp8.entropy_probs_buf) -+ return -ENOMEM; -+ -+ memcpy(&ctx->codec.vp8.entropy_probs_buf[2048], -+ prob_table_init, sizeof(prob_table_init)); -+ -+ return 0; -+} -+ -+static void cedrus_vp8_stop(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_engine_disable(dev); -+ -+ dma_free_coherent(dev->dev, CEDRUS_ENTROPY_PROBS_SIZE, -+ ctx->codec.vp8.entropy_probs_buf, -+ ctx->codec.vp8.entropy_probs_buf_dma); -+} -+ -+static void cedrus_vp8_trigger(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_VP8_SLICE_DECODE); -+} -+ -+struct cedrus_dec_ops cedrus_dec_ops_vp8 = { -+ .irq_clear = cedrus_vp8_irq_clear, -+ .irq_disable = cedrus_vp8_irq_disable, -+ .irq_status = cedrus_vp8_irq_status, -+ .setup = cedrus_vp8_setup, -+ .start = cedrus_vp8_start, -+ .stop = cedrus_vp8_stop, -+ .trigger = cedrus_vp8_trigger, -+}; diff --git a/projects/Allwinner/patches/linux/0044-HACK-h3-h5-Add-HDMI-sound-card.patch b/projects/Allwinner/patches/linux/0034-HACK-h3-h5-Add-HDMI-sound-card.patch similarity index 96% rename from projects/Allwinner/patches/linux/0044-HACK-h3-h5-Add-HDMI-sound-card.patch rename to projects/Allwinner/patches/linux/0034-HACK-h3-h5-Add-HDMI-sound-card.patch index 8f44848145..98377f709e 100644 --- a/projects/Allwinner/patches/linux/0044-HACK-h3-h5-Add-HDMI-sound-card.patch +++ b/projects/Allwinner/patches/linux/0034-HACK-h3-h5-Add-HDMI-sound-card.patch @@ -35,7 +35,7 @@ Signed-off-by: Jernej Skrabec clocks { #address-cells = <1>; #size-cells = <1>; -@@ -672,7 +690,6 @@ +@@ -681,7 +699,6 @@ dmas = <&dma 27>; resets = <&ccu RST_BUS_I2S2>; dma-names = "tx"; @@ -43,7 +43,7 @@ Signed-off-by: Jernej Skrabec }; codec: codec@1c22c00 { -@@ -806,6 +823,7 @@ +@@ -815,6 +832,7 @@ }; hdmi: hdmi@1ee0000 { diff --git a/projects/Allwinner/patches/linux/0045-h3-h5-power-key-wake-up-source.patch b/projects/Allwinner/patches/linux/0035-h3-h5-power-key-wake-up-source.patch similarity index 55% rename from projects/Allwinner/patches/linux/0045-h3-h5-power-key-wake-up-source.patch rename to projects/Allwinner/patches/linux/0035-h3-h5-power-key-wake-up-source.patch index 60a2ef447d..b0a8136ca4 100644 --- a/projects/Allwinner/patches/linux/0045-h3-h5-power-key-wake-up-source.patch +++ b/projects/Allwinner/patches/linux/0035-h3-h5-power-key-wake-up-source.patch @@ -4,7 +4,6 @@ Date: Sat, 30 Jan 2021 18:12:26 +0100 Subject: [PATCH] h3/h5: power key wake up source --- - arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 11 +++++++++++ arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 3 ++- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 ++- @@ -12,33 +11,9 @@ Subject: [PATCH] h3/h5: power key wake up source arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 1 + 6 files changed, 19 insertions(+), 3 deletions(-) -diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -index 45a24441ff18..24aff65f82ca 100644 ---- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -@@ -111,6 +111,17 @@ spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -+ -+ r_gpio_keys { -+ compatible = "gpio-keys"; -+ -+ power { -+ label = "power"; -+ linux,code = ; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ wakeup-source; -+ }; -+ }; - }; - - &de { -diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi -index 4df29a65316d..684a0a1f8886 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi -@@ -81,6 +81,7 @@ k1 { +@@ -81,6 +81,7 @@ label = "k1"; linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -46,11 +21,9 @@ index 4df29a65316d..684a0a1f8886 100644 }; }; }; -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts -index 597c425d08ec..9daffd90c12f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts -@@ -99,8 +99,9 @@ sw2 { +@@ -99,8 +99,9 @@ sw4 { label = "sw4"; @@ -61,11 +34,9 @@ index 597c425d08ec..9daffd90c12f 100644 }; }; -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -index 5aff8ecc66cb..90f75fa85e68 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -@@ -91,8 +91,9 @@ r_gpio_keys { +@@ -91,8 +91,9 @@ sw4 { label = "sw4"; @@ -76,11 +47,9 @@ index 5aff8ecc66cb..90f75fa85e68 100644 }; }; }; -diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi -index 8e5cb3b3fd68..b1066dedc1a2 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi -@@ -82,8 +82,9 @@ gpio_keys { +@@ -82,8 +82,9 @@ sw4 { label = "power"; @@ -91,11 +60,9 @@ index 8e5cb3b3fd68..b1066dedc1a2 100644 }; }; -diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi -index c44fd726945a..9e14fe5fdcde 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi -@@ -49,6 +49,7 @@ power { +@@ -49,6 +49,7 @@ label = "power"; linux,code = ; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ diff --git a/projects/Allwinner/patches/linux/0055-wip-h3-h5-cvbs.patch b/projects/Allwinner/patches/linux/0036-wip-h3-h5-cvbs.patch similarity index 84% rename from projects/Allwinner/patches/linux/0055-wip-h3-h5-cvbs.patch rename to projects/Allwinner/patches/linux/0036-wip-h3-h5-cvbs.patch index 1f036803eb..5f3f69b491 100644 --- a/projects/Allwinner/patches/linux/0055-wip-h3-h5-cvbs.patch +++ b/projects/Allwinner/patches/linux/0036-wip-h3-h5-cvbs.patch @@ -11,27 +11,25 @@ Subject: [PATCH] wip h3/h5 cvbs drivers/gpu/drm/sun4i/sun8i_mixer.h | 5 +- 6 files changed, 169 insertions(+), 9 deletions(-) -diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -index 22d533d18992..f18959b2e8df 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -101,7 +101,7 @@ osc32k: osc32k_clk { - +@@ -119,7 +119,7 @@ + de: display-engine { compatible = "allwinner,sun8i-h3-display-engine"; - allwinner,pipelines = <&mixer0>; + allwinner,pipelines = <&mixer0>, <&mixer1>; status = "disabled"; }; - -@@ -138,11 +138,50 @@ ports { + +@@ -163,11 +163,50 @@ #size-cells = <0>; - + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - + - mixer0_out_tcon0: endpoint { + mixer0_out_tcon0: endpoint@0 { + reg = <0>; @@ -76,14 +74,14 @@ index 22d533d18992..f18959b2e8df 100644 }; }; }; -@@ -171,11 +210,19 @@ ports { +@@ -196,11 +235,19 @@ #size-cells = <0>; - + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - + - tcon0_in_mixer0: endpoint { + tcon0_in_mixer0: endpoint@0 { + reg = <0>; @@ -95,12 +93,12 @@ index 22d533d18992..f18959b2e8df 100644 + remote-endpoint = <&mixer1_out_tcon0>; + }; }; - + tcon0_out: port@1 { -@@ -191,6 +238,49 @@ tcon0_out_hdmi: endpoint@1 { +@@ -216,6 +263,49 @@ }; }; - + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun8i-h3-tcon-tv", + "allwinner,sun8i-a83t-tcon-tv"; @@ -147,10 +145,10 @@ index 22d533d18992..f18959b2e8df 100644 mmc0: mmc@1c0f000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c0f000 0x1000>; -@@ -792,6 +882,21 @@ csi: camera@1cb0000 { +@@ -831,6 +921,21 @@ status = "disabled"; }; - + + tve: tv-encoder@1e00000 { + compatible = "allwinner,sun8i-h3-tv-encoder", + "allwinner,sun4i-a10-tv-encoder"; @@ -167,15 +165,13 @@ index 22d533d18992..f18959b2e8df 100644 + }; + hdmi: hdmi@1ee0000 { + #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; -diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c -index 7e629a4493af..334b7edea3b7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c -@@ -456,8 +456,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, +@@ -456,8 +456,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(tcon_cl CLK_SET_RATE_PARENT); - + static const char * const tve_parents[] = { "pll-de", "pll-periph1" }; -static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents, - 0x120, 0, 4, 24, 3, BIT(31), 0); @@ -191,30 +187,26 @@ index 7e629a4493af..334b7edea3b7 100644 + &ccu_div_ops, 0), + }, +}; - + static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, -diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile -index 0d04f2447b01..7b151994e904 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile -@@ -16,7 +16,7 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o - +@@ -16,7 +16,7 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk. + sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \ sun8i_vi_layer.o sun8i_ui_scaler.o \ - sun8i_vi_scaler.o sun8i_csc.o + sun8i_vi_scaler.o sun8i_csc.o sun4i_tv.o - + sun4i-tcon-y += sun4i_crtc.o sun4i-tcon-y += sun4i_dotclock.o -diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 5b42cf25cc86..35ca78a30087 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -32,6 +32,12 @@ struct de2_fmt_info { u32 de2_fmt; }; - + +static const u32 sun8i_rgb2yuv_coef[12] = { + 0x00000107, 0x00000204, 0x00000064, 0x00004200, + 0x00001f68, 0x00001ed6, 0x000001c2, 0x00020200, @@ -224,10 +216,10 @@ index 5b42cf25cc86..35ca78a30087 100644 static const struct de2_fmt_info de2_formats[] = { { .drm_fmt = DRM_FORMAT_ARGB8888, -@@ -298,9 +304,28 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm, +@@ -341,9 +347,28 @@ static struct drm_plane **sun8i_layers_i return planes; } - + +static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine) +{ + DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n"); @@ -253,12 +245,12 @@ index 5b42cf25cc86..35ca78a30087 100644 + .apply_color_correction = sun8i_mixer_apply_color_correction, + .disable_color_correction = sun8i_mixer_disable_color_correction, }; - - static const struct regmap_config sun8i_mixer_regmap_config = { -@@ -560,6 +585,15 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { + + static bool sun8i_mixer_volatile_reg(struct device *dev, unsigned int reg) +@@ -608,6 +633,15 @@ static const struct sun8i_mixer_cfg sun8 .vi_num = 1, }; - + +static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = { + .ccsc = 1, + .mod_rate = 432000000, @@ -271,25 +263,23 @@ index 5b42cf25cc86..35ca78a30087 100644 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { .ccsc = 0, .mod_rate = 297000000, -@@ -628,6 +662,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { - .compatible = "allwinner,sun8i-h3-de2-mixer-0", +@@ -677,6 +711,10 @@ static const struct of_device_id sun8i_m .data = &sun8i_h3_mixer0_cfg, }, -+ { + { + .compatible = "allwinner,sun8i-h3-de2-mixer-1", + .data = &sun8i_h3_mixer1_cfg, + }, - { ++ { .compatible = "allwinner,sun8i-r40-de2-mixer-0", .data = &sun8i_r40_mixer0_cfg, -diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h -index 7576b523fdbb..6593085cecf3 100644 + }, --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -120,6 +120,10 @@ /* format 20 is packed YVU444 10-bit */ /* format 21 is packed YUV444 10-bit */ - + +/* The DCSC sub-engine is used to do color space conversation */ +#define SUN8I_MIXER_DCSC_EN 0xb0000 +#define SUN8I_MIXER_DCSC_COEF_REG(x) (0xb0010 + 0x4 * (x)) @@ -302,6 +292,6 @@ index 7576b523fdbb..6593085cecf3 100644 #define SUN8I_MIXER_ASE_EN 0xa8000 #define SUN8I_MIXER_FCC_EN 0xaa000 -#define SUN8I_MIXER_DCSC_EN 0xb0000 - + #define SUN50I_MIXER_FCE_EN 0x70000 #define SUN50I_MIXER_PEAK_EN 0x70800 diff --git a/projects/Allwinner/patches/linux/0059-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch b/projects/Allwinner/patches/linux/0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch similarity index 95% rename from projects/Allwinner/patches/linux/0059-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch rename to projects/Allwinner/patches/linux/0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch index 63d1a7d76e..bbd2c4622b 100644 --- a/projects/Allwinner/patches/linux/0059-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch +++ b/projects/Allwinner/patches/linux/0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch @@ -10,8 +10,6 @@ Signed-off-by: Jonas Karlman include/media/hevc-ctrls.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 6e881b7896bc..46936bae7c30 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code { diff --git a/projects/Allwinner/patches/linux/0060-HACK-media-uapi-hevc-tiles-and-num_slices.patch b/projects/Allwinner/patches/linux/0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch similarity index 91% rename from projects/Allwinner/patches/linux/0060-HACK-media-uapi-hevc-tiles-and-num_slices.patch rename to projects/Allwinner/patches/linux/0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch index e24549b10c..7d1ceebd6a 100644 --- a/projects/Allwinner/patches/linux/0060-HACK-media-uapi-hevc-tiles-and-num_slices.patch +++ b/projects/Allwinner/patches/linux/0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch @@ -7,8 +7,6 @@ Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices include/media/hevc-ctrls.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 46936bae7c30..4d51c148d0ba 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -80,7 +80,8 @@ struct v4l2_ctrl_hevc_sps { diff --git a/projects/Allwinner/patches/linux/0046-drm-lima-add-governor-data-with-pre-defined-thresholds.patch b/projects/Allwinner/patches/linux/0046-drm-lima-add-governor-data-with-pre-defined-thresholds.patch deleted file mode 100644 index c74efcec2c..0000000000 --- a/projects/Allwinner/patches/linux/0046-drm-lima-add-governor-data-with-pre-defined-thresholds.patch +++ /dev/null @@ -1,57 +0,0 @@ -From: Christian Hewitt -Subject: [PATCH v2] drm/lima: add governor data with pre-defined thresholds -Date: Wed, 27 Jan 2021 19:40:47 +0000 - -This patch adapts the panfrost pre-defined thresholds change [0] to the -lima driver to improve real-world performance. The upthreshold value has -been set to ramp GPU frequency to max freq faster (compared to panfrost) -to compensate for the lower overall performance of utgard devices. - -[0] https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1-lukasz.luba@arm.com/ - -Signed-off-by: Christian Hewitt -Reviewed-by: Lukasz Luba -Reviewed-by: Qiang Yu ---- - drivers/gpu/drm/lima/lima_devfreq.c | 10 +++++++++- - drivers/gpu/drm/lima/lima_devfreq.h | 2 ++ - 2 files changed, 11 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -177,8 +177,16 @@ int lima_devfreq_init(struct lima_device - lima_devfreq_profile.initial_freq = cur_freq; - dev_pm_opp_put(opp); - -+ /* -+ * Setup default thresholds for the simple_ondemand governor. -+ * The values are chosen based on experiments. -+ */ -+ ldevfreq->gov_data.upthreshold = 30; -+ ldevfreq->gov_data.downdifferential = 5; -+ - devfreq = devm_devfreq_add_device(dev, &lima_devfreq_profile, -- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); -+ DEVFREQ_GOV_SIMPLE_ONDEMAND, -+ &ldevfreq->gov_data); - if (IS_ERR(devfreq)) { - dev_err(dev, "Couldn't initialize GPU devfreq\n"); - ret = PTR_ERR(devfreq); ---- a/drivers/gpu/drm/lima/lima_devfreq.h -+++ b/drivers/gpu/drm/lima/lima_devfreq.h -@@ -4,6 +4,7 @@ - #ifndef __LIMA_DEVFREQ_H__ - #define __LIMA_DEVFREQ_H__ - -+#include - #include - #include - -@@ -18,6 +19,7 @@ struct lima_devfreq { - struct opp_table *clkname_opp_table; - struct opp_table *regulators_opp_table; - struct thermal_cooling_device *cooling; -+ struct devfreq_simple_ondemand_data gov_data; - bool opp_of_table_added; - - ktime_t busy_time; diff --git a/projects/Allwinner/patches/linux/0047-drm-lima-Use-delayed-timer-as-default-in-devfreq-profile.patch b/projects/Allwinner/patches/linux/0047-drm-lima-Use-delayed-timer-as-default-in-devfreq-profile.patch deleted file mode 100644 index b6b0ff045d..0000000000 --- a/projects/Allwinner/patches/linux/0047-drm-lima-Use-delayed-timer-as-default-in-devfreq-profile.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Lukasz Luba -Subject: [PATCH] drm/lima: Use delayed timer as default in devfreq profile -Date: Wed, 27 Jan 2021 10:51:21 +0000 - -Devfreq framework supports 2 modes for monitoring devices. -Use delayed timer as default instead of deferrable timer -in order to monitor the GPU status regardless of CPU idle. - -Signed-off-by: Lukasz Luba -Reviewed-by: Qiang Yu ---- - drivers/gpu/drm/lima/lima_devfreq.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -86,6 +86,7 @@ static int lima_devfreq_get_dev_status(s - } - - static struct devfreq_dev_profile lima_devfreq_profile = { -+ .timer = DEVFREQ_TIMER_DELAYED, - .polling_ms = 50, /* ~3 frames */ - .target = lima_devfreq_target, - .get_dev_status = lima_devfreq_get_dev_status, diff --git a/projects/Allwinner/patches/linux/0048-drm-panfrost-Add-governor-data-with-pre-defined-thre.patch b/projects/Allwinner/patches/linux/0048-drm-panfrost-Add-governor-data-with-pre-defined-thre.patch deleted file mode 100644 index 38775afa97..0000000000 --- a/projects/Allwinner/patches/linux/0048-drm-panfrost-Add-governor-data-with-pre-defined-thre.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lukasz Luba -Date: Thu, 21 Jan 2021 17:04:45 +0000 -Subject: [PATCH] drm/panfrost: Add governor data with pre-defined thresholds - -The simple_ondemand devfreq governor uses two thresholds to decide about -the frequency change: upthreshold, downdifferential. These two tunable -change the behavior of the governor decision, e.g. how fast to increase -the frequency or how rapidly limit the frequency. This patch adds needed -governor data with thresholds values gathered experimentally in different -workloads. - -Signed-off-by: Lukasz Luba -Reviewed-by: Steven Price -Signed-off-by: Steven Price -Link: https://patchwork.freedesktop.org/patch/msgid/20210121170445.19761-1-lukasz.luba@arm.com ---- - drivers/gpu/drm/panfrost/panfrost_devfreq.c | 10 +++++++++- - drivers/gpu/drm/panfrost/panfrost_devfreq.h | 2 ++ - 2 files changed, 11 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -@@ -134,8 +134,16 @@ int panfrost_devfreq_init(struct panfros - panfrost_devfreq_profile.initial_freq = cur_freq; - dev_pm_opp_put(opp); - -+ /* -+ * Setup default thresholds for the simple_ondemand governor. -+ * The values are chosen based on experiments. -+ */ -+ pfdevfreq->gov_data.upthreshold = 45; -+ pfdevfreq->gov_data.downdifferential = 5; -+ - devfreq = devm_devfreq_add_device(dev, &panfrost_devfreq_profile, -- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); -+ DEVFREQ_GOV_SIMPLE_ONDEMAND, -+ &pfdevfreq->gov_data); - if (IS_ERR(devfreq)) { - DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n"); - ret = PTR_ERR(devfreq); ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h -@@ -4,6 +4,7 @@ - #ifndef __PANFROST_DEVFREQ_H__ - #define __PANFROST_DEVFREQ_H__ - -+#include - #include - #include - -@@ -17,6 +18,7 @@ struct panfrost_devfreq { - struct devfreq *devfreq; - struct opp_table *regulators_opp_table; - struct thermal_cooling_device *cooling; -+ struct devfreq_simple_ondemand_data gov_data; - bool opp_of_table_added; - - ktime_t busy_time; diff --git a/projects/Allwinner/patches/linux/0049-drm-panfrost-Use-delayed-timer-as-default-in-devfreq.patch b/projects/Allwinner/patches/linux/0049-drm-panfrost-Use-delayed-timer-as-default-in-devfreq.patch deleted file mode 100644 index ad17f86f78..0000000000 --- a/projects/Allwinner/patches/linux/0049-drm-panfrost-Use-delayed-timer-as-default-in-devfreq.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lukasz Luba -Date: Tue, 5 Jan 2021 16:41:11 +0000 -Subject: [PATCH] drm/panfrost: Use delayed timer as default in devfreq profile - -Devfreq framework supports 2 modes for monitoring devices. -Use delayed timer as default instead of deferrable timer -in order to monitor the GPU status regardless of CPU idle. - -Signed-off-by: Lukasz Luba -Reviewed-by: Steven Price -Signed-off-by: Steven Price -Link: https://patchwork.freedesktop.org/patch/msgid/20210105164111.30122-1-lukasz.luba@arm.com ---- - drivers/gpu/drm/panfrost/panfrost_devfreq.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -@@ -81,6 +81,7 @@ static int panfrost_devfreq_get_dev_stat - } - - static struct devfreq_dev_profile panfrost_devfreq_profile = { -+ .timer = DEVFREQ_TIMER_DELAYED, - .polling_ms = 50, /* ~3 frames */ - .target = panfrost_devfreq_target, - .get_dev_status = panfrost_devfreq_get_dev_status, diff --git a/projects/Allwinner/patches/linux/crust/0006-net-stmmac-dwmac-sun8i-Return-void-from-PHY-unpower.patch b/projects/Allwinner/patches/linux/crust/0006-net-stmmac-dwmac-sun8i-Return-void-from-PHY-unpower.patch deleted file mode 100644 index 0a25b6722d..0000000000 --- a/projects/Allwinner/patches/linux/crust/0006-net-stmmac-dwmac-sun8i-Return-void-from-PHY-unpower.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 3 Jan 2021 05:25:38 -0600 -Subject: [PATCH] net: stmmac: dwmac-sun8i: Return void from PHY unpower - -This is a deinitialization function that always returned zero, and that -return value was always ignored. Have it return void instead. - -Signed-off-by: Samuel Holland -Reviewed-by: Chen-Yu Tsai ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -820,15 +820,14 @@ static int sun8i_dwmac_power_internal_ph - return 0; - } - --static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) -+static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) - { - if (!gmac->internal_phy_powered) -- return 0; -+ return; - - clk_disable_unprepare(gmac->ephy_clk); - reset_control_assert(gmac->rst_ephy); - gmac->internal_phy_powered = false; -- return 0; - } - - /* MDIO multiplexing switch function diff --git a/projects/Allwinner/patches/linux/crust/0007-net-stmmac-dwmac-sun8i-Remove-unnecessary-PHY-power-.patch b/projects/Allwinner/patches/linux/crust/0007-net-stmmac-dwmac-sun8i-Remove-unnecessary-PHY-power-.patch deleted file mode 100644 index adce43d1e3..0000000000 --- a/projects/Allwinner/patches/linux/crust/0007-net-stmmac-dwmac-sun8i-Remove-unnecessary-PHY-power-.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 3 Jan 2021 05:25:39 -0600 -Subject: [PATCH] net: stmmac: dwmac-sun8i: Remove unnecessary PHY power check - -sun8i_dwmac_unpower_internal_phy already checks if the PHY is powered, -so there is no need to do it again here. - -Signed-off-by: Samuel Holland -Reviewed-by: Chen-Yu Tsai ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -1018,10 +1018,8 @@ static void sun8i_dwmac_exit(struct plat - { - struct sunxi_priv_data *gmac = priv; - -- if (gmac->variant->soc_has_internal_phy) { -- if (gmac->internal_phy_powered) -- sun8i_dwmac_unpower_internal_phy(gmac); -- } -+ if (gmac->variant->soc_has_internal_phy) -+ sun8i_dwmac_unpower_internal_phy(gmac); - - clk_disable_unprepare(gmac->tx_clk); - diff --git a/projects/Allwinner/patches/linux/crust/0008-net-stmmac-dwmac-sun8i-Use-reset_control_reset.patch b/projects/Allwinner/patches/linux/crust/0008-net-stmmac-dwmac-sun8i-Use-reset_control_reset.patch deleted file mode 100644 index d64e46cf67..0000000000 --- a/projects/Allwinner/patches/linux/crust/0008-net-stmmac-dwmac-sun8i-Use-reset_control_reset.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 3 Jan 2021 05:25:40 -0600 -Subject: [PATCH] net: stmmac: dwmac-sun8i: Use reset_control_reset - -Use the appropriate function instead of reimplementing it, -and update the error message to match the code. - -Signed-off-by: Samuel Holland -Reviewed-by: Chen-Yu Tsai ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -806,11 +806,9 @@ static int sun8i_dwmac_power_internal_ph - /* Make sure the EPHY is properly reseted, as U-Boot may leave - * it at deasserted state, and thus it may fail to reset EMAC. - */ -- reset_control_assert(gmac->rst_ephy); -- -- ret = reset_control_deassert(gmac->rst_ephy); -+ ret = reset_control_reset(gmac->rst_ephy); - if (ret) { -- dev_err(priv->device, "Cannot deassert internal phy\n"); -+ dev_err(priv->device, "Cannot reset internal PHY\n"); - clk_disable_unprepare(gmac->ephy_clk); - return ret; - } diff --git a/projects/Allwinner/patches/linux/crust/0009-net-stmmac-dwmac-sun8i-Minor-probe-function-cleanup.patch b/projects/Allwinner/patches/linux/crust/0009-net-stmmac-dwmac-sun8i-Minor-probe-function-cleanup.patch deleted file mode 100644 index 19f1d403a3..0000000000 --- a/projects/Allwinner/patches/linux/crust/0009-net-stmmac-dwmac-sun8i-Minor-probe-function-cleanup.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 3 Jan 2021 05:25:41 -0600 -Subject: [PATCH] net: stmmac: dwmac-sun8i: Minor probe function cleanup - -Adjust the spacing and use an explicit "return 0" in the success path -to make the function easier to parse. - -Signed-off-by: Samuel Holland -Reviewed-by: Chen-Yu Tsai ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -1227,6 +1227,7 @@ static int sun8i_dwmac_probe(struct plat - - ndev = dev_get_drvdata(&pdev->dev); - priv = netdev_priv(ndev); -+ - /* The mux must be registered after parent MDIO - * so after stmmac_dvr_probe() - */ -@@ -1245,7 +1246,8 @@ static int sun8i_dwmac_probe(struct plat - goto dwmac_remove; - } - -- return ret; -+ return 0; -+ - dwmac_mux: - reset_control_put(gmac->rst_ephy); - clk_put(gmac->ephy_clk); diff --git a/projects/Allwinner/patches/linux/crust/0010-net-stmmac-dwmac-sun8i-Add-a-shutdown-callback.patch b/projects/Allwinner/patches/linux/crust/0010-net-stmmac-dwmac-sun8i-Add-a-shutdown-callback.patch deleted file mode 100644 index b02c6cd7b0..0000000000 --- a/projects/Allwinner/patches/linux/crust/0010-net-stmmac-dwmac-sun8i-Add-a-shutdown-callback.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 3 Jan 2021 05:25:42 -0600 -Subject: [PATCH] net: stmmac: dwmac-sun8i: Add a shutdown callback - -The Ethernet MAC and PHY are usually major consumers of power on boards -which may not be able to fully power off (that have no PMIC). Powering -down the MAC and internal PHY saves power while these boards are "off". - -Signed-off-by: Samuel Holland -Reviewed-by: Chen-Yu Tsai ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -1282,6 +1282,15 @@ static int sun8i_dwmac_remove(struct pla - return 0; - } - -+static void sun8i_dwmac_shutdown(struct platform_device *pdev) -+{ -+ struct net_device *ndev = platform_get_drvdata(pdev); -+ struct stmmac_priv *priv = netdev_priv(ndev); -+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -+ -+ sun8i_dwmac_exit(pdev, gmac); -+} -+ - static const struct of_device_id sun8i_dwmac_match[] = { - { .compatible = "allwinner,sun8i-h3-emac", - .data = &emac_variant_h3 }, -@@ -1302,6 +1311,7 @@ MODULE_DEVICE_TABLE(of, sun8i_dwmac_matc - static struct platform_driver sun8i_dwmac_driver = { - .probe = sun8i_dwmac_probe, - .remove = sun8i_dwmac_remove, -+ .shutdown = sun8i_dwmac_shutdown, - .driver = { - .name = "dwmac-sun8i", - .pm = &stmmac_pltfr_pm_ops, diff --git a/projects/Allwinner/patches/linux/crust/0011-i2c-mv64xxx-Add-runtime-PM-support.patch b/projects/Allwinner/patches/linux/crust/0011-i2c-mv64xxx-Add-runtime-PM-support.patch deleted file mode 100644 index 347c5d2d1b..0000000000 --- a/projects/Allwinner/patches/linux/crust/0011-i2c-mv64xxx-Add-runtime-PM-support.patch +++ /dev/null @@ -1,237 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 12 Feb 2020 22:58:30 -0600 -Subject: [PATCH] i2c: mv64xxx: Add runtime PM support - -To save power, gate the clock when the bus is inactive, during system -sleep, and during shutdown. On some platforms, specifically Allwinner -A13/A20, gating the clock implicitly resets the module as well. Since -the module already needs to be reset after some suspend/resume cycles, -it is simple enough to reset it during every runtime suspend/resume. - -Because the bus may be used by wakeup source IRQ threads, it needs to -be functional as soon as IRQs are enabled. Thus, its system PM hooks -need to run in the noirq phase. - -Signed-off-by: Samuel Holland ---- - drivers/i2c/busses/i2c-mv64xxx.c | 118 ++++++++++++++++++++----------- - 1 file changed, 77 insertions(+), 41 deletions(-) - ---- a/drivers/i2c/busses/i2c-mv64xxx.c -+++ b/drivers/i2c/busses/i2c-mv64xxx.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -713,6 +714,10 @@ mv64xxx_i2c_xfer(struct i2c_adapter *ada - struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); - int rc, ret = num; - -+ rc = pm_runtime_resume_and_get(&adap->dev); -+ if (rc) -+ return rc; -+ - BUG_ON(drv_data->msgs != NULL); - drv_data->msgs = msgs; - drv_data->num_msgs = num; -@@ -728,6 +733,9 @@ mv64xxx_i2c_xfer(struct i2c_adapter *ada - drv_data->num_msgs = 0; - drv_data->msgs = NULL; - -+ pm_runtime_mark_last_busy(&adap->dev); -+ pm_runtime_put_autosuspend(&adap->dev); -+ - return ret; - } - -@@ -824,7 +832,6 @@ mv64xxx_of_config(struct mv64xxx_i2c_dat - rc = PTR_ERR(drv_data->rstc); - goto out; - } -- reset_control_deassert(drv_data->rstc); - - /* Its not yet defined how timeouts will be specified in device tree. - * So hard code the value to 1 second. -@@ -871,6 +878,32 @@ mv64xxx_of_config(struct mv64xxx_i2c_dat - #endif /* CONFIG_OF */ - - static int -+mv64xxx_i2c_runtime_suspend(struct device *dev) -+{ -+ struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev); -+ -+ reset_control_assert(drv_data->rstc); -+ clk_disable_unprepare(drv_data->reg_clk); -+ clk_disable_unprepare(drv_data->clk); -+ -+ return 0; -+} -+ -+static int -+mv64xxx_i2c_runtime_resume(struct device *dev) -+{ -+ struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev); -+ -+ clk_prepare_enable(drv_data->clk); -+ clk_prepare_enable(drv_data->reg_clk); -+ reset_control_reset(drv_data->rstc); -+ -+ mv64xxx_i2c_hw_init(drv_data); -+ -+ return 0; -+} -+ -+static int - mv64xxx_i2c_probe(struct platform_device *pd) - { - struct mv64xxx_i2c_data *drv_data; -@@ -897,18 +930,22 @@ mv64xxx_i2c_probe(struct platform_device - - /* Not all platforms have clocks */ - drv_data->clk = devm_clk_get(&pd->dev, NULL); -- if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER) -- return -EPROBE_DEFER; -- if (!IS_ERR(drv_data->clk)) -- clk_prepare_enable(drv_data->clk); -+ if (IS_ERR(drv_data->clk)) { -+ if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ drv_data->clk = NULL; -+ } - - drv_data->reg_clk = devm_clk_get(&pd->dev, "reg"); -- if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER) -- return -EPROBE_DEFER; -- if (!IS_ERR(drv_data->reg_clk)) -- clk_prepare_enable(drv_data->reg_clk); -+ if (IS_ERR(drv_data->reg_clk)) { -+ if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ drv_data->reg_clk = NULL; -+ } - - drv_data->irq = platform_get_irq(pd, 0); -+ if (drv_data->irq < 0) -+ return drv_data->irq; - - if (pdata) { - drv_data->freq_m = pdata->freq_m; -@@ -919,11 +956,7 @@ mv64xxx_i2c_probe(struct platform_device - } else if (pd->dev.of_node) { - rc = mv64xxx_of_config(drv_data, &pd->dev); - if (rc) -- goto exit_clk; -- } -- if (drv_data->irq < 0) { -- rc = drv_data->irq; -- goto exit_reset; -+ return rc; - } - - drv_data->adapter.dev.parent = &pd->dev; -@@ -935,7 +968,14 @@ mv64xxx_i2c_probe(struct platform_device - platform_set_drvdata(pd, drv_data); - i2c_set_adapdata(&drv_data->adapter, drv_data); - -- mv64xxx_i2c_hw_init(drv_data); -+ pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC); -+ pm_runtime_use_autosuspend(&pd->dev); -+ pm_runtime_enable(&pd->dev); -+ if (!pm_runtime_enabled(&pd->dev)) { -+ rc = mv64xxx_i2c_runtime_resume(&pd->dev); -+ if (rc) -+ goto exit_disable_pm; -+ } - - rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, - MV64XXX_I2C_CTLR_NAME, drv_data); -@@ -943,7 +983,7 @@ mv64xxx_i2c_probe(struct platform_device - dev_err(&drv_data->adapter.dev, - "mv64xxx: Can't register intr handler irq%d: %d\n", - drv_data->irq, rc); -- goto exit_reset; -+ goto exit_disable_pm; - } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { - dev_err(&drv_data->adapter.dev, - "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); -@@ -954,54 +994,50 @@ mv64xxx_i2c_probe(struct platform_device - - exit_free_irq: - free_irq(drv_data->irq, drv_data); --exit_reset: -- reset_control_assert(drv_data->rstc); --exit_clk: -- clk_disable_unprepare(drv_data->reg_clk); -- clk_disable_unprepare(drv_data->clk); -+exit_disable_pm: -+ pm_runtime_disable(&pd->dev); -+ if (!pm_runtime_status_suspended(&pd->dev)) -+ mv64xxx_i2c_runtime_suspend(&pd->dev); - - return rc; - } - - static int --mv64xxx_i2c_remove(struct platform_device *dev) -+mv64xxx_i2c_remove(struct platform_device *pd) - { -- struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); -+ struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd); - - i2c_del_adapter(&drv_data->adapter); - free_irq(drv_data->irq, drv_data); -- reset_control_assert(drv_data->rstc); -- clk_disable_unprepare(drv_data->reg_clk); -- clk_disable_unprepare(drv_data->clk); -+ pm_runtime_disable(&pd->dev); -+ if (!pm_runtime_status_suspended(&pd->dev)) -+ mv64xxx_i2c_runtime_suspend(&pd->dev); - - return 0; - } - --#ifdef CONFIG_PM --static int mv64xxx_i2c_resume(struct device *dev) -+static void -+mv64xxx_i2c_shutdown(struct platform_device *pd) - { -- struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev); -- -- mv64xxx_i2c_hw_init(drv_data); -- -- return 0; -+ pm_runtime_disable(&pd->dev); -+ if (!pm_runtime_status_suspended(&pd->dev)) -+ mv64xxx_i2c_runtime_suspend(&pd->dev); - } - --static const struct dev_pm_ops mv64xxx_i2c_pm = { -- .resume = mv64xxx_i2c_resume, -+static const struct dev_pm_ops mv64xxx_i2c_pm_ops = { -+ SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend, -+ mv64xxx_i2c_runtime_resume, NULL) -+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) - }; - --#define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm) --#else --#define mv64xxx_i2c_pm_ops NULL --#endif -- - static struct platform_driver mv64xxx_i2c_driver = { - .probe = mv64xxx_i2c_probe, - .remove = mv64xxx_i2c_remove, -+ .shutdown = mv64xxx_i2c_shutdown, - .driver = { - .name = MV64XXX_I2C_CTLR_NAME, -- .pm = mv64xxx_i2c_pm_ops, -+ .pm = &mv64xxx_i2c_pm_ops, - .of_match_table = mv64xxx_i2c_of_match_table, - }, - }; diff --git a/projects/Allwinner/patches/linux/crust/0012-media-sunxi-cir-Skip-register-writes-during-remove.patch b/projects/Allwinner/patches/linux/crust/0012-media-sunxi-cir-Skip-register-writes-during-remove.patch deleted file mode 100644 index cd57db6a1a..0000000000 --- a/projects/Allwinner/patches/linux/crust/0012-media-sunxi-cir-Skip-register-writes-during-remove.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 10 Jan 2021 00:41:23 -0600 -Subject: [PATCH] media: sunxi-cir: Skip register writes during remove - -These writes occur after the device is already put back in reset, so -they never had any effect. - -Signed-off-by: Samuel Holland ---- - drivers/media/rc/sunxi-cir.c | 10 ---------- - 1 file changed, 10 deletions(-) - ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -342,22 +342,12 @@ exit_reset_assert: - - static int sunxi_ir_remove(struct platform_device *pdev) - { -- unsigned long flags; - struct sunxi_ir *ir = platform_get_drvdata(pdev); - - clk_disable_unprepare(ir->clk); - clk_disable_unprepare(ir->apb_clk); - reset_control_assert(ir->rst); - -- spin_lock_irqsave(&ir->ir_lock, flags); -- /* disable IR IRQ */ -- writel(0, ir->base + SUNXI_IR_RXINT_REG); -- /* clear All Rx Interrupt Status */ -- writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); -- /* disable IR */ -- writel(0, ir->base + SUNXI_IR_CTL_REG); -- spin_unlock_irqrestore(&ir->ir_lock, flags); -- - rc_unregister_device(ir->rc); - return 0; - } diff --git a/projects/Allwinner/patches/linux/crust/0013-media-sunxi-cir-Remove-unnecessary-spinlock.patch b/projects/Allwinner/patches/linux/crust/0013-media-sunxi-cir-Remove-unnecessary-spinlock.patch deleted file mode 100644 index 748508337d..0000000000 --- a/projects/Allwinner/patches/linux/crust/0013-media-sunxi-cir-Remove-unnecessary-spinlock.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 10 Jan 2021 00:43:19 -0600 -Subject: [PATCH] media: sunxi-cir: Remove unnecessary spinlock - -Only one register, SUNXI_IR_CIR_REG, is written from outside the -interrupt handler, and that register is not written from inside it. -There is no overlap between different contexts, so no lock is needed. - -Signed-off-by: Samuel Holland ---- - drivers/media/rc/sunxi-cir.c | 10 ---------- - 1 file changed, 10 deletions(-) - ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -86,7 +86,6 @@ struct sunxi_ir_quirks { - }; - - struct sunxi_ir { -- spinlock_t ir_lock; - struct rc_dev *rc; - void __iomem *base; - int irq; -@@ -105,8 +104,6 @@ static irqreturn_t sunxi_ir_irq(int irqn - struct sunxi_ir *ir = dev_id; - struct ir_raw_event rawir = {}; - -- spin_lock(&ir->ir_lock); -- - status = readl(ir->base + SUNXI_IR_RXSTA_REG); - - /* clean all pending statuses */ -@@ -137,8 +134,6 @@ static irqreturn_t sunxi_ir_irq(int irqn - ir_raw_event_handle(ir->rc); - } - -- spin_unlock(&ir->ir_lock); -- - return IRQ_HANDLED; - } - -@@ -160,17 +155,14 @@ static int sunxi_ir_set_timeout(struct r - { - struct sunxi_ir *ir = rc_dev->priv; - unsigned int base_clk = clk_get_rate(ir->clk); -- unsigned long flags; - - unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout); - - dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr); - -- spin_lock_irqsave(&ir->ir_lock, flags); - /* Set noise threshold and idle threshold */ - writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr), - ir->base + SUNXI_IR_CIR_REG); -- spin_unlock_irqrestore(&ir->ir_lock, flags); - - rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr); - -@@ -199,8 +191,6 @@ static int sunxi_ir_probe(struct platfor - return -ENODEV; - } - -- spin_lock_init(&ir->ir_lock); -- - ir->fifo_size = quirks->fifo_size; - - /* Clock */ diff --git a/projects/Allwinner/patches/linux/crust/0014-media-sunxi-cir-Factor-out-hardware-initialization.patch b/projects/Allwinner/patches/linux/crust/0014-media-sunxi-cir-Factor-out-hardware-initialization.patch deleted file mode 100644 index b5ea04bc71..0000000000 --- a/projects/Allwinner/patches/linux/crust/0014-media-sunxi-cir-Factor-out-hardware-initialization.patch +++ /dev/null @@ -1,223 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 10 Jan 2021 00:50:32 -0600 -Subject: [PATCH] media: sunxi-cir: Factor out hardware initialization - -Signed-off-by: Samuel Holland ---- - drivers/media/rc/sunxi-cir.c | 142 ++++++++++++++++++++--------------- - 1 file changed, 82 insertions(+), 60 deletions(-) - ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -90,6 +90,7 @@ struct sunxi_ir { - void __iomem *base; - int irq; - int fifo_size; -+ u32 base_clk_freq; - struct clk *clk; - struct clk *apb_clk; - struct reset_control *rst; -@@ -169,10 +170,81 @@ static int sunxi_ir_set_timeout(struct r - return 0; - } - -+static int sunxi_ir_hw_init(struct device *dev) -+{ -+ struct sunxi_ir *ir = dev_get_drvdata(dev); -+ unsigned long tmp; -+ int ret; -+ -+ ret = reset_control_deassert(ir->rst); -+ if (ret) -+ return ret; -+ -+ ret = clk_set_rate(ir->clk, ir->base_clk_freq); -+ if (ret) { -+ dev_err(dev, "set ir base clock failed!\n"); -+ goto exit_reset_assert; -+ } -+ dev_dbg(dev, "set base clock frequency to %d Hz.\n", ir->base_clk_freq); -+ -+ if (clk_prepare_enable(ir->apb_clk)) { -+ dev_err(dev, "try to enable apb_ir_clk failed\n"); -+ ret = -EINVAL; -+ goto exit_reset_assert; -+ } -+ -+ if (clk_prepare_enable(ir->clk)) { -+ dev_err(dev, "try to enable ir_clk failed\n"); -+ ret = -EINVAL; -+ goto exit_apb_clk_disable; -+ } -+ -+ /* Enable CIR Mode */ -+ writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG); -+ -+ /* Set noise threshold and idle threshold */ -+ sunxi_ir_set_timeout(ir->rc, ir->rc->timeout); -+ -+ /* Invert Input Signal */ -+ writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); -+ -+ /* Clear All Rx Interrupt Status */ -+ writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); -+ -+ /* -+ * Enable IRQ on overflow, packet end, FIFO available with trigger -+ * level -+ */ -+ writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | -+ REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1), -+ ir->base + SUNXI_IR_RXINT_REG); -+ -+ /* Enable IR Module */ -+ tmp = readl(ir->base + SUNXI_IR_CTL_REG); -+ writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); -+ -+ return 0; -+ -+exit_apb_clk_disable: -+ clk_disable_unprepare(ir->apb_clk); -+exit_reset_assert: -+ reset_control_assert(ir->rst); -+ -+ return ret; -+} -+ -+static void sunxi_ir_hw_exit(struct device *dev) -+{ -+ struct sunxi_ir *ir = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(ir->clk); -+ clk_disable_unprepare(ir->apb_clk); -+ reset_control_assert(ir->rst); -+} -+ - static int sunxi_ir_probe(struct platform_device *pdev) - { - int ret = 0; -- unsigned long tmp = 0; - - struct device *dev = &pdev->dev; - struct device_node *dn = dev->of_node; -@@ -207,49 +279,26 @@ static int sunxi_ir_probe(struct platfor - - /* Base clock frequency (optional) */ - of_property_read_u32(dn, "clock-frequency", &b_clk_freq); -+ ir->base_clk_freq = b_clk_freq; - - /* Reset */ - if (quirks->has_reset) { - ir->rst = devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(ir->rst)) - return PTR_ERR(ir->rst); -- ret = reset_control_deassert(ir->rst); -- if (ret) -- return ret; -- } -- -- ret = clk_set_rate(ir->clk, b_clk_freq); -- if (ret) { -- dev_err(dev, "set ir base clock failed!\n"); -- goto exit_reset_assert; -- } -- dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq); -- -- if (clk_prepare_enable(ir->apb_clk)) { -- dev_err(dev, "try to enable apb_ir_clk failed\n"); -- ret = -EINVAL; -- goto exit_reset_assert; -- } -- -- if (clk_prepare_enable(ir->clk)) { -- dev_err(dev, "try to enable ir_clk failed\n"); -- ret = -EINVAL; -- goto exit_clkdisable_apb_clk; - } - - /* IO */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ir->base = devm_ioremap_resource(dev, res); - if (IS_ERR(ir->base)) { -- ret = PTR_ERR(ir->base); -- goto exit_clkdisable_clk; -+ return PTR_ERR(ir->base); - } - - ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW); - if (!ir->rc) { - dev_err(dev, "failed to allocate device\n"); -- ret = -ENOMEM; -- goto exit_clkdisable_clk; -+ return -ENOMEM; - } - - ir->rc->priv = ir; -@@ -265,6 +314,7 @@ static int sunxi_ir_probe(struct platfor - ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; - /* Frequency after IR internal divider with sample period in us */ - ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64)); -+ ir->rc->timeout = IR_DEFAULT_TIMEOUT; - ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0); - ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255); - ir->rc->s_timeout = sunxi_ir_set_timeout; -@@ -291,41 +341,15 @@ static int sunxi_ir_probe(struct platfor - goto exit_free_dev; - } - -- /* Enable CIR Mode */ -- writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); -- -- /* Set noise threshold and idle threshold */ -- sunxi_ir_set_timeout(ir->rc, IR_DEFAULT_TIMEOUT); -- -- /* Invert Input Signal */ -- writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); -- -- /* Clear All Rx Interrupt Status */ -- writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); -- -- /* -- * Enable IRQ on overflow, packet end, FIFO available with trigger -- * level -- */ -- writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | -- REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1), -- ir->base + SUNXI_IR_RXINT_REG); -- -- /* Enable IR Module */ -- tmp = readl(ir->base + SUNXI_IR_CTL_REG); -- writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); -+ ret = sunxi_ir_hw_init(dev); -+ if (ret) -+ goto exit_free_dev; - - dev_info(dev, "initialized sunXi IR driver\n"); - return 0; - - exit_free_dev: - rc_free_device(ir->rc); --exit_clkdisable_clk: -- clk_disable_unprepare(ir->clk); --exit_clkdisable_apb_clk: -- clk_disable_unprepare(ir->apb_clk); --exit_reset_assert: -- reset_control_assert(ir->rst); - - return ret; - } -@@ -334,11 +358,9 @@ static int sunxi_ir_remove(struct platfo - { - struct sunxi_ir *ir = platform_get_drvdata(pdev); - -- clk_disable_unprepare(ir->clk); -- clk_disable_unprepare(ir->apb_clk); -- reset_control_assert(ir->rst); -- -+ sunxi_ir_hw_exit(&pdev->dev); - rc_unregister_device(ir->rc); -+ - return 0; - } - diff --git a/projects/Allwinner/patches/linux/crust/0015-media-sunxi-cir-Implement-suspend-resume-shutdown-ca.patch b/projects/Allwinner/patches/linux/crust/0015-media-sunxi-cir-Implement-suspend-resume-shutdown-ca.patch deleted file mode 100644 index be55dd425c..0000000000 --- a/projects/Allwinner/patches/linux/crust/0015-media-sunxi-cir-Implement-suspend-resume-shutdown-ca.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 10 Jan 2021 00:51:31 -0600 -Subject: [PATCH] media: sunxi-cir: Implement suspend/resume/shutdown callbacks - -Signed-off-by: Samuel Holland ---- - drivers/media/rc/sunxi-cir.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -242,6 +242,18 @@ static void sunxi_ir_hw_exit(struct devi - reset_control_assert(ir->rst); - } - -+static int __maybe_unused sunxi_ir_suspend(struct device *dev) -+{ -+ sunxi_ir_hw_exit(dev); -+ -+ return 0; -+} -+ -+static int __maybe_unused sunxi_ir_resume(struct device *dev) -+{ -+ return sunxi_ir_hw_init(dev); -+} -+ - static int sunxi_ir_probe(struct platform_device *pdev) - { - int ret = 0; -@@ -364,6 +376,11 @@ static int sunxi_ir_remove(struct platfo - return 0; - } - -+static void sunxi_ir_shutdown(struct platform_device *pdev) -+{ -+ sunxi_ir_hw_exit(&pdev->dev); -+} -+ - static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = { - .has_reset = false, - .fifo_size = 16, -@@ -396,12 +413,16 @@ static const struct of_device_id sunxi_i - }; - MODULE_DEVICE_TABLE(of, sunxi_ir_match); - -+static SIMPLE_DEV_PM_OPS(sunxi_ir_pm_ops, sunxi_ir_suspend, sunxi_ir_resume); -+ - static struct platform_driver sunxi_ir_driver = { - .probe = sunxi_ir_probe, - .remove = sunxi_ir_remove, -+ .shutdown = sunxi_ir_shutdown, - .driver = { - .name = SUNXI_IR_DEV, - .of_match_table = sunxi_ir_match, -+ .pm = &sunxi_ir_pm_ops, - }, - }; - diff --git a/projects/Allwinner/patches/linux/crust/0016-irqchip-sun6i-r-Use-a-stacked-irqchip-driver.patch b/projects/Allwinner/patches/linux/crust/0016-irqchip-sun6i-r-Use-a-stacked-irqchip-driver.patch deleted file mode 100644 index 0bc0b2fd38..0000000000 --- a/projects/Allwinner/patches/linux/crust/0016-irqchip-sun6i-r-Use-a-stacked-irqchip-driver.patch +++ /dev/null @@ -1,437 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 25 Aug 2019 05:35:08 -0500 -Subject: [PATCH] irqchip/sun6i-r: Use a stacked irqchip driver - -The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the -original sun4i interrupt controller than the sun7i/sun9i NMI controller. -It is used for two distinct purposes: - - To control the trigger, latch, and mask for the NMI input pin - - To provide the interrupt input for the ARISC coprocessor - -As this interrupt controller is not documented, information about it -comes from vendor-provided firmware blobs and from experimentation. - -Differences from the sun4i interrupt controller appear to be: - - It only has one or two registers of each kind (max 32 or 64 IRQs) - - Multiplexing logic is added to support additional inputs - - There is no FIQ-related logic - - There is no interrupt priority logic - -In order to fulfill its two purposes, this hardware block combines four -types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this -chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0 -pending" output from this chip, if enabled, is then routed to a SPI IRQ -input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect -the NMI IRQ seen at the GIC. - -The NMI is followed by a contiguous block of 15 "direct" (my name for -them) IRQ inputs that are connected in parallel to both R_INTC and the -GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the -IRQs seen at the GIC. - -Following the direct IRQs are the ARISC's copy of banked IRQs for shared -peripherals. These are not relevant to Linux. The remaining IRQs are -connected to a multiplexer and provide access to the first (up to) 128 -SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs. - -Because of the 1:1 correspondence between R_INTC and GIC inputs, this is -a perfect scenario for using a stacked irqchip driver. We want to hook -into setting the NMI trigger type, but not actually handle any IRQ here. - -To allow access to all multiplexed IRQs, this driver requires a new -binding where the interrupt number matches the GIC interrupt number. -(This moves the NMI from number 0 to 32 or 96, depending on the SoC.) -For simplicity, copy the three-cell GIC binding; this disambiguates -interrupt 0 in the old binding (the NMI) from interrupt 0 in the new -binding (SPI 0) by the number of cells. - -Since R_INTC is in the always-on power domain, and its output is visible -to the power management coprocessor, a stacked irqchip driver provides a -simple way to add wakeup support to any of its IRQs. That is the next -patch; for now, just the NMI is moved over. - -This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi: -Support sun6i-a31-r-intc compatible"). - -Signed-off-by: Samuel Holland ---- - arch/arm/mach-sunxi/Kconfig | 2 + - arch/arm64/Kconfig.platforms | 2 + - drivers/irqchip/Makefile | 1 + - drivers/irqchip/irq-sun6i-r.c | 284 ++++++++++++++++++++++++++++++++ - drivers/irqchip/irq-sunxi-nmi.c | 26 +-- - 5 files changed, 292 insertions(+), 23 deletions(-) - create mode 100644 drivers/irqchip/irq-sun6i-r.c - ---- a/arch/arm/mach-sunxi/Kconfig -+++ b/arch/arm/mach-sunxi/Kconfig -@@ -6,6 +6,8 @@ menuconfig ARCH_SUNXI - select CLKSRC_MMIO - select GENERIC_IRQ_CHIP - select GPIOLIB -+ select IRQ_DOMAIN_HIERARCHY -+ select IRQ_FASTEOI_HIERARCHY_HANDLERS - select PINCTRL - select PM_OPP - select SUN4I_TIMER ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -17,6 +17,8 @@ config ARCH_SUNXI - bool "Allwinner sunxi 64-bit SoC Family" - select ARCH_HAS_RESET_CONTROLLER - select GENERIC_IRQ_CHIP -+ select IRQ_DOMAIN_HIERARCHY -+ select IRQ_FASTEOI_HIERARCHY_HANDLERS - select PINCTRL - select RESET_CONTROLLER - help ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic - obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o - obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o - obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o -+obj-$(CONFIG_ARCH_SUNXI) += irq-sun6i-r.o - obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o - obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o - obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o ---- /dev/null -+++ b/drivers/irqchip/irq-sun6i-r.c -@@ -0,0 +1,284 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * The R_INTC in Allwinner A31 and newer SoCs manages several types of -+ * interrupts, as shown below: -+ * -+ * NMI IRQ DIRECT IRQs MUXED IRQs -+ * bit 0 bits 1-15^ bits 19-31 -+ * -+ * +---------+ +---------+ +---------+ +---------+ -+ * | NMI Pad | | IRQ d | | IRQ m | | IRQ m+7 | -+ * +---------+ +---------+ +---------+ +---------+ -+ * | | | | | | | -+ * | | | | |......| | -+ * +------V------+ +------------+ | | | +--V------V--+ | -+ * | Invert/ | | Write 1 to | | | | | AND with | | -+ * | Edge Detect | | PENDING[0] | | | | | MUX[m/8] | | -+ * +-------------+ +------------+ | | | +------------+ | -+ * | | | | | | | -+ * +--V-------V--+ +--V--+ | +--V--+ | +--V--+ -+ * | Set Reset| | GIC | | | GIC | | | GIC | -+ * | Latch | | SPI | | | SPI |... | ...| SPI | -+ * +-------------+ | N+d | | | m | | | m+7 | -+ * | | +-----+ | +-----+ | +-----+ -+ * | | | | -+ * +-------V-+ +-V----------+ +---------V--+ +--------V--------+ -+ * | GIC SPI | | AND with | | AND with | | AND with | -+ * | N (=32) | | ENABLE[0] | | ENABLE[d] | | ENABLE[19+m/8] | -+ * +---------+ +------------+ +------------+ +-----------------+ -+ * | | | -+ * +------V-----+ +------V-----+ +--------V--------+ -+ * | Read | | Read | | Read | -+ * | PENDING[0] | | PENDING[d] | | PENDING[19+m/8] | -+ * +------------+ +------------+ +-----------------+ -+ * -+ * ^ bits 16-18 are direct IRQs for peripherals with banked interrupts, such as -+ * the MSGBOX. These IRQs do not map to any GIC SPI. -+ * -+ * The H6 variant adds two more (banked) direct IRQs and implements the full -+ * set of 128 mux bits. This requires a second set of top-level registers. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define SUN6I_NMI_CTRL (0x0c) -+#define SUN6I_IRQ_PENDING(n) (0x10 + 4 * (n)) -+#define SUN6I_IRQ_ENABLE(n) (0x40 + 4 * (n)) -+#define SUN6I_MUX_ENABLE(n) (0xc0 + 4 * (n)) -+ -+#define SUN6I_NMI_SRC_TYPE_LEVEL_LOW 0 -+#define SUN6I_NMI_SRC_TYPE_EDGE_FALLING 1 -+#define SUN6I_NMI_SRC_TYPE_LEVEL_HIGH 2 -+#define SUN6I_NMI_SRC_TYPE_EDGE_RISING 3 -+ -+#define SUN6I_NMI_BIT BIT(0) -+ -+#define SUN6I_NMI_NEEDS_ACK ((void *)1) -+ -+#define SUN6I_NR_TOP_LEVEL_IRQS 64 -+#define SUN6I_NR_DIRECT_IRQS 16 -+#define SUN6I_NR_MUX_BITS 128 -+ -+static void __iomem *base; -+static irq_hw_number_t nmi_hwirq; -+ -+static void sun6i_r_intc_ack_nmi(void) -+{ -+ writel(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0)); -+} -+ -+static void sun6i_r_intc_nmi_ack(struct irq_data *data) -+{ -+ if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH) -+ sun6i_r_intc_ack_nmi(); -+ else -+ data->chip_data = SUN6I_NMI_NEEDS_ACK; -+} -+ -+static void sun6i_r_intc_nmi_eoi(struct irq_data *data) -+{ -+ /* For oneshot IRQs, delay the ack until the IRQ is unmasked. */ -+ if (data->chip_data == SUN6I_NMI_NEEDS_ACK && !irqd_irq_masked(data)) { -+ sun6i_r_intc_ack_nmi(); -+ data->chip_data = 0; -+ } -+ -+ irq_chip_eoi_parent(data); -+} -+ -+static void sun6i_r_intc_nmi_unmask(struct irq_data *data) -+{ -+ if (data->chip_data == SUN6I_NMI_NEEDS_ACK) { -+ sun6i_r_intc_ack_nmi(); -+ data->chip_data = 0; -+ } -+ -+ irq_chip_unmask_parent(data); -+} -+ -+static int sun6i_r_intc_nmi_set_type(struct irq_data *data, unsigned int type) -+{ -+ u32 nmi_src_type; -+ -+ switch (type) { -+ case IRQ_TYPE_EDGE_RISING: -+ nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_RISING; -+ break; -+ case IRQ_TYPE_EDGE_FALLING: -+ nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_FALLING; -+ break; -+ case IRQ_TYPE_LEVEL_HIGH: -+ nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_HIGH; -+ break; -+ case IRQ_TYPE_LEVEL_LOW: -+ nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_LOW; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ writel_relaxed(nmi_src_type, base + SUN6I_NMI_CTRL); -+ -+ /* -+ * The "External NMI" GIC input connects to a latch inside R_INTC, not -+ * directly to the pin. So the GIC trigger type does not depend on the -+ * NMI pin trigger type. -+ */ -+ return irq_chip_set_type_parent(data, IRQ_TYPE_LEVEL_HIGH); -+} -+ -+static int sun6i_r_intc_nmi_set_irqchip_state(struct irq_data *data, -+ enum irqchip_irq_state which, -+ bool state) -+{ -+ if (which == IRQCHIP_STATE_PENDING && !state) -+ sun6i_r_intc_ack_nmi(); -+ -+ return irq_chip_set_parent_state(data, which, state); -+} -+ -+static struct irq_chip sun6i_r_intc_nmi_chip = { -+ .name = "sun6i-r-intc", -+ .irq_ack = sun6i_r_intc_nmi_ack, -+ .irq_mask = irq_chip_mask_parent, -+ .irq_unmask = sun6i_r_intc_nmi_unmask, -+ .irq_eoi = sun6i_r_intc_nmi_eoi, -+ .irq_set_affinity = irq_chip_set_affinity_parent, -+ .irq_set_type = sun6i_r_intc_nmi_set_type, -+ .irq_set_irqchip_state = sun6i_r_intc_nmi_set_irqchip_state, -+ .flags = IRQCHIP_SET_TYPE_MASKED | -+ IRQCHIP_SKIP_SET_WAKE, -+}; -+ -+static int sun6i_r_intc_domain_translate(struct irq_domain *domain, -+ struct irq_fwspec *fwspec, -+ unsigned long *hwirq, -+ unsigned int *type) -+{ -+ /* Accept the old two-cell binding for the NMI only. */ -+ if (fwspec->param_count == 2 && fwspec->param[0] == 0) { -+ *hwirq = nmi_hwirq; -+ *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; -+ return 0; -+ } -+ -+ /* Otherwise this binding should match the GIC SPI binding. */ -+ if (fwspec->param_count < 3) -+ return -EINVAL; -+ if (fwspec->param[0] != GIC_SPI) -+ return -EINVAL; -+ -+ *hwirq = fwspec->param[1]; -+ *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; -+ -+ return 0; -+} -+ -+static int sun6i_r_intc_domain_alloc(struct irq_domain *domain, -+ unsigned int virq, -+ unsigned int nr_irqs, void *arg) -+{ -+ struct irq_fwspec *fwspec = arg; -+ struct irq_fwspec gic_fwspec; -+ unsigned long hwirq; -+ unsigned int type; -+ int i, ret; -+ -+ ret = sun6i_r_intc_domain_translate(domain, fwspec, &hwirq, &type); -+ if (ret) -+ return ret; -+ if (hwirq + nr_irqs > SUN6I_NR_MUX_BITS) -+ return -EINVAL; -+ -+ /* Construct a GIC-compatible fwspec from this fwspec. */ -+ gic_fwspec = (struct irq_fwspec) { -+ .fwnode = domain->parent->fwnode, -+ .param_count = 3, -+ .param = { GIC_SPI, hwirq, type }, -+ }; -+ -+ ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < nr_irqs; ++i, ++hwirq, ++virq) { -+ if (hwirq == nmi_hwirq) { -+ irq_domain_set_hwirq_and_chip(domain, virq, hwirq, -+ &sun6i_r_intc_nmi_chip, 0); -+ irq_set_handler(virq, handle_fasteoi_ack_irq); -+ } else { -+ /* Only the NMI is currently supported. */ -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops sun6i_r_intc_domain_ops = { -+ .translate = sun6i_r_intc_domain_translate, -+ .alloc = sun6i_r_intc_domain_alloc, -+ .free = irq_domain_free_irqs_common, -+}; -+ -+static void sun6i_r_intc_resume(void) -+{ -+ int i; -+ -+ /* Only the NMI is relevant during normal operation. */ -+ writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_ENABLE(0)); -+ for (i = 1; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i) -+ writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); -+} -+ -+static int __init sun6i_r_intc_init(struct device_node *node, -+ struct device_node *parent) -+{ -+ struct irq_domain *domain, *parent_domain; -+ struct of_phandle_args nmi_parent; -+ int ret; -+ -+ /* Extract the NMI hwirq number from the OF node. */ -+ ret = of_irq_parse_one(node, 0, &nmi_parent); -+ if (ret) -+ return ret; -+ if (nmi_parent.args_count < 3 || -+ nmi_parent.args[0] != GIC_SPI || -+ nmi_parent.args[2] != IRQ_TYPE_LEVEL_HIGH) -+ return -EINVAL; -+ nmi_hwirq = nmi_parent.args[1]; -+ -+ parent_domain = irq_find_host(parent); -+ if (!parent_domain) { -+ pr_err("%pOF: Failed to obtain parent domain\n", node); -+ return -ENXIO; -+ } -+ -+ base = of_io_request_and_map(node, 0, NULL); -+ if (IS_ERR(base)) { -+ pr_err("%pOF: Failed to map MMIO region\n", node); -+ return PTR_ERR(base); -+ } -+ -+ domain = irq_domain_add_hierarchy(parent_domain, 0, 0, node, -+ &sun6i_r_intc_domain_ops, NULL); -+ if (!domain) { -+ pr_err("%pOF: Failed to allocate domain\n", node); -+ iounmap(base); -+ return -ENOMEM; -+ } -+ -+ sun6i_r_intc_ack_nmi(); -+ sun6i_r_intc_resume(); -+ -+ return 0; -+} -+IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init); ---- a/drivers/irqchip/irq-sunxi-nmi.c -+++ b/drivers/irqchip/irq-sunxi-nmi.c -@@ -27,18 +27,12 @@ - - #define SUNXI_NMI_IRQ_BIT BIT(0) - --#define SUN6I_R_INTC_CTRL 0x0c --#define SUN6I_R_INTC_PENDING 0x10 --#define SUN6I_R_INTC_ENABLE 0x40 -- - /* - * For deprecated sun6i-a31-sc-nmi compatible. -- * Registers are offset by 0x0c. - */ --#define SUN6I_R_INTC_NMI_OFFSET 0x0c --#define SUN6I_NMI_CTRL (SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET) --#define SUN6I_NMI_PENDING (SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET) --#define SUN6I_NMI_ENABLE (SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET) -+#define SUN6I_NMI_CTRL 0x00 -+#define SUN6I_NMI_PENDING 0x04 -+#define SUN6I_NMI_ENABLE 0x34 - - #define SUN7I_NMI_CTRL 0x00 - #define SUN7I_NMI_PENDING 0x04 -@@ -61,12 +55,6 @@ struct sunxi_sc_nmi_reg_offs { - u32 enable; - }; - --static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = { -- .ctrl = SUN6I_R_INTC_CTRL, -- .pend = SUN6I_R_INTC_PENDING, -- .enable = SUN6I_R_INTC_ENABLE, --}; -- - static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = { - .ctrl = SUN6I_NMI_CTRL, - .pend = SUN6I_NMI_PENDING, -@@ -232,14 +220,6 @@ fail_irqd_remove: - return ret; - } - --static int __init sun6i_r_intc_irq_init(struct device_node *node, -- struct device_node *parent) --{ -- return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs); --} --IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", -- sun6i_r_intc_irq_init); -- - static int __init sun6i_sc_nmi_irq_init(struct device_node *node, - struct device_node *parent) - { diff --git a/projects/Allwinner/patches/linux/crust/0017-irqchip-sun6i-r-Add-wakeup-support.patch b/projects/Allwinner/patches/linux/crust/0017-irqchip-sun6i-r-Add-wakeup-support.patch deleted file mode 100644 index 2c7140aa75..0000000000 --- a/projects/Allwinner/patches/linux/crust/0017-irqchip-sun6i-r-Add-wakeup-support.patch +++ /dev/null @@ -1,210 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 12 Jan 2020 20:00:36 -0600 -Subject: [PATCH] irqchip/sun6i-r: Add wakeup support - -Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them -to the hardware during the syscore phase of suspend and shutdown. Then -restore the original set of enabled IRQs (only the NMI) during resume. - -This serves two purposes. First, it lets power management firmware -running on the ARISC coprocessor know which wakeup sources Linux wants -to have enabled. That way, it can avoid turning them off when it shuts -down the remainder of the clock tree. Second, it preconfigures the -coprocessor's interrupt controller, so the firmware's wakeup logic -is as simple as waiting for an interrupt to arrive. - -The suspend/resume logic is not conditional on PM_SLEEP because it is -identical to the init/shutdown logic. Wake IRQs may be enabled during -shutdown to allow powering the board back on. As an example, see -commit a5c5e50cce9d ("Input: gpio-keys - add shutdown callback"). - -Signed-off-by: Samuel Holland ---- - drivers/irqchip/irq-sun6i-r.c | 107 ++++++++++++++++++++++++++++++++-- - 1 file changed, 101 insertions(+), 6 deletions(-) - ---- a/drivers/irqchip/irq-sun6i-r.c -+++ b/drivers/irqchip/irq-sun6i-r.c -@@ -39,6 +39,7 @@ - * set of 128 mux bits. This requires a second set of top-level registers. - */ - -+#include - #include - #include - #include -@@ -46,6 +47,7 @@ - #include - #include - #include -+#include - - #include - -@@ -67,8 +69,17 @@ - #define SUN6I_NR_DIRECT_IRQS 16 - #define SUN6I_NR_MUX_BITS 128 - -+struct sun6i_r_intc_variant { -+ u32 first_mux_irq; -+ u32 nr_mux_irqs; -+ u32 mux_valid[BITS_TO_U32(SUN6I_NR_MUX_BITS)]; -+}; -+ - static void __iomem *base; - static irq_hw_number_t nmi_hwirq; -+static DECLARE_BITMAP(wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS); -+static DECLARE_BITMAP(wake_mux_enabled, SUN6I_NR_MUX_BITS); -+static DECLARE_BITMAP(wake_mux_valid, SUN6I_NR_MUX_BITS); - - static void sun6i_r_intc_ack_nmi(void) - { -@@ -145,6 +156,21 @@ static int sun6i_r_intc_nmi_set_irqchip_ - return irq_chip_set_parent_state(data, which, state); - } - -+static int sun6i_r_intc_irq_set_wake(struct irq_data *data, unsigned int on) -+{ -+ unsigned long offset_from_nmi = data->hwirq - nmi_hwirq; -+ -+ if (offset_from_nmi < SUN6I_NR_DIRECT_IRQS) -+ assign_bit(offset_from_nmi, wake_irq_enabled, on); -+ else if (test_bit(data->hwirq, wake_mux_valid)) -+ assign_bit(data->hwirq, wake_mux_enabled, on); -+ else -+ /* Not wakeup capable. */ -+ return -EPERM; -+ -+ return 0; -+} -+ - static struct irq_chip sun6i_r_intc_nmi_chip = { - .name = "sun6i-r-intc", - .irq_ack = sun6i_r_intc_nmi_ack, -@@ -154,8 +180,19 @@ static struct irq_chip sun6i_r_intc_nmi_ - .irq_set_affinity = irq_chip_set_affinity_parent, - .irq_set_type = sun6i_r_intc_nmi_set_type, - .irq_set_irqchip_state = sun6i_r_intc_nmi_set_irqchip_state, -- .flags = IRQCHIP_SET_TYPE_MASKED | -- IRQCHIP_SKIP_SET_WAKE, -+ .irq_set_wake = sun6i_r_intc_irq_set_wake, -+ .flags = IRQCHIP_SET_TYPE_MASKED, -+}; -+ -+static struct irq_chip sun6i_r_intc_wakeup_chip = { -+ .name = "sun6i-r-intc", -+ .irq_mask = irq_chip_mask_parent, -+ .irq_unmask = irq_chip_unmask_parent, -+ .irq_eoi = irq_chip_eoi_parent, -+ .irq_set_affinity = irq_chip_set_affinity_parent, -+ .irq_set_type = irq_chip_set_type_parent, -+ .irq_set_wake = sun6i_r_intc_irq_set_wake, -+ .flags = IRQCHIP_SET_TYPE_MASKED, - }; - - static int sun6i_r_intc_domain_translate(struct irq_domain *domain, -@@ -215,8 +252,8 @@ static int sun6i_r_intc_domain_alloc(str - &sun6i_r_intc_nmi_chip, 0); - irq_set_handler(virq, handle_fasteoi_ack_irq); - } else { -- /* Only the NMI is currently supported. */ -- return -EINVAL; -+ irq_domain_set_hwirq_and_chip(domain, virq, hwirq, -+ &sun6i_r_intc_wakeup_chip, 0); - } - } - -@@ -229,6 +266,22 @@ static const struct irq_domain_ops sun6i - .free = irq_domain_free_irqs_common, - }; - -+static int sun6i_r_intc_suspend(void) -+{ -+ u32 buf[BITS_TO_U32(max(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))]; -+ int i; -+ -+ /* Wake IRQs are enabled during system sleep and shutdown. */ -+ bitmap_to_arr32(buf, wake_irq_enabled, SUN6I_NR_TOP_LEVEL_IRQS); -+ for (i = 0; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i) -+ writel_relaxed(buf[i], base + SUN6I_IRQ_ENABLE(i)); -+ bitmap_to_arr32(buf, wake_mux_enabled, SUN6I_NR_MUX_BITS); -+ for (i = 0; i < BITS_TO_U32(SUN6I_NR_MUX_BITS); ++i) -+ writel_relaxed(buf[i], base + SUN6I_MUX_ENABLE(i)); -+ -+ return 0; -+} -+ - static void sun6i_r_intc_resume(void) - { - int i; -@@ -239,8 +292,20 @@ static void sun6i_r_intc_resume(void) - writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); - } - -+static void sun6i_r_intc_shutdown(void) -+{ -+ sun6i_r_intc_suspend(); -+} -+ -+static struct syscore_ops sun6i_r_intc_syscore_ops = { -+ .suspend = sun6i_r_intc_suspend, -+ .resume = sun6i_r_intc_resume, -+ .shutdown = sun6i_r_intc_shutdown, -+}; -+ - static int __init sun6i_r_intc_init(struct device_node *node, -- struct device_node *parent) -+ struct device_node *parent, -+ const struct sun6i_r_intc_variant *v) - { - struct irq_domain *domain, *parent_domain; - struct of_phandle_args nmi_parent; -@@ -256,6 +321,9 @@ static int __init sun6i_r_intc_init(stru - return -EINVAL; - nmi_hwirq = nmi_parent.args[1]; - -+ bitmap_set(wake_irq_enabled, v->first_mux_irq, v->nr_mux_irqs); -+ bitmap_from_arr32(wake_mux_valid, v->mux_valid, SUN6I_NR_MUX_BITS); -+ - parent_domain = irq_find_host(parent); - if (!parent_domain) { - pr_err("%pOF: Failed to obtain parent domain\n", node); -@@ -276,9 +344,36 @@ static int __init sun6i_r_intc_init(stru - return -ENOMEM; - } - -+ register_syscore_ops(&sun6i_r_intc_syscore_ops); -+ - sun6i_r_intc_ack_nmi(); - sun6i_r_intc_resume(); - - return 0; - } --IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init); -+ -+static const struct sun6i_r_intc_variant sun6i_a31_r_intc_variant __initconst = { -+ .first_mux_irq = 19, -+ .nr_mux_irqs = 13, -+ .mux_valid = { 0xffffffff, 0xfff80000, 0xffffffff, 0x0000000f }, -+}; -+ -+static int __init sun6i_a31_r_intc_init(struct device_node *node, -+ struct device_node *parent) -+{ -+ return sun6i_r_intc_init(node, parent, &sun6i_a31_r_intc_variant); -+} -+IRQCHIP_DECLARE(sun6i_a31_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_a31_r_intc_init); -+ -+static const struct sun6i_r_intc_variant sun50i_h6_r_intc_variant __initconst = { -+ .first_mux_irq = 21, -+ .nr_mux_irqs = 16, -+ .mux_valid = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }, -+}; -+ -+static int __init sun50i_h6_r_intc_init(struct device_node *node, -+ struct device_node *parent) -+{ -+ return sun6i_r_intc_init(node, parent, &sun50i_h6_r_intc_variant); -+} -+IRQCHIP_DECLARE(sun50i_h6_r_intc, "allwinner,sun50i-h6-r-intc", sun50i_h6_r_intc_init); diff --git a/projects/Allwinner/patches/linux/crust/0018-ARM-dts-sunxi-Rename-nmi_intc-to-r_intc.patch b/projects/Allwinner/patches/linux/crust/0018-ARM-dts-sunxi-Rename-nmi_intc-to-r_intc.patch deleted file mode 100644 index 6c2476e745..0000000000 --- a/projects/Allwinner/patches/linux/crust/0018-ARM-dts-sunxi-Rename-nmi_intc-to-r_intc.patch +++ /dev/null @@ -1,194 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 25 Dec 2020 01:48:33 -0600 -Subject: [PATCH] ARM: dts: sunxi: Rename nmi_intc to r_intc - -The R_INTC block controls more than just the NMI, and it is a different -hardware block than the NMI INTC found in some other Allwinner SoCs, so -the label "nmi_intc" is inaccurate. Name it "r_intc" to match the -compatible and to match the few references in the vendor documentation. - -Signed-off-by: Samuel Holland ---- - arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +- - arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +- - arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +- - arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- - arch/arm/boot/dts/sun6i-a31s-primo81.dts | 2 +- - arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 2 +- - arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 +- - arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 2 +- - arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 2 +- - arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- - arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 2 +- - arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 2 +- - arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 2 +- - arch/arm/boot/dts/sun8i-r16-parrot.dts | 2 +- - arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +- - 15 files changed, 15 insertions(+), 15 deletions(-) - ---- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts -+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts -@@ -226,7 +226,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; - }; ---- a/arch/arm/boot/dts/sun6i-a31-m9.dts -+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts -@@ -115,7 +115,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; - }; ---- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts -+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts -@@ -115,7 +115,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; - }; ---- a/arch/arm/boot/dts/sun6i-a31.dtsi -+++ b/arch/arm/boot/dts/sun6i-a31.dtsi -@@ -1305,7 +1305,7 @@ - clock-output-names = "osc32k"; - }; - -- nmi_intc: interrupt-controller@1f00c00 { -+ r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; ---- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts -+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts -@@ -159,7 +159,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; - }; ---- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi -+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi -@@ -78,7 +78,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; - }; ---- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts -+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts -@@ -148,7 +148,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; ---- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts -+++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts -@@ -98,7 +98,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; - }; ---- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi -+++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi -@@ -79,7 +79,7 @@ - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; ---- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi -+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi -@@ -716,7 +716,7 @@ - #clock-cells = <1>; - }; - -- nmi_intc: interrupt-controller@1f00c00 { -+ r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; ---- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts -+++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts -@@ -98,7 +98,7 @@ - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; ---- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts -+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts -@@ -164,7 +164,7 @@ - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - }; ---- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts -+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts -@@ -163,7 +163,7 @@ - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; ---- a/arch/arm/boot/dts/sun8i-r16-parrot.dts -+++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts -@@ -164,7 +164,7 @@ - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; ---- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi -+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi -@@ -92,7 +92,7 @@ - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; -- interrupt-parent = <&nmi_intc>; -+ interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - drivevbus-supply = <®_vcc5v0>; diff --git a/projects/Allwinner/patches/linux/crust/0019-ARM-dts-sunxi-Use-the-new-r_intc-binding.patch b/projects/Allwinner/patches/linux/crust/0019-ARM-dts-sunxi-Use-the-new-r_intc-binding.patch deleted file mode 100644 index 2be8778578..0000000000 --- a/projects/Allwinner/patches/linux/crust/0019-ARM-dts-sunxi-Use-the-new-r_intc-binding.patch +++ /dev/null @@ -1,291 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 25 Dec 2020 01:49:51 -0600 -Subject: [PATCH] ARM: dts: sunxi: Use the new r_intc binding - -The binding of R_INTC was updated to allow specifying interrupts other -than the external NMI, since routing those interrupts through the R_INTC -driver allows using them for wakeup. - -Update the device trees to use the new binding. - -Signed-off-by: Samuel Holland ---- - arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +- - arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +- - arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +- - arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- - arch/arm/boot/dts/sun6i-a31s-primo81.dts | 2 +- - arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 2 +- - arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 +- - arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 2 +- - arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 2 +- - arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- - arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 2 +- - arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 2 +- - arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 4 ++-- - arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 4 ++-- - arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 4 ++-- - arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++-- - arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- - arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 2 +- - arch/arm/boot/dts/sun8i-r16-parrot.dts | 2 +- - arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +- - 20 files changed, 24 insertions(+), 24 deletions(-) - ---- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts -+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts -@@ -227,7 +227,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - x-powers,drive-vbus-en; - }; - }; ---- a/arch/arm/boot/dts/sun6i-a31-m9.dts -+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts -@@ -116,7 +116,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts -+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts -@@ -116,7 +116,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm/boot/dts/sun6i-a31.dtsi -+++ b/arch/arm/boot/dts/sun6i-a31.dtsi -@@ -1308,7 +1308,7 @@ - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; -- #interrupt-cells = <2>; -+ #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; ---- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts -+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts -@@ -160,7 +160,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - x-powers,drive-vbus-en; - }; - }; ---- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi -+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi -@@ -79,7 +79,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts -+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts -@@ -149,7 +149,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; ---- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts -+++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts -@@ -99,7 +99,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi -+++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi -@@ -80,7 +80,7 @@ - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; ---- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi -+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi -@@ -719,7 +719,7 @@ - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; -- #interrupt-cells = <2>; -+ #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; ---- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts -+++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts -@@ -99,7 +99,7 @@ - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; ---- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts -+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts -@@ -165,7 +165,7 @@ - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - }; - }; ---- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts -+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts -@@ -122,7 +122,7 @@ - compatible = "x-powers,axp818", "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - swin-supply = <®_dcdc1>; - }; -@@ -142,7 +142,7 @@ - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", ---- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts -+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts -@@ -203,7 +203,7 @@ - compatible = "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - fldoin-supply = <®_dcdc5>; - swin-supply = <®_dcdc1>; -@@ -225,7 +225,7 @@ - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", ---- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts -+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts -@@ -239,7 +239,7 @@ - compatible = "x-powers,axp818", "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; -@@ -260,7 +260,7 @@ - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", ---- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts -+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts -@@ -263,7 +263,7 @@ - compatible = "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -@@ -283,7 +283,7 @@ - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", ---- a/arch/arm/boot/dts/sun8i-a83t.dtsi -+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi -@@ -1114,7 +1114,7 @@ - compatible = "allwinner,sun8i-a83t-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; -- #interrupt-cells = <2>; -+ #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; ---- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts -+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts -@@ -164,7 +164,7 @@ - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; ---- a/arch/arm/boot/dts/sun8i-r16-parrot.dts -+++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts -@@ -165,7 +165,7 @@ - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; ---- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi -+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi -@@ -93,7 +93,7 @@ - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - eldoin-supply = <®_dcdc1>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; diff --git a/projects/Allwinner/patches/linux/crust/0020-ARM-dts-sunxi-h3-h5-Add-r_intc-node.patch b/projects/Allwinner/patches/linux/crust/0020-ARM-dts-sunxi-h3-h5-Add-r_intc-node.patch deleted file mode 100644 index 992b4afc9c..0000000000 --- a/projects/Allwinner/patches/linux/crust/0020-ARM-dts-sunxi-h3-h5-Add-r_intc-node.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 12 Jan 2020 20:27:08 -0600 -Subject: [PATCH] ARM: dts: sunxi: h3/h5: Add r_intc node - -The H3 and H5 SoCs have an additional interrupt controller in the RTC -power domain that can be used to enable wakeup for certain IRQs. - -Add a node for it. - -Signed-off-by: Samuel Holland ---- - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi -+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -877,6 +877,15 @@ - #clock-cells = <1>; - }; - -+ r_intc: interrupt-controller@1f00c00 { -+ compatible = "allwinner,sun8i-h3-r-intc", -+ "allwinner,sun6i-a31-r-intc"; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ reg = <0x01f00c00 0x400>; -+ interrupts = ; -+ }; -+ - r_ccu: clock@1f01400 { - compatible = "allwinner,sun8i-h3-r-ccu"; - reg = <0x01f01400 0x100>; diff --git a/projects/Allwinner/patches/linux/crust/0021-ARM-dts-sunxi-Move-wakeup-capable-IRQs-to-r_intc.patch b/projects/Allwinner/patches/linux/crust/0021-ARM-dts-sunxi-Move-wakeup-capable-IRQs-to-r_intc.patch deleted file mode 100644 index e92d678821..0000000000 --- a/projects/Allwinner/patches/linux/crust/0021-ARM-dts-sunxi-Move-wakeup-capable-IRQs-to-r_intc.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 25 Dec 2020 02:05:58 -0600 -Subject: [PATCH] ARM: dts: sunxi: Move wakeup-capable IRQs to r_intc - -All IRQs that can be used to wake up the system must be routed through -r_intc, so they are visible to firmware while the system is suspended. - -In addition to the external NMI input, which is already routed through -r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC. - -Signed-off-by: Samuel Holland ---- - arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++++ - arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 ++++ - arch/arm/boot/dts/sun8i-a83t.dtsi | 3 +++ - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 +++ - 4 files changed, 14 insertions(+) - ---- a/arch/arm/boot/dts/sun6i-a31.dtsi -+++ b/arch/arm/boot/dts/sun6i-a31.dtsi -@@ -611,6 +611,7 @@ - pio: pinctrl@1c20800 { - compatible = "allwinner,sun6i-a31-pinctrl"; - reg = <0x01c20800 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - , - , -@@ -802,6 +803,7 @@ - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - status = "disabled"; - }; -@@ -1299,6 +1301,7 @@ - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clocks = <&osc32k>; -@@ -1383,6 +1386,7 @@ - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun6i-a31-r-pinctrl"; - reg = <0x01f02c00 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; ---- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi -+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi -@@ -338,6 +338,7 @@ - pio: pinctrl@1c20800 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c20800 0x400>; -+ interrupt-parent = <&r_intc>; - /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; -@@ -473,6 +474,7 @@ - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - status = "disabled"; - }; -@@ -709,6 +711,7 @@ - rtc: rtc@1f00000 { - compatible = "allwinner,sun8i-a23-rtc"; - reg = <0x01f00000 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out"; -@@ -805,6 +808,7 @@ - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-a23-r-pinctrl"; - reg = <0x01f02c00 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; ---- a/arch/arm/boot/dts/sun8i-a83t.dtsi -+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi -@@ -708,6 +708,7 @@ - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-a83t-pinctrl"; -+ interrupt-parent = <&r_intc>; - interrupts = , - , - ; -@@ -1150,6 +1151,7 @@ - r_lradc: lradc@1f03c00 { - compatible = "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01f03c00 0x100>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - status = "disabled"; - }; -@@ -1157,6 +1159,7 @@ - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-a83t-r-pinctrl"; - reg = <0x01f02c00 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, - <&osc16Md512>; ---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi -+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -413,6 +413,7 @@ - pio: pinctrl@1c20800 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01c20800 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; -@@ -870,6 +871,7 @@ - rtc: rtc@1f00000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01f00000 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; -@@ -927,6 +929,7 @@ - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-h3-r-pinctrl"; - reg = <0x01f02c00 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; diff --git a/projects/Allwinner/patches/linux/crust/0022-arm64-dts-allwinner-Use-the-new-r_intc-binding.patch b/projects/Allwinner/patches/linux/crust/0022-arm64-dts-allwinner-Use-the-new-r_intc-binding.patch deleted file mode 100644 index 1ca5474ccc..0000000000 --- a/projects/Allwinner/patches/linux/crust/0022-arm64-dts-allwinner-Use-the-new-r_intc-binding.patch +++ /dev/null @@ -1,232 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 25 Dec 2020 01:56:58 -0600 -Subject: [PATCH] arm64: dts: allwinner: Use the new r_intc binding - -The binding of R_INTC was updated to allow specifying interrupts other -than the external NMI, since routing those interrupts through the R_INTC -driver allows using them for wakeup. - -Update the device trees to use the new binding. - -Signed-off-by: Samuel Holland ---- - arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 2 +- - arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++-- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 5 ++--- - 17 files changed, 19 insertions(+), 20 deletions(-) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts -@@ -173,7 +173,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts -@@ -191,7 +191,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts -@@ -152,7 +152,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -@@ -185,7 +185,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -@@ -192,7 +192,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -@@ -139,7 +139,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts -@@ -248,7 +248,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi -@@ -245,7 +245,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts -@@ -266,7 +266,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - x-powers,drive-vbus-en; - }; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -@@ -46,7 +46,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - }; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts -@@ -205,7 +205,7 @@ - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - wakeup-source; - }; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -1215,7 +1215,7 @@ - compatible = "allwinner,sun50i-a64-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; -- #interrupt-cells = <2>; -+ #interrupt-cells = <3>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -157,7 +157,7 @@ - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -182,7 +182,7 @@ - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -119,7 +119,7 @@ - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -@@ -167,7 +167,7 @@ - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; -@@ -280,7 +280,7 @@ - compatible = "nxp,pcf8563"; - reg = <0x51>; - interrupt-parent = <&r_intc>; -- interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ interrupts = ; - #clock-cells = <0>; - }; - }; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -931,10 +931,9 @@ - }; - - r_intc: interrupt-controller@7021000 { -- compatible = "allwinner,sun50i-h6-r-intc", -- "allwinner,sun6i-a31-r-intc"; -+ compatible = "allwinner,sun50i-h6-r-intc"; - interrupt-controller; -- #interrupt-cells = <2>; -+ #interrupt-cells = <3>; - reg = <0x07021000 0x400>; - interrupts = ; - }; diff --git a/projects/Allwinner/patches/linux/crust/0023-arm64-dts-allwinner-Move-wakeup-capable-IRQs-to-r_in.patch b/projects/Allwinner/patches/linux/crust/0023-arm64-dts-allwinner-Move-wakeup-capable-IRQs-to-r_in.patch deleted file mode 100644 index a889e893b8..0000000000 --- a/projects/Allwinner/patches/linux/crust/0023-arm64-dts-allwinner-Move-wakeup-capable-IRQs-to-r_in.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 25 Dec 2020 02:05:58 -0600 -Subject: [PATCH] arm64: dts: allwinner: Move wakeup-capable IRQs to r_intc - -All IRQs that can be used to wake up the system must be routed through -r_intc, so they are visible to firmware while the system is suspended. - -In addition to the external NMI input, which is already routed through -r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC. - -Signed-off-by: Samuel Holland ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++++ - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +++ - 2 files changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -644,6 +644,7 @@ - pio: pinctrl@1c20800 { - compatible = "allwinner,sun50i-a64-pinctrl"; - reg = <0x01c20800 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - , - ; -@@ -814,6 +815,7 @@ - compatible = "allwinner,sun50i-a64-lradc", - "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01c21800 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - status = "disabled"; - }; -@@ -1204,6 +1206,7 @@ - compatible = "allwinner,sun50i-a64-rtc", - "allwinner,sun8i-h3-rtc"; - reg = <0x01f00000 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; -@@ -1275,6 +1278,7 @@ - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun50i-a64-r-pinctrl"; - reg = <0x01f02c00 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -305,6 +305,7 @@ - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h6-pinctrl"; - reg = <0x0300b000 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - , - , -@@ -906,6 +907,7 @@ - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h6-rtc"; - reg = <0x07000000 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; -@@ -941,6 +943,7 @@ - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-h6-r-pinctrl"; - reg = <0x07022000 0x400>; -+ interrupt-parent = <&r_intc>; - interrupts = , - ; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; diff --git a/projects/Allwinner/patches/linux/crust/0026-DO-NOT-MERGE-ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch b/projects/Allwinner/patches/linux/crust/0026-DO-NOT-MERGE-ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch deleted file mode 100644 index 0ed0dcaac0..0000000000 --- a/projects/Allwinner/patches/linux/crust/0026-DO-NOT-MERGE-ARM-dts-sunxi-a83t-Protect-SCP-clocks.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 1 Jan 2020 16:03:34 -0600 -Subject: [PATCH] [DO NOT MERGE] ARM: dts: sunxi: a83t: Protect SCP clocks - -Signed-off-by: Samuel Holland ---- - arch/arm/boot/dts/sun8i-a83t.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/boot/dts/sun8i-a83t.dtsi -+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi -@@ -702,6 +702,7 @@ - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc16Md512>; - clock-names = "hosc", "losc"; -+ protected-clocks = ; - #clock-cells = <1>; - #reset-cells = <1>; - }; -@@ -1126,6 +1127,7 @@ - clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, - <&ccu CLK_PLL_PERIPH>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; -+ protected-clocks = ; - #clock-cells = <1>; - #reset-cells = <1>; - }; diff --git a/projects/Allwinner/patches/linux/crust/0030-bus-sunxi-rsb-Move-OF-match-table.patch b/projects/Allwinner/patches/linux/crust/0030-bus-sunxi-rsb-Move-OF-match-table.patch deleted file mode 100644 index 0a933a1bc8..0000000000 --- a/projects/Allwinner/patches/linux/crust/0030-bus-sunxi-rsb-Move-OF-match-table.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Mon, 30 Dec 2019 17:12:42 -0600 -Subject: [PATCH] bus: sunxi-rsb: Move OF match table - -For some reason, this driver's OF match table was placed above the -probe/remove functions, far away from the platform_driver definition. -Adding device PM ops would move the table even farther away. Let's move -it to the usual place, right before the platform_driver. - -Signed-off-by: Samuel Holland ---- - drivers/bus/sunxi-rsb.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/bus/sunxi-rsb.c -+++ b/drivers/bus/sunxi-rsb.c -@@ -614,12 +614,6 @@ static int of_rsb_register_devices(struc - return 0; - } - --static const struct of_device_id sunxi_rsb_of_match_table[] = { -- { .compatible = "allwinner,sun8i-a23-rsb" }, -- {} --}; --MODULE_DEVICE_TABLE(of, sunxi_rsb_of_match_table); -- - static int sunxi_rsb_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -747,6 +741,12 @@ static int sunxi_rsb_remove(struct platf - return 0; - } - -+static const struct of_device_id sunxi_rsb_of_match_table[] = { -+ { .compatible = "allwinner,sun8i-a23-rsb" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, sunxi_rsb_of_match_table); -+ - static struct platform_driver sunxi_rsb_driver = { - .probe = sunxi_rsb_probe, - .remove = sunxi_rsb_remove, diff --git a/projects/Allwinner/patches/linux/crust/0031-bus-sunxi-rsb-Split-out-controller-init-exit-functio.patch b/projects/Allwinner/patches/linux/crust/0031-bus-sunxi-rsb-Split-out-controller-init-exit-functio.patch deleted file mode 100644 index 8249d68a94..0000000000 --- a/projects/Allwinner/patches/linux/crust/0031-bus-sunxi-rsb-Split-out-controller-init-exit-functio.patch +++ /dev/null @@ -1,210 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Mon, 30 Dec 2019 22:36:04 -0600 -Subject: [PATCH] bus: sunxi-rsb: Split out controller init/exit functions - -This separates the resource acquisition from the hardware initialization -phase, so the hardware initialization can be repeated after system -suspend/resume. The same is done for the exit/remove function, except -that there is no resource deallocation phase due to the use of devres. - -The requested RSB clock frequency is stored in `struct sunxi_rsb` so it -will be available when reinitializing the hardware. - -Signed-off-by: Samuel Holland ---- - drivers/bus/sunxi-rsb.c | 127 ++++++++++++++++++++++------------------ - 1 file changed, 71 insertions(+), 56 deletions(-) - ---- a/drivers/bus/sunxi-rsb.c -+++ b/drivers/bus/sunxi-rsb.c -@@ -126,6 +126,7 @@ struct sunxi_rsb { - struct completion complete; - struct mutex lock; - unsigned int status; -+ u32 clk_freq; - }; - - /* bus / slave device related functions */ -@@ -614,16 +615,74 @@ static int of_rsb_register_devices(struc - return 0; - } - -+static int sunxi_rsb_hw_init(struct sunxi_rsb *rsb) -+{ -+ struct device *dev = rsb->dev; -+ unsigned long p_clk_freq; -+ u32 clk_delay, reg; -+ int clk_div, ret; -+ -+ ret = clk_prepare_enable(rsb->clk); -+ if (ret) { -+ dev_err(dev, "failed to enable clk: %d\n", ret); -+ return ret; -+ } -+ -+ ret = reset_control_deassert(rsb->rstc); -+ if (ret) { -+ dev_err(dev, "failed to deassert reset line: %d\n", ret); -+ goto err_clk_disable; -+ } -+ -+ /* reset the controller */ -+ writel(RSB_CTRL_SOFT_RST, rsb->regs + RSB_CTRL); -+ readl_poll_timeout(rsb->regs + RSB_CTRL, reg, -+ !(reg & RSB_CTRL_SOFT_RST), 1000, 100000); -+ -+ /* -+ * Clock frequency and delay calculation code is from -+ * Allwinner U-boot sources. -+ * -+ * From A83 user manual: -+ * bus clock frequency = parent clock frequency / (2 * (divider + 1)) -+ */ -+ p_clk_freq = clk_get_rate(rsb->clk); -+ clk_div = p_clk_freq / rsb->clk_freq / 2; -+ if (!clk_div) -+ clk_div = 1; -+ else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1) -+ clk_div = RSB_CCR_MAX_CLK_DIV + 1; -+ -+ clk_delay = clk_div >> 1; -+ if (!clk_delay) -+ clk_delay = 1; -+ -+ dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2); -+ writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1), -+ rsb->regs + RSB_CCR); -+ -+ return 0; -+ -+err_clk_disable: -+ clk_disable_unprepare(rsb->clk); -+ -+ return ret; -+} -+ -+static void sunxi_rsb_hw_exit(struct sunxi_rsb *rsb) -+{ -+ reset_control_assert(rsb->rstc); -+ clk_disable_unprepare(rsb->clk); -+} -+ - static int sunxi_rsb_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct resource *r; - struct sunxi_rsb *rsb; -- unsigned long p_clk_freq; -- u32 clk_delay, clk_freq = 3000000; -- int clk_div, irq, ret; -- u32 reg; -+ u32 clk_freq = 3000000; -+ int irq, ret; - - of_property_read_u32(np, "clock-frequency", &clk_freq); - if (clk_freq > RSB_MAX_FREQ) { -@@ -638,6 +697,7 @@ static int sunxi_rsb_probe(struct platfo - return -ENOMEM; - - rsb->dev = dev; -+ rsb->clk_freq = clk_freq; - platform_set_drvdata(pdev, rsb); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rsb->regs = devm_ioremap_resource(dev, r); -@@ -655,63 +715,27 @@ static int sunxi_rsb_probe(struct platfo - return ret; - } - -- ret = clk_prepare_enable(rsb->clk); -- if (ret) { -- dev_err(dev, "failed to enable clk: %d\n", ret); -- return ret; -- } -- -- p_clk_freq = clk_get_rate(rsb->clk); -- - rsb->rstc = devm_reset_control_get(dev, NULL); - if (IS_ERR(rsb->rstc)) { - ret = PTR_ERR(rsb->rstc); - dev_err(dev, "failed to retrieve reset controller: %d\n", ret); -- goto err_clk_disable; -- } -- -- ret = reset_control_deassert(rsb->rstc); -- if (ret) { -- dev_err(dev, "failed to deassert reset line: %d\n", ret); -- goto err_clk_disable; -+ return ret; - } - - init_completion(&rsb->complete); - mutex_init(&rsb->lock); - -- /* reset the controller */ -- writel(RSB_CTRL_SOFT_RST, rsb->regs + RSB_CTRL); -- readl_poll_timeout(rsb->regs + RSB_CTRL, reg, -- !(reg & RSB_CTRL_SOFT_RST), 1000, 100000); -- -- /* -- * Clock frequency and delay calculation code is from -- * Allwinner U-boot sources. -- * -- * From A83 user manual: -- * bus clock frequency = parent clock frequency / (2 * (divider + 1)) -- */ -- clk_div = p_clk_freq / clk_freq / 2; -- if (!clk_div) -- clk_div = 1; -- else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1) -- clk_div = RSB_CCR_MAX_CLK_DIV + 1; -- -- clk_delay = clk_div >> 1; -- if (!clk_delay) -- clk_delay = 1; -- -- dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2); -- writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1), -- rsb->regs + RSB_CCR); -- - ret = devm_request_irq(dev, irq, sunxi_rsb_irq, 0, RSB_CTRL_NAME, rsb); - if (ret) { - dev_err(dev, "can't register interrupt handler irq %d: %d\n", - irq, ret); -- goto err_reset_assert; -+ return ret; - } - -+ ret = sunxi_rsb_hw_init(rsb); -+ if (ret) -+ return ret; -+ - /* initialize all devices on the bus into RSB mode */ - ret = sunxi_rsb_init_device_mode(rsb); - if (ret) -@@ -720,14 +744,6 @@ static int sunxi_rsb_probe(struct platfo - of_rsb_register_devices(rsb); - - return 0; -- --err_reset_assert: -- reset_control_assert(rsb->rstc); -- --err_clk_disable: -- clk_disable_unprepare(rsb->clk); -- -- return ret; - } - - static int sunxi_rsb_remove(struct platform_device *pdev) -@@ -735,8 +751,7 @@ static int sunxi_rsb_remove(struct platf - struct sunxi_rsb *rsb = platform_get_drvdata(pdev); - - device_for_each_child(rsb->dev, NULL, sunxi_rsb_remove_devices); -- reset_control_assert(rsb->rstc); -- clk_disable_unprepare(rsb->clk); -+ sunxi_rsb_hw_exit(rsb); - - return 0; - } diff --git a/projects/Allwinner/patches/linux/crust/0032-bus-sunxi-rsb-Implement-suspend-resume-shutdown-call.patch b/projects/Allwinner/patches/linux/crust/0032-bus-sunxi-rsb-Implement-suspend-resume-shutdown-call.patch deleted file mode 100644 index 30546622a4..0000000000 --- a/projects/Allwinner/patches/linux/crust/0032-bus-sunxi-rsb-Implement-suspend-resume-shutdown-call.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Mon, 30 Dec 2019 22:50:02 -0600 -Subject: [PATCH] bus: sunxi-rsb: Implement suspend/resume/shutdown callbacks - -Since system firmware is likely to use the RSB bus to communicate with a -PMIC while the system is suspended, we cannot make any assumptions about -the controller state after resuming. Thus it is important to completely -reinitialize the controller. - -The RSB bus needs to be ready as soon as IRQs are enabled, to handle -wakeup event IRQs coming from the PMIC. Thus it uses NOIRQ callbacks. - -Signed-off-by: Samuel Holland ---- - drivers/bus/sunxi-rsb.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/drivers/bus/sunxi-rsb.c -+++ b/drivers/bus/sunxi-rsb.c -@@ -45,6 +45,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -675,6 +676,22 @@ static void sunxi_rsb_hw_exit(struct sun - clk_disable_unprepare(rsb->clk); - } - -+static int __maybe_unused sunxi_rsb_suspend(struct device *dev) -+{ -+ struct sunxi_rsb *rsb = dev_get_drvdata(dev); -+ -+ sunxi_rsb_hw_exit(rsb); -+ -+ return 0; -+} -+ -+static int __maybe_unused sunxi_rsb_resume(struct device *dev) -+{ -+ struct sunxi_rsb *rsb = dev_get_drvdata(dev); -+ -+ return sunxi_rsb_hw_init(rsb); -+} -+ - static int sunxi_rsb_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -756,6 +773,17 @@ static int sunxi_rsb_remove(struct platf - return 0; - } - -+static void sunxi_rsb_shutdown(struct platform_device *pdev) -+{ -+ struct sunxi_rsb *rsb = platform_get_drvdata(pdev); -+ -+ sunxi_rsb_hw_exit(rsb); -+} -+ -+static const struct dev_pm_ops sunxi_rsb_dev_pm_ops = { -+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sunxi_rsb_suspend, sunxi_rsb_resume) -+}; -+ - static const struct of_device_id sunxi_rsb_of_match_table[] = { - { .compatible = "allwinner,sun8i-a23-rsb" }, - {} -@@ -765,9 +793,11 @@ MODULE_DEVICE_TABLE(of, sunxi_rsb_of_mat - static struct platform_driver sunxi_rsb_driver = { - .probe = sunxi_rsb_probe, - .remove = sunxi_rsb_remove, -+ .shutdown = sunxi_rsb_shutdown, - .driver = { - .name = RSB_CTRL_NAME, - .of_match_table = sunxi_rsb_of_match_table, -+ .pm = &sunxi_rsb_dev_pm_ops, - }, - }; - diff --git a/projects/Allwinner/patches/linux/crust/0033-bus-sunxi-rsb-Implement-runtime-power-management.patch b/projects/Allwinner/patches/linux/crust/0033-bus-sunxi-rsb-Implement-runtime-power-management.patch deleted file mode 100644 index 44e9faad68..0000000000 --- a/projects/Allwinner/patches/linux/crust/0033-bus-sunxi-rsb-Implement-runtime-power-management.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 1 Jan 2020 00:10:40 -0600 -Subject: [PATCH] bus: sunxi-rsb: Implement runtime power management - -Gate the clock to save power while the controller is idle. - -Signed-off-by: Samuel Holland ---- - drivers/bus/sunxi-rsb.c | 44 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 44 insertions(+) - ---- a/drivers/bus/sunxi-rsb.c -+++ b/drivers/bus/sunxi-rsb.c -@@ -46,6 +46,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -337,6 +338,10 @@ static int sunxi_rsb_read(struct sunxi_r - return -EINVAL; - } - -+ ret = pm_runtime_resume_and_get(rsb->dev); -+ if (ret) -+ return ret; -+ - mutex_lock(&rsb->lock); - - writel(addr, rsb->regs + RSB_ADDR); -@@ -352,6 +357,9 @@ static int sunxi_rsb_read(struct sunxi_r - unlock: - mutex_unlock(&rsb->lock); - -+ pm_runtime_mark_last_busy(rsb->dev); -+ pm_runtime_put_autosuspend(rsb->dev); -+ - return ret; - } - -@@ -379,6 +387,10 @@ static int sunxi_rsb_write(struct sunxi_ - return -EINVAL; - } - -+ ret = pm_runtime_resume_and_get(rsb->dev); -+ if (ret) -+ return ret; -+ - mutex_lock(&rsb->lock); - - writel(addr, rsb->regs + RSB_ADDR); -@@ -389,6 +401,9 @@ static int sunxi_rsb_write(struct sunxi_ - - mutex_unlock(&rsb->lock); - -+ pm_runtime_mark_last_busy(rsb->dev); -+ pm_runtime_put_autosuspend(rsb->dev); -+ - return ret; - } - -@@ -672,10 +687,29 @@ err_clk_disable: - - static void sunxi_rsb_hw_exit(struct sunxi_rsb *rsb) - { -+ /* Keep the clock and PM reference counts consistent. */ -+ if (pm_runtime_status_suspended(rsb->dev)) -+ pm_runtime_resume(rsb->dev); - reset_control_assert(rsb->rstc); - clk_disable_unprepare(rsb->clk); - } - -+static int __maybe_unused sunxi_rsb_runtime_suspend(struct device *dev) -+{ -+ struct sunxi_rsb *rsb = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(rsb->clk); -+ -+ return 0; -+} -+ -+static int __maybe_unused sunxi_rsb_runtime_resume(struct device *dev) -+{ -+ struct sunxi_rsb *rsb = dev_get_drvdata(dev); -+ -+ return clk_prepare_enable(rsb->clk); -+} -+ - static int __maybe_unused sunxi_rsb_suspend(struct device *dev) - { - struct sunxi_rsb *rsb = dev_get_drvdata(dev); -@@ -758,6 +792,12 @@ static int sunxi_rsb_probe(struct platfo - if (ret) - dev_warn(dev, "Initialize device mode failed: %d\n", ret); - -+ pm_suspend_ignore_children(dev, true); -+ pm_runtime_set_active(dev); -+ pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); -+ pm_runtime_use_autosuspend(dev); -+ pm_runtime_enable(dev); -+ - of_rsb_register_devices(rsb); - - return 0; -@@ -768,6 +808,7 @@ static int sunxi_rsb_remove(struct platf - struct sunxi_rsb *rsb = platform_get_drvdata(pdev); - - device_for_each_child(rsb->dev, NULL, sunxi_rsb_remove_devices); -+ pm_runtime_disable(&pdev->dev); - sunxi_rsb_hw_exit(rsb); - - return 0; -@@ -777,10 +818,13 @@ static void sunxi_rsb_shutdown(struct pl - { - struct sunxi_rsb *rsb = platform_get_drvdata(pdev); - -+ pm_runtime_disable(&pdev->dev); - sunxi_rsb_hw_exit(rsb); - } - - static const struct dev_pm_ops sunxi_rsb_dev_pm_ops = { -+ SET_RUNTIME_PM_OPS(sunxi_rsb_runtime_suspend, -+ sunxi_rsb_runtime_resume, NULL) - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sunxi_rsb_suspend, sunxi_rsb_resume) - }; - From 0404b23ae18709bcfd910428bfc76ddc1482d34b Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 20 Aug 2021 21:37:06 +0200 Subject: [PATCH 39/51] linux (Allwinner): update patches for 5.14 --- ...01-HACK-SW-CEC-implementation-for-H3.patch | 24 +- ...001-ARM-dts-sun8i-r40-Add-timer-node.patch | 35 --- projects/Allwinner/linux/linux.aarch64.conf | 240 ++++++++++++++++-- projects/Allwinner/linux/linux.arm.conf | 76 ++++-- ...64-dts-allwinner-a64-Protect-SCP-clo.patch | 4 +- ...64-dts-allwinner-h6-Protect-SCP-cloc.patch | 2 +- ...i-Support-unidirectional-mailbox-cha.patch | 6 +- ...-dts-allwinner-a64-Add-SCPI-protocol.patch | 6 +- ...media-hevc-Add-segment-address-field.patch | 45 ++++ ...uapi-hevc-Add-scaling-matrix-control.patch | 85 ------- ...edia-hevc-Add-scaling-matrix-control.patch | 180 +++++++++++++ ...evc-Add-support-for-multiple-slices.patch} | 26 +- ...-uapi-hevc-Add-segment-address-field.patch | 36 --- ...-hevc-Add-support-for-scaling-lists.patch} | 30 ++- .../0018-media-cedrus-hevc-tiles-hack.patch | 14 +- ...drus-Add-callback-for-buffer-cleanup.patch | 6 +- ...edrus-hevc-Improve-buffer-management.patch | 24 +- ...edrus-h264-Improve-buffer-management.patch | 2 +- .../linux/0022-WIp-10-bit-HEVC-support.patch | 6 +- ...-check-for-H264-and-HEVC-limitations.patch | 6 +- .../0028-mfd-Add-support-for-AC200.patch | 2 +- .../linux/0033-WIP-I2S-multi-channel.patch | 2 +- ...i-hevc-add-fields-needed-for-rkvdec.patch} | 42 ++- ...media-uapi-hevc-tiles-and-num_slices.patch | 32 +++ .../0039-HACK-a64-Add-HDMI-sound-card.patch} | 6 +- ...media-uapi-hevc-tiles-and-num_slices.patch | 40 --- .../0040-a64-increase-mali-frequency.patch} | 2 +- .../linux/0041-bpi-m2u-analog-codec.patch} | 2 +- .../linux/0042-r40-hdmi-audio-wip.patch} | 4 +- .../0043-HACK-h6-Add-HDMI-sound-card.patch} | 4 +- ...Use-devm_regulator_get-for-PHY-regu.patch} | 0 ...Rename-PHY-regulator-variable-to-re.patch} | 0 ...Add-support-for-enabling-a-regulato.patch} | 0 ...lwinner-orange-pi-3-Enable-ethernet.patch} | 0 ...dts-h6-enable-USB3-port-on-Pine-H64.patch} | 0 ...ner-h6-Add-AC200-EPHY-related-nodes.patch} | 10 +- ...-allwinner-h6-tanix-tx6-enable-emmc.patch} | 0 ...winner-h6-tanix-tx6-enable-ethernet.patch} | 0 ...r-h6-Enable-USB3-for-OrangePi-Lite2.patch} | 0 ...suable-eMMC-on-some-H6-boards-by-di.patch} | 0 ...er-h6-tanix-tx6-add-bt-enable-rtw88.patch} | 0 41 files changed, 632 insertions(+), 367 deletions(-) delete mode 100644 projects/Allwinner/devices/R40/patches/linux/0001-ARM-dts-sun8i-r40-Add-timer-node.patch create mode 100644 projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch delete mode 100644 projects/Allwinner/patches/linux/0014-media-uapi-hevc-Add-scaling-matrix-control.patch create mode 100644 projects/Allwinner/patches/linux/0015-media-hevc-Add-scaling-matrix-control.patch rename projects/Allwinner/patches/linux/{0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch => 0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch} (80%) delete mode 100644 projects/Allwinner/patches/linux/0016-media-uapi-hevc-Add-segment-address-field.patch rename projects/Allwinner/patches/linux/{0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch => 0017-media-cedrus-hevc-Add-support-for-scaling-lists.patch} (85%) rename projects/Allwinner/patches/linux/{0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch => 0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch} (58%) create mode 100644 projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch rename projects/Allwinner/{devices/A64/patches/linux/0001-HACK-a64-Add-HDMI-sound-card.patch => patches/linux/0039-HACK-a64-Add-HDMI-sound-card.patch} (95%) delete mode 100644 projects/Allwinner/patches/linux/0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch rename projects/Allwinner/{devices/A64/patches/linux/0002-a64-increase-mali-frequency.patch => patches/linux/0040-a64-increase-mali-frequency.patch} (97%) rename projects/Allwinner/{devices/R40/patches/linux/0002-bpi-m2u-analog-codec.patch => patches/linux/0041-bpi-m2u-analog-codec.patch} (98%) rename projects/Allwinner/{devices/R40/patches/linux/0003-r40-hdmi-audio-wip.patch => patches/linux/0042-r40-hdmi-audio-wip.patch} (97%) rename projects/Allwinner/{devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch => patches/linux/0043-HACK-h6-Add-HDMI-sound-card.patch} (97%) rename projects/Allwinner/{devices/H6/patches/linux/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch => patches/linux/0044-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch => patches/linux/0045-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch => patches/linux/0046-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0005-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch => patches/linux/0047-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0006-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch => patches/linux/0048-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch => patches/linux/0049-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch} (95%) rename projects/Allwinner/{devices/H6/patches/linux/0008-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch => patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0009-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch => patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0010-arm64-allwinner-h6-Enable-USB3-for-OrangePi-Lite2.patch => patches/linux/0052-arm64-allwinner-h6-Enable-USB3-for-OrangePi-Lite2.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch => patches/linux/0053-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch} (100%) rename projects/Allwinner/{devices/H6/patches/linux/0020-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch => patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch} (100%) diff --git a/projects/Allwinner/devices/H3/patches/linux/0001-HACK-SW-CEC-implementation-for-H3.patch b/projects/Allwinner/devices/H3/patches/linux/0001-HACK-SW-CEC-implementation-for-H3.patch index ddfc795040..4677aba5c0 100644 --- a/projects/Allwinner/devices/H3/patches/linux/0001-HACK-SW-CEC-implementation-for-H3.patch +++ b/projects/Allwinner/devices/H3/patches/linux/0001-HACK-SW-CEC-implementation-for-H3.patch @@ -16,17 +16,6 @@ Signed-off-by: Jernej Skrabec include/drm/bridge/dw_hdmi.h | 2 + 5 files changed, 89 insertions(+), 3 deletions(-) ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -3421,7 +3421,7 @@ struct dw_hdmi *dw_hdmi_probe(struct pla - hdmi->audio = platform_device_register_full(&pdevinfo); - } - -- if (config0 & HDMI_CONFIG0_CEC) { -+ if (!plat_data->is_cec_unusable && (config0 & HDMI_CONFIG0_CEC)) { - cec.hdmi = hdmi; - cec.ops = &dw_hdmi_cec_ops; - cec.irq = irq; --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -56,6 +56,8 @@ config DRM_SUN8I_DW_HDMI @@ -98,7 +87,7 @@ Signed-off-by: Jernej Skrabec plat_data->cur_ctr = variant->cur_ctr; plat_data->phy_config = variant->phy_cfg; } -+ plat_data->is_cec_unusable = phy->variant->bit_bang_cec; ++ plat_data->disable_cec = phy->variant->bit_bang_cec; } +static int sun8i_hdmi_phy_cec_pin_read(struct cec_adapter *adap) @@ -197,14 +186,3 @@ Signed-off-by: Jernej Skrabec clk_disable_unprepare(phy->clk_mod); clk_disable_unprepare(phy->clk_bus); clk_disable_unprepare(phy->clk_phy); ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -153,6 +153,8 @@ struct dw_hdmi_plat_data { - const struct dw_hdmi_phy_config *phy_config; - int (*configure_phy)(struct dw_hdmi *hdmi, void *data, - unsigned long mpixelclock); -+ -+ unsigned int is_cec_unusable : 1; - }; - - struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, diff --git a/projects/Allwinner/devices/R40/patches/linux/0001-ARM-dts-sun8i-r40-Add-timer-node.patch b/projects/Allwinner/devices/R40/patches/linux/0001-ARM-dts-sun8i-r40-Add-timer-node.patch deleted file mode 100644 index 58fd3e7398..0000000000 --- a/projects/Allwinner/devices/R40/patches/linux/0001-ARM-dts-sun8i-r40-Add-timer-node.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 8e2b67acc77a0c7704b2001dd4bf8646f286e4be Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 16 Jan 2021 13:09:00 +0100 -Subject: [PATCH] ARM: dts: sun8i: r40: Add timer node - -Allwinner R40 has a timer. - -Add a node for it. - -Signed-off-by: Jernej Skrabec ---- - arch/arm/boot/dts/sun8i-r40.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm/boot/dts/sun8i-r40.dtsi -+++ b/arch/arm/boot/dts/sun8i-r40.dtsi -@@ -647,6 +647,18 @@ - }; - }; - -+ timer@1c20c00 { -+ compatible = "allwinner,sun4i-a10-timer"; -+ reg = <0x01c20c00 0x90>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ ; -+ clocks = <&osc24M>; -+ }; -+ - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index c2d05e73c1..2db57a611c 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.13.0 Kernel Configuration +# Linux/arm64 5.14.0-rc6 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103" CONFIG_CC_IS_GCC=y @@ -15,6 +15,7 @@ CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -210,9 +211,10 @@ CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_EXPERT is not set +CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y @@ -240,8 +242,10 @@ CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set # # Kernel Performance Events And Counters @@ -255,6 +259,7 @@ CONFIG_SLUB_DEBUG=y # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y +# CONFIG_SLOB is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set @@ -284,8 +289,6 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_ZONE_DMA32=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y @@ -399,7 +402,6 @@ CONFIG_NODES_SHIFT=2 CONFIG_USE_PERCPU_NUMA_NODE_ID=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_HOLES_IN_ZONE=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set @@ -448,6 +450,7 @@ CONFIG_ARM64_CNP=y # ARMv8.3 architectural features # CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_PAC=y @@ -504,6 +507,7 @@ CONFIG_SYSVIPC_COMPAT=y # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_HIBERNATION_SNAPSHOT_DEV=y @@ -585,6 +589,8 @@ CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_ARM_FFA_TRANSPORT is not set # CONFIG_GOOGLE_FIRMWARE is not set CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set @@ -642,6 +648,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y @@ -704,7 +711,6 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # @@ -733,6 +739,7 @@ CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y @@ -748,6 +755,7 @@ CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_WBT is not set CONFIG_BLK_CGROUP_IOLATENCY=y # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -804,7 +812,6 @@ CONFIG_COREDUMP=y # Memory Management options # CONFIG_SPARSEMEM=y -CONFIG_NEED_MULTIPLE_NODES=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -839,18 +846,21 @@ CONFIG_CMA_DEBUGFS=y CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y # end of Memory Management options CONFIG_NET=y @@ -1357,6 +1367,7 @@ CONFIG_WEXT_PRIV=y CONFIG_CFG80211=m # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y CONFIG_CFG80211_DEFAULT_PS=y @@ -1513,6 +1524,7 @@ CONFIG_MTD_CFI_I2=y # # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -1885,7 +1897,7 @@ CONFIG_AC200_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -1901,10 +1913,12 @@ CONFIG_AC200_PHY=y CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set @@ -1926,6 +1940,7 @@ CONFIG_SMSC_PHY=m # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_SUN4I is not set @@ -2113,7 +2128,13 @@ CONFIG_ZD1211RW=m CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set # CONFIG_WAN is not set + +# +# Wireless WAN +# # CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set @@ -2199,6 +2220,7 @@ CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y @@ -2411,6 +2433,7 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set # CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_IPMB_DEVICE_INTERFACE is not set @@ -2420,7 +2443,6 @@ CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y -# CONFIG_RAW_DRIVER is not set CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set @@ -2433,6 +2455,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_ST33ZP24_I2C is not set # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices # CONFIG_RANDOM_TRUST_CPU is not set @@ -2760,6 +2783,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set @@ -2875,6 +2899,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set @@ -2942,6 +2967,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -3033,6 +3059,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set CONFIG_MFD_RK808=y @@ -3084,6 +3111,7 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set CONFIG_MFD_VEXPRESS_SYSREG=y # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set @@ -3118,6 +3146,7 @@ CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -3137,6 +3166,8 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y @@ -3229,6 +3260,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_TUNER=m CONFIG_V4L2_MEM2MEM_DEV=y CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m # end of Video4Linux options @@ -3262,7 +3294,6 @@ CONFIG_DVB_MAX_ADAPTERS=16 # # Drivers filtered as selected at 'Filter media drivers' # -CONFIG_TTPCI_EEPROM=m CONFIG_MEDIA_USB_SUPPORT=y # @@ -3392,6 +3423,7 @@ CONFIG_MEDIA_COMMON_OPTIONS=y # CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=y CONFIG_VIDEOBUF2_V4L2=y @@ -3415,8 +3447,6 @@ CONFIG_DVB_PLATFORM_DRIVERS=y # CONFIG_SMS_SDIO_DRV is not set # end of Media drivers -CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y - # # Media ancillary drivers # @@ -3428,28 +3458,116 @@ CONFIG_MEDIA_ATTACH=y CONFIG_VIDEO_IR_I2C=y # -# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers' +# Audio decoders, processors and mixers # +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_TLV320AIC23B=m CONFIG_VIDEO_UDA1342=m CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_VP27SMPX=m CONFIG_VIDEO_SONY_BTF_MPX=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +CONFIG_VIDEO_SAA6588=m +# end of RDS decoders + +# +# Video decoders +# +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TVP514X=m CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m CONFIG_VIDEO_TW2804=m CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m +CONFIG_VIDEO_MAX9286=m # # Video and audio decoders # +CONFIG_VIDEO_SAA717X=m CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_ADV7511=m +CONFIG_VIDEO_ADV7511_CEC=y +CONFIG_VIDEO_AD9389B=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_THS8200=m +# end of Video encoders + +# +# Video improvement chips +# +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +# end of Video improvement chips + +# +# Audio/Video compression chips +# +CONFIG_VIDEO_SAA6752HS=m +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +CONFIG_VIDEO_THS7303=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_I2C=m +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips # # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set @@ -3525,8 +3643,10 @@ CONFIG_VIDEO_MT9V011=m # end of Flash devices # -# SPI I2C drivers auto-selected by 'Autoselect ancillary drivers' +# SPI helper chips # +CONFIG_VIDEO_GS1662=m +# end of SPI helper chips # # Media SPI Adapters @@ -3537,7 +3657,7 @@ CONFIG_CXD2880_SPI_DRV=m CONFIG_MEDIA_TUNER=y # -# Tuner drivers auto-selected by 'Autoselect ancillary drivers' +# Customize TV tuners # CONFIG_MEDIA_TUNER_SIMPLE=y CONFIG_MEDIA_TUNER_TDA18250=m @@ -3547,10 +3667,12 @@ CONFIG_MEDIA_TUNER_TDA18271=y CONFIG_MEDIA_TUNER_TDA9887=y CONFIG_MEDIA_TUNER_TEA5761=y CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MSI001=m CONFIG_MEDIA_TUNER_MT20XX=y CONFIG_MEDIA_TUNER_MT2060=m CONFIG_MEDIA_TUNER_MT2063=m CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m CONFIG_MEDIA_TUNER_QT1010=m CONFIG_MEDIA_TUNER_XC2028=y CONFIG_MEDIA_TUNER_XC5000=y @@ -3566,14 +3688,18 @@ CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_TDA18212=m CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_M88RS6000T=m CONFIG_MEDIA_TUNER_TUA9001=m CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_TUNER_IT913X=m CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_MXL301RF=m CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +# end of Customize TV tuners # -# DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers' +# Customise DVB Frontends # # @@ -3582,7 +3708,10 @@ CONFIG_MEDIA_TUNER_QM1D1C0042=m CONFIG_DVB_STB0899=m CONFIG_DVB_STB6100=m CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_MXL5XX=m CONFIG_DVB_M88DS3103=m # @@ -3597,8 +3726,10 @@ CONFIG_DVB_MN88473=m # # DVB-S (satellite) frontends # +CONFIG_DVB_CX24110=m CONFIG_DVB_CX24123=m CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m CONFIG_DVB_ZL10039=m CONFIG_DVB_S5H1420=m CONFIG_DVB_STV0288=m @@ -3606,22 +3737,32 @@ CONFIG_DVB_STB6000=m CONFIG_DVB_STV0299=m CONFIG_DVB_STV6110=m CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m CONFIG_DVB_TUNER_ITD1000=m CONFIG_DVB_TUNER_CX24113=m CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m CONFIG_DVB_CX24120=m CONFIG_DVB_SI21XX=m CONFIG_DVB_TS2020=m CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m CONFIG_DVB_TDA10071=m # # DVB-T (terrestrial) frontends # +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m +CONFIG_DVB_S5H1432=m CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m CONFIG_DVB_TDA1004X=m CONFIG_DVB_NXT6000=m CONFIG_DVB_MT352=m @@ -3630,9 +3771,11 @@ CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m CONFIG_DVB_TDA10048=m CONFIG_DVB_AF9013=m CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_CXD2841ER=m CONFIG_DVB_RTL2830=m @@ -3641,10 +3784,13 @@ CONFIG_DVB_SI2168=m CONFIG_DVB_AS102_FE=m CONFIG_DVB_ZD1301_DEMOD=m CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_CXD2880=m # # DVB-C (cable) frontends # +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m CONFIG_DVB_TDA10023=m CONFIG_DVB_STV0297=m @@ -3652,6 +3798,8 @@ CONFIG_DVB_STV0297=m # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_LGDT3305=m @@ -3675,6 +3823,7 @@ CONFIG_DVB_MB86A20S=m # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # CONFIG_DVB_TC90522=m +CONFIG_DVB_MN88443X=m # # Digital terrestrial only tuners/PLL @@ -3687,21 +3836,31 @@ CONFIG_DVB_TUNER_DIB0090=m # SEC control devices for DVB-S # CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m CONFIG_DVB_ISL6421=m CONFIG_DVB_ISL6423=m CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GL5=m CONFIG_DVB_LGS8GXX=m CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m CONFIG_DVB_IX2505V=m CONFIG_DVB_M88RS2000=m CONFIG_DVB_AF9033=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_HELENE=m # # Common Interface (EN50221) controller drivers # +CONFIG_DVB_CXD2099=m CONFIG_DVB_SP2=m +# end of Customise DVB Frontends # end of Media ancillary drivers # @@ -3712,9 +3871,10 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y @@ -3792,6 +3952,7 @@ CONFIG_DRM_DISPLAY_CONNECTOR=y # CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set # CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3809,6 +3970,7 @@ CONFIG_DRM_SIMPLE_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set CONFIG_DRM_ANALOGIX_ANX6345=m @@ -3828,6 +3990,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_MXSFB is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -4107,14 +4270,17 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RK817 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set # CONFIG_SND_SOC_SIMPLE_MUX is not set # CONFIG_SND_SOC_SPDIF is not set # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -4131,6 +4297,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4167,7 +4334,6 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set @@ -4944,9 +5110,18 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# CONFIG_CLK_VEXPRESS_OSC is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX77686 is not set # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_RK808 is not set @@ -4979,12 +5154,15 @@ CONFIG_SUN8I_DE2_CCU=y CONFIG_SUN8I_R_CCU=y # CONFIG_XILINX_VCU is not set CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_SUN6I=y # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_SUN4I_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y @@ -5156,6 +5334,8 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -5169,6 +5349,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -5232,6 +5413,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -5266,7 +5448,8 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5409,6 +5592,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5450,6 +5634,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5581,6 +5766,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5609,8 +5795,7 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set @@ -5620,6 +5805,7 @@ CONFIG_RESET_SUNXI=y # CONFIG_GENERIC_PHY=y CONFIG_PHY_XGENE=y +# CONFIG_PHY_CAN_TRANSCEIVER is not set CONFIG_PHY_SUN4I_USB=y # CONFIG_PHY_SUN6I_MIPI_DPHY is not set # CONFIG_PHY_SUN9I_USB is not set @@ -5871,7 +6057,6 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" # CONFIG_PSTORE_CONSOLE is not set # CONFIG_PSTORE_PMSG is not set # CONFIG_PSTORE_RAM is not set -# CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set @@ -6352,7 +6537,6 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y @@ -6366,6 +6550,7 @@ CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6395,8 +6580,10 @@ CONFIG_FRAME_WARN=2048 # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -6566,7 +6753,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set @@ -6577,10 +6763,12 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index e97659544e..4c20a3f954 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.13.0 Kernel Configuration +# Linux/arm 5.14.0-rc6 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0" +CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=100200 +CONFIG_GCC_VERSION=100300 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23501 @@ -15,6 +15,7 @@ CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y @@ -719,6 +720,7 @@ CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_WBT is not set CONFIG_BLK_CGROUP_IOLATENCY=y # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -794,7 +796,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 @@ -814,7 +815,6 @@ CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 # CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set @@ -1691,7 +1691,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -1707,10 +1707,12 @@ CONFIG_FIXED_PHY=y # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_MICROCHIP_T1_PHY=y # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set @@ -1732,6 +1734,7 @@ CONFIG_SMSC_PHY=y CONFIG_MICREL_KS8995MA=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_SUN4I=y @@ -1940,7 +1943,13 @@ CONFIG_ZD1211RW=m CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set # CONFIG_WAN is not set + +# +# Wireless WAN +# # CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set @@ -2026,6 +2035,7 @@ CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2169,9 +2179,9 @@ CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y -# CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices # CONFIG_RANDOM_TRUST_BOOTLOADER is not set @@ -2472,6 +2482,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set @@ -2586,6 +2597,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set @@ -2651,6 +2663,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -2751,6 +2764,7 @@ CONFIG_MFD_AXP20X_RSB=y # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set @@ -2805,6 +2819,7 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -2835,6 +2850,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -2852,6 +2868,8 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_SLG51000 is not set CONFIG_REGULATOR_SY8106A=y @@ -2945,6 +2963,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_TUNER=m CONFIG_V4L2_MEM2MEM_DEV=y CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m # end of Video4Linux options @@ -2974,7 +2993,6 @@ CONFIG_DVB_MAX_ADAPTERS=16 # # Media drivers # -CONFIG_TTPCI_EEPROM=m CONFIG_MEDIA_USB_SUPPORT=y # @@ -3104,6 +3122,7 @@ CONFIG_MEDIA_COMMON_OPTIONS=y # CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=y CONFIG_VIDEOBUF2_V4L2=y @@ -3251,6 +3270,7 @@ CONFIG_VIDEO_ST_MIPID02=m # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set @@ -3440,7 +3460,6 @@ CONFIG_DVB_TDA10071=m # # DVB-T (terrestrial) frontends # -CONFIG_DVB_SP8870=m CONFIG_DVB_SP887X=m CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m @@ -3563,7 +3582,6 @@ CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 @@ -3646,6 +3664,7 @@ CONFIG_DRM_DISPLAY_CONNECTOR=m # CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set # CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3663,6 +3682,7 @@ CONFIG_DRM_SIMPLE_BRIDGE=m # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set @@ -3681,6 +3701,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_MXSFB is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -3935,12 +3956,14 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set # CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -3957,6 +3980,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -3993,7 +4017,6 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set @@ -4760,9 +4783,17 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set @@ -4933,6 +4964,8 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -4946,6 +4979,7 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -5010,6 +5044,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -5044,7 +5079,8 @@ CONFIG_SUN4I_GPADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5187,6 +5223,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5228,6 +5265,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5352,6 +5390,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5377,8 +5416,7 @@ CONFIG_ARM_GIC_MAX_NR=1 # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set @@ -5388,6 +5426,7 @@ CONFIG_RESET_SUNXI=y # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y +# CONFIG_PHY_CAN_TRANSCEIVER is not set CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN6I_MIPI_DPHY=y CONFIG_PHY_SUN9I_USB=y @@ -6052,7 +6091,6 @@ CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y @@ -6066,6 +6104,7 @@ CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6086,7 +6125,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set # CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -6251,7 +6290,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set @@ -6262,10 +6300,12 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set diff --git a/projects/Allwinner/patches/linux/0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch b/projects/Allwinner/patches/linux/0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch index 60d4395dab..50c228e968 100644 --- a/projects/Allwinner/patches/linux/0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch +++ b/projects/Allwinner/patches/linux/0005-DO-NOT-MERGE-arm64-dts-allwinner-a64-Protect-SCP-clo.patch @@ -10,7 +10,7 @@ Signed-off-by: Samuel Holland --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -641,6 +641,7 @@ +@@ -646,6 +646,7 @@ reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; @@ -18,7 +18,7 @@ Signed-off-by: Samuel Holland #clock-cells = <1>; #reset-cells = <1>; }; -@@ -1233,6 +1234,7 @@ +@@ -1267,6 +1268,7 @@ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; diff --git a/projects/Allwinner/patches/linux/0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch b/projects/Allwinner/patches/linux/0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch index 7a05d092e9..27b526d2c5 100644 --- a/projects/Allwinner/patches/linux/0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch +++ b/projects/Allwinner/patches/linux/0006-DO-NOT-MERGE-arm64-dts-allwinner-h6-Protect-SCP-cloc.patch @@ -18,7 +18,7 @@ Signed-off-by: Samuel Holland #clock-cells = <1>; #reset-cells = <1>; }; -@@ -916,6 +917,7 @@ +@@ -925,6 +926,7 @@ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; diff --git a/projects/Allwinner/patches/linux/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch b/projects/Allwinner/patches/linux/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch index cbf3f66f77..8b79ee9924 100644 --- a/projects/Allwinner/patches/linux/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch +++ b/projects/Allwinner/patches/linux/0009-firmware-arm_scpi-Support-unidirectional-mailbox-cha.patch @@ -54,7 +54,7 @@ Signed-off-by: Samuel Holland } static int scpi_remove(struct platform_device *pdev) -@@ -905,6 +911,7 @@ static int scpi_probe(struct platform_de +@@ -913,6 +919,7 @@ static int scpi_probe(struct platform_de struct resource res; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -62,7 +62,7 @@ Signed-off-by: Samuel Holland scpi_info = devm_kzalloc(dev, sizeof(*scpi_info), GFP_KERNEL); if (!scpi_info) -@@ -918,6 +925,14 @@ static int scpi_probe(struct platform_de +@@ -926,6 +933,14 @@ static int scpi_probe(struct platform_de dev_err(dev, "no mboxes property in '%pOF'\n", np); return -ENODEV; } @@ -77,7 +77,7 @@ Signed-off-by: Samuel Holland scpi_info->channels = devm_kcalloc(dev, count, sizeof(struct scpi_chan), GFP_KERNEL); -@@ -963,15 +978,34 @@ static int scpi_probe(struct platform_de +@@ -974,15 +989,34 @@ static int scpi_probe(struct platform_de mutex_init(&pchan->xfers_lock); ret = scpi_alloc_xfer_list(dev, pchan); diff --git a/projects/Allwinner/patches/linux/0011-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch b/projects/Allwinner/patches/linux/0011-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch index 18f13caa2c..2a4e30b426 100644 --- a/projects/Allwinner/patches/linux/0011-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch +++ b/projects/Allwinner/patches/linux/0011-arm64-dts-allwinner-a64-Add-SCPI-protocol.patch @@ -22,9 +22,9 @@ Signed-off-by: Samuel Holland + }; + sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun50i-a64-audio"; -@@ -339,6 +346,19 @@ + #address-cells = <1>; + #size-cells = <0>; +@@ -344,6 +351,19 @@ #size-cells = <1>; ranges; diff --git a/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch b/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch new file mode 100644 index 0000000000..14f14b8070 --- /dev/null +++ b/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch @@ -0,0 +1,45 @@ +From 229e5bdcd39ed3ca0a71dc8500ba4ea90d4415db Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 6 Jun 2021 10:23:13 +0200 +Subject: [PATCH] media: hevc: Add segment address field + +If HEVC frame consists of multiple slices, segment address has to be +known in order to properly decode it. + +Add segment address field to slice parameters. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 3 +++ + include/media/hevc-ctrls.h | 3 ++- + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst ++++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +@@ -3000,6 +3000,9 @@ enum v4l2_mpeg_video_hevc_size_of_length + * - __u8 + - ``pic_struct`` + - ++ * - __u32 ++ - ``slice_segment_addr`` ++ - + * - __u8 + - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` + - The list of L0 reference elements as indices in the DPB. +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -196,10 +196,11 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 pic_struct; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ ++ __u32 slice_segment_addr; + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + +- __u8 padding[5]; ++ __u8 padding; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; diff --git a/projects/Allwinner/patches/linux/0014-media-uapi-hevc-Add-scaling-matrix-control.patch b/projects/Allwinner/patches/linux/0014-media-uapi-hevc-Add-scaling-matrix-control.patch deleted file mode 100644 index 1acd9d90f6..0000000000 --- a/projects/Allwinner/patches/linux/0014-media-uapi-hevc-Add-scaling-matrix-control.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 82a8ceccbaf9aa3d8cbc56d10e3905eec0d4ffb4 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 13:55:15 +0200 -Subject: [PATCH 23/44] media: uapi: hevc: Add scaling matrix control - -HEVC has a scaling matrix concept. Add support for it. - -Signed-off-by: Jernej Skrabec ---- - drivers/media/v4l2-core/v4l2-ctrls.c | 10 ++++++++++ - include/media/hevc-ctrls.h | 11 +++++++++++ - 2 files changed, 21 insertions(+) - ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1041,6 +1041,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; - case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; - -@@ -1526,6 +1527,9 @@ void v4l2_ctrl_fill(u32 id, const char * - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: -+ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; -+ break; - case V4L2_CID_UNIT_CELL_SIZE: - *type = V4L2_CTRL_TYPE_AREA; - *flags |= V4L2_CTRL_FLAG_READ_ONLY; -@@ -2237,6 +2241,9 @@ static int std_validate_compound(const s - - break; - -+ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: -+ break; -+ - case V4L2_CTRL_TYPE_AREA: - area = p; - if (!area->width || !area->height) -@@ -2953,6 +2960,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(s - case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY: - elem_size = sizeof(struct v4l2_ctrl_hdr10_mastering_display); - break; -+ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: -+ elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); -+ break; - case V4L2_CTRL_TYPE_AREA: - elem_size = sizeof(struct v4l2_area); - break; ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -19,6 +19,7 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) - #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) - #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) - -@@ -26,6 +27,7 @@ - #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 - #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 - #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 -+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 - - enum v4l2_mpeg_video_hevc_decode_mode { - V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -@@ -209,4 +211,13 @@ struct v4l2_ctrl_hevc_slice_params { - __u64 flags; - }; - -+struct v4l2_ctrl_hevc_scaling_matrix { -+ __u8 scaling_list_4x4[6][16]; -+ __u8 scaling_list_8x8[6][64]; -+ __u8 scaling_list_16x16[6][64]; -+ __u8 scaling_list_32x32[2][64]; -+ __u8 scaling_list_dc_coef_16x16[6]; -+ __u8 scaling_list_dc_coef_32x32[2]; -+}; -+ - #endif diff --git a/projects/Allwinner/patches/linux/0015-media-hevc-Add-scaling-matrix-control.patch b/projects/Allwinner/patches/linux/0015-media-hevc-Add-scaling-matrix-control.patch new file mode 100644 index 0000000000..2264fc6b1b --- /dev/null +++ b/projects/Allwinner/patches/linux/0015-media-hevc-Add-scaling-matrix-control.patch @@ -0,0 +1,180 @@ +From 478e8d8b3997e15825c49f6f716faf26e1becaeb Mon Sep 17 00:00:00 2001 +From: Benjamin Gaignard +Date: Thu, 15 Jul 2021 17:12:22 +0200 +Subject: [PATCH] media: hevc: Add scaling matrix control + +HEVC scaling lists are used for the scaling process for transform +coefficients. +V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED has to set when they are +encoded in the bitstream. + +Signed-off-by: Benjamin Gaignard +Reviewed-by: Jernej Skrabec +Reviewed-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../media/v4l/ext-ctrls-codec.rst | 57 +++++++++++++++++++ + .../media/v4l/vidioc-queryctrl.rst | 6 ++ + drivers/media/v4l2-core/v4l2-ctrls-core.c | 6 ++ + drivers/media/v4l2-core/v4l2-ctrls-defs.c | 4 ++ + include/media/hevc-ctrls.h | 11 ++++ + 5 files changed, 84 insertions(+) + +--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst ++++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +@@ -3071,6 +3071,63 @@ enum v4l2_mpeg_video_hevc_size_of_length + + \normalsize + ++``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)`` ++ Specifies the HEVC scaling matrix parameters used for the scaling process ++ for transform coefficients. ++ These matrix and parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.5 "Scaling list data semantics" of ++ the specification. ++ ++.. c:type:: v4l2_ctrl_hevc_scaling_matrix ++ ++.. raw:: latex ++ ++ \scriptsize ++ ++.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}| ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``scaling_list_4x4[6][16]`` ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. ++ * - __u8 ++ - ``scaling_list_8x8[6][64]`` ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. ++ * - __u8 ++ - ``scaling_list_16x16[6][64]`` ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. ++ * - __u8 ++ - ``scaling_list_32x32[2][64]`` ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. ++ * - __u8 ++ - ``scaling_list_dc_coef_16x16[6]`` ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. ++ * - __u8 ++ - ``scaling_list_dc_coef_32x32[2]`` ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. ++ ++.. raw:: latex ++ ++ \normalsize ++ + .. c:type:: v4l2_hevc_dpb_entry + + .. raw:: latex +--- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst ++++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst +@@ -495,6 +495,12 @@ See also the examples in :ref:`control`. + - n/a + - A struct :c:type:`v4l2_ctrl_hevc_slice_params`, containing HEVC + slice parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_hevc_scaling_matrix`, containing HEVC ++ scaling matrix for stateless video decoders. + * - ``V4L2_CTRL_TYPE_VP8_FRAME`` + - n/a + - n/a +--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c +@@ -687,6 +687,9 @@ static int std_validate_compound(const s + + break; + ++ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: ++ break; ++ + case V4L2_CTRL_TYPE_AREA: + area = p; + if (!area->width || !area->height) +@@ -1240,6 +1243,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(s + case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); + break; ++ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: ++ elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); ++ break; + case V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_hevc_decode_params); + break; +--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +@@ -996,6 +996,7 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: return "HEVC Decode Parameters"; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; + case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; +@@ -1488,6 +1489,9 @@ void v4l2_ctrl_fill(u32 id, const char * + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: + *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: ++ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; ++ break; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: + *type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS; + break; +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -19,6 +19,7 @@ + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) + #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) +@@ -27,6 +28,7 @@ + #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 + #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 + #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 ++#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 + #define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124 + + enum v4l2_mpeg_video_hevc_decode_mode { +@@ -225,6 +227,15 @@ struct v4l2_ctrl_hevc_decode_params { + __u64 flags; + }; + ++struct v4l2_ctrl_hevc_scaling_matrix { ++ __u8 scaling_list_4x4[6][16]; ++ __u8 scaling_list_8x8[6][64]; ++ __u8 scaling_list_16x16[6][64]; ++ __u8 scaling_list_32x32[2][64]; ++ __u8 scaling_list_dc_coef_16x16[6]; ++ __u8 scaling_list_dc_coef_32x32[2]; ++}; ++ + /* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */ + #define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) + /* diff --git a/projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch b/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch similarity index 80% rename from projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch rename to projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch index 85b39b62d6..4a2a85f591 100644 --- a/projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-multiple-slices.patch +++ b/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch @@ -1,12 +1,14 @@ -From d99740197a9776b9332d21b9f3b05dab658a90eb Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 15:44:15 +0200 -Subject: [PATCH 26/44] media: cedrus: hevc: Add support for multiple slices +From d92a4a27d983032267b231a32be98a11a9995e5c Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 6 Jun 2021 10:23:14 +0200 +Subject: [PATCH] media: cedrus: hevc: Add support for multiple slices Now that segment address is available, support for multi-slice frames can be easily added. -Signed-off-by: Jernej Skrabec +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab --- .../staging/media/sunxi/cedrus/cedrus_h265.c | 26 ++++++++++++------- .../staging/media/sunxi/cedrus/cedrus_video.c | 1 + @@ -14,17 +16,17 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -309,6 +309,8 @@ static void cedrus_h265_setup(struct ced - const struct v4l2_ctrl_hevc_pps *pps; +@@ -247,6 +247,8 @@ static void cedrus_h265_setup(struct ced const struct v4l2_ctrl_hevc_slice_params *slice_params; + const struct v4l2_ctrl_hevc_decode_params *decode_params; const struct v4l2_hevc_pred_weight_table *pred_weight_table; + unsigned int width_in_ctb_luma, ctb_size_luma; + unsigned int log2_max_luma_coding_block_size; dma_addr_t src_buf_addr; dma_addr_t src_buf_end_addr; u32 chroma_log2_weight_denom; -@@ -321,15 +323,17 @@ static void cedrus_h265_setup(struct ced - slice_params = run->h265.slice_params; +@@ -260,15 +262,17 @@ static void cedrus_h265_setup(struct ced + decode_params = run->h265.decode_params; pred_weight_table = &slice_params->pred_weight_table; + log2_max_luma_coding_block_size = @@ -46,7 +48,7 @@ Signed-off-by: Jernej Skrabec /* * Each CTB requires a MV col buffer with a specific unit size. -@@ -383,15 +387,17 @@ static void cedrus_h265_setup(struct ced +@@ -322,15 +326,17 @@ static void cedrus_h265_setup(struct ced reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); @@ -67,9 +69,9 @@ Signed-off-by: Jernej Skrabec /* Initialize bitstream access. */ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); -@@ -543,8 +549,8 @@ static void cedrus_h265_setup(struct ced +@@ -482,8 +488,8 @@ static void cedrus_h265_setup(struct ced V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT, - pps->flags); + slice_params->flags); - /* FIXME: For multi-slice support. */ - reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; diff --git a/projects/Allwinner/patches/linux/0016-media-uapi-hevc-Add-segment-address-field.patch b/projects/Allwinner/patches/linux/0016-media-uapi-hevc-Add-segment-address-field.patch deleted file mode 100644 index d2632df423..0000000000 --- a/projects/Allwinner/patches/linux/0016-media-uapi-hevc-Add-segment-address-field.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e61cf76fca5984dd9edcb0daf6c5cb5278f32e05 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 15:42:28 +0200 -Subject: [PATCH 25/44] media: uapi: hevc: Add segment address field - -If HEVC frame consists of multiple slices, segment address has to be -known in order to properly decode it. - -Add segment address field to slice parameters. - -Signed-off-by: Jernej Skrabec ---- - include/media/hevc-ctrls.h | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -167,6 +167,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u32 bit_size; - __u32 data_bit_offset; - -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; -+ - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; - __u8 nuh_temporal_id_plus1; -@@ -200,7 +203,7 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; - -- __u8 padding; -+ __u8 padding[5]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; diff --git a/projects/Allwinner/patches/linux/0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch b/projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-scaling-lists.patch similarity index 85% rename from projects/Allwinner/patches/linux/0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch rename to projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-scaling-lists.patch index 2be33c242a..bf9d2c6248 100644 --- a/projects/Allwinner/patches/linux/0015-media-cedrus-hevc-Add-support-for-scaling-matrix.patch +++ b/projects/Allwinner/patches/linux/0017-media-cedrus-hevc-Add-support-for-scaling-lists.patch @@ -1,22 +1,24 @@ -From b4b79b4eeacb63f0a72c866526e4a2021a201090 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 13:58:49 +0200 -Subject: [PATCH 24/44] media: cedrus: hevc: Add support for scaling matrix +From 297289d611b802ecd232df6cab02987f9059c3bc Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 6 Jun 2021 08:50:50 +0200 +Subject: [PATCH] media: cedrus: hevc: Add support for scaling lists HEVC frames may use scaling list feature. Add support for it. -Signed-off-by: Jernej Skrabec +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab --- - drivers/staging/media/sunxi/cedrus/cedrus.c | 7 ++ + drivers/staging/media/sunxi/cedrus/cedrus.c | 6 ++ drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + .../staging/media/sunxi/cedrus/cedrus_dec.c | 2 + .../staging/media/sunxi/cedrus/cedrus_h265.c | 70 ++++++++++++++++++- .../staging/media/sunxi/cedrus/cedrus_regs.h | 2 + - 5 files changed, 81 insertions(+), 1 deletion(-) + 5 files changed, 80 insertions(+), 1 deletion(-) --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -131,6 +131,12 @@ static const struct cedrus_control cedru +@@ -137,6 +137,12 @@ static const struct cedrus_control cedru }, { .cfg = { @@ -31,20 +33,20 @@ Signed-off-by: Jernej Skrabec .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -76,6 +76,7 @@ struct cedrus_h265_run { - const struct v4l2_ctrl_hevc_sps *sps; +@@ -78,6 +78,7 @@ struct cedrus_h265_run { const struct v4l2_ctrl_hevc_pps *pps; const struct v4l2_ctrl_hevc_slice_params *slice_params; + const struct v4l2_ctrl_hevc_decode_params *decode_params; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; }; struct cedrus_vp8_run { --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -68,6 +68,8 @@ void cedrus_device_run(void *priv) - V4L2_CID_MPEG_VIDEO_HEVC_PPS); - run.h265.slice_params = cedrus_find_control_data(ctx, +@@ -72,6 +72,8 @@ void cedrus_device_run(void *priv) V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); + run.h265.decode_params = cedrus_find_control_data(ctx, + V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS); + run.h265.scaling_matrix = cedrus_find_control_data(ctx, + V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX); break; @@ -122,7 +124,7 @@ Signed-off-by: Jernej Skrabec static void cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { -@@ -519,7 +582,12 @@ static void cedrus_h265_setup(struct ced +@@ -527,7 +590,12 @@ static void cedrus_h265_setup(struct ced /* Scaling list. */ diff --git a/projects/Allwinner/patches/linux/0018-media-cedrus-hevc-tiles-hack.patch b/projects/Allwinner/patches/linux/0018-media-cedrus-hevc-tiles-hack.patch index 670f87b6d3..0eb9a0017a 100644 --- a/projects/Allwinner/patches/linux/0018-media-cedrus-hevc-tiles-hack.patch +++ b/projects/Allwinner/patches/linux/0018-media-cedrus-hevc-tiles-hack.patch @@ -12,7 +12,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -142,6 +142,8 @@ struct cedrus_ctx { +@@ -144,6 +144,8 @@ struct cedrus_ctx { ssize_t mv_col_buf_unit_size; void *neighbor_info_buf; dma_addr_t neighbor_info_buf_addr; @@ -85,7 +85,7 @@ Signed-off-by: Jernej Skrabec static void cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { -@@ -311,6 +366,7 @@ static void cedrus_h265_setup(struct ced +@@ -312,6 +367,7 @@ static void cedrus_h265_setup(struct ced const struct v4l2_hevc_pred_weight_table *pred_weight_table; unsigned int width_in_ctb_luma, ctb_size_luma; unsigned int log2_max_luma_coding_block_size; @@ -93,7 +93,7 @@ Signed-off-by: Jernej Skrabec dma_addr_t src_buf_addr; dma_addr_t src_buf_end_addr; u32 chroma_log2_weight_denom; -@@ -388,12 +444,19 @@ static void cedrus_h265_setup(struct ced +@@ -390,12 +446,19 @@ static void cedrus_h265_setup(struct ced cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); /* Coding tree block address */ @@ -117,7 +117,7 @@ Signed-off-by: Jernej Skrabec /* Clear the number of correctly-decoded coding tree blocks. */ if (ctx->fh.m2m_ctx->new_frame) -@@ -497,7 +560,9 @@ static void cedrus_h265_setup(struct ced +@@ -499,7 +562,9 @@ static void cedrus_h265_setup(struct ced V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED, pps->flags); @@ -128,7 +128,7 @@ Signed-off-by: Jernej Skrabec reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED, V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED, -@@ -573,12 +638,14 @@ static void cedrus_h265_setup(struct ced +@@ -575,12 +640,14 @@ static void cedrus_h265_setup(struct ced chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + pred_weight_table->delta_chroma_log2_weight_denom; @@ -144,7 +144,7 @@ Signed-off-by: Jernej Skrabec /* Decoded picture size. */ reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | -@@ -672,6 +739,17 @@ static int cedrus_h265_start(struct cedr +@@ -674,6 +741,17 @@ static int cedrus_h265_start(struct cedr if (!ctx->codec.h265.neighbor_info_buf) return -ENOMEM; @@ -162,7 +162,7 @@ Signed-off-by: Jernej Skrabec return 0; } -@@ -690,6 +768,9 @@ static void cedrus_h265_stop(struct cedr +@@ -692,6 +770,9 @@ static void cedrus_h265_stop(struct cedr dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, ctx->codec.h265.neighbor_info_buf, ctx->codec.h265.neighbor_info_buf_addr); diff --git a/projects/Allwinner/patches/linux/0019-media-cedrus-Add-callback-for-buffer-cleanup.patch b/projects/Allwinner/patches/linux/0019-media-cedrus-Add-callback-for-buffer-cleanup.patch index f8ebf3ad21..10fde62a23 100644 --- a/projects/Allwinner/patches/linux/0019-media-cedrus-Add-callback-for-buffer-cleanup.patch +++ b/projects/Allwinner/patches/linux/0019-media-cedrus-Add-callback-for-buffer-cleanup.patch @@ -11,7 +11,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -164,6 +164,7 @@ struct cedrus_dec_ops { +@@ -166,6 +166,7 @@ struct cedrus_dec_ops { int (*start)(struct cedrus_ctx *ctx); void (*stop)(struct cedrus_ctx *ctx); void (*trigger)(struct cedrus_ctx *ctx); @@ -21,7 +21,7 @@ Signed-off-by: Jernej Skrabec struct cedrus_variant { --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -463,6 +463,18 @@ static int cedrus_buf_prepare(struct vb2 +@@ -469,6 +469,18 @@ static int cedrus_buf_prepare(struct vb2 return 0; } @@ -40,7 +40,7 @@ Signed-off-by: Jernej Skrabec static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) { struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); -@@ -547,6 +559,7 @@ static void cedrus_buf_request_complete( +@@ -551,6 +563,7 @@ static void cedrus_buf_request_complete( static struct vb2_ops cedrus_qops = { .queue_setup = cedrus_queue_setup, .buf_prepare = cedrus_buf_prepare, diff --git a/projects/Allwinner/patches/linux/0020-media-cedrus-hevc-Improve-buffer-management.patch b/projects/Allwinner/patches/linux/0020-media-cedrus-hevc-Improve-buffer-management.patch index 7c5ac09327..c575d4b93c 100644 --- a/projects/Allwinner/patches/linux/0020-media-cedrus-hevc-Improve-buffer-management.patch +++ b/projects/Allwinner/patches/linux/0020-media-cedrus-hevc-Improve-buffer-management.patch @@ -11,7 +11,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -103,6 +103,11 @@ struct cedrus_buffer { +@@ -105,6 +105,11 @@ struct cedrus_buffer { unsigned int position; enum cedrus_h264_pic_type pic_type; } h264; @@ -23,7 +23,7 @@ Signed-off-by: Jernej Skrabec } codec; }; -@@ -136,10 +141,6 @@ struct cedrus_ctx { +@@ -138,10 +143,6 @@ struct cedrus_ctx { ssize_t intra_pred_buf_size; } h264; struct { @@ -130,7 +130,7 @@ Signed-off-by: Jernej Skrabec } } -@@ -386,36 +427,6 @@ static void cedrus_h265_setup(struct ced +@@ -388,36 +429,6 @@ static void cedrus_h265_setup(struct ced width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); @@ -167,16 +167,16 @@ Signed-off-by: Jernej Skrabec /* Activate H265 engine. */ cedrus_engine_enable(ctx, CEDRUS_CODEC_H265); -@@ -669,7 +680,7 @@ static void cedrus_h265_setup(struct ced +@@ -671,7 +682,7 @@ static void cedrus_h265_setup(struct ced /* Write decoded picture buffer in pic list. */ - cedrus_h265_frame_info_write_dpb(ctx, slice_params->dpb, -- slice_params->num_active_dpb_entries); -+ slice_params->num_active_dpb_entries, sps); + cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb, +- decode_params->num_active_dpb_entries); ++ decode_params->num_active_dpb_entries, sps); /* Output frame. */ -@@ -680,7 +691,7 @@ static void cedrus_h265_setup(struct ced +@@ -682,7 +693,7 @@ static void cedrus_h265_setup(struct ced cedrus_h265_frame_info_write_single(ctx, output_pic_list_index, slice_params->pic_struct != 0, pic_order_cnt, @@ -185,7 +185,7 @@ Signed-off-by: Jernej Skrabec cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index); -@@ -729,9 +740,6 @@ static int cedrus_h265_start(struct cedr +@@ -731,9 +742,6 @@ static int cedrus_h265_start(struct cedr { struct cedrus_dev *dev = ctx->dev; @@ -195,7 +195,7 @@ Signed-off-by: Jernej Skrabec ctx->codec.h265.neighbor_info_buf = dma_alloc_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, &ctx->codec.h265.neighbor_info_buf_addr, -@@ -757,14 +765,6 @@ static void cedrus_h265_stop(struct cedr +@@ -759,14 +767,6 @@ static void cedrus_h265_stop(struct cedr { struct cedrus_dev *dev = ctx->dev; @@ -210,7 +210,7 @@ Signed-off-by: Jernej Skrabec dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, ctx->codec.h265.neighbor_info_buf, ctx->codec.h265.neighbor_info_buf_addr); -@@ -780,6 +780,16 @@ static void cedrus_h265_trigger(struct c +@@ -782,6 +782,16 @@ static void cedrus_h265_trigger(struct c cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE); } @@ -227,7 +227,7 @@ Signed-off-by: Jernej Skrabec struct cedrus_dec_ops cedrus_dec_ops_h265 = { .irq_clear = cedrus_h265_irq_clear, .irq_disable = cedrus_h265_irq_disable, -@@ -788,4 +798,5 @@ struct cedrus_dec_ops cedrus_dec_ops_h26 +@@ -790,4 +800,5 @@ struct cedrus_dec_ops cedrus_dec_ops_h26 .start = cedrus_h265_start, .stop = cedrus_h265_stop, .trigger = cedrus_h265_trigger, diff --git a/projects/Allwinner/patches/linux/0021-media-cedrus-h264-Improve-buffer-management.patch b/projects/Allwinner/patches/linux/0021-media-cedrus-h264-Improve-buffer-management.patch index 72f2887df5..f0aea0576b 100644 --- a/projects/Allwinner/patches/linux/0021-media-cedrus-h264-Improve-buffer-management.patch +++ b/projects/Allwinner/patches/linux/0021-media-cedrus-h264-Improve-buffer-management.patch @@ -11,7 +11,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -102,6 +102,9 @@ struct cedrus_buffer { +@@ -104,6 +104,9 @@ struct cedrus_buffer { struct { unsigned int position; enum cedrus_h264_pic_type pic_type; diff --git a/projects/Allwinner/patches/linux/0022-WIp-10-bit-HEVC-support.patch b/projects/Allwinner/patches/linux/0022-WIp-10-bit-HEVC-support.patch index 8d1ee5fde0..4c3b59d9f5 100644 --- a/projects/Allwinner/patches/linux/0022-WIp-10-bit-HEVC-support.patch +++ b/projects/Allwinner/patches/linux/0022-WIp-10-bit-HEVC-support.patch @@ -14,7 +14,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -277,7 +277,7 @@ static int cedrus_open(struct file *file +@@ -289,7 +289,7 @@ static int cedrus_open(struct file *file goto err_ctrls; } ctx->dst_fmt.pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12; @@ -23,7 +23,7 @@ Signed-off-by: Jernej Skrabec ctx->src_fmt.pixelformat = V4L2_PIX_FMT_MPEG2_SLICE; /* * TILED_NV12 has more strict requirements, so copy the width and -@@ -285,7 +285,7 @@ static int cedrus_open(struct file *file +@@ -297,7 +297,7 @@ static int cedrus_open(struct file *file */ ctx->src_fmt.width = ctx->dst_fmt.width; ctx->src_fmt.height = ctx->dst_fmt.height; @@ -34,7 +34,7 @@ Signed-off-by: Jernej Skrabec --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -532,6 +532,18 @@ static void cedrus_h265_setup(struct ced +@@ -534,6 +534,18 @@ static void cedrus_h265_setup(struct ced cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); diff --git a/projects/Allwinner/patches/linux/0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch b/projects/Allwinner/patches/linux/0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch index c9e25a8c1c..753573bb18 100644 --- a/projects/Allwinner/patches/linux/0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch +++ b/projects/Allwinner/patches/linux/0023-media-cedrus-add-check-for-H264-and-HEVC-limitations.patch @@ -62,7 +62,7 @@ Signed-off-by: Jernej Skrabec static const struct cedrus_control cedrus_controls[] = { { .cfg = { -@@ -56,6 +100,7 @@ static const struct cedrus_control cedru +@@ -62,6 +106,7 @@ static const struct cedrus_control cedru { .cfg = { .id = V4L2_CID_STATELESS_H264_SPS, @@ -70,7 +70,7 @@ Signed-off-by: Jernej Skrabec }, .codec = CEDRUS_CODEC_H264, }, -@@ -114,6 +159,7 @@ static const struct cedrus_control cedru +@@ -120,6 +165,7 @@ static const struct cedrus_control cedru { .cfg = { .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, @@ -78,7 +78,7 @@ Signed-off-by: Jernej Skrabec }, .codec = CEDRUS_CODEC_H265, }, -@@ -544,7 +590,8 @@ static const struct cedrus_variant sun50 +@@ -556,7 +602,8 @@ static const struct cedrus_variant sun50 CEDRUS_CAPABILITY_MPEG2_DEC | CEDRUS_CAPABILITY_H264_DEC | CEDRUS_CAPABILITY_H265_DEC | diff --git a/projects/Allwinner/patches/linux/0028-mfd-Add-support-for-AC200.patch b/projects/Allwinner/patches/linux/0028-mfd-Add-support-for-AC200.patch index 04dd0106f8..bbf6c04ec8 100644 --- a/projects/Allwinner/patches/linux/0028-mfd-Add-support-for-AC200.patch +++ b/projects/Allwinner/patches/linux/0028-mfd-Add-support-for-AC200.patch @@ -33,7 +33,7 @@ Signed-off-by: Jernej Skrabec select MFD_CORE --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile -@@ -143,6 +143,7 @@ obj-$(CONFIG_MFD_DA9052_SPI) += da9052-s +@@ -142,6 +142,7 @@ obj-$(CONFIG_MFD_DA9052_SPI) += da9052-s obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o obj-$(CONFIG_MFD_AC100) += ac100.o diff --git a/projects/Allwinner/patches/linux/0033-WIP-I2S-multi-channel.patch b/projects/Allwinner/patches/linux/0033-WIP-I2S-multi-channel.patch index 3dfb5efe03..10954bfc1f 100644 --- a/projects/Allwinner/patches/linux/0033-WIP-I2S-multi-channel.patch +++ b/projects/Allwinner/patches/linux/0033-WIP-I2S-multi-channel.patch @@ -278,7 +278,7 @@ Signed-off-by: Jernej Skrabec ret = clk_prepare_enable(i2s->mod_clk); if (ret) { -@@ -1527,6 +1583,7 @@ static int sun4i_i2s_probe(struct platfo +@@ -1526,6 +1582,7 @@ static int sun4i_i2s_probe(struct platfo i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; i2s->capture_dma_data.maxburst = 8; diff --git a/projects/Allwinner/patches/linux/0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch b/projects/Allwinner/patches/linux/0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch similarity index 58% rename from projects/Allwinner/patches/linux/0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch rename to projects/Allwinner/patches/linux/0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch index bbd2c4622b..1ece453403 100644 --- a/projects/Allwinner/patches/linux/0038-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch +++ b/projects/Allwinner/patches/linux/0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch @@ -12,39 +12,33 @@ Signed-off-by: Jonas Karlman --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code { +@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { /* The controls are not stable at the moment and will likely be reworked. */ struct v4l2_ctrl_hevc_sps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + __u8 video_parameter_set_id; + __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; __u16 pic_width_in_luma_samples; __u16 pic_height_in_luma_samples; __u8 bit_depth_luma_minus8; -@@ -76,9 +79,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 log2_diff_max_min_pcm_luma_coding_block_size; - __u8 num_short_term_ref_pic_sets; - __u8 num_long_term_ref_pics_sps; -- __u8 chroma_format_idc; - -- __u8 padding; -+ __u8 padding[7]; +@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; ++ __u8 padding[6]; ++ __u64 flags; }; -@@ -105,7 +107,10 @@ struct v4l2_ctrl_hevc_sps { + +@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps { struct v4l2_ctrl_hevc_pps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ + __u8 pic_parameter_set_id; __u8 num_extra_slice_header_bits; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; - __s8 init_qp_minus26; - __u8 diff_cu_qp_delta_depth; - __s8 pps_cb_qp_offset; -@@ -118,7 +123,7 @@ struct v4l2_ctrl_hevc_pps { + __u8 num_ref_idx_l0_default_active_minus1; + __u8 num_ref_idx_l1_default_active_minus1; +@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps { __s8 pps_tc_offset_div2; __u8 log2_parallel_merge_level_minus2; @@ -53,15 +47,15 @@ Signed-off-by: Jonas Karlman __u64 flags; }; -@@ -204,7 +209,10 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; +@@ -202,7 +207,10 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -- __u8 padding[5]; +- __u8 padding; + __u16 short_term_ref_pic_set_size; + __u16 long_term_ref_pic_set_size; + -+ __u8 padding; ++ __u8 padding[4]; - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; diff --git a/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch b/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch new file mode 100644 index 0000000000..0a239a86d8 --- /dev/null +++ b/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch @@ -0,0 +1,32 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 23 May 2020 15:07:15 +0000 +Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices + +--- + include/media/hevc-ctrls.h | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; + +- __u8 padding[6]; ++ __u8 num_slices; ++ __u8 padding[5]; + + __u64 flags; + }; +@@ -210,7 +211,9 @@ struct v4l2_ctrl_hevc_slice_params { + __u16 short_term_ref_pic_set_size; + __u16 long_term_ref_pic_set_size; + +- __u8 padding[4]; ++ __u32 num_entry_point_offsets; ++ __u32 entry_point_offset_minus1[256]; ++ __u8 padding[8]; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; diff --git a/projects/Allwinner/devices/A64/patches/linux/0001-HACK-a64-Add-HDMI-sound-card.patch b/projects/Allwinner/patches/linux/0039-HACK-a64-Add-HDMI-sound-card.patch similarity index 95% rename from projects/Allwinner/devices/A64/patches/linux/0001-HACK-a64-Add-HDMI-sound-card.patch rename to projects/Allwinner/patches/linux/0039-HACK-a64-Add-HDMI-sound-card.patch index be4cdd7bfa..0785adafee 100644 --- a/projects/Allwinner/devices/A64/patches/linux/0001-HACK-a64-Add-HDMI-sound-card.patch +++ b/projects/Allwinner/patches/linux/0039-HACK-a64-Add-HDMI-sound-card.patch @@ -10,7 +10,7 @@ Signed-off-by: Jernej Skrabec --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -161,6 +161,24 @@ +@@ -166,6 +166,24 @@ }; }; @@ -35,7 +35,7 @@ Signed-off-by: Jernej Skrabec timer { compatible = "arm,armv8-timer"; allwinner,erratum-unknown1; -@@ -878,7 +896,6 @@ +@@ -918,7 +936,6 @@ resets = <&ccu RST_BUS_I2S2>; dma-names = "rx", "tx"; dmas = <&dma 27>, <&dma 27>; @@ -43,7 +43,7 @@ Signed-off-by: Jernej Skrabec }; dai: dai@1c22c00 { -@@ -1178,6 +1195,7 @@ +@@ -1218,6 +1235,7 @@ }; hdmi: hdmi@1ee0000 { diff --git a/projects/Allwinner/patches/linux/0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch b/projects/Allwinner/patches/linux/0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch deleted file mode 100644 index 7d1ceebd6a..0000000000 --- a/projects/Allwinner/patches/linux/0039-HACK-media-uapi-hevc-tiles-and-num_slices.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:07:15 +0000 -Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices - ---- - include/media/hevc-ctrls.h | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -80,7 +80,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 num_short_term_ref_pic_sets; - __u8 num_long_term_ref_pics_sps; - -- __u8 padding[7]; -+ __u8 num_slices; -+ __u8 padding[6]; - - __u64 flags; - }; -@@ -175,6 +176,7 @@ struct v4l2_ctrl_hevc_slice_params { - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - __u32 slice_segment_addr; -+ __u32 num_entry_point_offsets; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; -@@ -212,7 +214,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u16 short_term_ref_pic_set_size; - __u16 long_term_ref_pic_set_size; - -- __u8 padding; -+ __u8 padding[5]; -+ -+ __u32 entry_point_offset_minus1[256]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; diff --git a/projects/Allwinner/devices/A64/patches/linux/0002-a64-increase-mali-frequency.patch b/projects/Allwinner/patches/linux/0040-a64-increase-mali-frequency.patch similarity index 97% rename from projects/Allwinner/devices/A64/patches/linux/0002-a64-increase-mali-frequency.patch rename to projects/Allwinner/patches/linux/0040-a64-increase-mali-frequency.patch index be00c324aa..c2e76e80ab 100644 --- a/projects/Allwinner/devices/A64/patches/linux/0002-a64-increase-mali-frequency.patch +++ b/projects/Allwinner/patches/linux/0040-a64-increase-mali-frequency.patch @@ -10,7 +10,7 @@ Signed-off-by: Jernej Skrabec --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -1101,6 +1101,9 @@ +@@ -1141,6 +1141,9 @@ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; clock-names = "bus", "core"; resets = <&ccu RST_BUS_GPU>; diff --git a/projects/Allwinner/devices/R40/patches/linux/0002-bpi-m2u-analog-codec.patch b/projects/Allwinner/patches/linux/0041-bpi-m2u-analog-codec.patch similarity index 98% rename from projects/Allwinner/devices/R40/patches/linux/0002-bpi-m2u-analog-codec.patch rename to projects/Allwinner/patches/linux/0041-bpi-m2u-analog-codec.patch index 7b19556c09..c1c95f315b 100644 --- a/projects/Allwinner/devices/R40/patches/linux/0002-bpi-m2u-analog-codec.patch +++ b/projects/Allwinner/patches/linux/0041-bpi-m2u-analog-codec.patch @@ -29,7 +29,7 @@ Signed-off-by: Jernej Skrabec }; --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi -@@ -692,6 +692,25 @@ +@@ -736,6 +736,25 @@ status = "disabled"; }; diff --git a/projects/Allwinner/devices/R40/patches/linux/0003-r40-hdmi-audio-wip.patch b/projects/Allwinner/patches/linux/0042-r40-hdmi-audio-wip.patch similarity index 97% rename from projects/Allwinner/devices/R40/patches/linux/0003-r40-hdmi-audio-wip.patch rename to projects/Allwinner/patches/linux/0042-r40-hdmi-audio-wip.patch index 76fcb9d50d..6d6bbeef47 100644 --- a/projects/Allwinner/devices/R40/patches/linux/0003-r40-hdmi-audio-wip.patch +++ b/projects/Allwinner/patches/linux/0042-r40-hdmi-audio-wip.patch @@ -35,7 +35,7 @@ Signed-off-by: Jernej Skrabec thermal-zones { cpu_thermal: cpu0-thermal { /* milliseconds */ -@@ -666,6 +684,19 @@ +@@ -710,6 +728,19 @@ clocks = <&osc24M>; }; @@ -55,7 +55,7 @@ Signed-off-by: Jernej Skrabec ir0: ir@1c21800 { compatible = "allwinner,sun8i-r40-ir", "allwinner,sun6i-a31-ir"; -@@ -1142,6 +1173,7 @@ +@@ -1186,6 +1217,7 @@ }; hdmi: hdmi@1ee0000 { diff --git a/projects/Allwinner/devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch b/projects/Allwinner/patches/linux/0043-HACK-h6-Add-HDMI-sound-card.patch similarity index 97% rename from projects/Allwinner/devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch rename to projects/Allwinner/patches/linux/0043-HACK-h6-Add-HDMI-sound-card.patch index 390a82e54a..dda3c2fd2d 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0001-HACK-h6-Add-HDMI-sound-card.patch +++ b/projects/Allwinner/patches/linux/0043-HACK-h6-Add-HDMI-sound-card.patch @@ -35,7 +35,7 @@ Signed-off-by: Jernej Skrabec soc { compatible = "simple-bus"; #address-cells = <1>; -@@ -655,7 +673,6 @@ +@@ -664,7 +682,6 @@ dmas = <&dma 4>, <&dma 4>; resets = <&ccu RST_BUS_I2S1>; dma-names = "rx", "tx"; @@ -43,7 +43,7 @@ Signed-off-by: Jernej Skrabec }; spdif: spdif@5093000 { -@@ -792,6 +809,7 @@ +@@ -801,6 +818,7 @@ }; hdmi: hdmi@6000000 { diff --git a/projects/Allwinner/devices/H6/patches/linux/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch b/projects/Allwinner/patches/linux/0044-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch rename to projects/Allwinner/patches/linux/0044-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch b/projects/Allwinner/patches/linux/0045-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch rename to projects/Allwinner/patches/linux/0045-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch b/projects/Allwinner/patches/linux/0046-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch rename to projects/Allwinner/patches/linux/0046-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0005-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch b/projects/Allwinner/patches/linux/0047-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0005-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch rename to projects/Allwinner/patches/linux/0047-arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0006-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch b/projects/Allwinner/patches/linux/0048-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0006-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch rename to projects/Allwinner/patches/linux/0048-arm64-allwinner-dts-h6-enable-USB3-port-on-Pine-H64.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch b/projects/Allwinner/patches/linux/0049-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch similarity index 95% rename from projects/Allwinner/devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch rename to projects/Allwinner/patches/linux/0049-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch index ba637b82ee..51bc021cb7 100644 --- a/projects/Allwinner/devices/H6/patches/linux/0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch +++ b/projects/Allwinner/patches/linux/0049-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch @@ -37,8 +37,8 @@ Signed-off-by: Jernej Skrabec + }; }; - watchdog: watchdog@30090a0 { -@@ -364,6 +378,13 @@ + timer@3009000 { +@@ -373,6 +387,13 @@ drive-strength = <40>; }; @@ -52,7 +52,7 @@ Signed-off-by: Jernej Skrabec hdmi_pins: hdmi-pins { pins = "PH8", "PH9", "PH10"; function = "hdmi"; -@@ -384,6 +405,11 @@ +@@ -393,6 +414,11 @@ function = "i2c2"; }; @@ -64,7 +64,7 @@ Signed-off-by: Jernej Skrabec mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; -@@ -410,6 +436,11 @@ +@@ -419,6 +445,11 @@ bias-pull-up; }; @@ -76,7 +76,7 @@ Signed-off-by: Jernej Skrabec /omit-if-no-ref/ spi0_pins: spi0-pins { pins = "PC0", "PC2", "PC3"; -@@ -643,6 +674,31 @@ +@@ -652,6 +683,31 @@ #size-cells = <0>; }; diff --git a/projects/Allwinner/devices/H6/patches/linux/0008-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch b/projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0008-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch rename to projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0009-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch b/projects/Allwinner/patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0009-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch rename to projects/Allwinner/patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0010-arm64-allwinner-h6-Enable-USB3-for-OrangePi-Lite2.patch b/projects/Allwinner/patches/linux/0052-arm64-allwinner-h6-Enable-USB3-for-OrangePi-Lite2.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0010-arm64-allwinner-h6-Enable-USB3-for-OrangePi-Lite2.patch rename to projects/Allwinner/patches/linux/0052-arm64-allwinner-h6-Enable-USB3-for-OrangePi-Lite2.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch b/projects/Allwinner/patches/linux/0053-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch rename to projects/Allwinner/patches/linux/0053-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/0020-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch b/projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch similarity index 100% rename from projects/Allwinner/devices/H6/patches/linux/0020-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch rename to projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch From a9d6859c7951f88527eb59cba3fcc9c4b16a5450 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 31 Aug 2021 17:28:13 +0200 Subject: [PATCH 40/51] ffmpeg: update v4l2-request patch 5.14 Patch created using revisions e2ee55c..36dbf22 from branch v4l2-request-hwaccel-4.3.2 of https://github.com/jernejsk/FFmpeg --- .../ffmpeg-001-v4l2-request.patch | 734 ++++++++---------- 1 file changed, 322 insertions(+), 412 deletions(-) diff --git a/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch b/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch index 6bd75c0343..a09da010de 100644 --- a/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch +++ b/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch @@ -1,7 +1,7 @@ -From 2c839cfe011862b06bf986a7999caf21c4d54d6e Mon Sep 17 00:00:00 2001 +From fd7c38d6a87d92faaf3b7f18df5cb19918aca3a7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 3 Dec 2018 23:48:04 +0100 -Subject: [PATCH 01/19] avutil: add av_buffer_pool_flush() +Subject: [PATCH 01/18] avutil: add av_buffer_pool_flush() Used by V4L2 request API hwaccel @@ -52,10 +52,10 @@ index c0f3f6cc9abe..998beec9ac5b 100644 * Mark the pool as being available for freeing. It will actually be freed only * once all the allocated buffers associated with the pool are released. Thus it -From adcd1a0731d769828bb88e4637452a8ad84a30d3 Mon Sep 17 00:00:00 2001 +From 73677b0d323aca461e88c9ee287afb4d6744a0bc Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 02/19] Add common V4L2 request API code +Subject: [PATCH 02/18] Add common V4L2 request API code Signed-off-by: Jonas Karlman --- @@ -1239,10 +1239,10 @@ index 000000000000..58d2aa70af80 + +#endif /* AVCODEC_V4L2_REQUEST_H */ -From bfb39057e0ba9a8b1e81c799d09730a70af1fa28 Mon Sep 17 00:00:00 2001 +From 4b5bc3f75955694bfe7af15a323f0c902e53acf1 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Wed, 20 Feb 2019 11:18:00 -0300 -Subject: [PATCH 03/19] h264dec: add idr_pic_id to slice context +Subject: [PATCH 03/18] h264dec: add idr_pic_id to slice context Used by V4L2 request API h264 hwaccel @@ -1279,10 +1279,10 @@ index a419615124b2..316dc6a2c890 100644 /** -From 34c532ae4ff98c49ae4517699acecd491661a4f0 Mon Sep 17 00:00:00 2001 +From 89a05a843c5ecef72b37e5381d2169027e3450b0 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 22 May 2019 14:44:22 +0200 -Subject: [PATCH 04/19] h264dec: add ref_pic_marking and pic_order_cnt bit_size +Subject: [PATCH 04/18] h264dec: add ref_pic_marking and pic_order_cnt bit_size to slice context Used by V4L2 request API h264 hwaccel @@ -1356,10 +1356,10 @@ index 316dc6a2c890..f2cabac468d0 100644 /** -From 67d7c840cdd1b687272e5c482af6688916843a52 Mon Sep 17 00:00:00 2001 +From bd9786a78eb4c44325caef40305f86b2856ecad4 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 05/19] Add V4L2 request API h264 hwaccel +Subject: [PATCH 05/18] Add V4L2 request API h264 hwaccel Signed-off-by: Jernej Skrabec Signed-off-by: Jonas Karlman @@ -1917,10 +1917,10 @@ index 000000000000..88da8f0a2db0 + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From d23614d6e368e796019db46b5330c76323bcc49e Mon Sep 17 00:00:00 2001 +From e36de603c7c9daa8e1a833539c7311438eb1dc0c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 06/19] Add V4L2 request API mpeg2 hwaccel +Subject: [PATCH 06/18] Add V4L2 request API mpeg2 hwaccel Signed-off-by: Jonas Karlman --- @@ -1928,8 +1928,8 @@ Signed-off-by: Jonas Karlman libavcodec/Makefile | 1 + libavcodec/hwaccels.h | 1 + libavcodec/mpeg12dec.c | 6 ++ - libavcodec/v4l2_request_mpeg2.c | 154 ++++++++++++++++++++++++++++++++ - 5 files changed, 165 insertions(+) + libavcodec/v4l2_request_mpeg2.c | 159 ++++++++++++++++++++++++++++++++ + 5 files changed, 170 insertions(+) create mode 100644 libavcodec/v4l2_request_mpeg2.c diff --git a/configure b/configure @@ -2003,10 +2003,10 @@ index 99e56532a59e..15aaf97a34c7 100644 }, diff --git a/libavcodec/v4l2_request_mpeg2.c b/libavcodec/v4l2_request_mpeg2.c new file mode 100644 -index 000000000000..88d86cc4c23f +index 000000000000..84d53209c79d --- /dev/null +++ b/libavcodec/v4l2_request_mpeg2.c -@@ -0,0 +1,154 @@ +@@ -0,0 +1,159 @@ +/* + * This file is part of FFmpeg. + * @@ -2030,8 +2030,9 @@ index 000000000000..88d86cc4c23f +#include "v4l2_request.h" + +typedef struct V4L2RequestControlsMPEG2 { -+ struct v4l2_ctrl_mpeg2_slice_params slice_params; -+ struct v4l2_ctrl_mpeg2_quantization quantization; ++ struct v4l2_ctrl_mpeg2_sequence sequence; ++ struct v4l2_ctrl_mpeg2_picture picture; ++ struct v4l2_ctrl_mpeg2_quantisation quantisation; +} V4L2RequestControlsMPEG2; + +static int v4l2_request_mpeg2_start_frame(AVCodecContext *avctx, @@ -2042,69 +2043,71 @@ index 000000000000..88d86cc4c23f + V4L2RequestControlsMPEG2 *controls = s->current_picture_ptr->hwaccel_picture_private; + V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)s->current_picture_ptr->f->data[0]; + -+ controls->slice_params = (struct v4l2_ctrl_mpeg2_slice_params) { -+ .bit_size = 0, -+ .data_bit_offset = 0, ++ controls->sequence = (struct v4l2_ctrl_mpeg2_sequence) { ++ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence header */ ++ .horizontal_size = s->width, ++ .vertical_size = s->height, ++ .vbv_buffer_size = req->output.size, + -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Slice */ -+ .quantiser_scale_code = s->qscale >> 1, -+ -+ .sequence = { -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence header */ -+ .horizontal_size = s->width, -+ .vertical_size = s->height, -+ .vbv_buffer_size = req->output.size, -+ -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence extension */ -+ .profile_and_level_indication = 0, -+ .progressive_sequence = s->progressive_sequence, -+ .chroma_format = s->chroma_format, -+ }, -+ -+ .picture = { -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Picture header */ -+ .picture_coding_type = s->pict_type, -+ -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Picture coding extension */ -+ .f_code[0][0] = s->mpeg_f_code[0][0], -+ .f_code[0][1] = s->mpeg_f_code[0][1], -+ .f_code[1][0] = s->mpeg_f_code[1][0], -+ .f_code[1][1] = s->mpeg_f_code[1][1], -+ .intra_dc_precision = s->intra_dc_precision, -+ .picture_structure = s->picture_structure, -+ .top_field_first = s->top_field_first, -+ .frame_pred_frame_dct = s->frame_pred_frame_dct, -+ .concealment_motion_vectors = s->concealment_motion_vectors, -+ .q_scale_type = s->q_scale_type, -+ .intra_vlc_format = s->intra_vlc_format, -+ .alternate_scan = s->alternate_scan, -+ .repeat_first_field = s->repeat_first_field, -+ .progressive_frame = s->progressive_frame, -+ }, ++ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence extension */ ++ .profile_and_level_indication = 0, ++ .chroma_format = s->chroma_format, + }; + ++ if (s->progressive_sequence) ++ controls->sequence.flags |= V4L2_MPEG2_SEQ_FLAG_PROGRESSIVE; ++ ++ controls->picture = (struct v4l2_ctrl_mpeg2_picture) { ++ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Picture header */ ++ .picture_coding_type = s->pict_type, ++ ++ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Picture coding extension */ ++ .f_code[0][0] = s->mpeg_f_code[0][0], ++ .f_code[0][1] = s->mpeg_f_code[0][1], ++ .f_code[1][0] = s->mpeg_f_code[1][0], ++ .f_code[1][1] = s->mpeg_f_code[1][1], ++ .picture_structure = s->picture_structure, ++ .intra_dc_precision = s->intra_dc_precision, ++ }; ++ ++ if (s->top_field_first) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST; ++ ++ if (s->frame_pred_frame_dct) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_FRAME_PRED_DCT; ++ ++ if (s->concealment_motion_vectors) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_CONCEALMENT_MV; ++ ++ if (s->intra_vlc_format) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_INTRA_VLC; ++ ++ if (s->q_scale_type) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_Q_SCALE_TYPE; ++ ++ if (s->alternate_scan) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_ALT_SCAN; ++ ++ if (s->repeat_first_field) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_REPEAT_FIRST; ++ ++ if (s->progressive_frame) ++ controls->picture.flags |= V4L2_MPEG2_PIC_FLAG_PROGRESSIVE; ++ + switch (s->pict_type) { + case AV_PICTURE_TYPE_B: -+ controls->slice_params.backward_ref_ts = ff_v4l2_request_get_capture_timestamp(s->next_picture.f); ++ controls->picture.backward_ref_ts = ff_v4l2_request_get_capture_timestamp(s->next_picture.f); + // fall-through + case AV_PICTURE_TYPE_P: -+ controls->slice_params.forward_ref_ts = ff_v4l2_request_get_capture_timestamp(s->last_picture.f); ++ controls->picture.forward_ref_ts = ff_v4l2_request_get_capture_timestamp(s->last_picture.f); + } + -+ controls->quantization = (struct v4l2_ctrl_mpeg2_quantization) { -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Quant matrix extension */ -+ .load_intra_quantiser_matrix = 1, -+ .load_non_intra_quantiser_matrix = 1, -+ .load_chroma_intra_quantiser_matrix = 1, -+ .load_chroma_non_intra_quantiser_matrix = 1, -+ }; -+ + for (int i = 0; i < 64; i++) { + int n = s->idsp.idct_permutation[ff_zigzag_direct[i]]; -+ controls->quantization.intra_quantiser_matrix[i] = s->intra_matrix[n]; -+ controls->quantization.non_intra_quantiser_matrix[i] = s->inter_matrix[n]; -+ controls->quantization.chroma_intra_quantiser_matrix[i] = s->chroma_intra_matrix[n]; -+ controls->quantization.chroma_non_intra_quantiser_matrix[i] = s->chroma_inter_matrix[n]; ++ controls->quantisation.intra_quantiser_matrix[i] = s->intra_matrix[n]; ++ controls->quantisation.non_intra_quantiser_matrix[i] = s->inter_matrix[n]; ++ controls->quantisation.chroma_intra_quantiser_matrix[i] = s->chroma_intra_matrix[n]; ++ controls->quantisation.chroma_non_intra_quantiser_matrix[i] = s->chroma_inter_matrix[n]; + } + + return ff_v4l2_request_reset_frame(avctx, s->current_picture_ptr->f); @@ -2121,23 +2124,25 @@ index 000000000000..88d86cc4c23f +{ + const MpegEncContext *s = avctx->priv_data; + V4L2RequestControlsMPEG2 *controls = s->current_picture_ptr->hwaccel_picture_private; -+ V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)s->current_picture_ptr->f->data[0]; + + struct v4l2_ext_control control[] = { + { -+ .id = V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS, -+ .ptr = &controls->slice_params, -+ .size = sizeof(controls->slice_params), ++ .id = V4L2_CID_STATELESS_MPEG2_SEQUENCE, ++ .ptr = &controls->sequence, ++ .size = sizeof(controls->sequence), + }, + { -+ .id = V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION, -+ .ptr = &controls->quantization, -+ .size = sizeof(controls->quantization), ++ .id = V4L2_CID_STATELESS_MPEG2_PICTURE, ++ .ptr = &controls->picture, ++ .size = sizeof(controls->picture), ++ }, ++ { ++ .id = V4L2_CID_STATELESS_MPEG2_QUANTISATION, ++ .ptr = &controls->quantisation, ++ .size = sizeof(controls->quantisation), + }, + }; + -+ controls->slice_params.bit_size = req->output.used * 8; -+ + return ff_v4l2_request_decode_frame(avctx, s->current_picture_ptr->f, control, FF_ARRAY_ELEMS(control)); +} + @@ -2162,10 +2167,10 @@ index 000000000000..88d86cc4c23f + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From d09f7dc15ca0d889dcd112a66d2ebc88046fc271 Mon Sep 17 00:00:00 2001 +From 8fedb1c1d5c232936ec7ddff71e72dd27dbace6d Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 22 May 2019 14:46:58 +0200 -Subject: [PATCH 07/19] Add V4L2 request API vp8 hwaccel +Subject: [PATCH 07/18] Add V4L2 request API vp8 hwaccel Signed-off-by: Boris Brezillon Signed-off-by: Ezequiel Garcia @@ -2444,10 +2449,10 @@ index e84fcdeaa1e7..0608d9e4e165 100644 NULL }, -From 81d6e95b5f2753737791a8a9561850d4a028ad86 Mon Sep 17 00:00:00 2001 +From aba2a109c8191b8e914522c7504f78385e1da3ed Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 08/19] Add V4L2 request API hevc hwaccel +Subject: [PATCH 08/18] Add V4L2 request API hevc hwaccel Signed-off-by: Jernej Skrabec Signed-off-by: Jonas Karlman @@ -2456,8 +2461,8 @@ Signed-off-by: Jonas Karlman libavcodec/Makefile | 1 + libavcodec/hevcdec.c | 10 + libavcodec/hwaccels.h | 1 + - libavcodec/v4l2_request_hevc.c | 533 +++++++++++++++++++++++++++++++++ - 5 files changed, 548 insertions(+) + libavcodec/v4l2_request_hevc.c | 574 +++++++++++++++++++++++++++++++++ + 5 files changed, 589 insertions(+) create mode 100644 libavcodec/v4l2_request_hevc.c diff --git a/configure b/configure @@ -2549,10 +2554,10 @@ index 14838083ec36..bd75e94f4cae 100644 extern const AVHWAccel ff_hevc_videotoolbox_hwaccel; diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c new file mode 100644 -index 000000000000..f72490954653 +index 000000000000..d385c2f03615 --- /dev/null +++ b/libavcodec/v4l2_request_hevc.c -@@ -0,0 +1,533 @@ +@@ -0,0 +1,574 @@ +/* + * This file is part of FFmpeg. + * @@ -2580,6 +2585,7 @@ index 000000000000..f72490954653 +typedef struct V4L2RequestControlsHEVC { + struct v4l2_ctrl_hevc_sps sps; + struct v4l2_ctrl_hevc_pps pps; ++ struct v4l2_ctrl_hevc_decode_params dec_params; + struct v4l2_ctrl_hevc_slice_params slice_params[MAX_SLICES]; + int first_slice; + int num_slices; //TODO: this should be in control @@ -2660,8 +2666,56 @@ index 000000000000..f72490954653 + return 0; +} + ++static void fill_dec_params(struct v4l2_ctrl_hevc_decode_params *dec_params, const HEVCContext *h) ++{ ++ const HEVCFrame *pic = h->ref; ++ const SliceHeader *sh = &h->sh; ++ int i, entries = 0; ++ ++ *dec_params = (struct v4l2_ctrl_hevc_decode_params) { ++ .pic_order_cnt_val = pic->poc, /* FIXME: is this same as slice_params->slice_pic_order_cnt ? */ ++ .num_poc_st_curr_before = h->rps[ST_CURR_BEF].nb_refs, ++ .num_poc_st_curr_after = h->rps[ST_CURR_AFT].nb_refs, ++ .num_poc_lt_curr = h->rps[LT_CURR].nb_refs, ++ }; ++ ++ for (i = 0; i < FF_ARRAY_ELEMS(h->DPB); i++) { ++ const HEVCFrame *frame = &h->DPB[i]; ++ if (frame != pic && (frame->flags & (HEVC_FRAME_FLAG_LONG_REF | HEVC_FRAME_FLAG_SHORT_REF))) { ++ struct v4l2_hevc_dpb_entry *entry = &dec_params->dpb[entries++]; ++ ++ entry->timestamp = ff_v4l2_request_get_capture_timestamp(frame->frame); ++ entry->rps = find_frame_rps_type(h, entry->timestamp); ++ entry->field_pic = frame->frame->interlaced_frame; ++ ++ /* TODO: Interleaved: Get the POC for each field. */ ++ entry->pic_order_cnt[0] = frame->poc; ++ entry->pic_order_cnt[1] = frame->poc; ++ } ++ } ++ ++ dec_params->num_active_dpb_entries = entries; ++ ++ if (IS_IRAP(h)) ++ dec_params->flags |= V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC; ++ ++ if (IS_IDR(h)) ++ dec_params->flags |= V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC; ++ ++ /* FIXME: is this really frame property? */ ++ if (sh->no_output_of_prior_pics_flag) ++ dec_params->flags |= V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR; ++ ++ /* ++ * TODO: fill ++ * dec_params->poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ * dec_params->poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ * dec_params->poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ */ ++} ++ +static uint8_t get_ref_pic_index(const HEVCContext *h, const HEVCFrame *frame, -+ struct v4l2_ctrl_hevc_slice_params *slice_params) ++ struct v4l2_ctrl_hevc_decode_params *dec_params) +{ + uint64_t timestamp; + @@ -2670,8 +2724,8 @@ index 000000000000..f72490954653 + + timestamp = ff_v4l2_request_get_capture_timestamp(frame->frame); + -+ for (uint8_t i = 0; i < slice_params->num_active_dpb_entries; i++) { -+ struct v4l2_hevc_dpb_entry *entry = &slice_params->dpb[i]; ++ for (uint8_t i = 0; i < dec_params->num_active_dpb_entries; i++) { ++ struct v4l2_hevc_dpb_entry *entry = &dec_params->dpb[i]; + if (entry->timestamp == timestamp) + return i; + } @@ -2680,12 +2734,13 @@ index 000000000000..f72490954653 +} + +static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, ++ struct v4l2_ctrl_hevc_decode_params *dec_params, + struct v4l2_ctrl_hevc_slice_params *slice_params) +{ + const HEVCFrame *pic = h->ref; + const SliceHeader *sh = &h->sh; -+ int i, entries = 0; + RefPicList *rpl; ++ int i; + + *slice_params = (struct v4l2_ctrl_hevc_slice_params) { + .bit_size = 0, @@ -2714,11 +2769,6 @@ index 000000000000..f72490954653 + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */ + .pic_struct = h->sei.picture_timing.picture_struct, -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ .num_rps_poc_st_curr_before = h->rps[ST_CURR_BEF].nb_refs, -+ .num_rps_poc_st_curr_after = h->rps[ST_CURR_AFT].nb_refs, -+ .num_rps_poc_lt_curr = h->rps[LT_CURR].nb_refs, + }; + + if (sh->slice_sample_adaptive_offset_flag[0]) @@ -2745,33 +2795,19 @@ index 000000000000..f72490954653 + if (sh->slice_loop_filter_across_slices_enabled_flag) + slice_params->flags |= V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED; + -+ for (i = 0; i < FF_ARRAY_ELEMS(h->DPB); i++) { -+ const HEVCFrame *frame = &h->DPB[i]; -+ if (frame != pic && (frame->flags & (HEVC_FRAME_FLAG_LONG_REF | HEVC_FRAME_FLAG_SHORT_REF))) { -+ struct v4l2_hevc_dpb_entry *entry = &slice_params->dpb[entries++]; -+ -+ entry->timestamp = ff_v4l2_request_get_capture_timestamp(frame->frame); -+ entry->rps = find_frame_rps_type(h, entry->timestamp); -+ entry->field_pic = frame->frame->interlaced_frame; -+ -+ /* TODO: Interleaved: Get the POC for each field. */ -+ entry->pic_order_cnt[0] = frame->poc; -+ entry->pic_order_cnt[1] = frame->poc; -+ } -+ } -+ -+ slice_params->num_active_dpb_entries = entries; ++ if (sh->dependent_slice_segment_flag) ++ slice_params->flags |= V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT; + + if (sh->slice_type != HEVC_SLICE_I) { + rpl = &h->ref->refPicList[0]; + for (i = 0; i < rpl->nb_refs; i++) -+ slice_params->ref_idx_l0[i] = get_ref_pic_index(h, rpl->ref[i], slice_params); ++ slice_params->ref_idx_l0[i] = get_ref_pic_index(h, rpl->ref[i], dec_params); + } + + if (sh->slice_type == HEVC_SLICE_B) { + rpl = &h->ref->refPicList[1]; + for (i = 0; i < rpl->nb_refs; i++) -+ slice_params->ref_idx_l1[i] = get_ref_pic_index(h, rpl->ref[i], slice_params); ++ slice_params->ref_idx_l1[i] = get_ref_pic_index(h, rpl->ref[i], dec_params); + } + + v4l2_request_hevc_fill_pred_table(h, &slice_params->pred_weight_table); @@ -2783,7 +2819,6 @@ index 000000000000..f72490954653 + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + *ctrl = (struct v4l2_ctrl_hevc_sps) { -+ .chroma_format_idc = sps->chroma_format_idc, + .pic_width_in_luma_samples = sps->width, + .pic_height_in_luma_samples = sps->height, + .bit_depth_luma_minus8 = sps->bit_depth - 8, @@ -2804,6 +2839,8 @@ index 000000000000..f72490954653 + .log2_diff_max_min_pcm_luma_coding_block_size = sps->pcm.log2_max_pcm_cb_size - sps->pcm.log2_min_pcm_cb_size, + .num_short_term_ref_pic_sets = sps->nb_st_rps, + .num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps, ++ .chroma_format_idc = sps->chroma_format_idc, ++ .sps_max_sub_layers_minus1 = sps->max_sub_layers - 1, + }; + + if (sps->separate_colour_plane_flag) @@ -2839,19 +2876,17 @@ index 000000000000..f72490954653 + av_unused uint32_t size) +{ + const HEVCContext *h = avctx->priv_data; -+ const HEVCSPS *sps = h->ps.sps; + const HEVCPPS *pps = h->ps.pps; -+ const ScalingList *sl = pps->scaling_list_data_present_flag ? -+ &pps->scaling_list : -+ sps->scaling_list_enable_flag ? -+ &sps->scaling_list : NULL; + V4L2RequestControlsHEVC *controls = h->ref->hwaccel_picture_private; + + fill_sps(&controls->sps, h); ++ fill_dec_params(&controls->dec_params, h); + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ + controls->pps = (struct v4l2_ctrl_hevc_pps) { + .num_extra_slice_header_bits = pps->num_extra_slice_header_bits, ++ .num_ref_idx_l0_default_active_minus1 = pps->num_ref_idx_l0_default_active - 1, ++ .num_ref_idx_l1_default_active_minus1 = pps->num_ref_idx_l1_default_active - 1, + .init_qp_minus26 = pps->pic_init_qp_minus26, + .diff_cu_qp_delta_depth = pps->diff_cu_qp_delta_depth, + .pps_cb_qp_offset = pps->cb_qp_offset, @@ -2862,7 +2897,7 @@ index 000000000000..f72490954653 + }; + + if (pps->dependent_slice_segments_enabled_flag) -+ controls->pps.flags |= V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT; ++ controls->pps.flags |= V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED; + + if (pps->output_flag_present_flag) + controls->pps.flags |= V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT; @@ -2918,6 +2953,12 @@ index 000000000000..f72490954653 + if (pps->slice_header_extension_present_flag) + controls->pps.flags |= V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT; + ++ if (pps->deblocking_filter_control_present_flag) ++ controls->pps.flags |= V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT; ++ ++ if (pps->uniform_spacing_flag) ++ controls->pps.flags |= V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING; ++ + if (pps->tiles_enabled_flag) { + controls->pps.num_tile_columns_minus1 = pps->num_tile_columns - 1; + controls->pps.num_tile_rows_minus1 = pps->num_tile_rows - 1; @@ -2953,6 +2994,11 @@ index 000000000000..f72490954653 + .size = sizeof(controls->pps), + }, + { ++ .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS, ++ .ptr = &controls->dec_params, ++ .size = sizeof(controls->dec_params), ++ }, ++ { + .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, + .ptr = &controls->slice_params, + .size = sizeof(controls->slice_params[0]) * FFMAX(FFMIN(controls->num_slices, MAX_SLICES), ctx->max_slices), @@ -2983,7 +3029,7 @@ index 000000000000..f72490954653 + controls->first_slice = 0; + } + -+ v4l2_request_hevc_fill_slice_params(h, &controls->slice_params[slice]); ++ v4l2_request_hevc_fill_slice_params(h, &controls->dec_params, &controls->slice_params[slice]); + + if (ctx->start_code == V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B) { + ret = ff_v4l2_request_append_output_buffer(avctx, h->ref->frame, nalu_slice_start_code, 3); @@ -3087,26 +3133,23 @@ index 000000000000..f72490954653 + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From 298f65eb9d5d1bae35e5940e27641b1674af884d Mon Sep 17 00:00:00 2001 +From 7f7d8dd75d175f9f6944ed334c67380b6b4c8cbf Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 14 Feb 2019 23:20:05 +0100 -Subject: [PATCH 09/19] Add and use private linux v5.13 headers for V4L2 +Subject: [PATCH 09/18] Add and use private linux v5.14 headers for V4L2 request API ctrls Signed-off-by: Jernej Skrabec Signed-off-by: Jonas Karlman --- - configure | 4 +- - libavcodec/hevc-ctrls.h | 212 ++++++++++++++++++++++++++++++++ - libavcodec/mpeg2-ctrls.h | 82 ++++++++++++ - libavcodec/v4l2_request_hevc.c | 1 + - libavcodec/v4l2_request_mpeg2.c | 1 + - 5 files changed, 298 insertions(+), 2 deletions(-) + configure | 2 +- + libavcodec/hevc-ctrls.h | 240 +++++++++++++++++++++++++++++++++ + libavcodec/v4l2_request_hevc.c | 1 + + 3 files changed, 242 insertions(+), 1 deletion(-) create mode 100644 libavcodec/hevc-ctrls.h - create mode 100644 libavcodec/mpeg2-ctrls.h diff --git a/configure b/configure -index 94476afd5df1..b24fb36a26c7 100755 +index 94476afd5df1..e90c9b913dcb 100755 --- a/configure +++ b/configure @@ -2941,7 +2941,7 @@ hevc_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_HEVC" @@ -3118,21 +3161,12 @@ index 94476afd5df1..b24fb36a26c7 100755 hevc_v4l2request_hwaccel_select="hevc_decoder" hevc_vaapi_hwaccel_deps="vaapi VAPictureParameterBufferHEVC" hevc_vaapi_hwaccel_select="hevc_decoder" -@@ -2971,7 +2971,7 @@ mpeg2_dxva2_hwaccel_deps="dxva2" - mpeg2_dxva2_hwaccel_select="mpeg2video_decoder" - mpeg2_nvdec_hwaccel_deps="nvdec" - mpeg2_nvdec_hwaccel_select="mpeg2video_decoder" --mpeg2_v4l2request_hwaccel_deps="v4l2_request mpeg2_v4l2_request" -+mpeg2_v4l2request_hwaccel_deps="v4l2_request" - mpeg2_v4l2request_hwaccel_select="mpeg2video_decoder" - mpeg2_vaapi_hwaccel_deps="vaapi" - mpeg2_vaapi_hwaccel_select="mpeg2video_decoder" diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h new file mode 100644 -index 000000000000..b4cb2ef02f17 +index 000000000000..53c0038c792b --- /dev/null +++ b/libavcodec/hevc-ctrls.h -@@ -0,0 +1,212 @@ +@@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * These are the HEVC state controls for use with stateless HEVC @@ -3154,6 +3188,7 @@ index 000000000000..b4cb2ef02f17 +#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) +#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) +#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012) +#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) +#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) + @@ -3161,6 +3196,7 @@ index 000000000000..b4cb2ef02f17 +#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 +#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 +#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 ++#define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124 + +enum v4l2_mpeg_video_hevc_decode_mode { + V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, @@ -3210,13 +3246,12 @@ index 000000000000..b4cb2ef02f17 + __u8 num_short_term_ref_pic_sets; + __u8 num_long_term_ref_pics_sps; + __u8 chroma_format_idc; -+ -+ __u8 padding; ++ __u8 sps_max_sub_layers_minus1; + + __u64 flags; +}; + -+#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 0) ++#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED (1ULL << 0) +#define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT (1ULL << 1) +#define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED (1ULL << 2) +#define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT (1ULL << 3) @@ -3235,10 +3270,14 @@ index 000000000000..b4cb2ef02f17 +#define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER (1ULL << 16) +#define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT (1ULL << 17) +#define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18) ++#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT (1ULL << 19) ++#define V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING (1ULL << 20) + +struct v4l2_ctrl_hevc_pps { + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ + __u8 num_extra_slice_header_bits; ++ __u8 num_ref_idx_l0_default_active_minus1; ++ __u8 num_ref_idx_l1_default_active_minus1; + __s8 init_qp_minus26; + __u8 diff_cu_qp_delta_depth; + __s8 pps_cb_qp_offset; @@ -3295,6 +3334,7 @@ index 000000000000..b4cb2ef02f17 +#define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6) +#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7) +#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8) ++#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 9) + +struct v4l2_ctrl_hevc_slice_params { + __u32 bit_size; @@ -3325,18 +3365,10 @@ index 000000000000..b4cb2ef02f17 + __u8 pic_struct; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u8 num_active_dpb_entries; + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + -+ __u8 num_rps_poc_st_curr_before; -+ __u8 num_rps_poc_st_curr_after; -+ __u8 num_rps_poc_lt_curr; -+ -+ __u8 padding; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u8 padding[5]; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; @@ -3344,97 +3376,39 @@ index 000000000000..b4cb2ef02f17 + __u64 flags; +}; + -+#endif -diff --git a/libavcodec/mpeg2-ctrls.h b/libavcodec/mpeg2-ctrls.h -new file mode 100644 -index 000000000000..2a4ae6701166 ---- /dev/null -+++ b/libavcodec/mpeg2-ctrls.h -@@ -0,0 +1,82 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ ++#define V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC 0x1 ++#define V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC 0x2 ++#define V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR 0x4 ++ ++struct v4l2_ctrl_hevc_decode_params { ++ __s32 pic_order_cnt_val; ++ __u8 num_active_dpb_entries; ++ struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u8 num_poc_st_curr_before; ++ __u8 num_poc_st_curr_after; ++ __u8 num_poc_lt_curr; ++ __u8 poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u8 poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u8 poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u64 flags; ++}; ++ ++/* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */ ++#define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) +/* -+ * These are the MPEG2 state controls for use with stateless MPEG-2 -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. ++ * V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP - ++ * the number of data (in bits) to skip in the ++ * slice segment header. ++ * If non-IDR, the bits to be skipped go from syntax element "pic_output_flag" ++ * to before syntax element "slice_temporal_mvp_enabled_flag". ++ * If IDR, the skipped bits are just "pic_output_flag" ++ * (separate_colour_plane_flag is not supported). + */ -+ -+#ifndef _MPEG2_CTRLS_H_ -+#define _MPEG2_CTRLS_H_ -+ -+#define V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS (V4L2_CID_CODEC_BASE+250) -+#define V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION (V4L2_CID_CODEC_BASE+251) -+ -+/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS 0x0103 -+#define V4L2_CTRL_TYPE_MPEG2_QUANTIZATION 0x0104 -+ -+#define V4L2_MPEG2_PICTURE_CODING_TYPE_I 1 -+#define V4L2_MPEG2_PICTURE_CODING_TYPE_P 2 -+#define V4L2_MPEG2_PICTURE_CODING_TYPE_B 3 -+#define V4L2_MPEG2_PICTURE_CODING_TYPE_D 4 -+ -+struct v4l2_mpeg2_sequence { -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence header */ -+ __u16 horizontal_size; -+ __u16 vertical_size; -+ __u32 vbv_buffer_size; -+ -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence extension */ -+ __u16 profile_and_level_indication; -+ __u8 progressive_sequence; -+ __u8 chroma_format; -+}; -+ -+struct v4l2_mpeg2_picture { -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Picture header */ -+ __u8 picture_coding_type; -+ -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Picture coding extension */ -+ __u8 f_code[2][2]; -+ __u8 intra_dc_precision; -+ __u8 picture_structure; -+ __u8 top_field_first; -+ __u8 frame_pred_frame_dct; -+ __u8 concealment_motion_vectors; -+ __u8 q_scale_type; -+ __u8 intra_vlc_format; -+ __u8 alternate_scan; -+ __u8 repeat_first_field; -+ __u16 progressive_frame; -+}; -+ -+struct v4l2_ctrl_mpeg2_slice_params { -+ __u32 bit_size; -+ __u32 data_bit_offset; -+ __u64 backward_ref_ts; -+ __u64 forward_ref_ts; -+ -+ struct v4l2_mpeg2_sequence sequence; -+ struct v4l2_mpeg2_picture picture; -+ -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Slice */ -+ __u32 quantiser_scale_code; -+}; -+ -+struct v4l2_ctrl_mpeg2_quantization { -+ /* ISO/IEC 13818-2, ITU-T Rec. H.262: Quant matrix extension */ -+ __u8 load_intra_quantiser_matrix; -+ __u8 load_non_intra_quantiser_matrix; -+ __u8 load_chroma_intra_quantiser_matrix; -+ __u8 load_chroma_non_intra_quantiser_matrix; -+ -+ __u8 intra_quantiser_matrix[64]; -+ __u8 non_intra_quantiser_matrix[64]; -+ __u8 chroma_intra_quantiser_matrix[64]; -+ __u8 chroma_non_intra_quantiser_matrix[64]; -+}; ++#define V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP (V4L2_CID_CODEC_HANTRO_BASE + 0) + +#endif diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index f72490954653..c16f8a868e38 100644 +index d385c2f03615..ad555c3bb836 100644 --- a/libavcodec/v4l2_request_hevc.c +++ b/libavcodec/v4l2_request_hevc.c @@ -19,6 +19,7 @@ @@ -3445,23 +3419,11 @@ index f72490954653..c16f8a868e38 100644 #define MAX_SLICES 16 -diff --git a/libavcodec/v4l2_request_mpeg2.c b/libavcodec/v4l2_request_mpeg2.c -index 88d86cc4c23f..bc251a6fd2c4 100644 ---- a/libavcodec/v4l2_request_mpeg2.c -+++ b/libavcodec/v4l2_request_mpeg2.c -@@ -19,6 +19,7 @@ - #include "hwconfig.h" - #include "mpegvideo.h" - #include "v4l2_request.h" -+#include "mpeg2-ctrls.h" - - typedef struct V4L2RequestControlsMPEG2 { - struct v4l2_ctrl_mpeg2_slice_params slice_params; -From dc55fcd8644515c6986b73ce340ceff4856acc3f Mon Sep 17 00:00:00 2001 +From 838ed5b6317f13d17b5890d769df325a3aaf0c98 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 29 Apr 2019 22:08:59 +0000 -Subject: [PATCH 10/19] HACK: hwcontext_drm: do not require drm device +Subject: [PATCH 10/18] HACK: hwcontext_drm: do not require drm device Signed-off-by: Jonas Karlman --- @@ -3485,19 +3447,19 @@ index 32cbde82ebfa..aa4794c5e665 100644 if (hwctx->fd < 0) return AVERROR(errno); -From 5793e491ca4057fa9baa797e354439c9e67b129a Mon Sep 17 00:00:00 2001 +From 72db468e754b14ea76ad00fea2deaf55f47fac26 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 11/19] WIP: hevc scaling matrix +Subject: [PATCH 11/18] WIP: hevc scaling matrix Signed-off-by: Jernej Skrabec --- libavcodec/hevc-ctrls.h | 11 +++++++++++ - libavcodec/v4l2_request_hevc.c | 22 ++++++++++++++++++++++ - 2 files changed, 33 insertions(+) + libavcodec/v4l2_request_hevc.c | 27 +++++++++++++++++++++++++++ + 2 files changed, 38 insertions(+) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index b4cb2ef02f17..2dc250edaa2f 100644 +index 53c0038c792b..0e5c4a2eecff 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h @@ -19,6 +19,7 @@ @@ -3505,18 +3467,18 @@ index b4cb2ef02f17..2dc250edaa2f 100644 #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) +#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012) #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) - -@@ -26,6 +27,7 @@ +@@ -27,6 +28,7 @@ #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 +#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 + #define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124 enum v4l2_mpeg_video_hevc_decode_mode { - V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -@@ -209,4 +211,13 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -224,6 +226,15 @@ struct v4l2_ctrl_hevc_decode_params { __u64 flags; }; @@ -3529,22 +3491,34 @@ index b4cb2ef02f17..2dc250edaa2f 100644 + __u8 scaling_list_dc_coef_32x32[2]; +}; + - #endif + /* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */ + #define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) + /* diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index c16f8a868e38..f400bf4f3c82 100644 +index ad555c3bb836..b6c191120e44 100644 --- a/libavcodec/v4l2_request_hevc.c +++ b/libavcodec/v4l2_request_hevc.c -@@ -26,6 +26,7 @@ - typedef struct V4L2RequestControlsHEVC { +@@ -27,6 +27,7 @@ typedef struct V4L2RequestControlsHEVC { struct v4l2_ctrl_hevc_sps sps; struct v4l2_ctrl_hevc_pps pps; + struct v4l2_ctrl_hevc_decode_params dec_params; + struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix; struct v4l2_ctrl_hevc_slice_params slice_params[MAX_SLICES]; int first_slice; int num_slices; //TODO: this should be in control -@@ -295,6 +296,22 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, +@@ -318,11 +319,32 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, + { + const HEVCContext *h = avctx->priv_data; + const HEVCPPS *pps = h->ps.pps; ++ const HEVCSPS *sps = h->ps.sps; ++ const ScalingList *sl = pps->scaling_list_data_present_flag ? ++ &pps->scaling_list : ++ sps->scaling_list_enable_flag ? ++ &sps->scaling_list : NULL; + V4L2RequestControlsHEVC *controls = h->ref->hwaccel_picture_private; fill_sps(&controls->sps, h); + fill_dec_params(&controls->dec_params, h); + if (sl) { + for (int i = 0; i < 6; i++) { @@ -3565,9 +3539,9 @@ index c16f8a868e38..f400bf4f3c82 100644 /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ controls->pps = (struct v4l2_ctrl_hevc_pps) { .num_extra_slice_header_bits = pps->num_extra_slice_header_bits, -@@ -398,6 +415,11 @@ static int v4l2_request_hevc_queue_decode(AVCodecContext *avctx, int last_slice) - .ptr = &controls->pps, - .size = sizeof(controls->pps), +@@ -439,6 +461,11 @@ static int v4l2_request_hevc_queue_decode(AVCodecContext *avctx, int last_slice) + .ptr = &controls->dec_params, + .size = sizeof(controls->dec_params), }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, @@ -3578,45 +3552,34 @@ index c16f8a868e38..f400bf4f3c82 100644 .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, .ptr = &controls->slice_params, -From 1b22861c6aebebcc404da0192a1b17bec4e0365d Mon Sep 17 00:00:00 2001 +From fb279e99271bed8ba6bb3a01fad6cf9232567ff8 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 12/19] WIP: hevc segment address +Subject: [PATCH 12/18] WIP: hevc segment address Signed-off-by: Jernej Skrabec --- - libavcodec/hevc-ctrls.h | 5 ++++- + libavcodec/hevc-ctrls.h | 1 + libavcodec/v4l2_request_hevc.c | 3 +++ - 2 files changed, 7 insertions(+), 1 deletion(-) + 2 files changed, 4 insertions(+) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index 2dc250edaa2f..f252286f7d9a 100644 +index 0e5c4a2eecff..42ad0fe81e66 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h -@@ -167,6 +167,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u32 bit_size; - __u32 data_bit_offset; - -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; -+ - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; - __u8 nuh_temporal_id_plus1; -@@ -200,7 +203,7 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; - -- __u8 padding; -+ __u8 padding[5]; +@@ -198,6 +198,7 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 pic_struct; /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u32 slice_segment_addr; + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index f400bf4f3c82..98222fc74c36 100644 +index b6c191120e44..f645c538c25c 100644 --- a/libavcodec/v4l2_request_hevc.c +++ b/libavcodec/v4l2_request_hevc.c -@@ -138,6 +138,9 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, +@@ -188,6 +188,9 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, .bit_size = 0, .data_bit_offset = get_bits_count(&h->HEVClc->gb), @@ -3627,45 +3590,37 @@ index f400bf4f3c82..98222fc74c36 100644 .nal_unit_type = h->nal_unit_type, .nuh_temporal_id_plus1 = h->temporal_id + 1, -From 19d9b2cf64743085edf06be00a3924384f13f4dc Mon Sep 17 00:00:00 2001 +From 55a85bb6be2b1661c4830b5d085e5657579436a4 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 13/19] WIP: hevc entry point offsets +Subject: [PATCH 13/18] WIP: hevc entry point offsets Signed-off-by: Jernej Skrabec --- - libavcodec/hevc-ctrls.h | 5 ++++- + libavcodec/hevc-ctrls.h | 4 +++- libavcodec/v4l2_request_hevc.c | 9 +++++++++ - 2 files changed, 13 insertions(+), 1 deletion(-) + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index f252286f7d9a..eb83c1d61b8d 100644 +index 42ad0fe81e66..a24916603017 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h -@@ -169,6 +169,7 @@ struct v4l2_ctrl_hevc_slice_params { - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - __u32 slice_segment_addr; -+ __u32 num_entry_point_offsets; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; -@@ -203,7 +204,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; +@@ -202,7 +202,9 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 padding[5]; -+ __u8 padding; -+ ++ __u32 num_entry_point_offsets; + __u32 entry_point_offset_minus1[256]; ++ __u8 padding[8]; - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index 98222fc74c36..7e77c83e4e4b 100644 +index f645c538c25c..601202a77d7a 100644 --- a/libavcodec/v4l2_request_hevc.c +++ b/libavcodec/v4l2_request_hevc.c -@@ -225,6 +225,15 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, +@@ -256,6 +256,15 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, } v4l2_request_hevc_fill_pred_table(h, &slice_params->pred_weight_table); @@ -3682,10 +3637,10 @@ index 98222fc74c36..7e77c83e4e4b 100644 static void fill_sps(struct v4l2_ctrl_hevc_sps *ctrl, const HEVCContext *h) -From 0aab6ac62a36c7f2c439e3182abc501aa70b19ea Mon Sep 17 00:00:00 2001 +From 4c1dd736399c6c4f0dbc5510616b16773b892832 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 12 Dec 2019 16:13:55 +0100 -Subject: [PATCH 14/19] WIP: Add V4L2 request API vp9 hwaccel +Subject: [PATCH 14/18] WIP: Add V4L2 request API vp9 hwaccel Signed-off-by: Boris Brezillon --- @@ -3699,7 +3654,7 @@ Signed-off-by: Boris Brezillon create mode 100644 libavcodec/v4l2_request_vp9.c diff --git a/configure b/configure -index b24fb36a26c7..9acb9235ef7b 100755 +index e90c9b913dcb..33c8ed54679a 100755 --- a/configure +++ b/configure @@ -3015,6 +3015,8 @@ vp9_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_VP9" @@ -4166,10 +4121,10 @@ index 54726df742f9..fee3568736f7 100644 uint8_t pred_prob[3]; struct { -From 324ec7647aa25c85b1dae47b86e11fbc4637ceac Mon Sep 17 00:00:00 2001 +From b4ce2068a1ba8723908fd39c1b2099b286715dde Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 12 Dec 2019 16:13:55 +0100 -Subject: [PATCH 15/19] WIP: Add and use vp9 private linux header +Subject: [PATCH 15/18] WIP: Add and use vp9 private linux header Signed-off-by: Boris Brezillon --- @@ -4180,7 +4135,7 @@ Signed-off-by: Boris Brezillon create mode 100644 libavcodec/vp9-ctrls.h diff --git a/configure b/configure -index 9acb9235ef7b..9942d74f1f09 100755 +index 33c8ed54679a..921e74470145 100755 --- a/configure +++ b/configure @@ -3015,7 +3015,7 @@ vp9_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_VP9" @@ -4696,10 +4651,10 @@ index 000000000000..0cdea8a18b72 + +#endif /* _VP9_CTRLS_H_ */ -From a787b57927be77f29178de8fb00afef0b7468c25 Mon Sep 17 00:00:00 2001 +From 5ba520963c60bb72e9e418a4392724c619e95f89 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 15 May 2020 16:54:05 +0000 -Subject: [PATCH 16/19] WIP: add NV15 and NV20 support +Subject: [PATCH 16/18] WIP: add NV15 and NV20 support Signed-off-by: Jonas Karlman --- @@ -4783,10 +4738,10 @@ index 5234b5049b0d..0b294feff2eb 100644 default: return -1; -From 8de8b20b540b68355e54a6e97b5543d0ae67cda3 Mon Sep 17 00:00:00 2001 +From ea35c24c6c19e90e8a33bf9415cf3b90143221f7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 27 Jul 2020 23:15:45 +0000 -Subject: [PATCH 17/19] HACK: define drm NV15 and NV20 format +Subject: [PATCH 17/18] HACK: define drm NV15 and NV20 format --- libavcodec/v4l2_request.c | 8 ++++++++ @@ -4812,92 +4767,49 @@ index 0b294feff2eb..a8f0ee79eeef 100644 { V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)frame->data[0]; -From b4ef09e9b03a4cdb442d87f5c3951ea406ff09e0 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 11 Apr 2021 08:40:57 +0000 -Subject: [PATCH 18/19] WIP: hevc: slice dependent flag - ---- - libavcodec/hevc-ctrls.h | 1 + - libavcodec/v4l2_request_hevc.c | 3 +++ - 2 files changed, 4 insertions(+) - -diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index eb83c1d61b8d..cd51fb6df1f0 100644 ---- a/libavcodec/hevc-ctrls.h -+++ b/libavcodec/hevc-ctrls.h -@@ -162,6 +162,7 @@ struct v4l2_hevc_pred_weight_table { - #define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6) - #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7) - #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 9) - - struct v4l2_ctrl_hevc_slice_params { - __u32 bit_size; -diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index 7e77c83e4e4b..116a69340af3 100644 ---- a/libavcodec/v4l2_request_hevc.c -+++ b/libavcodec/v4l2_request_hevc.c -@@ -195,6 +195,9 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, - if (sh->slice_loop_filter_across_slices_enabled_flag) - slice_params->flags |= V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED; - -+ if (sh->dependent_slice_segment_flag) -+ slice_params->flags |= V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT; -+ - for (i = 0; i < FF_ARRAY_ELEMS(h->DPB); i++) { - const HEVCFrame *frame = &h->DPB[i]; - if (frame != pic && (frame->flags & (HEVC_FRAME_FLAG_LONG_REF | HEVC_FRAME_FLAG_SHORT_REF))) { - -From 6a200d38c3ff00cfdecd92bb7b7083b590403017 Mon Sep 17 00:00:00 2001 +From 36dbf222487a459156f1752436530b3fae39d35c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 13 May 2020 22:51:21 +0000 -Subject: [PATCH 19/19] WIP: hevc rkvdec fields +Subject: [PATCH 18/18] WIP: hevc rkvdec fields Signed-off-by: Jonas Karlman --- - libavcodec/hevc-ctrls.h | 17 +++++++++++++---- + libavcodec/hevc-ctrls.h | 11 ++++++++++- libavcodec/v4l2_request_hevc.c | 12 ++++++++++++ - 2 files changed, 25 insertions(+), 4 deletions(-) + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index cd51fb6df1f0..4d51c148d0ba 100644 +index a24916603017..cd143526685f 100644 --- a/libavcodec/hevc-ctrls.h +++ b/libavcodec/hevc-ctrls.h -@@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code { +@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { /* The controls are not stable at the moment and will likely be reworked. */ struct v4l2_ctrl_hevc_sps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + __u8 video_parameter_set_id; + __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; __u16 pic_width_in_luma_samples; __u16 pic_height_in_luma_samples; __u8 bit_depth_luma_minus8; -@@ -76,9 +79,9 @@ struct v4l2_ctrl_hevc_sps { - __u8 log2_diff_max_min_pcm_luma_coding_block_size; - __u8 num_short_term_ref_pic_sets; - __u8 num_long_term_ref_pics_sps; -- __u8 chroma_format_idc; +@@ -81,6 +83,9 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; -- __u8 padding; + __u8 num_slices; -+ __u8 padding[6]; - ++ __u8 padding[5]; ++ __u64 flags; }; -@@ -105,7 +108,10 @@ struct v4l2_ctrl_hevc_sps { + +@@ -108,6 +113,7 @@ struct v4l2_ctrl_hevc_sps { struct v4l2_ctrl_hevc_pps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ + __u8 pic_parameter_set_id; __u8 num_extra_slice_header_bits; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; - __s8 init_qp_minus26; - __u8 diff_cu_qp_delta_depth; - __s8 pps_cb_qp_offset; -@@ -118,7 +124,7 @@ struct v4l2_ctrl_hevc_pps { + __u8 num_ref_idx_l0_default_active_minus1; + __u8 num_ref_idx_l1_default_active_minus1; +@@ -123,7 +129,7 @@ struct v4l2_ctrl_hevc_pps { __s8 pps_tc_offset_div2; __u8 log2_parallel_merge_level_minus2; @@ -4906,33 +4818,31 @@ index cd51fb6df1f0..4d51c148d0ba 100644 __u64 flags; }; -@@ -205,7 +211,10 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; +@@ -202,6 +208,9 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -- __u8 padding; + __u16 short_term_ref_pic_set_size; + __u16 long_term_ref_pic_set_size; -+ -+ __u8 padding[5]; - ++ + __u32 num_entry_point_offsets; __u32 entry_point_offset_minus1[256]; - + __u8 padding[8]; diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index 116a69340af3..eb493b309fe9 100644 +index 601202a77d7a..be7838244447 100644 --- a/libavcodec/v4l2_request_hevc.c +++ b/libavcodec/v4l2_request_hevc.c -@@ -169,6 +169,9 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, - .num_rps_poc_st_curr_before = h->rps[ST_CURR_BEF].nb_refs, - .num_rps_poc_st_curr_after = h->rps[ST_CURR_AFT].nb_refs, - .num_rps_poc_lt_curr = h->rps[LT_CURR].nb_refs, +@@ -214,6 +214,9 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */ + .pic_struct = h->sei.picture_timing.picture_struct, + + .short_term_ref_pic_set_size = sh->short_term_ref_pic_set_size, + .long_term_ref_pic_set_size = sh->long_term_ref_pic_set_size, }; if (sh->slice_sample_adaptive_offset_flag[0]) -@@ -242,9 +245,12 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, +@@ -270,9 +273,12 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, static void fill_sps(struct v4l2_ctrl_hevc_sps *ctrl, const HEVCContext *h) { const HEVCSPS *sps = h->ps.sps; @@ -4942,18 +4852,18 @@ index 116a69340af3..eb493b309fe9 100644 *ctrl = (struct v4l2_ctrl_hevc_sps) { + .video_parameter_set_id = sps->vps_id, + .seq_parameter_set_id = pps->sps_id, - .chroma_format_idc = sps->chroma_format_idc, .pic_width_in_luma_samples = sps->width, .pic_height_in_luma_samples = sps->height, -@@ -303,6 +309,7 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, - const HEVCContext *h = avctx->priv_data; - const HEVCSPS *sps = h->ps.sps; - const HEVCPPS *pps = h->ps.pps; -+ const SliceHeader *sh = &h->sh; - const ScalingList *sl = pps->scaling_list_data_present_flag ? + .bit_depth_luma_minus8 = sps->bit_depth - 8, +@@ -336,6 +342,7 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, &pps->scaling_list : sps->scaling_list_enable_flag ? -@@ -329,6 +336,9 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, + &sps->scaling_list : NULL; ++ const SliceHeader *sh = &h->sh; + V4L2RequestControlsHEVC *controls = h->ref->hwaccel_picture_private; + + fill_sps(&controls->sps, h); +@@ -359,6 +366,9 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ controls->pps = (struct v4l2_ctrl_hevc_pps) { @@ -4961,9 +4871,9 @@ index 116a69340af3..eb493b309fe9 100644 + .num_ref_idx_l0_default_active_minus1 = pps->num_ref_idx_l0_default_active - 1, + .num_ref_idx_l1_default_active_minus1 = pps->num_ref_idx_l1_default_active - 1, .num_extra_slice_header_bits = pps->num_extra_slice_header_bits, - .init_qp_minus26 = pps->pic_init_qp_minus26, - .diff_cu_qp_delta_depth = pps->diff_cu_qp_delta_depth, -@@ -445,6 +455,8 @@ static int v4l2_request_hevc_queue_decode(AVCodecContext *avctx, int last_slice) + .num_ref_idx_l0_default_active_minus1 = pps->num_ref_idx_l0_default_active - 1, + .num_ref_idx_l1_default_active_minus1 = pps->num_ref_idx_l1_default_active - 1, +@@ -488,6 +498,8 @@ static int v4l2_request_hevc_queue_decode(AVCodecContext *avctx, int last_slice) if (ctx->decode_mode == V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED) return ff_v4l2_request_decode_slice(avctx, h->ref->frame, control, FF_ARRAY_ELEMS(control), controls->first_slice, last_slice); From 8e5afd4fda76571704a41ce5b791425f891b53cb Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sat, 21 Aug 2021 21:21:57 +1000 Subject: [PATCH 41/51] linux (Allwinner): tidy up .config for 5.14 --- projects/Allwinner/linux/linux.aarch64.conf | 92 +++++++++------------ projects/Allwinner/linux/linux.arm.conf | 2 +- 2 files changed, 39 insertions(+), 55 deletions(-) diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index 2db57a611c..3cff18eff7 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -352,35 +352,33 @@ CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_832075=y +# CONFIG_ARM64_ERRATUM_832075 is not set CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_ARM64_ERRATUM_1418040=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1319367=y -CONFIG_ARM64_ERRATUM_1530923=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_1463225=y -CONFIG_ARM64_ERRATUM_1542419=y -CONFIG_ARM64_ERRATUM_1508412=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23144=y -CONFIG_CAVIUM_ERRATUM_23154=y -CONFIG_CAVIUM_ERRATUM_27456=y -CONFIG_CAVIUM_ERRATUM_30115=y -CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_FUJITSU_ERRATUM_010001=y -CONFIG_HISILICON_ERRATUM_161600802=y -CONFIG_QCOM_FALKOR_ERRATUM_1003=y -CONFIG_QCOM_FALKOR_ERRATUM_1009=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +# CONFIG_ARM64_ERRATUM_1024718 is not set +# CONFIG_ARM64_ERRATUM_1418040 is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1319367 is not set +# CONFIG_ARM64_ERRATUM_1530923 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23144 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set # CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set -CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework CONFIG_ARM64_4K_PAGES=y @@ -430,58 +428,48 @@ CONFIG_KUSER_HELPERS=y # # ARMv8.1 architectural features # -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAN=y +# CONFIG_ARM64_HW_AFDBM is not set +# CONFIG_ARM64_PAN is not set CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y -CONFIG_ARM64_LSE_ATOMICS=y -CONFIG_ARM64_USE_LSE_ATOMICS=y +# CONFIG_ARM64_USE_LSE_ATOMICS is not set # end of ARMv8.1 architectural features # # ARMv8.2 architectural features # # CONFIG_ARM64_PMEM is not set -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_CNP=y +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set # end of ARMv8.2 architectural features # # ARMv8.3 architectural features # -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_PTR_AUTH_KERNEL=y -CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +# CONFIG_ARM64_PTR_AUTH is not set CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_PAC=y -CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # end of ARMv8.3 architectural features # # ARMv8.4 architectural features # -CONFIG_ARM64_AMU_EXTN=y +# CONFIG_ARM64_AMU_EXTN is not set CONFIG_AS_HAS_ARMV8_4=y -CONFIG_ARM64_TLB_RANGE=y +# CONFIG_ARM64_TLB_RANGE is not set # end of ARMv8.4 architectural features # # ARMv8.5 architectural features # -CONFIG_AS_HAS_ARMV8_5=y -CONFIG_ARM64_BTI=y -CONFIG_ARM64_BTI_KERNEL=y -CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y -CONFIG_ARM64_E0PD=y -CONFIG_ARCH_RANDOM=y -CONFIG_ARM64_AS_HAS_MTE=y -CONFIG_ARM64_MTE=y +# CONFIG_ARM64_BTI is not set +# CONFIG_ARM64_E0PD is not set +# CONFIG_ARCH_RANDOM is not set # end of ARMv8.5 architectural features # # ARMv8.7 architectural features # -CONFIG_ARM64_EPAN=y # end of ARMv8.7 architectural features CONFIG_ARM64_SVE=y @@ -611,8 +599,8 @@ CONFIG_CRYPTO_SHA512_ARM64=m CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m +# CONFIG_CRYPTO_SHA3_ARM64 is not set +# CONFIG_CRYPTO_SM3_ARM64_CE is not set # CONFIG_CRYPTO_SM4_ARM64_CE is not set CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m @@ -1391,8 +1379,7 @@ CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y # CONFIG_RFKILL_GPIO is not set -CONFIG_NET_9P=y -# CONFIG_NET_9P_DEBUG is not set +# CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set # CONFIG_NFC is not set @@ -2734,7 +2721,7 @@ CONFIG_POWER_RESET_BRCMSTB=y # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_LTC2952 is not set -# CONFIG_POWER_RESET_REGULATOR is not set +CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_RESET_XGENE=y @@ -6103,9 +6090,6 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -CONFIG_9P_FS=y -# CONFIG_9P_FS_POSIX_ACL is not set -# CONFIG_9P_FS_SECURITY is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index 4c20a3f954..ff024d0501 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -408,7 +408,7 @@ CONFIG_ARM_DMA_MEM_BUFFERABLE=y CONFIG_ARM_HEAVY_MB=y CONFIG_DEBUG_ALIGN_RODATA=y # CONFIG_ARM_ERRATA_430973 is not set -CONFIG_ARM_ERRATA_643719=y +# CONFIG_ARM_ERRATA_643719 is not set # CONFIG_ARM_ERRATA_720789 is not set # CONFIG_ARM_ERRATA_754322 is not set # CONFIG_ARM_ERRATA_754327 is not set From 75fc9df7a93f92958d4a2c21fe143998572b7114 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 09:56:02 +1000 Subject: [PATCH 42/51] linux (NXP iMX8): tidy up .config for 5.14 --- .../NXP/devices/iMX8/linux/linux.aarch64.conf | 406 ++++++++++++------ 1 file changed, 276 insertions(+), 130 deletions(-) diff --git a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf index baeaf98cb2..cdf47bcaa7 100644 --- a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf +++ b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.53 Kernel Configuration +# Linux/arm64 5.14.0-rc6 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103" CONFIG_CC_IS_GCC=y @@ -59,7 +59,6 @@ CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -77,6 +76,19 @@ CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -142,6 +154,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y # CONFIG_CGROUP_PERF is not set CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -174,7 +187,6 @@ CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_BPF=y CONFIG_EXPERT=y # CONFIG_UID16 is not set CONFIG_MULTIUSER=y @@ -202,9 +214,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -223,7 +232,6 @@ CONFIG_PERF_EVENTS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -257,10 +265,7 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_ZONE_DMA32=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -272,10 +277,11 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # Platform selection # # CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_AGILEX is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set # CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set @@ -297,7 +303,7 @@ CONFIG_ARCH_MXC=y # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set @@ -307,7 +313,6 @@ CONFIG_ARCH_MXC=y # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set # end of Platform selection @@ -326,27 +331,29 @@ CONFIG_ARM64_ERRATUM_819472=y # CONFIG_ARM64_ERRATUM_832075 is not set CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y # CONFIG_ARM64_ERRATUM_1024718 is not set -CONFIG_ARM64_ERRATUM_1418040=y +# CONFIG_ARM64_ERRATUM_1418040 is not set CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y # CONFIG_ARM64_ERRATUM_1165522 is not set CONFIG_ARM64_ERRATUM_1319367=y -CONFIG_ARM64_ERRATUM_1530923=y +# CONFIG_ARM64_ERRATUM_1530923 is not set # CONFIG_ARM64_ERRATUM_1286807 is not set -CONFIG_ARM64_ERRATUM_1463225=y -CONFIG_ARM64_ERRATUM_1542419=y -CONFIG_ARM64_ERRATUM_1508412=y +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set # CONFIG_CAVIUM_ERRATUM_22375 is not set # CONFIG_CAVIUM_ERRATUM_23154 is not set # CONFIG_CAVIUM_ERRATUM_27456 is not set # CONFIG_CAVIUM_ERRATUM_30115 is not set -CONFIG_CAVIUM_TX2_ERRATUM_219=y +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set # CONFIG_FUJITSU_ERRATUM_010001 is not set # CONFIG_HISILICON_ERRATUM_161600802 is not set # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set # CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set # CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework @@ -365,24 +372,15 @@ CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_NR_CPUS=8 CONFIG_HOTPLUG_CPU=y # CONFIG_NUMA is not set -CONFIG_HOLES_IN_ZONE=y # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set CONFIG_HZ_300=y # CONFIG_HZ_1000 is not set CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HW_PERF_EVENTS=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_KEXEC is not set @@ -406,16 +404,14 @@ CONFIG_SETEND_EMULATION=y # # CONFIG_ARM64_HW_AFDBM is not set # CONFIG_ARM64_PAN is not set +CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y -CONFIG_ARM64_LSE_ATOMICS=y -CONFIG_ARM64_USE_LSE_ATOMICS=y -# CONFIG_ARM64_VHE is not set +# CONFIG_ARM64_USE_LSE_ATOMICS is not set # end of ARMv8.1 architectural features # # ARMv8.2 architectural features # -# CONFIG_ARM64_UAO is not set # CONFIG_ARM64_PMEM is not set # CONFIG_ARM64_RAS_EXTN is not set # CONFIG_ARM64_CNP is not set @@ -424,7 +420,7 @@ CONFIG_ARM64_USE_LSE_ATOMICS=y # # ARMv8.3 architectural features # -CONFIG_ARM64_PTR_AUTH=y +# CONFIG_ARM64_PTR_AUTH is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_PAC=y @@ -434,23 +430,27 @@ CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # # ARMv8.4 architectural features # -CONFIG_ARM64_AMU_EXTN=y +# CONFIG_ARM64_AMU_EXTN is not set CONFIG_AS_HAS_ARMV8_4=y -CONFIG_ARM64_TLB_RANGE=y +# CONFIG_ARM64_TLB_RANGE is not set # end of ARMv8.4 architectural features # # ARMv8.5 architectural features # -CONFIG_ARM64_BTI=y -CONFIG_ARM64_BTI_KERNEL=y +CONFIG_AS_HAS_ARMV8_5=y +# CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y -CONFIG_ARM64_E0PD=y -CONFIG_ARCH_RANDOM=y +# CONFIG_ARM64_E0PD is not set +# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y -CONFIG_ARM64_MTE=y # end of ARMv8.5 architectural features +# +# ARMv8.7 architectural features +# +# end of ARMv8.7 architectural features + CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set @@ -468,7 +468,6 @@ CONFIG_CMDLINE="" # end of Boot options CONFIG_SYSVIPC_COMPAT=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management options @@ -553,8 +552,9 @@ CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_ARM_SDE_INTERFACE is not set # CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_ARM_FFA_TRANSPORT is not set # CONFIG_GOOGLE_FIRMWARE is not set -# CONFIG_IMX_DSP is not set +CONFIG_IMX_DSP=m CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y CONFIG_ARM_PSCI_FW=y @@ -575,7 +575,7 @@ CONFIG_CRYPTO_SHA256_ARM64=y CONFIG_CRYPTO_SHA512_ARM64=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y -# CONFIG_CRYPTO_SHA512_ARM64_CE is not set +CONFIG_CRYPTO_SHA512_ARM64_CE=m # CONFIG_CRYPTO_SHA3_ARM64 is not set # CONFIG_CRYPTO_SM3_ARM64_CE is not set # CONFIG_CRYPTO_SM4_ARM64_CE is not set @@ -593,7 +593,6 @@ CONFIG_CRYPTO_AES_ARM64_BS=y # # General architecture-dependent options # -CONFIG_SET_FS=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -611,6 +610,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y @@ -631,16 +631,23 @@ CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y @@ -655,6 +662,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -664,6 +673,7 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -688,9 +698,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -704,6 +717,7 @@ CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -829,9 +843,6 @@ CONFIG_COREDUMP=y # # Memory Management options # -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y @@ -839,14 +850,17 @@ CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_COMPACTION=y # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y @@ -859,19 +873,21 @@ CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 # CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y -CONFIG_FRAME_VECTOR=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options @@ -989,7 +1005,7 @@ CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_NETLINK_LOG=m # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m -# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_LOG_SYSLOG is not set # CONFIG_NF_CONNTRACK_MARK is not set # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y @@ -1020,6 +1036,7 @@ CONFIG_NF_NAT_SIP=m CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1180,7 +1197,7 @@ CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set @@ -1261,14 +1278,15 @@ CONFIG_DNS_RESOLVER=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1291,6 +1309,7 @@ CONFIG_BT_HS=y CONFIG_BT_LE=y # CONFIG_BT_LEDS is not set # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set # CONFIG_BT_SELFTEST is not set @@ -1359,7 +1378,6 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1373,10 +1391,11 @@ CONFIG_RFKILL_GPIO=m # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1492,6 +1511,7 @@ CONFIG_MTD_CFI_I2=y # # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -1514,6 +1534,8 @@ CONFIG_MTD_CFI_I2=y # # ECC engine support # +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -1525,6 +1547,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_MTD_UBI is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y @@ -1582,7 +1607,6 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1611,6 +1635,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1683,12 +1708,6 @@ CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m # CONFIG_NLMON is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_ALTERA_TSE is not set @@ -1696,7 +1715,6 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_AMD is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set @@ -1708,10 +1726,12 @@ CONFIG_FEC=y # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_XGMAC_MDIO is not set # CONFIG_GIANFAR is not set +# CONFIG_FSL_ENETC_IERB is not set CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1742,6 +1762,7 @@ CONFIG_DWMAC_IMX8=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set CONFIG_PHYLINK=y @@ -1757,7 +1778,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -1772,11 +1793,15 @@ CONFIG_FIXED_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set CONFIG_AT803X_PHY=y # CONFIG_QSEMI_PHY is not set @@ -1796,6 +1821,7 @@ CONFIG_SMSC_PHY=m # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y @@ -1861,8 +1887,8 @@ CONFIG_USB_IPHETH=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ATH_COMMON=m CONFIG_WLAN_VENDOR_ATH=y @@ -1999,11 +2025,14 @@ CONFIG_ZD1211RW=m # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Wireless WAN # -# CONFIG_WAN is not set +# CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set @@ -2015,7 +2044,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set @@ -2107,6 +2135,7 @@ CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_JOYSTICK_PSXPAD_SPI=m CONFIG_JOYSTICK_PSXPAD_SPI_FF=y # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2133,9 +2162,11 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_RK805_PWRKEY is not set CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -2227,9 +2258,9 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set @@ -2242,7 +2273,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y @@ -2257,12 +2287,11 @@ CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y -# CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices -# CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # @@ -2319,6 +2348,7 @@ CONFIG_I2C_IMX_LPI2C=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2422,6 +2452,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_RK805 is not set # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set CONFIG_PINCTRL_IMX=y CONFIG_PINCTRL_IMX_SCU=y CONFIG_PINCTRL_IMX8MM=y @@ -2488,6 +2519,7 @@ CONFIG_GPIO_MXC=y # MFD GPIO expanders # # CONFIG_GPIO_ARIZONA is not set +# CONFIG_GPIO_WM8994 is not set # end of MFD GPIO expanders # @@ -2506,14 +2538,20 @@ CONFIG_GPIO_MXC=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMSTB is not set CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET_SYSCON=y @@ -2542,6 +2580,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set @@ -2550,8 +2589,10 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set @@ -2579,6 +2620,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2586,6 +2628,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2607,6 +2650,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2614,6 +2658,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2628,6 +2673,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2654,13 +2700,16 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set @@ -2728,6 +2777,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -2822,8 +2872,10 @@ CONFIG_MFD_CROS_EC_DEV=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set CONFIG_MFD_RK808=y @@ -2832,7 +2884,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -2861,7 +2912,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TC3589X is not set # CONFIG_MFD_TQMX86 is not set # CONFIG_MFD_LOCHNAGAR is not set -CONFIG_MFD_ARIZONA=y +CONFIG_MFD_ARIZONA=m CONFIG_MFD_ARIZONA_I2C=m CONFIG_MFD_ARIZONA_SPI=m # CONFIG_MFD_CS47L24 is not set @@ -2873,12 +2924,15 @@ CONFIG_MFD_WM5102=y # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set +CONFIG_MFD_WM8994=y CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -2896,6 +2950,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_ARIZONA_MICSUPP is not set # CONFIG_REGULATOR_BD718XX is not set # CONFIG_REGULATOR_CROS_EC is not set +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set @@ -2912,6 +2967,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -2922,6 +2978,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -2930,6 +2987,8 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set # CONFIG_REGULATOR_RK808 is not set # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set @@ -2945,6 +3004,7 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set +# CONFIG_REGULATOR_WM8994 is not set CONFIG_RC_CORE=m CONFIG_RC_MAP=m CONFIG_LIRC=y @@ -3020,6 +3080,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_JPEG_HELPER=m CONFIG_V4L2_H264=m CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_VIDEOBUF_GEN=m @@ -3051,7 +3112,6 @@ CONFIG_DVB_MAX_ADAPTERS=8 # # Media drivers # -CONFIG_TTPCI_EEPROM=m CONFIG_MEDIA_USB_SUPPORT=y # @@ -3166,6 +3226,7 @@ CONFIG_MEDIA_COMMON_OPTIONS=y # CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m @@ -3179,6 +3240,7 @@ CONFIG_SMS_SIANO_RC=y CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_CODA is not set # CONFIG_VIDEO_IMX_PXP is not set +CONFIG_VIDEO_IMX8_JPEG=m CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m # CONFIG_DVB_PLATFORM_DRIVERS is not set # CONFIG_SDR_PLATFORM_DRIVERS is not set @@ -3308,13 +3370,16 @@ CONFIG_VIDEO_CX25840=m # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3322,6 +3387,7 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3332,6 +3398,7 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3349,12 +3416,13 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3492,7 +3560,6 @@ CONFIG_DVB_TDA10071=m # # DVB-T (terrestrial) frontends # -# CONFIG_DVB_SP8870 is not set # CONFIG_DVB_SP887X is not set # CONFIG_DVB_CX22700 is not set CONFIG_DVB_CX22702=m @@ -3547,6 +3614,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m # # ISDB-T (terrestrial) frontends @@ -3612,7 +3680,6 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 @@ -3650,6 +3717,7 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y @@ -3679,9 +3747,13 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3699,10 +3771,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_CDNS_MHDP=y @@ -3717,10 +3791,11 @@ CONFIG_DRM_IMX_DCSS=y CONFIG_DRM_IMX_CDNS_MHDP=y CONFIG_DRM_ETNAVIV=y CONFIG_DRM_ETNAVIV_THERMAL=y -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -3733,6 +3808,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3814,6 +3890,8 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y CONFIG_SND_DMAENGINE_PCM=y CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y @@ -3845,6 +3923,7 @@ CONFIG_SND_SPI=y # CONFIG_SND_USB is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -3865,6 +3944,8 @@ CONFIG_SND_SOC_FSL_SSI=y CONFIG_SND_SOC_FSL_SPDIF=y CONFIG_SND_SOC_FSL_ESAI=y # CONFIG_SND_SOC_FSL_MICFIL is not set +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_AUD2HTX=y CONFIG_SND_SOC_IMX_PCM_DMA=y CONFIG_SND_SOC_IMX_AUDMUX=y CONFIG_SND_IMX_SOC=y @@ -3877,6 +3958,8 @@ CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_FSL_ASOC_CARD=y CONFIG_SND_SOC_IMX_AUDMIX=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_IMX_CARD=y # end of SoC Audio for Freescale CPUs # CONFIG_SND_I2S_HI6210_I2S is not set @@ -3893,13 +3976,15 @@ CONFIG_SND_SOC_IMX_AUDMIX=y # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # +CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -3908,12 +3993,12 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set -# CONFIG_SND_SOC_AK4458 is not set +CONFIG_SND_SOC_AK4458=y # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set -# CONFIG_SND_SOC_AK5558 is not set +CONFIG_SND_SOC_AK5558=y # CONFIG_SND_SOC_ALC5623 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set @@ -3941,6 +4026,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_CX2072X is not set # CONFIG_SND_SOC_DA7213 is not set # CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y CONFIG_SND_SOC_ES7134=y # CONFIG_SND_SOC_ES7241 is not set # CONFIG_SND_SOC_ES8316 is not set @@ -3968,16 +4054,21 @@ CONFIG_SND_SOC_ES8328_SPI=y # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RK817 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set CONFIG_SND_SOC_SGTL5000=y # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -3994,12 +4085,14 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set @@ -4028,17 +4121,22 @@ CONFIG_SND_SOC_WM8524=y # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set +CONFIG_SND_SOC_WM8994=y # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y @@ -4084,6 +4182,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -4129,11 +4228,13 @@ CONFIG_HID_PENMOUNT=y CONFIG_HID_PETALYNX=y # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set CONFIG_HID_SAMSUNG=y +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=y CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -4171,7 +4272,8 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4211,7 +4313,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y # CONFIG_USB_EHCI_FSL is not set -# CONFIG_USB_EHCI_MXC is not set CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set @@ -4263,7 +4364,7 @@ CONFIG_USB_UAS=m # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_HOST is not set @@ -4274,6 +4375,7 @@ CONFIG_USB_DWC3_DUAL_ROLE=y # Platform Glue Driver Support # CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3_IMX8MP=y CONFIG_USB_DWC2=y # CONFIG_USB_DWC2_HOST is not set @@ -4333,7 +4435,6 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_SERIAL_OPTICON is not set @@ -4342,6 +4443,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -4395,7 +4497,6 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # # USB Peripheral Controller # -# CONFIG_USB_FSL_USB2 is not set # CONFIG_USB_FOTG210_UDC is not set # CONFIG_USB_GR_UDC is not set # CONFIG_USB_R8A66597 is not set @@ -4524,6 +4625,10 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set +# +# Flash and Torch LED drivers +# + # # LED Triggers # @@ -4547,6 +4652,7 @@ CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -4617,7 +4723,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -4631,6 +4736,7 @@ CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232_HWMON=y # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -4669,6 +4775,7 @@ CONFIG_RTC_DRV_SNVS=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -4714,6 +4821,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -4736,9 +4844,9 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTLLIB is not set # CONFIG_RTL8723BS is not set # CONFIG_R8712U is not set @@ -4772,7 +4880,6 @@ CONFIG_STAGING=y # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -4805,6 +4912,7 @@ CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_IMX8M=y +# CONFIG_VIDEO_IMX_MEDIA is not set # # Android @@ -4818,12 +4926,6 @@ CONFIG_VIDEO_HANTRO_IMX8M=y # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set @@ -4842,9 +4944,17 @@ CONFIG_CROS_EC_SYSFS=y CONFIG_CROS_USBPD_NOTIFY=y # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_RK808 is not set # CONFIG_COMMON_CLK_SCPI is not set @@ -4857,7 +4967,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_COMMON_CLK_S2MPS11 is not set -# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_XGENE is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set @@ -4870,6 +4980,7 @@ CONFIG_CLK_IMX8MM=y # CONFIG_CLK_IMX8MP is not set CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -4889,6 +5000,7 @@ CONFIG_TIMER_IMX_SYS_CTR=y CONFIG_MAILBOX=y CONFIG_ARM_MHU=y +# CONFIG_ARM_MHU_V2 is not set CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set @@ -4938,11 +5050,6 @@ CONFIG_IOMMU_DMA=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -4964,6 +5071,12 @@ CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_SOC_IMX8M=y # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -4974,7 +5087,6 @@ CONFIG_SOC_IMX8M=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5001,7 +5113,6 @@ CONFIG_EXTCON=y # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set -# CONFIG_EXTCON_ARIZONA is not set # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set @@ -5010,6 +5121,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y # CONFIG_EXTCON_USBC_CROS_EC is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set CONFIG_IIO=y # CONFIG_IIO_BUFFER is not set @@ -5032,11 +5144,14 @@ CONFIG_IIO=y # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -5050,6 +5165,7 @@ CONFIG_IIO=y # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -5076,7 +5192,6 @@ CONFIG_IIO=y # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set -# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set @@ -5111,7 +5226,9 @@ CONFIG_IIO=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -5129,6 +5246,12 @@ CONFIG_IIO=y # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -5140,7 +5263,8 @@ CONFIG_IIO=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5151,6 +5275,11 @@ CONFIG_IIO=y # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -5176,6 +5305,7 @@ CONFIG_IIO=y # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5279,6 +5409,7 @@ CONFIG_IIO=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5320,6 +5451,7 @@ CONFIG_IIO=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5346,6 +5478,7 @@ CONFIG_IIO=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5414,6 +5547,7 @@ CONFIG_IIO=y # # Proximity and distance sensors # +# CONFIG_CROS_EC_MKBP_PROXIMITY is not set # CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set # CONFIG_MB1232 is not set @@ -5443,6 +5577,7 @@ CONFIG_IIO=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5451,6 +5586,7 @@ CONFIG_IIO=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_CROS_EC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_IMX1 is not set @@ -5475,9 +5611,8 @@ CONFIG_IMX_INTMUX=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set CONFIG_RESET_IMX7=y -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_TI_SYSCON is not set # @@ -5485,6 +5620,7 @@ CONFIG_RESET_IMX7=y # CONFIG_GENERIC_PHY=y # CONFIG_PHY_XGENE is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -5531,6 +5667,7 @@ CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_IMX_OCOTP=y # CONFIG_NVMEM_IMX_OCOTP_SCU is not set # CONFIG_NVMEM_SNVS_LPGPR is not set +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -5635,6 +5772,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -5679,6 +5818,7 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_INODE64 is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y # CONFIG_HUGETLBFS is not set CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y @@ -5733,7 +5873,7 @@ CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y -CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_NFS_V4_1_MIGRATION=y CONFIG_ROOT_NFS=y @@ -5747,6 +5887,7 @@ CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -5891,6 +6032,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -5943,17 +6085,13 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -5970,7 +6108,6 @@ CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set CONFIG_CRYPTO_CHACHA20=y # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -6053,6 +6190,8 @@ CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking +CONFIG_BINARY_PRINTF=y + # # Library routines # @@ -6065,6 +6204,7 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6139,6 +6279,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -6160,9 +6301,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -6172,6 +6314,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6186,16 +6329,16 @@ CONFIG_SYMBOLIC_ERRNAME=y # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 CONFIG_STRIP_ASM_SYMS=y # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -6247,9 +6390,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6298,10 +6444,10 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y # # Debug kernel data structures @@ -6340,7 +6486,6 @@ CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # @@ -6361,6 +6506,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking From f5d7d929e65651ee6d53cf57271bd8255a0e3e44 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 11:35:22 +1000 Subject: [PATCH 43/51] linux (NXP iMX6): tidy up .config for 5.14 --- .../NXP/devices/iMX6/linux/linux.arm.conf | 503 ++++++++++-------- 1 file changed, 282 insertions(+), 221 deletions(-) diff --git a/projects/NXP/devices/iMX6/linux/linux.arm.conf b/projects/NXP/devices/iMX6/linux/linux.arm.conf index ce8d282bd6..483cbefa28 100644 --- a/projects/NXP/devices/iMX6/linux/linux.arm.conf +++ b/projects/NXP/devices/iMX6/linux/linux.arm.conf @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.53 Kernel Configuration +# Linux/arm 5.14.0-rc6 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0" +CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=100200 +CONFIG_GCC_VERSION=100300 CONFIG_LD_VERSION=236010000 CONFIG_CLANG_VERSION=0 CONFIG_LLD_VERSION=0 @@ -84,6 +84,18 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -141,6 +153,7 @@ CONFIG_CGROUPS=y # CONFIG_CGROUP_CPUACCT is not set # CONFIG_CGROUP_PERF is not set CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y # CONFIG_NAMESPACES is not set @@ -168,7 +181,6 @@ CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -195,8 +207,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -252,7 +262,6 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_IOP32X is not set @@ -271,7 +280,7 @@ CONFIG_ARCH_MULTIPLATFORM=y # # CPU Core family selection # -CONFIG_ARCH_MULTI_V6=y +# CONFIG_ARCH_MULTI_V6 is not set CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_MULTI_V6_V7=y # end of Multiple platform selection @@ -284,7 +293,6 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set -# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_DIGICOLOR is not set # CONFIG_ARCH_EXYNOS is not set # CONFIG_ARCH_HIGHBANK is not set @@ -295,12 +303,6 @@ CONFIG_HAVE_IMX_GPC=y CONFIG_HAVE_IMX_MMDC=y CONFIG_HAVE_IMX_SRC=y -# -# ARM1136 platforms -# -# CONFIG_SOC_IMX31 is not set -# CONFIG_SOC_IMX35 is not set - # # Cortex-A platforms # @@ -321,7 +323,6 @@ CONFIG_SOC_IMX6UL=y # CONFIG_SOC_IMX7D is not set # CONFIG_SOC_IMX7ULP is not set # CONFIG_SOC_VF610 is not set -# CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_KEYSTONE is not set # CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_MESON is not set @@ -334,7 +335,6 @@ CONFIG_SOC_IMX6UL=y # # TI OMAP/AM/DM/DRA Family # -# CONFIG_ARCH_OMAP2 is not set # CONFIG_ARCH_OMAP3 is not set # CONFIG_ARCH_OMAP4 is not set # CONFIG_SOC_OMAP5 is not set @@ -343,50 +343,37 @@ CONFIG_SOC_IMX6UL=y # CONFIG_SOC_DRA7XX is not set # end of TI OMAP/AM/DM/DRA Family -# CONFIG_ARCH_OXNAS is not set -# CONFIG_ARCH_PICOXCELL is not set -# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_ROCKCHIP is not set -# CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_TANGO is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_VEXPRESS is not set -# CONFIG_ARCH_WM8750 is not set # CONFIG_ARCH_WM8850 is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQ is not set # # Processor Type # -CONFIG_CPU_V6K=y CONFIG_CPU_V7=y CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_32v6=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV6=y CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V6=y CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V6=y CONFIG_CPU_CACHE_V7=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V6=y CONFIG_CPU_TLB_V7=y CONFIG_CPU_HAS_ASID=y CONFIG_CPU_CP15=y @@ -395,6 +382,7 @@ CONFIG_CPU_CP15_MMU=y # # Processor Features # +# CONFIG_ARM_LPAE is not set CONFIG_ARM_THUMB=y # CONFIG_ARM_THUMBEE is not set CONFIG_ARM_VIRT_EXT=y @@ -407,7 +395,6 @@ CONFIG_CPU_SPECTRE=y CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_KUSER_HELPERS=y CONFIG_VDSO=y -CONFIG_DMA_CACHE_RWFO=y CONFIG_OUTER_CACHE=y CONFIG_OUTER_CACHE_SYNC=y CONFIG_MIGHT_HAVE_CACHE_L2X0=y @@ -423,12 +410,11 @@ CONFIG_ARM_DMA_MEM_BUFFERABLE=y CONFIG_ARM_HEAVY_MB=y CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y CONFIG_DEBUG_ALIGN_RODATA=y -# CONFIG_ARM_ERRATA_411920 is not set # CONFIG_ARM_ERRATA_430973 is not set CONFIG_ARM_ERRATA_643719=y -# CONFIG_ARM_ERRATA_720789 is not set +CONFIG_ARM_ERRATA_720789=y CONFIG_ARM_ERRATA_754322=y -# CONFIG_ARM_ERRATA_754327 is not set +CONFIG_ARM_ERRATA_754327=y CONFIG_ARM_ERRATA_764369=y CONFIG_ARM_ERRATA_775420=y # CONFIG_ARM_ERRATA_798181 is not set @@ -480,13 +466,13 @@ CONFIG_HZ_100=y # CONFIG_HZ_1000 is not set CONFIG_HZ=100 CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set CONFIG_ARM_PATCH_IDIV=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y @@ -637,9 +623,10 @@ CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=y CONFIG_CRYPTO_SHA256_ARM=y CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_BLAKE2S_ARM=y CONFIG_CRYPTO_AES_ARM=y -# CONFIG_CRYPTO_CHACHA20_NEON is not set -# CONFIG_CRYPTO_POLY1305_ARM is not set +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_POLY1305_ARM=m CONFIG_AS_VFP_VMRS_FPINST=y # @@ -648,7 +635,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_SET_FS=y -CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y @@ -672,13 +658,17 @@ CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -# CONFIG_SECCOMP is not set +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -702,6 +692,7 @@ CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling @@ -727,9 +718,12 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -794,7 +788,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 @@ -810,15 +803,15 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +CONFIG_KMAP_LOCAL=y # end of Memory Management options CONFIG_NET=y @@ -907,7 +900,7 @@ CONFIG_NETFILTER_FAMILY_BRIDGE=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NETFILTER_NETLINK_OSF is not set # CONFIG_NF_CONNTRACK is not set -# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_LOG_SYSLOG is not set # CONFIG_NF_TABLES is not set # CONFIG_NETFILTER_XTABLES is not set # end of Core Netfilter Configuration @@ -951,22 +944,25 @@ CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set CONFIG_NET_DSA=y # CONFIG_NET_DSA_TAG_AR9331 is not set # CONFIG_NET_DSA_TAG_BRCM is not set +# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set # CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set +# CONFIG_NET_DSA_TAG_HELLCREEK is not set # CONFIG_NET_DSA_TAG_GSWIP is not set +CONFIG_NET_DSA_TAG_DSA_COMMON=y CONFIG_NET_DSA_TAG_DSA=y CONFIG_NET_DSA_TAG_EDSA=y # CONFIG_NET_DSA_TAG_MTK is not set # CONFIG_NET_DSA_TAG_KSZ is not set # CONFIG_NET_DSA_TAG_RTL4_A is not set -# CONFIG_NET_DSA_TAG_OCELOT is not set # CONFIG_NET_DSA_TAG_QCA is not set # CONFIG_NET_DSA_TAG_LAN9303 is not set # CONFIG_NET_DSA_TAG_SJA1105 is not set # CONFIG_NET_DSA_TAG_TRAILER is not set +# CONFIG_NET_DSA_TAG_XRS700X is not set CONFIG_VLAN_8021Q=y # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_VLAN_8021Q_MVRP is not set @@ -993,14 +989,15 @@ CONFIG_NET_SWITCHDEV=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1013,59 +1010,7 @@ CONFIG_NET_FLOW_LIMIT=y # end of Networking options # CONFIG_HAMRADIO is not set -CONFIG_CAN=y -CONFIG_CAN_RAW=y -CONFIG_CAN_BCM=y -CONFIG_CAN_GW=y -# CONFIG_CAN_J1939 is not set -# CONFIG_CAN_ISOTP is not set - -# -# CAN Device Drivers -# -# CONFIG_CAN_VCAN is not set -# CONFIG_CAN_VXCAN is not set -# CONFIG_CAN_SLCAN is not set -CONFIG_CAN_DEV=y -CONFIG_CAN_CALC_BITTIMING=y -CONFIG_CAN_FLEXCAN=y -# CONFIG_CAN_GRCAN is not set -# CONFIG_CAN_KVASER_PCIEFD is not set -# CONFIG_CAN_TI_HECC is not set -# CONFIG_CAN_C_CAN is not set -# CONFIG_CAN_CC770 is not set -# CONFIG_CAN_IFI_CANFD is not set -# CONFIG_CAN_M_CAN is not set -# CONFIG_CAN_PEAK_PCIEFD is not set -# CONFIG_CAN_RCAR is not set -# CONFIG_CAN_RCAR_CANFD is not set -# CONFIG_CAN_SJA1000 is not set -# CONFIG_CAN_SOFTING is not set - -# -# CAN SPI interfaces -# -# CONFIG_CAN_HI311X is not set -# CONFIG_CAN_MCP251X is not set -# CONFIG_CAN_MCP251XFD is not set -# end of CAN SPI interfaces - -# -# CAN USB interfaces -# -# CONFIG_CAN_8DEV_USB is not set -# CONFIG_CAN_EMS_USB is not set -# CONFIG_CAN_ESD_USB2 is not set -# CONFIG_CAN_GS_USB is not set -# CONFIG_CAN_KVASER_USB is not set -# CONFIG_CAN_MCBA_USB is not set -# CONFIG_CAN_PEAK_USB is not set -# CONFIG_CAN_UCAN is not set -# end of CAN USB interfaces - -# CONFIG_CAN_DEBUG_DEVICES is not set -# end of CAN Device Drivers - +# CONFIG_CAN is not set CONFIG_BT=y CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=m @@ -1076,6 +1021,7 @@ CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set CONFIG_BT_DEBUGFS=y # CONFIG_BT_SELFTEST is not set # CONFIG_BT_FEATURE_DEBUG is not set @@ -1146,7 +1092,6 @@ CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1160,10 +1105,11 @@ CONFIG_RFKILL_INPUT=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y # CONFIG_FAILOVER is not set CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1204,10 +1150,12 @@ CONFIG_PCIE_BUS_DEFAULT=y # PCI controller drivers # # CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_IXP4XX is not set # CONFIG_PCI_HOST_GENERIC is not set # CONFIG_PCIE_XILINX is not set # CONFIG_PCI_V3_SEMI is not set # CONFIG_PCIE_ALTERA is not set +# CONFIG_PCIE_MICROCHIP_HOST is not set # # DesignWare PCI Core Support @@ -1245,14 +1193,14 @@ CONFIG_PCI_IMX6=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set # # Generic Driver Options # -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set @@ -1369,6 +1317,7 @@ CONFIG_MTD_DATAFLASH=y # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set # CONFIG_MTD_DATAFLASH_OTP is not set # CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set CONFIG_MTD_SST25L=y # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -1391,6 +1340,8 @@ CONFIG_MTD_SST25L=y # # ECC engine support # +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -1403,6 +1354,9 @@ CONFIG_MTD_SST25L=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 @@ -1426,7 +1380,6 @@ CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -1471,9 +1424,9 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y CONFIG_SRAM_EXEC=y +# CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1502,15 +1455,14 @@ CONFIG_EEPROM_AT25=y # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_ALTERA_STAPL is not set # CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set +# CONFIG_PVPANIC is not set # end of Misc devices -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - # # SCSI device support # @@ -1659,7 +1611,8 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set -# CONFIG_WIREGUARD is not set +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set # CONFIG_NET_TEAM is not set @@ -1689,12 +1642,13 @@ CONFIG_NLMON=y # CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set # CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y CONFIG_NET_DSA_MV88E6XXX_PTP=y # CONFIG_NET_DSA_MSCC_FELIX is not set # CONFIG_NET_DSA_MSCC_SEVILLE is not set # CONFIG_NET_DSA_AR9331 is not set # CONFIG_NET_DSA_SJA1105 is not set +# CONFIG_NET_DSA_XRS700X_I2C is not set +# CONFIG_NET_DSA_XRS700X_MDIO is not set # CONFIG_NET_DSA_QCA8K is not set # CONFIG_NET_DSA_REALTEK_SMI is not set # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set @@ -1722,6 +1676,7 @@ CONFIG_NET_VENDOR_AMD=y # CONFIG_AMD8111_ETH is not set # CONFIG_PCNET32 is not set CONFIG_NET_VENDOR_AQUANTIA=y +# CONFIG_AQTION is not set CONFIG_NET_VENDOR_ARC=y CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL2 is not set @@ -1729,7 +1684,6 @@ CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set # CONFIG_ALX is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_NET_VENDOR_BROCADE=y # CONFIG_BNA is not set @@ -1765,11 +1719,12 @@ CONFIG_FEC=y # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_XGMAC_MDIO is not set # CONFIG_GIANFAR is not set +# CONFIG_FSL_DPAA2_SWITCH is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_VF is not set +CONFIG_FSL_ENETC_IERB=m # CONFIG_FSL_ENETC_MDIO is not set CONFIG_NET_VENDOR_GOOGLE=y -# CONFIG_GVE is not set CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HIX5HD2_GMAC is not set # CONFIG_HISI_FEMAC is not set @@ -1794,6 +1749,7 @@ CONFIG_IGB_HWMON=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_JME is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y @@ -1881,6 +1837,7 @@ CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5100 is not set # CONFIG_WIZNET_W5300 is not set CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set # CONFIG_FDDI is not set @@ -1898,7 +1855,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=y # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -1913,11 +1870,15 @@ CONFIG_FIXED_PHY=y # CONFIG_LSI_ET1011C_PHY is not set CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set CONFIG_AT803X_PHY=y # CONFIG_QSEMI_PHY is not set @@ -1937,6 +1898,7 @@ CONFIG_SMSC_PHY=y # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y @@ -2007,8 +1969,8 @@ CONFIG_USB_NET_ZAURUS=y # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set # CONFIG_WLAN_VENDOR_ADMTEK is not set # CONFIG_WLAN_VENDOR_ATH is not set CONFIG_WLAN_VENDOR_ATMEL=y @@ -2045,11 +2007,14 @@ CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_MAC80211_HWSIM is not set # CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Wireless WAN # -# CONFIG_WAN is not set +# CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_VMXNET3 is not set # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set @@ -2062,7 +2027,6 @@ CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y @@ -2162,10 +2126,10 @@ CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_PROPERTIES=y CONFIG_TOUCHSCREEN_ADS7846=y # CONFIG_TOUCHSCREEN_AD7877 is not set # CONFIG_TOUCHSCREEN_AD7879 is not set @@ -2190,7 +2154,9 @@ CONFIG_TOUCHSCREEN_EGALAX=y # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_EKTF2127 is not set @@ -2202,6 +2168,7 @@ CONFIG_TOUCHSCREEN_MAX11801=y # CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set CONFIG_TOUCHSCREEN_IMX6UL_TSC=y # CONFIG_TOUCHSCREEN_INEXIO is not set @@ -2259,10 +2226,12 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DA9052_ONKEY is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -2340,7 +2309,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_RP2 is not set @@ -2357,13 +2325,13 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_TTY_PRINTK is not set # CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_HW_RANDOM_BA431 is not set @@ -2372,11 +2340,10 @@ CONFIG_HW_RANDOM_IMX_RNGC=y # CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set -# CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices # CONFIG_RANDOM_TRUST_BOOTLOADER is not set @@ -2460,6 +2427,7 @@ CONFIG_I2C_IMX=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2470,7 +2438,9 @@ CONFIG_I2C_IMX=y # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set -# CONFIG_I2C_SLAVE is not set +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_EEPROM is not set +# CONFIG_I2C_SLAVE_TESTUNIT is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -2544,8 +2514,10 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_KVM is not set # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2560,6 +2532,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set CONFIG_PINCTRL_IMX=y CONFIG_PINCTRL_IMX6Q=y CONFIG_PINCTRL_IMX6SL=y @@ -2632,6 +2605,7 @@ CONFIG_GPIO_PCA953X=y # CONFIG_GPIO_DA9052 is not set # CONFIG_HTC_EGPIO is not set CONFIG_GPIO_STMPE=y +# CONFIG_GPIO_WM8994 is not set # end of MFD GPIO expanders # @@ -2659,8 +2633,13 @@ CONFIG_GPIO_STMPE=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMKONA is not set @@ -2668,6 +2647,7 @@ CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_VERSATILE is not set CONFIG_POWER_RESET_SYSCON=y @@ -2698,6 +2678,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set @@ -2706,8 +2687,10 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set CONFIG_CHARGER_UCS1002=y @@ -2734,12 +2717,14 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set @@ -2765,6 +2750,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2772,6 +2758,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2786,6 +2773,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2812,13 +2800,16 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set @@ -2887,6 +2878,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -2963,6 +2955,7 @@ CONFIG_MFD_MC13XXX_I2C=y # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_PMT is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set @@ -2985,10 +2978,12 @@ CONFIG_MFD_MC13XXX_I2C=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set @@ -2997,7 +2992,6 @@ CONFIG_MFD_MC13XXX_I2C=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set CONFIG_MFD_STMPE=y # @@ -3044,12 +3038,15 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set +CONFIG_MFD_WM8994=y # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set CONFIG_RAVE_SP_CORE=y # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -3064,6 +3061,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set @@ -3080,6 +3078,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -3093,6 +3092,7 @@ CONFIG_REGULATOR_MC13892=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -3100,6 +3100,8 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set @@ -3112,6 +3114,7 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set +# CONFIG_REGULATOR_WM8994 is not set CONFIG_RC_CORE=y CONFIG_RC_MAP=y CONFIG_LIRC=y @@ -3333,6 +3336,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_CODA=y CONFIG_VIDEO_IMX_VDOA=y # CONFIG_VIDEO_IMX_PXP is not set +# CONFIG_VIDEO_IMX8_JPEG is not set CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m # CONFIG_DVB_PLATFORM_DRIVERS is not set # CONFIG_SDR_PLATFORM_DRIVERS is not set @@ -3468,7 +3472,9 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3476,6 +3482,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3486,6 +3493,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3503,12 +3511,13 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3646,7 +3655,6 @@ CONFIG_MEDIA_TUNER_MC44S803=y # # DVB-T (terrestrial) frontends # -# CONFIG_DVB_SP8870 is not set # CONFIG_DVB_SP887X is not set # CONFIG_DVB_CX22700 is not set # CONFIG_DVB_CX22702 is not set @@ -3698,6 +3706,7 @@ CONFIG_MEDIA_TUNER_MC44S803=y # CONFIG_DVB_AU8522_DTV is not set # CONFIG_DVB_AU8522_V4L is not set # CONFIG_DVB_S5H1411 is not set +# CONFIG_DVB_MXL692 is not set # # ISDB-T (terrestrial) frontends @@ -3762,12 +3771,10 @@ CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y -CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 @@ -3811,6 +3818,7 @@ CONFIG_DRM_SCHED=y # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_QXL is not set # CONFIG_DRM_BOCHS is not set +# CONFIG_DRM_VIRTIO_GPU is not set # CONFIG_DRM_FSL_DCU is not set # CONFIG_DRM_STM is not set CONFIG_DRM_PANEL=y @@ -3818,58 +3826,27 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set -# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set -# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set -# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y -# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set -# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set -# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set -# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set -# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set -# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set -# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set -# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set -# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set -# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set -# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set -# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set -# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set -# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set -# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set -# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set -# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set -# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set -# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -3879,9 +3856,13 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3899,10 +3880,12 @@ CONFIG_DRM_TOSHIBA_TC358767=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y @@ -3919,10 +3902,11 @@ CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y CONFIG_DRM_ETNAVIV_THERMAL=y -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -3937,6 +3921,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_PANFROST is not set # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -4155,6 +4140,7 @@ CONFIG_SND_USB_AUDIO=m # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -4176,11 +4162,11 @@ CONFIG_SND_SOC_FSL_SPDIF=y CONFIG_SND_SOC_FSL_ESAI=y # CONFIG_SND_SOC_FSL_MICFIL is not set # CONFIG_SND_SOC_FSL_EASRC is not set -CONFIG_SND_SOC_FSL_UTILS=y +CONFIG_SND_SOC_FSL_XCVR=y +CONFIG_SND_SOC_FSL_AUD2HTX=y CONFIG_SND_SOC_IMX_PCM_DMA=y CONFIG_SND_SOC_IMX_AUDMUX=y CONFIG_SND_IMX_SOC=y -CONFIG_SND_SOC_IMX_SSI=y # # SoC Audio support for Freescale i.MX boards: @@ -4189,9 +4175,10 @@ CONFIG_SND_SOC_EUKREA_TLV320=y CONFIG_SND_SOC_IMX_ES8328=y CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_SPDIF=y -CONFIG_SND_SOC_IMX_MC13783=y CONFIG_SND_SOC_FSL_ASOC_CARD=y # CONFIG_SND_SOC_IMX_AUDMIX is not set +CONFIG_SND_SOC_IMX_HDMI=m +CONFIG_SND_SOC_IMX_CARD=m # end of SoC Audio for Freescale CPUs # CONFIG_SND_I2S_HI6210_I2S is not set @@ -4208,13 +4195,15 @@ CONFIG_SND_SOC_FSL_ASOC_CARD=y # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # +CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -4223,12 +4212,12 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set -# CONFIG_SND_SOC_AK4458 is not set +CONFIG_SND_SOC_AK4458=m # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set -# CONFIG_SND_SOC_AK5558 is not set +CONFIG_SND_SOC_AK5558=m # CONFIG_SND_SOC_ALC5623 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set @@ -4284,16 +4273,20 @@ CONFIG_SND_SOC_ES8328_SPI=y # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set CONFIG_SND_SOC_SGTL5000=y # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set # CONFIG_SND_SOC_SPDIF is not set # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -4310,6 +4303,7 @@ CONFIG_SND_SOC_SGTL5000=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set CONFIG_SND_SOC_TLV320AIC23=y CONFIG_SND_SOC_TLV320AIC23_I2C=y # CONFIG_SND_SOC_TLV320AIC23_SPI is not set @@ -4317,6 +4311,8 @@ CONFIG_SND_SOC_TLV320AIC31XX=y # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set CONFIG_SND_SOC_TLV320AIC3X=y +CONFIG_SND_SOC_TLV320AIC3X_I2C=y +CONFIG_SND_SOC_TLV320AIC3X_SPI=y # CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set @@ -4345,18 +4341,22 @@ CONFIG_SND_SOC_WM8962=y # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set +CONFIG_SND_SOC_WM8994=y # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set -CONFIG_SND_SOC_MC13783=y # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set CONFIG_SND_SOC_TPA6130A2=y +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y @@ -4401,6 +4401,7 @@ CONFIG_HID_APPLE=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set # CONFIG_HID_EZKEY is not set +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -4438,11 +4439,13 @@ CONFIG_HID_OUYA=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=y CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -4479,7 +4482,8 @@ CONFIG_USB_HID=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4517,7 +4521,6 @@ CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=y # CONFIG_USB_EHCI_FSL is not set -CONFIG_USB_EHCI_MXC=y # CONFIG_USB_EHCI_HCD_PLATFORM is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set @@ -4527,7 +4530,6 @@ CONFIG_USB_EHCI_MXC=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_IMX21_HCD is not set # CONFIG_USB_HCD_TEST_MODE is not set # @@ -4568,7 +4570,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -4628,7 +4630,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=m # CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set CONFIG_USB_SERIAL_WWAN=m CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_SERIAL_OMNINET is not set @@ -4638,6 +4639,7 @@ CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -4693,7 +4695,6 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # # USB Peripheral Controller # -CONFIG_USB_FSL_USB2=y # CONFIG_USB_FUSB300 is not set # CONFIG_USB_FOTG210_UDC is not set # CONFIG_USB_GR_UDC is not set @@ -4879,6 +4880,10 @@ CONFIG_LEDS_PWM=y # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set +# +# Flash and Torch LED drivers +# + # # LED Triggers # @@ -4903,6 +4908,7 @@ CONFIG_LEDS_TRIGGER_GPIO=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -4975,7 +4981,6 @@ CONFIG_RTC_DRV_M41T80=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -4988,6 +4993,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -5025,6 +5031,7 @@ CONFIG_RTC_DRV_SNVS=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -5068,6 +5075,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -5092,9 +5100,9 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTL8192U is not set # CONFIG_RTLLIB is not set # CONFIG_RTL8723BS is not set @@ -5131,7 +5139,6 @@ CONFIG_STAGING=y # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -5176,12 +5183,6 @@ CONFIG_STAGING=y # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_QLGE is not set @@ -5190,9 +5191,17 @@ CONFIG_STAGING=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set @@ -5202,7 +5211,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y -# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set @@ -5216,6 +5225,7 @@ CONFIG_CLK_IMX6UL=y # CONFIG_CLK_IMX8MN is not set # CONFIG_CLK_IMX8MP is not set # CONFIG_CLK_IMX8MQ is not set +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -5266,11 +5276,6 @@ CONFIG_IOMMU_SUPPORT=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -5291,6 +5296,12 @@ CONFIG_IMX_GPCV2_PM_DOMAINS=y # CONFIG_SOC_IMX8M is not set # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -5301,7 +5312,6 @@ CONFIG_IMX_GPCV2_PM_DOMAINS=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5319,6 +5329,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y @@ -5348,11 +5359,14 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -5366,6 +5380,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -5427,7 +5442,9 @@ CONFIG_IMX7D_ADC=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set CONFIG_VF610_ADC=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -5445,6 +5462,12 @@ CONFIG_VF610_ADC=y # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -5456,7 +5479,8 @@ CONFIG_VF610_ADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5465,6 +5489,11 @@ CONFIG_VF610_ADC=y # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -5490,6 +5519,7 @@ CONFIG_VF610_ADC=y # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5593,6 +5623,7 @@ CONFIG_VF610_ADC=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5634,6 +5665,7 @@ CONFIG_VF610_ADC=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5660,6 +5692,7 @@ CONFIG_VF610_ADC=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5764,6 +5797,7 @@ CONFIG_MPL3115=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5774,6 +5808,8 @@ CONFIG_MPL3115=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_DWC is not set CONFIG_PWM_FSL_FTM=y # CONFIG_PWM_IMX1 is not set # CONFIG_PWM_IMX27 is not set @@ -5795,14 +5831,14 @@ CONFIG_IMX_INTMUX=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_TI_SYSCON is not set # # PHY Subsystem # # CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -5848,6 +5884,7 @@ CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_IMX_OCOTP=y # CONFIG_NVMEM_SNVS_LPGPR is not set CONFIG_RAVE_SP_EEPROM=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -5888,7 +5925,13 @@ CONFIG_FS_MBCACHE=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set # CONFIG_NILFS2_FS is not set # CONFIG_F2FS_FS is not set CONFIG_FS_POSIX_ACL=y @@ -5959,8 +6002,8 @@ CONFIG_PROC_PAGE_MONITOR=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_TMPFS_XATTR is not set +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=m # end of Pseudo filesystems @@ -6136,6 +6179,7 @@ CONFIG_INIT_STACK_NONE=y # end of Kernel hardening options # end of Security options +CONFIG_XOR_BLOCKS=m CONFIG_CRYPTO=y # @@ -6177,6 +6221,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -6220,8 +6265,8 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set -# CONFIG_CRYPTO_XXHASH is not set -# CONFIG_CRYPTO_BLAKE2B is not set +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m # CONFIG_CRYPTO_BLAKE2S is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_GHASH=y @@ -6229,17 +6274,13 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -6256,7 +6297,6 @@ CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -6298,13 +6338,17 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y -# CONFIG_CRYPTO_LIB_BLAKE2S is not set -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y +CONFIG_CRYPTO_LIB_BLAKE2S=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set @@ -6350,9 +6394,12 @@ CONFIG_BINARY_PRINTF=y # # Library routines # +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y CONFIG_LINEAR_RANGES=y # CONFIG_PACKING is not set CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y @@ -6421,6 +6468,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -6452,9 +6500,10 @@ CONFIG_FONT_8x16=y # CONFIG_FONT_6x8 is not set CONFIG_SG_POOL=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -6464,6 +6513,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6478,14 +6528,14 @@ CONFIG_SYMBOLIC_ERRNAME=y # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -6529,9 +6579,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set +CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6571,6 +6624,11 @@ CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y +CONFIG_LOCKDEP_BITS=15 +CONFIG_LOCKDEP_CHAINS_BITS=16 +CONFIG_LOCKDEP_STACK_TRACE_BITS=19 +CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 +CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 # CONFIG_DEBUG_LOCKDEP is not set # CONFIG_DEBUG_ATOMIC_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set @@ -6580,6 +6638,7 @@ CONFIG_LOCKDEP=y # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -6629,7 +6688,6 @@ CONFIG_TRACING=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # @@ -6658,9 +6716,9 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set +# CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set @@ -6668,10 +6726,12 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set @@ -6695,6 +6755,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking From a917b6bdc15f45ac9b21f1a51631688239ef04db Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 12:02:22 +1000 Subject: [PATCH 44/51] linux (Rockchip RK3288): tidy up .config for 5.14 --- .../RK3288/linux/default/linux.arm.conf | 307 +++++++++++++----- 1 file changed, 232 insertions(+), 75 deletions(-) diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index fdee34267f..7603c8dc79 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.52 Kernel Configuration +# Linux/arm 5.14.0-rc6 Kernel Configuration # # @@ -71,6 +71,18 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -141,6 +153,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -172,7 +185,6 @@ CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y -CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -198,8 +210,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -254,7 +264,6 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_IOP32X is not set @@ -311,7 +320,6 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_SOC_DRA7XX is not set # end of TI OMAP/AM/DM/DRA Family -# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set @@ -319,18 +327,16 @@ CONFIG_ARCH_MULTI_V6_V7=y CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_TANGO is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQ is not set # @@ -442,7 +448,6 @@ CONFIG_AEABI=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y @@ -591,6 +596,8 @@ CONFIG_CRYPTO_SHA1_ARM_NEON=y # CONFIG_CRYPTO_SHA2_ARM_CE is not set CONFIG_CRYPTO_SHA256_ARM=y CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_BLAKE2S_ARM=m +CONFIG_CRYPTO_BLAKE2B_NEON=m CONFIG_CRYPTO_AES_ARM=y CONFIG_CRYPTO_AES_ARM_BS=y # CONFIG_CRYPTO_AES_ARM_CE is not set @@ -631,14 +638,17 @@ CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -662,6 +672,7 @@ CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling @@ -686,10 +697,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y @@ -702,6 +715,7 @@ CONFIG_BLK_CMDLINE_PARSER=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -778,7 +792,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 @@ -794,15 +807,15 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +CONFIG_KMAP_LOCAL=y # end of Memory Management options CONFIG_NET=y @@ -894,23 +907,24 @@ CONFIG_NET_PTP_CLASSIFY=y # CONFIG_ATM is not set # CONFIG_L2TP is not set # CONFIG_BRIDGE is not set -CONFIG_HAVE_NET_DSA=y CONFIG_NET_DSA=m # CONFIG_NET_DSA_TAG_AR9331 is not set CONFIG_NET_DSA_TAG_BRCM_COMMON=m CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +# CONFIG_NET_DSA_TAG_HELLCREEK is not set # CONFIG_NET_DSA_TAG_GSWIP is not set # CONFIG_NET_DSA_TAG_DSA is not set # CONFIG_NET_DSA_TAG_EDSA is not set # CONFIG_NET_DSA_TAG_MTK is not set # CONFIG_NET_DSA_TAG_KSZ is not set # CONFIG_NET_DSA_TAG_RTL4_A is not set -# CONFIG_NET_DSA_TAG_OCELOT is not set # CONFIG_NET_DSA_TAG_QCA is not set # CONFIG_NET_DSA_TAG_LAN9303 is not set # CONFIG_NET_DSA_TAG_SJA1105 is not set # CONFIG_NET_DSA_TAG_TRAILER is not set +# CONFIG_NET_DSA_TAG_XRS700X is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -934,14 +948,15 @@ CONFIG_NET_SWITCHDEV=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -964,6 +979,7 @@ CONFIG_BT_HS=y CONFIG_BT_LE=y # CONFIG_BT_LEDS is not set # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set CONFIG_BT_DEBUGFS=y # CONFIG_BT_SELFTEST is not set @@ -1004,6 +1020,7 @@ CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set CONFIG_BT_MTKUART=m CONFIG_BT_HCIRSI=m +# CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1037,7 +1054,6 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1051,11 +1067,12 @@ CONFIG_RFKILL_GPIO=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1169,6 +1186,7 @@ CONFIG_MTD_CFI_I2=y # # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -1191,6 +1209,8 @@ CONFIG_MTD_CFI_I2=y # # ECC engine support # +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -1203,6 +1223,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 @@ -1269,7 +1292,6 @@ CONFIG_ISL29003=y # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1298,6 +1320,7 @@ CONFIG_EEPROM_93CX6=y # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1388,6 +1411,8 @@ CONFIG_NET_DSA_BCM_SF2=m # CONFIG_NET_DSA_MV88E6XXX is not set # CONFIG_NET_DSA_AR9331 is not set # CONFIG_NET_DSA_SJA1105 is not set +# CONFIG_NET_DSA_XRS700X_I2C is not set +# CONFIG_NET_DSA_XRS700X_MDIO is not set # CONFIG_NET_DSA_QCA8K is not set # CONFIG_NET_DSA_REALTEK_SMI is not set # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set @@ -1402,7 +1427,6 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set @@ -1416,6 +1440,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1475,11 +1500,15 @@ CONFIG_BCM_NET_PHYLIB=m # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set @@ -1568,6 +1597,7 @@ CONFIG_USB_NET_ZAURUS=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ATH_COMMON=m @@ -1663,6 +1693,7 @@ CONFIG_MT76_USB=m CONFIG_MT76_SDIO=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x2_COMMON=m @@ -1722,11 +1753,14 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Wireless WAN # -# CONFIG_WAN is not set +# CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set @@ -1738,7 +1772,6 @@ CONFIG_NET_FAILOVER=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=m @@ -1817,6 +1850,7 @@ CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -1850,12 +1884,14 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_VIBRA is not set CONFIG_INPUT_RK805_PWRKEY=y # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DA9063_ONKEY is not set CONFIG_INPUT_ADXL34X=m CONFIG_INPUT_ADXL34X_I2C=m CONFIG_INPUT_ADXL34X_SPI=m # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -1939,7 +1975,6 @@ CONFIG_SERIAL_BCM63XX=y CONFIG_SERIAL_BCM63XX_CONSOLE=y # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set @@ -1954,7 +1989,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y @@ -1970,10 +2004,9 @@ CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set -# CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices # CONFIG_RANDOM_TRUST_BOOTLOADER is not set @@ -2030,6 +2063,7 @@ CONFIG_I2C_XILINX=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2070,6 +2104,7 @@ CONFIG_SPI_GPIO=m # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=m +# CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_MXIC is not set @@ -2092,6 +2127,7 @@ CONFIG_SPI_SPIDEV=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set # CONFIG_HSI is not set CONFIG_PPS=y # CONFIG_PPS_DEBUG is not set @@ -2134,6 +2170,7 @@ CONFIG_PINCTRL_ROCKCHIP=y CONFIG_PINCTRL_PALMAS=y # CONFIG_PINCTRL_RK805 is not set # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # # Renesas pinctrl drivers @@ -2146,7 +2183,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -2216,8 +2252,13 @@ CONFIG_GPIO_TPS65910=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y @@ -2247,6 +2288,7 @@ CONFIG_BATTERY_CPCAP=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_MAX14577 is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_MAX77693 is not set @@ -2259,10 +2301,12 @@ CONFIG_BATTERY_CPCAP=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_CHARGER_TPS65090 is not set # CONFIG_CHARGER_TPS65217 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set @@ -2291,6 +2335,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2299,6 +2344,7 @@ CONFIG_SENSORS_ARM_SCPI=m # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2320,6 +2366,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2327,6 +2374,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2341,6 +2389,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2367,13 +2416,16 @@ CONFIG_SENSORS_LM90=y # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set @@ -2440,6 +2492,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -2535,9 +2588,11 @@ CONFIG_MFD_MAX8998=y # CONFIG_EZX_PCAP is not set CONFIG_MFD_CPCAP=y # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set CONFIG_MFD_PM8XXX=y +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set CONFIG_MFD_RK808=y @@ -2546,7 +2601,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set CONFIG_MFD_STMPE=y # @@ -2596,9 +2650,12 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_KHADAS_MCU is not set +# CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -2612,6 +2669,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ACT8865=y CONFIG_REGULATOR_ACT8945A=y # CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ARM_SCMI is not set CONFIG_REGULATOR_AS3711=y CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_AXP20X=y @@ -2619,6 +2677,7 @@ CONFIG_REGULATOR_BCM590XX=y CONFIG_REGULATOR_CPCAP=y # CONFIG_REGULATOR_CROS_EC is not set # CONFIG_REGULATOR_DA9063 is not set +# CONFIG_REGULATOR_DA9121 is not set CONFIG_REGULATOR_DA9210=y # CONFIG_REGULATOR_DA9211 is not set CONFIG_REGULATOR_FAN53555=y @@ -2636,6 +2695,7 @@ CONFIG_REGULATOR_MAX14577=m # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set CONFIG_REGULATOR_MAX8907=y # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set @@ -2651,8 +2711,10 @@ CONFIG_REGULATOR_MAX77802=m # CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_MT6315 is not set CONFIG_REGULATOR_PALMAS=y # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -2664,6 +2726,8 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_RN5T618=y # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y @@ -2763,6 +2827,7 @@ CONFIG_V4L2_H264=m CONFIG_V4L2_MEM2MEM_DEV=m # CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m # end of Video4Linux options @@ -2796,7 +2861,6 @@ CONFIG_DVB_MAX_ADAPTERS=16 # # Drivers filtered as selected at 'Filter media drivers' # -CONFIG_TTPCI_EEPROM=m CONFIG_MEDIA_USB_SUPPORT=y # @@ -2975,6 +3039,7 @@ CONFIG_MEDIA_COMMON_OPTIONS=y # CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m @@ -3033,13 +3098,16 @@ CONFIG_VIDEO_CX25840=m # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3047,6 +3115,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3057,6 +3126,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3074,12 +3144,13 @@ CONFIG_VIDEO_MT9V011=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3240,6 +3311,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m # # ISDB-T (terrestrial) frontends @@ -3290,7 +3362,6 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y @@ -3343,6 +3414,7 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y @@ -3372,9 +3444,14 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set +# CONFIG_DRM_CROS_EC_ANX7688 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3392,10 +3469,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y @@ -3406,9 +3485,10 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_STI is not set # CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -3423,6 +3503,7 @@ CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_PANFROST=y # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3549,6 +3630,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -3568,6 +3650,8 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -3593,13 +3677,14 @@ CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -3672,18 +3757,23 @@ CONFIG_SND_SOC_MAX98090=m # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RK817 is not set CONFIG_SND_SOC_RL6231=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set CONFIG_SND_SOC_RT5645=m +# CONFIG_SND_SOC_RT5659 is not set CONFIG_SND_SOC_SGTL5000=m # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=m # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -3700,12 +3790,14 @@ CONFIG_SND_SOC_STI_SAS=m # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_TSCS42XX is not set @@ -3735,21 +3827,26 @@ CONFIG_SND_SOC_TS3A227E=m CONFIG_SND_SOC_WM8978=m # CONFIG_SND_SOC_WM8985 is not set # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y +# CONFIG_SND_VIRTIO is not set # # HID support @@ -3790,6 +3887,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -3835,11 +3933,13 @@ CONFIG_HID_PENMOUNT=y CONFIG_HID_PETALYNX=y # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set CONFIG_HID_SAMSUNG=y +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=y CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -3877,7 +3977,8 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -3968,7 +4069,7 @@ CONFIG_USB_UAS=m # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set CONFIG_USB_MUSB_HDRC=m # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -4260,6 +4361,12 @@ CONFIG_LEDS_MAX8997=m # CONFIG_LEDS_TI_LMU_COMMON is not set # CONFIG_LEDS_SGM3140 is not set +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set + # # LED Triggers # @@ -4283,6 +4390,7 @@ CONFIG_LEDS_TRIGGER_CAMERA=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -4364,7 +4472,6 @@ CONFIG_RTC_DRV_S5M=m # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -4377,6 +4484,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -4414,6 +4522,7 @@ CONFIG_RTC_DRV_CPCAP=m # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -4451,6 +4560,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -4478,9 +4588,9 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m # CONFIG_R8712U is not set @@ -4514,7 +4624,6 @@ CONFIG_RTL8723BS=m # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -4548,7 +4657,6 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_VDEC=m -# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set # # Android @@ -4562,16 +4670,9 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set -# CONFIG_SPMI_HISI3670 is not set # CONFIG_MFD_HI6421_SPMI is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y @@ -4589,9 +4690,17 @@ CONFIG_CROS_EC_SYSFS=m CONFIG_CROS_USBPD_NOTIFY=m # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set CONFIG_COMMON_CLK_MAX77686=y # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_RK808=y @@ -4606,7 +4715,7 @@ CONFIG_COMMON_CLK_SCPI=m # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set CONFIG_COMMON_CLK_S2MPS11=m -CONFIG_CLK_QORIQ=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PALMAS is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set @@ -4618,6 +4727,7 @@ CONFIG_CLK_RK312X=y CONFIG_CLK_RK3188=y CONFIG_CLK_RK322X=y CONFIG_CLK_RK3288=y +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -4632,12 +4742,14 @@ CONFIG_ROCKCHIP_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_GLOBAL_TIMER=y +CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1 CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers CONFIG_MAILBOX=y CONFIG_ARM_MHU=m +# CONFIG_ARM_MHU_V2 is not set CONFIG_PLATFORM_MHU=m # CONFIG_PL320_MBOX is not set CONFIG_ROCKCHIP_MBOX=y @@ -4672,6 +4784,7 @@ CONFIG_ROCKCHIP_IOMMU=y # CONFIG_RPMSG=m # CONFIG_RPMSG_CHAR is not set +CONFIG_RPMSG_NS=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set CONFIG_RPMSG_VIRTIO=m # end of Rpmsg drivers @@ -4687,11 +4800,6 @@ CONFIG_RPMSG_VIRTIO=m # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -4710,6 +4818,12 @@ CONFIG_RPMSG_VIRTIO=m # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -4723,7 +4837,6 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -4762,6 +4875,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set # CONFIG_EXTCON_USBC_CROS_EC is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y @@ -4789,11 +4903,14 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -4807,6 +4924,7 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -4877,7 +4995,9 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set CONFIG_VF610_ADC=m # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -4895,6 +5015,12 @@ CONFIG_VF610_ADC=m # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -4906,7 +5032,8 @@ CONFIG_VF610_ADC=m # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -4917,6 +5044,12 @@ CONFIG_VF610_ADC=m # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# CONFIG_IIO_SCMI is not set +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -4942,6 +5075,7 @@ CONFIG_VF610_ADC=m # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5046,6 +5180,7 @@ CONFIG_MPU3050_I2C=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5087,6 +5222,7 @@ CONFIG_SENSORS_ISL29028=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5113,6 +5249,7 @@ CONFIG_AK8975=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5190,6 +5327,7 @@ CONFIG_IIO_HRTIMER_TRIGGER=y # # Proximity and distance sensors # +# CONFIG_CROS_EC_MKBP_PROXIMITY is not set # CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set # CONFIG_MB1232 is not set @@ -5219,6 +5357,7 @@ CONFIG_IIO_HRTIMER_TRIGGER=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5228,6 +5367,7 @@ CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set CONFIG_PWM_ATMEL_HLCDC_PWM=m +# CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_CROS_EC is not set CONFIG_PWM_FSL_FTM=m # CONFIG_PWM_PCA9685 is not set @@ -5246,8 +5386,7 @@ CONFIG_ARM_GIC_MAX_NR=1 # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set CONFIG_RESET_SCMI=y # CONFIG_RESET_TI_SYSCON is not set @@ -5255,6 +5394,7 @@ CONFIG_RESET_SCMI=y # PHY Subsystem # CONFIG_GENERIC_PHY=y +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -5274,6 +5414,7 @@ CONFIG_PHY_ROCKCHIP_DP=m CONFIG_PHY_ROCKCHIP_EMMC=m CONFIG_PHY_ROCKCHIP_INNO_HDMI=m CONFIG_PHY_ROCKCHIP_INNO_USB2=m +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_PCIE is not set @@ -5308,6 +5449,7 @@ CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_ROCKCHIP_EFUSE=y # CONFIG_ROCKCHIP_OTP is not set +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -5416,6 +5558,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -5499,6 +5643,7 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -5511,7 +5656,6 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_RAM=y -# CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set @@ -5539,6 +5683,7 @@ CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -5552,6 +5697,7 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set @@ -5690,6 +5836,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m @@ -5743,17 +5890,13 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -5770,7 +5913,6 @@ CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -5813,6 +5955,7 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m CONFIG_CRYPTO_LIB_BLAKE2S=m CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y @@ -5935,6 +6078,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -5955,9 +6099,10 @@ CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -5967,6 +6112,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -5984,10 +6130,11 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set # CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set # CONFIG_DEBUG_INFO_BTF is not set # CONFIG_GDB_SCRIPTS is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -6035,9 +6182,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set +CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6083,6 +6233,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -6135,6 +6286,8 @@ CONFIG_FTRACE=y # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_HWLAT_TRACER is not set +# CONFIG_OSNOISE_TRACER is not set +# CONFIG_TIMERLAT_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_FTRACE_SYSCALLS is not set # CONFIG_TRACER_SNAPSHOT is not set @@ -6147,14 +6300,15 @@ CONFIG_BPF_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y # CONFIG_SYNTH_EVENTS is not set +# CONFIG_HIST_TRIGGERS is not set # CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set # CONFIG_TRACE_EVAL_MAP_FILE is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # @@ -6183,9 +6337,9 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set +# CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set @@ -6193,10 +6347,12 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set @@ -6220,6 +6376,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking From 5e84c3cb477ec606e841999fcdb0b582232bb1d3 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 12:02:39 +1000 Subject: [PATCH 45/51] linux (Rockchip RK3328): tidy up .config for 5.14 --- .../RK3328/linux/default/linux.aarch64.conf | 451 ++++++++++++------ 1 file changed, 295 insertions(+), 156 deletions(-) diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf index 663f8bb4e8..92df8aebcc 100644 --- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.52 Kernel Configuration +# Linux/arm64 5.14.0 Kernel Configuration # # @@ -46,7 +46,6 @@ CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -64,6 +63,21 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_JIT_ALWAYS_ON is not set +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -138,6 +152,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -172,7 +187,6 @@ CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -199,11 +213,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_JIT_ALWAYS_ON is not set -CONFIG_BPF_JIT_DEFAULT_ON=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -252,10 +261,7 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_ZONE_DMA32=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -267,10 +273,11 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # Platform selection # # CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_AGILEX is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set # CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set @@ -292,7 +299,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set @@ -302,7 +309,6 @@ CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set # end of Platform selection @@ -318,32 +324,32 @@ CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_832075=y +# CONFIG_ARM64_ERRATUM_832075 is not set CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_ARM64_ERRATUM_1418040=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1319367=y -CONFIG_ARM64_ERRATUM_1530923=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_1463225=y -CONFIG_ARM64_ERRATUM_1542419=y -CONFIG_ARM64_ERRATUM_1508412=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23154=y -CONFIG_CAVIUM_ERRATUM_27456=y -CONFIG_CAVIUM_ERRATUM_30115=y -CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_FUJITSU_ERRATUM_010001=y -CONFIG_HISILICON_ERRATUM_161600802=y -CONFIG_QCOM_FALKOR_ERRATUM_1003=y -CONFIG_QCOM_FALKOR_ERRATUM_1009=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_QCOM_FALKOR_ERRATUM_E1041=y -CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +# CONFIG_ARM64_ERRATUM_1024718 is not set +# CONFIG_ARM64_ERRATUM_1418040 is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1319367 is not set +# CONFIG_ARM64_ERRATUM_1530923 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework CONFIG_ARM64_4K_PAGES=y @@ -361,24 +367,15 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=4 CONFIG_HOTPLUG_CPU=y # CONFIG_NUMA is not set -CONFIG_HOLES_IN_ZONE=y # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set CONFIG_HZ_300=y # CONFIG_HZ_1000 is not set CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HW_PERF_EVENTS=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_KEXEC is not set @@ -397,27 +394,25 @@ CONFIG_KUSER_HELPERS=y # # ARMv8.1 architectural features # -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAN=y +# CONFIG_ARM64_HW_AFDBM is not set +# CONFIG_ARM64_PAN is not set +CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y -CONFIG_ARM64_LSE_ATOMICS=y -CONFIG_ARM64_USE_LSE_ATOMICS=y -CONFIG_ARM64_VHE=y +# CONFIG_ARM64_USE_LSE_ATOMICS is not set # end of ARMv8.1 architectural features # # ARMv8.2 architectural features # -CONFIG_ARM64_UAO=y # CONFIG_ARM64_PMEM is not set -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_CNP=y +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set # end of ARMv8.2 architectural features # # ARMv8.3 architectural features # -CONFIG_ARM64_PTR_AUTH=y +# CONFIG_ARM64_PTR_AUTH is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_PAC=y @@ -427,23 +422,27 @@ CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # # ARMv8.4 architectural features # -CONFIG_ARM64_AMU_EXTN=y +# CONFIG_ARM64_AMU_EXTN is not set CONFIG_AS_HAS_ARMV8_4=y -CONFIG_ARM64_TLB_RANGE=y +# CONFIG_ARM64_TLB_RANGE is not set # end of ARMv8.4 architectural features # # ARMv8.5 architectural features # -CONFIG_ARM64_BTI=y -CONFIG_ARM64_BTI_KERNEL=y +CONFIG_AS_HAS_ARMV8_5=y +# CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y -CONFIG_ARM64_E0PD=y -CONFIG_ARCH_RANDOM=y +# CONFIG_ARM64_E0PD is not set +# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y -CONFIG_ARM64_MTE=y # end of ARMv8.5 architectural features +# +# ARMv8.7 architectural features +# +# end of ARMv8.7 architectural features + CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set @@ -461,8 +460,6 @@ CONFIG_CMDLINE="" # end of Boot options CONFIG_SYSVIPC_COMPAT=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management options @@ -546,6 +543,7 @@ CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_ARM_FFA_TRANSPORT is not set # CONFIG_GOOGLE_FIRMWARE is not set CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set @@ -583,7 +581,6 @@ CONFIG_CRYPTO_AES_ARM64_BS=y # # General architecture-dependent options # -CONFIG_SET_FS=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -601,6 +598,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y @@ -621,16 +619,23 @@ CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y @@ -645,6 +650,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -654,6 +661,8 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -678,10 +687,12 @@ CONFIG_MODVERSIONS=y CONFIG_ASM_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y @@ -694,6 +705,7 @@ CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -818,9 +830,6 @@ CONFIG_COREDUMP=y # # Memory Management options # -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y @@ -828,16 +837,20 @@ CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y @@ -851,20 +864,22 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y -CONFIG_FRAME_VECTOR=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y # end of Memory Management options CONFIG_NET=y @@ -956,8 +971,7 @@ CONFIG_NETFILTER_FAMILY_BRIDGE=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_LOG_SYSLOG=m # CONFIG_NF_CONNTRACK_MARK is not set # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y @@ -983,6 +997,7 @@ CONFIG_NF_NAT=m CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1144,7 +1159,7 @@ CONFIG_STP=m CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set @@ -1170,14 +1185,15 @@ CONFIG_DNS_RESOLVER=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -CONFIG_BPF_JIT=y # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1199,6 +1215,7 @@ CONFIG_BT_HIDP=m # CONFIG_BT_LE is not set CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set # CONFIG_BT_SELFTEST is not set @@ -1239,6 +1256,7 @@ CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set CONFIG_BT_MTKUART=m CONFIG_BT_HCIRSI=m +# CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1271,14 +1289,11 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=y -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -# CONFIG_NET_9P_DEBUG is not set +# CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set # CONFIG_NFC is not set @@ -1287,10 +1302,11 @@ CONFIG_NET_9P_VIRTIO=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1406,6 +1422,7 @@ CONFIG_MTD_CFI_I2=y # # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -1428,6 +1445,8 @@ CONFIG_MTD_CFI_I2=y # # ECC engine support # +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -1439,6 +1458,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_MTD_UBI is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y @@ -1495,7 +1517,6 @@ CONFIG_VIRTIO_BLK=y # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1524,6 +1545,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1595,12 +1617,6 @@ CONFIG_TAP=m CONFIG_VETH=m CONFIG_VIRTIO_NET=y # CONFIG_NLMON is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_ALTERA_TSE is not set @@ -1608,7 +1624,6 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_AMD is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set @@ -1619,6 +1634,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1662,7 +1678,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -1677,11 +1693,15 @@ CONFIG_FIXED_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set @@ -1701,6 +1721,7 @@ CONFIG_SMSC_PHY=m # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y @@ -1773,6 +1794,7 @@ CONFIG_USB_NET_ZAURUS=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ATH_COMMON=m @@ -1866,6 +1888,7 @@ CONFIG_MT76_USB=m CONFIG_MT76_SDIO=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x2_COMMON=m @@ -1925,11 +1948,14 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Wireless WAN # -# CONFIG_WAN is not set +# CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set @@ -1941,7 +1967,6 @@ CONFIG_NET_FAILOVER=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y @@ -2017,6 +2042,7 @@ CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2042,9 +2068,11 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_VIBRA is not set CONFIG_INPUT_RK805_PWRKEY=y # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -2123,9 +2151,9 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set @@ -2139,7 +2167,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y @@ -2154,12 +2181,11 @@ CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y -# CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices -# CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # @@ -2215,6 +2241,7 @@ CONFIG_I2C_RK3X=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2252,6 +2279,7 @@ CONFIG_SPI_GPIO=m # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=m +# CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_MXIC is not set @@ -2274,6 +2302,7 @@ CONFIG_SPI_SPIDEV=m # CONFIG_SPI_SLAVE is not set CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set # CONFIG_HSI is not set CONFIG_PPS=y # CONFIG_PPS_DEBUG is not set @@ -2297,6 +2326,7 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_KVM is not set # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support @@ -2314,6 +2344,7 @@ CONFIG_PINCTRL_ROCKCHIP=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_RK805=y # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # # Renesas pinctrl drivers @@ -2325,7 +2356,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -2389,14 +2419,20 @@ CONFIG_GPIO_MAX77620=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMSTB is not set # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET_SYSCON=y @@ -2427,6 +2463,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set @@ -2435,8 +2472,10 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set @@ -2463,6 +2502,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2470,6 +2510,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2491,6 +2532,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2498,6 +2540,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2512,6 +2555,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2538,13 +2582,16 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set @@ -2611,6 +2658,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -2702,8 +2750,10 @@ CONFIG_MFD_MAX77620=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set CONFIG_MFD_RK808=y @@ -2712,7 +2762,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -2751,9 +2800,12 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_KHADAS_MCU is not set +# CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -2766,6 +2818,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set CONFIG_REGULATOR_FAN53555=y @@ -2783,6 +2836,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX77620 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -2792,7 +2846,9 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_MT6315 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -2803,6 +2859,8 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set @@ -2896,6 +2954,7 @@ CONFIG_V4L2_H264=m CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_V4L2_FLASH_LED_CLASS=m CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m # end of Video4Linux options @@ -2929,7 +2988,6 @@ CONFIG_DVB_MAX_ADAPTERS=16 # # Drivers filtered as selected at 'Filter media drivers' # -CONFIG_TTPCI_EEPROM=m CONFIG_MEDIA_USB_SUPPORT=y # @@ -3058,6 +3116,7 @@ CONFIG_MEDIA_COMMON_OPTIONS=y # CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m @@ -3116,13 +3175,16 @@ CONFIG_VIDEO_CX25840=m # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3130,6 +3192,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3140,6 +3203,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3157,12 +3221,13 @@ CONFIG_VIDEO_MT9V011=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3323,6 +3388,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m # # ISDB-T (terrestrial) frontends @@ -3372,7 +3438,6 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y @@ -3418,6 +3483,7 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set @@ -3447,9 +3513,13 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3467,10 +3537,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y @@ -3480,10 +3552,11 @@ CONFIG_DRM_DW_HDMI_CEC=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -3496,6 +3569,7 @@ CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_LIMA=y # CONFIG_DRM_PANFROST is not set # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3620,6 +3694,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -3639,6 +3714,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -3664,13 +3740,14 @@ CONFIG_SND_SOC_RK3399_GRU_SOUND=m # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -3742,20 +3819,25 @@ CONFIG_SND_SOC_MAX98357A=m # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set CONFIG_SND_SOC_RK3328=y +# CONFIG_SND_SOC_RK817 is not set CONFIG_SND_SOC_RL6231=m CONFIG_SND_SOC_RT5514=m CONFIG_SND_SOC_RT5514_SPI=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set CONFIG_SND_SOC_RT5645=m +# CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -3772,12 +3854,14 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_TSCS42XX is not set @@ -3807,21 +3891,26 @@ CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y +# CONFIG_SND_VIRTIO is not set # # HID support @@ -3862,6 +3951,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -3906,11 +3996,13 @@ CONFIG_HID_PENMOUNT=y CONFIG_HID_PETALYNX=y # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set CONFIG_HID_SAMSUNG=y +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=y CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -3948,7 +4040,8 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4039,7 +4132,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -4281,6 +4374,12 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TI_LMU_COMMON is not set # CONFIG_LEDS_SGM3140 is not set +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set + # # LED Triggers # @@ -4304,6 +4403,7 @@ CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -4380,7 +4480,6 @@ CONFIG_RTC_DRV_S5M=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -4394,6 +4493,7 @@ CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232_HWMON=y # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -4426,6 +4526,7 @@ CONFIG_RTC_DRV_PL031=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -4464,6 +4565,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -4495,9 +4597,9 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m # CONFIG_R8712U is not set @@ -4531,7 +4633,6 @@ CONFIG_RTL8723BS=m # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -4565,7 +4666,6 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_VDEC=m -# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set # # Android @@ -4579,25 +4679,26 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set -# CONFIG_SPMI_HISI3670 is not set # CONFIG_MFD_HI6421_SPMI is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y # CONFIG_CROS_EC is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX77686 is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_RK808=y @@ -4611,17 +4712,19 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_CLK_QORIQ=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_COMMON_CLK_XGENE=y CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y +# CONFIG_CLK_PX30 is not set +# CONFIG_CLK_RK3308 is not set CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y +# CONFIG_CLK_RK3368 is not set +# CONFIG_CLK_RK3399 is not set +# CONFIG_CLK_RK3568 is not set +# CONFIG_XILINX_VCU is not set CONFIG_HWSPINLOCK=y # @@ -4642,6 +4745,7 @@ CONFIG_ARM64_ERRATUM_858921=y CONFIG_MAILBOX=y CONFIG_ARM_MHU=y +CONFIG_ARM_MHU_V2=m CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set CONFIG_ROCKCHIP_MBOX=y @@ -4696,11 +4800,6 @@ CONFIG_ARM_SMMU_V3=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -4719,6 +4818,12 @@ CONFIG_ARM_SMMU_V3=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -4732,7 +4837,6 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -4766,6 +4870,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y +# CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y @@ -4795,11 +4900,14 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -4813,6 +4921,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -4876,7 +4985,9 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -4894,6 +5005,12 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -4905,7 +5022,8 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -4914,6 +5032,11 @@ CONFIG_ROCKCHIP_SARADC=y # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -4939,6 +5062,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5042,6 +5166,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5083,6 +5208,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5109,6 +5235,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5213,6 +5340,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5221,6 +5349,7 @@ CONFIG_ROCKCHIP_SARADC=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y @@ -5240,8 +5369,7 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_TI_SYSCON is not set # @@ -5249,6 +5377,7 @@ CONFIG_RESET_CONTROLLER=y # CONFIG_GENERIC_PHY=y # CONFIG_PHY_XGENE is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -5268,6 +5397,7 @@ CONFIG_PHY_ROCKCHIP_DP=y CONFIG_PHY_ROCKCHIP_EMMC=y CONFIG_PHY_ROCKCHIP_INNO_HDMI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set CONFIG_PHY_ROCKCHIP_INNO_USB3=y # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set CONFIG_PHY_ROCKCHIP_PCIE=m @@ -5306,6 +5436,7 @@ CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_ROCKCHIP_EFUSE=y # CONFIG_ROCKCHIP_OTP is not set +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -5428,6 +5559,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -5473,6 +5606,7 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_INODE64 is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -5515,6 +5649,7 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -5527,7 +5662,6 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_RAM=y -# CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set @@ -5556,6 +5690,7 @@ CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -5569,14 +5704,11 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -CONFIG_9P_FS=y -# CONFIG_9P_FSCACHE is not set -# CONFIG_9P_FS_POSIX_ACL is not set -# CONFIG_9P_FS_SECURITY is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -5657,6 +5789,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set # CONFIG_IMA is not set @@ -5725,6 +5858,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m @@ -5778,17 +5912,13 @@ CONFIG_CRYPTO_POLY1305=m CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -5805,7 +5935,6 @@ CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set CONFIG_CRYPTO_CHACHA20=m # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -5888,6 +6017,8 @@ CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking +CONFIG_BINARY_PRINTF=y + # # Library routines # @@ -5900,6 +6031,7 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -5980,6 +6112,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -6001,9 +6134,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -6013,6 +6147,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6030,10 +6165,11 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set # CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set # CONFIG_DEBUG_INFO_BTF is not set # CONFIG_GDB_SCRIPTS is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -6093,9 +6229,12 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6142,10 +6281,10 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y # # Debug kernel data structures @@ -6184,7 +6323,6 @@ CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y # CONFIG_IO_STRICT_DEVMEM is not set @@ -6206,6 +6344,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking From f99ee721ada76e78dd09bfffc476d577a09982cd Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 13:11:51 +1000 Subject: [PATCH 46/51] linux (Rockchip RK3399): tidy up .config for 5.14 --- .../RK3399/linux/default/linux.aarch64.conf | 506 ++++++++++++------ 1 file changed, 329 insertions(+), 177 deletions(-) diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index b170219168..2660f6b3ea 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.52 Kernel Configuration +# Linux/arm64 5.14.0 Kernel Configuration # # @@ -46,7 +46,6 @@ CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -64,6 +63,21 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_JIT_ALWAYS_ON is not set +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -138,6 +152,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -172,7 +187,6 @@ CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -199,11 +213,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_JIT_ALWAYS_ON is not set -CONFIG_BPF_JIT_DEFAULT_ON=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -251,10 +260,7 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_ZONE_DMA32=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -266,10 +272,11 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # Platform selection # # CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_AGILEX is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set # CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set @@ -291,7 +298,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set @@ -301,7 +308,6 @@ CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set # end of Platform selection @@ -317,32 +323,33 @@ CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_832075=y +# CONFIG_ARM64_ERRATUM_832075 is not set CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +# CONFIG_ARM64_ERRATUM_1024718 is not set +# CONFIG_ARM64_ERRATUM_1418040 is not set CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM64_ERRATUM_1165522=y +# CONFIG_ARM64_ERRATUM_1165522 is not set CONFIG_ARM64_ERRATUM_1319367=y -CONFIG_ARM64_ERRATUM_1530923=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_1463225=y -CONFIG_ARM64_ERRATUM_1542419=y -CONFIG_ARM64_ERRATUM_1508412=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23154=y -CONFIG_CAVIUM_ERRATUM_27456=y -CONFIG_CAVIUM_ERRATUM_30115=y -CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_FUJITSU_ERRATUM_010001=y -CONFIG_HISILICON_ERRATUM_161600802=y -CONFIG_QCOM_FALKOR_ERRATUM_1003=y -CONFIG_QCOM_FALKOR_ERRATUM_1009=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_QCOM_FALKOR_ERRATUM_E1041=y -CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +# CONFIG_ARM64_ERRATUM_1530923 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework CONFIG_ARM64_4K_PAGES=y @@ -360,24 +367,15 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=6 CONFIG_HOTPLUG_CPU=y # CONFIG_NUMA is not set -CONFIG_HOLES_IN_ZONE=y # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set CONFIG_HZ_300=y # CONFIG_HZ_1000 is not set CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HW_PERF_EVENTS=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_KEXEC is not set @@ -396,27 +394,25 @@ CONFIG_KUSER_HELPERS=y # # ARMv8.1 architectural features # -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAN=y +# CONFIG_ARM64_HW_AFDBM is not set +# CONFIG_ARM64_PAN is not set +CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y -CONFIG_ARM64_LSE_ATOMICS=y -CONFIG_ARM64_USE_LSE_ATOMICS=y -CONFIG_ARM64_VHE=y +# CONFIG_ARM64_USE_LSE_ATOMICS is not set # end of ARMv8.1 architectural features # # ARMv8.2 architectural features # -CONFIG_ARM64_UAO=y # CONFIG_ARM64_PMEM is not set -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_CNP=y +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set # end of ARMv8.2 architectural features # # ARMv8.3 architectural features # -CONFIG_ARM64_PTR_AUTH=y +# CONFIG_ARM64_PTR_AUTH is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_PAC=y @@ -426,23 +422,27 @@ CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # # ARMv8.4 architectural features # -CONFIG_ARM64_AMU_EXTN=y +# CONFIG_ARM64_AMU_EXTN is not set CONFIG_AS_HAS_ARMV8_4=y -CONFIG_ARM64_TLB_RANGE=y +# CONFIG_ARM64_TLB_RANGE is not set # end of ARMv8.4 architectural features # # ARMv8.5 architectural features # -CONFIG_ARM64_BTI=y -CONFIG_ARM64_BTI_KERNEL=y +CONFIG_AS_HAS_ARMV8_5=y +# CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y -CONFIG_ARM64_E0PD=y -CONFIG_ARCH_RANDOM=y +# CONFIG_ARM64_E0PD is not set +# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y -CONFIG_ARM64_MTE=y # end of ARMv8.5 architectural features +# +# ARMv8.7 architectural features +# +# end of ARMv8.7 architectural features + CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set @@ -460,8 +460,6 @@ CONFIG_CMDLINE="" # end of Boot options CONFIG_SYSVIPC_COMPAT=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management options @@ -546,6 +544,7 @@ CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_ARM_SDE_INTERFACE is not set # CONFIG_FW_CFG_SYSFS is not set +# CONFIG_ARM_FFA_TRANSPORT is not set # CONFIG_GOOGLE_FIRMWARE is not set CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set @@ -583,7 +582,6 @@ CONFIG_CRYPTO_AES_ARM64_BS=y # # General architecture-dependent options # -CONFIG_SET_FS=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -601,6 +599,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y @@ -621,16 +620,23 @@ CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y @@ -645,6 +651,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -654,6 +662,8 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -677,10 +687,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y @@ -692,7 +704,9 @@ CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_FC_APPID is not set # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -818,9 +832,6 @@ CONFIG_COREDUMP=y # # Memory Management options # -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y @@ -828,16 +839,20 @@ CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y @@ -851,20 +866,22 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y -CONFIG_FRAME_VECTOR=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y # end of Memory Management options CONFIG_NET=y @@ -956,8 +973,7 @@ CONFIG_NETFILTER_FAMILY_BRIDGE=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_LOG_SYSLOG=m # CONFIG_NF_CONNTRACK_MARK is not set # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y @@ -983,6 +999,7 @@ CONFIG_NF_NAT=m CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1144,7 +1161,7 @@ CONFIG_STP=m CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set @@ -1170,14 +1187,15 @@ CONFIG_DNS_RESOLVER=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -CONFIG_BPF_JIT=y # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1199,6 +1217,7 @@ CONFIG_BT_HIDP=m # CONFIG_BT_LE is not set CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set # CONFIG_BT_SELFTEST is not set @@ -1239,6 +1258,7 @@ CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set CONFIG_BT_MTKUART=m CONFIG_BT_HCIRSI=m +# CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1271,14 +1291,11 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=y -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -# CONFIG_NET_9P_DEBUG is not set +# CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set # CONFIG_NFC is not set @@ -1287,10 +1304,11 @@ CONFIG_NET_9P_VIRTIO=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1330,6 +1348,7 @@ CONFIG_PCI_QUIRKS=y # CONFIG_PCI_HOST_THUNDER_ECAM is not set CONFIG_PCIE_ROCKCHIP=y CONFIG_PCIE_ROCKCHIP_HOST=m +# CONFIG_PCIE_MICROCHIP_HOST is not set # # DesignWare PCI Core Support @@ -1344,7 +1363,6 @@ CONFIG_PCIE_ROCKCHIP_HOST=m # # Mobiveil PCIe Core Support # -# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set # end of Mobiveil PCIe Core Support # @@ -1367,6 +1385,7 @@ CONFIG_PCIE_ROCKCHIP_HOST=m # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -1478,6 +1497,7 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_PMC551 is not set # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -1500,6 +1520,8 @@ CONFIG_MTD_CFI_I2=y # # ECC engine support # +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -1511,6 +1533,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_MTD_UBI is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y @@ -1531,13 +1556,11 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set CONFIG_CDROM=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SKD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set @@ -1584,9 +1607,9 @@ CONFIG_NVME_TARGET_FC=m # CONFIG_DS1682 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y +# CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1616,11 +1639,13 @@ CONFIG_EEPROM_93CX6=m CONFIG_ALTERA_STAPL=m # CONFIG_GENWQE is not set # CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1682,6 +1707,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_MPT3SAS is not set # CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set @@ -1690,7 +1716,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_SNIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FDOMAIN_PCI is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set @@ -1841,12 +1866,6 @@ CONFIG_VETH=m CONFIG_VIRTIO_NET=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_NET_VENDOR_3COM=y # CONFIG_VORTEX is not set @@ -1869,7 +1888,6 @@ CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set # CONFIG_ALX is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_NET_VENDOR_BROCADE=y # CONFIG_BNA is not set @@ -1897,6 +1915,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_JME is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set @@ -1952,6 +1971,7 @@ CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_ROCKCHIP=y # CONFIG_DWMAC_INTEL_PLAT is not set +# CONFIG_DWMAC_LOONGSON is not set # CONFIG_STMMAC_PCI is not set CONFIG_NET_VENDOR_SUN=y # CONFIG_HAPPYMEAL is not set @@ -1982,7 +2002,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -1997,11 +2017,15 @@ CONFIG_FIXED_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set @@ -2021,6 +2045,7 @@ CONFIG_SMSC_PHY=m # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y @@ -2094,6 +2119,7 @@ CONFIG_USB_NET_ZAURUS=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y # CONFIG_ADM8211 is not set @@ -2230,6 +2256,7 @@ CONFIG_MT76_USB=m CONFIG_MT76_SDIO=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x0E=m @@ -2243,6 +2270,7 @@ CONFIG_MT7663_USB_SDIO_COMMON=m CONFIG_MT7663U=m CONFIG_MT7663S=m CONFIG_MT7915E=m +# CONFIG_MT7921E is not set CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set @@ -2308,11 +2336,14 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Wireless WAN # -# CONFIG_WAN is not set +# CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_VMXNET3 is not set # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y @@ -2325,7 +2356,6 @@ CONFIG_NET_FAILOVER=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=m # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y @@ -2401,6 +2431,7 @@ CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2426,9 +2457,11 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_VIBRA is not set CONFIG_INPUT_RK805_PWRKEY=y # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -2513,9 +2546,9 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set @@ -2531,7 +2564,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y @@ -2548,13 +2580,12 @@ CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y -# CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices -# CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # @@ -2631,6 +2662,7 @@ CONFIG_I2C_RK3X=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2669,6 +2701,7 @@ CONFIG_SPI_GPIO=m CONFIG_SPI_PL022=y # CONFIG_SPI_PXA2XX is not set CONFIG_SPI_ROCKCHIP=m +# CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_MXIC is not set @@ -2692,6 +2725,7 @@ CONFIG_SPI_SPIDEV=m # CONFIG_SPI_SLAVE is not set CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set # CONFIG_HSI is not set CONFIG_PPS=y # CONFIG_PPS_DEBUG is not set @@ -2715,8 +2749,10 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_KVM is not set # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2732,6 +2768,7 @@ CONFIG_PINCTRL_ROCKCHIP=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_RK805=y # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # # Renesas pinctrl drivers @@ -2743,7 +2780,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -2817,14 +2853,20 @@ CONFIG_GPIO_MAX77620=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMSTB is not set # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET_SYSCON=y @@ -2855,6 +2897,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set @@ -2863,8 +2906,10 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set @@ -2891,6 +2936,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2898,6 +2944,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set @@ -2921,6 +2968,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2928,6 +2976,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2942,6 +2991,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2968,13 +3018,16 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set @@ -3044,6 +3097,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -3133,6 +3187,7 @@ CONFIG_MFD_CORE=y # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_PMT is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set @@ -3155,9 +3210,11 @@ CONFIG_MFD_MAX77620=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set CONFIG_MFD_RK808=y @@ -3166,7 +3223,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -3206,9 +3262,12 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_KHADAS_MCU is not set +# CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -3221,6 +3280,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set CONFIG_REGULATOR_FAN53555=y @@ -3238,6 +3298,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX77620 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -3247,7 +3308,9 @@ CONFIG_REGULATOR_MP8859=y # CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_MT6315 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -3258,6 +3321,8 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set @@ -3351,6 +3416,7 @@ CONFIG_V4L2_H264=m CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_V4L2_FLASH_LED_CLASS=m CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_DMA_SG=m CONFIG_VIDEOBUF_VMALLOC=m @@ -3385,7 +3451,6 @@ CONFIG_DVB_MAX_ADAPTERS=16 # # Drivers filtered as selected at 'Filter media drivers' # -CONFIG_TTPCI_EEPROM=m CONFIG_MEDIA_USB_SUPPORT=y # @@ -3524,9 +3589,6 @@ CONFIG_VIDEO_SAA7164=m # # Media digital TV PCI Adapters # -CONFIG_DVB_AV7110_IR=y -CONFIG_DVB_AV7110=m -# CONFIG_DVB_AV7110_OSD is not set # CONFIG_DVB_BUDGET_CORE is not set # CONFIG_DVB_B2C2_FLEXCOP_PCI is not set # CONFIG_DVB_PLUTO2 is not set @@ -3569,6 +3631,7 @@ CONFIG_MEDIA_COMMON_OPTIONS=y # CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m @@ -3582,7 +3645,13 @@ CONFIG_VIDEO_SAA7146=m CONFIG_VIDEO_SAA7146_VV=m CONFIG_SMS_SIANO_MDTV=m CONFIG_SMS_SIANO_RC=y -# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_CADENCE is not set +# CONFIG_VIDEO_ASPEED is not set +# CONFIG_VIDEO_MUX is not set +CONFIG_VIDEO_ROCKCHIP_ISP1=m +# CONFIG_VIDEO_XILINX is not set CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set CONFIG_VIDEO_ROCKCHIP_IEP=m @@ -3631,13 +3700,16 @@ CONFIG_VIDEO_CX25840=m # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3645,6 +3717,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3655,6 +3728,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3672,12 +3746,13 @@ CONFIG_VIDEO_MT9V011=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3805,7 +3880,6 @@ CONFIG_DVB_TDA10071=m # # DVB-T (terrestrial) frontends # -CONFIG_DVB_SP8870=m CONFIG_DVB_CX22702=m CONFIG_DVB_DRXD=m CONFIG_DVB_L64781=m @@ -3851,6 +3925,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m # # ISDB-T (terrestrial) frontends @@ -3907,7 +3982,6 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y @@ -3947,6 +4021,7 @@ CONFIG_ROCKCHIP_DW_HDMI=y # CONFIG_ROCKCHIP_LVDS is not set # CONFIG_ROCKCHIP_RGB is not set # CONFIG_ROCKCHIP_RK3066_HDMI is not set +# CONFIG_DRM_VMWGFX is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set @@ -3960,6 +4035,7 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set @@ -3989,9 +4065,13 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -4009,10 +4089,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y @@ -4022,12 +4104,13 @@ CONFIG_DRM_DW_HDMI_CEC=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -4040,6 +4123,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_LIMA is not set CONFIG_DRM_PANFROST=y # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -4255,6 +4339,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -4274,6 +4359,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -4299,13 +4385,14 @@ CONFIG_SND_SOC_RK3399_GRU_SOUND=m # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -4377,20 +4464,25 @@ CONFIG_SND_SOC_MAX98357A=m # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set CONFIG_SND_SOC_RK3328=y +# CONFIG_SND_SOC_RK817 is not set CONFIG_SND_SOC_RL6231=m CONFIG_SND_SOC_RT5514=m CONFIG_SND_SOC_RT5514_SPI=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set CONFIG_SND_SOC_RT5645=m +# CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -4407,12 +4499,14 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_TSCS42XX is not set @@ -4442,21 +4536,26 @@ CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y +# CONFIG_SND_VIRTIO is not set # # HID support @@ -4497,6 +4596,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -4541,11 +4641,13 @@ CONFIG_HID_PENMOUNT=y CONFIG_HID_PETALYNX=y # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set CONFIG_HID_SAMSUNG=y +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=y CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -4583,7 +4685,8 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4679,7 +4782,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -4704,7 +4807,7 @@ CONFIG_USB_DWC3_DUAL_ROLE=y # CONFIG_USB_DWC3_HAPS=y CONFIG_USB_DWC3_OF_SIMPLE=y -# CONFIG_USB_DWC3_ROCKCHIP_INNO is not set +CONFIG_USB_DWC3_ROCKCHIP_INNO=m CONFIG_USB_DWC2=y # CONFIG_USB_DWC2_HOST is not set @@ -4835,8 +4938,8 @@ CONFIG_TYPEC_TCPM=m # CONFIG_TYPEC_TCPCI is not set CONFIG_TYPEC_FUSB302=m # CONFIG_TYPEC_UCSI is not set -# CONFIG_TYPEC_HD3SS3220 is not set # CONFIG_TYPEC_TPS6598X is not set +# CONFIG_TYPEC_HD3SS3220 is not set # CONFIG_TYPEC_STUSB160X is not set # @@ -4954,6 +5057,12 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TI_LMU_COMMON is not set # CONFIG_LEDS_SGM3140 is not set +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set + # # LED Triggers # @@ -4978,6 +5087,7 @@ CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -5055,7 +5165,6 @@ CONFIG_RTC_DRV_S5M=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -5069,6 +5178,7 @@ CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232_HWMON=y # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -5101,6 +5211,7 @@ CONFIG_RTC_DRV_PL031=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -5144,6 +5255,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -5177,9 +5289,9 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTL8192U is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m @@ -5216,7 +5328,6 @@ CONFIG_RTL8723BS=m # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -5252,7 +5363,10 @@ CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_VIDEO_ZORAN is not set -# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110=m +# CONFIG_DVB_AV7110_OSD is not set +CONFIG_DVB_SP8870=m # # Android @@ -5266,27 +5380,26 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# CONFIG_STAGING_GASKET_FRAMEWORK is not set -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_QLGE is not set # CONFIG_WFX is not set -# CONFIG_SPMI_HISI3670 is not set # CONFIG_MFD_HI6421_SPMI is not set # CONFIG_GOLDFISH is not set -CONFIG_CHROME_PLATFORMS=y -# CONFIG_CROS_EC is not set +# CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX77686 is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_RK808=y @@ -5300,17 +5413,19 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_CLK_QORIQ=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_COMMON_CLK_XGENE=y CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y +# CONFIG_CLK_PX30 is not set +# CONFIG_CLK_RK3308 is not set +# CONFIG_CLK_RK3328 is not set +# CONFIG_CLK_RK3368 is not set CONFIG_CLK_RK3399=y +# CONFIG_CLK_RK3568 is not set +# CONFIG_XILINX_VCU is not set CONFIG_HWSPINLOCK=y # @@ -5322,15 +5437,15 @@ CONFIG_CLKSRC_MMIO=y CONFIG_ROCKCHIP_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_FSL_ERRATUM_A008585=y -CONFIG_HISILICON_ERRATUM_161010101=y -CONFIG_ARM64_ERRATUM_858921=y +# CONFIG_FSL_ERRATUM_A008585 is not set +# CONFIG_HISILICON_ERRATUM_161010101 is not set +# CONFIG_ARM64_ERRATUM_858921 is not set # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers CONFIG_MAILBOX=y CONFIG_ARM_MHU=y +CONFIG_ARM_MHU_V2=m CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set CONFIG_ROCKCHIP_MBOX=y @@ -5385,11 +5500,6 @@ CONFIG_ARM_SMMU_V3=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -5408,6 +5518,12 @@ CONFIG_ARM_SMMU_V3=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -5421,7 +5537,6 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5439,9 +5554,9 @@ CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # -# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +CONFIG_ARM_RK3399_DMC_DEVFREQ=m CONFIG_PM_DEVFREQ_EVENT=y -# CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y CONFIG_EXTCON=y # @@ -5455,6 +5570,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y +# CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y @@ -5484,11 +5600,14 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -5502,6 +5621,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -5565,7 +5685,9 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -5583,6 +5705,12 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -5594,7 +5722,8 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5603,6 +5732,11 @@ CONFIG_ROCKCHIP_SARADC=y # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -5628,6 +5762,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5731,6 +5866,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5772,6 +5908,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5798,6 +5935,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5902,6 +6040,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5912,6 +6051,8 @@ CONFIG_ROCKCHIP_SARADC=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y @@ -5933,15 +6074,16 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_TI_SYSCON is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y # CONFIG_PHY_XGENE is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -5961,7 +6103,8 @@ CONFIG_PHY_ROCKCHIP_DP=y CONFIG_PHY_ROCKCHIP_EMMC=y CONFIG_PHY_ROCKCHIP_INNO_HDMI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y -# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set +CONFIG_PHY_ROCKCHIP_INNO_USB3=m # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set CONFIG_PHY_ROCKCHIP_PCIE=m CONFIG_PHY_ROCKCHIP_TYPEC=y @@ -5999,7 +6142,8 @@ CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_ROCKCHIP_EFUSE=y -# CONFIG_ROCKCHIP_OTP is not set +CONFIG_ROCKCHIP_OTP=m +CONFIG_NVMEM_RMEM=m # # HW tracing support @@ -6122,6 +6266,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -6167,6 +6313,7 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_INODE64 is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -6209,6 +6356,7 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -6221,7 +6369,6 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_RAM=y -# CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set @@ -6250,6 +6397,7 @@ CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -6263,14 +6411,11 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -CONFIG_9P_FS=y -# CONFIG_9P_FSCACHE is not set -# CONFIG_9P_FS_POSIX_ACL is not set -# CONFIG_9P_FS_SECURITY is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -6351,6 +6496,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set # CONFIG_IMA is not set @@ -6419,6 +6565,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m @@ -6472,17 +6619,13 @@ CONFIG_CRYPTO_POLY1305=m CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -6499,7 +6642,6 @@ CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set CONFIG_CRYPTO_CHACHA20=m # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -6560,7 +6702,7 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_CCP is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set # CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set -# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +CONFIG_CRYPTO_DEV_ROCKCHIP=m CONFIG_CRYPTO_DEV_VIRTIO=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set @@ -6584,6 +6726,8 @@ CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking +CONFIG_BINARY_PRINTF=y + # # Library routines # @@ -6596,6 +6740,7 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6677,6 +6822,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -6698,9 +6844,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -6710,6 +6857,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6727,10 +6875,11 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set # CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set # CONFIG_DEBUG_INFO_BTF is not set # CONFIG_GDB_SCRIPTS is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -6790,9 +6939,12 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6839,10 +6991,10 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y # # Debug kernel data structures @@ -6881,7 +7033,6 @@ CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y # CONFIG_IO_STRICT_DEVMEM is not set @@ -6903,6 +7054,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking From 985b8b7e76dadf2e2a8871d0412d9089180296b5 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 22 Aug 2021 19:07:35 +1000 Subject: [PATCH 47/51] Rockchip: linux: update configs for 5.14 --- .../RK3288/linux/default/linux.arm.conf | 3 +- .../RK3399/linux/default/linux.aarch64.conf | 2 + .../default/linux-1002-for-libreelec.patch | 70 +++++++++++++++++++ 3 files changed, 74 insertions(+), 1 deletion(-) diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index 7603c8dc79..29950f0048 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -1484,7 +1484,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set CONFIG_BCM7XXX_PHY=m @@ -1528,6 +1528,7 @@ CONFIG_SMSC_PHY=m # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_BITBANG is not set diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index 2660f6b3ea..b086ee0250 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -3413,6 +3413,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m CONFIG_V4L2_H264=m +CONFIG_V4L2_VP9=m CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_V4L2_FLASH_LED_CLASS=m CONFIG_V4L2_FWNODE=m @@ -6939,6 +6940,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y diff --git a/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch index 474a2b40bc..1a39f05dc1 100644 --- a/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch @@ -643,3 +643,73 @@ index 3d98e2251ea5..b201700ccc8a 100644 .codec_ops = rk3399_vpu_codec_ops, .irqs = rockchip_vdpu2_irqs, .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: wed, 1 Sep 2021 14:00:00 +1000 +Subject: [PATCH] net: stmmac: dwmac-rk: fix unbalanced pm_runtime_enable warnings + +This LE11 REVERTS 5.14.0 commit +- reverts 2d26f6e39afb88d32b8f39e76a51b542c3c51674 + +BETWEEN THE LINE + +This reverts commit 2c896fb02e7f65299646f295a007bda043e0f382 +"net: stmmac: dwmac-rk: add pd_gmac support for rk3399" and fixes +unbalanced pm_runtime_enable warnings. + +In the commit to be reverted, support for power management was +introduced to the Rockchip glue code. Later, power management support +was introduced to the stmmac core code, resulting in multiple +invocations of pm_runtime_{enable,disable,get_sync,put_sync}. + +The multiple invocations happen in rk_gmac_powerup and +stmmac_{dvr_probe, resume} as well as in rk_gmac_powerdown and +stmmac_{dvr_remove, suspend}, respectively, which are always called +in conjunction. + +Fixes: 5ec55823438e850c91c6b92aec93fb04ebde29e2 ("net: stmmac: add clocks management for gmac driver") +Signed-off-by: Michael Riesch +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 9 --------- + 1 file changed, 9 deletions(-) + +ABOVE THE LINE + +diff -Nu a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + #include "stmmac_platform.h" + +@@ -1528,6 +1529,9 @@ + return ret; + } + ++ pm_runtime_enable(dev); ++ pm_runtime_get_sync(dev); ++ + if (bsp_priv->integrated_phy) + rk_gmac_integrated_phy_powerup(bsp_priv); + +@@ -1536,9 +1540,14 @@ + + static void rk_gmac_powerdown(struct rk_priv_data *gmac) + { ++ struct device *dev = &gmac->pdev->dev; ++ + if (gmac->integrated_phy) + rk_gmac_integrated_phy_powerdown(gmac); + ++ pm_runtime_put_sync(dev); ++ pm_runtime_disable(dev); ++ + phy_power_on(gmac, false); + gmac_clk_enable(gmac, false); + } From 221bd5a397d68e65cd23c39fa74f2bf8a0c2bde0 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 13:25:31 +1000 Subject: [PATCH 48/51] linux (Generic): tidy up .config for 5.14 --- projects/Generic/linux/linux.x86_64.conf | 380 +++++++++++++++-------- 1 file changed, 256 insertions(+), 124 deletions(-) diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index 84c0efd90e..134b77af2b 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.10.54 Kernel Configuration +# Linux/x86 5.14.0-rc6 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.2.0 (GCC) 10.2.0" +CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=100200 +CONFIG_GCC_VERSION=100300 CONFIG_LD_VERSION=235010000 CONFIG_CLANG_VERSION=0 CONFIG_LLD_VERSION=0 @@ -95,9 +95,23 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set +# CONFIG_SCHED_CORE is not set # # CPU/Task time and stats accounting @@ -168,6 +182,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -202,7 +217,6 @@ CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_BPF=y CONFIG_EXPERT=y # CONFIG_UID16 is not set CONFIG_MULTIUSER=y @@ -231,9 +245,6 @@ CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -252,7 +263,6 @@ CONFIG_PERF_EVENTS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -285,7 +295,6 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_FILTER_PGPROT=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y @@ -293,9 +302,7 @@ CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ZONE_DMA32=y CONFIG_AUDIT_ARCH=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_HAVE_INTEL_TXT=y CONFIG_X86_64_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y @@ -306,7 +313,6 @@ CONFIG_CC_HAS_SANE_STACKPROTECTOR=y # # Processor type and features # -CONFIG_ZONE_DMA=y CONFIG_SMP=y CONFIG_X86_FEATURE_NAMES=y # CONFIG_X86_X2APIC is not set @@ -407,7 +413,6 @@ CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 # CONFIG_X86_PMEM_LEGACY is not set CONFIG_X86_CHECK_BIOS_CORRUPTION=y CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y -CONFIG_X86_RESERVE_LOW=64 CONFIG_MTRR=y CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 @@ -421,6 +426,7 @@ CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y CONFIG_X86_INTEL_TSX_MODE_OFF=y # CONFIG_X86_INTEL_TSX_MODE_ON is not set # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +# CONFIG_X86_SGX is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_MIXED=y @@ -456,10 +462,8 @@ CONFIG_HAVE_LIVEPATCH=y # end of Processor type and features CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management and ACPI options @@ -490,6 +494,7 @@ CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y # CONFIG_ACPI_DEBUGGER is not set CONFIG_ACPI_SPCR_TABLE=y +# CONFIG_ACPI_FPDT is not set CONFIG_ACPI_LPIT=y CONFIG_ACPI_SLEEP=y CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y @@ -531,7 +536,7 @@ CONFIG_HAVE_ACPI_APEI_NMI=y # CONFIG_ACPI_CONFIGFS is not set # CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y -# CONFIG_SFI is not set +CONFIG_ACPI_PRMT=y # # CPU Frequency scaling @@ -659,8 +664,6 @@ CONFIG_AS_TPAUSE=y CONFIG_CRASH_CORE=y CONFIG_HOTPLUG_SMT=y CONFIG_GENERIC_ENTRY=y -CONFIG_HAVE_OPROFILE=y -CONFIG_OPROFILE_NMI_TIMER=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -685,6 +688,7 @@ CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y @@ -710,14 +714,20 @@ CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y @@ -726,6 +736,8 @@ CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -740,6 +752,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y # CONFIG_VMAP_STACK is not set +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -749,7 +763,10 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_STATIC_CALL=y CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y # # GCOV-based kernel profiling @@ -771,9 +788,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -787,6 +807,7 @@ CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -868,22 +889,23 @@ CONFIG_COREDUMP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y -CONFIG_NEED_MULTIPLE_NODES=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_MEMORY_ISOLATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # CONFIG_MEMORY_HOTPLUG is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_MMU_NOTIFIER=y # CONFIG_KSM is not set @@ -898,23 +920,28 @@ CONFIG_CLEANCACHE=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=19 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_HMM_MIRROR=y CONFIG_VMAP_PFN=y -CONFIG_FRAME_VECTOR=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y CONFIG_ARCH_HAS_PKEYS=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y +CONFIG_SECRETMEM=y # end of Memory Management options CONFIG_NET=y @@ -1026,7 +1053,7 @@ CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_NETLINK_LOG=m # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m -# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_LOG_SYSLOG is not set # CONFIG_NF_CONNTRACK_MARK is not set # CONFIG_NF_CONNTRACK_ZONES is not set # CONFIG_NF_CONNTRACK_PROCFS is not set @@ -1057,6 +1084,7 @@ CONFIG_NF_NAT_SIP=m CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1217,7 +1245,7 @@ CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set @@ -1298,14 +1326,15 @@ CONFIG_DNS_RESOLVER=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1331,6 +1360,7 @@ CONFIG_BT_HS=y CONFIG_BT_LE=y # CONFIG_BT_LEDS is not set # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set # CONFIG_BT_SELFTEST is not set @@ -1370,6 +1400,7 @@ CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m CONFIG_BT_MTKSDIO=m CONFIG_BT_MTKUART=m +# CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1408,7 +1439,6 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1422,10 +1452,11 @@ CONFIG_RFKILL_INPUT=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1447,7 +1478,6 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y # CONFIG_PCIE_DPC is not set # CONFIG_PCIE_PTM is not set -# CONFIG_PCIE_BW is not set CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y @@ -1501,12 +1531,14 @@ CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set # # Generic Driver Options # +CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -1562,13 +1594,11 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set CONFIG_CDROM=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=y -# CONFIG_BLK_DEV_SKD is not set # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 @@ -1611,10 +1641,10 @@ CONFIG_NVME_MULTIPATH=y # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set # CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set CONFIG_MISC_RTSX=y -# CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set # @@ -1645,16 +1675,15 @@ CONFIG_ALTERA_STAPL=m # CONFIG_VMWARE_VMCI is not set # CONFIG_GENWQE is not set # CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set CONFIG_MISC_RTSX_PCI=y CONFIG_MISC_RTSX_USB=y # CONFIG_HABANA_AI is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - # # SCSI device support # @@ -1718,6 +1747,7 @@ CONFIG_SCSI_MVSAS=y CONFIG_MEGARAID_SAS=y # CONFIG_SCSI_MPT3SAS is not set # CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set @@ -1728,7 +1758,6 @@ CONFIG_MEGARAID_SAS=y # CONFIG_SCSI_SNIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FDOMAIN_PCI is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_ISCI is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set @@ -1887,12 +1916,6 @@ CONFIG_VETH=m CONFIG_VIRTIO_NET=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_MDIO=y CONFIG_NET_VENDOR_3COM=y @@ -1918,7 +1941,6 @@ CONFIG_ATL1=y CONFIG_ATL1E=y CONFIG_ATL1C=y CONFIG_ALX=y -# CONFIG_NET_VENDOR_AURORA is not set CONFIG_NET_VENDOR_BROADCOM=y CONFIG_B44=y CONFIG_B44_PCI_AUTOSELECT=y @@ -1978,6 +2000,7 @@ CONFIG_IXGBE_HWMON=y CONFIG_ICE=y # CONFIG_FM10K is not set CONFIG_IGC=y +CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_JME=y CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set @@ -2046,8 +2069,9 @@ CONFIG_VIA_VELOCITY=y # CONFIG_HIPPI is not set # CONFIG_NET_SB1000 is not set CONFIG_PHYLIB=y +CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set -# CONFIG_FIXED_PHY is not set +CONFIG_FIXED_PHY=y # # MII PHY device drivers @@ -2055,7 +2079,7 @@ CONFIG_PHYLIB=y CONFIG_AMD_PHY=y # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=m CONFIG_BROADCOM_PHY=y # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -2071,11 +2095,15 @@ CONFIG_BCM_NET_PHYLIB=y # CONFIG_LSI_ET1011C_PHY is not set CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set CONFIG_AT803X_PHY=y # CONFIG_QSEMI_PHY is not set @@ -2094,6 +2122,8 @@ CONFIG_REALTEK_PHY=y # CONFIG_XILINX_GMII2RGMII is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_ACPI_MDIO=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_BITBANG is not set # CONFIG_MDIO_BCM_UNIMAC is not set @@ -2159,8 +2189,8 @@ CONFIG_USB_IPHETH=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y # CONFIG_ADM8211 is not set CONFIG_ATH_COMMON=m @@ -2296,6 +2326,7 @@ CONFIG_MT76_LEDS=y CONFIG_MT76_USB=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m # CONFIG_MT76x0E is not set @@ -2309,6 +2340,7 @@ CONFIG_MT7663_USB_SDIO_COMMON=m CONFIG_MT7663U=m # CONFIG_MT7663S is not set CONFIG_MT7915E=m +# CONFIG_MT7921E is not set CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set CONFIG_WLAN_VENDOR_RALINK=y @@ -2391,11 +2423,14 @@ CONFIG_ZD1211RW=m # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Wireless WAN # -# CONFIG_WAN is not set +# CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_VMXNET3 is not set # CONFIG_FUJITSU_ES is not set # CONFIG_NETDEVSIM is not set @@ -2409,7 +2444,6 @@ CONFIG_NET_FAILOVER=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set @@ -2504,10 +2538,10 @@ CONFIG_JOYSTICK_XPAD=m CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_PROPERTIES=y # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_ATMEL_MXT is not set # CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set @@ -2526,7 +2560,9 @@ CONFIG_TOUCHSCREEN_PROPERTIES=y # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_EKTF2127 is not set @@ -2538,6 +2574,7 @@ CONFIG_TOUCHSCREEN_ELAN=y # CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set @@ -2604,9 +2641,11 @@ CONFIG_INPUT_ATI_REMOTE2=m CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set @@ -2693,6 +2732,7 @@ CONFIG_SERIAL_CORE=y # CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_ARC is not set @@ -2707,7 +2747,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y @@ -2725,15 +2764,14 @@ CONFIG_HW_RANDOM_VIRTIO=m # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set # CONFIG_NVRAM is not set -# CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y # CONFIG_HPET is not set # CONFIG_HANGCHECK_TIMER is not set # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices # CONFIG_RANDOM_TRUST_CPU is not set @@ -2815,6 +2853,7 @@ CONFIG_I2C_DESIGNWARE_BAYTRAIL=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2862,6 +2901,7 @@ CONFIG_PTP_1588_CLOCK_KVM=y # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set # CONFIG_PTP_1588_CLOCK_VMW is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2876,14 +2916,17 @@ CONFIG_PINCTRL_BAYTRAIL=y CONFIG_PINCTRL_CHERRYVIEW=y CONFIG_PINCTRL_LYNXPOINT=y CONFIG_PINCTRL_INTEL=y +# CONFIG_PINCTRL_ALDERLAKE is not set CONFIG_PINCTRL_BROXTON=y CONFIG_PINCTRL_CANNONLAKE=y CONFIG_PINCTRL_CEDARFORK=y CONFIG_PINCTRL_DENVERTON=y +# CONFIG_PINCTRL_ELKHARTLAKE is not set CONFIG_PINCTRL_EMMITSBURG=y CONFIG_PINCTRL_GEMINILAKE=y CONFIG_PINCTRL_ICELAKE=y CONFIG_PINCTRL_JASPERLAKE=y +# CONFIG_PINCTRL_LAKEFIELD is not set CONFIG_PINCTRL_LEWISBURG=y CONFIG_PINCTRL_SUNRISEPOINT=y CONFIG_PINCTRL_TIGERLAKE=y @@ -2909,10 +2952,8 @@ CONFIG_GPIO_CDEV_V1=y # CONFIG_GPIO_DWAPB is not set # CONFIG_GPIO_EXAR is not set # CONFIG_GPIO_GENERIC_PLATFORM is not set -# CONFIG_GPIO_ICH is not set # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_VX855 is not set -# CONFIG_GPIO_XILINX is not set # CONFIG_GPIO_AMD_FCH is not set # end of Memory mapped GPIO drivers @@ -2959,8 +3000,13 @@ CONFIG_GPIO_CDEV_V1=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y @@ -2984,14 +3030,17 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24257 is not set # CONFIG_CHARGER_BQ24735 is not set # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_BD99954 is not set @@ -3018,18 +3067,19 @@ CONFIG_HWMON_VID=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set CONFIG_SENSORS_K8TEMP=m CONFIG_SENSORS_K10TEMP=m CONFIG_SENSORS_FAM15H_POWER=m -CONFIG_SENSORS_AMD_ENERGY=m # CONFIG_SENSORS_APPLESMC is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set @@ -3053,12 +3103,14 @@ CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -3072,6 +3124,7 @@ CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set @@ -3095,11 +3148,14 @@ CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_NCT6775 is not set # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set @@ -3158,13 +3214,15 @@ CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set -# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_USER_SPACE=y # CONFIG_THERMAL_EMULATION is not set # # Intel thermal drivers # CONFIG_INTEL_POWERCLAMP=m +CONFIG_X86_THERMAL_VECTOR=y +CONFIG_X86_PKG_TEMP_THERMAL=m CONFIG_INTEL_SOC_DTS_IOSF_CORE=m CONFIG_INTEL_SOC_DTS_THERMAL=m @@ -3175,6 +3233,7 @@ CONFIG_INTEL_SOC_DTS_THERMAL=m # end of ACPI INT340X thermal drivers # CONFIG_INTEL_PCH_THERMAL is not set +# CONFIG_INTEL_TCC_COOLING is not set # end of Intel thermal drivers # CONFIG_WATCHDOG is not set @@ -3230,6 +3289,7 @@ CONFIG_MFD_INTEL_LPSS=y CONFIG_MFD_INTEL_LPSS_ACPI=y CONFIG_MFD_INTEL_LPSS_PCI=y # CONFIG_MFD_INTEL_PMC_BXT is not set +# CONFIG_MFD_INTEL_PMT is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set @@ -3251,13 +3311,12 @@ CONFIG_MFD_INTEL_LPSS_PCI=y # CONFIG_MFD_PCF50633 is not set # CONFIG_UCB1400_CORE is not set # CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set # CONFIG_MFD_LP3943 is not set @@ -3269,7 +3328,6 @@ CONFIG_MFD_INTEL_LPSS_PCI=y # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65086 is not set # CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TPS68470 is not set # CONFIG_MFD_TI_LP873X is not set # CONFIG_MFD_TPS6586X is not set # CONFIG_MFD_TPS65910 is not set @@ -3286,6 +3344,7 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ATC260X_I2C is not set # CONFIG_RAVE_SP_CORE is not set # end of Multifunction device drivers @@ -3312,17 +3371,19 @@ CONFIG_REGULATOR=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MP8859 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_TPS51632 is not set @@ -3405,6 +3466,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_TUNER=m # CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_DMA_SG=m CONFIG_VIDEOBUF_VMALLOC=m @@ -3430,7 +3492,6 @@ CONFIG_DVB_MAX_ADAPTERS=64 # # Media drivers # -CONFIG_TTPCI_EEPROM=m CONFIG_MEDIA_USB_SUPPORT=y # @@ -3584,14 +3645,10 @@ CONFIG_VIDEO_SAA7164=m # # Media digital TV PCI Adapters # -CONFIG_DVB_AV7110_IR=y -CONFIG_DVB_AV7110=m -CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_CORE=m CONFIG_DVB_BUDGET=m CONFIG_DVB_BUDGET_CI=m CONFIG_DVB_BUDGET_AV=m -CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_B2C2_FLEXCOP_PCI=m # CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set # CONFIG_DVB_PLUTO2 is not set @@ -3606,6 +3663,7 @@ CONFIG_DVB_DDBRIDGE=m # CONFIG_DVB_DDBRIDGE_MSIENABLE is not set CONFIG_DVB_SMIPCIE=m CONFIG_VIDEO_IPU3_CIO2=m +# CONFIG_CIO2_BRIDGE is not set CONFIG_RADIO_ADAPTERS=y CONFIG_RADIO_TEA575X=m CONFIG_RADIO_SI470X=m @@ -3634,6 +3692,7 @@ CONFIG_MEDIA_COMMON_OPTIONS=y # CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m CONFIG_CYPRESS_FIRMWARE=m CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m @@ -3781,6 +3840,7 @@ CONFIG_SDR_MAX2175=m # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set @@ -3788,12 +3848,14 @@ CONFIG_SDR_MAX2175=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set # CONFIG_VIDEO_OV2685 is not set # CONFIG_VIDEO_OV2740 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3804,8 +3866,10 @@ CONFIG_SDR_MAX2175=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV9734 is not set # CONFIG_VIDEO_OV13858 is not set # CONFIG_VIDEO_VS6624 is not set # CONFIG_VIDEO_MT9M001 is not set @@ -3821,12 +3885,13 @@ CONFIG_SDR_MAX2175=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # end of Camera sensor devices @@ -3955,7 +4020,6 @@ CONFIG_DVB_TDA10071=m # # DVB-T (terrestrial) frontends # -CONFIG_DVB_SP8870=m CONFIG_DVB_SP887X=m CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m @@ -4009,6 +4073,7 @@ CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m # # ISDB-T (terrestrial) frontends @@ -4084,7 +4149,6 @@ CONFIG_DRM_DP_AUX_CHARDEV=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 @@ -4092,7 +4156,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=y -CONFIG_DRM_TTM_DMA_PAGE_POOL=y +CONFIG_DRM_TTM_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y @@ -4115,8 +4179,7 @@ CONFIG_DRM_RADEON=y CONFIG_DRM_AMDGPU=y CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y -# CONFIG_DRM_AMDGPU_USERPTR is not set -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set +CONFIG_DRM_AMDGPU_USERPTR=y # # ACP (Audio CoProcessor) Configuration @@ -4129,9 +4192,9 @@ CONFIG_DRM_AMD_ACP=y # CONFIG_DRM_AMD_DC=y CONFIG_DRM_AMD_DC_DCN=y -# CONFIG_DRM_AMD_DC_DCN3_0 is not set # CONFIG_DRM_AMD_DC_HDCP is not set # CONFIG_DRM_AMD_DC_SI is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set # end of Display Engine Configuration CONFIG_HSA_AMD=y @@ -4161,6 +4224,7 @@ CONFIG_DRM_I915_USERPTR=y # # drm/i915 Profile Guided Optimisation # +CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 CONFIG_DRM_I915_FENCE_TIMEOUT=10000 CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 @@ -4201,7 +4265,9 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_DRM_VBOXVIDEO is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -4269,6 +4335,7 @@ CONFIG_FB_UDL=m # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set # CONFIG_FB_SM712 is not set # end of Frame buffer Devices @@ -4330,6 +4397,7 @@ CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_DEBUG is not set CONFIG_SND_VMASTER=y CONFIG_SND_DMA_SGBUF=y +CONFIG_SND_CTL_LED=m # CONFIG_SND_SEQUENCER is not set CONFIG_SND_MPU401_UART=m CONFIG_SND_OPL3_LIB=m @@ -4444,6 +4512,7 @@ CONFIG_SND_HDA_EXT_CORE=m CONFIG_SND_HDA_PREALLOC_SIZE=0 CONFIG_SND_INTEL_NHLT=y CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y @@ -4474,6 +4543,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_COMPRESS=y CONFIG_SND_SOC_TOPOLOGY=y CONFIG_SND_SOC_ACPI=m +# CONFIG_SND_SOC_ADI is not set CONFIG_SND_SOC_AMD_ACP=m CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m @@ -4498,6 +4568,7 @@ CONFIG_SND_SOC_AMD_RENOIR_MACH=m # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -4524,6 +4595,7 @@ CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m CONFIG_SND_SOC_ACPI_INTEL_MATCH=m CONFIG_SND_SOC_INTEL_MACH=y # CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set +CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m @@ -4556,13 +4628,13 @@ CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set CONFIG_SND_SOC_ADAU7002=m @@ -4625,6 +4697,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_PCM186X_I2C is not set # CONFIG_SND_SOC_PCM3060_I2C is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_RK3328 is not set CONFIG_SND_SOC_RL6231=m @@ -4633,12 +4706,16 @@ CONFIG_SND_SOC_RL6231=m CONFIG_SND_SOC_RT5640=m CONFIG_SND_SOC_RT5645=m CONFIG_SND_SOC_RT5651=m +# CONFIG_SND_SOC_RT5659 is not set CONFIG_SND_SOC_RT5670=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682_I2C=m # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=m # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set # CONFIG_SND_SOC_STA32X is not set @@ -4654,10 +4731,11 @@ CONFIG_SND_SOC_SPDIF=m # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_TSCS42XX is not set @@ -4684,22 +4762,27 @@ CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set CONFIG_SND_SOC_NAU8824=m # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_X86=y CONFIG_HDMI_LPE_AUDIO=m +# CONFIG_SND_VIRTIO is not set CONFIG_AC97_BUS=m # @@ -4741,6 +4824,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -4785,11 +4869,13 @@ CONFIG_HID_PENMOUNT=y CONFIG_HID_PETALYNX=y # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set CONFIG_HID_SAMSUNG=y +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=y CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -4827,7 +4913,7 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -CONFIG_I2C_HID=m +# CONFIG_I2C_HID_ACPI is not set # end of I2C HID support # @@ -4835,6 +4921,12 @@ CONFIG_I2C_HID=m # # CONFIG_INTEL_ISH_HID is not set # end of Intel ISH HID support + +# +# AMD SFH HID Support +# +# CONFIG_AMD_SFH_HID is not set +# end of AMD SFH HID Support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -4928,7 +5020,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -4981,7 +5073,6 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_SERIAL_OPTICON is not set @@ -4990,6 +5081,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_QT2 is not set # CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -5108,6 +5200,7 @@ CONFIG_LEDS_CLASS_FLASH=y # CONFIG_LEDS_REGULATOR is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_LT3593 is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_LM355x is not set @@ -5123,6 +5216,11 @@ CONFIG_LEDS_CLASS_FLASH=y # CONFIG_LEDS_TI_LMU_COMMON is not set # CONFIG_LEDS_SGM3140 is not set +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_RT8515 is not set + # # LED Triggers # @@ -5146,6 +5244,7 @@ CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set CONFIG_LEDS_TRIGGER_AUDIO=m +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -5213,6 +5312,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -5241,6 +5341,7 @@ CONFIG_RTC_DRV_CMOS=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -5255,7 +5356,6 @@ CONFIG_INTEL_IDMA64=m # CONFIG_INTEL_IDXD is not set CONFIG_INTEL_IOATDMA=m # CONFIG_PLX_DMA is not set -# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=m @@ -5265,6 +5365,7 @@ CONFIG_DW_DMAC_PCI=m # CONFIG_DW_EDMA_PCIE is not set CONFIG_HSU_DMA=y # CONFIG_SF_PDMA is not set +# CONFIG_INTEL_LDMA is not set # # DMA Clients @@ -5280,6 +5381,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -5301,6 +5403,7 @@ CONFIG_UIO=y # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y @@ -5319,9 +5422,9 @@ CONFIG_VIRTIO_DMA_SHARED_BUFFER=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set CONFIG_RTL8192U=m # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m @@ -5335,6 +5438,11 @@ CONFIG_STAGING_MEDIA=y # CONFIG_INTEL_ATOMISP is not set # CONFIG_VIDEO_ZORAN is not set CONFIG_VIDEO_IPU3_IMGU=m +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET_PATCH=m +CONFIG_DVB_SP8870=m # # Android @@ -5346,59 +5454,48 @@ CONFIG_VIDEO_IPU3_IMGU=m # CONFIG_GS_FPGABOOT is not set # CONFIG_UNISYSSPAR is not set # CONFIG_KS7010 is not set - -# -# Gasket devices -# -# CONFIG_STAGING_GASKET_FRAMEWORK is not set -# end of Gasket devices - # CONFIG_FIELDBUS_DEV is not set -# CONFIG_KPC2000 is not set # CONFIG_QLGE is not set # CONFIG_WFX is not set CONFIG_X86_PLATFORM_DEVICES=y CONFIG_ACPI_WMI=y CONFIG_WMI_BMOF=y -# CONFIG_ALIENWARE_WMI is not set # CONFIG_HUAWEI_WMI is not set # CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set # CONFIG_INTEL_WMI_THUNDERBOLT is not set # CONFIG_MXM_WMI is not set # CONFIG_PEAQ_WMI is not set # CONFIG_XIAOMI_WMI is not set +# CONFIG_GIGABYTE_WMI is not set # CONFIG_ACERHDF is not set # CONFIG_ACER_WIRELESS is not set # CONFIG_ACER_WMI is not set +# CONFIG_AMD_PMC is not set +# CONFIG_ADV_SWBUTTON is not set # CONFIG_APPLE_GMUX is not set # CONFIG_ASUS_LAPTOP is not set # CONFIG_ASUS_WIRELESS is not set -# CONFIG_DCDBAS is not set -# CONFIG_DELL_SMBIOS is not set -# CONFIG_DELL_RBTN is not set -# CONFIG_DELL_RBU is not set -# CONFIG_DELL_SMO8800 is not set -# CONFIG_DELL_WMI_AIO is not set -# CONFIG_DELL_WMI_LED is not set +# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set # CONFIG_AMILO_RFKILL is not set # CONFIG_FUJITSU_LAPTOP is not set # CONFIG_FUJITSU_TABLET is not set # CONFIG_GPD_POCKET_FAN is not set # CONFIG_HP_ACCEL is not set -# CONFIG_HP_WIRELESS is not set +# CONFIG_WIRELESS_HOTKEY is not set # CONFIG_HP_WMI is not set # CONFIG_IBM_RTL is not set # CONFIG_IDEAPAD_LAPTOP is not set # CONFIG_SENSORS_HDAPS is not set # CONFIG_THINKPAD_ACPI is not set +# CONFIG_THINKPAD_LMI is not set +CONFIG_X86_PLATFORM_DRIVERS_INTEL=y +# CONFIG_INTEL_SKL_INT3472 is not set CONFIG_INTEL_ATOMISP2_PM=y # CONFIG_INTEL_HID_EVENT is not set # CONFIG_INTEL_INT0002_VGPIO is not set # CONFIG_INTEL_MENLOW is not set # CONFIG_INTEL_OAKTRAIL is not set # CONFIG_INTEL_VBTN is not set -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set # CONFIG_MSI_LAPTOP is not set # CONFIG_MSI_WMI is not set # CONFIG_PCENGINES_APU2 is not set @@ -5435,16 +5532,30 @@ CONFIG_INTEL_ATOMISP2_PM=y CONFIG_PMC_ATOM=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set +CONFIG_SURFACE_PLATFORMS=y +# CONFIG_SURFACE_3_POWER_OPREGION is not set +# CONFIG_SURFACE_GPE is not set +# CONFIG_SURFACE_HOTPLUG is not set +# CONFIG_SURFACE_PRO3_BUTTON is not set +# CONFIG_SURFACE_AGGREGATOR is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -5465,11 +5576,13 @@ CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # +CONFIG_IOMMU_IO_PGTABLE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_SVA_LIB=y CONFIG_AMD_IOMMU=y CONFIG_AMD_IOMMU_V2=y CONFIG_DMAR_TABLE=y @@ -5479,6 +5592,7 @@ CONFIG_INTEL_IOMMU_SVM=y CONFIG_INTEL_IOMMU_FLOPPY_WA=y # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set CONFIG_IRQ_REMAP=y +# CONFIG_VIRTIO_IOMMU is not set # # Remoteproc drivers @@ -5504,11 +5618,6 @@ CONFIG_IRQ_REMAP=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -5524,6 +5633,11 @@ CONFIG_IRQ_REMAP=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -5534,7 +5648,6 @@ CONFIG_IRQ_REMAP=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5553,7 +5666,7 @@ CONFIG_IRQ_REMAP=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set +# CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_TI_SYSCON is not set # @@ -5561,6 +5674,7 @@ CONFIG_RESET_CONTROLLER=y # # CONFIG_GENERIC_PHY is not set # CONFIG_USB_LGM_PHY is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set @@ -5571,6 +5685,7 @@ CONFIG_POWERCAP=y CONFIG_INTEL_RAPL_CORE=m CONFIG_INTEL_RAPL=m # CONFIG_IDLE_INJECT is not set +# CONFIG_DTPM is not set # CONFIG_MCB is not set # @@ -5591,6 +5706,7 @@ CONFIG_RAS=y # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -5656,7 +5772,6 @@ CONFIG_F2FS_FS=y CONFIG_F2FS_STAT_FS=y # CONFIG_F2FS_FS_XATTR is not set CONFIG_F2FS_CHECK_FS=y -# CONFIG_F2FS_IO_TRACE is not set # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set # CONFIG_FS_DAX is not set @@ -5687,6 +5802,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -5787,7 +5904,7 @@ CONFIG_NFS_SWAP=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y -CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_NFS_V4_1_MIGRATION=y CONFIG_ROOT_NFS=y @@ -5801,6 +5918,7 @@ CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -5817,6 +5935,7 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set @@ -5947,7 +6066,6 @@ CONFIG_CRYPTO_CRYPTD=y # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_GLUE_HELPER_X86=y # # Public-key cryptography @@ -5956,6 +6074,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -6016,10 +6135,7 @@ CONFIG_CRYPTO_POLY1305_X86_64=m CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA1_SSSE3=y CONFIG_CRYPTO_SHA256_SSSE3=y @@ -6029,7 +6145,6 @@ CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set @@ -6055,7 +6170,6 @@ CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_DES3_EDE_X86_64=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set CONFIG_CRYPTO_CHACHA20_X86_64=m # CONFIG_CRYPTO_SEED is not set @@ -6218,6 +6332,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_IOMMU_HELPER=y CONFIG_CHECK_SIGNATURE=y @@ -6229,6 +6344,7 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y +CONFIG_DIMLIB=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y @@ -6244,7 +6360,6 @@ CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y CONFIG_ARCH_HAS_COPY_MC=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines CONFIG_PLDMFW=y @@ -6258,6 +6373,7 @@ CONFIG_PLDMFW=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6272,16 +6388,16 @@ CONFIG_DEBUG_BUGVERBOSE=y # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -# CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FRAME_WARN=1024 CONFIG_STRIP_ASM_SYMS=y # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set CONFIG_FRAME_POINTER=y CONFIG_STACK_VALIDATION=y +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -6333,11 +6449,15 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6396,6 +6516,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_TRACE_IRQFLAGS=y CONFIG_TRACE_IRQFLAGS_NMI=y +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -6434,9 +6555,11 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y @@ -6460,6 +6583,8 @@ CONFIG_STACK_TRACER=y CONFIG_IRQSOFF_TRACER=y CONFIG_SCHED_TRACER=y # CONFIG_HWLAT_TRACER is not set +# CONFIG_OSNOISE_TRACER is not set +# CONFIG_TIMERLAT_TRACER is not set # CONFIG_MMIOTRACE is not set # CONFIG_FTRACE_SYSCALLS is not set CONFIG_TRACER_SNAPSHOT=y @@ -6476,14 +6601,17 @@ CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y # CONFIG_BPF_KPROBE_OVERRIDE is not set CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_CC=y # CONFIG_SYNTH_EVENTS is not set # CONFIG_HIST_TRIGGERS is not set # CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set # CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set # CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_KPROBE_EVENT_GEN_TEST is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set @@ -6531,9 +6659,9 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set +# CONFIG_TEST_DIV64 is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set @@ -6542,10 +6670,12 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set @@ -6570,6 +6700,8 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set # CONFIG_TEST_FPU is not set +# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set +CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking From 81d54360fb197f2814429ec36bac91c6dae33e87 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 14:08:02 +1000 Subject: [PATCH 49/51] linux (Qualcomm): tidy up .config for 5.14 --- .../Dragonboard/linux/linux.aarch64.conf | 516 ++++++++++++------ 1 file changed, 351 insertions(+), 165 deletions(-) diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index 5fd911af90..2d9d12e878 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.10.32 Kernel Configuration +# Linux/arm64 5.14.0-rc6 Kernel Configuration # # @@ -63,7 +63,6 @@ CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -81,6 +80,21 @@ CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_JIT_ALWAYS_ON is not set +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y @@ -115,6 +129,7 @@ CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y +CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem @@ -154,6 +169,8 @@ CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -188,7 +205,6 @@ CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -215,9 +231,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_BPF_SYSCALL is not set -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -CONFIG_BPF_JIT_DEFAULT_ON=y # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -265,10 +278,7 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_ZONE_DMA32=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -280,10 +290,11 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # Platform selection # # CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_AGILEX is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set # CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set @@ -305,7 +316,7 @@ CONFIG_ARCH_QCOM=y # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set @@ -315,7 +326,6 @@ CONFIG_ARCH_QCOM=y # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set # end of Platform selection @@ -331,32 +341,32 @@ CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_832075=y +# CONFIG_ARM64_ERRATUM_832075 is not set CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_ARM64_ERRATUM_1418040=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1319367=y -CONFIG_ARM64_ERRATUM_1530923=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_1463225=y -CONFIG_ARM64_ERRATUM_1542419=y -CONFIG_ARM64_ERRATUM_1508412=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23154=y -CONFIG_CAVIUM_ERRATUM_27456=y -CONFIG_CAVIUM_ERRATUM_30115=y -CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_FUJITSU_ERRATUM_010001=y -CONFIG_HISILICON_ERRATUM_161600802=y -CONFIG_QCOM_FALKOR_ERRATUM_1003=y -CONFIG_QCOM_FALKOR_ERRATUM_1009=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_QCOM_FALKOR_ERRATUM_E1041=y -CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +# CONFIG_ARM64_ERRATUM_1024718 is not set +# CONFIG_ARM64_ERRATUM_1418040 is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1319367 is not set +# CONFIG_ARM64_ERRATUM_1530923 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # end of ARM errata workarounds via the alternatives framework CONFIG_ARM64_4K_PAGES=y @@ -371,27 +381,18 @@ CONFIG_ARM64_PA_BITS=48 CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SCHED_MC=y # CONFIG_SCHED_SMT is not set -CONFIG_NR_CPUS=64 +CONFIG_NR_CPUS=4 CONFIG_HOTPLUG_CPU=y # CONFIG_NUMA is not set -CONFIG_HOLES_IN_ZONE=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HW_PERF_EVENTS=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y CONFIG_PARAVIRT=y # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_KEXEC=y @@ -414,27 +415,25 @@ CONFIG_SETEND_EMULATION=y # # ARMv8.1 architectural features # -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAN=y +# CONFIG_ARM64_HW_AFDBM is not set +# CONFIG_ARM64_PAN is not set +CONFIG_AS_HAS_LDAPR=y CONFIG_AS_HAS_LSE_ATOMICS=y -CONFIG_ARM64_LSE_ATOMICS=y -CONFIG_ARM64_USE_LSE_ATOMICS=y -CONFIG_ARM64_VHE=y +# CONFIG_ARM64_USE_LSE_ATOMICS is not set # end of ARMv8.1 architectural features # # ARMv8.2 architectural features # -CONFIG_ARM64_UAO=y # CONFIG_ARM64_PMEM is not set -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_CNP=y +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set # end of ARMv8.2 architectural features # # ARMv8.3 architectural features # -CONFIG_ARM64_PTR_AUTH=y +# CONFIG_ARM64_PTR_AUTH is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_PAC=y @@ -444,23 +443,27 @@ CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # # ARMv8.4 architectural features # -CONFIG_ARM64_AMU_EXTN=y +# CONFIG_ARM64_AMU_EXTN is not set CONFIG_AS_HAS_ARMV8_4=y -CONFIG_ARM64_TLB_RANGE=y +# CONFIG_ARM64_TLB_RANGE is not set # end of ARMv8.4 architectural features # # ARMv8.5 architectural features # -CONFIG_ARM64_BTI=y -CONFIG_ARM64_BTI_KERNEL=y +CONFIG_AS_HAS_ARMV8_5=y +# CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y -CONFIG_ARM64_E0PD=y -CONFIG_ARCH_RANDOM=y +# CONFIG_ARM64_E0PD is not set +# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y -CONFIG_ARM64_MTE=y # end of ARMv8.5 architectural features +# +# ARMv8.7 architectural features +# +# end of ARMv8.7 architectural features + CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set @@ -481,8 +484,6 @@ CONFIG_DMI=y # end of Boot options CONFIG_SYSVIPC_COMPAT=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management options @@ -573,6 +574,7 @@ CONFIG_DMIID=y # CONFIG_FW_CFG_SYSFS is not set CONFIG_QCOM_SCM=y # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +# CONFIG_ARM_FFA_TRANSPORT is not set # CONFIG_GOOGLE_FIRMWARE is not set # @@ -644,31 +646,30 @@ CONFIG_VIRTUALIZATION=y # CONFIG_KVM is not set CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA256_ARM64=y -# CONFIG_CRYPTO_SHA512_ARM64 is not set +CONFIG_CRYPTO_SHA512_ARM64=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y -# CONFIG_CRYPTO_SHA512_ARM64_CE is not set +CONFIG_CRYPTO_SHA512_ARM64_CE=y # CONFIG_CRYPTO_SHA3_ARM64 is not set # CONFIG_CRYPTO_SM3_ARM64_CE is not set # CONFIG_CRYPTO_SM4_ARM64_CE is not set CONFIG_CRYPTO_GHASH_ARM64_CE=y -# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_CRYPTO_CHACHA20_NEON=y CONFIG_CRYPTO_POLY1305_NEON=y # CONFIG_CRYPTO_NHPOLY1305_NEON is not set -# CONFIG_CRYPTO_AES_ARM64_BS is not set +CONFIG_CRYPTO_AES_ARM64_BS=y # # General architecture-dependent options # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y -CONFIG_SET_FS=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -686,6 +687,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y @@ -706,16 +708,23 @@ CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y @@ -730,6 +739,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -740,6 +751,7 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -763,10 +775,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y @@ -782,6 +796,7 @@ CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -839,9 +854,6 @@ CONFIG_COREDUMP=y # # Memory Management options # -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y @@ -849,16 +861,20 @@ CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 @@ -871,20 +887,22 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y -CONFIG_FRAME_VECTOR=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y # end of Memory Management options CONFIG_NET=y @@ -909,6 +927,7 @@ CONFIG_XFRM_USER=y # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set +# CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set @@ -923,7 +942,7 @@ CONFIG_IP_MROUTE_COMMON=y # CONFIG_IP_MROUTE is not set CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set -CONFIG_NET_UDP_TUNNEL=y +CONFIG_NET_UDP_TUNNEL=m CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set @@ -978,13 +997,13 @@ CONFIG_BRIDGE_NETFILTER=m CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_FAMILY_BRIDGE=y +# CONFIG_NETFILTER_NETLINK_HOOK is not set # CONFIG_NETFILTER_NETLINK_ACCT is not set # CONFIG_NETFILTER_NETLINK_QUEUE is not set # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_LOG_SYSLOG=m CONFIG_NF_CONNTRACK_MARK=y # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y @@ -1041,6 +1060,7 @@ CONFIG_NF_TABLES=m # CONFIG_NFT_SYNPROXY is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1159,6 +1179,7 @@ CONFIG_IP_VS_TAB_BITS=12 # CONFIG_IP_VS_MH is not set # CONFIG_IP_VS_SED is not set # CONFIG_IP_VS_NQ is not set +# CONFIG_IP_VS_TWOS is not set # # IPVS SH scheduler @@ -1261,7 +1282,7 @@ CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y # CONFIG_BRIDGE_MRP is not set -CONFIG_HAVE_NET_DSA=y +# CONFIG_BRIDGE_CFM is not set # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y CONFIG_VLAN_8021Q_GVRP=y @@ -1364,14 +1385,16 @@ CONFIG_QRTR=y CONFIG_QRTR_SMD=y # CONFIG_QRTR_TUN is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -CONFIG_BPF_JIT=y +# CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y # @@ -1396,6 +1419,7 @@ CONFIG_BT_LE=y # CONFIG_BT_6LOWPAN is not set CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set CONFIG_BT_DEBUGFS=y # CONFIG_BT_SELFTEST is not set @@ -1426,6 +1450,7 @@ CONFIG_BT_HCIUART_BCSP=y # CONFIG_BT_ATH3K is not set # CONFIG_BT_MTKSDIO is not set CONFIG_BT_QCOMSMD=y +# CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1456,15 +1481,11 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y # CONFIG_RFKILL_GPIO is not set -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -# CONFIG_NET_9P_XEN is not set -# CONFIG_NET_9P_DEBUG is not set +# CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set # CONFIG_NFC is not set @@ -1474,10 +1495,11 @@ CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1500,7 +1522,6 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y # CONFIG_PCIE_DPC is not set # CONFIG_PCIE_PTM is not set -# CONFIG_PCIE_BW is not set CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y @@ -1528,6 +1549,7 @@ CONFIG_PCI_XGENE_MSI=y # CONFIG_PCIE_ALTERA is not set # CONFIG_PCI_HOST_THUNDER_PEM is not set # CONFIG_PCI_HOST_THUNDER_ECAM is not set +# CONFIG_PCIE_MICROCHIP_HOST is not set # # DesignWare PCI Core Support @@ -1545,7 +1567,6 @@ CONFIG_PCIE_QCOM=y # # Mobiveil PCIe Core Support # -# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set # end of Mobiveil PCIe Core Support # @@ -1568,14 +1589,14 @@ CONFIG_PCIE_QCOM=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set # # Generic Driver Options # -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y @@ -1637,6 +1658,7 @@ CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_QCOMSMEM_PARTS is not set # end of Partition parsers # @@ -1682,6 +1704,7 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_PMC551 is not set # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set @@ -1704,6 +1727,8 @@ CONFIG_MTD_CFI_I2=y # # ECC engine support # +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set # end of ECC engine support # end of NAND @@ -1715,6 +1740,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_MTD_UBI is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y @@ -1739,13 +1767,11 @@ CONFIG_PNPACPI=y CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SKD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set @@ -1787,9 +1813,9 @@ CONFIG_VIRTIO_BLK=y # CONFIG_DS1682 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y +# CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1818,11 +1844,13 @@ CONFIG_SRAM=y # CONFIG_ALTERA_STAPL is not set # CONFIG_GENWQE is not set # CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1877,6 +1905,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_AIC94XX is not set CONFIG_SCSI_HISI_SAS=y # CONFIG_SCSI_HISI_SAS_PCI is not set +# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set # CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_MVUMI is not set # CONFIG_SCSI_ADVANSYS is not set @@ -1887,6 +1916,7 @@ CONFIG_SCSI_HISI_SAS=y # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_MPT3SAS is not set # CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PCI=y @@ -1903,7 +1933,6 @@ CONFIG_SCSI_UFS_QCOM=y # CONFIG_SCSI_SNIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FDOMAIN_PCI is not set -# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set @@ -2039,7 +2068,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set -CONFIG_WIREGUARD=y +CONFIG_WIREGUARD=m # CONFIG_WIREGUARD_DEBUG is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set @@ -2058,12 +2087,6 @@ CONFIG_TUN=y # CONFIG_VIRTIO_NET is not set # CONFIG_NLMON is not set # CONFIG_ARCNET is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_NET_VENDOR_3COM=y # CONFIG_VORTEX is not set @@ -2092,7 +2115,6 @@ CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL1E is not set CONFIG_ATL1C=y # CONFIG_ALX is not set -# CONFIG_NET_VENDOR_AURORA is not set CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_B44 is not set # CONFIG_BCMGENET is not set @@ -2163,6 +2185,7 @@ CONFIG_IGBVF=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_JME is not set CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set @@ -2176,6 +2199,7 @@ CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLX5_CORE is not set # CONFIG_MLXSW_CORE is not set # CONFIG_MLXFW is not set +# CONFIG_MLXBF_GIGE is not set CONFIG_NET_VENDOR_MICREL=y # CONFIG_KS8842 is not set # CONFIG_KS8851 is not set @@ -2253,6 +2277,7 @@ CONFIG_DWMAC_GENERIC=m CONFIG_DWMAC_IPQ806X=m CONFIG_DWMAC_QCOM_ETHQOS=m # CONFIG_DWMAC_INTEL_PLAT is not set +# CONFIG_DWMAC_LOONGSON is not set # CONFIG_STMMAC_PCI is not set CONFIG_NET_VENDOR_SUN=y # CONFIG_HAPPYMEAL is not set @@ -2273,10 +2298,12 @@ CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5100 is not set # CONFIG_WIZNET_W5300 is not set CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set +# CONFIG_QCOM_IPA is not set # CONFIG_NET_SB1000 is not set CONFIG_PHYLINK=y CONFIG_PHYLIB=y @@ -2291,7 +2318,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=y # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -2306,11 +2333,15 @@ CONFIG_FIXED_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=m @@ -2329,7 +2360,9 @@ CONFIG_SMSC_PHY=m # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y +CONFIG_ACPI_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y # CONFIG_MDIO_BCM_UNIMAC is not set @@ -2401,6 +2434,7 @@ CONFIG_USB_NET_ZAURUS=y # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y # CONFIG_ADM8211 is not set @@ -2441,12 +2475,15 @@ CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_MAC80211_HWSIM is not set # CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_VIRT_WIFI is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_IEEE802154_DRIVERS is not set + +# +# Wireless WAN +# +# CONFIG_WWAN is not set +# end of Wireless WAN + CONFIG_XEN_NETDEV_FRONTEND=y # CONFIG_XEN_NETDEV_BACKEND is not set # CONFIG_VMXNET3 is not set @@ -2462,7 +2499,6 @@ CONFIG_NET_FAILOVER=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set @@ -2536,7 +2572,6 @@ CONFIG_MOUSE_PS2_SMBUS=y # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_PROPERTIES=y # CONFIG_TOUCHSCREEN_ADS7846 is not set # CONFIG_TOUCHSCREEN_AD7877 is not set # CONFIG_TOUCHSCREEN_AD7879 is not set @@ -2561,7 +2596,9 @@ CONFIG_TOUCHSCREEN_PROPERTIES=y # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_EKTF2127 is not set @@ -2573,6 +2610,7 @@ CONFIG_TOUCHSCREEN_PROPERTIES=y # CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set # CONFIG_TOUCHSCREEN_INEXIO is not set @@ -2644,9 +2682,11 @@ CONFIG_INPUT_PM8941_PWRKEY=y # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y # CONFIG_INPUT_SOC_BUTTON_ARRAY is not set @@ -2730,9 +2770,9 @@ CONFIG_SERIAL_MSM_CONSOLE=y # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set @@ -2748,7 +2788,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y CONFIG_HVC_IRQ=y CONFIG_HVC_XEN=y @@ -2762,19 +2801,17 @@ CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_HW_RANDOM_HISI_V2=m CONFIG_HW_RANDOM_CAVIUM=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y -# CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices -# CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # @@ -2845,6 +2882,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y # CONFIG_I2C_DESIGNWARE_PCI is not set # CONFIG_I2C_EMEV2 is not set # CONFIG_I2C_GPIO is not set +# CONFIG_I2C_HISI is not set # CONFIG_I2C_NOMADIK is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set @@ -2859,6 +2897,7 @@ CONFIG_I2C_QUP=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2892,6 +2931,7 @@ CONFIG_SPI_MEM=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_HISI_KUNPENG is not set # CONFIG_SPI_HISI_SFC_V3XX is not set # CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set @@ -2925,6 +2965,7 @@ CONFIG_SPI_SPIDEV=m # CONFIG_SPI_SLAVE is not set CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set CONFIG_SPMI_MSM_PMIC_ARB=y # CONFIG_HSI is not set CONFIG_PPS=y @@ -2949,8 +2990,10 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_KVM is not set # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2967,6 +3010,7 @@ CONFIG_PINCTRL_SINGLE=y # CONFIG_PINCTRL_STMFX is not set CONFIG_PINCTRL_MAX77620=y # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_APQ8064=y CONFIG_PINCTRL_APQ8084=y @@ -2980,6 +3024,7 @@ CONFIG_PINCTRL_MSM8960=y CONFIG_PINCTRL_MDM9615=y CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_MSM8916=y +# CONFIG_PINCTRL_MSM8953 is not set # CONFIG_PINCTRL_MSM8976 is not set CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y @@ -2989,10 +3034,16 @@ CONFIG_PINCTRL_QDF2XXX=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y # CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SC7280 is not set +# CONFIG_PINCTRL_SC8180X is not set # CONFIG_PINCTRL_SDM660 is not set # CONFIG_PINCTRL_SDM845 is not set +# CONFIG_PINCTRL_SDX55 is not set +# CONFIG_PINCTRL_SM6125 is not set # CONFIG_PINCTRL_SM8150 is not set # CONFIG_PINCTRL_SM8250 is not set +# CONFIG_PINCTRL_SM8350 is not set +# CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers @@ -3005,7 +3056,6 @@ CONFIG_OF_GPIO=y CONFIG_GPIO_ACPI=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -3022,6 +3072,7 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_FTGPIO010 is not set CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HISI is not set # CONFIG_GPIO_HLWD is not set # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set @@ -3080,8 +3131,13 @@ CONFIG_GPIO_MAX77620=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMSTB is not set @@ -3090,6 +3146,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_MSM=y # CONFIG_POWER_RESET_QCOM_PON is not set # CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_RESET_XGENE=y @@ -3120,6 +3177,7 @@ CONFIG_BATTERY_BQ27XXX_I2C=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_QCOM_SMBB is not set # CONFIG_CHARGER_BQ2415X is not set @@ -3129,8 +3187,10 @@ CONFIG_BATTERY_BQ27XXX_I2C=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set @@ -3161,6 +3221,7 @@ CONFIG_THERMAL_EMULATION=y # Qualcomm thermal drivers # CONFIG_QCOM_TSENS=y +# CONFIG_QCOM_SPMI_ADC_TM5 is not set # CONFIG_QCOM_SPMI_TEMP_ALARM is not set # end of Qualcomm thermal drivers @@ -3170,6 +3231,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -3245,6 +3307,7 @@ CONFIG_MFD_CORE=y # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_PMT is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set @@ -3267,11 +3330,13 @@ CONFIG_MFD_MAX77620=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_QCOM_RPM is not set CONFIG_MFD_SPMI_PMIC=y # CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set @@ -3280,7 +3345,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -3294,7 +3358,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TPS65086 is not set # CONFIG_MFD_TPS65090 is not set # CONFIG_MFD_TPS65217 is not set -# CONFIG_MFD_TPS68470 is not set # CONFIG_MFD_TI_LP873X is not set # CONFIG_MFD_TI_LP87565 is not set # CONFIG_MFD_TPS65218 is not set @@ -3321,8 +3384,11 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set CONFIG_MFD_VEXPRESS_SYSREG=y # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -3335,6 +3401,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set @@ -3352,6 +3419,7 @@ CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MAX77826 is not set @@ -3361,7 +3429,9 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_MT6315 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -3372,6 +3442,8 @@ CONFIG_REGULATOR_QCOM_SPMI=y # CONFIG_REGULATOR_QCOM_USB_VBUS is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y @@ -3639,13 +3711,16 @@ CONFIG_VIDEO_IR_I2C=y # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -3654,6 +3729,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -3664,8 +3740,10 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV9734 is not set # CONFIG_VIDEO_OV13858 is not set # CONFIG_VIDEO_VS6624 is not set # CONFIG_VIDEO_MT9M001 is not set @@ -3681,12 +3759,13 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -3732,7 +3811,6 @@ CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y @@ -3760,6 +3838,7 @@ CONFIG_DRM_I2C_SIL164=m # CONFIG_DRM_NOUVEAU is not set # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set +# CONFIG_DRM_VMWGFX is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set @@ -3774,7 +3853,6 @@ CONFIG_DRM_MSM_GPU_STATE=y # CONFIG_DRM_MSM_HDMI_HDCP is not set CONFIG_DRM_MSM_DP=y CONFIG_DRM_MSM_DSI=y -CONFIG_DRM_MSM_DSI_PLL=y CONFIG_DRM_MSM_DSI_28NM_PHY=y CONFIG_DRM_MSM_DSI_20NM_PHY=y CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y @@ -3786,10 +3864,12 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +# CONFIG_DRM_PANEL_DSI_CM is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set @@ -3799,6 +3879,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set @@ -3807,6 +3888,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set @@ -3823,6 +3905,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set @@ -3832,6 +3915,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set @@ -3847,9 +3931,13 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -3867,10 +3955,12 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_I2C_ADV7511_CEC=y @@ -3878,12 +3968,13 @@ CONFIG_DRM_I2C_ADV7511_CEC=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -3893,10 +3984,11 @@ CONFIG_DRM_I2C_ADV7511_CEC=y # CONFIG_TINYDRM_ST7586 is not set # CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set -# CONFIG_DRM_XEN is not set +# CONFIG_DRM_XEN_FRONTEND is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -4112,6 +4204,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_TONEPORT is not set # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -4131,6 +4224,8 @@ CONFIG_SND_SOC=y # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -4144,6 +4239,7 @@ CONFIG_SND_SOC_LPASS_APQ8016=y # CONFIG_SND_SOC_STORM is not set CONFIG_SND_SOC_APQ8016_SBC=y CONFIG_SND_SOC_QCOM_COMMON=y +# CONFIG_SND_SOC_SC7180 is not set # CONFIG_SND_SOC_SOF_TOPLEVEL is not set # @@ -4155,13 +4251,14 @@ CONFIG_SND_SOC_QCOM_COMMON=y # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -4230,16 +4327,20 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set # CONFIG_SND_SOC_SPDIF is not set # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -4256,12 +4357,14 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set @@ -4291,22 +4394,27 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y # CONFIG_SND_AUDIO_GRAPH_CARD is not set # CONFIG_SND_XEN_FRONTEND is not set +# CONFIG_SND_VIRTIO is not set # # HID support @@ -4387,11 +4495,13 @@ CONFIG_HID_OUYA=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=m +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set CONFIG_HID_SONY=y CONFIG_SONY_FF=y # CONFIG_HID_SPEEDLINK is not set @@ -4428,7 +4538,9 @@ CONFIG_USB_HID=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_ACPI is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4522,7 +4634,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_ULPI is not set @@ -4610,7 +4722,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_WWAN=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m @@ -4620,6 +4731,7 @@ CONFIG_USB_SERIAL_WISHBONE=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m # CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -4850,6 +4962,10 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set +# +# Flash and Torch LED drivers +# + # # LED Triggers # @@ -4874,6 +4990,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -4945,7 +5062,6 @@ CONFIG_RTC_DRV_S5M=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -4958,6 +5074,7 @@ CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_DRV_DS3232=y # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -4992,6 +5109,7 @@ CONFIG_RTC_DRV_PL031=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -5017,6 +5135,7 @@ CONFIG_PL330_DMA=y # CONFIG_XILINX_ZYNQMP_DMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set CONFIG_QCOM_BAM_DMA=y +# CONFIG_QCOM_GPI_DMA is not set CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y # CONFIG_DW_DMAC is not set @@ -5039,6 +5158,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set # CONFIG_DMABUF_HEAPS is not set # end of DMABUF options @@ -5056,6 +5176,7 @@ CONFIG_VFIO_PCI_INTX=y # CONFIG_VFIO_MDEV is not set # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y @@ -5096,6 +5217,7 @@ CONFIG_XEN_AUTO_XLATE=y # end of Xen driver support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y @@ -5103,10 +5225,20 @@ CONFIG_CHROME_PLATFORMS=y # CONFIG_CROS_EC is not set # CONFIG_CROS_KBD_LED_BACKLIGHT is not set # CONFIG_MELLANOX_PLATFORM is not set +# CONFIG_SURFACE_PLATFORMS is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# CONFIG_CLK_VEXPRESS_OSC is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set # CONFIG_COMMON_CLK_MAX77686 is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_SCPI=y @@ -5119,7 +5251,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_CLK_QORIQ=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_COMMON_CLK_XGENE=y # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set @@ -5128,6 +5260,7 @@ CONFIG_QCOM_GDSC=y CONFIG_QCOM_RPMCC=y CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_A53PLL=y +# CONFIG_QCOM_A7PLL is not set # CONFIG_QCOM_CLK_APCC_MSM8996 is not set CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_APQ_GCC_8084=y @@ -5143,6 +5276,7 @@ CONFIG_MSM_GCC_8916=y # CONFIG_MSM_GCC_8939 is not set CONFIG_MSM_GCC_8960=y CONFIG_MSM_LCC_8960=y +# CONFIG_MDM_GCC_9607 is not set CONFIG_MDM_GCC_9615=y CONFIG_MDM_LCC_9615=y CONFIG_MSM_MMCC_8960=y @@ -5155,14 +5289,19 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_MSM_GPUCC_8998 is not set # CONFIG_MSM_MMCC_8998 is not set # CONFIG_QCS_GCC_404 is not set +# CONFIG_SC_CAMCC_7180 is not set # CONFIG_SC_DISPCC_7180 is not set # CONFIG_SC_GCC_7180 is not set +# CONFIG_SC_GCC_7280 is not set +# CONFIG_SC_GCC_8180X is not set # CONFIG_SC_LPASS_CORECC_7180 is not set # CONFIG_SC_GPUCC_7180 is not set # CONFIG_SC_MSS_7180 is not set # CONFIG_SC_VIDEOCC_7180 is not set # CONFIG_SDM_CAMCC_845 is not set # CONFIG_SDM_GCC_660 is not set +# CONFIG_SDM_MMCC_660 is not set +# CONFIG_SDM_GPUCC_660 is not set # CONFIG_QCS_TURING_404 is not set # CONFIG_QCS_Q6SSTOP_404 is not set # CONFIG_SDM_GCC_845 is not set @@ -5170,8 +5309,12 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_SDM_VIDEOCC_845 is not set # CONFIG_SDM_DISPCC_845 is not set # CONFIG_SDM_LPASSCC_845 is not set +# CONFIG_SDX_GCC_55 is not set +# CONFIG_SM_CAMCC_8250 is not set +# CONFIG_SM_GCC_6125 is not set # CONFIG_SM_GCC_8150 is not set # CONFIG_SM_GCC_8250 is not set +# CONFIG_SM_GCC_8350 is not set # CONFIG_SM_GPUCC_8150 is not set # CONFIG_SM_GPUCC_8250 is not set # CONFIG_SM_VIDEOCC_8150 is not set @@ -5179,6 +5322,8 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_SPMI_PMIC_CLKDIV is not set # CONFIG_QCOM_HFPLL is not set # CONFIG_KPSS_XCC is not set +# CONFIG_CLK_GFM_LPASS_SM8250 is not set +# CONFIG_XILINX_VCU is not set CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y @@ -5199,6 +5344,7 @@ CONFIG_ARM64_ERRATUM_858921=y CONFIG_MAILBOX=y CONFIG_ARM_MHU=y +CONFIG_ARM_MHU_V2=m # CONFIG_PLATFORM_MHU is not set # CONFIG_PL320_MBOX is not set # CONFIG_PCC is not set @@ -5250,6 +5396,7 @@ CONFIG_QCOM_WCNSS_PIL=m # CONFIG_RPMSG=y CONFIG_RPMSG_CHAR=y +# CONFIG_RPMSG_NS is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_QCOM_GLINK_SMEM is not set CONFIG_RPMSG_QCOM_SMD=y @@ -5267,11 +5414,6 @@ CONFIG_RPMSG_QCOM_SMD=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -5290,6 +5432,12 @@ CONFIG_RPMSG_QCOM_SMD=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # @@ -5319,7 +5467,6 @@ CONFIG_QCOM_WCNSS_CTRL=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5352,6 +5499,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y +# CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set CONFIG_IIO=y # CONFIG_IIO_BUFFER is not set @@ -5374,11 +5522,14 @@ CONFIG_IIO=y # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -5392,6 +5543,7 @@ CONFIG_IIO=y # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -5418,7 +5570,6 @@ CONFIG_IIO=y # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set -# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set @@ -5455,7 +5606,9 @@ CONFIG_IIO=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -5473,6 +5626,12 @@ CONFIG_IIO=y # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -5483,7 +5642,7 @@ CONFIG_IIO=y # CONFIG_IAQCORE is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5492,6 +5651,11 @@ CONFIG_IIO=y # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -5517,6 +5681,7 @@ CONFIG_IIO=y # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -5620,6 +5785,7 @@ CONFIG_IIO=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -5662,6 +5828,7 @@ CONFIG_IIO=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -5688,6 +5855,7 @@ CONFIG_IIO=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -5785,6 +5953,7 @@ CONFIG_IIO=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -5795,6 +5964,8 @@ CONFIG_IIO=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set @@ -5816,8 +5987,7 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_TI_SYSCON is not set @@ -5827,6 +5997,7 @@ CONFIG_RESET_CONTROLLER=y # CONFIG_GENERIC_PHY=y CONFIG_PHY_XGENE=y +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -5866,10 +6037,12 @@ CONFIG_PHY_SAMSUNG_USB2=y # CONFIG_ARM_CMN is not set CONFIG_ARM_PMU=y CONFIG_ARM_PMU_ACPI=y +# CONFIG_ARM_SMMU_V3_PMU is not set # CONFIG_ARM_DSU_PMU is not set # CONFIG_QCOM_L2_PMU is not set # CONFIG_QCOM_L3_PMU is not set # CONFIG_ARM_SPE_PMU is not set +# CONFIG_ARM_DMC620_PMU is not set # CONFIG_HISI_PMU is not set # end of Performance monitor support @@ -5888,6 +6061,7 @@ CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_QCOM_QFPROM=y # CONFIG_NVMEM_SPMI_SDAM is not set +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -6013,6 +6187,7 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_INODE64 is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -6070,7 +6245,7 @@ CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y -CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" # CONFIG_NFS_V4_1_MIGRATION is not set CONFIG_NFS_V4_SECURITY_LABEL=y @@ -6089,6 +6264,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -6097,9 +6273,6 @@ CONFIG_SUNRPC_BACKCHANNEL=y # CONFIG_CIFS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -CONFIG_9P_FS=y -# CONFIG_9P_FS_POSIX_ACL is not set -# CONFIG_9P_FS_SECURITY is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -6181,10 +6354,12 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y # CONFIG_IMA is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set # CONFIG_EVM is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="yama,loadpin,safesetid,integrity" @@ -6252,6 +6427,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -6304,17 +6480,13 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=y -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -6331,7 +6503,6 @@ CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -6401,6 +6572,7 @@ CONFIG_CRYPTO_DEV_VIRTIO=m # CONFIG_CRYPTO_DEV_HISI_SEC2 is not set # CONFIG_CRYPTO_DEV_HISI_ZIP is not set # CONFIG_CRYPTO_DEV_HISI_HPRE is not set +# CONFIG_CRYPTO_DEV_HISI_TRNG is not set # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y @@ -6420,6 +6592,8 @@ CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking +CONFIG_BINARY_PRINTF=y + # # Library routines # @@ -6432,6 +6606,7 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6454,7 +6629,7 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC4 is not set CONFIG_CRC7=y CONFIG_LIBCRC32C=y -# CONFIG_CRC8 is not set +CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_AUDIT_GENERIC=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y @@ -6515,6 +6690,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -6537,9 +6713,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -6549,6 +6726,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -6566,10 +6744,11 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set # CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set # CONFIG_DEBUG_INFO_BTF is not set # CONFIG_GDB_SCRIPTS is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -6629,9 +6808,12 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6682,10 +6864,10 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y # # Debug kernel data structures @@ -6724,7 +6906,6 @@ CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # @@ -6740,9 +6921,11 @@ CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y CONFIG_CORESIGHT_SINK_TPIU=y CONFIG_CORESIGHT_SINK_ETBV10=y CONFIG_CORESIGHT_SOURCE_ETM4X=y +# CONFIG_ETM4X_IMPDEF_FEATURE is not set # CONFIG_CORESIGHT_STM is not set # CONFIG_CORESIGHT_CPU_DEBUG is not set # CONFIG_CORESIGHT_CTI is not set +# CONFIG_CORESIGHT_TRBE is not set # end of arm64 Debugging # @@ -6756,9 +6939,9 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set +# CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set @@ -6766,10 +6949,12 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set @@ -6793,6 +6978,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking From 4841ef5929731b2e2684a73203aa0ff1b4cb08a8 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Sun, 22 Aug 2021 14:52:38 +1000 Subject: [PATCH 50/51] linux (Samsung): tidy up .config for 5.14 --- projects/Samsung/linux/linux.arm.conf | 343 ++++++++++++++++++-------- 1 file changed, 238 insertions(+), 105 deletions(-) diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf index 91c83777fb..a46bda05f7 100644 --- a/projects/Samsung/linux/linux.arm.conf +++ b/projects/Samsung/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.20 Kernel Configuration +# Linux/arm 5.14.0-rc6 Kernel Configuration # Compiler: armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0 # CONFIG_CC_IS_GCC=y @@ -81,6 +81,18 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y @@ -111,6 +123,7 @@ CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y +CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem @@ -138,7 +151,10 @@ CONFIG_CGROUPS=y # CONFIG_CGROUP_DEVICE is not set # CONFIG_CGROUP_CPUACCT is not set # CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y @@ -174,7 +190,6 @@ CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y -CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -200,7 +215,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_BPF_SYSCALL is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -255,7 +269,6 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_IOP32X is not set @@ -290,21 +303,18 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_DIGICOLOR is not set CONFIG_ARCH_EXYNOS=y CONFIG_S5P_DEV_MFC=y -CONFIG_ARCH_EXYNOS3=y -CONFIG_ARCH_EXYNOS4=y +# CONFIG_ARCH_EXYNOS3 is not set +# CONFIG_ARCH_EXYNOS4 is not set CONFIG_ARCH_EXYNOS5=y # # Exynos SoCs # -CONFIG_SOC_EXYNOS3250=y -CONFIG_CPU_EXYNOS4210=y -CONFIG_SOC_EXYNOS4412=y -CONFIG_SOC_EXYNOS5250=y -CONFIG_SOC_EXYNOS5260=y -CONFIG_SOC_EXYNOS5410=y +# CONFIG_SOC_EXYNOS5250 is not set +# CONFIG_SOC_EXYNOS5260 is not set +# CONFIG_SOC_EXYNOS5410 is not set CONFIG_SOC_EXYNOS5420=y -CONFIG_SOC_EXYNOS5800=y +# CONFIG_SOC_EXYNOS5800 is not set CONFIG_EXYNOS_MCPM=y CONFIG_EXYNOS_CPU_SUSPEND=y # CONFIG_ARCH_HIGHBANK is not set @@ -330,7 +340,6 @@ CONFIG_EXYNOS_CPU_SUSPEND=y # CONFIG_SOC_DRA7XX is not set # end of TI OMAP/AM/DM/DRA Family -# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set @@ -338,18 +347,16 @@ CONFIG_EXYNOS_CPU_SUSPEND=y # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_TANGO is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set -# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQ is not set # @@ -401,14 +408,14 @@ CONFIG_ARM_HEAVY_MB=y CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y CONFIG_DEBUG_ALIGN_RODATA=y # CONFIG_ARM_ERRATA_430973 is not set -CONFIG_ARM_ERRATA_643719=y +# CONFIG_ARM_ERRATA_643719 is not set # CONFIG_ARM_ERRATA_720789 is not set # CONFIG_ARM_ERRATA_754322 is not set # CONFIG_ARM_ERRATA_754327 is not set # CONFIG_ARM_ERRATA_764369 is not set # CONFIG_ARM_ERRATA_775420 is not set -# CONFIG_ARM_ERRATA_798181 is not set -# CONFIG_ARM_ERRATA_773022 is not set +CONFIG_ARM_ERRATA_798181=y +CONFIG_ARM_ERRATA_773022=y # CONFIG_ARM_ERRATA_818325_852422 is not set # CONFIG_ARM_ERRATA_821420 is not set # CONFIG_ARM_ERRATA_825619 is not set @@ -460,11 +467,9 @@ CONFIG_SCHED_HRTICK=y CONFIG_ARM_PATCH_IDIV=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y @@ -612,11 +617,13 @@ CONFIG_CRYPTO_SHA1_ARM_NEON=m # CONFIG_CRYPTO_SHA2_ARM_CE is not set CONFIG_CRYPTO_SHA256_ARM=m CONFIG_CRYPTO_SHA512_ARM=m -# CONFIG_CRYPTO_AES_ARM is not set +CONFIG_CRYPTO_BLAKE2S_ARM=y +CONFIG_CRYPTO_BLAKE2B_NEON=m +CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m # CONFIG_CRYPTO_AES_ARM_CE is not set -# CONFIG_CRYPTO_GHASH_ARM_CE is not set -# CONFIG_CRYPTO_CRC32_ARM_CE is not set +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=y CONFIG_CRYPTO_POLY1305_ARM=y # CONFIG_CRYPTO_NHPOLY1305_NEON is not set @@ -627,7 +634,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y # General architecture-dependent options # CONFIG_SET_FS=y -CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_UPROBES=y @@ -652,14 +658,17 @@ CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -683,6 +692,7 @@ CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling @@ -707,10 +717,12 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y @@ -790,7 +802,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 @@ -806,15 +817,15 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 # CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +CONFIG_KMAP_LOCAL=y # end of Memory Management options CONFIG_NET=y @@ -838,6 +849,7 @@ CONFIG_XFRM_ALGO=y # CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y # CONFIG_NET_KEY_MIGRATE is not set +# CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set @@ -851,7 +863,7 @@ CONFIG_NET_IP_TUNNEL=y # CONFIG_IP_MROUTE is not set # CONFIG_SYN_COOKIES is not set # CONFIG_NET_IPVTI is not set -CONFIG_NET_UDP_TUNNEL=y +CONFIG_NET_UDP_TUNNEL=m CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set @@ -897,7 +909,6 @@ CONFIG_IPV6_FOU=m # CONFIG_ATM is not set # CONFIG_L2TP is not set # CONFIG_BRIDGE is not set -CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set @@ -922,14 +933,16 @@ CONFIG_DNS_RESOLVER=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set +# CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y # @@ -954,6 +967,7 @@ CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set CONFIG_BT_DEBUGFS=y # CONFIG_BT_SELFTEST is not set @@ -1012,7 +1026,6 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1026,9 +1039,10 @@ CONFIG_RFKILL_INPUT=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y # CONFIG_FAILOVER is not set CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1149,7 +1163,6 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_SRAM=y CONFIG_SRAM_EXEC=y # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_C2PORT is not set @@ -1178,6 +1191,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices # @@ -1255,7 +1269,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set -CONFIG_WIREGUARD=y +CONFIG_WIREGUARD=m # CONFIG_WIREGUARD_DEBUG is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set @@ -1275,19 +1289,12 @@ CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m # CONFIG_NLMON is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_ALTERA_TSE is not set # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set @@ -1301,6 +1308,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1335,7 +1343,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set +CONFIG_AX88796B_PHY=y # CONFIG_BROADCOM_PHY is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set @@ -1350,11 +1358,15 @@ CONFIG_FIXED_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set @@ -1374,6 +1386,7 @@ CONFIG_SMSC_PHY=y # CONFIG_MICREL_KS8995MA is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_BITBANG is not set @@ -1436,6 +1449,7 @@ CONFIG_USB_IPHETH=m # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y # CONFIG_WLAN_VENDOR_ADMTEK is not set CONFIG_ATH_COMMON=m @@ -1550,11 +1564,14 @@ CONFIG_RTW88=m # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set # -# Enable WiMAX (Networking options) to see the WiMAX drivers +# Wireless WAN # -# CONFIG_WAN is not set +# CONFIG_WWAN is not set +# end of Wireless WAN + # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set @@ -1566,7 +1583,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y @@ -1615,7 +1631,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_PROPERTIES=y CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_AD7877 is not set # CONFIG_TOUCHSCREEN_AD7879 is not set @@ -1639,7 +1654,9 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_EKTF2127 is not set @@ -1651,6 +1668,7 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set # CONFIG_TOUCHSCREEN_INEXIO is not set @@ -1704,9 +1722,11 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_CMA3000 is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -1791,7 +1811,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set @@ -1805,7 +1824,6 @@ CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_HVC_DCC is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_VIRTIO_CONSOLE is not set @@ -1817,12 +1835,11 @@ CONFIG_HW_RANDOM_EXYNOS=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set -# CONFIG_RAW_DRIVER is not set CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set # CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C_CR50 is not set # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_I2C_NUVOTON is not set @@ -1831,6 +1848,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_ST33ZP24_I2C is not set # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set # end of Character devices # CONFIG_RANDOM_TRUST_BOOTLOADER is not set @@ -1888,6 +1906,7 @@ CONFIG_I2C_S3C2410=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -1970,6 +1989,7 @@ CONFIG_PINCONF=y # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # # Renesas pinctrl drivers @@ -1984,7 +2004,6 @@ CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_DEBUG_GPIO=y -# CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y @@ -2048,8 +2067,13 @@ CONFIG_GPIO_WM8994=y # # end of USB GPIO expanders +# +# Virtual GPIO drivers +# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + # CONFIG_W1 is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMKONA is not set @@ -2057,6 +2081,7 @@ CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_VERSATILE is not set CONFIG_POWER_RESET_SYSCON=y @@ -2085,6 +2110,7 @@ CONFIG_BATTERY_MAX17042=y # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set CONFIG_CHARGER_MAX14577=y # CONFIG_CHARGER_DETECTOR_MAX14656 is not set CONFIG_CHARGER_MAX77693=y @@ -2097,9 +2123,11 @@ CONFIG_CHARGER_MAX8998=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set CONFIG_CHARGER_TPS65090=y # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set @@ -2126,12 +2154,14 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2153,6 +2183,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2160,6 +2191,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -2174,6 +2206,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -2200,13 +2233,16 @@ CONFIG_SENSORS_NTC_THERMISTOR=y # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set @@ -2279,6 +2315,7 @@ CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors @@ -2372,9 +2409,11 @@ CONFIG_MFD_MAX8998=y # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set +# CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set @@ -2383,7 +2422,6 @@ CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -2425,8 +2463,11 @@ CONFIG_MFD_WM8994=y # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers @@ -2438,6 +2479,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set @@ -2455,6 +2497,7 @@ CONFIG_REGULATOR_MAX14577=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set CONFIG_REGULATOR_MAX8952=y # CONFIG_REGULATOR_MAX8973 is not set CONFIG_REGULATOR_MAX8997=y @@ -2470,6 +2513,7 @@ CONFIG_REGULATOR_MAX77802=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -2477,6 +2521,8 @@ CONFIG_REGULATOR_MAX77802=y # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTMV20 is not set CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y @@ -2530,6 +2576,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m # end of Video4Linux options # @@ -2728,13 +2775,16 @@ CONFIG_VIDEOBUF2_VMALLOC=m # Camera sensor devices # # CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -2742,6 +2792,7 @@ CONFIG_VIDEOBUF2_VMALLOC=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -2752,6 +2803,7 @@ CONFIG_VIDEOBUF2_VMALLOC=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -2769,12 +2821,13 @@ CONFIG_VIDEOBUF2_VMALLOC=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set CONFIG_VIDEO_S5K6A3=m # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set CONFIG_VIDEO_S5C73M3=m # end of Camera sensor devices @@ -2819,7 +2872,6 @@ CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set @@ -2884,10 +2936,12 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +# CONFIG_DRM_PANEL_DSI_CM is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set @@ -2897,6 +2951,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set @@ -2905,6 +2960,7 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set @@ -2921,6 +2977,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set @@ -2930,6 +2987,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set @@ -2945,9 +3003,13 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NWL_MIPI_DSI is not set @@ -2965,20 +3027,23 @@ CONFIG_DRM_TOSHIBA_TC358764=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set CONFIG_DRM_ANALOGIX_DP=y +# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set # end of Display Interface Bridges # CONFIG_DRM_STI is not set # CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set @@ -2993,6 +3058,7 @@ CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_PANFROST is not set # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3129,6 +3195,7 @@ CONFIG_SND_USB=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -3148,6 +3215,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -3177,7 +3245,6 @@ CONFIG_SND_SOC_ODROID=y # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y # @@ -3185,6 +3252,8 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -3253,16 +3322,20 @@ CONFIG_SND_SOC_MAX98090=y # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_RT5631=y +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set # CONFIG_SND_SOC_SPDIF is not set # CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -3279,12 +3352,14 @@ CONFIG_SND_SOC_RT5631=y # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set # CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set @@ -3315,16 +3390,20 @@ CONFIG_SND_SOC_RT5631=y # CONFIG_SND_SOC_WM8985 is not set CONFIG_SND_SOC_WM8994=y # CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y @@ -3410,11 +3489,13 @@ CONFIG_HID_MONTEREY=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SPEEDLINK is not set # CONFIG_HID_STEAM is not set @@ -3450,7 +3531,8 @@ CONFIG_USB_HID=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -3542,7 +3624,7 @@ CONFIG_REALTEK_AUTOPM=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_HOST is not set @@ -3758,6 +3840,12 @@ CONFIG_LEDS_MAX8997=y # CONFIG_LEDS_TI_LMU_COMMON is not set # CONFIG_LEDS_SGM3140 is not set +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set + # # LED Triggers # @@ -3780,6 +3868,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -3853,7 +3942,6 @@ CONFIG_RTC_DRV_S5M=y # CONFIG_RTC_DRV_MAX6916 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_PCF2123 is not set @@ -3866,6 +3954,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -3901,6 +3990,7 @@ CONFIG_RTC_DRV_S3C=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -3936,6 +4026,7 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set CONFIG_UDMABUF=y # CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -3956,9 +4047,9 @@ CONFIG_DMABUF_HEAPS_CMA=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set -# CONFIG_COMEDI is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m CONFIG_R8712U=m @@ -3992,7 +4083,6 @@ CONFIG_VT6656=m # # Capacitance to digital converters # -# CONFIG_AD7150 is not set # CONFIG_AD7746 is not set # end of Capacitance to digital converters @@ -4036,12 +4126,6 @@ CONFIG_VT6656=m # CONFIG_FB_TFT is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set - -# -# Gasket devices -# -# end of Gasket devices - # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set @@ -4049,9 +4133,17 @@ CONFIG_VT6656=m # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set CONFIG_COMMON_CLK_MAX77686=y # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set @@ -4063,12 +4155,15 @@ CONFIG_COMMON_CLK_MAX77686=y # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set CONFIG_COMMON_CLK_S2MPS11=y -# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_COMMON_CLK_SAMSUNG=y +CONFIG_EXYNOS_5420_COMMON_CLK=y CONFIG_EXYNOS_AUDSS_CLK_CON=y +CONFIG_EXYNOS_CLKOUT=m +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -4079,7 +4174,6 @@ CONFIG_TIMER_PROBE=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_CLKSRC_EXYNOS_MCT=y -CONFIG_CLKSRC_SAMSUNG_PWM=y # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers @@ -4126,11 +4220,6 @@ CONFIG_EXYNOS_IOMMU=y # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -4149,25 +4238,28 @@ CONFIG_EXYNOS_IOMMU=y # # end of i.MX SoC drivers +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + # # Qualcomm SoC drivers # # end of Qualcomm SoC drivers CONFIG_SOC_SAMSUNG=y -CONFIG_EXYNOS_ASV=y CONFIG_EXYNOS_ASV_ARM=y CONFIG_EXYNOS_CHIPID=y CONFIG_EXYNOS_PMU=y CONFIG_EXYNOS_PMU_ARM_DRIVERS=y CONFIG_EXYNOS_PM_DOMAINS=y -CONFIG_EXYNOS_REGULATOR_COUPLER=y # CONFIG_SOC_TI is not set # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -4205,6 +4297,7 @@ CONFIG_EXTCON_MAX8997=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_MEMORY=y CONFIG_DDR=y # CONFIG_ARM_PL172_MPMC is not set @@ -4240,11 +4333,14 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -4258,6 +4354,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set # end of Accelerometers @@ -4284,7 +4381,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set -# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set @@ -4318,7 +4414,9 @@ CONFIG_EXYNOS_ADC=y # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set # CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set # CONFIG_VF610_ADC is not set # CONFIG_XILINX_XADC is not set # end of Analog to digital converters @@ -4336,6 +4434,12 @@ CONFIG_EXYNOS_ADC=y # CONFIG_HMC425 is not set # end of Amplifiers +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + # # Chemical Sensors # @@ -4346,7 +4450,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_IAQCORE is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set +# CONFIG_SPS30_I2C is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -4355,6 +4459,11 @@ CONFIG_EXYNOS_ADC=y # # end of Hid Sensor IIO Common +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + # # SSP Sensor Common # @@ -4380,6 +4489,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -4483,6 +4593,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set # end of Inertial measurement units # @@ -4524,6 +4635,7 @@ CONFIG_CM36651=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set @@ -4550,6 +4662,7 @@ CONFIG_AK8975=y # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -4654,6 +4767,7 @@ CONFIG_AK8975=y # CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set @@ -4662,6 +4776,7 @@ CONFIG_AK8975=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SAMSUNG=y @@ -4672,7 +4787,6 @@ CONFIG_PWM_SAMSUNG=y CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 -CONFIG_GIC_NON_BANKED=y # CONFIG_AL_FIC is not set CONFIG_EXYNOS_IRQ_COMBINER=y # end of IRQ chip support @@ -4684,6 +4798,7 @@ CONFIG_EXYNOS_IRQ_COMBINER=y # PHY Subsystem # CONFIG_GENERIC_PHY=y +# CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -4700,11 +4815,8 @@ CONFIG_PHY_EXYNOS_MIPI_VIDEO=y # CONFIG_PHY_EXYNOS_PCIE is not set # CONFIG_PHY_SAMSUNG_UFS is not set CONFIG_PHY_SAMSUNG_USB2=y -CONFIG_PHY_EXYNOS4210_USB2=y -CONFIG_PHY_EXYNOS4X12_USB2=y CONFIG_PHY_EXYNOS5250_USB2=y CONFIG_PHY_EXYNOS5_USBDRD=y -CONFIG_PHY_EXYNOS5250_SATA=y # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -4729,6 +4841,7 @@ CONFIG_ARM_PMU=y # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -4784,7 +4897,7 @@ CONFIG_XFS_SUPPORT_V4=y # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m -# CONFIG_BTRFS_FS_POSIX_ACL is not set +CONFIG_BTRFS_FS_POSIX_ACL=y # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set @@ -4823,6 +4936,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -4918,7 +5033,7 @@ CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y CONFIG_PNFS_BLOCK=y -CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_NFS_V4_1_MIGRATION=y CONFIG_ROOT_NFS=y @@ -4932,6 +5047,7 @@ CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -4946,6 +5062,7 @@ CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set @@ -5085,6 +5202,7 @@ CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -5137,17 +5255,13 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # @@ -5164,7 +5278,6 @@ CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -CONFIG_CRYPTO_SALSA20=m # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set @@ -5207,7 +5320,7 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y CONFIG_CRYPTO_LIB_CHACHA=y @@ -5332,6 +5445,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -5363,9 +5477,10 @@ CONFIG_FONT_7x14=y # CONFIG_FONT_6x8 is not set CONFIG_SG_POOL=y CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set # end of Library routines +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + # # Kernel hacking # @@ -5375,6 +5490,7 @@ CONFIG_SBITMAP=y # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -5392,10 +5508,11 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_REDUCED is not set # CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set # CONFIG_DEBUG_INFO_BTF is not set # CONFIG_GDB_SCRIPTS is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -5446,9 +5563,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set +CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -5492,6 +5612,11 @@ CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y +CONFIG_LOCKDEP_BITS=15 +CONFIG_LOCKDEP_CHAINS_BITS=16 +CONFIG_LOCKDEP_STACK_TRACE_BITS=19 +CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 +CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 # CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set @@ -5501,6 +5626,7 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -5556,6 +5682,8 @@ CONFIG_FTRACE=y # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_HWLAT_TRACER is not set +# CONFIG_OSNOISE_TRACER is not set +# CONFIG_TIMERLAT_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_FTRACE_SYSCALLS is not set # CONFIG_TRACER_SNAPSHOT is not set @@ -5564,17 +5692,19 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_BLK_DEV_IO_TRACE is not set CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y # CONFIG_SYNTH_EVENTS is not set +# CONFIG_HIST_TRIGGERS is not set # CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set # CONFIG_TRACE_EVAL_MAP_FILE is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # @@ -5603,9 +5733,9 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set +# CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set @@ -5613,10 +5743,12 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set @@ -5640,6 +5772,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # end of Kernel hacking From 85ccd078f14e78785661099eb5de1c2204acad48 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Mon, 19 Jul 2021 12:13:00 +0000 Subject: [PATCH 51/51] linux: update to 5.14 --- packages/linux/package.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 60b1984a8f..a8309581cf 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -28,8 +28,8 @@ case "${LINUX}" in PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" ;; *) - PKG_VERSION="5.10.61" - PKG_SHA256="82eae38cc5cd11dd6aaac91c02ff0d006c7bafd6d4cf5c6a791930820a3a91d1" + PKG_VERSION="5.14" + PKG_SHA256="7e068b5e0d26a62b10e5320b25dce57588cbbc6f781c090442138c9c9c3271b2" PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" PKG_PATCH_DIRS="default" ;;