diff --git a/packages/linux-drivers/RTL8188EU/package.mk b/packages/linux-drivers/RTL8188EU/package.mk index bfe80b5b24..5aa42e58a1 100644 --- a/packages/linux-drivers/RTL8188EU/package.mk +++ b/packages/linux-drivers/RTL8188EU/package.mk @@ -3,8 +3,8 @@ # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) PKG_NAME="RTL8188EU" -PKG_VERSION="b02c92bc92e22fd8b51c9acd6d602637cfce7256" -PKG_SHA256="e855e210b27fc33212c558d34c32e0a5ccc32209d5c7e3f71fcf67695c224594" +PKG_VERSION="a69d6361ef0185aa7d2e4c774bc2de36fe83d81e" +PKG_SHA256="3e0f7506e4fe3c22cb8b7ccccb0cc778360545c5cb248119590912273b0bf8dc" PKG_LICENSE="GPL" # realtek: PKG_SITE="http://www.realtek.com.tw/downloads/downloadsView.aspx?Langid=1&PFid=48&Level=5&Conn=4&ProdID=274&DownTypeID=3&GetDown=false&Downloads=true" PKG_SITE="https://github.com/lwfinger/rtl8188eu" diff --git a/packages/linux-drivers/RTL8192CU/package.mk b/packages/linux-drivers/RTL8192CU/package.mk index 8d4270566c..664bef3a61 100644 --- a/packages/linux-drivers/RTL8192CU/package.mk +++ b/packages/linux-drivers/RTL8192CU/package.mk @@ -3,8 +3,8 @@ # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) PKG_NAME="RTL8192CU" -PKG_VERSION="7a15cb42e568b0f9c3c872bd6a06cdcab9f0ffd0" -PKG_SHA256="93cd979956ab3f60618707cd11395549ecff17135fa969e25f031a1f06453a7d" +PKG_VERSION="0f12fc0a99d5b020ccbe1e6e43aa2e866d578e4d" +PKG_SHA256="e94e4e0f0454d4643b06723204883cea83ad56687ea8fe3a43d9650833146877" PKG_LICENSE="GPL" PKG_SITE="https://github.com/pvaret/rtl8192cu-fixes" PKG_URL="${PKG_SITE}/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/linux-drivers/RTL8192DU/patches/5-15-0.patch b/packages/linux-drivers/RTL8192DU/patches/5-15-0.patch new file mode 100644 index 0000000000..92130e1cb2 --- /dev/null +++ b/packages/linux-drivers/RTL8192DU/patches/5-15-0.patch @@ -0,0 +1,61 @@ +--- a/core/rtw_br_ext.c 2021-10-10 13:28:28.410328649 +1100 ++++ b/core/rtw_br_ext.c 2021-10-10 13:28:28.410328649 +1100 +@@ -22,7 +22,10 @@ + #ifdef __KERNEL__ + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0) + #include ++#endif + #include + #include + #include +@@ -175,6 +175,7 @@ + } + + ++#ifdef _NET_INET_IPX_H_ + static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr) + { +@@ -195,6 +196,7 @@ + memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4); + memcpy(networkAddr+5, (unsigned char *)ipxSocketAddr, 2); + } ++#endif + + + static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr, +@@ -341,6 +343,7 @@ + + return x & (NAT25_HASH_SIZE - 1); + } ++#ifdef _NET_INET_IPX_H_ + else if(networkAddr[0] == NAT25_IPX) + { + unsigned long x; +@@ -350,6 +353,7 @@ + + return x & (NAT25_HASH_SIZE - 1); + } ++#endif + else if(networkAddr[0] == NAT25_APPLE) + { + unsigned long x; +@@ -932,6 +936,7 @@ + } + } + ++#ifdef _NET_INET_IPX_H_ + /*---------------------------------------------------*/ + /* Handle IPX and Apple Talk frame */ + /*---------------------------------------------------*/ +@@ -1195,6 +1200,7 @@ + + return -1; + } ++#endif + + /*---------------------------------------------------*/ + /* Handle PPPoE frame */ diff --git a/packages/linux-drivers/RTL8192EU/package.mk b/packages/linux-drivers/RTL8192EU/package.mk index 017af054ae..ce5db333fb 100644 --- a/packages/linux-drivers/RTL8192EU/package.mk +++ b/packages/linux-drivers/RTL8192EU/package.mk @@ -3,8 +3,8 @@ # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) PKG_NAME="RTL8192EU" -PKG_VERSION="faf68bbf82623335e7997a473f9222751e275927" -PKG_SHA256="f6988f1f0a4128cf935c2d09cd45a782f46414dc1a8d7c992c05ed7d565ac922" +PKG_VERSION="4c9751be79ef847ef44ef63203278f4f05f21e52" +PKG_SHA256="09a957d70eeec4042116b95a6614676645346dece3c53a467a1a13e8b33a1c83" PKG_LICENSE="GPL" PKG_SITE="https://github.com/Mange/rtl8192eu-linux-driver" PKG_URL="https://github.com/Mange/rtl8192eu-linux-driver/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/linux-drivers/RTL8812AU/package.mk b/packages/linux-drivers/RTL8812AU/package.mk index 81ae08ddd3..2859c8a4c5 100644 --- a/packages/linux-drivers/RTL8812AU/package.mk +++ b/packages/linux-drivers/RTL8812AU/package.mk @@ -3,8 +3,8 @@ # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) PKG_NAME="RTL8812AU" -PKG_VERSION="64e7aaa5657ef63ab7ce74ce5554b49a21552e68" -PKG_SHA256="1b7a79b15348f1a1125a351e5e5ff524456236519e20ee04b59484aefa6afbaa" +PKG_VERSION="b8167e66b4ac046b3b76c2c40008d84528e91594" +PKG_SHA256="2c5d8286a00273343fc10d0e16afc52e788ac73b7df57c8159e58a40707f61da" PKG_LICENSE="GPL" PKG_SITE="https://github.com/aircrack-ng/rtl8812au" PKG_URL="https://github.com/aircrack-ng/rtl8812au/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/linux-drivers/RTL8812AU/patches/5-15-0.patch b/packages/linux-drivers/RTL8812AU/patches/5-15-0.patch new file mode 100644 index 0000000000..87ec95c981 --- /dev/null +++ b/packages/linux-drivers/RTL8812AU/patches/5-15-0.patch @@ -0,0 +1,61 @@ +--- a/core/rtw_br_ext.c 2021-01-11 21:31:47.000000000 +1100 ++++ b/core/rtw_br_ext.c 2021-10-10 14:16:13.942229163 +1100 +@@ -17,7 +17,10 @@ + #ifdef __KERNEL__ + #include + #include ++ #include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0) + #include ++#endif + #include + #include + #include +@@ -169,6 +172,7 @@ + } + + ++#ifdef _NET_INET_IPX_H_ + static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr) + { +@@ -189,6 +193,7 @@ + memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4); + memcpy(networkAddr + 5, (unsigned char *)ipxSocketAddr, 2); + } ++#endif + + + static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr, +@@ -330,6 +335,7 @@ + x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + + return x & (NAT25_HASH_SIZE - 1); ++#ifdef _NET_INET_IPX_H_ + } else if (networkAddr[0] == NAT25_IPX) { + unsigned long x; + +@@ -337,6 +343,7 @@ + networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + + return x & (NAT25_HASH_SIZE - 1); ++#endif + } else if (networkAddr[0] == NAT25_APPLE) { + unsigned long x; + +@@ -889,6 +896,7 @@ + } + } + ++#ifdef _NET_INET_IPX_H_ + /*---------------------------------------------------*/ + /* Handle IPX and Apple Talk frame */ + /*---------------------------------------------------*/ +@@ -1109,6 +1117,7 @@ + + return -1; + } ++#endif + + /*---------------------------------------------------*/ + /* Handle PPPoE frame */ diff --git a/packages/linux-drivers/RTL8812AU/patches/Fix-GRO_DROP-deprecation-kernel-5-12.patch b/packages/linux-drivers/RTL8812AU/patches/Fix-GRO_DROP-deprecation-kernel-5-12.patch deleted file mode 100644 index c544a07ec7..0000000000 --- a/packages/linux-drivers/RTL8812AU/patches/Fix-GRO_DROP-deprecation-kernel-5-12.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e7e83f2593c9e67e3ee50d032f1ad39fe47ea81d Mon Sep 17 00:00:00 2001 -From: Carlos -Date: Sat, 3 Apr 2021 14:38:14 +0000 -Subject: [PATCH] Fix GRO_DROP deprecation kernel 5.12 - ---- - os_dep/linux/recv_linux.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/os_dep/linux/recv_linux.c b/os_dep/linux/recv_linux.c -index 2f7b3e37..7fecc843 100644 ---- a/os_dep/linux/recv_linux.c -+++ b/os_dep/linux/recv_linux.c -@@ -355,8 +355,12 @@ static int napi_recv(_adapter *padapter, int budget) - - #ifdef CONFIG_RTW_GRO - if (pregistrypriv->en_gro) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0) - if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP) - rx_ok = _TRUE; -+#else -+ rx_ok = _TRUE; -+#endif - goto next; - } - #endif /* CONFIG_RTW_GRO */ diff --git a/packages/linux-drivers/RTL8812AU/patches/Revert-issue-768-don-t-apply-ARM-options-to-ARM64.patch b/packages/linux-drivers/RTL8812AU/patches/Revert-issue-768-don-t-apply-ARM-options-to-ARM64.patch deleted file mode 100644 index bd3aa2d3c9..0000000000 --- a/packages/linux-drivers/RTL8812AU/patches/Revert-issue-768-don-t-apply-ARM-options-to-ARM64.patch +++ /dev/null @@ -1,68 +0,0 @@ -From a6daa2907399a2df2c3c1b576fe6256805766c71 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 12 Jan 2021 22:16:43 +0100 -Subject: [PATCH] Revert "issue #768: don't apply ARM options to ARM64" - -This reverts commit 3325543154cd8900490385eb6326f5e7911c6e7d. - -Commit 3325543154cd ("issue #768: don't apply ARM options to ARM64") -breaks compilation of driver on 32-bit ARM platforms. Issue is that each -and every 32-bit ARM kernel was always compiled with soft-fp ABI, not -just that for RPi. Commit author probably thinks on userspace which is -entirely different thing. Furthermore, same issue is very likely present -also on 32-bit x86 platforms. There too is soft float flag already part -of compile flags and can't be overriden with custom ones. - -One last thing - these flags are useful only when -CONFIG_MP_VHT_HW_TX_MODE is set to y. This is probably never used. ---- - Makefile | 26 ++++++++++---------------- - 1 file changed, 10 insertions(+), 16 deletions(-) - -diff --git a/Makefile b/Makefile -index 7ba03bb7e9f8..a23673bc3b42 100755 ---- a/Makefile -+++ b/Makefile -@@ -1118,6 +1118,16 @@ endif - - ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y) - EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE -+ifeq ($(CONFIG_PLATFORM_I386_PC), y) -+## For I386 X86 ToolChain use Hardware FLOATING -+EXTRA_CFLAGS += -mhard-float -+EXTRA_CFLAGS += -DMARK_KERNEL_PFU -+else -+## For ARM ToolChain use Hardware FLOATING -+# Raspbian kernel is with soft-float. -+# 'softfp' allows FP instructions, but no FP on function call interfaces -+EXTRA_CFLAGS += -mfloat-abi=softfp -+endif - endif - - ifeq ($(CONFIG_APPEND_VENDOR_IE_ENABLE), y) -@@ -2124,22 +2134,6 @@ endif - - endif - --ifeq ($(ARCH), i386) --EXTRA_CFLAGS += -mhard-float --EXTRA_CFLAGS += -DMARK_KERNEL_PFU --else ifeq ($(ARCH), x86_64) --EXTRA_CFLAGS += -mhard-float --EXTRA_CFLAGS += -DMARK_KERNEL_PFU --else ifeq ($(ARCH), arm) --# Raspbian kernel is with soft-float. --# 'softfp' allows FP instructions, but no FP on function call interfaces --ifeq ($(CONFIG_PLATFORM_ARM_RPI), y) --EXTRA_CFLAGS += -mfloat-abi=softfp --else --EXTRA_CFLAGS += -mfloat-abi=hard --endif --endif -- - ########### CUSTOMER ################################ - ifeq ($(CONFIG_CUSTOMER_HUAWEI_GENERAL), y) - CONFIG_CUSTOMER_HUAWEI = y --- -2.30.0 - diff --git a/packages/linux-firmware/iwlwifi-firmware/package.mk b/packages/linux-firmware/iwlwifi-firmware/package.mk index 2658444fae..8a26cb2bfd 100644 --- a/packages/linux-firmware/iwlwifi-firmware/package.mk +++ b/packages/linux-firmware/iwlwifi-firmware/package.mk @@ -3,8 +3,8 @@ # Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv) PKG_NAME="iwlwifi-firmware" -PKG_VERSION="be9ab3481819d49126a973a5e8ae732b754e9ef4" -PKG_SHA256="5437f92a26afd2c996800f0e8e7acf2cf288839fc57a8afe73c0717ff1f4841c" +PKG_VERSION="97df2badf8a4308f5b55ae0cf4d6b3ebe2fa564d" +PKG_SHA256="a14dad55a00aff022d4792d03dc904b929c4d32d07860f4db69d400c70ab5d46" PKG_LICENSE="Free-to-use" PKG_SITE="https://github.com/LibreELEC/iwlwifi-firmware" PKG_URL="https://github.com/LibreELEC/iwlwifi-firmware/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/linux/package.mk b/packages/linux/package.mk index e73a2a13e5..3ba8cf420f 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -28,8 +28,8 @@ case "${LINUX}" in PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" ;; *) - PKG_VERSION="5.14.9" - PKG_SHA256="ba8f07db92d514a2636e882bcd646f79f1c8ab83f5ad82910732dd0ec83c87e6" + PKG_VERSION="5.15" + PKG_SHA256="57b2cf6991910e3b67a1b3490022e8a0674b6965c74c12da1e99d138d1991ee8" PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" PKG_PATCH_DIRS="default" ;; diff --git a/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-0005-fix-5.9.patch b/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-0005-fix-5.9.patch index 0702651c26..d3cc5b9c2f 100644 --- a/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-0005-fix-5.9.patch +++ b/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-0005-fix-5.9.patch @@ -29,11 +29,13 @@ diff -Naur NVIDIA-Linux-x86_64-340.108-old/kernel/nv-drm.c NVIDIA-Linux-x86_64-3 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .gem_prime_export = drm_gem_prime_export, -@@ -470,8 +474,12 @@ +@@ -470,8 +474,14 @@ #if defined(NV_DRM_GEM_OBJECT_PUT_UNLOCKED_PRESENT) drm_gem_object_put_unlocked(&nv_obj->base); #else -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) ++ drm_gem_object_put(&nv_obj->base); ++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) + drm_gem_object_put_locked(&nv_obj->base); +#else drm_gem_object_unreference_unlocked(&nv_obj->base); diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index 06907c1779..19224a0507 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.14.5 Kernel Configuration +# Linux/arm64 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -25,6 +25,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -142,6 +143,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -219,7 +221,6 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y @@ -283,7 +284,6 @@ CONFIG_NO_IOPORT_MAP=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y @@ -447,8 +447,10 @@ CONFIG_AS_HAS_LSE_ATOMICS=y # ARMv8.3 architectural features # # CONFIG_ARM64_PTR_AUTH is not set +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # end of ARMv8.3 architectural features # @@ -462,9 +464,12 @@ CONFIG_AS_HAS_ARMV8_4=y # # ARMv8.5 architectural features # +CONFIG_AS_HAS_ARMV8_5=y # CONFIG_ARM64_BTI is not set +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y # CONFIG_ARM64_E0PD is not set # CONFIG_ARCH_RANDOM is not set +CONFIG_ARM64_AS_HAS_MTE=y # end of ARMv8.5 architectural features # @@ -570,28 +575,6 @@ CONFIG_ARM_SCPI_CPUFREQ=y # end of CPU Frequency scaling # end of CPU Power Management -# -# Firmware Drivers -# -# CONFIG_ARM_SCMI_PROTOCOL is not set -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -# CONFIG_ARM_SDE_INTERFACE is not set -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_ARM_FFA_TRANSPORT is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - # CONFIG_VIRTUALIZATION is not set CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA256_ARM64=y @@ -627,6 +610,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -699,6 +683,7 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # @@ -730,16 +715,14 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set CONFIG_BLK_CGROUP_IOLATENCY=y # CONFIG_BLK_CGROUP_IOCOST is not set @@ -758,6 +741,7 @@ CONFIG_EFI_PARTITION=y CONFIG_BLOCK_COMPAT=y CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y # # IO Schedulers @@ -843,12 +827,17 @@ CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -863,6 +852,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -925,6 +915,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set @@ -1346,6 +1337,7 @@ CONFIG_BT_MTKUART=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -1455,6 +1447,35 @@ CONFIG_VEXPRESS_CONFIG=y # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_ARM_FFA_TRANSPORT is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1474,6 +1495,10 @@ CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -1642,6 +1667,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1653,6 +1679,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_LOGGING is not set @@ -1681,6 +1708,7 @@ CONFIG_SCSI_UFSHCD_PLATFORM=m # CONFIG_SCSI_UFS_CDNS_PLATFORM is not set # CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set # CONFIG_SCSI_UFS_BSG is not set +# CONFIG_SCSI_UFS_HPB is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # end of SCSI device support @@ -1818,6 +1846,7 @@ CONFIG_NET_VENDOR_HUAWEI=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_MVMDIO=y CONFIG_NET_VENDOR_MELLANOX=y @@ -1900,6 +1929,7 @@ CONFIG_AX88796B_PHY=m CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=m @@ -2125,7 +2155,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2429,6 +2458,7 @@ CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_BA431 is not set # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m CONFIG_DEVMEM=y CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y @@ -2443,10 +2473,8 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - -# CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2509,6 +2537,7 @@ CONFIG_I2C_RK3X=y # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2584,6 +2613,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2748,7 +2778,6 @@ CONFIG_BATTERY_BQ27XXX=y CONFIG_BATTERY_BQ27XXX_I2C=y # CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set CONFIG_AXP20X_POWER=y -# CONFIG_AXP288_FUEL_GAUGE is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_ISP1704 is not set @@ -2797,6 +2826,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2883,6 +2913,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -3102,6 +3133,8 @@ CONFIG_MFD_WL1273_CORE=m CONFIG_MFD_VEXPRESS_SYSREG=y # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -3155,7 +3188,9 @@ CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_S5M8767 is not set @@ -3562,7 +3597,9 @@ CONFIG_VIDEO_I2C=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set @@ -3583,6 +3620,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3908,12 +3946,16 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set @@ -3924,6 +3966,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -4233,6 +4276,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98357A is not set @@ -4991,6 +5035,7 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options @@ -5183,6 +5228,8 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y @@ -5436,6 +5483,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set @@ -5678,6 +5726,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -5907,16 +5956,16 @@ CONFIG_F2FS_FS_POSIX_ACL=y # CONFIG_F2FS_FAULT_INJECTION is not set CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y -CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_IOSTAT=y # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y @@ -5970,6 +6019,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -6081,7 +6134,6 @@ CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set CONFIG_CIFS_DEBUG=y @@ -6090,6 +6142,8 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_CIFS_SWN_UPCALL is not set # CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -6356,7 +6410,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_BLAKE2S=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y @@ -6484,6 +6538,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_REMAP=y @@ -6558,7 +6613,6 @@ CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set # CONFIG_DEBUG_INFO_BTF is not set -CONFIG_PAHOLE_HAS_SPLIT_BTF=y # CONFIG_GDB_SCRIPTS is not set CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set @@ -6621,7 +6675,6 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y -CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y @@ -6704,7 +6757,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y @@ -6740,7 +6792,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index b60a3aa87a..e11d68d3b0 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.14.5 Kernel Configuration +# Linux/arm 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -24,6 +24,7 @@ CONFIG_BUILDTIME_TABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -137,6 +138,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -207,12 +209,12 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -263,7 +265,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -587,26 +588,6 @@ CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options -# -# Firmware Drivers -# -# CONFIG_ARM_SCMI_PROTOCOL is not set -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_TRUSTED_FOUNDATIONS is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=y CONFIG_CRYPTO_SHA256_ARM=y @@ -620,7 +601,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # -CONFIG_SET_FS=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y @@ -629,6 +609,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -708,15 +689,13 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set CONFIG_BLK_CGROUP_IOLATENCY=y # CONFIG_BLK_CGROUP_IOCOST is not set @@ -752,6 +731,7 @@ CONFIG_EFI_PARTITION=y # end of Partition Types CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y # # IO Schedulers @@ -821,6 +801,12 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -834,6 +820,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -895,6 +882,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y @@ -1282,6 +1270,7 @@ CONFIG_BT_MTKUART=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -1380,7 +1369,6 @@ CONFIG_ARM_CCI400_COMMON=y CONFIG_ARM_CCI400_PORT_CTRL=y # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set -# CONFIG_SIMPLE_PM_BUS is not set CONFIG_SUN50I_DE2_BUS=y CONFIG_SUNXI_RSB=y # CONFIG_VEXPRESS_CONFIG is not set @@ -1388,6 +1376,33 @@ CONFIG_SUNXI_RSB=y # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_TRUSTED_FOUNDATIONS is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set # CONFIG_MTD is not set CONFIG_DTC=y @@ -1480,6 +1495,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y CONFIG_SCSI_PROC_FS=y @@ -1491,6 +1507,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_LOGGING is not set @@ -1568,7 +1585,6 @@ CONFIG_DM_PERSISTENT_DATA=m CONFIG_DM_THIN_PROVISIONING=m # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set -# CONFIG_DM_EBS is not set # CONFIG_DM_ERA is not set # CONFIG_DM_CLONE is not set # CONFIG_DM_MIRROR is not set @@ -1640,6 +1656,7 @@ CONFIG_NET_VENDOR_HISILICON=y # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1707,6 +1724,7 @@ CONFIG_AX88796B_PHY=m # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y @@ -1953,7 +1971,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2178,13 +2195,13 @@ CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_BA431 is not set # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2243,6 +2260,7 @@ CONFIG_I2C_MV64XXX=y # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2315,6 +2333,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2460,7 +2479,6 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_AXP20X is not set # CONFIG_BATTERY_AXP20X is not set CONFIG_AXP20X_POWER=y -# CONFIG_AXP288_FUEL_GAUGE is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_ISP1704 is not set @@ -2509,6 +2527,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2594,6 +2613,7 @@ CONFIG_HWMON=y # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2822,6 +2842,8 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -2870,7 +2892,9 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_SLG51000 is not set CONFIG_REGULATOR_SY8106A=y # CONFIG_REGULATOR_SY8824X is not set @@ -3278,7 +3302,9 @@ CONFIG_VIDEO_ST_MIPID02=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set @@ -3299,6 +3325,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3637,6 +3664,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set @@ -3930,6 +3958,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98357A is not set @@ -4677,6 +4706,7 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options @@ -5080,6 +5110,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set @@ -5315,6 +5346,7 @@ CONFIG_SUN4I_GPADC=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -5540,15 +5572,15 @@ CONFIG_F2FS_FS_POSIX_ACL=y # CONFIG_F2FS_FAULT_INJECTION is not set CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y -CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_IOSTAT=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y @@ -5594,6 +5626,9 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5684,7 +5719,6 @@ CONFIG_SUNRPC_SWAP=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set CONFIG_CIFS_DEBUG=y @@ -5693,6 +5727,8 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_CIFS_SWN_UPCALL is not set # CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -5941,7 +5977,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y @@ -6251,7 +6287,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y @@ -6293,7 +6328,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set diff --git a/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch b/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch deleted file mode 100644 index 14f14b8070..0000000000 --- a/projects/Allwinner/patches/linux/0014-media-hevc-Add-segment-address-field.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 229e5bdcd39ed3ca0a71dc8500ba4ea90d4415db Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 6 Jun 2021 10:23:13 +0200 -Subject: [PATCH] media: hevc: Add segment address field - -If HEVC frame consists of multiple slices, segment address has to be -known in order to properly decode it. - -Add segment address field to slice parameters. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 3 +++ - include/media/hevc-ctrls.h | 3 ++- - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -3000,6 +3000,9 @@ enum v4l2_mpeg_video_hevc_size_of_length - * - __u8 - - ``pic_struct`` - - -+ * - __u32 -+ - ``slice_segment_addr`` -+ - - * - __u8 - - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` - - The list of L0 reference elements as indices in the DPB. ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -196,10 +196,11 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 pic_struct; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -- __u8 padding[5]; -+ __u8 padding; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; diff --git a/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch b/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch deleted file mode 100644 index 4a2a85f591..0000000000 --- a/projects/Allwinner/patches/linux/0016-media-cedrus-hevc-Add-support-for-multiple-slices.patch +++ /dev/null @@ -1,92 +0,0 @@ -From d92a4a27d983032267b231a32be98a11a9995e5c Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 6 Jun 2021 10:23:14 +0200 -Subject: [PATCH] media: cedrus: hevc: Add support for multiple slices - -Now that segment address is available, support for multi-slice frames -can be easily added. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/sunxi/cedrus/cedrus_h265.c | 26 ++++++++++++------- - .../staging/media/sunxi/cedrus/cedrus_video.c | 1 + - 2 files changed, 17 insertions(+), 10 deletions(-) - ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -247,6 +247,8 @@ static void cedrus_h265_setup(struct ced - const struct v4l2_ctrl_hevc_slice_params *slice_params; - const struct v4l2_ctrl_hevc_decode_params *decode_params; - const struct v4l2_hevc_pred_weight_table *pred_weight_table; -+ unsigned int width_in_ctb_luma, ctb_size_luma; -+ unsigned int log2_max_luma_coding_block_size; - dma_addr_t src_buf_addr; - dma_addr_t src_buf_end_addr; - u32 chroma_log2_weight_denom; -@@ -260,15 +262,17 @@ static void cedrus_h265_setup(struct ced - decode_params = run->h265.decode_params; - pred_weight_table = &slice_params->pred_weight_table; - -+ log2_max_luma_coding_block_size = -+ sps->log2_min_luma_coding_block_size_minus3 + 3 + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_luma = 1UL << log2_max_luma_coding_block_size; -+ width_in_ctb_luma = -+ DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); -+ - /* MV column buffer size and allocation. */ - if (!ctx->codec.h265.mv_col_buf_size) { - unsigned int num_buffers = - run->dst->vb2_buf.vb2_queue->num_buffers; -- unsigned int log2_max_luma_coding_block_size = -- sps->log2_min_luma_coding_block_size_minus3 + 3 + -- sps->log2_diff_max_min_luma_coding_block_size; -- unsigned int ctb_size_luma = -- 1UL << log2_max_luma_coding_block_size; - - /* - * Each CTB requires a MV col buffer with a specific unit size. -@@ -322,15 +326,17 @@ static void cedrus_h265_setup(struct ced - reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); - cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); - -- /* Coding tree block address: start at the beginning. */ -- reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0); -+ /* Coding tree block address */ -+ reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma); -+ reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma); - cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); - - cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); - cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); - - /* Clear the number of correctly-decoded coding tree blocks. */ -- cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); -+ if (ctx->fh.m2m_ctx->new_frame) -+ cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); - - /* Initialize bitstream access. */ - cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); -@@ -482,8 +488,8 @@ static void cedrus_h265_setup(struct ced - V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT, - slice_params->flags); - -- /* FIXME: For multi-slice support. */ -- reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; -+ if (ctx->fh.m2m_ctx->new_frame) -+ reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; - - cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); - ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -340,6 +340,7 @@ static int cedrus_s_fmt_vid_out(struct f - - switch (ctx->src_fmt.pixelformat) { - case V4L2_PIX_FMT_H264_SLICE: -+ case V4L2_PIX_FMT_HEVC_SLICE: - vq->subsystem_flags |= - VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF; - break; diff --git a/projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch b/projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch deleted file mode 100644 index 1d719749c0..0000000000 --- a/projects/Allwinner/patches/linux/0050-arm64-dts-allwinner-h6-tanix-tx6-enable-emmc.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 15 Jan 2020 18:39:17 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: tanix-tx6: enable emmc - -Tanix TX6 has 32 GiB eMMC. Add a node for it. - -Signed-off-by: Jernej Skrabec ---- - .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 20 +++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -32,6 +32,13 @@ - }; - }; - -+ reg_vcc1v8: regulator-vcc1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; -@@ -91,6 +98,15 @@ - status = "okay"; - }; - -+&mmc2 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc1v8>; -+ non-removable; -+ cap-mmc-hw-reset; -+ bus-width = <8>; -+ status = "okay"; -+}; -+ - &ohci0 { - status = "okay"; - }; -@@ -99,6 +115,10 @@ - status = "okay"; - }; - -+&pio { -+ vcc-pc-supply = <®_vcc1v8>; -+}; -+ - &r_ir { - linux,rc-map-name = "rc-tanix-tx5max"; - status = "okay"; diff --git a/projects/Allwinner/patches/linux/0056-drm-sun4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch b/projects/Allwinner/patches/linux/0056-drm-sun4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch deleted file mode 100644 index 2fbf20dab2..0000000000 --- a/projects/Allwinner/patches/linux/0056-drm-sun4i-dw-hdmi-Fix-HDMI-PHY-clock-setup.patch +++ /dev/null @@ -1,210 +0,0 @@ -From 887d1018e2c5ab5e81edbd1318bbf4bbd2c739b0 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 12 Sep 2021 20:15:26 +0200 -Subject: [PATCH] drm/sun4i: dw-hdmi: Fix HDMI PHY clock setup - -Recent rework which made HDMI PHY driver a platform device inadvertely -reversed clock setup order. HW is very touch about it. Proper way is to -handle controllers resets and clocks first and HDMI PHYs second. - -Move HDMI PHY reset & clocks handling to sun8i_hdmi_phy_init() which -will assure that code is executed after controllers reset & clocks are -handled. Additionally, add sun8i_hdmi_phy_deinit() which will deinit it -at controllers driver unload. - -Fixes: 9bf3797796f5 ("drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 7 +- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 4 +- - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 97 ++++++++++++++------------ - 3 files changed, 61 insertions(+), 47 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -index f75fb157f2ff..5fa5407ac583 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -216,11 +216,13 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, - goto err_disable_clk_tmds; - } - -+ ret = sun8i_hdmi_phy_init(hdmi->phy); -+ if (ret) -+ return ret; -+ - drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - -- sun8i_hdmi_phy_init(hdmi->phy); -- - plat_data->mode_valid = hdmi->quirks->mode_valid; - plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe; - sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data); -@@ -262,6 +264,7 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, - struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev); - - dw_hdmi_unbind(hdmi->hdmi); -+ sun8i_hdmi_phy_deinit(hdmi->phy); - clk_disable_unprepare(hdmi->clk_tmds); - reset_control_assert(hdmi->rst_ctrl); - gpiod_set_value(hdmi->ddc_en, 0); -diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -index 74f6ed0e2570..bffe1b9cd3dc 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -169,6 +169,7 @@ struct sun8i_hdmi_phy { - struct clk *clk_phy; - struct clk *clk_pll0; - struct clk *clk_pll1; -+ struct device *dev; - unsigned int rcal; - struct regmap *regs; - struct reset_control *rst_phy; -@@ -205,7 +206,8 @@ encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder) - - int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node); - --void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy); -+int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy); -+void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy); - void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, - struct dw_hdmi_plat_data *plat_data); - -diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -index c9239708d398..78b152973957 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -506,9 +506,60 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) - phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2; - } - --void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) -+int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) - { -+ int ret; -+ -+ ret = reset_control_deassert(phy->rst_phy); -+ if (ret) { -+ dev_err(phy->dev, "Cannot deassert phy reset control: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(phy->clk_bus); -+ if (ret) { -+ dev_err(phy->dev, "Cannot enable bus clock: %d\n", ret); -+ goto err_deassert_rst_phy; -+ } -+ -+ ret = clk_prepare_enable(phy->clk_mod); -+ if (ret) { -+ dev_err(phy->dev, "Cannot enable mod clock: %d\n", ret); -+ goto err_disable_clk_bus; -+ } -+ -+ if (phy->variant->has_phy_clk) { -+ ret = sun8i_phy_clk_create(phy, phy->dev, -+ phy->variant->has_second_pll); -+ if (ret) { -+ dev_err(phy->dev, "Couldn't create the PHY clock\n"); -+ goto err_disable_clk_mod; -+ } -+ -+ clk_prepare_enable(phy->clk_phy); -+ } -+ - phy->variant->phy_init(phy); -+ -+ return 0; -+ -+err_disable_clk_mod: -+ clk_disable_unprepare(phy->clk_mod); -+err_disable_clk_bus: -+ clk_disable_unprepare(phy->clk_bus); -+err_deassert_rst_phy: -+ reset_control_assert(phy->rst_phy); -+ -+ return ret; -+} -+ -+void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy) -+{ -+ clk_disable_unprepare(phy->clk_mod); -+ clk_disable_unprepare(phy->clk_bus); -+ clk_disable_unprepare(phy->clk_phy); -+ -+ reset_control_assert(phy->rst_phy); - } - - void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, -@@ -638,6 +689,7 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev) - return -ENOMEM; - - phy->variant = (struct sun8i_hdmi_phy_variant *)match->data; -+ phy->dev = dev; - - ret = of_address_to_resource(node, 0, &res); - if (ret) { -@@ -696,47 +748,10 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev) - goto err_put_clk_pll1; - } - -- ret = reset_control_deassert(phy->rst_phy); -- if (ret) { -- dev_err(dev, "Cannot deassert phy reset control: %d\n", ret); -- goto err_put_rst_phy; -- } -- -- ret = clk_prepare_enable(phy->clk_bus); -- if (ret) { -- dev_err(dev, "Cannot enable bus clock: %d\n", ret); -- goto err_deassert_rst_phy; -- } -- -- ret = clk_prepare_enable(phy->clk_mod); -- if (ret) { -- dev_err(dev, "Cannot enable mod clock: %d\n", ret); -- goto err_disable_clk_bus; -- } -- -- if (phy->variant->has_phy_clk) { -- ret = sun8i_phy_clk_create(phy, dev, -- phy->variant->has_second_pll); -- if (ret) { -- dev_err(dev, "Couldn't create the PHY clock\n"); -- goto err_disable_clk_mod; -- } -- -- clk_prepare_enable(phy->clk_phy); -- } -- - platform_set_drvdata(pdev, phy); - - return 0; - --err_disable_clk_mod: -- clk_disable_unprepare(phy->clk_mod); --err_disable_clk_bus: -- clk_disable_unprepare(phy->clk_bus); --err_deassert_rst_phy: -- reset_control_assert(phy->rst_phy); --err_put_rst_phy: -- reset_control_put(phy->rst_phy); - err_put_clk_pll1: - clk_put(phy->clk_pll1); - err_put_clk_pll0: -@@ -753,12 +768,6 @@ static int sun8i_hdmi_phy_remove(struct platform_device *pdev) - { - struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev); - -- clk_disable_unprepare(phy->clk_mod); -- clk_disable_unprepare(phy->clk_bus); -- clk_disable_unprepare(phy->clk_phy); -- -- reset_control_assert(phy->rst_phy); -- - reset_control_put(phy->rst_phy); - - clk_put(phy->clk_pll0); --- -2.33.0 - diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index 3aeccb8ece..2c1f5d7cdc 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.14.5 Kernel Configuration +# Linux/x86 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -25,6 +25,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -152,6 +153,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # @@ -176,7 +178,7 @@ CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set # CONFIG_CGROUP_PIDS is not set # CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y @@ -229,7 +231,6 @@ CONFIG_MULTIUSER=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y # CONFIG_PCSPKR_PLATFORM is not set @@ -304,6 +305,7 @@ CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_NR_GPIO=1024 CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_AUDIT_ARCH=y @@ -387,6 +389,7 @@ CONFIG_PERF_EVENTS_INTEL_UNCORE=y CONFIG_PERF_EVENTS_INTEL_RAPL=y CONFIG_PERF_EVENTS_INTEL_CSTATE=y CONFIG_PERF_EVENTS_AMD_POWER=y +CONFIG_PERF_EVENTS_AMD_UNCORE=y # end of Performance monitoring CONFIG_X86_16BIT=y @@ -602,7 +605,6 @@ CONFIG_MMCONF_FAM10H=y # CONFIG_ISA_BUS is not set CONFIG_ISA_DMA_API=y CONFIG_AMD_NB=y -# CONFIG_X86_SYSFB is not set # end of Bus options (PCI etc.) # @@ -616,45 +618,6 @@ CONFIG_COMPAT_FOR_U64_ALIGNMENT=y CONFIG_SYSVIPC_COMPAT=y # end of Binary Emulations -# -# Firmware Drivers -# -# CONFIG_EDD is not set -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_DMIID=y -CONFIG_DMI_SYSFS=m -CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y -CONFIG_ISCSI_IBFT_FIND=y -CONFIG_ISCSI_IBFT=y -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_VARS=y -CONFIG_EFI_ESRT=y -# CONFIG_EFI_FAKE_MEMMAP is not set -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -CONFIG_APPLE_PROPERTIES=y -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_EFI_RCI2_TABLE is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_EFI_DEV_PATH_PARSER=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - CONFIG_HAVE_KVM=y # CONFIG_VIRTUALIZATION is not set CONFIG_AS_AVX512=y @@ -684,6 +647,7 @@ CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_KPROBES_ON_FTRACE=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -771,6 +735,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_HAS_ELFCORE_COMPAT=y +CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y # # GCOV-based kernel profiling @@ -801,13 +766,11 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_DEV_THROTTLING is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -946,6 +909,12 @@ CONFIG_ARCH_HAS_PKEYS=y CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_SECRETMEM=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -959,6 +928,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -1038,6 +1008,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y @@ -1409,6 +1380,7 @@ CONFIG_BT_MTKUART=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y @@ -1581,6 +1553,54 @@ CONFIG_DMA_SHARED_BUFFER=y CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +# CONFIG_EDD is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMIID=y +CONFIG_DMI_SYSFS=m +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +CONFIG_ISCSI_IBFT_FIND=y +CONFIG_ISCSI_IBFT=y +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=y +CONFIG_EFI_ESRT=y +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +CONFIG_APPLE_PROPERTIES=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_RCI2_TABLE is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_DEV_PATH_PARSER=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set # CONFIG_MTD is not set # CONFIG_OF is not set @@ -1693,6 +1713,7 @@ CONFIG_MISC_RTSX_USB=y # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1704,6 +1725,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -2006,6 +2028,7 @@ CONFIG_ICE=y CONFIG_IGC=y CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_JME=y +# CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set CONFIG_SKGE=y @@ -2100,6 +2123,7 @@ CONFIG_BCM_NET_PHYLIB=y CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_PHY is not set @@ -2308,7 +2332,6 @@ CONFIG_P54_COMMON=m CONFIG_P54_USB=m CONFIG_P54_PCI=m CONFIG_P54_LEDS=y -# CONFIG_PRISM54 is not set CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_LIBERTAS=m # CONFIG_LIBERTAS_USB is not set @@ -2440,7 +2463,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2776,10 +2798,9 @@ CONFIG_DEVPORT=y # CONFIG_TELCLOCK is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2866,6 +2887,7 @@ CONFIG_I2C_DESIGNWARE_BAYTRAIL=y # Other I2C/SMBus bus drivers # # CONFIG_I2C_MLXCPLD is not set +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2897,6 +2919,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2905,7 +2928,6 @@ CONFIG_PTP_1588_CLOCK_KVM=y # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set # CONFIG_PTP_1588_CLOCK_VMW is not set -# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -3009,6 +3031,7 @@ CONFIG_GPIO_CDEV_V1=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_VIRTIO is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -3072,6 +3095,7 @@ CONFIG_HWMON_VID=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -3156,6 +3180,7 @@ CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -3238,6 +3263,7 @@ CONFIG_INTEL_SOC_DTS_THERMAL=m # CONFIG_INTEL_PCH_THERMAL is not set # CONFIG_INTEL_TCC_COOLING is not set +# CONFIG_INTEL_MENLOW is not set # end of Intel thermal drivers # CONFIG_WATCHDOG is not set @@ -3388,7 +3414,9 @@ CONFIG_REGULATOR=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set @@ -4242,12 +4270,12 @@ CONFIG_DRM_I915_TIMESLICE_DURATION=1 # CONFIG_DRM_VKMS is not set CONFIG_DRM_VMWGFX=y CONFIG_DRM_VMWGFX_FBCON=y +# CONFIG_DRM_VMWGFX_MKSSTATS is not set # CONFIG_DRM_GMA500 is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set # CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set CONFIG_DRM_VIRTIO_GPU=y CONFIG_DRM_PANEL=y @@ -4267,6 +4295,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set @@ -4497,6 +4526,7 @@ CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_CIRRUS=m +# CONFIG_SND_HDA_CODEC_CS8409 is not set CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CA0110=m CONFIG_SND_HDA_CODEC_CA0132=m @@ -4554,6 +4584,7 @@ CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m CONFIG_SND_SOC_AMD_ACP3x=m CONFIG_SND_SOC_AMD_RENOIR=m CONFIG_SND_SOC_AMD_RENOIR_MACH=m +# CONFIG_SND_SOC_AMD_ACP5x is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4684,6 +4715,7 @@ CONFIG_SND_SOC_ES8316=m # CONFIG_SND_SOC_GTM601 is not set CONFIG_SND_SOC_HDAC_HDMI=m CONFIG_SND_SOC_HDAC_HDA=m +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set CONFIG_SND_SOC_MAX98090=m @@ -5188,11 +5220,9 @@ CONFIG_LEDS_CLASS_FLASH=y # LED drivers # # CONFIG_LEDS_APU is not set -# CONFIG_LEDS_AS3645A is not set # CONFIG_LEDS_LM3530 is not set # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set -# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_GPIO is not set # CONFIG_LEDS_LP3944 is not set @@ -5218,12 +5248,14 @@ CONFIG_LEDS_CLASS_FLASH=y # CONFIG_LEDS_USER is not set # CONFIG_LEDS_NIC78BX is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_SGM3140 is not set # # Flash and Torch LED drivers # +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set # # LED Triggers @@ -5358,8 +5390,10 @@ CONFIG_DMA_ACPI=y # CONFIG_ALTERA_MSGDMA is not set CONFIG_INTEL_IDMA64=m # CONFIG_INTEL_IDXD is not set +# CONFIG_INTEL_IDXD_COMPAT is not set CONFIG_INTEL_IOATDMA=m # CONFIG_PLX_DMA is not set +# CONFIG_AMD_PTDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=m @@ -5388,6 +5422,7 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options @@ -5465,8 +5500,6 @@ CONFIG_X86_PLATFORM_DEVICES=y CONFIG_ACPI_WMI=y CONFIG_WMI_BMOF=y # CONFIG_HUAWEI_WMI is not set -# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set -# CONFIG_INTEL_WMI_THUNDERBOLT is not set # CONFIG_MXM_WMI is not set # CONFIG_PEAQ_WMI is not set # CONFIG_XIAOMI_WMI is not set @@ -5493,13 +5526,29 @@ CONFIG_WMI_BMOF=y # CONFIG_THINKPAD_ACPI is not set # CONFIG_THINKPAD_LMI is not set CONFIG_X86_PLATFORM_DRIVERS_INTEL=y -# CONFIG_INTEL_SKL_INT3472 is not set +CONFIG_INTEL_ATOMISP2_PDX86=y CONFIG_INTEL_ATOMISP2_PM=y +# CONFIG_INTEL_SAR_INT1092 is not set +# CONFIG_INTEL_SKL_INT3472 is not set +# CONFIG_INTEL_PMC_CORE is not set + +# +# Intel Speed Select Technology interface support +# +# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set +# end of Intel Speed Select Technology interface support + +# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set +# CONFIG_INTEL_WMI_THUNDERBOLT is not set # CONFIG_INTEL_HID_EVENT is not set -# CONFIG_INTEL_INT0002_VGPIO is not set -# CONFIG_INTEL_MENLOW is not set -# CONFIG_INTEL_OAKTRAIL is not set # CONFIG_INTEL_VBTN is not set +# CONFIG_INTEL_INT0002_VGPIO is not set +# CONFIG_INTEL_OAKTRAIL is not set +# CONFIG_INTEL_PUNIT_IPC is not set +# CONFIG_INTEL_RST is not set +# CONFIG_INTEL_SMARTCONNECT is not set +# CONFIG_INTEL_TURBO_MAX_3 is not set +# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set # CONFIG_MSI_LAPTOP is not set # CONFIG_MSI_WMI is not set # CONFIG_PCENGINES_APU2 is not set @@ -5518,19 +5567,6 @@ CONFIG_INTEL_ATOMISP2_PM=y # CONFIG_I2C_MULTI_INSTANTIATE is not set # CONFIG_MLX_PLATFORM is not set # CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_RST is not set -# CONFIG_INTEL_SMARTCONNECT is not set - -# -# Intel Speed Select Technology interface support -# -# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set -# end of Intel Speed Select Technology interface support - -# CONFIG_INTEL_TURBO_MAX_3 is not set -# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set -# CONFIG_INTEL_PMC_CORE is not set -# CONFIG_INTEL_PUNIT_IPC is not set # CONFIG_INTEL_SCU_PCI is not set # CONFIG_INTEL_SCU_PLATFORM is not set CONFIG_PMC_ATOM=y @@ -5584,6 +5620,8 @@ CONFIG_IOMMU_IO_PGTABLE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y CONFIG_IOMMU_DMA=y CONFIG_IOMMU_SVA_LIB=y @@ -5764,7 +5802,7 @@ CONFIG_XFS_SUPPORT_V4=y # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=y -# CONFIG_BTRFS_FS_POSIX_ACL is not set +CONFIG_BTRFS_FS_POSIX_ACL=y # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set @@ -5777,6 +5815,7 @@ CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -5809,9 +5848,7 @@ CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -5836,6 +5873,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5933,7 +5974,6 @@ CONFIG_RPCSEC_GSS_KRB5=m CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set CONFIG_CIFS_DEBUG=y @@ -5943,6 +5983,8 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -6160,7 +6202,7 @@ CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set CONFIG_CRYPTO_AES_NI_INTEL=y # CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set # CONFIG_CRYPTO_CAMELLIA is not set @@ -6183,6 +6225,8 @@ CONFIG_CRYPTO_CHACHA20_X86_64=m # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set # CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set +# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_TWOFISH_X86_64 is not set @@ -6221,7 +6265,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m CONFIG_CRYPTO_LIB_BLAKE2S=m @@ -6550,7 +6594,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_USER_STACKTRACE_SUPPORT=y @@ -6629,7 +6672,6 @@ CONFIG_STRICT_DEVMEM=y # # x86 Debugging # -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y # CONFIG_X86_VERBOSE_BOOTUP is not set # CONFIG_EARLY_PRINTK is not set @@ -6666,7 +6708,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set diff --git a/projects/NXP/devices/iMX6/linux/linux.arm.conf b/projects/NXP/devices/iMX6/linux/linux.arm.conf index 84a8365422..b31f927ede 100644 --- a/projects/NXP/devices/iMX6/linux/linux.arm.conf +++ b/projects/NXP/devices/iMX6/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.14.5 Kernel Configuration +# Linux/arm 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -24,6 +24,7 @@ CONFIG_BUILDTIME_TABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -138,6 +139,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -193,12 +195,12 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -250,7 +252,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -603,26 +604,6 @@ CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options -# -# Firmware Drivers -# -# CONFIG_ARM_SCMI_PROTOCOL is not set -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_TRUSTED_FOUNDATIONS is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=y CONFIG_CRYPTO_SHA256_ARM=y @@ -638,7 +619,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y -CONFIG_SET_FS=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y @@ -647,6 +627,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -731,12 +712,9 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSGLIB is not set # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set @@ -816,6 +794,12 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -829,6 +813,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -886,6 +871,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y @@ -962,6 +948,8 @@ CONFIG_NET_DSA_TAG_EDSA=y # CONFIG_NET_DSA_TAG_MTK is not set # CONFIG_NET_DSA_TAG_KSZ is not set # CONFIG_NET_DSA_TAG_RTL4_A is not set +# CONFIG_NET_DSA_TAG_OCELOT is not set +# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set # CONFIG_NET_DSA_TAG_QCA is not set # CONFIG_NET_DSA_TAG_LAN9303 is not set # CONFIG_NET_DSA_TAG_SJA1105 is not set @@ -1070,6 +1058,7 @@ CONFIG_BT_MTKUART=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -1154,7 +1143,6 @@ CONFIG_PCIE_BUS_DEFAULT=y # PCI controller drivers # # CONFIG_PCI_FTPCI100 is not set -# CONFIG_PCI_IXP4XX is not set # CONFIG_PCI_HOST_GENERIC is not set # CONFIG_PCIE_XILINX is not set # CONFIG_PCI_V3_SEMI is not set @@ -1245,7 +1233,6 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set CONFIG_IMX_WEIM=y -# CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_FSL_MC_BUS is not set # CONFIG_MHI_BUS is not set @@ -1253,6 +1240,33 @@ CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_TRUSTED_FOUNDATIONS is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1272,6 +1286,10 @@ CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -1472,6 +1490,7 @@ CONFIG_EEPROM_AT25=y # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1483,6 +1502,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set +# CONFIG_BLK_DEV_BSG is not set # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -1755,6 +1775,7 @@ CONFIG_IGB_HWMON=y # CONFIG_IGC is not set # CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_JME is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLX4_EN is not set @@ -1875,6 +1896,7 @@ CONFIG_AX88796B_PHY=y CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y @@ -2023,7 +2045,6 @@ CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2342,15 +2363,15 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_IMX_RNGC=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2439,6 +2460,7 @@ CONFIG_I2C_IMX=y # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2514,6 +2536,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2521,7 +2544,6 @@ CONFIG_PTP_1588_CLOCK=y # CONFIG_PTP_1588_CLOCK_KVM is not set # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set -# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2547,6 +2569,7 @@ CONFIG_PINCTRL_IMX6UL=y # CONFIG_PINCTRL_IMX8MN is not set # CONFIG_PINCTRL_IMX8MP is not set # CONFIG_PINCTRL_IMX8MQ is not set +# CONFIG_PINCTRL_IMX8ULP is not set # # Renesas pinctrl drivers @@ -2722,6 +2745,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2810,6 +2834,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -3053,6 +3078,8 @@ CONFIG_MFD_WM8994=y # CONFIG_MFD_QCOM_PM8008 is not set CONFIG_RAVE_SP_CORE=y # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -3106,7 +3133,9 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set @@ -3330,6 +3359,7 @@ CONFIG_VIDEOBUF2_V4L2=y CONFIG_VIDEOBUF2_MEMOPS=y CONFIG_VIDEOBUF2_DMA_CONTIG=y CONFIG_VIDEOBUF2_VMALLOC=y +CONFIG_VIDEOBUF2_DMA_SG=m CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_VIDEO_CAFE_CCIC is not set # CONFIG_VIDEO_CADENCE is not set @@ -3477,7 +3507,9 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set @@ -3498,6 +3530,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3775,6 +3808,7 @@ CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y +CONFIG_DRM_DP_AUX_BUS=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set @@ -3821,7 +3855,6 @@ CONFIG_DRM_SCHED=y # CONFIG_DRM_OMAP is not set # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set # CONFIG_DRM_VIRTIO_GPU is not set # CONFIG_DRM_FSL_DCU is not set # CONFIG_DRM_STM is not set @@ -3835,12 +3868,16 @@ CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set @@ -3851,6 +3888,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -3908,6 +3946,7 @@ CONFIG_DRM_ETNAVIV=y CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_MXSFB is not set # CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set @@ -4257,6 +4296,7 @@ CONFIG_SND_SOC_ES8328=y CONFIG_SND_SOC_ES8328_I2C=y CONFIG_SND_SOC_ES8328_SPI=y # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98357A is not set @@ -5082,6 +5122,7 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options @@ -5484,6 +5525,7 @@ CONFIG_VF610_ADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set @@ -5726,6 +5768,7 @@ CONFIG_VF610_ADC=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -5994,6 +6037,9 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -6090,6 +6136,7 @@ CONFIG_SUNRPC_GSS=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set +# CONFIG_SMB_SERVER is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -6293,7 +6340,7 @@ CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set @@ -6341,7 +6388,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S=m CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m @@ -6672,7 +6719,6 @@ CONFIG_RCU_TRACE=y # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_NOP_TRACER=y @@ -6721,7 +6767,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set diff --git a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf index a217e4c3aa..1ffb037635 100644 --- a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf +++ b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.14.5 Kernel Configuration +# Linux/arm64 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -25,6 +25,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -129,6 +130,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -199,7 +201,6 @@ CONFIG_MULTIUSER=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y @@ -263,7 +264,6 @@ CONFIG_NO_IOPORT_MAP=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y @@ -548,31 +548,6 @@ CONFIG_ARM_IMX_CPUFREQ_DT=y # end of CPU Frequency scaling # end of CPU Power Management -# -# Firmware Drivers -# -# CONFIG_ARM_SCMI_PROTOCOL is not set -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -# CONFIG_ARM_SDE_INTERFACE is not set -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_ARM_FFA_TRANSPORT is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_IMX_DSP=m -CONFIG_IMX_SCU=y -CONFIG_IMX_SCU_PD=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - # CONFIG_VIRTUALIZATION is not set CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA256_ARM64=y @@ -605,6 +580,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -712,13 +688,11 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_DEV_THROTTLING is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -895,6 +869,12 @@ CONFIG_ZONE_DMA32=y # CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -909,6 +889,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -992,6 +973,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -1357,6 +1339,7 @@ CONFIG_BT_ATH3K=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -1454,12 +1437,43 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set # CONFIG_IMX_WEIM is not set -# CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_ARM_FFA_TRANSPORT is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_IMX_DSP=m +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1479,6 +1493,10 @@ CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -1648,6 +1666,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1659,6 +1678,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -1737,6 +1757,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1799,6 +1820,7 @@ CONFIG_AX88796B_PHY=m # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m @@ -2041,7 +2063,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2291,13 +2312,13 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2362,6 +2383,7 @@ CONFIG_I2C_IMX_LPI2C=y # Other I2C/SMBus bus drivers # # CONFIG_I2C_CROS_EC_TUNNEL is not set +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2438,6 +2460,7 @@ CONFIG_PPS=y # PTP clock support # # CONFIG_PTP_1588_CLOCK is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2467,6 +2490,7 @@ CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y # CONFIG_PINCTRL_IMX8DXL is not set +# CONFIG_PINCTRL_IMX8ULP is not set # # Renesas pinctrl drivers @@ -2601,6 +2625,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set +# CONFIG_CHARGER_CROS_PCHG is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y @@ -2626,6 +2651,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2711,6 +2737,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2940,6 +2967,8 @@ CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -2994,7 +3023,9 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set # CONFIG_REGULATOR_S5M8767 is not set @@ -3383,7 +3414,9 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set @@ -3404,6 +3437,7 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3681,6 +3715,7 @@ CONFIG_DVB_SP2=m # Graphics support # CONFIG_DRM=y +CONFIG_DRM_DP_AUX_BUS=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set @@ -3727,12 +3762,16 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set @@ -3743,6 +3782,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -4039,6 +4079,7 @@ CONFIG_SND_SOC_ES8328=y CONFIG_SND_SOC_ES8328_I2C=y CONFIG_SND_SOC_ES8328_SPI=y # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98357A is not set @@ -4829,6 +4870,7 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options @@ -5026,6 +5068,8 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y @@ -5269,6 +5313,7 @@ CONFIG_IIO=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set @@ -5506,6 +5551,7 @@ CONFIG_IIO=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -5749,12 +5795,12 @@ CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y @@ -5781,9 +5827,7 @@ CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -5807,6 +5851,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="ascii" # CONFIG_FAT_DEFAULT_UTF8 is not set # CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5901,6 +5949,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set +# CONFIG_SMB_SERVER is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -6267,6 +6316,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_REMAP=y @@ -6478,7 +6528,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index a70941a612..818a2bfe39 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.14.6 Kernel Configuration +# Linux/arm64 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -25,6 +25,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -141,6 +142,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -213,7 +215,6 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y @@ -273,7 +274,6 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 CONFIG_STACKTRACE_SUPPORT=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y @@ -562,52 +562,6 @@ CONFIG_ARM_QCOM_CPUFREQ_HW=y # end of CPU Frequency scaling # end of CPU Power Management -# -# Firmware Drivers -# -# CONFIG_ARM_SCMI_PROTOCOL is not set -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -# CONFIG_ARM_SDE_INTERFACE is not set -CONFIG_DMIID=y -# CONFIG_DMI_SYSFS is not set -# CONFIG_ISCSI_IBFT is not set -# CONFIG_FW_CFG_SYSFS is not set -CONFIG_QCOM_SCM=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -# CONFIG_ARM_FFA_TRANSPORT is not set -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_ESRT=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB=y -CONFIG_EFI_ARMSTUB_DTB_LOADER=y -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - CONFIG_ARCH_SUPPORTS_ACPI=y CONFIG_ACPI=y CONFIG_ACPI_GENERIC_GSI=y @@ -679,6 +633,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -785,16 +740,14 @@ CONFIG_MODULE_COMPRESS_NONE=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -905,6 +858,12 @@ CONFIG_ZONE_DMA32=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -919,6 +878,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -984,6 +944,7 @@ CONFIG_IPV6_PIMSM_V2=y # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set @@ -1457,6 +1418,7 @@ CONFIG_BT_QCOMSMD=y # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y @@ -1648,6 +1610,61 @@ CONFIG_VEXPRESS_CONFIG=y # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +# CONFIG_ARM_SDE_INTERFACE is not set +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +# CONFIG_ISCSI_IBFT is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_QCOM_SCM=y +# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +# CONFIG_ARM_FFA_TRANSPORT is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1802,6 +1819,7 @@ CONFIG_VIRTIO_BLK=y # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HI6421V600_IRQ is not set # CONFIG_HP_ILO is not set # CONFIG_QCOM_COINCELL is not set # CONFIG_QCOM_FASTRPC is not set @@ -1860,6 +1878,7 @@ CONFIG_SRAM=y # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1871,6 +1890,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -1928,6 +1948,7 @@ CONFIG_SCSI_UFSHCD_PLATFORM=y # CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set CONFIG_SCSI_UFS_QCOM=y # CONFIG_SCSI_UFS_BSG is not set +# CONFIG_SCSI_UFS_HPB is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set @@ -2189,6 +2210,7 @@ CONFIG_IGBVF=y # CONFIG_IGC is not set # CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_JME is not set +# CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set # CONFIG_SKGE is not set @@ -2336,6 +2358,7 @@ CONFIG_AX88796B_PHY=y # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=m @@ -2493,7 +2516,6 @@ CONFIG_XEN_NETDEV_FRONTEND=y # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2806,15 +2828,15 @@ CONFIG_HW_RANDOM_VIRTIO=m CONFIG_HW_RANDOM_CAVIUM=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2907,6 +2929,7 @@ CONFIG_I2C_QUP=y # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2988,6 +3011,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -3023,6 +3047,7 @@ CONFIG_PINCTRL_IPQ8074=y # CONFIG_PINCTRL_MSM8226 is not set CONFIG_PINCTRL_MSM8660=y CONFIG_PINCTRL_MSM8960=y +# CONFIG_PINCTRL_MDM9607 is not set CONFIG_PINCTRL_MDM9615=y CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_MSM8916=y @@ -3041,6 +3066,7 @@ CONFIG_PINCTRL_QCOM_SSBI_PMIC=y # CONFIG_PINCTRL_SDM660 is not set # CONFIG_PINCTRL_SDM845 is not set # CONFIG_PINCTRL_SDX55 is not set +# CONFIG_PINCTRL_SM6115 is not set # CONFIG_PINCTRL_SM6125 is not set # CONFIG_PINCTRL_SM8150 is not set # CONFIG_PINCTRL_SM8250 is not set @@ -3138,6 +3164,7 @@ CONFIG_GPIO_MAX77620=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_VIRTIO is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -3225,6 +3252,7 @@ CONFIG_THERMAL_EMULATION=y CONFIG_QCOM_TSENS=y # CONFIG_QCOM_SPMI_ADC_TM5 is not set # CONFIG_QCOM_SPMI_TEMP_ALARM is not set +CONFIG_QCOM_LMH=m # end of Qualcomm thermal drivers CONFIG_WATCHDOG=y @@ -3305,6 +3333,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_HI6421_SPMI is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set @@ -3393,6 +3422,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_QCOM_PM8008 is not set CONFIG_MFD_VEXPRESS_SYSREG=y # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -3446,7 +3477,9 @@ CONFIG_REGULATOR_QCOM_SPMI=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_S5M8767 is not set @@ -3721,7 +3754,9 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set @@ -3743,6 +3778,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV9734 is not set @@ -3809,6 +3845,7 @@ CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_DP_AUX_BUS=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set @@ -3817,6 +3854,7 @@ CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_SCHED=y # # I2C encoder or helper chips @@ -3847,7 +3885,6 @@ CONFIG_DRM_I2C_SIL164=m # CONFIG_DRM_RCAR_DW_HDMI is not set # CONFIG_DRM_RCAR_LVDS is not set # CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set # CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_MSM=y CONFIG_DRM_MSM_GPU_STATE=y @@ -3879,6 +3916,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set @@ -3901,6 +3939,8 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set @@ -3923,6 +3963,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels @@ -3974,6 +4015,7 @@ CONFIG_DRM_I2C_ADV7511_CEC=y # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set # CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set @@ -4308,6 +4350,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98357A is not set @@ -5163,17 +5206,19 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set # CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +CONFIG_VFIO=y CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO_VIRQFD=y -CONFIG_VFIO=y # CONFIG_VFIO_NOIOMMU is not set -CONFIG_VFIO_PCI=y +CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=y # CONFIG_VFIO_PLATFORM is not set # CONFIG_VFIO_MDEV is not set # CONFIG_VIRT_DRIVERS is not set @@ -5194,6 +5239,7 @@ CONFIG_VHOST_MENU=y # # Microsoft Hyper-V guest support # +# CONFIG_HYPERV is not set # end of Microsoft Hyper-V guest support # @@ -5282,8 +5328,10 @@ CONFIG_MSM_LCC_8960=y CONFIG_MDM_GCC_9615=y CONFIG_MDM_LCC_9615=y CONFIG_MSM_MMCC_8960=y +# CONFIG_MSM_GCC_8953 is not set CONFIG_MSM_GCC_8974=y CONFIG_MSM_MMCC_8974=y +# CONFIG_MSM_MMCC_8994 is not set CONFIG_MSM_GCC_8994=y CONFIG_MSM_GCC_8996=y CONFIG_MSM_MMCC_8996=y @@ -5293,13 +5341,16 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_QCS_GCC_404 is not set # CONFIG_SC_CAMCC_7180 is not set # CONFIG_SC_DISPCC_7180 is not set +# CONFIG_SC_DISPCC_7280 is not set # CONFIG_SC_GCC_7180 is not set # CONFIG_SC_GCC_7280 is not set # CONFIG_SC_GCC_8180X is not set # CONFIG_SC_LPASS_CORECC_7180 is not set # CONFIG_SC_GPUCC_7180 is not set +# CONFIG_SC_GPUCC_7280 is not set # CONFIG_SC_MSS_7180 is not set # CONFIG_SC_VIDEOCC_7180 is not set +# CONFIG_SC_VIDEOCC_7280 is not set # CONFIG_SDM_CAMCC_845 is not set # CONFIG_SDM_GCC_660 is not set # CONFIG_SDM_MMCC_660 is not set @@ -5313,7 +5364,9 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_SDM_LPASSCC_845 is not set # CONFIG_SDX_GCC_55 is not set # CONFIG_SM_CAMCC_8250 is not set +# CONFIG_SM_GCC_6115 is not set # CONFIG_SM_GCC_6125 is not set +# CONFIG_SM_GCC_6350 is not set # CONFIG_SM_GCC_8150 is not set # CONFIG_SM_GCC_8250 is not set # CONFIG_SM_GCC_8350 is not set @@ -5368,12 +5421,15 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y CONFIG_ARM_SMMU=y # CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y +CONFIG_ARM_SMMU_QCOM=y # CONFIG_ARM_SMMU_V3 is not set CONFIG_QCOM_IOMMU=y # CONFIG_VIRTIO_IOMMU is not set @@ -5644,6 +5700,7 @@ CONFIG_IIO=y # CONFIG_IAQCORE is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5879,6 +5936,7 @@ CONFIG_IIO=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -6172,6 +6230,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set # CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -6272,6 +6334,7 @@ CONFIG_SUNRPC_BACKCHANNEL=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set +# CONFIG_SMB_SERVER is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -6496,7 +6559,7 @@ CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set @@ -6544,7 +6607,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_BLAKE2S=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y @@ -6674,6 +6737,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_REMAP=y @@ -6894,7 +6958,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y @@ -6941,7 +7004,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index b222f36ca0..ef76319deb 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.14.5 Kernel Configuration +# Linux/arm 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -24,6 +24,7 @@ CONFIG_BUILDTIME_TABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -141,6 +142,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -208,12 +210,12 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -264,7 +266,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -587,24 +588,6 @@ CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options -# -# Firmware Drivers -# -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCMI_POWER_DOMAIN=m -CONFIG_ARM_SCPI_PROTOCOL=m -CONFIG_ARM_SCPI_POWER_DOMAIN=m -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_TRUSTED_FOUNDATIONS is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_HAVE_ARM_SMCCC=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=y CONFIG_CRYPTO_SHA1_ARM_NEON=y @@ -628,8 +611,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # -CONFIG_SET_FS=y -CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_UPROBES=y @@ -639,6 +620,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -721,13 +703,11 @@ CONFIG_MODULE_COMPRESS_NONE=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y # CONFIG_BLK_DEV_BSGLIB is not set # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_DEV_THROTTLING is not set -CONFIG_BLK_CMDLINE_PARSER=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -832,6 +812,12 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -844,6 +830,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -910,6 +897,7 @@ CONFIG_IPV6_MULTIPLE_TABLES=y # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y @@ -936,6 +924,8 @@ CONFIG_NET_DSA_TAG_BRCM_PREPEND=m # CONFIG_NET_DSA_TAG_MTK is not set # CONFIG_NET_DSA_TAG_KSZ is not set # CONFIG_NET_DSA_TAG_RTL4_A is not set +# CONFIG_NET_DSA_TAG_OCELOT is not set +# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set # CONFIG_NET_DSA_TAG_QCA is not set # CONFIG_NET_DSA_TAG_LAN9303 is not set # CONFIG_NET_DSA_TAG_SJA1105 is not set @@ -1041,6 +1031,7 @@ CONFIG_BT_HCIRSI=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y @@ -1146,6 +1137,35 @@ CONFIG_SIMPLE_PM_BUS=y # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCMI_HAVE_TRANSPORT=y +CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y +# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set +CONFIG_ARM_SCMI_POWER_DOMAIN=m +# end of ARM System Control and Management Interface Protocol + +CONFIG_ARM_SCPI_PROTOCOL=m +CONFIG_ARM_SCPI_POWER_DOMAIN=m +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_TRUSTED_FOUNDATIONS is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_HAVE_ARM_SMCCC=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1165,6 +1185,10 @@ CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -1297,6 +1321,7 @@ CONFIG_AD525X_DPOT_I2C=y # CONFIG_DUMMY_IRQ is not set CONFIG_ICS932S401=y # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HI6421V600_IRQ is not set CONFIG_APDS9802ALS=y CONFIG_ISL29003=y # CONFIG_ISL29020 is not set @@ -1344,6 +1369,7 @@ CONFIG_EEPROM_93CX6=y # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y CONFIG_SCSI_PROC_FS=y @@ -1355,6 +1381,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -1457,6 +1484,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1517,6 +1545,7 @@ CONFIG_BCM_NET_PHYLIB=m # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m @@ -1781,7 +1810,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2024,9 +2052,8 @@ CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2089,6 +2116,7 @@ CONFIG_I2C_XILINX=y # Other I2C/SMBus bus drivers # CONFIG_I2C_CROS_EC_TUNNEL=m +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2164,6 +2192,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2219,6 +2248,7 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_PL061 is not set +CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y @@ -2274,6 +2304,7 @@ CONFIG_GPIO_TPS65910=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_VIRTIO is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2296,7 +2327,6 @@ CONFIG_BATTERY_CPCAP=y # CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set # CONFIG_AXP20X_POWER is not set -# CONFIG_AXP288_FUEL_GAUGE is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_ISP1704 is not set @@ -2327,9 +2357,9 @@ CONFIG_BATTERY_CPCAP=y # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set +# CONFIG_CHARGER_CROS_PCHG is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set -# CONFIG_RN5T618_POWER is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2353,6 +2383,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2439,6 +2470,7 @@ CONFIG_SENSORS_LM90=y # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2582,6 +2614,7 @@ CONFIG_MFD_DA9063=m # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_HI6421_SPMI is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_MFD_IQS62X is not set @@ -2675,6 +2708,8 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -2745,7 +2780,9 @@ CONFIG_REGULATOR_RN5T618=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y @@ -3123,7 +3160,9 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set @@ -3144,6 +3183,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3375,6 +3415,7 @@ CONFIG_DVB_SP2=m # # CONFIG_IMX_IPUV3_CORE is not set CONFIG_DRM=y +CONFIG_DRM_DP_AUX_BUS=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set @@ -3436,12 +3477,15 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set @@ -3452,6 +3496,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -3752,6 +3797,7 @@ CONFIG_SND_SOC_ES8328=m CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_ES8328_SPI=m # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set CONFIG_SND_SOC_MAX98090=m @@ -4329,9 +4375,7 @@ CONFIG_LEDS_CLASS_FLASH=m # # LED drivers # -# CONFIG_LEDS_AAT1290 is not set # CONFIG_LEDS_AN30259A is not set -# CONFIG_LEDS_AS3645A is not set # CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set @@ -4342,7 +4386,6 @@ CONFIG_LEDS_CPCAP=m # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_LM3692X is not set -# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set @@ -4359,10 +4402,8 @@ CONFIG_LEDS_PWM=y # CONFIG_LEDS_LT3593 is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set -CONFIG_LEDS_MAX77693=m CONFIG_LEDS_MAX8997=m # CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_KTD2692 is not set # CONFIG_LEDS_IS31FL319X is not set # CONFIG_LEDS_IS31FL32XX is not set @@ -4376,13 +4417,18 @@ CONFIG_LEDS_MAX8997=m # CONFIG_LEDS_USER is not set # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_SGM3140 is not set # # Flash and Torch LED drivers # +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_LM3601X is not set +# CONFIG_LEDS_MAX77693 is not set # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set # # LED Triggers @@ -4580,6 +4626,7 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options @@ -4691,7 +4738,6 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set -# CONFIG_MFD_HI6421_SPMI is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=m @@ -4786,6 +4832,8 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_ROCKCHIP_IOMMU=y @@ -5050,6 +5098,7 @@ CONFIG_VF610_ADC=m # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set @@ -5298,6 +5347,7 @@ CONFIG_IIO_HRTIMER_TRIGGER=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -5543,6 +5593,7 @@ CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -5579,9 +5630,7 @@ CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -5606,6 +5655,9 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5709,7 +5761,6 @@ CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set CONFIG_CIFS_DEBUG=y @@ -5719,6 +5770,8 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -5973,7 +6026,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m CONFIG_CRYPTO_LIB_BLAKE2S=m @@ -6281,7 +6334,6 @@ CONFIG_RCU_TRACE=y # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_NOP_TRACER=y @@ -6357,7 +6409,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf index 9515801941..648a54d545 100644 --- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.14.5 Kernel Configuration +# Linux/arm64 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -25,6 +25,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -137,6 +138,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -211,7 +213,6 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y @@ -272,7 +273,6 @@ CONFIG_NO_IOPORT_MAP=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y @@ -553,27 +553,6 @@ CONFIG_ARM_SCPI_CPUFREQ=y # end of CPU Frequency scaling # end of CPU Power Management -# -# Firmware Drivers -# -# CONFIG_ARM_SCMI_PROTOCOL is not set -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -# CONFIG_ARM_SDE_INTERFACE is not set -# CONFIG_ARM_FFA_TRANSPORT is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - # CONFIG_VIRTUALIZATION is not set CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA256_ARM64=y @@ -606,6 +585,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -712,13 +692,11 @@ CONFIG_MODULE_COMPRESS_NONE=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y # CONFIG_BLK_DEV_BSGLIB is not set # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_DEV_THROTTLING is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -897,6 +875,12 @@ CONFIG_ZONE_DMA32=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -911,6 +895,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -969,6 +954,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set @@ -1278,6 +1264,7 @@ CONFIG_BT_HCIRSI=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -1377,12 +1364,39 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set -# CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_ARM_FFA_TRANSPORT is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1402,6 +1416,10 @@ CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -1523,6 +1541,7 @@ CONFIG_VIRTIO_BLK=y # CONFIG_DUMMY_IRQ is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HI6421V600_IRQ is not set # CONFIG_APDS9802ALS is not set # CONFIG_ISL29003 is not set # CONFIG_ISL29020 is not set @@ -1570,6 +1589,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1581,6 +1601,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -1652,6 +1673,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1711,6 +1733,7 @@ CONFIG_AX88796B_PHY=m # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m @@ -1976,7 +1999,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2197,13 +2219,13 @@ CONFIG_HW_RANDOM=m CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2266,6 +2288,7 @@ CONFIG_I2C_RK3X=y # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2339,6 +2362,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2391,6 +2415,7 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_PL061=y +CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y @@ -2441,6 +2466,7 @@ CONFIG_GPIO_MAX77620=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_VIRTIO is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2520,6 +2546,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2605,6 +2632,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2744,6 +2772,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_HI6421_SPMI is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_MFD_IQS62X is not set @@ -2825,6 +2854,8 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -2878,7 +2909,9 @@ CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set # CONFIG_REGULATOR_S5M8767 is not set @@ -3200,7 +3233,9 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set @@ -3221,6 +3256,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -3505,12 +3541,15 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set @@ -3521,6 +3560,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -3814,6 +3854,7 @@ CONFIG_SND_SOC_ES8328=m CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_ES8328_SPI=m # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set CONFIG_SND_SOC_MAX98090=m @@ -4346,9 +4387,7 @@ CONFIG_LEDS_CLASS_FLASH=m # # LED drivers # -# CONFIG_LEDS_AAT1290 is not set # CONFIG_LEDS_AN30259A is not set -# CONFIG_LEDS_AS3645A is not set # CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set @@ -4358,7 +4397,6 @@ CONFIG_LEDS_CLASS_FLASH=m # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_LM3692X is not set -# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set @@ -4376,7 +4414,6 @@ CONFIG_LEDS_PWM=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_KTD2692 is not set # CONFIG_LEDS_IS31FL319X is not set # CONFIG_LEDS_IS31FL32XX is not set @@ -4389,13 +4426,17 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_USER is not set # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_SGM3140 is not set # # Flash and Torch LED drivers # +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set # # LED Triggers @@ -4585,14 +4626,15 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set -CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO=y +CONFIG_VFIO_IOMMU_TYPE1=y # CONFIG_VFIO_NOIOMMU is not set # CONFIG_VFIO_PLATFORM is not set # CONFIG_VFIO_MDEV is not set @@ -4700,7 +4742,6 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_WFX is not set -# CONFIG_MFD_HI6421_SPMI is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y # CONFIG_CROS_EC is not set @@ -4783,6 +4824,8 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y @@ -5040,6 +5083,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set @@ -5282,6 +5326,7 @@ CONFIG_ROCKCHIP_SARADC=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -5541,6 +5586,7 @@ CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -5580,9 +5626,7 @@ CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -5607,6 +5651,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5716,7 +5764,6 @@ CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set CONFIG_CIFS_DEBUG=y @@ -5726,6 +5773,8 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -5993,7 +6042,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m CONFIG_CRYPTO_LIB_BLAKE2S=m CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y @@ -6114,6 +6163,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_REMAP=y @@ -6329,7 +6379,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index a6052b92da..7d43d435e0 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.14.5 Kernel Configuration +# Linux/arm64 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -25,6 +25,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -137,6 +138,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -211,7 +213,6 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y @@ -271,7 +272,6 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 CONFIG_STACKTRACE_SUPPORT=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y @@ -553,28 +553,6 @@ CONFIG_ARM_SCPI_CPUFREQ=y # end of CPU Frequency scaling # end of CPU Power Management -# -# Firmware Drivers -# -# CONFIG_ARM_SCMI_PROTOCOL is not set -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -# CONFIG_ARM_SDE_INTERFACE is not set -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_ARM_FFA_TRANSPORT is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - # CONFIG_VIRTUALIZATION is not set CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA256_ARM64=y @@ -607,6 +585,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -712,13 +691,11 @@ CONFIG_MODULE_COMPRESS_NONE=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y # CONFIG_BLK_DEV_BSGLIB is not set # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_DEV_THROTTLING is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_FC_APPID is not set @@ -899,6 +876,12 @@ CONFIG_ZONE_DMA32=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -913,6 +896,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -971,6 +955,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set @@ -1280,6 +1265,7 @@ CONFIG_BT_HCIRSI=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -1372,6 +1358,7 @@ CONFIG_PCIE_ROCKCHIP_HOST=m # # CONFIG_PCIE_DW_PLAT_HOST is not set # CONFIG_PCI_HISI is not set +# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set # CONFIG_PCIE_KIRIN is not set # CONFIG_PCI_MESON is not set # CONFIG_PCIE_AL is not set @@ -1450,12 +1437,40 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set -# CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_ARM_FFA_TRANSPORT is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set @@ -1475,6 +1490,10 @@ CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -1613,6 +1632,7 @@ CONFIG_NVME_TARGET_FC=m # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HI6421V600_IRQ is not set # CONFIG_HP_ILO is not set # CONFIG_APDS9802ALS is not set # CONFIG_ISL29003 is not set @@ -1670,6 +1690,7 @@ CONFIG_ALTERA_STAPL=m # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1681,6 +1702,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -1934,6 +1956,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_JME is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -2035,6 +2058,7 @@ CONFIG_AX88796B_PHY=m # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m @@ -2249,7 +2273,6 @@ CONFIG_P54_USB=m # CONFIG_P54_PCI is not set # CONFIG_P54_SPI is not set CONFIG_P54_LEDS=y -# CONFIG_PRISM54 is not set CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_LIBERTAS=m CONFIG_LIBERTAS_USB=m @@ -2365,7 +2388,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -2595,15 +2617,15 @@ CONFIG_HW_RANDOM_CAVIUM=m CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -2687,6 +2709,7 @@ CONFIG_I2C_RK3X=y # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -2762,6 +2785,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2816,6 +2840,7 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_PL061=y +CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y @@ -2875,6 +2900,7 @@ CONFIG_GPIO_MAX77620=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_VIRTIO is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2954,6 +2980,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -3041,6 +3068,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -3200,6 +3228,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_HI6421_SPMI is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set @@ -3287,6 +3316,8 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -3340,7 +3371,9 @@ CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set # CONFIG_REGULATOR_S5M8767 is not set @@ -3430,7 +3463,6 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m CONFIG_V4L2_H264=m -CONFIG_V4L2_VP9=m CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_V4L2_FLASH_LED_CLASS=m CONFIG_V4L2_FWNODE=m @@ -3726,7 +3758,9 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set @@ -3747,6 +3781,7 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -4046,7 +4081,6 @@ CONFIG_ROCKCHIP_DW_HDMI=y # CONFIG_DRM_RCAR_DW_HDMI is not set # CONFIG_DRM_RCAR_LVDS is not set # CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set # CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_PANEL=y @@ -4058,12 +4092,15 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set @@ -4074,6 +4111,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -4126,6 +4164,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set # CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set @@ -4460,6 +4499,7 @@ CONFIG_SND_SOC_ES8328=m CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_ES8328_SPI=m # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set CONFIG_SND_SOC_MAX98090=m @@ -5030,9 +5070,7 @@ CONFIG_LEDS_CLASS_FLASH=m # # LED drivers # -# CONFIG_LEDS_AAT1290 is not set # CONFIG_LEDS_AN30259A is not set -# CONFIG_LEDS_AS3645A is not set # CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set @@ -5042,7 +5080,6 @@ CONFIG_LEDS_CLASS_FLASH=m # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_LM3692X is not set -# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set @@ -5060,7 +5097,6 @@ CONFIG_LEDS_PWM=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_KTD2692 is not set # CONFIG_LEDS_IS31FL319X is not set # CONFIG_LEDS_IS31FL32XX is not set @@ -5073,13 +5109,17 @@ CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_USER is not set # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_SGM3140 is not set # # Flash and Torch LED drivers # +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set # # LED Triggers @@ -5276,15 +5316,18 @@ CONFIG_SYNC_FILE=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set -CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO=y +CONFIG_VFIO_IOMMU_TYPE1=y # CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y # CONFIG_VFIO_PCI is not set # CONFIG_VFIO_PLATFORM is not set # CONFIG_VFIO_MDEV is not set @@ -5403,7 +5446,6 @@ CONFIG_DVB_SP8870=m # CONFIG_FIELDBUS_DEV is not set # CONFIG_QLGE is not set # CONFIG_WFX is not set -# CONFIG_MFD_HI6421_SPMI is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -5484,6 +5526,8 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y @@ -5741,6 +5785,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set # CONFIG_VZ89X is not set @@ -5983,6 +6028,7 @@ CONFIG_ROCKCHIP_SARADC=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -6249,6 +6295,7 @@ CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -6288,9 +6335,7 @@ CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -6315,6 +6360,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -6424,7 +6473,6 @@ CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set CONFIG_CIFS_DEBUG=y @@ -6434,6 +6482,8 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -6701,7 +6751,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m CONFIG_CRYPTO_LIB_BLAKE2S=m CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y @@ -6825,6 +6875,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_REMAP=y @@ -7041,7 +7092,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.16.patch similarity index 63% rename from projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch rename to projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.16.patch index ac5bbdd8bd..566916de34 100644 --- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch +++ b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.16.patch @@ -1,339 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Tue, 13 Jul 2021 17:47:13 +0800 -Subject: [PATCH] clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036 - -Add dt-binding for hclk_sfc on rk3036 - -Signed-off-by: Chris Morgan -Signed-off-by: Jon Lin -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20210713094718.1709-1-jon.lin@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - include/dt-bindings/clock/rk3036-cru.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h -index 35a5a01f9697..a96a9870ad59 100644 ---- a/include/dt-bindings/clock/rk3036-cru.h -+++ b/include/dt-bindings/clock/rk3036-cru.h -@@ -81,6 +81,7 @@ - #define HCLK_OTG0 449 - #define HCLK_OTG1 450 - #define HCLK_NANDC 453 -+#define HCLK_SFC 454 - #define HCLK_SDMMC 456 - #define HCLK_SDIO 457 - #define HCLK_EMMC 459 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jon Lin -Date: Tue, 13 Jul 2021 17:44:50 +0800 -Subject: [PATCH] clk: rockchip: rk3036: fix up the sclk_sfc parent error - -Choose the correct pll - -Signed-off-by: Elaine Zhang -Signed-off-by: Jon Lin -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20210713094456.23288-5-jon.lin@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3036.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c -index 614845cc5b4a..c38ad4ec8746 100644 ---- a/drivers/clk/rockchip/clk-rk3036.c -+++ b/drivers/clk/rockchip/clk-rk3036.c -@@ -121,6 +121,7 @@ PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; - PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; - - PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" }; -+PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" }; - - PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; - PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; -@@ -340,7 +341,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS, - RK2928_CLKGATE_CON(10), 4, GFLAGS), - -- COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, -+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0, - RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, - RK2928_CLKGATE_CON(10), 5, GFLAGS), - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jon Lin -Date: Tue, 13 Jul 2021 17:47:14 +0800 -Subject: [PATCH] clk: rockchip: Add support for hclk_sfc on rk3036 - -Add support for the bus clock for the serial flash controller on the -rk3036. Taken from the Rockchip BSP kernel but not tested on real -hardware (as I lack a 3036 based SoC to test). - -Signed-off-by: Chris Morgan -Signed-off-by: Jon Lin -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20210713094718.1709-2-jon.lin@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3036.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c -index c38ad4ec8746..d644bc155ec6 100644 ---- a/drivers/clk/rockchip/clk-rk3036.c -+++ b/drivers/clk/rockchip/clk-rk3036.c -@@ -404,7 +404,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), - GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), - GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), -- GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), -+ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), - GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), - - /* pclk_peri gates */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 10 Jun 2021 14:56:13 -0300 -Subject: [PATCH] dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Convert the rockchip,rk3399-cru binding to DT schema format. -Tested with -ARCH=arm64 make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml -ARCH=arm64 make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml - -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20210610175613.167601-1-nfraprado@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../bindings/clock/rockchip,rk3399-cru.txt | 68 -------------- - .../bindings/clock/rockchip,rk3399-cru.yaml | 92 +++++++++++++++++++ - 2 files changed, 92 insertions(+), 68 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt - create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml - -diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt -deleted file mode 100644 -index 3bc56fae90ac..000000000000 ---- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt -+++ /dev/null -@@ -1,68 +0,0 @@ --* Rockchip RK3399 Clock and Reset Unit -- --The RK3399 clock controller generates and supplies clock to various --controllers within the SoC and also implements a reset controller for SoC --peripherals. -- --Required Properties: -- --- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" --- compatible: CRU should be "rockchip,rk3399-cru" --- reg: physical base address of the controller and length of memory mapped -- region. --- #clock-cells: should be 1. --- #reset-cells: should be 1. -- --Optional Properties: -- --- rockchip,grf: phandle to the syscon managing the "general register files". -- It is used for GRF muxes, if missing any muxes present in the GRF will not -- be available. -- --Each clock is assigned an identifier and client nodes can use this identifier --to specify the clock which they consume. All available clocks are defined as --preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be --used in device tree sources. Similar macros exist for the reset sources in --these files. -- --External clocks: -- --There are several clocks that are generated outside the SoC. It is expected --that they are defined using standard clock bindings with following --clock-output-names: -- - "xin24m" - crystal input - required, -- - "xin32k" - rtc clock - optional, -- - "clkin_gmac" - external GMAC clock - optional, -- - "clkin_i2s" - external I2S clock - optional, -- - "pclkin_cif" - external ISP clock - optional, -- - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 -- - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 -- --Example: Clock controller node: -- -- pmucru: pmu-clock-controller@ff750000 { -- compatible = "rockchip,rk3399-pmucru"; -- reg = <0x0 0xff750000 0x0 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; -- }; -- -- cru: clock-controller@ff760000 { -- compatible = "rockchip,rk3399-cru"; -- reg = <0x0 0xff760000 0x0 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; -- }; -- --Example: UART controller node that consumes the clock generated by the clock -- controller: -- -- uart0: serial@ff1a0000 { -- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xff180000 0x0 0x100>; -- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; -- clock-names = "baudclk", "apb_pclk"; -- interrupts = ; -- reg-shift = <2>; -- reg-io-width = <4>; -- }; -diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml -new file mode 100644 -index 000000000000..72b286a1beba ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml -@@ -0,0 +1,92 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip RK3399 Clock and Reset Unit -+ -+maintainers: -+ - Xing Zheng -+ - Heiko Stuebner -+ -+description: | -+ The RK3399 clock controller generates and supplies clock to various -+ controllers within the SoC and also implements a reset controller for SoC -+ peripherals. -+ Each clock is assigned an identifier and client nodes can use this identifier -+ to specify the clock which they consume. All available clocks are defined as -+ preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be -+ used in device tree sources. Similar macros exist for the reset sources in -+ these files. -+ There are several clocks that are generated outside the SoC. It is expected -+ that they are defined using standard clock bindings with following -+ clock-output-names: -+ - "xin24m" - crystal input - required, -+ - "xin32k" - rtc clock - optional, -+ - "clkin_gmac" - external GMAC clock - optional, -+ - "clkin_i2s" - external I2S clock - optional, -+ - "pclkin_cif" - external ISP clock - optional, -+ - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 -+ - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,rk3399-pmucru -+ - rockchip,rk3399-cru -+ -+ reg: -+ maxItems: 1 -+ -+ "#clock-cells": -+ const: 1 -+ -+ "#reset-cells": -+ const: 1 -+ -+ clocks: -+ minItems: 1 -+ -+ assigned-clocks: -+ minItems: 1 -+ maxItems: 64 -+ -+ assigned-clock-parents: -+ minItems: 1 -+ maxItems: 64 -+ -+ assigned-clock-rates: -+ minItems: 1 -+ maxItems: 64 -+ -+ rockchip,grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: > -+ phandle to the syscon managing the "general register files". It is used -+ for GRF muxes, if missing any muxes present in the GRF will not be -+ available. -+ -+required: -+ - compatible -+ - reg -+ - "#clock-cells" -+ - "#reset-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ pmucru: pmu-clock-controller@ff750000 { -+ compatible = "rockchip,rk3399-pmucru"; -+ reg = <0xff750000 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ - | -+ cru: clock-controller@ff760000 { -+ compatible = "rockchip,rk3399-cru"; -+ reg = <0xff760000 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Yunhao Tian -Date: Wed, 21 Jul 2021 20:48:16 +0800 -Subject: [PATCH] clk: rockchip: make rk3308 ddrphy4x clock critical - -Currently, no driver support for DDR memory controller (DMC) is present, -as a result, no driver is explicitly consuming the ddrphy clock. This means -that VPLL1 (parent of ddr clock) will be shutdown if we enable -and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX). -If VPLL1 is disabled, the whole system will freeze, because the DDR -controller will lose its clock. So, it's necessary to prevent VPLL1 from -shutting down, by marking the ddrphy4x CLK_IS_CRITICAL. - -This bug was discovered when I was porting rockchip_i2s_tdm driver to -mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip -SoCs without DMC driver may need the same patch. If this applies to -other devices, please let us know. - -Signed-off-by: Yunhao Tian -Link: https://lore.kernel.org/r/BYAPR20MB24886765F888A9705CBEB70789E39@BYAPR20MB2488.namprd20.prod.outlook.com -[adapted subject, changed to add the clock to the critical list] -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3308.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c -index 2c3bd0c749f2..db3396c3e6e9 100644 ---- a/drivers/clk/rockchip/clk-rk3308.c -+++ b/drivers/clk/rockchip/clk-rk3308.c -@@ -911,6 +911,7 @@ static const char *const rk3308_critical_clocks[] __initconst = { - "hclk_audio", - "pclk_audio", - "sclk_ddrc", -+ "clk_ddrphy4x", - }; - - static void __init rk3308_clk_init(struct device_node *np) - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sun, 11 Jul 2021 16:34:30 +0200 @@ -2496,928 +2160,139 @@ index 7fc674a99a6c..35218c2771a2 100644 status = "okay"; }; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Thu, 12 Aug 2021 21:45:41 +0800 -Subject: [PATCH] spi: rockchip-sfc: Bindings for Rockchip serial flash - controller +From 6594988fd625ff0d9a8f90f1788e16185358a3e6 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 16 Oct 2021 12:50:22 +0200 +Subject: clk: composite: Use rate_ops.determine_rate when also a mux is + available -Add bindings for the Rockchip serial flash controller. New device -specific parameter of rockchip,sfc-no-dma included in documentation. +Update clk_composite_determine_rate() to use rate_ops.determine_rate +when available in combination with a mux. So far clk_divider_ops provide +both, .round_rate and .determine_rate. Removing the former would make +clk-composite fail silently for example on Rockchip platforms (which +heavily use composite clocks). +Add support for using rate_ops.determine_rate when either +rate_ops.round_rate is not available or both (.round_rate and +.determine_rate) are provided. -Signed-off-by: Chris Morgan -Signed-off-by: Jon Lin -Tested-by: Peter Geis -Link: https://lore.kernel.org/r/20210812134546.31340-2-jon.lin@rock-chips.com -Signed-off-by: Mark Brown +Suggested-by: Alex Bee +Signed-off-by: Martin Blumenstingl +Link: https://lore.kernel.org/r/20211016105022.303413-3-martin.blumenstingl@googlemail.com +Tested-by: Alex Bee +Tested-by: Chen-Yu Tsai +Signed-off-by: Stephen Boyd --- - .../devicetree/bindings/spi/rockchip-sfc.yaml | 91 +++++++++++++++++++ - 1 file changed, 91 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml + drivers/clk/clk-composite.c | 68 ++++++++++++++++++++++++++++++++------------- + 1 file changed, 48 insertions(+), 20 deletions(-) -diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml -new file mode 100644 -index 000000000000..339fb39529f3 ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml -@@ -0,0 +1,91 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip Serial Flash Controller (SFC) -+ -+maintainers: -+ - Heiko Stuebner -+ - Chris Morgan -+ -+allOf: -+ - $ref: spi-controller.yaml# -+ -+properties: -+ compatible: -+ const: rockchip,sfc -+ description: -+ The rockchip sfc controller is a standalone IP with version register, -+ and the driver can handle all the feature difference inside the IP -+ depending on the version register. -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: Bus Clock -+ - description: Module Clock -+ -+ clock-names: -+ items: -+ - const: clk_sfc -+ - const: hclk_sfc -+ -+ power-domains: -+ maxItems: 1 -+ -+ rockchip,sfc-no-dma: -+ description: Disable DMA and utilize FIFO mode only -+ type: boolean -+ -+patternProperties: -+ "^flash@[0-3]$": -+ type: object -+ properties: -+ reg: -+ minimum: 0 -+ maximum: 3 -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ -+ sfc: spi@ff3a0000 { -+ compatible = "rockchip,sfc"; -+ reg = <0xff3a0000 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -+ clock-names = "clk_sfc", "hclk_sfc"; -+ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; -+ pinctrl-names = "default"; -+ power-domains = <&power PX30_PD_MMC_NAND>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <108000000>; -+ spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <2>; -+ }; -+ }; -+ -+... - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Thu, 12 Aug 2021 21:45:42 +0800 -Subject: [PATCH] spi: rockchip-sfc: add rockchip serial flash controller - -Add the rockchip serial flash controller (SFC) driver. - -Signed-off-by: Chris Morgan -Signed-off-by: Jon Lin -Tested-by: Peter Geis -Tested-by: Chris Morgan -Link: https://lore.kernel.org/r/20210812134546.31340-3-jon.lin@rock-chips.com -Signed-off-by: Mark Brown ---- - drivers/spi/Kconfig | 12 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-rockchip-sfc.c | 694 +++++++++++++++++++++++++++++++++ - 3 files changed, 707 insertions(+) - create mode 100644 drivers/spi/spi-rockchip-sfc.c - -diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index e71a4c514f7b..83e352b0c8f9 100644 ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -658,6 +658,18 @@ config SPI_ROCKCHIP - The main usecase of this controller is to use spi flash as boot - device. - -+config SPI_ROCKCHIP_SFC -+ tristate "Rockchip Serial Flash Controller (SFC)" -+ depends on ARCH_ROCKCHIP || COMPILE_TEST -+ depends on HAS_IOMEM && HAS_DMA -+ help -+ This enables support for Rockchip serial flash controller. This -+ is a specialized controller used to access SPI flash on some -+ Rockchip SOCs. -+ -+ ROCKCHIP SFC supports DMA and PIO modes. When DMA is not available, -+ the driver automatically falls back to PIO mode. -+ - config SPI_RB4XX - tristate "Mikrotik RB4XX SPI master" - depends on SPI_MASTER && ATH79 -diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index 13e54c45e9df..699db95c8441 100644 ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -95,6 +95,7 @@ obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o - obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o - obj-$(CONFIG_SPI_QUP) += spi-qup.o - obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o -+obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o - obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o - obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o -diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c -new file mode 100644 -index 000000000000..7c4d47fe80c2 ---- /dev/null -+++ b/drivers/spi/spi-rockchip-sfc.c -@@ -0,0 +1,694 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Rockchip Serial Flash Controller Driver -+ * -+ * Copyright (c) 2017-2021, Rockchip Inc. -+ * Author: Shawn Lin -+ * Chris Morgan -+ * Jon Lin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* System control */ -+#define SFC_CTRL 0x0 -+#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) -+#define SFC_CTRL_CMD_BITS_SHIFT 8 -+#define SFC_CTRL_ADDR_BITS_SHIFT 10 -+#define SFC_CTRL_DATA_BITS_SHIFT 12 -+ -+/* Interrupt mask */ -+#define SFC_IMR 0x4 -+#define SFC_IMR_RX_FULL BIT(0) -+#define SFC_IMR_RX_UFLOW BIT(1) -+#define SFC_IMR_TX_OFLOW BIT(2) -+#define SFC_IMR_TX_EMPTY BIT(3) -+#define SFC_IMR_TRAN_FINISH BIT(4) -+#define SFC_IMR_BUS_ERR BIT(5) -+#define SFC_IMR_NSPI_ERR BIT(6) -+#define SFC_IMR_DMA BIT(7) -+ -+/* Interrupt clear */ -+#define SFC_ICLR 0x8 -+#define SFC_ICLR_RX_FULL BIT(0) -+#define SFC_ICLR_RX_UFLOW BIT(1) -+#define SFC_ICLR_TX_OFLOW BIT(2) -+#define SFC_ICLR_TX_EMPTY BIT(3) -+#define SFC_ICLR_TRAN_FINISH BIT(4) -+#define SFC_ICLR_BUS_ERR BIT(5) -+#define SFC_ICLR_NSPI_ERR BIT(6) -+#define SFC_ICLR_DMA BIT(7) -+ -+/* FIFO threshold level */ -+#define SFC_FTLR 0xc -+#define SFC_FTLR_TX_SHIFT 0 -+#define SFC_FTLR_TX_MASK 0x1f -+#define SFC_FTLR_RX_SHIFT 8 -+#define SFC_FTLR_RX_MASK 0x1f -+ -+/* Reset FSM and FIFO */ -+#define SFC_RCVR 0x10 -+#define SFC_RCVR_RESET BIT(0) -+ -+/* Enhanced mode */ -+#define SFC_AX 0x14 -+ -+/* Address Bit number */ -+#define SFC_ABIT 0x18 -+ -+/* Interrupt status */ -+#define SFC_ISR 0x1c -+#define SFC_ISR_RX_FULL_SHIFT BIT(0) -+#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) -+#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) -+#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) -+#define SFC_ISR_TX_FINISH_SHIFT BIT(4) -+#define SFC_ISR_BUS_ERR_SHIFT BIT(5) -+#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) -+#define SFC_ISR_DMA_SHIFT BIT(7) -+ -+/* FIFO status */ -+#define SFC_FSR 0x20 -+#define SFC_FSR_TX_IS_FULL BIT(0) -+#define SFC_FSR_TX_IS_EMPTY BIT(1) -+#define SFC_FSR_RX_IS_EMPTY BIT(2) -+#define SFC_FSR_RX_IS_FULL BIT(3) -+#define SFC_FSR_TXLV_MASK GENMASK(12, 8) -+#define SFC_FSR_TXLV_SHIFT 8 -+#define SFC_FSR_RXLV_MASK GENMASK(20, 16) -+#define SFC_FSR_RXLV_SHIFT 16 -+ -+/* FSM status */ -+#define SFC_SR 0x24 -+#define SFC_SR_IS_IDLE 0x0 -+#define SFC_SR_IS_BUSY 0x1 -+ -+/* Raw interrupt status */ -+#define SFC_RISR 0x28 -+#define SFC_RISR_RX_FULL BIT(0) -+#define SFC_RISR_RX_UNDERFLOW BIT(1) -+#define SFC_RISR_TX_OVERFLOW BIT(2) -+#define SFC_RISR_TX_EMPTY BIT(3) -+#define SFC_RISR_TRAN_FINISH BIT(4) -+#define SFC_RISR_BUS_ERR BIT(5) -+#define SFC_RISR_NSPI_ERR BIT(6) -+#define SFC_RISR_DMA BIT(7) -+ -+/* Version */ -+#define SFC_VER 0x2C -+#define SFC_VER_3 0x3 -+#define SFC_VER_4 0x4 -+#define SFC_VER_5 0x5 -+ -+/* Delay line controller resiter */ -+#define SFC_DLL_CTRL0 0x3C -+#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) -+#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU -+#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU -+ -+/* Master trigger */ -+#define SFC_DMA_TRIGGER 0x80 -+#define SFC_DMA_TRIGGER_START 1 -+ -+/* Src or Dst addr for master */ -+#define SFC_DMA_ADDR 0x84 -+ -+/* Length control register extension 32GB */ -+#define SFC_LEN_CTRL 0x88 -+#define SFC_LEN_CTRL_TRB_SEL 1 -+#define SFC_LEN_EXT 0x8C -+ -+/* Command */ -+#define SFC_CMD 0x100 -+#define SFC_CMD_IDX_SHIFT 0 -+#define SFC_CMD_DUMMY_SHIFT 8 -+#define SFC_CMD_DIR_SHIFT 12 -+#define SFC_CMD_DIR_RD 0 -+#define SFC_CMD_DIR_WR 1 -+#define SFC_CMD_ADDR_SHIFT 14 -+#define SFC_CMD_ADDR_0BITS 0 -+#define SFC_CMD_ADDR_24BITS 1 -+#define SFC_CMD_ADDR_32BITS 2 -+#define SFC_CMD_ADDR_XBITS 3 -+#define SFC_CMD_TRAN_BYTES_SHIFT 16 -+#define SFC_CMD_CS_SHIFT 30 -+ -+/* Address */ -+#define SFC_ADDR 0x104 -+ -+/* Data */ -+#define SFC_DATA 0x108 -+ -+/* The controller and documentation reports that it supports up to 4 CS -+ * devices (0-3), however I have only been able to test a single CS (CS 0) -+ * due to the configuration of my device. -+ */ -+#define SFC_MAX_CHIPSELECT_NUM 4 -+ -+/* The SFC can transfer max 16KB - 1 at one time -+ * we set it to 15.5KB here for alignment. -+ */ -+#define SFC_MAX_IOSIZE_VER3 (512 * 31) -+ -+/* DMA is only enabled for large data transmission */ -+#define SFC_DMA_TRANS_THRETHOLD (0x40) -+ -+/* Maximum clock values from datasheet suggest keeping clock value under -+ * 150MHz. No minimum or average value is suggested. -+ */ -+#define SFC_MAX_SPEED (150 * 1000 * 1000) -+ -+struct rockchip_sfc { -+ struct device *dev; -+ void __iomem *regbase; -+ struct clk *hclk; -+ struct clk *clk; -+ u32 frequency; -+ /* virtual mapped addr for dma_buffer */ -+ void *buffer; -+ dma_addr_t dma_buffer; -+ struct completion cp; -+ bool use_dma; -+ u32 max_iosize; -+ u16 version; -+}; -+ -+static int rockchip_sfc_reset(struct rockchip_sfc *sfc) -+{ -+ int err; -+ u32 status; -+ -+ writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); -+ -+ err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, -+ !(status & SFC_RCVR_RESET), 20, -+ jiffies_to_usecs(HZ)); -+ if (err) -+ dev_err(sfc->dev, "SFC reset never finished\n"); -+ -+ /* Still need to clear the masked interrupt from RISR */ -+ writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR); -+ -+ dev_dbg(sfc->dev, "reset\n"); -+ -+ return err; -+} -+ -+static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) -+{ -+ return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); -+} -+ -+static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) -+{ -+ return SFC_MAX_IOSIZE_VER3; -+} -+ -+static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask) -+{ -+ u32 reg; -+ -+ /* Enable transfer complete interrupt */ -+ reg = readl(sfc->regbase + SFC_IMR); -+ reg &= ~mask; -+ writel(reg, sfc->regbase + SFC_IMR); -+} -+ -+static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask) -+{ -+ u32 reg; -+ -+ /* Disable transfer finish interrupt */ -+ reg = readl(sfc->regbase + SFC_IMR); -+ reg |= mask; -+ writel(reg, sfc->regbase + SFC_IMR); -+} -+ -+static int rockchip_sfc_init(struct rockchip_sfc *sfc) -+{ -+ writel(0, sfc->regbase + SFC_CTRL); -+ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); -+ rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF); -+ if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) -+ writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); -+ -+ return 0; -+} -+ -+static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) -+{ -+ int ret = 0; -+ u32 status; -+ -+ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, -+ status & SFC_FSR_TXLV_MASK, 0, -+ timeout_us); -+ if (ret) { -+ dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); -+ -+ ret = -ETIMEDOUT; -+ } -+ -+ return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; -+} -+ -+static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) -+{ -+ int ret = 0; -+ u32 status; -+ -+ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, -+ status & SFC_FSR_RXLV_MASK, 0, -+ timeout_us); -+ if (ret) { -+ dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); -+ -+ ret = -ETIMEDOUT; -+ } -+ -+ return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; -+} -+ -+static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) -+{ -+ if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { -+ /* -+ * SFC not support output DUMMY cycles right after CMD cycles, so -+ * treat it as ADDR cycles. -+ */ -+ op->addr.nbytes = op->dummy.nbytes; -+ op->addr.buswidth = op->dummy.buswidth; -+ op->addr.val = 0xFFFFFFFFF; -+ -+ op->dummy.nbytes = 0; -+ } -+} -+ -+static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, -+ struct spi_mem *mem, -+ const struct spi_mem_op *op, -+ u32 len) -+{ -+ u32 ctrl = 0, cmd = 0; -+ -+ /* set CMD */ -+ cmd = op->cmd.opcode; -+ ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); -+ -+ /* set ADDR */ -+ if (op->addr.nbytes) { -+ if (op->addr.nbytes == 4) { -+ cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; -+ } else if (op->addr.nbytes == 3) { -+ cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; -+ } else { -+ cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; -+ writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); -+ } -+ -+ ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); -+ } -+ -+ /* set DUMMY */ -+ if (op->dummy.nbytes) { -+ if (op->dummy.buswidth == 4) -+ cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; -+ else if (op->dummy.buswidth == 2) -+ cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; -+ else -+ cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; -+ } -+ -+ /* set DATA */ -+ if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ -+ writel(len, sfc->regbase + SFC_LEN_EXT); -+ else -+ cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; -+ if (len) { -+ if (op->data.dir == SPI_MEM_DATA_OUT) -+ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; -+ -+ ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); -+ } -+ if (!len && op->addr.nbytes) -+ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; -+ -+ /* set the Controller */ -+ ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; -+ cmd |= mem->spi->chip_select << SFC_CMD_CS_SHIFT; -+ -+ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", -+ op->addr.nbytes, op->addr.buswidth, -+ op->dummy.nbytes, op->dummy.buswidth); -+ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", -+ ctrl, cmd, op->addr.val, len); -+ -+ writel(ctrl, sfc->regbase + SFC_CTRL); -+ writel(cmd, sfc->regbase + SFC_CMD); -+ if (op->addr.nbytes) -+ writel(op->addr.val, sfc->regbase + SFC_ADDR); -+ -+ return 0; -+} -+ -+static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) -+{ -+ u8 bytes = len & 0x3; -+ u32 dwords; -+ int tx_level; -+ u32 write_words; -+ u32 tmp = 0; -+ -+ dwords = len >> 2; -+ while (dwords) { -+ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); -+ if (tx_level < 0) -+ return tx_level; -+ write_words = min_t(u32, tx_level, dwords); -+ iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words); -+ buf += write_words << 2; -+ dwords -= write_words; -+ } -+ -+ /* write the rest non word aligned bytes */ -+ if (bytes) { -+ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); -+ if (tx_level < 0) -+ return tx_level; -+ memcpy(&tmp, buf, bytes); -+ writel(tmp, sfc->regbase + SFC_DATA); -+ } -+ -+ return len; -+} -+ -+static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) -+{ -+ u8 bytes = len & 0x3; -+ u32 dwords; -+ u8 read_words; -+ int rx_level; -+ int tmp; -+ -+ /* word aligned access only */ -+ dwords = len >> 2; -+ while (dwords) { -+ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); -+ if (rx_level < 0) -+ return rx_level; -+ read_words = min_t(u32, rx_level, dwords); -+ ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words); -+ buf += read_words << 2; -+ dwords -= read_words; -+ } -+ -+ /* read the rest non word aligned bytes */ -+ if (bytes) { -+ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); -+ if (rx_level < 0) -+ return rx_level; -+ tmp = readl(sfc->regbase + SFC_DATA); -+ memcpy(buf, &tmp, bytes); -+ } -+ -+ return len; -+} -+ -+static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) -+{ -+ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); -+ writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); -+ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); -+ -+ return len; -+} -+ -+static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, -+ const struct spi_mem_op *op, u32 len) -+{ -+ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); -+ -+ if (op->data.dir == SPI_MEM_DATA_OUT) -+ return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); -+ else -+ return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); -+} -+ -+static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, -+ const struct spi_mem_op *op, u32 len) -+{ -+ int ret; -+ -+ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); -+ -+ if (op->data.dir == SPI_MEM_DATA_OUT) -+ memcpy_toio(sfc->buffer, op->data.buf.out, len); -+ -+ ret = rockchip_sfc_fifo_transfer_dma(sfc, sfc->dma_buffer, len); -+ if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) { -+ dev_err(sfc->dev, "DMA wait for transfer finish timeout\n"); -+ ret = -ETIMEDOUT; -+ } -+ rockchip_sfc_irq_mask(sfc, SFC_IMR_DMA); -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ memcpy_fromio(op->data.buf.in, sfc->buffer, len); -+ -+ return ret; -+} -+ -+static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) -+{ -+ int ret = 0; -+ u32 status; -+ -+ ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, -+ !(status & SFC_SR_IS_BUSY), -+ 20, timeout_us); -+ if (ret) { -+ dev_err(sfc->dev, "wait sfc idle timeout\n"); -+ rockchip_sfc_reset(sfc); -+ -+ ret = -EIO; -+ } -+ -+ return ret; -+} -+ -+static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) -+{ -+ struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); -+ u32 len = op->data.nbytes; -+ int ret; -+ -+ if (unlikely(mem->spi->max_speed_hz != sfc->frequency)) { -+ ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz); -+ if (ret) -+ return ret; -+ sfc->frequency = mem->spi->max_speed_hz; -+ dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", -+ sfc->frequency, clk_get_rate(sfc->clk)); -+ } -+ -+ rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); -+ rockchip_sfc_xfer_setup(sfc, mem, op, len); -+ if (len) { -+ if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { -+ init_completion(&sfc->cp); -+ rockchip_sfc_irq_unmask(sfc, SFC_IMR_DMA); -+ ret = rockchip_sfc_xfer_data_dma(sfc, op, len); -+ } else { -+ ret = rockchip_sfc_xfer_data_poll(sfc, op, len); -+ } -+ -+ if (ret != len) { -+ dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); -+ -+ return -EIO; -+ } -+ } -+ -+ return rockchip_sfc_xfer_done(sfc, 100000); -+} -+ -+static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) -+{ -+ struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); -+ -+ op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); -+ -+ return 0; -+} -+ -+static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { -+ .exec_op = rockchip_sfc_exec_mem_op, -+ .adjust_op_size = rockchip_sfc_adjust_op_size, -+}; -+ -+static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) -+{ -+ struct rockchip_sfc *sfc = dev_id; -+ u32 reg; -+ -+ reg = readl(sfc->regbase + SFC_RISR); -+ -+ /* Clear interrupt */ -+ writel_relaxed(reg, sfc->regbase + SFC_ICLR); -+ -+ if (reg & SFC_RISR_DMA) { -+ complete(&sfc->cp); -+ -+ return IRQ_HANDLED; -+ } -+ -+ return IRQ_NONE; -+} -+ -+static int rockchip_sfc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct spi_master *master; -+ struct resource *res; -+ struct rockchip_sfc *sfc; -+ int ret; -+ -+ master = devm_spi_alloc_master(&pdev->dev, sizeof(*sfc)); -+ if (!master) -+ return -ENOMEM; -+ -+ master->flags = SPI_MASTER_HALF_DUPLEX; -+ master->mem_ops = &rockchip_sfc_mem_ops; -+ master->dev.of_node = pdev->dev.of_node; -+ master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL; -+ master->max_speed_hz = SFC_MAX_SPEED; -+ master->num_chipselect = SFC_MAX_CHIPSELECT_NUM; -+ -+ sfc = spi_master_get_devdata(master); -+ sfc->dev = dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ sfc->regbase = devm_ioremap_resource(dev, res); -+ if (IS_ERR(sfc->regbase)) -+ return PTR_ERR(sfc->regbase); -+ -+ sfc->clk = devm_clk_get(&pdev->dev, "clk_sfc"); -+ if (IS_ERR(sfc->clk)) { -+ dev_err(&pdev->dev, "Failed to get sfc interface clk\n"); -+ return PTR_ERR(sfc->clk); -+ } -+ -+ sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc"); -+ if (IS_ERR(sfc->hclk)) { -+ dev_err(&pdev->dev, "Failed to get sfc ahb clk\n"); -+ return PTR_ERR(sfc->hclk); -+ } -+ -+ sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, -+ "rockchip,sfc-no-dma"); -+ -+ if (sfc->use_dma) { -+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_warn(dev, "Unable to set dma mask\n"); -+ return ret; -+ } -+ -+ sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_IOSIZE_VER3, -+ &sfc->dma_buffer, -+ GFP_KERNEL); -+ if (!sfc->buffer) -+ return -ENOMEM; -+ } -+ -+ ret = clk_prepare_enable(sfc->hclk); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to enable ahb clk\n"); -+ goto err_hclk; -+ } -+ -+ ret = clk_prepare_enable(sfc->clk); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to enable interface clk\n"); -+ goto err_clk; -+ } -+ -+ /* Find the irq */ -+ ret = platform_get_irq(pdev, 0); -+ if (ret < 0) { -+ dev_err(dev, "Failed to get the irq\n"); -+ goto err_irq; -+ } -+ -+ ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler, -+ 0, pdev->name, sfc); -+ if (ret) { -+ dev_err(dev, "Failed to request irq\n"); -+ -+ return ret; -+ } -+ -+ ret = rockchip_sfc_init(sfc); -+ if (ret) -+ goto err_irq; -+ -+ sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); -+ sfc->version = rockchip_sfc_get_version(sfc); -+ -+ ret = spi_register_master(master); -+ if (ret) -+ goto err_irq; -+ -+ return 0; -+ -+err_irq: -+ clk_disable_unprepare(sfc->clk); -+err_clk: -+ clk_disable_unprepare(sfc->hclk); -+err_hclk: -+ return ret; -+} -+ -+static int rockchip_sfc_remove(struct platform_device *pdev) -+{ -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct rockchip_sfc *sfc = platform_get_drvdata(pdev); -+ -+ spi_unregister_master(master); -+ -+ clk_disable_unprepare(sfc->clk); -+ clk_disable_unprepare(sfc->hclk); -+ -+ return 0; -+} -+ -+static const struct of_device_id rockchip_sfc_dt_ids[] = { -+ { .compatible = "rockchip,sfc"}, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids); -+ -+static struct platform_driver rockchip_sfc_driver = { -+ .driver = { -+ .name = "rockchip-sfc", -+ .of_match_table = rockchip_sfc_dt_ids, -+ }, -+ .probe = rockchip_sfc_probe, -+ .remove = rockchip_sfc_remove, -+}; -+module_platform_driver(rockchip_sfc_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver"); -+MODULE_AUTHOR("Shawn Lin "); -+MODULE_AUTHOR("Chris Morgan "); -+MODULE_AUTHOR("Jon Lin "); -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Punit Agrawal -Date: Wed, 29 Sep 2021 22:50:49 +0900 -Subject: [PATCH] net: stmmac: dwmac-rk: Fix ethernet on rk3399 based devices - -Commit 2d26f6e39afb ("net: stmmac: dwmac-rk: fix unbalanced pm_runtime_enable warnings") -while getting rid of a runtime PM warning ended up breaking ethernet -on rk3399 based devices. By dropping an extra reference to the device, -the commit ends up enabling suspend / resume of the ethernet device - -which appears to be broken. - -While the issue with runtime pm is being investigated, partially -revert commit 2d26f6e39afb to restore the network on rk3399. - -Fixes: 2d26f6e39afb ("net: stmmac: dwmac-rk: fix unbalanced pm_runtime_enable warnings") -Suggested-by: Heiko Stuebner -Signed-off-by: Punit Agrawal -Cc: Michael Riesch -Tested-by: Heiko Stuebner ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -index ed817011a94a..6924a6aacbd5 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - - #include "stmmac_platform.h" - -@@ -1528,6 +1529,8 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) - return ret; - } - -+ pm_runtime_get_sync(dev); -+ - if (bsp_priv->integrated_phy) - rk_gmac_integrated_phy_powerup(bsp_priv); - -@@ -1539,6 +1542,8 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac) - if (gmac->integrated_phy) - rk_gmac_integrated_phy_powerdown(gmac); - -+ pm_runtime_put_sync(&gmac->pdev->dev); -+ - phy_power_on(gmac, false); - gmac_clk_enable(gmac, false); +diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c +index 510a9965633bb..075c7f2a7ec4d 100644 +--- a/drivers/clk/clk-composite.c ++++ b/drivers/clk/clk-composite.c +@@ -42,6 +42,29 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, + return rate_ops->recalc_rate(rate_hw, parent_rate); } + ++static int clk_composite_determine_rate_for_parent(struct clk_hw *rate_hw, ++ struct clk_rate_request *req, ++ struct clk_hw *parent_hw, ++ const struct clk_ops *rate_ops) ++{ ++ long rate; ++ ++ req->best_parent_hw = parent_hw; ++ req->best_parent_rate = clk_hw_get_rate(parent_hw); ++ ++ if (rate_ops->determine_rate) ++ return rate_ops->determine_rate(rate_hw, req); ++ ++ rate = rate_ops->round_rate(rate_hw, req->rate, ++ &req->best_parent_rate); ++ if (rate < 0) ++ return rate; ++ ++ req->rate = rate; ++ ++ return 0; ++} ++ + static int clk_composite_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) + { +@@ -51,51 +74,56 @@ static int clk_composite_determine_rate(struct clk_hw *hw, + struct clk_hw *rate_hw = composite->rate_hw; + struct clk_hw *mux_hw = composite->mux_hw; + struct clk_hw *parent; +- unsigned long parent_rate; +- long tmp_rate, best_rate = 0; + unsigned long rate_diff; + unsigned long best_rate_diff = ULONG_MAX; +- long rate; +- int i; ++ unsigned long best_rate = 0; ++ int i, ret; + +- if (rate_hw && rate_ops && rate_ops->round_rate && ++ if (rate_hw && rate_ops && ++ (rate_ops->determine_rate || rate_ops->round_rate) && + mux_hw && mux_ops && mux_ops->set_parent) { + req->best_parent_hw = NULL; + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { ++ struct clk_rate_request tmp_req = *req; ++ + parent = clk_hw_get_parent(mux_hw); +- req->best_parent_hw = parent; +- req->best_parent_rate = clk_hw_get_rate(parent); + +- rate = rate_ops->round_rate(rate_hw, req->rate, +- &req->best_parent_rate); +- if (rate < 0) +- return rate; ++ ret = clk_composite_determine_rate_for_parent(rate_hw, ++ &tmp_req, ++ parent, ++ rate_ops); ++ if (ret) ++ return ret; ++ ++ req->rate = tmp_req.rate; ++ req->best_parent_rate = tmp_req.best_parent_rate; + +- req->rate = rate; + return 0; + } + + for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) { ++ struct clk_rate_request tmp_req = *req; ++ + parent = clk_hw_get_parent_by_index(mux_hw, i); + if (!parent) + continue; + +- parent_rate = clk_hw_get_rate(parent); +- +- tmp_rate = rate_ops->round_rate(rate_hw, req->rate, +- &parent_rate); +- if (tmp_rate < 0) ++ ret = clk_composite_determine_rate_for_parent(rate_hw, ++ &tmp_req, ++ parent, ++ rate_ops); ++ if (ret) + continue; + +- rate_diff = abs(req->rate - tmp_rate); ++ rate_diff = abs(req->rate - tmp_req.rate); + + if (!rate_diff || !req->best_parent_hw + || best_rate_diff > rate_diff) { + req->best_parent_hw = parent; +- req->best_parent_rate = parent_rate; ++ req->best_parent_rate = tmp_req.best_parent_rate; + best_rate_diff = rate_diff; +- best_rate = tmp_rate; ++ best_rate = tmp_req.rate; + } + + if (!rate_diff) diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch deleted file mode 100644 index 7f916173a2..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch +++ /dev/null @@ -1,1210 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Mon, 19 Jul 2021 22:52:34 +0200 -Subject: [PATCH] media: hantro: Make struct hantro_variant.init() optional - -The hantro_variant.init() function is there for platforms -to perform hardware-specific initialization, such as -clock rate bumping. - -Not all platforms require it, so make it optional. - -Signed-off-by: Ezequiel Garcia -Tested-by: Alex Bee -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/hantro.h | 4 ++-- - drivers/staging/media/hantro/hantro_drv.c | 10 ++++++---- - drivers/staging/media/hantro/sama5d4_vdec_hw.c | 6 ------ - 3 files changed, 8 insertions(+), 12 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index a70c386de6f1..c2e2dca38628 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -61,8 +61,8 @@ struct hantro_irq { - * @num_postproc_fmts: Number of post-processor formats. - * @codec: Supported codecs - * @codec_ops: Codec ops. -- * @init: Initialize hardware. -- * @runtime_resume: reenable hardware after power gating -+ * @init: Initialize hardware, optional. -+ * @runtime_resume: reenable hardware after power gating, optional. - * @irqs: array of irq names and interrupt handlers - * @num_irqs: number of irqs in the array - * @clk_names: array of clock names -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 31d8449ca1d2..9b5415176bfe 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -942,10 +942,12 @@ static int hantro_probe(struct platform_device *pdev) - } - } - -- ret = vpu->variant->init(vpu); -- if (ret) { -- dev_err(&pdev->dev, "Failed to init VPU hardware\n"); -- return ret; -+ if (vpu->variant->init) { -+ ret = vpu->variant->init(vpu); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to init VPU hardware\n"); -+ return ret; -+ } - } - - pm_runtime_set_autosuspend_delay(vpu->dev, 100); -diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -index 58ae72c2b723..9c3b8cd0b239 100644 ---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c -+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -@@ -64,11 +64,6 @@ static const struct hantro_fmt sama5d4_vdec_fmts[] = { - }, - }; - --static int sama5d4_hw_init(struct hantro_dev *vpu) --{ -- return 0; --} -- - /* - * Supported codec ops. - */ -@@ -109,7 +104,6 @@ const struct hantro_variant sama5d4_vdec_variant = { - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = sama5d4_vdec_codec_ops, -- .init = sama5d4_hw_init, - .irqs = sama5d4_irqs, - .num_irqs = ARRAY_SIZE(sama5d4_irqs), - .clk_names = sama5d4_clk_names, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Mon, 19 Jul 2021 22:52:35 +0200 -Subject: [PATCH] media: hantro: Avoid redundant hantro_get_{dst,src}_buf() - calls - -Getting the next src/dst buffer is relatively expensive -so avoid doing it multiple times. - -Signed-off-by: Ezequiel Garcia -Tested-by: Alex Bee -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++++++++--------- - .../staging/media/hantro/hantro_g1_vp8_dec.c | 18 +++++++++--------- - .../media/hantro/rockchip_vpu2_hw_vp8_dec.c | 19 +++++++++---------- - 3 files changed, 26 insertions(+), 28 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -index 5c792b7bcb79..2aa37baad0c3 100644 ---- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c -+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -@@ -19,13 +19,12 @@ - #include "hantro_hw.h" - #include "hantro_v4l2.h" - --static void set_params(struct hantro_ctx *ctx) -+static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) - { - const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; - const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; - const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; - const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; -- struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx); - struct hantro_dev *vpu = ctx->dev; - u32 reg; - -@@ -226,22 +225,20 @@ static void set_ref(struct hantro_ctx *ctx) - } - } - --static void set_buffers(struct hantro_ctx *ctx) -+static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) - { - const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; -- struct vb2_v4l2_buffer *src_buf, *dst_buf; -+ struct vb2_v4l2_buffer *dst_buf; - struct hantro_dev *vpu = ctx->dev; - dma_addr_t src_dma, dst_dma; - size_t offset = 0; - -- src_buf = hantro_get_src_buf(ctx); -- dst_buf = hantro_get_dst_buf(ctx); -- - /* Source (stream) buffer. */ - src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); - vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR); - - /* Destination (decoded frame) buffer. */ -+ dst_buf = hantro_get_dst_buf(ctx); - dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); - /* Adjust dma addr to start at second line for bottom field */ - if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) -@@ -276,6 +273,7 @@ static void set_buffers(struct hantro_ctx *ctx) - int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *src_buf; - int ret; - - /* Prepare the H264 decoder context. */ -@@ -284,9 +282,10 @@ int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) - return ret; - - /* Configure hardware registers. */ -- set_params(ctx); -+ src_buf = hantro_get_src_buf(ctx); -+ set_params(ctx, src_buf); - set_ref(ctx); -- set_buffers(ctx); -+ set_buffers(ctx, src_buf); - - hantro_end_prepare_run(ctx); - -diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c -index 2afd5996d75f..6180b23e7d94 100644 ---- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c -+++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c -@@ -367,13 +367,12 @@ static void cfg_tap(struct hantro_ctx *ctx, - } - - static void cfg_ref(struct hantro_ctx *ctx, -- const struct v4l2_ctrl_vp8_frame *hdr) -+ const struct v4l2_ctrl_vp8_frame *hdr, -+ struct vb2_v4l2_buffer *vb2_dst) - { - struct hantro_dev *vpu = ctx->dev; -- struct vb2_v4l2_buffer *vb2_dst; - dma_addr_t ref; - -- vb2_dst = hantro_get_dst_buf(ctx); - - ref = hantro_get_ref(ctx, hdr->last_frame_ts); - if (!ref) { -@@ -405,16 +404,14 @@ static void cfg_ref(struct hantro_ctx *ctx, - } - - static void cfg_buffers(struct hantro_ctx *ctx, -- const struct v4l2_ctrl_vp8_frame *hdr) -+ const struct v4l2_ctrl_vp8_frame *hdr, -+ struct vb2_v4l2_buffer *vb2_dst) - { - const struct v4l2_vp8_segment *seg = &hdr->segment; - struct hantro_dev *vpu = ctx->dev; -- struct vb2_v4l2_buffer *vb2_dst; - dma_addr_t dst_dma; - u32 reg; - -- vb2_dst = hantro_get_dst_buf(ctx); -- - /* Set probability table buffer address */ - vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, - G1_REG_ADDR_QTABLE); -@@ -436,6 +433,7 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) - { - const struct v4l2_ctrl_vp8_frame *hdr; - struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *vb2_dst; - size_t height = ctx->dst_fmt.height; - size_t width = ctx->dst_fmt.width; - u32 mb_width, mb_height; -@@ -499,8 +497,10 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) - cfg_qp(ctx, hdr); - cfg_parts(ctx, hdr); - cfg_tap(ctx, hdr); -- cfg_ref(ctx, hdr); -- cfg_buffers(ctx, hdr); -+ -+ vb2_dst = hantro_get_dst_buf(ctx); -+ cfg_ref(ctx, hdr, vb2_dst); -+ cfg_buffers(ctx, hdr, vb2_dst); - - hantro_end_prepare_run(ctx); - -diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c -index 704607511b57..d079075448c9 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c -+++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c -@@ -444,14 +444,12 @@ static void cfg_tap(struct hantro_ctx *ctx, - } - - static void cfg_ref(struct hantro_ctx *ctx, -- const struct v4l2_ctrl_vp8_frame *hdr) -+ const struct v4l2_ctrl_vp8_frame *hdr, -+ struct vb2_v4l2_buffer *vb2_dst) - { - struct hantro_dev *vpu = ctx->dev; -- struct vb2_v4l2_buffer *vb2_dst; - dma_addr_t ref; - -- vb2_dst = hantro_get_dst_buf(ctx); -- - ref = hantro_get_ref(ctx, hdr->last_frame_ts); - if (!ref) { - vpu_debug(0, "failed to find last frame ts=%llu\n", -@@ -482,16 +480,14 @@ static void cfg_ref(struct hantro_ctx *ctx, - } - - static void cfg_buffers(struct hantro_ctx *ctx, -- const struct v4l2_ctrl_vp8_frame *hdr) -+ const struct v4l2_ctrl_vp8_frame *hdr, -+ struct vb2_v4l2_buffer *vb2_dst) - { - const struct v4l2_vp8_segment *seg = &hdr->segment; - struct hantro_dev *vpu = ctx->dev; -- struct vb2_v4l2_buffer *vb2_dst; - dma_addr_t dst_dma; - u32 reg; - -- vb2_dst = hantro_get_dst_buf(ctx); -- - /* Set probability table buffer address */ - vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, - VDPU_REG_ADDR_QTABLE); -@@ -514,6 +510,7 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) - { - const struct v4l2_ctrl_vp8_frame *hdr; - struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *vb2_dst; - size_t height = ctx->dst_fmt.height; - size_t width = ctx->dst_fmt.width; - u32 mb_width, mb_height; -@@ -590,8 +587,10 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) - cfg_qp(ctx, hdr); - cfg_parts(ctx, hdr); - cfg_tap(ctx, hdr); -- cfg_ref(ctx, hdr); -- cfg_buffers(ctx, hdr); -+ -+ vb2_dst = hantro_get_dst_buf(ctx); -+ cfg_ref(ctx, hdr, vb2_dst); -+ cfg_buffers(ctx, hdr, vb2_dst); - - hantro_end_prepare_run(ctx); - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Mon, 19 Jul 2021 22:52:36 +0200 -Subject: [PATCH] media: hantro: h264: Move DPB valid and long-term bitmaps - -In order to reuse these bitmaps, move this process to -struct hantro_h264_dec_hw_ctx. This will be used by -the Rockchip VDPU2 H.264 driver. - -This idea was originally proposed by Jonas Karlman -in "[RFC 08/12] media: hantro: Fix H264 decoding of field encoded content" -which was posted a while ago. - -Link: https://lore.kernel.org/linux-media/HE1PR06MB4011EA39133818A85768B91FACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ - -Signed-off-by: Ezequiel Garcia -Tested-by: Alex Bee -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++--------------- - drivers/staging/media/hantro/hantro_h264.c | 13 +++++++++++++ - drivers/staging/media/hantro/hantro_hw.h | 4 ++++ - 3 files changed, 19 insertions(+), 15 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -index 2aa37baad0c3..6faacfc44c7c 100644 ---- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c -+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -@@ -129,25 +129,12 @@ static void set_ref(struct hantro_ctx *ctx) - struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; - const u8 *b0_reflist, *b1_reflist, *p_reflist; - struct hantro_dev *vpu = ctx->dev; -- u32 dpb_longterm = 0; -- u32 dpb_valid = 0; - int reg_num; - u32 reg; - int i; - -- /* -- * Set up bit maps of valid and long term DPBs. -- * NOTE: The bits are reversed, i.e. MSb is DPB 0. -- */ -- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) -- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -- -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -- } -- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF); -- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF); -+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); -+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); - - /* - * Set up reference frame picture numbers. -diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index ed6eaf11d96f..6d72136760e7 100644 ---- a/drivers/staging/media/hantro/hantro_h264.c -+++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -229,12 +229,25 @@ static void prepare_table(struct hantro_ctx *ctx) - const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; - struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; - const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; -+ u32 dpb_longterm = 0; -+ u32 dpb_valid = 0; - int i; - - for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { - tbl->poc[i * 2] = dpb[i].top_field_order_cnt; - tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; -+ -+ /* -+ * Set up bit maps of valid and long term DPBs. -+ * NOTE: The bits are reversed, i.e. MSb is DPB 0. -+ */ -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) -+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); - } -+ ctx->h264_dec.dpb_valid = dpb_valid << 16; -+ ctx->h264_dec.dpb_longterm = dpb_longterm << 16; - - tbl->poc[32] = dec_param->top_field_order_cnt; - tbl->poc[33] = dec_param->bottom_field_order_cnt; -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 5dcf65805396..ce678fedaad6 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -89,12 +89,16 @@ struct hantro_h264_dec_reflists { - * @dpb: DPB - * @reflists: P/B0/B1 reflists - * @ctrls: V4L2 controls attached to a run -+ * @dpb_longterm: DPB long-term -+ * @dpb_valid: DPB valid - */ - struct hantro_h264_dec_hw_ctx { - struct hantro_aux_buf priv; - struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; - struct hantro_h264_dec_reflists reflists; - struct hantro_h264_dec_ctrls ctrls; -+ u32 dpb_longterm; -+ u32 dpb_valid; - }; - - /** - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Mon, 19 Jul 2021 22:52:37 +0200 -Subject: [PATCH] media: hantro: h264: Move reference picture number to a - helper - -Add a hantro_h264_get_ref_nbr() helper function to get the reference -picture numbers. This will be used by the Rockchip VDPU2 H.264 driver. - -This idea was originally proposed by Jonas Karlman in -"[RFC 09/12] media: hantro: Refactor G1 H264 code" -posted a while ago. - -Link: https://lore.kernel.org/linux-media/HE1PR06MB401165F2BA0AD8A634FDFAF2ACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ - -Signed-off-by: Ezequiel Garcia -Tested-by: Alex Bee -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/hantro_g1_h264_dec.c | 14 ++------------ - drivers/staging/media/hantro/hantro_h264.c | 11 +++++++++++ - drivers/staging/media/hantro/hantro_hw.h | 2 ++ - 3 files changed, 15 insertions(+), 12 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -index 6faacfc44c7c..236ce24ca00c 100644 ---- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c -+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -@@ -126,7 +126,6 @@ static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) - - static void set_ref(struct hantro_ctx *ctx) - { -- struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; - const u8 *b0_reflist, *b1_reflist, *p_reflist; - struct hantro_dev *vpu = ctx->dev; - int reg_num; -@@ -143,17 +142,8 @@ static void set_ref(struct hantro_ctx *ctx) - * subsequential reference pictures. - */ - for (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) { -- reg = 0; -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -- reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num); -- else -- reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num); -- -- if (dpb[i + 1].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -- reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num); -- else -- reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num); -- -+ reg = G1_REG_REF_PIC_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, i)) | -+ G1_REG_REF_PIC_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, i + 1)); - vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2)); - } - -diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index 6d72136760e7..0b4d2491be3b 100644 ---- a/drivers/staging/media/hantro/hantro_h264.c -+++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -348,6 +348,17 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, - return dma_addr; - } - -+u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) -+{ -+ const struct v4l2_h264_dpb_entry *dpb = &ctx->h264_dec.dpb[dpb_idx]; -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ return 0; -+ if (dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -+ return dpb->pic_num; -+ return dpb->frame_num; -+} -+ - int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) - { - struct hantro_h264_dec_hw_ctx *h264_ctx = &ctx->h264_dec; -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index ce678fedaad6..7a8048afe357 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -238,6 +238,8 @@ void hantro_jpeg_enc_done(struct hantro_ctx *ctx); - - dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, - unsigned int dpb_idx); -+u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, -+ unsigned int dpb_idx); - int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); - int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); - int hantro_h264_dec_init(struct hantro_ctx *ctx); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 19 Jul 2021 22:52:38 +0200 -Subject: [PATCH] media: hantro: Add H.264 support for Rockchip VDPU2 - -Rockchip VDPU2 core is present on RK3328, RK3326/PX30, RK3399 -and others. It's similar to Hantro G1, but it's not compatible with it. - -Signed-off-by: Jonas Karlman -Signed-off-by: Ezequiel Garcia -Tested-by: Alex Bee -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/Makefile | 1 + - drivers/staging/media/hantro/hantro_hw.h | 1 + - .../media/hantro/rockchip_vpu2_hw_h264_dec.c | 491 ++++++++++++++++++ - 3 files changed, 493 insertions(+) - create mode 100644 drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c - -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index 287370188d2a..90036831fec4 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -13,6 +13,7 @@ hantro-vpu-y += \ - hantro_g2_hevc_dec.o \ - hantro_g1_vp8_dec.o \ - rockchip_vpu2_hw_jpeg_enc.o \ -+ rockchip_vpu2_hw_h264_dec.o \ - rockchip_vpu2_hw_mpeg2_dec.o \ - rockchip_vpu2_hw_vp8_dec.o \ - hantro_jpeg.o \ -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 7a8048afe357..9296624654a6 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -241,6 +241,7 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, - u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, - unsigned int dpb_idx); - int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); -+int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx); - int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); - int hantro_h264_dec_init(struct hantro_ctx *ctx); - void hantro_h264_dec_exit(struct hantro_ctx *ctx); -diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c -new file mode 100644 -index 000000000000..64a6330475eb ---- /dev/null -+++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c -@@ -0,0 +1,491 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VPU codec driver -+ * -+ * Copyright (c) 2014 Rockchip Electronics Co., Ltd. -+ * Hertz Wong -+ * Herman Chen -+ * -+ * Copyright (C) 2014 Google, Inc. -+ * Tomasz Figa -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "hantro_hw.h" -+#include "hantro_v4l2.h" -+ -+#define VDPU_SWREG(nr) ((nr) * 4) -+ -+#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63) -+#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64) -+#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61) -+#define VDPU_REG_DIR_MV_BASE VDPU_SWREG(62) -+#define VDPU_REG_REFER_BASE(i) (VDPU_SWREG(84 + (i))) -+#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) -+ -+#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) -+#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) -+#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) -+#define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) -+#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) -+ -+#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) -+#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) -+ -+#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) -+#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) -+#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) -+ -+#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0)) -+ -+#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0) -+#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0) -+#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0) -+#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) -+#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) -+#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) -+ -+#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0) -+#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16)) -+#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8)) -+#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0)) -+ -+#define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0) -+#define VDPU_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(21) : 0) -+#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) -+#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0) -+#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0) -+#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0) -+#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0) -+#define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0) -+#define VDPU_REG_PICORD_COUNT_E(v) ((v) ? BIT(6) : 0) -+#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0) -+#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0) -+ -+#define VDPU_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22)) -+#define VDPU_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12)) -+#define VDPU_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2)) -+ -+#define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0) -+ -+#define VDPU_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25)) -+#define VDPU_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20)) -+#define VDPU_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25)) -+#define VDPU_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20)) -+#define VDPU_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16)) -+#define VDPU_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_BINIT_RLIST_F5(v) (((v) << 25) & GENMASK(29, 25)) -+#define VDPU_REG_BINIT_RLIST_F4(v) (((v) << 20) & GENMASK(24, 20)) -+#define VDPU_REG_BINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_BINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_BINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_BINIT_RLIST_F11(v) (((v) << 25) & GENMASK(29, 25)) -+#define VDPU_REG_BINIT_RLIST_F10(v) (((v) << 20) & GENMASK(24, 20)) -+#define VDPU_REG_BINIT_RLIST_F9(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_BINIT_RLIST_F8(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_BINIT_RLIST_F7(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_BINIT_RLIST_F15(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_BINIT_RLIST_F14(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_BINIT_RLIST_F13(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25)) -+#define VDPU_REG_BINIT_RLIST_B4(v) (((v) << 20) & GENMASK(24, 20)) -+#define VDPU_REG_BINIT_RLIST_B3(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_BINIT_RLIST_B2(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_BINIT_RLIST_B1(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_BINIT_RLIST_B0(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25)) -+#define VDPU_REG_BINIT_RLIST_B10(v) (((v) << 20) & GENMASK(24, 20)) -+#define VDPU_REG_BINIT_RLIST_B9(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_BINIT_RLIST_B8(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_BINIT_RLIST_B7(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_BINIT_RLIST_B6(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_BINIT_RLIST_B15(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_BINIT_RLIST_B14(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_BINIT_RLIST_B13(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_BINIT_RLIST_B12(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_PINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) -+#define VDPU_REG_PINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) -+#define VDPU_REG_PINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) -+#define VDPU_REG_PINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0)) -+ -+#define VDPU_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0)) -+ -+#define VDPU_REG_STRM_START_BIT(v) (((v) << 0) & GENMASK(5, 0)) -+ -+#define VDPU_REG_CH_QP_OFFSET2(v) (((v) << 22) & GENMASK(26, 22)) -+#define VDPU_REG_CH_QP_OFFSET(v) (((v) << 17) & GENMASK(21, 17)) -+#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 9) & GENMASK(16, 9)) -+#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 0) & GENMASK(8, 0)) -+ -+#define VDPU_REG_WEIGHT_BIPR_IDC(v) (((v) << 16) & GENMASK(17, 16)) -+#define VDPU_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0)) -+ -+#define VDPU_REG_FILT_CTRL_PRES(v) ((v) ? BIT(31) : 0) -+#define VDPU_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(30) : 0) -+#define VDPU_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16)) -+#define VDPU_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_REFPIC_MK_LEN(v) (((v) << 16) & GENMASK(26, 16)) -+#define VDPU_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0)) -+ -+#define VDPU_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24)) -+#define VDPU_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19)) -+#define VDPU_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14)) -+#define VDPU_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0)) -+ -+#define VDPU_REG_IDR_PIC_E(v) ((v) ? BIT(8) : 0) -+#define VDPU_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(7) : 0) -+#define VDPU_REG_BLACKWHITE_E(v) ((v) ? BIT(6) : 0) -+#define VDPU_REG_CABAC_E(v) ((v) ? BIT(5) : 0) -+#define VDPU_REG_WEIGHT_PRED_E(v) ((v) ? BIT(4) : 0) -+#define VDPU_REG_CONST_INTRA_E(v) ((v) ? BIT(3) : 0) -+#define VDPU_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(2) : 0) -+#define VDPU_REG_TYPE1_QUANT_E(v) ((v) ? BIT(1) : 0) -+#define VDPU_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0) -+ -+static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) -+{ -+ const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; -+ const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; -+ const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; -+ const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; -+ struct hantro_dev *vpu = ctx->dev; -+ u32 reg; -+ -+ reg = VDPU_REG_DEC_ADV_PRE_DIS(0) | -+ VDPU_REG_DEC_SCMD_DIS(0) | -+ VDPU_REG_FILTERING_DIS(0) | -+ VDPU_REG_PIC_FIXED_QUANT(0) | -+ VDPU_REG_DEC_LATENCY(0); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); -+ -+ reg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) | -+ VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); -+ -+ reg = VDPU_REG_APF_THRESHOLD(8) | -+ VDPU_REG_STARTMB_X(0) | -+ VDPU_REG_STARTMB_Y(0); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); -+ -+ reg = VDPU_REG_DEC_MODE(0); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); -+ -+ reg = VDPU_REG_DEC_STRENDIAN_E(1) | -+ VDPU_REG_DEC_STRSWAP32_E(1) | -+ VDPU_REG_DEC_OUTSWAP32_E(1) | -+ VDPU_REG_DEC_INSWAP32_E(1) | -+ VDPU_REG_DEC_OUT_ENDIAN(1) | -+ VDPU_REG_DEC_IN_ENDIAN(0); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); -+ -+ reg = VDPU_REG_DEC_DATA_DISC_E(0) | -+ VDPU_REG_DEC_MAX_BURST(16) | -+ VDPU_REG_DEC_AXI_WR_ID(0) | -+ VDPU_REG_DEC_AXI_RD_ID(0xff); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); -+ -+ reg = VDPU_REG_START_CODE_E(1) | -+ VDPU_REG_CH_8PIX_ILEAV_E(0) | -+ VDPU_REG_RLC_MODE_E(0) | -+ VDPU_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && -+ (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || -+ dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) | -+ VDPU_REG_PIC_FIELDMODE_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) | -+ VDPU_REG_PIC_TOPFIELD_E(!(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)) | -+ VDPU_REG_WRITE_MVS_E((sps->profile_idc > 66) && dec_param->nal_ref_idc) | -+ VDPU_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) | -+ VDPU_REG_PICORD_COUNT_E(sps->profile_idc > 66) | -+ VDPU_REG_DEC_TIMEOUT_E(1) | -+ VDPU_REG_DEC_CLK_GATE_E(1); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); -+ -+ reg = VDPU_REG_PRED_BC_TAP_0_0(1) | -+ VDPU_REG_PRED_BC_TAP_0_1((u32)-5) | -+ VDPU_REG_PRED_BC_TAP_0_2(20); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); -+ -+ reg = VDPU_REG_REFBU_E(0); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); -+ -+ reg = VDPU_REG_STRM_START_BIT(0); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109)); -+ -+ reg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) | -+ VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) | -+ VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) | -+ VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110)); -+ -+ reg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) | -+ VDPU_REG_REF_FRAMES(sps->max_num_ref_frames); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111)); -+ -+ reg = VDPU_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) | -+ VDPU_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) | -+ VDPU_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | -+ VDPU_REG_FRAMENUM(dec_param->frame_num); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112)); -+ -+ reg = VDPU_REG_REFPIC_MK_LEN(dec_param->dec_ref_pic_marking_bit_size) | -+ VDPU_REG_IDR_PIC_ID(dec_param->idr_pic_id); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113)); -+ -+ reg = VDPU_REG_PPS_ID(pps->pic_parameter_set_id) | -+ VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | -+ VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | -+ VDPU_REG_POC_LENGTH(dec_param->pic_order_cnt_bit_size); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114)); -+ -+ reg = VDPU_REG_IDR_PIC_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) | -+ VDPU_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) | -+ VDPU_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) | -+ VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) | -+ VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) | -+ VDPU_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) | -+ VDPU_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) | -+ VDPU_REG_TYPE1_QUANT_E(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) | -+ VDPU_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115)); -+} -+ -+static void set_ref(struct hantro_ctx *ctx) -+{ -+ const u8 *b0_reflist, *b1_reflist, *p_reflist; -+ struct hantro_dev *vpu = ctx->dev; -+ u32 reg; -+ int i; -+ -+ b0_reflist = ctx->h264_dec.reflists.b0; -+ b1_reflist = ctx->h264_dec.reflists.b1; -+ p_reflist = ctx->h264_dec.reflists.p; -+ -+ reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9]) | -+ VDPU_REG_PINIT_RLIST_F8(p_reflist[8]) | -+ VDPU_REG_PINIT_RLIST_F7(p_reflist[7]) | -+ VDPU_REG_PINIT_RLIST_F6(p_reflist[6]) | -+ VDPU_REG_PINIT_RLIST_F5(p_reflist[5]) | -+ VDPU_REG_PINIT_RLIST_F4(p_reflist[4]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74)); -+ -+ reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15]) | -+ VDPU_REG_PINIT_RLIST_F14(p_reflist[14]) | -+ VDPU_REG_PINIT_RLIST_F13(p_reflist[13]) | -+ VDPU_REG_PINIT_RLIST_F12(p_reflist[12]) | -+ VDPU_REG_PINIT_RLIST_F11(p_reflist[11]) | -+ VDPU_REG_PINIT_RLIST_F10(p_reflist[10]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75)); -+ -+ reg = VDPU_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) | -+ VDPU_REG_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, 0)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76)); -+ -+ reg = VDPU_REG_REFER3_NBR(hantro_h264_get_ref_nbr(ctx, 3)) | -+ VDPU_REG_REFER2_NBR(hantro_h264_get_ref_nbr(ctx, 2)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77)); -+ -+ reg = VDPU_REG_REFER5_NBR(hantro_h264_get_ref_nbr(ctx, 5)) | -+ VDPU_REG_REFER4_NBR(hantro_h264_get_ref_nbr(ctx, 4)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78)); -+ -+ reg = VDPU_REG_REFER7_NBR(hantro_h264_get_ref_nbr(ctx, 7)) | -+ VDPU_REG_REFER6_NBR(hantro_h264_get_ref_nbr(ctx, 6)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79)); -+ -+ reg = VDPU_REG_REFER9_NBR(hantro_h264_get_ref_nbr(ctx, 9)) | -+ VDPU_REG_REFER8_NBR(hantro_h264_get_ref_nbr(ctx, 8)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80)); -+ -+ reg = VDPU_REG_REFER11_NBR(hantro_h264_get_ref_nbr(ctx, 11)) | -+ VDPU_REG_REFER10_NBR(hantro_h264_get_ref_nbr(ctx, 10)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81)); -+ -+ reg = VDPU_REG_REFER13_NBR(hantro_h264_get_ref_nbr(ctx, 13)) | -+ VDPU_REG_REFER12_NBR(hantro_h264_get_ref_nbr(ctx, 12)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82)); -+ -+ reg = VDPU_REG_REFER15_NBR(hantro_h264_get_ref_nbr(ctx, 15)) | -+ VDPU_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14)); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83)); -+ -+ reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5]) | -+ VDPU_REG_BINIT_RLIST_F4(b0_reflist[4]) | -+ VDPU_REG_BINIT_RLIST_F3(b0_reflist[3]) | -+ VDPU_REG_BINIT_RLIST_F2(b0_reflist[2]) | -+ VDPU_REG_BINIT_RLIST_F1(b0_reflist[1]) | -+ VDPU_REG_BINIT_RLIST_F0(b0_reflist[0]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100)); -+ -+ reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11]) | -+ VDPU_REG_BINIT_RLIST_F10(b0_reflist[10]) | -+ VDPU_REG_BINIT_RLIST_F9(b0_reflist[9]) | -+ VDPU_REG_BINIT_RLIST_F8(b0_reflist[8]) | -+ VDPU_REG_BINIT_RLIST_F7(b0_reflist[7]) | -+ VDPU_REG_BINIT_RLIST_F6(b0_reflist[6]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101)); -+ -+ reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15]) | -+ VDPU_REG_BINIT_RLIST_F14(b0_reflist[14]) | -+ VDPU_REG_BINIT_RLIST_F13(b0_reflist[13]) | -+ VDPU_REG_BINIT_RLIST_F12(b0_reflist[12]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102)); -+ -+ reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5]) | -+ VDPU_REG_BINIT_RLIST_B4(b1_reflist[4]) | -+ VDPU_REG_BINIT_RLIST_B3(b1_reflist[3]) | -+ VDPU_REG_BINIT_RLIST_B2(b1_reflist[2]) | -+ VDPU_REG_BINIT_RLIST_B1(b1_reflist[1]) | -+ VDPU_REG_BINIT_RLIST_B0(b1_reflist[0]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103)); -+ -+ reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11]) | -+ VDPU_REG_BINIT_RLIST_B10(b1_reflist[10]) | -+ VDPU_REG_BINIT_RLIST_B9(b1_reflist[9]) | -+ VDPU_REG_BINIT_RLIST_B8(b1_reflist[8]) | -+ VDPU_REG_BINIT_RLIST_B7(b1_reflist[7]) | -+ VDPU_REG_BINIT_RLIST_B6(b1_reflist[6]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104)); -+ -+ reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15]) | -+ VDPU_REG_BINIT_RLIST_B14(b1_reflist[14]) | -+ VDPU_REG_BINIT_RLIST_B13(b1_reflist[13]) | -+ VDPU_REG_BINIT_RLIST_B12(b1_reflist[12]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105)); -+ -+ reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3]) | -+ VDPU_REG_PINIT_RLIST_F2(p_reflist[2]) | -+ VDPU_REG_PINIT_RLIST_F1(p_reflist[1]) | -+ VDPU_REG_PINIT_RLIST_F0(p_reflist[0]); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106)); -+ -+ reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107)); -+ -+ reg = VDPU_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid); -+ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108)); -+ -+ /* Set up addresses of DPB buffers. */ -+ for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) { -+ dma_addr_t dma_addr = hantro_h264_get_ref_buf(ctx, i); -+ -+ vdpu_write_relaxed(vpu, dma_addr, VDPU_REG_REFER_BASE(i)); -+ } -+} -+ -+static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) -+{ -+ const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; -+ struct vb2_v4l2_buffer *dst_buf; -+ struct hantro_dev *vpu = ctx->dev; -+ dma_addr_t src_dma, dst_dma; -+ size_t offset = 0; -+ -+ /* Source (stream) buffer. */ -+ src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ vdpu_write_relaxed(vpu, src_dma, VDPU_REG_RLC_VLC_BASE); -+ -+ /* Destination (decoded frame) buffer. */ -+ dst_buf = hantro_get_dst_buf(ctx); -+ dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); -+ /* Adjust dma addr to start at second line for bottom field */ -+ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) -+ offset = ALIGN(ctx->src_fmt.width, MB_DIM); -+ vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DEC_OUT_BASE); -+ -+ /* Higher profiles require DMV buffer appended to reference frames. */ -+ if (ctrls->sps->profile_idc > 66 && ctrls->decode->nal_ref_idc) { -+ unsigned int bytes_per_mb = 384; -+ -+ /* DMV buffer for monochrome start directly after Y-plane */ -+ if (ctrls->sps->profile_idc >= 100 && -+ ctrls->sps->chroma_format_idc == 0) -+ bytes_per_mb = 256; -+ offset = bytes_per_mb * MB_WIDTH(ctx->src_fmt.width) * -+ MB_HEIGHT(ctx->src_fmt.height); -+ -+ /* -+ * DMV buffer is split in two for field encoded frames, -+ * adjust offset for bottom field -+ */ -+ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) -+ offset += 32 * MB_WIDTH(ctx->src_fmt.width) * -+ MB_HEIGHT(ctx->src_fmt.height); -+ vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DIR_MV_BASE); -+ } -+ -+ /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ -+ vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE); -+} -+ -+int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *src_buf; -+ u32 reg; -+ int ret; -+ -+ /* Prepare the H264 decoder context. */ -+ ret = hantro_h264_dec_prepare_run(ctx); -+ if (ret) -+ return ret; -+ -+ src_buf = hantro_get_src_buf(ctx); -+ set_params(ctx, src_buf); -+ set_ref(ctx); -+ set_buffers(ctx, src_buf); -+ -+ hantro_end_prepare_run(ctx); -+ -+ /* Start decoding! */ -+ reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1); -+ vdpu_write(vpu, reg, VDPU_SWREG(57)); -+ -+ return 0; -+} - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Mon, 19 Jul 2021 22:52:39 +0200 -Subject: [PATCH] media: hantro: Enable H.264 on Rockchip VDPU2 - -Given H.264 support for VDPU2 was just added, let's enable it. -For now, this is only enabled on platform that don't have -an RKVDEC core, such as RK3328. - -Signed-off-by: Ezequiel Garcia -Tested-by: Alex Bee -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++- - 1 file changed, 25 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index 3ccc16413f42..e4e3b5e7689b 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { - .fourcc = V4L2_PIX_FMT_NV12, - .codec_mode = HANTRO_MODE_NONE, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_H264_SLICE, -+ .codec_mode = HANTRO_MODE_H264_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = 48, -+ .max_width = 1920, -+ .step_width = MB_DIM, -+ .min_height = 48, -+ .max_height = 1088, -+ .step_height = MB_DIM, -+ }, -+ }, - { - .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, - .codec_mode = HANTRO_MODE_MPEG2_DEC, -@@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { - .init = hantro_jpeg_enc_init, - .exit = hantro_jpeg_enc_exit, - }, -+ [HANTRO_MODE_H264_DEC] = { -+ .run = rockchip_vpu2_h264_dec_run, -+ .reset = rockchip_vpu2_dec_reset, -+ .init = hantro_h264_dec_init, -+ .exit = hantro_h264_dec_exit, -+ }, - [HANTRO_MODE_MPEG2_DEC] = { - .run = rockchip_vpu2_mpeg2_dec_run, - .reset = rockchip_vpu2_dec_reset, -@@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = { - "aclk", "hclk" - }; - -+/* VDPU1/VEPU1 */ -+ - const struct hantro_variant rk3036_vpu_variant = { - .dec_offset = 0x400, - .dec_fmts = rk3066_vpu_dec_fmts, -@@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = { - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; - -+/* VDPU2/VEPU2 */ -+ - const struct hantro_variant rk3328_vpu_variant = { - .dec_offset = 0x400, - .dec_fmts = rk3399_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -- .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER, -+ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | -+ HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, - .irqs = rockchip_vdpu2_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Mon, 19 Jul 2021 22:52:41 +0200 -Subject: [PATCH] media: dt-bindings: media: rockchip-vpu: Add PX30 compatible - -The Rockchip PX30 SoC has a Hantro VPU that features a decoder (VDPU2) -and an encoder (VEPU2). - -Suggested-by: Alex Bee -Signed-off-by: Paul Kocialkowski -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -index b88172a59de7..bacb60a34989 100644 ---- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -@@ -22,6 +22,7 @@ properties: - - rockchip,rk3288-vpu - - rockchip,rk3328-vpu - - rockchip,rk3399-vpu -+ - rockchip,px30-vpu - - items: - - const: rockchip,rk3188-vpu - - const: rockchip,rk3066-vpu - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Mon, 19 Jul 2021 22:52:40 +0200 -Subject: [PATCH] media: hantro: Add support for the Rockchip PX30 - -The PX30 SoC includes both the VDPU2 and VEPU2 blocks which are similar -to the RK3399 (Hantro G1/H1 with shuffled registers). - -Signed-off-by: Paul Kocialkowski -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/hantro_drv.c | 1 + - drivers/staging/media/hantro/hantro_hw.h | 1 + - drivers/staging/media/hantro/rockchip_vpu_hw.c | 17 +++++++++++++++++ - 3 files changed, 19 insertions(+) - -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 9b5415176bfe..8a2edd67f2c6 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -582,6 +582,7 @@ static const struct v4l2_file_operations hantro_fops = { - - static const struct of_device_id of_hantro_match[] = { - #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP -+ { .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, }, - { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, }, - { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, }, - { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 9296624654a6..df7b5e3a57b9 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -209,6 +209,7 @@ enum hantro_enc_fmt { - - extern const struct hantro_variant imx8mq_vpu_g2_variant; - extern const struct hantro_variant imx8mq_vpu_variant; -+extern const struct hantro_variant px30_vpu_variant; - extern const struct hantro_variant rk3036_vpu_variant; - extern const struct hantro_variant rk3066_vpu_variant; - extern const struct hantro_variant rk3288_vpu_variant; -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index e4e3b5e7689b..d4f52957cc53 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -548,3 +548,20 @@ const struct hantro_variant rk3399_vpu_variant = { - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; -+ -+const struct hantro_variant px30_vpu_variant = { -+ .enc_offset = 0x0, -+ .enc_fmts = rockchip_vpu_enc_fmts, -+ .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), -+ .dec_offset = 0x400, -+ .dec_fmts = rk3399_vpu_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | -+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, -+ .codec_ops = rk3399_vpu_codec_ops, -+ .irqs = rockchip_vpu2_irqs, -+ .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), -+ .init = rk3036_vpu_hw_init, -+ .clk_names = rockchip_vpu_clk_names, -+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -+}; diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index 6c72bcb544..e60383eaf2 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -189,56 +189,6 @@ index 53c0038c792b..0e5c4a2eecff 100644 #define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) /* -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 6 Jun 2021 10:23:13 +0200 -Subject: [PATCH] media: hevc: Add segment address field - -If HEVC frame consists of multiple slices, segment address has to be -known in order to properly decode it. - -Add segment address field to slice parameters. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 3 +++ - include/media/hevc-ctrls.h | 3 ++- - 2 files changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index dc08368d62fe..9b25674fcd40 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -3000,6 +3000,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - * - __u8 - - ``pic_struct`` - - -+ * - __u32 -+ - ``slice_segment_addr`` -+ - - * - __u8 - - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` - - The list of L0 reference elements as indices in the DPB. -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 0e5c4a2eecff..ef63bc205756 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -198,10 +198,11 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 pic_struct; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -- __u8 padding[5]; -+ __u8 padding; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 23 May 2020 15:03:46 +0000 diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf index 95ef669423..4646664cfa 100644 --- a/projects/Samsung/linux/linux.arm.conf +++ b/projects/Samsung/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.14.5 Kernel Configuration +# Linux/arm 5.15.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -24,6 +24,7 @@ CONFIG_BUILDTIME_TABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -137,6 +138,7 @@ CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set CONFIG_GENERIC_SCHED_CLOCK=y # @@ -201,12 +203,12 @@ CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -257,7 +259,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -600,20 +601,6 @@ CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options -# -# Firmware Drivers -# -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_TRUSTED_FOUNDATIONS is not set -# CONFIG_GOOGLE_FIRMWARE is not set -CONFIG_HAVE_ARM_SMCCC=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA1_ARM_NEON=m @@ -637,7 +624,6 @@ CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # -CONFIG_SET_FS=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_UPROBES=y @@ -647,6 +633,7 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y @@ -729,12 +716,10 @@ CONFIG_MODULE_COMPRESS_NONE=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set -# CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set @@ -766,6 +751,7 @@ CONFIG_EFI_PARTITION=y # end of Partition Types CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y # # IO Schedulers @@ -830,6 +816,12 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y @@ -842,6 +834,7 @@ CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -901,6 +894,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -1005,6 +999,7 @@ CONFIG_BT_ATH3K=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -1102,12 +1097,33 @@ CONFIG_ARM_CCI400_COMMON=y CONFIG_ARM_CCI400_PORT_CTRL=y # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set -# CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_TRUSTED_FOUNDATIONS is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_HAVE_ARM_SMCCC=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + # CONFIG_GNSS is not set # CONFIG_MTD is not set CONFIG_DTC=y @@ -1203,6 +1219,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set @@ -1214,6 +1231,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y # CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -1251,7 +1269,6 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_THIN_PROVISIONING is not set # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set -# CONFIG_DM_EBS is not set # CONFIG_DM_ERA is not set # CONFIG_DM_CLONE is not set # CONFIG_DM_MIRROR is not set @@ -1313,6 +1330,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set @@ -1363,6 +1381,7 @@ CONFIG_AX88796B_PHY=y # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MICREL_PHY is not set CONFIG_MICROCHIP_PHY=m @@ -1579,7 +1598,6 @@ CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_NETDEVSIM is not set # CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set -# CONFIG_NVM is not set # # Input device support @@ -1853,9 +1871,8 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -# end of Character devices - # CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices # # I2C support @@ -1918,6 +1935,7 @@ CONFIG_I2C_S3C2410=y # # Other I2C/SMBus bus drivers # +# CONFIG_I2C_VIRTIO is not set # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set @@ -1978,6 +1996,7 @@ CONFIG_SPI_DYNAMIC=y # PTP clock support # # CONFIG_PTP_1588_CLOCK is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -2159,6 +2178,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set @@ -2243,6 +2263,7 @@ CONFIG_SENSORS_NTC_THERMISTOR=y # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=y # CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2473,6 +2494,8 @@ CONFIG_MFD_WM8994=y # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set # end of Multifunction device drivers CONFIG_REGULATOR=y @@ -2527,7 +2550,9 @@ CONFIG_REGULATOR_MAX77802=y # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y @@ -2787,7 +2812,9 @@ CONFIG_VIDEOBUF2_VMALLOC=m # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set # CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set @@ -2808,6 +2835,7 @@ CONFIG_VIDEOBUF2_VMALLOC=m # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set # CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -2872,6 +2900,7 @@ CONFIG_VIDEO_S5C73M3=m # CONFIG_IMX_IPUV3_CORE is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_DP_AUX_BUS=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set @@ -2953,6 +2982,7 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set @@ -2975,6 +3005,8 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y @@ -2997,6 +3029,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # end of Display Panels @@ -3305,6 +3338,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set CONFIG_SND_SOC_MAX98090=y @@ -3797,9 +3831,7 @@ CONFIG_LEDS_CLASS_FLASH=y # # LED drivers # -CONFIG_LEDS_AAT1290=y # CONFIG_LEDS_AN30259A is not set -# CONFIG_LEDS_AS3645A is not set # CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set @@ -3809,7 +3841,6 @@ CONFIG_LEDS_AAT1290=y # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_LM3692X is not set -# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set @@ -3826,10 +3857,8 @@ CONFIG_LEDS_PWM=y # CONFIG_LEDS_LT3593 is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set -CONFIG_LEDS_MAX77693=y CONFIG_LEDS_MAX8997=y # CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_KTD2692 is not set # CONFIG_LEDS_IS31FL319X is not set # CONFIG_LEDS_IS31FL32XX is not set @@ -3842,13 +3871,18 @@ CONFIG_LEDS_MAX8997=y # CONFIG_LEDS_USER is not set # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_SGM3140 is not set # # Flash and Torch LED drivers # +CONFIG_LEDS_AAT1290=y +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_LM3601X is not set +CONFIG_LEDS_MAX77693=y # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set # # LED Triggers @@ -4033,6 +4067,7 @@ CONFIG_UDMABUF=y # CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options @@ -4196,6 +4231,8 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_EXYNOS_IOMMU=y @@ -4455,6 +4492,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_IAQCORE is not set # CONFIG_SCD30_CORE is not set # CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -4696,6 +4734,7 @@ CONFIG_AK8975=y # # Digital potentiometers # +# CONFIG_AD5110 is not set # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set # CONFIG_MAX5432 is not set @@ -4915,11 +4954,11 @@ CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y @@ -4945,9 +4984,7 @@ CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -4972,6 +5009,9 @@ CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" # CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5062,7 +5102,6 @@ CONFIG_SUNRPC_SWAP=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set CONFIG_CIFS_DEBUG=y @@ -5072,6 +5111,8 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -5326,7 +5367,7 @@ CONFIG_CRYPTO_HASH_INFO=y # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_LIB_BLAKE2S=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y @@ -5663,7 +5704,6 @@ CONFIG_RCU_TRACE=y # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set CONFIG_NOP_TRACER=y @@ -5741,7 +5781,6 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set