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linux: add patch to fix buffer-alignment regression with Nvidia HDMI, this should fix #152
Signed-off-by: Stephan Raue <stephan@openelec.tv>
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From 52409aa6a0e96337da137c069856298f4dd825a0 Mon Sep 17 00:00:00 2001
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From: Takashi Iwai <tiwai@suse.de>
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Date: Mon, 23 Jan 2012 17:10:24 +0100
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Subject: [PATCH] ALSA: hda - Fix buffer-alignment regression with Nvidia HDMI
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The commit 2ae66c26550cd94b0e2606a9275eb0ab7070ad0e
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ALSA: hda: option to enable arbitrary buffer/period sizes
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introduced a regression on machines with Intel controller and Nvidia
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HDMI. The reason is that the driver modifies the global variable
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align_buffer_size when an Intel controller is found, and the Nvidia
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HDMI controller is probed after Intel although Nvidia chips require
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the aligned buffers.
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This patch fixes the problem by moving the flag into the local struct
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so that it's not affected by other controllers.
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Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=42567
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Cc: <stable@kernel.org>
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Signed-off-by: Takashi Iwai <tiwai@suse.de>
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---
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sound/pci/hda/hda_intel.c | 6 ++++--
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1 files changed, 4 insertions(+), 2 deletions(-)
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diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
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index fb35474..95dfb68 100644
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--- a/sound/pci/hda/hda_intel.c
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+++ b/sound/pci/hda/hda_intel.c
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@@ -469,6 +469,7 @@ struct azx {
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unsigned int irq_pending_warned :1;
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unsigned int probing :1; /* codec probing phase */
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unsigned int snoop:1;
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+ unsigned int align_buffer_size:1;
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/* for debugging */
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unsigned int last_cmd[AZX_MAX_CODECS];
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@@ -1690,7 +1691,7 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
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runtime->hw.rates = hinfo->rates;
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snd_pcm_limit_hw_rates(runtime);
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snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
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- if (align_buffer_size)
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+ if (chip->align_buffer_size)
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/* constrain buffer sizes to be multiple of 128
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bytes. This is more efficient in terms of memory
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access but isn't required by the HDA spec and
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@@ -2773,8 +2774,9 @@ static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
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}
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/* disable buffer size rounding to 128-byte multiples if supported */
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+ chip->align_buffer_size = align_buffer_size;
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if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
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- align_buffer_size = 0;
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+ chip->align_buffer_size = 0;
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/* allow 64bit DMA address if supported by H/W */
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if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
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--
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1.7.8.3
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