mirror of
https://github.com/LibreELEC/LibreELEC.tv.git
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Merge pull request #4491 from jernejsk/fixes
Allwinner: DRM and VPU driver fixes
This commit is contained in:
Christian Hewitt
GitHub
commit
bff4206e6a
@ -1439,3 +1439,110 @@ index 05050c0a0921..d42e4ebf6cad 100644
|
||||
--
|
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2.25.1
|
||||
|
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From 19c227cb73d6cd040341987d25cf1ad23e1454a2 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Tue, 21 Jul 2020 21:53:27 +0200
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Subject: [PATCH] media: cedrus: add check for H264 and HEVC limitations
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||||
|
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
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---
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drivers/staging/media/sunxi/cedrus/cedrus.c | 49 ++++++++++++++++++++-
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drivers/staging/media/sunxi/cedrus/cedrus.h | 1 +
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2 files changed, 49 insertions(+), 1 deletion(-)
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
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index e6b864f05364..c3101c0225d6 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
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@@ -28,6 +28,50 @@
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#include "cedrus_dec.h"
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#include "cedrus_hw.h"
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+static int cedrus_try_ctrl(struct v4l2_ctrl *ctrl)
|
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+{
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+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS) {
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+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
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+
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+ if (sps->chroma_format_idc != 1)
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+ /* Only 4:2:0 is supported */
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+ return -EINVAL;
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+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
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+ /* Luma and chroma bit depth mismatch */
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+ return -EINVAL;
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+ if (sps->bit_depth_luma_minus8 != 0)
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+ /* Only 8-bit is supported */
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+ return -EINVAL;
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+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
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+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
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+ struct cedrus_ctx *ctx = container_of(ctrl->handler, struct cedrus_ctx, hdl);
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+
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+ if (sps->chroma_format_idc != 1)
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+ /* Only 4:2:0 is supported */
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+ return -EINVAL;
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+
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+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
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+ /* Luma and chroma bit depth mismatch */
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+ return -EINVAL;
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+
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+ if (ctx->dev->capabilities & CEDRUS_CAPABILITY_H265_10_DEC) {
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+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
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+ /* Only 8-bit and 10-bit are supported */
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+ return -EINVAL;
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+ } else {
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+ if (sps->bit_depth_luma_minus8 != 0)
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+ /* Only 8-bit is supported */
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+ return -EINVAL;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct v4l2_ctrl_ops cedrus_ctrl_ops = {
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+ .try_ctrl = cedrus_try_ctrl,
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+};
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+
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static const struct cedrus_control cedrus_controls[] = {
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{
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.cfg = {
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@@ -60,6 +104,7 @@ static const struct cedrus_control cedrus_controls[] = {
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{
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.cfg = {
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.id = V4L2_CID_MPEG_VIDEO_H264_SPS,
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+ .ops = &cedrus_ctrl_ops,
|
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},
|
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.codec = CEDRUS_CODEC_H264,
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.required = true,
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@@ -99,6 +144,7 @@ static const struct cedrus_control cedrus_controls[] = {
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{
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.cfg = {
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.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
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+ .ops = &cedrus_ctrl_ops,
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},
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.codec = CEDRUS_CODEC_H265,
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.required = true,
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@@ -525,7 +571,8 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = {
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static const struct cedrus_variant sun50i_h6_cedrus_variant = {
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.capabilities = CEDRUS_CAPABILITY_UNTILED |
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- CEDRUS_CAPABILITY_H265_DEC,
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+ CEDRUS_CAPABILITY_H265_DEC |
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+ CEDRUS_CAPABILITY_H265_10_DEC,
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.quirks = CEDRUS_QUIRK_NO_DMA_OFFSET,
|
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.mod_rate = 600000000,
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};
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
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index 353cb04b4ce5..b8d3a685b549 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
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@@ -28,6 +28,7 @@
|
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|
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#define CEDRUS_CAPABILITY_UNTILED BIT(0)
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#define CEDRUS_CAPABILITY_H265_DEC BIT(1)
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+#define CEDRUS_CAPABILITY_H265_10_DEC BIT(2)
|
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|
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#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0)
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--
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2.27.0
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|
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|
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389
projects/Allwinner/patches/linux/0007-drm-fixes.patch
Normal file
389
projects/Allwinner/patches/linux/0007-drm-fixes.patch
Normal file
@ -0,0 +1,389 @@
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From 8132877d34935f3d0a2c661f00f67f782b6bc8f8 Mon Sep 17 00:00:00 2001
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From: Roman Stratiienko <roman.stratiienko@globallogic.com>
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Date: Sat, 28 Dec 2019 22:28:17 +0200
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Subject: [PATCH 1/3] drm/sun4i: Reimplement plane z position setting logic
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To set blending channel order register software needs to know state and
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position of each channel, which impossible at plane commit stage.
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Move this procedure to atomic_flush stage, where all necessary information
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is available.
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Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/gpu/drm/sun4i/sun8i_mixer.c | 43 ++++++++++++++++++++++++--
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drivers/gpu/drm/sun4i/sun8i_mixer.h | 5 +++
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drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 42 ++++---------------------
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drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 39 +++--------------------
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4 files changed, 57 insertions(+), 72 deletions(-)
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diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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index cc4fb916318f..1ad704b737cf 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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@@ -250,8 +250,45 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
|
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static void sun8i_mixer_commit(struct sunxi_engine *engine)
|
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{
|
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+ struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
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+ int channel_by_zpos[SUN8I_MIXER_MAX_CHANNELS];
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+ u32 base = sun8i_blender_base(mixer);
|
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+ u32 route = 0, pipe_ctl = 0;
|
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+ unsigned int channel_count;
|
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+ int i, j;
|
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+
|
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+ channel_count = mixer->cfg->vi_num + mixer->cfg->ui_num;
|
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+
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+ DRM_DEBUG_DRIVER("Update blender routing\n");
|
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+
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+ for (i = 0; i < SUN8I_MIXER_MAX_CHANNELS; i++)
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+ channel_by_zpos[i] = -1;
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+
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+ for (i = 0; i < channel_count; i++) {
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+ int zpos = mixer->channel_zpos[i];
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+
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+ if (zpos >= 0 && zpos < channel_count)
|
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+ channel_by_zpos[zpos] = i;
|
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+ }
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+
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+ j = 0;
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+ for (i = 0; i < channel_count; i++) {
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+ int ch = channel_by_zpos[i];
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+
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+ if (ch >= 0) {
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+ pipe_ctl |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(j);
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+ route |= ch << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(j);
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+ j++;
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+ }
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+ }
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+
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+ regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
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+ SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, pipe_ctl);
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+
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+ regmap_write(mixer->engine.regs,
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+ SUN8I_MIXER_BLEND_ROUTE(base), route);
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+
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DRM_DEBUG_DRIVER("Committing changes\n");
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-
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regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
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SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
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}
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@@ -489,10 +526,12 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
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SUN8I_MIXER_BLEND_COLOR_BLACK);
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plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
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- for (i = 0; i < plane_cnt; i++)
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+ for (i = 0; i < plane_cnt; i++) {
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_MODE(base, i),
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SUN8I_MIXER_BLEND_MODE_DEF);
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+ mixer->channel_zpos[i] = -1;
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+ }
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regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
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SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
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diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
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index 7576b523fdbb..7b378d6e4dd9 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
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@@ -12,6 +12,8 @@
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#include "sunxi_engine.h"
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+#define SUN8I_MIXER_MAX_CHANNELS 5
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+
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#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
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#define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
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@@ -179,6 +181,9 @@ struct sun8i_mixer {
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struct clk *bus_clk;
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struct clk *mod_clk;
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+
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+ /* -1 means that layer is disabled */
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+ int channel_zpos[SUN8I_MIXER_MAX_CHANNELS];
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};
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static inline struct sun8i_mixer *
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diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
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index 54f937a7d5e7..651d3bf096c6 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
|
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@@ -24,12 +24,10 @@
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#include "sun8i_ui_scaler.h"
|
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static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
|
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- int overlay, bool enable, unsigned int zpos,
|
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- unsigned int old_zpos)
|
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+ int overlay, bool enable, unsigned int zpos)
|
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{
|
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- u32 val, bld_base, ch_base;
|
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+ u32 val, ch_base;
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|
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- bld_base = sun8i_blender_base(mixer);
|
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ch_base = sun8i_channel_base(mixer, channel);
|
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|
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DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
|
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@@ -44,32 +42,7 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
|
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
|
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
|
||||
|
||||
- if (!enable || zpos != old_zpos) {
|
||||
- regmap_update_bits(mixer->engine.regs,
|
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- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
|
||||
- 0);
|
||||
-
|
||||
- regmap_update_bits(mixer->engine.regs,
|
||||
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
|
||||
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
|
||||
- 0);
|
||||
- }
|
||||
-
|
||||
- if (enable) {
|
||||
- val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
|
||||
-
|
||||
- regmap_update_bits(mixer->engine.regs,
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
|
||||
- val, val);
|
||||
-
|
||||
- val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
|
||||
-
|
||||
- regmap_update_bits(mixer->engine.regs,
|
||||
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
|
||||
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
|
||||
- val);
|
||||
- }
|
||||
+ mixer->channel_zpos[channel] = enable ? zpos : -1;
|
||||
}
|
||||
|
||||
static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
|
||||
@@ -267,11 +240,9 @@ static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
|
||||
- unsigned int old_zpos = old_state->normalized_zpos;
|
||||
struct sun8i_mixer *mixer = layer->mixer;
|
||||
|
||||
- sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
|
||||
- old_zpos);
|
||||
+ sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0);
|
||||
}
|
||||
|
||||
static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
|
||||
@@ -279,12 +250,11 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
|
||||
{
|
||||
struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
|
||||
unsigned int zpos = plane->state->normalized_zpos;
|
||||
- unsigned int old_zpos = old_state->normalized_zpos;
|
||||
struct sun8i_mixer *mixer = layer->mixer;
|
||||
|
||||
if (!plane->state->visible) {
|
||||
sun8i_ui_layer_enable(mixer, layer->channel,
|
||||
- layer->overlay, false, 0, old_zpos);
|
||||
+ layer->overlay, false, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -295,7 +265,7 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
|
||||
sun8i_ui_layer_update_buffer(mixer, layer->channel,
|
||||
layer->overlay, plane);
|
||||
sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
|
||||
- true, zpos, old_zpos);
|
||||
+ true, zpos);
|
||||
}
|
||||
|
||||
static struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
|
||||
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
|
||||
index 22c8c5375d0d..bd28e76363d9 100644
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
|
||||
@@ -18,8 +18,7 @@
|
||||
#include "sun8i_vi_scaler.h"
|
||||
|
||||
static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
|
||||
- int overlay, bool enable, unsigned int zpos,
|
||||
- unsigned int old_zpos)
|
||||
+ int overlay, bool enable, unsigned int zpos)
|
||||
{
|
||||
u32 val, bld_base, ch_base;
|
||||
|
||||
@@ -38,32 +37,7 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
|
||||
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
|
||||
SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
|
||||
|
||||
- if (!enable || zpos != old_zpos) {
|
||||
- regmap_update_bits(mixer->engine.regs,
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
|
||||
- 0);
|
||||
-
|
||||
- regmap_update_bits(mixer->engine.regs,
|
||||
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
|
||||
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
|
||||
- 0);
|
||||
- }
|
||||
-
|
||||
- if (enable) {
|
||||
- val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
|
||||
-
|
||||
- regmap_update_bits(mixer->engine.regs,
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
|
||||
- val, val);
|
||||
-
|
||||
- val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
|
||||
-
|
||||
- regmap_update_bits(mixer->engine.regs,
|
||||
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
|
||||
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
|
||||
- val);
|
||||
- }
|
||||
+ mixer->channel_zpos[channel] = enable ? zpos : -1;
|
||||
}
|
||||
|
||||
static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
|
||||
@@ -370,11 +344,9 @@ static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
|
||||
- unsigned int old_zpos = old_state->normalized_zpos;
|
||||
struct sun8i_mixer *mixer = layer->mixer;
|
||||
|
||||
- sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
|
||||
- old_zpos);
|
||||
+ sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0);
|
||||
}
|
||||
|
||||
static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
|
||||
@@ -382,12 +354,11 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
|
||||
{
|
||||
struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
|
||||
unsigned int zpos = plane->state->normalized_zpos;
|
||||
- unsigned int old_zpos = old_state->normalized_zpos;
|
||||
struct sun8i_mixer *mixer = layer->mixer;
|
||||
|
||||
if (!plane->state->visible) {
|
||||
sun8i_vi_layer_enable(mixer, layer->channel,
|
||||
- layer->overlay, false, 0, old_zpos);
|
||||
+ layer->overlay, false, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -398,7 +369,7 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
|
||||
sun8i_vi_layer_update_buffer(mixer, layer->channel,
|
||||
layer->overlay, plane);
|
||||
sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
|
||||
- true, zpos, old_zpos);
|
||||
+ true, zpos);
|
||||
}
|
||||
|
||||
static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
|
||||
--
|
||||
2.27.0
|
||||
|
||||
|
||||
From 9d11b18afdb63d60714a78c5966f674aa66ee6b9 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Sun, 19 Jul 2020 11:28:49 +0200
|
||||
Subject: [PATCH 2/3] drm/sun4i: Don't use update regmap variant for blend pipe
|
||||
register
|
||||
|
||||
Readout might return invalid value, so always write it.
|
||||
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_mixer.c | 19 ++++++++-----------
|
||||
1 file changed, 8 insertions(+), 11 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
index 1ad704b737cf..8825518e06c8 100644
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
@@ -282,8 +282,14 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine)
|
||||
}
|
||||
}
|
||||
|
||||
- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, pipe_ctl);
|
||||
+ /*
|
||||
+ * Set fill color of bottom plane to black. Generally not needed
|
||||
+ * except when VI plane is at bottom (zpos = 0) and enabled.
|
||||
+ */
|
||||
+ pipe_ctl |= SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0);
|
||||
+
|
||||
+ regmap_write(mixer->engine.regs,
|
||||
+ SUN8I_MIXER_BLEND_PIPE_CTL(base), pipe_ctl);
|
||||
|
||||
regmap_write(mixer->engine.regs,
|
||||
SUN8I_MIXER_BLEND_ROUTE(base), route);
|
||||
@@ -516,12 +522,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
|
||||
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
|
||||
SUN8I_MIXER_BLEND_COLOR_BLACK);
|
||||
|
||||
- /*
|
||||
- * Set fill color of bottom plane to black. Generally not needed
|
||||
- * except when VI plane is at bottom (zpos = 0) and enabled.
|
||||
- */
|
||||
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
|
||||
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
|
||||
SUN8I_MIXER_BLEND_COLOR_BLACK);
|
||||
|
||||
@@ -533,9 +533,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
|
||||
mixer->channel_zpos[i] = -1;
|
||||
}
|
||||
|
||||
- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
|
||||
- SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
|
||||
-
|
||||
return 0;
|
||||
|
||||
err_disable_bus_clk:
|
||||
--
|
||||
2.27.0
|
||||
|
||||
|
||||
From bb41e6a8620fc7c3fd91be8155ef5972ea04c0c8 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Sun, 19 Jul 2020 11:37:41 +0200
|
||||
Subject: [PATCH 3/3] drm/sun4i: mixer: Add caching support
|
||||
|
||||
Most registers are not safe to read out so enable cache in regmap.
|
||||
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
index 8825518e06c8..006b746b0e95 100644
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
|
||||
@@ -346,11 +346,23 @@ static const struct sunxi_engine_ops sun8i_engine_ops = {
|
||||
.layers_init = sun8i_layers_init,
|
||||
};
|
||||
|
||||
+static bool sun8i_mixer_volatile_reg(struct device *dev, unsigned int reg)
|
||||
+{
|
||||
+ switch (reg) {
|
||||
+ case SUN8I_MIXER_GLOBAL_STATUS:
|
||||
+ case SUN8I_MIXER_GLOBAL_DBUFF:
|
||||
+ return true;
|
||||
+ }
|
||||
+ return false;
|
||||
+}
|
||||
+
|
||||
static struct regmap_config sun8i_mixer_regmap_config = {
|
||||
+ .cache_type = REGCACHE_FLAT,
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 0xbfffc, /* guessed */
|
||||
+ .volatile_reg = sun8i_mixer_volatile_reg,
|
||||
};
|
||||
|
||||
static int sun8i_mixer_of_get_id(struct device_node *node)
|
||||
--
|
||||
2.27.0
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user