From c01f524e803ac4b969b9936465657e26aa65b5cf Mon Sep 17 00:00:00 2001 From: MilhouseVH Date: Thu, 13 Jun 2019 14:15:11 +0100 Subject: [PATCH] linux (Allwinner): update to 5.1.9 --- .../A64/patches/linux/03-opi-win-bt.patch | 62 - .../patches/linux/01-increase-bt-speed.patch | 12 + .../devices/H6/patches/linux/03-VPU.patch | 240 -- .../patches/linux/06-10-bit-HEVC-hack.patch | 91 + .../linux/06-cedrus-increase-frequency.patch | 25 - .../linux/07-limit-max-pixel-clock.patch | 20 - .../H6/patches/linux/08-clock-fixes.patch | 96 - projects/Allwinner/linux/linux.aarch64.conf | 166 +- projects/Allwinner/linux/linux.arm.conf | 142 +- .../linux/0001-hdmi-sound-improvements.patch | 2 +- ...5.2.patch => 0002-backport-from-5.2.patch} | 313 ++ .../patches/linux/0002-fixes-from-5.1.patch | 1571 ---------- .../linux/0003-backport-from-5.3.patch | 2765 +++++++++++++++++ ...nd-Cedrus.patch => 0004-cedrus-hevc.patch} | 883 ++++-- ...dia-cedrus-Add-H264-decoding-support.patch | 1420 --------- ....patch => 0006-wip-cec-improvements.patch} | 108 +- ...us-Fix-decoding-for-some-H264-videos.patch | 76 + ...x-H264-default-reference-index-count.patch | 36 + ...-media-cedrus-WIP-H264-improvements.patch} | 43 +- ...patch => 0010-WIP-HEVC-improvements.patch} | 166 +- ...WIP-dw-hdmi-cec-sleep-100ms-on-error.patch | 62 - ...264-4k.patch => 0011-cedrus-h264-4k.patch} | 69 +- .../0018-cedrus-increase-frequency.patch | 25 - 23 files changed, 4377 insertions(+), 4016 deletions(-) delete mode 100644 projects/Allwinner/devices/A64/patches/linux/03-opi-win-bt.patch create mode 100644 projects/Allwinner/devices/H3/patches/linux/01-increase-bt-speed.patch delete mode 100644 projects/Allwinner/devices/H6/patches/linux/03-VPU.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/06-10-bit-HEVC-hack.patch delete mode 100644 projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch delete mode 100644 projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch delete mode 100644 projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch rename projects/Allwinner/patches/linux/{0003-fixes-from-5.2.patch => 0002-backport-from-5.2.patch} (65%) delete mode 100644 projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch create mode 100644 projects/Allwinner/patches/linux/0003-backport-from-5.3.patch rename projects/Allwinner/patches/linux/{0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch => 0004-cedrus-hevc.patch} (74%) delete mode 100644 projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch rename projects/Allwinner/patches/linux/{0013-cec-improvements.patch => 0006-wip-cec-improvements.patch} (65%) create mode 100644 projects/Allwinner/patches/linux/0007-media-cedrus-Fix-decoding-for-some-H264-videos.patch create mode 100644 projects/Allwinner/patches/linux/0008-media-cedrus-Fix-H264-default-reference-index-count.patch rename projects/Allwinner/patches/linux/{0007-H264-improvements.patch => 0009-media-cedrus-WIP-H264-improvements.patch} (72%) rename projects/Allwinner/patches/linux/{0008-HEVC-improvements.patch => 0010-WIP-HEVC-improvements.patch} (84%) delete mode 100644 projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch rename projects/Allwinner/patches/linux/{0009-cedrus-h264-4k.patch => 0011-cedrus-h264-4k.patch} (86%) delete mode 100644 projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch diff --git a/projects/Allwinner/devices/A64/patches/linux/03-opi-win-bt.patch b/projects/Allwinner/devices/A64/patches/linux/03-opi-win-bt.patch deleted file mode 100644 index dc6dc67d00..0000000000 --- a/projects/Allwinner/devices/A64/patches/linux/03-opi-win-bt.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 398a7c7ab82ab344d693a62ee633351f93046d91 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 11 Mar 2019 17:30:24 +0100 -Subject: [PATCH] orangepi win: wifi & bt - -Signed-off-by: Jernej Skrabec ---- - .../dts/allwinner/sun50i-a64-orangepi-win.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -index 510f661229dc..5ef3c62c765e 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -@@ -109,6 +109,8 @@ - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; - }; - }; - -@@ -170,6 +172,14 @@ - bus-width = <4>; - non-removable; - status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&r_pio>; -+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ -+ interrupt-names = "host-wake"; -+ }; - }; - - &ohci0 { -@@ -342,7 +352,20 @@ - &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; - status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <1500000>; -+ clocks = <&rtc 1>; -+ clock-names = "lpo"; -+ vbat-supply = <®_dldo2>; -+ vddio-supply = <®_dldo4>; -+ device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ -+ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ -+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ -+ }; - }; - - /* On Pi-2 connector, RTS/CTS optional */ --- -2.21.0 - diff --git a/projects/Allwinner/devices/H3/patches/linux/01-increase-bt-speed.patch b/projects/Allwinner/devices/H3/patches/linux/01-increase-bt-speed.patch new file mode 100644 index 0000000000..c96395e739 --- /dev/null +++ b/projects/Allwinner/devices/H3/patches/linux/01-increase-bt-speed.patch @@ -0,0 +1,12 @@ +diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +index 39263e74fbb5..0ec6109ec625 100644 +--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi ++++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +@@ -219,6 +219,7 @@ + + bluetooth { + compatible = "brcm,bcm43438-bt"; ++ max-speed = <1500000>; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; diff --git a/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch b/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch deleted file mode 100644 index 53eb2a0463..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch +++ /dev/null @@ -1,240 +0,0 @@ -From ed19ec00d4d62a74857ad9c2ea1dbf9671ac3580 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:36:54 +0100 -Subject: [PATCH 1/6] dt-bindings: media: cedrus: Add H6 compatible - -This adds a compatible for H6. H6 VPU supports 10-bit HEVC decoding and -additional AFBC output format for HEVC. - -Signed-off-by: Jernej Skrabec ---- - Documentation/devicetree/bindings/media/cedrus.txt | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt -index bce0705df953..20c82fb0c343 100644 ---- a/Documentation/devicetree/bindings/media/cedrus.txt -+++ b/Documentation/devicetree/bindings/media/cedrus.txt -@@ -13,6 +13,7 @@ Required properties: - - "allwinner,sun8i-h3-video-engine" - - "allwinner,sun50i-a64-video-engine" - - "allwinner,sun50i-h5-video-engine" -+ - "allwinner,sun50i-h6-video-engine" - - reg : register base and length of VE; - - clocks : list of clock specifiers, corresponding to entries in - the clock-names property; --- -2.20.1 - - -From bb6b00e1225a5b382b723d3c2190429e15a4c607 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:45:38 +0100 -Subject: [PATCH 2/6] media: cedrus: Add a quirk for not setting DMA offset - -H6 VPU doesn't work if DMA offset is set. - -Add a quirk for it. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus.h | 3 +++ - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 3 ++- - 2 files changed, 5 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 4aedd24a9848..c57c04b41d2e 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -28,6 +28,8 @@ - - #define CEDRUS_CAPABILITY_UNTILED BIT(0) - -+#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) -+ - enum cedrus_codec { - CEDRUS_CODEC_MPEG2, - -@@ -91,6 +93,7 @@ struct cedrus_dec_ops { - - struct cedrus_variant { - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct cedrus_dev { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index 0acf219a8c91..fbfff7c1c771 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -177,7 +177,8 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - */ - - #ifdef PHYS_PFN_OFFSET -- dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; -+ if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET)) -+ dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; - #endif - - ret = of_reserved_mem_device_init(dev->dev); --- -2.20.1 - - -From 744c66f8c328ef40b6fb246f8b9f2daa9cce4d9d Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:47:33 +0100 -Subject: [PATCH 3/6] media: cedrus: Add support for H6 - -H6 has improved VPU. It supports 10-bit HEVC decoding and AFBC output -format for HEVC. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index ff11cbeba205..b98add3cdedd 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -396,6 +396,11 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, - }; - -+static const struct cedrus_variant sun50i_h6_cedrus_variant = { -+ .capabilities = CEDRUS_CAPABILITY_UNTILED | CEDRUS_CAPABILITY_H265_DEC, -+ .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, -+}; -+ - static const struct of_device_id cedrus_dt_match[] = { - { - .compatible = "allwinner,sun4i-a10-video-engine", -@@ -425,6 +430,10 @@ static const struct of_device_id cedrus_dt_match[] = { - .compatible = "allwinner,sun50i-h5-video-engine", - .data = &sun50i_h5_cedrus_variant, - }, -+ { -+ .compatible = "allwinner,sun50i-h6-video-engine", -+ .data = &sun50i_h6_cedrus_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, cedrus_dt_match); --- -2.20.1 - - -From b4ca53c594950b80d71ac320b3505a303e7f6092 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 20:05:47 +0100 -Subject: [PATCH 4/6] dt-bindings: sram: sunxi: Add compatible for the H6 SRAM - C1 - -This introduces a new compatible for the H6 SRAM C1 section, that is -compatible with the SRAM C1 section as found on the A10. - -Signed-off-by: Jernej Skrabec ---- - Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt -index ab5a70bb9a64..380246a805f2 100644 ---- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt -+++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt -@@ -63,6 +63,7 @@ The valid sections compatible for H5 are: - - The valid sections compatible for H6 are: - - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c -+ - allwinner,sun50i-h6-sram-c1, allwinner,sun4i-a10-sram-c1 - - The valid sections compatible for F1C100s are: - - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d --- -2.20.1 - - -From 6a505c910b90581b2a980e52f9b6fcb03d234cb7 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:53:30 +0100 -Subject: [PATCH 5/6] arm64: dts: allwinner: h6: Add support for the SRAM C1 - section - -Add a node for H6 SRAM C1 section. - -Manual calls it VE SRAM, but for consistency with older SoCs, SRAM C1 -name is used. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index d93a7add67e7..247dc0a5ce89 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -167,6 +167,20 @@ - reg = <0x0000 0x1e000>; - }; - }; -+ -+ sram_c1: sram@1a00000 { -+ compatible = "mmio-sram"; -+ reg = <0x01a00000 0x200000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x01a00000 0x200000>; -+ -+ ve_sram: sram-section@0 { -+ compatible = "allwinner,sun50i-h6-sram-c1", -+ "allwinner,sun4i-a10-sram-c1"; -+ reg = <0x000000 0x200000>; -+ }; -+ }; - }; - - ccu: clock@3001000 { --- -2.20.1 - - -From c1b3128ac98c05c0afde4e6e065d6b1f2ae1dfa7 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 28 Jan 2019 19:59:27 +0100 -Subject: [PATCH 6/6] arm64: dts: allwinner: h6: Add Video Engine node - -This adds the Video engine node for H6. It can use whole DRAM range so -there is no need for reserved memory node. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 247dc0a5ce89..de4b7a1f1012 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -146,6 +146,17 @@ - }; - }; - -+ video-codec@1c0e000 { -+ compatible = "allwinner,sun50i-h6-video-engine"; -+ reg = <0x01c0e000 0x2000>; -+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, -+ <&ccu CLK_MBUS_VE>; -+ clock-names = "ahb", "mod", "ram"; -+ resets = <&ccu RST_BUS_VE>; -+ interrupts = ; -+ allwinner,sram = <&ve_sram 1>; -+ }; -+ - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h6-system-control", - "allwinner,sun50i-a64-system-control"; --- -2.20.1 - diff --git a/projects/Allwinner/devices/H6/patches/linux/06-10-bit-HEVC-hack.patch b/projects/Allwinner/devices/H6/patches/linux/06-10-bit-HEVC-hack.patch new file mode 100644 index 0000000000..2068b70a1e --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/06-10-bit-HEVC-hack.patch @@ -0,0 +1,91 @@ +From d117460aed81ee5cd384045a1189c9de758d17c6 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 28 May 2019 21:05:34 +0200 +Subject: [PATCH] 10-bit HEVC hack + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 12 ++++++++++++ + drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 4 ++++ + drivers/staging/media/sunxi/cedrus/cedrus_video.c | 13 +++++++++++-- + 3 files changed, 27 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index 8bbbe69ae51f..04ba7d60ebcd 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -453,6 +453,18 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + + cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); + ++ if (sps->bit_depth_luma_minus8) { ++ unsigned int size; ++ ++ size = ALIGN(ctx->src_fmt.width, 16) * ALIGN(ctx->src_fmt.height, 16); ++ ++ reg = (size * 3) / 2; ++ cedrus_write(dev, VE_DEC_H265_OFFSET_ADDR_FIRST_OUT, reg); ++ ++ reg = DIV_ROUND_UP(ctx->src_fmt.width, 4); ++ cedrus_write(dev, VE_DEC_H265_10BIT_CONFIGURE, ALIGN(reg, 32)); ++ } ++ + reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | + VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) | + VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) | +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index d1f010ae49ef..dd69031a2779 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -505,6 +505,10 @@ + + #define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) + ++#define VE_DEC_H265_OFFSET_ADDR_FIRST_OUT (VE_ENGINE_DEC_H265 + 0x84) ++#define VE_DEC_H265_OFFSET_ADDR_SECOND_OUT (VE_ENGINE_DEC_H265 + 0x88) ++#define VE_DEC_H265_10BIT_CONFIGURE (VE_ENGINE_DEC_H265 + 0x8c) ++ + #define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ + (((a) << 24) & GENMASK(31, 24)) + #define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \ +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index d27a9e82ff91..2c2288319c9d 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -372,6 +372,7 @@ static int cedrus_queue_setup(struct vb2_queue *vq, unsigned int *nbufs, + struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); + struct cedrus_dev *dev = ctx->dev; + struct v4l2_pix_format *pix_fmt; ++ unsigned int extra_size = 0; + u32 directions; + + if (V4L2_TYPE_IS_OUTPUT(vq->type)) { +@@ -380,6 +381,14 @@ static int cedrus_queue_setup(struct vb2_queue *vq, unsigned int *nbufs, + } else { + directions = CEDRUS_DECODE_DST; + pix_fmt = &ctx->dst_fmt; ++ ++ /* The HEVC decoder needs extra size on the output buffer. */ ++ if (ctx->src_fmt.pixelformat == V4L2_PIX_FMT_HEVC_SLICE) { ++ extra_size = DIV_ROUND_UP(pix_fmt->width, 4); ++ extra_size = ALIGN(extra_size, 32); ++ extra_size *= ALIGN(pix_fmt->height, 16) * 3; ++ extra_size /= 2; ++ } + } + + if (!cedrus_check_format(pix_fmt->pixelformat, directions, +@@ -387,8 +396,8 @@ static int cedrus_queue_setup(struct vb2_queue *vq, unsigned int *nbufs, + return -EINVAL; + + if (*nplanes) { +- if (sizes[0] < pix_fmt->sizeimage) +- return -EINVAL; ++ if (sizes[0] < (pix_fmt->sizeimage + extra_size)) ++ sizes[0] = pix_fmt->sizeimage + extra_size; + } else { + sizes[0] = pix_fmt->sizeimage; + *nplanes = 1; +-- +2.21.0 + diff --git a/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch b/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch deleted file mode 100644 index 7abb69bb99..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 18c9a269e2b744ee84f32de9d5c6c66857725ef8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 15 Dec 2018 12:56:53 +0100 -Subject: [PATCH 20/20] cedrus increase frequency - ---- - drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index b43c77d54b95..70677571f3d3 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -16,7 +16,7 @@ - #ifndef _CEDRUS_HW_H_ - #define _CEDRUS_HW_H_ - --#define CEDRUS_CLOCK_RATE_DEFAULT 402000000 -+#define CEDRUS_CLOCK_RATE_DEFAULT 600000000 - - int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); - void cedrus_engine_disable(struct cedrus_dev *dev); --- -2.20.0 - diff --git a/projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch b/projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch deleted file mode 100644 index 29bd0ce45f..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -index caea5a9f8f1d..ba4ce576b471 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -48,8 +48,13 @@ static enum drm_mode_status - sun8i_dw_hdmi_mode_valid_h6(struct drm_connector *connector, - const struct drm_display_mode *mode) - { -- /* This is max for HDMI 2.0b (4K@60Hz) */ -- if (mode->clock > 594000) -+ /* -+ * Controller support maximum of 594 MHz, which correlates to -+ * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than -+ * 340 MHz scrambling has to be enabled. Because scrambling is -+ * not yet implemented, just limit to 340 MHz for now. -+ */ -+ if (mode->clock > 340000) - return MODE_CLOCK_HIGH; - - return MODE_OK; diff --git a/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch b/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch deleted file mode 100644 index 68c1d5a8c8..0000000000 --- a/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 9413130f5b213551519c97482462a6daea9a5343 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 2 Apr 2019 19:32:01 +0200 -Subject: [PATCH 1/2] clk: sunxi-ng: h6: Change CEC clock parent - -Signed-off-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index daf78966555e..33980067b06e 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -656,6 +656,8 @@ static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; - static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { - { .index = 1, .div = 36621 }, - }; -+ -+#define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10 - static struct ccu_mux hdmi_cec_clk = { - .enable = BIT(31), - -@@ -1200,6 +1202,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) - val &= ~(GENMASK(21, 16) | BIT(0)); - writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); - -+ /* -+ * First clock parent (osc32K) is unusable for CEC. But since there -+ * is no good way to force parent switch (both run with same frequency), -+ * just set second clock parent here. -+ */ -+ val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); -+ val |= BIT(24); -+ writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); -+ - return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); - } - --- -2.21.0 - - -From eab64a1ccf6b7cda339fdfdbfa9e1973e4cc0c85 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 2 Apr 2019 21:15:45 +0200 -Subject: [PATCH 2/2] clk: sunxi-ng: h6: Allow video & vpu clocks to change - parent rate - -Video related clocks need to set rate as close as possible to the -requested one, so they should be able to change parent clock rate. - -VPU clock sometimes has to be set to higher than default parent clock -rate. This is requ - -Add CLK_SET_RATE_PARENT flag to tcon-lcd0, tcon-tv0 and ve. - -Signed-off-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index 33980067b06e..3c32d7798f27 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, - 0, 3, /* M */ - 24, 1, /* mux */ - BIT(31), /* gate */ -- 0); -+ CLK_SET_RATE_PARENT); - - static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", - 0x69c, BIT(0), 0); -@@ -691,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", - tcon_lcd0_parents, 0xb60, - 24, 3, /* mux */ - BIT(31), /* gate */ -- 0); -+ CLK_SET_RATE_PARENT); - - static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", - 0xb7c, BIT(0), 0); -@@ -706,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", - 8, 2, /* P */ - 24, 3, /* mux */ - BIT(31), /* gate */ -- 0); -+ CLK_SET_RATE_PARENT); - - static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", - 0xb9c, BIT(0), 0); --- -2.21.0 - diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index 43978f63cf..6c5aecac90 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,15 +1,16 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.0.2 Kernel Configuration +# Linux/arm64 5.1.6 Kernel Configuration # # -# Compiler: aarch64-linux-gnu-gcc.real (Linaro GCC 7.3-2018.05) 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] +# Compiler: aarch64-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0 # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70301 +CONFIG_GCC_VERSION=80300 CONFIG_CLANG_VERSION=0 CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -180,6 +181,7 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y @@ -247,6 +249,7 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set # CONFIG_ARCH_EXYNOS is not set # CONFIG_ARCH_K3 is not set @@ -293,6 +296,7 @@ CONFIG_ARM64_ERRATUM_1024718=y CONFIG_ARM64_ERRATUM_1188873=y CONFIG_ARM64_ERRATUM_1165522=y CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1463225=y CONFIG_CAVIUM_ERRATUM_22375=y CONFIG_CAVIUM_ERRATUM_23144=y CONFIG_CAVIUM_ERRATUM_23154=y @@ -305,6 +309,7 @@ CONFIG_QCOM_QDF2400_ERRATUM_0065=y CONFIG_SOCIONEXT_SYNQUACER_PREITS=y CONFIG_HISILICON_ERRATUM_161600802=y CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_FUJITSU_ERRATUM_010001=y CONFIG_ARM64_4K_PAGES=y # CONFIG_ARM64_16K_PAGES is not set # CONFIG_ARM64_64K_PAGES is not set @@ -389,6 +394,7 @@ CONFIG_EFI=y CONFIG_DMI=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y # # Power management options @@ -426,6 +432,7 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set CONFIG_DT_IDLE_STATES=y # @@ -472,7 +479,6 @@ CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_ARM_SDE_INTERFACE is not set CONFIG_DMIID=y # CONFIG_DMI_SYSFS is not set -# CONFIG_INTEL_STRATIX10_SERVICE is not set CONFIG_HAVE_ARM_SMCCC=y # CONFIG_GOOGLE_FIRMWARE is not set @@ -488,6 +494,7 @@ CONFIG_EFI_ARMSTUB_DTB_LOADER=y CONFIG_EFI_CAPSULE_LOADER=y # CONFIG_EFI_TEST is not set # CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_EFI_EARLYCON=y # # Tegra firmware driver @@ -571,6 +578,7 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_64BIT_TIME=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y @@ -580,15 +588,15 @@ CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_REFCOUNT_FULL=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_PLUGIN_HOSTCC="g++" +CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y -# CONFIG_GCC_PLUGINS is not set CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y @@ -708,6 +716,7 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y +CONFIG_UNIX_SCM=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -819,6 +828,7 @@ CONFIG_NF_NAT_NEEDED=y CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m @@ -960,8 +970,6 @@ CONFIG_NF_DEFRAG_IPV4=m # CONFIG_NF_LOG_ARP is not set CONFIG_NF_LOG_IPV4=m CONFIG_NF_REJECT_IPV4=m -CONFIG_NF_NAT_IPV4=m -CONFIG_NF_NAT_MASQUERADE_IPV4=y CONFIG_IP_NF_IPTABLES=m # CONFIG_IP_NF_MATCH_AH is not set # CONFIG_IP_NF_MATCH_ECN is not set @@ -990,8 +998,6 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_NF_DUP_IPV6 is not set CONFIG_NF_REJECT_IPV6=m CONFIG_NF_LOG_IPV6=m -CONFIG_NF_NAT_IPV6=m -CONFIG_NF_NAT_MASQUERADE_IPV6=y CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -1214,7 +1220,6 @@ CONFIG_NET_9P=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y # CONFIG_NET_DEVLINK is not set -CONFIG_MAY_USE_DEVLINK=y CONFIG_FAILOVER=y CONFIG_HAVE_EBPF_JIT=y @@ -1258,17 +1263,6 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set -CONFIG_DMA_CMA=y - -# -# Default contiguous memory area size: -# -CONFIG_CMA_SIZE_MBYTES=256 -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_ALIGNMENT=8 CONFIG_GENERIC_ARCH_TOPOLOGY=y # @@ -1364,9 +1358,9 @@ CONFIG_MTD_NAND_DENALI_DT=y # # CONFIG_MTD_LPDDR is not set CONFIG_MTD_SPI_NOR=y -# CONFIG_MTD_MT81xx_NOR is not set CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_MTK_QUADSPI is not set # CONFIG_MTD_UBI is not set CONFIG_DTC=y CONFIG_OF=y @@ -1459,6 +1453,7 @@ CONFIG_EEPROM_AT25=m # # VOP Bus Driver # +# CONFIG_VOP_BUS is not set # # Intel MIC Host Driver @@ -1526,7 +1521,6 @@ CONFIG_SCSI_UFSHCD_PLATFORM=m # CONFIG_SCSI_UFS_BSG is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_HAVE_PATA_PLATFORM=y CONFIG_ATA=y CONFIG_ATA_VERBOSE_ERROR=y @@ -1603,6 +1597,7 @@ CONFIG_DUMMY=m # CONFIG_NET_TEAM is not set CONFIG_MACVLAN=m CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y CONFIG_IPVLAN=m # CONFIG_IPVTAP is not set CONFIG_VXLAN=m @@ -1698,8 +1693,8 @@ CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_SUNXI=y -CONFIG_DWMAC_SUN8I=y +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_SUN8I=m CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set CONFIG_NET_VENDOR_VIA=y @@ -1715,6 +1710,7 @@ CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BUS_MUX=y # CONFIG_MDIO_BUS_MUX_GPIO is not set CONFIG_MDIO_BUS_MUX_MMIOREG=y +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_GPIO is not set # CONFIG_MDIO_HISI_FEMAC is not set # CONFIG_MDIO_MSCC_MIIM is not set @@ -1939,7 +1935,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_TM2_TOUCHKEY is not set # CONFIG_KEYBOARD_XTKBD is not set -CONFIG_KEYBOARD_CROS_EC=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_BCM is not set # CONFIG_INPUT_MOUSE is not set @@ -2016,6 +2011,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_ATMEL_CAPTOUCH is not set # CONFIG_INPUT_BMA150 is not set # CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MSM_VIBRATOR is not set # CONFIG_INPUT_MMA8450 is not set # CONFIG_INPUT_GP2A is not set # CONFIG_INPUT_GPIO_BEEPER is not set @@ -2077,6 +2073,7 @@ CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_TRACE_SINK is not set +CONFIG_LDISC_AUTOLOAD=y CONFIG_DEVMEM=y # @@ -2129,7 +2126,6 @@ CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set CONFIG_TCG_TPM=y # CONFIG_TCG_TIS is not set @@ -2201,7 +2197,6 @@ CONFIG_I2C_RK3X=y # # Other I2C/SMBus bus drivers # -CONFIG_I2C_CROS_EC_TUNNEL=y # CONFIG_I2C_STUB is not set CONFIG_I2C_SLAVE=y # CONFIG_I2C_SLAVE_EEPROM is not set @@ -2222,12 +2217,14 @@ CONFIG_SPI_MEM=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y # CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_SUN4I is not set # CONFIG_SPI_SUN6I is not set # CONFIG_SPI_MXIC is not set @@ -2314,12 +2311,14 @@ CONFIG_GPIO_PL061=y # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_XGENE=y # CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set # # I2C GPIO expanders # # CONFIG_GPIO_ADP5588 is not set # CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y @@ -2330,7 +2329,6 @@ CONFIG_GPIO_PCA953X_IRQ=y # # MFD GPIO expanders # -# CONFIG_GPIO_BD9571MWV is not set CONFIG_GPIO_MAX77620=y # @@ -2395,7 +2393,6 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_CHARGER_RT9455 is not set -# CONFIG_CHARGER_CROS_USBPD is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2570,7 +2567,7 @@ CONFIG_ARM_SP805_WATCHDOG=y # CONFIG_ARM_SBSA_WATCHDOG is not set # CONFIG_CADENCE_WATCHDOG is not set # CONFIG_DW_WATCHDOG is not set -# CONFIG_SUNXI_WATCHDOG is not set +CONFIG_SUNXI_WATCHDOG=y # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_MAX77620_WATCHDOG is not set # CONFIG_MEN_A21_WDT is not set @@ -2602,13 +2599,12 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_ATMEL_FLEXCOM is not set # CONFIG_MFD_ATMEL_HLCDC is not set # CONFIG_MFD_BCM590XX is not set -CONFIG_MFD_BD9571MWV=y +# CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AC100 is not set CONFIG_MFD_AXP20X=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_CROS_EC=y -CONFIG_MFD_CROS_EC_CHARDEV=m +# CONFIG_MFD_CROS_EC is not set # CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set @@ -2680,6 +2676,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WL1273_CORE is not set # CONFIG_MFD_LM3533 is not set # CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_LOCHNAGAR is not set # CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_ARIZONA_SPI is not set # CONFIG_MFD_WM8400 is not set @@ -2688,6 +2686,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_STPMIC1 is not set CONFIG_MFD_VEXPRESS_SYSREG=y # CONFIG_RAVE_SP_CORE is not set CONFIG_REGULATOR=y @@ -2700,7 +2699,6 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ANATOP is not set CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_BD9571MWV=y # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set CONFIG_REGULATOR_FAN53555=y @@ -3067,10 +3065,6 @@ CONFIG_VIDEO_MT9V011=m # Miscellaneous helper chips # -# -# Sensors used on soc_camera driver -# - # # Media SPI Adapters # @@ -3260,8 +3254,13 @@ CONFIG_DRM_I2C_CH7006=m CONFIG_DRM_I2C_SIL164=m # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_NXP_TDA9950 is not set + +# +# ARM devices +# # CONFIG_DRM_HDLCD is not set # CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set # # ACP (Audio CoProcessor) Configuration @@ -3298,6 +3297,7 @@ CONFIG_DRM_PANEL_SIMPLE=m # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y @@ -3324,6 +3324,7 @@ CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set CONFIG_DRM_DW_HDMI_I2S_AUDIO=y CONFIG_DRM_DW_HDMI_CEC=y +# CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set @@ -3468,9 +3469,11 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # CONFIG_SND_I2S_HI6210_I2S is not set # CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set # # STMicroelectronics STM32 SOC audio support @@ -3487,6 +3490,8 @@ CONFIG_SND_SUN4I_I2S=y CONFIG_SND_SUN4I_SPDIF=y CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y # CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set # CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y @@ -3514,6 +3519,7 @@ CONFIG_SND_SOC_AK4613=m # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set # CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set # CONFIG_SND_SOC_CS42L42 is not set # CONFIG_SND_SOC_CS42L51_I2C is not set # CONFIG_SND_SOC_CS42L52 is not set @@ -3525,6 +3531,7 @@ CONFIG_SND_SOC_AK4613=m # CONFIG_SND_SOC_CS4271_SPI is not set # CONFIG_SND_SOC_CS42XX8_I2C is not set # CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set # CONFIG_SND_SOC_DMIC is not set @@ -3556,6 +3563,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_PCM3168A_SPI is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_SGTL5000 is not set @@ -3602,6 +3610,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_WM8804_I2C is not set # CONFIG_SND_SOC_WM8804_SPI is not set # CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set # CONFIG_SND_SOC_WM8960 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8974 is not set @@ -3610,6 +3619,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set @@ -3617,9 +3627,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_TPA6130A2 is not set CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y -# CONFIG_SND_SIMPLE_SCU_CARD is not set CONFIG_SND_AUDIO_GRAPH_CARD=y -# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set # # HID support @@ -3659,12 +3667,12 @@ CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_HOLTEK is not set -# CONFIG_HID_GOOGLE_HAMMER is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set # CONFIG_HID_KYE is not set # CONFIG_HID_UCLOGIC is not set # CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_ICADE is not set CONFIG_HID_ITE=y @@ -3681,6 +3689,7 @@ CONFIG_HID_LOGITECH=y # CONFIG_LOGIG940_FF is not set # CONFIG_LOGIWHEELS_FF is not set # CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set CONFIG_HID_REDRAGON=y CONFIG_HID_MICROSOFT=y @@ -3749,6 +3758,7 @@ CONFIG_USB_OTG=y # CONFIG_USB_OTG_BLACKLIST_HUB is not set # CONFIG_USB_OTG_FSM is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set # CONFIG_USB_WUSB_CBAF is not set @@ -3762,6 +3772,7 @@ CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_FSL is not set CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set @@ -4067,6 +4078,7 @@ CONFIG_RTC_INTF_DEV=y # I2C RTC drivers # # CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set # CONFIG_RTC_DRV_ABX80X is not set # CONFIG_RTC_DRV_DS1307 is not set # CONFIG_RTC_DRV_DS1374 is not set @@ -4093,8 +4105,10 @@ CONFIG_RTC_DRV_RK808=m # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV8803 is not set CONFIG_RTC_DRV_S5M=y +# CONFIG_RTC_DRV_SD3078 is not set # # SPI RTC drivers @@ -4143,7 +4157,6 @@ CONFIG_RTC_DRV_EFI=y # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # CONFIG_RTC_DRV_ZYNQMP is not set -CONFIG_RTC_DRV_CROS_EC=y # # on-CPU RTC drivers @@ -4151,6 +4164,7 @@ CONFIG_RTC_DRV_CROS_EC=y # CONFIG_RTC_DRV_PL030 is not set CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_SUN6I=y +# CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_R7301 is not set @@ -4158,7 +4172,6 @@ CONFIG_RTC_DRV_SUN6I=y # # HID Sensor RTC drivers # -# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -4175,6 +4188,7 @@ CONFIG_BCM_SBA_RAID=m CONFIG_DMA_SUN6I=y # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set # CONFIG_INTEL_IDMA64 is not set CONFIG_MV_XOR_V2=y CONFIG_PL330_DMA=y @@ -4227,7 +4241,6 @@ CONFIG_RTL8723BS=m # # Analog to digital converters # -# CONFIG_AD7606 is not set # CONFIG_AD7780 is not set # CONFIG_AD7816 is not set # CONFIG_AD7192 is not set @@ -4242,7 +4255,6 @@ CONFIG_RTL8723BS=m # Capacitance to digital converters # # CONFIG_AD7150 is not set -# CONFIG_AD7152 is not set # CONFIG_AD7746 is not set # @@ -4274,6 +4286,10 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y +# +# soc_camera sensor drivers +# + # # Android # @@ -4289,7 +4305,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_KS7010 is not set # CONFIG_GREYBUS is not set # CONFIG_PI433 is not set -# CONFIG_MTK_MMC is not set # # Gasket devices @@ -4297,11 +4312,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_EROFS_FS is not set # CONFIG_GOLDFISH is not set -CONFIG_CHROME_PLATFORMS=y -CONFIG_CROS_EC_CTL=m -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y -CONFIG_CROS_EC_PROTO=y +# CONFIG_CHROME_PLATFORMS is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -4327,6 +4338,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_XGENE is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_SUNXI_CCU=y CONFIG_SUN50I_A64_CCU=y CONFIG_SUN50I_H6_CCU=y @@ -4429,10 +4441,10 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_ADC_JACK is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set CONFIG_IIO=y @@ -4440,7 +4452,6 @@ CONFIG_IIO_BUFFER=y # CONFIG_IIO_BUFFER_CB is not set # CONFIG_IIO_BUFFER_HW_CONSUMER is not set CONFIG_IIO_KFIFO_BUF=m -CONFIG_IIO_TRIGGERED_BUFFER=m # CONFIG_IIO_CONFIGFS is not set CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 @@ -4489,7 +4500,10 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7291 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set # CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set # CONFIG_AD7791 is not set # CONFIG_AD7793 is not set # CONFIG_AD7887 is not set @@ -4529,6 +4543,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8688 is not set +# CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set @@ -4549,9 +4564,10 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_BME680 is not set # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set +# CONFIG_PMS7003 is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SPS30 is not set # CONFIG_VZ89X is not set -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m # # Hid Sensor IIO Common @@ -4600,6 +4616,7 @@ CONFIG_IIO_CROS_EC_SENSORS=m # CONFIG_TI_DAC082S085 is not set # CONFIG_TI_DAC5571 is not set # CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set # CONFIG_VF610_DAC is not set # @@ -4682,7 +4699,6 @@ CONFIG_IIO_CROS_EC_SENSORS=m # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set -CONFIG_IIO_CROS_EC_LIGHT_PROX=m # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set @@ -4692,6 +4708,7 @@ CONFIG_IIO_CROS_EC_LIGHT_PROX=m # CONFIG_LTR501 is not set # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set @@ -4765,7 +4782,6 @@ CONFIG_IIO_CROS_EC_LIGHT_PROX=m # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set -CONFIG_IIO_CROS_EC_BARO=m # CONFIG_HP03 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set @@ -4811,7 +4827,6 @@ CONFIG_IIO_CROS_EC_BARO=m # CONFIG_TSYS02D is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y -CONFIG_PWM_CROS_EC=m # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_SUN4I is not set @@ -4839,9 +4854,11 @@ CONFIG_RESET_SUNXI=y CONFIG_GENERIC_PHY=y CONFIG_PHY_XGENE=y CONFIG_PHY_SUN4I_USB=y +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set # CONFIG_PHY_SUN9I_USB is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -4886,11 +4903,13 @@ CONFIG_NVMEM=y CONFIG_PM_OPP=y # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set # # File systems # CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set @@ -4898,7 +4917,6 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_USE_FOR_EXT2=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_ENCRYPTION is not set # CONFIG_EXT4_DEBUG is not set CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set @@ -4928,7 +4946,6 @@ CONFIG_F2FS_FS_XATTR=y CONFIG_F2FS_FS_POSIX_ACL=y # CONFIG_F2FS_FS_SECURITY is not set # CONFIG_F2FS_CHECK_FS is not set -# CONFIG_F2FS_FS_ENCRYPTION is not set # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y @@ -5163,13 +5180,14 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_SECURITY_APPARMOR is not set # CONFIG_SECURITY_LOADPIN is not set # CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y # CONFIG_IMA is not set # CONFIG_EVM is not set CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" +CONFIG_LSM="yama,loadpin,safesetid,integrity" CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y @@ -5400,7 +5418,8 @@ CONFIG_HAS_DMA=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y @@ -5408,6 +5427,18 @@ CONFIG_ARCH_HAS_DMA_MMAP_PGPROT=y CONFIG_SWIOTLB=y CONFIG_DMA_REMAP=y CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=384 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -5438,6 +5469,7 @@ CONFIG_SBITMAP=y # printk and dmesg options # CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -5457,7 +5489,6 @@ CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_PAGE_OWNER is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set @@ -5475,6 +5506,7 @@ CONFIG_DEBUG_KERNEL=y # # CONFIG_PAGE_EXTENSION is not set # CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_OBJECTS is not set @@ -5563,7 +5595,6 @@ CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set -# CONFIG_DMA_API_DEBUG is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_LIST_SORT is not set @@ -5586,6 +5617,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_HASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set +# CONFIG_TEST_VMALLOC is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set # CONFIG_FIND_BIT_BENCHMARK is not set @@ -5595,6 +5627,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STATIC_KEYS is not set # CONFIG_TEST_KMOD is not set # CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set CONFIG_MEMTEST=y # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set @@ -5602,6 +5635,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y # CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y # CONFIG_IO_STRICT_DEVMEM is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index a2a6548133..c0d6495b30 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,15 +1,16 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.0.2 Kernel Configuration +# Linux/arm 5.1.5 Kernel Configuration # # -# Compiler: armv7ve-libreelec-linux-gnueabi-gcc-8.2.0 (GCC) 8.2.0 +# Compiler: armv7ve-libreelec-linux-gnueabi-gcc-8.3.0 (GCC) 8.3.0 # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=80200 +CONFIG_GCC_VERSION=80300 CONFIG_CLANG_VERSION=0 CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y @@ -178,6 +179,7 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y @@ -278,6 +280,7 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_KEYSTONE is not set # CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MILBEAUT is not set # CONFIG_ARCH_MMP is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_NPCM is not set @@ -488,6 +491,7 @@ CONFIG_CPUFREQ_DT_PLATDEV=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set # # ARM CPU Idle Drivers @@ -536,7 +540,6 @@ CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_FW_CFG_SYSFS is not set -# CONFIG_INTEL_STRATIX10_SERVICE is not set CONFIG_HAVE_ARM_SMCCC=y # CONFIG_GOOGLE_FIRMWARE is not set @@ -569,6 +572,7 @@ CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_CLK=y @@ -594,6 +598,8 @@ CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y +CONFIG_64BIT_TIME=y +CONFIG_COMPAT_32BIT_TIME=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y @@ -608,9 +614,8 @@ CONFIG_REFCOUNT_FULL=y # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_PLUGIN_HOSTCC="g++" +CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y -# CONFIG_GCC_PLUGINS is not set CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y @@ -731,6 +736,7 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y +CONFIG_UNIX_SCM=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y @@ -838,6 +844,7 @@ CONFIG_NF_NAT_NEEDED=y CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=m @@ -973,8 +980,6 @@ CONFIG_NF_DEFRAG_IPV4=m # CONFIG_NF_LOG_ARP is not set # CONFIG_NF_LOG_IPV4 is not set # CONFIG_NF_REJECT_IPV4 is not set -CONFIG_NF_NAT_IPV4=m -CONFIG_NF_NAT_MASQUERADE_IPV4=y CONFIG_IP_NF_IPTABLES=m # CONFIG_IP_NF_MATCH_AH is not set # CONFIG_IP_NF_MATCH_ECN is not set @@ -998,7 +1003,6 @@ CONFIG_IP_NF_TARGET_REDIRECT=m # CONFIG_NF_DUP_IPV6 is not set # CONFIG_NF_REJECT_IPV6 is not set # CONFIG_NF_LOG_IPV6 is not set -# CONFIG_NF_NAT_IPV6 is not set # CONFIG_IP6_NF_IPTABLES is not set CONFIG_NF_DEFRAG_IPV6=m # CONFIG_BRIDGE_NF_EBTABLES is not set @@ -1171,16 +1175,23 @@ CONFIG_BT_LEDS=y CONFIG_BT_INTEL=m CONFIG_BT_BCM=m CONFIG_BT_RTL=m +CONFIG_BT_QCA=m CONFIG_BT_HCIBTUSB=m # CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set CONFIG_BT_HCIBTUSB_BCM=y CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_NOKIA is not set CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=m @@ -1190,6 +1201,7 @@ CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m +CONFIG_BT_MTKUART=m # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set CONFIG_WIRELESS=y @@ -1230,7 +1242,6 @@ CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y # CONFIG_NET_DEVLINK is not set -CONFIG_MAY_USE_DEVLINK=y # CONFIG_FAILOVER is not set CONFIG_HAVE_EBPF_JIT=y @@ -1272,17 +1283,6 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set -CONFIG_DMA_CMA=y - -# -# Default contiguous memory area size: -# -CONFIG_CMA_SIZE_MBYTES=256 -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_ALIGNMENT=8 CONFIG_GENERIC_ARCH_TOPOLOGY=y # @@ -1391,6 +1391,7 @@ CONFIG_EEPROM_93CX6=m # # VOP Bus Driver # +# CONFIG_VOP_BUS is not set # # Intel MIC Host Driver @@ -1451,7 +1452,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_SATA_PMP=y @@ -1525,6 +1525,7 @@ CONFIG_DUMMY=m # CONFIG_NET_TEAM is not set CONFIG_MACVLAN=m # CONFIG_MACVTAP is not set +CONFIG_IPVLAN_L3S=y CONFIG_IPVLAN=m # CONFIG_IPVTAP is not set CONFIG_VXLAN=m @@ -1588,6 +1589,7 @@ CONFIG_NET_VENDOR_NI=y # CONFIG_ETHOC is not set CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set +# CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set # CONFIG_RMNET is not set CONFIG_NET_VENDOR_RENESAS=y @@ -1615,6 +1617,7 @@ CONFIG_MDIO_BUS=y CONFIG_MDIO_BUS_MUX=y # CONFIG_MDIO_BUS_MUX_GPIO is not set # CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_HISI_FEMAC is not set # CONFIG_MDIO_MSCC_MIIM is not set CONFIG_MDIO_SUN4I=y @@ -1910,6 +1913,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_ATMEL_CAPTOUCH is not set # CONFIG_INPUT_BMA150 is not set # CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MSM_VIBRATOR is not set # CONFIG_INPUT_MMA8450 is not set # CONFIG_INPUT_GP2A is not set # CONFIG_INPUT_GPIO_BEEPER is not set @@ -1968,6 +1972,7 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_TRACE_SINK is not set +CONFIG_LDISC_AUTOLOAD=y CONFIG_DEVMEM=y CONFIG_DEVKMEM=y @@ -2010,12 +2015,12 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_FSL_LPUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set -# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_TTY_PRINTK is not set # CONFIG_HVC_DCC is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set @@ -2094,11 +2099,13 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set CONFIG_SPI_SUN4I=y CONFIG_SPI_SUN6I=y # CONFIG_SPI_MXIC is not set @@ -2183,12 +2190,14 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_XILINX is not set # CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_AMD_FCH is not set # # I2C GPIO expanders # # CONFIG_GPIO_ADP5588 is not set # CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set @@ -2541,6 +2550,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_LOCHNAGAR is not set # CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_ARIZONA_SPI is not set # CONFIG_MFD_WM8400 is not set @@ -2549,6 +2560,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_RAVE_SP_CORE is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -2902,10 +2915,6 @@ CONFIG_VIDEO_OV7640=m # Miscellaneous helper chips # -# -# Sensors used on soc_camera driver -# - # # Media SPI Adapters # @@ -3088,8 +3097,13 @@ CONFIG_DRM_KMS_CMA_HELPER=y # CONFIG_DRM_I2C_SIL164 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_NXP_TDA9950 is not set + +# +# ARM devices +# # CONFIG_DRM_HDLCD is not set # CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set # # ACP (Audio CoProcessor) Configuration @@ -3158,6 +3172,7 @@ CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_HDMI_I2S_AUDIO=y CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_STI is not set +# CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set # CONFIG_DRM_TINYDRM is not set @@ -3273,9 +3288,11 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # CONFIG_SND_I2S_HI6210_I2S is not set # CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set # # STMicroelectronics STM32 SOC audio support @@ -3291,6 +3308,8 @@ CONFIG_SND_SUN4I_I2S=y CONFIG_SND_SUN4I_SPDIF=y CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y # CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set # CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y @@ -3318,6 +3337,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set # CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set # CONFIG_SND_SOC_CS42L42 is not set # CONFIG_SND_SOC_CS42L51_I2C is not set # CONFIG_SND_SOC_CS42L52 is not set @@ -3329,6 +3349,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_CS4271_SPI is not set # CONFIG_SND_SOC_CS42XX8_I2C is not set # CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set # CONFIG_SND_SOC_DMIC is not set @@ -3359,6 +3380,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_PCM3168A_SPI is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_SGTL5000 is not set @@ -3405,6 +3427,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_WM8804_I2C is not set # CONFIG_SND_SOC_WM8804_SPI is not set # CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set # CONFIG_SND_SOC_WM8960 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8974 is not set @@ -3413,6 +3436,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ZX_AUD96P22 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set @@ -3420,9 +3444,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_TPA6130A2 is not set CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_SCU_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y -CONFIG_SND_AUDIO_GRAPH_SCU_CARD=y # # HID support @@ -3467,6 +3489,7 @@ CONFIG_HID_EZKEY=y # CONFIG_HID_KYE is not set # CONFIG_HID_UCLOGIC is not set # CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_ICADE is not set # CONFIG_HID_ITE is not set @@ -3483,6 +3506,7 @@ CONFIG_HID_LOGITECH=y # CONFIG_LOGIG940_FF is not set # CONFIG_LOGIWHEELS_FF is not set # CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set # CONFIG_HID_REDRAGON is not set CONFIG_HID_MICROSOFT=y @@ -3550,6 +3574,7 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=m # CONFIG_USB_WUSB_CBAF is not set @@ -3561,6 +3586,7 @@ CONFIG_USB_MON=m CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_ROOT_HUB_TT is not set CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_FSL is not set CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set @@ -3872,6 +3898,7 @@ CONFIG_RTC_INTF_DEV=y # I2C RTC drivers # # CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set # CONFIG_RTC_DRV_ABX80X is not set # CONFIG_RTC_DRV_DS1307 is not set # CONFIG_RTC_DRV_DS1374 is not set @@ -3896,7 +3923,9 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set # # SPI RTC drivers @@ -3949,6 +3978,7 @@ CONFIG_RTC_I2C_AND_SPI=y # on-CPU RTC drivers # CONFIG_RTC_DRV_SUN6I=y +# CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_R7301 is not set @@ -3956,7 +3986,6 @@ CONFIG_RTC_DRV_SUN6I=y # # HID Sensor RTC drivers # -# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -3970,6 +3999,7 @@ CONFIG_DMA_OF=y CONFIG_DMA_SUN6I=y # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_NBPFAXI_DMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set @@ -4018,7 +4048,6 @@ CONFIG_STAGING=y # # Analog to digital converters # -# CONFIG_AD7606 is not set # CONFIG_AD7780 is not set # CONFIG_AD7816 is not set # CONFIG_AD7192 is not set @@ -4033,7 +4062,6 @@ CONFIG_STAGING=y # Capacitance to digital converters # # CONFIG_AD7150 is not set -# CONFIG_AD7152 is not set # CONFIG_AD7746 is not set # @@ -4065,6 +4093,10 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y +# +# soc_camera sensor drivers +# + # # Android # @@ -4080,7 +4112,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_KS7010 is not set # CONFIG_GREYBUS is not set # CONFIG_PI433 is not set -# CONFIG_MTK_MMC is not set # # Gasket devices @@ -4109,6 +4140,7 @@ CONFIG_COMMON_CLK=y # CONFIG_CLK_QORIQ is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_SUNXI_CCU=y CONFIG_SUN8I_A23_CCU=y CONFIG_SUN8I_A33_CCU=y @@ -4198,6 +4230,7 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_ADC_JACK is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set @@ -4254,7 +4287,10 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_AD7291 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set # CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set # CONFIG_AD7791 is not set # CONFIG_AD7793 is not set # CONFIG_AD7887 is not set @@ -4292,6 +4328,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8688 is not set +# CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set @@ -4312,6 +4349,9 @@ CONFIG_SUN4I_GPADC=y # CONFIG_BME680 is not set # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set +# CONFIG_PMS7003 is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SPS30 is not set # CONFIG_VZ89X is not set # @@ -4361,6 +4401,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_TI_DAC082S085 is not set # CONFIG_TI_DAC5571 is not set # CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set # CONFIG_VF610_DAC is not set # @@ -4452,6 +4493,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_LTR501 is not set # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set @@ -4586,10 +4628,13 @@ CONFIG_RESET_SUNXI=y # PHY Subsystem # CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN6I_MIPI_DPHY=y CONFIG_PHY_SUN9I_USB=y # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -4627,11 +4672,13 @@ CONFIG_NVMEM_SUNXI_SID=y CONFIG_PM_OPP=y # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set # # File systems # CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set @@ -4639,7 +4686,6 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_USE_FOR_EXT2=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_ENCRYPTION is not set # CONFIG_EXT4_DEBUG is not set CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set @@ -4670,7 +4716,6 @@ CONFIG_F2FS_FS_XATTR=y CONFIG_F2FS_FS_POSIX_ACL=y # CONFIG_F2FS_FS_SECURITY is not set # CONFIG_F2FS_CHECK_FS is not set -# CONFIG_F2FS_FS_ENCRYPTION is not set # CONFIG_F2FS_FAULT_INJECTION is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -4869,7 +4914,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" +CONFIG_LSM="yama,loadpin,safesetid,integrity" CONFIG_CRYPTO=y # @@ -5085,8 +5130,22 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_DMA_REMAP=y +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -5116,6 +5175,7 @@ CONFIG_SBITMAP=y # printk and dmesg options # CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 @@ -5131,7 +5191,6 @@ CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_PAGE_OWNER is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set @@ -5147,6 +5206,7 @@ CONFIG_DEBUG_KERNEL=y # # CONFIG_PAGE_EXTENSION is not set # CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_OBJECTS is not set @@ -5231,7 +5291,6 @@ CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set -# CONFIG_DMA_API_DEBUG is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_LIST_SORT is not set @@ -5254,6 +5313,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_HASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set +# CONFIG_TEST_VMALLOC is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set # CONFIG_FIND_BIT_BENCHMARK is not set @@ -5263,12 +5323,14 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STATIC_KEYS is not set # CONFIG_TEST_KMOD is not set # CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set # CONFIG_MEMTEST is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set # CONFIG_ARM_PTDUMP_DEBUGFS is not set diff --git a/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch index d62f69510e..105944ec2a 100644 --- a/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch +++ b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch @@ -401,9 +401,9 @@ index ccb5aa8468e0..e78be449e763 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); - void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); + void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); +void dw_hdmi_set_update_eld(struct dw_hdmi *hdmi, + void (*update_eld)(struct device *dev, u8 *eld)); diff --git a/projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch b/projects/Allwinner/patches/linux/0002-backport-from-5.2.patch similarity index 65% rename from projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch rename to projects/Allwinner/patches/linux/0002-backport-from-5.2.patch index 738a3a4b50..cfeada910b 100644 --- a/projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch +++ b/projects/Allwinner/patches/linux/0002-backport-from-5.2.patch @@ -674,3 +674,316 @@ index b98add3cdedd..d0429c0e6b6b 100644 -- 2.21.0 +From ed19ec00d4d62a74857ad9c2ea1dbf9671ac3580 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:36:54 +0100 +Subject: [PATCH 1/6] dt-bindings: media: cedrus: Add H6 compatible + +This adds a compatible for H6. H6 VPU supports 10-bit HEVC decoding and +additional AFBC output format for HEVC. + +Signed-off-by: Jernej Skrabec +--- + Documentation/devicetree/bindings/media/cedrus.txt | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt +index bce0705df953..20c82fb0c343 100644 +--- a/Documentation/devicetree/bindings/media/cedrus.txt ++++ b/Documentation/devicetree/bindings/media/cedrus.txt +@@ -13,6 +13,7 @@ Required properties: + - "allwinner,sun8i-h3-video-engine" + - "allwinner,sun50i-a64-video-engine" + - "allwinner,sun50i-h5-video-engine" ++ - "allwinner,sun50i-h6-video-engine" + - reg : register base and length of VE; + - clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +-- +2.20.1 + + +From 744c66f8c328ef40b6fb246f8b9f2daa9cce4d9d Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:47:33 +0100 +Subject: [PATCH 3/6] media: cedrus: Add support for H6 + +H6 has improved VPU. It supports 10-bit HEVC decoding and AFBC output +format for HEVC. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index ff11cbeba205..b98add3cdedd 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -396,6 +396,11 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, + }; + ++static const struct cedrus_variant sun50i_h6_cedrus_variant = { ++ .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, ++}; ++ + static const struct of_device_id cedrus_dt_match[] = { + { + .compatible = "allwinner,sun4i-a10-video-engine", +@@ -425,6 +430,10 @@ static const struct of_device_id cedrus_dt_match[] = { + .compatible = "allwinner,sun50i-h5-video-engine", + .data = &sun50i_h5_cedrus_variant, + }, ++ { ++ .compatible = "allwinner,sun50i-h6-video-engine", ++ .data = &sun50i_h6_cedrus_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, cedrus_dt_match); +-- +2.20.1 + + +From c1b3128ac98c05c0afde4e6e065d6b1f2ae1dfa7 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:59:27 +0100 +Subject: [PATCH 6/6] arm64: dts: allwinner: h6: Add Video Engine node + +This adds the Video engine node for H6. It can use whole DRAM range so +there is no need for reserved memory node. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 247dc0a5ce89..de4b7a1f1012 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -146,6 +146,17 @@ + }; + }; + ++ video-codec@1c0e000 { ++ compatible = "allwinner,sun50i-h6-video-engine"; ++ reg = <0x01c0e000 0x2000>; ++ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, ++ <&ccu CLK_MBUS_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ interrupts = ; ++ allwinner,sram = <&ve_sram 1>; ++ }; ++ + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h6-system-control", + "allwinner,sun50i-a64-system-control"; +-- +2.20.1 + +From 87effaae9e90474546d441b9123bca824e670a0b Mon Sep 17 00:00:00 2001 +From: Fish Lin +Date: Thu, 28 Mar 2019 23:20:46 -0400 +Subject: [PATCH] media: v4l: add I / P frame min max QP definitions + +Add following V4L2 QP parameters for H.264: +* V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP +* V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP +* V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP +* V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP + +These controls will limit QP range for intra and inter frame, +provide more manual control to improve video encode quality. + +Signed-off-by: Fish Lin +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../media/uapi/v4l/ext-ctrls-codec.rst | 24 +++++++++++++++++++ + drivers/media/v4l2-core/v4l2-ctrls.c | 4 ++++ + include/uapi/linux/v4l2-controls.h | 4 ++++ + 3 files changed, 32 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index 67a122339c0e..4a8446203085 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -1055,6 +1055,30 @@ enum v4l2_mpeg_video_h264_entropy_mode - + Quantization parameter for an B frame for H264. Valid range: from 0 + to 51. + ++``V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (integer)`` ++ Minimum quantization parameter for the H264 I frame to limit I frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MIN_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ ++``V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (integer)`` ++ Maximum quantization parameter for the H264 I frame to limit I frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MAX_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ ++``V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (integer)`` ++ Minimum quantization parameter for the H264 P frame to limit P frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MIN_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ ++``V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (integer)`` ++ Maximum quantization parameter for the H264 P frame to limit P frame ++ quality to a range. Valid range: from 0 to 51. If ++ V4L2_CID_MPEG_VIDEO_H264_MAX_QP is also set, the quantization parameter ++ should be chosen to meet both requirements. ++ + ``V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (integer)`` + Quantization parameter for an I frame for MPEG4. Valid range: from 1 + to 31. +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index b1ae2e555c68..89a1fe564675 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -828,6 +828,10 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: + return "H264 Constrained Intra Pred"; + case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: return "H264 Chroma QP Index Offset"; ++ case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: return "H264 I-Frame Minimum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index 78816ec88751..37807f23231e 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -539,6 +539,10 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type { + #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) + #define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383) + #define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_MPEG_BASE+384) ++#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+385) ++#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+386) ++#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+387) ++#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+388) + #define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) + #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) + #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +-- +2.21.0 + +From 26fae7a41313506931c9be5f532c12d8d654f153 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 2 Apr 2019 23:06:22 +0200 +Subject: [PATCH] clk: sunxi-ng: h6: Preset hdmi-cec clock parent + +H6 manual and BSP clock driver both states that hdmi-cec clock has two +possible parents, osc32k and pll-periph0-2x with 36621 predivider. +Because pll-periph0-2x is always 1.2 GHz, both parents give same +hdmi-cec rate - 32768 Hz, which is exactly the rate needed for HDMI CEC +controller to operate correctly. + +However, for some reason, HDMI CEC controller doesn't work if default +parent (osc32k) is used. BSP HDMI driver also always use pll-periph0-2x +as hdmi-cec clock parent. + +In order to solve the issue, preset hdmi-cec clock parent to +pll-periph0-2x. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index daf78966555e..33980067b06e 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -656,6 +656,8 @@ static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; + static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { + { .index = 1, .div = 36621 }, + }; ++ ++#define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10 + static struct ccu_mux hdmi_cec_clk = { + .enable = BIT(31), + +@@ -1200,6 +1202,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) + val &= ~(GENMASK(21, 16) | BIT(0)); + writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); + ++ /* ++ * First clock parent (osc32K) is unusable for CEC. But since there ++ * is no good way to force parent switch (both run with same frequency), ++ * just set second clock parent here. ++ */ ++ val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); ++ val |= BIT(24); ++ writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); ++ + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); + } + +-- +2.21.0 + +From 6597ce3de9e443f0cab693496fc529f55ae6eb01 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Wed, 3 Apr 2019 17:14:03 +0200 +Subject: [PATCH] clk: sunxi-ng: h6: Allow video & vpu clocks to change parent + rate + +Video related clocks need to set rate as close as possible to the +requested one, so they should be able to change parent clock rate. + +When processing 4K video, VPU clock has to be set to higher rate than it +is default parent rate. Because of that, VPU clock should be able to +change parent clock rate. + +Add CLK_SET_RATE_PARENT flag to tcon-lcd0, tcon-tv0 and ve. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 33980067b06e..3c32d7798f27 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, + 0, 3, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", + 0x69c, BIT(0), 0); +@@ -691,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", + tcon_lcd0_parents, 0xb60, + 24, 3, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", + 0xb7c, BIT(0), 0); +@@ -706,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", + 0xb9c, BIT(0), 0); +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch b/projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch deleted file mode 100644 index 0744eecd7a..0000000000 --- a/projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch +++ /dev/null @@ -1,1571 +0,0 @@ -From e2d8ffe2e76028457759988ba6216fd13eeea01b Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Tue, 13 Nov 2018 03:52:18 -0500 -Subject: [PATCH] media: v4l2-mem2mem: add v4l2_m2m_buf_copy_data helper - function - -Memory-to-memory devices should copy various parts of -struct v4l2_buffer from the output buffer to the capture buffer. - -Add a helper function that does that to simplify the driver code. - -Signed-off-by: Hans Verkuil -Reviewed-by: Paul Kocialkowski -Reviewed-by: Alexandre Courbot -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-mem2mem.c | 20 ++++++++++++++++++++ - include/media/v4l2-mem2mem.h | 20 ++++++++++++++++++++ - 2 files changed, 40 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c -index 5bbdec55b7d7..631f4e2aa942 100644 ---- a/drivers/media/v4l2-core/v4l2-mem2mem.c -+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c -@@ -975,6 +975,26 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx, - } - EXPORT_SYMBOL_GPL(v4l2_m2m_buf_queue); - -+void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, -+ struct vb2_v4l2_buffer *cap_vb, -+ bool copy_frame_flags) -+{ -+ u32 mask = V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK; -+ -+ if (copy_frame_flags) -+ mask |= V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_PFRAME | -+ V4L2_BUF_FLAG_BFRAME; -+ -+ cap_vb->vb2_buf.timestamp = out_vb->vb2_buf.timestamp; -+ -+ if (out_vb->flags & V4L2_BUF_FLAG_TIMECODE) -+ cap_vb->timecode = out_vb->timecode; -+ cap_vb->field = out_vb->field; -+ cap_vb->flags &= ~mask; -+ cap_vb->flags |= out_vb->flags & mask; -+} -+EXPORT_SYMBOL_GPL(v4l2_m2m_buf_copy_data); -+ - void v4l2_m2m_request_queue(struct media_request *req) - { - struct media_request_object *obj, *obj_safe; -diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h -index 5467264771ec..43e447dcf69d 100644 ---- a/include/media/v4l2-mem2mem.h -+++ b/include/media/v4l2-mem2mem.h -@@ -622,6 +622,26 @@ v4l2_m2m_dst_buf_remove_by_idx(struct v4l2_m2m_ctx *m2m_ctx, unsigned int idx) - return v4l2_m2m_buf_remove_by_idx(&m2m_ctx->cap_q_ctx, idx); - } - -+/** -+ * v4l2_m2m_buf_copy_data() - copy buffer data from the output buffer to the -+ * capture buffer -+ * -+ * @out_vb: the output buffer that is the source of the data. -+ * @cap_vb: the capture buffer that will receive the data. -+ * @copy_frame_flags: copy the KEY/B/PFRAME flags as well. -+ * -+ * This helper function copies the timestamp, timecode (if the TIMECODE -+ * buffer flag was set), field and the TIMECODE, KEYFRAME, BFRAME, PFRAME -+ * and TSTAMP_SRC_MASK flags from @out_vb to @cap_vb. -+ * -+ * If @copy_frame_flags is false, then the KEYFRAME, BFRAME and PFRAME -+ * flags are not copied. This is typically needed for encoders that -+ * set this bits explicitly. -+ */ -+void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, -+ struct vb2_v4l2_buffer *cap_vb, -+ bool copy_frame_flags); -+ - /* v4l2 request helper */ - - void v4l2_m2m_request_queue(struct media_request *req); --- -2.20.1 - -From c2eb8effb265ac5cdd960d8e61ecb931e9c767cd Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Wed, 24 Oct 2018 06:50:34 -0400 -Subject: [PATCH] media: videodev2.h: add v4l2_timeval_to_ns inline function - -We want to be able to uniquely identify buffers for stateless -codecs. The internal timestamp (a u64) as stored internally in the -kernel is a suitable candidate for that, but in struct v4l2_buffer -it is represented as a struct timeval. - -Add a v4l2_timeval_to_ns() function that converts the struct timeval -into a u64 in the same way that the kernel does. This makes it possible -to use this u64 elsewhere as a unique identifier of the buffer. - -Since timestamps are also copied from the output buffer to the -corresponding capture buffer(s) by M2M devices, the u64 can be -used to refer to both output and capture buffers. - -The plan is that in the future we redesign struct v4l2_buffer and use -u64 for the timestamp instead of a struct timeval (which has lots of -problems with 32 vs 64 bit and y2038 layout changes), and then there -is no more need to use this function. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - include/uapi/linux/videodev2.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index b5671ce2724f..d6eed479c3a6 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -973,6 +973,18 @@ struct v4l2_buffer { - }; - }; - -+/** -+ * v4l2_timeval_to_ns - Convert timeval to nanoseconds -+ * @ts: pointer to the timeval variable to be converted -+ * -+ * Returns the scalar nanosecond representation of the timeval -+ * parameter. -+ */ -+static inline __u64 v4l2_timeval_to_ns(const struct timeval *tv) -+{ -+ return (__u64)tv->tv_sec * 1000000000ULL + tv->tv_usec * 1000; -+} -+ - /* Flags for 'flags' field */ - /* Buffer is mapped (flag) */ - #define V4L2_BUF_FLAG_MAPPED 0x00000001 --- -2.20.1 - -From 245ede423b43a6e081e94e0e5d4e895bd1f31228 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Wed, 24 Oct 2018 06:51:01 -0400 -Subject: [PATCH] media: vb2: add vb2_find_timestamp() - -Use v4l2_timeval_to_ns instead of timeval_to_ns to ensure that -both kernelspace and userspace will use the same conversion -function. - -Next add a new vb2_find_timestamp() function to find buffers -with a specific timestamp. - -This function will only look at DEQUEUED and DONE buffers, i.e. -buffers that are already processed. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/common/videobuf2/videobuf2-v4l2.c | 19 ++++++++++++++++++- - include/media/videobuf2-v4l2.h | 17 +++++++++++++++++ - 2 files changed, 35 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c -index 3a0ca2f9854f..75ea90e795d8 100644 ---- a/drivers/media/common/videobuf2/videobuf2-v4l2.c -+++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c -@@ -143,7 +143,7 @@ static void __copy_timestamp(struct vb2_buffer *vb, const void *pb) - * and the timecode field and flag if needed. - */ - if (q->copy_timestamp) -- vb->timestamp = timeval_to_ns(&b->timestamp); -+ vb->timestamp = v4l2_timeval_to_ns(&b->timestamp); - vbuf->flags |= b->flags & V4L2_BUF_FLAG_TIMECODE; - if (b->flags & V4L2_BUF_FLAG_TIMECODE) - vbuf->timecode = b->timecode; -@@ -589,6 +589,23 @@ static const struct vb2_buf_ops v4l2_buf_ops = { - .copy_timestamp = __copy_timestamp, - }; - -+int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp, -+ unsigned int start_idx) -+{ -+ unsigned int i; -+ -+ for (i = start_idx; i < q->num_buffers; i++) { -+ struct vb2_buffer *vb = q->bufs[i]; -+ -+ if ((vb->state == VB2_BUF_STATE_DEQUEUED || -+ vb->state == VB2_BUF_STATE_DONE) && -+ vb->timestamp == timestamp) -+ return i; -+ } -+ return -1; -+} -+EXPORT_SYMBOL_GPL(vb2_find_timestamp); -+ - /* - * vb2_querybuf() - query video buffer information - * @q: videobuf queue -diff --git a/include/media/videobuf2-v4l2.h b/include/media/videobuf2-v4l2.h -index 727855463838..a9961bc776dc 100644 ---- a/include/media/videobuf2-v4l2.h -+++ b/include/media/videobuf2-v4l2.h -@@ -55,6 +55,23 @@ struct vb2_v4l2_buffer { - #define to_vb2_v4l2_buffer(vb) \ - container_of(vb, struct vb2_v4l2_buffer, vb2_buf) - -+/** -+ * vb2_find_timestamp() - Find buffer with given timestamp in the queue -+ * -+ * @q: pointer to &struct vb2_queue with videobuf2 queue. -+ * @timestamp: the timestamp to find. Only buffers in state DEQUEUED or DONE -+ * are considered. -+ * @start_idx: the start index (usually 0) in the buffer array to start -+ * searching from. Note that there may be multiple buffers -+ * with the same timestamp value, so you can restart the search -+ * by setting @start_idx to the previously found index + 1. -+ * -+ * Returns the buffer index of the buffer with the given @timestamp, or -+ * -1 if no buffer with @timestamp was found. -+ */ -+int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp, -+ unsigned int start_idx); -+ - int vb2_querybuf(struct vb2_queue *q, struct v4l2_buffer *b); - - /** --- -2.20.1 - -From d998e03e322fc497454f584adfc35743713a44c5 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Fri, 9 Nov 2018 04:16:21 -0500 -Subject: [PATCH] media: cedrus: identify buffers by timestamp - -Use the new v4l2_m2m_buf_copy_data helper function and use -timestamps to refer to reference frames instead of using -buffer indices. - -Also remove the padding fields in the structs, that's a bad -idea. Just use the right types to keep everything aligned. - -Signed-off-by: Hans Verkuil -Tested-by: Paul Kocialkowski -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-ctrls.c | 9 -------- - drivers/staging/media/sunxi/cedrus/cedrus.h | 9 +++++--- - .../staging/media/sunxi/cedrus/cedrus_dec.c | 2 ++ - .../staging/media/sunxi/cedrus/cedrus_mpeg2.c | 23 +++++++++---------- - include/media/mpeg2-ctrls.h | 14 ++++------- - 5 files changed, 24 insertions(+), 33 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 5e3806feb5d7..e3bd441fa29a 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1661,15 +1661,6 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, - return -EINVAL; - } - -- if (p_mpeg2_slice_params->backward_ref_index >= VIDEO_MAX_FRAME || -- p_mpeg2_slice_params->forward_ref_index >= VIDEO_MAX_FRAME) -- return -EINVAL; -- -- if (p_mpeg2_slice_params->pad || -- p_mpeg2_slice_params->picture.pad || -- p_mpeg2_slice_params->sequence.pad) -- return -EINVAL; -- - return 0; - - case V4L2_CTRL_TYPE_MPEG2_QUANTIZATION: -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 3acfdcf83691..4aedd24a9848 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -140,11 +140,14 @@ static inline dma_addr_t cedrus_buf_addr(struct vb2_buffer *buf, - } - - static inline dma_addr_t cedrus_dst_buf_addr(struct cedrus_ctx *ctx, -- unsigned int index, -- unsigned int plane) -+ int index, unsigned int plane) - { -- struct vb2_buffer *buf = ctx->dst_bufs[index]; -+ struct vb2_buffer *buf; - -+ if (index < 0) -+ return 0; -+ -+ buf = ctx->dst_bufs[index]; - return buf ? cedrus_buf_addr(buf, &ctx->dst_fmt, plane) : 0; - } - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index 591d191d4286..443fb037e1cf 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -50,6 +50,8 @@ void cedrus_device_run(void *priv) - break; - } - -+ v4l2_m2m_buf_copy_data(run.src, run.dst, true); -+ - dev->dec_ops[ctx->current_codec]->setup(ctx, &run); - - /* Complete request(s) controls if needed. */ -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -index 9abd39cae38c..cb45fda9aaeb 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -@@ -82,7 +82,10 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) - dma_addr_t fwd_luma_addr, fwd_chroma_addr; - dma_addr_t bwd_luma_addr, bwd_chroma_addr; - struct cedrus_dev *dev = ctx->dev; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; - const u8 *matrix; -+ int forward_idx; -+ int backward_idx; - unsigned int i; - u32 reg; - -@@ -156,23 +159,19 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) - cedrus_write(dev, VE_DEC_MPEG_PICBOUNDSIZE, reg); - - /* Forward and backward prediction reference buffers. */ -+ forward_idx = vb2_find_timestamp(cap_q, -+ slice_params->forward_ref_ts, 0); - -- fwd_luma_addr = cedrus_dst_buf_addr(ctx, -- slice_params->forward_ref_index, -- 0); -- fwd_chroma_addr = cedrus_dst_buf_addr(ctx, -- slice_params->forward_ref_index, -- 1); -+ fwd_luma_addr = cedrus_dst_buf_addr(ctx, forward_idx, 0); -+ fwd_chroma_addr = cedrus_dst_buf_addr(ctx, forward_idx, 1); - - cedrus_write(dev, VE_DEC_MPEG_FWD_REF_LUMA_ADDR, fwd_luma_addr); - cedrus_write(dev, VE_DEC_MPEG_FWD_REF_CHROMA_ADDR, fwd_chroma_addr); - -- bwd_luma_addr = cedrus_dst_buf_addr(ctx, -- slice_params->backward_ref_index, -- 0); -- bwd_chroma_addr = cedrus_dst_buf_addr(ctx, -- slice_params->backward_ref_index, -- 1); -+ backward_idx = vb2_find_timestamp(cap_q, -+ slice_params->backward_ref_ts, 0); -+ bwd_luma_addr = cedrus_dst_buf_addr(ctx, backward_idx, 0); -+ bwd_chroma_addr = cedrus_dst_buf_addr(ctx, backward_idx, 1); - - cedrus_write(dev, VE_DEC_MPEG_BWD_REF_LUMA_ADDR, bwd_luma_addr); - cedrus_write(dev, VE_DEC_MPEG_BWD_REF_CHROMA_ADDR, bwd_chroma_addr); -diff --git a/include/media/mpeg2-ctrls.h b/include/media/mpeg2-ctrls.h -index d21f40edc09e..6601455b3d5e 100644 ---- a/include/media/mpeg2-ctrls.h -+++ b/include/media/mpeg2-ctrls.h -@@ -30,10 +30,9 @@ struct v4l2_mpeg2_sequence { - __u32 vbv_buffer_size; - - /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence extension */ -- __u8 profile_and_level_indication; -+ __u16 profile_and_level_indication; - __u8 progressive_sequence; - __u8 chroma_format; -- __u8 pad; - }; - - struct v4l2_mpeg2_picture { -@@ -51,23 +50,20 @@ struct v4l2_mpeg2_picture { - __u8 intra_vlc_format; - __u8 alternate_scan; - __u8 repeat_first_field; -- __u8 progressive_frame; -- __u8 pad; -+ __u16 progressive_frame; - }; - - struct v4l2_ctrl_mpeg2_slice_params { - __u32 bit_size; - __u32 data_bit_offset; -+ __u64 backward_ref_ts; -+ __u64 forward_ref_ts; - - struct v4l2_mpeg2_sequence sequence; - struct v4l2_mpeg2_picture picture; - - /* ISO/IEC 13818-2, ITU-T Rec. H.262: Slice */ -- __u8 quantiser_scale_code; -- -- __u8 backward_ref_index; -- __u8 forward_ref_index; -- __u8 pad; -+ __u32 quantiser_scale_code; - }; - - struct v4l2_ctrl_mpeg2_quantization { --- -2.20.1 - -From 03535e7a3a9937da99ee18304309e0574d2504fc Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Thu, 24 Jan 2019 06:47:49 -0200 -Subject: [PATCH] media: vb2: vb2_find_timestamp: drop restriction on buffer - state - -There really is no reason why vb2_find_timestamp can't just find -buffers in any state. Drop that part of the test. - -This also means that vb->timestamp should only be set to 0 when -the driver doesn't copy timestamps. - -This change allows for more efficient pipelining (i.e. you can use -a buffer for a reference frame even when it is queued). - -Signed-off-by: Hans Verkuil -Reviewed-by: Tomasz Figa -Reviewed-by: Alexandre Courbot -Reviewed-by: Paul Kocialkowski -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/common/videobuf2/videobuf2-v4l2.c | 11 +++-------- - include/media/videobuf2-v4l2.h | 3 +-- - 2 files changed, 4 insertions(+), 10 deletions(-) - -diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c -index 75ea90e795d8..2f3b3ca5bde6 100644 ---- a/drivers/media/common/videobuf2/videobuf2-v4l2.c -+++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c -@@ -567,7 +567,7 @@ static int __fill_vb2_buffer(struct vb2_buffer *vb, struct vb2_plane *planes) - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); - unsigned int plane; - -- if (!vb->vb2_queue->is_output || !vb->vb2_queue->copy_timestamp) -+ if (!vb->vb2_queue->copy_timestamp) - vb->timestamp = 0; - - for (plane = 0; plane < vb->num_planes; ++plane) { -@@ -594,14 +594,9 @@ int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp, - { - unsigned int i; - -- for (i = start_idx; i < q->num_buffers; i++) { -- struct vb2_buffer *vb = q->bufs[i]; -- -- if ((vb->state == VB2_BUF_STATE_DEQUEUED || -- vb->state == VB2_BUF_STATE_DONE) && -- vb->timestamp == timestamp) -+ for (i = start_idx; i < q->num_buffers; i++) -+ if (q->bufs[i]->timestamp == timestamp) - return i; -- } - return -1; - } - EXPORT_SYMBOL_GPL(vb2_find_timestamp); -diff --git a/include/media/videobuf2-v4l2.h b/include/media/videobuf2-v4l2.h -index a9961bc776dc..8a10889dc2fd 100644 ---- a/include/media/videobuf2-v4l2.h -+++ b/include/media/videobuf2-v4l2.h -@@ -59,8 +59,7 @@ struct vb2_v4l2_buffer { - * vb2_find_timestamp() - Find buffer with given timestamp in the queue - * - * @q: pointer to &struct vb2_queue with videobuf2 queue. -- * @timestamp: the timestamp to find. Only buffers in state DEQUEUED or DONE -- * are considered. -+ * @timestamp: the timestamp to find. - * @start_idx: the start index (usually 0) in the buffer array to start - * searching from. Note that there may be multiple buffers - * with the same timestamp value, so you can restart the search --- -2.20.1 - -From 2cc1802f62e562611e86f04d9dae1337c824991e Mon Sep 17 00:00:00 2001 -From: Pawel Osciak -Date: Thu, 24 Jan 2019 07:51:55 -0200 -Subject: [PATCH] media: vb2: Keep dma-buf buffers mapped until they are freed - -When using vb2 for video decoding, dequeued capture buffers may still -be accessed by the hardware: this is the case when they are used as -reference frames for decoding subsequent frames. - -When the buffer is imported with dma-buf, it needs to be mapped before -access. Until now, it was mapped when queuing and unmapped when -dequeuing, which doesn't work for access as a reference frames. - -One way to solve this would be to map the buffer again when it is -needed as a reference, but the mapping/unmapping operations can -seriously impact performance. As a result, map the buffer once (when it -is first needed when queued) and keep it mapped until it is freed. - -Reviewed-on: https://chromium-review.googlesource.com/334103 -[Paul: Updated for mainline and changed commit message] - -Signed-off-by: Pawel Osciak -Signed-off-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/common/videobuf2/videobuf2-core.c | 11 +++-------- - 1 file changed, 3 insertions(+), 8 deletions(-) - -diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c -index 70e8c3366f9c..ce9294a635cc 100644 ---- a/drivers/media/common/videobuf2/videobuf2-core.c -+++ b/drivers/media/common/videobuf2/videobuf2-core.c -@@ -1196,6 +1196,9 @@ static int __prepare_dmabuf(struct vb2_buffer *vb) - * userspace knows sooner rather than later if the dma-buf map fails. - */ - for (plane = 0; plane < vb->num_planes; ++plane) { -+ if (vb->planes[plane].dbuf_mapped) -+ continue; -+ - ret = call_memop(vb, map_dmabuf, vb->planes[plane].mem_priv); - if (ret) { - dprintk(1, "failed to map dmabuf for plane %d\n", -@@ -1758,14 +1761,6 @@ static void __vb2_dqbuf(struct vb2_buffer *vb) - - vb->state = VB2_BUF_STATE_DEQUEUED; - -- /* unmap DMABUF buffer */ -- if (q->memory == VB2_MEMORY_DMABUF) -- for (i = 0; i < vb->num_planes; ++i) { -- if (!vb->planes[i].dbuf_mapped) -- continue; -- call_void_memop(vb, unmap_dmabuf, vb->planes[i].mem_priv); -- vb->planes[i].dbuf_mapped = 0; -- } - call_void_bufop(q, init_buffer, vb); - } - --- -2.20.1 - -From 6f2c6afa79e0513d339871337bfc8c6c621d3ab1 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 21 Dec 2018 11:56:41 -0500 -Subject: [PATCH] media: sunxi: cedrus: Fix missing error message context - -When cedrus_hw_probe is called, v4l2_dev is not yet initialized. -Use dev_err instead. - -Signed-off-by: Ondrej Jirman -Acked-by: Paul Kocialkowski -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/sunxi/cedrus/cedrus_hw.c | 28 +++++++++---------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index 300339fee1bc..0acf219a8c91 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -157,14 +157,14 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - - irq_dec = platform_get_irq(dev->pdev, 0); - if (irq_dec <= 0) { -- v4l2_err(&dev->v4l2_dev, "Failed to get IRQ\n"); -+ dev_err(dev->dev, "Failed to get IRQ\n"); - - return irq_dec; - } - ret = devm_request_irq(dev->dev, irq_dec, cedrus_irq, - 0, dev_name(dev->dev), dev); - if (ret) { -- v4l2_err(&dev->v4l2_dev, "Failed to request IRQ\n"); -+ dev_err(dev->dev, "Failed to request IRQ\n"); - - return ret; - } -@@ -182,21 +182,21 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - - ret = of_reserved_mem_device_init(dev->dev); - if (ret && ret != -ENODEV) { -- v4l2_err(&dev->v4l2_dev, "Failed to reserve memory\n"); -+ dev_err(dev->dev, "Failed to reserve memory\n"); - - return ret; - } - - ret = sunxi_sram_claim(dev->dev); - if (ret) { -- v4l2_err(&dev->v4l2_dev, "Failed to claim SRAM\n"); -+ dev_err(dev->dev, "Failed to claim SRAM\n"); - - goto err_mem; - } - - dev->ahb_clk = devm_clk_get(dev->dev, "ahb"); - if (IS_ERR(dev->ahb_clk)) { -- v4l2_err(&dev->v4l2_dev, "Failed to get AHB clock\n"); -+ dev_err(dev->dev, "Failed to get AHB clock\n"); - - ret = PTR_ERR(dev->ahb_clk); - goto err_sram; -@@ -204,7 +204,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - - dev->mod_clk = devm_clk_get(dev->dev, "mod"); - if (IS_ERR(dev->mod_clk)) { -- v4l2_err(&dev->v4l2_dev, "Failed to get MOD clock\n"); -+ dev_err(dev->dev, "Failed to get MOD clock\n"); - - ret = PTR_ERR(dev->mod_clk); - goto err_sram; -@@ -212,7 +212,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - - dev->ram_clk = devm_clk_get(dev->dev, "ram"); - if (IS_ERR(dev->ram_clk)) { -- v4l2_err(&dev->v4l2_dev, "Failed to get RAM clock\n"); -+ dev_err(dev->dev, "Failed to get RAM clock\n"); - - ret = PTR_ERR(dev->ram_clk); - goto err_sram; -@@ -220,7 +220,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - - dev->rstc = devm_reset_control_get(dev->dev, NULL); - if (IS_ERR(dev->rstc)) { -- v4l2_err(&dev->v4l2_dev, "Failed to get reset control\n"); -+ dev_err(dev->dev, "Failed to get reset control\n"); - - ret = PTR_ERR(dev->rstc); - goto err_sram; -@@ -229,7 +229,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - res = platform_get_resource(dev->pdev, IORESOURCE_MEM, 0); - dev->base = devm_ioremap_resource(dev->dev, res); - if (IS_ERR(dev->base)) { -- v4l2_err(&dev->v4l2_dev, "Failed to map registers\n"); -+ dev_err(dev->dev, "Failed to map registers\n"); - - ret = PTR_ERR(dev->base); - goto err_sram; -@@ -237,35 +237,35 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - - ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT); - if (ret) { -- v4l2_err(&dev->v4l2_dev, "Failed to set clock rate\n"); -+ dev_err(dev->dev, "Failed to set clock rate\n"); - - goto err_sram; - } - - ret = clk_prepare_enable(dev->ahb_clk); - if (ret) { -- v4l2_err(&dev->v4l2_dev, "Failed to enable AHB clock\n"); -+ dev_err(dev->dev, "Failed to enable AHB clock\n"); - - goto err_sram; - } - - ret = clk_prepare_enable(dev->mod_clk); - if (ret) { -- v4l2_err(&dev->v4l2_dev, "Failed to enable MOD clock\n"); -+ dev_err(dev->dev, "Failed to enable MOD clock\n"); - - goto err_ahb_clk; - } - - ret = clk_prepare_enable(dev->ram_clk); - if (ret) { -- v4l2_err(&dev->v4l2_dev, "Failed to enable RAM clock\n"); -+ dev_err(dev->dev, "Failed to enable RAM clock\n"); - - goto err_mod_clk; - } - - ret = reset_control_reset(dev->rstc); - if (ret) { -- v4l2_err(&dev->v4l2_dev, "Failed to apply reset\n"); -+ dev_err(dev->dev, "Failed to apply reset\n"); - - goto err_ram_clk; - } --- -2.20.1 - -From 6f4b9d9a6c08f692f627700c2d0e250e406ac81f Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Wed, 9 Jan 2019 12:19:19 -0200 -Subject: [PATCH] media: cedrus: Cleanup duplicate declarations from cedrus_dec - header - -Some leftover declarations are still in the cedrus_dec header although -they were moved to cedrus_video already. Clean them up. - -Signed-off-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_dec.h | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.h b/drivers/staging/media/sunxi/cedrus/cedrus_dec.h -index 4f423d3a1cad..d1ae7903677b 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.h -@@ -16,12 +16,6 @@ - #ifndef _CEDRUS_DEC_H_ - #define _CEDRUS_DEC_H_ - --extern const struct v4l2_ioctl_ops cedrus_ioctl_ops; -- --void cedrus_device_work(struct work_struct *work); - void cedrus_device_run(void *priv); - --int cedrus_queue_init(void *priv, struct vb2_queue *src_vq, -- struct vb2_queue *dst_vq); -- - #endif --- -2.20.1 - -From 55ea54441fb3b6532d5d32417911ff5a10750903 Mon Sep 17 00:00:00 2001 -From: Christoph Hellwig -Date: Fri, 4 Jan 2019 10:42:49 +0100 -Subject: [PATCH] videobuf2: replace a layering violation with dma_map_resource - -vb2_dc_get_userptr pokes into arm direct mapping details to get the -resemblance of a dma address for a a physical address that does is -not backed by a page struct. Not only is this not portable to other -architectures with dma direct mapping offsets, but also not to uses -of IOMMUs of any kind. Switch to the proper dma_map_resource / -dma_unmap_resource interface instead. - -Signed-off-by: Christoph Hellwig -Acked-by: Mauro Carvalho Chehab -Tested-by: Marek Szyprowski ---- - .../common/videobuf2/videobuf2-dma-contig.c | 41 ++++--------------- - 1 file changed, 9 insertions(+), 32 deletions(-) - -diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c -index aff0ab7bf83d..82389aead6ed 100644 ---- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c -+++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c -@@ -439,42 +439,14 @@ static void vb2_dc_put_userptr(void *buf_priv) - set_page_dirty_lock(pages[i]); - sg_free_table(sgt); - kfree(sgt); -+ } else { -+ dma_unmap_resource(buf->dev, buf->dma_addr, buf->size, -+ buf->dma_dir, 0); - } - vb2_destroy_framevec(buf->vec); - kfree(buf); - } - --/* -- * For some kind of reserved memory there might be no struct page available, -- * so all that can be done to support such 'pages' is to try to convert -- * pfn to dma address or at the last resort just assume that -- * dma address == physical address (like it has been assumed in earlier version -- * of videobuf2-dma-contig -- */ -- --#ifdef __arch_pfn_to_dma --static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) --{ -- return (dma_addr_t)__arch_pfn_to_dma(dev, pfn); --} --#elif defined(__pfn_to_bus) --static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) --{ -- return (dma_addr_t)__pfn_to_bus(pfn); --} --#elif defined(__pfn_to_phys) --static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) --{ -- return (dma_addr_t)__pfn_to_phys(pfn); --} --#else --static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) --{ -- /* really, we cannot do anything better at this point */ -- return (dma_addr_t)(pfn) << PAGE_SHIFT; --} --#endif -- - static void *vb2_dc_get_userptr(struct device *dev, unsigned long vaddr, - unsigned long size, enum dma_data_direction dma_dir) - { -@@ -528,7 +500,12 @@ static void *vb2_dc_get_userptr(struct device *dev, unsigned long vaddr, - for (i = 1; i < n_pages; i++) - if (nums[i-1] + 1 != nums[i]) - goto fail_pfnvec; -- buf->dma_addr = vb2_dc_pfn_to_dma(buf->dev, nums[0]); -+ buf->dma_addr = dma_map_resource(buf->dev, -+ __pfn_to_phys(nums[0]), size, buf->dma_dir, 0); -+ if (dma_mapping_error(buf->dev, buf->dma_addr)) { -+ ret = -ENOMEM; -+ goto fail_pfnvec; -+ } - goto out; - } - --- -2.20.1 - -From 28d77c21cbeb2c6039d48ef88401b87a56a7a07f Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Wed, 16 Jan 2019 10:01:13 -0200 -Subject: [PATCH] media: vb2: add buf_out_validate callback - -When queueing a buffer to a request the 'field' value is not validated. -That field is only validated when the _buf_prepare() is called, -which happens when the request is queued. - -However, this validation should happen at QBUF time, since you want -to know about this as soon as possible. Also, the spec requires that -the 'field' value is validated at QBUF time. - -This patch adds a new buf_out_validate callback to validate the -output buffer at buf_prepare time or when QBUF queues an unprepared -buffer to a request. This callback is mandatory for output queues -that support requests. - -This issue was found by v4l2-compliance since it failed to replace -V4L2_FIELD_ANY by a proper field value when testing the vivid video -output in combination with requests. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/common/videobuf2/videobuf2-core.c | 22 ++++++++++++++++--- - include/media/videobuf2-core.h | 5 +++++ - 2 files changed, 24 insertions(+), 3 deletions(-) - -diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c -index ce9294a635cc..e07b6bdb6982 100644 ---- a/drivers/media/common/videobuf2/videobuf2-core.c -+++ b/drivers/media/common/videobuf2/videobuf2-core.c -@@ -499,9 +499,9 @@ static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers) - pr_info(" buf_init: %u buf_cleanup: %u buf_prepare: %u buf_finish: %u\n", - vb->cnt_buf_init, vb->cnt_buf_cleanup, - vb->cnt_buf_prepare, vb->cnt_buf_finish); -- pr_info(" buf_queue: %u buf_done: %u buf_request_complete: %u\n", -- vb->cnt_buf_queue, vb->cnt_buf_done, -- vb->cnt_buf_request_complete); -+ pr_info(" buf_out_validate: %u buf_queue: %u buf_done: %u buf_request_complete: %u\n", -+ vb->cnt_buf_out_validate, vb->cnt_buf_queue, -+ vb->cnt_buf_done, vb->cnt_buf_request_complete); - pr_info(" alloc: %u put: %u prepare: %u finish: %u mmap: %u\n", - vb->cnt_mem_alloc, vb->cnt_mem_put, - vb->cnt_mem_prepare, vb->cnt_mem_finish, -@@ -1277,6 +1277,14 @@ static int __buf_prepare(struct vb2_buffer *vb) - return 0; - WARN_ON(vb->synced); - -+ if (q->is_output) { -+ ret = call_vb_qop(vb, buf_out_validate, vb); -+ if (ret) { -+ dprintk(1, "buffer validation failed\n"); -+ return ret; -+ } -+ } -+ - vb->state = VB2_BUF_STATE_PREPARING; - - switch (q->memory) { -@@ -1523,6 +1531,14 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb, - return -EINVAL; - } - -+ if (q->is_output && !vb->prepared) { -+ ret = call_vb_qop(vb, buf_out_validate, vb); -+ if (ret) { -+ dprintk(1, "buffer validation failed\n"); -+ return ret; -+ } -+ } -+ - media_request_object_init(&vb->req_obj); - - /* Make sure the request is in a safe state for updating. */ -diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h -index 4a737b2c610b..4849b865b908 100644 ---- a/include/media/videobuf2-core.h -+++ b/include/media/videobuf2-core.h -@@ -296,6 +296,7 @@ struct vb2_buffer { - u32 cnt_mem_num_users; - u32 cnt_mem_mmap; - -+ u32 cnt_buf_out_validate; - u32 cnt_buf_init; - u32 cnt_buf_prepare; - u32 cnt_buf_finish; -@@ -342,6 +343,9 @@ struct vb2_buffer { - * @wait_finish: reacquire all locks released in the previous callback; - * required to continue operation after sleeping while - * waiting for a new buffer to arrive. -+ * @buf_out_validate: called when the output buffer is prepared or queued -+ * to a request; drivers can use this to validate -+ * userspace-provided information; optional. - * @buf_init: called once after allocating a buffer (in MMAP case) - * or after acquiring a new USERPTR buffer; drivers may - * perform additional buffer-related initialization; -@@ -409,6 +413,7 @@ struct vb2_ops { - void (*wait_prepare)(struct vb2_queue *q); - void (*wait_finish)(struct vb2_queue *q); - -+ int (*buf_out_validate)(struct vb2_buffer *vb); - int (*buf_init)(struct vb2_buffer *vb); - int (*buf_prepare)(struct vb2_buffer *vb); - void (*buf_finish)(struct vb2_buffer *vb); --- -2.20.1 - -From 1284ed59a147c27cb882e49213571f7d52976eb5 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Wed, 16 Jan 2019 10:01:17 -0200 -Subject: [PATCH] media: vb2: check that buf_out_validate is present - -The buf_out_validate is required for output queues in combination -with requests. Check this. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/common/videobuf2/videobuf2-v4l2.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c -index 2f3b3ca5bde6..3aeaea3af42a 100644 ---- a/drivers/media/common/videobuf2/videobuf2-v4l2.c -+++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c -@@ -409,6 +409,15 @@ static int vb2_queue_or_prepare_buf(struct vb2_queue *q, struct media_device *md - */ - if (WARN_ON(!q->ops->buf_request_complete)) - return -EINVAL; -+ /* -+ * Make sure this op is implemented by the driver for the output queue. -+ * It's easy to forget this callback, but is it important to correctly -+ * validate the 'field' value at QBUF time. -+ */ -+ if (WARN_ON((q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT || -+ q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) && -+ !q->ops->buf_out_validate)) -+ return -EINVAL; - - if (vb->state != VB2_BUF_STATE_DEQUEUED) { - dprintk(1, "%s: buffer is not in dequeued state\n", opname); --- -2.20.1 - -From 6b3e4c4cc162390b833e57de656644786ca88919 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Wed, 16 Jan 2019 10:01:16 -0200 -Subject: [PATCH] media: cedrus: add buf_out_validate callback - -Validate the field for an output buffer. This ensures that the -field is validated when the buffer is queued to a request, and -not when the request itself is queued, which is too late. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_video.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index 8721b4a7d496..b5cc79389d67 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -416,6 +416,14 @@ static void cedrus_buf_cleanup(struct vb2_buffer *vb) - ctx->dst_bufs[vb->index] = NULL; - } - -+static int cedrus_buf_out_validate(struct vb2_buffer *vb) -+{ -+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); -+ -+ vbuf->field = V4L2_FIELD_NONE; -+ return 0; -+} -+ - static int cedrus_buf_prepare(struct vb2_buffer *vb) - { - struct vb2_queue *vq = vb->vb2_queue; -@@ -493,6 +501,7 @@ static struct vb2_ops cedrus_qops = { - .buf_init = cedrus_buf_init, - .buf_cleanup = cedrus_buf_cleanup, - .buf_queue = cedrus_buf_queue, -+ .buf_out_validate = cedrus_buf_out_validate, - .buf_request_complete = cedrus_buf_request_complete, - .start_streaming = cedrus_start_streaming, - .stop_streaming = cedrus_stop_streaming, --- -2.20.1 - -From a4d3d61254d3645d8de738102c3c473b176180a5 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 5 Feb 2019 16:20:33 -0500 -Subject: [PATCH] media: v4l2-mem2mem: Rename v4l2_m2m_buf_copy_data to - v4l2_m2m_buf_copy_metadata - -The v4l2_m2m_buf_copy_data helper is used to copy the buffer -metadata, such as its timestamp and its flags. - -Therefore, the v4l2_m2m_buf_copy_metadata name is more clear -and avoids confusion with a payload data copy. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -[hverkuil-cisco@xs4all.nl: also fix cedrus_dec.c] -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-mem2mem.c | 8 ++++---- - drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 2 +- - include/media/v4l2-mem2mem.h | 14 +++++++------- - 5 files changed, 15 insertions(+), 15 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c -index 631f4e2aa942..1494d0d5951a 100644 ---- a/drivers/media/v4l2-core/v4l2-mem2mem.c -+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c -@@ -975,9 +975,9 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx, - } - EXPORT_SYMBOL_GPL(v4l2_m2m_buf_queue); - --void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, -- struct vb2_v4l2_buffer *cap_vb, -- bool copy_frame_flags) -+void v4l2_m2m_buf_copy_metadata(const struct vb2_v4l2_buffer *out_vb, -+ struct vb2_v4l2_buffer *cap_vb, -+ bool copy_frame_flags) - { - u32 mask = V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK; - -@@ -993,7 +993,7 @@ void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, - cap_vb->flags &= ~mask; - cap_vb->flags |= out_vb->flags & mask; - } --EXPORT_SYMBOL_GPL(v4l2_m2m_buf_copy_data); -+EXPORT_SYMBOL_GPL(v4l2_m2m_buf_copy_metadata); - - void v4l2_m2m_request_queue(struct media_request *req) - { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index 443fb037e1cf..4d6d602cdde6 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -50,7 +50,7 @@ void cedrus_device_run(void *priv) - break; - } - -- v4l2_m2m_buf_copy_data(run.src, run.dst, true); -+ v4l2_m2m_buf_copy_metadata(run.src, run.dst, true); - - dev->dec_ops[ctx->current_codec]->setup(ctx, &run); - -diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h -index 43e447dcf69d..47c6d9aa0bf4 100644 ---- a/include/media/v4l2-mem2mem.h -+++ b/include/media/v4l2-mem2mem.h -@@ -623,11 +623,11 @@ v4l2_m2m_dst_buf_remove_by_idx(struct v4l2_m2m_ctx *m2m_ctx, unsigned int idx) - } - - /** -- * v4l2_m2m_buf_copy_data() - copy buffer data from the output buffer to the -- * capture buffer -+ * v4l2_m2m_buf_copy_metadata() - copy buffer metadata from -+ * the output buffer to the capture buffer - * -- * @out_vb: the output buffer that is the source of the data. -- * @cap_vb: the capture buffer that will receive the data. -+ * @out_vb: the output buffer that is the source of the metadata. -+ * @cap_vb: the capture buffer that will receive the metadata. - * @copy_frame_flags: copy the KEY/B/PFRAME flags as well. - * - * This helper function copies the timestamp, timecode (if the TIMECODE -@@ -638,9 +638,9 @@ v4l2_m2m_dst_buf_remove_by_idx(struct v4l2_m2m_ctx *m2m_ctx, unsigned int idx) - * flags are not copied. This is typically needed for encoders that - * set this bits explicitly. - */ --void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, -- struct vb2_v4l2_buffer *cap_vb, -- bool copy_frame_flags); -+void v4l2_m2m_buf_copy_metadata(const struct vb2_v4l2_buffer *out_vb, -+ struct vb2_v4l2_buffer *cap_vb, -+ bool copy_frame_flags); - - /* v4l2 request helper */ - --- -2.20.1 - -From 50656bad786d001b294764e9f047c5d5b3e4db75 Mon Sep 17 00:00:00 2001 -From: Philipp Zabel -Date: Thu, 10 Jan 2019 11:56:09 -0500 -Subject: [PATCH] media: v4l2-ctrl: Add control to enable h.264 constrained - intra prediction - -Allow to enable h.264 constrained intra prediction (macroblocks using -intra prediction modes are not allowed to use residual data and decoded -samples of neighboring macroblocks coded using inter prediction modes). -This control directly corresponds to the constrained_intra_pred_flag -field in the h.264 picture parameter set. - -Signed-off-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/extended-controls.rst | 4 ++++ - drivers/media/v4l2-core/v4l2-ctrls.c | 2 ++ - include/uapi/linux/v4l2-controls.h | 1 + - 3 files changed, 7 insertions(+) - -diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst -index af4273aa5e85..235d0c293983 100644 ---- a/Documentation/media/uapi/v4l/extended-controls.rst -+++ b/Documentation/media/uapi/v4l/extended-controls.rst -@@ -1154,6 +1154,10 @@ enum v4l2_mpeg_video_h264_entropy_mode - - ``V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (boolean)`` - Enable 8X8 transform for H264. Applicable to the H264 encoder. - -+``V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (boolean)`` -+ Enable constrained intra prediction for H264. Applicable to the H264 -+ encoder. -+ - ``V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (integer)`` - Cyclic intra macroblock refresh. This is the number of continuous - macroblocks refreshed every frame. Each frame a successive set of -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 8c47d8f00429..50b56185c02e 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -825,6 +825,8 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER:return "H264 Number of HC Layers"; - case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP: - return "H264 Set QP Value for HC Layers"; -+ case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: -+ return "H264 Constrained Intra Pred"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index 3dcfc6148f99..fd65c710b144 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -533,6 +533,7 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type { - }; - #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) - #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) -+#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383) - #define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) - #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) - #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) --- -2.21.0 - -From d034696cbe5a6e00f76ca4b7869c6cdef66aebd5 Mon Sep 17 00:00:00 2001 -From: Philipp Zabel -Date: Thu, 10 Jan 2019 11:56:10 -0500 -Subject: [PATCH] media: v4l2-ctrl: Add control for h.264 chroma qp offset - -Allow to add fixed quantization parameter offset between luma and -chroma quantization parameters. This control directly corresponds -to the chroma_qp_index_offset field of the h.264 picture parameter -set. - -Signed-off-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/extended-controls.rst | 5 +++++ - drivers/media/v4l2-core/v4l2-ctrls.c | 1 + - include/uapi/linux/v4l2-controls.h | 1 + - 3 files changed, 7 insertions(+) - -diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst -index 235d0c293983..00934efdc9e4 100644 ---- a/Documentation/media/uapi/v4l/extended-controls.rst -+++ b/Documentation/media/uapi/v4l/extended-controls.rst -@@ -1158,6 +1158,11 @@ enum v4l2_mpeg_video_h264_entropy_mode - - Enable constrained intra prediction for H264. Applicable to the H264 - encoder. - -+``V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (integer)`` -+ Specify the offset that should be added to the luma quantization -+ parameter to determine the chroma quantization parameter. Applicable -+ to the H264 encoder. -+ - ``V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (integer)`` - Cyclic intra macroblock refresh. This is the number of continuous - macroblocks refreshed every frame. Each frame a successive set of -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 50b56185c02e..99308dac2daa 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -827,6 +827,7 @@ const char *v4l2_ctrl_get_name(u32 id) - return "H264 Set QP Value for HC Layers"; - case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: - return "H264 Constrained Intra Pred"; -+ case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: return "H264 Chroma QP Index Offset"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index fd65c710b144..06479f2fb3ae 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -534,6 +534,7 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type { - #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) - #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) - #define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383) -+#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_MPEG_BASE+384) - #define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) - #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) - #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) --- -2.21.0 - -From 97e15cb4614733f7ebad2c9527b5ff82557dc247 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 2 Apr 2019 19:31:14 +0200 -Subject: [PATCH] clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0) - -Signed-off-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu_nkmp.c | 18 +++++++++++++----- - 1 file changed, 13 insertions(+), 5 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c -index 9b49adb20d07..69dfc6de1c4e 100644 ---- a/drivers/clk/sunxi-ng/ccu_nkmp.c -+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c -@@ -167,7 +167,7 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { - struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw); -- u32 n_mask, k_mask, m_mask, p_mask; -+ u32 n_mask = 0, k_mask = 0, m_mask = 0, p_mask = 0; - struct _ccu_nkmp _nkmp; - unsigned long flags; - u32 reg; -@@ -186,10 +186,18 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, - - ccu_nkmp_find_best(parent_rate, rate, &_nkmp); - -- n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift); -- k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift); -- m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift); -- p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift); -+ if (nkmp->n.width) -+ n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, -+ nkmp->n.shift); -+ if (nkmp->k.width) -+ k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, -+ nkmp->k.shift); -+ if (nkmp->m.width) -+ m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, -+ nkmp->m.shift); -+ if (nkmp->p.width) -+ p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, -+ nkmp->p.shift); - - spin_lock_irqsave(nkmp->common.lock, flags); - --- -2.21.0 - -From 6f3656f3552a3b32c625c93ddafcbe10bf0fea6d Mon Sep 17 00:00:00 2001 -From: Colin Ian King -Date: Sat, 22 Dec 2018 11:31:59 +0000 -Subject: [PATCH] regulator: axp20x: check rdev is null before dereferencing it - -Currently rdev is dereferenced when assigning desc before rdev is null -checked, hence there is a potential null pointer dereference on rdev. -Fix this by null checking rdev first. - -Detected by CoverityScan, CID#1476031 ("Dereference before null check") - -Fixes: 77e3e3b165db ("regulator: axp20x: add software based soft_start for AXP209 LDO3") -Signed-off-by: Colin Ian King -Signed-off-by: Mark Brown ---- - drivers/regulator/axp20x-regulator.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - -diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c -index 48af859fd053..0dfa4ea6bbdf 100644 ---- a/drivers/regulator/axp20x-regulator.c -+++ b/drivers/regulator/axp20x-regulator.c -@@ -367,7 +367,7 @@ static const int axp209_dcdc2_ldo3_slew_rates[] = { - static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) - { - struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); -- const struct regulator_desc *desc = rdev->desc; -+ const struct regulator_desc *desc; - u8 reg, mask, enable, cfg = 0xff; - const int *slew_rates; - int rate_count = 0; -@@ -375,6 +375,8 @@ static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) - if (!rdev) - return -EINVAL; - -+ desc = rdev->desc; -+ - switch (axp20x->variant) { - case AXP209_ID: - if (desc->id == AXP20X_DCDC2) { -@@ -436,11 +438,13 @@ static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) - static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev) - { - struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); -- const struct regulator_desc *desc = rdev->desc; -+ const struct regulator_desc *desc; - - if (!rdev) - return -EINVAL; - -+ desc = rdev->desc; -+ - switch (axp20x->variant) { - case AXP209_ID: - if ((desc->id == AXP20X_LDO3) && --- -2.21.0 - -From d02337709390c854186c6a21f997dc39760591e1 Mon Sep 17 00:00:00 2001 -From: Axel Lin -Date: Mon, 28 Jan 2019 22:02:19 +0800 -Subject: [PATCH] regulator: axp20x: Fix incorrect vsel_mask settings - -Fix copy-paste mistake while converting to use defines for masks. - -Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") -Signed-off-by: Axel Lin -Signed-off-by: Mark Brown ---- - drivers/regulator/axp20x-regulator.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c -index 48af859fd053..dd0193d77960 100644 ---- a/drivers/regulator/axp20x-regulator.c -+++ b/drivers/regulator/axp20x-regulator.c -@@ -573,7 +573,7 @@ static const struct regulator_desc axp22x_regulators[] = { - AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), - AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, -- AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT, -+ AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), - AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, - AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, -@@ -952,7 +952,7 @@ static const struct regulator_desc axp813_regulators[] = { - AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), - AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100, -- AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT, -+ AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), - AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100, - AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, -@@ -962,7 +962,7 @@ static const struct regulator_desc axp813_regulators[] = { - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), - AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", - axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, -- AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT, -+ AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), - AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100, - AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, -@@ -977,7 +977,7 @@ static const struct regulator_desc axp813_regulators[] = { - AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), - AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50, -- AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT, -+ AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), - /* to do / check ... */ - AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50, --- -2.21.0 - -From 4afa60d3a88aae3d052e0e8e1e62d6fc15a2be82 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Mon, 18 Feb 2019 02:01:20 +0100 -Subject: [PATCH] regulator: axp20x: fix DCDCB and BLDO2 definitions for AXP806 - -This fixes another set of errors from the refactoring of literals -to mask preproccesor definitions. - -Found by debugging a broken voltage setup on Orange Pi One Plus. - -Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") -Signed-off-by: Ondrej Jirman -Acked-by: Chen-Yu Tsai -Signed-off-by: Mark Brown ---- - drivers/regulator/axp20x-regulator.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c -index 1b51d557ab55..62243957bd19 100644 ---- a/drivers/regulator/axp20x-regulator.c -+++ b/drivers/regulator/axp20x-regulator.c -@@ -791,7 +791,7 @@ static const struct regulator_desc axp806_regulators[] = { - AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK, - AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK), - AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50, -- AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL, -+ AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK, - AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK), - AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", - axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, -@@ -817,7 +817,7 @@ static const struct regulator_desc axp806_regulators[] = { - AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK, - AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK), - AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100, -- AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL, -+ AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK, - AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK), - AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100, - AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK, --- -2.21.0 - -From 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 12 Jan 2019 20:17:19 -0600 -Subject: [PATCH] arm64: dts: allwinner: a64: Enable A64 timer workaround - -As instability in the architectural timer has been observed on multiple -devices using this SoC, inluding the Pine64 and the Orange Pi Win, -enable the workaround in the SoC's device tree. - -Acked-by: Maxime Ripard -Signed-off-by: Samuel Holland -Signed-off-by: Chen-Yu Tsai ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index bf9b719481c4..8171c0a7f265 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -200,6 +200,7 @@ - - timer { - compatible = "arm,armv8-timer"; -+ allwinner,erratum-unknown1; - interrupts = , - -X-Patchwork-Id: 1035824 -Return-Path: -Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 1B380C282C3 - for ; Sat, 26 Jan 2019 06:18:58 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) - by mail.kernel.org (Postfix) with ESMTP id DA5CC218A6 - for ; Sat, 26 Jan 2019 06:18:57 +0000 (UTC) -Authentication-Results: mail.kernel.org; - dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com - header.b="iKvIgjXT" -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1727857AbfAZGST (ORCPT - ); - Sat, 26 Jan 2019 01:18:19 -0500 -Received: from mail-pf1-f195.google.com ([209.85.210.195]:32902 "EHLO - mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1726030AbfAZGSS (ORCPT - ); - Sat, 26 Jan 2019 01:18:18 -0500 -Received: by mail-pf1-f195.google.com with SMTP id c123so5748894pfb.0 - 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DLDO2 and ELDO3 definitions for AXP803 -Date: Fri, 25 Jan 2019 22:18:09 -0800 -Message-Id: <20190126061809.18035-1-anarsoul@gmail.com> -X-Mailer: git-send-email 2.20.1 -MIME-Version: 1.0 -Sender: linux-kernel-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-kernel@vger.kernel.org - -Looks like refactoring didn't go well and left ALDO2, DLDO2 and ELDO3 -definitions broken for AXP803 - now they are using register address -instead of mask. Fix it by using mask where necessary. - -Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") -Signed-off-by: Vasily Khoruzhick -Reviewed-by: Chen-Yu Tsai ---- - drivers/regulator/axp20x-regulator.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c -index 48af859fd053..a808b03cae10 100644 ---- a/drivers/regulator/axp20x-regulator.c -+++ b/drivers/regulator/axp20x-regulator.c -@@ -719,7 +719,7 @@ static const struct regulator_desc axp803_regulators[] = { - AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), - AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, -- AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT, -+ AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), - AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, - AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, -@@ -729,7 +729,7 @@ static const struct regulator_desc axp803_regulators[] = { - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), - AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", - axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, -- AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT, -+ AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), - AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, - AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, -@@ -744,7 +744,7 @@ static const struct regulator_desc axp803_regulators[] = { - AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), - AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, -- AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT, -+ AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, - AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), - AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, - AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, diff --git a/projects/Allwinner/patches/linux/0003-backport-from-5.3.patch b/projects/Allwinner/patches/linux/0003-backport-from-5.3.patch new file mode 100644 index 0000000000..b9e475980b --- /dev/null +++ b/projects/Allwinner/patches/linux/0003-backport-from-5.3.patch @@ -0,0 +1,2765 @@ +From 9bd1acf0cdd4dd78a130714ad42163eac20871a3 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 18 May 2019 18:24:04 +0200 +Subject: [PATCH] media: cedrus: Allow different mod clock rates + +Some VPU variants may run at higher clock speeds. They actually need +extra speed to be capable of decoding more complex codecs like HEVC or +bigger image sizes (4K). + +Expand variant structure with mod_rate information. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.c | 11 ++++++++--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + + drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 2 +- + drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 -- + 4 files changed, 10 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index d0429c0e6b6b..9349a082a29c 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -369,36 +369,41 @@ static int cedrus_remove(struct platform_device *pdev) + } + + static const struct cedrus_variant sun4i_a10_cedrus_variant = { +- /* No particular capability. */ ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun5i_a13_cedrus_variant = { +- /* No particular capability. */ ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun7i_a20_cedrus_variant = { +- /* No particular capability. */ ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun8i_a33_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 320000000, + }; + + static const struct cedrus_variant sun8i_h3_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 402000000, + }; + + static const struct cedrus_variant sun50i_a64_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 402000000, + }; + + static const struct cedrus_variant sun50i_h5_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .mod_rate = 402000000, + }; + + static const struct cedrus_variant sun50i_h6_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, + .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, ++ .mod_rate = 600000000, + }; + + static const struct of_device_id cedrus_dt_match[] = { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index c57c04b41d2e..25ee1f80f2c7 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -94,6 +94,7 @@ struct cedrus_dec_ops { + struct cedrus_variant { + unsigned int capabilities; + unsigned int quirks; ++ unsigned int mod_rate; + }; + + struct cedrus_dev { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index fbfff7c1c771..60406b2d4595 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -236,7 +236,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + goto err_sram; + } + +- ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT); ++ ret = clk_set_rate(dev->mod_clk, variant->mod_rate); + if (ret) { + dev_err(dev->dev, "Failed to set clock rate\n"); + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +index b43c77d54b95..27d0882397aa 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +@@ -16,8 +16,6 @@ + #ifndef _CEDRUS_HW_H_ + #define _CEDRUS_HW_H_ + +-#define CEDRUS_CLOCK_RATE_DEFAULT 320000000 +- + int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); + void cedrus_engine_disable(struct cedrus_dev *dev); + +-- +2.21.0 + +From 79084d4e9a6783688ce497b6d17e8ecf09950bf5 Mon Sep 17 00:00:00 2001 +From: Philipp Zabel +Date: Wed, 24 Apr 2019 12:43:47 +0200 +Subject: [PATCH] media: v4l2-ctrl: add MPEG-2 profile and level controls + +Add MPEG-2 CID definitions for profiles and levels defined in ITU-T Rec. +H.262. + +Signed-off-by: Philipp Zabel +Signed-off-by: Hans Verkuil +--- + .../media/uapi/v4l/ext-ctrls-codec.rst | 56 +++++++++++++++++++ + drivers/media/v4l2-core/v4l2-ctrls.c | 23 ++++++++ + include/uapi/linux/v4l2-controls.h | 18 ++++++ + 3 files changed, 97 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index 4a8446203085..843c93e8e7bc 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -759,6 +759,32 @@ enum v4l2_mpeg_video_h264_level - + + + ++.. _v4l2-mpeg-video-mpeg2-level: ++ ++``V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL`` ++ (enum) ++ ++enum v4l2_mpeg_video_mpeg2_level - ++ The level information for the MPEG2 elementary stream. Applicable to ++ MPEG2 codecs. Possible values are: ++ ++ ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW`` ++ - Low Level (LL) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN`` ++ - Main Level (ML) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440`` ++ - High-1440 Level (H-14) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH`` ++ - High Level (HL) ++ ++ ++ + .. _v4l2-mpeg-video-mpeg4-level: + + ``V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL`` +@@ -845,6 +871,36 @@ enum v4l2_mpeg_video_h264_profile - + + + ++.. _v4l2-mpeg-video-mpeg2-profile: ++ ++``V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE`` ++ (enum) ++ ++enum v4l2_mpeg_video_mpeg2_profile - ++ The profile information for MPEG2. Applicable to MPEG2 codecs. ++ Possible values are: ++ ++ ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE`` ++ - Simple profile (SP) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN`` ++ - Main profile (MP) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE`` ++ - SNR Scalable profile (SNR) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE`` ++ - Spatially Scalable profile (Spt) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH`` ++ - High profile (HP) ++ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW`` ++ - Multi-view profile (MVP) ++ ++ ++ + .. _v4l2-mpeg-video-mpeg4-profile: + + ``V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE`` +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 420e3fc237cd..3380accc24ed 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -406,6 +406,21 @@ const char * const *v4l2_ctrl_get_menu(u32 id) + "Explicit", + NULL, + }; ++ static const char * const mpeg_mpeg2_level[] = { ++ "Low", ++ "Main", ++ "High 1440", ++ "High", ++ NULL, ++ }; ++ static const char * const mpeg2_profile[] = { ++ "Simple", ++ "Main", ++ "SNR Scalable", ++ "Spatially Scalable", ++ "High", ++ NULL, ++ }; + static const char * const mpeg_mpeg4_level[] = { + "0", + "0b", +@@ -622,6 +637,10 @@ const char * const *v4l2_ctrl_get_menu(u32 id) + return h264_fp_arrangement_type; + case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: + return h264_fmo_map_type; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: ++ return mpeg_mpeg2_level; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: ++ return mpeg2_profile; + case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: + return mpeg_mpeg4_level; + case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE: +@@ -832,6 +851,8 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; ++ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; +@@ -1197,6 +1218,8 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC: + case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE: + case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: ++ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: ++ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: + case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: + case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE: + case V4L2_CID_JPEG_CHROMA_SUBSAMPLING: +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index 37807f23231e..d9f2c76b71bb 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -404,6 +404,24 @@ enum v4l2_mpeg_video_multi_slice_mode { + #define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228) + #define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229) + ++/* CIDs for the MPEG-2 Part 2 (H.262) codec */ ++#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_BASE+270) ++enum v4l2_mpeg_video_mpeg2_level { ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW = 0, ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN = 1, ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440 = 2, ++ V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH = 3, ++}; ++#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_BASE+271) ++enum v4l2_mpeg_video_mpeg2_profile { ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE = 0, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN = 1, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 2, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE = 3, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH = 4, ++ V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW = 5, ++}; ++ + /* CIDs for the FWHT codec as used by the vicodec driver. */ + #define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_MPEG_BASE + 290) + #define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_MPEG_BASE + 291) +-- +2.21.0 + +From e5929e797865802d8124a20de14f202ec143cafd Mon Sep 17 00:00:00 2001 +From: Pawel Osciak +Date: Fri, 24 May 2019 11:20:28 +0200 +Subject: [PATCH 05/12] media: uapi: Add H264 low-level decoder API compound + controls. + +Stateless video codecs will require both the H264 metadata and slices in +order to be able to decode frames. + +This introduces the definitions for the structures used to pass the +metadata from the userspace to the kernel. + +Reviewed-by: Paul Kocialkowski +Reviewed-by: Tomasz Figa +Signed-off-by: Pawel Osciak +Signed-off-by: Guenter Roeck +Co-developed-by: Maxime Ripard +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + Documentation/media/uapi/v4l/biblio.rst | 9 + + .../media/uapi/v4l/ext-ctrls-codec.rst | 569 ++++++++++++++++++ + .../media/uapi/v4l/vidioc-queryctrl.rst | 30 + + .../media/videodev2.h.rst.exceptions | 5 + + drivers/media/v4l2-core/v4l2-ctrls.c | 42 ++ + include/media/v4l2-ctrls.h | 13 +- + 6 files changed, 667 insertions(+), 1 deletion(-) + +diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst +index ec33768c055e..8f4eb8823d82 100644 +--- a/Documentation/media/uapi/v4l/biblio.rst ++++ b/Documentation/media/uapi/v4l/biblio.rst +@@ -122,6 +122,15 @@ ITU BT.1119 + + :author: International Telecommunication Union (http://www.itu.ch) + ++.. _h264: ++ ++ITU-T Rec. H.264 Specification (04/2017 Edition) ++================================================ ++ ++:title: ITU-T Recommendation H.264 "Advanced Video Coding for Generic Audiovisual Services" ++ ++:author: International Telecommunication Union (http://www.itu.ch) ++ + .. _jfif: + + JFIF +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index 843c93e8e7bc..b0c178f0ff9b 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -1451,6 +1451,575 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - + - Layer number + + ++.. _v4l2-mpeg-h264: ++ ++``V4L2_CID_MPEG_VIDEO_H264_SPS (struct)`` ++ Specifies the sequence parameter set (as extracted from the ++ bitstream) for the associated H264 slice data. This includes the ++ necessary parameters for configuring a stateless hardware decoding ++ pipeline for H264. The bitstream parameters are defined according ++ to :ref:`h264`, section 7.4.2.1.1 "Sequence Parameter Set Data ++ Semantics". For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_sps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_sps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``profile_idc`` ++ - ++ * - __u8 ++ - ``constraint_set_flags`` ++ - See :ref:`Sequence Parameter Set Constraints Set Flags ` ++ * - __u8 ++ - ``level_idc`` ++ - ++ * - __u8 ++ - ``seq_parameter_set_id`` ++ - ++ * - __u8 ++ - ``chroma_format_idc`` ++ - ++ * - __u8 ++ - ``bit_depth_luma_minus8`` ++ - ++ * - __u8 ++ - ``bit_depth_chroma_minus8`` ++ - ++ * - __u8 ++ - ``log2_max_frame_num_minus4`` ++ - ++ * - __u8 ++ - ``pic_order_cnt_type`` ++ - ++ * - __u8 ++ - ``log2_max_pic_order_cnt_lsb_minus4`` ++ - ++ * - __u8 ++ - ``max_num_ref_frames`` ++ - ++ * - __u8 ++ - ``num_ref_frames_in_pic_order_cnt_cycle`` ++ - ++ * - __s32 ++ - ``offset_for_ref_frame[255]`` ++ - ++ * - __s32 ++ - ``offset_for_non_ref_pic`` ++ - ++ * - __s32 ++ - ``offset_for_top_to_bottom_field`` ++ - ++ * - __u16 ++ - ``pic_width_in_mbs_minus1`` ++ - ++ * - __u16 ++ - ``pic_height_in_map_units_minus1`` ++ - ++ * - __u32 ++ - ``flags`` ++ - See :ref:`Sequence Parameter Set Flags ` ++ ++.. _h264_sps_constraints_set_flags: ++ ++``Sequence Parameter Set Constraints Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET0_FLAG`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET1_FLAG`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET2_FLAG`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET3_FLAG`` ++ - 0x00000008 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET4_FLAG`` ++ - 0x00000010 ++ - ++ * - ``V4L2_H264_SPS_CONSTRAINT_SET5_FLAG`` ++ - 0x00000020 ++ - ++ ++.. _h264_sps_flags: ++ ++``Sequence Parameter Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED`` ++ - 0x00000008 ++ - ++ * - ``V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY`` ++ - 0x00000010 ++ - ++ * - ``V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD`` ++ - 0x00000020 ++ - ++ * - ``V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE`` ++ - 0x00000040 ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_PPS (struct)`` ++ Specifies the picture parameter set (as extracted from the ++ bitstream) for the associated H264 slice data. This includes the ++ necessary parameters for configuring a stateless hardware decoding ++ pipeline for H264. The bitstream parameters are defined according ++ to :ref:`h264`, section 7.4.2.2 "Picture Parameter Set RBSP ++ Semantics". For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_pps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_pps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``pic_parameter_set_id`` ++ - ++ * - __u8 ++ - ``seq_parameter_set_id`` ++ - ++ * - __u8 ++ - ``num_slice_groups_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l0_default_active_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l1_default_active_minus1`` ++ - ++ * - __u8 ++ - ``weighted_bipred_idc`` ++ - ++ * - __s8 ++ - ``pic_init_qp_minus26`` ++ - ++ * - __s8 ++ - ``pic_init_qs_minus26`` ++ - ++ * - __s8 ++ - ``chroma_qp_index_offset`` ++ - ++ * - __s8 ++ - ``second_chroma_qp_index_offset`` ++ - ++ * - __u16 ++ - ``flags`` ++ - See :ref:`Picture Parameter Set Flags ` ++ ++.. _h264_pps_flags: ++ ++``Picture Parameter Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_PPS_FLAG_WEIGHTED_PRED`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT`` ++ - 0x00000008 ++ - ++ * - ``V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED`` ++ - 0x00000010 ++ - ++ * - ``V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT`` ++ - 0x00000020 ++ - ++ * - ``V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE`` ++ - 0x00000040 ++ - ++ * - ``V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT`` ++ - 0x00000080 ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (struct)`` ++ Specifies the scaling matrix (as extracted from the bitstream) for ++ the associated H264 slice data. The bitstream parameters are ++ defined according to :ref:`h264`, section 7.4.2.1.1.1 "Scaling ++ List Semantics".For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_scaling_matrix ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_scaling_matrix ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``scaling_list_4x4[6][16]`` ++ - ++ * - __u8 ++ - ``scaling_list_8x8[6][64]`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (struct)`` ++ Specifies the slice parameters (as extracted from the bitstream) ++ for the associated H264 slice data. This includes the necessary ++ parameters for configuring a stateless hardware decoding pipeline ++ for H264. The bitstream parameters are defined according to ++ :ref:`h264`, section 7.4.3 "Slice Header Semantics". For further ++ documentation, refer to the above specification, unless there is ++ an explicit comment stating otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API ++ and it is expected to change. ++ ++ This structure is expected to be passed as an array, with one ++ entry for each slice included in the bitstream buffer. ++ ++.. c:type:: v4l2_ctrl_h264_slice_params ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_slice_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``size`` ++ - ++ * - __u32 ++ - ``header_bit_size`` ++ - ++ * - __u16 ++ - ``first_mb_in_slice`` ++ - ++ * - __u8 ++ - ``slice_type`` ++ - ++ * - __u8 ++ - ``pic_parameter_set_id`` ++ - ++ * - __u8 ++ - ``colour_plane_id`` ++ - ++ * - __u8 ++ - ``redundant_pic_cnt`` ++ - ++ * - __u16 ++ - ``frame_num`` ++ - ++ * - __u16 ++ - ``idr_pic_id`` ++ - ++ * - __u16 ++ - ``pic_order_cnt_lsb`` ++ - ++ * - __s32 ++ - ``delta_pic_order_cnt_bottom`` ++ - ++ * - __s32 ++ - ``delta_pic_order_cnt0`` ++ - ++ * - __s32 ++ - ``delta_pic_order_cnt1`` ++ - ++ * - struct :c:type:`v4l2_h264_pred_weight_table` ++ - ``pred_weight_table`` ++ - ++ * - __u32 ++ - ``dec_ref_pic_marking_bit_size`` ++ - ++ * - __u32 ++ - ``pic_order_cnt_bit_size`` ++ - ++ * - __u8 ++ - ``cabac_init_idc`` ++ - ++ * - __s8 ++ - ``slice_qp_delta`` ++ - ++ * - __s8 ++ - ``slice_qs_delta`` ++ - ++ * - __u8 ++ - ``disable_deblocking_filter_idc`` ++ - ++ * - __s8 ++ - ``slice_alpha_c0_offset_div2`` ++ - ++ * - __s8 ++ - ``slice_beta_offset_div2`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l0_active_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l1_active_minus1`` ++ - ++ * - __u32 ++ - ``slice_group_change_cycle`` ++ - ++ * - __u8 ++ - ``ref_pic_list0[32]`` ++ - Reference picture list after applying the per-slice modifications ++ * - __u8 ++ - ``ref_pic_list1[32]`` ++ - Reference picture list after applying the per-slice modifications ++ * - __u32 ++ - ``flags`` ++ - See :ref:`Slice Parameter Flags ` ++ ++.. _h264_slice_flags: ++ ++``Slice Parameter Set Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_SLICE_FLAG_FIELD_PIC`` ++ - 0x00000001 ++ - ++ * - ``V4L2_H264_SLICE_FLAG_BOTTOM_FIELD`` ++ - 0x00000002 ++ - ++ * - ``V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED`` ++ - 0x00000004 ++ - ++ * - ``V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH`` ++ - 0x00000008 ++ - ++ ++``Prediction Weight Table`` ++ ++ The bitstream parameters are defined according to :ref:`h264`, ++ section 7.4.3.2 "Prediction Weight Table Semantics". For further ++ documentation, refer to the above specification, unless there is ++ an explicit comment stating otherwise. ++ ++.. c:type:: v4l2_h264_pred_weight_table ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_h264_pred_weight_table ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u16 ++ - ``luma_log2_weight_denom`` ++ - ++ * - __u16 ++ - ``chroma_log2_weight_denom`` ++ - ++ * - struct :c:type:`v4l2_h264_weight_factors` ++ - ``weight_factors[2]`` ++ - The weight factors at index 0 are the weight factors for the reference ++ list 0, the one at index 1 for the reference list 1. ++ ++.. c:type:: v4l2_h264_weight_factors ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_h264_weight_factors ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __s16 ++ - ``luma_weight[32]`` ++ - ++ * - __s16 ++ - ``luma_offset[32]`` ++ - ++ * - __s16 ++ - ``chroma_weight[32][2]`` ++ - ++ * - __s16 ++ - ``chroma_offset[32][2]`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (struct)`` ++ Specifies the decode parameters (as extracted from the bitstream) ++ for the associated H264 slice data. This includes the necessary ++ parameters for configuring a stateless hardware decoding pipeline ++ for H264. The bitstream parameters are defined according to ++ :ref:`h264`. For further documentation, refer to the above ++ specification, unless there is an explicit comment stating ++ otherwise. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_h264_decode_params ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_h264_decode_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``num_slices`` ++ - Number of slices needed to decode the current frame ++ * - __u32 ++ - ``nal_ref_idc`` ++ - NAL reference ID value coming from the NAL Unit header ++ * - __u8 ++ - ``ref_pic_list_p0[32]`` ++ - Backward reference list used by P-frames in the original bitstream order ++ * - __u8 ++ - ``ref_pic_list_b0[32]`` ++ - Backward reference list used by B-frames in the original bitstream order ++ * - __u8 ++ - ``ref_pic_list_b1[32]`` ++ - Forward reference list used by B-frames in the original bitstream order ++ * - __s32 ++ - ``top_field_order_cnt`` ++ - Picture Order Count for the coded top field ++ * - __s32 ++ - ``bottom_field_order_cnt`` ++ - Picture Order Count for the coded bottom field ++ * - __u32 ++ - ``flags`` ++ - See :ref:`Decode Parameters Flags ` ++ * - struct :c:type:`v4l2_h264_dpb_entry` ++ - ``dpb[16]`` ++ - ++ ++.. _h264_decode_params_flags: ++ ++``Decode Parameters Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC`` ++ - 0x00000001 ++ - That picture is an IDR picture ++ ++.. c:type:: v4l2_h264_dpb_entry ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_h264_dpb_entry ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u64 ++ - ``reference_ts`` ++ - Timestamp of the V4L2 capture buffer to use as reference, used ++ with B-coded and P-coded frames. The timestamp refers to the ++ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the ++ :c:func:`v4l2_timeval_to_ns()` function to convert the struct ++ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. ++ * - __u16 ++ - ``frame_num`` ++ - ++ * - __u16 ++ - ``pic_num`` ++ - ++ * - __s32 ++ - ``top_field_order_cnt`` ++ - ++ * - __s32 ++ - ``bottom_field_order_cnt`` ++ - ++ * - __u32 ++ - ``flags`` ++ - See :ref:`DPB Entry Flags ` ++ ++.. _h264_dpb_flags: ++ ++``DPB Entries Flags`` ++ ++.. cssclass:: longtable ++ ++.. flat-table:: ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - ``V4L2_H264_DPB_ENTRY_FLAG_VALID`` ++ - 0x00000001 ++ - The DPB entry is valid and should be considered ++ * - ``V4L2_H264_DPB_ENTRY_FLAG_ACTIVE`` ++ - 0x00000002 ++ - The DPB entry is currently being used as a reference frame ++ * - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM`` ++ - 0x00000004 ++ - The DPB entry is a long term reference frame + + .. _v4l2-mpeg-mpeg2: + +diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +index f824162d0ea9..dc500632095d 100644 +--- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst ++++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +@@ -443,6 +443,36 @@ See also the examples in :ref:`control`. + - n/a + - A struct :c:type:`v4l2_ctrl_mpeg2_quantization`, containing MPEG-2 + quantization matrices for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_sps`, containing H264 ++ sequence parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_PPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_pps`, containing H264 ++ picture parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SCALING_MATRIX`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_scaling_matrix`, containing H264 ++ scaling matrices for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SLICE_PARAMS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_slice_params`, containing H264 ++ slice parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_DECODE_PARAMS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 ++ decode parameters for stateless video decoders. + + .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| + +diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions +index 64d348e67df9..55cbe324b9fc 100644 +--- a/Documentation/media/videodev2.h.rst.exceptions ++++ b/Documentation/media/videodev2.h.rst.exceptions +@@ -136,6 +136,11 @@ replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_MPEG2_QUANTIZATION :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` + + # V4L2 capability defines + replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 3380accc24ed..b72dc54ba638 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -851,6 +851,11 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; ++ case V4L2_CID_MPEG_VIDEO_H264_SPS: return "H264 Sequence Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_H264_PPS: return "H264 Picture Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix"; ++ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; ++ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; + case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; + case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; +@@ -1337,6 +1342,21 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: + *type = V4L2_CTRL_TYPE_FWHT_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_H264_SPS: ++ *type = V4L2_CTRL_TYPE_H264_SPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_PPS: ++ *type = V4L2_CTRL_TYPE_H264_PPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: ++ *type = V4L2_CTRL_TYPE_H264_SCALING_MATRIX; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: ++ *type = V4L2_CTRL_TYPE_H264_SLICE_PARAMS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: ++ *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; ++ break; + default: + *type = V4L2_CTRL_TYPE_INTEGER; + break; +@@ -1706,6 +1726,13 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + case V4L2_CTRL_TYPE_FWHT_PARAMS: + return 0; + ++ case V4L2_CTRL_TYPE_H264_SPS: ++ case V4L2_CTRL_TYPE_H264_PPS: ++ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: ++ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: ++ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: ++ return 0; ++ + default: + return -EINVAL; + } +@@ -2289,6 +2316,21 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_FWHT_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_fwht_params); + break; ++ case V4L2_CTRL_TYPE_H264_SPS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_sps); ++ break; ++ case V4L2_CTRL_TYPE_H264_PPS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_pps); ++ break; ++ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: ++ elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix); ++ break; ++ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_slice_params); ++ break; ++ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); ++ break; + default: + if (type < V4L2_CTRL_COMPOUND_TYPES) + elem_size = sizeof(s32); +diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h +index ee026387f513..a8aede26491e 100644 +--- a/include/media/v4l2-ctrls.h ++++ b/include/media/v4l2-ctrls.h +@@ -23,11 +23,12 @@ + #include + + /* +- * Include the mpeg2 and fwht stateless codec compound control definitions. ++ * Include the stateless codec compound control definitions. + * This will move to the public headers once this API is fully stable. + */ + #include + #include ++#include + + /* forward references */ + struct file; +@@ -51,6 +52,11 @@ struct poll_table_struct; + * @p_mpeg2_slice_params: Pointer to a MPEG2 slice parameters structure. + * @p_mpeg2_quantization: Pointer to a MPEG2 quantization data structure. + * @p_fwht_params: Pointer to a FWHT stateless parameters structure. ++ * @p_h264_sps: Pointer to a struct v4l2_ctrl_h264_sps. ++ * @p_h264_pps: Pointer to a struct v4l2_ctrl_h264_pps. ++ * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. ++ * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. ++ * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. + * @p: Pointer to a compound value. + */ + union v4l2_ctrl_ptr { +@@ -63,6 +69,11 @@ union v4l2_ctrl_ptr { + struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; + struct v4l2_ctrl_mpeg2_quantization *p_mpeg2_quantization; + struct v4l2_ctrl_fwht_params *p_fwht_params; ++ struct v4l2_ctrl_h264_sps *p_h264_sps; ++ struct v4l2_ctrl_h264_pps *p_h264_pps; ++ struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; ++ struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; ++ struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; + void *p; + }; + +-- +2.21.0 + +From 973e931fe8eefc32616f8eadadd0a018cbd096b5 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 24 May 2019 11:20:29 +0200 +Subject: [PATCH 06/12] media: pixfmt: Add H264 Slice format + +The H264_SLICE_RAW format is meant to hold the parsed slice data without +the start code. This will be needed by stateless decoders. + +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/media/h264-ctrls.h | 197 +++++++++++++++++++++++++++ + 2 files changed, 198 insertions(+) + create mode 100644 include/media/h264-ctrls.h + +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index ac87c3e37280..f6e1254064d2 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1325,6 +1325,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_PIX_FMT_H264: descr = "H.264"; break; + case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; + case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; ++ case V4L2_PIX_FMT_H264_SLICE_RAW: descr = "H.264 Parsed Slice Data"; break; + case V4L2_PIX_FMT_H263: descr = "H.263"; break; + case V4L2_PIX_FMT_MPEG1: descr = "MPEG-1 ES"; break; + case V4L2_PIX_FMT_MPEG2: descr = "MPEG-2 ES"; break; +diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h +new file mode 100644 +index 000000000000..e1404d78d6ff +--- /dev/null ++++ b/include/media/h264-ctrls.h +@@ -0,0 +1,197 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * These are the H.264 state controls for use with stateless H.264 ++ * codec drivers. ++ * ++ * It turns out that these structs are not stable yet and will undergo ++ * more changes. So keep them private until they are stable and ready to ++ * become part of the official public API. ++ */ ++ ++#ifndef _H264_CTRLS_H_ ++#define _H264_CTRLS_H_ ++ ++#include ++ ++/* Our pixel format isn't stable at the moment */ ++#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ ++ ++/* ++ * This is put insanely high to avoid conflicting with controls that ++ * would be added during the phase where those controls are not ++ * stable. It should be fixed eventually. ++ */ ++#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) ++#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) ++#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) ++#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) ++#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) ++ ++/* enum v4l2_ctrl_type type values */ ++#define V4L2_CTRL_TYPE_H264_SPS 0x0110 ++#define V4L2_CTRL_TYPE_H264_PPS 0x0111 ++#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 ++#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 ++#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 ++ ++#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 ++#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 ++#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 ++#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 ++#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 ++#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 ++ ++#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 ++#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 ++#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 ++#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 ++#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 ++#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 ++#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 ++ ++struct v4l2_ctrl_h264_sps { ++ __u8 profile_idc; ++ __u8 constraint_set_flags; ++ __u8 level_idc; ++ __u8 seq_parameter_set_id; ++ __u8 chroma_format_idc; ++ __u8 bit_depth_luma_minus8; ++ __u8 bit_depth_chroma_minus8; ++ __u8 log2_max_frame_num_minus4; ++ __u8 pic_order_cnt_type; ++ __u8 log2_max_pic_order_cnt_lsb_minus4; ++ __u8 max_num_ref_frames; ++ __u8 num_ref_frames_in_pic_order_cnt_cycle; ++ __s32 offset_for_ref_frame[255]; ++ __s32 offset_for_non_ref_pic; ++ __s32 offset_for_top_to_bottom_field; ++ __u16 pic_width_in_mbs_minus1; ++ __u16 pic_height_in_map_units_minus1; ++ __u32 flags; ++}; ++ ++#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 ++#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 ++#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 ++#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 ++#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 ++#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 ++#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 ++#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 ++ ++struct v4l2_ctrl_h264_pps { ++ __u8 pic_parameter_set_id; ++ __u8 seq_parameter_set_id; ++ __u8 num_slice_groups_minus1; ++ __u8 num_ref_idx_l0_default_active_minus1; ++ __u8 num_ref_idx_l1_default_active_minus1; ++ __u8 weighted_bipred_idc; ++ __s8 pic_init_qp_minus26; ++ __s8 pic_init_qs_minus26; ++ __s8 chroma_qp_index_offset; ++ __s8 second_chroma_qp_index_offset; ++ __u16 flags; ++}; ++ ++struct v4l2_ctrl_h264_scaling_matrix { ++ __u8 scaling_list_4x4[6][16]; ++ __u8 scaling_list_8x8[6][64]; ++}; ++ ++struct v4l2_h264_weight_factors { ++ __s16 luma_weight[32]; ++ __s16 luma_offset[32]; ++ __s16 chroma_weight[32][2]; ++ __s16 chroma_offset[32][2]; ++}; ++ ++struct v4l2_h264_pred_weight_table { ++ __u16 luma_log2_weight_denom; ++ __u16 chroma_log2_weight_denom; ++ struct v4l2_h264_weight_factors weight_factors[2]; ++}; ++ ++#define V4L2_H264_SLICE_TYPE_P 0 ++#define V4L2_H264_SLICE_TYPE_B 1 ++#define V4L2_H264_SLICE_TYPE_I 2 ++#define V4L2_H264_SLICE_TYPE_SP 3 ++#define V4L2_H264_SLICE_TYPE_SI 4 ++ ++#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 ++#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 ++#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 ++#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 ++ ++struct v4l2_ctrl_h264_slice_params { ++ /* Size in bytes, including header */ ++ __u32 size; ++ /* Offset in bits to slice_data() from the beginning of this slice. */ ++ __u32 header_bit_size; ++ ++ __u16 first_mb_in_slice; ++ __u8 slice_type; ++ __u8 pic_parameter_set_id; ++ __u8 colour_plane_id; ++ __u8 redundant_pic_cnt; ++ __u16 frame_num; ++ __u16 idr_pic_id; ++ __u16 pic_order_cnt_lsb; ++ __s32 delta_pic_order_cnt_bottom; ++ __s32 delta_pic_order_cnt0; ++ __s32 delta_pic_order_cnt1; ++ ++ struct v4l2_h264_pred_weight_table pred_weight_table; ++ /* Size in bits of dec_ref_pic_marking() syntax element. */ ++ __u32 dec_ref_pic_marking_bit_size; ++ /* Size in bits of pic order count syntax. */ ++ __u32 pic_order_cnt_bit_size; ++ ++ __u8 cabac_init_idc; ++ __s8 slice_qp_delta; ++ __s8 slice_qs_delta; ++ __u8 disable_deblocking_filter_idc; ++ __s8 slice_alpha_c0_offset_div2; ++ __s8 slice_beta_offset_div2; ++ __u8 num_ref_idx_l0_active_minus1; ++ __u8 num_ref_idx_l1_active_minus1; ++ __u32 slice_group_change_cycle; ++ ++ /* ++ * Entries on each list are indices into ++ * v4l2_ctrl_h264_decode_params.dpb[]. ++ */ ++ __u8 ref_pic_list0[32]; ++ __u8 ref_pic_list1[32]; ++ ++ __u32 flags; ++}; ++ ++#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 ++#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 ++#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 ++ ++struct v4l2_h264_dpb_entry { ++ __u64 reference_ts; ++ __u16 frame_num; ++ __u16 pic_num; ++ /* Note that field is indicated by v4l2_buffer.field */ ++ __s32 top_field_order_cnt; ++ __s32 bottom_field_order_cnt; ++ __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ ++}; ++ ++#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 ++ ++struct v4l2_ctrl_h264_decode_params { ++ struct v4l2_h264_dpb_entry dpb[16]; ++ __u16 num_slices; ++ __u16 nal_ref_idc; ++ __u8 ref_pic_list_p0[32]; ++ __u8 ref_pic_list_b0[32]; ++ __u8 ref_pic_list_b1[32]; ++ __s32 top_field_order_cnt; ++ __s32 bottom_field_order_cnt; ++ __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ ++}; ++ ++#endif +-- +2.21.0 + +From 129c7799b038de2a4fa90e6cff2bbb843187b06f Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 24 May 2019 11:20:30 +0200 +Subject: [PATCH 07/12] media: pixfmt: Add H264_SLICE_RAW format documentation + +The H264_SLICE_RAW format introduced before is meant for stateless +decoders that will need the H264 parsed slice data without the start code. + +Let's document it. + +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + .../media/uapi/v4l/pixfmt-compressed.rst | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +index 6c961cfb74da..4b701fc7653e 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +@@ -52,6 +52,31 @@ Compressed Formats + - ``V4L2_PIX_FMT_H264_MVC`` + - 'M264' + - H264 MVC video elementary stream. ++ * .. _V4L2-PIX-FMT-H264-SLICE-RAW: ++ ++ - ``V4L2_PIX_FMT_H264_SLICE_RAW`` ++ - 'S264' ++ - H264 parsed slice data, without the start code and as ++ extracted from the H264 bitstream. This format is adapted for ++ stateless video decoders that implement an H264 pipeline ++ (using the :ref:`mem2mem` and :ref:`media-request-api`). ++ Metadata associated with the frame to decode are required to ++ be passed through the ``V4L2_CID_MPEG_VIDEO_H264_SPS``, ++ ``V4L2_CID_MPEG_VIDEO_H264_PPS``, ++ ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``, ++ ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and ++ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS`` controls. See the ++ :ref:`associated Codec Control IDs `. Exactly ++ one output and one capture buffer must be provided for use ++ with this pixel format. The output buffer must contain the ++ appropriate number of macroblocks to decode a full ++ corresponding frame to the matching capture buffer. ++ ++ .. note:: ++ ++ This format is not yet part of the public kernel API and it ++ is expected to change. ++ + * .. _V4L2-PIX-FMT-H263: + + - ``V4L2_PIX_FMT_H263`` +-- +2.21.0 + +From 83b448edec51503daf61a823643a50db5e68cb15 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 24 May 2019 11:20:31 +0200 +Subject: [PATCH 08/12] media: cedrus: Add H264 decoding support + +Introduce some basic H264 decoding support in cedrus. So far, only the +baseline profile videos have been tested, and some more advanced features +used in higher profiles are not even implemented. + +Reviewed-by: Jernej Skrabec +Reviewed-by: Paul Kocialkowski +Signed-off-by: Maxime Ripard +Signed-off-by: Hans Verkuil +--- + drivers/staging/media/sunxi/cedrus/Makefile | 3 +- + drivers/staging/media/sunxi/cedrus/cedrus.c | 31 + + drivers/staging/media/sunxi/cedrus/cedrus.h | 38 +- + .../staging/media/sunxi/cedrus/cedrus_dec.c | 13 + + .../staging/media/sunxi/cedrus/cedrus_h264.c | 576 ++++++++++++++++++ + .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 + + .../staging/media/sunxi/cedrus/cedrus_regs.h | 91 +++ + .../staging/media/sunxi/cedrus/cedrus_video.c | 9 + + 8 files changed, 763 insertions(+), 2 deletions(-) + create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h264.c + +diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile +index 808842f0119e..c85ac6db0302 100644 +--- a/drivers/staging/media/sunxi/cedrus/Makefile ++++ b/drivers/staging/media/sunxi/cedrus/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o + +-sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o ++sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ ++ cedrus_mpeg2.o cedrus_h264.o +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index 9349a082a29c..370937edfc14 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -40,6 +40,36 @@ static const struct cedrus_control cedrus_controls[] = { + .codec = CEDRUS_CODEC_MPEG2, + .required = false, + }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_decode_params), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_slice_params), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_sps), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_pps), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, + }; + + #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) +@@ -278,6 +308,7 @@ static int cedrus_probe(struct platform_device *pdev) + } + + dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; ++ dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; + + mutex_init(&dev->dev_mutex); + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 25ee1f80f2c7..3f476d0fd981 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -32,7 +32,7 @@ + + enum cedrus_codec { + CEDRUS_CODEC_MPEG2, +- ++ CEDRUS_CODEC_H264, + CEDRUS_CODEC_LAST, + }; + +@@ -42,6 +42,12 @@ enum cedrus_irq_status { + CEDRUS_IRQ_OK, + }; + ++enum cedrus_h264_pic_type { ++ CEDRUS_H264_PIC_TYPE_FRAME = 0, ++ CEDRUS_H264_PIC_TYPE_FIELD, ++ CEDRUS_H264_PIC_TYPE_MBAFF, ++}; ++ + struct cedrus_control { + u32 id; + u32 elem_size; +@@ -49,6 +55,14 @@ struct cedrus_control { + unsigned char required:1; + }; + ++struct cedrus_h264_run { ++ const struct v4l2_ctrl_h264_decode_params *decode_params; ++ const struct v4l2_ctrl_h264_pps *pps; ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; ++ const struct v4l2_ctrl_h264_slice_params *slice_params; ++ const struct v4l2_ctrl_h264_sps *sps; ++}; ++ + struct cedrus_mpeg2_run { + const struct v4l2_ctrl_mpeg2_slice_params *slice_params; + const struct v4l2_ctrl_mpeg2_quantization *quantization; +@@ -59,12 +73,20 @@ struct cedrus_run { + struct vb2_v4l2_buffer *dst; + + union { ++ struct cedrus_h264_run h264; + struct cedrus_mpeg2_run mpeg2; + }; + }; + + struct cedrus_buffer { + struct v4l2_m2m_buffer m2m_buf; ++ ++ union { ++ struct { ++ unsigned int position; ++ enum cedrus_h264_pic_type pic_type; ++ } h264; ++ } codec; + }; + + struct cedrus_ctx { +@@ -79,6 +101,19 @@ struct cedrus_ctx { + struct v4l2_ctrl **ctrls; + + struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; ++ ++ union { ++ struct { ++ void *mv_col_buf; ++ dma_addr_t mv_col_buf_dma; ++ ssize_t mv_col_buf_field_size; ++ ssize_t mv_col_buf_size; ++ void *pic_info_buf; ++ dma_addr_t pic_info_buf_dma; ++ void *neighbor_info_buf; ++ dma_addr_t neighbor_info_buf_dma; ++ } h264; ++ } codec; + }; + + struct cedrus_dec_ops { +@@ -122,6 +157,7 @@ struct cedrus_dev { + }; + + extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; ++extern struct cedrus_dec_ops cedrus_dec_ops_h264; + + static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) + { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index 4d6d602cdde6..bdad87eb9d79 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -46,6 +46,19 @@ void cedrus_device_run(void *priv) + V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); + break; + ++ case V4L2_PIX_FMT_H264_SLICE_RAW: ++ run.h264.decode_params = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); ++ run.h264.pps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_PPS); ++ run.h264.scaling_matrix = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX); ++ run.h264.slice_params = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); ++ run.h264.sps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SPS); ++ break; ++ + default: + break; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +new file mode 100644 +index 000000000000..a30bb283f69f +--- /dev/null ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -0,0 +1,576 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Cedrus VPU driver ++ * ++ * Copyright (c) 2013 Jens Kuske ++ * Copyright (c) 2018 Bootlin ++ */ ++ ++#include ++ ++#include ++ ++#include "cedrus.h" ++#include "cedrus_hw.h" ++#include "cedrus_regs.h" ++ ++enum cedrus_h264_sram_off { ++ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE = 0x000, ++ CEDRUS_SRAM_H264_FRAMEBUFFER_LIST = 0x100, ++ CEDRUS_SRAM_H264_REF_LIST_0 = 0x190, ++ CEDRUS_SRAM_H264_REF_LIST_1 = 0x199, ++ CEDRUS_SRAM_H264_SCALING_LIST_8x8_0 = 0x200, ++ CEDRUS_SRAM_H264_SCALING_LIST_8x8_1 = 0x210, ++ CEDRUS_SRAM_H264_SCALING_LIST_4x4 = 0x220, ++}; ++ ++struct cedrus_h264_sram_ref_pic { ++ __le32 top_field_order_cnt; ++ __le32 bottom_field_order_cnt; ++ __le32 frame_info; ++ __le32 luma_ptr; ++ __le32 chroma_ptr; ++ __le32 mv_col_top_ptr; ++ __le32 mv_col_bot_ptr; ++ __le32 reserved; ++} __packed; ++ ++#define CEDRUS_H264_FRAME_NUM 18 ++ ++#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) ++#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) ++ ++static void cedrus_h264_write_sram(struct cedrus_dev *dev, ++ enum cedrus_h264_sram_off off, ++ const void *data, size_t len) ++{ ++ const u32 *buffer = data; ++ size_t count = DIV_ROUND_UP(len, 4); ++ ++ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, off << 2); ++ ++ while (count--) ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++); ++} ++ ++static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, ++ unsigned int position, ++ unsigned int field) ++{ ++ dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; ++ ++ /* Adjust for the position */ ++ addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; ++ ++ /* Adjust for the field */ ++ addr += field * ctx->codec.h264.mv_col_buf_field_size; ++ ++ return addr; ++} ++ ++static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, ++ struct cedrus_buffer *buf, ++ unsigned int top_field_order_cnt, ++ unsigned int bottom_field_order_cnt, ++ struct cedrus_h264_sram_ref_pic *pic) ++{ ++ struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; ++ unsigned int position = buf->codec.h264.position; ++ ++ pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt); ++ pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt); ++ pic->frame_info = cpu_to_le32(buf->codec.h264.pic_type << 8); ++ ++ pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0)); ++ pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1)); ++ pic->mv_col_top_ptr = ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0)); ++ pic->mv_col_bot_ptr = ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1)); ++} ++ ++static void cedrus_write_frame_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM]; ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; ++ struct cedrus_buffer *output_buf; ++ struct cedrus_dev *dev = ctx->dev; ++ unsigned long used_dpbs = 0; ++ unsigned int position; ++ unsigned int output = 0; ++ unsigned int i; ++ ++ memset(pic_list, 0, sizeof(pic_list)); ++ ++ for (i = 0; i < ARRAY_SIZE(decode->dpb); i++) { ++ const struct v4l2_h264_dpb_entry *dpb = &decode->dpb[i]; ++ struct cedrus_buffer *cedrus_buf; ++ int buf_idx; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) ++ continue; ++ ++ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); ++ if (buf_idx < 0) ++ continue; ++ ++ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[buf_idx]); ++ position = cedrus_buf->codec.h264.position; ++ used_dpbs |= BIT(position); ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ continue; ++ ++ cedrus_fill_ref_pic(ctx, cedrus_buf, ++ dpb->top_field_order_cnt, ++ dpb->bottom_field_order_cnt, ++ &pic_list[position]); ++ ++ output = max(position, output); ++ } ++ ++ position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, ++ output); ++ if (position >= CEDRUS_H264_FRAME_NUM) ++ position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); ++ ++ output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); ++ output_buf->codec.h264.position = position; ++ ++ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; ++ else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_MBAFF; ++ else ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FRAME; ++ ++ cedrus_fill_ref_pic(ctx, output_buf, ++ decode->top_field_order_cnt, ++ decode->bottom_field_order_cnt, ++ &pic_list[position]); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_FRAMEBUFFER_LIST, ++ pic_list, sizeof(pic_list)); ++ ++ cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position); ++} ++ ++#define CEDRUS_MAX_REF_IDX 32 ++ ++static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run, ++ const u8 *ref_list, u8 num_ref, ++ enum cedrus_h264_sram_off sram) ++{ ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; ++ struct cedrus_dev *dev = ctx->dev; ++ u8 sram_array[CEDRUS_MAX_REF_IDX]; ++ unsigned int i; ++ size_t size; ++ ++ memset(sram_array, 0, sizeof(sram_array)); ++ ++ for (i = 0; i < num_ref; i++) { ++ const struct v4l2_h264_dpb_entry *dpb; ++ const struct cedrus_buffer *cedrus_buf; ++ const struct vb2_v4l2_buffer *ref_buf; ++ unsigned int position; ++ int buf_idx; ++ u8 dpb_idx; ++ ++ dpb_idx = ref_list[i]; ++ dpb = &decode->dpb[dpb_idx]; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ continue; ++ ++ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); ++ if (buf_idx < 0) ++ continue; ++ ++ ref_buf = to_vb2_v4l2_buffer(ctx->dst_bufs[buf_idx]); ++ cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); ++ position = cedrus_buf->codec.h264.position; ++ ++ sram_array[i] |= position << 1; ++ if (ref_buf->field == V4L2_FIELD_BOTTOM) ++ sram_array[i] |= BIT(0); ++ } ++ ++ size = min_t(size_t, ALIGN(num_ref, 4), sizeof(sram_array)); ++ cedrus_h264_write_sram(dev, sram, &sram_array, size); ++} ++ ++static void cedrus_write_ref_list0(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ ++ _cedrus_write_ref_list(ctx, run, ++ slice->ref_pic_list0, ++ slice->num_ref_idx_l0_active_minus1 + 1, ++ CEDRUS_SRAM_H264_REF_LIST_0); ++} ++ ++static void cedrus_write_ref_list1(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ ++ _cedrus_write_ref_list(ctx, run, ++ slice->ref_pic_list1, ++ slice->num_ref_idx_l1_active_minus1 + 1, ++ CEDRUS_SRAM_H264_REF_LIST_1); ++} ++ ++static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling = ++ run->h264.scaling_matrix; ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_0, ++ scaling->scaling_list_8x8[0], ++ sizeof(scaling->scaling_list_8x8[0])); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, ++ scaling->scaling_list_8x8[3], ++ sizeof(scaling->scaling_list_8x8[3])); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, ++ scaling->scaling_list_4x4, ++ sizeof(scaling->scaling_list_4x4)); ++} ++ ++static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = ++ run->h264.slice_params; ++ const struct v4l2_h264_pred_weight_table *pred_weight = ++ &slice->pred_weight_table; ++ struct cedrus_dev *dev = ctx->dev; ++ int i, j, k; ++ ++ cedrus_write(dev, VE_H264_SHS_WP, ++ ((pred_weight->chroma_log2_weight_denom & 0x7) << 4) | ++ ((pred_weight->luma_log2_weight_denom & 0x7) << 0)); ++ ++ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, ++ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE << 2); ++ ++ for (i = 0; i < ARRAY_SIZE(pred_weight->weight_factors); i++) { ++ const struct v4l2_h264_weight_factors *factors = ++ &pred_weight->weight_factors[i]; ++ ++ for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { ++ u32 val; ++ ++ val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | ++ (factors->luma_weight[j] & 0x1ff); ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); ++ } ++ ++ for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { ++ for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { ++ u32 val; ++ ++ val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | ++ (factors->chroma_weight[j][k] & 0x1ff); ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); ++ } ++ } ++ } ++} ++ ++static void cedrus_set_params(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ struct vb2_buffer *src_buf = &run->src->vb2_buf; ++ struct cedrus_dev *dev = ctx->dev; ++ dma_addr_t src_buf_addr; ++ u32 offset = slice->header_bit_size; ++ u32 len = (slice->size * 8) - offset; ++ u32 reg; ++ ++ cedrus_write(dev, VE_H264_VLD_LEN, len); ++ cedrus_write(dev, VE_H264_VLD_OFFSET, offset); ++ ++ src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); ++ cedrus_write(dev, VE_H264_VLD_END, ++ src_buf_addr + vb2_get_plane_payload(src_buf, 0)); ++ cedrus_write(dev, VE_H264_VLD_ADDR, ++ VE_H264_VLD_ADDR_VAL(src_buf_addr) | ++ VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | ++ VE_H264_VLD_ADDR_LAST); ++ ++ /* ++ * FIXME: Since the bitstream parsing is done in software, and ++ * in userspace, this shouldn't be needed anymore. But it ++ * turns out that removing it breaks the decoding process, ++ * without any clear indication why. ++ */ ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, ++ VE_H264_TRIGGER_TYPE_INIT_SWDEC); ++ ++ if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_P || ++ slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || ++ (pps->weighted_bipred_idc == 1 && ++ slice->slice_type == V4L2_H264_SLICE_TYPE_B)) ++ cedrus_write_pred_weight_table(ctx, run); ++ ++ if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_SP) || ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) ++ cedrus_write_ref_list0(ctx, run); ++ ++ if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) ++ cedrus_write_ref_list1(ctx, run); ++ ++ // picture parameters ++ reg = 0; ++ /* ++ * FIXME: the kernel headers are allowing the default value to ++ * be passed, but the libva doesn't give us that. ++ */ ++ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; ++ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; ++ reg |= (pps->weighted_bipred_idc & 0x3) << 2; ++ if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) ++ reg |= VE_H264_PPS_ENTROPY_CODING_MODE; ++ if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) ++ reg |= VE_H264_PPS_WEIGHTED_PRED; ++ if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) ++ reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; ++ if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) ++ reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; ++ cedrus_write(dev, VE_H264_PPS, reg); ++ ++ // sequence parameters ++ reg = 0; ++ reg |= (sps->chroma_format_idc & 0x7) << 19; ++ reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; ++ reg |= sps->pic_height_in_map_units_minus1 & 0xff; ++ if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) ++ reg |= VE_H264_SPS_MBS_ONLY; ++ if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) ++ reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; ++ if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) ++ reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; ++ cedrus_write(dev, VE_H264_SPS, reg); ++ ++ // slice parameters ++ reg = 0; ++ reg |= decode->nal_ref_idc ? BIT(12) : 0; ++ reg |= (slice->slice_type & 0xf) << 8; ++ reg |= slice->cabac_init_idc & 0x3; ++ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) ++ reg |= VE_H264_SHS_FIELD_PIC; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ++ reg |= VE_H264_SHS_BOTTOM_FIELD; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED) ++ reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; ++ cedrus_write(dev, VE_H264_SHS, reg); ++ ++ reg = 0; ++ reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; ++ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; ++ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; ++ reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; ++ reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; ++ reg |= slice->slice_beta_offset_div2 & 0xf; ++ cedrus_write(dev, VE_H264_SHS2, reg); ++ ++ reg = 0; ++ reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; ++ reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; ++ reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; ++ cedrus_write(dev, VE_H264_SHS_QP, reg); ++ ++ // clear status flags ++ cedrus_write(dev, VE_H264_STATUS, cedrus_read(dev, VE_H264_STATUS)); ++ ++ // enable int ++ cedrus_write(dev, VE_H264_CTRL, ++ VE_H264_CTRL_SLICE_DECODE_INT | ++ VE_H264_CTRL_DECODE_ERR_INT | ++ VE_H264_CTRL_VLD_DATA_REQ_INT); ++} ++ ++static enum cedrus_irq_status ++cedrus_h264_irq_status(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg = cedrus_read(dev, VE_H264_STATUS); ++ ++ if (reg & (VE_H264_STATUS_DECODE_ERR_INT | ++ VE_H264_STATUS_VLD_DATA_REQ_INT)) ++ return CEDRUS_IRQ_ERROR; ++ ++ if (reg & VE_H264_CTRL_SLICE_DECODE_INT) ++ return CEDRUS_IRQ_OK; ++ ++ return CEDRUS_IRQ_NONE; ++} ++ ++static void cedrus_h264_irq_clear(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_H264_STATUS, ++ VE_H264_STATUS_INT_MASK); ++} ++ ++static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg = cedrus_read(dev, VE_H264_CTRL); ++ ++ cedrus_write(dev, VE_H264_CTRL, ++ reg & ~VE_H264_CTRL_INT_MASK); ++} ++ ++static void cedrus_h264_setup(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_engine_enable(dev, CEDRUS_CODEC_H264); ++ ++ cedrus_write(dev, VE_H264_SDROT_CTRL, 0); ++ cedrus_write(dev, VE_H264_EXTRA_BUFFER1, ++ ctx->codec.h264.pic_info_buf_dma); ++ cedrus_write(dev, VE_H264_EXTRA_BUFFER2, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ ++ cedrus_write_scaling_lists(ctx, run); ++ cedrus_write_frame_list(ctx, run); ++ ++ cedrus_set_params(ctx, run); ++} ++ ++static int cedrus_h264_start(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ unsigned int field_size; ++ unsigned int mv_col_size; ++ int ret; ++ ++ /* ++ * FIXME: It seems that the H6 cedarX code is using a formula ++ * here based on the size of the frame, while all the older ++ * code is using a fixed size, so that might need to be ++ * changed at some point. ++ */ ++ ctx->codec.h264.pic_info_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ &ctx->codec.h264.pic_info_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.pic_info_buf) ++ return -ENOMEM; ++ ++ /* ++ * That buffer is supposed to be 16kiB in size, and be aligned ++ * on 16kiB as well. However, dma_alloc_coherent provides the ++ * guarantee that we'll have a CPU and DMA address aligned on ++ * the smallest page order that is greater to the requested ++ * size, so we don't have to overallocate. ++ */ ++ ctx->codec.h264.neighbor_info_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ &ctx->codec.h264.neighbor_info_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.neighbor_info_buf) { ++ ret = -ENOMEM; ++ goto err_pic_buf; ++ } ++ ++ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * ++ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; ++ ++ /* ++ * FIXME: This is actually conditional to ++ * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we ++ * might have to rework this if memory efficiency ever is ++ * something we need to work on. ++ */ ++ field_size = field_size * 2; ++ ++ /* ++ * FIXME: This is actually conditional to ++ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might ++ * have to rework this if memory efficiency ever is something ++ * we need to work on. ++ */ ++ field_size = field_size * 2; ++ ctx->codec.h264.mv_col_buf_field_size = field_size; ++ ++ mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; ++ ctx->codec.h264.mv_col_buf_size = mv_col_size; ++ ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, ++ ctx->codec.h264.mv_col_buf_size, ++ &ctx->codec.h264.mv_col_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.mv_col_buf) { ++ ret = -ENOMEM; ++ goto err_neighbor_buf; ++ } ++ ++ return 0; ++ ++err_neighbor_buf: ++ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h264.neighbor_info_buf, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ ++err_pic_buf: ++ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ ctx->codec.h264.pic_info_buf, ++ ctx->codec.h264.pic_info_buf_dma); ++ return ret; ++} ++ ++static void cedrus_h264_stop(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, ++ ctx->codec.h264.mv_col_buf, ++ ctx->codec.h264.mv_col_buf_dma); ++ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h264.neighbor_info_buf, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ ctx->codec.h264.pic_info_buf, ++ ctx->codec.h264.pic_info_buf_dma); ++} ++ ++static void cedrus_h264_trigger(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, ++ VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); ++} ++ ++struct cedrus_dec_ops cedrus_dec_ops_h264 = { ++ .irq_clear = cedrus_h264_irq_clear, ++ .irq_disable = cedrus_h264_irq_disable, ++ .irq_status = cedrus_h264_irq_status, ++ .setup = cedrus_h264_setup, ++ .start = cedrus_h264_start, ++ .stop = cedrus_h264_stop, ++ .trigger = cedrus_h264_trigger, ++}; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index 60406b2d4595..c34aec7c6e40 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -46,6 +46,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) + reg |= VE_MODE_DEC_MPEG; + break; + ++ case CEDRUS_CODEC_H264: ++ reg |= VE_MODE_DEC_H264; ++ break; ++ + default: + return -EINVAL; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index de2d6b6f64bf..3e9931416e45 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -232,4 +232,95 @@ + #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) + #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) + ++#define VE_H264_SPS 0x200 ++#define VE_H264_SPS_MBS_ONLY BIT(18) ++#define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) ++#define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) ++ ++#define VE_H264_PPS 0x204 ++#define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) ++#define VE_H264_PPS_WEIGHTED_PRED BIT(4) ++#define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) ++#define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) ++ ++#define VE_H264_SHS 0x208 ++#define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) ++#define VE_H264_SHS_FIELD_PIC BIT(4) ++#define VE_H264_SHS_BOTTOM_FIELD BIT(3) ++#define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) ++ ++#define VE_H264_SHS2 0x20c ++#define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) ++ ++#define VE_H264_SHS_WP 0x210 ++ ++#define VE_H264_SHS_QP 0x21c ++#define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) ++ ++#define VE_H264_CTRL 0x220 ++#define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) ++#define VE_H264_CTRL_DECODE_ERR_INT BIT(1) ++#define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) ++ ++#define VE_H264_CTRL_INT_MASK (VE_H264_CTRL_VLD_DATA_REQ_INT | \ ++ VE_H264_CTRL_DECODE_ERR_INT | \ ++ VE_H264_CTRL_SLICE_DECODE_INT) ++ ++#define VE_H264_TRIGGER_TYPE 0x224 ++#define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) ++#define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) ++ ++#define VE_H264_STATUS 0x228 ++#define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT ++#define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT ++#define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT ++ ++#define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK ++ ++#define VE_H264_CUR_MB_NUM 0x22c ++ ++#define VE_H264_VLD_ADDR 0x230 ++#define VE_H264_VLD_ADDR_FIRST BIT(30) ++#define VE_H264_VLD_ADDR_LAST BIT(29) ++#define VE_H264_VLD_ADDR_VALID BIT(28) ++#define VE_H264_VLD_ADDR_VAL(x) (((x) & 0x0ffffff0) | ((x) >> 28)) ++ ++#define VE_H264_VLD_OFFSET 0x234 ++#define VE_H264_VLD_LEN 0x238 ++#define VE_H264_VLD_END 0x23c ++#define VE_H264_SDROT_CTRL 0x240 ++#define VE_H264_OUTPUT_FRAME_IDX 0x24c ++#define VE_H264_EXTRA_BUFFER1 0x250 ++#define VE_H264_EXTRA_BUFFER2 0x254 ++#define VE_H264_BASIC_BITS 0x2dc ++#define VE_AVC_SRAM_PORT_OFFSET 0x2e0 ++#define VE_AVC_SRAM_PORT_DATA 0x2e4 ++ ++#define VE_ISP_INPUT_SIZE 0xa00 ++#define VE_ISP_INPUT_STRIDE 0xa04 ++#define VE_ISP_CTRL 0xa08 ++#define VE_ISP_INPUT_LUMA 0xa78 ++#define VE_ISP_INPUT_CHROMA 0xa7c ++ ++#define VE_AVC_PARAM 0xb04 ++#define VE_AVC_QP 0xb08 ++#define VE_AVC_MOTION_EST 0xb10 ++#define VE_AVC_CTRL 0xb14 ++#define VE_AVC_TRIGGER 0xb18 ++#define VE_AVC_STATUS 0xb1c ++#define VE_AVC_BASIC_BITS 0xb20 ++#define VE_AVC_UNK_BUF 0xb60 ++#define VE_AVC_VLE_ADDR 0xb80 ++#define VE_AVC_VLE_END 0xb84 ++#define VE_AVC_VLE_OFFSET 0xb88 ++#define VE_AVC_VLE_MAX 0xb8c ++#define VE_AVC_VLE_LENGTH 0xb90 ++#define VE_AVC_REF_LUMA 0xba0 ++#define VE_AVC_REF_CHROMA 0xba4 ++#define VE_AVC_REC_LUMA 0xbb0 ++#define VE_AVC_REC_CHROMA 0xbb4 ++#define VE_AVC_REF_SLUMA 0xbb8 ++#define VE_AVC_REC_SLUMA 0xbbc ++#define VE_AVC_MB_INFO 0xbc0 ++ + #endif +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index 9673874ece10..e2b530b1a956 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -37,6 +37,10 @@ static struct cedrus_format cedrus_formats[] = { + .pixelformat = V4L2_PIX_FMT_MPEG2_SLICE, + .directions = CEDRUS_DECODE_SRC, + }, ++ { ++ .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, ++ .directions = CEDRUS_DECODE_SRC, ++ }, + { + .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, + .directions = CEDRUS_DECODE_DST, +@@ -100,6 +104,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) + + switch (pix_fmt->pixelformat) { + case V4L2_PIX_FMT_MPEG2_SLICE: ++ case V4L2_PIX_FMT_H264_SLICE_RAW: + /* Zero bytes per line for encoded source. */ + bytesperline = 0; + +@@ -464,6 +469,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) + ctx->current_codec = CEDRUS_CODEC_MPEG2; + break; + ++ case V4L2_PIX_FMT_H264_SLICE_RAW: ++ ctx->current_codec = CEDRUS_CODEC_H264; ++ break; ++ + default: + return -EINVAL; + } +-- +2.21.0 + +From ca0961011db57e39880df0b5708df8aa3339dc6f Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 18 May 2019 17:40:14 +0200 +Subject: [PATCH] ARM: dts: sun8i-h3: Fix wifi in Beelink X2 DT + +mmc1 node where wifi module is connected doesn't have properly defined +power supplies so wifi module is never powered up. Fix that by +specifying additional power supplies. + +Additionally, this STB may have either Realtek or Broadcom based wifi +module. One based on Broadcom module also needs external clock to work +properly. Fix that by adding clock property to wifi_pwrseq node. + +Fixes: e582b47a9252 ("ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB") +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +index 6277f13f3eb3..ac9e26b1d906 100644 +--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts ++++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +@@ -90,6 +90,8 @@ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; + }; + + sound_spdif { +@@ -155,6 +157,8 @@ + + &mmc1 { + vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +-- +2.21.0 + +From 85c6fadd185e495a3ef9cd8a60bb70b82b72d941 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 14 May 2019 22:54:45 +0200 +Subject: [PATCH] arm64: dts: allwinner: a64: orangepi-win: Add wifi and + bluetooth nodes + +The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side +identifies as BCM43430, while the Bluetooth side identifies as BCM43438. + +WiFi is connected to mmc1 and the Bluetooth side is connected to UART1 +in a 4 wire configuration. Same as the WiFi side, due to being the same +chip and package, DLDO2 provides overall power via VBAT, and DLDO4 +provides I/O power via VDDIO. The RTC clock output provides the LPO low +power clock at 32.768 kHz. + +This patch enables WiFi and Bluetooth on OrangePi Win boards and adds +missing LPO clock on the WiFi side. PCM connection also exists for +Bluetooth audio, but it's not used here. + +Bluetooth UART speed is set to 1.5 MBaud in order to be able transmit +audio. While module supports even higher speeds, currently sunxi clock +driver doesn't support higher speed. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + .../dts/allwinner/sun50i-a64-orangepi-win.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +index 510f661229dc..5ef3c62c765e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +@@ -109,6 +109,8 @@ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; + }; + }; + +@@ -170,6 +172,14 @@ + bus-width = <4>; + non-removable; + status = "okay"; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ ++ interrupt-names = "host-wake"; ++ }; + }; + + &ohci0 { +@@ -342,7 +352,20 @@ + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; + status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <1500000>; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ vbat-supply = <®_dldo2>; ++ vddio-supply = <®_dldo4>; ++ device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ ++ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ ++ }; + }; + + /* On Pi-2 connector, RTS/CTS optional */ +-- +2.21.0 + +From ae3ceed0a399fa0cc83410ce7bbf3a1675b733a9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Thu, 23 May 2019 17:10:49 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: add r_watchog node +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Allwinner H6 has a r_watchdog similar to A64. + +Declare it in the device-tree. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 13e70aebddbe..b9a7dc8d2a40 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -631,6 +631,13 @@ + #reset-cells = <1>; + }; + ++ r_watchdog: watchdog@7020400 { ++ compatible = "allwinner,sun50i-h6-wdt", ++ "allwinner,sun6i-a31-wdt"; ++ reg = <0x07020400 0x20>; ++ interrupts = ; ++ }; ++ + r_intc: interrupt-controller@7021000 { + compatible = "allwinner,sun50i-h6-r-intc", + "allwinner,sun6i-a31-r-intc"; +-- +2.21.0 + +From f7275345728a0ff18a0607dd3706f2ca25dc53e0 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sat, 13 Apr 2019 18:54:12 +0200 +Subject: [PATCH] pinctrl: sunxi: Prepare for alternative bias voltage setting + methods + +H6 has a different I/O voltage bias setting method than A80. Prepare +existing code for using alternative bias voltage setting methods. + +Signed-off-by: Ondrej Jirman +Acked-by: Maxime Ripard +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 2 +- + drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 +- + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 47 ++++++++++++--------- + drivers/pinctrl/sunxi/pinctrl-sunxi.h | 11 ++++- + 4 files changed, 39 insertions(+), 23 deletions(-) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +index e05dd9a5551d..a191a65217ac 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +@@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = { + .pin_base = PL_BASE, + .irq_banks = 2, + .disable_strict_mode = true, +- .has_io_bias_cfg = true, ++ .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, + }; + + static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +index da37d594a13d..0633a03d5e13 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +@@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { + .npins = ARRAY_SIZE(sun9i_a80_pins), + .irq_banks = 5, + .disable_strict_mode = true, +- .has_io_bias_cfg = true, ++ .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, + }; + + static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +index be04223591d4..98c4de5f4019 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -617,7 +617,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + u32 val, reg; + int uV; + +- if (!pctl->desc->has_io_bias_cfg) ++ if (!pctl->desc->io_bias_cfg_variant) + return 0; + + uV = regulator_get_voltage(supply); +@@ -628,25 +628,32 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + if (uV == 0) + return 0; + +- /* Configured value must be equal or greater to actual voltage */ +- if (uV <= 1800000) +- val = 0x0; /* 1.8V */ +- else if (uV <= 2500000) +- val = 0x6; /* 2.5V */ +- else if (uV <= 2800000) +- val = 0x9; /* 2.8V */ +- else if (uV <= 3000000) +- val = 0xA; /* 3.0V */ +- else +- val = 0xD; /* 3.3V */ +- +- pin -= pctl->desc->pin_base; +- +- reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); +- reg &= ~IO_BIAS_MASK; +- writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); +- +- return 0; ++ switch (pctl->desc->io_bias_cfg_variant) { ++ case BIAS_VOLTAGE_GRP_CONFIG: ++ /* ++ * Configured value must be equal or greater to actual ++ * voltage. ++ */ ++ if (uV <= 1800000) ++ val = 0x0; /* 1.8V */ ++ else if (uV <= 2500000) ++ val = 0x6; /* 2.5V */ ++ else if (uV <= 2800000) ++ val = 0x9; /* 2.8V */ ++ else if (uV <= 3000000) ++ val = 0xA; /* 3.0V */ ++ else ++ val = 0xD; /* 3.3V */ ++ ++ pin -= pctl->desc->pin_base; ++ ++ reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); ++ reg &= ~IO_BIAS_MASK; ++ writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); ++ return 0; ++ default: ++ return -EINVAL; ++ } + } + + static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +index ee15ab067b5f..a62b81357136 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +@@ -95,6 +95,15 @@ + #define PINCTRL_SUN7I_A20 BIT(7) + #define PINCTRL_SUN8I_R40 BIT(8) + ++enum sunxi_desc_bias_voltage { ++ BIAS_VOLTAGE_NONE, ++ /* ++ * Bias voltage configuration is done through ++ * Pn_GRP_CONFIG registers, as seen on A80 SoC. ++ */ ++ BIAS_VOLTAGE_GRP_CONFIG, ++}; ++ + struct sunxi_desc_function { + unsigned long variant; + const char *name; +@@ -117,7 +126,7 @@ struct sunxi_pinctrl_desc { + const unsigned int *irq_bank_map; + bool irq_read_needs_mux; + bool disable_strict_mode; +- bool has_io_bias_cfg; ++ enum sunxi_desc_bias_voltage io_bias_cfg_variant; + }; + + struct sunxi_pinctrl_function { +-- +2.21.0 + +From cc62383fcebe7f03c274462790fd912f4346304b Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sat, 13 Apr 2019 18:54:13 +0200 +Subject: [PATCH] pinctrl: sunxi: Support I/O bias voltage setting on H6 + +H6 SoC has a "pio group withstand voltage mode" register (datasheet +description), that needs to be used to select either 1.8V or 3.3V I/O mode, +based on what voltage is powering the respective pin banks and is thus used +for I/O signals. + +Add support for configuring this register according to the voltage of the +pin bank regulator (if enabled). + +This is similar to the support for I/O bias voltage setting patch for A80 +and the same concerns apply. See: + + commit 402bfb3c1352 ("Support I/O bias voltage setting on A80") + +Signed-off-by: Ondrej Jirman +Acked-by: Maxime Ripard +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 11 +++++++++++ + drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +++++++ + 3 files changed, 19 insertions(+) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +index ef4268cc6227..3cc1121589c9 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +@@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = { + .irq_banks = 4, + .irq_bank_map = h6_irq_bank_map, + .irq_read_needs_mux = true, ++ .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + }; + + static int h6_pinctrl_probe(struct platform_device *pdev) +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +index 98c4de5f4019..0cbca30b75dc 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -614,6 +614,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + unsigned pin, + struct regulator *supply) + { ++ unsigned short bank = pin / PINS_PER_BANK; ++ unsigned long flags; + u32 val, reg; + int uV; + +@@ -651,6 +653,15 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, + reg &= ~IO_BIAS_MASK; + writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + return 0; ++ case BIAS_VOLTAGE_PIO_POW_MODE_SEL: ++ val = uV <= 1800000 ? 1 : 0; ++ ++ raw_spin_lock_irqsave(&pctl->lock, flags); ++ reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); ++ reg &= ~(1 << bank); ++ writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); ++ raw_spin_unlock_irqrestore(&pctl->lock, flags); ++ return 0; + default: + return -EINVAL; + } +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +index a62b81357136..44e30deeee38 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h +@@ -95,6 +95,8 @@ + #define PINCTRL_SUN7I_A20 BIT(7) + #define PINCTRL_SUN8I_R40 BIT(8) + ++#define PIO_POW_MOD_SEL_REG 0x340 ++ + enum sunxi_desc_bias_voltage { + BIAS_VOLTAGE_NONE, + /* +@@ -102,6 +104,11 @@ enum sunxi_desc_bias_voltage { + * Pn_GRP_CONFIG registers, as seen on A80 SoC. + */ + BIAS_VOLTAGE_GRP_CONFIG, ++ /* ++ * Bias voltage is set through PIO_POW_MOD_SEL_REG ++ * register, as seen on H6 SoC, for example. ++ */ ++ BIAS_VOLTAGE_PIO_POW_MODE_SEL, + }; + + struct sunxi_desc_function { +-- +2.21.0 + +From 22538576beb671038bd21be4094432fa8070ad81 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Fri, 3 May 2019 17:47:20 +0800 +Subject: [PATCH] arm64: dts: allwinner: h6: add PIO VCC bank supplies for Pine + H64 + +The Allwinner H6 SoC features tweakable VCC for PC, PD, PG, PL and PM +banks. + +This patch adds supplies for these banks except PL bank. PL bank is +where PMIC is attached, and currently if a PMIC regulator is added +for it a dependency loop will happen. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +index 4802902e128f..9e464d40cbff 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +@@ -127,6 +127,12 @@ + status = "okay"; + }; + ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_aldo1>; ++}; ++ + &r_i2c { + status = "okay"; + +@@ -247,6 +253,10 @@ + }; + }; + ++&r_pio { ++ vcc-pm-supply = <®_aldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch b/projects/Allwinner/patches/linux/0004-cedrus-hevc.patch similarity index 74% rename from projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch rename to projects/Allwinner/patches/linux/0004-cedrus-hevc.patch index dd5aac6690..a5184d98a5 100644 --- a/projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch +++ b/projects/Allwinner/patches/linux/0004-cedrus-hevc.patch @@ -1,80 +1,16 @@ -From patchwork Thu Feb 14 09:53:08 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Paul Kocialkowski -X-Patchwork-Id: 10812217 -Return-Path: -Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org - [172.30.200.125]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E14113B4 - for ; - Thu, 14 Feb 2019 09:55:00 +0000 (UTC) -Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED4C528703 - for ; - Thu, 14 Feb 2019 09:54:59 +0000 (UTC) -Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) - id E062E28758; Thu, 14 Feb 2019 09:54:59 +0000 (UTC) -X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on - pdx-wl-mail.web.codeaurora.org -X-Spam-Level: -X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, - RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 -Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 388EF28703 - for ; - Thu, 14 Feb 2019 09:54:57 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S2392986AbfBNJyo (ORCPT - ); - Thu, 14 Feb 2019 04:54:44 -0500 -Received: from relay8-d.mail.gandi.net ([217.70.183.201]:58429 "EHLO - relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S2392838AbfBNJyn (ORCPT - ); - Thu, 14 Feb 2019 04:54:43 -0500 -X-Originating-IP: 90.88.30.68 -Received: from localhost.localdomain - (aaubervilliers-681-1-89-68.w90-88.abo.wanadoo.fr [90.88.30.68]) - (Authenticated sender: paul.kocialkowski@bootlin.com) - by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 7E9C61BF20B; - Thu, 14 Feb 2019 09:54:37 +0000 (UTC) +From 2a7c76208e46bd164d7e968d063d870fcb1e9314 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski -To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, - devel@driverdev.osuosl.org, linux-arm-kernel@lists.infradead.org, - linux-sunxi@googlegroups.com -Cc: Mauro Carvalho Chehab , - Maxime Ripard , - Paul Kocialkowski , - Greg Kroah-Hartman , - Chen-Yu Tsai , - Thomas Petazzoni , - Hans Verkuil , - Sakari Ailus , - Randy Li , - Ezequiel Garcia , - Tomasz Figa , - Alexandre Courbot -Subject: [PATCH v3 1/2] media: v4l: Add definitions for the HEVC slice format - and controls -Date: Thu, 14 Feb 2019 10:53:08 +0100 -Message-Id: <20190214095309.19594-2-paul.kocialkowski@bootlin.com> -X-Mailer: git-send-email 2.20.1 -In-Reply-To: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -References: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -MIME-Version: 1.0 -Sender: linux-media-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-media@vger.kernel.org -X-Virus-Scanned: ClamAV using ClamSMTP +Date: Fri, 24 May 2019 11:36:32 +0200 +Subject: [PATCH 09/12] media: v4l: Add definitions for the HEVC slice controls This introduces the required definitions for HEVC decoding support with stateless VPUs. The controls associated to the HEVC slice format provide the required meta-data for decoding slices extracted from the bitstream. -This interface comes with the following limitations: +They are not exported to the public V4L2 API since reworking this API +will be needed for covering various use-cases and new hardware. + +The interface comes with the following limitations: * No custom quantization matrices (scaling lists); * Support for a single temporal layer only; * No slice entry point offsets support; @@ -83,25 +19,24 @@ This interface comes with the following limitations: * No support for SPS extensions: range, multilayer, 3d, scc, 4 bits; * No support for PPS extensions: range, multilayer, 3d, scc, 4 bits. -Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil --- Documentation/media/uapi/v4l/biblio.rst | 9 + - .../media/uapi/v4l/pixfmt-compressed.rst | 15 + + .../media/uapi/v4l/ext-ctrls-codec.rst | 429 +++++++++++++++++- .../media/uapi/v4l/vidioc-queryctrl.rst | 18 + .../media/videodev2.h.rst.exceptions | 3 + drivers/media/v4l2-core/v4l2-ctrls.c | 26 ++ drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/hevc-ctrls.h | 181 ++++++++ + include/media/hevc-ctrls.h | 182 ++++++++ include/media/v4l2-ctrls.h | 7 + - include/uapi/linux/videodev2.h | 1 + - 10 files changed, 679 insertions(+) + 8 files changed, 672 insertions(+), 3 deletions(-) create mode 100644 include/media/hevc-ctrls.h diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst -index 3fc3f7ff338a..b4b3fcec55dd 100644 +index 8f4eb8823d82..e38ef5ee4209 100644 --- a/Documentation/media/uapi/v4l/biblio.rst +++ b/Documentation/media/uapi/v4l/biblio.rst -@@ -131,6 +131,15 @@ ITU H.264 +@@ -131,6 +131,15 @@ ITU-T Rec. H.264 Specification (04/2017 Edition) :author: International Telecommunication Union (http://www.itu.ch) @@ -117,39 +52,457 @@ index 3fc3f7ff338a..b4b3fcec55dd 100644 .. _jfif: JFIF -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index b6f857ac1a8e..ee82526cdc00 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -138,6 +138,21 @@ Compressed Formats - - ``V4L2_PIX_FMT_HEVC`` - - 'HEVC' - - HEVC/H.265 video elementary stream. -+ * .. _V4L2-PIX-FMT-HEVC-SLICE: +diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +index b0c178f0ff9b..19e5bfba888b 100644 +--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst ++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst +@@ -1981,9 +1981,9 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - + - ``reference_ts`` + - Timestamp of the V4L2 capture buffer to use as reference, used + with B-coded and P-coded frames. The timestamp refers to the +- ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the +- :c:func:`v4l2_timeval_to_ns()` function to convert the struct +- :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. ++ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the ++ :c:func:`v4l2_timeval_to_ns()` function to convert the struct ++ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. + * - __u16 + - ``frame_num`` + - +@@ -3291,3 +3291,426 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + Indicates whether to generate SPS and PPS at every IDR. Setting it to 0 + disables generating SPS and PPS at every IDR. Setting it to one enables + generating SPS and PPS at every IDR. + -+ - ``V4L2_PIX_FMT_HEVC_SLICE`` -+ - 'S265' -+ - HEVC parsed slice data, as extracted from the HEVC bitstream. -+ This format is adapted for stateless video decoders that implement a -+ HEVC pipeline (using the :ref:`codec` and :ref:`media-request-api`). -+ Metadata associated with the frame to decode is required to be passed -+ through the following controls : -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` -+ See the :ref:`associated Codec Control IDs `. -+ Buffers associated with this pixel format must contain the appropriate -+ number of macroblocks to decode a full corresponding frame. - * .. _V4L2-PIX-FMT-FWHT: - - - ``V4L2_PIX_FMT_FWHT`` ++.. _v4l2-mpeg-hevc: ++ ++``V4L2_CID_MPEG_VIDEO_HEVC_SPS (struct)`` ++ Specifies the Sequence Parameter Set fields (as extracted from the ++ bitstream) for the associated HEVC slice data. ++ These bitstream parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.3.2 "Sequence parameter set RBSP ++ semantics" of the specification. ++ ++.. c:type:: v4l2_ctrl_hevc_sps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_hevc_sps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``chroma_format_idc`` ++ - ++ * - __u8 ++ - ``separate_colour_plane_flag`` ++ - ++ * - __u16 ++ - ``pic_width_in_luma_samples`` ++ - ++ * - __u16 ++ - ``pic_height_in_luma_samples`` ++ - ++ * - __u8 ++ - ``bit_depth_luma_minus8`` ++ - ++ * - __u8 ++ - ``bit_depth_chroma_minus8`` ++ - ++ * - __u8 ++ - ``log2_max_pic_order_cnt_lsb_minus4`` ++ - ++ * - __u8 ++ - ``sps_max_dec_pic_buffering_minus1`` ++ - ++ * - __u8 ++ - ``sps_max_num_reorder_pics`` ++ - ++ * - __u8 ++ - ``sps_max_latency_increase_plus1`` ++ - ++ * - __u8 ++ - ``log2_min_luma_coding_block_size_minus3`` ++ - ++ * - __u8 ++ - ``log2_diff_max_min_luma_coding_block_size`` ++ - ++ * - __u8 ++ - ``log2_min_luma_transform_block_size_minus2`` ++ - ++ * - __u8 ++ - ``log2_diff_max_min_luma_transform_block_size`` ++ - ++ * - __u8 ++ - ``max_transform_hierarchy_depth_inter`` ++ - ++ * - __u8 ++ - ``max_transform_hierarchy_depth_intra`` ++ - ++ * - __u8 ++ - ``scaling_list_enabled_flag`` ++ - ++ * - __u8 ++ - ``amp_enabled_flag`` ++ - ++ * - __u8 ++ - ``sample_adaptive_offset_enabled_flag`` ++ - ++ * - __u8 ++ - ``pcm_enabled_flag`` ++ - ++ * - __u8 ++ - ``pcm_sample_bit_depth_luma_minus1`` ++ - ++ * - __u8 ++ - ``pcm_sample_bit_depth_chroma_minus1`` ++ - ++ * - __u8 ++ - ``log2_min_pcm_luma_coding_block_size_minus3`` ++ - ++ * - __u8 ++ - ``log2_diff_max_min_pcm_luma_coding_block_size`` ++ - ++ * - __u8 ++ - ``pcm_loop_filter_disabled_flag`` ++ - ++ * - __u8 ++ - ``num_short_term_ref_pic_sets`` ++ - ++ * - __u8 ++ - ``long_term_ref_pics_present_flag`` ++ - ++ * - __u8 ++ - ``num_long_term_ref_pics_sps`` ++ - ++ * - __u8 ++ - ``sps_temporal_mvp_enabled_flag`` ++ - ++ * - __u8 ++ - ``strong_intra_smoothing_enabled_flag`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_HEVC_PPS (struct)`` ++ Specifies the Picture Parameter Set fields (as extracted from the ++ bitstream) for the associated HEVC slice data. ++ These bitstream parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.3.3 "Picture parameter set RBSP ++ semantics" of the specification. ++ ++.. c:type:: v4l2_ctrl_hevc_pps ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_hevc_pps ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``dependent_slice_segment_flag`` ++ - ++ * - __u8 ++ - ``output_flag_present_flag`` ++ - ++ * - __u8 ++ - ``num_extra_slice_header_bits`` ++ - ++ * - __u8 ++ - ``sign_data_hiding_enabled_flag`` ++ - ++ * - __u8 ++ - ``cabac_init_present_flag`` ++ - ++ * - __s8 ++ - ``init_qp_minus26`` ++ - ++ * - __u8 ++ - ``constrained_intra_pred_flag`` ++ - ++ * - __u8 ++ - ``transform_skip_enabled_flag`` ++ - ++ * - __u8 ++ - ``cu_qp_delta_enabled_flag`` ++ - ++ * - __u8 ++ - ``diff_cu_qp_delta_depth`` ++ - ++ * - __s8 ++ - ``pps_cb_qp_offset`` ++ - ++ * - __s8 ++ - ``pps_cr_qp_offset`` ++ - ++ * - __u8 ++ - ``pps_slice_chroma_qp_offsets_present_flag`` ++ - ++ * - __u8 ++ - ``weighted_pred_flag`` ++ - ++ * - __u8 ++ - ``weighted_bipred_flag`` ++ - ++ * - __u8 ++ - ``transquant_bypass_enabled_flag`` ++ - ++ * - __u8 ++ - ``tiles_enabled_flag`` ++ - ++ * - __u8 ++ - ``entropy_coding_sync_enabled_flag`` ++ - ++ * - __u8 ++ - ``num_tile_columns_minus1`` ++ - ++ * - __u8 ++ - ``num_tile_rows_minus1`` ++ - ++ * - __u8 ++ - ``column_width_minus1[20]`` ++ - ++ * - __u8 ++ - ``row_height_minus1[22]`` ++ - ++ * - __u8 ++ - ``loop_filter_across_tiles_enabled_flag`` ++ - ++ * - __u8 ++ - ``pps_loop_filter_across_slices_enabled_flag`` ++ - ++ * - __u8 ++ - ``deblocking_filter_override_enabled_flag`` ++ - ++ * - __u8 ++ - ``pps_disable_deblocking_filter_flag`` ++ - ++ * - __s8 ++ - ``pps_beta_offset_div2`` ++ - ++ * - __s8 ++ - ``pps_tc_offset_div2`` ++ - ++ * - __u8 ++ - ``lists_modification_present_flag`` ++ - ++ * - __u8 ++ - ``log2_parallel_merge_level_minus2`` ++ - ++ * - __u8 ++ - ``slice_segment_header_extension_present_flag`` ++ - ++ ++``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (struct)`` ++ Specifies various slice-specific parameters, especially from the NAL unit ++ header, general slice segment header and weighted prediction parameter ++ parts of the bitstream. ++ These bitstream parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.7 "General slice segment header ++ semantics" of the specification. ++ ++.. c:type:: v4l2_ctrl_hevc_slice_params ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_ctrl_hevc_slice_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``bit_size`` ++ - Size (in bits) of the current slice data. ++ * - __u32 ++ - ``data_bit_offset`` ++ - Offset (in bits) to the video data in the current slice data. ++ * - __u8 ++ - ``nal_unit_type`` ++ - ++ * - __u8 ++ - ``nuh_temporal_id_plus1`` ++ - ++ * - __u8 ++ - ``slice_type`` ++ - ++ (V4L2_HEVC_SLICE_TYPE_I, V4L2_HEVC_SLICE_TYPE_P or ++ V4L2_HEVC_SLICE_TYPE_B). ++ * - __u8 ++ - ``colour_plane_id`` ++ - ++ * - __u16 ++ - ``slice_pic_order_cnt`` ++ - ++ * - __u8 ++ - ``slice_sao_luma_flag`` ++ - ++ * - __u8 ++ - ``slice_sao_chroma_flag`` ++ - ++ * - __u8 ++ - ``slice_temporal_mvp_enabled_flag`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l0_active_minus1`` ++ - ++ * - __u8 ++ - ``num_ref_idx_l1_active_minus1`` ++ - ++ * - __u8 ++ - ``mvd_l1_zero_flag`` ++ - ++ * - __u8 ++ - ``cabac_init_flag`` ++ - ++ * - __u8 ++ - ``collocated_from_l0_flag`` ++ - ++ * - __u8 ++ - ``collocated_ref_idx`` ++ - ++ * - __u8 ++ - ``five_minus_max_num_merge_cand`` ++ - ++ * - __u8 ++ - ``use_integer_mv_flag`` ++ - ++ * - __s8 ++ - ``slice_qp_delta`` ++ - ++ * - __s8 ++ - ``slice_cb_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_cr_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_act_y_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_act_cb_qp_offset`` ++ - ++ * - __s8 ++ - ``slice_act_cr_qp_offset`` ++ - ++ * - __u8 ++ - ``slice_deblocking_filter_disabled_flag`` ++ - ++ * - __s8 ++ - ``slice_beta_offset_div2`` ++ - ++ * - __s8 ++ - ``slice_tc_offset_div2`` ++ - ++ * - __u8 ++ - ``slice_loop_filter_across_slices_enabled_flag`` ++ - ++ * - __u8 ++ - ``pic_struct`` ++ - ++ * - struct :c:type:`v4l2_hevc_dpb_entry` ++ - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - The decoded picture buffer, for meta-data about reference frames. ++ * - __u8 ++ - ``num_active_dpb_entries`` ++ - The number of entries in ``dpb``. ++ * - __u8 ++ - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - The list of L0 reference elements as indices in the DPB. ++ * - __u8 ++ - ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - The list of L1 reference elements as indices in the DPB. ++ * - __u8 ++ - ``num_rps_poc_st_curr_before`` ++ - The number of reference pictures in the short-term set that come before ++ the current frame. ++ * - __u8 ++ - ``num_rps_poc_st_curr_after`` ++ - The number of reference pictures in the short-term set that come after ++ the current frame. ++ * - __u8 ++ - ``num_rps_poc_lt_curr`` ++ - The number of reference pictures in the long-term set. ++ * - struct :c:type:`v4l2_hevc_pred_weight_table` ++ - ``pred_weight_table`` ++ - The prediction weight coefficients for inter-picture prediction. ++ ++.. c:type:: v4l2_hevc_dpb_entry ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_hevc_dpb_entry ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u64 ++ - ``timestamp`` ++ - Timestamp of the V4L2 capture buffer to use as reference, used ++ with B-coded and P-coded frames. The timestamp refers to the ++ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the ++ :c:func:`v4l2_timeval_to_ns()` function to convert the struct ++ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. ++ * - __u8 ++ - ``rps`` ++ - The reference set for the reference frame ++ (V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE, ++ V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER or ++ V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) ++ * - __u8 ++ - ``field_pic`` ++ - Whether the reference is a field picture or a frame. ++ * - __u16 ++ - ``pic_order_cnt[2]`` ++ - The picture order count of the reference. Only the first element of the ++ array is used for frame pictures, while the first element identifies the ++ top field and the second the bottom field in field-coded pictures. ++ ++.. c:type:: v4l2_hevc_pred_weight_table ++ ++.. cssclass:: longtable ++ ++.. flat-table:: struct v4l2_hevc_pred_weight_table ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``luma_log2_weight_denom`` ++ - ++ * - __s8 ++ - ``delta_chroma_log2_weight_denom`` ++ - ++ * - __s8 ++ - ``delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - ++ * - __s8 ++ - ``chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - ++ * - __s8 ++ - ``delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` ++ - ++ * - __s8 ++ - ``delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - ++ * - __s8 ++ - ``chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` ++ - diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -index bf29dc5b9758..f37cb377e258 100644 +index dc500632095d..e090ef33231c 100644 --- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst @@ -473,6 +473,24 @@ See also the examples in :ref:`control`. - n/a - - A struct :c:type:`v4l2_ctrl_h264_decode_param`, containing H264 + - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 decode parameters for stateless video decoders. + * - ``V4L2_CTRL_TYPE_HEVC_SPS`` + - n/a @@ -187,10 +540,10 @@ index 55cbe324b9fc..afba7d71971a 100644 # V4L2 capability defines replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 366200d31bc0..106c80ec9312 100644 +index b72dc54ba638..d93717697402 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -916,6 +916,9 @@ const char *v4l2_ctrl_get_name(u32 id) +@@ -944,6 +944,9 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD: return "HEVC Size of Length Field"; case V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES: return "Reference Frames for a P-Frame"; case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: return "Prepend SPS and PPS to IDR"; @@ -200,7 +553,7 @@ index 366200d31bc0..106c80ec9312 100644 /* CAMERA controls */ /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1323,6 +1326,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, +@@ -1357,6 +1360,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; break; @@ -216,7 +569,7 @@ index 366200d31bc0..106c80ec9312 100644 default: *type = V4L2_CTRL_TYPE_INTEGER; break; -@@ -1696,6 +1708,11 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, +@@ -1733,6 +1745,11 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: return 0; @@ -228,9 +581,9 @@ index 366200d31bc0..106c80ec9312 100644 default: return -EINVAL; } -@@ -2291,6 +2308,15 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, +@@ -2331,6 +2348,15 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_h264_decode_param); + elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); break; + case V4L2_CTRL_TYPE_HEVC_SPS: + elem_size = sizeof(struct v4l2_ctrl_hevc_sps); @@ -245,23 +598,23 @@ index 366200d31bc0..106c80ec9312 100644 if (type < V4L2_CTRL_COMPOUND_TYPES) elem_size = sizeof(s32); diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 8aa7de17ecfa..e792fc97e263 100644 +index f6e1254064d2..0960f719da5d 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1331,6 +1331,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1337,6 +1337,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_VP8: descr = "VP8"; break; case V4L2_PIX_FMT_VP9: descr = "VP9"; break; case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ + case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ + case V4L2_PIX_FMT_FWHT_STATELESS: descr = "FWHT Stateless"; break; /* used in vicodec */ case V4L2_PIX_FMT_CPIA1: descr = "GSPCA CPiA YUV"; break; - case V4L2_PIX_FMT_WNVA: descr = "WNVA"; break; diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h new file mode 100644 -index 000000000000..005c71c67163 +index 000000000000..9ea013c88afc --- /dev/null +++ b/include/media/hevc-ctrls.h -@@ -0,0 +1,181 @@ +@@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * These are the HEVC state controls for use with stateless HEVC @@ -275,19 +628,20 @@ index 000000000000..005c71c67163 +#ifndef _HEVC_CTRLS_H_ +#define _HEVC_CTRLS_H_ + -+#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 645) -+#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 646) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 647) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) ++#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) + +/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_HEVC_SPS 0x0115 -+#define V4L2_CTRL_TYPE_HEVC_PPS 0x0116 -+#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0117 ++#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 ++#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 ++#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 + +#define V4L2_HEVC_SLICE_TYPE_B 0 +#define V4L2_HEVC_SLICE_TYPE_P 1 +#define V4L2_HEVC_SLICE_TYPE_I 2 + ++/* The controls are not stable at the moment and will likely be reworked. */ +struct v4l2_ctrl_hevc_sps { + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + __u8 chroma_format_idc; @@ -444,120 +798,137 @@ index 000000000000..005c71c67163 + +#endif diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 22b6d09c4764..f24a835e5920 100644 +index a8aede26491e..630083e1936d 100644 --- a/include/media/v4l2-ctrls.h +++ b/include/media/v4l2-ctrls.h -@@ -28,6 +28,7 @@ - */ +@@ -29,6 +29,7 @@ #include + #include #include +#include /* forward references */ struct file; -@@ -55,6 +56,9 @@ struct poll_table_struct; +@@ -57,6 +58,9 @@ struct poll_table_struct; * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. - * @p_h264_slice_param: Pointer to a struct v4l2_ctrl_h264_slice_params. - * @p_h264_decode_param: Pointer to a struct v4l2_ctrl_h264_decode_params. + * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. + * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. + * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. + * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. + * @p_hevc_slice_params Pointer to an HEVC slice parameters structure. * @p: Pointer to a compound value. */ union v4l2_ctrl_ptr { -@@ -71,6 +75,9 @@ union v4l2_ctrl_ptr { +@@ -74,6 +78,9 @@ union v4l2_ctrl_ptr { struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; - struct v4l2_ctrl_h264_slice_params *p_h264_slice_param; - struct v4l2_ctrl_h264_decode_params *p_h264_decode_param; + struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; + struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; + struct v4l2_ctrl_hevc_sps *p_hevc_sps; + struct v4l2_ctrl_hevc_pps *p_hevc_pps; + struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; void *p; }; -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 673172c84fb9..5ae4f00f4078 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -669,6 +669,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ - #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ - #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ -+#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ - #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ - - /* Vendor-specific formats */ +-- +2.21.0 -From patchwork Thu Feb 14 09:53:09 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Paul Kocialkowski -X-Patchwork-Id: 10812215 -Return-Path: -Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org - [172.30.200.125]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE979746 - for ; - Thu, 14 Feb 2019 09:54:56 +0000 (UTC) -Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB33928703 - for ; - Thu, 14 Feb 2019 09:54:56 +0000 (UTC) -Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) - id 9ED1728752; Thu, 14 Feb 2019 09:54:56 +0000 (UTC) -X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on - pdx-wl-mail.web.codeaurora.org -X-Spam-Level: -X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, - RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 -Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) - by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6651528703 - for ; - Thu, 14 Feb 2019 09:54:54 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S2438109AbfBNJys (ORCPT - ); - Thu, 14 Feb 2019 04:54:48 -0500 -Received: from relay8-d.mail.gandi.net ([217.70.183.201]:40921 "EHLO - relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S2392881AbfBNJyq (ORCPT - ); - Thu, 14 Feb 2019 04:54:46 -0500 -X-Originating-IP: 90.88.30.68 -Received: from localhost.localdomain - (aaubervilliers-681-1-89-68.w90-88.abo.wanadoo.fr [90.88.30.68]) - (Authenticated sender: paul.kocialkowski@bootlin.com) - by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 2F2A01BF219; - Thu, 14 Feb 2019 09:54:39 +0000 (UTC) +From dd424b21e39cd7e65a40298ddbaba468878ad1f5 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski -To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, - devel@driverdev.osuosl.org, linux-arm-kernel@lists.infradead.org, - linux-sunxi@googlegroups.com -Cc: Mauro Carvalho Chehab , - Maxime Ripard , - Paul Kocialkowski , - Greg Kroah-Hartman , - Chen-Yu Tsai , - Thomas Petazzoni , - Hans Verkuil , - Sakari Ailus , - Randy Li , - Ezequiel Garcia , - Tomasz Figa , - Alexandre Courbot -Subject: [PATCH v3 2/2] media: cedrus: Add HEVC/H.265 decoding support -Date: Thu, 14 Feb 2019 10:53:09 +0100 -Message-Id: <20190214095309.19594-3-paul.kocialkowski@bootlin.com> -X-Mailer: git-send-email 2.20.1 -In-Reply-To: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -References: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> -MIME-Version: 1.0 -Sender: linux-media-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-media@vger.kernel.org -X-Virus-Scanned: ClamAV using ClamSMTP +Date: Fri, 24 May 2019 11:36:33 +0200 +Subject: [PATCH 10/12] media: pixfmt: Add HEVC slice pixel format + +Introduce the V4L2_PIX_FMT_HEVC_SLICE pixel format, which currently +describes an output buffer with enough appended slice data for +producing one decoded frame with a stateless video decoder. + +This will need to be reworked (along with the controls and the core) to +allow passing slice data individually, as it is the natural decoding +unit in HEVC. + +We also need to figure out the description of the possible source data: +* Compressed slice data only, with slice controls attached; +* Slice data in Annex-B format (with raw slice header), without slice + controls attached; +* Slice data in Annex-B format (with raw slice header), with slice + controls attached. + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +--- + include/media/hevc-ctrls.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h +index 9ea013c88afc..2de83d9f6d47 100644 +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -11,6 +11,9 @@ + #ifndef _HEVC_CTRLS_H_ + #define _HEVC_CTRLS_H_ + ++/* The pixel format isn't stable at the moment and will likely be renamed. */ ++#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ ++ + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) +-- +2.21.0 + +From 256c89e4dd0621198cad6fbf0689682116cad795 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Fri, 24 May 2019 11:36:34 +0200 +Subject: [PATCH 11/12] media: pixfmt: Document the HEVC slice pixel format + +Document the current state of the HEVC slice pixel format. +The format will need to evolve in the future, which is why it is +not part of the public API. + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +--- + .../media/uapi/v4l/pixfmt-compressed.rst | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +index 4b701fc7653e..9d4195723c3e 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +@@ -143,6 +143,27 @@ Compressed Formats + - ``V4L2_PIX_FMT_HEVC`` + - 'HEVC' + - HEVC/H.265 video elementary stream. ++ * .. _V4L2-PIX-FMT-HEVC-SLICE: ++ ++ - ``V4L2_PIX_FMT_HEVC_SLICE`` ++ - 'S265' ++ - HEVC parsed slice data, as extracted from the HEVC bitstream. ++ This format is adapted for stateless video decoders that implement a ++ HEVC pipeline (using the :ref:`codec` and :ref:`media-request-api`). ++ Metadata associated with the frame to decode is required to be passed ++ through the following controls : ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` ++ See the :ref:`associated Codec Control IDs `. ++ Buffers associated with this pixel format must contain the appropriate ++ number of macroblocks to decode a full corresponding frame. ++ ++ .. note:: ++ ++ This format is not yet part of the public kernel API and it ++ is expected to change. ++ + * .. _V4L2-PIX-FMT-FWHT: + + - ``V4L2_PIX_FMT_FWHT`` +-- +2.21.0 + +From ef19574101a1e649c440c43615420b7047f8f4ef Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Fri, 24 May 2019 11:36:35 +0200 +Subject: [PATCH 12/12] media: cedrus: Add HEVC/H.265 decoding support This introduces support for HEVC/H.265 to the Cedrus VPU driver, with both uni-directional and bi-directional prediction modes supported. @@ -566,37 +937,37 @@ Field-coded (interlaced) pictures, custom quantization matrices and 10-bit output are not supported at this point. Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil --- drivers/staging/media/sunxi/cedrus/Makefile | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus.c | 27 +- + drivers/staging/media/sunxi/cedrus/cedrus.c | 31 +- drivers/staging/media/sunxi/cedrus/cedrus.h | 18 + .../staging/media/sunxi/cedrus/cedrus_dec.c | 9 + - .../staging/media/sunxi/cedrus/cedrus_h265.c | 531 ++++++++++++++++++ + .../staging/media/sunxi/cedrus/cedrus_h265.c | 532 ++++++++++++++++++ .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 + .../staging/media/sunxi/cedrus/cedrus_regs.h | 290 ++++++++++ .../staging/media/sunxi/cedrus/cedrus_video.c | 10 + - 8 files changed, 887 insertions(+), 4 deletions(-) + 8 files changed, 891 insertions(+), 5 deletions(-) create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h265.c diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile -index aaf141fc58b6..186cb6d01b67 100644 +index c85ac6db0302..1bce49d3e7e2 100644 --- a/drivers/staging/media/sunxi/cedrus/Makefile +++ b/drivers/staging/media/sunxi/cedrus/Makefile -@@ -1,4 +1,4 @@ +@@ -2,4 +2,4 @@ obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ - cedrus_mpeg2.o cedrus_h264.o + cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index b275607b8111..a713630ce7ba 100644 +index 370937edfc14..70642834f351 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -68,6 +68,23 @@ static const struct cedrus_control cedrus_controls[] = { - .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, - .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), +@@ -70,6 +70,24 @@ static const struct cedrus_control cedrus_controls[] = { .codec = CEDRUS_CODEC_H264, -+ }, + .required = true, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, + .elem_size = sizeof(struct v4l2_ctrl_hevc_sps), @@ -613,10 +984,12 @@ index b275607b8111..a713630ce7ba 100644 + .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, + .elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params), + .codec = CEDRUS_CODEC_H265, - .required = true, - }, ++ .required = true, ++ }, }; -@@ -309,6 +326,7 @@ static int cedrus_probe(struct platform_device *pdev) + + #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) +@@ -309,6 +327,7 @@ static int cedrus_probe(struct platform_device *pdev) dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; @@ -624,38 +997,49 @@ index b275607b8111..a713630ce7ba 100644 mutex_init(&dev->dev_mutex); -@@ -416,15 +434,18 @@ static const struct cedrus_variant sun8i_a33_cedrus_variant = { +@@ -417,22 +436,26 @@ static const struct cedrus_variant sun8i_a33_cedrus_variant = { }; static const struct cedrus_variant sun8i_h3_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, + .capabilities = CEDRUS_CAPABILITY_UNTILED | + CEDRUS_CAPABILITY_H265_DEC, + .mod_rate = 402000000, }; static const struct cedrus_variant sun50i_a64_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, + .capabilities = CEDRUS_CAPABILITY_UNTILED | + CEDRUS_CAPABILITY_H265_DEC, + .mod_rate = 402000000, }; static const struct cedrus_variant sun50i_h5_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, + .capabilities = CEDRUS_CAPABILITY_UNTILED | + CEDRUS_CAPABILITY_H265_DEC, + .mod_rate = 402000000, }; - static const struct of_device_id cedrus_dt_match[] = { + static const struct cedrus_variant sun50i_h6_cedrus_variant = { +- .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .capabilities = CEDRUS_CAPABILITY_UNTILED | ++ CEDRUS_CAPABILITY_H265_DEC, + .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, + .mod_rate = 600000000, + }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 8c64f9a27e9d..b5d083812bea 100644 +index 3f476d0fd981..f19be772d78b 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -27,10 +27,12 @@ +@@ -27,12 +27,14 @@ #define CEDRUS_NAME "cedrus" #define CEDRUS_CAPABILITY_UNTILED BIT(0) +#define CEDRUS_CAPABILITY_H265_DEC BIT(1) + #define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) + enum cedrus_codec { CEDRUS_CODEC_MPEG2, CEDRUS_CODEC_H264, @@ -663,7 +1047,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 CEDRUS_CODEC_LAST, }; -@@ -66,6 +68,12 @@ struct cedrus_mpeg2_run { +@@ -68,6 +70,12 @@ struct cedrus_mpeg2_run { const struct v4l2_ctrl_mpeg2_quantization *quantization; }; @@ -676,7 +1060,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 struct cedrus_run { struct vb2_v4l2_buffer *src; struct vb2_v4l2_buffer *dst; -@@ -73,6 +81,7 @@ struct cedrus_run { +@@ -75,6 +83,7 @@ struct cedrus_run { union { struct cedrus_h264_run h264; struct cedrus_mpeg2_run mpeg2; @@ -684,7 +1068,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 }; }; -@@ -111,6 +120,14 @@ struct cedrus_ctx { +@@ -113,6 +122,14 @@ struct cedrus_ctx { void *neighbor_info_buf; dma_addr_t neighbor_info_buf_dma; } h264; @@ -699,7 +1083,7 @@ index 8c64f9a27e9d..b5d083812bea 100644 } codec; }; -@@ -154,6 +171,7 @@ struct cedrus_dev { +@@ -158,6 +175,7 @@ struct cedrus_dev { extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; extern struct cedrus_dec_ops cedrus_dec_ops_h264; @@ -708,10 +1092,10 @@ index 8c64f9a27e9d..b5d083812bea 100644 static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) { diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index abf17dc18ecf..c50397f8692f 100644 +index bdad87eb9d79..c6d0ef66cdd0 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -61,6 +61,15 @@ void cedrus_device_run(void *priv) +@@ -59,6 +59,15 @@ void cedrus_device_run(void *priv) V4L2_CID_MPEG_VIDEO_H264_SPS); break; @@ -729,10 +1113,10 @@ index abf17dc18ecf..c50397f8692f 100644 } diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c new file mode 100644 -index 000000000000..f1c3665e95ab +index 000000000000..fd4d86b02156 --- /dev/null +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -0,0 +1,531 @@ +@@ -0,0 +1,532 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Cedrus VPU driver @@ -849,16 +1233,17 @@ index 000000000000..f1c3665e95ab + u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + + VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; + struct cedrus_h265_sram_frame_info frame_info = { -+ .top_pic_order_cnt = pic_order_cnt[0], -+ .bottom_pic_order_cnt = field_pic ? pic_order_cnt[1] : -+ pic_order_cnt[0], ++ .top_pic_order_cnt = cpu_to_le32(pic_order_cnt[0]), ++ .bottom_pic_order_cnt = cpu_to_le32(field_pic ? ++ pic_order_cnt[1] : ++ pic_order_cnt[0]), + .top_mv_col_buf_addr = -+ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0]), -+ .bottom_mv_col_buf_addr = field_pic ? ++ cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), ++ .bottom_mv_col_buf_addr = cpu_to_le32(field_pic ? + VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) : -+ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0]), -+ .luma_addr = VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr), -+ .chroma_addr = VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr), ++ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), ++ .luma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr)), ++ .chroma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr)), + }; + + cedrus_h265_sram_write_offset(dev, offset); @@ -925,7 +1310,7 @@ index 000000000000..f1c3665e95ab + u32 sram_luma_offset, + u32 sram_chroma_offset) +{ -+ struct cedrus_h265_sram_pred_weight pred_weight[2] = { 0 }; ++ struct cedrus_h265_sram_pred_weight pred_weight[2] = { { 0 } }; + unsigned int i, j; + + cedrus_h265_sram_write_offset(dev, sram_luma_offset); @@ -1265,7 +1650,7 @@ index 000000000000..f1c3665e95ab + .trigger = cedrus_h265_trigger, +}; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index ab402b0cac4e..6be604c52d5c 100644 +index c34aec7c6e40..7d2f6eedfc28 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -50,6 +50,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) @@ -1592,7 +1977,7 @@ index 3e9931416e45..87651d6b6227 100644 #define VE_H264_SPS_MBS_ONLY BIT(18) #define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index d1c0562d1a62..b871976b5ead 100644 +index e2b530b1a956..6cc65d85cf98 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c @@ -41,6 +41,11 @@ static struct cedrus_format cedrus_formats[] = { @@ -1626,3 +2011,5 @@ index d1c0562d1a62..b871976b5ead 100644 default: return -EINVAL; } +-- +2.21.0 diff --git a/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch b/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch deleted file mode 100644 index 923ccba80d..0000000000 --- a/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch +++ /dev/null @@ -1,1420 +0,0 @@ -Date: Thu, 4 Apr 2019 14:59:02 +0200 - -From: Pawel Osciak - -Stateless video codecs will require both the H264 metadata and slices in -order to be able to decode frames. - -This introduces the definitions for a new pixel format for H264 slices that -have been parsed, as well as the structures used to pass the metadata from -the userspace to the kernel. - -Reviewed-by: Tomasz Figa -Signed-off-by: Pawel Osciak -Signed-off-by: Guenter Roeck -Co-developed-by: Maxime Ripard -Signed-off-by: Maxime Ripard ---- - Documentation/media/uapi/v4l/biblio.rst | 9 +- - Documentation/media/uapi/v4l/ext-ctrls-codec.rst | 569 ++++++++++++++- - Documentation/media/uapi/v4l/pixfmt-compressed.rst | 19 +- - Documentation/media/uapi/v4l/vidioc-queryctrl.rst | 30 +- - Documentation/media/videodev2.h.rst.exceptions | 5 +- - drivers/media/v4l2-core/v4l2-ctrls.c | 42 +- - drivers/media/v4l2-core/v4l2-ioctl.c | 1 +- - include/media/h264-ctrls.h | 192 +++++- - include/media/v4l2-ctrls.h | 13 +- - include/uapi/linux/videodev2.h | 1 +- - 10 files changed, 880 insertions(+), 1 deletion(-) - create mode 100644 include/media/h264-ctrls.h - -diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst -index ec33768c055e..8f4eb8823d82 100644 ---- a/Documentation/media/uapi/v4l/biblio.rst -+++ b/Documentation/media/uapi/v4l/biblio.rst -@@ -122,6 +122,15 @@ ITU BT.1119 - - :author: International Telecommunication Union (http://www.itu.ch) - -+.. _h264: -+ -+ITU-T Rec. H.264 Specification (04/2017 Edition) -+================================================ -+ -+:title: ITU-T Recommendation H.264 "Advanced Video Coding for Generic Audiovisual Services" -+ -+:author: International Telecommunication Union (http://www.itu.ch) -+ - .. _jfif: - - JFIF -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index 6c961cfb74da..ea0a8a68759b 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -52,6 +52,25 @@ Compressed Formats - - ``V4L2_PIX_FMT_H264_MVC`` - - 'M264' - - H264 MVC video elementary stream. -+ * .. _V4L2-PIX-FMT-H264-SLICE: -+ -+ - ``V4L2_PIX_FMT_H264_SLICE_RAW`` -+ - 'S264' -+ - H264 parsed slice data, as extracted from the H264 bitstream. -+ This format is adapted for stateless video decoders that -+ implement an H264 pipeline (using the :ref:`codec` and -+ :ref:`media-request-api`). Metadata associated with the frame -+ to decode are required to be passed through the -+ ``V4L2_CID_MPEG_VIDEO_H264_SPS``, -+ ``V4L2_CID_MPEG_VIDEO_H264_PPS``, -+ ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``, -+ ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and -+ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS`` controls. See the -+ :ref:`associated Codec Control IDs `. -+ Exactly one output and one capture buffer must be provided for -+ use with this pixel format. The output buffer must contain the -+ appropriate number of macroblocks to decode a full -+ corresponding frame to the matching capture buffer. - * .. _V4L2-PIX-FMT-H263: - - - ``V4L2_PIX_FMT_H263`` -diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -index f824162d0ea9..dc500632095d 100644 ---- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -+++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -@@ -443,6 +443,36 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_mpeg2_quantization`, containing MPEG-2 - quantization matrices for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_sps`, containing H264 -+ sequence parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_PPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_pps`, containing H264 -+ picture parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SCALING_MATRIX`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_scaling_matrix`, containing H264 -+ scaling matrices for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SLICE_PARAMS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_slice_params`, containing H264 -+ slice parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_DECODE_PARAMS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 -+ decode parameters for stateless video decoders. - - .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| - -diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions -index 64d348e67df9..55cbe324b9fc 100644 ---- a/Documentation/media/videodev2.h.rst.exceptions -+++ b/Documentation/media/videodev2.h.rst.exceptions -@@ -136,6 +136,11 @@ replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_MPEG2_QUANTIZATION :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` - - # V4L2 capability defines - replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index b1ae2e555c68..46aec8c3acde 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -828,6 +828,11 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: - return "H264 Constrained Intra Pred"; - case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: return "H264 Chroma QP Index Offset"; -+ case V4L2_CID_MPEG_VIDEO_H264_SPS: return "H264 Sequence Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_H264_PPS: return "H264 Picture Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix"; -+ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; -@@ -1309,6 +1314,21 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: - *type = V4L2_CTRL_TYPE_FWHT_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_H264_SPS: -+ *type = V4L2_CTRL_TYPE_H264_SPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_PPS: -+ *type = V4L2_CTRL_TYPE_H264_PPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: -+ *type = V4L2_CTRL_TYPE_H264_SCALING_MATRIX; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: -+ *type = V4L2_CTRL_TYPE_H264_SLICE_PARAMS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: -+ *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; -+ break; - default: - *type = V4L2_CTRL_TYPE_INTEGER; - break; -@@ -1678,6 +1698,13 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_FWHT_PARAMS: - return 0; - -+ case V4L2_CTRL_TYPE_H264_SPS: -+ case V4L2_CTRL_TYPE_H264_PPS: -+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -+ return 0; -+ - default: - return -EINVAL; - } -@@ -2261,6 +2288,21 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_FWHT_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_fwht_params); - break; -+ case V4L2_CTRL_TYPE_H264_SPS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_sps); -+ break; -+ case V4L2_CTRL_TYPE_H264_PPS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_pps); -+ break; -+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -+ elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix); -+ break; -+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_slice_params); -+ break; -+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); -+ break; - default: - if (type < V4L2_CTRL_COMPOUND_TYPES) - elem_size = sizeof(s32); -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index ac87c3e37280..f6e1254064d2 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1325,6 +1325,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_H264: descr = "H.264"; break; - case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; - case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; -+ case V4L2_PIX_FMT_H264_SLICE_RAW: descr = "H.264 Parsed Slice Data"; break; - case V4L2_PIX_FMT_H263: descr = "H.263"; break; - case V4L2_PIX_FMT_MPEG1: descr = "MPEG-1 ES"; break; - case V4L2_PIX_FMT_MPEG2: descr = "MPEG-2 ES"; break; -diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h -new file mode 100644 -index 000000000000..e2f83b3cdbef ---- /dev/null -+++ b/include/media/h264-ctrls.h -@@ -0,0 +1,192 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the H.264 state controls for use with stateless H.264 -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _H264_CTRLS_H_ -+#define _H264_CTRLS_H_ -+ -+/* -+ * This is put insanely high to avoid conflicting with controls that -+ * would be added during the phase where those controls are not -+ * stable. It should be fixed eventually. -+ */ -+#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) -+#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) -+#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) -+#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) -+#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) -+ -+/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_H264_SPS 0x0110 -+#define V4L2_CTRL_TYPE_H264_PPS 0x0111 -+#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 -+#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 -+#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 -+ -+#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 -+#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 -+#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 -+#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 -+#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 -+#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 -+ -+#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 -+#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 -+#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 -+#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 -+#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 -+#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 -+#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 -+ -+struct v4l2_ctrl_h264_sps { -+ __u8 profile_idc; -+ __u8 constraint_set_flags; -+ __u8 level_idc; -+ __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; -+ __u8 bit_depth_luma_minus8; -+ __u8 bit_depth_chroma_minus8; -+ __u8 log2_max_frame_num_minus4; -+ __u8 pic_order_cnt_type; -+ __u8 log2_max_pic_order_cnt_lsb_minus4; -+ __u8 max_num_ref_frames; -+ __u8 num_ref_frames_in_pic_order_cnt_cycle; -+ __s32 offset_for_ref_frame[255]; -+ __s32 offset_for_non_ref_pic; -+ __s32 offset_for_top_to_bottom_field; -+ __u16 pic_width_in_mbs_minus1; -+ __u16 pic_height_in_map_units_minus1; -+ __u32 flags; -+}; -+ -+#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 -+#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 -+#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 -+#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 -+#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 -+#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 -+#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 -+#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 -+ -+struct v4l2_ctrl_h264_pps { -+ __u8 pic_parameter_set_id; -+ __u8 seq_parameter_set_id; -+ __u8 num_slice_groups_minus1; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; -+ __u8 weighted_bipred_idc; -+ __s8 pic_init_qp_minus26; -+ __s8 pic_init_qs_minus26; -+ __s8 chroma_qp_index_offset; -+ __s8 second_chroma_qp_index_offset; -+ __u16 flags; -+}; -+ -+struct v4l2_ctrl_h264_scaling_matrix { -+ __u8 scaling_list_4x4[6][16]; -+ __u8 scaling_list_8x8[6][64]; -+}; -+ -+struct v4l2_h264_weight_factors { -+ __s16 luma_weight[32]; -+ __s16 luma_offset[32]; -+ __s16 chroma_weight[32][2]; -+ __s16 chroma_offset[32][2]; -+}; -+ -+struct v4l2_h264_pred_weight_table { -+ __u16 luma_log2_weight_denom; -+ __u16 chroma_log2_weight_denom; -+ struct v4l2_h264_weight_factors weight_factors[2]; -+}; -+ -+#define V4L2_H264_SLICE_TYPE_P 0 -+#define V4L2_H264_SLICE_TYPE_B 1 -+#define V4L2_H264_SLICE_TYPE_I 2 -+#define V4L2_H264_SLICE_TYPE_SP 3 -+#define V4L2_H264_SLICE_TYPE_SI 4 -+ -+#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 -+#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 -+#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 -+#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 -+ -+struct v4l2_ctrl_h264_slice_params { -+ /* Size in bytes, including header */ -+ __u32 size; -+ /* Offset in bits to slice_data() from the beginning of this slice. */ -+ __u32 header_bit_size; -+ -+ __u16 first_mb_in_slice; -+ __u8 slice_type; -+ __u8 pic_parameter_set_id; -+ __u8 colour_plane_id; -+ __u8 redundant_pic_cnt; -+ __u16 frame_num; -+ __u16 idr_pic_id; -+ __u16 pic_order_cnt_lsb; -+ __s32 delta_pic_order_cnt_bottom; -+ __s32 delta_pic_order_cnt0; -+ __s32 delta_pic_order_cnt1; -+ -+ struct v4l2_h264_pred_weight_table pred_weight_table; -+ /* Size in bits of dec_ref_pic_marking() syntax element. */ -+ __u32 dec_ref_pic_marking_bit_size; -+ /* Size in bits of pic order count syntax. */ -+ __u32 pic_order_cnt_bit_size; -+ -+ __u8 cabac_init_idc; -+ __s8 slice_qp_delta; -+ __s8 slice_qs_delta; -+ __u8 disable_deblocking_filter_idc; -+ __s8 slice_alpha_c0_offset_div2; -+ __s8 slice_beta_offset_div2; -+ __u8 num_ref_idx_l0_active_minus1; -+ __u8 num_ref_idx_l1_active_minus1; -+ __u32 slice_group_change_cycle; -+ -+ /* -+ * Entries on each list are indices into -+ * v4l2_ctrl_h264_decode_params.dpb[]. -+ */ -+ __u8 ref_pic_list0[32]; -+ __u8 ref_pic_list1[32]; -+ -+ __u32 flags; -+}; -+ -+#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 -+#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 -+#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 -+ -+struct v4l2_h264_dpb_entry { -+ __u64 reference_ts; -+ __u16 frame_num; -+ __u16 pic_num; -+ /* Note that field is indicated by v4l2_buffer.field */ -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ -+}; -+ -+#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 -+ -+struct v4l2_ctrl_h264_decode_params { -+ struct v4l2_h264_dpb_entry dpb[16]; -+ __u16 num_slices; -+ __u16 nal_ref_idc; -+ __u8 ref_pic_list_p0[32]; -+ __u8 ref_pic_list_b0[32]; -+ __u8 ref_pic_list_b1[32]; -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ -+}; -+ -+#endif -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index bd621cec65a5..dce6f33fd749 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -23,11 +23,12 @@ - #include - - /* -- * Include the mpeg2 and fwht stateless codec compound control definitions. -+ * Include the stateless codec compound control definitions. - * This will move to the public headers once this API is fully stable. - */ - #include - #include -+#include - - /* forward references */ - struct file; -@@ -51,6 +52,11 @@ struct poll_table_struct; - * @p_mpeg2_slice_params: Pointer to a MPEG2 slice parameters structure. - * @p_mpeg2_quantization: Pointer to a MPEG2 quantization data structure. - * @p_fwht_params: Pointer to a FWHT stateless parameters structure. -+ * @p_h264_sps: Pointer to a struct v4l2_ctrl_h264_sps. -+ * @p_h264_pps: Pointer to a struct v4l2_ctrl_h264_pps. -+ * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. -+ * @p_h264_slice_param: Pointer to a struct v4l2_ctrl_h264_slice_params. -+ * @p_h264_decode_param: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p: Pointer to a compound value. - */ - union v4l2_ctrl_ptr { -@@ -63,6 +69,11 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; - struct v4l2_ctrl_mpeg2_quantization *p_mpeg2_quantization; - struct v4l2_ctrl_fwht_params *p_fwht_params; -+ struct v4l2_ctrl_h264_sps *p_h264_sps; -+ struct v4l2_ctrl_h264_pps *p_h264_pps; -+ struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; -+ struct v4l2_ctrl_h264_slice_params *p_h264_slice_param; -+ struct v4l2_ctrl_h264_decode_params *p_h264_decode_param; - void *p; - }; - -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 496e6453450c..838732acdefc 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -657,6 +657,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ - #define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ - #define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ -+#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ - #define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ - #define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ - #define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ -From patchwork Thu Apr 4 12:59:03 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,2/2] media: cedrus: Add H264 decoding support -From: Maxime Ripard -X-Patchwork-Id: 55457 -Message-Id: <157519b5571e24c9ef4189d30f8434b5b61121b1.1554382670.git-series.maxime.ripard@bootlin.com> -X-Patchwork-Delegate: hverkuil@xs4all.nl -To: hans.verkuil@cisco.com, acourbot@chromium.org, - sakari.ailus@linux.intel.com, - Laurent Pinchart -Cc: tfiga@chromium.org, posciak@chromium.org, - Paul Kocialkowski , - Chen-Yu Tsai , linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, - nicolas.dufresne@collabora.com, jenskuske@gmail.com, - jernej.skrabec@gmail.com, jonas@kwiboo.se, ezequiel@collabora.com, - linux-sunxi@googlegroups.com, - Thomas Petazzoni , - Maxime Ripard , - Jernej Skrabec -Date: Thu, 4 Apr 2019 14:59:03 +0200 - -Introduce some basic H264 decoding support in cedrus. So far, only the -baseline profile videos have been tested, and some more advanced features -used in higher profiles are not even implemented. - -Reviewed-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - drivers/staging/media/sunxi/cedrus/Makefile | 3 +- - drivers/staging/media/sunxi/cedrus/cedrus.c | 31 +- - drivers/staging/media/sunxi/cedrus/cedrus.h | 38 +- - drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 13 +- - drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 574 +++++++++++++++- - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 4 +- - drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 91 ++- - drivers/staging/media/sunxi/cedrus/cedrus_video.c | 9 +- - 8 files changed, 761 insertions(+), 2 deletions(-) - create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h264.c - -diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile -index 808842f0119e..c85ac6db0302 100644 ---- a/drivers/staging/media/sunxi/cedrus/Makefile -+++ b/drivers/staging/media/sunxi/cedrus/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o - --sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o -+sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ -+ cedrus_mpeg2.o cedrus_h264.o -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index b98add3cdedd..d613f5c24a2f 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -40,6 +40,36 @@ static const struct cedrus_control cedrus_controls[] = { - .codec = CEDRUS_CODEC_MPEG2, - .required = false, - }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_decode_params), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_slice_params), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_sps), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_pps), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, - }; - - #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) -@@ -278,6 +308,7 @@ static int cedrus_probe(struct platform_device *pdev) - } - - dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; -+ dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; - - mutex_init(&dev->dev_mutex); - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index c57c04b41d2e..bef79f630520 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -32,7 +32,7 @@ - - enum cedrus_codec { - CEDRUS_CODEC_MPEG2, -- -+ CEDRUS_CODEC_H264, - CEDRUS_CODEC_LAST, - }; - -@@ -42,6 +42,12 @@ enum cedrus_irq_status { - CEDRUS_IRQ_OK, - }; - -+enum cedrus_h264_pic_type { -+ CEDRUS_H264_PIC_TYPE_FRAME = 0, -+ CEDRUS_H264_PIC_TYPE_FIELD, -+ CEDRUS_H264_PIC_TYPE_MBAFF, -+}; -+ - struct cedrus_control { - u32 id; - u32 elem_size; -@@ -49,6 +55,14 @@ struct cedrus_control { - unsigned char required:1; - }; - -+struct cedrus_h264_run { -+ const struct v4l2_ctrl_h264_decode_params *decode_params; -+ const struct v4l2_ctrl_h264_pps *pps; -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; -+ const struct v4l2_ctrl_h264_slice_params *slice_params; -+ const struct v4l2_ctrl_h264_sps *sps; -+}; -+ - struct cedrus_mpeg2_run { - const struct v4l2_ctrl_mpeg2_slice_params *slice_params; - const struct v4l2_ctrl_mpeg2_quantization *quantization; -@@ -59,12 +73,20 @@ struct cedrus_run { - struct vb2_v4l2_buffer *dst; - - union { -+ struct cedrus_h264_run h264; - struct cedrus_mpeg2_run mpeg2; - }; - }; - - struct cedrus_buffer { - struct v4l2_m2m_buffer m2m_buf; -+ -+ union { -+ struct { -+ unsigned int position; -+ enum cedrus_h264_pic_type pic_type; -+ } h264; -+ } codec; - }; - - struct cedrus_ctx { -@@ -79,6 +101,19 @@ struct cedrus_ctx { - struct v4l2_ctrl **ctrls; - - struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; -+ -+ union { -+ struct { -+ void *mv_col_buf; -+ dma_addr_t mv_col_buf_dma; -+ ssize_t mv_col_buf_field_size; -+ ssize_t mv_col_buf_size; -+ void *pic_info_buf; -+ dma_addr_t pic_info_buf_dma; -+ void *neighbor_info_buf; -+ dma_addr_t neighbor_info_buf_dma; -+ } h264; -+ } codec; - }; - - struct cedrus_dec_ops { -@@ -121,6 +156,7 @@ struct cedrus_dev { - }; - - extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; -+extern struct cedrus_dec_ops cedrus_dec_ops_h264; - - static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) - { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index 4d6d602cdde6..bdad87eb9d79 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -46,6 +46,19 @@ void cedrus_device_run(void *priv) - V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); - break; - -+ case V4L2_PIX_FMT_H264_SLICE_RAW: -+ run.h264.decode_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); -+ run.h264.pps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_PPS); -+ run.h264.scaling_matrix = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX); -+ run.h264.slice_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); -+ run.h264.sps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SPS); -+ break; -+ - default: - break; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -new file mode 100644 -index 000000000000..2c98a3e46d2b ---- /dev/null -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -0,0 +1,574 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Cedrus VPU driver -+ * -+ * Copyright (c) 2013 Jens Kuske -+ * Copyright (c) 2018 Bootlin -+ */ -+ -+#include -+ -+#include -+ -+#include "cedrus.h" -+#include "cedrus_hw.h" -+#include "cedrus_regs.h" -+ -+enum cedrus_h264_sram_off { -+ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE = 0x000, -+ CEDRUS_SRAM_H264_FRAMEBUFFER_LIST = 0x100, -+ CEDRUS_SRAM_H264_REF_LIST_0 = 0x190, -+ CEDRUS_SRAM_H264_REF_LIST_1 = 0x199, -+ CEDRUS_SRAM_H264_SCALING_LIST_8x8_0 = 0x200, -+ CEDRUS_SRAM_H264_SCALING_LIST_8x8_1 = 0x210, -+ CEDRUS_SRAM_H264_SCALING_LIST_4x4 = 0x220, -+}; -+ -+struct cedrus_h264_sram_ref_pic { -+ __le32 top_field_order_cnt; -+ __le32 bottom_field_order_cnt; -+ __le32 frame_info; -+ __le32 luma_ptr; -+ __le32 chroma_ptr; -+ __le32 mv_col_top_ptr; -+ __le32 mv_col_bot_ptr; -+ __le32 reserved; -+} __packed; -+ -+#define CEDRUS_H264_FRAME_NUM 18 -+ -+#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) -+#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) -+ -+static void cedrus_h264_write_sram(struct cedrus_dev *dev, -+ enum cedrus_h264_sram_off off, -+ const void *data, size_t len) -+{ -+ const u32 *buffer = data; -+ size_t count = DIV_ROUND_UP(len, 4); -+ -+ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, off << 2); -+ -+ while (count--) -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++); -+} -+ -+static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, -+ unsigned int position, -+ unsigned int field) -+{ -+ dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; -+ -+ /* Adjust for the position */ -+ addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; -+ -+ /* Adjust for the field */ -+ addr += field * ctx->codec.h264.mv_col_buf_field_size; -+ -+ return addr; -+} -+ -+static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, -+ struct cedrus_buffer *buf, -+ unsigned int top_field_order_cnt, -+ unsigned int bottom_field_order_cnt, -+ struct cedrus_h264_sram_ref_pic *pic) -+{ -+ struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; -+ unsigned int position = buf->codec.h264.position; -+ -+ pic->top_field_order_cnt = top_field_order_cnt; -+ pic->bottom_field_order_cnt = bottom_field_order_cnt; -+ pic->frame_info = buf->codec.h264.pic_type << 8; -+ -+ pic->luma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0); -+ pic->chroma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1); -+ pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 0); -+ pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 1); -+} -+ -+static void cedrus_write_frame_list(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM]; -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ struct cedrus_buffer *output_buf; -+ struct cedrus_dev *dev = ctx->dev; -+ unsigned long used_dpbs = 0; -+ unsigned int position; -+ unsigned int output = 0; -+ unsigned int i; -+ -+ memset(pic_list, 0, sizeof(pic_list)); -+ -+ for (i = 0; i < ARRAY_SIZE(decode->dpb); i++) { -+ const struct v4l2_h264_dpb_entry *dpb = &decode->dpb[i]; -+ struct cedrus_buffer *cedrus_buf; -+ int buf_idx; -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) -+ continue; -+ -+ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); -+ if (buf_idx < 0) -+ continue; -+ -+ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[buf_idx]); -+ position = cedrus_buf->codec.h264.position; -+ used_dpbs |= BIT(position); -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ cedrus_fill_ref_pic(ctx, cedrus_buf, -+ dpb->top_field_order_cnt, -+ dpb->bottom_field_order_cnt, -+ &pic_list[position]); -+ -+ output = max(position, output); -+ } -+ -+ position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, -+ output); -+ if (position >= CEDRUS_H264_FRAME_NUM) -+ position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); -+ -+ output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); -+ output_buf->codec.h264.position = position; -+ -+ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; -+ else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_MBAFF; -+ else -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FRAME; -+ -+ cedrus_fill_ref_pic(ctx, output_buf, -+ decode->top_field_order_cnt, -+ decode->bottom_field_order_cnt, -+ &pic_list[position]); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_FRAMEBUFFER_LIST, -+ pic_list, sizeof(pic_list)); -+ -+ cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position); -+} -+ -+#define CEDRUS_MAX_REF_IDX 32 -+ -+static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, -+ struct cedrus_run *run, -+ const u8 *ref_list, u8 num_ref, -+ enum cedrus_h264_sram_off sram) -+{ -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ struct cedrus_dev *dev = ctx->dev; -+ u8 sram_array[CEDRUS_MAX_REF_IDX]; -+ unsigned int i; -+ size_t size; -+ -+ memset(sram_array, 0, sizeof(sram_array)); -+ -+ for (i = 0; i < num_ref; i++) { -+ const struct v4l2_h264_dpb_entry *dpb; -+ const struct cedrus_buffer *cedrus_buf; -+ const struct vb2_v4l2_buffer *ref_buf; -+ unsigned int position; -+ int buf_idx; -+ u8 dpb_idx; -+ -+ dpb_idx = ref_list[i]; -+ dpb = &decode->dpb[dpb_idx]; -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); -+ if (buf_idx < 0) -+ continue; -+ -+ ref_buf = to_vb2_v4l2_buffer(ctx->dst_bufs[buf_idx]); -+ cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); -+ position = cedrus_buf->codec.h264.position; -+ -+ sram_array[i] |= position << 1; -+ if (ref_buf->field == V4L2_FIELD_BOTTOM) -+ sram_array[i] |= BIT(0); -+ } -+ -+ size = min_t(size_t, ALIGN(num_ref, 4), sizeof(sram_array)); -+ cedrus_h264_write_sram(dev, sram, &sram_array, size); -+} -+ -+static void cedrus_write_ref_list0(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ -+ _cedrus_write_ref_list(ctx, run, -+ slice->ref_pic_list0, -+ slice->num_ref_idx_l0_active_minus1 + 1, -+ CEDRUS_SRAM_H264_REF_LIST_0); -+} -+ -+static void cedrus_write_ref_list1(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ -+ _cedrus_write_ref_list(ctx, run, -+ slice->ref_pic_list1, -+ slice->num_ref_idx_l1_active_minus1 + 1, -+ CEDRUS_SRAM_H264_REF_LIST_1); -+} -+ -+static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling = -+ run->h264.scaling_matrix; -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_0, -+ scaling->scaling_list_8x8[0], -+ sizeof(scaling->scaling_list_8x8[0])); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, -+ scaling->scaling_list_8x8[3], -+ sizeof(scaling->scaling_list_8x8[3])); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, -+ scaling->scaling_list_4x4, -+ sizeof(scaling->scaling_list_4x4)); -+} -+ -+static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = -+ run->h264.slice_params; -+ const struct v4l2_h264_pred_weight_table *pred_weight = -+ &slice->pred_weight_table; -+ struct cedrus_dev *dev = ctx->dev; -+ int i, j, k; -+ -+ cedrus_write(dev, VE_H264_SHS_WP, -+ ((pred_weight->chroma_log2_weight_denom & 0x7) << 4) | -+ ((pred_weight->luma_log2_weight_denom & 0x7) << 0)); -+ -+ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, -+ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE << 2); -+ -+ for (i = 0; i < ARRAY_SIZE(pred_weight->weight_factors); i++) { -+ const struct v4l2_h264_weight_factors *factors = -+ &pred_weight->weight_factors[i]; -+ -+ for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { -+ u32 val; -+ -+ val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | -+ (factors->luma_weight[j] & 0x1ff); -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); -+ } -+ -+ for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { -+ for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { -+ u32 val; -+ -+ val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | -+ (factors->chroma_weight[j][k] & 0x1ff); -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); -+ } -+ } -+ } -+} -+ -+static void cedrus_set_params(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; -+ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; -+ struct vb2_buffer *src_buf = &run->src->vb2_buf; -+ struct cedrus_dev *dev = ctx->dev; -+ dma_addr_t src_buf_addr; -+ u32 offset = slice->header_bit_size; -+ u32 len = (slice->size * 8) - offset; -+ u32 reg; -+ -+ cedrus_write(dev, VE_H264_VLD_LEN, len); -+ cedrus_write(dev, VE_H264_VLD_OFFSET, offset); -+ -+ src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); -+ cedrus_write(dev, VE_H264_VLD_END, -+ src_buf_addr + vb2_get_plane_payload(src_buf, 0)); -+ cedrus_write(dev, VE_H264_VLD_ADDR, -+ VE_H264_VLD_ADDR_VAL(src_buf_addr) | -+ VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | -+ VE_H264_VLD_ADDR_LAST); -+ -+ /* -+ * FIXME: Since the bitstream parsing is done in software, and -+ * in userspace, this shouldn't be needed anymore. But it -+ * turns out that removing it breaks the decoding process, -+ * without any clear indication why. -+ */ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_INIT_SWDEC); -+ -+ if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_P || -+ slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || -+ (pps->weighted_bipred_idc == 1 && -+ slice->slice_type == V4L2_H264_SLICE_TYPE_B)) -+ cedrus_write_pred_weight_table(ctx, run); -+ -+ if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_SP) || -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) -+ cedrus_write_ref_list0(ctx, run); -+ -+ if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) -+ cedrus_write_ref_list1(ctx, run); -+ -+ // picture parameters -+ reg = 0; -+ /* -+ * FIXME: the kernel headers are allowing the default value to -+ * be passed, but the libva doesn't give us that. -+ */ -+ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; -+ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; -+ reg |= (pps->weighted_bipred_idc & 0x3) << 2; -+ if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) -+ reg |= VE_H264_PPS_ENTROPY_CODING_MODE; -+ if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) -+ reg |= VE_H264_PPS_WEIGHTED_PRED; -+ if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) -+ reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; -+ if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) -+ reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; -+ cedrus_write(dev, VE_H264_PPS, reg); -+ -+ // sequence parameters -+ reg = 0; -+ reg |= (sps->chroma_format_idc & 0x7) << 19; -+ reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; -+ reg |= sps->pic_height_in_map_units_minus1 & 0xff; -+ if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) -+ reg |= VE_H264_SPS_MBS_ONLY; -+ if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -+ reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; -+ if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) -+ reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; -+ cedrus_write(dev, VE_H264_SPS, reg); -+ -+ // slice parameters -+ reg = 0; -+ reg |= decode->nal_ref_idc ? BIT(12) : 0; -+ reg |= (slice->slice_type & 0xf) << 8; -+ reg |= slice->cabac_init_idc & 0x3; -+ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) -+ reg |= VE_H264_SHS_FIELD_PIC; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) -+ reg |= VE_H264_SHS_BOTTOM_FIELD; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED) -+ reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; -+ cedrus_write(dev, VE_H264_SHS, reg); -+ -+ reg = 0; -+ reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; -+ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; -+ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; -+ reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; -+ reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; -+ reg |= slice->slice_beta_offset_div2 & 0xf; -+ cedrus_write(dev, VE_H264_SHS2, reg); -+ -+ reg = 0; -+ reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; -+ reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; -+ reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; -+ cedrus_write(dev, VE_H264_SHS_QP, reg); -+ -+ // clear status flags -+ cedrus_write(dev, VE_H264_STATUS, cedrus_read(dev, VE_H264_STATUS)); -+ -+ // enable int -+ cedrus_write(dev, VE_H264_CTRL, -+ VE_H264_CTRL_SLICE_DECODE_INT | -+ VE_H264_CTRL_DECODE_ERR_INT | -+ VE_H264_CTRL_VLD_DATA_REQ_INT); -+} -+ -+static enum cedrus_irq_status -+cedrus_h264_irq_status(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_STATUS); -+ -+ if (reg & (VE_H264_STATUS_DECODE_ERR_INT | -+ VE_H264_STATUS_VLD_DATA_REQ_INT)) -+ return CEDRUS_IRQ_ERROR; -+ -+ if (reg & VE_H264_CTRL_SLICE_DECODE_INT) -+ return CEDRUS_IRQ_OK; -+ -+ return CEDRUS_IRQ_NONE; -+} -+ -+static void cedrus_h264_irq_clear(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_STATUS, -+ VE_H264_STATUS_INT_MASK); -+} -+ -+static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_CTRL); -+ -+ cedrus_write(dev, VE_H264_CTRL, -+ reg & ~VE_H264_CTRL_INT_MASK); -+} -+ -+static void cedrus_h264_setup(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_engine_enable(dev, CEDRUS_CODEC_H264); -+ -+ cedrus_write(dev, VE_H264_SDROT_CTRL, 0); -+ cedrus_write(dev, VE_H264_EXTRA_BUFFER1, -+ ctx->codec.h264.pic_info_buf_dma); -+ cedrus_write(dev, VE_H264_EXTRA_BUFFER2, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ -+ cedrus_write_scaling_lists(ctx, run); -+ cedrus_write_frame_list(ctx, run); -+ -+ cedrus_set_params(ctx, run); -+} -+ -+static int cedrus_h264_start(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ unsigned int field_size; -+ unsigned int mv_col_size; -+ int ret; -+ -+ /* -+ * FIXME: It seems that the H6 cedarX code is using a formula -+ * here based on the size of the frame, while all the older -+ * code is using a fixed size, so that might need to be -+ * changed at some point. -+ */ -+ ctx->codec.h264.pic_info_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ &ctx->codec.h264.pic_info_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.pic_info_buf) -+ return -ENOMEM; -+ -+ /* -+ * That buffer is supposed to be 16kiB in size, and be aligned -+ * on 16kiB as well. However, dma_alloc_coherent provides the -+ * guarantee that we'll have a CPU and DMA address aligned on -+ * the smallest page order that is greater to the requested -+ * size, so we don't have to overallocate. -+ */ -+ ctx->codec.h264.neighbor_info_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ &ctx->codec.h264.neighbor_info_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.neighbor_info_buf) { -+ ret = -ENOMEM; -+ goto err_pic_buf; -+ } -+ -+ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * -+ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; -+ -+ /* -+ * FIXME: This is actually conditional to -+ * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we -+ * might have to rework this if memory efficiency ever is -+ * something we need to work on. -+ */ -+ field_size = field_size * 2; -+ -+ /* -+ * FIXME: This is actually conditional to -+ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might -+ * have to rework this if memory efficiency ever is something -+ * we need to work on. -+ */ -+ field_size = field_size * 2; -+ ctx->codec.h264.mv_col_buf_field_size = field_size; -+ -+ mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; -+ ctx->codec.h264.mv_col_buf_size = mv_col_size; -+ ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, -+ ctx->codec.h264.mv_col_buf_size, -+ &ctx->codec.h264.mv_col_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.mv_col_buf) { -+ ret = -ENOMEM; -+ goto err_neighbor_buf; -+ } -+ -+ return 0; -+ -+err_neighbor_buf: -+ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h264.neighbor_info_buf, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ -+err_pic_buf: -+ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ ctx->codec.h264.pic_info_buf, -+ ctx->codec.h264.pic_info_buf_dma); -+ return ret; -+} -+ -+static void cedrus_h264_stop(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, -+ ctx->codec.h264.mv_col_buf, -+ ctx->codec.h264.mv_col_buf_dma); -+ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h264.neighbor_info_buf, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ ctx->codec.h264.pic_info_buf, -+ ctx->codec.h264.pic_info_buf_dma); -+} -+ -+static void cedrus_h264_trigger(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); -+} -+ -+struct cedrus_dec_ops cedrus_dec_ops_h264 = { -+ .irq_clear = cedrus_h264_irq_clear, -+ .irq_disable = cedrus_h264_irq_disable, -+ .irq_status = cedrus_h264_irq_status, -+ .setup = cedrus_h264_setup, -+ .start = cedrus_h264_start, -+ .stop = cedrus_h264_stop, -+ .trigger = cedrus_h264_trigger, -+}; -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index fbfff7c1c771..748f7f673547 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -46,6 +46,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) - reg |= VE_MODE_DEC_MPEG; - break; - -+ case CEDRUS_CODEC_H264: -+ reg |= VE_MODE_DEC_H264; -+ break; -+ - default: - return -EINVAL; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index de2d6b6f64bf..3e9931416e45 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -232,4 +232,95 @@ - #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) - #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) - -+#define VE_H264_SPS 0x200 -+#define VE_H264_SPS_MBS_ONLY BIT(18) -+#define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) -+#define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) -+ -+#define VE_H264_PPS 0x204 -+#define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) -+#define VE_H264_PPS_WEIGHTED_PRED BIT(4) -+#define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) -+#define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) -+ -+#define VE_H264_SHS 0x208 -+#define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) -+#define VE_H264_SHS_FIELD_PIC BIT(4) -+#define VE_H264_SHS_BOTTOM_FIELD BIT(3) -+#define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) -+ -+#define VE_H264_SHS2 0x20c -+#define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) -+ -+#define VE_H264_SHS_WP 0x210 -+ -+#define VE_H264_SHS_QP 0x21c -+#define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) -+ -+#define VE_H264_CTRL 0x220 -+#define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) -+#define VE_H264_CTRL_DECODE_ERR_INT BIT(1) -+#define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) -+ -+#define VE_H264_CTRL_INT_MASK (VE_H264_CTRL_VLD_DATA_REQ_INT | \ -+ VE_H264_CTRL_DECODE_ERR_INT | \ -+ VE_H264_CTRL_SLICE_DECODE_INT) -+ -+#define VE_H264_TRIGGER_TYPE 0x224 -+#define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) -+#define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) -+ -+#define VE_H264_STATUS 0x228 -+#define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT -+#define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT -+#define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT -+ -+#define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK -+ -+#define VE_H264_CUR_MB_NUM 0x22c -+ -+#define VE_H264_VLD_ADDR 0x230 -+#define VE_H264_VLD_ADDR_FIRST BIT(30) -+#define VE_H264_VLD_ADDR_LAST BIT(29) -+#define VE_H264_VLD_ADDR_VALID BIT(28) -+#define VE_H264_VLD_ADDR_VAL(x) (((x) & 0x0ffffff0) | ((x) >> 28)) -+ -+#define VE_H264_VLD_OFFSET 0x234 -+#define VE_H264_VLD_LEN 0x238 -+#define VE_H264_VLD_END 0x23c -+#define VE_H264_SDROT_CTRL 0x240 -+#define VE_H264_OUTPUT_FRAME_IDX 0x24c -+#define VE_H264_EXTRA_BUFFER1 0x250 -+#define VE_H264_EXTRA_BUFFER2 0x254 -+#define VE_H264_BASIC_BITS 0x2dc -+#define VE_AVC_SRAM_PORT_OFFSET 0x2e0 -+#define VE_AVC_SRAM_PORT_DATA 0x2e4 -+ -+#define VE_ISP_INPUT_SIZE 0xa00 -+#define VE_ISP_INPUT_STRIDE 0xa04 -+#define VE_ISP_CTRL 0xa08 -+#define VE_ISP_INPUT_LUMA 0xa78 -+#define VE_ISP_INPUT_CHROMA 0xa7c -+ -+#define VE_AVC_PARAM 0xb04 -+#define VE_AVC_QP 0xb08 -+#define VE_AVC_MOTION_EST 0xb10 -+#define VE_AVC_CTRL 0xb14 -+#define VE_AVC_TRIGGER 0xb18 -+#define VE_AVC_STATUS 0xb1c -+#define VE_AVC_BASIC_BITS 0xb20 -+#define VE_AVC_UNK_BUF 0xb60 -+#define VE_AVC_VLE_ADDR 0xb80 -+#define VE_AVC_VLE_END 0xb84 -+#define VE_AVC_VLE_OFFSET 0xb88 -+#define VE_AVC_VLE_MAX 0xb8c -+#define VE_AVC_VLE_LENGTH 0xb90 -+#define VE_AVC_REF_LUMA 0xba0 -+#define VE_AVC_REF_CHROMA 0xba4 -+#define VE_AVC_REC_LUMA 0xbb0 -+#define VE_AVC_REC_CHROMA 0xbb4 -+#define VE_AVC_REF_SLUMA 0xbb8 -+#define VE_AVC_REC_SLUMA 0xbbc -+#define VE_AVC_MB_INFO 0xbc0 -+ - #endif -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index 9673874ece10..e2b530b1a956 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -38,6 +38,10 @@ static struct cedrus_format cedrus_formats[] = { - .directions = CEDRUS_DECODE_SRC, - }, - { -+ .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, -+ .directions = CEDRUS_DECODE_SRC, -+ }, -+ { - .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, - .directions = CEDRUS_DECODE_DST, - }, -@@ -100,6 +104,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - - switch (pix_fmt->pixelformat) { - case V4L2_PIX_FMT_MPEG2_SLICE: -+ case V4L2_PIX_FMT_H264_SLICE_RAW: - /* Zero bytes per line for encoded source. */ - bytesperline = 0; - -@@ -464,6 +469,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) - ctx->current_codec = CEDRUS_CODEC_MPEG2; - break; - -+ case V4L2_PIX_FMT_H264_SLICE_RAW: -+ ctx->current_codec = CEDRUS_CODEC_H264; -+ break; -+ - default: - return -EINVAL; - } diff --git a/projects/Allwinner/patches/linux/0013-cec-improvements.patch b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch similarity index 65% rename from projects/Allwinner/patches/linux/0013-cec-improvements.patch rename to projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch index f9360ec979..fc1b07d068 100644 --- a/projects/Allwinner/patches/linux/0013-cec-improvements.patch +++ b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch @@ -1,8 +1,85 @@ +From bf21ad0889bdcc1dc12fe5a024fd7df7ad2c4310 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 26 Feb 2019 20:45:14 +0000 +Subject: [PATCH 1/2] WIP: dw-hdmi-cec: sleep 100ms on error + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +index 6c323510f128..b5a1a85c8700 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +@@ -7,6 +7,7 @@ + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ ++#include + #include + #include + #include +@@ -132,8 +133,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + + dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); + +- if (stat & CEC_STAT_ERROR_INIT) { +- cec->tx_status = CEC_TX_STATUS_ERROR; ++ /* Status with both done and error_initiator bits have been seen ++ * on Rockchip RK3328 devices, transmit attempt seems to have failed ++ * when this happens, report as low drive and block cec-framework ++ * 100ms before core retransmits the failed message, this seems to ++ * mitigate the issue with failed transmit attempts. ++ */ ++ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { ++ pr_info("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); ++ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { +@@ -144,6 +152,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + cec->tx_status = CEC_TX_STATUS_NACK; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; ++ } else if (stat & CEC_STAT_ERROR_INIT) { ++ cec->tx_status = CEC_TX_STATUS_ERROR; ++ cec->tx_done = true; ++ ret = IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { +@@ -176,6 +188,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) + + if (cec->tx_done) { + cec->tx_done = false; ++ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) ++ msleep(100); + cec_transmit_attempt_done(adap, cec->tx_status); + } + if (cec->rx_done) { +-- +2.21.0 + + +From 12f1abe2b5cee6575c6dd9cd29b17b589f044b80 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 12:03:39 +0200 +Subject: [PATCH 2/2] WIP: sun8i-hdmi CEC improvements + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- + drivers/gpu/drm/sun4i/Kconfig | 10 +++ + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 11 +++ + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 83 ++++++++++++++++++++++- + include/drm/bridge/dw_hdmi.h | 2 + + 5 files changed, 105 insertions(+), 3 deletions(-) + diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index a63e5f0dae56..fdda26f8b056 100644 +index 09fdc9f87651..f359c4c3f1d1 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2634,7 +2634,7 @@ __dw_hdmi_probe(struct platform_device *pdev, +@@ -2713,7 +2713,7 @@ __dw_hdmi_probe(struct platform_device *pdev, hdmi->audio = platform_device_register_full(&pdevinfo); } @@ -33,7 +110,7 @@ index 1dbbc3a1b763..7149c72e44c8 100644 tristate "Support for Allwinner Display Engine 2.0 Mixer" default MACH_SUN8I diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -index 720c5aa8adc1..82dd84094638 100644 +index 720c5aa8adc1..49ca001923e3 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -12,6 +12,7 @@ @@ -71,15 +148,15 @@ index 720c5aa8adc1..82dd84094638 100644 struct sun8i_hdmi_phy { + struct cec_adapter *cec_adapter; -+ struct cec_notifier *cec_notifier; ++ struct cec_notifier *cec_notifier; struct clk *clk_bus; struct clk *clk_mod; struct clk *clk_phy; diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -index 66ea3a902e36..70e291353569 100644 +index 43643ad31730..d840bc07cba6 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -503,8 +503,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) +@@ -504,8 +504,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0); @@ -91,7 +168,7 @@ index 66ea3a902e36..70e291353569 100644 /* read calibration data */ regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); -@@ -530,8 +531,49 @@ void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, +@@ -531,8 +532,49 @@ void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, plat_data->cur_ctr = variant->cur_ctr; plat_data->phy_config = variant->phy_cfg; } @@ -141,7 +218,7 @@ index 66ea3a902e36..70e291353569 100644 static struct regmap_config sun8i_hdmi_phy_regmap_config = { .reg_bits = 32, .val_bits = 32, -@@ -548,6 +590,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = { +@@ -549,6 +591,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = { }; static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { @@ -149,7 +226,7 @@ index 66ea3a902e36..70e291353569 100644 .has_phy_clk = true, .is_custom_phy = true, .phy_init = &sun8i_hdmi_phy_init_h3, -@@ -556,6 +599,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { +@@ -557,6 +600,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { }; static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { @@ -157,7 +234,7 @@ index 66ea3a902e36..70e291353569 100644 .has_phy_clk = true, .has_second_pll = true, .is_custom_phy = true, -@@ -565,6 +609,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { +@@ -566,6 +610,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { }; static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { @@ -165,7 +242,7 @@ index 66ea3a902e36..70e291353569 100644 .has_phy_clk = true, .is_custom_phy = true, .phy_init = &sun8i_hdmi_phy_init_h3, -@@ -708,10 +753,40 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) +@@ -711,10 +756,40 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) clk_prepare_enable(phy->clk_phy); } @@ -204,9 +281,9 @@ index 66ea3a902e36..70e291353569 100644 +err_disable_clk_phy: + clk_disable_unprepare(phy->clk_phy); err_disable_clk_mod: - clk_disable_unprepare(phy->clk_mod); + clk_disable_unprepare(phy->clk_mod); err_disable_clk_bus: -@@ -736,6 +811,10 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) +@@ -739,6 +814,10 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) { struct sun8i_hdmi_phy *phy = hdmi->phy; @@ -218,7 +295,7 @@ index 66ea3a902e36..70e291353569 100644 clk_disable_unprepare(phy->clk_bus); clk_disable_unprepare(phy->clk_phy); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 66e70770cce5..764b8bcfa62c 100644 +index 323febe7f102..cec73761856d 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -144,6 +144,8 @@ struct dw_hdmi_plat_data { @@ -230,3 +307,6 @@ index 66e70770cce5..764b8bcfa62c 100644 }; struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0007-media-cedrus-Fix-decoding-for-some-H264-videos.patch b/projects/Allwinner/patches/linux/0007-media-cedrus-Fix-decoding-for-some-H264-videos.patch new file mode 100644 index 0000000000..f8ba373631 --- /dev/null +++ b/projects/Allwinner/patches/linux/0007-media-cedrus-Fix-decoding-for-some-H264-videos.patch @@ -0,0 +1,76 @@ +From 443ca53cf78c635aa5bebe9f115721e55fe9ca38 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 12:33:05 +0200 +Subject: [PATCH] media: cedrus: Fix decoding for some H264 videos + +It seems that for some H264 videos at least one bitstream parsing +trigger must be called in order to be decoded correctly. There is no +explanation why this helps, but it was observed that two sample videos +with this fix are now decoded correctly and there is no regression with +others. + +Signed-off-by: Jernej Skrabec +--- + .../staging/media/sunxi/cedrus/cedrus_h264.c | 22 ++++++++++++++++--- + 1 file changed, 19 insertions(+), 3 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +index a30bb283f69f..fab14de1815a 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -6,6 +6,7 @@ + * Copyright (c) 2018 Bootlin + */ + ++#include + #include + + #include +@@ -289,6 +290,20 @@ static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, + } + } + ++static void cedrus_skip_bits(struct cedrus_dev *dev, int num) ++{ ++ for (; num > 32; num -= 32) { ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, 0x3 | (32 << 8)); ++ while (cedrus_read(dev, VE_H264_STATUS) & (1 << 8)) ++ udelay(1); ++ } ++ if (num > 0) { ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, 0x3 | (num << 8)); ++ while (cedrus_read(dev, VE_H264_STATUS) & (1 << 8)) ++ udelay(1); ++ } ++} ++ + static void cedrus_set_params(struct cedrus_ctx *ctx, + struct cedrus_run *run) + { +@@ -299,12 +314,11 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + struct vb2_buffer *src_buf = &run->src->vb2_buf; + struct cedrus_dev *dev = ctx->dev; + dma_addr_t src_buf_addr; +- u32 offset = slice->header_bit_size; +- u32 len = (slice->size * 8) - offset; ++ u32 len = slice->size * 8; + u32 reg; + + cedrus_write(dev, VE_H264_VLD_LEN, len); +- cedrus_write(dev, VE_H264_VLD_OFFSET, offset); ++ cedrus_write(dev, VE_H264_VLD_OFFSET, 0); + + src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); + cedrus_write(dev, VE_H264_VLD_END, +@@ -323,6 +337,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + cedrus_write(dev, VE_H264_TRIGGER_TYPE, + VE_H264_TRIGGER_TYPE_INIT_SWDEC); + ++ cedrus_skip_bits(dev, slice->header_bit_size); ++ + if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && + (slice->slice_type == V4L2_H264_SLICE_TYPE_P || + slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0008-media-cedrus-Fix-H264-default-reference-index-count.patch b/projects/Allwinner/patches/linux/0008-media-cedrus-Fix-H264-default-reference-index-count.patch new file mode 100644 index 0000000000..6b08bad539 --- /dev/null +++ b/projects/Allwinner/patches/linux/0008-media-cedrus-Fix-H264-default-reference-index-count.patch @@ -0,0 +1,36 @@ +From fce7f7e700176b402b303d2a62813cc0cdd061e0 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 13:18:50 +0200 +Subject: [PATCH 2/5] media: cedrus: Fix H264 default reference index count + +Reference index count in VE_H264_PPS should come from PPS control. +However, this is not really important, because reference index count is +in our case always overridden by that from slice header. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +index fab14de1815a..d0ee3f90ff46 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -356,12 +356,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + + // picture parameters + reg = 0; +- /* +- * FIXME: the kernel headers are allowing the default value to +- * be passed, but the libva doesn't give us that. +- */ +- reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; +- reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; ++ reg |= (pps->num_ref_idx_l0_default_active_minus1 & 0x1f) << 10; ++ reg |= (pps->num_ref_idx_l1_default_active_minus1 & 0x1f) << 5; + reg |= (pps->weighted_bipred_idc & 0x3) << 2; + if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) + reg |= VE_H264_PPS_ENTROPY_CODING_MODE; +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0007-H264-improvements.patch b/projects/Allwinner/patches/linux/0009-media-cedrus-WIP-H264-improvements.patch similarity index 72% rename from projects/Allwinner/patches/linux/0007-H264-improvements.patch rename to projects/Allwinner/patches/linux/0009-media-cedrus-WIP-H264-improvements.patch index 0efa61a7fc..3abe59c038 100644 --- a/projects/Allwinner/patches/linux/0007-H264-improvements.patch +++ b/projects/Allwinner/patches/linux/0009-media-cedrus-WIP-H264-improvements.patch @@ -1,18 +1,18 @@ -From e41186f41a546d1c60797f090001da969f5eda5a Mon Sep 17 00:00:00 2001 +From 9714cf1bc8c5b48f21af3500e34497621b51a4b1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 14 Feb 2019 22:50:12 +0100 -Subject: [PATCH] cedrus: Improve H264 +Subject: [PATCH 3/5] media: cedrus: WIP H264 improvements Signed-off-by: Jernej Skrabec --- - .../staging/media/sunxi/cedrus/cedrus_h264.c | 69 +++++++++++-------- - 1 file changed, 41 insertions(+), 28 deletions(-) + .../staging/media/sunxi/cedrus/cedrus_h264.c | 37 ++++++++++++++----- + 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index a5c5f13ffecb..405545947b85 100644 +index d0ee3f90ff46..dcb8d3837869 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -38,7 +38,7 @@ struct cedrus_h264_sram_ref_pic { +@@ -39,7 +39,7 @@ struct cedrus_h264_sram_ref_pic { #define CEDRUS_H264_FRAME_NUM 18 #define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) @@ -21,7 +21,7 @@ index a5c5f13ffecb..405545947b85 100644 static void cedrus_h264_write_sram(struct cedrus_dev *dev, enum cedrus_h264_sram_off off, -@@ -101,7 +101,7 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -102,7 +102,7 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, struct cedrus_dev *dev = ctx->dev; unsigned long used_dpbs = 0; unsigned int position; @@ -30,7 +30,7 @@ index a5c5f13ffecb..405545947b85 100644 unsigned int i; memset(pic_list, 0, sizeof(pic_list)); -@@ -126,6 +126,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -123,6 +123,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, position = cedrus_buf->codec.h264.position; used_dpbs |= BIT(position); @@ -42,7 +42,7 @@ index a5c5f13ffecb..405545947b85 100644 if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) continue; -@@ -133,13 +138,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -130,13 +135,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, dpb->top_field_order_cnt, dpb->bottom_field_order_cnt, &pic_list[position]); @@ -59,7 +59,7 @@ index a5c5f13ffecb..405545947b85 100644 position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); -@@ -165,6 +168,10 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -162,6 +165,10 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, #define CEDRUS_MAX_REF_IDX 32 @@ -70,7 +70,7 @@ index a5c5f13ffecb..405545947b85 100644 static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, struct cedrus_run *run, const u8 *ref_list, u8 num_ref, -@@ -187,7 +194,7 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, +@@ -184,7 +191,7 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, int buf_idx; u8 dpb_idx; @@ -79,7 +79,7 @@ index a5c5f13ffecb..405545947b85 100644 dpb = &decode->dpb[dpb_idx]; if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -@@ -206,7 +213,8 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, +@@ -199,7 +206,8 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, position = cedrus_buf->codec.h264.position; sram_array[i] |= position << 1; @@ -89,16 +89,16 @@ index a5c5f13ffecb..405545947b85 100644 sram_array[i] |= BIT(0); } -@@ -309,6 +317,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, +@@ -315,6 +323,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + struct cedrus_dev *dev = ctx->dev; dma_addr_t src_buf_addr; - u32 offset = slice->header_bit_size; - u32 len = (slice->size * 8) - offset; + u32 len = slice->size * 8; + unsigned int pic_width_in_mbs; + bool mbaff_picture; u32 reg; cedrus_write(dev, VE_H264_VLD_LEN, len); -@@ -378,12 +387,19 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, +@@ -382,12 +392,19 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; cedrus_write(dev, VE_H264_SPS, reg); @@ -119,15 +119,6 @@ index a5c5f13ffecb..405545947b85 100644 if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) reg |= VE_H264_SHS_FIELD_PIC; if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) -@@ -531,7 +541,7 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) - * we need to work on. - */ - field_size = field_size * 2; -- ctx->codec.h264.mv_col_buf_field_size = field_size; -+ ctx->codec.h264.mv_col_buf_field_size = ALIGN(field_size, 1024); - - mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; - ctx->codec.h264.mv_col_buf_size = mv_col_size; -- -2.20.1 +2.21.0 diff --git a/projects/Allwinner/patches/linux/0008-HEVC-improvements.patch b/projects/Allwinner/patches/linux/0010-WIP-HEVC-improvements.patch similarity index 84% rename from projects/Allwinner/patches/linux/0008-HEVC-improvements.patch rename to projects/Allwinner/patches/linux/0010-WIP-HEVC-improvements.patch index 38c5f5f04c..96c0a6da59 100644 --- a/projects/Allwinner/patches/linux/0008-HEVC-improvements.patch +++ b/projects/Allwinner/patches/linux/0010-WIP-HEVC-improvements.patch @@ -1,8 +1,25 @@ +From c6582c38df2f78dc9d4f8fd920780a82a01e4d8e Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 25 May 2019 13:58:17 +0200 +Subject: [PATCH 2/3] WIP: HEVC improvements + +Signed-off-by: Jernej Skrabec +--- + drivers/media/v4l2-core/v4l2-ctrls.c | 8 + + drivers/staging/media/sunxi/cedrus/cedrus.c | 6 + + drivers/staging/media/sunxi/cedrus/cedrus.h | 11 +- + .../staging/media/sunxi/cedrus/cedrus_dec.c | 2 + + .../staging/media/sunxi/cedrus/cedrus_h265.c | 348 +++++++++++++----- + .../staging/media/sunxi/cedrus/cedrus_regs.h | 3 + + .../staging/media/sunxi/cedrus/cedrus_video.c | 12 +- + include/media/hevc-ctrls.h | 20 +- + 8 files changed, 301 insertions(+), 109 deletions(-) + diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 3bab9d4e3304..a14762dff91d 100644 +index 1107698b9d06..aed7a4526193 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -916,6 +916,7 @@ const char *v4l2_ctrl_get_name(u32 id) +@@ -947,6 +947,7 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; @@ -10,7 +27,7 @@ index 3bab9d4e3304..a14762dff91d 100644 /* CAMERA controls */ /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1332,6 +1333,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, +@@ -1368,6 +1369,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; break; @@ -20,7 +37,7 @@ index 3bab9d4e3304..a14762dff91d 100644 default: *type = V4L2_CTRL_TYPE_INTEGER; break; -@@ -1708,6 +1712,7 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, +@@ -1747,6 +1751,7 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, case V4L2_CTRL_TYPE_HEVC_SPS: case V4L2_CTRL_TYPE_HEVC_PPS: case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: @@ -28,7 +45,7 @@ index 3bab9d4e3304..a14762dff91d 100644 return 0; default: -@@ -2314,6 +2319,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, +@@ -2356,6 +2361,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); break; @@ -39,10 +56,10 @@ index 3bab9d4e3304..a14762dff91d 100644 if (type < V4L2_CTRL_COMPOUND_TYPES) elem_size = sizeof(s32); diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index a713630ce7ba..3040f483e0a2 100644 +index 70642834f351..01860f247aa6 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -87,6 +87,12 @@ static const struct cedrus_control cedrus_controls[] = { +@@ -88,6 +88,12 @@ static const struct cedrus_control cedrus_controls[] = { .codec = CEDRUS_CODEC_H265, .required = true, }, @@ -56,10 +73,10 @@ index a713630ce7ba..3040f483e0a2 100644 #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index b5d083812bea..deb9fa1de97c 100644 +index f19be772d78b..b518c5613fdf 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -72,6 +72,7 @@ struct cedrus_h265_run { +@@ -74,6 +74,7 @@ struct cedrus_h265_run { const struct v4l2_ctrl_hevc_sps *sps; const struct v4l2_ctrl_hevc_pps *pps; const struct v4l2_ctrl_hevc_slice_params *slice_params; @@ -67,7 +84,7 @@ index b5d083812bea..deb9fa1de97c 100644 }; struct cedrus_run { -@@ -88,6 +89,10 @@ struct cedrus_run { +@@ -90,6 +91,10 @@ struct cedrus_run { struct cedrus_buffer { struct v4l2_m2m_buffer m2m_buf; @@ -78,7 +95,7 @@ index b5d083812bea..deb9fa1de97c 100644 union { struct { unsigned int position; -@@ -121,12 +126,10 @@ struct cedrus_ctx { +@@ -123,12 +128,10 @@ struct cedrus_ctx { dma_addr_t neighbor_info_buf_dma; } h264; struct { @@ -94,10 +111,10 @@ index b5d083812bea..deb9fa1de97c 100644 } codec; }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index c50397f8692f..80c6d920142d 100644 +index c6d0ef66cdd0..104adb08492c 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -68,6 +68,8 @@ void cedrus_device_run(void *priv) +@@ -66,6 +66,8 @@ void cedrus_device_run(void *priv) V4L2_CID_MPEG_VIDEO_HEVC_PPS); run.h265.slice_params = cedrus_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); @@ -107,7 +124,7 @@ index c50397f8692f..80c6d920142d 100644 default: diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index f1c3665e95ab..2cc36d69548e 100644 +index fd4d86b02156..82d29c59b787 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -77,24 +77,25 @@ static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset) @@ -157,7 +174,7 @@ index f1c3665e95ab..2cc36d69548e 100644 }; u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; -@@ -157,28 +157,24 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, +@@ -158,28 +158,24 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, u8 num_ref_idx_active, u32 sram_offset) { @@ -195,7 +212,7 @@ index f1c3665e95ab..2cc36d69548e 100644 } static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, -@@ -219,6 +215,105 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, +@@ -220,6 +216,131 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, } } @@ -204,6 +221,7 @@ index f1c3665e95ab..2cc36d69548e 100644 +{ + const struct v4l2_ctrl_hevc_scaling_matrix *scaling; + struct cedrus_dev *dev = ctx->dev; ++ u32 i, j, k, val; + + scaling = run->h265.scaling_matrix; + @@ -219,21 +237,46 @@ index f1c3665e95ab..2cc36d69548e 100644 + (scaling->scaling_list_dc_coef_16x16[3] << 8) | + (scaling->scaling_list_dc_coef_16x16[2] << 0)); + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_8x8); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_8x8, -+ sizeof(scaling->scaling_list_8x8)); ++ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS); + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_32x32); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_32x32, -+ sizeof(scaling->scaling_list_32x32)); ++ for (i = 0; i < 6; i++) ++ for (j = 0; j < 8; j++) ++ for (k = 0; k < 8; k += 4) { ++ val = ((u32)scaling->scaling_list_8x8[i][j + (k + 3) * 8] << 24) | ++ ((u32)scaling->scaling_list_8x8[i][j + (k + 2) * 8] << 16) | ++ ((u32)scaling->scaling_list_8x8[i][j + (k + 1) * 8] << 8) | ++ scaling->scaling_list_8x8[i][j + k * 8]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_16x16); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_16x16, -+ sizeof(scaling->scaling_list_16x16)); ++ for (i = 0; i < 2; i++) ++ for (j = 0; j < 8; j++) ++ for (k = 0; k < 8; k += 4) { ++ val = ((u32)scaling->scaling_list_32x32[i][j + (k + 3) * 8] << 24) | ++ ((u32)scaling->scaling_list_32x32[i][j + (k + 2) * 8] << 16) | ++ ((u32)scaling->scaling_list_32x32[i][j + (k + 1) * 8] << 8) | ++ scaling->scaling_list_32x32[i][j + k * 8]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } + -+ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_4x4); -+ cedrus_h265_sram_write_data(dev, scaling->scaling_list_4x4, -+ sizeof(scaling->scaling_list_4x4)); ++ for (i = 0; i < 6; i++) ++ for (j = 0; j < 8; j++) ++ for (k = 0; k < 8; k += 4) { ++ val = ((u32)scaling->scaling_list_16x16[i][j + (k + 3) * 8] << 24) | ++ ((u32)scaling->scaling_list_16x16[i][j + (k + 2) * 8] << 16) | ++ ((u32)scaling->scaling_list_16x16[i][j + (k + 1) * 8] << 8) | ++ scaling->scaling_list_16x16[i][j + k * 8]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } ++ ++ for (i = 0; i < 6; i++) ++ for (j = 0; j < 4; j++) { ++ val = ((u32)scaling->scaling_list_4x4[i][j + 12] << 24) | ++ ((u32)scaling->scaling_list_4x4[i][j + 8] << 16) | ++ ((u32)scaling->scaling_list_4x4[i][j + 4] << 8) | ++ scaling->scaling_list_4x4[i][j]; ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val); ++ } +} + +static void write_entry_point_list(struct cedrus_ctx *ctx, @@ -301,7 +344,7 @@ index f1c3665e95ab..2cc36d69548e 100644 static void cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) { -@@ -227,6 +322,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -228,6 +349,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, const struct v4l2_ctrl_hevc_pps *pps; const struct v4l2_ctrl_hevc_slice_params *slice_params; const struct v4l2_hevc_pred_weight_table *pred_weight_table; @@ -309,7 +352,7 @@ index f1c3665e95ab..2cc36d69548e 100644 dma_addr_t src_buf_addr; dma_addr_t src_buf_end_addr; u32 chroma_log2_weight_denom; -@@ -239,43 +335,10 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -240,43 +362,10 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, slice_params = run->h265.slice_params; pred_weight_table = &slice_params->pred_weight_table; @@ -355,7 +398,7 @@ index f1c3665e95ab..2cc36d69548e 100644 /* Source offset and length in bits. */ -@@ -299,18 +362,35 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -300,18 +389,35 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, src_buf_end_addr = src_buf_addr + DIV_ROUND_UP(slice_params->bit_size, 8); @@ -397,7 +440,7 @@ index f1c3665e95ab..2cc36d69548e 100644 /* Initialize bitstream access. */ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); -@@ -333,6 +413,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -334,6 +440,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | @@ -405,7 +448,7 @@ index f1c3665e95ab..2cc36d69548e 100644 VE_DEC_H265_DEC_SPS_HDR_SEPARATE_COLOUR_PLANE_FLAG(sps->separate_colour_plane_flag) | VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); -@@ -362,7 +443,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -363,7 +470,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, VE_DEC_H265_DEC_PPS_CTRL1_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG(pps->pps_loop_filter_across_slices_enabled_flag) | VE_DEC_H265_DEC_PPS_CTRL1_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG(pps->loop_filter_across_tiles_enabled_flag) | VE_DEC_H265_DEC_PPS_CTRL1_ENTROPY_CODING_SYNC_ENABLED_FLAG(pps->entropy_coding_sync_enabled_flag) | @@ -414,7 +457,7 @@ index f1c3665e95ab..2cc36d69548e 100644 VE_DEC_H265_DEC_PPS_CTRL1_TRANSQUANT_BYPASS_ENABLE_FLAG(pps->transquant_bypass_enabled_flag) | VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_BIPRED_FLAG(pps->weighted_bipred_flag) | VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_PRED_FLAG(pps->weighted_pred_flag); -@@ -383,7 +464,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -384,7 +491,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) | VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type) | VE_DEC_H265_DEC_SLICE_HDR_INFO0_DEPENDENT_SLICE_SEGMENT_FLAG(pps->dependent_slice_segment_flag) | @@ -423,7 +466,7 @@ index f1c3665e95ab..2cc36d69548e 100644 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); -@@ -400,34 +481,68 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -401,34 +508,68 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + pred_weight_table->delta_chroma_log2_weight_denom; @@ -497,7 +540,7 @@ index f1c3665e95ab..2cc36d69548e 100644 output_pic_list_index = V4L2_HEVC_DPB_ENTRIES_NUM_MAX; pic_order_cnt[0] = slice_params->slice_pic_order_cnt; pic_order_cnt[1] = slice_params->slice_pic_order_cnt; -@@ -443,36 +558,36 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -444,36 +585,36 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, slice_params->ref_idx_l0, @@ -552,7 +595,7 @@ index f1c3665e95ab..2cc36d69548e 100644 } /* Enable appropriate interruptions. */ -@@ -483,9 +598,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) +@@ -484,9 +625,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -562,7 +605,7 @@ index f1c3665e95ab..2cc36d69548e 100644 ctx->codec.h265.neighbor_info_buf = dma_alloc_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, &ctx->codec.h265.neighbor_info_buf_addr, -@@ -493,6 +605,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) +@@ -494,6 +632,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) if (!ctx->codec.h265.neighbor_info_buf) return -ENOMEM; @@ -580,7 +623,7 @@ index f1c3665e95ab..2cc36d69548e 100644 return 0; } -@@ -500,17 +623,12 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) +@@ -501,17 +650,12 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -602,7 +645,7 @@ index f1c3665e95ab..2cc36d69548e 100644 static void cedrus_h265_trigger(struct cedrus_ctx *ctx) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index 87651d6b6227..a2931f322c7a 100644 +index 87651d6b6227..8d153dbe4f83 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h @@ -496,6 +496,9 @@ @@ -615,23 +658,11 @@ index 87651d6b6227..a2931f322c7a 100644 #define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) #define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ -@@ -513,7 +516,10 @@ - #define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80 - #define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO 0x400 - #define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT 0x20 --#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS 0x800 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_8x8 0x800 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_32x32 0x980 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_16x16 0xa00 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_4x4 0xb80 - #define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0 0xc00 - #define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1 0xc10 - diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index b9acdc03c839..adf00513c15f 100644 +index dbe6f9510641..a0817cae1d69 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -423,8 +423,18 @@ static void cedrus_buf_cleanup(struct vb2_buffer *vb) +@@ -433,8 +433,18 @@ static void cedrus_buf_cleanup(struct vb2_buffer *vb) struct vb2_queue *vq = vb->vb2_queue; struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); @@ -652,24 +683,24 @@ index b9acdc03c839..adf00513c15f 100644 static int cedrus_buf_out_validate(struct vb2_buffer *vb) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 005c71c67163..4bf3d79047f4 100644 +index 2de83d9f6d47..19469097c6d4 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -14,11 +14,13 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 645) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 646) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 647) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 648) +@@ -17,11 +17,13 @@ + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011) /* enum v4l2_ctrl_type type values */ - #define V4L2_CTRL_TYPE_HEVC_SPS 0x0115 - #define V4L2_CTRL_TYPE_HEVC_PPS 0x0116 - #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0117 -+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0118 + #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 + #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 + #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 ++#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 #define V4L2_HEVC_SLICE_TYPE_B 0 #define V4L2_HEVC_SLICE_TYPE_P 1 -@@ -91,7 +93,7 @@ struct v4l2_ctrl_hevc_pps { +@@ -95,7 +97,7 @@ struct v4l2_ctrl_hevc_pps { __u8 lists_modification_present_flag; __u8 log2_parallel_merge_level_minus2; __u8 slice_segment_header_extension_present_flag; @@ -678,7 +709,7 @@ index 005c71c67163..4bf3d79047f4 100644 }; #define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01 -@@ -175,7 +177,21 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -179,7 +181,21 @@ struct v4l2_ctrl_hevc_slice_params { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ struct v4l2_hevc_pred_weight_table pred_weight_table; @@ -701,3 +732,6 @@ index 005c71c67163..4bf3d79047f4 100644 }; #endif +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch b/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch deleted file mode 100644 index 4ce824a326..0000000000 --- a/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 9ce5c66f0f98cc968598307f7f7feb39a83d7342 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 26 Feb 2019 20:45:14 +0000 -Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error - ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -index 6c323510f128..b5a1a85c8700 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c -@@ -7,6 +7,7 @@ - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -+#include - #include - #include - #include -@@ -132,8 +133,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) - - dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); - -- if (stat & CEC_STAT_ERROR_INIT) { -- cec->tx_status = CEC_TX_STATUS_ERROR; -+ /* Status with both done and error_initiator bits have been seen -+ * on Rockchip RK3328 devices, transmit attempt seems to have failed -+ * when this happens, report as low drive and block cec-framework -+ * 100ms before core retransmits the failed message, this seems to -+ * mitigate the issue with failed transmit attempts. -+ */ -+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { -+ pr_info("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); -+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; - } else if (stat & CEC_STAT_DONE) { -@@ -144,6 +152,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) - cec->tx_status = CEC_TX_STATUS_NACK; - cec->tx_done = true; - ret = IRQ_WAKE_THREAD; -+ } else if (stat & CEC_STAT_ERROR_INIT) { -+ cec->tx_status = CEC_TX_STATUS_ERROR; -+ cec->tx_done = true; -+ ret = IRQ_WAKE_THREAD; - } - - if (stat & CEC_STAT_EOM) { -@@ -176,6 +188,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) - - if (cec->tx_done) { - cec->tx_done = false; -+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) -+ msleep(100); - cec_transmit_attempt_done(adap, cec->tx_status); - } - if (cec->rx_done) { --- -2.20.1 - diff --git a/projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch b/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch similarity index 86% rename from projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch rename to projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch index 40849ac4ab..2d5ff656c0 100644 --- a/projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch +++ b/projects/Allwinner/patches/linux/0011-cedrus-h264-4k.patch @@ -1,7 +1,7 @@ -From bd5fed9f390fea4ef8df1abb5f4ac6b64fab5974 Mon Sep 17 00:00:00 2001 +From 6a900f36a70f921886f05373846368ca6f09446e Mon Sep 17 00:00:00 2001 From: Jernej Skrabec -Date: Mon, 18 Feb 2019 21:51:31 +0100 -Subject: [PATCH] cedrus h264 4k +Date: Sat, 25 May 2019 14:16:55 +0200 +Subject: [PATCH 5/5] cedrus h264 4k Signed-off-by: Jernej Skrabec --- @@ -16,10 +16,10 @@ Signed-off-by: Jernej Skrabec 8 files changed, 98 insertions(+), 59 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index deb9fa1de97c..8815332fe1c1 100644 +index b518c5613fdf..ee00449d3345 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -116,14 +116,18 @@ struct cedrus_ctx { +@@ -118,14 +118,18 @@ struct cedrus_ctx { union { struct { @@ -43,7 +43,7 @@ index deb9fa1de97c..8815332fe1c1 100644 struct { void *neighbor_info_buf; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index 405545947b85..737a317fd1ee 100644 +index dcb8d3837869..4fafaf2c6c0a 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c @@ -55,16 +55,14 @@ static void cedrus_h264_write_sram(struct cedrus_dev *dev, @@ -73,20 +73,21 @@ index 405545947b85..737a317fd1ee 100644 struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; - unsigned int position = buf->codec.h264.position; - pic->top_field_order_cnt = top_field_order_cnt; - pic->bottom_field_order_cnt = bottom_field_order_cnt; -@@ -84,8 +81,8 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, - - pic->luma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0); - pic->chroma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1); -- pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 0); -- pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 1); -+ pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, buf, 0); -+ pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, buf, 1); + pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt); + pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt); +@@ -85,9 +82,9 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, + pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0)); + pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1)); + pic->mv_col_top_ptr = +- cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0)); ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 0)); + pic->mv_col_bot_ptr = +- cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1)); ++ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 1)); } static void cedrus_write_frame_list(struct cedrus_ctx *ctx, -@@ -148,6 +145,28 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -145,6 +142,28 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); output_buf->codec.h264.position = position; @@ -101,7 +102,7 @@ index 405545947b85..737a317fd1ee 100644 + if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) + field_size = field_size * 2; + -+ output_buf->mv_col_buf_size = ALIGN(field_size, 1024) * 2; ++ output_buf->mv_col_buf_size = field_size * 2; + output_buf->mv_col_buf = + dma_alloc_coherent(dev->dev, + output_buf->mv_col_buf_size, @@ -115,7 +116,7 @@ index 405545947b85..737a317fd1ee 100644 if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -@@ -331,6 +350,14 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, +@@ -338,6 +357,14 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | VE_H264_VLD_ADDR_LAST); @@ -130,7 +131,7 @@ index 405545947b85..737a317fd1ee 100644 /* * FIXME: Since the bitstream parsing is done in software, and * in userspace, this shouldn't be needed anymore. But it -@@ -471,7 +498,8 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, +@@ -476,7 +503,8 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, { struct cedrus_dev *dev = ctx->dev; @@ -140,7 +141,7 @@ index 405545947b85..737a317fd1ee 100644 cedrus_write(dev, VE_H264_SDROT_CTRL, 0); cedrus_write(dev, VE_H264_EXTRA_BUFFER1, -@@ -490,8 +518,6 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, +@@ -493,8 +521,6 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, static int cedrus_h264_start(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -149,7 +150,7 @@ index 405545947b85..737a317fd1ee 100644 int ret; /* -@@ -523,44 +549,42 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) +@@ -526,44 +552,42 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) goto err_pic_buf; } @@ -183,7 +184,7 @@ index 405545947b85..737a317fd1ee 100644 - * we need to work on. - */ - field_size = field_size * 2; -- ctx->codec.h264.mv_col_buf_field_size = ALIGN(field_size, 1024); +- ctx->codec.h264.mv_col_buf_field_size = field_size; - - mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; - ctx->codec.h264.mv_col_buf_size = mv_col_size; @@ -221,7 +222,7 @@ index 405545947b85..737a317fd1ee 100644 err_pic_buf: dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ctx->codec.h264.pic_info_buf, -@@ -572,15 +596,20 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx) +@@ -575,15 +599,20 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx) { struct cedrus_dev *dev = ctx->dev; @@ -246,10 +247,10 @@ index 405545947b85..737a317fd1ee 100644 static void cedrus_h264_trigger(struct cedrus_ctx *ctx) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index 2cc36d69548e..246d747d3fa9 100644 +index 51ee459b2d21..f915429e9c88 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -336,9 +336,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -337,9 +337,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, pred_weight_table = &slice_params->pred_weight_table; /* Activate H265 engine. */ @@ -261,7 +262,7 @@ index 2cc36d69548e..246d747d3fa9 100644 /* Source offset and length in bits. */ diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index 6be604c52d5c..4b6c69010e39 100644 +index 7d2f6eedfc28..9503d395855b 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -30,7 +30,8 @@ @@ -297,12 +298,12 @@ index 6be604c52d5c..4b6c69010e39 100644 cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index b43c77d54b95..40b44722b7c0 100644 +index 27d0882397aa..0e67c69812be 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -18,7 +18,8 @@ - - #define CEDRUS_CLOCK_RATE_DEFAULT 320000000 +@@ -16,7 +16,8 @@ + #ifndef _CEDRUS_HW_H_ + #define _CEDRUS_HW_H_ -int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); +int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec, @@ -311,7 +312,7 @@ index b43c77d54b95..40b44722b7c0 100644 void cedrus_dst_format_set(struct cedrus_dev *dev, diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -index cb45fda9aaeb..2f6384ca385d 100644 +index 13c34927bad5..fc00a2cbf9bf 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c @@ -96,7 +96,7 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) @@ -339,7 +340,7 @@ index a2931f322c7a..df000b7c99be 100644 #define VE_PRIMARY_FB_LINE_STRIDE 0xc8 diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index adf00513c15f..b24317b26fd2 100644 +index a0817cae1d69..d27a9e82ff91 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c @@ -29,8 +29,8 @@ @@ -354,5 +355,5 @@ index adf00513c15f..b24317b26fd2 100644 static struct cedrus_format cedrus_formats[] = { { -- -2.20.1 +2.21.0 diff --git a/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch b/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch deleted file mode 100644 index 680adb5aff..0000000000 --- a/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 18c9a269e2b744ee84f32de9d5c6c66857725ef8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 15 Dec 2018 12:56:53 +0100 -Subject: [PATCH 20/20] cedrus increase frequency - ---- - drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index b43c77d54b95..70677571f3d3 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -16,7 +16,7 @@ - #ifndef _CEDRUS_HW_H_ - #define _CEDRUS_HW_H_ - --#define CEDRUS_CLOCK_RATE_DEFAULT 320000000 -+#define CEDRUS_CLOCK_RATE_DEFAULT 402000000 - - int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); - void cedrus_engine_disable(struct cedrus_dev *dev); --- -2.20.0 -