Radeon: More PLL finetuning

packages/linux/patches/3.14.1/linux-997-02-drm-radeon-more-pll-bits.patch

@@ -0,0 +1,53 @@
+From 19de393134c00989b5b1cc5e6dd4ed444a897ace Mon Sep 17 00:00:00 2001
+From: Christian König <christian.koenig@amd.com>
+Date: Wed, 16 Apr 2014 09:54:21 +0000
+Subject: drm/radeon: improve PLL params if we don't match exactly
+
+Otherwise we might be quite off on older chipsets.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
+index 2f42912..fb3b505 100644
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -865,7 +865,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ 	unsigned post_div_min, post_div_max, post_div;
+ 	unsigned ref_div_min, ref_div_max, ref_div;
+ 	unsigned post_div_best, diff_best;
+-	unsigned nom, den, tmp;
++	unsigned nom, den;
+ 
+ 	/* determine allowed feedback divider range */
+ 	fb_div_min = pll->min_feedback_div;
+@@ -941,22 +941,23 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ 	ref_div_max = min(210 / post_div, ref_div_max);
+ 
+ 	/* get matching reference and feedback divider */
+-	ref_div = max(den / post_div, 1u);
+-	fb_div = nom;
++	ref_div = DIV_ROUND_CLOSEST(den, post_div);
++	fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den);
+ 
+ 	/* we're almost done, but reference and feedback
+ 	   divider might be to large now */
+ 
+-	tmp = ref_div;
++	nom = fb_div;
++	den = ref_div;
+ 
+         if (fb_div > fb_div_max) {
+-		ref_div = ref_div * fb_div_max / fb_div;
++		ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom);
+ 		fb_div = fb_div_max;
+ 	}
+ 
+ 	if (ref_div > ref_div_max) {
+ 		ref_div = ref_div_max;
+-		fb_div = nom * ref_div_max / tmp;
++		fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den);
+ 	}
+ 
+ 	/* reduce the numbers to a simpler ratio once more */
+--
+cgit v0.9.0.2-2-gbebe

packages/linux/patches/3.14.1/linux-997-03-drm-radeon-more-pll-bits-more-logging.patch

@@ -0,0 +1,57 @@
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
+index fb3b505..037db45 100644
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -820,6 +820,9 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
+ {
+ 	unsigned tmp;
+ 
++	DRM_DEBUG_KMS("nom: %d den: %d nom_min %d den_min %d\n",
++		      *nom, *den, nom_min, den_min);
++
+ 	/* reduce the numbers to a simpler ratio */
+ 	tmp = gcd(*nom, *den);
+ 	*nom /= tmp;
+@@ -876,6 +879,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ 		fb_div_max *= 10;
+ 	}
+ 
++	DRM_DEBUG_KMS("fb_div_min: %d fb_div_max: %d\n",
++		      fb_div_min, fb_div_max);
++
+ 	/* determine allowed ref divider range */
+ 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
+ 		ref_div_min = pll->reference_div;
+@@ -883,6 +889,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ 		ref_div_min = pll->min_ref_div;
+ 	ref_div_max = pll->max_ref_div;
+ 
++	DRM_DEBUG_KMS("ref_div_min: %d ref_div_max: %d\n",
++		      ref_div_min, ref_div_max);
++
+ 	/* determine allowed post divider range */
+ 	if (pll->flags & RADEON_PLL_USE_POST_DIV) {
+ 		post_div_min = pll->post_div;
+@@ -912,6 +921,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ 			post_div_max = pll->max_post_div;
+ 	}
+ 
++	DRM_DEBUG_KMS("post_div_min: %d post_div_max: %d\n",
++		      post_div_min, post_div_max);
++
+ 	/* represent the searched ratio as fractional number */
+ 	nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
+ 	den = pll->reference_freq;
+@@ -980,7 +992,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ 	*post_div_p = post_div;
+ 
+ 	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
+-		      freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
++		      freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
+ 		      ref_div, post_div);
+ }
+ 
+--
+cgit v0.9.0.2-2-gbebe