From c619b82a5d24bb8efb229397069dfaae3a2c6ff9 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 29 Mar 2020 12:11:55 +0200 Subject: [PATCH] Allwinner: Update to Linux 5.6 --- ...002-Add-support-for-sun4i-HDMI-audio.patch | 105 +- .../A20/patches/linux/0003-edid-fix.patch | 26 + projects/Allwinner/linux/linux.aarch64.conf | 83 +- projects/Allwinner/linux/linux.arm.conf | 56 +- .../linux/0001-backport-from-5.6.patch | 1957 ----------------- ...5.7.patch => 0001-backport-from-5.7.patch} | 0 .../linux/0006-wip-cec-improvements.patch | 29 +- 7 files changed, 158 insertions(+), 2098 deletions(-) create mode 100644 projects/Allwinner/devices/A20/patches/linux/0003-edid-fix.patch delete mode 100644 projects/Allwinner/patches/linux/0001-backport-from-5.6.patch rename projects/Allwinner/patches/linux/{0002-backport-from-5.7.patch => 0001-backport-from-5.7.patch} (100%) diff --git a/projects/Allwinner/devices/A20/patches/linux/0002-Add-support-for-sun4i-HDMI-audio.patch b/projects/Allwinner/devices/A20/patches/linux/0002-Add-support-for-sun4i-HDMI-audio.patch index 5564bbb8ba..47d8a672c0 100644 --- a/projects/Allwinner/devices/A20/patches/linux/0002-Add-support-for-sun4i-HDMI-audio.patch +++ b/projects/Allwinner/devices/A20/patches/linux/0002-Add-support-for-sun4i-HDMI-audio.patch @@ -1,102 +1,3 @@ -Subject: [1/2] dmaengine: sun4i: Add support for cyclic requests with dedicated DMA -From: Stefan Mavrodiev -Date: Fri, 10 Jan 2020 16:11:39 +0200 - -Currently the cyclic transfers can be used only with normal DMAs. They -can be used by pcm_dmaengine module, which is required for implementing -sound with sun4i-hdmi encoder. This is so because the controller can -accept audio only from a dedicated DMA. - -This patch enables them, following the existing style for the -scatter/gather type transfers. - -Signed-off-by: Stefan Mavrodiev ---- - drivers/dma/sun4i-dma.c | 45 ++++++++++++++++++++++------------------- - 1 file changed, 24 insertions(+), 21 deletions(-) - -diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c -index e397a50058c8..7b41815d86fb 100644 ---- a/drivers/dma/sun4i-dma.c -+++ b/drivers/dma/sun4i-dma.c -@@ -669,43 +669,41 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len, - dma_addr_t src, dest; - u32 endpoints; - int nr_periods, offset, plength, i; -+ u8 ram_type, io_mode, linear_mode; - - if (!is_slave_direction(dir)) { - dev_err(chan2dev(chan), "Invalid DMA direction\n"); - return NULL; - } - -- if (vchan->is_dedicated) { -- /* -- * As we are using this just for audio data, we need to use -- * normal DMA. There is nothing stopping us from supporting -- * dedicated DMA here as well, so if a client comes up and -- * requires it, it will be simple to implement it. -- */ -- dev_err(chan2dev(chan), -- "Cyclic transfers are only supported on Normal DMA\n"); -- return NULL; -- } -- - contract = generate_dma_contract(); - if (!contract) - return NULL; - - contract->is_cyclic = 1; - -- /* Figure out the endpoints and the address we need */ -+ if (vchan->is_dedicated) { -+ io_mode = SUN4I_DDMA_ADDR_MODE_IO; -+ linear_mode = SUN4I_DDMA_ADDR_MODE_LINEAR; -+ ram_type = SUN4I_DDMA_DRQ_TYPE_SDRAM; -+ } else { -+ io_mode = SUN4I_NDMA_ADDR_MODE_IO; -+ linear_mode = SUN4I_NDMA_ADDR_MODE_LINEAR; -+ ram_type = SUN4I_NDMA_DRQ_TYPE_SDRAM; -+ } -+ - if (dir == DMA_MEM_TO_DEV) { - src = buf; - dest = sconfig->dst_addr; -- endpoints = SUN4I_DMA_CFG_SRC_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM) | -- SUN4I_DMA_CFG_DST_DRQ_TYPE(vchan->endpoint) | -- SUN4I_DMA_CFG_DST_ADDR_MODE(SUN4I_NDMA_ADDR_MODE_IO); -+ endpoints = SUN4I_DMA_CFG_DST_DRQ_TYPE(vchan->endpoint) | -+ SUN4I_DMA_CFG_DST_ADDR_MODE(io_mode) | -+ SUN4I_DMA_CFG_SRC_DRQ_TYPE(ram_type); - } else { - src = sconfig->src_addr; - dest = buf; -- endpoints = SUN4I_DMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) | -- SUN4I_DMA_CFG_SRC_ADDR_MODE(SUN4I_NDMA_ADDR_MODE_IO) | -- SUN4I_DMA_CFG_DST_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM); -+ endpoints = SUN4I_DMA_CFG_DST_DRQ_TYPE(ram_type) | -+ SUN4I_DMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) | -+ SUN4I_DMA_CFG_SRC_ADDR_MODE(io_mode); - } - - /* -@@ -747,8 +745,13 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len, - dest = buf + offset; - - /* Make the promise */ -- promise = generate_ndma_promise(chan, src, dest, -- plength, sconfig, dir); -+ if (vchan->is_dedicated) -+ promise = generate_ddma_promise(chan, src, dest, -+ plength, sconfig); -+ else -+ promise = generate_ndma_promise(chan, src, dest, -+ plength, sconfig, dir); -+ - if (!promise) { - /* TODO: should we free everything? */ - return NULL; - Subject: [2/2] drm: sun4i: hdmi: Add support for sun4i HDMI encoder audio From: Stefan Mavrodiev Date: Fri, 10 Jan 2020 16:11:40 +0200 @@ -124,10 +25,10 @@ index 37e90e42943f..192b732b10cd 100644 +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -19,6 +19,7 @@ if DRM_SUN4I config DRM_SUN4I_HDMI - tristate "Allwinner A10 HDMI Controller Support" - default DRM_SUN4I + tristate "Allwinner A10 HDMI Controller Support" + default DRM_SUN4I + select SND_PCM_ELD - help + help Choose this option if you have an Allwinner SoC with an HDMI controller. diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile diff --git a/projects/Allwinner/devices/A20/patches/linux/0003-edid-fix.patch b/projects/Allwinner/devices/A20/patches/linux/0003-edid-fix.patch new file mode 100644 index 0000000000..331a4a3e3c --- /dev/null +++ b/projects/Allwinner/devices/A20/patches/linux/0003-edid-fix.patch @@ -0,0 +1,26 @@ +diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h +index 7ad3f06c127e..00ca35f07ba5 100644 +--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h +@@ -148,7 +148,7 @@ + #define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3 + + #define SUN4I_HDMI_DDC_CLK_REG 0x528 +-#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3) ++#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0xf) << 3) + #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7) + + #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540 +diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c +index 2ff780114106..6573de73ba74 100644 +--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c +@@ -33,7 +33,7 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long rate, + unsigned long best_rate = 0; + u8 best_m = 0, best_n = 0, _m, _n; + +- for (_m = 0; _m < 8; _m++) { ++ for (_m = 1; _m < 16; _m++) { + for (_n = 0; _n < 8; _n++) { + unsigned long tmp_rate; + diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index a8e93d9fbe..55aaa62b36 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,20 +1,20 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.5.0 Kernel Configuration +# Linux/arm64 5.6.0-rc7 Kernel Configuration # # -# Compiler: aarch64-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0 +# Compiler: aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025 # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=80300 +CONFIG_GCC_VERSION=90201 CONFIG_CLANG_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # @@ -104,6 +104,7 @@ CONFIG_CPU_ISOLATION=y # # RCU Subsystem # +CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y @@ -176,7 +177,9 @@ CONFIG_INITRAMFS_ROOT_GID=0 # CONFIG_RD_XZ is not set # CONFIG_RD_LZO is not set CONFIG_RD_LZ4=y -CONFIG_INITRAMFS_COMPRESSION=".lz4" +CONFIG_INITRAMFS_COMPRESSION_LZ4=y +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y @@ -196,6 +199,7 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -209,7 +213,9 @@ CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_BPF_SYSCALL=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y # CONFIG_BPF_JIT_ALWAYS_ON is not set +CONFIG_BPF_JIT_DEFAULT_ON=y # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_RSEQ=y @@ -323,8 +329,11 @@ CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y CONFIG_ARM64_ERRATUM_1024718=y CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE=y CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1530923=y CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_NVHE=y CONFIG_ARM64_ERRATUM_1319367=y CONFIG_ARM64_ERRATUM_1463225=y CONFIG_ARM64_ERRATUM_1542419=y @@ -405,6 +414,7 @@ CONFIG_KUSER_HELPERS=y CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM64_VHE=y # end of ARMv8.1 architectural features @@ -423,6 +433,13 @@ CONFIG_ARM64_CNP=y CONFIG_ARM64_PTR_AUTH=y # end of ARMv8.3 architectural features +# +# ARMv8.5 architectural features +# +CONFIG_ARM64_E0PD=y +CONFIG_ARCH_RANDOM=y +# end of ARMv8.5 architectural features + CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set @@ -593,7 +610,8 @@ CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y @@ -665,6 +683,7 @@ CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set @@ -812,6 +831,7 @@ CONFIG_NET_FOU=m # CONFIG_INET_AH is not set CONFIG_INET_ESP=y # CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=m CONFIG_INET_DIAG=y @@ -842,6 +862,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_NETLABEL is not set +# CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -1147,6 +1168,7 @@ CONFIG_NET_SCHED=y # CONFIG_NET_SCH_HHF is not set # CONFIG_NET_SCH_PIE is not set # CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set # CONFIG_NET_SCH_DEFAULT is not set # @@ -1298,6 +1320,7 @@ CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # @@ -1657,6 +1680,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set CONFIG_DUMMY=m +# CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set CONFIG_MACVLAN=m @@ -1799,6 +1823,7 @@ CONFIG_AC200_PHY=y # CONFIG_BCM7XXX_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM84881_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set @@ -2232,6 +2257,7 @@ CONFIG_DEVMEM=y CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y @@ -2351,7 +2377,6 @@ CONFIG_I2C_RK3X=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2488,9 +2513,11 @@ CONFIG_GPIO_DWAPB=y CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_GRGPIO is not set # CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_PL061=y # CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_XGENE=y # CONFIG_GPIO_XILINX is not set @@ -2536,6 +2563,7 @@ CONFIG_GPIO_MAX77620=y # CONFIG_GPIO_MOCKUP is not set # CONFIG_W1 is not set CONFIG_POWER_AVS=y +# CONFIG_QCOM_CPR is not set CONFIG_POWER_RESET=y CONFIG_POWER_RESET_BRCMSTB=y # CONFIG_POWER_RESET_GPIO is not set @@ -2600,6 +2628,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7310 is not set # CONFIG_SENSORS_ADT7410 is not set @@ -2612,6 +2641,7 @@ CONFIG_HWMON=y CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2645,6 +2675,7 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set # CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set @@ -2738,6 +2769,7 @@ CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set # CONFIG_THERMAL_GOV_USER_SPACE is not set CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y # CONFIG_CLOCK_THERMAL is not set # CONFIG_DEVFREQ_THERMAL is not set CONFIG_THERMAL_EMULATION=y @@ -2885,6 +2917,7 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set CONFIG_MFD_VEXPRESS_SYSREG=y @@ -2922,6 +2955,8 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -3452,7 +3487,7 @@ CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_KMS_CMA_HELPER=y @@ -3527,10 +3562,9 @@ CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # -# CONFIG_DRM_ANALOGIX_ANX78XX is not set # CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_DUMB_VGA_DAC is not set -# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set @@ -3542,6 +3576,9 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI86 is not set +CONFIG_DRM_ANALOGIX_ANX6345=m +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +CONFIG_DRM_ANALOGIX_DP=m # CONFIG_DRM_I2C_ADV7511 is not set CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set @@ -3630,6 +3667,7 @@ CONFIG_BACKLIGHT_LP855X=m # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set # CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_LED is not set # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y @@ -3880,6 +3918,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set @@ -4473,6 +4512,7 @@ CONFIG_DMA_SUN6I=y # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_QDMA is not set +# CONFIG_HISI_DMA is not set # CONFIG_INTEL_IDMA64 is not set CONFIG_MV_XOR_V2=y CONFIG_PL330_DMA=y @@ -4497,6 +4537,9 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_SELFTESTS is not set +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -4618,7 +4661,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_FIELDBUS_DEV is not set # CONFIG_USB_WUSB_CBAF is not set # CONFIG_UWB is not set -# CONFIG_EXFAT_FS is not set +# CONFIG_STAGING_EXFAT_FS is not set # CONFIG_WFX is not set # CONFIG_GOLDFISH is not set # CONFIG_MFD_CROS_EC is not set @@ -4678,6 +4721,7 @@ CONFIG_HISILICON_ERRATUM_161010101=y CONFIG_ARM64_ERRATUM_858921=y CONFIG_SUN50I_ERRATUM_UNKNOWN1=y CONFIG_CLKSRC_VERSATILE=y +# CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers CONFIG_MAILBOX=y @@ -4747,6 +4791,7 @@ CONFIG_SOC_BRCMSTB=y # # NXP/Freescale QorIQ SoC drivers # +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers @@ -4822,6 +4867,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_ADXL372_I2C is not set # CONFIG_BMA180 is not set # CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set @@ -4848,6 +4894,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # Analog to digital converters # +# CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set # CONFIG_AD7266 is not set # CONFIG_AD7291 is not set @@ -4874,6 +4921,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_INA2XX_ADC is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set # CONFIG_LTC2497 is not set # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set @@ -5164,6 +5212,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set # CONFIG_DPS310 is not set # CONFIG_HP03 is not set # CONFIG_MPL115_I2C is not set @@ -5189,6 +5238,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set # CONFIG_MB1232 is not set +# CONFIG_PING is not set # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set # CONFIG_SX9500 is not set @@ -5238,6 +5288,8 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_BRCMSTB_RESCAL is not set +# CONFIG_RESET_INTEL_GW is not set CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set @@ -5266,6 +5318,7 @@ CONFIG_PHY_QCOM_USB_HS=y # CONFIG_PHY_QCOM_USB_HSIC is not set CONFIG_PHY_SAMSUNG_USB2=y # CONFIG_PHY_TUSB1210 is not set +# CONFIG_PHY_INTEL_EMMC is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -5354,6 +5407,9 @@ CONFIG_F2FS_FS_POSIX_ACL=y # CONFIG_F2FS_FS_SECURITY is not set # CONFIG_F2FS_CHECK_FS is not set # CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZ4=y # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -5503,6 +5559,7 @@ CONFIG_NFS_V4_SECURITY_LABEL=y CONFIG_ROOT_NFS=y # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y # CONFIG_NFSD is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -5869,6 +5926,7 @@ CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMPRESS=m CONFIG_ZSTD_DECOMPRESS=y @@ -5999,6 +6057,8 @@ CONFIG_DEBUG_MISC=y # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set @@ -6108,7 +6168,6 @@ CONFIG_STRICT_DEVMEM=y # # arm64 Debugging # -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set # CONFIG_PID_IN_CONTEXTIDR is not set # CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set # CONFIG_DEBUG_WX is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index 936f1da8d8..1f1ab12365 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.5.0 Kernel Configuration +# Linux/arm 5.6.0-rc7 Kernel Configuration # # @@ -14,7 +14,7 @@ CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y # # General setup @@ -168,9 +168,9 @@ CONFIG_RD_GZIP=y # CONFIG_RD_XZ is not set # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set -CONFIG_INITRAMFS_COMPRESSION_NONE=y # CONFIG_INITRAMFS_COMPRESSION_GZIP is not set -CONFIG_INITRAMFS_COMPRESSION="" +CONFIG_INITRAMFS_COMPRESSION_NONE=y +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y @@ -832,6 +832,7 @@ CONFIG_NET_FOU=m # CONFIG_INET_AH is not set CONFIG_INET_ESP=m # CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=m # CONFIG_INET_DIAG is not set @@ -857,6 +858,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -1128,6 +1130,7 @@ CONFIG_NET_SCHED=y # CONFIG_NET_SCH_HHF is not set # CONFIG_NET_SCH_PIE is not set # CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set # CONFIG_NET_SCH_DEFAULT is not set # @@ -1325,6 +1328,7 @@ CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_PAGE_POOL=y # CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # @@ -1593,6 +1597,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set CONFIG_DUMMY=m +# CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set CONFIG_MACVLAN=m @@ -1712,6 +1717,7 @@ CONFIG_SWPHY=y # CONFIG_BCM7XXX_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM84881_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set @@ -2098,6 +2104,7 @@ CONFIG_DEVKMEM=y CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y @@ -2199,7 +2206,6 @@ CONFIG_I2C_MV64XXX=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2329,9 +2335,11 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set # CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_XILINX is not set # CONFIG_GPIO_ZEVIO is not set @@ -2428,6 +2436,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7310 is not set # CONFIG_SENSORS_ADT7410 is not set @@ -2439,6 +2448,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2472,6 +2482,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set # CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set @@ -2564,6 +2575,7 @@ CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set # CONFIG_THERMAL_GOV_USER_SPACE is not set CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y CONFIG_CLOCK_THERMAL=y CONFIG_DEVFREQ_THERMAL=y # CONFIG_THERMAL_EMULATION is not set @@ -2722,6 +2734,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_RAVE_SP_CORE is not set @@ -2755,6 +2768,8 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -3395,7 +3410,7 @@ CONFIG_DRM_KMS_FB_HELPER=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_KMS_CMA_HELPER=y @@ -3469,10 +3484,9 @@ CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # -# CONFIG_DRM_ANALOGIX_ANX78XX is not set # CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_DUMB_VGA_DAC is not set -# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set @@ -3484,6 +3498,8 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set # CONFIG_DRM_I2C_ADV7511 is not set CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set @@ -3797,6 +3813,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set @@ -4404,6 +4421,9 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_SELFTESTS is not set +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -4524,7 +4544,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_FIELDBUS_DEV is not set # CONFIG_USB_WUSB_CBAF is not set # CONFIG_UWB is not set -# CONFIG_EXFAT_FS is not set +# CONFIG_STAGING_EXFAT_FS is not set # CONFIG_WFX is not set # CONFIG_GOLDFISH is not set # CONFIG_MFD_CROS_EC is not set @@ -4580,6 +4600,7 @@ CONFIG_SUN4I_TIMER=y CONFIG_SUN5I_HSTIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers # CONFIG_MAILBOX is not set @@ -4622,6 +4643,7 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # # NXP/Freescale QorIQ SoC drivers # +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers @@ -4695,6 +4717,7 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_ADXL372_I2C is not set # CONFIG_BMA180 is not set # CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set @@ -4721,6 +4744,7 @@ CONFIG_IIO_SW_TRIGGER=y # # Analog to digital converters # +# CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set # CONFIG_AD7266 is not set # CONFIG_AD7291 is not set @@ -4747,6 +4771,7 @@ CONFIG_AXP20X_ADC=y # CONFIG_INA2XX_ADC is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set # CONFIG_LTC2497 is not set # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set @@ -5031,6 +5056,7 @@ CONFIG_SUN4I_GPADC=y # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set # CONFIG_DPS310 is not set # CONFIG_HP03 is not set # CONFIG_MPL115_I2C is not set @@ -5056,6 +5082,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set # CONFIG_MB1232 is not set +# CONFIG_PING is not set # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set # CONFIG_SX9500 is not set @@ -5102,6 +5129,8 @@ CONFIG_ARM_GIC_MAX_NR=1 # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_BRCMSTB_RESCAL is not set +# CONFIG_RESET_INTEL_GW is not set CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set @@ -5126,6 +5155,7 @@ CONFIG_PHY_SUN50I_USB3=y # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set +# CONFIG_PHY_INTEL_EMMC is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -5218,6 +5248,9 @@ CONFIG_F2FS_FS_POSIX_ACL=y # CONFIG_F2FS_FS_SECURITY is not set # CONFIG_F2FS_CHECK_FS is not set # CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZ4=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -5239,7 +5272,6 @@ CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set -# CONFIG_OVERLAY_FS_XINO_AUTO is not set # CONFIG_OVERLAY_FS_METACOPY is not set # @@ -5339,6 +5371,7 @@ CONFIG_NFS_V4_1_MIGRATION=y CONFIG_ROOT_NFS=y # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y # CONFIG_NFSD is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -5676,8 +5709,9 @@ CONFIG_XXHASH=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_LZO_COMPRESS=m +CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMPRESS=m CONFIG_ZSTD_DECOMPRESS=y diff --git a/projects/Allwinner/patches/linux/0001-backport-from-5.6.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.6.patch deleted file mode 100644 index ef5f45e946..0000000000 --- a/projects/Allwinner/patches/linux/0001-backport-from-5.6.patch +++ /dev/null @@ -1,1957 +0,0 @@ -From 2c63afdafa5100397308036a9dfbde24db5aecd5 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Sat, 9 Nov 2019 12:34:36 +0100 -Subject: [PATCH] arm64: dts: allwinner: orange-pi-3: Enable IR receiver - -Orange Pi 3 has an on-board IR receiver, enable it. - -Signed-off-by: Andre Heider -Acked-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index 4ed3fc2c7734..d422bc68dcf3 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -274,6 +274,10 @@ sw { - }; - }; - -+&r_ir { -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; --- -2.24.1 - -From 59f3f4dcf68d276ff2ed0245f7c1938403de4c91 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Thu, 14 Nov 2019 11:25:41 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: Enable USB 3.0 host for Beelink - GS1 and Tanix TX6 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enable USB 3.0 phy and host controller. - -VBUS is directly connected to DCIN 5V and doesn't -require to be switched on. - -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 8 ++++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 8 ++++++++ - 2 files changed, 16 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index f335f7482a73..b004e151222a 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -76,6 +76,10 @@ &de { - status = "okay"; - }; - -+&dwc3 { -+ status = "okay"; -+}; -+ - &ehci0 { - status = "okay"; - }; -@@ -292,3 +296,7 @@ &usb2phy { - usb0_vbus-supply = <®_vcc5v>; - status = "okay"; - }; -+ -+&usb3phy { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -index bccfe1e65b6a..0b6361a5c172 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -45,6 +45,10 @@ &de { - status = "okay"; - }; - -+&dwc3 { -+ status = "okay"; -+}; -+ - &ehci0 { - status = "okay"; - }; -@@ -102,3 +106,7 @@ &usb2otg { - &usb2phy { - status = "okay"; - }; -+ -+&usb3phy { -+ status = "okay"; -+}; --- -2.24.1 - -From 42ccc3d79b7f5685beef2e0b26e6ec01c61f5162 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 17 Nov 2019 14:00:58 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: tanix-tx6: Add IR remote mapping - -Tanix TX6 box comes with a remote. Add a mapping for it. - -Suggested-by: Michael Lange -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -index 0b6361a5c172..50d51f69dc5d 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -89,6 +89,7 @@ &ohci3 { - }; - - &r_ir { -+ linux,rc-map-name = "rc-tanix-tx5max"; - status = "okay"; - }; - --- -2.24.1 - -From 88432f5f8469ba67a2e20aeda04bd64cb88f9c6c Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 19 Nov 2019 18:53:18 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: Add PWM node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Allwinner H6 PWM is similar to that in A20 except that it has additional -bus clock and reset line. - -Note that first PWM channel is connected to output pin and second -channel is used internally, as a clock source to AC200 co-packaged chip. -This means that any combination of these two channels can be used and -thus it doesn't make sense to add pinctrl nodes at this point. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 24ffe2dcbddb..83f98bd75ee6 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -255,6 +255,16 @@ watchdog: watchdog@30090a0 { - status = "disabled"; - }; - -+ pwm: pwm@300a000 { -+ compatible = "allwinner,sun50i-h6-pwm"; -+ reg = <0x0300a000 0x400>; -+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; -+ clock-names = "mod", "bus"; -+ resets = <&ccu RST_BUS_PWM>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h6-pinctrl"; - reg = <0x0300b000 0x400>; --- -2.24.1 - -From 730a45ccd9322dd918a5dcaf8ae1482400fa5b23 Mon Sep 17 00:00:00 2001 -From: Yangtao Li -Date: Thu, 19 Dec 2019 09:28:17 -0800 -Subject: [PATCH] thermal/drivers/sun8i: Add thermal driver for - H6/H5/H3/A64/A83T/R40 - -This patch adds the support for allwinner thermal sensor, within -allwinner SoC. It will register sensors for thermal framework -and use device tree to bind cooling device. - -Signed-off-by: Yangtao Li -Signed-off-by: Ondrej Jirman -Signed-off-by: Vasily Khoruzhick -Acked-by: Maxime Ripard -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20191219172823.1652600-2-anarsoul@gmail.com ---- - MAINTAINERS | 8 + - drivers/thermal/Kconfig | 14 + - drivers/thermal/Makefile | 1 + - drivers/thermal/sun8i_thermal.c | 639 ++++++++++++++++++++++++++++++++ - 4 files changed, 662 insertions(+) - create mode 100644 drivers/thermal/sun8i_thermal.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index 6d4940474674..723513023ec6 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -694,6 +694,14 @@ L: linux-crypto@vger.kernel.org - S: Maintained - F: drivers/crypto/allwinner/ - -+ALLWINNER THERMAL DRIVER -+M: Vasily Khoruzhick -+M: Yangtao Li -+L: linux-pm@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml -+F: drivers/thermal/sun8i_thermal.c -+ - ALLWINNER VPU DRIVER - M: Maxime Ripard - M: Paul Kocialkowski -diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index dc36941aef6e..5a05db5438d6 100644 ---- a/drivers/thermal/Kconfig -+++ b/drivers/thermal/Kconfig -@@ -280,6 +280,20 @@ config SPEAR_THERMAL - Enable this to plug the SPEAr thermal sensor driver into the Linux - thermal framework. - -+config SUN8I_THERMAL -+ tristate "Allwinner sun8i thermal driver" -+ depends on ARCH_SUNXI || COMPILE_TEST -+ depends on HAS_IOMEM -+ depends on NVMEM -+ depends on OF -+ depends on RESET_CONTROLLER -+ help -+ Support for the sun8i thermal sensor driver into the Linux thermal -+ framework. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called sun8i-thermal. -+ - config ROCKCHIP_THERMAL - tristate "Rockchip thermal driver" - depends on ARCH_ROCKCHIP || COMPILE_TEST -diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index d502a597a717..9fb88e26fb10 100644 ---- a/drivers/thermal/Makefile -+++ b/drivers/thermal/Makefile -@@ -32,6 +32,7 @@ thermal_sys-$(CONFIG_DEVFREQ_THERMAL) += devfreq_cooling.o - obj-y += broadcom/ - obj-$(CONFIG_THERMAL_MMIO) += thermal_mmio.o - obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o -+obj-$(CONFIG_SUN8I_THERMAL) += sun8i_thermal.o - obj-$(CONFIG_ROCKCHIP_THERMAL) += rockchip_thermal.o - obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o - obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o -diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c -new file mode 100644 -index 000000000000..23a5f4aa4be4 ---- /dev/null -+++ b/drivers/thermal/sun8i_thermal.c -@@ -0,0 +1,639 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Thermal sensor driver for Allwinner SOC -+ * Copyright (C) 2019 Yangtao Li -+ * -+ * Based on the work of Icenowy Zheng -+ * Based on the work of Ondrej Jirman -+ * Based on the work of Josef Gajdusek -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MAX_SENSOR_NUM 4 -+ -+#define FT_TEMP_MASK GENMASK(11, 0) -+#define TEMP_CALIB_MASK GENMASK(11, 0) -+#define CALIBRATE_DEFAULT 0x800 -+ -+#define SUN8I_THS_CTRL0 0x00 -+#define SUN8I_THS_CTRL2 0x40 -+#define SUN8I_THS_IC 0x44 -+#define SUN8I_THS_IS 0x48 -+#define SUN8I_THS_MFC 0x70 -+#define SUN8I_THS_TEMP_CALIB 0x74 -+#define SUN8I_THS_TEMP_DATA 0x80 -+ -+#define SUN50I_THS_CTRL0 0x00 -+#define SUN50I_H6_THS_ENABLE 0x04 -+#define SUN50I_H6_THS_PC 0x08 -+#define SUN50I_H6_THS_DIC 0x10 -+#define SUN50I_H6_THS_DIS 0x20 -+#define SUN50I_H6_THS_MFC 0x30 -+#define SUN50I_H6_THS_TEMP_CALIB 0xa0 -+#define SUN50I_H6_THS_TEMP_DATA 0xc0 -+ -+#define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x)) -+#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16) -+#define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8) -+ -+#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16) -+#define SUN50I_THS_FILTER_EN BIT(2) -+#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) -+#define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) -+#define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x) -+ -+/* millidegree celsius */ -+#define THS_EFUSE_CP_FT_MASK 0x3000 -+#define THS_EFUSE_CP_FT_BIT 12 -+#define THS_CALIBRATION_IN_FT 1 -+ -+struct tsensor { -+ struct ths_device *tmdev; -+ struct thermal_zone_device *tzd; -+ int id; -+}; -+ -+struct ths_thermal_chip { -+ bool has_mod_clk; -+ bool has_bus_clk_reset; -+ int sensor_num; -+ int offset; -+ int scale; -+ int ft_deviation; -+ int temp_data_base; -+ int (*calibrate)(struct ths_device *tmdev, -+ u16 *caldata, int callen); -+ int (*init)(struct ths_device *tmdev); -+ int (*irq_ack)(struct ths_device *tmdev); -+ int (*calc_temp)(struct ths_device *tmdev, -+ int id, int reg); -+}; -+ -+struct ths_device { -+ const struct ths_thermal_chip *chip; -+ struct device *dev; -+ struct regmap *regmap; -+ struct reset_control *reset; -+ struct clk *bus_clk; -+ struct clk *mod_clk; -+ struct tsensor sensor[MAX_SENSOR_NUM]; -+ u32 cp_ft_flag; -+}; -+ -+/* Temp Unit: millidegree Celsius */ -+static int sun8i_ths_calc_temp(struct ths_device *tmdev, -+ int id, int reg) -+{ -+ return tmdev->chip->offset - (reg * tmdev->chip->scale / 10); -+} -+ -+static int sun50i_h5_calc_temp(struct ths_device *tmdev, -+ int id, int reg) -+{ -+ if (reg >= 0x500) -+ return -1191 * reg / 10 + 223000; -+ else if (!id) -+ return -1452 * reg / 10 + 259000; -+ else -+ return -1590 * reg / 10 + 276000; -+} -+ -+static int sun8i_ths_get_temp(void *data, int *temp) -+{ -+ struct tsensor *s = data; -+ struct ths_device *tmdev = s->tmdev; -+ int val = 0; -+ -+ regmap_read(tmdev->regmap, tmdev->chip->temp_data_base + -+ 0x4 * s->id, &val); -+ -+ /* ths have no data yet */ -+ if (!val) -+ return -EAGAIN; -+ -+ *temp = tmdev->chip->calc_temp(tmdev, s->id, val); -+ /* -+ * According to the original sdk, there are some platforms(rarely) -+ * that add a fixed offset value after calculating the temperature -+ * value. We can't simply put it on the formula for calculating the -+ * temperature above, because the formula for calculating the -+ * temperature above is also used when the sensor is calibrated. If -+ * do this, the correct calibration formula is hard to know. -+ */ -+ *temp += tmdev->chip->ft_deviation; -+ -+ return 0; -+} -+ -+static const struct thermal_zone_of_device_ops ths_ops = { -+ .get_temp = sun8i_ths_get_temp, -+}; -+ -+static const struct regmap_config config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .fast_io = true, -+ .max_register = 0xfc, -+}; -+ -+static int sun8i_h3_irq_ack(struct ths_device *tmdev) -+{ -+ int i, state, ret = 0; -+ -+ regmap_read(tmdev->regmap, SUN8I_THS_IS, &state); -+ -+ for (i = 0; i < tmdev->chip->sensor_num; i++) { -+ if (state & SUN8I_THS_DATA_IRQ_STS(i)) { -+ regmap_write(tmdev->regmap, SUN8I_THS_IS, -+ SUN8I_THS_DATA_IRQ_STS(i)); -+ ret |= BIT(i); -+ } -+ } -+ -+ return ret; -+} -+ -+static int sun50i_h6_irq_ack(struct ths_device *tmdev) -+{ -+ int i, state, ret = 0; -+ -+ regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, &state); -+ -+ for (i = 0; i < tmdev->chip->sensor_num; i++) { -+ if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) { -+ regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS, -+ SUN50I_H6_THS_DATA_IRQ_STS(i)); -+ ret |= BIT(i); -+ } -+ } -+ -+ return ret; -+} -+ -+static irqreturn_t sun8i_irq_thread(int irq, void *data) -+{ -+ struct ths_device *tmdev = data; -+ int i, state; -+ -+ state = tmdev->chip->irq_ack(tmdev); -+ -+ for (i = 0; i < tmdev->chip->sensor_num; i++) { -+ if (state & BIT(i)) -+ thermal_zone_device_update(tmdev->sensor[i].tzd, -+ THERMAL_EVENT_UNSPECIFIED); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int sun8i_h3_ths_calibrate(struct ths_device *tmdev, -+ u16 *caldata, int callen) -+{ -+ int i; -+ -+ if (!caldata[0] || callen < 2 * tmdev->chip->sensor_num) -+ return -EINVAL; -+ -+ for (i = 0; i < tmdev->chip->sensor_num; i++) { -+ int offset = (i % 2) << 4; -+ -+ regmap_update_bits(tmdev->regmap, -+ SUN8I_THS_TEMP_CALIB + (4 * (i >> 1)), -+ 0xfff << offset, -+ caldata[i] << offset); -+ } -+ -+ return 0; -+} -+ -+static int sun50i_h6_ths_calibrate(struct ths_device *tmdev, -+ u16 *caldata, int callen) -+{ -+ struct device *dev = tmdev->dev; -+ int i, ft_temp; -+ -+ if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) -+ return -EINVAL; -+ -+ /* -+ * efuse layout: -+ * -+ * 0 11 16 32 -+ * +-------+-------+-------+ -+ * |temp| |sensor0|sensor1| -+ * +-------+-------+-------+ -+ * -+ * The calibration data on the H6 is the ambient temperature and -+ * sensor values that are filled during the factory test stage. -+ * -+ * The unit of stored FT temperature is 0.1 degreee celusis. -+ * -+ * We need to calculate a delta between measured and caluclated -+ * register values and this will become a calibration offset. -+ */ -+ ft_temp = (caldata[0] & FT_TEMP_MASK) * 100; -+ tmdev->cp_ft_flag = (caldata[0] & THS_EFUSE_CP_FT_MASK) -+ >> THS_EFUSE_CP_FT_BIT; -+ -+ for (i = 0; i < tmdev->chip->sensor_num; i++) { -+ int sensor_reg = caldata[i + 1]; -+ int cdata, offset; -+ int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); -+ -+ /* -+ * Calibration data is CALIBRATE_DEFAULT - (calculated -+ * temperature from sensor reading at factory temperature -+ * minus actual factory temperature) * 14.88 (scale from -+ * temperature to register values) -+ */ -+ cdata = CALIBRATE_DEFAULT - -+ ((sensor_temp - ft_temp) * 10 / tmdev->chip->scale); -+ if (cdata & ~TEMP_CALIB_MASK) { -+ /* -+ * Calibration value more than 12-bit, but calibration -+ * register is 12-bit. In this case, ths hardware can -+ * still work without calibration, although the data -+ * won't be so accurate. -+ */ -+ dev_warn(dev, "sensor%d is not calibrated.\n", i); -+ continue; -+ } -+ -+ offset = (i % 2) * 16; -+ regmap_update_bits(tmdev->regmap, -+ SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4), -+ 0xfff << offset, -+ cdata << offset); -+ } -+ -+ return 0; -+} -+ -+static int sun8i_ths_calibrate(struct ths_device *tmdev) -+{ -+ struct nvmem_cell *calcell; -+ struct device *dev = tmdev->dev; -+ u16 *caldata; -+ size_t callen; -+ int ret = 0; -+ -+ calcell = devm_nvmem_cell_get(dev, "calibration"); -+ if (IS_ERR(calcell)) { -+ if (PTR_ERR(calcell) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ /* -+ * Even if the external calibration data stored in sid is -+ * not accessible, the THS hardware can still work, although -+ * the data won't be so accurate. -+ * -+ * The default value of calibration register is 0x800 for -+ * every sensor, and the calibration value is usually 0x7xx -+ * or 0x8xx, so they won't be away from the default value -+ * for a lot. -+ * -+ * So here we do not return error if the calibartion data is -+ * not available, except the probe needs deferring. -+ */ -+ goto out; -+ } -+ -+ caldata = nvmem_cell_read(calcell, &callen); -+ if (IS_ERR(caldata)) { -+ ret = PTR_ERR(caldata); -+ goto out; -+ } -+ -+ tmdev->chip->calibrate(tmdev, caldata, callen); -+ -+ kfree(caldata); -+out: -+ return ret; -+} -+ -+static int sun8i_ths_resource_init(struct ths_device *tmdev) -+{ -+ struct device *dev = tmdev->dev; -+ struct platform_device *pdev = to_platform_device(dev); -+ void __iomem *base; -+ int ret; -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ tmdev->regmap = devm_regmap_init_mmio(dev, base, &config); -+ if (IS_ERR(tmdev->regmap)) -+ return PTR_ERR(tmdev->regmap); -+ -+ if (tmdev->chip->has_bus_clk_reset) { -+ tmdev->reset = devm_reset_control_get(dev, 0); -+ if (IS_ERR(tmdev->reset)) -+ return PTR_ERR(tmdev->reset); -+ -+ tmdev->bus_clk = devm_clk_get(&pdev->dev, "bus"); -+ if (IS_ERR(tmdev->bus_clk)) -+ return PTR_ERR(tmdev->bus_clk); -+ } -+ -+ if (tmdev->chip->has_mod_clk) { -+ tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod"); -+ if (IS_ERR(tmdev->mod_clk)) -+ return PTR_ERR(tmdev->mod_clk); -+ } -+ -+ ret = reset_control_deassert(tmdev->reset); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(tmdev->bus_clk); -+ if (ret) -+ goto assert_reset; -+ -+ ret = clk_set_rate(tmdev->mod_clk, 24000000); -+ if (ret) -+ goto bus_disable; -+ -+ ret = clk_prepare_enable(tmdev->mod_clk); -+ if (ret) -+ goto bus_disable; -+ -+ ret = sun8i_ths_calibrate(tmdev); -+ if (ret) -+ goto mod_disable; -+ -+ return 0; -+ -+mod_disable: -+ clk_disable_unprepare(tmdev->mod_clk); -+bus_disable: -+ clk_disable_unprepare(tmdev->bus_clk); -+assert_reset: -+ reset_control_assert(tmdev->reset); -+ -+ return ret; -+} -+ -+static int sun8i_h3_thermal_init(struct ths_device *tmdev) -+{ -+ int val; -+ -+ /* average over 4 samples */ -+ regmap_write(tmdev->regmap, SUN8I_THS_MFC, -+ SUN50I_THS_FILTER_EN | -+ SUN50I_THS_FILTER_TYPE(1)); -+ /* -+ * clkin = 24MHz -+ * filter_samples = 4 -+ * period = 0.25s -+ * -+ * x = period * clkin / 4096 / filter_samples - 1 -+ * = 365 -+ */ -+ val = GENMASK(7 + tmdev->chip->sensor_num, 8); -+ regmap_write(tmdev->regmap, SUN8I_THS_IC, -+ SUN50I_H6_THS_PC_TEMP_PERIOD(365) | val); -+ /* -+ * T_acq = 20us -+ * clkin = 24MHz -+ * -+ * x = T_acq * clkin - 1 -+ * = 479 -+ */ -+ regmap_write(tmdev->regmap, SUN8I_THS_CTRL0, -+ SUN8I_THS_CTRL0_T_ACQ0(479)); -+ val = GENMASK(tmdev->chip->sensor_num - 1, 0); -+ regmap_write(tmdev->regmap, SUN8I_THS_CTRL2, -+ SUN8I_THS_CTRL2_T_ACQ1(479) | val); -+ -+ return 0; -+} -+ -+/* -+ * Without this undocummented value, the returned temperatures would -+ * be higher than real ones by about 20C. -+ */ -+#define SUN50I_H6_CTRL0_UNK 0x0000002f -+ -+static int sun50i_h6_thermal_init(struct ths_device *tmdev) -+{ -+ int val; -+ -+ /* -+ * T_acq = 20us -+ * clkin = 24MHz -+ * -+ * x = T_acq * clkin - 1 -+ * = 479 -+ */ -+ regmap_write(tmdev->regmap, SUN50I_THS_CTRL0, -+ SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479)); -+ /* average over 4 samples */ -+ regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC, -+ SUN50I_THS_FILTER_EN | -+ SUN50I_THS_FILTER_TYPE(1)); -+ /* -+ * clkin = 24MHz -+ * filter_samples = 4 -+ * period = 0.25s -+ * -+ * x = period * clkin / 4096 / filter_samples - 1 -+ * = 365 -+ */ -+ regmap_write(tmdev->regmap, SUN50I_H6_THS_PC, -+ SUN50I_H6_THS_PC_TEMP_PERIOD(365)); -+ /* enable sensor */ -+ val = GENMASK(tmdev->chip->sensor_num - 1, 0); -+ regmap_write(tmdev->regmap, SUN50I_H6_THS_ENABLE, val); -+ /* thermal data interrupt enable */ -+ val = GENMASK(tmdev->chip->sensor_num - 1, 0); -+ regmap_write(tmdev->regmap, SUN50I_H6_THS_DIC, val); -+ -+ return 0; -+} -+ -+static int sun8i_ths_register(struct ths_device *tmdev) -+{ -+ int i; -+ -+ for (i = 0; i < tmdev->chip->sensor_num; i++) { -+ tmdev->sensor[i].tmdev = tmdev; -+ tmdev->sensor[i].id = i; -+ tmdev->sensor[i].tzd = -+ devm_thermal_zone_of_sensor_register(tmdev->dev, -+ i, -+ &tmdev->sensor[i], -+ &ths_ops); -+ if (IS_ERR(tmdev->sensor[i].tzd)) -+ return PTR_ERR(tmdev->sensor[i].tzd); -+ } -+ -+ return 0; -+} -+ -+static int sun8i_ths_probe(struct platform_device *pdev) -+{ -+ struct ths_device *tmdev; -+ struct device *dev = &pdev->dev; -+ int ret, irq; -+ -+ tmdev = devm_kzalloc(dev, sizeof(*tmdev), GFP_KERNEL); -+ if (!tmdev) -+ return -ENOMEM; -+ -+ tmdev->dev = dev; -+ tmdev->chip = of_device_get_match_data(&pdev->dev); -+ if (!tmdev->chip) -+ return -EINVAL; -+ -+ platform_set_drvdata(pdev, tmdev); -+ -+ ret = sun8i_ths_resource_init(tmdev); -+ if (ret) -+ return ret; -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = tmdev->chip->init(tmdev); -+ if (ret) -+ return ret; -+ -+ ret = sun8i_ths_register(tmdev); -+ if (ret) -+ return ret; -+ -+ /* -+ * Avoid entering the interrupt handler, the thermal device is not -+ * registered yet, we deffer the registration of the interrupt to -+ * the end. -+ */ -+ ret = devm_request_threaded_irq(dev, irq, NULL, -+ sun8i_irq_thread, -+ IRQF_ONESHOT, "ths", tmdev); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int sun8i_ths_remove(struct platform_device *pdev) -+{ -+ struct ths_device *tmdev = platform_get_drvdata(pdev); -+ -+ clk_disable_unprepare(tmdev->mod_clk); -+ clk_disable_unprepare(tmdev->bus_clk); -+ reset_control_assert(tmdev->reset); -+ -+ return 0; -+} -+ -+static const struct ths_thermal_chip sun8i_a83t_ths = { -+ .sensor_num = 3, -+ .scale = 705, -+ .offset = 191668, -+ .temp_data_base = SUN8I_THS_TEMP_DATA, -+ .calibrate = sun8i_h3_ths_calibrate, -+ .init = sun8i_h3_thermal_init, -+ .irq_ack = sun8i_h3_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ -+static const struct ths_thermal_chip sun8i_h3_ths = { -+ .sensor_num = 1, -+ .scale = 1211, -+ .offset = 217000, -+ .has_mod_clk = true, -+ .has_bus_clk_reset = true, -+ .temp_data_base = SUN8I_THS_TEMP_DATA, -+ .calibrate = sun8i_h3_ths_calibrate, -+ .init = sun8i_h3_thermal_init, -+ .irq_ack = sun8i_h3_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ -+static const struct ths_thermal_chip sun8i_r40_ths = { -+ .sensor_num = 3, -+ .offset = 251086, -+ .scale = 1130, -+ .has_mod_clk = true, -+ .has_bus_clk_reset = true, -+ .temp_data_base = SUN8I_THS_TEMP_DATA, -+ .calibrate = sun8i_h3_ths_calibrate, -+ .init = sun8i_h3_thermal_init, -+ .irq_ack = sun8i_h3_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ -+static const struct ths_thermal_chip sun50i_a64_ths = { -+ .sensor_num = 3, -+ .offset = 260890, -+ .scale = 1170, -+ .has_mod_clk = true, -+ .has_bus_clk_reset = true, -+ .temp_data_base = SUN8I_THS_TEMP_DATA, -+ .calibrate = sun8i_h3_ths_calibrate, -+ .init = sun8i_h3_thermal_init, -+ .irq_ack = sun8i_h3_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ -+static const struct ths_thermal_chip sun50i_h5_ths = { -+ .sensor_num = 2, -+ .has_mod_clk = true, -+ .has_bus_clk_reset = true, -+ .temp_data_base = SUN8I_THS_TEMP_DATA, -+ .calibrate = sun8i_h3_ths_calibrate, -+ .init = sun8i_h3_thermal_init, -+ .irq_ack = sun8i_h3_irq_ack, -+ .calc_temp = sun50i_h5_calc_temp, -+}; -+ -+static const struct ths_thermal_chip sun50i_h6_ths = { -+ .sensor_num = 2, -+ .has_bus_clk_reset = true, -+ .ft_deviation = 7000, -+ .offset = 187744, -+ .scale = 672, -+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, -+ .calibrate = sun50i_h6_ths_calibrate, -+ .init = sun50i_h6_thermal_init, -+ .irq_ack = sun50i_h6_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ -+static const struct of_device_id of_ths_match[] = { -+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, -+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, -+ { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths }, -+ { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths }, -+ { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, -+ { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, -+ { /* sentinel */ }, -+}; -+MODULE_DEVICE_TABLE(of, of_ths_match); -+ -+static struct platform_driver ths_driver = { -+ .probe = sun8i_ths_probe, -+ .remove = sun8i_ths_remove, -+ .driver = { -+ .name = "sun8i-thermal", -+ .of_match_table = of_ths_match, -+ }, -+}; -+module_platform_driver(ths_driver); -+ -+MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SOC"); -+MODULE_LICENSE("GPL v2"); --- -2.24.1 - -From 59f5e9b9a802a177727017218dcf026dc390c37d Mon Sep 17 00:00:00 2001 -From: Vasily Khoruzhick -Date: Thu, 19 Dec 2019 09:28:23 -0800 -Subject: [PATCH] arm64: dts: allwinner: a64: Add thermal sensors and thermal - zones - -A64 has 3 thermal sensors: 1 for CPU, 2 for GPU. - -Signed-off-by: Vasily Khoruzhick -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 42 +++++++++++++++++++ - 1 file changed, 42 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index ab42c0664b3e..9a89324d02db 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - - / { - interrupt-parent = <&gic>; -@@ -172,6 +173,29 @@ timer { - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - -+ thermal-zones { -+ cpu_thermal: cpu0-thermal { -+ /* milliseconds */ -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 0>; -+ }; -+ -+ gpu0_thermal: gpu0-thermal { -+ /* milliseconds */ -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 1>; -+ }; -+ -+ gpu1_thermal: gpu1-thermal { -+ /* milliseconds */ -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 2>; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - #address-cells = <1>; -@@ -446,6 +470,12 @@ mmc2: mmc@1c11000 { - sid: eeprom@1c14000 { - compatible = "allwinner,sun50i-a64-sid"; - reg = <0x1c14000 0x400>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ ths_calibration: thermal-sensor-calibration@34 { -+ reg = <0x34 0x8>; -+ }; - }; - - crypto: crypto@1c15000 { -@@ -771,6 +801,18 @@ codec: codec@1c22e00 { - status = "disabled"; - }; - -+ ths: thermal-sensor@1c25000 { -+ compatible = "allwinner,sun50i-a64-ths"; -+ reg = <0x01c25000 0x100>; -+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; -+ clock-names = "bus", "mod"; -+ interrupts = ; -+ resets = <&ccu RST_BUS_THS>; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ #thermal-sensor-cells = <1>; -+ }; -+ - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; --- -2.24.1 - -From d7cfb661b206c0f9e66c9cdb3634f416c4283449 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Thu, 19 Dec 2019 09:28:22 -0800 -Subject: [PATCH] arm64: dts: allwinner: h6: Add thermal sensor and thermal - zones - -There are two sensors, one for CPU, one for GPU. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Vasily Khoruzhick -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 33 ++++++++++++++++++++ - 1 file changed, 33 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 6567dabbc0c7..3329283e38ab 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - / { - interrupt-parent = <&gic>; -@@ -241,6 +242,12 @@ dma: dma-controller@3002000 { - sid: efuse@3006000 { - compatible = "allwinner,sun50i-h6-sid"; - reg = <0x03006000 0x400>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ ths_calibration: thermal-sensor-calibration@14 { -+ reg = <0x14 0x8>; -+ }; - }; - - watchdog: watchdog@30090a0 { -@@ -874,5 +881,31 @@ r_i2c: i2c@7081400 { - #address-cells = <1>; - #size-cells = <0>; - }; -+ -+ ths: thermal-sensor@5070400 { -+ compatible = "allwinner,sun50i-h6-ths"; -+ reg = <0x05070400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_THS>; -+ clock-names = "bus"; -+ resets = <&ccu RST_BUS_THS>; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 0>; -+ }; -+ -+ gpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 1>; -+ }; - }; - }; --- -2.24.1 - -From fe67dfcb44c6477dbde6c897c7787bf20e2281a3 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 17 Nov 2019 13:52:50 +0100 -Subject: [PATCH] ARM: dts: sun8i: h3: Add rc map for Beelink X2 - -Beelink X2 box comes with a remote. Add a mapping for it. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -index ac9e26b1d906..45a24441ff18 100644 ---- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -@@ -143,6 +143,7 @@ hdmi_out_con: endpoint { - }; - - &ir { -+ linux,rc-map-name = "rc-tanix-tx3mini"; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; --- -2.24.1 - -From b37da9c8e62ef8ea14c19d40837dcd5beb8470e6 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Thu, 19 Dec 2019 09:28:20 -0800 -Subject: [PATCH] ARM: dts: sun8i-h3: Add thermal sensor and thermal zones - -There is just one sensor for the CPU. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Vasily Khoruzhick -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sun8i-h3.dtsi | 20 ++++++++++++++++++++ - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ++++++ - 2 files changed, 26 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi -index b4f1673df9ee..20217e2ca4d3 100644 ---- a/arch/arm/boot/dts/sun8i-h3.dtsi -+++ b/arch/arm/boot/dts/sun8i-h3.dtsi -@@ -208,6 +208,26 @@ mali: gpu@1c40000 { - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; -+ -+ ths: thermal-sensor@1c25000 { -+ compatible = "allwinner,sun8i-h3-ths"; -+ reg = <0x01c25000 0x400>; -+ interrupts = ; -+ resets = <&ccu RST_BUS_THS>; -+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; -+ clock-names = "bus", "mod"; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ #thermal-sensor-cells = <0>; -+ }; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 0>; -+ }; - }; - }; - -diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -index 0afea59486c2..6e68ed831015 100644 ---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi -+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -231,6 +231,12 @@ mmc2: mmc@1c11000 { - sid: eeprom@1c14000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x1c14000 0x400>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ ths_calibration: thermal-sensor-calibration@34 { -+ reg = <0x34 4>; -+ }; - }; - - usb_otg: usb@1c19000 { --- -2.24.1 - -From 624b4b48d9d870c2858c016d8709715495409654 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Tue, 29 Oct 2019 12:28:46 +0100 -Subject: [PATCH] drm: sun4i: Add support for suspending the display driver - -Shut down the display engine during suspend. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Maxime Ripard -Link: https://patchwork.freedesktop.org/patch/msgid/20191029112846.3604925-1-megous@megous.com ---- - drivers/gpu/drm/sun4i/sun4i_drv.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c -index a5757b11b730..5ae67d526b1d 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_drv.c -+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c -@@ -346,6 +346,27 @@ static int sun4i_drv_add_endpoints(struct device *dev, - return count; - } - -+#ifdef CONFIG_PM_SLEEP -+static int sun4i_drv_drm_sys_suspend(struct device *dev) -+{ -+ struct drm_device *drm = dev_get_drvdata(dev); -+ -+ return drm_mode_config_helper_suspend(drm); -+} -+ -+static int sun4i_drv_drm_sys_resume(struct device *dev) -+{ -+ struct drm_device *drm = dev_get_drvdata(dev); -+ -+ return drm_mode_config_helper_resume(drm); -+} -+#endif -+ -+static const struct dev_pm_ops sun4i_drv_drm_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(sun4i_drv_drm_sys_suspend, -+ sun4i_drv_drm_sys_resume) -+}; -+ - static int sun4i_drv_probe(struct platform_device *pdev) - { - struct component_match *match = NULL; -@@ -418,6 +439,7 @@ static struct platform_driver sun4i_drv_platform_driver = { - .driver = { - .name = "sun4i-drm", - .of_match_table = sun4i_drv_of_table, -+ .pm = &sun4i_drv_drm_pm_ops, - }, - }; - module_platform_driver(sun4i_drv_platform_driver); --- -2.24.1 - -From a7fe985633f927401037d2905df2c9701dff09a1 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 24 Nov 2019 18:29:03 +0100 -Subject: [PATCH 1/6] pwm: sun4i: Add an optional probe for reset line -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 PWM core needs deasserted reset line in order to work. - -Add an optional probe for it. - -Signed-off-by: Jernej Skrabec -Reviewed-by: Uwe Kleine-König -Signed-off-by: Clément Péron -Signed-off-by: Thierry Reding ---- - drivers/pwm/pwm-sun4i.c | 34 ++++++++++++++++++++++++++++++++-- - 1 file changed, 32 insertions(+), 2 deletions(-) - -diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c -index 581d23287333..487899d4cc3f 100644 ---- a/drivers/pwm/pwm-sun4i.c -+++ b/drivers/pwm/pwm-sun4i.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -78,6 +79,7 @@ struct sun4i_pwm_data { - struct sun4i_pwm_chip { - struct pwm_chip chip; - struct clk *clk; -+ struct reset_control *rst; - void __iomem *base; - spinlock_t ctrl_lock; - const struct sun4i_pwm_data *data; -@@ -364,6 +366,22 @@ static int sun4i_pwm_probe(struct platform_device *pdev) - if (IS_ERR(pwm->clk)) - return PTR_ERR(pwm->clk); - -+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); -+ if (IS_ERR(pwm->rst)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get reset failed %pe\n", -+ pwm->rst); -+ return PTR_ERR(pwm->rst); -+ } -+ -+ /* Deassert reset */ -+ ret = reset_control_deassert(pwm->rst); -+ if (ret) { -+ dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", -+ ERR_PTR(ret)); -+ return ret; -+ } -+ - pwm->chip.dev = &pdev->dev; - pwm->chip.ops = &sun4i_pwm_ops; - pwm->chip.base = -1; -@@ -376,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) - ret = pwmchip_add(&pwm->chip); - if (ret < 0) { - dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); -- return ret; -+ goto err_pwm_add; - } - - platform_set_drvdata(pdev, pwm); - - return 0; -+ -+err_pwm_add: -+ reset_control_assert(pwm->rst); -+ -+ return ret; - } - - static int sun4i_pwm_remove(struct platform_device *pdev) - { - struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); -+ int ret; -+ -+ ret = pwmchip_remove(&pwm->chip); -+ if (ret) -+ return ret; -+ -+ reset_control_assert(pwm->rst); - -- return pwmchip_remove(&pwm->chip); -+ return 0; - } - - static struct platform_driver sun4i_pwm_driver = { --- -2.24.1 - - -From b8d74644f34a82a6dcd5f45d5bd57e64f1db0d4d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sun, 24 Nov 2019 18:29:04 +0100 -Subject: [PATCH 2/6] pwm: sun4i: Prefer "mod" clock to unnamed -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -New device tree bindings called the source clock of the module -"mod" when several clocks are defined. - -Try to get a clock called "mod" if nothing is found try to get -an unnamed clock. - -Reviewed-by: Uwe Kleine-König -Signed-off-by: Clément Péron -Signed-off-by: Thierry Reding ---- - drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++-- - 1 file changed, 27 insertions(+), 2 deletions(-) - -diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c -index 487899d4cc3f..80026167044b 100644 ---- a/drivers/pwm/pwm-sun4i.c -+++ b/drivers/pwm/pwm-sun4i.c -@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev) - if (IS_ERR(pwm->base)) - return PTR_ERR(pwm->base); - -- pwm->clk = devm_clk_get(&pdev->dev, NULL); -- if (IS_ERR(pwm->clk)) -+ /* -+ * All hardware variants need a source clock that is divided and -+ * then feeds the counter that defines the output wave form. In the -+ * device tree this clock is either unnamed or called "mod". -+ * Some variants (e.g. H6) need another clock to access the -+ * hardware registers; this is called "bus". -+ * So we request "mod" first (and ignore the corner case that a -+ * parent provides a "mod" clock while the right one would be the -+ * unnamed one of the PWM device) and if this is not found we fall -+ * back to the first clock of the PWM. -+ */ -+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); -+ if (IS_ERR(pwm->clk)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get mod clock failed %pe\n", -+ pwm->clk); - return PTR_ERR(pwm->clk); -+ } -+ -+ if (!pwm->clk) { -+ pwm->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(pwm->clk)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n", -+ pwm->clk); -+ return PTR_ERR(pwm->clk); -+ } -+ } - - pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); - if (IS_ERR(pwm->rst)) { --- -2.24.1 - - -From 5b090b430d750961305030232314b6acdb0102aa Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 24 Nov 2019 18:29:05 +0100 -Subject: [PATCH 3/6] pwm: sun4i: Add an optional probe for bus clock -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 PWM core needs bus clock to be enabled in order to work. - -Add an optional probe for it. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Reviewed-by: Uwe Kleine-König -Signed-off-by: Thierry Reding ---- - drivers/pwm/pwm-sun4i.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c -index 80026167044b..a6727dd89e28 100644 ---- a/drivers/pwm/pwm-sun4i.c -+++ b/drivers/pwm/pwm-sun4i.c -@@ -78,6 +78,7 @@ struct sun4i_pwm_data { - - struct sun4i_pwm_chip { - struct pwm_chip chip; -+ struct clk *bus_clk; - struct clk *clk; - struct reset_control *rst; - void __iomem *base; -@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev) - } - } - -+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); -+ if (IS_ERR(pwm->bus_clk)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get bus clock failed %pe\n", -+ pwm->bus_clk); -+ return PTR_ERR(pwm->bus_clk); -+ } -+ - pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); - if (IS_ERR(pwm->rst)) { - if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -@@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev) - return ret; - } - -+ /* -+ * We're keeping the bus clock on for the sake of simplicity. -+ * Actually it only needs to be on for hardware register accesses. -+ */ -+ ret = clk_prepare_enable(pwm->bus_clk); -+ if (ret) { -+ dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", -+ ERR_PTR(ret)); -+ goto err_bus; -+ } -+ - pwm->chip.dev = &pdev->dev; - pwm->chip.ops = &sun4i_pwm_ops; - pwm->chip.base = -1; -@@ -427,6 +447,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) - return 0; - - err_pwm_add: -+ clk_disable_unprepare(pwm->bus_clk); -+err_bus: - reset_control_assert(pwm->rst); - - return ret; -@@ -441,6 +463,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev) - if (ret) - return ret; - -+ clk_disable_unprepare(pwm->bus_clk); - reset_control_assert(pwm->rst); - - return 0; --- -2.24.1 - - -From fa4d81784681a26bcf7d2a43c6ac5cf991ef28f5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sun, 24 Nov 2019 18:29:06 +0100 -Subject: [PATCH 4/6] pwm: sun4i: Always calculate params when applying new - parameters -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Bypass mode will require to be re-calculated when the pwm state -is changed. - -Remove the condition so pwm_sun4i_calculate is always called. - -Reviewed-by: Uwe Kleine-König -Signed-off-by: Clément Péron -Signed-off-by: Thierry Reding ---- - drivers/pwm/pwm-sun4i.c | 52 ++++++++++++++++++----------------------- - 1 file changed, 23 insertions(+), 29 deletions(-) - -diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c -index a6727dd89e28..e369b5a398f4 100644 ---- a/drivers/pwm/pwm-sun4i.c -+++ b/drivers/pwm/pwm-sun4i.c -@@ -202,9 +202,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - { - struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); - struct pwm_state cstate; -- u32 ctrl; -+ u32 ctrl, duty, period, val; - int ret; -- unsigned int delay_us; -+ unsigned int delay_us, prescaler; - unsigned long now; - - pwm_get_state(pwm, &cstate); -@@ -220,43 +220,37 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - spin_lock(&sun4i_pwm->ctrl_lock); - ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - -- if ((cstate.period != state->period) || -- (cstate.duty_cycle != state->duty_cycle)) { -- u32 period, duty, val; -- unsigned int prescaler; -- -- ret = sun4i_pwm_calculate(sun4i_pwm, state, -- &duty, &period, &prescaler); -- if (ret) { -- dev_err(chip->dev, "period exceeds the maximum value\n"); -- spin_unlock(&sun4i_pwm->ctrl_lock); -- if (!cstate.enabled) -- clk_disable_unprepare(sun4i_pwm->clk); -- return ret; -- } -- -- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { -- /* Prescaler changed, the clock has to be gated */ -- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); -+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler); -+ if (ret) { -+ dev_err(chip->dev, "period exceeds the maximum value\n"); -+ spin_unlock(&sun4i_pwm->ctrl_lock); -+ if (!cstate.enabled) -+ clk_disable_unprepare(sun4i_pwm->clk); -+ return ret; -+ } - -- ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); -- ctrl |= BIT_CH(prescaler, pwm->hwpwm); -- } -+ if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { -+ /* Prescaler changed, the clock has to be gated */ -+ ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - -- val = (duty & PWM_DTY_MASK) | PWM_PRD(period); -- sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); -- sun4i_pwm->next_period[pwm->hwpwm] = jiffies + -- usecs_to_jiffies(cstate.period / 1000 + 1); -- sun4i_pwm->needs_delay[pwm->hwpwm] = true; -+ ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); -+ ctrl |= BIT_CH(prescaler, pwm->hwpwm); - } - -+ val = (duty & PWM_DTY_MASK) | PWM_PRD(period); -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); -+ sun4i_pwm->next_period[pwm->hwpwm] = jiffies + -+ usecs_to_jiffies(cstate.period / 1000 + 1); -+ sun4i_pwm->needs_delay[pwm->hwpwm] = true; -+ - if (state->polarity != PWM_POLARITY_NORMAL) - ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); - else - ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); - - ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ - if (state->enabled) { - ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); - } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { --- -2.24.1 - - -From 9f28e95b5286fce63a3d0d90dc7ca43eca8dda58 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 24 Nov 2019 18:29:07 +0100 -Subject: [PATCH 5/6] pwm: sun4i: Add support to output source clock directly -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -PWM core has an option to bypass whole logic and output unchanged source -clock as PWM output. This is achieved by enabling bypass bit. - -Note that when bypass is enabled, no other setting has any meaning, not -even enable bit. - -This mode of operation is needed to achieve high enough frequency to -serve as clock source for AC200 chip which is integrated into same -package as H6 SoC. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Reviewed-by: Uwe Kleine-König -Signed-off-by: Thierry Reding ---- - drivers/pwm/pwm-sun4i.c | 48 +++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 46 insertions(+), 2 deletions(-) - -diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c -index e369b5a398f4..63aa9da92c22 100644 ---- a/drivers/pwm/pwm-sun4i.c -+++ b/drivers/pwm/pwm-sun4i.c -@@ -3,6 +3,10 @@ - * Driver for Allwinner sun4i Pulse Width Modulation Controller - * - * Copyright (C) 2014 Alexandre Belloni -+ * -+ * Limitations: -+ * - When outputing the source clock directly, the PWM logic will be bypassed -+ * and the currently running period is not guaranteed to be completed - */ - - #include -@@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { - - struct sun4i_pwm_data { - bool has_prescaler_bypass; -+ bool has_direct_mod_clk_output; - unsigned int npwm; - }; - -@@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, - - val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - -+ /* -+ * PWM chapter in H6 manual has a diagram which explains that if bypass -+ * bit is set, no other setting has any meaning. Even more, experiment -+ * proved that also enable bit is ignored in this case. -+ */ -+ if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && -+ sun4i_pwm->data->has_direct_mod_clk_output) { -+ state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); -+ state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); -+ state->polarity = PWM_POLARITY_NORMAL; -+ state->enabled = true; -+ return; -+ } -+ - if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && - sun4i_pwm->data->has_prescaler_bypass) - prescaler = 1; -@@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, - - static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, - const struct pwm_state *state, -- u32 *dty, u32 *prd, unsigned int *prsclr) -+ u32 *dty, u32 *prd, unsigned int *prsclr, -+ bool *bypass) - { - u64 clk_rate, div = 0; - unsigned int pval, prescaler = 0; - - clk_rate = clk_get_rate(sun4i_pwm->clk); - -+ *bypass = sun4i_pwm->data->has_direct_mod_clk_output && -+ state->enabled && -+ (state->period * clk_rate >= NSEC_PER_SEC) && -+ (state->period * clk_rate < 2 * NSEC_PER_SEC) && -+ (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); -+ -+ /* Skip calculation of other parameters if we bypass them */ -+ if (*bypass) -+ return 0; -+ - if (sun4i_pwm->data->has_prescaler_bypass) { - /* First, test without any prescaler when available */ - prescaler = PWM_PRESCAL_MASK; -@@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - int ret; - unsigned int delay_us, prescaler; - unsigned long now; -+ bool bypass; - - pwm_get_state(pwm, &cstate); - -@@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - spin_lock(&sun4i_pwm->ctrl_lock); - ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - -- ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler); -+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, -+ &bypass); - if (ret) { - dev_err(chip->dev, "period exceeds the maximum value\n"); - spin_unlock(&sun4i_pwm->ctrl_lock); -@@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - return ret; - } - -+ if (sun4i_pwm->data->has_direct_mod_clk_output) { -+ if (bypass) { -+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); -+ /* We can skip other parameter */ -+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); -+ spin_unlock(&sun4i_pwm->ctrl_lock); -+ return 0; -+ } -+ -+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); -+ } -+ - if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { - /* Prescaler changed, the clock has to be gated */ - ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); --- -2.24.1 - - -From fdd2c12e3761f0418596cd0e0156719a255d23c8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 24 Nov 2019 18:29:08 +0100 -Subject: [PATCH 6/6] pwm: sun4i: Add support for H6 PWM -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Now that sun4i PWM driver supports deasserting reset line and enabling -bus clock, support for H6 PWM can be added. - -Note that while H6 PWM has two channels, only first one is wired to -output pin. Second channel is used as a clock source to companion AC200 -chip which is bundled into same package. - -Signed-off-by: Jernej Skrabec -Acked-by: Uwe Kleine-König -Signed-off-by: Clément Péron -Signed-off-by: Thierry Reding ---- - drivers/pwm/pwm-sun4i.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c -index 63aa9da92c22..1afd41ebd3fd 100644 ---- a/drivers/pwm/pwm-sun4i.c -+++ b/drivers/pwm/pwm-sun4i.c -@@ -360,6 +360,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { - .npwm = 1, - }; - -+static const struct sun4i_pwm_data sun50i_h6_pwm_data = { -+ .has_prescaler_bypass = true, -+ .has_direct_mod_clk_output = true, -+ .npwm = 2, -+}; -+ - static const struct of_device_id sun4i_pwm_dt_ids[] = { - { - .compatible = "allwinner,sun4i-a10-pwm", -@@ -376,6 +382,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { - }, { - .compatible = "allwinner,sun8i-h3-pwm", - .data = &sun4i_pwm_single_bypass, -+ }, { -+ .compatible = "allwinner,sun50i-h6-pwm", -+ .data = &sun50i_h6_pwm_data, - }, { - /* sentinel */ - }, --- -2.24.1 - -From 7678c5462680c1aba8d07926ab4d8ee906fb98cf Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 13 Dec 2019 17:15:15 +0100 -Subject: [PATCH] media: cedrus: Fix decoding for some HEVC videos - -It seems that for some HEVC videos at least one bitstream parsing -trigger must be called in order to be decoded correctly. There is no -explanation why this helps, but it was observed that several videos -with this fix are now decoded correctly and there is no regression with -others. - -Without this fix, those same videos totally crash HEVC decoder (other -decoder engines are unaffected). After decoding those problematic -videos, HEVC decoder always returns only green image (all zeros). -Only complete HW reset helps. - -This fix is similar to that for H264. - -Signed-off-by: Jernej Skrabec -Acked-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/sunxi/cedrus/cedrus_h265.c | 25 ++++++++++++++++--- - .../staging/media/sunxi/cedrus/cedrus_regs.h | 1 + - 2 files changed, 23 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index 6945dc74e1d7..c17d30e74bb1 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -7,6 +7,7 @@ - * Copyright (C) 2018 Bootlin - */ - -+#include - #include - - #include -@@ -220,6 +221,23 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, - } - } - -+static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) -+{ -+ int count = 0; -+ -+ while (count < num) { -+ int tmp = min(num - count, 32); -+ -+ cedrus_write(dev, VE_DEC_H265_TRIGGER, -+ VE_DEC_H265_TRIGGER_FLUSH_BITS | -+ VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp)); -+ while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY) -+ udelay(1); -+ -+ count += tmp; -+ } -+} -+ - static void cedrus_h265_setup(struct cedrus_ctx *ctx, - struct cedrus_run *run) - { -@@ -280,10 +298,9 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, - - /* Source offset and length in bits. */ - -- reg = slice_params->data_bit_offset; -- cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, reg); -+ cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0); - -- reg = slice_params->bit_size - slice_params->data_bit_offset; -+ reg = slice_params->bit_size; - cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg); - - /* Source beginning and end addresses. */ -@@ -316,6 +333,8 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, - /* Initialize bitstream access. */ - cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); - -+ cedrus_h265_skip_bits(dev, slice_params->data_bit_offset); -+ - /* Bitstream parameters. */ - - reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) | -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index 7beb03d3bb39..66b152f18d17 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -424,6 +424,7 @@ - - #define VE_DEC_H265_TRIGGER (VE_ENGINE_DEC_H265 + 0x34) - -+#define VE_DEC_H265_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8) - #define VE_DEC_H265_TRIGGER_STCD_VC1 (0x02 << 4) - #define VE_DEC_H265_TRIGGER_STCD_AVS (0x01 << 4) - #define VE_DEC_H265_TRIGGER_STCD_HEVC (0x00 << 4) --- -2.24.1 - -From 7fcaed4ab4bc454757da266076f4b28fa93f54d1 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 13 Dec 2019 17:15:16 +0100 -Subject: [PATCH] media: cedrus: hevc: Add luma bit depth - -Add luma bit depth. - -Signed-off-by: Jernej Skrabec -Acked-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index c17d30e74bb1..ce497d0197df 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -351,6 +351,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, - VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | - VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | - VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | -+ VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) | - VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); - - reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE, --- -2.24.1 - -From 9ad42557109a9db9ca16964352c3c045a775b018 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Thu, 19 Dec 2019 09:28:21 -0800 -Subject: [PATCH] arm64: dts: allwinner: h5: Add thermal sensor and thermal - zones - -There are two sensors, one for CPU, one for GPU. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Vasily Khoruzhick -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 26 ++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi -index 3e724788dd3e..9893aa64dd0b 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi -@@ -147,6 +147,32 @@ mali: gpu@1e80000 { - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; -+ -+ ths: thermal-sensor@1c25000 { -+ compatible = "allwinner,sun50i-h5-ths"; -+ reg = <0x01c25000 0x400>; -+ interrupts = ; -+ resets = <&ccu RST_BUS_THS>; -+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; -+ clock-names = "bus", "mod"; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 0>; -+ }; -+ -+ gpu_thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 1>; -+ }; - }; - }; - --- -2.25.0 - diff --git a/projects/Allwinner/patches/linux/0002-backport-from-5.7.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.7.patch similarity index 100% rename from projects/Allwinner/patches/linux/0002-backport-from-5.7.patch rename to projects/Allwinner/patches/linux/0001-backport-from-5.7.patch diff --git a/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch index a76231d10e..8bc2106a74 100644 --- a/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch +++ b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch @@ -243,31 +243,29 @@ index 43643ad31730..d840bc07cba6 100644 .has_phy_clk = true, .is_custom_phy = true, .phy_init = &sun8i_hdmi_phy_init_h3, -@@ -711,10 +756,40 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) +@@ -711,10 +756,38 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) clk_prepare_enable(phy->clk_phy); } +#ifdef CONFIG_DRM_SUN8I_DW_HDMI_CEC + if (phy->variant->bit_bang_cec) { -+ phy->cec_notifier = cec_notifier_get(dev); -+ if (!phy->cec_notifier) { -+ ret = -ENOMEM; -+ goto err_disable_clk_phy; -+ } -+ + phy->cec_adapter = + cec_pin_allocate_adapter(&sun8i_hdmi_phy_cec_pin_ops, + phy, "sun8i-cec", + CEC_CAP_DEFAULTS); + ret = PTR_ERR_OR_ZERO(phy->cec_adapter); + if (ret < 0) -+ goto err_put_cec_notifier; ++ goto err_disable_clk_phy; ++ ++ phy->cec_notifier = cec_notifier_cec_adap_register(dev, NULL, phy->cec_adapter); ++ if (!phy->cec_notifier) { ++ ret = -ENOMEM; ++ goto err_delete_cec_adapter; ++ } + + ret = cec_register_adapter(phy->cec_adapter, dev); + if (ret < 0) -+ goto err_delete_cec_adapter; -+ -+ cec_register_cec_notifier(phy->cec_adapter, phy->cec_notifier); ++ goto err_put_cec_notifier; + } +#endif + @@ -275,22 +273,21 @@ index 43643ad31730..d840bc07cba6 100644 return 0; ++err_put_cec_notifier: ++ cec_notifier_cec_adap_unregister(phy->cec_notifier, phy->cec_adapter); +err_delete_cec_adapter: + cec_delete_adapter(phy->cec_adapter); -+err_put_cec_notifier: -+ cec_notifier_put(phy->cec_notifier); +err_disable_clk_phy: + clk_disable_unprepare(phy->clk_phy); err_disable_clk_mod: clk_disable_unprepare(phy->clk_mod); err_disable_clk_bus: -@@ -739,6 +814,10 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) +@@ -739,6 +814,9 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) { struct sun8i_hdmi_phy *phy = hdmi->phy; ++ cec_notifier_cec_adap_unregister(phy->cec_notifier, phy->cec_adapter); + cec_unregister_adapter(phy->cec_adapter); -+ if (phy->cec_notifier) -+ cec_notifier_put(phy->cec_notifier); + clk_disable_unprepare(phy->clk_mod); clk_disable_unprepare(phy->clk_bus);