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Intel: Backport drm/i915: Disable PSMI sleep messages on all rings around context switches
this drops the preliminary other gpu hang fixes
This commit is contained in:
fritsch
Stephan Raue
parent
4c41dd5830
commit
cd5f42c2ef
152
packages/linux/patches/3.17.7/linux-010-intel-fix-gpu-hang.patch
vendored
Normal file
152
packages/linux/patches/3.17.7/linux-010-intel-fix-gpu-hang.patch
vendored
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@ -0,0 +1,152 @@
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commit 0da5fe8cc74e6aec119ea0cc56f3e2cc92caccec
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Author: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Tue Dec 16 10:02:27 2014 +0000
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drm/i915: Disable PSMI sleep messages on all rings around context switches
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There exists a current workaround to prevent a hang on context switch
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should the ring go to sleep in the middle of the restore,
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WaProgramMiArbOnOffAroundMiSetContext (applicable to all gen7+). In
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spite of disabling arbitration (which prevents the ring from powering
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down during the critical section) we were still hitting hangs that had
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the hallmarks of the known erratum. That is we are still seeing hangs
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"on the last instruction in the context restore". By comparing -nightly
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(broken) with requests (working), we were able to deduce that it was the
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semaphore LRI cross-talk that reproduced the original failure. The key
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was that requests implemented deferred semaphore signalling, and
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disabling that, i.e. emitting the semaphore signal to every other ring
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after every batch restored the frequent hang. Explicitly disabling PSMI
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sleep on the RCS ring was insufficient, all the rings had to be awake to
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prevent the hangs. Fortunately, we can reduce the wakelock to the
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MI_SET_CONTEXT operation itself, and so should be able to limit the extra
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power implications.
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Since the MI_ARB_ON_OFF workaround is listed for all gen7 and above
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products, we should apply this extra hammer for all of the same
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platforms despite so far that we have only been able to reproduce the
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hang on certain ivb and hsw models. The last question is whether we want
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to always use the extra hammer or only when we know semaphores are in
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operation. At the moment, we only use LRI on non-RCS rings for
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semaphores, but that may change in the future with the possibility of
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reintroducing this bug under subtle conditions.
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v2: Make it explicit that the PSMI LRI are an extension to the original
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workaround for the other rings.
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v3: Bikeshedding variable names and whitespacing
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80660
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83677
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Cc: Simon Farnsworth <simon@farnz.org.uk>
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Cc: Daniel Vetter <daniel@ffwll.ch>
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Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Tested-by: Peter Frühberger <fritsch@xbmc.org>
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Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
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Cc: stable@vger.kernel.org
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Backported to 3.17:
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Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Conflicts:
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drivers/gpu/drm/i915/i915_gem_context.c
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diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
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index 3b99390..7f76ea2 100644
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--- a/drivers/gpu/drm/i915/i915_gem_context.c
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+++ b/drivers/gpu/drm/i915/i915_gem_context.c
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@@ -563,7 +563,12 @@ mi_set_context(struct intel_engine_cs *ring,
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struct intel_context *new_context,
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u32 hw_flags)
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{
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- int ret;
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+ const int num_rings =
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+ /* Use an extended w/a on ivb+ if signalling from other rings */
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+ i915_semaphore_is_enabled(ring->dev) ?
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+ hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
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+ 0;
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+ int len, i, ret;
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/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
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* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
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@@ -576,15 +581,30 @@ mi_set_context(struct intel_engine_cs *ring,
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return ret;
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}
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- ret = intel_ring_begin(ring, 6);
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+ len = 4;
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+ if (INTEL_INFO(ring->dev)->gen >= 7)
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+ len += 2 + (num_rings ? 4*num_rings + 2 : 0);
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+
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+ ret = intel_ring_begin(ring, len);
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if (ret)
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return ret;
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/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
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- if (INTEL_INFO(ring->dev)->gen >= 7)
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+ if (INTEL_INFO(ring->dev)->gen >= 7) {
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intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
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- else
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- intel_ring_emit(ring, MI_NOOP);
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+ if (num_rings) {
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+ struct intel_engine_cs *signaller;
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+
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+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
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+ for_each_ring(signaller, to_i915(ring->dev), i) {
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+ if (signaller == ring)
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+ continue;
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+
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+ intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
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+ intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
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+ }
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+ }
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+ }
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_emit(ring, MI_SET_CONTEXT);
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@@ -599,10 +619,21 @@ mi_set_context(struct intel_engine_cs *ring,
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*/
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intel_ring_emit(ring, MI_NOOP);
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- if (INTEL_INFO(ring->dev)->gen >= 7)
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+ if (INTEL_INFO(ring->dev)->gen >= 7) {
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+ if (num_rings) {
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+ struct intel_engine_cs *signaller;
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+
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+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
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+ for_each_ring(signaller, to_i915(ring->dev), i) {
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+ if (signaller == ring)
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+ continue;
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+
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+ intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
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+ intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
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+ }
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+ }
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intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
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- else
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- intel_ring_emit(ring, MI_NOOP);
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+ }
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intel_ring_advance(ring);
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index f29b44c..df02a15 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -1029,6 +1029,7 @@ enum punit_power_well {
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#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
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#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
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#define GEN6_NOSYNC 0
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+#define RING_PSMI_CTL(base) ((base)+0x50)
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#define RING_MAX_IDLE(base) ((base)+0x54)
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#define RING_HWS_PGA(base) ((base)+0x80)
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#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
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@@ -1354,6 +1355,7 @@ enum punit_power_well {
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#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
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#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
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+#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
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#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
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#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
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@ -1,32 +0,0 @@
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From aae8d9091ebefbb30c4e05f2c7d7c54c53a710e1 Mon Sep 17 00:00:00 2001
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From: root <root@localhost.localdomain>
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Date: Wed, 10 Dec 2014 13:46:30 +0000
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Subject: [PATCH 1/2] flush-flags
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---
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drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
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index 47a126a..fec60de 100644
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--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
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+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
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@@ -351,12 +351,15 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
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flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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+ flags |= 1 << 16;
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/*
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* TLB invalidate requires a post-sync write.
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*/
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flags |= PIPE_CONTROL_QW_WRITE;
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flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
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+ flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
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+
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/* Workaround: we must issue a pipe_control with CS-stall bit
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* set before a pipe_control command that has the state cache
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* invalidate bit set. */
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--
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1.9.1
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@ -1,88 +0,0 @@
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From 21feaa695380e86bc8e3301038374a3a65c05540 Mon Sep 17 00:00:00 2001
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From: root <root@localhost.localdomain>
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Date: Wed, 10 Dec 2014 13:47:00 +0000
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Subject: [PATCH 2/2] pmsi-ctl-around-ctx
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Conflicts:
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drivers/gpu/drm/i915/i915_gem_context.c
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---
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drivers/gpu/drm/i915/i915_gem_context.c | 25 +++++++++++++++++++++++--
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drivers/gpu/drm/i915/i915_reg.h | 2 ++
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2 files changed, 25 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
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index 3b99390..9567ba6 100644
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--- a/drivers/gpu/drm/i915/i915_gem_context.c
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+++ b/drivers/gpu/drm/i915/i915_gem_context.c
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@@ -563,7 +563,10 @@ mi_set_context(struct intel_engine_cs *ring,
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struct intel_context *new_context,
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u32 hw_flags)
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{
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- int ret;
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+ u32 flags = hw_flags | MI_MM_SPACE_GTT;
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+ struct intel_engine_cs *engine;
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+ int num_rings;
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+ int ret, i;
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/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
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* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
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@@ -576,10 +579,22 @@ mi_set_context(struct intel_engine_cs *ring,
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return ret;
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}
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- ret = intel_ring_begin(ring, 6);
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+ /* These flags are for resource streamer on HSW+ */
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+ if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)
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+ flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
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+
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+ num_rings = hweight32(INTEL_INFO(ring->dev)->ring_mask);
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+
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+ ret = intel_ring_begin(ring, 6 + 2*(num_rings*2 + 1));
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if (ret)
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return ret;
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+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
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+ for_each_ring(engine, to_i915(ring->dev), i) {
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+ intel_ring_emit(ring, RING_PSMI_CTL(engine->mmio_base));
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+ intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
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+ }
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+
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/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
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if (INTEL_INFO(ring->dev)->gen >= 7)
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intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
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@@ -604,6 +619,12 @@ mi_set_context(struct intel_engine_cs *ring,
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else
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intel_ring_emit(ring, MI_NOOP);
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+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
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+ for_each_ring(engine, to_i915(ring->dev), i) {
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+ intel_ring_emit(ring, RING_PSMI_CTL(engine->mmio_base));
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+ intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
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+ }
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+
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intel_ring_advance(ring);
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return ret;
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index f29b44c..df02a15 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -1029,6 +1029,7 @@ enum punit_power_well {
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#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
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#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
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#define GEN6_NOSYNC 0
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+#define RING_PSMI_CTL(base) ((base)+0x50)
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#define RING_MAX_IDLE(base) ((base)+0x54)
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#define RING_HWS_PGA(base) ((base)+0x80)
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#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
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@@ -1354,6 +1355,7 @@ enum punit_power_well {
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#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
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#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
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+#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
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#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
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#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
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--
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1.9.1
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