diff --git a/projects/Rockchip/patches/u-boot/0001-202301-arm-rockchip-rk3399-Program-PLL-clock-for-DDR-at-50-.patch b/projects/Rockchip/patches/u-boot/0001-202301-arm-rockchip-rk3399-Program-PLL-clock-for-DDR-at-50-.patch deleted file mode 100644 index 12e3907ecb..0000000000 --- a/projects/Rockchip/patches/u-boot/0001-202301-arm-rockchip-rk3399-Program-PLL-clock-for-DDR-at-50-.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 2cb23b80e4169e121c520ff33cb6a60e0a0ded21 Mon Sep 17 00:00:00 2001 -From: Xavier Drudis Ferran -Date: Sat, 16 Jul 2022 12:31:45 +0200 -Subject: [PATCH] arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in - documented range -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The original code set up the DDR clock to 48 MHz, not 50MHz as -requested, and did it in a way that didn't satisfy the Application -Notes in RK3399 TRM [1]. 2.9.2.B says: - - PLL frequency range requirement - [...] - FOUTVCO: 800MHz to 3.2GHz - -2.9.2.A : - PLL output frequency configuration - [...] - FOUTVCO = FREF / REFDIV * FBDIV - FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 - -FREF = 24 MHz - -The original code gives FOUTVCO: 24MHz/1 * 12 = 288MHz < 800MHz -And the resulting FOUTPOSTDIV is 288MHz / 3 / 2 = 48MHz -but the requested frequency was 50MHz - -Note: -2.7.2 Detail Register Description -PMUCRU_PPLL_CON0 says - - fbdiv - Feedback Divide Value - Valid divider settings are: - [16, 3200] in integer mode - -So .fbdiv = 12 wouldn't be right. But 2.9.2.C says: - - PLL setting consideration - [...] - The following settings are valid for FBDIV: - DSMPD=1 (Integer Mode): - 12,13,14,16-4095 (practical value is limited to 3200, 2400, or 1600 - (FVCOMAX / FREFMIN)) - [...] - -So .fbdiv = 12 would be right. - -In any case FOUTVCO is still wrong. I thank YouMin Chen for -confirmation and explanation. - -Despite documentation, I don't seem to be able to reproduce a -practical problem with the wrong FOUTVCO. When I initially found it I -thought some problems with detecting the RAM capacity in my Rock Pi 4B -could be related to it and my patch seemed to help. But since I'm no -longer able to reproduce the issue, it works with or without this -patch. And meanwhile a patch[2] by Lee Jones and YouMin Chen addresses -this issue. Btw, shouldn't that be commited? - -So this patches solves no visible problem. Yet, to prevent future -problems, I think it'd be best to stick to spec. - -An alternative to this patch could be - - {.refdiv = 1, .fbdiv = 75, .postdiv1 = 6, .postdiv2 = 6}; - -This would theoretically consume more power and yield less jitter, -according to 2.9.2.C : - - PLL setting consideration - [...] - For lowest power operation, the minimum VCO and FREF frequencies - should be used. For minimum jitter operation, the highest VCO and - FREF frequencies should be used. - [...] - -But I haven't tried it because I don't think it matters much. 50MHz -for DDR is only shortly used by TPL at RAM init. Normal operation is -at 800MHz. Maybe it's better to use less power until later when more -complex software can control batteries or charging or whatever ? - -Cc: Simon Glass -Cc: Philipp Tomsich -Cc: Kever Yang -Cc: Lukasz Majewski -Cc: Sean Anderson - -Link: [1] https://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf -Link: [2] https://patchwork.ozlabs.org/project/uboot/list/?series=305766 - -Signed-off-by: Xavier Drudis Ferran -Tested-by: Michal Suchánek -Reviewed-by: Kever Yang ---- - drivers/clk/rockchip/clk_rk3399.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c -index 97bf1c6e15..eaeac451df 100644 ---- a/drivers/clk/rockchip/clk_rk3399.c -+++ b/drivers/clk/rockchip/clk_rk3399.c -@@ -856,7 +856,7 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, - switch (set_rate) { - case 50 * MHz: - dpll_cfg = (struct pll_div) -- {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2}; -+ {.refdiv = 2, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 6}; - break; - case 200 * MHz: - dpll_cfg = (struct pll_div) --- -2.39.0 - diff --git a/projects/Rockchip/patches/u-boot/0001-rockchip-efuse-add-support-for-RK322x-non-secure-efu.patch b/projects/Rockchip/patches/u-boot/0001-rockchip-efuse-add-support-for-RK322x-non-secure-efu.patch deleted file mode 100644 index b7c5e57993..0000000000 --- a/projects/Rockchip/patches/u-boot/0001-rockchip-efuse-add-support-for-RK322x-non-secure-efu.patch +++ /dev/null @@ -1,150 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Francis Fan -Date: Tue, 7 Nov 2017 17:50:11 +0800 -Subject: [PATCH 1/6] rockchip: efuse: add support for RK322x non-secure efuse - block - -Signed-off-by: Francis Fan -Signed-off-by: Cody Xie ---- - drivers/misc/rockchip-efuse.c | 96 +++++++++++++++++++++++++++++++++-- - 1 file changed, 92 insertions(+), 4 deletions(-) - -diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c -index 083ee65e0a..4c9239f7ba 100644 ---- a/drivers/misc/rockchip-efuse.c -+++ b/drivers/misc/rockchip-efuse.c -@@ -27,6 +27,17 @@ - #define RK3399_STROBE BIT(1) - #define RK3399_CSB BIT(0) - -+#define RK3288_A_SHIFT 6 -+#define RK3288_A_MASK 0x3ff -+#define RK3288_NFUSES 32 -+#define RK3288_BYTES_PER_FUSE 1 -+#define RK3288_PGENB BIT(3) -+#define RK3288_LOAD BIT(2) -+#define RK3288_STROBE BIT(1) -+#define RK3288_CSB BIT(0) -+ -+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size); -+ - struct rockchip_efuse_regs { - u32 ctrl; /* 0x00 efuse control register */ - u32 dout; /* 0x04 efuse data out register */ -@@ -53,7 +64,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, - */ - - struct udevice *dev; -- u8 fuses[128]; -+ u8 fuses[128] = {0}; - int ret; - - /* retrieve the device */ -@@ -77,7 +88,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, - } - - U_BOOT_CMD( -- rk3399_dump_efuses, 1, 1, dump_efuses, -+ rockchip_dump_efuses, 1, 1, dump_efuses, - "Dump the content of the efuses", - "" - ); -@@ -127,10 +138,59 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset, - return 0; - } - -+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, -+ void *buf, int size) -+{ -+ struct rockchip_efuse_plat *plat = dev_get_plat(dev); -+ struct rockchip_efuse_regs *efuse = -+ (struct rockchip_efuse_regs *)plat->base; -+ u8 *buffer = buf; -+ int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE; -+ -+ if (size > (max_size - offset)) -+ size = max_size - offset; -+ -+ /* Switch to read mode */ -+ writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl); -+ udelay(1); -+ -+ while (size--) { -+ writel(readl(&efuse->ctrl) & -+ (~(RK3288_A_MASK << RK3288_A_SHIFT)), -+ &efuse->ctrl); -+ /* set addr */ -+ writel(readl(&efuse->ctrl) | -+ ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT), -+ &efuse->ctrl); -+ udelay(1); -+ /* strobe low to high */ -+ writel(readl(&efuse->ctrl) | -+ RK3288_STROBE, &efuse->ctrl); -+ ndelay(60); -+ /* read data */ -+ *buffer++ = readl(&efuse->dout); -+ /* reset strobe to low */ -+ writel(readl(&efuse->ctrl) & -+ (~RK3288_STROBE), &efuse->ctrl); -+ udelay(1); -+ } -+ -+ /* Switch to standby mode */ -+ writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl); -+ -+ return 0; -+} -+ - static int rockchip_efuse_read(struct udevice *dev, int offset, - void *buf, int size) - { -- return rockchip_rk3399_efuse_read(dev, offset, buf, size); -+ EFUSE_READ efuse_read = NULL; -+ -+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev); -+ if (!efuse_read) -+ return -ENOSYS; -+ -+ return (*efuse_read)(dev, offset, buf, size); - } - - static const struct misc_ops rockchip_efuse_ops = { -@@ -146,7 +206,35 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev) - } - - static const struct udevice_id rockchip_efuse_ids[] = { -- { .compatible = "rockchip,rk3399-efuse" }, -+ /* deprecated but kept around for dts binding compatibility */ -+ { -+ .compatible = "rockchip,rockchip-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3066a-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3188-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3228-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3288-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3368-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3399-efuse", -+ .data = (ulong)&rockchip_rk3399_efuse_read, -+ }, - {} - }; - diff --git a/projects/Rockchip/patches/u-boot/0002-rockchip-efuse-add-support-for-RK3328-non-secure-efu.patch b/projects/Rockchip/patches/u-boot/0002-rockchip-efuse-add-support-for-RK3328-non-secure-efu.patch deleted file mode 100644 index 62d190d8ce..0000000000 --- a/projects/Rockchip/patches/u-boot/0002-rockchip-efuse-add-support-for-RK3328-non-secure-efu.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Joseph Chen -Date: Thu, 2 Aug 2018 20:33:16 +0800 -Subject: [PATCH 2/6] rockchip: efuse: add support for RK3328 non-secure efuse - block - -Signed-off-by: Joseph Chen ---- - drivers/misc/rockchip-efuse.c | 67 +++++++++++++++++++++++++++++++++++ - 1 file changed, 67 insertions(+) - -diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c -index 4c9239f7ba..c75405bfcf 100644 ---- a/drivers/misc/rockchip-efuse.c -+++ b/drivers/misc/rockchip-efuse.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - - #define RK3399_A_SHIFT 16 -@@ -36,6 +37,13 @@ - #define RK3288_STROBE BIT(1) - #define RK3288_CSB BIT(0) - -+#define RK3328_INT_STATUS 0x0018 -+#define RK3328_DOUT 0x0020 -+#define RK3328_AUTO_CTRL 0x0024 -+#define RK3328_INT_FINISH BIT(0) -+#define RK3328_AUTO_ENB BIT(0) -+#define RK3328_AUTO_RD BIT(1) -+ - typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size); - - struct rockchip_efuse_regs { -@@ -46,6 +54,10 @@ struct rockchip_efuse_regs { - u32 jtag_pass; /* 0x10 JTAG password */ - u32 strobe_finish_ctrl; - /* 0x14 efuse strobe finish control register */ -+ u32 int_status;/* 0x18 */ -+ u32 reserved; /* 0x1c */ -+ u32 dout2; /* 0x20 */ -+ u32 auto_ctrl; /* 0x24 */ - }; - - struct rockchip_efuse_plat { -@@ -181,6 +193,57 @@ static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, - return 0; - } - -+static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset, -+ void *buf, int size) -+{ -+ struct rockchip_efuse_plat *plat = dev_get_plat(dev); -+ struct rockchip_efuse_regs *efuse = -+ (struct rockchip_efuse_regs *)plat->base; -+ unsigned int addr_start, addr_end, addr_offset, addr_len; -+ u32 out_value, status; -+ u8 *buffer; -+ int ret = 0, i = 0, j = 0; -+ -+ /* Max non-secure Byte */ -+ if (size > 32) -+ size = 32; -+ -+ /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */ -+ offset += 96; -+ addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) / -+ RK3399_BYTES_PER_FUSE; -+ addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) / -+ RK3399_BYTES_PER_FUSE; -+ addr_offset = offset % RK3399_BYTES_PER_FUSE; -+ addr_len = addr_end - addr_start; -+ -+ buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE); -+ if (!buffer) -+ return -ENOMEM; -+ -+ for (j = 0; j < addr_len; j++) { -+ writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | -+ ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), -+ &efuse->auto_ctrl); -+ udelay(5); -+ status = readl(&efuse->int_status); -+ if (!(status & RK3328_INT_FINISH)) { -+ ret = -EIO; -+ goto err; -+ } -+ out_value = readl(&efuse->dout2); -+ writel(RK3328_INT_FINISH, &efuse->int_status); -+ -+ memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE); -+ i += RK3399_BYTES_PER_FUSE; -+ } -+ memcpy(buf, buffer + addr_offset, size); -+err: -+ free(buffer); -+ -+ return ret; -+} -+ - static int rockchip_efuse_read(struct udevice *dev, int offset, - void *buf, int size) - { -@@ -231,6 +294,10 @@ static const struct udevice_id rockchip_efuse_ids[] = { - .compatible = "rockchip,rk3368-efuse", - .data = (ulong)&rockchip_rk3288_efuse_read, - }, -+ { -+ .compatible = "rockchip,rk3328-efuse", -+ .data = (ulong)&rockchip_rk3328_efuse_read, -+ }, - { - .compatible = "rockchip,rk3399-efuse", - .data = (ulong)&rockchip_rk3399_efuse_read, diff --git a/projects/Rockchip/patches/u-boot/0003-arm-dts-enable-efuse-for-RK3288.patch b/projects/Rockchip/patches/u-boot/0003-arm-dts-enable-efuse-for-RK3288.patch deleted file mode 100644 index 61dee23e84..0000000000 --- a/projects/Rockchip/patches/u-boot/0003-arm-dts-enable-efuse-for-RK3288.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 11 Sep 2022 10:56:43 +0200 -Subject: [PATCH 3/6] arm: dts: update efuse for RK3288 for 0x20 - ---- - arch/arm/dts/rk3288.dtsi | 3 +- - 1 file changed, 1 insertion(+), 1 deletions(-) - -diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi -index 53ee760b98..f923630f63 100644 ---- a/arch/arm/dts/rk3288.dtsi -+++ b/arch/arm/dts/rk3288.dtsi -@@ -1214,7 +1214,7 @@ - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; -- reg = <0xffb40000 0x10000>; -+ reg = <0xffb40000 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>;