From 911422d08e32d66e9dfe128bd2114fb5f47de9b9 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Mon, 31 Oct 2022 11:08:11 +0100 Subject: [PATCH 1/4] Rockchip: linux: fixup and squash drm patches for dual screen usage --- .../linux-0001-rockchip-from-6.1.patch | 18 +- .../default/linux-0011-v4l2-from-list.patch | 8 +- .../default/linux-1000-drm-rockchip.patch | 692 ++++++------------ .../default/linux-1001-v4l2-rockchip.patch | 1 - .../default/linux-1002-for-libreelec.patch | 1 + .../linux-2000-v4l2-wip-rkvdec-hevc.patch | 6 +- 6 files changed, 254 insertions(+), 472 deletions(-) diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch index c8558662e1..e5a757b059 100644 --- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch +++ b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch @@ -20,7 +20,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -index 02d5f5a8ca03..3897980d69d1 100644 +index 528bb4e8ac77..c8315d703ad0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -42,6 +42,21 @@ led-user { @@ -98,7 +98,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 6b5093a1a6cf..a848a2a2ab68 100644 +index b2e040dffb59..169d4b1d0a34 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -131,6 +131,22 @@ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { @@ -155,7 +155,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index a848a2a2ab68..e883afa83617 100644 +index 169d4b1d0a34..f0f96c72ec51 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -147,6 +147,22 @@ regulator-state-mem { @@ -215,7 +215,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index e883afa83617..cd8cc0c3c68a 100644 +index f0f96c72ec51..52a437f48301 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -472,6 +472,18 @@ codec { @@ -404,7 +404,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index 5e34bd0b214d..7a8d55a898f5 100644 +index 93d383b8be87..bc34061a421e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -86,6 +86,66 @@ vcc5v0_sys: vcc5v0-sys { @@ -3287,7 +3287,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index 7a8d55a898f5..950613595f42 100644 +index bc34061a421e..c282f6e79960 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -46,7 +46,7 @@ green_led: led-1 { @@ -4533,7 +4533,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts -index 3897980d69d1..1f709e5d8a87 100644 +index c8315d703ad0..0f623198970f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -69,6 +69,18 @@ sdio_pwrseq: sdio-pwrseq { @@ -4615,7 +4615,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index cd8cc0c3c68a..037a2c3b1602 100644 +index 52a437f48301..28a1db4958c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -484,6 +484,23 @@ &i2c4 { @@ -4673,7 +4673,7 @@ Signed-off-by: Heiko Stuebner 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 037a2c3b1602..e35f6ce812bd 100644 +index 28a1db4958c7..fb87a168fe96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -67,6 +67,18 @@ vcc12v_dcin: vcc12v-dcin { diff --git a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch index c64009b7a7..7c4afd72e9 100644 --- a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch @@ -168,7 +168,7 @@ index cb2f1acab7cf..8446a1deffd8 100644 { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index c314025d977e..298cb762b8d5 100644 +index e6fd355a2e92..24771edaa4f2 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) @@ -212,7 +212,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 4af5a831bde0..5590abfaa44d 100644 +index 4fc167b42cf0..a8635105e387 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx, @@ -487,7 +487,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 5590abfaa44d..09cab1e53377 100644 +index a8635105e387..0069d3d198db 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, @@ -624,7 +624,7 @@ Signed-off-by: Alex Bee 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 09cab1e53377..6536c123a243 100644 +index 0069d3d198db..2c27acaba85e 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, diff --git a/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch index ffd04f6941..5bbdaabb75 100644 --- a/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch @@ -42,12 +42,13 @@ from the requested pixel clock. This filter is only applied to tmds only connector and/or encoders. Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index dbe4d411b30f..8711d810b48a 100644 +index dbe4d411b30f..fac23d370ee0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1206,6 +1206,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) @@ -70,10 +71,10 @@ index dbe4d411b30f..8711d810b48a 100644 + } + + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) -+ if (encoder->encoder_type != DRM_MODE_ENCODER_TMDS) -+ return false; ++ if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) ++ return true; + -+ return true; ++ return false; +} + +/* @@ -133,7 +134,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 8711d810b48a..ec6983494f05 100644 +index fac23d370ee0..9f7326c5b1f5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1244,6 +1244,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, @@ -268,49 +269,85 @@ Subject: [PATCH] drm/rockchip: vop: filter modes above max output supported Filter any mode with a resolution not supported by the VOP. Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 48 +++++++++++++++------ + 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index ec6983494f05..a1a470a91169 100644 +index 9f7326c5b1f5..30e252ba7184 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1238,6 +1238,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, - const struct drm_display_mode *mode) - { - struct vop *vop = to_vop(crtc); +@@ -1228,6 +1228,24 @@ static bool vop_crtc_is_tmds(struct drm_crtc *crtc) + return false; + } + ++static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode) ++{ ++ struct vop *vop = to_vop(crtc); + const struct vop_rect *max_output = &vop->data->max_output; ++ ++ if (max_output->width && max_output->height) { ++ /* only the size of the resulting rect matters */ ++ if(drm_mode_validate_size(mode, max_output->width, ++ max_output->height) != MODE_OK) { ++ return drm_mode_validate_size(mode, max_output->height, ++ max_output->width); ++ } ++ } ++ ++ return MODE_OK; ++} ++ + /* + * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance. + * The CVT spec reuses that tolerance in its examples. +@@ -1241,25 +1259,24 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, long rounded_rate; long lowest, highest; -@@ -1259,6 +1260,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, - if (rounded_rate > highest) - return MODE_CLOCK_HIGH; +- if (!vop_crtc_is_tmds(crtc)) +- return MODE_OK; +- + if (mode->flags & DRM_MODE_FLAG_INTERLACE) +- return MODE_NO_INTERLACE; ++ return MODE_NO_INTERLACE; -+ if (max_output->width && max_output->height) -+ return drm_mode_validate_size(mode, max_output->width, -+ max_output->height); -+ - return MODE_OK; +- rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); +- if (rounded_rate < 0) +- return MODE_NOCLOCK; ++ if (vop_crtc_is_tmds(crtc)) { ++ rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999); ++ if (rounded_rate < 0) ++ return MODE_NOCLOCK; + +- lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); +- if (rounded_rate < lowest) +- return MODE_CLOCK_LOW; ++ lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate < lowest) ++ return MODE_CLOCK_LOW; + +- highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); +- if (rounded_rate > highest) +- return MODE_CLOCK_HIGH; ++ highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE); ++ if (rounded_rate > highest) ++ return MODE_CLOCK_HIGH; ++ } + +- return MODE_OK; ++ return vop_crtc_size_valid(crtc, mode); } -@@ -1267,8 +1272,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, - struct drm_display_mode *adjusted_mode) - { + static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1269,6 +1286,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, struct vop *vop = to_vop(crtc); -+ const struct vop_rect *max_output = &vop->data->max_output; unsigned long rate; -+ if (max_output->width && max_output->height) { -+ enum drm_mode_status status; -+ -+ status = drm_mode_validate_size(adjusted_mode, -+ max_output->width, -+ max_output->height); -+ if (status != MODE_OK) -+ return false; -+ } ++ if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK) ++ return false; + /* * Clock craziness. @@ -673,30 +710,6 @@ index 0370bb247fcb..55c0b8dddad5 100644 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 3 May 2020 22:36:23 +0000 -Subject: [PATCH] drm/rockchip: dw-hdmi: limit resolution to 3840x2160 - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 55c0b8dddad5..dadd2f6ef39a 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -246,7 +246,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - (info->max_tmds_clock && mode->clock > info->max_tmds_clock)) - return MODE_CLOCK_HIGH; - -- return MODE_OK; -+ return drm_mode_validate_size(mode, 3840, 2160); - } - - static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 8 Jan 2020 21:07:49 +0000 @@ -710,7 +723,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index dadd2f6ef39a..62fbeaecbc92 100644 +index 55c0b8dddad5..15ecb257b902 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -327,6 +327,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, @@ -738,7 +751,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 62fbeaecbc92..a4583fa1643e 100644 +index 15ecb257b902..38dded2baaf7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -417,9 +417,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { @@ -773,7 +786,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a4583fa1643e..1bac3c741ee2 100644 +index 38dded2baaf7..9e460b7e14a4 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -558,7 +558,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, @@ -936,7 +949,7 @@ Signed-off-by: Jonas Karlman 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 25a60eb4d67c..64792b597833 100644 +index 40d8ca37f5bc..22af42a08980 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -138,7 +138,8 @@ struct dw_hdmi_phy_data { @@ -1013,7 +1026,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 64792b597833..02b954e92180 100644 +index 22af42a08980..7fd45a7006b1 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1592,6 +1592,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, @@ -1072,7 +1085,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 02b954e92180..6345c0759473 100644 +index 7fd45a7006b1..a2d101ebf7a7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1594,7 +1594,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, @@ -1110,7 +1123,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 1bac3c741ee2..1bf68ddc124c 100644 +index 9e460b7e14a4..d42ac9fa3246 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -242,8 +242,15 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -1130,7 +1143,7 @@ index 1bac3c741ee2..1bf68ddc124c 100644 + (info->max_tmds_clock && clock > info->max_tmds_clock)) return MODE_CLOCK_HIGH; - return drm_mode_validate_size(mode, 3840, 2160); + return MODE_OK; @@ -531,6 +538,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return -ENOMEM; @@ -1151,7 +1164,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 1bf68ddc124c..454c7bba0969 100644 +index d42ac9fa3246..a37565649c13 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -177,6 +177,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { @@ -1222,7 +1235,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 454c7bba0969..cb8b2135ddf0 100644 +index a37565649c13..66fee351f4a7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -217,6 +217,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { @@ -1299,7 +1312,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 81 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cb8b2135ddf0..4d64305e409b 100644 +index 66fee351f4a7..d6d8f3335813 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -5,6 +5,7 @@ @@ -1334,7 +1347,7 @@ index cb8b2135ddf0..4d64305e409b 100644 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { @@ -335,31 +335,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - return drm_mode_validate_size(mode, 3840, 2160); + return MODE_OK; } - -static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) @@ -1536,10 +1549,10 @@ index 092bf863110b..e2ee0d6a8d55 100644 dev->mode_config.helper_private = &rockchip_mode_config_helpers; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index a1a470a91169..2792c7d27bec 100644 +index 30e252ba7184..897f7980ee5d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1913,7 +1913,7 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1917,7 +1917,7 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1548,7 +1561,7 @@ index a1a470a91169..2792c7d27bec 100644 const struct vop_win_data *win_data) { unsigned int flags = 0; -@@ -1923,6 +1923,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, +@@ -1927,6 +1927,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, if (flags) drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | flags); @@ -1557,7 +1570,7 @@ index a1a470a91169..2792c7d27bec 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1963,7 +1965,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1967,7 +1969,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1578,10 +1591,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 2792c7d27bec..1529d5fbc7c7 100644 +index 897f7980ee5d..eadf1b0f1704 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1913,8 +1913,23 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1917,8 +1917,23 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1606,7 +1619,7 @@ index 2792c7d27bec..1529d5fbc7c7 100644 { unsigned int flags = 0; -@@ -1925,6 +1940,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, +@@ -1929,6 +1944,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, DRM_MODE_ROTATE_0 | flags); drm_plane_create_zpos_immutable_property(plane, zpos); @@ -1626,7 +1639,7 @@ index 2792c7d27bec..1529d5fbc7c7 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1965,7 +1993,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1969,7 +1997,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1646,10 +1659,11 @@ MINIARM: set npll be used for hdmi only Signed-off-by: Nickey Yang Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- arch/arm/boot/dts/rk3288.dtsi | 2 ++ - drivers/clk/rockchip/clk-rk3288.c | 4 ++-- - 2 files changed, 4 insertions(+), 2 deletions(-) + drivers/clk/rockchip/clk-rk3288.c | 9 +++++---- + 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index c60eacab8a79..d1ae42757242 100644 @@ -1665,10 +1679,22 @@ index c60eacab8a79..d1ae42757242 100644 vopb_out: port { diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index baa5aebd3277..20a3cdbbe909 100644 +index baa5aebd3277..5cfcbaaa154e 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -232,7 +232,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -195,8 +195,9 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; + PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; + + PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; +-PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; +-PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; ++PNAME(mux_pll_src_npll_cpll_gpll_p) = { "prevent:npll", "cpll", "gpll" }; ++PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "prevent:npll" }; ++PNAME(vop0_mux_pll_src_cpll_gpll_npll_p) = { "prevent:cpll", "prevent:gpll", "npll" }; + PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; + PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; + +@@ -232,7 +233,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1677,12 +1703,12 @@ index baa5aebd3277..20a3cdbbe909 100644 }; static struct clk_div_table div_hclk_cpu_t[] = { -@@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { +@@ -442,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 4, GFLAGS), - COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, -+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, ++ COMPOSITE(DCLK_VOP0, "dclk_vop0", vop0_mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, RK3288_CLKGATE_CON(3), 1, GFLAGS), COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, @@ -1696,43 +1722,60 @@ Subject: [PATCH] HACK: clk: rockchip: rk3288: use npll table to to improve Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3 Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- - drivers/clk/rockchip/clk-rk3288.c | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) + drivers/clk/rockchip/clk-rk3288.c | 39 ++++++++++++++++++++++++++++++- + 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 20a3cdbbe909..47a2527fd238 100644 +index 5cfcbaaa154e..fa1c6e646bdf 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -121,6 +121,27 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { +@@ -121,6 +121,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { { /* sentinel */ }, }; +static struct rockchip_pll_rate_table rk3288_npll_rates[] = { -+ RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32), ++ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), + RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), + RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), + RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), + RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), ++ RK3066_PLL_RATE(348500000, 8, 697, 6), + RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), + RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), + RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), + RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), ++ RK3066_PLL_RATE(241500000, 2, 161, 8), ++ RK3066_PLL_RATE(162000000, 1, 81, 12), ++ RK3066_PLL_RATE(154000000, 6, 539, 14), + RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), + RK3066_PLL_RATE(148352000, 13, 1125, 14), + RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), ++ RK3066_PLL_RATE(121750000, 6, 487, 16), ++ RK3066_PLL_RATE(119000000, 3, 238, 16), + RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), + RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), ++ RK3066_PLL_RATE(101000000, 3, 202, 16), ++ RK3066_PLL_RATE(88750000, 6, 355, 16), + RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), ++ RK3066_PLL_RATE(83500000, 3, 167, 16), ++ RK3066_PLL_RATE(79500000, 1, 53, 16), + RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), + RK3066_PLL_RATE(74176000, 26, 1125, 14), ++ RK3066_PLL_RATE(72000000, 1, 48, 16), ++ RK3066_PLL_RATE(71000000, 3, 142, 16), ++ RK3066_PLL_RATE(68250000, 2, 91, 16), ++ RK3066_PLL_RATE(65000000, 3, 130, 16), ++ RK3066_PLL_RATE(40000000, 3, 80, 16), ++ RK3066_PLL_RATE(33750000, 2, 45, 16), + { /* sentinel */ }, +}; + #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf -@@ -232,7 +253,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -233,7 +270,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1742,100 +1785,72 @@ index 20a3cdbbe909..47a2527fd238 100644 static struct clk_div_table div_hclk_cpu_t[] = { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 28 Oct 2018 21:43:01 +0100 -Subject: [PATCH] HACK: clk: rockchip: rk3288: add more npll clocks - -Fixes 2560x1440@60Hz, 1600x1200@60Hz, 1920x1200@60Hz, 1680x1050@60Hz and 1440x900@60Hz modes on my monitor - -Signed-off-by: Jonas Karlman ---- - drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 47a2527fd238..233890555616 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -127,18 +127,34 @@ static struct rockchip_pll_rate_table rk3288_npll_rates[] = { - RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), - RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), - RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), -+ RK3066_PLL_RATE(348500000, 8, 697, 6), - RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), - RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), - RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), - RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), -+ RK3066_PLL_RATE(241500000, 2, 161, 8), -+ RK3066_PLL_RATE(162000000, 1, 81, 12), -+ RK3066_PLL_RATE(154000000, 6, 539, 14), - RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), - RK3066_PLL_RATE(148352000, 13, 1125, 14), - RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), -+ RK3066_PLL_RATE(121750000, 6, 487, 16), -+ RK3066_PLL_RATE(119000000, 3, 238, 16), - RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), - RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), -+ RK3066_PLL_RATE(101000000, 3, 202, 16), -+ RK3066_PLL_RATE(88750000, 6, 355, 16), - RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), -+ RK3066_PLL_RATE(83500000, 3, 167, 16), -+ RK3066_PLL_RATE(79500000, 1, 53, 16), - RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), - RK3066_PLL_RATE(74176000, 26, 1125, 14), -+ RK3066_PLL_RATE(72000000, 1, 48, 16), -+ RK3066_PLL_RATE(71000000, 3, 142, 16), -+ RK3066_PLL_RATE(68250000, 2, 91, 16), -+ RK3066_PLL_RATE(65000000, 3, 130, 16), -+ RK3066_PLL_RATE(40000000, 3, 80, 16), -+ RK3066_PLL_RATE(33750000, 2, 45, 16), - { /* sentinel */ }, - }; - - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 25 May 2020 20:36:45 +0000 Subject: [PATCH] HACK: clk: rockchip: rk3399: dedicate vpll for vopb and hdmi use +Rockchip PLLs are kown provide the least jitter for +vco rates between 800 MHz and 2 GHz. I added the +rates for VPLL which are used for VOPs dclk and there- +fore HDMI phy in that manner and used the rates which +require the lowest frac divs. +Additionally I added some rates which are useful to +provide additional VESA and non-VESA rates for HDMI +output. + Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- - drivers/clk/rockchip/clk-rk3399.c | 32 +++++++++++++++++++++++++------ - 1 file changed, 26 insertions(+), 6 deletions(-) + drivers/clk/rockchip/clk-rk3399.c | 49 ++++++++++++++++++++++++++----- + 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 306910a3a0d3..1db62a3a4c67 100644 +index 306910a3a0d3..436d2789611c 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c -@@ -105,6 +105,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { +@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { { /* sentinel */ }, }; +static struct rockchip_pll_rate_table rk3399_vpll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ -+ RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */ -+ RK3036_PLL_RATE( 593406592, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */ -+ RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */ -+ RK3036_PLL_RATE( 296703296, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */ -+ RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */ -+ RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */ -+ RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */ -+ RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */ -+ RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */ -+ RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */ -+ RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */ -+ RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */ -+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */ -+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */ ++ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */ ++ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */ ++ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */ ++ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */ ++ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */ ++ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */ ++ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */ ++ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/ ++ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */ ++ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */ ++ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */ ++ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */ ++ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */ ++ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */ ++ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */ ++ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */ ++ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */ ++ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */ ++ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */ ++ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */ ++ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */ ++ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */ ++ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */ ++ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */ ++ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */ ++ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */ ++ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */ ++ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */ + { /* sentinel */ }, +}; + /* CRU parents */ PNAME(mux_pll_p) = { "xin24m", "xin32k" }; -@@ -123,7 +142,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", +@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", @@ -1844,11 +1859,14 @@ index 306910a3a0d3..1db62a3a4c67 100644 PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" }; PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", -@@ -150,9 +169,10 @@ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", +@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", + PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; - PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; +-PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; -PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", ++PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "prevent:vpll", "cpll", "gpll" }; ++PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "prevent:cpll", "prevent:gpll" }; + +PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll", "npll" }; @@ -1857,7 +1875,7 @@ index 306910a3a0d3..1db62a3a4c67 100644 "xin24m" }; PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", -@@ -229,7 +249,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { +@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), @@ -1866,7 +1884,7 @@ index 306910a3a0d3..1db62a3a4c67 100644 }; static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { -@@ -279,7 +299,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = +@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = @@ -1875,12 +1893,12 @@ index 306910a3a0d3..1db62a3a4c67 100644 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = -@@ -1162,7 +1182,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { +@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(28), 0, GFLAGS), - COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, -+ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 12, GFLAGS), @@ -1961,7 +1979,7 @@ Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to 1 file changed, 76 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 6345c0759473..9a16cedc9fd2 100644 +index a2d101ebf7a7..7f6ffbc3e7b2 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2003,6 +2003,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, @@ -2190,7 +2208,7 @@ Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 4d64305e409b..9068c953b843 100644 +index d6d8f3335813..89424c5bc24a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -84,6 +84,8 @@ struct rockchip_hdmi { @@ -2301,7 +2319,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 9a16cedc9fd2..039923902d5f 100644 +index 7f6ffbc3e7b2..ae4c49e84470 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1790,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, @@ -2350,11 +2368,11 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv444 support drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 6 +++++ - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 14 ++++++++++ - 4 files changed, 77 insertions(+), 1 deletion(-) + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 ++++++++++++++ + 4 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 9068c953b843..e5b827253f47 100644 +index 89424c5bc24a..05de2052d95d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -68,6 +68,7 @@ struct rockchip_hdmi_chip_data { @@ -2432,7 +2450,7 @@ index 9068c953b843..e5b827253f47 100644 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 1529d5fbc7c7..8a9875bf7977 100644 +index eadf1b0f1704..0e4eca0d5121 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -347,6 +347,17 @@ static int vop_convert_afbc_format(uint32_t format) @@ -2453,7 +2471,7 @@ index 1529d5fbc7c7..8a9875bf7977 100644 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t dst, bool is_horizontal, int vsu_mode, int *vskiplines) -@@ -1451,6 +1462,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1455,6 +1466,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; int dither_bpc = s->output_bpc ? s->output_bpc : 10; @@ -2461,7 +2479,7 @@ index 1529d5fbc7c7..8a9875bf7977 100644 int ret; if (old_state && old_state->self_refresh_active) { -@@ -1516,6 +1528,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1520,6 +1532,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2470,7 +2488,7 @@ index 1529d5fbc7c7..8a9875bf7977 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else -@@ -1531,6 +1545,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1535,6 +1549,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2514,7 +2532,7 @@ index ca4e2b7415fe..47ad74ef1afb 100644 struct vop_intr { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index a2b281e290e0..a8a3e9d13fe5 100644 +index a2b281e290e0..b16a4c42773c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -705,6 +705,11 @@ static const struct vop_common rk3288_common = { @@ -2529,7 +2547,19 @@ index a2b281e290e0..a8a3e9d13fe5 100644 }; /* -@@ -1096,6 +1101,10 @@ static const struct vop_output rk3328_output = { +@@ -926,6 +931,11 @@ static const struct vop_common rk3399_common = { + .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), + .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), ++ ++ .overlay_mode = VOP_REG(RK3399_SYS_CTRL, 0x1, 16), ++ .dsp_data_swap = VOP_REG(RK3399_DSP_CTRL0, 0x1f, 12), ++ .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), ++ .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), + }; + + static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { +@@ -1096,6 +1106,10 @@ static const struct vop_output rk3328_output = { static const struct vop_misc rk3328_misc = { .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), @@ -2540,7 +2570,7 @@ index a2b281e290e0..a8a3e9d13fe5 100644 }; static const struct vop_common rk3328_common = { -@@ -1108,6 +1117,11 @@ static const struct vop_common rk3328_common = { +@@ -1108,6 +1122,11 @@ static const struct vop_common rk3328_common = { .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), @@ -2566,7 +2596,7 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv420 support 4 files changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index e5b827253f47..9bdf6211f15c 100644 +index 05de2052d95d..cb201612199f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -407,9 +407,21 @@ static bool is_yuv444(u32 format) @@ -2630,7 +2660,7 @@ index e5b827253f47..9bdf6211f15c 100644 static struct rockchip_hdmi_chip_data rk3399_chip_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 8a9875bf7977..154e08e7e47a 100644 +index 0e4eca0d5121..e50f71ad3ceb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -10,6 +10,7 @@ @@ -2661,7 +2691,7 @@ index 8a9875bf7977..154e08e7e47a 100644 { switch (bus_format) { case MEDIA_BUS_FMT_YUV8_1X24: -@@ -1528,7 +1542,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1532,7 +1546,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2670,7 +2700,7 @@ index 8a9875bf7977..154e08e7e47a 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); -@@ -1545,6 +1559,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1549,6 +1563,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2710,7 +2740,7 @@ index 47ad74ef1afb..94a615dca672 100644 /* output flags */ #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index a8a3e9d13fe5..50c157ff366b 100644 +index b16a4c42773c..5463b04240f7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -707,6 +707,7 @@ static const struct vop_common rk3288_common = { @@ -2721,7 +2751,7 @@ index a8a3e9d13fe5..50c157ff366b 100644 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), -@@ -1119,6 +1120,7 @@ static const struct vop_common rk3328_common = { +@@ -1124,6 +1125,7 @@ static const struct vop_common rk3328_common = { .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), @@ -2741,7 +2771,7 @@ Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 9bdf6211f15c..688c99e07c69 100644 +index cb201612199f..8627f6826bfe 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -616,6 +616,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { @@ -2772,21 +2802,20 @@ this will allow modes >= 2160p@50Hz on RK3288/RK3399 (RGB444) Signed-off-by: Alex Bee --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 688c99e07c69..c720d1ce48a4 100644 +index 8627f6826bfe..e259362f6414 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -326,16 +326,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -326,16 +326,29 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, const struct drm_display_mode *mode) { struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data; + const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg; -+ int clock = mode->clock; -+ int i = 0; ++ unsigned int i = 0; if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && - (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) @@ -2809,91 +2838,10 @@ index 688c99e07c69..c720d1ce48a4 100644 + return MODE_CLOCK_HIGH; + } + - return drm_mode_validate_size(mode, 3840, 2160); + return MODE_OK; } static void -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 15 Aug 2020 21:11:08 +0200 -Subject: [PATCH] !fixup drm/rockchip: rk3368's vop does not support 10-bit - formats - ---- - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 50c157ff366b..e33c499d3041 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -794,8 +794,8 @@ static const struct vop_intr rk3368_vop_intr = { - - static const struct vop_win_phy rk3368_win01_data = { - .scl = &rk3288_win_full_scl, -- .data_formats = formats_win_full_10, -- .nformats = ARRAY_SIZE(formats_win_full_10), -+ .data_formats = formats_win_full, -+ .nformats = ARRAY_SIZE(formats_win_full), - .format_modifiers = format_modifiers_win_full, - .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), - .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Oct 2020 16:42:05 +0100 -Subject: [PATCH] drm/rockchip: split rk3328 vop for 10-bit support - -Signed-off-by: Alex Bee ---- - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 30 ++++++++++++++++++--- - 1 file changed, 27 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index e33c499d3041..cc235baa9d50 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -1136,12 +1136,36 @@ static const struct vop_intr rk3328_vop_intr = { - .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), - }; - -+static const struct vop_win_phy rk3328_win01_data = { -+ .scl = &rk3288_win_full_scl, -+ .data_formats = formats_win_full_10, -+ .nformats = ARRAY_SIZE(formats_win_full_10), -+ .format_modifiers = format_modifiers_win_full, -+ .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), -+ .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), -+ .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), -+ .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), -+ .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), -+ .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), -+ .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0), -+ .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0), -+ .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0), -+ .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0), -+ .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0), -+ .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0), -+ .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16), -+ .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0), -+ .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0), -+ .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0), -+}; -+ -+ - static const struct vop_win_data rk3328_vop_win_data[] = { -- { .base = 0xd0, .phy = &rk3368_win01_data, -+ { .base = 0xd0, .phy = &rk3328_win01_data, - .type = DRM_PLANE_TYPE_PRIMARY }, -- { .base = 0x1d0, .phy = &rk3368_win01_data, -+ { .base = 0x1d0, .phy = &rk3328_win01_data, - .type = DRM_PLANE_TYPE_OVERLAY }, -- { .base = 0x2d0, .phy = &rk3368_win01_data, -+ { .base = 0x2d0, .phy = &rk3328_win01_data, - .type = DRM_PLANE_TYPE_CURSOR }, - }; - - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 18 Nov 2017 11:09:39 +0100 @@ -2904,7 +2852,7 @@ Subject: [PATCH] rockchip: vop: force skip lines if image too big 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 154e08e7e47a..c0f136bf74db 100644 +index e50f71ad3ceb..ef0a078c22f4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -965,6 +965,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, @@ -2979,36 +2927,6 @@ index d7e44d174d7b..5519347232f6 100644 <100000000>, <100000000>, <50000000>, <50000000>, -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Mon, 1 Mar 2021 20:31:15 +0100 -Subject: [PATCH] clk: rockchip: rk3288: use common PLL setting for 594 MHz in - NPLL table - -The settings in the NPLL table (which were obviously copied from RK3368) don't -provide a stable signal for 594 MHz, what leads to random short-term black -screen periods (@2160p@60Hz) on some sensetive HDMI sinks when using this PLL -as the source for VOPs dclk. -Using the PLL settings from the common PLL table for this frequency fixes -this. ---- - drivers/clk/rockchip/clk-rk3288.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 233890555616..676e7c3c6f2b 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -122,7 +122,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { - }; - - static struct rockchip_pll_rate_table rk3288_npll_rates[] = { -- RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32), -+ RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), - RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), - RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), - RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 10 Apr 2021 16:54:26 +0200 @@ -3035,7 +2953,7 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 039923902d5f..20fc0981ef18 100644 +index ae4c49e84470..92e621f2714f 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { @@ -3061,79 +2979,6 @@ index 039923902d5f..20fc0981ef18 100644 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 20 Mar 2021 11:12:07 +0100 -Subject: [PATCH] clk: rockchip: RK3399: adapt VPLL rates - -Rockchip PLLs are kown provide the least jitter for -vco rates between 800 MHz and 2 GHz. I converted the -rates for VPLL which are used for VOPs dclk and there- -fore HDMI phy in that manner and used the rates which -require the lowest frac divs. -Additionally I added some rates which are useful to -provide additional VESA and non-VESA rates for HDMI -output. - -Signed-off-by: Alex Bee ---- - drivers/clk/rockchip/clk-rk3399.c | 42 ++++++++++++++++++++----------- - 1 file changed, 28 insertions(+), 14 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 1db62a3a4c67..b4f559e2b86c 100644 ---- a/drivers/clk/rockchip/clk-rk3399.c -+++ b/drivers/clk/rockchip/clk-rk3399.c -@@ -107,20 +107,34 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { - - static struct rockchip_pll_rate_table rk3399_vpll_rates[] = { - /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ -- RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */ -- RK3036_PLL_RATE( 593406592, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */ -- RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */ -- RK3036_PLL_RATE( 296703296, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */ -- RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */ -- RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */ -- RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */ -- RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */ -- RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */ -- RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */ -- RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */ -- RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */ -- RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */ -- RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */ -+ RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0, 4194304), /* vco = 1782000000 fout = 594000000 */ -+ RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0, 2949838), /* vco = 1780219777 fout = 593406592.36908 */ -+ RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640), /* vco = 1918500000 fout = 319750000 */ -+ RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0, 4194304), /* vco = 1782000000 fout = 297000000 */ -+ RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0, 2949838), /* vco = 1780219777 fout = 296703296.18454 */ -+ RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0, 6291456), /* vco = 1449000000 fout = 241500000 */ -+ RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0, 8388608), /* vco = 1620000000 fout = 162000000 */ -+ RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0, 4194304), /* vco = 1782000000 fout = 148500000*/ -+ RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0, 2949838), /* vco = 1780219777 fout = 148351648.09227 */ -+ RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0, 6291456), /* vco = 1641000000 fout = 136750000 */ -+ RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0, 4194304), /* vco = 1350000000 fout = 135000000 */ -+ RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0, 8388608), /* vco = 1428000000 fout = 119000000 */ -+ RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1, 0), /* vco = 1512000000 fout = 108000000 */ -+ RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0, 2097152), /* vco = 1491000000 fout = 106500000 */ -+ RK3036_PLL_RATE( 88750000, 1, 55, 5, 3, 0, 7864320), /* vco = 1331250000 fout = 88750000 */ -+ RK3036_PLL_RATE( 85500000, 1, 57, 4, 4, 1, 0), /* vco = 1368000000 fout = 85500000 */ -+ RK3036_PLL_RATE( 78750000, 1, 59, 6, 3, 0, 1048576), /* vco = 1417500000 fout = 78750000 */ -+ RK3036_PLL_RATE( 74250000, 1, 74, 6, 4, 0, 4194304), /* vco = 1782000000 fout = 74250000 */ -+ RK3036_PLL_RATE( 74175824, 1, 74, 6, 4, 0, 2949838), /* vco = 1780219777 fout = 74175824.046135 */ -+ RK3036_PLL_RATE( 71000000, 1, 71, 6, 4, 1, 0), /* vco = 1704000000 fout = 71000000 */ -+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 0, 0), /* vco = 1560000000 fout = 65000000 */ -+ RK3036_PLL_RATE( 59340659, 1, 59, 6, 4, 0, 5715310), /* vco = 1424175816 fout = 59340659.022331 */ -+ RK3036_PLL_RATE( 54000000, 1, 63, 7, 4, 1, 0), /* vco = 1512000000 fout = 54000000 */ -+ RK3036_PLL_RATE( 49500000, 1, 72, 5, 7, 0, 3145728), /* vco = 1732500000 fout = 49500000 */ -+ RK3036_PLL_RATE( 40000000, 1, 70, 7, 6, 1, 0), /* vco = 1680000000 fout = 40000000 */ -+ RK3036_PLL_RATE( 31500000, 1, 55, 7, 6, 0, 2097152), /* vco = 1323000000 fout = 31500000 */ -+ RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 fout = 27000000 */ -+ RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173214), /* vco = 1321678296 fout = 26973026.450799 */ - { /* sentinel */ }, - }; - - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 23 Mar 2021 19:45:07 +0100 @@ -3372,42 +3217,6 @@ index 2f01259823ea..1889e78e18ea 100644 }; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Algea Cao -Date: Wed, 6 Jun 2018 15:47:12 +0800 -Subject: [PATCH] drm/bridge: synopsys: dw-hdmi: Select formula1 for csc - decimation - -Formula3 and Formula2 for csc decimation will cause hdmi yuv422 -display err. - -Formula3: -The pixel color of left 0-14 columns and right 0-12 columns is -err. - -Formula2: -The pixel color of left 0-2 columns is err. - -Change-Id: I94fdd5fd962a24fde02dde1fe3ac10437ad117ad -Signed-off-by: Algea Cao ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 20fc0981ef18..3082387aa53e 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1179,7 +1179,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) - if (is_color_space_interpolation(hdmi)) - interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; - else if (is_color_space_decimation(hdmi)) -- decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; -+ decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1; - - switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { - case 8: - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 1 Jun 2021 19:24:37 +0200 @@ -3420,25 +3229,11 @@ vop_crtc_mode_valid anyways. Signed-off-by: Alex Bee --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++-- - 2 files changed, 3 insertions(+), 3 deletions(-) + 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index c720d1ce48a4..1062afa26c56 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -350,7 +350,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - return MODE_CLOCK_HIGH; - } - -- return drm_mode_validate_size(mode, 3840, 2160); -+ return MODE_OK; - } - static void - dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index c0f136bf74db..140f52fe2348 100644 +index ef0a078c22f4..49619f794061 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -424,8 +424,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, @@ -3623,20 +3418,14 @@ depending on sink's implementation. Signed-off-by: Alex Bee --- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 16 ++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 84cc52858ffb..3c20ef3bd3c1 100644 +index 92e621f2714f..7551e3ab77d6 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -3036,24 +3036,11 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) - * ask the source to re-read the EDID. - */ - if (intr_stat & -- (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { -+ (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) - dw_hdmi_setup_rx_sense(hdmi, +@@ -3179,12 +3179,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) phy_stat & HDMI_PHY_HPD, phy_stat & HDMI_PHY_RX_SENSE); @@ -3646,17 +3435,10 @@ index 84cc52858ffb..3c20ef3bd3c1 100644 - mutex_unlock(&hdmi->cec_notifier_mutex); - } - -- if (phy_stat & HDMI_PHY_HPD) -- status = connector_status_connected; -- -- if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE))) -- status = connector_status_disconnected; -- } -- - if (status != connector_status_unknown) { - dev_dbg(hdmi->dev, "EVENT=%s\n", - status == connector_status_connected ? -@@ -3061,6 +3054,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + if (phy_stat & HDMI_PHY_HPD) + status = connector_status_connected; + +@@ -3201,6 +3195,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) drm_helper_hpd_irq_event(hdmi->bridge.dev); drm_bridge_hpd_notify(&hdmi->bridge, status); } @@ -3683,10 +3465,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 140f52fe2348..40fdfc50b7a8 100644 +index 49619f794061..9915bf124374 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -2019,19 +2019,10 @@ static int vop_create_crtc(struct vop *vop) +@@ -2023,19 +2023,10 @@ static int vop_create_crtc(struct vop *vop) int ret; int i; @@ -3706,7 +3488,7 @@ index 140f52fe2348..40fdfc50b7a8 100644 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 0, &vop_plane_funcs, win_data->phy->data_formats, -@@ -2064,32 +2055,13 @@ static int vop_create_crtc(struct vop *vop) +@@ -2068,32 +2059,13 @@ static int vop_create_crtc(struct vop *vop) drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); } diff --git a/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch index be3b737d5b..e489f58c87 100644 --- a/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch @@ -540,4 +540,3 @@ index 5519347232f6..431c4ec198be 100644 iommus = <&vdec_mmu>; power-domains = <&power RK3328_PD_VIDEO>; }; - diff --git a/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch index 2892b62b64..40e7e14714 100644 --- a/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch @@ -666,6 +666,7 @@ index a2f0860b20bb..8961f9c7885d 100644 .audio_startup = dw_hdmi_i2s_audio_startup, .audio_shutdown = dw_hdmi_i2s_audio_shutdown, .get_eld = dw_hdmi_i2s_get_eld, + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 18 Sep 2022 10:35:52 +0200 diff --git a/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch index 40441c1565..34c37c4ffa 100644 --- a/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch @@ -28,7 +28,7 @@ index cb86b429cfaa..a77122641d14 100644 +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c new file mode 100644 -index 000000000000..fd87cbf9c1f8 +index 000000000000..7a375a23eaf1 --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -0,0 +1,2572 @@ @@ -3118,7 +3118,7 @@ Signed-off-by: Nicolas Dufresne 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index fd87cbf9c1f8..2fbed8d49a76 100644 +index 7a375a23eaf1..580073d49b6a 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -10,6 +10,7 @@ @@ -3194,7 +3194,7 @@ Signed-off-by: Nicolas Dufresne 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 2fbed8d49a76..4a15ebb94149 100644 +index 580073d49b6a..ce15028918b2 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, From e1a99e2316c0f271c7c417a49365ebea48fd66f8 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Mon, 31 Oct 2022 17:22:47 +0100 Subject: [PATCH 2/4] Rockchip: u-boot: Separate patches and add fix for vendor boot chain --- ...dd-support-for-RK322x-non-secure-efu.patch | 150 +++++++++ ...-efuse-drivers-for-RK3288-and-RK3328.patch | 292 ------------------ ...dd-support-for-RK3328-non-secure-efu.patch | 117 +++++++ ...0003-arm-dts-enable-efuse-for-RK3288.patch | 23 ++ ...oot-rockchip-rk3288-switch-bootorder.patch | 13 - ...rk3328-Set-VOP-QoS-to-high-priority.patch} | 4 +- ...88-Pick-SD-card-as-first-boot-device.patch | 26 ++ ...9-evb-Don-t-initalize-i2c-bus-in-SPL.patch | 37 +++ 8 files changed, 355 insertions(+), 307 deletions(-) create mode 100644 projects/Rockchip/patches/u-boot/0001-rockchip-efuse-add-support-for-RK322x-non-secure-efu.patch delete mode 100644 projects/Rockchip/patches/u-boot/0001-u-boot-add-efuse-drivers-for-RK3288-and-RK3328.patch create mode 100644 projects/Rockchip/patches/u-boot/0002-rockchip-efuse-add-support-for-RK3328-non-secure-efu.patch create mode 100644 projects/Rockchip/patches/u-boot/0003-arm-dts-enable-efuse-for-RK3288.patch delete mode 100644 projects/Rockchip/patches/u-boot/0003-u-boot-rockchip-rk3288-switch-bootorder.patch rename projects/Rockchip/patches/u-boot/{0002-u-boot-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch => 0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch} (90%) create mode 100644 projects/Rockchip/patches/u-boot/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch create mode 100644 projects/Rockchip/patches/u-boot/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch diff --git a/projects/Rockchip/patches/u-boot/0001-rockchip-efuse-add-support-for-RK322x-non-secure-efu.patch b/projects/Rockchip/patches/u-boot/0001-rockchip-efuse-add-support-for-RK322x-non-secure-efu.patch new file mode 100644 index 0000000000..b7c5e57993 --- /dev/null +++ b/projects/Rockchip/patches/u-boot/0001-rockchip-efuse-add-support-for-RK322x-non-secure-efu.patch @@ -0,0 +1,150 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Francis Fan +Date: Tue, 7 Nov 2017 17:50:11 +0800 +Subject: [PATCH 1/6] rockchip: efuse: add support for RK322x non-secure efuse + block + +Signed-off-by: Francis Fan +Signed-off-by: Cody Xie +--- + drivers/misc/rockchip-efuse.c | 96 +++++++++++++++++++++++++++++++++-- + 1 file changed, 92 insertions(+), 4 deletions(-) + +diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c +index 083ee65e0a..4c9239f7ba 100644 +--- a/drivers/misc/rockchip-efuse.c ++++ b/drivers/misc/rockchip-efuse.c +@@ -27,6 +27,17 @@ + #define RK3399_STROBE BIT(1) + #define RK3399_CSB BIT(0) + ++#define RK3288_A_SHIFT 6 ++#define RK3288_A_MASK 0x3ff ++#define RK3288_NFUSES 32 ++#define RK3288_BYTES_PER_FUSE 1 ++#define RK3288_PGENB BIT(3) ++#define RK3288_LOAD BIT(2) ++#define RK3288_STROBE BIT(1) ++#define RK3288_CSB BIT(0) ++ ++typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size); ++ + struct rockchip_efuse_regs { + u32 ctrl; /* 0x00 efuse control register */ + u32 dout; /* 0x04 efuse data out register */ +@@ -53,7 +64,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, + */ + + struct udevice *dev; +- u8 fuses[128]; ++ u8 fuses[128] = {0}; + int ret; + + /* retrieve the device */ +@@ -77,7 +88,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, + } + + U_BOOT_CMD( +- rk3399_dump_efuses, 1, 1, dump_efuses, ++ rockchip_dump_efuses, 1, 1, dump_efuses, + "Dump the content of the efuses", + "" + ); +@@ -127,10 +138,59 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset, + return 0; + } + ++static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, ++ void *buf, int size) ++{ ++ struct rockchip_efuse_plat *plat = dev_get_plat(dev); ++ struct rockchip_efuse_regs *efuse = ++ (struct rockchip_efuse_regs *)plat->base; ++ u8 *buffer = buf; ++ int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE; ++ ++ if (size > (max_size - offset)) ++ size = max_size - offset; ++ ++ /* Switch to read mode */ ++ writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl); ++ udelay(1); ++ ++ while (size--) { ++ writel(readl(&efuse->ctrl) & ++ (~(RK3288_A_MASK << RK3288_A_SHIFT)), ++ &efuse->ctrl); ++ /* set addr */ ++ writel(readl(&efuse->ctrl) | ++ ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT), ++ &efuse->ctrl); ++ udelay(1); ++ /* strobe low to high */ ++ writel(readl(&efuse->ctrl) | ++ RK3288_STROBE, &efuse->ctrl); ++ ndelay(60); ++ /* read data */ ++ *buffer++ = readl(&efuse->dout); ++ /* reset strobe to low */ ++ writel(readl(&efuse->ctrl) & ++ (~RK3288_STROBE), &efuse->ctrl); ++ udelay(1); ++ } ++ ++ /* Switch to standby mode */ ++ writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl); ++ ++ return 0; ++} ++ + static int rockchip_efuse_read(struct udevice *dev, int offset, + void *buf, int size) + { +- return rockchip_rk3399_efuse_read(dev, offset, buf, size); ++ EFUSE_READ efuse_read = NULL; ++ ++ efuse_read = (EFUSE_READ)dev_get_driver_data(dev); ++ if (!efuse_read) ++ return -ENOSYS; ++ ++ return (*efuse_read)(dev, offset, buf, size); + } + + static const struct misc_ops rockchip_efuse_ops = { +@@ -146,7 +206,35 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev) + } + + static const struct udevice_id rockchip_efuse_ids[] = { +- { .compatible = "rockchip,rk3399-efuse" }, ++ /* deprecated but kept around for dts binding compatibility */ ++ { ++ .compatible = "rockchip,rockchip-efuse", ++ .data = (ulong)&rockchip_rk3288_efuse_read, ++ }, ++ { ++ .compatible = "rockchip,rk3066a-efuse", ++ .data = (ulong)&rockchip_rk3288_efuse_read, ++ }, ++ { ++ .compatible = "rockchip,rk3188-efuse", ++ .data = (ulong)&rockchip_rk3288_efuse_read, ++ }, ++ { ++ .compatible = "rockchip,rk3228-efuse", ++ .data = (ulong)&rockchip_rk3288_efuse_read, ++ }, ++ { ++ .compatible = "rockchip,rk3288-efuse", ++ .data = (ulong)&rockchip_rk3288_efuse_read, ++ }, ++ { ++ .compatible = "rockchip,rk3368-efuse", ++ .data = (ulong)&rockchip_rk3288_efuse_read, ++ }, ++ { ++ .compatible = "rockchip,rk3399-efuse", ++ .data = (ulong)&rockchip_rk3399_efuse_read, ++ }, + {} + }; + diff --git a/projects/Rockchip/patches/u-boot/0001-u-boot-add-efuse-drivers-for-RK3288-and-RK3328.patch b/projects/Rockchip/patches/u-boot/0001-u-boot-add-efuse-drivers-for-RK3288-and-RK3328.patch deleted file mode 100644 index c76d11da0d..0000000000 --- a/projects/Rockchip/patches/u-boot/0001-u-boot-add-efuse-drivers-for-RK3288-and-RK3328.patch +++ /dev/null @@ -1,292 +0,0 @@ -From ae3121ae4a50702c8e52078ed52bd279d339b68b Mon Sep 17 00:00:00 2001 -From: Francis Fan -Date: Tue, 7 Nov 2017 17:50:11 +0800 -Subject: [PATCH] rockchip: efuse: add support for RK322x non-secure efuse - block - -Signed-off-by: Francis Fan -Signed-off-by: Cody Xie ---- - drivers/misc/rockchip-efuse.c | 96 +++++++++++++++++++++++++++++++++-- - 1 file changed, 92 insertions(+), 4 deletions(-) - -diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c -index 083ee65e0a..85a9384581 100644 ---- a/drivers/misc/rockchip-efuse.c -+++ b/drivers/misc/rockchip-efuse.c -@@ -27,6 +27,17 @@ - #define RK3399_STROBE BIT(1) - #define RK3399_CSB BIT(0) - -+#define RK3288_A_SHIFT 6 -+#define RK3288_A_MASK 0x3ff -+#define RK3288_NFUSES 32 -+#define RK3288_BYTES_PER_FUSE 1 -+#define RK3288_PGENB BIT(3) -+#define RK3288_LOAD BIT(2) -+#define RK3288_STROBE BIT(1) -+#define RK3288_CSB BIT(0) -+ -+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size); -+ - struct rockchip_efuse_regs { - u32 ctrl; /* 0x00 efuse control register */ - u32 dout; /* 0x04 efuse data out register */ -@@ -53,7 +64,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, - */ - - struct udevice *dev; -- u8 fuses[128]; -+ u8 fuses[128] = {0}; - int ret; - - /* retrieve the device */ -@@ -77,7 +88,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag, - } - - U_BOOT_CMD( -- rk3399_dump_efuses, 1, 1, dump_efuses, -+ rockchip_dump_efuses, 1, 1, dump_efuses, - "Dump the content of the efuses", - "" - ); -@@ -127,10 +138,59 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset, - return 0; - } - -+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, -+ void *buf, int size) -+{ -+ struct rockchip_efuse_plat *plat = dev_get_plat(dev); -+ struct rockchip_efuse_regs *efuse = -+ (struct rockchip_efuse_regs *)plat->base; -+ u8 *buffer = buf; -+ int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE; -+ -+ if (size > (max_size - offset)) -+ size = max_size - offset; -+ -+ /* Switch to read mode */ -+ writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl); -+ udelay(1); -+ -+ while (size--) { -+ writel(readl(&efuse->ctrl) & -+ (~(RK3288_A_MASK << RK3288_A_SHIFT)), -+ &efuse->ctrl); -+ /* set addr */ -+ writel(readl(&efuse->ctrl) | -+ ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT), -+ &efuse->ctrl); -+ udelay(1); -+ /* strobe low to high */ -+ writel(readl(&efuse->ctrl) | -+ RK3288_STROBE, &efuse->ctrl); -+ ndelay(60); -+ /* read data */ -+ *buffer++ = readl(&efuse->dout); -+ /* reset strobe to low */ -+ writel(readl(&efuse->ctrl) & -+ (~RK3288_STROBE), &efuse->ctrl); -+ udelay(1); -+ } -+ -+ /* Switch to standby mode */ -+ writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl); -+ -+ return 0; -+} -+ - static int rockchip_efuse_read(struct udevice *dev, int offset, - void *buf, int size) - { -- return rockchip_rk3399_efuse_read(dev, offset, buf, size); -+ EFUSE_READ efuse_read = NULL; -+ -+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev); -+ if (!efuse_read) -+ return -ENOSYS; -+ -+ return (*efuse_read)(dev, offset, buf, size); - } - - static const struct misc_ops rockchip_efuse_ops = { -@@ -146,7 +206,35 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev) - } - - static const struct udevice_id rockchip_efuse_ids[] = { -- { .compatible = "rockchip,rk3399-efuse" }, -+ /* deprecated but kept around for dts binding compatibility */ -+ { -+ .compatible = "rockchip,rockchip-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3066a-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3188-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3228-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3288-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3368-efuse", -+ .data = (ulong)&rockchip_rk3288_efuse_read, -+ }, -+ { -+ .compatible = "rockchip,rk3399-efuse", -+ .data = (ulong)&rockchip_rk3399_efuse_read, -+ }, - {} - }; - - -From 8b1ce76598895a8979c98cdf27a408b19727d708 Mon Sep 17 00:00:00 2001 -From: Joseph Chen -Date: Thu, 2 Aug 2018 20:33:16 +0800 -Subject: [PATCH] rockchip: efuse: add support for RK3328 non-secure efuse - block - -Signed-off-by: Joseph Chen ---- - drivers/misc/rockchip-efuse.c | 67 +++++++++++++++++++++++++++++++++++ - 1 file changed, 67 insertions(+) - -diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c -index 85a9384581..1b0e81f4ad 100644 ---- a/drivers/misc/rockchip-efuse.c -+++ b/drivers/misc/rockchip-efuse.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - - #define RK3399_A_SHIFT 16 -@@ -36,6 +37,13 @@ - #define RK3288_STROBE BIT(1) - #define RK3288_CSB BIT(0) - -+#define RK3328_INT_STATUS 0x0018 -+#define RK3328_DOUT 0x0020 -+#define RK3328_AUTO_CTRL 0x0024 -+#define RK3328_INT_FINISH BIT(0) -+#define RK3328_AUTO_ENB BIT(0) -+#define RK3328_AUTO_RD BIT(1) -+ - typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size); - - struct rockchip_efuse_regs { -@@ -46,6 +54,10 @@ struct rockchip_efuse_regs { - u32 jtag_pass; /* 0x10 JTAG password */ - u32 strobe_finish_ctrl; - /* 0x14 efuse strobe finish control register */ -+ u32 int_status;/* 0x18 */ -+ u32 reserved; /* 0x1c */ -+ u32 dout2; /* 0x20 */ -+ u32 auto_ctrl; /* 0x24 */ - }; - - struct rockchip_efuse_plat { -@@ -181,6 +193,57 @@ static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, - return 0; - } - -+static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset, -+ void *buf, int size) -+{ -+ struct rockchip_efuse_plat *plat = dev_get_plat(dev); -+ struct rockchip_efuse_regs *efuse = -+ (struct rockchip_efuse_regs *)plat->base; -+ unsigned int addr_start, addr_end, addr_offset, addr_len; -+ u32 out_value, status; -+ u8 *buffer; -+ int ret = 0, i = 0, j = 0; -+ -+ /* Max non-secure Byte */ -+ if (size > 32) -+ size = 32; -+ -+ /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */ -+ offset += 96; -+ addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) / -+ RK3399_BYTES_PER_FUSE; -+ addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) / -+ RK3399_BYTES_PER_FUSE; -+ addr_offset = offset % RK3399_BYTES_PER_FUSE; -+ addr_len = addr_end - addr_start; -+ -+ buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE); -+ if (!buffer) -+ return -ENOMEM; -+ -+ for (j = 0; j < addr_len; j++) { -+ writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | -+ ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), -+ &efuse->auto_ctrl); -+ udelay(5); -+ status = readl(&efuse->int_status); -+ if (!(status & RK3328_INT_FINISH)) { -+ ret = -EIO; -+ goto err; -+ } -+ out_value = readl(&efuse->dout2); -+ writel(RK3328_INT_FINISH, &efuse->int_status); -+ -+ memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE); -+ i += RK3399_BYTES_PER_FUSE; -+ } -+ memcpy(buf, buffer + addr_offset, size); -+err: -+ free(buffer); -+ -+ return ret; -+} -+ - static int rockchip_efuse_read(struct udevice *dev, int offset, - void *buf, int size) - { -@@ -231,6 +294,10 @@ static const struct udevice_id rockchip_efuse_ids[] = { - .compatible = "rockchip,rk3368-efuse", - .data = (ulong)&rockchip_rk3288_efuse_read, - }, -+ { -+ .compatible = "rockchip,rk3328-efuse", -+ .data = (ulong)&rockchip_rk3328_efuse_read, -+ }, - { - .compatible = "rockchip,rk3399-efuse", - .data = (ulong)&rockchip_rk3399_efuse_read, - -From add1c5f168cdf625813e5a159af1057e6a9f96e2 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 11 Sep 2022 10:56:43 +0200 -Subject: [PATCH] arm: dts: enable efuse for RK3288 - ---- - arch/arm/dts/rk3288.dtsi | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi -index 9fb6d86bc1..4d0a7190f0 100644 ---- a/arch/arm/dts/rk3288.dtsi -+++ b/arch/arm/dts/rk3288.dtsi -@@ -866,8 +866,7 @@ - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; -- reg = <0xffb40000 0x10000>; -- status = "disabled"; -+ reg = <0xffb40000 0x20>; - }; - - gic: interrupt-controller@ffc01000 { diff --git a/projects/Rockchip/patches/u-boot/0002-rockchip-efuse-add-support-for-RK3328-non-secure-efu.patch b/projects/Rockchip/patches/u-boot/0002-rockchip-efuse-add-support-for-RK3328-non-secure-efu.patch new file mode 100644 index 0000000000..62d190d8ce --- /dev/null +++ b/projects/Rockchip/patches/u-boot/0002-rockchip-efuse-add-support-for-RK3328-non-secure-efu.patch @@ -0,0 +1,117 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Joseph Chen +Date: Thu, 2 Aug 2018 20:33:16 +0800 +Subject: [PATCH 2/6] rockchip: efuse: add support for RK3328 non-secure efuse + block + +Signed-off-by: Joseph Chen +--- + drivers/misc/rockchip-efuse.c | 67 +++++++++++++++++++++++++++++++++++ + 1 file changed, 67 insertions(+) + +diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c +index 4c9239f7ba..c75405bfcf 100644 +--- a/drivers/misc/rockchip-efuse.c ++++ b/drivers/misc/rockchip-efuse.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + + #define RK3399_A_SHIFT 16 +@@ -36,6 +37,13 @@ + #define RK3288_STROBE BIT(1) + #define RK3288_CSB BIT(0) + ++#define RK3328_INT_STATUS 0x0018 ++#define RK3328_DOUT 0x0020 ++#define RK3328_AUTO_CTRL 0x0024 ++#define RK3328_INT_FINISH BIT(0) ++#define RK3328_AUTO_ENB BIT(0) ++#define RK3328_AUTO_RD BIT(1) ++ + typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size); + + struct rockchip_efuse_regs { +@@ -46,6 +54,10 @@ struct rockchip_efuse_regs { + u32 jtag_pass; /* 0x10 JTAG password */ + u32 strobe_finish_ctrl; + /* 0x14 efuse strobe finish control register */ ++ u32 int_status;/* 0x18 */ ++ u32 reserved; /* 0x1c */ ++ u32 dout2; /* 0x20 */ ++ u32 auto_ctrl; /* 0x24 */ + }; + + struct rockchip_efuse_plat { +@@ -181,6 +193,57 @@ static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, + return 0; + } + ++static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset, ++ void *buf, int size) ++{ ++ struct rockchip_efuse_plat *plat = dev_get_plat(dev); ++ struct rockchip_efuse_regs *efuse = ++ (struct rockchip_efuse_regs *)plat->base; ++ unsigned int addr_start, addr_end, addr_offset, addr_len; ++ u32 out_value, status; ++ u8 *buffer; ++ int ret = 0, i = 0, j = 0; ++ ++ /* Max non-secure Byte */ ++ if (size > 32) ++ size = 32; ++ ++ /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */ ++ offset += 96; ++ addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) / ++ RK3399_BYTES_PER_FUSE; ++ addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) / ++ RK3399_BYTES_PER_FUSE; ++ addr_offset = offset % RK3399_BYTES_PER_FUSE; ++ addr_len = addr_end - addr_start; ++ ++ buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE); ++ if (!buffer) ++ return -ENOMEM; ++ ++ for (j = 0; j < addr_len; j++) { ++ writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | ++ ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), ++ &efuse->auto_ctrl); ++ udelay(5); ++ status = readl(&efuse->int_status); ++ if (!(status & RK3328_INT_FINISH)) { ++ ret = -EIO; ++ goto err; ++ } ++ out_value = readl(&efuse->dout2); ++ writel(RK3328_INT_FINISH, &efuse->int_status); ++ ++ memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE); ++ i += RK3399_BYTES_PER_FUSE; ++ } ++ memcpy(buf, buffer + addr_offset, size); ++err: ++ free(buffer); ++ ++ return ret; ++} ++ + static int rockchip_efuse_read(struct udevice *dev, int offset, + void *buf, int size) + { +@@ -231,6 +294,10 @@ static const struct udevice_id rockchip_efuse_ids[] = { + .compatible = "rockchip,rk3368-efuse", + .data = (ulong)&rockchip_rk3288_efuse_read, + }, ++ { ++ .compatible = "rockchip,rk3328-efuse", ++ .data = (ulong)&rockchip_rk3328_efuse_read, ++ }, + { + .compatible = "rockchip,rk3399-efuse", + .data = (ulong)&rockchip_rk3399_efuse_read, diff --git a/projects/Rockchip/patches/u-boot/0003-arm-dts-enable-efuse-for-RK3288.patch b/projects/Rockchip/patches/u-boot/0003-arm-dts-enable-efuse-for-RK3288.patch new file mode 100644 index 0000000000..00e5d0dbdc --- /dev/null +++ b/projects/Rockchip/patches/u-boot/0003-arm-dts-enable-efuse-for-RK3288.patch @@ -0,0 +1,23 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 11 Sep 2022 10:56:43 +0200 +Subject: [PATCH 3/6] arm: dts: enable efuse for RK3288 + +--- + arch/arm/dts/rk3288.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi +index 53ee760b98..f923630f63 100644 +--- a/arch/arm/dts/rk3288.dtsi ++++ b/arch/arm/dts/rk3288.dtsi +@@ -866,8 +866,7 @@ + + efuse: efuse@ffb40000 { + compatible = "rockchip,rk3288-efuse"; +- reg = <0xffb40000 0x10000>; +- status = "disabled"; ++ reg = <0xffb40000 0x20>; + }; + + gic: interrupt-controller@ffc01000 { diff --git a/projects/Rockchip/patches/u-boot/0003-u-boot-rockchip-rk3288-switch-bootorder.patch b/projects/Rockchip/patches/u-boot/0003-u-boot-rockchip-rk3288-switch-bootorder.patch deleted file mode 100644 index 7af66965e4..0000000000 --- a/projects/Rockchip/patches/u-boot/0003-u-boot-rockchip-rk3288-switch-bootorder.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi -index 9eb696b141..3f3c77ca64 100644 ---- a/arch/arm/dts/rk3288-u-boot.dtsi -+++ b/arch/arm/dts/rk3288-u-boot.dtsi -@@ -25,7 +25,7 @@ - - chosen { - u-boot,spl-boot-order = \ -- "same-as-spl", &emmc, &sdmmc; -+ "same-as-spl", &sdmmc, &emmc; - }; - - dmc: dmc@ff610000 { diff --git a/projects/Rockchip/patches/u-boot/0002-u-boot-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch b/projects/Rockchip/patches/u-boot/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch similarity index 90% rename from projects/Rockchip/patches/u-boot/0002-u-boot-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch rename to projects/Rockchip/patches/u-boot/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch index c912f09bca..7aa2d3f8bd 100644 --- a/projects/Rockchip/patches/u-boot/0002-u-boot-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch +++ b/projects/Rockchip/patches/u-boot/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch @@ -1,7 +1,7 @@ -From 16bcb2e9a7e187d76d0f627668ad2babf66126e4 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 23 Jul 2022 13:23:19 +0200 -Subject: [PATCH] rockchip: rk3328: Set VOP QoS to high priority +Subject: [PATCH 4/6] rockchip: rk3328: Set VOP QoS to high priority The default priority for the quality of service for the video output results in unsightly glitches on the output whenever there diff --git a/projects/Rockchip/patches/u-boot/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch b/projects/Rockchip/patches/u-boot/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch new file mode 100644 index 0000000000..9ca11334db --- /dev/null +++ b/projects/Rockchip/patches/u-boot/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch @@ -0,0 +1,26 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 31 Oct 2022 17:13:47 +0100 +Subject: [PATCH 5/6] rockchip: rk3288: Pick SD card as first boot device + +In order to be able to boot from SD card at SPL level, always check this first +and any other mmc device later. + +Signed-off-by: Alex Bee +--- + arch/arm/dts/rk3288-u-boot.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi +index e411445ed6..17f2dd4d12 100644 +--- a/arch/arm/dts/rk3288-u-boot.dtsi ++++ b/arch/arm/dts/rk3288-u-boot.dtsi +@@ -25,7 +25,7 @@ + + chosen { + u-boot,spl-boot-order = \ +- "same-as-spl", &emmc, &sdmmc; ++ "same-as-spl", &sdmmc, &emmc; + }; + + dmc: dmc@ff610000 { diff --git a/projects/Rockchip/patches/u-boot/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch b/projects/Rockchip/patches/u-boot/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch new file mode 100644 index 0000000000..baa200a7aa --- /dev/null +++ b/projects/Rockchip/patches/u-boot/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch @@ -0,0 +1,37 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 31 Oct 2022 17:16:07 +0100 +Subject: [PATCH 6/6] Rockchip: rk3399-evb: Don't initalize i2c bus in SPL + +Since we are using this device as fallback for boards which are not supported +by mainline u-boot in combination with vendor TPL/SPL, we need to make sure +that i2c is initalized in BL33 because vendor bootchain doesn't do that in +an earlier level. +--- + arch/arm/dts/rk3399-evb-u-boot.dtsi | 10 +--------- + 1 file changed, 1 insertion(+), 9 deletions(-) + +diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi +index 5e39b1493d..18733da7f9 100644 +--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi +@@ -9,18 +9,10 @@ + / { + chosen { + stdout-path = "serial2:1500000n8"; +- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; + }; + +-&i2c0 { +- u-boot,dm-pre-reloc; +-}; +- +-&rk808 { +- u-boot,dm-pre-reloc; +-}; +- + &tcphy1 { + status = "okay"; + }; From 7da16186c8edd6fc233fbfe998f7476b7185de06 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Mon, 31 Oct 2022 17:33:14 +0100 Subject: [PATCH 3/4] Rockchip: RK3288: enable E/OHCI platform drivers Also disabe Inno HDMI phy driver as it does not exist in RK3288. --- .../Rockchip/devices/RK3288/linux/default/linux.arm.conf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index 04f1261c78..756f6b441d 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -4302,13 +4302,13 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y # CONFIG_USB_EHCI_FSL is not set -# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_MAX3421_HCD is not set CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_OHCI_HCD_PLATFORM=y # CONFIG_USB_SL811_HCD is not set CONFIG_USB_R8A66597_HCD=m # CONFIG_USB_HCD_BCMA is not set @@ -5752,7 +5752,7 @@ CONFIG_GENERIC_PHY=y CONFIG_PHY_ROCKCHIP_DP=m # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set CONFIG_PHY_ROCKCHIP_EMMC=m -CONFIG_PHY_ROCKCHIP_INNO_HDMI=m +# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=m # CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set From 830104f3e6760bc472ebe77b3f7436aec4d61b59 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Mon, 31 Oct 2022 18:00:38 +0100 Subject: [PATCH 4/4] Rockchip: RK3399: Enable DSI Also enable drivers for panels that might be relevant and do some cleanup --- .../RK3399/linux/default/linux.aarch64.conf | 130 ++++++++++++------ 1 file changed, 90 insertions(+), 40 deletions(-) diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index 4779866469..dd214a2dee 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.0.3-rc1 Kernel Configuration +# Linux/arm64 6.0.3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-elf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y @@ -14,7 +14,7 @@ CONFIG_LLD_VERSION=0 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y -CONFIG_PAHOLE_VERSION=0 +CONFIG_PAHOLE_VERSION=122 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -4218,6 +4218,8 @@ CONFIG_DVB_SP2=m # Graphics support # CONFIG_DRM=y +CONFIG_DRM_MIPI_DBI=y +CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y @@ -4262,7 +4264,7 @@ CONFIG_ROCKCHIP_VOP=y # CONFIG_ROCKCHIP_ANALOGIX_DP is not set # CONFIG_ROCKCHIP_CDN_DP is not set CONFIG_ROCKCHIP_DW_HDMI=y -# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set +CONFIG_ROCKCHIP_DW_MIPI_DSI=y # CONFIG_ROCKCHIP_INNO_HDMI is not set # CONFIG_ROCKCHIP_LVDS is not set # CONFIG_ROCKCHIP_RGB is not set @@ -4281,35 +4283,80 @@ CONFIG_DRM_PANEL=y # # Display Panels # -# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set -# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +CONFIG_DRM_PANEL_ABT_Y030XX067A=y +CONFIG_DRM_PANEL_ARM_VERSATILE=y +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=y +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=y +CONFIG_DRM_PANEL_BOE_HIMAX8279D=y +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y +CONFIG_DRM_PANEL_DSI_CM=y # CONFIG_DRM_PANEL_LVDS is not set -# CONFIG_DRM_PANEL_SIMPLE is not set -CONFIG_DRM_PANEL_EDP=y -# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set -# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set -# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set -# CONFIG_DRM_PANEL_LG_LB035Q02 is not set -# CONFIG_DRM_PANEL_LG_LG4573 is not set -# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set -# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set -# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set -# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_EBBG_FT8719=y +CONFIG_DRM_PANEL_ELIDA_KD35T133=y +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=y +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y +CONFIG_DRM_PANEL_ILITEK_IL9322=y +CONFIG_DRM_PANEL_ILITEK_ILI9341=y +CONFIG_DRM_PANEL_ILITEK_ILI9881C=y +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=y +CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y +CONFIG_DRM_PANEL_JDI_LT070ME05000=y +CONFIG_DRM_PANEL_JDI_R63452=y +CONFIG_DRM_PANEL_KHADAS_TS050=y +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=y +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=y +CONFIG_DRM_PANEL_SAMSUNG_LD9040=y +CONFIG_DRM_PANEL_LG_LB035Q02=y +CONFIG_DRM_PANEL_LG_LG4573=y +CONFIG_DRM_PANEL_NEC_NL8048HL11=y +CONFIG_DRM_PANEL_NEWVISION_NV3052C=y +CONFIG_DRM_PANEL_NOVATEK_NT35510=y +CONFIG_DRM_PANEL_NOVATEK_NT35560=y +CONFIG_DRM_PANEL_NOVATEK_NT35950=y +CONFIG_DRM_PANEL_NOVATEK_NT36672A=y +CONFIG_DRM_PANEL_NOVATEK_NT39016=y +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=y +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=y +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=y +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=y +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_RONBO_RB070D30=y +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=y +CONFIG_DRM_PANEL_SAMSUNG_DB7430=y +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=y +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=y +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set -# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set -# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set -# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set -# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set -# CONFIG_DRM_PANEL_TPO_TPG110 is not set -# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y +CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y +CONFIG_DRM_PANEL_SHARP_LS043T1LE01=y +CONFIG_DRM_PANEL_SHARP_LS060T1SX01=y +CONFIG_DRM_PANEL_SITRONIX_ST7701=y +CONFIG_DRM_PANEL_SITRONIX_ST7703=y +CONFIG_DRM_PANEL_SITRONIX_ST7789V=y +CONFIG_DRM_PANEL_SONY_ACX565AKM=y +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=y +CONFIG_DRM_PANEL_TDO_TL070WSH30=y +CONFIG_DRM_PANEL_TPO_TD028TTEC1=y +CONFIG_DRM_PANEL_TPO_TD043MTEA1=y +CONFIG_DRM_PANEL_TPO_TPG110=y +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y +CONFIG_DRM_PANEL_VISIONOX_RM69299=y +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=y +CONFIG_DRM_PANEL_XINPENG_XPP055C272=y # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -4321,7 +4368,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set -# CONFIG_DRM_DISPLAY_CONNECTOR is not set +CONFIG_DRM_DISPLAY_CONNECTOR=y # CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9211 is not set @@ -4359,6 +4406,7 @@ CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_HDMI_I2S_AUDIO=y # CONFIG_DRM_DW_HDMI_GP_AUDIO is not set CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_DW_MIPI_DSI=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set @@ -4458,7 +4506,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set -# CONFIG_BACKLIGHT_PWM is not set +CONFIG_BACKLIGHT_PWM=y # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set @@ -4484,7 +4532,7 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set # end of Console display driver support @@ -4748,8 +4796,8 @@ CONFIG_SND_SOC_MAX98357A=m # CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set -CONFIG_SND_SOC_RK3328=y -# CONFIG_SND_SOC_RK817 is not set +# CONFIG_SND_SOC_RK3328 is not set +CONFIG_SND_SOC_RK817=m CONFIG_SND_SOC_RL6231=m CONFIG_SND_SOC_RT5514=m CONFIG_SND_SOC_RT5514_SPI=m @@ -4760,7 +4808,7 @@ CONFIG_SND_SOC_RT5645=m # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_RT9120 is not set # CONFIG_SND_SOC_SGTL5000 is not set -# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m # CONFIG_SND_SOC_SIMPLE_MUX is not set CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_SSM2305 is not set @@ -5252,7 +5300,8 @@ CONFIG_TYPEC_FUSB302=m # # USB Type-C Alternate Mode drivers # -# CONFIG_TYPEC_DP_ALTMODE is not set +CONFIG_TYPEC_DP_ALTMODE=y +# CONFIG_TYPEC_NVIDIA_ALTMODE is not set # end of USB Type-C Alternate Mode drivers CONFIG_USB_ROLE_SWITCH=y @@ -5759,7 +5808,7 @@ CONFIG_ARM_MHU=y CONFIG_ARM_MHU_V2=m CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set -CONFIG_ROCKCHIP_MBOX=y +# CONFIG_ROCKCHIP_MBOX is not set # CONFIG_ALTERA_MBOX is not set # CONFIG_MAILBOX_TEST is not set CONFIG_IOMMU_IOVA=y @@ -6461,12 +6510,12 @@ CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_PHY_ROCKCHIP_DP=y # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=y +# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=y # CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set -CONFIG_PHY_ROCKCHIP_PCIE=m +CONFIG_PHY_ROCKCHIP_PCIE=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y # CONFIG_PHY_SAMSUNG_USB2 is not set @@ -7276,6 +7325,7 @@ CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_COMPRESSED is not set # CONFIG_DEBUG_INFO_SPLIT is not set # CONFIG_DEBUG_INFO_BTF is not set +CONFIG_PAHOLE_HAS_SPLIT_BTF=y # CONFIG_GDB_SCRIPTS is not set CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set