Merge pull request #5895 from jernejsk/h3-cec-cleanup

Allwinner: H3: CEC cleanup
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CvH 2021-11-20 19:21:13 +01:00 committed by GitHub
commit da59b2cb2d
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3 changed files with 81 additions and 41 deletions

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@ -101,9 +101,11 @@ CONFIG_BPF_SYSCALL=y
# CONFIG_BPF_PRELOAD is not set # CONFIG_BPF_PRELOAD is not set
# end of BPF subsystem # end of BPF subsystem
CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y
# #
# CPU/Task time and stats accounting # CPU/Task time and stats accounting
@ -123,10 +125,12 @@ CONFIG_CPU_ISOLATION=y
# RCU Subsystem # RCU Subsystem
# #
CONFIG_TREE_RCU=y CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set # CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y CONFIG_SRCU=y
CONFIG_TREE_SRCU=y CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_TRACE_RCU=y CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_NEED_SEGCBLIST=y
@ -742,11 +746,7 @@ CONFIG_MQ_IOSCHED_KYBER=y
# end of IO Schedulers # end of IO Schedulers
CONFIG_ASN1=y CONFIG_ASN1=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y
@ -1288,6 +1288,8 @@ CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y CONFIG_CFG80211_WEXT=y
CONFIG_LIB80211=m CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
# CONFIG_LIB80211_DEBUG is not set # CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_HAS_RC=y
@ -2950,6 +2952,7 @@ CONFIG_CEC_PIN=y
# CONFIG_CEC_PIN_ERROR_INJ is not set # CONFIG_CEC_PIN_ERROR_INJ is not set
CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_MEDIA_CEC_SUPPORT=y
# CONFIG_CEC_CH7322 is not set # CONFIG_CEC_CH7322 is not set
CONFIG_CEC_GPIO=m
CONFIG_USB_PULSE8_CEC=m CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m CONFIG_USB_RAINSHADOW_CEC=m
CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_SUPPORT=y
@ -5628,8 +5631,6 @@ CONFIG_EXFAT_FS=m
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set # CONFIG_NTFS_FS is not set
# CONFIG_NTFS3_FS is not set # CONFIG_NTFS3_FS is not set
# CONFIG_NTFS3_LZX_XPRESS is not set
# CONFIG_NTFS3_FS_POSIX_ACL is not set
# end of DOS/FAT/EXFAT/NT Filesystems # end of DOS/FAT/EXFAT/NT Filesystems
# #
@ -6239,6 +6240,7 @@ CONFIG_PANIC_TIMEOUT=0
# end of Scheduler Debugging # end of Scheduler Debugging
# CONFIG_DEBUG_TIMEKEEPING is not set # CONFIG_DEBUG_TIMEKEEPING is not set
CONFIG_DEBUG_PREEMPT=y
# #
# Lock Debugging (spinlocks, mutexes, etc...) # Lock Debugging (spinlocks, mutexes, etc...)

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@ -1,4 +1,4 @@
From 411f022496f0f9715ca3dc9296f5823cbc0c867c Mon Sep 17 00:00:00 2001 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@gmail.com> From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Mon, 11 Oct 2021 20:13:41 +0200 Date: Mon, 11 Oct 2021 20:13:41 +0200
Subject: [PATCH] HACK: SW CEC implementation for H3 Subject: [PATCH] HACK: SW CEC implementation for H3
@ -9,12 +9,10 @@ instead. That makes it usable, albeit sensitive to cpufreq changes.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
--- ---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- drivers/gpu/drm/sun4i/Kconfig | 2 +
drivers/gpu/drm/sun4i/Kconfig | 2 + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 13 ++++
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 12 ++++ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 83 +++++++++++++++++++++++++-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 76 ++++++++++++++++++++++- 3 files changed, 96 insertions(+), 2 deletions(-)
include/drm/bridge/dw_hdmi.h | 2 +
5 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 5755f0432e77..b93eb2fb52ce 100644 index 5755f0432e77..b93eb2fb52ce 100644
@ -30,7 +28,7 @@ index 5755f0432e77..b93eb2fb52ce 100644
Choose this option if you have an Allwinner SoC with the Choose this option if you have an Allwinner SoC with the
DesignWare HDMI controller with custom HDMI PHY. If M is DesignWare HDMI controller with custom HDMI PHY. If M is
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index bffe1b9cd3dc..438f7398e26d 100644 index bffe1b9cd3dc..61c97619cba1 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -13,6 +13,8 @@ @@ -13,6 +13,8 @@
@ -56,15 +54,7 @@ index bffe1b9cd3dc..438f7398e26d 100644
struct sun8i_hdmi_phy; struct sun8i_hdmi_phy;
@@ -152,6 +161,7 @@ struct sun8i_hdmi_phy_variant { @@ -164,6 +173,8 @@ struct sun8i_hdmi_phy_variant {
bool has_phy_clk;
bool has_second_pll;
unsigned int is_custom_phy : 1;
+ unsigned int bit_bang_cec : 1;
const struct dw_hdmi_curr_ctrl *cur_ctr;
const struct dw_hdmi_mpll_config *mpll_cfg;
const struct dw_hdmi_phy_config *phy_cfg;
@@ -164,6 +174,8 @@ struct sun8i_hdmi_phy_variant {
}; };
struct sun8i_hdmi_phy { struct sun8i_hdmi_phy {
@ -73,8 +63,17 @@ index bffe1b9cd3dc..438f7398e26d 100644
struct clk *clk_bus; struct clk *clk_bus;
struct clk *clk_mod; struct clk *clk_mod;
struct clk *clk_phy; struct clk *clk_phy;
@@ -174,6 +185,8 @@ struct sun8i_hdmi_phy {
struct regmap *regs;
struct reset_control *rst_phy;
struct sun8i_hdmi_phy_variant *variant;
+ unsigned int disable_cec : 1;
+ unsigned int bit_bang_cec : 1;
};
struct sun8i_dw_hdmi_quirks {
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 78b152973957..0d87b56b700a 100644 index b64d93da651d..e2936e7745b8 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -498,8 +498,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) @@ -498,8 +498,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
@ -85,7 +84,7 @@ index 78b152973957..0d87b56b700a 100644
- regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0); - regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
+ /* manual control of CEC pins */ + /* manual control of CEC pins */
+ regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, + regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG,
+ phy->variant->bit_bang_cec ? SUN8I_HDMI_PHY_CEC_PIN_CTRL : 0); + phy->bit_bang_cec ? SUN8I_HDMI_PHY_CEC_PIN_CTRL : 0);
/* read calibration data */ /* read calibration data */
regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
@ -93,7 +92,7 @@ index 78b152973957..0d87b56b700a 100644
plat_data->cur_ctr = variant->cur_ctr; plat_data->cur_ctr = variant->cur_ctr;
plat_data->phy_config = variant->phy_cfg; plat_data->phy_config = variant->phy_cfg;
} }
+ plat_data->disable_cec = phy->variant->bit_bang_cec; + plat_data->disable_cec = phy->disable_cec;
} }
+static int sun8i_hdmi_phy_cec_pin_read(struct cec_adapter *adap) +static int sun8i_hdmi_phy_cec_pin_read(struct cec_adapter *adap)
@ -137,15 +136,7 @@ index 78b152973957..0d87b56b700a 100644
static const struct regmap_config sun8i_hdmi_phy_regmap_config = { static const struct regmap_config sun8i_hdmi_phy_regmap_config = {
.reg_bits = 32, .reg_bits = 32,
.val_bits = 32, .val_bits = 32,
@@ -594,6 +634,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = { @@ -653,6 +693,7 @@ int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
};
static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
+ .bit_bang_cec = true,
.has_phy_clk = true,
.is_custom_phy = true,
.phy_init = &sun8i_hdmi_phy_init_h3,
@@ -653,6 +694,7 @@ int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
{ {
struct platform_device *pdev = of_find_device_by_node(node); struct platform_device *pdev = of_find_device_by_node(node);
struct sun8i_hdmi_phy *phy; struct sun8i_hdmi_phy *phy;
@ -153,12 +144,12 @@ index 78b152973957..0d87b56b700a 100644
if (!pdev) if (!pdev)
return -EPROBE_DEFER; return -EPROBE_DEFER;
@@ -664,8 +706,35 @@ int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node) @@ -664,8 +705,35 @@ int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
hdmi->phy = phy; hdmi->phy = phy;
put_device(&pdev->dev); put_device(&pdev->dev);
+ +
+ if (phy->variant->bit_bang_cec) { + if (phy->bit_bang_cec) {
+ phy->cec_adapter = + phy->cec_adapter =
+ cec_pin_allocate_adapter(&sun8i_hdmi_phy_cec_pin_ops, + cec_pin_allocate_adapter(&sun8i_hdmi_phy_cec_pin_ops,
+ phy, "sun8i-cec", + phy, "sun8i-cec",
@ -189,7 +180,22 @@ index 78b152973957..0d87b56b700a 100644
} }
static int sun8i_hdmi_phy_probe(struct platform_device *pdev) static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
@@ -768,6 +837,9 @@ static int sun8i_hdmi_phy_remove(struct platform_device *pdev) @@ -690,6 +758,14 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
phy->variant = (struct sun8i_hdmi_phy_variant *)match->data;
phy->dev = dev;
+ phy->disable_cec = of_machine_is_compatible("roofull,beelink-x2") ||
+ of_machine_is_compatible("friendlyarm,nanopi-m1") ||
+ of_machine_is_compatible("xunlong,orangepi-lite") ||
+ of_machine_is_compatible("xunlong,orangepi-one") ||
+ of_machine_is_compatible("xunlong,orangepi-pc-plus") ||
+ of_machine_is_compatible("xunlong,orangepi-plus2e");
+ phy->bit_bang_cec = phy->disable_cec &&
+ !of_machine_is_compatible("roofull,beelink-x2");
ret = of_address_to_resource(node, 0, &res);
if (ret) {
@@ -768,6 +844,9 @@ static int sun8i_hdmi_phy_remove(struct platform_device *pdev)
{ {
struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev); struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev);

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@ -0,0 +1,32 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Sat, 20 Nov 2021 10:35:25 +0100
Subject: [PATCH] ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node
Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has
dedicated GPIO pin for that purpose.
Add a node for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index f0e591e1c771..4ab4bbf001ba 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -57,6 +57,12 @@ aliases {
ethernet1 = &sdiowifi;
};
+ cec-gpio {
+ compatible = "cec-gpio";
+ cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
+ hdmi-phandle = <&hdmi>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};