diff --git a/projects/Allwinner/devices/H6/patches/linux/18-OrangePi-Lite2-support.patch b/projects/Allwinner/devices/H6/patches/linux/18-OrangePi-Lite2-support.patch new file mode 100644 index 0000000000..90ed61b4ca --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/18-OrangePi-Lite2-support.patch @@ -0,0 +1,230 @@ +From 9b743eadc7adb8a5ffe79742ea3925d2903788f2 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 4 Apr 2020 20:42:41 +0200 +Subject: [PATCH 1/4] arm64: dts: allwinner: h6: orangepi: Add gpio power + supply + +OrangePi Lite2 and One Plus have GPIO ports powered by same power +supplies. Add them in common DT. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index 9287976c4a50..f1be3dd558ca 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -106,6 +106,12 @@ &ohci3 { + status = "okay"; + }; + ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_aldo1>; ++}; ++ + &r_i2c { + status = "okay"; + +@@ -230,6 +236,10 @@ &r_ir { + status = "okay"; + }; + ++&r_pio { ++ vcc-pm-supply = <®_bldo3>; ++}; ++ + &rtc { + clocks = <&ext_osc32k>; + }; +-- +2.26.0 + + +From d98355dc8de0a3075a49f6ecb103dd67e68ac0c8 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 4 Apr 2020 20:55:52 +0200 +Subject: [PATCH 2/4] arm64: dts: allwinner: h6: orangepi: Disable OTG mode + +As can be seen from OrangePi Lite 2 and One Plus schematics, VBUS pin on +USB OTG port is directly connected to 5 V power supply. This mean that +OTG port can safely operate only in host mode, even though these two +boards have ID pin connected. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index f1be3dd558ca..ebc120a9232f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -251,7 +251,12 @@ &uart0 { + }; + + &usb2otg { +- dr_mode = "otg"; ++ /* ++ * OrangePi Lite 2 and One Plus, where this DT is used, don't ++ * have a controllable VBUS even though they do have an ID pin. ++ * Using it as anything but a USB host is unsafe. ++ */ ++ dr_mode = "host"; + status = "okay"; + }; + +-- +2.26.0 + + +From 0e4de8b92b2cab1e4dbeef5ef2913b745b25c39f Mon Sep 17 00:00:00 2001 +From: Sebastian Meyer +Date: Mon, 3 Feb 2020 21:06:07 +0100 +Subject: [PATCH 3/4] arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI + combo module + +OrangePi Lite2 has AP6255 BT+WIFI combo chip. Add support for it. + +Signed-off-by: Sebastian Meyer +[merged BT and WIFI patches and updated commit message] +Signed-off-by: Jernej Skrabec +--- + .../allwinner/sun50i-h6-orangepi-lite2.dts | 65 +++++++++++++++++++ + 1 file changed, 65 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +index e7ca75c0d0f7..e8770858b5d0 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +@@ -6,4 +6,69 @@ + / { + model = "OrangePi Lite2"; + compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial1 = &uart1; /* BT-UART */ ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_cldo2>; ++ vqmmc-supply = <®_bldo3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcm: sdio-wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++®_cldo2 { ++ /* ++ * This regulator is connected with CLDO3. ++ * Before the kernel can support synchronized ++ * enable of coupled regulators, keep them ++ * both always on as a ugly hack. ++ */ ++ regulator-always-on; ++}; ++ ++®_cldo3 { ++ /* ++ * This regulator is connected with CLDO2. ++ * See the comments for CLDO2. ++ */ ++ regulator-always-on; ++}; ++ ++/* There's the BT part of the AP6255 connected to that UART */ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ ++ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ ++ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ ++ max-speed = <1500000>; ++ }; + }; +-- +2.26.0 + + +From e087c727b23ed0665136973e24a0292c14522723 Mon Sep 17 00:00:00 2001 +From: Sebastian Meyer +Date: Mon, 3 Feb 2020 21:27:47 +0100 +Subject: [PATCH 4/4] arm64: allwinner: h6: Enable USB3 for OrangePi Lite2 + +Signed-off-by: Sebastian Meyer +--- + .../allwinner/sun50i-h6-orangepi-lite2.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +index e8770858b5d0..6ca46b1cabb9 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +@@ -11,6 +11,16 @@ aliases { + serial1 = &uart1; /* BT-UART */ + }; + ++ reg_usb_vbus: vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ startup-delay-us = <100000>; ++ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 USB0-DRVVBUS */ ++ enable-active-high; ++ }; ++ + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; +@@ -20,6 +30,10 @@ wifi_pwrseq: wifi_pwrseq { + }; + }; + ++&dwc3 { ++ status = "okay"; ++}; ++ + &mmc1 { + vmmc-supply = <®_cldo2>; + vqmmc-supply = <®_bldo3>; +@@ -72,3 +86,8 @@ bluetooth { + max-speed = <1500000>; + }; + }; ++ ++&usb3phy { ++ phy-supply = <®_usb_vbus>; ++ status = "okay"; ++}; +-- +2.26.0 +