diff --git a/config/optimize b/config/optimize index f345fcddb0..ffd03af6a4 100644 --- a/config/optimize +++ b/config/optimize @@ -25,4 +25,3 @@ GCC_OPTIM="$GCC_OPTIM -flto" LD_OPTIM="$LD_OPTIM -fuse-linker-plugin" LD_OPTIM="$LD_OPTIM -fuse-ld=gold" LD_OPTIM="$LD_OPTIM -Wl,--as-needed" - diff --git a/config/options b/config/options index 8be7749531..9797a93a60 100644 --- a/config/options +++ b/config/options @@ -6,7 +6,7 @@ else PROJECT="$PROJECT" fi -# determines TARGET_ARCH, if not forced by user (i386 / x86_64 / powerpc) +# determines TARGET_ARCH, if not forced by user (i386 / x86_64 / arm) # default is i386 if [ -z "$ARCH" ]; then TARGET_ARCH="i386" @@ -63,7 +63,6 @@ fi # set jpeg library depending on ARCH if [ "$TARGET_ARCH" = "i386" -o "$TARGET_ARCH" = "x86_64" ]; then LIBJPEG="libjpeg-turbo" -# LIBJPEG="jpeg" else LIBJPEG="jpeg" fi diff --git a/config/path b/config/path index 1fb3ccbb0e..1022476e5a 100644 --- a/config/path +++ b/config/path @@ -2,6 +2,11 @@ set -e # determine architecture's family case $TARGET_ARCH in + arm) + TARGET_FAMILY=arm + TARGET_ABI=eabi + ;; + i386) TARGET_FAMILY=i686 ;; @@ -14,12 +19,16 @@ esac # determines TARGET_CPU, if not forced by user if [ -z "$TARGET_CPU" ]; then case $TARGET_ARCH in + arm) + TARGET_CPU=cortex-a8 + ;; + i386) TARGET_CPU=i686 ;; x86_64) - TARGET_CPU=i686 + TARGET_CPU=core2 ;; esac fi @@ -34,7 +43,7 @@ fi ADDONS=addons HOST_NAME=`$SCRIPTS/configtools/config.guess` -TARGET_NAME=$TARGET_FAMILY-openelec-linux-gnu +TARGET_NAME=${TARGET_FAMILY}-openelec-linux-gnu${TARGET_ABI} BUILD=$BUILD_BASE.$DISTRONAME-$PROJECT.$TARGET_ARCH-$OPENELEC_VERSION TARGET_IMG=$ROOT/$TARGET @@ -115,14 +124,20 @@ TARGET_LDFLAGS="$GCC_OPTIM $LD_OPTIM" case $TARGET_ARCH in i386) TARGET_CFLAGS="$TARGET_CFLAGS -march=$TARGET_CPU -m32" - TARGET_CXXFLAGS="$TARGET_CXXFLAGS -march=$TARGET_CPU -m32" + TARGET_CXXFLAGS="$TARGET_CFLAGS" TARGET_LDFLAGS="$TARGET_LDFLAGS -march=$TARGET_CPU -m32" ;; x86_64) TARGET_CFLAGS="$TARGET_CFLAGS -fPIC -march=$TARGET_CPU -m64" - TARGET_CXXFLAGS="$TARGET_CXXFLAGS -fPIC -march=$TARGET_CPU -m64" + TARGET_CXXFLAGS="$TARGET_CFLAGS" TARGET_LDFLAGS="$TARGET_LDFLAGS -fPIC -march=$TARGET_CPU -m64" ;; + arm) + TARGET_CFLAGS="$TARGET_CFLAGS -fPIC -mcpu=$TARGET_CPU" + [ -n "$TARGET_FPU" ] && TARGET_CFLAGS="$TARGET_CFLAGS -mfpu=$TARGET_FPU" + TARGET_CXXFLAGS="$TARGET_CFLAGS" + TARGET_LDFLAGS="$TARGET_LDFLAGS -fPIC -mcpu=$TARGET_CPU" + ;; esac TARGET_PKG_CONFIG_PATH="" diff --git a/packages/debug/gdb/build b/packages/debug/gdb/build index 1f28cb4147..3ad77c41ba 100755 --- a/packages/debug/gdb/build +++ b/packages/debug/gdb/build @@ -22,6 +22,8 @@ . config/options $1 +strip_lto + export bash_cv_have_mbstate_t=set export CC_FOR_BUILD="$HOST_CC" @@ -38,5 +40,6 @@ mkdir -p objdir && cd objdir --without-x \ --disable-tui \ --disable-libada \ + --disable-werror \ make diff --git a/packages/debug/w_scan/meta b/packages/debug/w_scan/meta index d0ad52d592..f9ceeeb4e4 100644 --- a/packages/debug/w_scan/meta +++ b/packages/debug/w_scan/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="w_scan" -PKG_VERSION="20110206" +PKG_VERSION="20110306" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/debug/w_scan/patches/w_scan-20110206-001-remove_videodev_include-0.1.patch b/packages/debug/w_scan/patches/w_scan-20110206-001-remove_videodev_include-0.1.patch deleted file mode 100644 index 9c3cbbe1f0..0000000000 --- a/packages/debug/w_scan/patches/w_scan-20110206-001-remove_videodev_include-0.1.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Naur w_scan-20110206/countries.c w_scan-20110206.patch/countries.c ---- w_scan-20110206/countries.c 2011-02-05 20:03:50.000000000 +0100 -+++ w_scan-20110206.patch/countries.c 2011-02-21 23:21:51.194553010 +0100 -@@ -31,7 +31,6 @@ - #include - #include - #include --#include - #include - - #ifdef VDRVERSNUM diff --git a/packages/devel/boost/meta b/packages/devel/boost/meta index e6defe90de..4c5fd25bb9 100644 --- a/packages/devel/boost/meta +++ b/packages/devel/boost/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="boost" -PKG_VERSION="1_45_0" +PKG_VERSION="1_46_0" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="OSS" diff --git a/packages/devel/glib/meta b/packages/devel/glib/meta index 983d182651..0ee8aeda04 100644 --- a/packages/devel/glib/meta +++ b/packages/devel/glib/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="glib" -PKG_VERSION="2.28.1" +PKG_VERSION="2.28.2" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="LGPL" diff --git a/packages/devel/glib/patches/glib-2.28.1-linux_magic_h.patch b/packages/devel/glib/patches/glib-2.28.2-linux_magic_h.patch similarity index 100% rename from packages/devel/glib/patches/glib-2.28.1-linux_magic_h.patch rename to packages/devel/glib/patches/glib-2.28.2-linux_magic_h.patch diff --git a/packages/devel/ncurses/meta b/packages/devel/ncurses/meta index e96756f362..a563bfb2a8 100644 --- a/packages/devel/ncurses/meta +++ b/packages/devel/ncurses/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="ncurses" -PKG_VERSION="5.7" +PKG_VERSION="5.8" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="MIT" diff --git a/packages/devel/talloc/install b/packages/devel/talloc/install deleted file mode 100755 index a1da801b91..0000000000 --- a/packages/devel/talloc/install +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. config/options $1 - -mkdir -p $INSTALL/usr/lib - cp -P $PKG_BUILD/libtalloc.so* $INSTALL/usr/lib diff --git a/packages/devel/talloc/meta b/packages/devel/talloc/meta deleted file mode 100644 index eb82f20894..0000000000 --- a/packages/devel/talloc/meta +++ /dev/null @@ -1,36 +0,0 @@ -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -PKG_NAME="talloc" -PKG_VERSION="2.0.1" -PKG_REV="1" -PKG_ARCH="any" -PKG_LICENSE="LGPL" -PKG_SITE="http://www.samba.org" -PKG_URL="http://samba.org/ftp/talloc/$PKG_NAME-$PKG_VERSION.tar.gz" -PKG_DEPENDS="" -PKG_BUILD_DEPENDS="toolchain" -PKG_PRIORITY="optional" -PKG_SECTION="devel" -PKG_SHORTDESC="talloc: talloc is a hierarchical, reference counted memory pool system with destructors." -PKG_LONGDESC="talloc is a hierarchical, reference counted memory pool system with destructors. It is the core memory allocator used in Samba." -PKG_IS_ADDON="no" - -PKG_AUTORECONF="no" diff --git a/packages/graphics/Mesa/meta b/packages/graphics/Mesa/meta index 15f3b757c2..e041d0768a 100644 --- a/packages/graphics/Mesa/meta +++ b/packages/graphics/Mesa/meta @@ -25,8 +25,8 @@ PKG_ARCH="any" PKG_LICENSE="OSS" PKG_SITE="http://www.mesa3d.org/" PKG_URL="ftp://ftp.freedesktop.org/pub/mesa/$PKG_VERSION/MesaLib-$PKG_VERSION.tar.bz2" -PKG_DEPENDS="libXdamage libdrm talloc expat libXext libXfixes libXxf86vm libxcb libX11" -PKG_BUILD_DEPENDS="toolchain Python makedepend libxml2-host talloc expat glproto dri2proto libdrm libXext libXdamage libXfixes libXxf86vm libxcb libX11" +PKG_DEPENDS="libXdamage libdrm expat libXext libXfixes libXxf86vm libxcb libX11" +PKG_BUILD_DEPENDS="toolchain Python makedepend libxml2-host expat glproto dri2proto libdrm libXext libXdamage libXfixes libXxf86vm libxcb libX11" PKG_PRIORITY="optional" PKG_SECTION="graphics" PKG_SHORTDESC="mesa: 3-D graphics library with OpenGL API" @@ -36,6 +36,6 @@ PKG_IS_ADDON="no" PKG_AUTORECONF="yes" if [ "$MESA_MASTER" = "yes" ]; then - PKG_VERSION="20110110" + PKG_VERSION="0f84dda" PKG_URL="$OPENELEC_SRC/$PKG_NAME-$PKG_VERSION.tar.bz2" fi diff --git a/packages/graphics/Mesa/patches/Mesa-7.10.1-__atom.patch b/packages/graphics/Mesa/patches/Mesa-7.10.1-__atom.patch new file mode 100644 index 0000000000..1787a37369 --- /dev/null +++ b/packages/graphics/Mesa/patches/Mesa-7.10.1-__atom.patch @@ -0,0 +1,15 @@ +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/r200/r200_cmdbuf.c Mesa-7.10.1-new/src/mesa/drivers/dri/r200/r200_cmdbuf.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/r200/r200_cmdbuf.c 2011-03-02 17:30:39.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/r200/r200_cmdbuf.c 2011-03-02 17:31:59.000000000 -0800 +@@ -47,9 +47,8 @@ + */ + #define insert_at_tail_if(atom_list, atom) \ + do { \ +- struct radeon_state_atom* __atom = (atom); \ +- if (__atom->check) \ +- insert_at_tail((atom_list), __atom); \ ++ if ((atom)->check) \ ++ insert_at_tail((atom_list), (atom)); \ + } while(0) + + void r200SetUpAtomList( r200ContextPtr rmesa ) diff --git a/packages/graphics/Mesa/patches/Mesa-7.10.1-libdrm_nouveau.patch b/packages/graphics/Mesa/patches/Mesa-7.10.1-libdrm_nouveau.patch new file mode 100644 index 0000000000..445e9170b3 --- /dev/null +++ b/packages/graphics/Mesa/patches/Mesa-7.10.1-libdrm_nouveau.patch @@ -0,0 +1,208 @@ +diff -Naur Mesa-7.10.1-old/src/gallium/drivers/nv50/nv50_context.h Mesa-7.10.1-new/src/gallium/drivers/nv50/nv50_context.h +--- Mesa-7.10.1-old/src/gallium/drivers/nv50/nv50_context.h 2010-12-15 15:02:44.000000000 -0800 ++++ Mesa-7.10.1-new/src/gallium/drivers/nv50/nv50_context.h 2011-03-02 17:31:09.000000000 -0800 +@@ -15,6 +15,8 @@ + + #include "nouveau/nouveau_winsys.h" + #include "nouveau/nouveau_gldefs.h" ++/* Hack to silence warnings caused by nouveau/nouveau_stateobj.h using BEGIN_BIND marcro */ ++#include + #include "nouveau/nouveau_stateobj.h" + #include "nv50_reg.h" + +diff -Naur Mesa-7.10.1-old/src/gallium/drivers/nvfx/nv04_2d.c Mesa-7.10.1-new/src/gallium/drivers/nvfx/nv04_2d.c +--- Mesa-7.10.1-old/src/gallium/drivers/nvfx/nv04_2d.c 2011-01-25 15:52:45.000000000 -0800 ++++ Mesa-7.10.1-new/src/gallium/drivers/nvfx/nv04_2d.c 2011-03-02 17:31:09.000000000 -0800 +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + #include "nv04_2d.h" + + #include "nouveau/nv_object.xml.h" +diff -Naur Mesa-7.10.1-old/src/gallium/drivers/nvfx/nvfx_buffer.c Mesa-7.10.1-new/src/gallium/drivers/nvfx/nvfx_buffer.c +--- Mesa-7.10.1-old/src/gallium/drivers/nvfx/nvfx_buffer.c 2010-12-15 15:02:44.000000000 -0800 ++++ Mesa-7.10.1-new/src/gallium/drivers/nvfx/nvfx_buffer.c 2011-03-02 17:31:09.000000000 -0800 +@@ -1,4 +1,3 @@ +- + #include "util/u_inlines.h" + #include "util/u_memory.h" + #include "util/u_math.h" +diff -Naur Mesa-7.10.1-old/src/gallium/drivers/nvfx/nvfx_screen.c Mesa-7.10.1-new/src/gallium/drivers/nvfx/nvfx_screen.c +--- Mesa-7.10.1-old/src/gallium/drivers/nvfx/nvfx_screen.c 2011-01-25 15:52:45.000000000 -0800 ++++ Mesa-7.10.1-new/src/gallium/drivers/nvfx/nvfx_screen.c 2011-03-02 17:31:09.000000000 -0800 +@@ -10,6 +10,8 @@ + #include "nvfx_resource.h" + #include "nvfx_tex.h" + ++#include "nouveau/nv04_pushbuf.h" ++ + #define NV30_3D_CHIPSET_3X_MASK 0x00000003 + #define NV34_3D_CHIPSET_3X_MASK 0x00000010 + #define NV35_3D_CHIPSET_3X_MASK 0x000001e0 +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv04_driver.h Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv04_driver.h +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv04_driver.h 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv04_driver.h 2011-03-02 17:31:09.000000000 -0800 +@@ -28,6 +28,7 @@ + #define __NV04_DRIVER_H__ + + #include "nv04_context.h" ++#include "nv04_pushbuf.h" + + enum { + NOUVEAU_STATE_BLEND = NUM_NOUVEAU_STATE, +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_render.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_render.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_render.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_render.c 2011-03-02 17:31:09.000000000 -0800 +@@ -27,6 +27,7 @@ + #include "nouveau_driver.h" + #include "nouveau_context.h" + #include "nv10_3d.xml.h" ++#include "nv04_driver.h" + #include "nv10_driver.h" + + #define NUM_VERTEX_ATTRS 8 +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_fb.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_fb.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_fb.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_fb.c 2011-03-02 17:31:09.000000000 -0800 +@@ -30,6 +30,7 @@ + #include "nouveau_util.h" + #include "nv_object.xml.h" + #include "nv10_3d.xml.h" ++#include "nv04_driver.h" + #include "nv10_driver.h" + + static inline unsigned +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_frag.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_frag.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_frag.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_frag.c 2011-03-02 17:31:09.000000000 -0800 +@@ -30,6 +30,7 @@ + #include "nv10_3d.xml.h" + #include "nouveau_util.h" + #include "nv10_driver.h" ++#include "nv04_driver.h" + #include "nv20_driver.h" + + #define RC_IN_SHIFT_A 24 +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c 2011-03-02 17:31:09.000000000 -0800 +@@ -29,6 +29,7 @@ + #include "nouveau_gldefs.h" + #include "nouveau_util.h" + #include "nv10_3d.xml.h" ++#include "nv04_driver.h" + #include "nv10_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_raster.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_raster.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_raster.c 2011-01-25 15:52:45.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_raster.c 2011-03-02 17:31:09.000000000 -0800 +@@ -29,6 +29,7 @@ + #include "nouveau_gldefs.h" + #include "nouveau_util.h" + #include "nv10_3d.xml.h" ++#include "nv04_driver.h" + #include "nv10_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_tex.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_tex.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_tex.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_tex.c 2011-03-02 17:31:09.000000000 -0800 +@@ -30,6 +30,7 @@ + #include "nouveau_texture.h" + #include "nv10_3d.xml.h" + #include "nouveau_util.h" ++#include "nv04_driver.h" + #include "nv10_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c 2011-03-02 17:31:09.000000000 -0800 +@@ -29,6 +29,7 @@ + #include "nouveau_gldefs.h" + #include "nouveau_util.h" + #include "nv10_3d.xml.h" ++#include "nv04_driver.h" + #include "nv10_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_render.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_render.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_render.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_render.c 2011-03-02 17:31:09.000000000 -0800 +@@ -27,6 +27,7 @@ + #include "nouveau_driver.h" + #include "nouveau_context.h" + #include "nv20_3d.xml.h" ++#include "nv04_driver.h" + #include "nv20_driver.h" + + #define NUM_VERTEX_ATTRS 16 +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_fb.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_fb.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_fb.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_fb.c 2011-03-02 17:31:09.000000000 -0800 +@@ -30,6 +30,7 @@ + #include "nouveau_gldefs.h" + #include "nouveau_util.h" + #include "nv20_3d.xml.h" ++#include "nv04_driver.h" + #include "nv20_driver.h" + + static inline unsigned +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_frag.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_frag.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_frag.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_frag.c 2011-03-02 17:31:09.000000000 -0800 +@@ -28,6 +28,7 @@ + #include "nouveau_context.h" + #include "nv20_3d.xml.h" + #include "nv10_driver.h" ++#include "nv04_driver.h" + #include "nv20_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c 2011-03-02 17:31:09.000000000 -0800 +@@ -28,6 +28,7 @@ + #include "nouveau_context.h" + #include "nouveau_gldefs.h" + #include "nv20_3d.xml.h" ++#include "nv04_driver.h" + #include "nv20_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_raster.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_raster.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_raster.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_raster.c 2011-03-02 17:31:09.000000000 -0800 +@@ -29,6 +29,7 @@ + #include "nouveau_gldefs.h" + #include "nouveau_util.h" + #include "nv20_3d.xml.h" ++#include "nv04_driver.h" + #include "nv20_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_tex.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_tex.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_tex.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_tex.c 2011-03-02 17:31:09.000000000 -0800 +@@ -30,6 +30,7 @@ + #include "nouveau_texture.h" + #include "nv20_3d.xml.h" + #include "nouveau_util.h" ++#include "nv04_driver.h" + #include "nv20_driver.h" + + void +diff -Naur Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c +--- Mesa-7.10.1-old/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c 2010-12-14 13:43:15.000000000 -0800 ++++ Mesa-7.10.1-new/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c 2011-03-02 17:31:09.000000000 -0800 +@@ -29,6 +29,7 @@ + #include "nouveau_gldefs.h" + #include "nouveau_util.h" + #include "nv20_3d.xml.h" ++#include "nv04_driver.h" + #include "nv10_driver.h" + #include "nv20_driver.h" + diff --git a/packages/graphics/libdrm/meta b/packages/graphics/libdrm/meta index bee3010ff4..6fa2e829ca 100644 --- a/packages/graphics/libdrm/meta +++ b/packages/graphics/libdrm/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="libdrm" -PKG_VERSION="2.4.23" +PKG_VERSION="2.4.24" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/graphics/libjpeg-turbo/meta b/packages/graphics/libjpeg-turbo/meta index 5716ed732c..c1fd149641 100644 --- a/packages/graphics/libjpeg-turbo/meta +++ b/packages/graphics/libjpeg-turbo/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="libjpeg-turbo" -PKG_VERSION="1.0.1" +PKG_VERSION="1.1.0" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/linux-firmware/wlan-firmware/meta b/packages/linux-firmware/wlan-firmware/meta index 55d96a0dd3..423dd66029 100644 --- a/packages/linux-firmware/wlan-firmware/meta +++ b/packages/linux-firmware/wlan-firmware/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="wlan-firmware" -PKG_VERSION="0.0.1" +PKG_VERSION="0.0.2" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="Free-to-use" diff --git a/packages/linux/build b/packages/linux/build index 38e5d374dd..84ad3d5c16 100755 --- a/packages/linux/build +++ b/packages/linux/build @@ -25,8 +25,18 @@ export INSTALL=$(kernel_path) $SCRIPTS/install busybox-initramfs +if [ "$BOOTLOADER" = "u-boot" ]; then + $SCRIPTS/build u-boot + KERNEL_IMAGE="uImage" +else + KERNEL_IMAGE="bzImage" +fi + unset LDFLAGS +# dont build parallel + MAKEFLAGS=-j1 + cd $(kernel_path) rm -rf modules mkdir -p modules @@ -36,5 +46,5 @@ make INSTALL_MOD_PATH=modules DEPMOD="$ROOT/$TOOLCHAIN/sbin/depmod" modules_inst rm -f modules/lib/modules/*/build rm -f modules/lib/modules/*/source -make bzImage +make $KERNEL_IMAGE diff --git a/packages/linux/meta b/packages/linux/meta index d2dcca2f1b..7ef67b2fae 100644 --- a/packages/linux/meta +++ b/packages/linux/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="linux" -PKG_VERSION="2.6.38-rc7" +PKG_VERSION="2.6.38-rc8" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" @@ -37,6 +37,6 @@ PKG_IS_ADDON="no" PKG_AUTORECONF="no" if [ "$LINUX_NEXT" = "yes" ]; then - PKG_VERSION="2.6.37" + PKG_VERSION="2.6.38-rc7" PKG_URL="http://www.kernel.org/pub/linux/kernel/v2.6/testing/$PKG_NAME-$PKG_VERSION.tar.bz2" fi diff --git a/packages/linux/patches/linux-2.6.38-rc7-700_701-730_BFS_patches.txt b/packages/linux/patches/linux-2.6.38-rc7-700_701-730_BFS_patches.txt deleted file mode 100644 index 61f91594ef..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-700_701-730_BFS_patches.txt +++ /dev/null @@ -1,20 +0,0 @@ -http://www.kernel.org/pub/linux/kernel/people/ck/patches/2.6/2.6.37/2.6.37-ck2/patches/ - -2.6.37-sched-bfs-363.patch -2637-bfs363-nonhotplug_fix.patch -sched-add-above-background-load-function.patch -mm-zero_swappiness.patch -mm-enable_swaptoken_only_when_swap_full.patch -mm-drop_swap_cache_aggressively.patch -mm-kswapd_inherit_prio-1.patch -mm-background_scan.patch -mm-idleprio_prio-1.patch -mm-lru_cache_add_lru_tail.patch -mm-decrease_default_dirty_ratio.patch -kconfig-expose_vmsplit_option.patch -hz-default_1000.patch -hz-no_default_250.patch -hz-raise_max.patch -preempt-desktop-tune.patch -cpufreq-bfs_tweaks.patch -ck2-version.patch \ No newline at end of file diff --git a/packages/linux/patches/linux-2.6.38-rc7-701_sched-bfs-363.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-701_sched-bfs-363.patch.disabled deleted file mode 100644 index 77a4076fdc..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-701_sched-bfs-363.patch.disabled +++ /dev/null @@ -1,8243 +0,0 @@ -The Brain Fuck Scheduler v0.363 by Con Kolivas. - -A single shared runqueue O(n) strict fairness earliest deadline first design. - -Ultra low latency and excellent desktop performance for 1 to many CPUs. -Not recommended for 4096 cpus. - -Scalability is optimal when your workload is equal to the number of CPUs on -bfs. ie you should ONLY do make -j4 on quad core, -j2 on dual core and so on. - -Features SCHED_IDLEPRIO and SCHED_ISO scheduling policies as well. -You do NOT need to use these policies for good performance, they are purely -optional for even better performance in extreme conditions. - -To run something idleprio, use schedtool like so: - -schedtool -D -e make -j4 - -To run something isoprio, use schedtool like so: - -schedtool -I -e amarok - -Includes accurate sub-tick accounting of tasks so userspace reported -cpu usage may be very different if you have very short lived tasks. - --ck - ---- - Documentation/scheduler/sched-BFS.txt | 351 + - Documentation/sysctl/kernel.txt | 26 - arch/powerpc/platforms/cell/spufs/sched.c | 5 - fs/proc/base.c | 2 - include/linux/init_task.h | 63 - include/linux/ioprio.h | 2 - include/linux/jiffies.h | 2 - include/linux/sched.h | 91 - init/Kconfig | 16 - init/main.c | 1 - kernel/delayacct.c | 2 - kernel/exit.c | 2 - kernel/kthread.c | 2 - kernel/posix-cpu-timers.c | 14 - kernel/sched.c | 4 - kernel/sched_bfs.c | 7223 ++++++++++++++++++++++++++++++ - kernel/sysctl.c | 31 - lib/Kconfig.debug | 2 - 18 files changed, 7812 insertions(+), 27 deletions(-) - -Index: linux-2.6.37-ck2/arch/powerpc/platforms/cell/spufs/sched.c -=================================================================== ---- linux-2.6.37-ck2.orig/arch/powerpc/platforms/cell/spufs/sched.c 2010-05-17 18:51:19.000000000 +1000 -+++ linux-2.6.37-ck2/arch/powerpc/platforms/cell/spufs/sched.c 2011-02-14 09:47:50.982252001 +1100 -@@ -64,11 +64,6 @@ - static struct timer_list spuloadavg_timer; - - /* -- * Priority of a normal, non-rt, non-niced'd process (aka nice level 0). -- */ --#define NORMAL_PRIO 120 -- --/* - * Frequency of the spu scheduler tick. By default we do one SPU scheduler - * tick for every 10 CPU scheduler ticks. - */ -Index: linux-2.6.37-ck2/Documentation/scheduler/sched-BFS.txt -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.37-ck2/Documentation/scheduler/sched-BFS.txt 2011-02-14 09:47:50.984252001 +1100 -@@ -0,0 +1,351 @@ -+BFS - The Brain Fuck Scheduler by Con Kolivas. -+ -+Goals. -+ -+The goal of the Brain Fuck Scheduler, referred to as BFS from here on, is to -+completely do away with the complex designs of the past for the cpu process -+scheduler and instead implement one that is very simple in basic design. -+The main focus of BFS is to achieve excellent desktop interactivity and -+responsiveness without heuristics and tuning knobs that are difficult to -+understand, impossible to model and predict the effect of, and when tuned to -+one workload cause massive detriment to another. -+ -+ -+Design summary. -+ -+BFS is best described as a single runqueue, O(n) lookup, earliest effective -+virtual deadline first design, loosely based on EEVDF (earliest eligible virtual -+deadline first) and my previous Staircase Deadline scheduler. Each component -+shall be described in order to understand the significance of, and reasoning for -+it. The codebase when the first stable version was released was approximately -+9000 lines less code than the existing mainline linux kernel scheduler (in -+2.6.31). This does not even take into account the removal of documentation and -+the cgroups code that is not used. -+ -+Design reasoning. -+ -+The single runqueue refers to the queued but not running processes for the -+entire system, regardless of the number of CPUs. The reason for going back to -+a single runqueue design is that once multiple runqueues are introduced, -+per-CPU or otherwise, there will be complex interactions as each runqueue will -+be responsible for the scheduling latency and fairness of the tasks only on its -+own runqueue, and to achieve fairness and low latency across multiple CPUs, any -+advantage in throughput of having CPU local tasks causes other disadvantages. -+This is due to requiring a very complex balancing system to at best achieve some -+semblance of fairness across CPUs and can only maintain relatively low latency -+for tasks bound to the same CPUs, not across them. To increase said fairness -+and latency across CPUs, the advantage of local runqueue locking, which makes -+for better scalability, is lost due to having to grab multiple locks. -+ -+A significant feature of BFS is that all accounting is done purely based on CPU -+used and nowhere is sleep time used in any way to determine entitlement or -+interactivity. Interactivity "estimators" that use some kind of sleep/run -+algorithm are doomed to fail to detect all interactive tasks, and to falsely tag -+tasks that aren't interactive as being so. The reason for this is that it is -+close to impossible to determine that when a task is sleeping, whether it is -+doing it voluntarily, as in a userspace application waiting for input in the -+form of a mouse click or otherwise, or involuntarily, because it is waiting for -+another thread, process, I/O, kernel activity or whatever. Thus, such an -+estimator will introduce corner cases, and more heuristics will be required to -+cope with those corner cases, introducing more corner cases and failed -+interactivity detection and so on. Interactivity in BFS is built into the design -+by virtue of the fact that tasks that are waking up have not used up their quota -+of CPU time, and have earlier effective deadlines, thereby making it very likely -+they will preempt any CPU bound task of equivalent nice level. See below for -+more information on the virtual deadline mechanism. Even if they do not preempt -+a running task, because the rr interval is guaranteed to have a bound upper -+limit on how long a task will wait for, it will be scheduled within a timeframe -+that will not cause visible interface jitter. -+ -+ -+Design details. -+ -+Task insertion. -+ -+BFS inserts tasks into each relevant queue as an O(1) insertion into a double -+linked list. On insertion, *every* running queue is checked to see if the newly -+queued task can run on any idle queue, or preempt the lowest running task on the -+system. This is how the cross-CPU scheduling of BFS achieves significantly lower -+latency per extra CPU the system has. In this case the lookup is, in the worst -+case scenario, O(n) where n is the number of CPUs on the system. -+ -+Data protection. -+ -+BFS has one single lock protecting the process local data of every task in the -+global queue. Thus every insertion, removal and modification of task data in the -+global runqueue needs to grab the global lock. However, once a task is taken by -+a CPU, the CPU has its own local data copy of the running process' accounting -+information which only that CPU accesses and modifies (such as during a -+timer tick) thus allowing the accounting data to be updated lockless. Once a -+CPU has taken a task to run, it removes it from the global queue. Thus the -+global queue only ever has, at most, -+ -+ (number of tasks requesting cpu time) - (number of logical CPUs) + 1 -+ -+tasks in the global queue. This value is relevant for the time taken to look up -+tasks during scheduling. This will increase if many tasks with CPU affinity set -+in their policy to limit which CPUs they're allowed to run on if they outnumber -+the number of CPUs. The +1 is because when rescheduling a task, the CPU's -+currently running task is put back on the queue. Lookup will be described after -+the virtual deadline mechanism is explained. -+ -+Virtual deadline. -+ -+The key to achieving low latency, scheduling fairness, and "nice level" -+distribution in BFS is entirely in the virtual deadline mechanism. The one -+tunable in BFS is the rr_interval, or "round robin interval". This is the -+maximum time two SCHED_OTHER (or SCHED_NORMAL, the common scheduling policy) -+tasks of the same nice level will be running for, or looking at it the other -+way around, the longest duration two tasks of the same nice level will be -+delayed for. When a task requests cpu time, it is given a quota (time_slice) -+equal to the rr_interval and a virtual deadline. The virtual deadline is -+offset from the current time in jiffies by this equation: -+ -+ jiffies + (prio_ratio * rr_interval) -+ -+The prio_ratio is determined as a ratio compared to the baseline of nice -20 -+and increases by 10% per nice level. The deadline is a virtual one only in that -+no guarantee is placed that a task will actually be scheduled by this time, but -+it is used to compare which task should go next. There are three components to -+how a task is next chosen. First is time_slice expiration. If a task runs out -+of its time_slice, it is descheduled, the time_slice is refilled, and the -+deadline reset to that formula above. Second is sleep, where a task no longer -+is requesting CPU for whatever reason. The time_slice and deadline are _not_ -+adjusted in this case and are just carried over for when the task is next -+scheduled. Third is preemption, and that is when a newly waking task is deemed -+higher priority than a currently running task on any cpu by virtue of the fact -+that it has an earlier virtual deadline than the currently running task. The -+earlier deadline is the key to which task is next chosen for the first and -+second cases. Once a task is descheduled, it is put back on the queue, and an -+O(n) lookup of all queued-but-not-running tasks is done to determine which has -+the earliest deadline and that task is chosen to receive CPU next. -+ -+The CPU proportion of different nice tasks works out to be approximately the -+ -+ (prio_ratio difference)^2 -+ -+The reason it is squared is that a task's deadline does not change while it is -+running unless it runs out of time_slice. Thus, even if the time actually -+passes the deadline of another task that is queued, it will not get CPU time -+unless the current running task deschedules, and the time "base" (jiffies) is -+constantly moving. -+ -+Task lookup. -+ -+BFS has 103 priority queues. 100 of these are dedicated to the static priority -+of realtime tasks, and the remaining 3 are, in order of best to worst priority, -+SCHED_ISO (isochronous), SCHED_NORMAL, and SCHED_IDLEPRIO (idle priority -+scheduling). When a task of these priorities is queued, a bitmap of running -+priorities is set showing which of these priorities has tasks waiting for CPU -+time. When a CPU is made to reschedule, the lookup for the next task to get -+CPU time is performed in the following way: -+ -+First the bitmap is checked to see what static priority tasks are queued. If -+any realtime priorities are found, the corresponding queue is checked and the -+first task listed there is taken (provided CPU affinity is suitable) and lookup -+is complete. If the priority corresponds to a SCHED_ISO task, they are also -+taken in FIFO order (as they behave like SCHED_RR). If the priority corresponds -+to either SCHED_NORMAL or SCHED_IDLEPRIO, then the lookup becomes O(n). At this -+stage, every task in the runlist that corresponds to that priority is checked -+to see which has the earliest set deadline, and (provided it has suitable CPU -+affinity) it is taken off the runqueue and given the CPU. If a task has an -+expired deadline, it is taken and the rest of the lookup aborted (as they are -+chosen in FIFO order). -+ -+Thus, the lookup is O(n) in the worst case only, where n is as described -+earlier, as tasks may be chosen before the whole task list is looked over. -+ -+ -+Scalability. -+ -+The major limitations of BFS will be that of scalability, as the separate -+runqueue designs will have less lock contention as the number of CPUs rises. -+However they do not scale linearly even with separate runqueues as multiple -+runqueues will need to be locked concurrently on such designs to be able to -+achieve fair CPU balancing, to try and achieve some sort of nice-level fairness -+across CPUs, and to achieve low enough latency for tasks on a busy CPU when -+other CPUs would be more suited. BFS has the advantage that it requires no -+balancing algorithm whatsoever, as balancing occurs by proxy simply because -+all CPUs draw off the global runqueue, in priority and deadline order. Despite -+the fact that scalability is _not_ the prime concern of BFS, it both shows very -+good scalability to smaller numbers of CPUs and is likely a more scalable design -+at these numbers of CPUs. -+ -+It also has some very low overhead scalability features built into the design -+when it has been deemed their overhead is so marginal that they're worth adding. -+The first is the local copy of the running process' data to the CPU it's running -+on to allow that data to be updated lockless where possible. Then there is -+deference paid to the last CPU a task was running on, by trying that CPU first -+when looking for an idle CPU to use the next time it's scheduled. Finally there -+is the notion of cache locality beyond the last running CPU. The sched_domains -+information is used to determine the relative virtual "cache distance" that -+other CPUs have from the last CPU a task was running on. CPUs with shared -+caches, such as SMT siblings, or multicore CPUs with shared caches, are treated -+as cache local. CPUs without shared caches are treated as not cache local, and -+CPUs on different NUMA nodes are treated as very distant. This "relative cache -+distance" is used by modifying the virtual deadline value when doing lookups. -+Effectively, the deadline is unaltered between "cache local" CPUs, doubled for -+"cache distant" CPUs, and quadrupled for "very distant" CPUs. The reasoning -+behind the doubling of deadlines is as follows. The real cost of migrating a -+task from one CPU to another is entirely dependant on the cache footprint of -+the task, how cache intensive the task is, how long it's been running on that -+CPU to take up the bulk of its cache, how big the CPU cache is, how fast and -+how layered the CPU cache is, how fast a context switch is... and so on. In -+other words, it's close to random in the real world where we do more than just -+one sole workload. The only thing we can be sure of is that it's not free. So -+BFS uses the principle that an idle CPU is a wasted CPU and utilising idle CPUs -+is more important than cache locality, and cache locality only plays a part -+after that. Doubling the effective deadline is based on the premise that the -+"cache local" CPUs will tend to work on the same tasks up to double the number -+of cache local CPUs, and once the workload is beyond that amount, it is likely -+that none of the tasks are cache warm anywhere anyway. The quadrupling for NUMA -+is a value I pulled out of my arse. -+ -+When choosing an idle CPU for a waking task, the cache locality is determined -+according to where the task last ran and then idle CPUs are ranked from best -+to worst to choose the most suitable idle CPU based on cache locality, NUMA -+node locality and hyperthread sibling business. They are chosen in the -+following preference (if idle): -+ -+* Same core, idle or busy cache, idle threads -+* Other core, same cache, idle or busy cache, idle threads. -+* Same node, other CPU, idle cache, idle threads. -+* Same node, other CPU, busy cache, idle threads. -+* Same core, busy threads. -+* Other core, same cache, busy threads. -+* Same node, other CPU, busy threads. -+* Other node, other CPU, idle cache, idle threads. -+* Other node, other CPU, busy cache, idle threads. -+* Other node, other CPU, busy threads. -+ -+This shows the SMT or "hyperthread" awareness in the design as well which will -+choose a real idle core first before a logical SMT sibling which already has -+tasks on the physical CPU. -+ -+Early benchmarking of BFS suggested scalability dropped off at the 16 CPU mark. -+However this benchmarking was performed on an earlier design that was far less -+scalable than the current one so it's hard to know how scalable it is in terms -+of both CPUs (due to the global runqueue) and heavily loaded machines (due to -+O(n) lookup) at this stage. Note that in terms of scalability, the number of -+_logical_ CPUs matters, not the number of _physical_ CPUs. Thus, a dual (2x) -+quad core (4X) hyperthreaded (2X) machine is effectively a 16X. Newer benchmark -+results are very promising indeed, without needing to tweak any knobs, features -+or options. Benchmark contributions are most welcome. -+ -+ -+Features -+ -+As the initial prime target audience for BFS was the average desktop user, it -+was designed to not need tweaking, tuning or have features set to obtain benefit -+from it. Thus the number of knobs and features has been kept to an absolute -+minimum and should not require extra user input for the vast majority of cases. -+There are precisely 2 tunables, and 2 extra scheduling policies. The rr_interval -+and iso_cpu tunables, and the SCHED_ISO and SCHED_IDLEPRIO policies. In addition -+to this, BFS also uses sub-tick accounting. What BFS does _not_ now feature is -+support for CGROUPS. The average user should neither need to know what these -+are, nor should they need to be using them to have good desktop behaviour. -+ -+rr_interval -+ -+There is only one "scheduler" tunable, the round robin interval. This can be -+accessed in -+ -+ /proc/sys/kernel/rr_interval -+ -+The value is in milliseconds, and the default value is set to 6 on a -+uniprocessor machine, and automatically set to a progressively higher value on -+multiprocessor machines. The reasoning behind increasing the value on more CPUs -+is that the effective latency is decreased by virtue of there being more CPUs on -+BFS (for reasons explained above), and increasing the value allows for less -+cache contention and more throughput. Valid values are from 1 to 1000 -+Decreasing the value will decrease latencies at the cost of decreasing -+throughput, while increasing it will improve throughput, but at the cost of -+worsening latencies. The accuracy of the rr interval is limited by HZ resolution -+of the kernel configuration. Thus, the worst case latencies are usually slightly -+higher than this actual value. The default value of 6 is not an arbitrary one. -+It is based on the fact that humans can detect jitter at approximately 7ms, so -+aiming for much lower latencies is pointless under most circumstances. It is -+worth noting this fact when comparing the latency performance of BFS to other -+schedulers. Worst case latencies being higher than 7ms are far worse than -+average latencies not being in the microsecond range. -+ -+Isochronous scheduling. -+ -+Isochronous scheduling is a unique scheduling policy designed to provide -+near-real-time performance to unprivileged (ie non-root) users without the -+ability to starve the machine indefinitely. Isochronous tasks (which means -+"same time") are set using, for example, the schedtool application like so: -+ -+ schedtool -I -e amarok -+ -+This will start the audio application "amarok" as SCHED_ISO. How SCHED_ISO works -+is that it has a priority level between true realtime tasks and SCHED_NORMAL -+which would allow them to preempt all normal tasks, in a SCHED_RR fashion (ie, -+if multiple SCHED_ISO tasks are running, they purely round robin at rr_interval -+rate). However if ISO tasks run for more than a tunable finite amount of time, -+they are then demoted back to SCHED_NORMAL scheduling. This finite amount of -+time is the percentage of _total CPU_ available across the machine, configurable -+as a percentage in the following "resource handling" tunable (as opposed to a -+scheduler tunable): -+ -+ /proc/sys/kernel/iso_cpu -+ -+and is set to 70% by default. It is calculated over a rolling 5 second average -+Because it is the total CPU available, it means that on a multi CPU machine, it -+is possible to have an ISO task running as realtime scheduling indefinitely on -+just one CPU, as the other CPUs will be available. Setting this to 100 is the -+equivalent of giving all users SCHED_RR access and setting it to 0 removes the -+ability to run any pseudo-realtime tasks. -+ -+A feature of BFS is that it detects when an application tries to obtain a -+realtime policy (SCHED_RR or SCHED_FIFO) and the caller does not have the -+appropriate privileges to use those policies. When it detects this, it will -+give the task SCHED_ISO policy instead. Thus it is transparent to the user. -+Because some applications constantly set their policy as well as their nice -+level, there is potential for them to undo the override specified by the user -+on the command line of setting the policy to SCHED_ISO. To counter this, once -+a task has been set to SCHED_ISO policy, it needs superuser privileges to set -+it back to SCHED_NORMAL. This will ensure the task remains ISO and all child -+processes and threads will also inherit the ISO policy. -+ -+Idleprio scheduling. -+ -+Idleprio scheduling is a scheduling policy designed to give out CPU to a task -+_only_ when the CPU would be otherwise idle. The idea behind this is to allow -+ultra low priority tasks to be run in the background that have virtually no -+effect on the foreground tasks. This is ideally suited to distributed computing -+clients (like setiathome, folding, mprime etc) but can also be used to start -+a video encode or so on without any slowdown of other tasks. To avoid this -+policy from grabbing shared resources and holding them indefinitely, if it -+detects a state where the task is waiting on I/O, the machine is about to -+suspend to ram and so on, it will transiently schedule them as SCHED_NORMAL. As -+per the Isochronous task management, once a task has been scheduled as IDLEPRIO, -+it cannot be put back to SCHED_NORMAL without superuser privileges. Tasks can -+be set to start as SCHED_IDLEPRIO with the schedtool command like so: -+ -+ schedtool -D -e ./mprime -+ -+Subtick accounting. -+ -+It is surprisingly difficult to get accurate CPU accounting, and in many cases, -+the accounting is done by simply determining what is happening at the precise -+moment a timer tick fires off. This becomes increasingly inaccurate as the -+timer tick frequency (HZ) is lowered. It is possible to create an application -+which uses almost 100% CPU, yet by being descheduled at the right time, records -+zero CPU usage. While the main problem with this is that there are possible -+security implications, it is also difficult to determine how much CPU a task -+really does use. BFS tries to use the sub-tick accounting from the TSC clock, -+where possible, to determine real CPU usage. This is not entirely reliable, but -+is far more likely to produce accurate CPU usage data than the existing designs -+and will not show tasks as consuming no CPU usage when they actually are. Thus, -+the amount of CPU reported as being used by BFS will more accurately represent -+how much CPU the task itself is using (as is shown for example by the 'time' -+application), so the reported values may be quite different to other schedulers. -+Values reported as the 'load' are more prone to problems with this design, but -+per process values are closer to real usage. When comparing throughput of BFS -+to other designs, it is important to compare the actual completed work in terms -+of total wall clock time taken and total work done, rather than the reported -+"cpu usage". -+ -+ -+Con Kolivas Fri Aug 27 2010 -Index: linux-2.6.37-ck2/Documentation/sysctl/kernel.txt -=================================================================== ---- linux-2.6.37-ck2.orig/Documentation/sysctl/kernel.txt 2011-01-06 14:04:07.000000000 +1100 -+++ linux-2.6.37-ck2/Documentation/sysctl/kernel.txt 2011-02-14 09:47:50.984252001 +1100 -@@ -32,6 +32,7 @@ - - domainname - - hostname - - hotplug -+- iso_cpu - - java-appletviewer [ binfmt_java, obsolete ] - - java-interpreter [ binfmt_java, obsolete ] - - kstack_depth_to_print [ X86 only ] -@@ -54,6 +55,7 @@ - - randomize_va_space - - real-root-dev ==> Documentation/initrd.txt - - reboot-cmd [ SPARC only ] -+- rr_interval - - rtsig-max - - rtsig-nr - - sem -@@ -254,6 +256,16 @@ - - ============================================================== - -+iso_cpu: (BFS CPU scheduler only). -+ -+This sets the percentage cpu that the unprivileged SCHED_ISO tasks can -+run effectively at realtime priority, averaged over a rolling five -+seconds over the -whole- system, meaning all cpus. -+ -+Set to 70 (percent) by default. -+ -+============================================================== -+ - l2cr: (PPC only) - - This flag controls the L2 cache of G3 processor boards. If -@@ -428,6 +440,20 @@ - - ============================================================== - -+rr_interval: (BFS CPU scheduler only) -+ -+This is the smallest duration that any cpu process scheduling unit -+will run for. Increasing this value can increase throughput of cpu -+bound tasks substantially but at the expense of increased latencies -+overall. Conversely decreasing it will decrease average and maximum -+latencies but at the expense of throughput. This value is in -+milliseconds and the default value chosen depends on the number of -+cpus available at scheduler initialisation with a minimum of 6. -+ -+Valid values are from 1-1000. -+ -+============================================================== -+ - rtsig-max & rtsig-nr: - - The file rtsig-max can be used to tune the maximum number -Index: linux-2.6.37-ck2/fs/proc/base.c -=================================================================== ---- linux-2.6.37-ck2.orig/fs/proc/base.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/fs/proc/base.c 2011-02-14 09:47:50.986252000 +1100 -@@ -356,7 +356,7 @@ - static int proc_pid_schedstat(struct task_struct *task, char *buffer) - { - return sprintf(buffer, "%llu %llu %lu\n", -- (unsigned long long)task->se.sum_exec_runtime, -+ (unsigned long long)tsk_seruntime(task), - (unsigned long long)task->sched_info.run_delay, - task->sched_info.pcount); - } -Index: linux-2.6.37-ck2/include/linux/init_task.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/init_task.h 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/include/linux/init_task.h 2011-02-14 09:47:50.986252001 +1100 -@@ -114,6 +114,67 @@ - * INIT_TASK is used to set up the first task table, touch at - * your own risk!. Base=0, limit=0x1fffff (=2MB) - */ -+#ifdef CONFIG_SCHED_BFS -+#define INIT_TASK(tsk) \ -+{ \ -+ .state = 0, \ -+ .stack = &init_thread_info, \ -+ .usage = ATOMIC_INIT(2), \ -+ .flags = PF_KTHREAD, \ -+ .lock_depth = -1, \ -+ .prio = NORMAL_PRIO, \ -+ .static_prio = MAX_PRIO-20, \ -+ .normal_prio = NORMAL_PRIO, \ -+ .deadline = 0, \ -+ .policy = SCHED_NORMAL, \ -+ .cpus_allowed = CPU_MASK_ALL, \ -+ .mm = NULL, \ -+ .active_mm = &init_mm, \ -+ .run_list = LIST_HEAD_INIT(tsk.run_list), \ -+ .time_slice = HZ, \ -+ .tasks = LIST_HEAD_INIT(tsk.tasks), \ -+ .pushable_tasks = PLIST_NODE_INIT(tsk.pushable_tasks, MAX_PRIO), \ -+ .ptraced = LIST_HEAD_INIT(tsk.ptraced), \ -+ .ptrace_entry = LIST_HEAD_INIT(tsk.ptrace_entry), \ -+ .real_parent = &tsk, \ -+ .parent = &tsk, \ -+ .children = LIST_HEAD_INIT(tsk.children), \ -+ .sibling = LIST_HEAD_INIT(tsk.sibling), \ -+ .group_leader = &tsk, \ -+ RCU_INIT_POINTER(.real_cred, &init_cred), \ -+ RCU_INIT_POINTER(.cred, &init_cred), \ -+ .comm = "swapper", \ -+ .thread = INIT_THREAD, \ -+ .fs = &init_fs, \ -+ .files = &init_files, \ -+ .signal = &init_signals, \ -+ .sighand = &init_sighand, \ -+ .nsproxy = &init_nsproxy, \ -+ .pending = { \ -+ .list = LIST_HEAD_INIT(tsk.pending.list), \ -+ .signal = {{0}}}, \ -+ .blocked = {{0}}, \ -+ .alloc_lock = __SPIN_LOCK_UNLOCKED(tsk.alloc_lock), \ -+ .journal_info = NULL, \ -+ .cpu_timers = INIT_CPU_TIMERS(tsk.cpu_timers), \ -+ .fs_excl = ATOMIC_INIT(0), \ -+ .pi_lock = __RAW_SPIN_LOCK_UNLOCKED(tsk.pi_lock), \ -+ .timer_slack_ns = 50000, /* 50 usec default slack */ \ -+ .pids = { \ -+ [PIDTYPE_PID] = INIT_PID_LINK(PIDTYPE_PID), \ -+ [PIDTYPE_PGID] = INIT_PID_LINK(PIDTYPE_PGID), \ -+ [PIDTYPE_SID] = INIT_PID_LINK(PIDTYPE_SID), \ -+ }, \ -+ .dirties = INIT_PROP_LOCAL_SINGLE(dirties), \ -+ INIT_IDS \ -+ INIT_PERF_EVENTS(tsk) \ -+ INIT_TRACE_IRQFLAGS \ -+ INIT_LOCKDEP \ -+ INIT_FTRACE_GRAPH \ -+ INIT_TRACE_RECURSION \ -+ INIT_TASK_RCU_PREEMPT(tsk) \ -+} -+#else /* CONFIG_SCHED_BFS */ - #define INIT_TASK(tsk) \ - { \ - .state = 0, \ -@@ -179,7 +240,7 @@ - INIT_TRACE_RECURSION \ - INIT_TASK_RCU_PREEMPT(tsk) \ - } -- -+#endif /* CONFIG_SCHED_BFS */ - - #define INIT_CPU_TIMERS(cpu_timers) \ - { \ -Index: linux-2.6.37-ck2/include/linux/ioprio.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/ioprio.h 2009-06-10 13:05:27.000000000 +1000 -+++ linux-2.6.37-ck2/include/linux/ioprio.h 2011-02-14 09:47:50.986252001 +1100 -@@ -64,6 +64,8 @@ - - static inline int task_nice_ioprio(struct task_struct *task) - { -+ if (iso_task(task)) -+ return 0; - return (task_nice(task) + 20) / 5; - } - -Index: linux-2.6.37-ck2/include/linux/sched.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/sched.h 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/include/linux/sched.h 2011-02-14 09:47:50.988252000 +1100 -@@ -36,8 +36,15 @@ - #define SCHED_FIFO 1 - #define SCHED_RR 2 - #define SCHED_BATCH 3 --/* SCHED_ISO: reserved but not implemented yet */ -+/* SCHED_ISO: Implemented on BFS only */ - #define SCHED_IDLE 5 -+#ifdef CONFIG_SCHED_BFS -+#define SCHED_ISO 4 -+#define SCHED_IDLEPRIO SCHED_IDLE -+#define SCHED_MAX (SCHED_IDLEPRIO) -+#define SCHED_RANGE(policy) ((policy) <= SCHED_MAX) -+#endif -+ - /* Can be ORed in to make sure the process is reverted back to SCHED_NORMAL on fork */ - #define SCHED_RESET_ON_FORK 0x40000000 - -@@ -268,8 +275,6 @@ - extern void init_idle(struct task_struct *idle, int cpu); - extern void init_idle_bootup_task(struct task_struct *idle); - --extern int runqueue_is_locked(int cpu); -- - extern cpumask_var_t nohz_cpu_mask; - #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ) - extern void select_nohz_load_balancer(int stop_tick); -@@ -1188,17 +1193,31 @@ - - int lock_depth; /* BKL lock depth */ - -+#ifndef CONFIG_SCHED_BFS - #ifdef CONFIG_SMP - #ifdef __ARCH_WANT_UNLOCKED_CTXSW - int oncpu; - #endif - #endif -+#else /* CONFIG_SCHED_BFS */ -+ int oncpu; -+#endif - - int prio, static_prio, normal_prio; - unsigned int rt_priority; -+#ifdef CONFIG_SCHED_BFS -+ int time_slice; -+ u64 deadline; -+ struct list_head run_list; -+ u64 last_ran; -+ u64 sched_time; /* sched_clock time spent running */ -+ -+ unsigned long rt_timeout; -+#else /* CONFIG_SCHED_BFS */ - const struct sched_class *sched_class; - struct sched_entity se; - struct sched_rt_entity rt; -+#endif - - #ifdef CONFIG_PREEMPT_NOTIFIERS - /* list of struct preempt_notifier: */ -@@ -1295,6 +1314,9 @@ - int __user *clear_child_tid; /* CLONE_CHILD_CLEARTID */ - - cputime_t utime, stime, utimescaled, stimescaled; -+#ifdef CONFIG_SCHED_BFS -+ unsigned long utime_pc, stime_pc; -+#endif - cputime_t gtime; - #ifndef CONFIG_VIRT_CPU_ACCOUNTING - cputime_t prev_utime, prev_stime; -@@ -1514,6 +1536,53 @@ - #endif - }; - -+#ifdef CONFIG_SCHED_BFS -+extern int grunqueue_is_locked(void); -+extern void grq_unlock_wait(void); -+#define tsk_seruntime(t) ((t)->sched_time) -+#define tsk_rttimeout(t) ((t)->rt_timeout) -+ -+static inline void tsk_cpus_current(struct task_struct *p) -+{ -+} -+ -+#define runqueue_is_locked(cpu) grunqueue_is_locked() -+ -+static inline void print_scheduler_version(void) -+{ -+ printk(KERN_INFO"BFS CPU scheduler v0.363 by Con Kolivas.\n"); -+} -+ -+static inline int iso_task(struct task_struct *p) -+{ -+ return (p->policy == SCHED_ISO); -+} -+extern void remove_cpu(unsigned long cpu); -+#else /* CFS */ -+extern int runqueue_is_locked(int cpu); -+#define tsk_seruntime(t) ((t)->se.sum_exec_runtime) -+#define tsk_rttimeout(t) ((t)->rt.timeout) -+ -+static inline void tsk_cpus_current(struct task_struct *p) -+{ -+ p->rt.nr_cpus_allowed = current->rt.nr_cpus_allowed; -+} -+ -+static inline void print_scheduler_version(void) -+{ -+ printk(KERN_INFO"CFS CPU scheduler.\n"); -+} -+ -+static inline int iso_task(struct task_struct *p) -+{ -+ return 0; -+} -+ -+static inline void remove_cpu(unsigned long cpu) -+{ -+} -+#endif /* CONFIG_SCHED_BFS */ -+ - /* Future-safe accessor for struct task_struct's cpus_allowed. */ - #define tsk_cpus_allowed(tsk) (&(tsk)->cpus_allowed) - -@@ -1531,10 +1600,20 @@ - */ - - #define MAX_USER_RT_PRIO 100 --#define MAX_RT_PRIO MAX_USER_RT_PRIO -+#define MAX_RT_PRIO (MAX_USER_RT_PRIO + 1) -+#define DEFAULT_PRIO (MAX_RT_PRIO + 20) - -+#ifdef CONFIG_SCHED_BFS -+#define PRIO_RANGE (40) -+#define MAX_PRIO (MAX_RT_PRIO + PRIO_RANGE) -+#define ISO_PRIO (MAX_RT_PRIO) -+#define NORMAL_PRIO (MAX_RT_PRIO + 1) -+#define IDLE_PRIO (MAX_RT_PRIO + 2) -+#define PRIO_LIMIT ((IDLE_PRIO) + 1) -+#else /* CONFIG_SCHED_BFS */ - #define MAX_PRIO (MAX_RT_PRIO + 40) --#define DEFAULT_PRIO (MAX_RT_PRIO + 20) -+#define NORMAL_PRIO DEFAULT_PRIO -+#endif /* CONFIG_SCHED_BFS */ - - static inline int rt_prio(int prio) - { -@@ -1862,7 +1941,7 @@ - extern unsigned long long thread_group_sched_runtime(struct task_struct *task); - - /* sched_exec is called by processes performing an exec */ --#ifdef CONFIG_SMP -+#if defined(CONFIG_SMP) && !defined(CONFIG_SCHED_BFS) - extern void sched_exec(void); - #else - #define sched_exec() {} -Index: linux-2.6.37-ck2/init/Kconfig -=================================================================== ---- linux-2.6.37-ck2.orig/init/Kconfig 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/init/Kconfig 2011-02-14 09:47:50.988252001 +1100 -@@ -30,6 +30,19 @@ - - menu "General setup" - -+config SCHED_BFS -+ bool "BFS cpu scheduler" -+ ---help--- -+ The Brain Fuck CPU Scheduler for excellent interactivity and -+ responsiveness on the desktop and solid scalability on normal -+ hardware. Not recommended for 4096 CPUs. -+ -+ Currently incompatible with the Group CPU scheduler, and RCU TORTURE -+ TEST so these options are disabled. -+ -+ Say Y here. -+ default y -+ - config EXPERIMENTAL - bool "Prompt for development and/or incomplete code/drivers" - ---help--- -@@ -563,6 +576,7 @@ - - config CGROUP_CPUACCT - bool "Simple CPU accounting cgroup subsystem" -+ depends on !SCHED_BFS - help - Provides a simple Resource Controller for monitoring the - total CPU consumed by the tasks in a cgroup. -@@ -629,7 +643,7 @@ - - menuconfig CGROUP_SCHED - bool "Group CPU scheduler" -- depends on EXPERIMENTAL -+ depends on EXPERIMENTAL && !SCHED_BFS - default n - help - This feature lets CPU scheduler recognize task groups and control CPU -Index: linux-2.6.37-ck2/init/main.c -=================================================================== ---- linux-2.6.37-ck2.orig/init/main.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/init/main.c 2011-02-14 09:47:50.989252001 +1100 -@@ -824,6 +824,7 @@ - system_state = SYSTEM_RUNNING; - numa_default_policy(); - -+ print_scheduler_version(); - - current->signal->flags |= SIGNAL_UNKILLABLE; - -Index: linux-2.6.37-ck2/kernel/delayacct.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/delayacct.c 2009-12-03 21:40:09.000000000 +1100 -+++ linux-2.6.37-ck2/kernel/delayacct.c 2011-02-14 09:47:50.989252001 +1100 -@@ -128,7 +128,7 @@ - */ - t1 = tsk->sched_info.pcount; - t2 = tsk->sched_info.run_delay; -- t3 = tsk->se.sum_exec_runtime; -+ t3 = tsk_seruntime(tsk); - - d->cpu_count += t1; - -Index: linux-2.6.37-ck2/kernel/exit.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/exit.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/kernel/exit.c 2011-02-14 09:47:50.989252001 +1100 -@@ -132,7 +132,7 @@ - sig->inblock += task_io_get_inblock(tsk); - sig->oublock += task_io_get_oublock(tsk); - task_io_accounting_add(&sig->ioac, &tsk->ioac); -- sig->sum_sched_runtime += tsk->se.sum_exec_runtime; -+ sig->sum_sched_runtime += tsk_seruntime(tsk); - } - - sig->nr_threads--; -Index: linux-2.6.37-ck2/kernel/kthread.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/kthread.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/kernel/kthread.c 2011-02-14 09:47:50.989252001 +1100 -@@ -184,7 +184,9 @@ - } - - p->cpus_allowed = cpumask_of_cpu(cpu); -+#ifndef CONFIG_SCHED_BFS - p->rt.nr_cpus_allowed = 1; -+#endif - p->flags |= PF_THREAD_BOUND; - } - EXPORT_SYMBOL(kthread_bind); -Index: linux-2.6.37-ck2/kernel/posix-cpu-timers.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/posix-cpu-timers.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/kernel/posix-cpu-timers.c 2011-02-14 09:47:50.990252001 +1100 -@@ -248,7 +248,7 @@ - do { - times->utime = cputime_add(times->utime, t->utime); - times->stime = cputime_add(times->stime, t->stime); -- times->sum_exec_runtime += t->se.sum_exec_runtime; -+ times->sum_exec_runtime += tsk_seruntime(t); - } while_each_thread(tsk, t); - out: - rcu_read_unlock(); -@@ -508,7 +508,7 @@ - void posix_cpu_timers_exit(struct task_struct *tsk) - { - cleanup_timers(tsk->cpu_timers, -- tsk->utime, tsk->stime, tsk->se.sum_exec_runtime); -+ tsk->utime, tsk->stime, tsk_seruntime(tsk)); - - } - void posix_cpu_timers_exit_group(struct task_struct *tsk) -@@ -518,7 +518,7 @@ - cleanup_timers(tsk->signal->cpu_timers, - cputime_add(tsk->utime, sig->utime), - cputime_add(tsk->stime, sig->stime), -- tsk->se.sum_exec_runtime + sig->sum_sched_runtime); -+ tsk_seruntime(tsk) + sig->sum_sched_runtime); - } - - static void clear_dead_task(struct k_itimer *timer, union cpu_time_count now) -@@ -949,7 +949,7 @@ - struct cpu_timer_list *t = list_first_entry(timers, - struct cpu_timer_list, - entry); -- if (!--maxfire || tsk->se.sum_exec_runtime < t->expires.sched) { -+ if (!--maxfire || tsk_seruntime(tsk) < t->expires.sched) { - tsk->cputime_expires.sched_exp = t->expires.sched; - break; - } -@@ -966,7 +966,7 @@ - ACCESS_ONCE(sig->rlim[RLIMIT_RTTIME].rlim_max); - - if (hard != RLIM_INFINITY && -- tsk->rt.timeout > DIV_ROUND_UP(hard, USEC_PER_SEC/HZ)) { -+ tsk_rttimeout(tsk) > DIV_ROUND_UP(hard, USEC_PER_SEC/HZ)) { - /* - * At the hard limit, we just die. - * No need to calculate anything else now. -@@ -974,7 +974,7 @@ - __group_send_sig_info(SIGKILL, SEND_SIG_PRIV, tsk); - return; - } -- if (tsk->rt.timeout > DIV_ROUND_UP(soft, USEC_PER_SEC/HZ)) { -+ if (tsk_rttimeout(tsk) > DIV_ROUND_UP(soft, USEC_PER_SEC/HZ)) { - /* - * At the soft limit, send a SIGXCPU every second. - */ -@@ -1276,7 +1276,7 @@ - struct task_cputime task_sample = { - .utime = tsk->utime, - .stime = tsk->stime, -- .sum_exec_runtime = tsk->se.sum_exec_runtime -+ .sum_exec_runtime = tsk_seruntime(tsk) - }; - - if (task_cputime_expired(&task_sample, &tsk->cputime_expires)) -Index: linux-2.6.37-ck2/kernel/sched_bfs.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.37-ck2/kernel/sched_bfs.c 2011-02-14 09:47:50.993252001 +1100 -@@ -0,0 +1,7223 @@ -+/* -+ * kernel/sched_bfs.c, was sched.c -+ * -+ * Kernel scheduler and related syscalls -+ * -+ * Copyright (C) 1991-2002 Linus Torvalds -+ * -+ * 1996-12-23 Modified by Dave Grothe to fix bugs in semaphores and -+ * make semaphores SMP safe -+ * 1998-11-19 Implemented schedule_timeout() and related stuff -+ * by Andrea Arcangeli -+ * 2002-01-04 New ultra-scalable O(1) scheduler by Ingo Molnar: -+ * hybrid priority-list and round-robin design with -+ * an array-switch method of distributing timeslices -+ * and per-CPU runqueues. Cleanups and useful suggestions -+ * by Davide Libenzi, preemptible kernel bits by Robert Love. -+ * 2003-09-03 Interactivity tuning by Con Kolivas. -+ * 2004-04-02 Scheduler domains code by Nick Piggin -+ * 2007-04-15 Work begun on replacing all interactivity tuning with a -+ * fair scheduling design by Con Kolivas. -+ * 2007-05-05 Load balancing (smp-nice) and other improvements -+ * by Peter Williams -+ * 2007-05-06 Interactivity improvements to CFS by Mike Galbraith -+ * 2007-07-01 Group scheduling enhancements by Srivatsa Vaddagiri -+ * 2007-11-29 RT balancing improvements by Steven Rostedt, Gregory Haskins, -+ * Thomas Gleixner, Mike Kravetz -+ * now Brainfuck deadline scheduling policy by Con Kolivas deletes -+ * a whole lot of those previous things. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "sched_cpupri.h" -+#include "workqueue_sched.h" -+ -+#define CREATE_TRACE_POINTS -+#include -+ -+#define rt_prio(prio) unlikely((prio) < MAX_RT_PRIO) -+#define rt_task(p) rt_prio((p)->prio) -+#define rt_queue(rq) rt_prio((rq)->rq_prio) -+#define batch_task(p) (unlikely((p)->policy == SCHED_BATCH)) -+#define is_rt_policy(policy) ((policy) == SCHED_FIFO || \ -+ (policy) == SCHED_RR) -+#define has_rt_policy(p) unlikely(is_rt_policy((p)->policy)) -+#define idleprio_task(p) unlikely((p)->policy == SCHED_IDLEPRIO) -+#define iso_task(p) unlikely((p)->policy == SCHED_ISO) -+#define iso_queue(rq) unlikely((rq)->rq_policy == SCHED_ISO) -+#define ISO_PERIOD ((5 * HZ * num_online_cpus()) + 1) -+ -+/* -+ * Convert user-nice values [ -20 ... 0 ... 19 ] -+ * to static priority [ MAX_RT_PRIO..MAX_PRIO-1 ], -+ * and back. -+ */ -+#define NICE_TO_PRIO(nice) (MAX_RT_PRIO + (nice) + 20) -+#define PRIO_TO_NICE(prio) ((prio) - MAX_RT_PRIO - 20) -+#define TASK_NICE(p) PRIO_TO_NICE((p)->static_prio) -+ -+/* -+ * 'User priority' is the nice value converted to something we -+ * can work with better when scaling various scheduler parameters, -+ * it's a [ 0 ... 39 ] range. -+ */ -+#define USER_PRIO(p) ((p) - MAX_RT_PRIO) -+#define TASK_USER_PRIO(p) USER_PRIO((p)->static_prio) -+#define MAX_USER_PRIO (USER_PRIO(MAX_PRIO)) -+#define SCHED_PRIO(p) ((p) + MAX_RT_PRIO) -+#define STOP_PRIO (MAX_RT_PRIO - 1) -+ -+/* -+ * Some helpers for converting to/from various scales. Use shifts to get -+ * approximate multiples of ten for less overhead. -+ */ -+#define JIFFIES_TO_NS(TIME) ((TIME) * (1000000000 / HZ)) -+#define JIFFY_NS (1000000000 / HZ) -+#define HALF_JIFFY_NS (1000000000 / HZ / 2) -+#define HALF_JIFFY_US (1000000 / HZ / 2) -+#define MS_TO_NS(TIME) ((TIME) << 20) -+#define MS_TO_US(TIME) ((TIME) << 10) -+#define NS_TO_MS(TIME) ((TIME) >> 20) -+#define NS_TO_US(TIME) ((TIME) >> 10) -+ -+#define RESCHED_US (100) /* Reschedule if less than this many μs left */ -+ -+/* -+ * This is the time all tasks within the same priority round robin. -+ * Value is in ms and set to a minimum of 6ms. Scales with number of cpus. -+ * Tunable via /proc interface. -+ */ -+int rr_interval __read_mostly = 6; -+ -+/* -+ * sched_iso_cpu - sysctl which determines the cpu percentage SCHED_ISO tasks -+ * are allowed to run five seconds as real time tasks. This is the total over -+ * all online cpus. -+ */ -+int sched_iso_cpu __read_mostly = 70; -+ -+/* -+ * The relative length of deadline for each priority(nice) level. -+ */ -+static int prio_ratios[PRIO_RANGE] __read_mostly; -+ -+/* -+ * The quota handed out to tasks of all priority levels when refilling their -+ * time_slice. -+ */ -+static inline unsigned long timeslice(void) -+{ -+ return MS_TO_US(rr_interval); -+} -+ -+/* -+ * The global runqueue data that all CPUs work off. Data is protected either -+ * by the global grq lock, or the discrete lock that precedes the data in this -+ * struct. -+ */ -+struct global_rq { -+ raw_spinlock_t lock; -+ unsigned long nr_running; -+ unsigned long nr_uninterruptible; -+ unsigned long long nr_switches; -+ struct list_head queue[PRIO_LIMIT]; -+ DECLARE_BITMAP(prio_bitmap, PRIO_LIMIT + 1); -+#ifdef CONFIG_SMP -+ unsigned long qnr; /* queued not running */ -+ cpumask_t cpu_idle_map; -+ int idle_cpus; -+#endif -+ u64 niffies; /* Nanosecond jiffies */ -+ unsigned long last_jiffy; /* Last jiffy we updated niffies */ -+ -+ raw_spinlock_t iso_lock; -+ int iso_ticks; -+ int iso_refractory; -+}; -+ -+/* There can be only one */ -+static struct global_rq grq; -+ -+/* -+ * This is the main, per-CPU runqueue data structure. -+ * This data should only be modified by the local cpu. -+ */ -+struct rq { -+#ifdef CONFIG_SMP -+#ifdef CONFIG_NO_HZ -+ u64 nohz_stamp; -+ unsigned char in_nohz_recently; -+#endif -+#endif -+ -+ struct task_struct *curr, *idle, *stop; -+ struct mm_struct *prev_mm; -+ -+ /* Stored data about rq->curr to work outside grq lock */ -+ u64 rq_deadline; -+ unsigned int rq_policy; -+ int rq_time_slice; -+ u64 rq_last_ran; -+ int rq_prio; -+ int rq_running; /* There is a task running */ -+ -+ /* Accurate timekeeping data */ -+ u64 timekeep_clock; -+ unsigned long user_pc, nice_pc, irq_pc, softirq_pc, system_pc, -+ iowait_pc, idle_pc; -+ atomic_t nr_iowait; -+ -+#ifdef CONFIG_SMP -+ int cpu; /* cpu of this runqueue */ -+ int online; -+ -+ struct root_domain *rd; -+ struct sched_domain *sd; -+ unsigned long *cpu_locality; /* CPU relative cache distance */ -+#ifdef CONFIG_SCHED_SMT -+ int (*siblings_idle)(unsigned long cpu); -+ /* See if all smt siblings are idle */ -+ cpumask_t smt_siblings; -+#endif -+#ifdef CONFIG_SCHED_MC -+ int (*cache_idle)(unsigned long cpu); -+ /* See if all cache siblings are idle */ -+ cpumask_t cache_siblings; -+#endif -+ u64 last_niffy; /* Last time this RQ updated grq.niffies */ -+#endif -+#ifdef CONFIG_IRQ_TIME_ACCOUNTING -+ u64 prev_irq_time; -+#endif -+ u64 clock, old_clock, last_tick; -+ u64 clock_task; -+ int dither; -+ -+#ifdef CONFIG_SCHEDSTATS -+ -+ /* latency stats */ -+ struct sched_info rq_sched_info; -+ unsigned long long rq_cpu_time; -+ /* could above be rq->cfs_rq.exec_clock + rq->rt_rq.rt_runtime ? */ -+ -+ /* sys_sched_yield() stats */ -+ unsigned int yld_count; -+ -+ /* schedule() stats */ -+ unsigned int sched_switch; -+ unsigned int sched_count; -+ unsigned int sched_goidle; -+ -+ /* try_to_wake_up() stats */ -+ unsigned int ttwu_count; -+ unsigned int ttwu_local; -+ -+ /* BKL stats */ -+ unsigned int bkl_count; -+#endif -+}; -+ -+static DEFINE_PER_CPU(struct rq, runqueues) ____cacheline_aligned_in_smp; -+static DEFINE_MUTEX(sched_hotcpu_mutex); -+ -+#ifdef CONFIG_SMP -+/* -+ * sched_domains_mutex serializes calls to arch_init_sched_domains, -+ * detach_destroy_domains and partition_sched_domains. -+ */ -+static DEFINE_MUTEX(sched_domains_mutex); -+ -+/* -+ * By default the system creates a single root-domain with all cpus as -+ * members (mimicking the global state we have today). -+ */ -+static struct root_domain def_root_domain; -+ -+int __weak arch_sd_sibling_asym_packing(void) -+{ -+ return 0*SD_ASYM_PACKING; -+} -+#endif -+ -+/* -+ * We add the notion of a root-domain which will be used to define per-domain -+ * variables. Each exclusive cpuset essentially defines an island domain by -+ * fully partitioning the member cpus from any other cpuset. Whenever a new -+ * exclusive cpuset is created, we also create and attach a new root-domain -+ * object. -+ * -+ */ -+struct root_domain { -+ atomic_t refcount; -+ cpumask_var_t span; -+ cpumask_var_t online; -+ -+ /* -+ * The "RT overload" flag: it gets set if a CPU has more than -+ * one runnable RT task. -+ */ -+ cpumask_var_t rto_mask; -+ atomic_t rto_count; -+#ifdef CONFIG_SMP -+ struct cpupri cpupri; -+#endif -+}; -+ -+#define rcu_dereference_check_sched_domain(p) \ -+ rcu_dereference_check((p), \ -+ rcu_read_lock_sched_held() || \ -+ lockdep_is_held(&sched_domains_mutex)) -+ -+/* -+ * The domain tree (rq->sd) is protected by RCU's quiescent state transition. -+ * See detach_destroy_domains: synchronize_sched for details. -+ * -+ * The domain tree of any CPU may only be accessed from within -+ * preempt-disabled sections. -+ */ -+#define for_each_domain(cpu, __sd) \ -+ for (__sd = rcu_dereference_check_sched_domain(cpu_rq(cpu)->sd); __sd; __sd = __sd->parent) -+ -+static inline void update_rq_clock(struct rq *rq); -+ -+/* -+ * Sanity check should sched_clock return bogus values. We make sure it does -+ * not appear to go backwards, and use jiffies to determine the maximum and -+ * minimum it could possibly have increased, and round down to the nearest -+ * jiffy when it falls outside this. -+ */ -+static inline void niffy_diff(s64 *niff_diff, int jiff_diff) -+{ -+ unsigned long min_diff, max_diff; -+ -+ if (jiff_diff > 1) -+ min_diff = JIFFIES_TO_NS(jiff_diff - 1); -+ else -+ min_diff = 1; -+ /* Round up to the nearest tick for maximum */ -+ max_diff = JIFFIES_TO_NS(jiff_diff + 1); -+ -+ if (unlikely(*niff_diff < min_diff || *niff_diff > max_diff)) -+ *niff_diff = min_diff; -+} -+ -+#ifdef CONFIG_SMP -+#define cpu_rq(cpu) (&per_cpu(runqueues, (cpu))) -+#define this_rq() (&__get_cpu_var(runqueues)) -+#define task_rq(p) cpu_rq(task_cpu(p)) -+#define cpu_curr(cpu) (cpu_rq(cpu)->curr) -+static inline int cpu_of(struct rq *rq) -+{ -+ return rq->cpu; -+} -+ -+/* -+ * Niffies are a globally increasing nanosecond counter. Whenever a runqueue -+ * clock is updated with the grq.lock held, it is an opportunity to update the -+ * niffies value. Any CPU can update it by adding how much its clock has -+ * increased since it last updated niffies, minus any added niffies by other -+ * CPUs. -+ */ -+static inline void update_clocks(struct rq *rq) -+{ -+ s64 ndiff; -+ long jdiff; -+ -+ update_rq_clock(rq); -+ ndiff = rq->clock - rq->old_clock; -+ /* old_clock is only updated when we are updating niffies */ -+ rq->old_clock = rq->clock; -+ ndiff -= grq.niffies - rq->last_niffy; -+ jdiff = jiffies - grq.last_jiffy; -+ niffy_diff(&ndiff, jdiff); -+ grq.last_jiffy += jdiff; -+ grq.niffies += ndiff; -+ rq->last_niffy = grq.niffies; -+} -+#else /* CONFIG_SMP */ -+static struct rq *uprq; -+#define cpu_rq(cpu) (uprq) -+#define this_rq() (uprq) -+#define task_rq(p) (uprq) -+#define cpu_curr(cpu) ((uprq)->curr) -+static inline int cpu_of(struct rq *rq) -+{ -+ return 0; -+} -+ -+static inline void update_clocks(struct rq *rq) -+{ -+ s64 ndiff; -+ long jdiff; -+ -+ update_rq_clock(rq); -+ ndiff = rq->clock - rq->old_clock; -+ rq->old_clock = rq->clock; -+ jdiff = jiffies - grq.last_jiffy; -+ niffy_diff(&ndiff, jdiff); -+ grq.last_jiffy += jdiff; -+ grq.niffies += ndiff; -+} -+#endif -+#define raw_rq() (&__raw_get_cpu_var(runqueues)) -+ -+#include "sched_stats.h" -+ -+#ifndef prepare_arch_switch -+# define prepare_arch_switch(next) do { } while (0) -+#endif -+#ifndef finish_arch_switch -+# define finish_arch_switch(prev) do { } while (0) -+#endif -+ -+/* -+ * All common locking functions performed on grq.lock. rq->clock is local to -+ * the CPU accessing it so it can be modified just with interrupts disabled -+ * when we're not updating niffies. -+ * Looking up task_rq must be done under grq.lock to be safe. -+ */ -+static void update_rq_clock_task(struct rq *rq, s64 delta); -+ -+static inline void update_rq_clock(struct rq *rq) -+{ -+ s64 delta = sched_clock_cpu(cpu_of(rq)) - rq->clock; -+ -+ rq->clock += delta; -+ update_rq_clock_task(rq, delta); -+} -+ -+static inline int task_running(struct task_struct *p) -+{ -+ return p->oncpu; -+} -+ -+static inline void grq_lock(void) -+ __acquires(grq.lock) -+{ -+ raw_spin_lock(&grq.lock); -+} -+ -+static inline void grq_unlock(void) -+ __releases(grq.lock) -+{ -+ raw_spin_unlock(&grq.lock); -+} -+ -+static inline void grq_lock_irq(void) -+ __acquires(grq.lock) -+{ -+ raw_spin_lock_irq(&grq.lock); -+} -+ -+static inline void time_lock_grq(struct rq *rq) -+ __acquires(grq.lock) -+{ -+ grq_lock(); -+ update_clocks(rq); -+} -+ -+static inline void grq_unlock_irq(void) -+ __releases(grq.lock) -+{ -+ raw_spin_unlock_irq(&grq.lock); -+} -+ -+static inline void grq_lock_irqsave(unsigned long *flags) -+ __acquires(grq.lock) -+{ -+ raw_spin_lock_irqsave(&grq.lock, *flags); -+} -+ -+static inline void grq_unlock_irqrestore(unsigned long *flags) -+ __releases(grq.lock) -+{ -+ raw_spin_unlock_irqrestore(&grq.lock, *flags); -+} -+ -+static inline struct rq -+*task_grq_lock(struct task_struct *p, unsigned long *flags) -+ __acquires(grq.lock) -+{ -+ grq_lock_irqsave(flags); -+ return task_rq(p); -+} -+ -+static inline struct rq -+*time_task_grq_lock(struct task_struct *p, unsigned long *flags) -+ __acquires(grq.lock) -+{ -+ struct rq *rq = task_grq_lock(p, flags); -+ update_clocks(rq); -+ return rq; -+} -+ -+static inline struct rq *task_grq_lock_irq(struct task_struct *p) -+ __acquires(grq.lock) -+{ -+ grq_lock_irq(); -+ return task_rq(p); -+} -+ -+static inline void time_task_grq_lock_irq(struct task_struct *p) -+ __acquires(grq.lock) -+{ -+ struct rq *rq = task_grq_lock_irq(p); -+ update_clocks(rq); -+} -+ -+static inline void task_grq_unlock_irq(void) -+ __releases(grq.lock) -+{ -+ grq_unlock_irq(); -+} -+ -+static inline void task_grq_unlock(unsigned long *flags) -+ __releases(grq.lock) -+{ -+ grq_unlock_irqrestore(flags); -+} -+ -+/** -+ * grunqueue_is_locked -+ * -+ * Returns true if the global runqueue is locked. -+ * This interface allows printk to be called with the runqueue lock -+ * held and know whether or not it is OK to wake up the klogd. -+ */ -+inline int grunqueue_is_locked(void) -+{ -+ return raw_spin_is_locked(&grq.lock); -+} -+ -+inline void grq_unlock_wait(void) -+ __releases(grq.lock) -+{ -+ smp_mb(); /* spin-unlock-wait is not a full memory barrier */ -+ raw_spin_unlock_wait(&grq.lock); -+} -+ -+static inline void time_grq_lock(struct rq *rq, unsigned long *flags) -+ __acquires(grq.lock) -+{ -+ local_irq_save(*flags); -+ time_lock_grq(rq); -+} -+ -+static inline struct rq *__task_grq_lock(struct task_struct *p) -+ __acquires(grq.lock) -+{ -+ grq_lock(); -+ return task_rq(p); -+} -+ -+static inline void __task_grq_unlock(void) -+ __releases(grq.lock) -+{ -+ grq_unlock(); -+} -+ -+#ifndef __ARCH_WANT_UNLOCKED_CTXSW -+static inline void prepare_lock_switch(struct rq *rq, struct task_struct *next) -+{ -+} -+ -+static inline void finish_lock_switch(struct rq *rq, struct task_struct *prev) -+{ -+#ifdef CONFIG_DEBUG_SPINLOCK -+ /* this is a valid case when another task releases the spinlock */ -+ grq.lock.owner = current; -+#endif -+ /* -+ * If we are tracking spinlock dependencies then we have to -+ * fix up the runqueue lock - which gets 'carried over' from -+ * prev into current: -+ */ -+ spin_acquire(&grq.lock.dep_map, 0, 0, _THIS_IP_); -+ -+ grq_unlock_irq(); -+} -+ -+#else /* __ARCH_WANT_UNLOCKED_CTXSW */ -+ -+static inline void prepare_lock_switch(struct rq *rq, struct task_struct *next) -+{ -+#ifdef __ARCH_WANT_INTERRUPTS_ON_CTXSW -+ grq_unlock_irq(); -+#else -+ grq_unlock(); -+#endif -+} -+ -+static inline void finish_lock_switch(struct rq *rq, struct task_struct *prev) -+{ -+ smp_wmb(); -+#ifndef __ARCH_WANT_INTERRUPTS_ON_CTXSW -+ local_irq_enable(); -+#endif -+} -+#endif /* __ARCH_WANT_UNLOCKED_CTXSW */ -+ -+static inline int deadline_before(u64 deadline, u64 time) -+{ -+ return (deadline < time); -+} -+ -+static inline int deadline_after(u64 deadline, u64 time) -+{ -+ return (deadline > time); -+} -+ -+/* -+ * A task that is queued but not running will be on the grq run list. -+ * A task that is not running or queued will not be on the grq run list. -+ * A task that is currently running will have ->oncpu set but not on the -+ * grq run list. -+ */ -+static inline int task_queued(struct task_struct *p) -+{ -+ return (!list_empty(&p->run_list)); -+} -+ -+/* -+ * Removing from the global runqueue. Enter with grq locked. -+ */ -+static void dequeue_task(struct task_struct *p) -+{ -+ list_del_init(&p->run_list); -+ if (list_empty(grq.queue + p->prio)) -+ __clear_bit(p->prio, grq.prio_bitmap); -+} -+ -+/* -+ * To determine if it's safe for a task of SCHED_IDLEPRIO to actually run as -+ * an idle task, we ensure none of the following conditions are met. -+ */ -+static int idleprio_suitable(struct task_struct *p) -+{ -+ return (!freezing(p) && !signal_pending(p) && -+ !(task_contributes_to_load(p)) && !(p->flags & (PF_EXITING))); -+} -+ -+/* -+ * To determine if a task of SCHED_ISO can run in pseudo-realtime, we check -+ * that the iso_refractory flag is not set. -+ */ -+static int isoprio_suitable(void) -+{ -+ return !grq.iso_refractory; -+} -+ -+/* -+ * Adding to the global runqueue. Enter with grq locked. -+ */ -+static void enqueue_task(struct task_struct *p) -+{ -+ if (!rt_task(p)) { -+ /* Check it hasn't gotten rt from PI */ -+ if ((idleprio_task(p) && idleprio_suitable(p)) || -+ (iso_task(p) && isoprio_suitable())) -+ p->prio = p->normal_prio; -+ else -+ p->prio = NORMAL_PRIO; -+ } -+ __set_bit(p->prio, grq.prio_bitmap); -+ list_add_tail(&p->run_list, grq.queue + p->prio); -+ sched_info_queued(p); -+} -+ -+/* Only idle task does this as a real time task*/ -+static inline void enqueue_task_head(struct task_struct *p) -+{ -+ __set_bit(p->prio, grq.prio_bitmap); -+ list_add(&p->run_list, grq.queue + p->prio); -+ sched_info_queued(p); -+} -+ -+static inline void requeue_task(struct task_struct *p) -+{ -+ sched_info_queued(p); -+} -+ -+/* -+ * Returns the relative length of deadline all compared to the shortest -+ * deadline which is that of nice -20. -+ */ -+static inline int task_prio_ratio(struct task_struct *p) -+{ -+ return prio_ratios[TASK_USER_PRIO(p)]; -+} -+ -+/* -+ * task_timeslice - all tasks of all priorities get the exact same timeslice -+ * length. CPU distribution is handled by giving different deadlines to -+ * tasks of different priorities. Use 128 as the base value for fast shifts. -+ */ -+static inline int task_timeslice(struct task_struct *p) -+{ -+ return (rr_interval * task_prio_ratio(p) / 128); -+} -+ -+#ifdef CONFIG_SMP -+/* -+ * qnr is the "queued but not running" count which is the total number of -+ * tasks on the global runqueue list waiting for cpu time but not actually -+ * currently running on a cpu. -+ */ -+static inline void inc_qnr(void) -+{ -+ grq.qnr++; -+} -+ -+static inline void dec_qnr(void) -+{ -+ grq.qnr--; -+} -+ -+static inline int queued_notrunning(void) -+{ -+ return grq.qnr; -+} -+ -+/* -+ * The cpu_idle_map stores a bitmap of all the CPUs currently idle to -+ * allow easy lookup of whether any suitable idle CPUs are available. -+ * It's cheaper to maintain a binary yes/no if there are any idle CPUs on the -+ * idle_cpus variable than to do a full bitmask check when we are busy. -+ */ -+static inline void set_cpuidle_map(unsigned long cpu) -+{ -+ if (likely(cpu_online(cpu))) { -+ cpu_set(cpu, grq.cpu_idle_map); -+ grq.idle_cpus = 1; -+ } -+} -+ -+static inline void clear_cpuidle_map(unsigned long cpu) -+{ -+ cpu_clear(cpu, grq.cpu_idle_map); -+ if (cpus_empty(grq.cpu_idle_map)) -+ grq.idle_cpus = 0; -+} -+ -+static int suitable_idle_cpus(struct task_struct *p) -+{ -+ if (!grq.idle_cpus) -+ return 0; -+ return (cpus_intersects(p->cpus_allowed, grq.cpu_idle_map)); -+} -+ -+static void resched_task(struct task_struct *p); -+ -+#define CPUIDLE_DIFF_THREAD (1) -+#define CPUIDLE_DIFF_CORE (2) -+#define CPUIDLE_CACHE_BUSY (4) -+#define CPUIDLE_DIFF_CPU (8) -+#define CPUIDLE_THREAD_BUSY (16) -+#define CPUIDLE_DIFF_NODE (32) -+ -+/* -+ * The best idle CPU is chosen according to the CPUIDLE ranking above where the -+ * lowest value would give the most suitable CPU to schedule p onto next. We -+ * iterate from the last CPU upwards instead of using for_each_cpu_mask so as -+ * to be able to break out immediately if the last CPU is idle. The order works -+ * out to be the following: -+ * -+ * Same core, idle or busy cache, idle threads -+ * Other core, same cache, idle or busy cache, idle threads. -+ * Same node, other CPU, idle cache, idle threads. -+ * Same node, other CPU, busy cache, idle threads. -+ * Same core, busy threads. -+ * Other core, same cache, busy threads. -+ * Same node, other CPU, busy threads. -+ * Other node, other CPU, idle cache, idle threads. -+ * Other node, other CPU, busy cache, idle threads. -+ * Other node, other CPU, busy threads. -+ * -+ * If p was the last task running on this rq, then regardless of where -+ * it has been running since then, it is cache warm on this rq. -+ */ -+static void resched_best_idle(struct task_struct *p) -+{ -+ unsigned long cpu_tmp, best_cpu, best_ranking; -+ cpumask_t tmpmask; -+ struct rq *rq; -+ int iterate; -+ -+ cpus_and(tmpmask, p->cpus_allowed, grq.cpu_idle_map); -+ iterate = cpus_weight(tmpmask); -+ best_cpu = task_cpu(p); -+ /* -+ * Start below the last CPU and work up with next_cpu as the last -+ * CPU might not be idle or affinity might not allow it. -+ */ -+ cpu_tmp = best_cpu - 1; -+ rq = cpu_rq(best_cpu); -+ best_ranking = ~0UL; -+ -+ do { -+ unsigned long ranking; -+ struct rq *tmp_rq; -+ -+ ranking = 0; -+ cpu_tmp = next_cpu(cpu_tmp, tmpmask); -+ if (cpu_tmp >= nr_cpu_ids) { -+ cpu_tmp = -1; -+ cpu_tmp = next_cpu(cpu_tmp, tmpmask); -+ } -+ tmp_rq = cpu_rq(cpu_tmp); -+ -+#ifdef CONFIG_NUMA -+ if (rq->cpu_locality[cpu_tmp] > 3) -+ ranking |= CPUIDLE_DIFF_NODE; -+ else -+#endif -+ if (rq->cpu_locality[cpu_tmp] > 2) -+ ranking |= CPUIDLE_DIFF_CPU; -+#ifdef CONFIG_SCHED_MC -+ if (rq->cpu_locality[cpu_tmp] == 2) -+ ranking |= CPUIDLE_DIFF_CORE; -+ if (!(tmp_rq->cache_idle(cpu_tmp))) -+ ranking |= CPUIDLE_CACHE_BUSY; -+#endif -+#ifdef CONFIG_SCHED_SMT -+ if (rq->cpu_locality[cpu_tmp] == 1) -+ ranking |= CPUIDLE_DIFF_THREAD; -+ if (!(tmp_rq->siblings_idle(cpu_tmp))) -+ ranking |= CPUIDLE_THREAD_BUSY; -+#endif -+ if (ranking < best_ranking) { -+ best_cpu = cpu_tmp; -+ if (ranking == 0) -+ break; -+ best_ranking = ranking; -+ } -+ } while (--iterate > 0); -+ -+ resched_task(cpu_rq(best_cpu)->curr); -+} -+ -+static inline void resched_suitable_idle(struct task_struct *p) -+{ -+ if (suitable_idle_cpus(p)) -+ resched_best_idle(p); -+} -+ -+/* -+ * The cpu cache locality difference between CPUs is used to determine how far -+ * to offset the virtual deadline. <2 difference in locality means that one -+ * timeslice difference is allowed longer for the cpu local tasks. This is -+ * enough in the common case when tasks are up to 2* number of CPUs to keep -+ * tasks within their shared cache CPUs only. CPUs on different nodes or not -+ * even in this domain (NUMA) have "4" difference, allowing 4 times longer -+ * deadlines before being taken onto another cpu, allowing for 2* the double -+ * seen by separate CPUs above. -+ * Simple summary: Virtual deadlines are equal on shared cache CPUs, double -+ * on separate CPUs and quadruple in separate NUMA nodes. -+ */ -+static inline int -+cache_distance(struct rq *task_rq, struct rq *rq, struct task_struct *p) -+{ -+ int locality = rq->cpu_locality[cpu_of(task_rq)] - 2; -+ -+ if (locality > 0) -+ return task_timeslice(p) << locality; -+ return 0; -+} -+#else /* CONFIG_SMP */ -+static inline void inc_qnr(void) -+{ -+} -+ -+static inline void dec_qnr(void) -+{ -+} -+ -+static inline int queued_notrunning(void) -+{ -+ return grq.nr_running; -+} -+ -+static inline void set_cpuidle_map(unsigned long cpu) -+{ -+} -+ -+static inline void clear_cpuidle_map(unsigned long cpu) -+{ -+} -+ -+static inline int suitable_idle_cpus(struct task_struct *p) -+{ -+ return uprq->curr == uprq->idle; -+} -+ -+static inline void resched_suitable_idle(struct task_struct *p) -+{ -+} -+ -+static inline int -+cache_distance(struct rq *task_rq, struct rq *rq, struct task_struct *p) -+{ -+ return 0; -+} -+#endif /* CONFIG_SMP */ -+ -+/* -+ * activate_idle_task - move idle task to the _front_ of runqueue. -+ */ -+static inline void activate_idle_task(struct task_struct *p) -+{ -+ enqueue_task_head(p); -+ grq.nr_running++; -+ inc_qnr(); -+} -+ -+static inline int normal_prio(struct task_struct *p) -+{ -+ if (has_rt_policy(p)) -+ return MAX_RT_PRIO - 1 - p->rt_priority; -+ if (idleprio_task(p)) -+ return IDLE_PRIO; -+ if (iso_task(p)) -+ return ISO_PRIO; -+ return NORMAL_PRIO; -+} -+ -+/* -+ * Calculate the current priority, i.e. the priority -+ * taken into account by the scheduler. This value might -+ * be boosted by RT tasks as it will be RT if the task got -+ * RT-boosted. If not then it returns p->normal_prio. -+ */ -+static int effective_prio(struct task_struct *p) -+{ -+ p->normal_prio = normal_prio(p); -+ /* -+ * If we are RT tasks or we were boosted to RT priority, -+ * keep the priority unchanged. Otherwise, update priority -+ * to the normal priority: -+ */ -+ if (!rt_prio(p->prio)) -+ return p->normal_prio; -+ return p->prio; -+} -+ -+/* -+ * activate_task - move a task to the runqueue. Enter with grq locked. -+ */ -+static void activate_task(struct task_struct *p, struct rq *rq) -+{ -+ update_clocks(rq); -+ -+ /* -+ * Sleep time is in units of nanosecs, so shift by 20 to get a -+ * milliseconds-range estimation of the amount of time that the task -+ * spent sleeping: -+ */ -+ if (unlikely(prof_on == SLEEP_PROFILING)) { -+ if (p->state == TASK_UNINTERRUPTIBLE) -+ profile_hits(SLEEP_PROFILING, (void *)get_wchan(p), -+ (rq->clock - p->last_ran) >> 20); -+ } -+ -+ p->prio = effective_prio(p); -+ if (task_contributes_to_load(p)) -+ grq.nr_uninterruptible--; -+ enqueue_task(p); -+ grq.nr_running++; -+ inc_qnr(); -+} -+ -+/* -+ * deactivate_task - If it's running, it's not on the grq and we can just -+ * decrement the nr_running. Enter with grq locked. -+ */ -+static inline void deactivate_task(struct task_struct *p) -+{ -+ if (task_contributes_to_load(p)) -+ grq.nr_uninterruptible++; -+ grq.nr_running--; -+} -+ -+#ifdef CONFIG_SMP -+void set_task_cpu(struct task_struct *p, unsigned int cpu) -+{ -+ trace_sched_migrate_task(p, cpu); -+ if (task_cpu(p) != cpu) -+ perf_sw_event(PERF_COUNT_SW_CPU_MIGRATIONS, 1, 1, NULL, 0); -+ -+ /* -+ * After ->cpu is set up to a new value, task_grq_lock(p, ...) can be -+ * successfuly executed on another CPU. We must ensure that updates of -+ * per-task data have been completed by this moment. -+ */ -+ smp_wmb(); -+ task_thread_info(p)->cpu = cpu; -+} -+#endif -+ -+/* -+ * Move a task off the global queue and take it to a cpu for it will -+ * become the running task. -+ */ -+static inline void take_task(struct rq *rq, struct task_struct *p) -+{ -+ set_task_cpu(p, cpu_of(rq)); -+ dequeue_task(p); -+ dec_qnr(); -+} -+ -+/* -+ * Returns a descheduling task to the grq runqueue unless it is being -+ * deactivated. -+ */ -+static inline void return_task(struct task_struct *p, int deactivate) -+{ -+ if (deactivate) -+ deactivate_task(p); -+ else { -+ inc_qnr(); -+ enqueue_task(p); -+ } -+} -+ -+/* -+ * resched_task - mark a task 'to be rescheduled now'. -+ * -+ * On UP this means the setting of the need_resched flag, on SMP it -+ * might also involve a cross-CPU call to trigger the scheduler on -+ * the target CPU. -+ */ -+#ifdef CONFIG_SMP -+ -+#ifndef tsk_is_polling -+#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG) -+#endif -+ -+static void resched_task(struct task_struct *p) -+{ -+ int cpu; -+ -+ assert_raw_spin_locked(&grq.lock); -+ -+ if (unlikely(test_tsk_thread_flag(p, TIF_NEED_RESCHED))) -+ return; -+ -+ set_tsk_thread_flag(p, TIF_NEED_RESCHED); -+ -+ cpu = task_cpu(p); -+ if (cpu == smp_processor_id()) -+ return; -+ -+ /* NEED_RESCHED must be visible before we test polling */ -+ smp_mb(); -+ if (!tsk_is_polling(p)) -+ smp_send_reschedule(cpu); -+} -+ -+#else -+static inline void resched_task(struct task_struct *p) -+{ -+ assert_raw_spin_locked(&grq.lock); -+ set_tsk_need_resched(p); -+} -+#endif -+ -+/** -+ * task_curr - is this task currently executing on a CPU? -+ * @p: the task in question. -+ */ -+inline int task_curr(const struct task_struct *p) -+{ -+ return cpu_curr(task_cpu(p)) == p; -+} -+ -+#ifdef CONFIG_SMP -+struct migration_req { -+ struct task_struct *task; -+ int dest_cpu; -+}; -+ -+/* -+ * wait_task_inactive - wait for a thread to unschedule. -+ * -+ * If @match_state is nonzero, it's the @p->state value just checked and -+ * not expected to change. If it changes, i.e. @p might have woken up, -+ * then return zero. When we succeed in waiting for @p to be off its CPU, -+ * we return a positive number (its total switch count). If a second call -+ * a short while later returns the same number, the caller can be sure that -+ * @p has remained unscheduled the whole time. -+ * -+ * The caller must ensure that the task *will* unschedule sometime soon, -+ * else this function might spin for a *long* time. This function can't -+ * be called with interrupts off, or it may introduce deadlock with -+ * smp_call_function() if an IPI is sent by the same process we are -+ * waiting to become inactive. -+ */ -+unsigned long wait_task_inactive(struct task_struct *p, long match_state) -+{ -+ unsigned long flags; -+ int running, on_rq; -+ unsigned long ncsw; -+ struct rq *rq; -+ -+ for (;;) { -+ /* -+ * We do the initial early heuristics without holding -+ * any task-queue locks at all. We'll only try to get -+ * the runqueue lock when things look like they will -+ * work out! In the unlikely event rq is dereferenced -+ * since we're lockless, grab it again. -+ */ -+#ifdef CONFIG_SMP -+retry_rq: -+ rq = task_rq(p); -+ if (unlikely(!rq)) -+ goto retry_rq; -+#else /* CONFIG_SMP */ -+ rq = task_rq(p); -+#endif -+ /* -+ * If the task is actively running on another CPU -+ * still, just relax and busy-wait without holding -+ * any locks. -+ * -+ * NOTE! Since we don't hold any locks, it's not -+ * even sure that "rq" stays as the right runqueue! -+ * But we don't care, since this will return false -+ * if the runqueue has changed and p is actually now -+ * running somewhere else! -+ */ -+ while (task_running(p) && p == rq->curr) { -+ if (match_state && unlikely(p->state != match_state)) -+ return 0; -+ cpu_relax(); -+ } -+ -+ /* -+ * Ok, time to look more closely! We need the grq -+ * lock now, to be *sure*. If we're wrong, we'll -+ * just go back and repeat. -+ */ -+ rq = task_grq_lock(p, &flags); -+ trace_sched_wait_task(p); -+ running = task_running(p); -+ on_rq = task_queued(p); -+ ncsw = 0; -+ if (!match_state || p->state == match_state) -+ ncsw = p->nvcsw | LONG_MIN; /* sets MSB */ -+ task_grq_unlock(&flags); -+ -+ /* -+ * If it changed from the expected state, bail out now. -+ */ -+ if (unlikely(!ncsw)) -+ break; -+ -+ /* -+ * Was it really running after all now that we -+ * checked with the proper locks actually held? -+ * -+ * Oops. Go back and try again.. -+ */ -+ if (unlikely(running)) { -+ cpu_relax(); -+ continue; -+ } -+ -+ /* -+ * It's not enough that it's not actively running, -+ * it must be off the runqueue _entirely_, and not -+ * preempted! -+ * -+ * So if it was still runnable (but just not actively -+ * running right now), it's preempted, and we should -+ * yield - it could be a while. -+ */ -+ if (unlikely(on_rq)) { -+ schedule_timeout_uninterruptible(1); -+ continue; -+ } -+ -+ /* -+ * Ahh, all good. It wasn't running, and it wasn't -+ * runnable, which means that it will never become -+ * running in the future either. We're all done! -+ */ -+ break; -+ } -+ -+ return ncsw; -+} -+ -+/*** -+ * kick_process - kick a running thread to enter/exit the kernel -+ * @p: the to-be-kicked thread -+ * -+ * Cause a process which is running on another CPU to enter -+ * kernel-mode, without any delay. (to get signals handled.) -+ * -+ * NOTE: this function doesnt have to take the runqueue lock, -+ * because all it wants to ensure is that the remote task enters -+ * the kernel. If the IPI races and the task has been migrated -+ * to another CPU then no harm is done and the purpose has been -+ * achieved as well. -+ */ -+void kick_process(struct task_struct *p) -+{ -+ int cpu; -+ -+ preempt_disable(); -+ cpu = task_cpu(p); -+ if ((cpu != smp_processor_id()) && task_curr(p)) -+ smp_send_reschedule(cpu); -+ preempt_enable(); -+} -+EXPORT_SYMBOL_GPL(kick_process); -+#endif -+ -+#define rq_idle(rq) ((rq)->rq_prio == PRIO_LIMIT) -+ -+/* -+ * RT tasks preempt purely on priority. SCHED_NORMAL tasks preempt on the -+ * basis of earlier deadlines. SCHED_IDLEPRIO don't preempt anything else or -+ * between themselves, they cooperatively multitask. An idle rq scores as -+ * prio PRIO_LIMIT so it is always preempted. -+ */ -+static inline int -+can_preempt(struct task_struct *p, int prio, u64 deadline, -+ unsigned int policy) -+{ -+ /* Better static priority RT task or better policy preemption */ -+ if (p->prio < prio) -+ return 1; -+ if (p->prio > prio) -+ return 0; -+ /* SCHED_NORMAL, BATCH and ISO will preempt based on deadline */ -+ if (!deadline_before(p->deadline, deadline)) -+ return 0; -+ return 1; -+} -+#ifdef CONFIG_SMP -+#ifdef CONFIG_HOTPLUG_CPU -+/* -+ * Check to see if there is a task that is affined only to offline CPUs but -+ * still wants runtime. This happens to kernel threads during suspend/halt and -+ * disabling of CPUs. -+ */ -+static inline int online_cpus(struct task_struct *p) -+{ -+ return (likely(cpus_intersects(cpu_online_map, p->cpus_allowed))); -+} -+#else /* CONFIG_HOTPLUG_CPU */ -+/* All available CPUs are always online without hotplug. */ -+static inline int online_cpus(struct task_struct *p) -+{ -+ return 1; -+} -+#endif -+ -+/* -+ * Check to see if p can run on cpu, and if not, whether there are any online -+ * CPUs it can run on instead. -+ */ -+static inline int needs_other_cpu(struct task_struct *p, int cpu) -+{ -+ if (unlikely(!cpu_isset(cpu, p->cpus_allowed))) -+ return 1; -+ return 0; -+} -+ -+/* -+ * latest_deadline and highest_prio_rq are initialised only to silence the -+ * compiler. When all else is equal, still prefer this_rq. -+ */ -+static void try_preempt(struct task_struct *p, struct rq *this_rq) -+{ -+ struct rq *highest_prio_rq = this_rq; -+ u64 latest_deadline; -+ unsigned long cpu; -+ int highest_prio; -+ cpumask_t tmp; -+ -+ if (suitable_idle_cpus(p)) { -+ resched_best_idle(p); -+ return; -+ } -+ -+ /* IDLEPRIO tasks never preempt anything */ -+ if (p->policy == SCHED_IDLEPRIO) -+ return; -+ -+ if (likely(online_cpus(p))) -+ cpus_and(tmp, cpu_online_map, p->cpus_allowed); -+ else -+ return; -+ -+ latest_deadline = 0; -+ highest_prio = -1; -+ -+ for_each_cpu_mask(cpu, tmp) { -+ u64 offset_deadline; -+ struct rq *rq; -+ int rq_prio; -+ -+ rq = cpu_rq(cpu); -+ rq_prio = rq->rq_prio; -+ if (rq_prio < highest_prio) -+ continue; -+ -+ offset_deadline = rq->rq_deadline - -+ cache_distance(this_rq, rq, p); -+ -+ if (rq_prio > highest_prio || (rq_prio == highest_prio && -+ deadline_after(offset_deadline, latest_deadline))) { -+ latest_deadline = offset_deadline; -+ highest_prio = rq_prio; -+ highest_prio_rq = rq; -+ } -+ } -+ -+ if (!can_preempt(p, highest_prio, highest_prio_rq->rq_deadline, -+ highest_prio_rq->rq_policy)) -+ return; -+ -+ resched_task(highest_prio_rq->curr); -+} -+#else /* CONFIG_SMP */ -+static inline int needs_other_cpu(struct task_struct *p, int cpu) -+{ -+ return 0; -+} -+ -+static void try_preempt(struct task_struct *p, struct rq *this_rq) -+{ -+ if (p->policy == SCHED_IDLEPRIO) -+ return; -+ if (can_preempt(p, uprq->rq_prio, uprq->rq_deadline, -+ uprq->rq_policy)) -+ resched_task(uprq->curr); -+} -+#endif /* CONFIG_SMP */ -+ -+/** -+ * task_oncpu_function_call - call a function on the cpu on which a task runs -+ * @p: the task to evaluate -+ * @func: the function to be called -+ * @info: the function call argument -+ * -+ * Calls the function @func when the task is currently running. This might -+ * be on the current CPU, which just calls the function directly -+ */ -+void task_oncpu_function_call(struct task_struct *p, -+ void (*func) (void *info), void *info) -+{ -+ int cpu; -+ -+ preempt_disable(); -+ cpu = task_cpu(p); -+ if (task_curr(p)) -+ smp_call_function_single(cpu, func, info, 1); -+ preempt_enable(); -+} -+ -+static inline void ttwu_activate(struct task_struct *p, struct rq *rq, -+ bool is_sync) -+{ -+ activate_task(p, rq); -+ -+ /* -+ * Sync wakeups (i.e. those types of wakeups where the waker -+ * has indicated that it will leave the CPU in short order) -+ * don't trigger a preemption if there are no idle cpus, -+ * instead waiting for current to deschedule. -+ */ -+ if (!is_sync || suitable_idle_cpus(p)) -+ try_preempt(p, rq); -+} -+ -+static inline void ttwu_post_activation(struct task_struct *p, struct rq *rq, -+ bool success) -+{ -+ trace_sched_wakeup(p, success); -+ p->state = TASK_RUNNING; -+ -+ /* -+ * if a worker is waking up, notify workqueue. Note that on BFS, we -+ * don't really know what cpu it will be, so we fake it for -+ * wq_worker_waking_up :/ -+ */ -+ if ((p->flags & PF_WQ_WORKER) && success) -+ wq_worker_waking_up(p, cpu_of(rq)); -+} -+ -+/*** -+ * try_to_wake_up - wake up a thread -+ * @p: the thread to be awakened -+ * @state: the mask of task states that can be woken -+ * @wake_flags: wake modifier flags (WF_*) -+ * -+ * Put it on the run-queue if it's not already there. The "current" -+ * thread is always on the run-queue (except when the actual -+ * re-schedule is in progress), and as such you're allowed to do -+ * the simpler "current->state = TASK_RUNNING" to mark yourself -+ * runnable without the overhead of this. -+ * -+ * Returns %true if @p was woken up, %false if it was already running -+ * or @state didn't match @p's state. -+ */ -+static int try_to_wake_up(struct task_struct *p, unsigned int state, -+ int wake_flags) -+{ -+ unsigned long flags; -+ int success = 0; -+ struct rq *rq; -+ -+ get_cpu(); -+ -+ /* This barrier is undocumented, probably for p->state? ãã */ -+ smp_wmb(); -+ -+ /* -+ * No need to do time_lock_grq as we only need to update the rq clock -+ * if we activate the task -+ */ -+ rq = task_grq_lock(p, &flags); -+ -+ /* state is a volatile long, ã©ã†ã—ã¦ã€åˆ†ã‹ã‚‰ãªã„ */ -+ if (!((unsigned int)p->state & state)) -+ goto out_unlock; -+ -+ if (task_queued(p) || task_running(p)) -+ goto out_running; -+ -+ ttwu_activate(p, rq, wake_flags & WF_SYNC); -+ success = true; -+ -+out_running: -+ ttwu_post_activation(p, rq, success); -+out_unlock: -+ task_grq_unlock(&flags); -+ put_cpu(); -+ -+ return success; -+} -+ -+/** -+ * try_to_wake_up_local - try to wake up a local task with grq lock held -+ * @p: the thread to be awakened -+ * -+ * Put @p on the run-queue if it's not already there. The caller must -+ * ensure that grq is locked and, @p is not the current task. -+ * grq stays locked over invocation. -+ */ -+static void try_to_wake_up_local(struct task_struct *p) -+{ -+ struct rq *rq = task_rq(p); -+ bool success = false; -+ -+ WARN_ON(rq != this_rq()); -+ BUG_ON(p == current); -+ lockdep_assert_held(&grq.lock); -+ -+ if (!(p->state & TASK_NORMAL)) -+ return; -+ -+ if (!task_queued(p)) { -+ if (likely(!task_running(p))) { -+ schedstat_inc(rq, ttwu_count); -+ schedstat_inc(rq, ttwu_local); -+ } -+ ttwu_activate(p, rq, false); -+ success = true; -+ } -+ ttwu_post_activation(p, rq, success); -+} -+ -+/** -+ * wake_up_process - Wake up a specific process -+ * @p: The process to be woken up. -+ * -+ * Attempt to wake up the nominated process and move it to the set of runnable -+ * processes. Returns 1 if the process was woken up, 0 if it was already -+ * running. -+ * -+ * It may be assumed that this function implies a write memory barrier before -+ * changing the task state if and only if any tasks are woken up. -+ */ -+int wake_up_process(struct task_struct *p) -+{ -+ return try_to_wake_up(p, TASK_ALL, 0); -+} -+EXPORT_SYMBOL(wake_up_process); -+ -+int wake_up_state(struct task_struct *p, unsigned int state) -+{ -+ return try_to_wake_up(p, state, 0); -+} -+ -+static void time_slice_expired(struct task_struct *p); -+ -+/* -+ * Perform scheduler related setup for a newly forked process p. -+ * p is forked by current. -+ */ -+void sched_fork(struct task_struct *p, int clone_flags) -+{ -+ struct task_struct *curr; -+ int cpu = get_cpu(); -+ struct rq *rq; -+ -+#ifdef CONFIG_PREEMPT_NOTIFIERS -+ INIT_HLIST_HEAD(&p->preempt_notifiers); -+#endif -+ /* -+ * We mark the process as running here. This guarantees that -+ * nobody will actually run it, and a signal or other external -+ * event cannot wake it up and insert it on the runqueue either. -+ */ -+ p->state = TASK_RUNNING; -+ set_task_cpu(p, cpu); -+ -+ /* Should be reset in fork.c but done here for ease of bfs patching */ -+ p->sched_time = p->stime_pc = p->utime_pc = 0; -+ -+ /* -+ * Revert to default priority/policy on fork if requested. -+ */ -+ if (unlikely(p->sched_reset_on_fork)) { -+ if (p->policy == SCHED_FIFO || p->policy == SCHED_RR) { -+ p->policy = SCHED_NORMAL; -+ p->normal_prio = normal_prio(p); -+ } -+ -+ if (PRIO_TO_NICE(p->static_prio) < 0) { -+ p->static_prio = NICE_TO_PRIO(0); -+ p->normal_prio = p->static_prio; -+ } -+ -+ /* -+ * We don't need the reset flag anymore after the fork. It has -+ * fulfilled its duty: -+ */ -+ p->sched_reset_on_fork = 0; -+ } -+ -+ curr = current; -+ /* -+ * Make sure we do not leak PI boosting priority to the child. -+ */ -+ p->prio = curr->normal_prio; -+ -+ INIT_LIST_HEAD(&p->run_list); -+#if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT) -+ if (unlikely(sched_info_on())) -+ memset(&p->sched_info, 0, sizeof(p->sched_info)); -+#endif -+ -+ p->oncpu = 0; -+ -+#ifdef CONFIG_PREEMPT -+ /* Want to start with kernel preemption disabled. */ -+ task_thread_info(p)->preempt_count = 1; -+#endif -+ if (unlikely(p->policy == SCHED_FIFO)) -+ goto out; -+ /* -+ * Share the timeslice between parent and child, thus the -+ * total amount of pending timeslices in the system doesn't change, -+ * resulting in more scheduling fairness. If it's negative, it won't -+ * matter since that's the same as being 0. current's time_slice is -+ * actually in rq_time_slice when it's running, as is its last_ran -+ * value. rq->rq_deadline is only modified within schedule() so it -+ * is always equal to current->deadline. -+ */ -+ rq = task_grq_lock_irq(curr); -+ if (likely(rq->rq_time_slice >= RESCHED_US * 2)) { -+ rq->rq_time_slice /= 2; -+ p->time_slice = rq->rq_time_slice; -+ } else { -+ /* -+ * Forking task has run out of timeslice. Reschedule it and -+ * start its child with a new time slice and deadline. The -+ * child will end up running first because its deadline will -+ * be slightly earlier. -+ */ -+ rq->rq_time_slice = 0; -+ set_tsk_need_resched(curr); -+ time_slice_expired(p); -+ } -+ p->last_ran = rq->rq_last_ran; -+ task_grq_unlock_irq(); -+out: -+ put_cpu(); -+} -+ -+/* -+ * wake_up_new_task - wake up a newly created task for the first time. -+ * -+ * This function will do some initial scheduler statistics housekeeping -+ * that must be done for every newly created context, then puts the task -+ * on the runqueue and wakes it. -+ */ -+void wake_up_new_task(struct task_struct *p, unsigned long clone_flags) -+{ -+ struct task_struct *parent; -+ unsigned long flags; -+ struct rq *rq; -+ -+ rq = task_grq_lock(p, &flags); -+ p->state = TASK_RUNNING; -+ parent = p->parent; -+ /* Unnecessary but small chance that the parent changed CPU */ -+ set_task_cpu(p, task_cpu(parent)); -+ activate_task(p, rq); -+ trace_sched_wakeup_new(p, 1); -+ if (!(clone_flags & CLONE_VM) && rq->curr == parent && -+ !suitable_idle_cpus(p)) { -+ /* -+ * The VM isn't cloned, so we're in a good position to -+ * do child-runs-first in anticipation of an exec. This -+ * usually avoids a lot of COW overhead. -+ */ -+ resched_task(parent); -+ } else -+ try_preempt(p, rq); -+ task_grq_unlock(&flags); -+} -+ -+#ifdef CONFIG_PREEMPT_NOTIFIERS -+ -+/** -+ * preempt_notifier_register - tell me when current is being preempted & rescheduled -+ * @notifier: notifier struct to register -+ */ -+void preempt_notifier_register(struct preempt_notifier *notifier) -+{ -+ hlist_add_head(¬ifier->link, ¤t->preempt_notifiers); -+} -+EXPORT_SYMBOL_GPL(preempt_notifier_register); -+ -+/** -+ * preempt_notifier_unregister - no longer interested in preemption notifications -+ * @notifier: notifier struct to unregister -+ * -+ * This is safe to call from within a preemption notifier. -+ */ -+void preempt_notifier_unregister(struct preempt_notifier *notifier) -+{ -+ hlist_del(¬ifier->link); -+} -+EXPORT_SYMBOL_GPL(preempt_notifier_unregister); -+ -+static void fire_sched_in_preempt_notifiers(struct task_struct *curr) -+{ -+ struct preempt_notifier *notifier; -+ struct hlist_node *node; -+ -+ hlist_for_each_entry(notifier, node, &curr->preempt_notifiers, link) -+ notifier->ops->sched_in(notifier, raw_smp_processor_id()); -+} -+ -+static void -+fire_sched_out_preempt_notifiers(struct task_struct *curr, -+ struct task_struct *next) -+{ -+ struct preempt_notifier *notifier; -+ struct hlist_node *node; -+ -+ hlist_for_each_entry(notifier, node, &curr->preempt_notifiers, link) -+ notifier->ops->sched_out(notifier, next); -+} -+ -+#else /* !CONFIG_PREEMPT_NOTIFIERS */ -+ -+static void fire_sched_in_preempt_notifiers(struct task_struct *curr) -+{ -+} -+ -+static void -+fire_sched_out_preempt_notifiers(struct task_struct *curr, -+ struct task_struct *next) -+{ -+} -+ -+#endif /* CONFIG_PREEMPT_NOTIFIERS */ -+ -+/** -+ * prepare_task_switch - prepare to switch tasks -+ * @rq: the runqueue preparing to switch -+ * @next: the task we are going to switch to. -+ * -+ * This is called with the rq lock held and interrupts off. It must -+ * be paired with a subsequent finish_task_switch after the context -+ * switch. -+ * -+ * prepare_task_switch sets up locking and calls architecture specific -+ * hooks. -+ */ -+static inline void -+prepare_task_switch(struct rq *rq, struct task_struct *prev, -+ struct task_struct *next) -+{ -+ fire_sched_out_preempt_notifiers(prev, next); -+ prepare_lock_switch(rq, next); -+ prepare_arch_switch(next); -+} -+ -+/** -+ * finish_task_switch - clean up after a task-switch -+ * @rq: runqueue associated with task-switch -+ * @prev: the thread we just switched away from. -+ * -+ * finish_task_switch must be called after the context switch, paired -+ * with a prepare_task_switch call before the context switch. -+ * finish_task_switch will reconcile locking set up by prepare_task_switch, -+ * and do any other architecture-specific cleanup actions. -+ * -+ * Note that we may have delayed dropping an mm in context_switch(). If -+ * so, we finish that here outside of the runqueue lock. (Doing it -+ * with the lock held can cause deadlocks; see schedule() for -+ * details.) -+ */ -+static inline void finish_task_switch(struct rq *rq, struct task_struct *prev) -+ __releases(grq.lock) -+{ -+ struct mm_struct *mm = rq->prev_mm; -+ long prev_state; -+ -+ rq->prev_mm = NULL; -+ -+ /* -+ * A task struct has one reference for the use as "current". -+ * If a task dies, then it sets TASK_DEAD in tsk->state and calls -+ * schedule one last time. The schedule call will never return, and -+ * the scheduled task must drop that reference. -+ * The test for TASK_DEAD must occur while the runqueue locks are -+ * still held, otherwise prev could be scheduled on another cpu, die -+ * there before we look at prev->state, and then the reference would -+ * be dropped twice. -+ * Manfred Spraul -+ */ -+ prev_state = prev->state; -+ finish_arch_switch(prev); -+#ifdef __ARCH_WANT_INTERRUPTS_ON_CTXSW -+ local_irq_disable(); -+#endif /* __ARCH_WANT_INTERRUPTS_ON_CTXSW */ -+ perf_event_task_sched_in(current); -+#ifdef __ARCH_WANT_INTERRUPTS_ON_CTXSW -+ local_irq_enable(); -+#endif /* __ARCH_WANT_INTERRUPTS_ON_CTXSW */ -+ finish_lock_switch(rq, prev); -+ -+ fire_sched_in_preempt_notifiers(current); -+ if (mm) -+ mmdrop(mm); -+ if (unlikely(prev_state == TASK_DEAD)) { -+ /* -+ * Remove function-return probe instances associated with this -+ * task and put them back on the free list. -+ */ -+ kprobe_flush_task(prev); -+ put_task_struct(prev); -+ } -+} -+ -+/** -+ * schedule_tail - first thing a freshly forked thread must call. -+ * @prev: the thread we just switched away from. -+ */ -+asmlinkage void schedule_tail(struct task_struct *prev) -+ __releases(grq.lock) -+{ -+ struct rq *rq = this_rq(); -+ -+ finish_task_switch(rq, prev); -+#ifdef __ARCH_WANT_UNLOCKED_CTXSW -+ /* In this case, finish_task_switch does not reenable preemption */ -+ preempt_enable(); -+#endif -+ if (current->set_child_tid) -+ put_user(current->pid, current->set_child_tid); -+} -+ -+/* -+ * context_switch - switch to the new MM and the new -+ * thread's register state. -+ */ -+static inline void -+context_switch(struct rq *rq, struct task_struct *prev, -+ struct task_struct *next) -+{ -+ struct mm_struct *mm, *oldmm; -+ -+ prepare_task_switch(rq, prev, next); -+ trace_sched_switch(prev, next); -+ mm = next->mm; -+ oldmm = prev->active_mm; -+ /* -+ * For paravirt, this is coupled with an exit in switch_to to -+ * combine the page table reload and the switch backend into -+ * one hypercall. -+ */ -+ arch_start_context_switch(prev); -+ -+ if (!mm) { -+ next->active_mm = oldmm; -+ atomic_inc(&oldmm->mm_count); -+ enter_lazy_tlb(oldmm, next); -+ } else -+ switch_mm(oldmm, mm, next); -+ -+ if (!prev->mm) { -+ prev->active_mm = NULL; -+ rq->prev_mm = oldmm; -+ } -+ /* -+ * Since the runqueue lock will be released by the next -+ * task (which is an invalid locking op but in the case -+ * of the scheduler it's an obvious special-case), so we -+ * do an early lockdep release here: -+ */ -+#ifndef __ARCH_WANT_UNLOCKED_CTXSW -+ spin_release(&grq.lock.dep_map, 1, _THIS_IP_); -+#endif -+ -+ /* Here we just switch the register state and the stack. */ -+ switch_to(prev, next, prev); -+ -+ barrier(); -+ /* -+ * this_rq must be evaluated again because prev may have moved -+ * CPUs since it called schedule(), thus the 'rq' on its stack -+ * frame will be invalid. -+ */ -+ finish_task_switch(this_rq(), prev); -+} -+ -+/* -+ * nr_running, nr_uninterruptible and nr_context_switches: -+ * -+ * externally visible scheduler statistics: current number of runnable -+ * threads, current number of uninterruptible-sleeping threads, total -+ * number of context switches performed since bootup. All are measured -+ * without grabbing the grq lock but the occasional inaccurate result -+ * doesn't matter so long as it's positive. -+ */ -+unsigned long nr_running(void) -+{ -+ long nr = grq.nr_running; -+ -+ if (unlikely(nr < 0)) -+ nr = 0; -+ return (unsigned long)nr; -+} -+ -+unsigned long nr_uninterruptible(void) -+{ -+ long nu = grq.nr_uninterruptible; -+ -+ if (unlikely(nu < 0)) -+ nu = 0; -+ return nu; -+} -+ -+unsigned long long nr_context_switches(void) -+{ -+ long long ns = grq.nr_switches; -+ -+ /* This is of course impossible */ -+ if (unlikely(ns < 0)) -+ ns = 1; -+ return (long long)ns; -+} -+ -+unsigned long nr_iowait(void) -+{ -+ unsigned long i, sum = 0; -+ -+ for_each_possible_cpu(i) -+ sum += atomic_read(&cpu_rq(i)->nr_iowait); -+ -+ return sum; -+} -+ -+unsigned long nr_iowait_cpu(int cpu) -+{ -+ struct rq *this = cpu_rq(cpu); -+ return atomic_read(&this->nr_iowait); -+} -+ -+unsigned long nr_active(void) -+{ -+ return nr_running() + nr_uninterruptible(); -+} -+ -+/* Beyond a task running on this CPU, load is equal everywhere on BFS */ -+unsigned long this_cpu_load(void) -+{ -+ return this_rq()->rq_running + -+ (queued_notrunning() + nr_uninterruptible()) / -+ (1 + num_online_cpus()); -+} -+ -+/* Variables and functions for calc_load */ -+static unsigned long calc_load_update; -+unsigned long avenrun[3]; -+EXPORT_SYMBOL(avenrun); -+ -+/** -+ * get_avenrun - get the load average array -+ * @loads: pointer to dest load array -+ * @offset: offset to add -+ * @shift: shift count to shift the result left -+ * -+ * These values are estimates at best, so no need for locking. -+ */ -+void get_avenrun(unsigned long *loads, unsigned long offset, int shift) -+{ -+ loads[0] = (avenrun[0] + offset) << shift; -+ loads[1] = (avenrun[1] + offset) << shift; -+ loads[2] = (avenrun[2] + offset) << shift; -+} -+ -+static unsigned long -+calc_load(unsigned long load, unsigned long exp, unsigned long active) -+{ -+ load *= exp; -+ load += active * (FIXED_1 - exp); -+ return load >> FSHIFT; -+} -+ -+/* -+ * calc_load - update the avenrun load estimates every LOAD_FREQ seconds. -+ */ -+void calc_global_load(unsigned long ticks) -+{ -+ long active; -+ -+ if (time_before(jiffies, calc_load_update)) -+ return; -+ active = nr_active() * FIXED_1; -+ -+ avenrun[0] = calc_load(avenrun[0], EXP_1, active); -+ avenrun[1] = calc_load(avenrun[1], EXP_5, active); -+ avenrun[2] = calc_load(avenrun[2], EXP_15, active); -+ -+ calc_load_update = jiffies + LOAD_FREQ; -+} -+ -+DEFINE_PER_CPU(struct kernel_stat, kstat); -+ -+EXPORT_PER_CPU_SYMBOL(kstat); -+ -+#ifdef CONFIG_IRQ_TIME_ACCOUNTING -+ -+/* -+ * There are no locks covering percpu hardirq/softirq time. -+ * They are only modified in account_system_vtime, on corresponding CPU -+ * with interrupts disabled. So, writes are safe. -+ * They are read and saved off onto struct rq in update_rq_clock(). -+ * This may result in other CPU reading this CPU's irq time and can -+ * race with irq/account_system_vtime on this CPU. We would either get old -+ * or new value with a side effect of accounting a slice of irq time to wrong -+ * task when irq is in progress while we read rq->clock. That is a worthy -+ * compromise in place of having locks on each irq in account_system_time. -+ */ -+static DEFINE_PER_CPU(u64, cpu_hardirq_time); -+static DEFINE_PER_CPU(u64, cpu_softirq_time); -+ -+static DEFINE_PER_CPU(u64, irq_start_time); -+static int sched_clock_irqtime; -+ -+void enable_sched_clock_irqtime(void) -+{ -+ sched_clock_irqtime = 1; -+} -+ -+void disable_sched_clock_irqtime(void) -+{ -+ sched_clock_irqtime = 0; -+} -+ -+#ifndef CONFIG_64BIT -+static DEFINE_PER_CPU(seqcount_t, irq_time_seq); -+ -+static inline void irq_time_write_begin(void) -+{ -+ __this_cpu_inc(irq_time_seq.sequence); -+ smp_wmb(); -+} -+ -+static inline void irq_time_write_end(void) -+{ -+ smp_wmb(); -+ __this_cpu_inc(irq_time_seq.sequence); -+} -+ -+static inline u64 irq_time_read(int cpu) -+{ -+ u64 irq_time; -+ unsigned seq; -+ -+ do { -+ seq = read_seqcount_begin(&per_cpu(irq_time_seq, cpu)); -+ irq_time = per_cpu(cpu_softirq_time, cpu) + -+ per_cpu(cpu_hardirq_time, cpu); -+ } while (read_seqcount_retry(&per_cpu(irq_time_seq, cpu), seq)); -+ -+ return irq_time; -+} -+#else /* CONFIG_64BIT */ -+static inline void irq_time_write_begin(void) -+{ -+} -+ -+static inline void irq_time_write_end(void) -+{ -+} -+ -+static inline u64 irq_time_read(int cpu) -+{ -+ return per_cpu(cpu_softirq_time, cpu) + per_cpu(cpu_hardirq_time, cpu); -+} -+#endif /* CONFIG_64BIT */ -+ -+/* -+ * Called before incrementing preempt_count on {soft,}irq_enter -+ * and before decrementing preempt_count on {soft,}irq_exit. -+ */ -+void account_system_vtime(struct task_struct *curr) -+{ -+ unsigned long flags; -+ s64 delta; -+ int cpu; -+ -+ if (!sched_clock_irqtime) -+ return; -+ -+ local_irq_save(flags); -+ -+ cpu = smp_processor_id(); -+ delta = sched_clock_cpu(cpu) - __this_cpu_read(irq_start_time); -+ __this_cpu_add(irq_start_time, delta); -+ -+ irq_time_write_begin(); -+ /* -+ * We do not account for softirq time from ksoftirqd here. -+ * We want to continue accounting softirq time to ksoftirqd thread -+ * in that case, so as not to confuse scheduler with a special task -+ * that do not consume any time, but still wants to run. -+ */ -+ if (hardirq_count()) -+ __this_cpu_add(cpu_hardirq_time, delta); -+ else if (in_serving_softirq() && !(curr->flags & PF_KSOFTIRQD)) -+ __this_cpu_add(cpu_softirq_time, delta); -+ -+ irq_time_write_end(); -+ local_irq_restore(flags); -+} -+EXPORT_SYMBOL_GPL(account_system_vtime); -+ -+static void update_rq_clock_task(struct rq *rq, s64 delta) -+{ -+ s64 irq_delta; -+ -+ irq_delta = irq_time_read(cpu_of(rq)) - rq->prev_irq_time; -+ -+ /* -+ * Since irq_time is only updated on {soft,}irq_exit, we might run into -+ * this case when a previous update_rq_clock() happened inside a -+ * {soft,}irq region. -+ * -+ * When this happens, we stop ->clock_task and only update the -+ * prev_irq_time stamp to account for the part that fit, so that a next -+ * update will consume the rest. This ensures ->clock_task is -+ * monotonic. -+ * -+ * It does however cause some slight miss-attribution of {soft,}irq -+ * time, a more accurate solution would be to update the irq_time using -+ * the current rq->clock timestamp, except that would require using -+ * atomic ops. -+ */ -+ if (irq_delta > delta) -+ irq_delta = delta; -+ -+ rq->prev_irq_time += irq_delta; -+ delta -= irq_delta; -+ rq->clock_task += delta; -+} -+ -+#else /* CONFIG_IRQ_TIME_ACCOUNTING */ -+ -+static void update_rq_clock_task(struct rq *rq, s64 delta) -+{ -+ rq->clock_task += delta; -+} -+ -+#endif /* CONFIG_IRQ_TIME_ACCOUNTING */ -+ -+/* -+ * On each tick, see what percentage of that tick was attributed to each -+ * component and add the percentage to the _pc values. Once a _pc value has -+ * accumulated one tick's worth, account for that. This means the total -+ * percentage of load components will always be 100 per tick. -+ */ -+static void pc_idle_time(struct rq *rq, unsigned long pc) -+{ -+ struct cpu_usage_stat *cpustat = &kstat_this_cpu.cpustat; -+ cputime64_t tmp = cputime_to_cputime64(cputime_one_jiffy); -+ -+ if (atomic_read(&rq->nr_iowait) > 0) { -+ rq->iowait_pc += pc; -+ if (rq->iowait_pc >= 100) { -+ rq->iowait_pc %= 100; -+ cpustat->iowait = cputime64_add(cpustat->iowait, tmp); -+ } -+ } else { -+ rq->idle_pc += pc; -+ if (rq->idle_pc >= 100) { -+ rq->idle_pc %= 100; -+ cpustat->idle = cputime64_add(cpustat->idle, tmp); -+ } -+ } -+} -+ -+static void -+pc_system_time(struct rq *rq, struct task_struct *p, int hardirq_offset, -+ unsigned long pc, unsigned long ns) -+{ -+ struct cpu_usage_stat *cpustat = &kstat_this_cpu.cpustat; -+ cputime_t one_jiffy_scaled = cputime_to_scaled(cputime_one_jiffy); -+ cputime64_t tmp = cputime_to_cputime64(cputime_one_jiffy); -+ -+ p->stime_pc += pc; -+ if (p->stime_pc >= 100) { -+ p->stime_pc -= 100; -+ p->stime = cputime_add(p->stime, cputime_one_jiffy); -+ p->stimescaled = cputime_add(p->stimescaled, one_jiffy_scaled); -+ account_group_system_time(p, cputime_one_jiffy); -+ acct_update_integrals(p); -+ } -+ p->sched_time += ns; -+ -+ if (hardirq_count() - hardirq_offset) { -+ rq->irq_pc += pc; -+ if (rq->irq_pc >= 100) { -+ rq->irq_pc %= 100; -+ cpustat->irq = cputime64_add(cpustat->irq, tmp); -+ } -+ } else if (in_serving_softirq()) { -+ rq->softirq_pc += pc; -+ if (rq->softirq_pc >= 100) { -+ rq->softirq_pc %= 100; -+ cpustat->softirq = cputime64_add(cpustat->softirq, tmp); -+ } -+ } else { -+ rq->system_pc += pc; -+ if (rq->system_pc >= 100) { -+ rq->system_pc %= 100; -+ cpustat->system = cputime64_add(cpustat->system, tmp); -+ } -+ } -+} -+ -+static void pc_user_time(struct rq *rq, struct task_struct *p, -+ unsigned long pc, unsigned long ns) -+{ -+ struct cpu_usage_stat *cpustat = &kstat_this_cpu.cpustat; -+ cputime_t one_jiffy_scaled = cputime_to_scaled(cputime_one_jiffy); -+ cputime64_t tmp = cputime_to_cputime64(cputime_one_jiffy); -+ -+ p->utime_pc += pc; -+ if (p->utime_pc >= 100) { -+ p->utime_pc -= 100; -+ p->utime = cputime_add(p->utime, cputime_one_jiffy); -+ p->utimescaled = cputime_add(p->utimescaled, one_jiffy_scaled); -+ account_group_user_time(p, cputime_one_jiffy); -+ acct_update_integrals(p); -+ } -+ p->sched_time += ns; -+ -+ if (TASK_NICE(p) > 0 || idleprio_task(p)) { -+ rq->nice_pc += pc; -+ if (rq->nice_pc >= 100) { -+ rq->nice_pc %= 100; -+ cpustat->nice = cputime64_add(cpustat->nice, tmp); -+ } -+ } else { -+ rq->user_pc += pc; -+ if (rq->user_pc >= 100) { -+ rq->user_pc %= 100; -+ cpustat->user = cputime64_add(cpustat->user, tmp); -+ } -+ } -+} -+ -+/* Convert nanoseconds to percentage of one tick. */ -+#define NS_TO_PC(NS) (NS * 100 / JIFFY_NS) -+ -+/* -+ * This is called on clock ticks and on context switches. -+ * Bank in p->sched_time the ns elapsed since the last tick or switch. -+ * CPU scheduler quota accounting is also performed here in microseconds. -+ */ -+static void -+update_cpu_clock(struct rq *rq, struct task_struct *p, int tick) -+{ -+ long account_ns = rq->clock - rq->timekeep_clock; -+ struct task_struct *idle = rq->idle; -+ unsigned long account_pc; -+ -+ if (unlikely(account_ns < 0)) -+ account_ns = 0; -+ -+ account_pc = NS_TO_PC(account_ns); -+ -+ if (tick) { -+ int user_tick = user_mode(get_irq_regs()); -+ -+ /* Accurate tick timekeeping */ -+ if (user_tick) -+ pc_user_time(rq, p, account_pc, account_ns); -+ else if (p != idle || (irq_count() != HARDIRQ_OFFSET)) -+ pc_system_time(rq, p, HARDIRQ_OFFSET, -+ account_pc, account_ns); -+ else -+ pc_idle_time(rq, account_pc); -+ } else { -+ /* Accurate subtick timekeeping */ -+ if (p == idle) -+ pc_idle_time(rq, account_pc); -+ else -+ pc_user_time(rq, p, account_pc, account_ns); -+ } -+ -+ /* time_slice accounting is done in usecs to avoid overflow on 32bit */ -+ if (rq->rq_policy != SCHED_FIFO && p != idle) { -+ s64 time_diff = rq->clock - rq->rq_last_ran; -+ -+ niffy_diff(&time_diff, 1); -+ rq->rq_time_slice -= NS_TO_US(time_diff); -+ } -+ rq->rq_last_ran = rq->timekeep_clock = rq->clock; -+} -+ -+/* -+ * Return any ns on the sched_clock that have not yet been accounted in -+ * @p in case that task is currently running. -+ * -+ * Called with task_grq_lock() held. -+ */ -+static u64 do_task_delta_exec(struct task_struct *p, struct rq *rq) -+{ -+ u64 ns = 0; -+ -+ if (p == rq->curr) { -+ update_clocks(rq); -+ ns = rq->clock_task - rq->rq_last_ran; -+ if (unlikely((s64)ns < 0)) -+ ns = 0; -+ } -+ -+ return ns; -+} -+ -+unsigned long long task_delta_exec(struct task_struct *p) -+{ -+ unsigned long flags; -+ struct rq *rq; -+ u64 ns; -+ -+ rq = task_grq_lock(p, &flags); -+ ns = do_task_delta_exec(p, rq); -+ task_grq_unlock(&flags); -+ -+ return ns; -+} -+ -+/* -+ * Return accounted runtime for the task. -+ * In case the task is currently running, return the runtime plus current's -+ * pending runtime that have not been accounted yet. -+ */ -+unsigned long long task_sched_runtime(struct task_struct *p) -+{ -+ unsigned long flags; -+ struct rq *rq; -+ u64 ns; -+ -+ rq = task_grq_lock(p, &flags); -+ ns = p->sched_time + do_task_delta_exec(p, rq); -+ task_grq_unlock(&flags); -+ -+ return ns; -+} -+ -+/* -+ * Return sum_exec_runtime for the thread group. -+ * In case the task is currently running, return the sum plus current's -+ * pending runtime that have not been accounted yet. -+ * -+ * Note that the thread group might have other running tasks as well, -+ * so the return value not includes other pending runtime that other -+ * running tasks might have. -+ */ -+unsigned long long thread_group_sched_runtime(struct task_struct *p) -+{ -+ struct task_cputime totals; -+ unsigned long flags; -+ struct rq *rq; -+ u64 ns; -+ -+ rq = task_grq_lock(p, &flags); -+ thread_group_cputime(p, &totals); -+ ns = totals.sum_exec_runtime + do_task_delta_exec(p, rq); -+ task_grq_unlock(&flags); -+ -+ return ns; -+} -+ -+/* Compatibility crap for removal */ -+void account_user_time(struct task_struct *p, cputime_t cputime, -+ cputime_t cputime_scaled) -+{ -+} -+ -+void account_idle_time(cputime_t cputime) -+{ -+} -+ -+/* -+ * Account guest cpu time to a process. -+ * @p: the process that the cpu time gets accounted to -+ * @cputime: the cpu time spent in virtual machine since the last update -+ * @cputime_scaled: cputime scaled by cpu frequency -+ */ -+static void account_guest_time(struct task_struct *p, cputime_t cputime, -+ cputime_t cputime_scaled) -+{ -+ cputime64_t tmp; -+ struct cpu_usage_stat *cpustat = &kstat_this_cpu.cpustat; -+ -+ tmp = cputime_to_cputime64(cputime); -+ -+ /* Add guest time to process. */ -+ p->utime = cputime_add(p->utime, cputime); -+ p->utimescaled = cputime_add(p->utimescaled, cputime_scaled); -+ account_group_user_time(p, cputime); -+ p->gtime = cputime_add(p->gtime, cputime); -+ -+ /* Add guest time to cpustat. */ -+ if (TASK_NICE(p) > 0) { -+ cpustat->nice = cputime64_add(cpustat->nice, tmp); -+ cpustat->guest_nice = cputime64_add(cpustat->guest_nice, tmp); -+ } else { -+ cpustat->user = cputime64_add(cpustat->user, tmp); -+ cpustat->guest = cputime64_add(cpustat->guest, tmp); -+ } -+} -+ -+/* -+ * Account system cpu time to a process. -+ * @p: the process that the cpu time gets accounted to -+ * @hardirq_offset: the offset to subtract from hardirq_count() -+ * @cputime: the cpu time spent in kernel space since the last update -+ * @cputime_scaled: cputime scaled by cpu frequency -+ * This is for guest only now. -+ */ -+void account_system_time(struct task_struct *p, int hardirq_offset, -+ cputime_t cputime, cputime_t cputime_scaled) -+{ -+ -+ if ((p->flags & PF_VCPU) && (irq_count() - hardirq_offset == 0)) -+ account_guest_time(p, cputime, cputime_scaled); -+} -+ -+/* -+ * Account for involuntary wait time. -+ * @steal: the cpu time spent in involuntary wait -+ */ -+void account_steal_time(cputime_t cputime) -+{ -+ struct cpu_usage_stat *cpustat = &kstat_this_cpu.cpustat; -+ cputime64_t cputime64 = cputime_to_cputime64(cputime); -+ -+ cpustat->steal = cputime64_add(cpustat->steal, cputime64); -+} -+ -+/* -+ * Account for idle time. -+ * @cputime: the cpu time spent in idle wait -+ */ -+static void account_idle_times(cputime_t cputime) -+{ -+ struct cpu_usage_stat *cpustat = &kstat_this_cpu.cpustat; -+ cputime64_t cputime64 = cputime_to_cputime64(cputime); -+ struct rq *rq = this_rq(); -+ -+ if (atomic_read(&rq->nr_iowait) > 0) -+ cpustat->iowait = cputime64_add(cpustat->iowait, cputime64); -+ else -+ cpustat->idle = cputime64_add(cpustat->idle, cputime64); -+} -+ -+#ifndef CONFIG_VIRT_CPU_ACCOUNTING -+ -+void account_process_tick(struct task_struct *p, int user_tick) -+{ -+} -+ -+/* -+ * Account multiple ticks of steal time. -+ * @p: the process from which the cpu time has been stolen -+ * @ticks: number of stolen ticks -+ */ -+void account_steal_ticks(unsigned long ticks) -+{ -+ account_steal_time(jiffies_to_cputime(ticks)); -+} -+ -+/* -+ * Account multiple ticks of idle time. -+ * @ticks: number of stolen ticks -+ */ -+void account_idle_ticks(unsigned long ticks) -+{ -+ account_idle_times(jiffies_to_cputime(ticks)); -+} -+#endif -+ -+static inline void grq_iso_lock(void) -+ __acquires(grq.iso_lock) -+{ -+ raw_spin_lock(&grq.iso_lock); -+} -+ -+static inline void grq_iso_unlock(void) -+ __releases(grq.iso_lock) -+{ -+ raw_spin_unlock(&grq.iso_lock); -+} -+ -+/* -+ * Functions to test for when SCHED_ISO tasks have used their allocated -+ * quota as real time scheduling and convert them back to SCHED_NORMAL. -+ * Where possible, the data is tested lockless, to avoid grabbing iso_lock -+ * because the occasional inaccurate result won't matter. However the -+ * tick data is only ever modified under lock. iso_refractory is only simply -+ * set to 0 or 1 so it's not worth grabbing the lock yet again for that. -+ */ -+static void set_iso_refractory(void) -+{ -+ grq.iso_refractory = 1; -+} -+ -+static void clear_iso_refractory(void) -+{ -+ grq.iso_refractory = 0; -+} -+ -+/* -+ * Test if SCHED_ISO tasks have run longer than their alloted period as RT -+ * tasks and set the refractory flag if necessary. There is 10% hysteresis -+ * for unsetting the flag. 115/128 is ~90/100 as a fast shift instead of a -+ * slow division. -+ */ -+static unsigned int test_ret_isorefractory(struct rq *rq) -+{ -+ if (likely(!grq.iso_refractory)) { -+ if (grq.iso_ticks > ISO_PERIOD * sched_iso_cpu) -+ set_iso_refractory(); -+ } else { -+ if (grq.iso_ticks < ISO_PERIOD * (sched_iso_cpu * 115 / 128)) -+ clear_iso_refractory(); -+ } -+ return grq.iso_refractory; -+} -+ -+static void iso_tick(void) -+{ -+ grq_iso_lock(); -+ grq.iso_ticks += 100; -+ grq_iso_unlock(); -+} -+ -+/* No SCHED_ISO task was running so decrease rq->iso_ticks */ -+static inline void no_iso_tick(void) -+{ -+ if (grq.iso_ticks) { -+ grq_iso_lock(); -+ grq.iso_ticks -= grq.iso_ticks / ISO_PERIOD + 1; -+ if (unlikely(grq.iso_refractory && grq.iso_ticks < -+ ISO_PERIOD * (sched_iso_cpu * 115 / 128))) -+ clear_iso_refractory(); -+ grq_iso_unlock(); -+ } -+} -+ -+static int rq_running_iso(struct rq *rq) -+{ -+ return rq->rq_prio == ISO_PRIO; -+} -+ -+/* This manages tasks that have run out of timeslice during a scheduler_tick */ -+static void task_running_tick(struct rq *rq) -+{ -+ struct task_struct *p; -+ -+ /* -+ * If a SCHED_ISO task is running we increment the iso_ticks. In -+ * order to prevent SCHED_ISO tasks from causing starvation in the -+ * presence of true RT tasks we account those as iso_ticks as well. -+ */ -+ if ((rt_queue(rq) || (iso_queue(rq) && !grq.iso_refractory))) { -+ if (grq.iso_ticks <= (ISO_PERIOD * 100) - 100) -+ iso_tick(); -+ } else -+ no_iso_tick(); -+ -+ if (iso_queue(rq)) { -+ if (unlikely(test_ret_isorefractory(rq))) { -+ if (rq_running_iso(rq)) { -+ /* -+ * SCHED_ISO task is running as RT and limit -+ * has been hit. Force it to reschedule as -+ * SCHED_NORMAL by zeroing its time_slice -+ */ -+ rq->rq_time_slice = 0; -+ } -+ } -+ } -+ -+ /* SCHED_FIFO tasks never run out of timeslice. */ -+ if (rq->rq_policy == SCHED_FIFO) -+ return; -+ /* -+ * Tasks that were scheduled in the first half of a tick are not -+ * allowed to run into the 2nd half of the next tick if they will -+ * run out of time slice in the interim. Otherwise, if they have -+ * less than RESCHED_US μs of time slice left they will be rescheduled. -+ */ -+ if (rq->dither) { -+ if (rq->rq_time_slice > HALF_JIFFY_US) -+ return; -+ else -+ rq->rq_time_slice = 0; -+ } else if (rq->rq_time_slice >= RESCHED_US) -+ return; -+ -+ /* p->time_slice < RESCHED_US. We only modify task_struct under grq lock */ -+ p = rq->curr; -+ requeue_task(p); -+ grq_lock(); -+ set_tsk_need_resched(p); -+ grq_unlock(); -+} -+ -+void wake_up_idle_cpu(int cpu); -+ -+/* -+ * This function gets called by the timer code, with HZ frequency. -+ * We call it with interrupts disabled. The data modified is all -+ * local to struct rq so we don't need to grab grq lock. -+ */ -+void scheduler_tick(void) -+{ -+ int cpu __maybe_unused = smp_processor_id(); -+ struct rq *rq = cpu_rq(cpu); -+ -+ sched_clock_tick(); -+ /* grq lock not grabbed, so only update rq clock */ -+ update_rq_clock(rq); -+ update_cpu_clock(rq, rq->curr, 1); -+ if (!rq_idle(rq)) -+ task_running_tick(rq); -+ else -+ no_iso_tick(); -+ rq->last_tick = rq->clock; -+ perf_event_task_tick(); -+} -+ -+notrace unsigned long get_parent_ip(unsigned long addr) -+{ -+ if (in_lock_functions(addr)) { -+ addr = CALLER_ADDR2; -+ if (in_lock_functions(addr)) -+ addr = CALLER_ADDR3; -+ } -+ return addr; -+} -+ -+#if defined(CONFIG_PREEMPT) && (defined(CONFIG_DEBUG_PREEMPT) || \ -+ defined(CONFIG_PREEMPT_TRACER)) -+void __kprobes add_preempt_count(int val) -+{ -+#ifdef CONFIG_DEBUG_PREEMPT -+ /* -+ * Underflow? -+ */ -+ if (DEBUG_LOCKS_WARN_ON((preempt_count() < 0))) -+ return; -+#endif -+ preempt_count() += val; -+#ifdef CONFIG_DEBUG_PREEMPT -+ /* -+ * Spinlock count overflowing soon? -+ */ -+ DEBUG_LOCKS_WARN_ON((preempt_count() & PREEMPT_MASK) >= -+ PREEMPT_MASK - 10); -+#endif -+ if (preempt_count() == val) -+ trace_preempt_off(CALLER_ADDR0, get_parent_ip(CALLER_ADDR1)); -+} -+EXPORT_SYMBOL(add_preempt_count); -+ -+void __kprobes sub_preempt_count(int val) -+{ -+#ifdef CONFIG_DEBUG_PREEMPT -+ /* -+ * Underflow? -+ */ -+ if (DEBUG_LOCKS_WARN_ON(val > preempt_count())) -+ return; -+ /* -+ * Is the spinlock portion underflowing? -+ */ -+ if (DEBUG_LOCKS_WARN_ON((val < PREEMPT_MASK) && -+ !(preempt_count() & PREEMPT_MASK))) -+ return; -+#endif -+ -+ if (preempt_count() == val) -+ trace_preempt_on(CALLER_ADDR0, get_parent_ip(CALLER_ADDR1)); -+ preempt_count() -= val; -+} -+EXPORT_SYMBOL(sub_preempt_count); -+#endif -+ -+/* -+ * Deadline is "now" in niffies + (offset by priority). Setting the deadline -+ * is the key to everything. It distributes cpu fairly amongst tasks of the -+ * same nice value, it proportions cpu according to nice level, it means the -+ * task that last woke up the longest ago has the earliest deadline, thus -+ * ensuring that interactive tasks get low latency on wake up. The CPU -+ * proportion works out to the square of the virtual deadline difference, so -+ * this equation will give nice 19 3% CPU compared to nice 0. -+ */ -+static inline u64 prio_deadline_diff(int user_prio) -+{ -+ return (prio_ratios[user_prio] * rr_interval * (MS_TO_NS(1) / 128)); -+} -+ -+static inline u64 task_deadline_diff(struct task_struct *p) -+{ -+ return prio_deadline_diff(TASK_USER_PRIO(p)); -+} -+ -+static inline u64 static_deadline_diff(int static_prio) -+{ -+ return prio_deadline_diff(USER_PRIO(static_prio)); -+} -+ -+static inline int ms_longest_deadline_diff(void) -+{ -+ return NS_TO_MS(prio_deadline_diff(39)); -+} -+ -+/* -+ * The time_slice is only refilled when it is empty and that is when we set a -+ * new deadline. -+ */ -+static void time_slice_expired(struct task_struct *p) -+{ -+ p->time_slice = timeslice(); -+ p->deadline = grq.niffies + task_deadline_diff(p); -+} -+ -+/* -+ * Timeslices below RESCHED_US are considered as good as expired as there's no -+ * point rescheduling when there's so little time left. SCHED_BATCH tasks -+ * have been flagged be not latency sensitive and likely to be fully CPU -+ * bound so every time they're rescheduled they have their time_slice -+ * refilled, but get a new later deadline to have little effect on -+ * SCHED_NORMAL tasks. -+ -+ */ -+static inline void check_deadline(struct task_struct *p) -+{ -+ if (p->time_slice < RESCHED_US || batch_task(p)) -+ time_slice_expired(p); -+} -+ -+/* -+ * O(n) lookup of all tasks in the global runqueue. The real brainfuck -+ * of lock contention and O(n). It's not really O(n) as only the queued, -+ * but not running tasks are scanned, and is O(n) queued in the worst case -+ * scenario only because the right task can be found before scanning all of -+ * them. -+ * Tasks are selected in this order: -+ * Real time tasks are selected purely by their static priority and in the -+ * order they were queued, so the lowest value idx, and the first queued task -+ * of that priority value is chosen. -+ * If no real time tasks are found, the SCHED_ISO priority is checked, and -+ * all SCHED_ISO tasks have the same priority value, so they're selected by -+ * the earliest deadline value. -+ * If no SCHED_ISO tasks are found, SCHED_NORMAL tasks are selected by the -+ * earliest deadline. -+ * Finally if no SCHED_NORMAL tasks are found, SCHED_IDLEPRIO tasks are -+ * selected by the earliest deadline. -+ */ -+static inline struct -+task_struct *earliest_deadline_task(struct rq *rq, struct task_struct *idle) -+{ -+ u64 dl, earliest_deadline = 0; /* Initialise to silence compiler */ -+ struct task_struct *p, *edt = idle; -+ unsigned int cpu = cpu_of(rq); -+ struct list_head *queue; -+ int idx = 0; -+ -+retry: -+ idx = find_next_bit(grq.prio_bitmap, PRIO_LIMIT, idx); -+ if (idx >= PRIO_LIMIT) -+ goto out; -+ queue = grq.queue + idx; -+ list_for_each_entry(p, queue, run_list) { -+ /* Make sure cpu affinity is ok */ -+ if (needs_other_cpu(p, cpu)) -+ continue; -+ if (idx < MAX_RT_PRIO) { -+ /* We found an rt task */ -+ edt = p; -+ goto out_take; -+ } -+ -+ dl = p->deadline + cache_distance(task_rq(p), rq, p); -+ -+ /* -+ * No rt tasks. Find the earliest deadline task. Now we're in -+ * O(n) territory. This is what we silenced the compiler for: -+ * edt will always start as idle. -+ */ -+ if (edt == idle || -+ deadline_before(dl, earliest_deadline)) { -+ earliest_deadline = dl; -+ edt = p; -+ } -+ } -+ if (edt == idle) { -+ if (++idx < PRIO_LIMIT) -+ goto retry; -+ goto out; -+ } -+out_take: -+ take_task(rq, edt); -+out: -+ return edt; -+} -+ -+/* -+ * Print scheduling while atomic bug: -+ */ -+static noinline void __schedule_bug(struct task_struct *prev) -+{ -+ struct pt_regs *regs = get_irq_regs(); -+ -+ printk(KERN_ERR "BUG: scheduling while atomic: %s/%d/0x%08x\n", -+ prev->comm, prev->pid, preempt_count()); -+ -+ debug_show_held_locks(prev); -+ print_modules(); -+ if (irqs_disabled()) -+ print_irqtrace_events(prev); -+ -+ if (regs) -+ show_regs(regs); -+ else -+ dump_stack(); -+} -+ -+/* -+ * Various schedule()-time debugging checks and statistics: -+ */ -+static inline void schedule_debug(struct task_struct *prev) -+{ -+ /* -+ * Test if we are atomic. Since do_exit() needs to call into -+ * schedule() atomically, we ignore that path for now. -+ * Otherwise, whine if we are scheduling when we should not be. -+ */ -+ if (unlikely(in_atomic_preempt_off() && !prev->exit_state)) -+ __schedule_bug(prev); -+ -+ profile_hit(SCHED_PROFILING, __builtin_return_address(0)); -+ -+ schedstat_inc(this_rq(), sched_count); -+#ifdef CONFIG_SCHEDSTATS -+ if (unlikely(prev->lock_depth >= 0)) { -+ schedstat_inc(this_rq(), bkl_count); -+ schedstat_inc(prev, sched_info.bkl_count); -+ } -+#endif -+} -+ -+/* -+ * The currently running task's information is all stored in rq local data -+ * which is only modified by the local CPU, thereby allowing the data to be -+ * changed without grabbing the grq lock. -+ */ -+static inline void set_rq_task(struct rq *rq, struct task_struct *p) -+{ -+ rq->rq_time_slice = p->time_slice; -+ rq->rq_deadline = p->deadline; -+ rq->rq_last_ran = p->last_ran; -+ rq->rq_policy = p->policy; -+ rq->rq_prio = p->prio; -+ if (p != rq->idle) -+ rq->rq_running = 1; -+ else -+ rq->rq_running = 0; -+} -+ -+static void reset_rq_task(struct rq *rq, struct task_struct *p) -+{ -+ rq->rq_policy = p->policy; -+ rq->rq_prio = p->prio; -+} -+ -+/* -+ * schedule() is the main scheduler function. -+ */ -+asmlinkage void __sched schedule(void) -+{ -+ struct task_struct *prev, *next, *idle; -+ unsigned long *switch_count; -+ int deactivate, cpu; -+ struct rq *rq; -+ -+need_resched: -+ preempt_disable(); -+ -+ cpu = smp_processor_id(); -+ rq = cpu_rq(cpu); -+ idle = rq->idle; -+ rcu_note_context_switch(cpu); -+ prev = rq->curr; -+ -+ release_kernel_lock(prev); -+need_resched_nonpreemptible: -+ -+ deactivate = 0; -+ schedule_debug(prev); -+ -+ grq_lock_irq(); -+ update_clocks(rq); -+ update_cpu_clock(rq, prev, 0); -+ if (rq->clock - rq->last_tick > HALF_JIFFY_NS) -+ rq->dither = 0; -+ else -+ rq->dither = 1; -+ -+ clear_tsk_need_resched(prev); -+ -+ switch_count = &prev->nivcsw; -+ if (prev->state && !(preempt_count() & PREEMPT_ACTIVE)) { -+ if (unlikely(signal_pending_state(prev->state, prev))) { -+ prev->state = TASK_RUNNING; -+ } else { -+ deactivate = 1; -+ /* -+ * If a worker is going to sleep, notify and -+ * ask workqueue whether it wants to wake up a -+ * task to maintain concurrency. If so, wake -+ * up the task. -+ */ -+ if (prev->flags & PF_WQ_WORKER) { -+ struct task_struct *to_wakeup; -+ -+ to_wakeup = wq_worker_sleeping(prev, cpu); -+ if (to_wakeup) { -+ /* This shouldn't happen, but does */ -+ if (unlikely(to_wakeup == prev)) -+ deactivate = 0; -+ else -+ try_to_wake_up_local(to_wakeup); -+ } -+ } -+ } -+ switch_count = &prev->nvcsw; -+ } -+ -+ if (prev != idle) { -+ /* Update all the information stored on struct rq */ -+ prev->time_slice = rq->rq_time_slice; -+ prev->deadline = rq->rq_deadline; -+ check_deadline(prev); -+ prev->last_ran = rq->clock; -+ -+ /* Task changed affinity off this CPU */ -+ if (needs_other_cpu(prev, cpu)) -+ resched_suitable_idle(prev); -+ else if (!deactivate) { -+ if (!queued_notrunning()) { -+ /* -+ * We now know prev is the only thing that is -+ * awaiting CPU so we can bypass rechecking for -+ * the earliest deadline task and just run it -+ * again. -+ */ -+ grq_unlock_irq(); -+ goto rerun_prev_unlocked; -+ } else { -+ /* -+ * If prev got kicked off by a task that has to -+ * run on this CPU for affinity reasons then -+ * there may be an idle CPU it can go to. -+ */ -+ resched_suitable_idle(prev); -+ } -+ } -+ return_task(prev, deactivate); -+ } -+ -+ if (unlikely(!queued_notrunning())) { -+ /* -+ * This CPU is now truly idle as opposed to when idle is -+ * scheduled as a high priority task in its own right. -+ */ -+ next = idle; -+ schedstat_inc(rq, sched_goidle); -+ set_cpuidle_map(cpu); -+ } else { -+ next = earliest_deadline_task(rq, idle); -+ prefetch(next); -+ prefetch_stack(next); -+ clear_cpuidle_map(cpu); -+ } -+ -+ if (likely(prev != next)) { -+ sched_info_switch(prev, next); -+ perf_event_task_sched_out(prev, next); -+ -+ set_rq_task(rq, next); -+ grq.nr_switches++; -+ prev->oncpu = 0; -+ next->oncpu = 1; -+ rq->curr = next; -+ ++*switch_count; -+ -+ context_switch(rq, prev, next); /* unlocks the grq */ -+ /* -+ * The context switch have flipped the stack from under us -+ * and restored the local variables which were saved when -+ * this task called schedule() in the past. prev == current -+ * is still correct, but it can be moved to another cpu/rq. -+ */ -+ cpu = smp_processor_id(); -+ rq = cpu_rq(cpu); -+ idle = rq->idle; -+ } else -+ grq_unlock_irq(); -+ -+rerun_prev_unlocked: -+ if (unlikely(reacquire_kernel_lock(prev))) -+ goto need_resched_nonpreemptible; -+ -+ preempt_enable_no_resched(); -+ if (need_resched()) -+ goto need_resched; -+} -+EXPORT_SYMBOL(schedule); -+ -+#ifdef CONFIG_SMP -+int mutex_spin_on_owner(struct mutex *lock, struct thread_info *owner) -+{ -+ unsigned int cpu; -+ struct rq *rq; -+ -+#ifdef CONFIG_DEBUG_PAGEALLOC -+ /* -+ * Need to access the cpu field knowing that -+ * DEBUG_PAGEALLOC could have unmapped it if -+ * the mutex owner just released it and exited. -+ */ -+ if (probe_kernel_address(&owner->cpu, cpu)) -+ return 0; -+#else -+ cpu = owner->cpu; -+#endif -+ -+ /* -+ * Even if the access succeeded (likely case), -+ * the cpu field may no longer be valid. -+ */ -+ if (cpu >= nr_cpumask_bits) -+ return 0; -+ -+ /* -+ * We need to validate that we can do a -+ * get_cpu() and that we have the percpu area. -+ */ -+ if (!cpu_online(cpu)) -+ return 0; -+ -+ rq = cpu_rq(cpu); -+ -+ for (;;) { -+ /* -+ * Owner changed, break to re-assess state. -+ */ -+ if (lock->owner != owner) -+ break; -+ -+ /* -+ * Is that owner really running on that cpu? -+ */ -+ if (task_thread_info(rq->curr) != owner || need_resched()) -+ return 0; -+ -+ cpu_relax(); -+ } -+ -+ return 1; -+} -+#endif -+ -+#ifdef CONFIG_PREEMPT -+/* -+ * this is the entry point to schedule() from in-kernel preemption -+ * off of preempt_enable. Kernel preemptions off return from interrupt -+ * occur there and call schedule directly. -+ */ -+asmlinkage void __sched notrace preempt_schedule(void) -+{ -+ struct thread_info *ti = current_thread_info(); -+ -+ /* -+ * If there is a non-zero preempt_count or interrupts are disabled, -+ * we do not want to preempt the current task. Just return.. -+ */ -+ if (likely(ti->preempt_count || irqs_disabled())) -+ return; -+ -+ do { -+ add_preempt_count_notrace(PREEMPT_ACTIVE); -+ schedule(); -+ sub_preempt_count_notrace(PREEMPT_ACTIVE); -+ -+ /* -+ * Check again in case we missed a preemption opportunity -+ * between schedule and now. -+ */ -+ barrier(); -+ } while (need_resched()); -+} -+EXPORT_SYMBOL(preempt_schedule); -+ -+/* -+ * this is the entry point to schedule() from kernel preemption -+ * off of irq context. -+ * Note, that this is called and return with irqs disabled. This will -+ * protect us against recursive calling from irq. -+ */ -+asmlinkage void __sched preempt_schedule_irq(void) -+{ -+ struct thread_info *ti = current_thread_info(); -+ -+ /* Catch callers which need to be fixed */ -+ BUG_ON(ti->preempt_count || !irqs_disabled()); -+ -+ do { -+ add_preempt_count(PREEMPT_ACTIVE); -+ local_irq_enable(); -+ schedule(); -+ local_irq_disable(); -+ sub_preempt_count(PREEMPT_ACTIVE); -+ -+ /* -+ * Check again in case we missed a preemption opportunity -+ * between schedule and now. -+ */ -+ barrier(); -+ } while (need_resched()); -+} -+ -+#endif /* CONFIG_PREEMPT */ -+ -+int default_wake_function(wait_queue_t *curr, unsigned mode, int wake_flags, -+ void *key) -+{ -+ return try_to_wake_up(curr->private, mode, wake_flags); -+} -+EXPORT_SYMBOL(default_wake_function); -+ -+/* -+ * The core wakeup function. Non-exclusive wakeups (nr_exclusive == 0) just -+ * wake everything up. If it's an exclusive wakeup (nr_exclusive == small +ve -+ * number) then we wake all the non-exclusive tasks and one exclusive task. -+ * -+ * There are circumstances in which we can try to wake a task which has already -+ * started to run but is not in state TASK_RUNNING. try_to_wake_up() returns -+ * zero in this (rare) case, and we handle it by continuing to scan the queue. -+ */ -+static void __wake_up_common(wait_queue_head_t *q, unsigned int mode, -+ int nr_exclusive, int wake_flags, void *key) -+{ -+ struct list_head *tmp, *next; -+ -+ list_for_each_safe(tmp, next, &q->task_list) { -+ wait_queue_t *curr = list_entry(tmp, wait_queue_t, task_list); -+ unsigned int flags = curr->flags; -+ -+ if (curr->func(curr, mode, wake_flags, key) && -+ (flags & WQ_FLAG_EXCLUSIVE) && !--nr_exclusive) -+ break; -+ } -+} -+ -+/** -+ * __wake_up - wake up threads blocked on a waitqueue. -+ * @q: the waitqueue -+ * @mode: which threads -+ * @nr_exclusive: how many wake-one or wake-many threads to wake up -+ * @key: is directly passed to the wakeup function -+ * -+ * It may be assumed that this function implies a write memory barrier before -+ * changing the task state if and only if any tasks are woken up. -+ */ -+void __wake_up(wait_queue_head_t *q, unsigned int mode, -+ int nr_exclusive, void *key) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&q->lock, flags); -+ __wake_up_common(q, mode, nr_exclusive, 0, key); -+ spin_unlock_irqrestore(&q->lock, flags); -+} -+EXPORT_SYMBOL(__wake_up); -+ -+/* -+ * Same as __wake_up but called with the spinlock in wait_queue_head_t held. -+ */ -+void __wake_up_locked(wait_queue_head_t *q, unsigned int mode) -+{ -+ __wake_up_common(q, mode, 1, 0, NULL); -+} -+EXPORT_SYMBOL_GPL(__wake_up_locked); -+ -+void __wake_up_locked_key(wait_queue_head_t *q, unsigned int mode, void *key) -+{ -+ __wake_up_common(q, mode, 1, 0, key); -+} -+ -+/** -+ * __wake_up_sync_key - wake up threads blocked on a waitqueue. -+ * @q: the waitqueue -+ * @mode: which threads -+ * @nr_exclusive: how many wake-one or wake-many threads to wake up -+ * @key: opaque value to be passed to wakeup targets -+ * -+ * The sync wakeup differs that the waker knows that it will schedule -+ * away soon, so while the target thread will be woken up, it will not -+ * be migrated to another CPU - ie. the two threads are 'synchronised' -+ * with each other. This can prevent needless bouncing between CPUs. -+ * -+ * On UP it can prevent extra preemption. -+ * -+ * It may be assumed that this function implies a write memory barrier before -+ * changing the task state if and only if any tasks are woken up. -+ */ -+void __wake_up_sync_key(wait_queue_head_t *q, unsigned int mode, -+ int nr_exclusive, void *key) -+{ -+ unsigned long flags; -+ int wake_flags = WF_SYNC; -+ -+ if (unlikely(!q)) -+ return; -+ -+ if (unlikely(!nr_exclusive)) -+ wake_flags = 0; -+ -+ spin_lock_irqsave(&q->lock, flags); -+ __wake_up_common(q, mode, nr_exclusive, wake_flags, key); -+ spin_unlock_irqrestore(&q->lock, flags); -+} -+EXPORT_SYMBOL_GPL(__wake_up_sync_key); -+ -+/** -+ * __wake_up_sync - wake up threads blocked on a waitqueue. -+ * @q: the waitqueue -+ * @mode: which threads -+ * @nr_exclusive: how many wake-one or wake-many threads to wake up -+ * -+ * The sync wakeup differs that the waker knows that it will schedule -+ * away soon, so while the target thread will be woken up, it will not -+ * be migrated to another CPU - ie. the two threads are 'synchronised' -+ * with each other. This can prevent needless bouncing between CPUs. -+ * -+ * On UP it can prevent extra preemption. -+ */ -+void __wake_up_sync(wait_queue_head_t *q, unsigned int mode, int nr_exclusive) -+{ -+ unsigned long flags; -+ int sync = 1; -+ -+ if (unlikely(!q)) -+ return; -+ -+ if (unlikely(!nr_exclusive)) -+ sync = 0; -+ -+ spin_lock_irqsave(&q->lock, flags); -+ __wake_up_common(q, mode, nr_exclusive, sync, NULL); -+ spin_unlock_irqrestore(&q->lock, flags); -+} -+EXPORT_SYMBOL_GPL(__wake_up_sync); /* For internal use only */ -+ -+/** -+ * complete: - signals a single thread waiting on this completion -+ * @x: holds the state of this particular completion -+ * -+ * This will wake up a single thread waiting on this completion. Threads will be -+ * awakened in the same order in which they were queued. -+ * -+ * See also complete_all(), wait_for_completion() and related routines. -+ * -+ * It may be assumed that this function implies a write memory barrier before -+ * changing the task state if and only if any tasks are woken up. -+ */ -+void complete(struct completion *x) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&x->wait.lock, flags); -+ x->done++; -+ __wake_up_common(&x->wait, TASK_NORMAL, 1, 0, NULL); -+ spin_unlock_irqrestore(&x->wait.lock, flags); -+} -+EXPORT_SYMBOL(complete); -+ -+/** -+ * complete_all: - signals all threads waiting on this completion -+ * @x: holds the state of this particular completion -+ * -+ * This will wake up all threads waiting on this particular completion event. -+ * -+ * It may be assumed that this function implies a write memory barrier before -+ * changing the task state if and only if any tasks are woken up. -+ */ -+void complete_all(struct completion *x) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&x->wait.lock, flags); -+ x->done += UINT_MAX/2; -+ __wake_up_common(&x->wait, TASK_NORMAL, 0, 0, NULL); -+ spin_unlock_irqrestore(&x->wait.lock, flags); -+} -+EXPORT_SYMBOL(complete_all); -+ -+static inline long __sched -+do_wait_for_common(struct completion *x, long timeout, int state) -+{ -+ if (!x->done) { -+ DECLARE_WAITQUEUE(wait, current); -+ -+ __add_wait_queue_tail_exclusive(&x->wait, &wait); -+ do { -+ if (signal_pending_state(state, current)) { -+ timeout = -ERESTARTSYS; -+ break; -+ } -+ __set_current_state(state); -+ spin_unlock_irq(&x->wait.lock); -+ timeout = schedule_timeout(timeout); -+ spin_lock_irq(&x->wait.lock); -+ } while (!x->done && timeout); -+ __remove_wait_queue(&x->wait, &wait); -+ if (!x->done) -+ return timeout; -+ } -+ x->done--; -+ return timeout ?: 1; -+} -+ -+static long __sched -+wait_for_common(struct completion *x, long timeout, int state) -+{ -+ might_sleep(); -+ -+ spin_lock_irq(&x->wait.lock); -+ timeout = do_wait_for_common(x, timeout, state); -+ spin_unlock_irq(&x->wait.lock); -+ return timeout; -+} -+ -+/** -+ * wait_for_completion: - waits for completion of a task -+ * @x: holds the state of this particular completion -+ * -+ * This waits to be signaled for completion of a specific task. It is NOT -+ * interruptible and there is no timeout. -+ * -+ * See also similar routines (i.e. wait_for_completion_timeout()) with timeout -+ * and interrupt capability. Also see complete(). -+ */ -+void __sched wait_for_completion(struct completion *x) -+{ -+ wait_for_common(x, MAX_SCHEDULE_TIMEOUT, TASK_UNINTERRUPTIBLE); -+} -+EXPORT_SYMBOL(wait_for_completion); -+ -+/** -+ * wait_for_completion_timeout: - waits for completion of a task (w/timeout) -+ * @x: holds the state of this particular completion -+ * @timeout: timeout value in jiffies -+ * -+ * This waits for either a completion of a specific task to be signaled or for a -+ * specified timeout to expire. The timeout is in jiffies. It is not -+ * interruptible. -+ */ -+unsigned long __sched -+wait_for_completion_timeout(struct completion *x, unsigned long timeout) -+{ -+ return wait_for_common(x, timeout, TASK_UNINTERRUPTIBLE); -+} -+EXPORT_SYMBOL(wait_for_completion_timeout); -+ -+/** -+ * wait_for_completion_interruptible: - waits for completion of a task (w/intr) -+ * @x: holds the state of this particular completion -+ * -+ * This waits for completion of a specific task to be signaled. It is -+ * interruptible. -+ */ -+int __sched wait_for_completion_interruptible(struct completion *x) -+{ -+ long t = wait_for_common(x, MAX_SCHEDULE_TIMEOUT, TASK_INTERRUPTIBLE); -+ if (t == -ERESTARTSYS) -+ return t; -+ return 0; -+} -+EXPORT_SYMBOL(wait_for_completion_interruptible); -+ -+/** -+ * wait_for_completion_interruptible_timeout: - waits for completion (w/(to,intr)) -+ * @x: holds the state of this particular completion -+ * @timeout: timeout value in jiffies -+ * -+ * This waits for either a completion of a specific task to be signaled or for a -+ * specified timeout to expire. It is interruptible. The timeout is in jiffies. -+ */ -+unsigned long __sched -+wait_for_completion_interruptible_timeout(struct completion *x, -+ unsigned long timeout) -+{ -+ return wait_for_common(x, timeout, TASK_INTERRUPTIBLE); -+} -+EXPORT_SYMBOL(wait_for_completion_interruptible_timeout); -+ -+/** -+ * wait_for_completion_killable: - waits for completion of a task (killable) -+ * @x: holds the state of this particular completion -+ * -+ * This waits to be signaled for completion of a specific task. It can be -+ * interrupted by a kill signal. -+ */ -+int __sched wait_for_completion_killable(struct completion *x) -+{ -+ long t = wait_for_common(x, MAX_SCHEDULE_TIMEOUT, TASK_KILLABLE); -+ if (t == -ERESTARTSYS) -+ return t; -+ return 0; -+} -+EXPORT_SYMBOL(wait_for_completion_killable); -+ -+/** -+ * wait_for_completion_killable_timeout: - waits for completion of a task (w/(to,killable)) -+ * @x: holds the state of this particular completion -+ * @timeout: timeout value in jiffies -+ * -+ * This waits for either a completion of a specific task to be -+ * signaled or for a specified timeout to expire. It can be -+ * interrupted by a kill signal. The timeout is in jiffies. -+ */ -+unsigned long __sched -+wait_for_completion_killable_timeout(struct completion *x, -+ unsigned long timeout) -+{ -+ return wait_for_common(x, timeout, TASK_KILLABLE); -+} -+EXPORT_SYMBOL(wait_for_completion_killable_timeout); -+ -+/** -+ * try_wait_for_completion - try to decrement a completion without blocking -+ * @x: completion structure -+ * -+ * Returns: 0 if a decrement cannot be done without blocking -+ * 1 if a decrement succeeded. -+ * -+ * If a completion is being used as a counting completion, -+ * attempt to decrement the counter without blocking. This -+ * enables us to avoid waiting if the resource the completion -+ * is protecting is not available. -+ */ -+bool try_wait_for_completion(struct completion *x) -+{ -+ unsigned long flags; -+ int ret = 1; -+ -+ spin_lock_irqsave(&x->wait.lock, flags); -+ if (!x->done) -+ ret = 0; -+ else -+ x->done--; -+ spin_unlock_irqrestore(&x->wait.lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL(try_wait_for_completion); -+ -+/** -+ * completion_done - Test to see if a completion has any waiters -+ * @x: completion structure -+ * -+ * Returns: 0 if there are waiters (wait_for_completion() in progress) -+ * 1 if there are no waiters. -+ * -+ */ -+bool completion_done(struct completion *x) -+{ -+ unsigned long flags; -+ int ret = 1; -+ -+ spin_lock_irqsave(&x->wait.lock, flags); -+ if (!x->done) -+ ret = 0; -+ spin_unlock_irqrestore(&x->wait.lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL(completion_done); -+ -+static long __sched -+sleep_on_common(wait_queue_head_t *q, int state, long timeout) -+{ -+ unsigned long flags; -+ wait_queue_t wait; -+ -+ init_waitqueue_entry(&wait, current); -+ -+ __set_current_state(state); -+ -+ spin_lock_irqsave(&q->lock, flags); -+ __add_wait_queue(q, &wait); -+ spin_unlock(&q->lock); -+ timeout = schedule_timeout(timeout); -+ spin_lock_irq(&q->lock); -+ __remove_wait_queue(q, &wait); -+ spin_unlock_irqrestore(&q->lock, flags); -+ -+ return timeout; -+} -+ -+void __sched interruptible_sleep_on(wait_queue_head_t *q) -+{ -+ sleep_on_common(q, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); -+} -+EXPORT_SYMBOL(interruptible_sleep_on); -+ -+long __sched -+interruptible_sleep_on_timeout(wait_queue_head_t *q, long timeout) -+{ -+ return sleep_on_common(q, TASK_INTERRUPTIBLE, timeout); -+} -+EXPORT_SYMBOL(interruptible_sleep_on_timeout); -+ -+void __sched sleep_on(wait_queue_head_t *q) -+{ -+ sleep_on_common(q, TASK_UNINTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); -+} -+EXPORT_SYMBOL(sleep_on); -+ -+long __sched sleep_on_timeout(wait_queue_head_t *q, long timeout) -+{ -+ return sleep_on_common(q, TASK_UNINTERRUPTIBLE, timeout); -+} -+EXPORT_SYMBOL(sleep_on_timeout); -+ -+#ifdef CONFIG_RT_MUTEXES -+ -+/* -+ * rt_mutex_setprio - set the current priority of a task -+ * @p: task -+ * @prio: prio value (kernel-internal form) -+ * -+ * This function changes the 'effective' priority of a task. It does -+ * not touch ->normal_prio like __setscheduler(). -+ * -+ * Used by the rt_mutex code to implement priority inheritance logic. -+ */ -+void rt_mutex_setprio(struct task_struct *p, int prio) -+{ -+ unsigned long flags; -+ int queued, oldprio; -+ struct rq *rq; -+ -+ BUG_ON(prio < 0 || prio > MAX_PRIO); -+ -+ rq = task_grq_lock(p, &flags); -+ -+ trace_sched_pi_setprio(p, prio); -+ oldprio = p->prio; -+ queued = task_queued(p); -+ if (queued) -+ dequeue_task(p); -+ p->prio = prio; -+ if (task_running(p) && prio > oldprio) -+ resched_task(p); -+ if (queued) { -+ enqueue_task(p); -+ try_preempt(p, rq); -+ } -+ -+ task_grq_unlock(&flags); -+} -+ -+#endif -+ -+/* -+ * Adjust the deadline for when the priority is to change, before it's -+ * changed. -+ */ -+static inline void adjust_deadline(struct task_struct *p, int new_prio) -+{ -+ p->deadline += static_deadline_diff(new_prio) - task_deadline_diff(p); -+} -+ -+void set_user_nice(struct task_struct *p, long nice) -+{ -+ int queued, new_static, old_static; -+ unsigned long flags; -+ struct rq *rq; -+ -+ if (TASK_NICE(p) == nice || nice < -20 || nice > 19) -+ return; -+ new_static = NICE_TO_PRIO(nice); -+ /* -+ * We have to be careful, if called from sys_setpriority(), -+ * the task might be in the middle of scheduling on another CPU. -+ */ -+ rq = time_task_grq_lock(p, &flags); -+ /* -+ * The RT priorities are set via sched_setscheduler(), but we still -+ * allow the 'normal' nice value to be set - but as expected -+ * it wont have any effect on scheduling until the task is -+ * not SCHED_NORMAL/SCHED_BATCH: -+ */ -+ if (has_rt_policy(p)) { -+ p->static_prio = new_static; -+ goto out_unlock; -+ } -+ queued = task_queued(p); -+ if (queued) -+ dequeue_task(p); -+ -+ adjust_deadline(p, new_static); -+ old_static = p->static_prio; -+ p->static_prio = new_static; -+ p->prio = effective_prio(p); -+ -+ if (queued) { -+ enqueue_task(p); -+ if (new_static < old_static) -+ try_preempt(p, rq); -+ } else if (task_running(p)) { -+ reset_rq_task(rq, p); -+ if (old_static < new_static) -+ resched_task(p); -+ } -+out_unlock: -+ task_grq_unlock(&flags); -+} -+EXPORT_SYMBOL(set_user_nice); -+ -+/* -+ * can_nice - check if a task can reduce its nice value -+ * @p: task -+ * @nice: nice value -+ */ -+int can_nice(const struct task_struct *p, const int nice) -+{ -+ /* convert nice value [19,-20] to rlimit style value [1,40] */ -+ int nice_rlim = 20 - nice; -+ -+ return (nice_rlim <= task_rlimit(p, RLIMIT_NICE) || -+ capable(CAP_SYS_NICE)); -+} -+ -+#ifdef __ARCH_WANT_SYS_NICE -+ -+/* -+ * sys_nice - change the priority of the current process. -+ * @increment: priority increment -+ * -+ * sys_setpriority is a more generic, but much slower function that -+ * does similar things. -+ */ -+SYSCALL_DEFINE1(nice, int, increment) -+{ -+ long nice, retval; -+ -+ /* -+ * Setpriority might change our priority at the same moment. -+ * We don't have to worry. Conceptually one call occurs first -+ * and we have a single winner. -+ */ -+ if (increment < -40) -+ increment = -40; -+ if (increment > 40) -+ increment = 40; -+ -+ nice = TASK_NICE(current) + increment; -+ if (nice < -20) -+ nice = -20; -+ if (nice > 19) -+ nice = 19; -+ -+ if (increment < 0 && !can_nice(current, nice)) -+ return -EPERM; -+ -+ retval = security_task_setnice(current, nice); -+ if (retval) -+ return retval; -+ -+ set_user_nice(current, nice); -+ return 0; -+} -+ -+#endif -+ -+/** -+ * task_prio - return the priority value of a given task. -+ * @p: the task in question. -+ * -+ * This is the priority value as seen by users in /proc. -+ * RT tasks are offset by -100. Normal tasks are centered around 1, value goes -+ * from 0 (SCHED_ISO) up to 82 (nice +19 SCHED_IDLEPRIO). -+ */ -+int task_prio(const struct task_struct *p) -+{ -+ int delta, prio = p->prio - MAX_RT_PRIO; -+ -+ /* rt tasks and iso tasks */ -+ if (prio <= 0) -+ goto out; -+ -+ /* Convert to ms to avoid overflows */ -+ delta = NS_TO_MS(p->deadline - grq.niffies); -+ delta = delta * 40 / ms_longest_deadline_diff(); -+ if (delta > 0 && delta <= 80) -+ prio += delta; -+ if (idleprio_task(p)) -+ prio += 40; -+out: -+ return prio; -+} -+ -+/** -+ * task_nice - return the nice value of a given task. -+ * @p: the task in question. -+ */ -+int task_nice(const struct task_struct *p) -+{ -+ return TASK_NICE(p); -+} -+EXPORT_SYMBOL_GPL(task_nice); -+ -+/** -+ * idle_cpu - is a given cpu idle currently? -+ * @cpu: the processor in question. -+ */ -+int idle_cpu(int cpu) -+{ -+ return cpu_curr(cpu) == cpu_rq(cpu)->idle; -+} -+ -+/** -+ * idle_task - return the idle task for a given cpu. -+ * @cpu: the processor in question. -+ */ -+struct task_struct *idle_task(int cpu) -+{ -+ return cpu_rq(cpu)->idle; -+} -+ -+/** -+ * find_process_by_pid - find a process with a matching PID value. -+ * @pid: the pid in question. -+ */ -+static inline struct task_struct *find_process_by_pid(pid_t pid) -+{ -+ return pid ? find_task_by_vpid(pid) : current; -+} -+ -+/* Actually do priority change: must hold grq lock. */ -+static void -+__setscheduler(struct task_struct *p, struct rq *rq, int policy, int prio) -+{ -+ int oldrtprio, oldprio; -+ -+ BUG_ON(task_queued(p)); -+ -+ p->policy = policy; -+ oldrtprio = p->rt_priority; -+ p->rt_priority = prio; -+ p->normal_prio = normal_prio(p); -+ oldprio = p->prio; -+ /* we are holding p->pi_lock already */ -+ p->prio = rt_mutex_getprio(p); -+ if (task_running(p)) { -+ reset_rq_task(rq, p); -+ /* Resched only if we might now be preempted */ -+ if (p->prio > oldprio || p->rt_priority > oldrtprio) -+ resched_task(p); -+ } -+} -+ -+/* -+ * check the target process has a UID that matches the current process's -+ */ -+static bool check_same_owner(struct task_struct *p) -+{ -+ const struct cred *cred = current_cred(), *pcred; -+ bool match; -+ -+ rcu_read_lock(); -+ pcred = __task_cred(p); -+ match = (cred->euid == pcred->euid || -+ cred->euid == pcred->uid); -+ rcu_read_unlock(); -+ return match; -+} -+ -+static int __sched_setscheduler(struct task_struct *p, int policy, -+ struct sched_param *param, bool user) -+{ -+ struct sched_param zero_param = { .sched_priority = 0 }; -+ int queued, retval, oldpolicy = -1; -+ unsigned long flags, rlim_rtprio = 0; -+ int reset_on_fork; -+ struct rq *rq; -+ -+ /* may grab non-irq protected spin_locks */ -+ BUG_ON(in_interrupt()); -+ -+ if (is_rt_policy(policy) && !capable(CAP_SYS_NICE)) { -+ unsigned long lflags; -+ -+ if (!lock_task_sighand(p, &lflags)) -+ return -ESRCH; -+ rlim_rtprio = task_rlimit(p, RLIMIT_RTPRIO); -+ unlock_task_sighand(p, &lflags); -+ if (rlim_rtprio) -+ goto recheck; -+ /* -+ * If the caller requested an RT policy without having the -+ * necessary rights, we downgrade the policy to SCHED_ISO. -+ * We also set the parameter to zero to pass the checks. -+ */ -+ policy = SCHED_ISO; -+ param = &zero_param; -+ } -+recheck: -+ /* double check policy once rq lock held */ -+ if (policy < 0) { -+ reset_on_fork = p->sched_reset_on_fork; -+ policy = oldpolicy = p->policy; -+ } else { -+ reset_on_fork = !!(policy & SCHED_RESET_ON_FORK); -+ policy &= ~SCHED_RESET_ON_FORK; -+ -+ if (!SCHED_RANGE(policy)) -+ return -EINVAL; -+ } -+ -+ /* -+ * Valid priorities for SCHED_FIFO and SCHED_RR are -+ * 1..MAX_USER_RT_PRIO-1, valid priority for SCHED_NORMAL and -+ * SCHED_BATCH is 0. -+ */ -+ if (param->sched_priority < 0 || -+ (p->mm && param->sched_priority > MAX_USER_RT_PRIO - 1) || -+ (!p->mm && param->sched_priority > MAX_RT_PRIO - 1)) -+ return -EINVAL; -+ if (is_rt_policy(policy) != (param->sched_priority != 0)) -+ return -EINVAL; -+ -+ /* -+ * Allow unprivileged RT tasks to decrease priority: -+ */ -+ if (user && !capable(CAP_SYS_NICE)) { -+ if (is_rt_policy(policy)) { -+ unsigned long rlim_rtprio = -+ task_rlimit(p, RLIMIT_RTPRIO); -+ -+ /* can't set/change the rt policy */ -+ if (policy != p->policy && !rlim_rtprio) -+ return -EPERM; -+ -+ /* can't increase priority */ -+ if (param->sched_priority > p->rt_priority && -+ param->sched_priority > rlim_rtprio) -+ return -EPERM; -+ } else { -+ switch (p->policy) { -+ /* -+ * Can only downgrade policies but not back to -+ * SCHED_NORMAL -+ */ -+ case SCHED_ISO: -+ if (policy == SCHED_ISO) -+ goto out; -+ if (policy == SCHED_NORMAL) -+ return -EPERM; -+ break; -+ case SCHED_BATCH: -+ if (policy == SCHED_BATCH) -+ goto out; -+ if (policy != SCHED_IDLEPRIO) -+ return -EPERM; -+ break; -+ case SCHED_IDLEPRIO: -+ if (policy == SCHED_IDLEPRIO) -+ goto out; -+ return -EPERM; -+ default: -+ break; -+ } -+ } -+ -+ /* can't change other user's priorities */ -+ if (!check_same_owner(p)) -+ return -EPERM; -+ -+ /* Normal users shall not reset the sched_reset_on_fork flag */ -+ if (p->sched_reset_on_fork && !reset_on_fork) -+ return -EPERM; -+ } -+ -+ if (user) { -+ retval = security_task_setscheduler(p); -+ if (retval) -+ return retval; -+ } -+ -+ /* -+ * make sure no PI-waiters arrive (or leave) while we are -+ * changing the priority of the task: -+ */ -+ raw_spin_lock_irqsave(&p->pi_lock, flags); -+ /* -+ * To be able to change p->policy safely, the apropriate -+ * runqueue lock must be held. -+ */ -+ rq = __task_grq_lock(p); -+ -+ /* -+ * Changing the policy of the stop threads its a very bad idea -+ */ -+ if (p == rq->stop) { -+ __task_grq_unlock(); -+ raw_spin_unlock_irqrestore(&p->pi_lock, flags); -+ return -EINVAL; -+ } -+ -+ /* recheck policy now with rq lock held */ -+ if (unlikely(oldpolicy != -1 && oldpolicy != p->policy)) { -+ policy = oldpolicy = -1; -+ __task_grq_unlock(); -+ raw_spin_unlock_irqrestore(&p->pi_lock, flags); -+ goto recheck; -+ } -+ update_clocks(rq); -+ p->sched_reset_on_fork = reset_on_fork; -+ -+ queued = task_queued(p); -+ if (queued) -+ dequeue_task(p); -+ __setscheduler(p, rq, policy, param->sched_priority); -+ if (queued) { -+ enqueue_task(p); -+ try_preempt(p, rq); -+ } -+ __task_grq_unlock(); -+ raw_spin_unlock_irqrestore(&p->pi_lock, flags); -+ -+ rt_mutex_adjust_pi(p); -+out: -+ return 0; -+} -+ -+/** -+ * sched_setscheduler - change the scheduling policy and/or RT priority of a thread. -+ * @p: the task in question. -+ * @policy: new policy. -+ * @param: structure containing the new RT priority. -+ * -+ * NOTE that the task may be already dead. -+ */ -+int sched_setscheduler(struct task_struct *p, int policy, -+ struct sched_param *param) -+{ -+ return __sched_setscheduler(p, policy, param, true); -+} -+ -+EXPORT_SYMBOL_GPL(sched_setscheduler); -+ -+/** -+ * sched_setscheduler_nocheck - change the scheduling policy and/or RT priority of a thread from kernelspace. -+ * @p: the task in question. -+ * @policy: new policy. -+ * @param: structure containing the new RT priority. -+ * -+ * Just like sched_setscheduler, only don't bother checking if the -+ * current context has permission. For example, this is needed in -+ * stop_machine(): we create temporary high priority worker threads, -+ * but our caller might not have that capability. -+ */ -+int sched_setscheduler_nocheck(struct task_struct *p, int policy, -+ struct sched_param *param) -+{ -+ return __sched_setscheduler(p, policy, param, false); -+} -+ -+static int -+do_sched_setscheduler(pid_t pid, int policy, struct sched_param __user *param) -+{ -+ struct sched_param lparam; -+ struct task_struct *p; -+ int retval; -+ -+ if (!param || pid < 0) -+ return -EINVAL; -+ if (copy_from_user(&lparam, param, sizeof(struct sched_param))) -+ return -EFAULT; -+ -+ rcu_read_lock(); -+ retval = -ESRCH; -+ p = find_process_by_pid(pid); -+ if (p != NULL) -+ retval = sched_setscheduler(p, policy, &lparam); -+ rcu_read_unlock(); -+ -+ return retval; -+} -+ -+/** -+ * sys_sched_setscheduler - set/change the scheduler policy and RT priority -+ * @pid: the pid in question. -+ * @policy: new policy. -+ * @param: structure containing the new RT priority. -+ */ -+asmlinkage long sys_sched_setscheduler(pid_t pid, int policy, -+ struct sched_param __user *param) -+{ -+ /* negative values for policy are not valid */ -+ if (policy < 0) -+ return -EINVAL; -+ -+ return do_sched_setscheduler(pid, policy, param); -+} -+ -+/** -+ * sys_sched_setparam - set/change the RT priority of a thread -+ * @pid: the pid in question. -+ * @param: structure containing the new RT priority. -+ */ -+SYSCALL_DEFINE2(sched_setparam, pid_t, pid, struct sched_param __user *, param) -+{ -+ return do_sched_setscheduler(pid, -1, param); -+} -+ -+/** -+ * sys_sched_getscheduler - get the policy (scheduling class) of a thread -+ * @pid: the pid in question. -+ */ -+SYSCALL_DEFINE1(sched_getscheduler, pid_t, pid) -+{ -+ struct task_struct *p; -+ int retval = -EINVAL; -+ -+ if (pid < 0) -+ goto out_nounlock; -+ -+ retval = -ESRCH; -+ rcu_read_lock(); -+ p = find_process_by_pid(pid); -+ if (p) { -+ retval = security_task_getscheduler(p); -+ if (!retval) -+ retval = p->policy; -+ } -+ rcu_read_unlock(); -+ -+out_nounlock: -+ return retval; -+} -+ -+/** -+ * sys_sched_getscheduler - get the RT priority of a thread -+ * @pid: the pid in question. -+ * @param: structure containing the RT priority. -+ */ -+SYSCALL_DEFINE2(sched_getparam, pid_t, pid, struct sched_param __user *, param) -+{ -+ struct sched_param lp; -+ struct task_struct *p; -+ int retval = -EINVAL; -+ -+ if (!param || pid < 0) -+ goto out_nounlock; -+ -+ rcu_read_lock(); -+ p = find_process_by_pid(pid); -+ retval = -ESRCH; -+ if (!p) -+ goto out_unlock; -+ -+ retval = security_task_getscheduler(p); -+ if (retval) -+ goto out_unlock; -+ -+ lp.sched_priority = p->rt_priority; -+ rcu_read_unlock(); -+ -+ /* -+ * This one might sleep, we cannot do it with a spinlock held ... -+ */ -+ retval = copy_to_user(param, &lp, sizeof(*param)) ? -EFAULT : 0; -+ -+out_nounlock: -+ return retval; -+ -+out_unlock: -+ rcu_read_unlock(); -+ return retval; -+} -+ -+long sched_setaffinity(pid_t pid, const struct cpumask *in_mask) -+{ -+ cpumask_var_t cpus_allowed, new_mask; -+ struct task_struct *p; -+ int retval; -+ -+ get_online_cpus(); -+ rcu_read_lock(); -+ -+ p = find_process_by_pid(pid); -+ if (!p) { -+ rcu_read_unlock(); -+ put_online_cpus(); -+ return -ESRCH; -+ } -+ -+ /* Prevent p going away */ -+ get_task_struct(p); -+ rcu_read_unlock(); -+ -+ if (!alloc_cpumask_var(&cpus_allowed, GFP_KERNEL)) { -+ retval = -ENOMEM; -+ goto out_put_task; -+ } -+ if (!alloc_cpumask_var(&new_mask, GFP_KERNEL)) { -+ retval = -ENOMEM; -+ goto out_free_cpus_allowed; -+ } -+ retval = -EPERM; -+ if (!check_same_owner(p) && !capable(CAP_SYS_NICE)) -+ goto out_unlock; -+ -+ retval = security_task_setscheduler(p); -+ if (retval) -+ goto out_unlock; -+ -+ cpuset_cpus_allowed(p, cpus_allowed); -+ cpumask_and(new_mask, in_mask, cpus_allowed); -+again: -+ retval = set_cpus_allowed_ptr(p, new_mask); -+ -+ if (!retval) { -+ cpuset_cpus_allowed(p, cpus_allowed); -+ if (!cpumask_subset(new_mask, cpus_allowed)) { -+ /* -+ * We must have raced with a concurrent cpuset -+ * update. Just reset the cpus_allowed to the -+ * cpuset's cpus_allowed -+ */ -+ cpumask_copy(new_mask, cpus_allowed); -+ goto again; -+ } -+ } -+out_unlock: -+ free_cpumask_var(new_mask); -+out_free_cpus_allowed: -+ free_cpumask_var(cpus_allowed); -+out_put_task: -+ put_task_struct(p); -+ put_online_cpus(); -+ return retval; -+} -+ -+static int get_user_cpu_mask(unsigned long __user *user_mask_ptr, unsigned len, -+ cpumask_t *new_mask) -+{ -+ if (len < sizeof(cpumask_t)) { -+ memset(new_mask, 0, sizeof(cpumask_t)); -+ } else if (len > sizeof(cpumask_t)) { -+ len = sizeof(cpumask_t); -+ } -+ return copy_from_user(new_mask, user_mask_ptr, len) ? -EFAULT : 0; -+} -+ -+ -+/** -+ * sys_sched_setaffinity - set the cpu affinity of a process -+ * @pid: pid of the process -+ * @len: length in bytes of the bitmask pointed to by user_mask_ptr -+ * @user_mask_ptr: user-space pointer to the new cpu mask -+ */ -+SYSCALL_DEFINE3(sched_setaffinity, pid_t, pid, unsigned int, len, -+ unsigned long __user *, user_mask_ptr) -+{ -+ cpumask_var_t new_mask; -+ int retval; -+ -+ if (!alloc_cpumask_var(&new_mask, GFP_KERNEL)) -+ return -ENOMEM; -+ -+ retval = get_user_cpu_mask(user_mask_ptr, len, new_mask); -+ if (retval == 0) -+ retval = sched_setaffinity(pid, new_mask); -+ free_cpumask_var(new_mask); -+ return retval; -+} -+ -+long sched_getaffinity(pid_t pid, cpumask_t *mask) -+{ -+ struct task_struct *p; -+ unsigned long flags; -+ struct rq *rq; -+ int retval; -+ -+ get_online_cpus(); -+ rcu_read_lock(); -+ -+ retval = -ESRCH; -+ p = find_process_by_pid(pid); -+ if (!p) -+ goto out_unlock; -+ -+ retval = security_task_getscheduler(p); -+ if (retval) -+ goto out_unlock; -+ -+ rq = task_grq_lock(p, &flags); -+ cpumask_and(mask, &p->cpus_allowed, cpu_online_mask); -+ task_grq_unlock(&flags); -+ -+out_unlock: -+ rcu_read_unlock(); -+ put_online_cpus(); -+ -+ return retval; -+} -+ -+/** -+ * sys_sched_getaffinity - get the cpu affinity of a process -+ * @pid: pid of the process -+ * @len: length in bytes of the bitmask pointed to by user_mask_ptr -+ * @user_mask_ptr: user-space pointer to hold the current cpu mask -+ */ -+SYSCALL_DEFINE3(sched_getaffinity, pid_t, pid, unsigned int, len, -+ unsigned long __user *, user_mask_ptr) -+{ -+ int ret; -+ cpumask_var_t mask; -+ -+ if ((len * BITS_PER_BYTE) < nr_cpu_ids) -+ return -EINVAL; -+ if (len & (sizeof(unsigned long)-1)) -+ return -EINVAL; -+ -+ if (!alloc_cpumask_var(&mask, GFP_KERNEL)) -+ return -ENOMEM; -+ -+ ret = sched_getaffinity(pid, mask); -+ if (ret == 0) { -+ size_t retlen = min_t(size_t, len, cpumask_size()); -+ -+ if (copy_to_user(user_mask_ptr, mask, retlen)) -+ ret = -EFAULT; -+ else -+ ret = retlen; -+ } -+ free_cpumask_var(mask); -+ -+ return ret; -+} -+ -+/** -+ * sys_sched_yield - yield the current processor to other threads. -+ * -+ * This function yields the current CPU to other tasks. It does this by -+ * scheduling away the current task. If it still has the earliest deadline -+ * it will be scheduled again as the next task. -+ */ -+SYSCALL_DEFINE0(sched_yield) -+{ -+ struct task_struct *p; -+ struct rq *rq; -+ -+ p = current; -+ rq = task_grq_lock_irq(p); -+ schedstat_inc(rq, yld_count); -+ requeue_task(p); -+ -+ /* -+ * Since we are going to call schedule() anyway, there's -+ * no need to preempt or enable interrupts: -+ */ -+ __release(grq.lock); -+ spin_release(&grq.lock.dep_map, 1, _THIS_IP_); -+ do_raw_spin_unlock(&grq.lock); -+ preempt_enable_no_resched(); -+ -+ schedule(); -+ -+ return 0; -+} -+ -+static inline int should_resched(void) -+{ -+ return need_resched() && !(preempt_count() & PREEMPT_ACTIVE); -+} -+ -+static void __cond_resched(void) -+{ -+ /* NOT a real fix but will make voluntary preempt work. 馬鹿ãªäº‹ */ -+ if (unlikely(system_state != SYSTEM_RUNNING)) -+ return; -+ -+ add_preempt_count(PREEMPT_ACTIVE); -+ schedule(); -+ sub_preempt_count(PREEMPT_ACTIVE); -+} -+ -+int __sched _cond_resched(void) -+{ -+ if (should_resched()) { -+ __cond_resched(); -+ return 1; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(_cond_resched); -+ -+/* -+ * __cond_resched_lock() - if a reschedule is pending, drop the given lock, -+ * call schedule, and on return reacquire the lock. -+ * -+ * This works OK both with and without CONFIG_PREEMPT. We do strange low-level -+ * operations here to prevent schedule() from being called twice (once via -+ * spin_unlock(), once by hand). -+ */ -+int __cond_resched_lock(spinlock_t *lock) -+{ -+ int resched = should_resched(); -+ int ret = 0; -+ -+ lockdep_assert_held(lock); -+ -+ if (spin_needbreak(lock) || resched) { -+ spin_unlock(lock); -+ if (resched) -+ __cond_resched(); -+ else -+ cpu_relax(); -+ ret = 1; -+ spin_lock(lock); -+ } -+ return ret; -+} -+EXPORT_SYMBOL(__cond_resched_lock); -+ -+int __sched __cond_resched_softirq(void) -+{ -+ BUG_ON(!in_softirq()); -+ -+ if (should_resched()) { -+ local_bh_enable(); -+ __cond_resched(); -+ local_bh_disable(); -+ return 1; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(__cond_resched_softirq); -+ -+/** -+ * yield - yield the current processor to other threads. -+ * -+ * This is a shortcut for kernel-space yielding - it marks the -+ * thread runnable and calls sys_sched_yield(). -+ */ -+void __sched yield(void) -+{ -+ set_current_state(TASK_RUNNING); -+ sys_sched_yield(); -+} -+EXPORT_SYMBOL(yield); -+ -+/* -+ * This task is about to go to sleep on IO. Increment rq->nr_iowait so -+ * that process accounting knows that this is a task in IO wait state. -+ * -+ * But don't do that if it is a deliberate, throttling IO wait (this task -+ * has set its backing_dev_info: the queue against which it should throttle) -+ */ -+void __sched io_schedule(void) -+{ -+ struct rq *rq = raw_rq(); -+ -+ delayacct_blkio_start(); -+ atomic_inc(&rq->nr_iowait); -+ current->in_iowait = 1; -+ schedule(); -+ current->in_iowait = 0; -+ atomic_dec(&rq->nr_iowait); -+ delayacct_blkio_end(); -+} -+EXPORT_SYMBOL(io_schedule); -+ -+long __sched io_schedule_timeout(long timeout) -+{ -+ struct rq *rq = raw_rq(); -+ long ret; -+ -+ delayacct_blkio_start(); -+ atomic_inc(&rq->nr_iowait); -+ current->in_iowait = 1; -+ ret = schedule_timeout(timeout); -+ current->in_iowait = 0; -+ atomic_dec(&rq->nr_iowait); -+ delayacct_blkio_end(); -+ return ret; -+} -+ -+/** -+ * sys_sched_get_priority_max - return maximum RT priority. -+ * @policy: scheduling class. -+ * -+ * this syscall returns the maximum rt_priority that can be used -+ * by a given scheduling class. -+ */ -+SYSCALL_DEFINE1(sched_get_priority_max, int, policy) -+{ -+ int ret = -EINVAL; -+ -+ switch (policy) { -+ case SCHED_FIFO: -+ case SCHED_RR: -+ ret = MAX_USER_RT_PRIO-1; -+ break; -+ case SCHED_NORMAL: -+ case SCHED_BATCH: -+ case SCHED_ISO: -+ case SCHED_IDLEPRIO: -+ ret = 0; -+ break; -+ } -+ return ret; -+} -+ -+/** -+ * sys_sched_get_priority_min - return minimum RT priority. -+ * @policy: scheduling class. -+ * -+ * this syscall returns the minimum rt_priority that can be used -+ * by a given scheduling class. -+ */ -+SYSCALL_DEFINE1(sched_get_priority_min, int, policy) -+{ -+ int ret = -EINVAL; -+ -+ switch (policy) { -+ case SCHED_FIFO: -+ case SCHED_RR: -+ ret = 1; -+ break; -+ case SCHED_NORMAL: -+ case SCHED_BATCH: -+ case SCHED_ISO: -+ case SCHED_IDLEPRIO: -+ ret = 0; -+ break; -+ } -+ return ret; -+} -+ -+/** -+ * sys_sched_rr_get_interval - return the default timeslice of a process. -+ * @pid: pid of the process. -+ * @interval: userspace pointer to the timeslice value. -+ * -+ * this syscall writes the default timeslice value of a given process -+ * into the user-space timespec buffer. A value of '0' means infinity. -+ */ -+SYSCALL_DEFINE2(sched_rr_get_interval, pid_t, pid, -+ struct timespec __user *, interval) -+{ -+ struct task_struct *p; -+ unsigned int time_slice; -+ unsigned long flags; -+ struct rq *rq; -+ int retval; -+ struct timespec t; -+ -+ if (pid < 0) -+ return -EINVAL; -+ -+ retval = -ESRCH; -+ rcu_read_lock(); -+ p = find_process_by_pid(pid); -+ if (!p) -+ goto out_unlock; -+ -+ retval = security_task_getscheduler(p); -+ if (retval) -+ goto out_unlock; -+ -+ rq = task_grq_lock(p, &flags); -+ time_slice = p->policy == SCHED_FIFO ? 0 : MS_TO_NS(task_timeslice(p)); -+ task_grq_unlock(&flags); -+ -+ rcu_read_unlock(); -+ t = ns_to_timespec(time_slice); -+ retval = copy_to_user(interval, &t, sizeof(t)) ? -EFAULT : 0; -+ return retval; -+ -+out_unlock: -+ rcu_read_unlock(); -+ return retval; -+} -+ -+static const char stat_nam[] = TASK_STATE_TO_CHAR_STR; -+ -+void sched_show_task(struct task_struct *p) -+{ -+ unsigned long free = 0; -+ unsigned state; -+ -+ state = p->state ? __ffs(p->state) + 1 : 0; -+ printk(KERN_INFO "%-13.13s %c", p->comm, -+ state < sizeof(stat_nam) - 1 ? stat_nam[state] : '?'); -+#if BITS_PER_LONG == 32 -+ if (state == TASK_RUNNING) -+ printk(KERN_CONT " running "); -+ else -+ printk(KERN_CONT " %08lx ", thread_saved_pc(p)); -+#else -+ if (state == TASK_RUNNING) -+ printk(KERN_CONT " running task "); -+ else -+ printk(KERN_CONT " %016lx ", thread_saved_pc(p)); -+#endif -+#ifdef CONFIG_DEBUG_STACK_USAGE -+ free = stack_not_used(p); -+#endif -+ printk(KERN_CONT "%5lu %5d %6d 0x%08lx\n", free, -+ task_pid_nr(p), task_pid_nr(p->real_parent), -+ (unsigned long)task_thread_info(p)->flags); -+ -+ show_stack(p, NULL); -+} -+ -+void show_state_filter(unsigned long state_filter) -+{ -+ struct task_struct *g, *p; -+ -+#if BITS_PER_LONG == 32 -+ printk(KERN_INFO -+ " task PC stack pid father\n"); -+#else -+ printk(KERN_INFO -+ " task PC stack pid father\n"); -+#endif -+ read_lock(&tasklist_lock); -+ do_each_thread(g, p) { -+ /* -+ * reset the NMI-timeout, listing all files on a slow -+ * console might take alot of time: -+ */ -+ touch_nmi_watchdog(); -+ if (!state_filter || (p->state & state_filter)) -+ sched_show_task(p); -+ } while_each_thread(g, p); -+ -+ touch_all_softlockup_watchdogs(); -+ -+ read_unlock(&tasklist_lock); -+ /* -+ * Only show locks if all tasks are dumped: -+ */ -+ if (!state_filter) -+ debug_show_all_locks(); -+} -+ -+/** -+ * init_idle - set up an idle thread for a given CPU -+ * @idle: task in question -+ * @cpu: cpu the idle task belongs to -+ * -+ * NOTE: this function does not set the idle thread's NEED_RESCHED -+ * flag, to make booting more robust. -+ */ -+void init_idle(struct task_struct *idle, int cpu) -+{ -+ struct rq *rq = cpu_rq(cpu); -+ unsigned long flags; -+ -+ time_grq_lock(rq, &flags); -+ idle->last_ran = rq->clock; -+ idle->state = TASK_RUNNING; -+ /* Setting prio to illegal value shouldn't matter when never queued */ -+ idle->prio = PRIO_LIMIT; -+ set_rq_task(rq, idle); -+ idle->cpus_allowed = cpumask_of_cpu(cpu); -+ /* Silence PROVE_RCU */ -+ rcu_read_lock(); -+ set_task_cpu(idle, cpu); -+ rcu_read_unlock(); -+ rq->curr = rq->idle = idle; -+ idle->oncpu = 1; -+ set_cpuidle_map(cpu); -+ grq_unlock_irqrestore(&flags); -+ -+ /* Set the preempt count _outside_ the spinlocks! */ -+#if defined(CONFIG_PREEMPT) && !defined(CONFIG_PREEMPT_BKL) -+ task_thread_info(idle)->preempt_count = (idle->lock_depth >= 0); -+#else -+ task_thread_info(idle)->preempt_count = 0; -+#endif -+ ftrace_graph_init_task(idle); -+} -+ -+/* -+ * In a system that switches off the HZ timer nohz_cpu_mask -+ * indicates which cpus entered this state. This is used -+ * in the rcu update to wait only for active cpus. For system -+ * which do not switch off the HZ timer nohz_cpu_mask should -+ * always be CPU_BITS_NONE. -+ */ -+cpumask_var_t nohz_cpu_mask; -+ -+#ifdef CONFIG_SMP -+#ifdef CONFIG_NO_HZ -+void select_nohz_load_balancer(int stop_tick) -+{ -+} -+#if defined(CONFIG_SCHED_MC) || defined(CONFIG_SCHED_SMT) -+/** -+ * lowest_flag_domain - Return lowest sched_domain containing flag. -+ * @cpu: The cpu whose lowest level of sched domain is to -+ * be returned. -+ * @flag: The flag to check for the lowest sched_domain -+ * for the given cpu. -+ * -+ * Returns the lowest sched_domain of a cpu which contains the given flag. -+ */ -+static inline struct sched_domain *lowest_flag_domain(int cpu, int flag) -+{ -+ struct sched_domain *sd; -+ -+ for_each_domain(cpu, sd) -+ if (sd && (sd->flags & flag)) -+ break; -+ -+ return sd; -+} -+ -+/** -+ * for_each_flag_domain - Iterates over sched_domains containing the flag. -+ * @cpu: The cpu whose domains we're iterating over. -+ * @sd: variable holding the value of the power_savings_sd -+ * for cpu. -+ * @flag: The flag to filter the sched_domains to be iterated. -+ * -+ * Iterates over all the scheduler domains for a given cpu that has the 'flag' -+ * set, starting from the lowest sched_domain to the highest. -+ */ -+#define for_each_flag_domain(cpu, sd, flag) \ -+ for (sd = lowest_flag_domain(cpu, flag); \ -+ (sd && (sd->flags & flag)); sd = sd->parent) -+ -+#endif /* (CONFIG_SCHED_MC || CONFIG_SCHED_SMT) */ -+ -+static inline void resched_cpu(int cpu) -+{ -+ unsigned long flags; -+ -+ grq_lock_irqsave(&flags); -+ resched_task(cpu_curr(cpu)); -+ grq_unlock_irqrestore(&flags); -+} -+ -+/* -+ * In the semi idle case, use the nearest busy cpu for migrating timers -+ * from an idle cpu. This is good for power-savings. -+ * -+ * We don't do similar optimization for completely idle system, as -+ * selecting an idle cpu will add more delays to the timers than intended -+ * (as that cpu's timer base may not be uptodate wrt jiffies etc). -+ */ -+int get_nohz_timer_target(void) -+{ -+ int cpu = smp_processor_id(); -+ int i; -+ struct sched_domain *sd; -+ -+ for_each_domain(cpu, sd) { -+ for_each_cpu(i, sched_domain_span(sd)) -+ if (!idle_cpu(i)) -+ return i; -+ } -+ return cpu; -+} -+ -+/* -+ * When add_timer_on() enqueues a timer into the timer wheel of an -+ * idle CPU then this timer might expire before the next timer event -+ * which is scheduled to wake up that CPU. In case of a completely -+ * idle system the next event might even be infinite time into the -+ * future. wake_up_idle_cpu() ensures that the CPU is woken up and -+ * leaves the inner idle loop so the newly added timer is taken into -+ * account when the CPU goes back to idle and evaluates the timer -+ * wheel for the next timer event. -+ */ -+void wake_up_idle_cpu(int cpu) -+{ -+ struct task_struct *idle; -+ struct rq *rq; -+ -+ if (cpu == smp_processor_id()) -+ return; -+ -+ rq = cpu_rq(cpu); -+ idle = rq->idle; -+ -+ /* -+ * This is safe, as this function is called with the timer -+ * wheel base lock of (cpu) held. When the CPU is on the way -+ * to idle and has not yet set rq->curr to idle then it will -+ * be serialised on the timer wheel base lock and take the new -+ * timer into account automatically. -+ */ -+ if (unlikely(rq->curr != idle)) -+ return; -+ -+ /* -+ * We can set TIF_RESCHED on the idle task of the other CPU -+ * lockless. The worst case is that the other CPU runs the -+ * idle task through an additional NOOP schedule() -+ */ -+ set_tsk_need_resched(idle); -+ -+ /* NEED_RESCHED must be visible before we test polling */ -+ smp_mb(); -+ if (!tsk_is_polling(idle)) -+ smp_send_reschedule(cpu); -+} -+ -+#endif /* CONFIG_NO_HZ */ -+ -+/* -+ * Change a given task's CPU affinity. Migrate the thread to a -+ * proper CPU and schedule it away if the CPU it's executing on -+ * is removed from the allowed bitmask. -+ * -+ * NOTE: the caller must have a valid reference to the task, the -+ * task must not exit() & deallocate itself prematurely. The -+ * call is not atomic; no spinlocks may be held. -+ */ -+int set_cpus_allowed_ptr(struct task_struct *p, const struct cpumask *new_mask) -+{ -+ unsigned long flags; -+ int running_wrong = 0; -+ int queued = 0; -+ struct rq *rq; -+ int ret = 0; -+ -+ rq = task_grq_lock(p, &flags); -+ -+ if (!cpumask_intersects(new_mask, cpu_active_mask)) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ if (unlikely((p->flags & PF_THREAD_BOUND) && p != current && -+ !cpumask_equal(&p->cpus_allowed, new_mask))) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ queued = task_queued(p); -+ -+ cpumask_copy(&p->cpus_allowed, new_mask); -+ -+ /* Can the task run on the task's current CPU? If so, we're done */ -+ if (cpumask_test_cpu(task_cpu(p), new_mask)) -+ goto out; -+ -+ if (task_running(p)) { -+ /* Task is running on the wrong cpu now, reschedule it. */ -+ if (rq == this_rq()) { -+ set_tsk_need_resched(p); -+ running_wrong = 1; -+ } else -+ resched_task(p); -+ } else -+ set_task_cpu(p, cpumask_any_and(cpu_active_mask, new_mask)); -+ -+out: -+ if (queued) -+ try_preempt(p, rq); -+ task_grq_unlock(&flags); -+ -+ if (running_wrong) -+ _cond_resched(); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(set_cpus_allowed_ptr); -+ -+#ifdef CONFIG_HOTPLUG_CPU -+/* -+ * Reschedule a task if it's on a dead CPU. -+ */ -+void move_task_off_dead_cpu(int dead_cpu, struct task_struct *p) -+{ -+ unsigned long flags; -+ struct rq *rq, *dead_rq; -+ -+ dead_rq = cpu_rq(dead_cpu); -+ rq = task_grq_lock(p, &flags); -+ if (rq == dead_rq && task_running(p)) -+ resched_task(p); -+ task_grq_unlock(&flags); -+ -+} -+ -+/* Run through task list and find tasks affined to just the dead cpu, then -+ * allocate a new affinity */ -+static void break_sole_affinity(int src_cpu) -+{ -+ struct task_struct *p, *t; -+ -+ do_each_thread(t, p) { -+ if (!online_cpus(p)) { -+ cpumask_copy(&p->cpus_allowed, cpu_possible_mask); -+ /* -+ * Don't tell them about moving exiting tasks or -+ * kernel threads (both mm NULL), since they never -+ * leave kernel. -+ */ -+ if (p->mm && printk_ratelimit()) { -+ printk(KERN_INFO "process %d (%s) no " -+ "longer affine to cpu %d\n", -+ task_pid_nr(p), p->comm, src_cpu); -+ } -+ } -+ } while_each_thread(t, p); -+} -+ -+/* -+ * Schedules idle task to be the next runnable task on current CPU. -+ * It does so by boosting its priority to highest possible. -+ * Used by CPU offline code. -+ */ -+void sched_idle_next(void) -+{ -+ int this_cpu = smp_processor_id(); -+ struct rq *rq = cpu_rq(this_cpu); -+ struct task_struct *idle = rq->idle; -+ unsigned long flags; -+ -+ /* cpu has to be offline */ -+ BUG_ON(cpu_online(this_cpu)); -+ -+ /* -+ * Strictly not necessary since rest of the CPUs are stopped by now -+ * and interrupts disabled on the current cpu. -+ */ -+ grq_lock_irqsave(&flags); -+ break_sole_affinity(this_cpu); -+ -+ __setscheduler(idle, rq, SCHED_FIFO, STOP_PRIO); -+ -+ activate_idle_task(idle); -+ set_tsk_need_resched(rq->curr); -+ -+ grq_unlock_irqrestore(&flags); -+} -+ -+void sched_set_stop_task(int cpu, struct task_struct *stop) -+{ -+ struct sched_param stop_param = { .sched_priority = STOP_PRIO }; -+ struct sched_param start_param = { .sched_priority = MAX_USER_RT_PRIO - 1 }; -+ struct task_struct *old_stop = cpu_rq(cpu)->stop; -+ -+ if (stop) { -+ /* -+ * Make it appear like a SCHED_FIFO task, its something -+ * userspace knows about and won't get confused about. -+ * -+ * Also, it will make PI more or less work without too -+ * much confusion -- but then, stop work should not -+ * rely on PI working anyway. -+ */ -+ sched_setscheduler_nocheck(stop, SCHED_FIFO, &stop_param); -+ } -+ -+ cpu_rq(cpu)->stop = stop; -+ -+ if (old_stop) { -+ /* -+ * Reset it back to a normal rt scheduling prio so that -+ * it can die in pieces. -+ */ -+ sched_setscheduler_nocheck(old_stop, SCHED_FIFO, &start_param); -+ } -+} -+ -+/* -+ * Ensures that the idle task is using init_mm right before its cpu goes -+ * offline. -+ */ -+void idle_task_exit(void) -+{ -+ struct mm_struct *mm = current->active_mm; -+ -+ BUG_ON(cpu_online(smp_processor_id())); -+ -+ if (mm != &init_mm) -+ switch_mm(mm, &init_mm, current); -+ mmdrop(mm); -+} -+ -+#endif /* CONFIG_HOTPLUG_CPU */ -+ -+#if defined(CONFIG_SCHED_DEBUG) && defined(CONFIG_SYSCTL) -+ -+static struct ctl_table sd_ctl_dir[] = { -+ { -+ .procname = "sched_domain", -+ .mode = 0555, -+ }, -+ {} -+}; -+ -+static struct ctl_table sd_ctl_root[] = { -+ { -+ .procname = "kernel", -+ .mode = 0555, -+ .child = sd_ctl_dir, -+ }, -+ {} -+}; -+ -+static struct ctl_table *sd_alloc_ctl_entry(int n) -+{ -+ struct ctl_table *entry = -+ kcalloc(n, sizeof(struct ctl_table), GFP_KERNEL); -+ -+ return entry; -+} -+ -+static void sd_free_ctl_entry(struct ctl_table **tablep) -+{ -+ struct ctl_table *entry; -+ -+ /* -+ * In the intermediate directories, both the child directory and -+ * procname are dynamically allocated and could fail but the mode -+ * will always be set. In the lowest directory the names are -+ * static strings and all have proc handlers. -+ */ -+ for (entry = *tablep; entry->mode; entry++) { -+ if (entry->child) -+ sd_free_ctl_entry(&entry->child); -+ if (entry->proc_handler == NULL) -+ kfree(entry->procname); -+ } -+ -+ kfree(*tablep); -+ *tablep = NULL; -+} -+ -+static void -+set_table_entry(struct ctl_table *entry, -+ const char *procname, void *data, int maxlen, -+ mode_t mode, proc_handler *proc_handler) -+{ -+ entry->procname = procname; -+ entry->data = data; -+ entry->maxlen = maxlen; -+ entry->mode = mode; -+ entry->proc_handler = proc_handler; -+} -+ -+static struct ctl_table * -+sd_alloc_ctl_domain_table(struct sched_domain *sd) -+{ -+ struct ctl_table *table = sd_alloc_ctl_entry(13); -+ -+ if (table == NULL) -+ return NULL; -+ -+ set_table_entry(&table[0], "min_interval", &sd->min_interval, -+ sizeof(long), 0644, proc_doulongvec_minmax); -+ set_table_entry(&table[1], "max_interval", &sd->max_interval, -+ sizeof(long), 0644, proc_doulongvec_minmax); -+ set_table_entry(&table[2], "busy_idx", &sd->busy_idx, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[3], "idle_idx", &sd->idle_idx, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[4], "newidle_idx", &sd->newidle_idx, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[5], "wake_idx", &sd->wake_idx, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[6], "forkexec_idx", &sd->forkexec_idx, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[7], "busy_factor", &sd->busy_factor, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[8], "imbalance_pct", &sd->imbalance_pct, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[9], "cache_nice_tries", -+ &sd->cache_nice_tries, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[10], "flags", &sd->flags, -+ sizeof(int), 0644, proc_dointvec_minmax); -+ set_table_entry(&table[11], "name", sd->name, -+ CORENAME_MAX_SIZE, 0444, proc_dostring); -+ /* &table[12] is terminator */ -+ -+ return table; -+} -+ -+static ctl_table *sd_alloc_ctl_cpu_table(int cpu) -+{ -+ struct ctl_table *entry, *table; -+ struct sched_domain *sd; -+ int domain_num = 0, i; -+ char buf[32]; -+ -+ for_each_domain(cpu, sd) -+ domain_num++; -+ entry = table = sd_alloc_ctl_entry(domain_num + 1); -+ if (table == NULL) -+ return NULL; -+ -+ i = 0; -+ for_each_domain(cpu, sd) { -+ snprintf(buf, 32, "domain%d", i); -+ entry->procname = kstrdup(buf, GFP_KERNEL); -+ entry->mode = 0555; -+ entry->child = sd_alloc_ctl_domain_table(sd); -+ entry++; -+ i++; -+ } -+ return table; -+} -+ -+static struct ctl_table_header *sd_sysctl_header; -+static void register_sched_domain_sysctl(void) -+{ -+ int i, cpu_num = num_possible_cpus(); -+ struct ctl_table *entry = sd_alloc_ctl_entry(cpu_num + 1); -+ char buf[32]; -+ -+ WARN_ON(sd_ctl_dir[0].child); -+ sd_ctl_dir[0].child = entry; -+ -+ if (entry == NULL) -+ return; -+ -+ for_each_possible_cpu(i) { -+ snprintf(buf, 32, "cpu%d", i); -+ entry->procname = kstrdup(buf, GFP_KERNEL); -+ entry->mode = 0555; -+ entry->child = sd_alloc_ctl_cpu_table(i); -+ entry++; -+ } -+ -+ WARN_ON(sd_sysctl_header); -+ sd_sysctl_header = register_sysctl_table(sd_ctl_root); -+} -+ -+/* may be called multiple times per register */ -+static void unregister_sched_domain_sysctl(void) -+{ -+ if (sd_sysctl_header) -+ unregister_sysctl_table(sd_sysctl_header); -+ sd_sysctl_header = NULL; -+ if (sd_ctl_dir[0].child) -+ sd_free_ctl_entry(&sd_ctl_dir[0].child); -+} -+#else -+static void register_sched_domain_sysctl(void) -+{ -+} -+static void unregister_sched_domain_sysctl(void) -+{ -+} -+#endif -+ -+static void set_rq_online(struct rq *rq) -+{ -+ if (!rq->online) { -+ cpumask_set_cpu(cpu_of(rq), rq->rd->online); -+ rq->online = 1; -+ } -+} -+ -+static void set_rq_offline(struct rq *rq) -+{ -+ if (rq->online) { -+ cpumask_clear_cpu(cpu_of(rq), rq->rd->online); -+ rq->online = 0; -+ } -+} -+ -+/* -+ * migration_call - callback that gets triggered when a CPU is added. -+ */ -+static int __cpuinit -+migration_call(struct notifier_block *nfb, unsigned long action, void *hcpu) -+{ -+#ifdef CONFIG_HOTPLUG_CPU -+ struct task_struct *idle; -+#endif -+ int cpu = (long)hcpu; -+ unsigned long flags; -+ struct rq *rq = cpu_rq(cpu); -+ -+ switch (action) { -+ -+ case CPU_UP_PREPARE: -+ case CPU_UP_PREPARE_FROZEN: -+ break; -+ -+ case CPU_ONLINE: -+ case CPU_ONLINE_FROZEN: -+ /* Update our root-domain */ -+ grq_lock_irqsave(&flags); -+ if (rq->rd) { -+ BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span)); -+ -+ set_rq_online(rq); -+ } -+ grq_unlock_irqrestore(&flags); -+ break; -+ -+#ifdef CONFIG_HOTPLUG_CPU -+ case CPU_DEAD: -+ case CPU_DEAD_FROZEN: -+ idle = rq->idle; -+ /* Idle task back to normal (off runqueue, low prio) */ -+ grq_lock_irq(); -+ return_task(idle, 1); -+ idle->static_prio = MAX_PRIO; -+ __setscheduler(idle, rq, SCHED_NORMAL, 0); -+ idle->prio = PRIO_LIMIT; -+ set_rq_task(rq, idle); -+ update_clocks(rq); -+ grq_unlock_irq(); -+ break; -+ -+ case CPU_DYING: -+ case CPU_DYING_FROZEN: -+ /* Update our root-domain */ -+ grq_lock_irqsave(&flags); -+ if (rq->rd) { -+ BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span)); -+ set_rq_offline(rq); -+ } -+ grq_unlock_irqrestore(&flags); -+ break; -+#endif -+ } -+ return NOTIFY_OK; -+} -+ -+/* -+ * Register at high priority so that task migration (migrate_all_tasks) -+ * happens before everything else. This has to be lower priority than -+ * the notifier in the perf_counter subsystem, though. -+ */ -+static struct notifier_block __cpuinitdata migration_notifier = { -+ .notifier_call = migration_call, -+ .priority = CPU_PRI_MIGRATION, -+}; -+ -+static int __cpuinit sched_cpu_active(struct notifier_block *nfb, -+ unsigned long action, void *hcpu) -+{ -+ switch (action & ~CPU_TASKS_FROZEN) { -+ case CPU_ONLINE: -+ case CPU_DOWN_FAILED: -+ set_cpu_active((long)hcpu, true); -+ return NOTIFY_OK; -+ default: -+ return NOTIFY_DONE; -+ } -+} -+ -+static int __cpuinit sched_cpu_inactive(struct notifier_block *nfb, -+ unsigned long action, void *hcpu) -+{ -+ switch (action & ~CPU_TASKS_FROZEN) { -+ case CPU_DOWN_PREPARE: -+ set_cpu_active((long)hcpu, false); -+ return NOTIFY_OK; -+ default: -+ return NOTIFY_DONE; -+ } -+} -+ -+int __init migration_init(void) -+{ -+ void *cpu = (void *)(long)smp_processor_id(); -+ int err; -+ -+ /* Initialise migration for the boot CPU */ -+ err = migration_call(&migration_notifier, CPU_UP_PREPARE, cpu); -+ BUG_ON(err == NOTIFY_BAD); -+ migration_call(&migration_notifier, CPU_ONLINE, cpu); -+ register_cpu_notifier(&migration_notifier); -+ -+ /* Register cpu active notifiers */ -+ cpu_notifier(sched_cpu_active, CPU_PRI_SCHED_ACTIVE); -+ cpu_notifier(sched_cpu_inactive, CPU_PRI_SCHED_INACTIVE); -+ -+ return 0; -+} -+early_initcall(migration_init); -+#endif -+ -+#ifdef CONFIG_SMP -+ -+#ifdef CONFIG_SCHED_DEBUG -+ -+static __read_mostly int sched_domain_debug_enabled; -+ -+static int __init sched_domain_debug_setup(char *str) -+{ -+ sched_domain_debug_enabled = 1; -+ -+ return 0; -+} -+early_param("sched_debug", sched_domain_debug_setup); -+ -+static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level, -+ struct cpumask *groupmask) -+{ -+ struct sched_group *group = sd->groups; -+ char str[256]; -+ -+ cpulist_scnprintf(str, sizeof(str), sched_domain_span(sd)); -+ cpumask_clear(groupmask); -+ -+ printk(KERN_DEBUG "%*s domain %d: ", level, "", level); -+ -+ if (!(sd->flags & SD_LOAD_BALANCE)) { -+ printk("does not load-balance\n"); -+ if (sd->parent) -+ printk(KERN_ERR "ERROR: !SD_LOAD_BALANCE domain" -+ " has parent"); -+ return -1; -+ } -+ -+ printk(KERN_CONT "span %s level %s\n", str, sd->name); -+ -+ if (!cpumask_test_cpu(cpu, sched_domain_span(sd))) { -+ printk(KERN_ERR "ERROR: domain->span does not contain " -+ "CPU%d\n", cpu); -+ } -+ if (!cpumask_test_cpu(cpu, sched_group_cpus(group))) { -+ printk(KERN_ERR "ERROR: domain->groups does not contain" -+ " CPU%d\n", cpu); -+ } -+ -+ printk(KERN_DEBUG "%*s groups:", level + 1, ""); -+ do { -+ if (!group) { -+ printk("\n"); -+ printk(KERN_ERR "ERROR: group is NULL\n"); -+ break; -+ } -+ -+ if (!group->cpu_power) { -+ printk(KERN_CONT "\n"); -+ printk(KERN_ERR "ERROR: domain->cpu_power not " -+ "set\n"); -+ break; -+ } -+ -+ if (!cpumask_weight(sched_group_cpus(group))) { -+ printk(KERN_CONT "\n"); -+ printk(KERN_ERR "ERROR: empty group\n"); -+ break; -+ } -+ -+ if (cpumask_intersects(groupmask, sched_group_cpus(group))) { -+ printk(KERN_CONT "\n"); -+ printk(KERN_ERR "ERROR: repeated CPUs\n"); -+ break; -+ } -+ -+ cpumask_or(groupmask, groupmask, sched_group_cpus(group)); -+ -+ cpulist_scnprintf(str, sizeof(str), sched_group_cpus(group)); -+ -+ printk(KERN_CONT " %s", str); -+ if (group->cpu_power != SCHED_LOAD_SCALE) { -+ printk(KERN_CONT " (cpu_power = %d)", -+ group->cpu_power); -+ } -+ -+ group = group->next; -+ } while (group != sd->groups); -+ printk(KERN_CONT "\n"); -+ -+ if (!cpumask_equal(sched_domain_span(sd), groupmask)) -+ printk(KERN_ERR "ERROR: groups don't span domain->span\n"); -+ -+ if (sd->parent && -+ !cpumask_subset(groupmask, sched_domain_span(sd->parent))) -+ printk(KERN_ERR "ERROR: parent span is not a superset " -+ "of domain->span\n"); -+ return 0; -+} -+ -+static void sched_domain_debug(struct sched_domain *sd, int cpu) -+{ -+ cpumask_var_t groupmask; -+ int level = 0; -+ -+ if (!sched_domain_debug_enabled) -+ return; -+ -+ if (!sd) { -+ printk(KERN_DEBUG "CPU%d attaching NULL sched-domain.\n", cpu); -+ return; -+ } -+ -+ printk(KERN_DEBUG "CPU%d attaching sched-domain:\n", cpu); -+ -+ if (!alloc_cpumask_var(&groupmask, GFP_KERNEL)) { -+ printk(KERN_DEBUG "Cannot load-balance (out of memory)\n"); -+ return; -+ } -+ -+ for (;;) { -+ if (sched_domain_debug_one(sd, cpu, level, groupmask)) -+ break; -+ level++; -+ sd = sd->parent; -+ if (!sd) -+ break; -+ } -+ free_cpumask_var(groupmask); -+} -+#else /* !CONFIG_SCHED_DEBUG */ -+# define sched_domain_debug(sd, cpu) do { } while (0) -+#endif /* CONFIG_SCHED_DEBUG */ -+ -+static int sd_degenerate(struct sched_domain *sd) -+{ -+ if (cpumask_weight(sched_domain_span(sd)) == 1) -+ return 1; -+ -+ /* Following flags need at least 2 groups */ -+ if (sd->flags & (SD_LOAD_BALANCE | -+ SD_BALANCE_NEWIDLE | -+ SD_BALANCE_FORK | -+ SD_BALANCE_EXEC | -+ SD_SHARE_CPUPOWER | -+ SD_SHARE_PKG_RESOURCES)) { -+ if (sd->groups != sd->groups->next) -+ return 0; -+ } -+ -+ /* Following flags don't use groups */ -+ if (sd->flags & (SD_WAKE_AFFINE)) -+ return 0; -+ -+ return 1; -+} -+ -+static int -+sd_parent_degenerate(struct sched_domain *sd, struct sched_domain *parent) -+{ -+ unsigned long cflags = sd->flags, pflags = parent->flags; -+ -+ if (sd_degenerate(parent)) -+ return 1; -+ -+ if (!cpumask_equal(sched_domain_span(sd), sched_domain_span(parent))) -+ return 0; -+ -+ /* Flags needing groups don't count if only 1 group in parent */ -+ if (parent->groups == parent->groups->next) { -+ pflags &= ~(SD_LOAD_BALANCE | -+ SD_BALANCE_NEWIDLE | -+ SD_BALANCE_FORK | -+ SD_BALANCE_EXEC | -+ SD_SHARE_CPUPOWER | -+ SD_SHARE_PKG_RESOURCES); -+ if (nr_node_ids == 1) -+ pflags &= ~SD_SERIALIZE; -+ } -+ if (~cflags & pflags) -+ return 0; -+ -+ return 1; -+} -+ -+static void free_rootdomain(struct root_domain *rd) -+{ -+ synchronize_sched(); -+ -+ free_cpumask_var(rd->rto_mask); -+ free_cpumask_var(rd->online); -+ free_cpumask_var(rd->span); -+ kfree(rd); -+} -+ -+static void rq_attach_root(struct rq *rq, struct root_domain *rd) -+{ -+ struct root_domain *old_rd = NULL; -+ unsigned long flags; -+ -+ grq_lock_irqsave(&flags); -+ -+ if (rq->rd) { -+ old_rd = rq->rd; -+ -+ if (cpumask_test_cpu(cpu_of(rq), old_rd->online)) -+ set_rq_offline(rq); -+ -+ cpumask_clear_cpu(cpu_of(rq), old_rd->span); -+ -+ /* -+ * If we dont want to free the old_rt yet then -+ * set old_rd to NULL to skip the freeing later -+ * in this function: -+ */ -+ if (!atomic_dec_and_test(&old_rd->refcount)) -+ old_rd = NULL; -+ } -+ -+ atomic_inc(&rd->refcount); -+ rq->rd = rd; -+ -+ cpumask_set_cpu(cpu_of(rq), rd->span); -+ if (cpumask_test_cpu(rq->cpu, cpu_active_mask)) -+ set_rq_online(rq); -+ -+ grq_unlock_irqrestore(&flags); -+ -+ if (old_rd) -+ free_rootdomain(old_rd); -+} -+ -+static int init_rootdomain(struct root_domain *rd) -+{ -+ memset(rd, 0, sizeof(*rd)); -+ -+ if (!alloc_cpumask_var(&rd->span, GFP_KERNEL)) -+ goto out; -+ if (!alloc_cpumask_var(&rd->online, GFP_KERNEL)) -+ goto free_span; -+ if (!alloc_cpumask_var(&rd->rto_mask, GFP_KERNEL)) -+ goto free_online; -+ -+ if (cpupri_init(&rd->cpupri) != 0) -+ goto free_rto_mask; -+ return 0; -+ -+free_rto_mask: -+ free_cpumask_var(rd->rto_mask); -+free_online: -+ free_cpumask_var(rd->online); -+free_span: -+ free_cpumask_var(rd->span); -+out: -+ return -ENOMEM; -+} -+ -+static void init_defrootdomain(void) -+{ -+ init_rootdomain(&def_root_domain); -+ -+ atomic_set(&def_root_domain.refcount, 1); -+} -+ -+static struct root_domain *alloc_rootdomain(void) -+{ -+ struct root_domain *rd; -+ -+ rd = kmalloc(sizeof(*rd), GFP_KERNEL); -+ if (!rd) -+ return NULL; -+ -+ if (init_rootdomain(rd) != 0) { -+ kfree(rd); -+ return NULL; -+ } -+ -+ return rd; -+} -+ -+/* -+ * Attach the domain 'sd' to 'cpu' as its base domain. Callers must -+ * hold the hotplug lock. -+ */ -+static void -+cpu_attach_domain(struct sched_domain *sd, struct root_domain *rd, int cpu) -+{ -+ struct rq *rq = cpu_rq(cpu); -+ struct sched_domain *tmp; -+ -+ for (tmp = sd; tmp; tmp = tmp->parent) -+ tmp->span_weight = cpumask_weight(sched_domain_span(tmp)); -+ -+ /* Remove the sched domains which do not contribute to scheduling. */ -+ for (tmp = sd; tmp; ) { -+ struct sched_domain *parent = tmp->parent; -+ if (!parent) -+ break; -+ -+ if (sd_parent_degenerate(tmp, parent)) { -+ tmp->parent = parent->parent; -+ if (parent->parent) -+ parent->parent->child = tmp; -+ } else -+ tmp = tmp->parent; -+ } -+ -+ if (sd && sd_degenerate(sd)) { -+ sd = sd->parent; -+ if (sd) -+ sd->child = NULL; -+ } -+ -+ sched_domain_debug(sd, cpu); -+ -+ rq_attach_root(rq, rd); -+ rcu_assign_pointer(rq->sd, sd); -+} -+ -+/* cpus with isolated domains */ -+static cpumask_var_t cpu_isolated_map; -+ -+/* Setup the mask of cpus configured for isolated domains */ -+static int __init isolated_cpu_setup(char *str) -+{ -+ alloc_bootmem_cpumask_var(&cpu_isolated_map); -+ cpulist_parse(str, cpu_isolated_map); -+ return 1; -+} -+ -+__setup("isolcpus=", isolated_cpu_setup); -+ -+/* -+ * init_sched_build_groups takes the cpumask we wish to span, and a pointer -+ * to a function which identifies what group(along with sched group) a CPU -+ * belongs to. The return value of group_fn must be a >= 0 and < nr_cpu_ids -+ * (due to the fact that we keep track of groups covered with a struct cpumask). -+ * -+ * init_sched_build_groups will build a circular linked list of the groups -+ * covered by the given span, and will set each group's ->cpumask correctly, -+ * and ->cpu_power to 0. -+ */ -+static void -+init_sched_build_groups(const struct cpumask *span, -+ const struct cpumask *cpu_map, -+ int (*group_fn)(int cpu, const struct cpumask *cpu_map, -+ struct sched_group **sg, -+ struct cpumask *tmpmask), -+ struct cpumask *covered, struct cpumask *tmpmask) -+{ -+ struct sched_group *first = NULL, *last = NULL; -+ int i; -+ -+ cpumask_clear(covered); -+ -+ for_each_cpu(i, span) { -+ struct sched_group *sg; -+ int group = group_fn(i, cpu_map, &sg, tmpmask); -+ int j; -+ -+ if (cpumask_test_cpu(i, covered)) -+ continue; -+ -+ cpumask_clear(sched_group_cpus(sg)); -+ sg->cpu_power = 0; -+ -+ for_each_cpu(j, span) { -+ if (group_fn(j, cpu_map, NULL, tmpmask) != group) -+ continue; -+ -+ cpumask_set_cpu(j, covered); -+ cpumask_set_cpu(j, sched_group_cpus(sg)); -+ } -+ if (!first) -+ first = sg; -+ if (last) -+ last->next = sg; -+ last = sg; -+ } -+ last->next = first; -+} -+ -+#define SD_NODES_PER_DOMAIN 16 -+ -+#ifdef CONFIG_NUMA -+ -+/** -+ * find_next_best_node - find the next node to include in a sched_domain -+ * @node: node whose sched_domain we're building -+ * @used_nodes: nodes already in the sched_domain -+ * -+ * Find the next node to include in a given scheduling domain. Simply -+ * finds the closest node not already in the @used_nodes map. -+ * -+ * Should use nodemask_t. -+ */ -+static int find_next_best_node(int node, nodemask_t *used_nodes) -+{ -+ int i, n, val, min_val, best_node = 0; -+ -+ min_val = INT_MAX; -+ -+ for (i = 0; i < nr_node_ids; i++) { -+ /* Start at @node */ -+ n = (node + i) % nr_node_ids; -+ -+ if (!nr_cpus_node(n)) -+ continue; -+ -+ /* Skip already used nodes */ -+ if (node_isset(n, *used_nodes)) -+ continue; -+ -+ /* Simple min distance search */ -+ val = node_distance(node, n); -+ -+ if (val < min_val) { -+ min_val = val; -+ best_node = n; -+ } -+ } -+ -+ node_set(best_node, *used_nodes); -+ return best_node; -+} -+ -+/** -+ * sched_domain_node_span - get a cpumask for a node's sched_domain -+ * @node: node whose cpumask we're constructing -+ * @span: resulting cpumask -+ * -+ * Given a node, construct a good cpumask for its sched_domain to span. It -+ * should be one that prevents unnecessary balancing, but also spreads tasks -+ * out optimally. -+ */ -+static void sched_domain_node_span(int node, struct cpumask *span) -+{ -+ nodemask_t used_nodes; -+ int i; -+ -+ cpumask_clear(span); -+ nodes_clear(used_nodes); -+ -+ cpumask_or(span, span, cpumask_of_node(node)); -+ node_set(node, used_nodes); -+ -+ for (i = 1; i < SD_NODES_PER_DOMAIN; i++) { -+ int next_node = find_next_best_node(node, &used_nodes); -+ -+ cpumask_or(span, span, cpumask_of_node(next_node)); -+ } -+} -+#endif /* CONFIG_NUMA */ -+ -+int sched_smt_power_savings = 0, sched_mc_power_savings = 0; -+ -+/* -+ * The cpus mask in sched_group and sched_domain hangs off the end. -+ * -+ * ( See the the comments in include/linux/sched.h:struct sched_group -+ * and struct sched_domain. ) -+ */ -+struct static_sched_group { -+ struct sched_group sg; -+ DECLARE_BITMAP(cpus, CONFIG_NR_CPUS); -+}; -+ -+struct static_sched_domain { -+ struct sched_domain sd; -+ DECLARE_BITMAP(span, CONFIG_NR_CPUS); -+}; -+ -+struct s_data { -+#ifdef CONFIG_NUMA -+ int sd_allnodes; -+ cpumask_var_t domainspan; -+ cpumask_var_t covered; -+ cpumask_var_t notcovered; -+#endif -+ cpumask_var_t nodemask; -+ cpumask_var_t this_sibling_map; -+ cpumask_var_t this_core_map; -+ cpumask_var_t this_book_map; -+ cpumask_var_t send_covered; -+ cpumask_var_t tmpmask; -+ struct sched_group **sched_group_nodes; -+ struct root_domain *rd; -+}; -+ -+enum s_alloc { -+ sa_sched_groups = 0, -+ sa_rootdomain, -+ sa_tmpmask, -+ sa_send_covered, -+ sa_this_book_map, -+ sa_this_core_map, -+ sa_this_sibling_map, -+ sa_nodemask, -+ sa_sched_group_nodes, -+#ifdef CONFIG_NUMA -+ sa_notcovered, -+ sa_covered, -+ sa_domainspan, -+#endif -+ sa_none, -+}; -+ -+/* -+ * SMT sched-domains: -+ */ -+#ifdef CONFIG_SCHED_SMT -+static DEFINE_PER_CPU(struct static_sched_domain, cpu_domains); -+static DEFINE_PER_CPU(struct static_sched_group, sched_groups); -+ -+static int -+cpu_to_cpu_group(int cpu, const struct cpumask *cpu_map, -+ struct sched_group **sg, struct cpumask *unused) -+{ -+ if (sg) -+ *sg = &per_cpu(sched_groups, cpu).sg; -+ return cpu; -+} -+#endif /* CONFIG_SCHED_SMT */ -+ -+/* -+ * multi-core sched-domains: -+ */ -+#ifdef CONFIG_SCHED_MC -+static DEFINE_PER_CPU(struct static_sched_domain, core_domains); -+static DEFINE_PER_CPU(struct static_sched_group, sched_group_core); -+ -+static int -+cpu_to_core_group(int cpu, const struct cpumask *cpu_map, -+ struct sched_group **sg, struct cpumask *mask) -+{ -+ int group; -+#ifdef CONFIG_SCHED_SMT -+ cpumask_and(mask, topology_thread_cpumask(cpu), cpu_map); -+ group = cpumask_first(mask); -+#else -+ group = cpu; -+#endif -+ if (sg) -+ *sg = &per_cpu(sched_group_core, group).sg; -+ return group; -+} -+#endif /* CONFIG_SCHED_MC */ -+ -+/* -+ * book sched-domains: -+ */ -+#ifdef CONFIG_SCHED_BOOK -+static DEFINE_PER_CPU(struct static_sched_domain, book_domains); -+static DEFINE_PER_CPU(struct static_sched_group, sched_group_book); -+ -+static int -+cpu_to_book_group(int cpu, const struct cpumask *cpu_map, -+ struct sched_group **sg, struct cpumask *mask) -+{ -+ int group = cpu; -+#ifdef CONFIG_SCHED_MC -+ cpumask_and(mask, cpu_coregroup_mask(cpu), cpu_map); -+ group = cpumask_first(mask); -+#elif defined(CONFIG_SCHED_SMT) -+ cpumask_and(mask, topology_thread_cpumask(cpu), cpu_map); -+ group = cpumask_first(mask); -+#endif -+ if (sg) -+ *sg = &per_cpu(sched_group_book, group).sg; -+ return group; -+} -+#endif /* CONFIG_SCHED_BOOK */ -+ -+static DEFINE_PER_CPU(struct static_sched_domain, phys_domains); -+static DEFINE_PER_CPU(struct static_sched_group, sched_group_phys); -+ -+static int -+cpu_to_phys_group(int cpu, const struct cpumask *cpu_map, -+ struct sched_group **sg, struct cpumask *mask) -+{ -+ int group; -+#ifdef CONFIG_SCHED_BOOK -+ cpumask_and(mask, cpu_book_mask(cpu), cpu_map); -+ group = cpumask_first(mask); -+#elif defined(CONFIG_SCHED_MC) -+ cpumask_and(mask, cpu_coregroup_mask(cpu), cpu_map); -+ group = cpumask_first(mask); -+#elif defined(CONFIG_SCHED_SMT) -+ cpumask_and(mask, topology_thread_cpumask(cpu), cpu_map); -+ group = cpumask_first(mask); -+#else -+ group = cpu; -+#endif -+ if (sg) -+ *sg = &per_cpu(sched_group_phys, group).sg; -+ return group; -+} -+ -+/** -+ * group_first_cpu - Returns the first cpu in the cpumask of a sched_group. -+ * @group: The group whose first cpu is to be returned. -+ */ -+static inline unsigned int group_first_cpu(struct sched_group *group) -+{ -+ return cpumask_first(sched_group_cpus(group)); -+} -+ -+#ifdef CONFIG_NUMA -+/* -+ * The init_sched_build_groups can't handle what we want to do with node -+ * groups, so roll our own. Now each node has its own list of groups which -+ * gets dynamically allocated. -+ */ -+static DEFINE_PER_CPU(struct static_sched_domain, node_domains); -+static struct sched_group ***sched_group_nodes_bycpu; -+ -+static DEFINE_PER_CPU(struct static_sched_domain, allnodes_domains); -+static DEFINE_PER_CPU(struct static_sched_group, sched_group_allnodes); -+ -+static int cpu_to_allnodes_group(int cpu, const struct cpumask *cpu_map, -+ struct sched_group **sg, -+ struct cpumask *nodemask) -+{ -+ int group; -+ -+ cpumask_and(nodemask, cpumask_of_node(cpu_to_node(cpu)), cpu_map); -+ group = cpumask_first(nodemask); -+ -+ if (sg) -+ *sg = &per_cpu(sched_group_allnodes, group).sg; -+ return group; -+} -+ -+static void init_numa_sched_groups_power(struct sched_group *group_head) -+{ -+ struct sched_group *sg = group_head; -+ int j; -+ -+ if (!sg) -+ return; -+ do { -+ for_each_cpu(j, sched_group_cpus(sg)) { -+ struct sched_domain *sd; -+ -+ sd = &per_cpu(phys_domains, j).sd; -+ if (j != group_first_cpu(sd->groups)) { -+ /* -+ * Only add "power" once for each -+ * physical package. -+ */ -+ continue; -+ } -+ -+ sg->cpu_power += sd->groups->cpu_power; -+ } -+ sg = sg->next; -+ } while (sg != group_head); -+} -+ -+static int build_numa_sched_groups(struct s_data *d, -+ const struct cpumask *cpu_map, int num) -+{ -+ struct sched_domain *sd; -+ struct sched_group *sg, *prev; -+ int n, j; -+ -+ cpumask_clear(d->covered); -+ cpumask_and(d->nodemask, cpumask_of_node(num), cpu_map); -+ if (cpumask_empty(d->nodemask)) { -+ d->sched_group_nodes[num] = NULL; -+ goto out; -+ } -+ -+ sched_domain_node_span(num, d->domainspan); -+ cpumask_and(d->domainspan, d->domainspan, cpu_map); -+ -+ sg = kmalloc_node(sizeof(struct sched_group) + cpumask_size(), -+ GFP_KERNEL, num); -+ if (!sg) { -+ printk(KERN_WARNING "Can not alloc domain group for node %d\n", -+ num); -+ return -ENOMEM; -+ } -+ d->sched_group_nodes[num] = sg; -+ -+ for_each_cpu(j, d->nodemask) { -+ sd = &per_cpu(node_domains, j).sd; -+ sd->groups = sg; -+ } -+ -+ sg->cpu_power = 0; -+ cpumask_copy(sched_group_cpus(sg), d->nodemask); -+ sg->next = sg; -+ cpumask_or(d->covered, d->covered, d->nodemask); -+ -+ prev = sg; -+ for (j = 0; j < nr_node_ids; j++) { -+ n = (num + j) % nr_node_ids; -+ cpumask_complement(d->notcovered, d->covered); -+ cpumask_and(d->tmpmask, d->notcovered, cpu_map); -+ cpumask_and(d->tmpmask, d->tmpmask, d->domainspan); -+ if (cpumask_empty(d->tmpmask)) -+ break; -+ cpumask_and(d->tmpmask, d->tmpmask, cpumask_of_node(n)); -+ if (cpumask_empty(d->tmpmask)) -+ continue; -+ sg = kmalloc_node(sizeof(struct sched_group) + cpumask_size(), -+ GFP_KERNEL, num); -+ if (!sg) { -+ printk(KERN_WARNING -+ "Can not alloc domain group for node %d\n", j); -+ return -ENOMEM; -+ } -+ sg->cpu_power = 0; -+ cpumask_copy(sched_group_cpus(sg), d->tmpmask); -+ sg->next = prev->next; -+ cpumask_or(d->covered, d->covered, d->tmpmask); -+ prev->next = sg; -+ prev = sg; -+ } -+out: -+ return 0; -+} -+#endif /* CONFIG_NUMA */ -+ -+#ifdef CONFIG_NUMA -+/* Free memory allocated for various sched_group structures */ -+static void free_sched_groups(const struct cpumask *cpu_map, -+ struct cpumask *nodemask) -+{ -+ int cpu, i; -+ -+ for_each_cpu(cpu, cpu_map) { -+ struct sched_group **sched_group_nodes -+ = sched_group_nodes_bycpu[cpu]; -+ -+ if (!sched_group_nodes) -+ continue; -+ -+ for (i = 0; i < nr_node_ids; i++) { -+ struct sched_group *oldsg, *sg = sched_group_nodes[i]; -+ -+ cpumask_and(nodemask, cpumask_of_node(i), cpu_map); -+ if (cpumask_empty(nodemask)) -+ continue; -+ -+ if (sg == NULL) -+ continue; -+ sg = sg->next; -+next_sg: -+ oldsg = sg; -+ sg = sg->next; -+ kfree(oldsg); -+ if (oldsg != sched_group_nodes[i]) -+ goto next_sg; -+ } -+ kfree(sched_group_nodes); -+ sched_group_nodes_bycpu[cpu] = NULL; -+ } -+} -+#else /* !CONFIG_NUMA */ -+static void free_sched_groups(const struct cpumask *cpu_map, -+ struct cpumask *nodemask) -+{ -+} -+#endif /* CONFIG_NUMA */ -+ -+/* -+ * Initialise sched groups cpu_power. -+ * -+ * cpu_power indicates the capacity of sched group, which is used while -+ * distributing the load between different sched groups in a sched domain. -+ * Typically cpu_power for all the groups in a sched domain will be same unless -+ * there are asymmetries in the topology. If there are asymmetries, group -+ * having more cpu_power will pickup more load compared to the group having -+ * less cpu_power. -+ * -+ * cpu_power will be a multiple of SCHED_LOAD_SCALE. This multiple represents -+ * the maximum number of tasks a group can handle in the presence of other idle -+ * or lightly loaded groups in the same sched domain. -+ */ -+static void init_sched_groups_power(int cpu, struct sched_domain *sd) -+{ -+ struct sched_domain *child; -+ struct sched_group *group; -+ long power; -+ int weight; -+ -+ WARN_ON(!sd || !sd->groups); -+ -+ if (cpu != group_first_cpu(sd->groups)) -+ return; -+ -+ sd->groups->group_weight = cpumask_weight(sched_group_cpus(sd->groups)); -+ -+ child = sd->child; -+ -+ sd->groups->cpu_power = 0; -+ -+ if (!child) { -+ power = SCHED_LOAD_SCALE; -+ weight = cpumask_weight(sched_domain_span(sd)); -+ /* -+ * SMT siblings share the power of a single core. -+ * Usually multiple threads get a better yield out of -+ * that one core than a single thread would have, -+ * reflect that in sd->smt_gain. -+ */ -+ if ((sd->flags & SD_SHARE_CPUPOWER) && weight > 1) { -+ power *= sd->smt_gain; -+ power /= weight; -+ power >>= SCHED_LOAD_SHIFT; -+ } -+ sd->groups->cpu_power += power; -+ return; -+ } -+ -+ /* -+ * Add cpu_power of each child group to this groups cpu_power -+ */ -+ group = child->groups; -+ do { -+ sd->groups->cpu_power += group->cpu_power; -+ group = group->next; -+ } while (group != child->groups); -+} -+ -+/* -+ * Initialisers for schedule domains -+ * Non-inlined to reduce accumulated stack pressure in build_sched_domains() -+ */ -+ -+#ifdef CONFIG_SCHED_DEBUG -+# define SD_INIT_NAME(sd, type) sd->name = #type -+#else -+# define SD_INIT_NAME(sd, type) do { } while (0) -+#endif -+ -+#define SD_INIT(sd, type) sd_init_##type(sd) -+ -+#define SD_INIT_FUNC(type) \ -+static noinline void sd_init_##type(struct sched_domain *sd) \ -+{ \ -+ memset(sd, 0, sizeof(*sd)); \ -+ *sd = SD_##type##_INIT; \ -+ sd->level = SD_LV_##type; \ -+ SD_INIT_NAME(sd, type); \ -+} -+ -+SD_INIT_FUNC(CPU) -+#ifdef CONFIG_NUMA -+ SD_INIT_FUNC(ALLNODES) -+ SD_INIT_FUNC(NODE) -+#endif -+#ifdef CONFIG_SCHED_SMT -+ SD_INIT_FUNC(SIBLING) -+#endif -+#ifdef CONFIG_SCHED_MC -+ SD_INIT_FUNC(MC) -+#endif -+#ifdef CONFIG_SCHED_BOOK -+ SD_INIT_FUNC(BOOK) -+#endif -+ -+static int default_relax_domain_level = -1; -+ -+static int __init setup_relax_domain_level(char *str) -+{ -+ unsigned long val; -+ -+ val = simple_strtoul(str, NULL, 0); -+ if (val < SD_LV_MAX) -+ default_relax_domain_level = val; -+ -+ return 1; -+} -+__setup("relax_domain_level=", setup_relax_domain_level); -+ -+static void set_domain_attribute(struct sched_domain *sd, -+ struct sched_domain_attr *attr) -+{ -+ int request; -+ -+ if (!attr || attr->relax_domain_level < 0) { -+ if (default_relax_domain_level < 0) -+ return; -+ else -+ request = default_relax_domain_level; -+ } else -+ request = attr->relax_domain_level; -+ if (request < sd->level) { -+ /* turn off idle balance on this domain */ -+ sd->flags &= ~(SD_BALANCE_WAKE|SD_BALANCE_NEWIDLE); -+ } else { -+ /* turn on idle balance on this domain */ -+ sd->flags |= (SD_BALANCE_WAKE|SD_BALANCE_NEWIDLE); -+ } -+} -+ -+static void __free_domain_allocs(struct s_data *d, enum s_alloc what, -+ const struct cpumask *cpu_map) -+{ -+ switch (what) { -+ case sa_sched_groups: -+ free_sched_groups(cpu_map, d->tmpmask); /* fall through */ -+ d->sched_group_nodes = NULL; -+ case sa_rootdomain: -+ free_rootdomain(d->rd); /* fall through */ -+ case sa_tmpmask: -+ free_cpumask_var(d->tmpmask); /* fall through */ -+ case sa_send_covered: -+ free_cpumask_var(d->send_covered); /* fall through */ -+ case sa_this_book_map: -+ free_cpumask_var(d->this_book_map); /* fall through */ -+ case sa_this_core_map: -+ free_cpumask_var(d->this_core_map); /* fall through */ -+ case sa_this_sibling_map: -+ free_cpumask_var(d->this_sibling_map); /* fall through */ -+ case sa_nodemask: -+ free_cpumask_var(d->nodemask); /* fall through */ -+ case sa_sched_group_nodes: -+#ifdef CONFIG_NUMA -+ kfree(d->sched_group_nodes); /* fall through */ -+ case sa_notcovered: -+ free_cpumask_var(d->notcovered); /* fall through */ -+ case sa_covered: -+ free_cpumask_var(d->covered); /* fall through */ -+ case sa_domainspan: -+ free_cpumask_var(d->domainspan); /* fall through */ -+#endif -+ case sa_none: -+ break; -+ } -+} -+ -+static enum s_alloc __visit_domain_allocation_hell(struct s_data *d, -+ const struct cpumask *cpu_map) -+{ -+#ifdef CONFIG_NUMA -+ if (!alloc_cpumask_var(&d->domainspan, GFP_KERNEL)) -+ return sa_none; -+ if (!alloc_cpumask_var(&d->covered, GFP_KERNEL)) -+ return sa_domainspan; -+ if (!alloc_cpumask_var(&d->notcovered, GFP_KERNEL)) -+ return sa_covered; -+ /* Allocate the per-node list of sched groups */ -+ d->sched_group_nodes = kcalloc(nr_node_ids, -+ sizeof(struct sched_group *), GFP_KERNEL); -+ if (!d->sched_group_nodes) { -+ printk(KERN_WARNING "Can not alloc sched group node list\n"); -+ return sa_notcovered; -+ } -+ sched_group_nodes_bycpu[cpumask_first(cpu_map)] = d->sched_group_nodes; -+#endif -+ if (!alloc_cpumask_var(&d->nodemask, GFP_KERNEL)) -+ return sa_sched_group_nodes; -+ if (!alloc_cpumask_var(&d->this_sibling_map, GFP_KERNEL)) -+ return sa_nodemask; -+ if (!alloc_cpumask_var(&d->this_core_map, GFP_KERNEL)) -+ return sa_this_sibling_map; -+ if (!alloc_cpumask_var(&d->this_book_map, GFP_KERNEL)) -+ return sa_this_core_map; -+ if (!alloc_cpumask_var(&d->send_covered, GFP_KERNEL)) -+ return sa_this_book_map; -+ if (!alloc_cpumask_var(&d->tmpmask, GFP_KERNEL)) -+ return sa_send_covered; -+ d->rd = alloc_rootdomain(); -+ if (!d->rd) { -+ printk(KERN_WARNING "Cannot alloc root domain\n"); -+ return sa_tmpmask; -+ } -+ return sa_rootdomain; -+} -+ -+static struct sched_domain *__build_numa_sched_domains(struct s_data *d, -+ const struct cpumask *cpu_map, struct sched_domain_attr *attr, int i) -+{ -+ struct sched_domain *sd = NULL; -+#ifdef CONFIG_NUMA -+ struct sched_domain *parent; -+ -+ d->sd_allnodes = 0; -+ if (cpumask_weight(cpu_map) > -+ SD_NODES_PER_DOMAIN * cpumask_weight(d->nodemask)) { -+ sd = &per_cpu(allnodes_domains, i).sd; -+ SD_INIT(sd, ALLNODES); -+ set_domain_attribute(sd, attr); -+ cpumask_copy(sched_domain_span(sd), cpu_map); -+ cpu_to_allnodes_group(i, cpu_map, &sd->groups, d->tmpmask); -+ d->sd_allnodes = 1; -+ } -+ parent = sd; -+ -+ sd = &per_cpu(node_domains, i).sd; -+ SD_INIT(sd, NODE); -+ set_domain_attribute(sd, attr); -+ sched_domain_node_span(cpu_to_node(i), sched_domain_span(sd)); -+ sd->parent = parent; -+ if (parent) -+ parent->child = sd; -+ cpumask_and(sched_domain_span(sd), sched_domain_span(sd), cpu_map); -+#endif -+ return sd; -+} -+ -+static struct sched_domain *__build_cpu_sched_domain(struct s_data *d, -+ const struct cpumask *cpu_map, struct sched_domain_attr *attr, -+ struct sched_domain *parent, int i) -+{ -+ struct sched_domain *sd; -+ sd = &per_cpu(phys_domains, i).sd; -+ SD_INIT(sd, CPU); -+ set_domain_attribute(sd, attr); -+ cpumask_copy(sched_domain_span(sd), d->nodemask); -+ sd->parent = parent; -+ if (parent) -+ parent->child = sd; -+ cpu_to_phys_group(i, cpu_map, &sd->groups, d->tmpmask); -+ return sd; -+} -+ -+static struct sched_domain *__build_book_sched_domain(struct s_data *d, -+ const struct cpumask *cpu_map, struct sched_domain_attr *attr, -+ struct sched_domain *parent, int i) -+{ -+ struct sched_domain *sd = parent; -+#ifdef CONFIG_SCHED_BOOK -+ sd = &per_cpu(book_domains, i).sd; -+ SD_INIT(sd, BOOK); -+ set_domain_attribute(sd, attr); -+ cpumask_and(sched_domain_span(sd), cpu_map, cpu_book_mask(i)); -+ sd->parent = parent; -+ parent->child = sd; -+ cpu_to_book_group(i, cpu_map, &sd->groups, d->tmpmask); -+#endif -+ return sd; -+} -+ -+static struct sched_domain *__build_mc_sched_domain(struct s_data *d, -+ const struct cpumask *cpu_map, struct sched_domain_attr *attr, -+ struct sched_domain *parent, int i) -+{ -+ struct sched_domain *sd = parent; -+#ifdef CONFIG_SCHED_MC -+ sd = &per_cpu(core_domains, i).sd; -+ SD_INIT(sd, MC); -+ set_domain_attribute(sd, attr); -+ cpumask_and(sched_domain_span(sd), cpu_map, cpu_coregroup_mask(i)); -+ sd->parent = parent; -+ parent->child = sd; -+ cpu_to_core_group(i, cpu_map, &sd->groups, d->tmpmask); -+#endif -+ return sd; -+} -+ -+static struct sched_domain *__build_smt_sched_domain(struct s_data *d, -+ const struct cpumask *cpu_map, struct sched_domain_attr *attr, -+ struct sched_domain *parent, int i) -+{ -+ struct sched_domain *sd = parent; -+#ifdef CONFIG_SCHED_SMT -+ sd = &per_cpu(cpu_domains, i).sd; -+ SD_INIT(sd, SIBLING); -+ set_domain_attribute(sd, attr); -+ cpumask_and(sched_domain_span(sd), cpu_map, topology_thread_cpumask(i)); -+ sd->parent = parent; -+ parent->child = sd; -+ cpu_to_cpu_group(i, cpu_map, &sd->groups, d->tmpmask); -+#endif -+ return sd; -+} -+ -+static void build_sched_groups(struct s_data *d, enum sched_domain_level l, -+ const struct cpumask *cpu_map, int cpu) -+{ -+ switch (l) { -+#ifdef CONFIG_SCHED_SMT -+ case SD_LV_SIBLING: /* set up CPU (sibling) groups */ -+ cpumask_and(d->this_sibling_map, cpu_map, -+ topology_thread_cpumask(cpu)); -+ if (cpu == cpumask_first(d->this_sibling_map)) -+ init_sched_build_groups(d->this_sibling_map, cpu_map, -+ &cpu_to_cpu_group, -+ d->send_covered, d->tmpmask); -+ break; -+#endif -+#ifdef CONFIG_SCHED_MC -+ case SD_LV_MC: /* set up multi-core groups */ -+ cpumask_and(d->this_core_map, cpu_map, cpu_coregroup_mask(cpu)); -+ if (cpu == cpumask_first(d->this_core_map)) -+ init_sched_build_groups(d->this_core_map, cpu_map, -+ &cpu_to_core_group, -+ d->send_covered, d->tmpmask); -+ break; -+#endif -+#ifdef CONFIG_SCHED_BOOK -+ case SD_LV_BOOK: /* set up book groups */ -+ cpumask_and(d->this_book_map, cpu_map, cpu_book_mask(cpu)); -+ if (cpu == cpumask_first(d->this_book_map)) -+ init_sched_build_groups(d->this_book_map, cpu_map, -+ &cpu_to_book_group, -+ d->send_covered, d->tmpmask); -+ break; -+#endif -+ case SD_LV_CPU: /* set up physical groups */ -+ cpumask_and(d->nodemask, cpumask_of_node(cpu), cpu_map); -+ if (!cpumask_empty(d->nodemask)) -+ init_sched_build_groups(d->nodemask, cpu_map, -+ &cpu_to_phys_group, -+ d->send_covered, d->tmpmask); -+ break; -+#ifdef CONFIG_NUMA -+ case SD_LV_ALLNODES: -+ init_sched_build_groups(cpu_map, cpu_map, &cpu_to_allnodes_group, -+ d->send_covered, d->tmpmask); -+ break; -+#endif -+ default: -+ break; -+ } -+} -+ -+/* -+ * Build sched domains for a given set of cpus and attach the sched domains -+ * to the individual cpus -+ */ -+static int __build_sched_domains(const struct cpumask *cpu_map, -+ struct sched_domain_attr *attr) -+{ -+ enum s_alloc alloc_state = sa_none; -+ struct s_data d; -+ struct sched_domain *sd; -+ int i; -+#ifdef CONFIG_NUMA -+ d.sd_allnodes = 0; -+#endif -+ -+ alloc_state = __visit_domain_allocation_hell(&d, cpu_map); -+ if (alloc_state != sa_rootdomain) -+ goto error; -+ alloc_state = sa_sched_groups; -+ -+ /* -+ * Set up domains for cpus specified by the cpu_map. -+ */ -+ for_each_cpu(i, cpu_map) { -+ cpumask_and(d.nodemask, cpumask_of_node(cpu_to_node(i)), -+ cpu_map); -+ -+ sd = __build_numa_sched_domains(&d, cpu_map, attr, i); -+ sd = __build_cpu_sched_domain(&d, cpu_map, attr, sd, i); -+ sd = __build_book_sched_domain(&d, cpu_map, attr, sd, i); -+ sd = __build_mc_sched_domain(&d, cpu_map, attr, sd, i); -+ sd = __build_smt_sched_domain(&d, cpu_map, attr, sd, i); -+ } -+ -+ for_each_cpu(i, cpu_map) { -+ build_sched_groups(&d, SD_LV_SIBLING, cpu_map, i); -+ build_sched_groups(&d, SD_LV_BOOK, cpu_map, i); -+ build_sched_groups(&d, SD_LV_MC, cpu_map, i); -+ } -+ -+ /* Set up physical groups */ -+ for (i = 0; i < nr_node_ids; i++) -+ build_sched_groups(&d, SD_LV_CPU, cpu_map, i); -+ -+#ifdef CONFIG_NUMA -+ /* Set up node groups */ -+ if (d.sd_allnodes) -+ build_sched_groups(&d, SD_LV_ALLNODES, cpu_map, 0); -+ -+ for (i = 0; i < nr_node_ids; i++) -+ if (build_numa_sched_groups(&d, cpu_map, i)) -+ goto error; -+#endif -+ -+ /* Calculate CPU power for physical packages and nodes */ -+#ifdef CONFIG_SCHED_SMT -+ for_each_cpu(i, cpu_map) { -+ sd = &per_cpu(cpu_domains, i).sd; -+ init_sched_groups_power(i, sd); -+ } -+#endif -+#ifdef CONFIG_SCHED_MC -+ for_each_cpu(i, cpu_map) { -+ sd = &per_cpu(core_domains, i).sd; -+ init_sched_groups_power(i, sd); -+ } -+#endif -+#ifdef CONFIG_SCHED_BOOK -+ for_each_cpu(i, cpu_map) { -+ sd = &per_cpu(book_domains, i).sd; -+ init_sched_groups_power(i, sd); -+ } -+#endif -+ -+ for_each_cpu(i, cpu_map) { -+ sd = &per_cpu(phys_domains, i).sd; -+ init_sched_groups_power(i, sd); -+ } -+ -+#ifdef CONFIG_NUMA -+ for (i = 0; i < nr_node_ids; i++) -+ init_numa_sched_groups_power(d.sched_group_nodes[i]); -+ -+ if (d.sd_allnodes) { -+ struct sched_group *sg; -+ -+ cpu_to_allnodes_group(cpumask_first(cpu_map), cpu_map, &sg, -+ d.tmpmask); -+ init_numa_sched_groups_power(sg); -+ } -+#endif -+ -+ /* Attach the domains */ -+ for_each_cpu(i, cpu_map) { -+#ifdef CONFIG_SCHED_SMT -+ sd = &per_cpu(cpu_domains, i).sd; -+#elif defined(CONFIG_SCHED_MC) -+ sd = &per_cpu(core_domains, i).sd; -+#elif defined(CONFIG_SCHED_BOOK) -+ sd = &per_cpu(book_domains, i).sd; -+#else -+ sd = &per_cpu(phys_domains, i).sd; -+#endif -+ cpu_attach_domain(sd, d.rd, i); -+ } -+ -+ d.sched_group_nodes = NULL; /* don't free this we still need it */ -+ __free_domain_allocs(&d, sa_tmpmask, cpu_map); -+ return 0; -+ -+error: -+ __free_domain_allocs(&d, alloc_state, cpu_map); -+ return -ENOMEM; -+} -+ -+static int build_sched_domains(const struct cpumask *cpu_map) -+{ -+ return __build_sched_domains(cpu_map, NULL); -+} -+ -+static cpumask_var_t *doms_cur; /* current sched domains */ -+static int ndoms_cur; /* number of sched domains in 'doms_cur' */ -+static struct sched_domain_attr *dattr_cur; -+ /* attribues of custom domains in 'doms_cur' */ -+ -+/* -+ * Special case: If a kmalloc of a doms_cur partition (array of -+ * cpumask) fails, then fallback to a single sched domain, -+ * as determined by the single cpumask fallback_doms. -+ */ -+static cpumask_var_t fallback_doms; -+ -+/* -+ * arch_update_cpu_topology lets virtualised architectures update the -+ * cpu core maps. It is supposed to return 1 if the topology changed -+ * or 0 if it stayed the same. -+ */ -+int __attribute__((weak)) arch_update_cpu_topology(void) -+{ -+ return 0; -+} -+ -+cpumask_var_t *alloc_sched_domains(unsigned int ndoms) -+{ -+ int i; -+ cpumask_var_t *doms; -+ -+ doms = kmalloc(sizeof(*doms) * ndoms, GFP_KERNEL); -+ if (!doms) -+ return NULL; -+ for (i = 0; i < ndoms; i++) { -+ if (!alloc_cpumask_var(&doms[i], GFP_KERNEL)) { -+ free_sched_domains(doms, i); -+ return NULL; -+ } -+ } -+ return doms; -+} -+ -+void free_sched_domains(cpumask_var_t doms[], unsigned int ndoms) -+{ -+ unsigned int i; -+ for (i = 0; i < ndoms; i++) -+ free_cpumask_var(doms[i]); -+ kfree(doms); -+} -+ -+/* -+ * Set up scheduler domains and groups. Callers must hold the hotplug lock. -+ * For now this just excludes isolated cpus, but could be used to -+ * exclude other special cases in the future. -+ */ -+static int arch_init_sched_domains(const struct cpumask *cpu_map) -+{ -+ int err; -+ -+ arch_update_cpu_topology(); -+ ndoms_cur = 1; -+ doms_cur = alloc_sched_domains(ndoms_cur); -+ if (!doms_cur) -+ doms_cur = &fallback_doms; -+ cpumask_andnot(doms_cur[0], cpu_map, cpu_isolated_map); -+ dattr_cur = NULL; -+ err = build_sched_domains(doms_cur[0]); -+ register_sched_domain_sysctl(); -+ -+ return err; -+} -+ -+static void arch_destroy_sched_domains(const struct cpumask *cpu_map, -+ struct cpumask *tmpmask) -+{ -+ free_sched_groups(cpu_map, tmpmask); -+} -+ -+/* -+ * Detach sched domains from a group of cpus specified in cpu_map -+ * These cpus will now be attached to the NULL domain -+ */ -+static void detach_destroy_domains(const struct cpumask *cpu_map) -+{ -+ /* Save because hotplug lock held. */ -+ static DECLARE_BITMAP(tmpmask, CONFIG_NR_CPUS); -+ int i; -+ -+ for_each_cpu(i, cpu_map) -+ cpu_attach_domain(NULL, &def_root_domain, i); -+ synchronize_sched(); -+ arch_destroy_sched_domains(cpu_map, to_cpumask(tmpmask)); -+} -+ -+/* handle null as "default" */ -+static int dattrs_equal(struct sched_domain_attr *cur, int idx_cur, -+ struct sched_domain_attr *new, int idx_new) -+{ -+ struct sched_domain_attr tmp; -+ -+ /* fast path */ -+ if (!new && !cur) -+ return 1; -+ -+ tmp = SD_ATTR_INIT; -+ return !memcmp(cur ? (cur + idx_cur) : &tmp, -+ new ? (new + idx_new) : &tmp, -+ sizeof(struct sched_domain_attr)); -+} -+ -+/* -+ * Partition sched domains as specified by the 'ndoms_new' -+ * cpumasks in the array doms_new[] of cpumasks. This compares -+ * doms_new[] to the current sched domain partitioning, doms_cur[]. -+ * It destroys each deleted domain and builds each new domain. -+ * -+ * 'doms_new' is an array of cpumask_var_t's of length 'ndoms_new'. -+ * The masks don't intersect (don't overlap.) We should setup one -+ * sched domain for each mask. CPUs not in any of the cpumasks will -+ * not be load balanced. If the same cpumask appears both in the -+ * current 'doms_cur' domains and in the new 'doms_new', we can leave -+ * it as it is. -+ * -+ * The passed in 'doms_new' should be allocated using -+ * alloc_sched_domains. This routine takes ownership of it and will -+ * free_sched_domains it when done with it. If the caller failed the -+ * alloc call, then it can pass in doms_new == NULL && ndoms_new == 1, -+ * and partition_sched_domains() will fallback to the single partition -+ * 'fallback_doms', it also forces the domains to be rebuilt. -+ * -+ * If doms_new == NULL it will be replaced with cpu_online_mask. -+ * ndoms_new == 0 is a special case for destroying existing domains, -+ * and it will not create the default domain. -+ * -+ * Call with hotplug lock held -+ */ -+void partition_sched_domains(int ndoms_new, cpumask_var_t doms_new[], -+ struct sched_domain_attr *dattr_new) -+{ -+ int i, j, n; -+ int new_topology; -+ -+ mutex_lock(&sched_domains_mutex); -+ -+ /* always unregister in case we don't destroy any domains */ -+ unregister_sched_domain_sysctl(); -+ -+ /* Let architecture update cpu core mappings. */ -+ new_topology = arch_update_cpu_topology(); -+ -+ n = doms_new ? ndoms_new : 0; -+ -+ /* Destroy deleted domains */ -+ for (i = 0; i < ndoms_cur; i++) { -+ for (j = 0; j < n && !new_topology; j++) { -+ if (cpumask_equal(doms_cur[i], doms_new[j]) -+ && dattrs_equal(dattr_cur, i, dattr_new, j)) -+ goto match1; -+ } -+ /* no match - a current sched domain not in new doms_new[] */ -+ detach_destroy_domains(doms_cur[i]); -+match1: -+ ; -+ } -+ -+ if (doms_new == NULL) { -+ ndoms_cur = 0; -+ doms_new = &fallback_doms; -+ cpumask_andnot(doms_new[0], cpu_active_mask, cpu_isolated_map); -+ WARN_ON_ONCE(dattr_new); -+ } -+ -+ /* Build new domains */ -+ for (i = 0; i < ndoms_new; i++) { -+ for (j = 0; j < ndoms_cur && !new_topology; j++) { -+ if (cpumask_equal(doms_new[i], doms_cur[j]) -+ && dattrs_equal(dattr_new, i, dattr_cur, j)) -+ goto match2; -+ } -+ /* no match - add a new doms_new */ -+ __build_sched_domains(doms_new[i], -+ dattr_new ? dattr_new + i : NULL); -+match2: -+ ; -+ } -+ -+ /* Remember the new sched domains */ -+ if (doms_cur != &fallback_doms) -+ free_sched_domains(doms_cur, ndoms_cur); -+ kfree(dattr_cur); /* kfree(NULL) is safe */ -+ doms_cur = doms_new; -+ dattr_cur = dattr_new; -+ ndoms_cur = ndoms_new; -+ -+ register_sched_domain_sysctl(); -+ -+ mutex_unlock(&sched_domains_mutex); -+} -+ -+#if defined(CONFIG_SCHED_MC) || defined(CONFIG_SCHED_SMT) -+static void arch_reinit_sched_domains(void) -+{ -+ get_online_cpus(); -+ -+ /* Destroy domains first to force the rebuild */ -+ partition_sched_domains(0, NULL, NULL); -+ -+ rebuild_sched_domains(); -+ put_online_cpus(); -+} -+ -+static ssize_t sched_power_savings_store(const char *buf, size_t count, int smt) -+{ -+ unsigned int level = 0; -+ -+ if (sscanf(buf, "%u", &level) != 1) -+ return -EINVAL; -+ -+ /* -+ * level is always be positive so don't check for -+ * level < POWERSAVINGS_BALANCE_NONE which is 0 -+ * What happens on 0 or 1 byte write, -+ * need to check for count as well? -+ */ -+ -+ if (level >= MAX_POWERSAVINGS_BALANCE_LEVELS) -+ return -EINVAL; -+ -+ if (smt) -+ sched_smt_power_savings = level; -+ else -+ sched_mc_power_savings = level; -+ -+ arch_reinit_sched_domains(); -+ -+ return count; -+} -+ -+#ifdef CONFIG_SCHED_MC -+static ssize_t sched_mc_power_savings_show(struct sysdev_class *class, -+ struct sysdev_class_attribute *attr, -+ char *page) -+{ -+ return sprintf(page, "%u\n", sched_mc_power_savings); -+} -+static ssize_t sched_mc_power_savings_store(struct sysdev_class *class, -+ struct sysdev_class_attribute *attr, -+ const char *buf, size_t count) -+{ -+ return sched_power_savings_store(buf, count, 0); -+} -+static SYSDEV_CLASS_ATTR(sched_mc_power_savings, 0644, -+ sched_mc_power_savings_show, -+ sched_mc_power_savings_store); -+#endif -+ -+#ifdef CONFIG_SCHED_SMT -+static ssize_t sched_smt_power_savings_show(struct sysdev_class *dev, -+ struct sysdev_class_attribute *attr, -+ char *page) -+{ -+ return sprintf(page, "%u\n", sched_smt_power_savings); -+} -+static ssize_t sched_smt_power_savings_store(struct sysdev_class *dev, -+ struct sysdev_class_attribute *attr, -+ const char *buf, size_t count) -+{ -+ return sched_power_savings_store(buf, count, 1); -+} -+static SYSDEV_CLASS_ATTR(sched_smt_power_savings, 0644, -+ sched_smt_power_savings_show, -+ sched_smt_power_savings_store); -+#endif -+ -+int __init sched_create_sysfs_power_savings_entries(struct sysdev_class *cls) -+{ -+ int err = 0; -+ -+#ifdef CONFIG_SCHED_SMT -+ if (smt_capable()) -+ err = sysfs_create_file(&cls->kset.kobj, -+ &attr_sched_smt_power_savings.attr); -+#endif -+#ifdef CONFIG_SCHED_MC -+ if (!err && mc_capable()) -+ err = sysfs_create_file(&cls->kset.kobj, -+ &attr_sched_mc_power_savings.attr); -+#endif -+ return err; -+} -+#endif /* CONFIG_SCHED_MC || CONFIG_SCHED_SMT */ -+ -+/* -+ * Update cpusets according to cpu_active mask. If cpusets are -+ * disabled, cpuset_update_active_cpus() becomes a simple wrapper -+ * around partition_sched_domains(). -+ */ -+static int cpuset_cpu_active(struct notifier_block *nfb, unsigned long action, -+ void *hcpu) -+{ -+ switch (action & ~CPU_TASKS_FROZEN) { -+ case CPU_ONLINE: -+ case CPU_DOWN_FAILED: -+ cpuset_update_active_cpus(); -+ return NOTIFY_OK; -+ default: -+ return NOTIFY_DONE; -+ } -+} -+ -+static int cpuset_cpu_inactive(struct notifier_block *nfb, unsigned long action, -+ void *hcpu) -+{ -+ switch (action & ~CPU_TASKS_FROZEN) { -+ case CPU_DOWN_PREPARE: -+ cpuset_update_active_cpus(); -+ return NOTIFY_OK; -+ default: -+ return NOTIFY_DONE; -+ } -+} -+ -+static int update_runtime(struct notifier_block *nfb, -+ unsigned long action, void *hcpu) -+{ -+ switch (action) { -+ case CPU_DOWN_PREPARE: -+ case CPU_DOWN_PREPARE_FROZEN: -+ return NOTIFY_OK; -+ -+ case CPU_DOWN_FAILED: -+ case CPU_DOWN_FAILED_FROZEN: -+ case CPU_ONLINE: -+ case CPU_ONLINE_FROZEN: -+ return NOTIFY_OK; -+ -+ default: -+ return NOTIFY_DONE; -+ } -+} -+ -+#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) -+/* -+ * Cheaper version of the below functions in case support for SMT and MC is -+ * compiled in but CPUs have no siblings. -+ */ -+static int sole_cpu_idle(unsigned long cpu) -+{ -+ return rq_idle(cpu_rq(cpu)); -+} -+#endif -+#ifdef CONFIG_SCHED_SMT -+/* All this CPU's SMT siblings are idle */ -+static int siblings_cpu_idle(unsigned long cpu) -+{ -+ return cpumask_subset(&(cpu_rq(cpu)->smt_siblings), -+ &grq.cpu_idle_map); -+} -+#endif -+#ifdef CONFIG_SCHED_MC -+/* All this CPU's shared cache siblings are idle */ -+static int cache_cpu_idle(unsigned long cpu) -+{ -+ return cpumask_subset(&(cpu_rq(cpu)->cache_siblings), -+ &grq.cpu_idle_map); -+} -+#endif -+ -+void __init sched_init_smp(void) -+{ -+ struct sched_domain *sd; -+ int cpu, cpus; -+ -+ cpumask_var_t non_isolated_cpus; -+ -+ alloc_cpumask_var(&non_isolated_cpus, GFP_KERNEL); -+ alloc_cpumask_var(&fallback_doms, GFP_KERNEL); -+ -+#if defined(CONFIG_NUMA) -+ sched_group_nodes_bycpu = kzalloc(nr_cpu_ids * sizeof(void **), -+ GFP_KERNEL); -+ BUG_ON(sched_group_nodes_bycpu == NULL); -+#endif -+ get_online_cpus(); -+ mutex_lock(&sched_domains_mutex); -+ arch_init_sched_domains(cpu_active_mask); -+ cpumask_andnot(non_isolated_cpus, cpu_possible_mask, cpu_isolated_map); -+ if (cpumask_empty(non_isolated_cpus)) -+ cpumask_set_cpu(smp_processor_id(), non_isolated_cpus); -+ mutex_unlock(&sched_domains_mutex); -+ put_online_cpus(); -+ -+ hotcpu_notifier(cpuset_cpu_active, CPU_PRI_CPUSET_ACTIVE); -+ hotcpu_notifier(cpuset_cpu_inactive, CPU_PRI_CPUSET_INACTIVE); -+ -+ /* RT runtime code needs to handle some hotplug events */ -+ hotcpu_notifier(update_runtime, 0); -+ -+ /* Move init over to a non-isolated CPU */ -+ if (set_cpus_allowed_ptr(current, non_isolated_cpus) < 0) -+ BUG(); -+ free_cpumask_var(non_isolated_cpus); -+ -+ /* -+ * Assume that every added cpu gives us slightly less overall latency -+ * allowing us to increase the base rr_interval, non-linearly and with -+ * an upper bound. -+ */ -+ cpus = num_online_cpus(); -+ rr_interval = rr_interval * (4 * cpus + 4) / (cpus + 6); -+ -+ grq_lock_irq(); -+ /* -+ * Set up the relative cache distance of each online cpu from each -+ * other in a simple array for quick lookup. Locality is determined -+ * by the closest sched_domain that CPUs are separated by. CPUs with -+ * shared cache in SMT and MC are treated as local. Separate CPUs -+ * (within the same package or physically) within the same node are -+ * treated as not local. CPUs not even in the same domain (different -+ * nodes) are treated as very distant. -+ */ -+ for_each_online_cpu(cpu) { -+ struct rq *rq = cpu_rq(cpu); -+ for_each_domain(cpu, sd) { -+ unsigned long locality; -+ int other_cpu; -+ -+#ifdef CONFIG_SCHED_SMT -+ if (sd->level == SD_LV_SIBLING) { -+ for_each_cpu_mask(other_cpu, *sched_domain_span(sd)) -+ cpumask_set_cpu(other_cpu, &rq->smt_siblings); -+ } -+#endif -+#ifdef CONFIG_SCHED_MC -+ if (sd->level == SD_LV_MC) { -+ for_each_cpu_mask(other_cpu, *sched_domain_span(sd)) -+ cpumask_set_cpu(other_cpu, &rq->cache_siblings); -+ } -+#endif -+ if (sd->level <= SD_LV_SIBLING) -+ locality = 1; -+ else if (sd->level <= SD_LV_MC) -+ locality = 2; -+ else if (sd->level <= SD_LV_NODE) -+ locality = 3; -+ else -+ continue; -+ -+ for_each_cpu_mask(other_cpu, *sched_domain_span(sd)) { -+ if (locality < rq->cpu_locality[other_cpu]) -+ rq->cpu_locality[other_cpu] = locality; -+ } -+ } -+ -+/* -+ * Each runqueue has its own function in case it doesn't have -+ * siblings of its own allowing mixed topologies. -+ */ -+#ifdef CONFIG_SCHED_SMT -+ if (cpus_weight(rq->smt_siblings) > 1) -+ rq->siblings_idle = siblings_cpu_idle; -+#endif -+#ifdef CONFIG_SCHED_MC -+ if (cpus_weight(rq->cache_siblings) > 1) -+ rq->cache_idle = cache_cpu_idle; -+#endif -+ } -+ grq_unlock_irq(); -+} -+#else -+void __init sched_init_smp(void) -+{ -+} -+#endif /* CONFIG_SMP */ -+ -+unsigned int sysctl_timer_migration = 1; -+ -+int in_sched_functions(unsigned long addr) -+{ -+ return in_lock_functions(addr) || -+ (addr >= (unsigned long)__sched_text_start -+ && addr < (unsigned long)__sched_text_end); -+} -+ -+void __init sched_init(void) -+{ -+ int i; -+ struct rq *rq; -+ -+ prio_ratios[0] = 128; -+ for (i = 1 ; i < PRIO_RANGE ; i++) -+ prio_ratios[i] = prio_ratios[i - 1] * 11 / 10; -+ -+ raw_spin_lock_init(&grq.lock); -+ grq.nr_running = grq.nr_uninterruptible = grq.nr_switches = 0; -+ grq.niffies = 0; -+ grq.last_jiffy = jiffies; -+ raw_spin_lock_init(&grq.iso_lock); -+ grq.iso_ticks = grq.iso_refractory = 0; -+#ifdef CONFIG_SMP -+ init_defrootdomain(); -+ grq.qnr = grq.idle_cpus = 0; -+ cpumask_clear(&grq.cpu_idle_map); -+#else -+ uprq = &per_cpu(runqueues, 0); -+#endif -+ for_each_possible_cpu(i) { -+ rq = cpu_rq(i); -+ rq->user_pc = rq->nice_pc = rq->softirq_pc = rq->system_pc = -+ rq->iowait_pc = rq->idle_pc = 0; -+ rq->dither = 0; -+#ifdef CONFIG_SMP -+ rq->last_niffy = 0; -+ rq->sd = NULL; -+ rq->rd = NULL; -+ rq->online = 0; -+ rq->cpu = i; -+ rq_attach_root(rq, &def_root_domain); -+#endif -+ atomic_set(&rq->nr_iowait, 0); -+ } -+ -+#ifdef CONFIG_SMP -+ nr_cpu_ids = i; -+ /* -+ * Set the base locality for cpu cache distance calculation to -+ * "distant" (3). Make sure the distance from a CPU to itself is 0. -+ */ -+ for_each_possible_cpu(i) { -+ int j; -+ -+ rq = cpu_rq(i); -+#ifdef CONFIG_SCHED_SMT -+ cpumask_clear(&rq->smt_siblings); -+ cpumask_set_cpu(i, &rq->smt_siblings); -+ rq->siblings_idle = sole_cpu_idle; -+ cpumask_set_cpu(i, &rq->smt_siblings); -+#endif -+#ifdef CONFIG_SCHED_MC -+ cpumask_clear(&rq->cache_siblings); -+ cpumask_set_cpu(i, &rq->cache_siblings); -+ rq->cache_idle = sole_cpu_idle; -+ cpumask_set_cpu(i, &rq->cache_siblings); -+#endif -+ rq->cpu_locality = kmalloc(nr_cpu_ids * sizeof(unsigned long), -+ GFP_NOWAIT); -+ for_each_possible_cpu(j) { -+ if (i == j) -+ rq->cpu_locality[j] = 0; -+ else -+ rq->cpu_locality[j] = 4; -+ } -+ } -+#endif -+ -+ for (i = 0; i < PRIO_LIMIT; i++) -+ INIT_LIST_HEAD(grq.queue + i); -+ /* delimiter for bitsearch */ -+ __set_bit(PRIO_LIMIT, grq.prio_bitmap); -+ -+#ifdef CONFIG_PREEMPT_NOTIFIERS -+ INIT_HLIST_HEAD(&init_task.preempt_notifiers); -+#endif -+ -+#ifdef CONFIG_RT_MUTEXES -+ plist_head_init_raw(&init_task.pi_waiters, &init_task.pi_lock); -+#endif -+ -+ /* -+ * The boot idle thread does lazy MMU switching as well: -+ */ -+ atomic_inc(&init_mm.mm_count); -+ enter_lazy_tlb(&init_mm, current); -+ -+ /* -+ * Make us the idle thread. Technically, schedule() should not be -+ * called from this thread, however somewhere below it might be, -+ * but because we are the idle thread, we just pick up running again -+ * when this runqueue becomes "idle". -+ */ -+ init_idle(current, smp_processor_id()); -+ -+ /* Allocate the nohz_cpu_mask if CONFIG_CPUMASK_OFFSTACK */ -+ zalloc_cpumask_var(&nohz_cpu_mask, GFP_NOWAIT); -+#ifdef CONFIG_SMP -+ /* May be allocated at isolcpus cmdline parse time */ -+ if (cpu_isolated_map == NULL) -+ zalloc_cpumask_var(&cpu_isolated_map, GFP_NOWAIT); -+#endif /* SMP */ -+ perf_event_init(); -+} -+ -+#ifdef CONFIG_DEBUG_SPINLOCK_SLEEP -+static inline int preempt_count_equals(int preempt_offset) -+{ -+ int nested = (preempt_count() & ~PREEMPT_ACTIVE) + rcu_preempt_depth(); -+ -+ return (nested == PREEMPT_INATOMIC_BASE + preempt_offset); -+} -+ -+void __might_sleep(const char *file, int line, int preempt_offset) -+{ -+#ifdef in_atomic -+ static unsigned long prev_jiffy; /* ratelimiting */ -+ -+ if ((preempt_count_equals(preempt_offset) && !irqs_disabled()) || -+ system_state != SYSTEM_RUNNING || oops_in_progress) -+ return; -+ if (time_before(jiffies, prev_jiffy + HZ) && prev_jiffy) -+ return; -+ prev_jiffy = jiffies; -+ -+ printk(KERN_ERR -+ "BUG: sleeping function called from invalid context at %s:%d\n", -+ file, line); -+ printk(KERN_ERR -+ "in_atomic(): %d, irqs_disabled(): %d, pid: %d, name: %s\n", -+ in_atomic(), irqs_disabled(), -+ current->pid, current->comm); -+ -+ debug_show_held_locks(current); -+ if (irqs_disabled()) -+ print_irqtrace_events(current); -+ dump_stack(); -+#endif -+} -+EXPORT_SYMBOL(__might_sleep); -+#endif -+ -+#ifdef CONFIG_MAGIC_SYSRQ -+void normalize_rt_tasks(void) -+{ -+ struct task_struct *g, *p; -+ unsigned long flags; -+ struct rq *rq; -+ int queued; -+ -+ read_lock_irq(&tasklist_lock); -+ -+ do_each_thread(g, p) { -+ if (!rt_task(p) && !iso_task(p)) -+ continue; -+ -+ raw_spin_lock_irqsave(&p->pi_lock, flags); -+ rq = __task_grq_lock(p); -+ -+ queued = task_queued(p); -+ if (queued) -+ dequeue_task(p); -+ __setscheduler(p, rq, SCHED_NORMAL, 0); -+ if (queued) { -+ enqueue_task(p); -+ try_preempt(p, rq); -+ } -+ -+ __task_grq_unlock(); -+ raw_spin_unlock_irqrestore(&p->pi_lock, flags); -+ } while_each_thread(g, p); -+ -+ read_unlock_irq(&tasklist_lock); -+} -+#endif /* CONFIG_MAGIC_SYSRQ */ -+ -+#if defined(CONFIG_IA64) || defined(CONFIG_KGDB_KDB) -+/* -+ * These functions are only useful for the IA64 MCA handling, or kdb. -+ * -+ * They can only be called when the whole system has been -+ * stopped - every CPU needs to be quiescent, and no scheduling -+ * activity can take place. Using them for anything else would -+ * be a serious bug, and as a result, they aren't even visible -+ * under any other configuration. -+ */ -+ -+/** -+ * curr_task - return the current task for a given cpu. -+ * @cpu: the processor in question. -+ * -+ * ONLY VALID WHEN THE WHOLE SYSTEM IS STOPPED! -+ */ -+struct task_struct *curr_task(int cpu) -+{ -+ return cpu_curr(cpu); -+} -+ -+#endif /* defined(CONFIG_IA64) || defined(CONFIG_KGDB_KDB) */ -+ -+#ifdef CONFIG_IA64 -+/** -+ * set_curr_task - set the current task for a given cpu. -+ * @cpu: the processor in question. -+ * @p: the task pointer to set. -+ * -+ * Description: This function must only be used when non-maskable interrupts -+ * are serviced on a separate stack. It allows the architecture to switch the -+ * notion of the current task on a cpu in a non-blocking manner. This function -+ * must be called with all CPU's synchronised, and interrupts disabled, the -+ * and caller must save the original value of the current task (see -+ * curr_task() above) and restore that value before reenabling interrupts and -+ * re-starting the system. -+ * -+ * ONLY VALID WHEN THE WHOLE SYSTEM IS STOPPED! -+ */ -+void set_curr_task(int cpu, struct task_struct *p) -+{ -+ cpu_curr(cpu) = p; -+} -+ -+#endif -+ -+/* -+ * Use precise platform statistics if available: -+ */ -+#ifdef CONFIG_VIRT_CPU_ACCOUNTING -+void task_times(struct task_struct *p, cputime_t *ut, cputime_t *st) -+{ -+ *ut = p->utime; -+ *st = p->stime; -+} -+ -+void thread_group_times(struct task_struct *p, cputime_t *ut, cputime_t *st) -+{ -+ struct task_cputime cputime; -+ -+ thread_group_cputime(p, &cputime); -+ -+ *ut = cputime.utime; -+ *st = cputime.stime; -+} -+#else -+ -+#ifndef nsecs_to_cputime -+# define nsecs_to_cputime(__nsecs) nsecs_to_jiffies(__nsecs) -+#endif -+ -+void task_times(struct task_struct *p, cputime_t *ut, cputime_t *st) -+{ -+ cputime_t rtime, utime = p->utime, total = cputime_add(utime, p->stime); -+ -+ rtime = nsecs_to_cputime(p->sched_time); -+ -+ if (total) { -+ u64 temp; -+ -+ temp = (u64)(rtime * utime); -+ do_div(temp, total); -+ utime = (cputime_t)temp; -+ } else -+ utime = rtime; -+ -+ /* -+ * Compare with previous values, to keep monotonicity: -+ */ -+ p->prev_utime = max(p->prev_utime, utime); -+ p->prev_stime = max(p->prev_stime, cputime_sub(rtime, p->prev_utime)); -+ -+ *ut = p->prev_utime; -+ *st = p->prev_stime; -+} -+ -+/* -+ * Must be called with siglock held. -+ */ -+void thread_group_times(struct task_struct *p, cputime_t *ut, cputime_t *st) -+{ -+ struct signal_struct *sig = p->signal; -+ struct task_cputime cputime; -+ cputime_t rtime, utime, total; -+ -+ thread_group_cputime(p, &cputime); -+ -+ total = cputime_add(cputime.utime, cputime.stime); -+ rtime = nsecs_to_cputime(cputime.sum_exec_runtime); -+ -+ if (total) { -+ u64 temp; -+ -+ temp = (u64)(rtime * cputime.utime); -+ do_div(temp, total); -+ utime = (cputime_t)temp; -+ } else -+ utime = rtime; -+ -+ sig->prev_utime = max(sig->prev_utime, utime); -+ sig->prev_stime = max(sig->prev_stime, -+ cputime_sub(rtime, sig->prev_utime)); -+ -+ *ut = sig->prev_utime; -+ *st = sig->prev_stime; -+} -+#endif -+ -+inline cputime_t task_gtime(struct task_struct *p) -+{ -+ return p->gtime; -+} -+ -+void __cpuinit init_idle_bootup_task(struct task_struct *idle) -+{} -+ -+#ifdef CONFIG_SCHED_DEBUG -+void proc_sched_show_task(struct task_struct *p, struct seq_file *m) -+{} -+ -+void proc_sched_set_task(struct task_struct *p) -+{} -+#endif -+ -+/* No RCU torture test support */ -+void synchronize_sched_expedited(void) -+{ -+ barrier(); -+} -+EXPORT_SYMBOL_GPL(synchronize_sched_expedited); -+ -+#ifdef CONFIG_SMP -+unsigned long default_scale_freq_power(struct sched_domain *sd, int cpu) -+{ -+ return SCHED_LOAD_SCALE; -+} -+ -+unsigned long default_scale_smt_power(struct sched_domain *sd, int cpu) -+{ -+ unsigned long weight = cpumask_weight(sched_domain_span(sd)); -+ unsigned long smt_gain = sd->smt_gain; -+ -+ smt_gain /= weight; -+ -+ return smt_gain; -+} -+#endif -Index: linux-2.6.37-ck2/kernel/sched.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/sched.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/kernel/sched.c 2011-02-14 09:47:50.994252001 +1100 -@@ -1,3 +1,6 @@ -+#ifdef CONFIG_SCHED_BFS -+#include "sched_bfs.c" -+#else - /* - * kernel/sched.c - * -@@ -9603,3 +9606,4 @@ - EXPORT_SYMBOL_GPL(synchronize_sched_expedited); - - #endif /* #else #ifndef CONFIG_SMP */ -+#endif /* CONFIG_SCHED_BFS */ -Index: linux-2.6.37-ck2/kernel/sysctl.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/sysctl.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/kernel/sysctl.c 2011-02-14 09:47:50.995252001 +1100 -@@ -117,7 +117,12 @@ - static int __maybe_unused one = 1; - static int __maybe_unused two = 2; - static unsigned long one_ul = 1; --static int one_hundred = 100; -+static int __maybe_unused one_hundred = 100; -+#ifdef CONFIG_SCHED_BFS -+extern int rr_interval; -+extern int sched_iso_cpu; -+static int __read_mostly one_thousand = 1000; -+#endif - #ifdef CONFIG_PRINTK - static int ten_thousand = 10000; - #endif -@@ -252,7 +257,7 @@ - { } - }; - --#ifdef CONFIG_SCHED_DEBUG -+#if defined(CONFIG_SCHED_DEBUG) && !defined(CONFIG_SCHED_BFS) - static int min_sched_granularity_ns = 100000; /* 100 usecs */ - static int max_sched_granularity_ns = NSEC_PER_SEC; /* 1 second */ - static int min_wakeup_granularity_ns; /* 0 usecs */ -@@ -269,6 +274,7 @@ - #endif - - static struct ctl_table kern_table[] = { -+#ifndef CONFIG_SCHED_BFS - { - .procname = "sched_child_runs_first", - .data = &sysctl_sched_child_runs_first, -@@ -382,6 +388,7 @@ - .mode = 0644, - .proc_handler = proc_dointvec, - }, -+#endif /* !CONFIG_SCHED_BFS */ - #ifdef CONFIG_PROVE_LOCKING - { - .procname = "prove_locking", -@@ -815,6 +822,26 @@ - .proc_handler = proc_dointvec, - }, - #endif -+#ifdef CONFIG_SCHED_BFS -+ { -+ .procname = "rr_interval", -+ .data = &rr_interval, -+ .maxlen = sizeof (int), -+ .mode = 0644, -+ .proc_handler = &proc_dointvec_minmax, -+ .extra1 = &one, -+ .extra2 = &one_thousand, -+ }, -+ { -+ .procname = "iso_cpu", -+ .data = &sched_iso_cpu, -+ .maxlen = sizeof (int), -+ .mode = 0644, -+ .proc_handler = &proc_dointvec_minmax, -+ .extra1 = &zero, -+ .extra2 = &one_hundred, -+ }, -+#endif - #if defined(CONFIG_S390) && defined(CONFIG_SMP) - { - .procname = "spin_retry", -Index: linux-2.6.37-ck2/lib/Kconfig.debug -=================================================================== ---- linux-2.6.37-ck2.orig/lib/Kconfig.debug 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/lib/Kconfig.debug 2011-02-14 09:47:50.995252001 +1100 -@@ -833,7 +833,7 @@ - - config RCU_TORTURE_TEST - tristate "torture tests for RCU" -- depends on DEBUG_KERNEL -+ depends on DEBUG_KERNEL && !SCHED_BFS - default n - help - This option provides a kernel module that runs torture tests -Index: linux-2.6.37-ck2/include/linux/jiffies.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/jiffies.h 2010-02-25 21:51:52.000000000 +1100 -+++ linux-2.6.37-ck2/include/linux/jiffies.h 2011-02-14 09:47:50.995252001 +1100 -@@ -164,7 +164,7 @@ - * Have the 32 bit jiffies value wrap 5 minutes after boot - * so jiffies wrap bugs show up earlier. - */ --#define INITIAL_JIFFIES ((unsigned long)(unsigned int) (-300*HZ)) -+#define INITIAL_JIFFIES ((unsigned long)(unsigned int) (-10*HZ)) - - /* - * Change timeval to jiffies, trying to avoid the diff --git a/packages/linux/patches/linux-2.6.38-rc7-702_2637-bfs363-nonhotplug_fix.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-702_2637-bfs363-nonhotplug_fix.patch.disabled deleted file mode 100644 index 59b401dea6..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-702_2637-bfs363-nonhotplug_fix.patch.disabled +++ /dev/null @@ -1,60 +0,0 @@ -Fix a failure to build if CPU hotplug is disabled with BFS. - --ck - ---- - kernel/sched_bfs.c | 34 +++++++++++++++++----------------- - 1 file changed, 17 insertions(+), 17 deletions(-) - -Index: linux-2.6.37-ck2/kernel/sched_bfs.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/sched_bfs.c 2011-02-14 09:50:24.351252002 +1100 -+++ linux-2.6.37-ck2/kernel/sched_bfs.c 2011-02-14 09:53:53.820252000 +1100 -@@ -4812,6 +4812,23 @@ - grq_unlock_irqrestore(&flags); - } - -+/* -+ * Ensures that the idle task is using init_mm right before its cpu goes -+ * offline. -+ */ -+void idle_task_exit(void) -+{ -+ struct mm_struct *mm = current->active_mm; -+ -+ BUG_ON(cpu_online(smp_processor_id())); -+ -+ if (mm != &init_mm) -+ switch_mm(mm, &init_mm, current); -+ mmdrop(mm); -+} -+ -+#endif /* CONFIG_HOTPLUG_CPU */ -+ - void sched_set_stop_task(int cpu, struct task_struct *stop) - { - struct sched_param stop_param = { .sched_priority = STOP_PRIO }; -@@ -4841,23 +4858,6 @@ - } - } - --/* -- * Ensures that the idle task is using init_mm right before its cpu goes -- * offline. -- */ --void idle_task_exit(void) --{ -- struct mm_struct *mm = current->active_mm; -- -- BUG_ON(cpu_online(smp_processor_id())); -- -- if (mm != &init_mm) -- switch_mm(mm, &init_mm, current); -- mmdrop(mm); --} -- --#endif /* CONFIG_HOTPLUG_CPU */ -- - #if defined(CONFIG_SCHED_DEBUG) && defined(CONFIG_SYSCTL) - - static struct ctl_table sd_ctl_dir[] = { diff --git a/packages/linux/patches/linux-2.6.38-rc7-702_ck2-version.patch b/packages/linux/patches/linux-2.6.38-rc7-702_ck2-version.patch deleted file mode 100644 index 4f34a3ebed..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-702_ck2-version.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- - Makefile | 4 ++++ - 1 file changed, 4 insertions(+) - -Index: linux-2.6.37-ck2/Makefile -=================================================================== ---- linux-2.6.37-ck2.orig/Makefile 2011-01-06 14:04:07.000000000 +1100 -+++ linux-2.6.37-ck2/Makefile 2011-02-14 10:11:20.469252000 +1100 -@@ -10,6 +10,10 @@ - # Comments in this file are targeted only to the developer, do not - # expect to learn how to build the kernel reading this file. - -+CKVERSION = -ck2 -+CKNAME = BFS Powered -+EXTRAVERSION := $(EXTRAVERSION)$(CKVERSION) -+ - # Do not: - # o use make's built-in rules and variables - # (this increases performance and avoids hard-to-debug behaviour); diff --git a/packages/linux/patches/linux-2.6.38-rc7-703_cpufreq-bfs_tweaks.patch b/packages/linux/patches/linux-2.6.38-rc7-703_cpufreq-bfs_tweaks.patch deleted file mode 100644 index fc0122e323..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-703_cpufreq-bfs_tweaks.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- - drivers/cpufreq/cpufreq_ondemand.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -Index: linux-2.6.37-ck2/drivers/cpufreq/cpufreq_ondemand.c -=================================================================== ---- linux-2.6.37-ck2.orig/drivers/cpufreq/cpufreq_ondemand.c 2011-01-06 14:04:08.000000000 +1100 -+++ linux-2.6.37-ck2/drivers/cpufreq/cpufreq_ondemand.c 2011-02-14 10:11:11.438252001 +1100 -@@ -28,12 +28,12 @@ - * It helps to keep variable names smaller, simpler - */ - --#define DEF_FREQUENCY_DOWN_DIFFERENTIAL (10) --#define DEF_FREQUENCY_UP_THRESHOLD (80) -+#define DEF_FREQUENCY_DOWN_DIFFERENTIAL (17) -+#define DEF_FREQUENCY_UP_THRESHOLD (63) - #define DEF_SAMPLING_DOWN_FACTOR (1) - #define MAX_SAMPLING_DOWN_FACTOR (100000) - #define MICRO_FREQUENCY_DOWN_DIFFERENTIAL (3) --#define MICRO_FREQUENCY_UP_THRESHOLD (95) -+#define MICRO_FREQUENCY_UP_THRESHOLD (80) - #define MICRO_FREQUENCY_MIN_SAMPLE_RATE (10000) - #define MIN_FREQUENCY_UP_THRESHOLD (11) - #define MAX_FREQUENCY_UP_THRESHOLD (100) -@@ -513,10 +513,10 @@ - - /* - * Every sampling_rate, we check, if current idle time is less -- * than 20% (default), then we try to increase frequency -+ * than 37% (default), then we try to increase frequency - * Every sampling_rate, we look for a the lowest - * frequency which can sustain the load while keeping idle time over -- * 30%. If such a frequency exist, we try to decrease to this frequency. -+ * 50%. If such a frequency exist, we try to decrease to this frequency. - * - * Any frequency increase takes it to the maximum frequency. - * Frequency reduction happens at minimum steps of diff --git a/packages/linux/patches/linux-2.6.38-rc7-704_hz-default_1000.patch b/packages/linux/patches/linux-2.6.38-rc7-704_hz-default_1000.patch deleted file mode 100644 index 5af5138068..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-704_hz-default_1000.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- - kernel/Kconfig.hz | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -Index: linux-2.6.37-ck2/kernel/Kconfig.hz -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/Kconfig.hz 2009-06-10 13:05:27.000000000 +1000 -+++ linux-2.6.37-ck2/kernel/Kconfig.hz 2011-02-14 10:11:10.474252000 +1100 -@@ -4,7 +4,7 @@ - - choice - prompt "Timer frequency" -- default HZ_250 -+ default HZ_1000 - help - Allows the configuration of the timer frequency. It is customary - to have the timer interrupt run at 1000 Hz but 100 Hz may be more diff --git a/packages/linux/patches/linux-2.6.38-rc7-705_hz-no_default_250.patch b/packages/linux/patches/linux-2.6.38-rc7-705_hz-no_default_250.patch deleted file mode 100644 index 051075471a..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-705_hz-no_default_250.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- - kernel/Kconfig.hz | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - -Index: linux-2.6.37-ck2/kernel/Kconfig.hz -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/Kconfig.hz 2011-02-14 10:11:10.474252000 +1100 -+++ linux-2.6.37-ck2/kernel/Kconfig.hz 2011-02-14 10:11:10.702252000 +1100 -@@ -23,13 +23,14 @@ - with lots of processors that may show reduced performance if - too many timer interrupts are occurring. - -- config HZ_250 -+ config HZ_250_NODEFAULT - bool "250 HZ" - help -- 250 Hz is a good compromise choice allowing server performance -- while also showing good interactive responsiveness even -- on SMP and NUMA systems. If you are going to be using NTSC video -- or multimedia, selected 300Hz instead. -+ 250 HZ is a lousy compromise choice allowing server interactivity -+ while also showing desktop throughput and no extra power saving on -+ laptops. No good for anything. -+ -+ Recommend 100 or 1000 instead. - - config HZ_300 - bool "300 HZ" -@@ -43,14 +44,16 @@ - bool "1000 HZ" - help - 1000 Hz is the preferred choice for desktop systems and other -- systems requiring fast interactive responses to events. -+ systems requiring fast interactive responses to events. Laptops -+ can also benefit from this choice without sacrificing battery life -+ if dynticks is also enabled. - - endchoice - - config HZ - int - default 100 if HZ_100 -- default 250 if HZ_250 -+ default 250 if HZ_250_NODEFAULT - default 300 if HZ_300 - default 1000 if HZ_1000 - diff --git a/packages/linux/patches/linux-2.6.38-rc7-706_hz-raise_max.patch b/packages/linux/patches/linux-2.6.38-rc7-706_hz-raise_max.patch deleted file mode 100644 index bf70f54392..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-706_hz-raise_max.patch +++ /dev/null @@ -1,174 +0,0 @@ ---- - arch/x86/kernel/cpu/proc.c | 2 - - arch/x86/kernel/smpboot.c | 2 - - include/linux/nfsd/stats.h | 4 +- - include/net/inet_timewait_sock.h | 10 ++++-- - init/calibrate.c | 2 - - kernel/Kconfig.hz | 64 +++++++++++++++++++++++++++++++++++++++ - 6 files changed, 76 insertions(+), 8 deletions(-) - -Index: linux-2.6.37-ck2/arch/x86/kernel/cpu/proc.c -=================================================================== ---- linux-2.6.37-ck2.orig/arch/x86/kernel/cpu/proc.c 2009-12-03 21:39:58.000000000 +1100 -+++ linux-2.6.37-ck2/arch/x86/kernel/cpu/proc.c 2011-02-14 10:11:10.919252001 +1100 -@@ -109,7 +109,7 @@ - - seq_printf(m, "\nbogomips\t: %lu.%02lu\n", - c->loops_per_jiffy/(500000/HZ), -- (c->loops_per_jiffy/(5000/HZ)) % 100); -+ (c->loops_per_jiffy * 10 /(50000/HZ)) % 100); - - #ifdef CONFIG_X86_64 - if (c->x86_tlbsize > 0) -Index: linux-2.6.37-ck2/arch/x86/kernel/smpboot.c -=================================================================== ---- linux-2.6.37-ck2.orig/arch/x86/kernel/smpboot.c 2011-01-06 14:04:08.000000000 +1100 -+++ linux-2.6.37-ck2/arch/x86/kernel/smpboot.c 2011-02-14 10:11:10.920252001 +1100 -@@ -497,7 +497,7 @@ - "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", - num_online_cpus(), - bogosum/(500000/HZ), -- (bogosum/(5000/HZ))%100); -+ (bogosum * 10/(50000/HZ))%100); - - pr_debug("Before bogocount - setting activated=1.\n"); - } -Index: linux-2.6.37-ck2/include/linux/nfsd/stats.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/nfsd/stats.h 2009-06-10 13:05:27.000000000 +1000 -+++ linux-2.6.37-ck2/include/linux/nfsd/stats.h 2011-02-14 10:11:10.920252001 +1100 -@@ -11,8 +11,8 @@ - - #include - --/* thread usage wraps very million seconds (approx one fortnight) */ --#define NFSD_USAGE_WRAP (HZ*1000000) -+/* thread usage wraps every one hundred thousand seconds (approx one day) */ -+#define NFSD_USAGE_WRAP (HZ*100000) - - #ifdef __KERNEL__ - -Index: linux-2.6.37-ck2/include/net/inet_timewait_sock.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/net/inet_timewait_sock.h 2010-08-02 11:12:25.000000000 +1000 -+++ linux-2.6.37-ck2/include/net/inet_timewait_sock.h 2011-02-14 10:11:10.920252001 +1100 -@@ -39,8 +39,8 @@ - * If time > 4sec, it is "slow" path, no recycling is required, - * so that we select tick to get range about 4 seconds. - */ --#if HZ <= 16 || HZ > 4096 --# error Unsupported: HZ <= 16 or HZ > 4096 -+#if HZ <= 16 || HZ > 16384 -+# error Unsupported: HZ <= 16 or HZ > 16384 - #elif HZ <= 32 - # define INET_TWDR_RECYCLE_TICK (5 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) - #elif HZ <= 64 -@@ -55,8 +55,12 @@ - # define INET_TWDR_RECYCLE_TICK (10 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) - #elif HZ <= 2048 - # define INET_TWDR_RECYCLE_TICK (11 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) --#else -+#elif HZ <= 4096 - # define INET_TWDR_RECYCLE_TICK (12 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) -+#elif HZ <= 8192 -+# define INET_TWDR_RECYCLE_TICK (13 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) -+#else -+# define INET_TWDR_RECYCLE_TICK (14 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) - #endif - - /* TIME_WAIT reaping mechanism. */ -Index: linux-2.6.37-ck2/init/calibrate.c -=================================================================== ---- linux-2.6.37-ck2.orig/init/calibrate.c 2010-02-25 21:51:52.000000000 +1100 -+++ linux-2.6.37-ck2/init/calibrate.c 2011-02-14 10:11:10.921252001 +1100 -@@ -176,7 +176,7 @@ - if (!printed) - pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n", - loops_per_jiffy/(500000/HZ), -- (loops_per_jiffy/(5000/HZ)) % 100, loops_per_jiffy); -+ (loops_per_jiffy * 10 /(50000/HZ)) % 100, loops_per_jiffy); - - printed = true; - } -Index: linux-2.6.37-ck2/kernel/Kconfig.hz -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/Kconfig.hz 2011-02-14 10:11:10.702252000 +1100 -+++ linux-2.6.37-ck2/kernel/Kconfig.hz 2011-02-14 10:11:10.921252001 +1100 -@@ -48,6 +48,63 @@ - can also benefit from this choice without sacrificing battery life - if dynticks is also enabled. - -+ config HZ_1500 -+ bool "1500 HZ" -+ help -+ 1500 Hz is an insane value to use to run broken software that is Hz -+ limited. -+ -+ Being over 1000, driver breakage is likely. -+ -+ config HZ_2000 -+ bool "2000 HZ" -+ help -+ 2000 Hz is an insane value to use to run broken software that is Hz -+ limited. -+ -+ Being over 1000, driver breakage is likely. -+ -+ config HZ_3000 -+ bool "3000 HZ" -+ help -+ 3000 Hz is an insane value to use to run broken software that is Hz -+ limited. -+ -+ Being over 1000, driver breakage is likely. -+ -+ config HZ_4000 -+ bool "4000 HZ" -+ help -+ 4000 Hz is an insane value to use to run broken software that is Hz -+ limited. -+ -+ Being over 1000, driver breakage is likely. -+ -+ config HZ_5000 -+ bool "5000 HZ" -+ help -+ 5000 Hz is an obscene value to use to run broken software that is Hz -+ limited. -+ -+ Being over 1000, driver breakage is likely. -+ -+ config HZ_7500 -+ bool "7500 HZ" -+ help -+ 7500 Hz is an obscene value to use to run broken software that is Hz -+ limited. -+ -+ Being over 1000, driver breakage is likely. -+ -+ config HZ_10000 -+ bool "10000 HZ" -+ help -+ 10000 Hz is an obscene value to use to run broken software that is Hz -+ limited. -+ -+ Being over 1000, driver breakage is likely. -+ -+ - endchoice - - config HZ -@@ -56,6 +113,13 @@ - default 250 if HZ_250_NODEFAULT - default 300 if HZ_300 - default 1000 if HZ_1000 -+ default 1500 if HZ_1500 -+ default 2000 if HZ_2000 -+ default 3000 if HZ_3000 -+ default 4000 if HZ_4000 -+ default 5000 if HZ_5000 -+ default 7500 if HZ_7500 -+ default 10000 if HZ_10000 - - config SCHED_HRTICK - def_bool HIGH_RES_TIMERS && (!SMP || USE_GENERIC_SMP_HELPERS) diff --git a/packages/linux/patches/linux-2.6.38-rc7-707_kconfig-expose_vmsplit_option.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-707_kconfig-expose_vmsplit_option.patch.disabled deleted file mode 100644 index 937cf72f31..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-707_kconfig-expose_vmsplit_option.patch.disabled +++ /dev/null @@ -1,40 +0,0 @@ ---- - arch/x86/Kconfig | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -Index: linux-2.6.37-ck2/arch/x86/Kconfig -=================================================================== ---- linux-2.6.37-ck2.orig/arch/x86/Kconfig 2011-01-06 14:04:08.000000000 +1100 -+++ linux-2.6.37-ck2/arch/x86/Kconfig 2011-02-14 10:11:10.260252001 +1100 -@@ -1046,7 +1046,7 @@ - - choice - depends on EXPERIMENTAL -- prompt "Memory split" if EMBEDDED -+ prompt "Memory split" - default VMSPLIT_3G - depends on X86_32 - ---help--- -@@ -1066,17 +1066,17 @@ - option alone! - - config VMSPLIT_3G -- bool "3G/1G user/kernel split" -+ bool "Default 896MB lowmem (3G/1G user/kernel split)" - config VMSPLIT_3G_OPT - depends on !X86_PAE -- bool "3G/1G user/kernel split (for full 1G low memory)" -+ bool "1GB lowmem (3G/1G user/kernel split)" - config VMSPLIT_2G -- bool "2G/2G user/kernel split" -+ bool "2GB lowmem (2G/2G user/kernel split)" - config VMSPLIT_2G_OPT - depends on !X86_PAE -- bool "2G/2G user/kernel split (for full 2G low memory)" -+ bool "2GB lowmem (2G/2G user/kernel split)" - config VMSPLIT_1G -- bool "1G/3G user/kernel split" -+ bool "3GB lowmem (1G/3G user/kernel split)" - endchoice - - config PAGE_OFFSET diff --git a/packages/linux/patches/linux-2.6.38-rc7-708_mm-kswapd_inherit_prio-1.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-708_mm-kswapd_inherit_prio-1.patch.disabled deleted file mode 100644 index 04d3712fe7..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-708_mm-kswapd_inherit_prio-1.patch.disabled +++ /dev/null @@ -1,69 +0,0 @@ ---- - mm/vmscan.c | 33 ++++++++++++++++++++++++++++++++- - 1 file changed, 32 insertions(+), 1 deletion(-) - -Index: linux-2.6.37-ck2/mm/vmscan.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/vmscan.c 2011-02-14 10:11:00.986252001 +1100 -+++ linux-2.6.37-ck2/mm/vmscan.c 2011-02-14 10:11:01.254252001 +1100 -@@ -1855,6 +1855,33 @@ - } - - /* -+ * Helper functions to adjust nice level of kswapd, based on the priority of -+ * the task (p) that called it. If it is already higher priority we do not -+ * demote its nice level since it is still working on behalf of a higher -+ * priority task. With kernel threads we leave it at nice 0. -+ * -+ * We don't ever run kswapd real time, so if a real time task calls kswapd we -+ * set it to highest SCHED_NORMAL priority. -+ */ -+static inline int effective_sc_prio(struct task_struct *p) -+{ -+ if (likely(p->mm)) { -+ if (rt_task(p)) -+ return -20; -+ return task_nice(p); -+ } -+ return 0; -+} -+ -+static void set_kswapd_nice(struct task_struct *kswapd, int active) -+{ -+ long nice = effective_sc_prio(current); -+ -+ if (task_nice(kswapd) > nice || !active) -+ set_user_nice(kswapd, nice); -+} -+ -+/* - * This is the direct reclaim path, for page-allocating processes. We only - * try to reclaim pages from zones which will satisfy the caller's allocation - * request. -@@ -2457,6 +2484,7 @@ - } - } - -+ set_user_nice(tsk, 0); - order = pgdat->kswapd_max_order; - } - finish_wait(&pgdat->kswapd_wait, &wait); -@@ -2483,6 +2511,7 @@ - void wakeup_kswapd(struct zone *zone, int order) - { - pg_data_t *pgdat; -+ int active; - - if (!populated_zone(zone)) - return; -@@ -2495,7 +2524,9 @@ - trace_mm_vmscan_wakeup_kswapd(pgdat->node_id, zone_idx(zone), order); - if (!cpuset_zone_allowed_hardwall(zone, GFP_KERNEL)) - return; -- if (!waitqueue_active(&pgdat->kswapd_wait)) -+ active = waitqueue_active(&pgdat->kswapd_wait); -+ set_kswapd_nice(pgdat->kswapd, active); -+ if (!active) - return; - wake_up_interruptible(&pgdat->kswapd_wait); - } diff --git a/packages/linux/patches/linux-2.6.38-rc7-709_mm-decrease_default_dirty_ratio.patch b/packages/linux/patches/linux-2.6.38-rc7-709_mm-decrease_default_dirty_ratio.patch deleted file mode 100644 index 804bccfcd4..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-709_mm-decrease_default_dirty_ratio.patch +++ /dev/null @@ -1,34 +0,0 @@ -The default dirty ratio is chosen to be a compromise between throughput and -overall system latency. On a desktop, if an application writes to disk a lot, -that application should be the one to slow down rather than the desktop as a -whole. At higher dirty ratio settings, an application could write a lot to -disk and then happily use lots of CPU time after that while the rest of the -system is busy waiting on that naughty applications disk writes to complete -before anything else happening. - -Lower ratios mean that the application that do a lot of disk writes end up -being responsible for their own actions and they're the ones that slow down -rather than the system in general. - -This does decrease overall write throughput slightly, but to the benefit of -the latency of the system as a whole. - --ck - ---- - mm/page-writeback.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -Index: linux-2.6.37-ck2/mm/page-writeback.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/page-writeback.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/mm/page-writeback.c 2011-02-14 10:11:10.037252000 +1100 -@@ -78,7 +78,7 @@ - /* - * The generator of dirty data starts writeback at this percentage - */ --int vm_dirty_ratio = 20; -+int vm_dirty_ratio = 5; - - /* - * vm_dirty_bytes starts at 0 (disabled) so that it is a function of diff --git a/packages/linux/patches/linux-2.6.38-rc7-710_mm-drop_swap_cache_aggressively.patch b/packages/linux/patches/linux-2.6.38-rc7-710_mm-drop_swap_cache_aggressively.patch deleted file mode 100644 index 2cd9f63b62..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-710_mm-drop_swap_cache_aggressively.patch +++ /dev/null @@ -1,87 +0,0 @@ ---- - include/linux/swap.h | 2 +- - mm/memory.c | 2 +- - mm/swapfile.c | 9 ++++----- - mm/vmscan.c | 2 +- - 4 files changed, 7 insertions(+), 8 deletions(-) - -Index: linux-2.6.37-ck2/include/linux/swap.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/swap.h 2011-02-14 10:11:00.763252001 +1100 -+++ linux-2.6.37-ck2/include/linux/swap.h 2011-02-14 10:11:00.982252001 +1100 -@@ -192,7 +192,7 @@ - int next; /* swapfile to be used next */ - }; - --/* Swap 50% full? Release swapcache more aggressively.. */ -+/* Swap 50% full? */ - #define vm_swap_full() (nr_swap_pages*2 < total_swap_pages) - - /* linux/mm/page_alloc.c */ -Index: linux-2.6.37-ck2/mm/memory.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/memory.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/mm/memory.c 2011-02-14 10:11:00.984252001 +1100 -@@ -2754,7 +2754,7 @@ - mem_cgroup_commit_charge_swapin(page, ptr); - - swap_free(entry); -- if (vm_swap_full() || (vma->vm_flags & VM_LOCKED) || PageMlocked(page)) -+ if ((vma->vm_flags & VM_LOCKED) || PageMlocked(page)) - try_to_free_swap(page); - unlock_page(page); - if (swapcache) { -Index: linux-2.6.37-ck2/mm/swapfile.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/swapfile.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/mm/swapfile.c 2011-02-14 10:11:00.985252001 +1100 -@@ -321,7 +321,7 @@ - scan_base = offset = si->lowest_bit; - - /* reuse swap entry of cache-only swap if not busy. */ -- if (vm_swap_full() && si->swap_map[offset] == SWAP_HAS_CACHE) { -+ if (si->swap_map[offset] == SWAP_HAS_CACHE) { - int swap_was_freed; - spin_unlock(&swap_lock); - swap_was_freed = __try_to_reclaim_swap(si, offset); -@@ -410,7 +410,7 @@ - spin_lock(&swap_lock); - goto checks; - } -- if (vm_swap_full() && si->swap_map[offset] == SWAP_HAS_CACHE) { -+ if (si->swap_map[offset] == SWAP_HAS_CACHE) { - spin_lock(&swap_lock); - goto checks; - } -@@ -425,7 +425,7 @@ - spin_lock(&swap_lock); - goto checks; - } -- if (vm_swap_full() && si->swap_map[offset] == SWAP_HAS_CACHE) { -+ if (si->swap_map[offset] == SWAP_HAS_CACHE) { - spin_lock(&swap_lock); - goto checks; - } -@@ -739,8 +739,7 @@ - * Not mapped elsewhere, or swap space full? Free it! - * Also recheck PageSwapCache now page is locked (above). - */ -- if (PageSwapCache(page) && !PageWriteback(page) && -- (!page_mapped(page) || vm_swap_full())) { -+ if (PageSwapCache(page) && !PageWriteback(page)) { - delete_from_swap_cache(page); - SetPageDirty(page); - } -Index: linux-2.6.37-ck2/mm/vmscan.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/vmscan.c 2011-02-14 10:11:00.536252000 +1100 -+++ linux-2.6.37-ck2/mm/vmscan.c 2011-02-14 10:11:00.986252001 +1100 -@@ -900,7 +900,7 @@ - - activate_locked: - /* Not a candidate for swapping, so reclaim swap space. */ -- if (PageSwapCache(page) && vm_swap_full()) -+ if (PageSwapCache(page)) - try_to_free_swap(page); - VM_BUG_ON(PageActive(page)); - SetPageActive(page); diff --git a/packages/linux/patches/linux-2.6.38-rc7-711_mm-enable_swaptoken_only_when_swap_full.patch b/packages/linux/patches/linux-2.6.38-rc7-711_mm-enable_swaptoken_only_when_swap_full.patch deleted file mode 100644 index f7f76ea318..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-711_mm-enable_swaptoken_only_when_swap_full.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- - include/linux/swap.h | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -Index: linux-2.6.37-ck2/include/linux/swap.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/swap.h 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/include/linux/swap.h 2011-02-14 10:11:00.763252001 +1100 -@@ -348,9 +348,10 @@ - extern void grab_swap_token(struct mm_struct *); - extern void __put_swap_token(struct mm_struct *); - -+/* Only allow swap token to have effect if swap is full */ - static inline int has_swap_token(struct mm_struct *mm) - { -- return (mm == swap_token_mm); -+ return (mm == swap_token_mm && vm_swap_full()); - } - - static inline void put_swap_token(struct mm_struct *mm) diff --git a/packages/linux/patches/linux-2.6.38-rc7-712_mm-background_scan.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-712_mm-background_scan.patch.disabled deleted file mode 100644 index c84d37d1af..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-712_mm-background_scan.patch.disabled +++ /dev/null @@ -1,137 +0,0 @@ ---- - include/linux/mmzone.h | 6 +++++- - mm/vmscan.c | 42 ++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 47 insertions(+), 1 deletion(-) - -Index: linux-2.6.37-ck2/include/linux/mmzone.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/mmzone.h 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/include/linux/mmzone.h 2011-02-14 10:11:01.470252001 +1100 -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -161,12 +162,14 @@ - WMARK_MIN, - WMARK_LOW, - WMARK_HIGH, -+ WMARK_LOTS, - NR_WMARK - }; - - #define min_wmark_pages(z) (z->watermark[WMARK_MIN]) - #define low_wmark_pages(z) (z->watermark[WMARK_LOW]) - #define high_wmark_pages(z) (z->watermark[WMARK_HIGH]) -+#define lots_wmark_pages(z) (z->watermark[WMARK_LOTS]) - - struct per_cpu_pages { - int count; /* number of pages in the list */ -@@ -343,7 +346,7 @@ - ZONE_PADDING(_pad1_) - - /* Fields commonly accessed by the page reclaim scanner */ -- spinlock_t lru_lock; -+ spinlock_t lru_lock; - struct zone_lru { - struct list_head list; - } lru[NR_LRU_LISTS]; -@@ -645,6 +648,7 @@ - wait_queue_head_t kswapd_wait; - struct task_struct *kswapd; - int kswapd_max_order; -+ struct timer_list watermark_timer; - } pg_data_t; - - #define node_present_pages(nid) (NODE_DATA(nid)->node_present_pages) -Index: linux-2.6.37-ck2/mm/vmscan.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/vmscan.c 2011-02-14 10:11:01.254252001 +1100 -+++ linux-2.6.37-ck2/mm/vmscan.c 2011-02-14 10:11:01.471252001 +1100 -@@ -36,6 +36,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2398,6 +2399,8 @@ - return sc.nr_reclaimed; - } - -+#define WT_EXPIRY (HZ * 5) /* Time to wakeup watermark_timer */ -+ - /* - * The background pageout daemon, started as a kernel thread - * from the init process. -@@ -2448,6 +2451,8 @@ - unsigned long new_order; - int ret; - -+ /* kswapd has been busy so delay watermark_timer */ -+ mod_timer(&pgdat->watermark_timer, jiffies + WT_EXPIRY); - prepare_to_wait(&pgdat->kswapd_wait, &wait, TASK_INTERRUPTIBLE); - new_order = pgdat->kswapd_max_order; - pgdat->kswapd_max_order = 0; -@@ -2632,20 +2637,57 @@ - } - - /* -+ * We wake up kswapd every WT_EXPIRY till free ram is above pages_lots -+ */ -+static void watermark_wakeup(unsigned long data) -+{ -+ pg_data_t *pgdat = (pg_data_t *)data; -+ struct timer_list *wt = &pgdat->watermark_timer; -+ int i; -+ -+ if (!waitqueue_active(&pgdat->kswapd_wait) || above_background_load()) -+ goto out; -+ for (i = pgdat->nr_zones - 1; i >= 0; i--) { -+ struct zone *z = pgdat->node_zones + i; -+ -+ if (!populated_zone(z) || is_highmem(z)) { -+ /* We are better off leaving highmem full */ -+ continue; -+ } -+ if (!zone_watermark_ok(z, 0, lots_wmark_pages(z), 0, 0)) { -+ wake_up_interruptible(&pgdat->kswapd_wait); -+ goto out; -+ } -+ } -+out: -+ mod_timer(wt, jiffies + WT_EXPIRY); -+ return; -+} -+ -+/* - * This kswapd start function will be called by init and node-hot-add. - * On node-hot-add, kswapd will moved to proper cpus if cpus are hot-added. - */ - int kswapd_run(int nid) - { - pg_data_t *pgdat = NODE_DATA(nid); -+ struct timer_list *wt; - int ret = 0; - - if (pgdat->kswapd) - return 0; - -+ wt = &pgdat->watermark_timer; -+ init_timer(wt); -+ wt->data = (unsigned long)pgdat; -+ wt->function = watermark_wakeup; -+ wt->expires = jiffies + WT_EXPIRY; -+ add_timer(wt); -+ - pgdat->kswapd = kthread_run(kswapd, pgdat, "kswapd%d", nid); - if (IS_ERR(pgdat->kswapd)) { - /* failure at boot is fatal */ -+ del_timer(wt); - BUG_ON(system_state == SYSTEM_BOOTING); - printk("Failed to start kswapd on node %d\n",nid); - ret = -1; diff --git a/packages/linux/patches/linux-2.6.38-rc7-713_mm-idleprio_prio-1.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-713_mm-idleprio_prio-1.patch.disabled deleted file mode 100644 index f0ca19b956..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-713_mm-idleprio_prio-1.patch.disabled +++ /dev/null @@ -1,33 +0,0 @@ ---- - include/linux/sched.h | 2 +- - mm/vmscan.c | 2 ++ - 2 files changed, 3 insertions(+), 1 deletion(-) - -Index: linux-2.6.37-ck1/include/linux/sched.h -=================================================================== ---- linux-2.6.37-ck1.orig/include/linux/sched.h 2011-01-06 14:07:19.971048973 +1100 -+++ linux-2.6.37-ck1/include/linux/sched.h 2011-01-06 14:07:58.442334300 +1100 -@@ -38,9 +38,9 @@ - #define SCHED_BATCH 3 - /* SCHED_ISO: Implemented on BFS only */ - #define SCHED_IDLE 5 -+#define SCHED_IDLEPRIO SCHED_IDLE - #ifdef CONFIG_SCHED_BFS - #define SCHED_ISO 4 --#define SCHED_IDLEPRIO SCHED_IDLE - #define SCHED_MAX (SCHED_IDLEPRIO) - #define SCHED_RANGE(policy) ((policy) <= SCHED_MAX) - #endif -Index: linux-2.6.37-ck1/mm/vmscan.c -=================================================================== ---- linux-2.6.37-ck1.orig/mm/vmscan.c 2011-01-06 14:07:58.305326159 +1100 -+++ linux-2.6.37-ck1/mm/vmscan.c 2011-01-06 14:07:58.443334359 +1100 -@@ -1874,6 +1874,8 @@ static inline int effective_sc_prio(stru - if (likely(p->mm)) { - if (rt_task(p)) - return -20; -+ if (p->policy == SCHED_IDLEPRIO) -+ return 19; - return task_nice(p); - } - return 0; diff --git a/packages/linux/patches/linux-2.6.38-rc7-714_mm-lru_cache_add_lru_tail.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-714_mm-lru_cache_add_lru_tail.patch.disabled deleted file mode 100644 index 98cf2994f4..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-714_mm-lru_cache_add_lru_tail.patch.disabled +++ /dev/null @@ -1,250 +0,0 @@ ---- - include/linux/mm_inline.h | 14 +++++++++++- - include/linux/swap.h | 8 ++++++- - mm/filemap.c | 50 +++++++++++++++++++++++++++++++++++++++------- - mm/swap.c | 30 ++++++++++++++++++++++----- - 4 files changed, 86 insertions(+), 16 deletions(-) - -Index: linux-2.6.37-ck2/include/linux/mm_inline.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/mm_inline.h 2009-12-03 21:40:09.000000000 +1100 -+++ linux-2.6.37-ck2/include/linux/mm_inline.h 2011-02-14 10:11:09.770252000 +1100 -@@ -20,14 +20,24 @@ - } - - static inline void --add_page_to_lru_list(struct zone *zone, struct page *page, enum lru_list l) -+__add_page_to_lru_list(struct zone *zone, struct page *page, enum lru_list l, int tail) - { -- list_add(&page->lru, &zone->lru[l].list); -+ /* See if this should be added to the tail of this lru list */ -+ if (tail) -+ list_add_tail(&page->lru, &zone->lru[l].list); -+ else -+ list_add(&page->lru, &zone->lru[l].list); - __inc_zone_state(zone, NR_LRU_BASE + l); - mem_cgroup_add_lru_list(page, l); - } - - static inline void -+add_page_to_lru_list(struct zone *zone, struct page *page, enum lru_list l) -+{ -+ __add_page_to_lru_list(zone, page, l, 0); -+} -+ -+static inline void - del_page_from_lru_list(struct zone *zone, struct page *page, enum lru_list l) - { - list_del(&page->lru); -Index: linux-2.6.37-ck2/include/linux/swap.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/swap.h 2011-02-14 10:11:00.982252001 +1100 -+++ linux-2.6.37-ck2/include/linux/swap.h 2011-02-14 10:11:09.770252000 +1100 -@@ -206,6 +206,7 @@ - - - /* linux/mm/swap.c */ -+extern void ____lru_cache_add(struct page *, enum lru_list lru, int tail); - extern void __lru_cache_add(struct page *, enum lru_list lru); - extern void lru_cache_add_lru(struct page *, enum lru_list lru); - extern void activate_page(struct page *); -@@ -226,9 +227,14 @@ - __lru_cache_add(page, LRU_INACTIVE_ANON); - } - -+static inline void lru_cache_add_file_tail(struct page *page, int tail) -+{ -+ ____lru_cache_add(page, LRU_INACTIVE_FILE, tail); -+} -+ - static inline void lru_cache_add_file(struct page *page) - { -- __lru_cache_add(page, LRU_INACTIVE_FILE); -+ ____lru_cache_add(page, LRU_INACTIVE_FILE, 0); - } - - /* LRU Isolation modes. */ -Index: linux-2.6.37-ck2/mm/filemap.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/filemap.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/mm/filemap.c 2011-02-14 10:11:09.772252000 +1100 -@@ -439,8 +439,8 @@ - } - EXPORT_SYMBOL(add_to_page_cache_locked); - --int add_to_page_cache_lru(struct page *page, struct address_space *mapping, -- pgoff_t offset, gfp_t gfp_mask) -+int __add_to_page_cache_lru(struct page *page, struct address_space *mapping, -+ pgoff_t offset, gfp_t gfp_mask, int tail) - { - int ret; - -@@ -456,12 +456,18 @@ - ret = add_to_page_cache(page, mapping, offset, gfp_mask); - if (ret == 0) { - if (page_is_file_cache(page)) -- lru_cache_add_file(page); -+ lru_cache_add_file_tail(page, tail); - else - lru_cache_add_anon(page); - } - return ret; - } -+ -+int add_to_page_cache_lru(struct page *page, struct address_space *mapping, -+ pgoff_t offset, gfp_t gfp_mask) -+{ -+ return __add_to_page_cache_lru(page, mapping, offset, gfp_mask, 0); -+} - EXPORT_SYMBOL_GPL(add_to_page_cache_lru); - - #ifdef CONFIG_NUMA -@@ -968,6 +974,28 @@ - ra->ra_pages /= 4; - } - -+static inline int nr_mapped(void) -+{ -+ return global_page_state(NR_FILE_MAPPED) + -+ global_page_state(NR_ANON_PAGES); -+} -+ -+/* -+ * This examines how large in pages a file size is and returns 1 if it is -+ * more than half the unmapped ram. Avoid doing read_page_state which is -+ * expensive unless we already know it is likely to be large enough. -+ */ -+static int large_isize(unsigned long nr_pages) -+{ -+ if (nr_pages * 6 > vm_total_pages) { -+ unsigned long unmapped_ram = vm_total_pages - nr_mapped(); -+ -+ if (nr_pages * 2 > unmapped_ram) -+ return 1; -+ } -+ return 0; -+} -+ - /** - * do_generic_file_read - generic file read routine - * @filp: the file to read -@@ -992,7 +1020,7 @@ - pgoff_t prev_index; - unsigned long offset; /* offset into pagecache page */ - unsigned int prev_offset; -- int error; -+ int error, tail = 0; - - index = *ppos >> PAGE_CACHE_SHIFT; - prev_index = ra->prev_pos >> PAGE_CACHE_SHIFT; -@@ -1003,7 +1031,7 @@ - for (;;) { - struct page *page; - pgoff_t end_index; -- loff_t isize; -+ loff_t isize = 0; - unsigned long nr, ret; - - cond_resched(); -@@ -1177,8 +1205,16 @@ - desc->error = -ENOMEM; - goto out; - } -- error = add_to_page_cache_lru(page, mapping, -- index, GFP_KERNEL); -+ /* -+ * If we know the file is large we add the pages read to the -+ * end of the lru as we're unlikely to be able to cache the -+ * whole file in ram so make those pages the first to be -+ * dropped if not referenced soon. -+ */ -+ if (large_isize(end_index)) -+ tail = 1; -+ error = __add_to_page_cache_lru(page, mapping, -+ index, GFP_KERNEL, tail); - if (error) { - page_cache_release(page); - if (error == -EEXIST) -Index: linux-2.6.37-ck2/mm/swap.c -=================================================================== ---- linux-2.6.37-ck2.orig/mm/swap.c 2011-01-06 14:04:10.000000000 +1100 -+++ linux-2.6.37-ck2/mm/swap.c 2011-02-14 10:11:09.772252000 +1100 -@@ -215,15 +215,23 @@ - - EXPORT_SYMBOL(mark_page_accessed); - --void __lru_cache_add(struct page *page, enum lru_list lru) -+void ______pagevec_lru_add(struct pagevec *pvec, enum lru_list lru, int tail); -+ -+void ____lru_cache_add(struct page *page, enum lru_list lru, int tail) - { - struct pagevec *pvec = &get_cpu_var(lru_add_pvecs)[lru]; - - page_cache_get(page); - if (!pagevec_add(pvec, page)) -- ____pagevec_lru_add(pvec, lru); -+ ______pagevec_lru_add(pvec, lru, tail); - put_cpu_var(lru_add_pvecs); - } -+EXPORT_SYMBOL(____lru_cache_add); -+ -+void __lru_cache_add(struct page *page, enum lru_list lru) -+{ -+ ____lru_cache_add(page, lru, 0); -+} - EXPORT_SYMBOL(__lru_cache_add); - - /** -@@ -231,7 +239,7 @@ - * @page: the page to be added to the LRU. - * @lru: the LRU list to which the page is added. - */ --void lru_cache_add_lru(struct page *page, enum lru_list lru) -+void __lru_cache_add_lru(struct page *page, enum lru_list lru, int tail) - { - if (PageActive(page)) { - VM_BUG_ON(PageUnevictable(page)); -@@ -242,7 +250,12 @@ - } - - VM_BUG_ON(PageLRU(page) || PageActive(page) || PageUnevictable(page)); -- __lru_cache_add(page, lru); -+ ____lru_cache_add(page, lru, tail); -+} -+ -+void lru_cache_add_lru(struct page *page, enum lru_list lru) -+{ -+ __lru_cache_add_lru(page, lru, 0); - } - - /** -@@ -403,7 +416,7 @@ - * Add the passed pages to the LRU, then drop the caller's refcount - * on them. Reinitialises the caller's pagevec. - */ --void ____pagevec_lru_add(struct pagevec *pvec, enum lru_list lru) -+void ______pagevec_lru_add(struct pagevec *pvec, enum lru_list lru, int tail) - { - int i; - struct zone *zone = NULL; -@@ -431,7 +444,7 @@ - if (active) - SetPageActive(page); - update_page_reclaim_stat(zone, page, file, active); -- add_page_to_lru_list(zone, page, lru); -+ __add_page_to_lru_list(zone, page, lru, tail); - } - if (zone) - spin_unlock_irq(&zone->lru_lock); -@@ -439,6 +452,11 @@ - pagevec_reinit(pvec); - } - -+void ____pagevec_lru_add(struct pagevec *pvec, enum lru_list lru) -+{ -+ ______pagevec_lru_add(pvec, lru, 0); -+} -+ - EXPORT_SYMBOL(____pagevec_lru_add); - - /* diff --git a/packages/linux/patches/linux-2.6.38-rc7-717_preempt-desktop-tune.patch b/packages/linux/patches/linux-2.6.38-rc7-717_preempt-desktop-tune.patch deleted file mode 100644 index 89d3f3aead..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-717_preempt-desktop-tune.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- - kernel/Kconfig.preempt | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -Index: linux-2.6.37-ck2/kernel/Kconfig.preempt -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/Kconfig.preempt 2009-06-10 13:05:27.000000000 +1000 -+++ linux-2.6.37-ck2/kernel/Kconfig.preempt 2011-02-14 10:11:11.217252001 +1100 -@@ -1,7 +1,7 @@ - - choice - prompt "Preemption Model" -- default PREEMPT_NONE -+ default PREEMPT - - config PREEMPT_NONE - bool "No Forced Preemption (Server)" -@@ -17,7 +17,7 @@ - latencies. - - config PREEMPT_VOLUNTARY -- bool "Voluntary Kernel Preemption (Desktop)" -+ bool "Voluntary Kernel Preemption (Nothing)" - help - This option reduces the latency of the kernel by adding more - "explicit preemption points" to the kernel code. These new -@@ -31,7 +31,8 @@ - applications to run more 'smoothly' even when the system is - under load. - -- Select this if you are building a kernel for a desktop system. -+ Select this for no system in particular (choose Preemptible -+ instead on a desktop if you know what's good for you). - - config PREEMPT - bool "Preemptible Kernel (Low-Latency Desktop)" diff --git a/packages/linux/patches/linux-2.6.38-rc7-718_sched-add-above-background-load-function.patch.disabled b/packages/linux/patches/linux-2.6.38-rc7-718_sched-add-above-background-load-function.patch.disabled deleted file mode 100644 index ea1c1fa5b1..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc7-718_sched-add-above-background-load-function.patch.disabled +++ /dev/null @@ -1,61 +0,0 @@ ---- - include/linux/sched.h | 7 +++++++ - kernel/sched_bfs.c | 20 ++++++++++++++++++++ - 2 files changed, 27 insertions(+) - -Index: linux-2.6.37-ck2/include/linux/sched.h -=================================================================== ---- linux-2.6.37-ck2.orig/include/linux/sched.h 2011-02-14 09:47:50.988252000 +1100 -+++ linux-2.6.37-ck2/include/linux/sched.h 2011-02-14 10:11:00.292251999 +1100 -@@ -1558,6 +1558,7 @@ - return (p->policy == SCHED_ISO); - } - extern void remove_cpu(unsigned long cpu); -+extern int above_background_load(void); - #else /* CFS */ - extern int runqueue_is_locked(int cpu); - #define tsk_seruntime(t) ((t)->se.sum_exec_runtime) -@@ -1581,6 +1582,12 @@ - static inline void remove_cpu(unsigned long cpu) - { - } -+ -+/* Anyone feel like implementing this? */ -+static inline int above_background_load(void) -+{ -+ return 1; -+} - #endif /* CONFIG_SCHED_BFS */ - - /* Future-safe accessor for struct task_struct's cpus_allowed. */ -Index: linux-2.6.37-ck2/kernel/sched_bfs.c -=================================================================== ---- linux-2.6.37-ck2.orig/kernel/sched_bfs.c 2011-02-14 09:53:53.820252000 +1100 -+++ linux-2.6.37-ck2/kernel/sched_bfs.c 2011-02-14 10:11:00.294252001 +1100 -@@ -559,6 +559,26 @@ - grq_unlock(); - } - -+/* -+ * Look for any tasks *anywhere* that are running nice 0 or better. We do -+ * this lockless for overhead reasons since the occasional wrong result -+ * is harmless. -+ */ -+int above_background_load(void) -+{ -+ struct task_struct *cpu_curr; -+ unsigned long cpu; -+ -+ for_each_online_cpu(cpu) { -+ cpu_curr = cpu_rq(cpu)->curr; -+ if (unlikely(!cpu_curr)) -+ continue; -+ if (PRIO_TO_NICE(cpu_curr->static_prio) < 1) -+ return 1; -+ } -+ return 0; -+} -+ - #ifndef __ARCH_WANT_UNLOCKED_CTXSW - static inline void prepare_lock_switch(struct rq *rq, struct task_struct *next) - { diff --git a/packages/linux/patches/linux-2.6.38-rc7-000_crosscompile.patch b/packages/linux/patches/linux-2.6.38-rc8-000_crosscompile.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-000_crosscompile.patch rename to packages/linux/patches/linux-2.6.38-rc8-000_crosscompile.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-002_bash_only_feature.patch b/packages/linux/patches/linux-2.6.38-rc8-002_bash_only_feature.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-002_bash_only_feature.patch rename to packages/linux/patches/linux-2.6.38-rc8-002_bash_only_feature.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-003-no_dev_console.patch b/packages/linux/patches/linux-2.6.38-rc8-003-no_dev_console.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-003-no_dev_console.patch rename to packages/linux/patches/linux-2.6.38-rc8-003-no_dev_console.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-004_lower_undefined_mode_timeout.patch b/packages/linux/patches/linux-2.6.38-rc8-004_lower_undefined_mode_timeout.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-004_lower_undefined_mode_timeout.patch rename to packages/linux/patches/linux-2.6.38-rc8-004_lower_undefined_mode_timeout.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-005_kconfig_no_timestamp.patch b/packages/linux/patches/linux-2.6.38-rc8-005_kconfig_no_timestamp.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-005_kconfig_no_timestamp.patch rename to packages/linux/patches/linux-2.6.38-rc8-005_kconfig_no_timestamp.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-006_enable_utf8.patch b/packages/linux/patches/linux-2.6.38-rc8-006_enable_utf8.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-006_enable_utf8.patch rename to packages/linux/patches/linux-2.6.38-rc8-006_enable_utf8.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-007_die_floppy_die.patch b/packages/linux/patches/linux-2.6.38-rc8-007_die_floppy_die.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-007_die_floppy_die.patch rename to packages/linux/patches/linux-2.6.38-rc8-007_die_floppy_die.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-008-hda_intel_prealloc_4mb_dmabuffer.patch b/packages/linux/patches/linux-2.6.38-rc8-008-hda_intel_prealloc_4mb_dmabuffer.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-008-hda_intel_prealloc_4mb_dmabuffer.patch rename to packages/linux/patches/linux-2.6.38-rc8-008-hda_intel_prealloc_4mb_dmabuffer.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-009_disable_i8042_check_on_apple_mac.patch b/packages/linux/patches/linux-2.6.38-rc8-009_disable_i8042_check_on_apple_mac.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-009_disable_i8042_check_on_apple_mac.patch rename to packages/linux/patches/linux-2.6.38-rc8-009_disable_i8042_check_on_apple_mac.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-050_add_appleir_usb_driver.patch b/packages/linux/patches/linux-2.6.38-rc8-050_add_appleir_usb_driver.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-050_add_appleir_usb_driver.patch rename to packages/linux/patches/linux-2.6.38-rc8-050_add_appleir_usb_driver.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-051_add_ite-cir_driver-0.1.patch b/packages/linux/patches/linux-2.6.38-rc8-051_add_ite-cir_driver-0.1.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-051_add_ite-cir_driver-0.1.patch rename to packages/linux/patches/linux-2.6.38-rc8-051_add_ite-cir_driver-0.1.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-052-aureal_remote_quirk-0.1.patch b/packages/linux/patches/linux-2.6.38-rc8-052-aureal_remote_quirk-0.1.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-052-aureal_remote_quirk-0.1.patch rename to packages/linux/patches/linux-2.6.38-rc8-052-aureal_remote_quirk-0.1.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-053_ati-remote_all_keys_and_keychange-0.1.patch b/packages/linux/patches/linux-2.6.38-rc8-053_ati-remote_all_keys_and_keychange-0.1.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-053_ati-remote_all_keys_and_keychange-0.1.patch rename to packages/linux/patches/linux-2.6.38-rc8-053_ati-remote_all_keys_and_keychange-0.1.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-054_fix_nuvoton_wakeup-0.1.patch b/packages/linux/patches/linux-2.6.38-rc8-054_fix_nuvoton_wakeup-0.1.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-054_fix_nuvoton_wakeup-0.1.patch rename to packages/linux/patches/linux-2.6.38-rc8-054_fix_nuvoton_wakeup-0.1.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-062-Pioneer_DVR-216D_failed_xfermode-0.1.patch b/packages/linux/patches/linux-2.6.38-rc8-062-Pioneer_DVR-216D_failed_xfermode-0.1.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-062-Pioneer_DVR-216D_failed_xfermode-0.1.patch rename to packages/linux/patches/linux-2.6.38-rc8-062-Pioneer_DVR-216D_failed_xfermode-0.1.patch diff --git a/packages/linux/patches/linux-2.6.38-rc7-110-drm_nouveau_upstream-20110222.patch b/packages/linux/patches/linux-2.6.38-rc8-110-drm_nouveau_upstream-20110312.patch similarity index 77% rename from packages/linux/patches/linux-2.6.38-rc7-110-drm_nouveau_upstream-20110222.patch rename to packages/linux/patches/linux-2.6.38-rc8-110-drm_nouveau_upstream-20110312.patch index 32cbe2de6d..4abd334599 100644 --- a/packages/linux/patches/linux-2.6.38-rc7-110-drm_nouveau_upstream-20110222.patch +++ b/packages/linux/patches/linux-2.6.38-rc8-110-drm_nouveau_upstream-20110312.patch @@ -1,6 +1,6 @@ -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bios.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_bios.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bios.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_bios.c 2011-02-22 14:25:08.609606768 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_bios.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_bios.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_bios.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_bios.c 2011-03-09 18:30:58.000000000 +0100 @@ -282,7 +282,7 @@ { #if 0 @@ -108,9 +108,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bios.c linux-2.6/dri bios->dev = dev; if (!NVShadowVBIOS(dev, bios->data)) -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bios.h linux-2.6/drivers/gpu/drm/nouveau/nouveau_bios.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bios.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_bios.h 2011-02-22 14:16:21.580230479 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_bios.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_bios.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_bios.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_bios.h 2011-03-09 18:30:58.000000000 +0100 @@ -251,7 +251,7 @@ uint8_t digital_min_front_porch; bool fp_no_ddc; @@ -120,10 +120,10 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bios.h linux-2.6/dri uint8_t data[NV_PROM_SIZE]; unsigned int length; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_bo.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_bo.c 2011-02-22 14:32:02.564311615 +0100 -@@ -54,8 +54,8 @@ +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_bo.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_bo.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_bo.c 2011-03-09 18:30:58.000000000 +0100 +@@ -57,8 +57,8 @@ } static void @@ -134,7 +134,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive { struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); -@@ -80,7 +80,7 @@ +@@ -83,7 +83,7 @@ } } else { if (likely(dev_priv->chan_vm)) { @@ -143,7 +143,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive *page_shift = dev_priv->chan_vm->lpg_shift; else *page_shift = dev_priv->chan_vm->spg_shift; -@@ -98,8 +98,7 @@ +@@ -101,8 +101,7 @@ int nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, int size, int align, uint32_t flags, uint32_t tile_mode, @@ -153,7 +153,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_bo *nvbo; -@@ -110,16 +109,14 @@ +@@ -113,16 +112,14 @@ return -ENOMEM; INIT_LIST_HEAD(&nvbo->head); INIT_LIST_HEAD(&nvbo->entry); @@ -172,7 +172,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive ret = nouveau_vm_get(dev_priv->chan_vm, size, page_shift, NV_MEM_ACCESS_RW, &nvbo->vma); if (ret) { -@@ -140,11 +137,8 @@ +@@ -144,11 +141,8 @@ } nvbo->channel = NULL; @@ -186,7 +186,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive *pnvbo = nvbo; return 0; } -@@ -314,11 +308,8 @@ +@@ -318,11 +312,8 @@ if (ret) return ret; @@ -200,7 +200,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive return 0; } -@@ -381,7 +372,8 @@ +@@ -385,7 +376,8 @@ case NOUVEAU_GART_AGP: return ttm_agp_backend_init(bdev, dev->agp->bridge); #endif @@ -210,7 +210,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive return nouveau_sgdma_init_ttm(dev); default: NV_ERROR(dev, "Unknown GART type %d\n", -@@ -427,7 +419,10 @@ +@@ -431,7 +423,10 @@ man->default_caching = TTM_PL_FLAG_WC; break; case TTM_PL_TT: @@ -222,7 +222,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive switch (dev_priv->gart_info.type) { case NOUVEAU_GART_AGP: man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; -@@ -435,7 +430,8 @@ +@@ -439,7 +434,8 @@ TTM_PL_FLAG_WC; man->default_caching = TTM_PL_FLAG_WC; break; @@ -232,7 +232,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; man->available_caching = TTM_PL_MASK_CACHING; -@@ -497,45 +493,22 @@ +@@ -501,45 +497,22 @@ return ret; } @@ -286,7 +286,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive page_count = new_mem->num_pages; while (page_count) { -@@ -570,33 +543,18 @@ +@@ -574,33 +547,18 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) { @@ -327,7 +327,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive while (length) { u32 amount, stride, height; -@@ -677,6 +635,15 @@ +@@ -681,6 +639,15 @@ return 0; } @@ -343,7 +343,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive static int nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) -@@ -730,15 +697,43 @@ +@@ -734,15 +701,43 @@ { struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); @@ -388,7 +388,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive if (dev_priv->card_type < NV_50) ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem); else -@@ -752,6 +747,7 @@ +@@ -756,6 +751,7 @@ no_wait_gpu, new_mem); } @@ -396,7 +396,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive if (chan == dev_priv->channel) mutex_unlock(&chan->mutex); return ret; -@@ -762,6 +758,7 @@ +@@ -766,6 +762,7 @@ bool no_wait_reserve, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { @@ -404,7 +404,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; struct ttm_placement placement; struct ttm_mem_reg tmp_mem; -@@ -781,7 +778,23 @@ +@@ -785,7 +782,23 @@ if (ret) goto out; @@ -428,7 +428,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive if (ret) goto out; -@@ -824,6 +837,36 @@ +@@ -828,6 +841,36 @@ return ret; } @@ -465,7 +465,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive static int nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, struct nouveau_tile_reg **new_tile) -@@ -831,19 +874,13 @@ +@@ -835,19 +878,13 @@ struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); struct drm_device *dev = dev_priv->dev; struct nouveau_bo *nvbo = nouveau_bo(bo); @@ -489,7 +489,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, nvbo->tile_mode, nvbo->tile_flags); -@@ -860,11 +897,8 @@ +@@ -864,11 +901,8 @@ struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); struct drm_device *dev = dev_priv->dev; @@ -503,7 +503,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive } static int -@@ -878,9 +912,11 @@ +@@ -882,9 +916,11 @@ struct nouveau_tile_reg *new_tile = NULL; int ret = 0; @@ -518,7 +518,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive /* Fake bo copy. */ if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { -@@ -911,10 +947,12 @@ +@@ -915,10 +951,12 @@ ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); out: @@ -535,7 +535,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive return ret; } -@@ -955,7 +993,7 @@ +@@ -959,7 +997,7 @@ break; case TTM_PL_VRAM: { @@ -544,7 +544,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive u8 page_shift; if (!dev_priv->bar1_vm) { -@@ -966,23 +1004,23 @@ +@@ -970,23 +1008,23 @@ } if (dev_priv->card_type == NV_C0) @@ -573,7 +573,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive if (dev_priv->card_type == NV_50) /*XXX*/ mem->bus.offset -= 0x0020000000ULL; mem->bus.base = pci_resource_start(dev->pdev, 1); -@@ -999,16 +1037,16 @@ +@@ -1003,16 +1041,16 @@ nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); @@ -594,7 +594,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive } static int -@@ -1058,6 +1096,7 @@ +@@ -1062,6 +1100,7 @@ .invalidate_caches = nouveau_bo_invalidate_caches, .init_mem_type = nouveau_bo_init_mem_type, .evict_flags = nouveau_bo_evict_flags, @@ -602,9 +602,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_bo.c linux-2.6/drive .move = nouveau_bo_move, .verify_access = nouveau_bo_verify_access, .sync_obj_signaled = __nouveau_fence_signalled, -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_channel.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_channel.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_channel.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_channel.c 2011-02-22 14:16:21.581230459 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_channel.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_channel.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_channel.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_channel.c 2011-03-09 18:30:58.000000000 +0100 @@ -35,7 +35,7 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_bo *pb = chan->pushbuf_bo; @@ -624,9 +624,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_channel.c linux-2.6/ if (ret) { NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret); return NULL; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_display.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_display.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_display.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_display.c 2011-02-22 14:16:21.582230439 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_display.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_display.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_display.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_display.c 2011-03-09 18:30:58.000000000 +0100 @@ -32,6 +32,7 @@ #include "nouveau_hw.h" #include "nouveau_crtc.h" @@ -758,10 +758,10 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_display.c linux-2.6/ kfree(s); spin_unlock_irqrestore(&dev->event_lock, flags); -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dma.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_dma.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dma.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_dma.c 2011-02-22 14:16:21.582230439 +0100 -@@ -96,13 +96,15 @@ +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_dma.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_dma.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_dma.c 2011-03-12 22:37:55.420744532 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_dma.c 2011-03-09 18:30:58.000000000 +0100 +@@ -97,13 +97,15 @@ OUT_RING(chan, 0); /* Initialise NV_MEMORY_TO_MEMORY_FORMAT */ @@ -781,9 +781,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dma.c linux-2.6/driv /* Sit back and pray the channel works.. */ FIRE_RING(chan); -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dma.h linux-2.6/drivers/gpu/drm/nouveau/nouveau_dma.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dma.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_dma.h 2011-02-22 14:16:21.582230439 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_dma.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_dma.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_dma.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_dma.h 2011-03-09 18:30:58.000000000 +0100 @@ -61,8 +61,6 @@ NvM2MF = 0x80000001, NvDmaFB = 0x80000002, @@ -810,9 +810,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dma.h linux-2.6/driv }; #define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dp.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_dp.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dp.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_dp.c 2011-02-22 14:16:21.582230439 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_dp.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_dp.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_dp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_dp.c 2011-03-09 18:30:58.000000000 +0100 @@ -175,7 +175,6 @@ { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); @@ -829,9 +829,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_dp.c linux-2.6/drive ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2); if (ret) -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_drv.h linux-2.6/drivers/gpu/drm/nouveau/nouveau_drv.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_drv.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_drv.h 2011-02-22 14:16:21.583230419 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_drv.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_drv.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_drv.h 2011-03-12 22:37:55.423744472 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_drv.h 2011-03-09 18:30:58.000000000 +0100 @@ -57,7 +57,7 @@ #include "nouveau_util.h" @@ -953,7 +953,16 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_drv.h linux-2.6/driv /* nouveau_notifier.c */ extern int nouveau_notifier_init_channel(struct nouveau_channel *); -@@ -1294,7 +1295,7 @@ +@@ -1076,7 +1077,7 @@ + /* nv50_fb.c */ + extern int nv50_fb_init(struct drm_device *); + extern void nv50_fb_takedown(struct drm_device *); +-extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); ++extern void nv50_fb_vm_trap(struct drm_device *, int display); + + /* nvc0_fb.c */ + extern int nvc0_fb_init(struct drm_device *); +@@ -1295,7 +1296,7 @@ extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, int size, int align, uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, @@ -962,7 +971,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_drv.h linux-2.6/driv extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); extern int nouveau_bo_unpin(struct nouveau_bo *); extern int nouveau_bo_map(struct nouveau_bo *); -@@ -1355,9 +1356,9 @@ +@@ -1356,9 +1357,9 @@ /* nouveau_gem.c */ extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, @@ -974,9 +983,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_drv.h linux-2.6/driv extern int nouveau_gem_object_new(struct drm_gem_object *); extern void nouveau_gem_object_del(struct drm_gem_object *); extern int nouveau_gem_ioctl_new(struct drm_device *, void *, -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fbcon.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_fbcon.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fbcon.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_fbcon.c 2011-02-22 14:16:21.584230398 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_fbcon.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_fbcon.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_fbcon.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_fbcon.c 2011-03-09 18:30:58.000000000 +0100 @@ -296,8 +296,8 @@ size = mode_cmd.pitch * mode_cmd.height; size = roundup(size, PAGE_SIZE); @@ -988,9 +997,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fbcon.c linux-2.6/dr if (ret) { NV_ERROR(dev, "failed to allocate framebuffer\n"); goto out; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fb.h linux-2.6/drivers/gpu/drm/nouveau/nouveau_fb.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fb.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_fb.h 2011-02-22 14:16:21.584230398 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_fb.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_fb.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_fb.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_fb.h 2011-03-09 18:30:58.000000000 +0100 @@ -30,6 +30,9 @@ struct nouveau_framebuffer { struct drm_framebuffer base; @@ -1001,10 +1010,18 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fb.h linux-2.6/drive }; static inline struct nouveau_framebuffer * -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_fence.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_fence.c 2011-02-22 14:16:21.584230398 +0100 -@@ -32,8 +32,7 @@ +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_fence.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_fence.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_fence.c 2011-03-09 18:30:58.000000000 +0100 +@@ -27,13 +27,15 @@ + #include "drmP.h" + #include "drm.h" + ++#include ++#include ++ + #include "nouveau_drv.h" + #include "nouveau_ramht.h" #include "nouveau_dma.h" #define USE_REFCNT(dev) (nouveau_private(dev)->chipset >= 0x10) @@ -1014,7 +1031,33 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr struct nouveau_fence { struct nouveau_channel *channel; -@@ -259,11 +258,12 @@ +@@ -230,7 +232,8 @@ + __nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr) + { + unsigned long timeout = jiffies + (3 * DRM_HZ); +- unsigned long sleep_time = jiffies + 1; ++ unsigned long sleep_time = NSEC_PER_MSEC / 1000; ++ ktime_t t; + int ret = 0; + + while (1) { +@@ -244,8 +247,13 @@ + + __set_current_state(intr ? TASK_INTERRUPTIBLE + : TASK_UNINTERRUPTIBLE); +- if (lazy && time_after_eq(jiffies, sleep_time)) +- schedule_timeout(1); ++ if (lazy) { ++ t = ktime_set(0, sleep_time); ++ schedule_hrtimeout(&t, HRTIMER_MODE_REL); ++ sleep_time *= 2; ++ if (sleep_time > NSEC_PER_MSEC) ++ sleep_time = NSEC_PER_MSEC; ++ } + + if (intr && signal_pending(current)) { + ret = -ERESTARTSYS; +@@ -259,11 +267,12 @@ } static struct nouveau_semaphore * @@ -1029,7 +1072,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr if (!USE_SEMA(dev)) return NULL; -@@ -277,9 +277,9 @@ +@@ -277,9 +286,9 @@ goto fail; spin_lock(&dev_priv->fence.lock); @@ -1041,7 +1084,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr spin_unlock(&dev_priv->fence.lock); if (!sema->mem) -@@ -287,7 +287,8 @@ +@@ -287,7 +296,8 @@ kref_init(&sema->ref); sema->dev = dev; @@ -1051,7 +1094,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr return sema; fail: -@@ -296,7 +297,7 @@ +@@ -296,7 +306,7 @@ } static void @@ -1060,7 +1103,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr { struct nouveau_semaphore *sema = container_of(ref, struct nouveau_semaphore, ref); -@@ -318,61 +319,107 @@ +@@ -318,61 +328,107 @@ if (unlikely(!signalled)) nouveau_bo_wr32(dev_priv->fence.bo, sema->mem->start / 4, 1); @@ -1213,7 +1256,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr } /* Delay semaphore destruction until its work is done */ -@@ -383,7 +430,6 @@ +@@ -383,7 +439,6 @@ kref_get(&sema->ref); nouveau_fence_work(fence, semaphore_work, sema); nouveau_fence_unref(&fence); @@ -1221,7 +1264,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr return 0; } -@@ -400,7 +446,7 @@ +@@ -400,7 +455,7 @@ nouveau_fence_signalled(fence))) goto out; @@ -1230,7 +1273,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr if (!sema) { /* Early card or broken userspace, fall back to * software sync. */ -@@ -418,17 +464,17 @@ +@@ -418,17 +473,17 @@ } /* Make wchan wait until it gets signalled */ @@ -1251,7 +1294,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr out: if (chan) nouveau_channel_put_unlocked(&chan); -@@ -449,22 +495,23 @@ +@@ -449,22 +504,23 @@ struct nouveau_gpuobj *obj = NULL; int ret; @@ -1283,7 +1326,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem; ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, -@@ -484,14 +531,20 @@ +@@ -484,14 +540,20 @@ return ret; BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1); OUT_RING(chan, NvSema); @@ -1305,7 +1348,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr return 0; } -@@ -519,12 +572,13 @@ +@@ -519,12 +581,13 @@ nouveau_fence_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -1321,9 +1364,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_fence.c linux-2.6/dr if (ret) return ret; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_gem.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_gem.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_gem.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_gem.c 2011-02-22 14:16:21.585230377 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_gem.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_gem.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_gem.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_gem.c 2011-03-09 18:30:58.000000000 +0100 @@ -61,19 +61,36 @@ int @@ -1417,9 +1460,36 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_gem.c linux-2.6/driv (write_domains ? write_domains : read_domains); uint32_t pref_flags = 0, valid_flags = 0; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_mem.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_mem.c 2011-02-22 14:16:21.587230337 +0100 +@@ -592,7 +600,7 @@ + if (push[i].bo_index >= req->nr_buffers) { + NV_ERROR(dev, "push %d buffer not in list\n", i); + ret = -EINVAL; +- goto out; ++ goto out_prevalid; + } + + bo[push[i].bo_index].read_domains |= (1 << 31); +@@ -604,7 +612,7 @@ + if (ret) { + if (ret != -ERESTARTSYS) + NV_ERROR(dev, "validate: %d\n", ret); +- goto out; ++ goto out_prevalid; + } + + /* Apply any relocations that are required */ +@@ -697,6 +705,8 @@ + out: + validate_fini(&op, fence); + nouveau_fence_unref(&fence); ++ ++out_prevalid: + kfree(bo); + kfree(push); + +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_mem.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_mem.c 2011-03-12 22:37:55.425744434 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_mem.c 2011-03-09 18:30:58.000000000 +0100 @@ -152,7 +152,6 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -1451,7 +1521,48 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6/driv ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits)); if (ret) -@@ -455,13 +460,17 @@ +@@ -419,14 +424,32 @@ + } + + /* reserve space at end of VRAM for PRAMIN */ +- if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 || +- dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) +- dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024); +- else +- if (dev_priv->card_type >= NV_40) +- dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024); +- else +- dev_priv->ramin_rsvd_vram = (512 * 1024); ++ if (dev_priv->card_type >= NV_50) { ++ dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024; ++ } else ++ if (dev_priv->card_type >= NV_40) { ++ u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8); ++ u32 rsvd; ++ ++ /* estimate grctx size, the magics come from nv40_grctx.c */ ++ if (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs; ++ else if (dev_priv->chipset < 0x43) rsvd = 0x4f00 * vs; ++ else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs; ++ else rsvd = 0x4a40 * vs; ++ rsvd += 16 * 1024; ++ rsvd *= dev_priv->engine.fifo.channels; ++ ++ /* pciegart table */ ++ if (drm_device_is_pcie(dev)) ++ rsvd += 512 * 1024; ++ ++ /* object storage */ ++ rsvd += 512 * 1024; ++ ++ dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096); ++ } else { ++ dev_priv->ramin_rsvd_vram = 512 * 1024; ++ } + + ret = dev_priv->engine.vram.init(dev); + if (ret) +@@ -455,13 +478,17 @@ return ret; } @@ -1476,7 +1587,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6/driv } dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1), -@@ -666,13 +675,14 @@ +@@ -666,13 +693,14 @@ { struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev); struct nouveau_mm *mm; @@ -1495,7 +1606,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6/driv if (ret) return ret; -@@ -700,9 +710,15 @@ +@@ -700,9 +728,15 @@ { struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev); struct nouveau_vram_engine *vram = &dev_priv->engine.vram; @@ -1512,7 +1623,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6/driv } static int -@@ -715,7 +731,7 @@ +@@ -715,7 +749,7 @@ struct nouveau_vram_engine *vram = &dev_priv->engine.vram; struct drm_device *dev = dev_priv->dev; struct nouveau_bo *nvbo = nouveau_bo(bo); @@ -1521,16 +1632,16 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6/driv u32 size_nc = 0; int ret; -@@ -724,7 +740,7 @@ +@@ -724,7 +758,7 @@ ret = vram->get(dev, mem->num_pages << PAGE_SHIFT, mem->page_alignment << PAGE_SHIFT, size_nc, - (nvbo->tile_flags >> 8) & 0xff, &node); + (nvbo->tile_flags >> 8) & 0x3ff, &node); - if (ret) - return ret; - -@@ -769,3 +785,84 @@ + if (ret) { + mem->mm_node = NULL; + return (ret == -ENOSPC) ? 0 : ret; +@@ -771,3 +805,84 @@ nouveau_vram_manager_del, nouveau_vram_manager_debug }; @@ -1615,9 +1726,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mem.c linux-2.6/driv + nouveau_gart_manager_del, + nouveau_gart_manager_debug +}; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mm.h linux-2.6/drivers/gpu/drm/nouveau/nouveau_mm.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mm.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_mm.h 2011-02-22 14:16:21.587230337 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_mm.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_mm.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_mm.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_mm.h 2011-03-09 18:30:58.000000000 +0100 @@ -53,13 +53,13 @@ int nv50_vram_init(struct drm_device *); @@ -1635,9 +1746,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_mm.h linux-2.6/drive bool nvc0_vram_flags_valid(struct drm_device *, u32 tile_flags); #endif -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_notifier.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_notifier.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_notifier.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_notifier.c 2011-02-22 14:16:21.587230337 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_notifier.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_notifier.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_notifier.c 2011-03-12 22:37:55.427744395 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_notifier.c 2011-03-09 18:30:58.000000000 +0100 @@ -39,12 +39,11 @@ int ret; @@ -1654,15 +1765,15 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_notifier.c linux-2.6 if (ret) return ret; -@@ -99,6 +98,7 @@ - int size, uint32_t *b_offset) +@@ -100,6 +99,7 @@ + uint32_t *b_offset) { struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *nobj = NULL; struct drm_mm_node *mem; uint32_t offset; -@@ -112,11 +112,16 @@ +@@ -114,11 +114,16 @@ return -ENOMEM; } @@ -1684,9 +1795,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_notifier.c linux-2.6 offset += mem->start; ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, offset, -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_object.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_object.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_object.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_object.c 2011-02-22 14:16:21.588230317 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_object.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_object.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_object.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_object.c 2011-03-09 18:30:58.000000000 +0100 @@ -36,6 +36,7 @@ #include "nouveau_drm.h" #include "nouveau_ramht.h" @@ -1761,9 +1872,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_object.c linux-2.6/d } /* VRAM ctxdma */ -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_ramht.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_ramht.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_ramht.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_ramht.c 2011-02-22 14:16:21.589230297 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_ramht.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_ramht.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_ramht.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_ramht.c 2011-03-09 18:30:58.000000000 +0100 @@ -114,7 +114,9 @@ (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); } else { @@ -1775,9 +1886,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_ramht.c linux-2.6/dr } else { ctx = (gpuobj->cinst >> 4) | ((gpuobj->engine << -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_sgdma.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_sgdma.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_sgdma.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_sgdma.c 2011-02-22 14:16:21.589230297 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_sgdma.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_sgdma.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_sgdma.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_sgdma.c 2011-03-09 18:30:58.000000000 +0100 @@ -74,8 +74,24 @@ } } @@ -2089,7 +2200,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_sgdma.c linux-2.6/dr return &nvbe->backend; } -@@ -210,21 +409,65 @@ +@@ -210,21 +409,64 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *gpuobj = NULL; @@ -2110,8 +2221,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_sgdma.c linux-2.6/dr - ret = nouveau_gpuobj_new(dev, NULL, obj_size, 16, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, &gpuobj); -+ if (dev_priv->card_type >= NV_50 || -+ dev_priv->ramin_rsvd_vram >= 2 * 1024 * 1024) ++ if (dev_priv->card_type >= NV_50 || drm_device_is_pcie(dev)) + aper_size = 512 * 1024 * 1024; + else + aper_size = 64 * 1024 * 1024; @@ -2169,7 +2279,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_sgdma.c linux-2.6/dr if (ret) { NV_ERROR(dev, "Error creating sgdma object: %d\n", ret); return ret; -@@ -236,25 +479,14 @@ +@@ -236,25 +478,14 @@ (0 << 14) /* RW */ | (2 << 16) /* PCI */); nv_wo32(gpuobj, 4, aper_size - 1); @@ -2197,7 +2307,7 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_sgdma.c linux-2.6/dr return 0; } -@@ -264,7 +496,13 @@ +@@ -264,7 +495,13 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; nouveau_gpuobj_ref(NULL, &dev_priv->gart_info.sg_ctxdma); @@ -2212,9 +2322,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_sgdma.c linux-2.6/dr } uint32_t -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_state.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_state.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_state.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_state.c 2011-02-22 14:16:21.590230277 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_state.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_state.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_state.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_state.c 2011-03-09 18:30:58.000000000 +0100 @@ -544,7 +544,6 @@ nouveau_card_init_channel(struct drm_device *dev) { @@ -2305,9 +2415,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_state.c linux-2.6/dr break; case NOUVEAU_GETPARAM_GRAPH_UNITS: /* NV40 and NV50 versions are quite different, but register -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_temp.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_temp.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_temp.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_temp.c 2011-02-22 14:16:21.590230277 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_temp.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_temp.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_temp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_temp.c 2011-03-09 18:30:58.000000000 +0100 @@ -239,11 +239,9 @@ probe_monitoring_device(struct nouveau_i2c_chan *i2c, struct i2c_board_info *info) @@ -2321,9 +2431,65 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_temp.c linux-2.6/dri client = i2c_new_device(&i2c->adapter, info); if (!client) -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_vm.c linux-2.6/drivers/gpu/drm/nouveau/nouveau_vm.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_vm.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_vm.c 2011-02-22 14:16:21.591230257 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_util.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_util.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_util.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_util.c 2011-03-09 18:30:58.000000000 +0100 +@@ -47,18 +47,27 @@ + printk(" (unknown bits 0x%08x)", value); + } + +-void +-nouveau_enum_print(const struct nouveau_enum *en, u32 value) ++const struct nouveau_enum * ++nouveau_enum_find(const struct nouveau_enum *en, u32 value) + { + while (en->name) { +- if (value == en->value) { +- printk("%s", en->name); +- return; +- } +- ++ if (en->value == value) ++ return en; + en++; + } + ++ return NULL; ++} ++ ++void ++nouveau_enum_print(const struct nouveau_enum *en, u32 value) ++{ ++ en = nouveau_enum_find(en, value); ++ if (en) { ++ printk("%s", en->name); ++ return; ++ } ++ + printk("(unknown enum 0x%08x)", value); + } + +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_util.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_util.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_util.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_util.h 2011-03-09 18:30:58.000000000 +0100 +@@ -36,10 +36,14 @@ + struct nouveau_enum { + u32 value; + const char *name; ++ void *data; + }; + + void nouveau_bitfield_print(const struct nouveau_bitfield *, u32 value); + void nouveau_enum_print(const struct nouveau_enum *, u32 value); ++const struct nouveau_enum * ++nouveau_enum_find(const struct nouveau_enum *, u32 value); ++ + int nouveau_ratelimit(void); + + #endif +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_vm.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_vm.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_vm.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_vm.c 2011-03-09 18:30:58.000000000 +0100 @@ -28,7 +28,7 @@ #include "nouveau_vm.h" @@ -2388,9 +2554,29 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_vm.c linux-2.6/drive num -= len; pte += len; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_vm.h linux-2.6/drivers/gpu/drm/nouveau/nouveau_vm.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_vm.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nouveau_vm.h 2011-02-22 14:16:21.591230257 +0100 +@@ -311,18 +314,7 @@ + vm->spg_shift = 12; + vm->lpg_shift = 17; + pgt_bits = 27; +- +- /* Should be 4096 everywhere, this is a hack that's +- * currently necessary to avoid an elusive bug that +- * causes corruption when mixing small/large pages +- */ +- if (length < (1ULL << 40)) +- block = 4096; +- else { +- block = (1 << pgt_bits); +- if (length < block) +- block = length; +- } ++ block = 4096; + } else { + kfree(vm); + return -ENOSYS; +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_vm.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_vm.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nouveau_vm.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nouveau_vm.h 2011-03-09 18:30:58.000000000 +0100 @@ -67,9 +67,10 @@ void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, struct nouveau_gpuobj *pgt[2]); @@ -2442,9 +2628,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nouveau_vm.h linux-2.6/drive void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt); void nvc0_vm_flush(struct nouveau_vm *); -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv04_crtc.c linux-2.6/drivers/gpu/drm/nouveau/nv04_crtc.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv04_crtc.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv04_crtc.c 2011-02-22 14:16:21.592230236 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv04_crtc.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv04_crtc.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv04_crtc.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv04_crtc.c 2011-03-09 18:30:58.000000000 +0100 @@ -1031,7 +1031,7 @@ drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); @@ -2454,9 +2640,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv04_crtc.c linux-2.6/driver if (!ret) { ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); if (!ret) -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv04_fifo.c linux-2.6/drivers/gpu/drm/nouveau/nv04_fifo.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv04_fifo.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv04_fifo.c 2011-02-22 14:16:21.593230215 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv04_fifo.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv04_fifo.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv04_fifo.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv04_fifo.c 2011-03-09 18:30:58.000000000 +0100 @@ -379,6 +379,15 @@ return handled; } @@ -2497,9 +2683,18 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv04_fifo.c linux-2.6/driver if (dma_get != dma_put) nv_wr32(dev, 0x003244, dma_put); -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv40_fb.c linux-2.6/drivers/gpu/drm/nouveau/nv40_fb.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv40_fb.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv40_fb.c 2011-02-22 14:16:21.596230155 +0100 +@@ -505,7 +516,7 @@ + + if (dev_priv->card_type == NV_50) { + if (status & 0x00000010) { +- nv50_fb_vm_trap(dev, 1, "PFIFO_BAR_FAULT"); ++ nv50_fb_vm_trap(dev, nouveau_ratelimit()); + status &= ~0x00000010; + nv_wr32(dev, 0x002100, 0x00000010); + } +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv40_fb.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv40_fb.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv40_fb.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv40_fb.c 2011-03-09 18:30:58.000000000 +0100 @@ -24,6 +24,53 @@ } } @@ -2573,9 +2768,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv40_fb.c linux-2.6/drivers/ switch (dev_priv->chipset) { case 0x40: -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_crtc.c linux-2.6/drivers/gpu/drm/nouveau/nv50_crtc.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_crtc.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_crtc.c 2011-02-22 14:16:21.598230115 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_crtc.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_crtc.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_crtc.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_crtc.c 2011-03-09 18:30:58.000000000 +0100 @@ -65,7 +65,7 @@ { struct drm_device *dev = nv_crtc->base.dev; @@ -2874,9 +3069,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_crtc.c linux-2.6/driver if (!ret) { ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); if (!ret) -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_cursor.c linux-2.6/drivers/gpu/drm/nouveau/nv50_cursor.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_cursor.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_cursor.c 2011-02-22 14:16:21.598230115 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_cursor.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_cursor.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_cursor.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_cursor.c 2011-03-09 18:30:58.000000000 +0100 @@ -36,9 +36,9 @@ static void nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update) @@ -2901,9 +3096,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_cursor.c linux-2.6/driv int ret; NV_DEBUG_KMS(dev, "\n"); -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_dac.c linux-2.6/drivers/gpu/drm/nouveau/nv50_dac.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_dac.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_dac.c 2011-02-22 14:16:21.599230095 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_dac.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_dac.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_dac.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_dac.c 2011-03-09 18:30:58.000000000 +0100 @@ -41,8 +41,7 @@ { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); @@ -2924,9 +3119,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_dac.c linux-2.6/drivers struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc); uint32_t mode_ctl = 0, mode_ctl2 = 0; int ret; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_display.c linux-2.6/drivers/gpu/drm/nouveau/nv50_display.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_display.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_display.c 2011-02-22 14:16:21.599230095 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_display.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_display.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_display.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_display.c 2011-03-09 18:30:58.000000000 +0100 @@ -24,6 +24,7 @@ * */ @@ -3269,9 +3464,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_display.c linux-2.6/dri delayed |= clock; intr1 &= ~clock; } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_display.h linux-2.6/drivers/gpu/drm/nouveau/nv50_display.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_display.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_display.h 2011-02-22 14:16:21.599230095 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_display.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_display.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_display.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_display.h 2011-03-09 18:30:58.000000000 +0100 @@ -35,7 +35,36 @@ #include "nouveau_crtc.h" #include "nv50_evo.h" @@ -3326,9 +3521,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_display.h linux-2.6/dri + u64 base, u64 size, struct nouveau_gpuobj **); + #endif /* __NV50_DISPLAY_H__ */ -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_evo.c linux-2.6/drivers/gpu/drm/nouveau/nv50_evo.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_evo.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_evo.c 2011-02-22 14:16:21.599230095 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_evo.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_evo.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_evo.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_evo.c 2011-03-09 18:30:58.000000000 +0100 @@ -27,20 +27,17 @@ #include "nouveau_drv.h" #include "nouveau_dma.h" @@ -3745,9 +3940,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_evo.c linux-2.6/drivers + + nv50_evo_destroy(dev); } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_evo.h linux-2.6/drivers/gpu/drm/nouveau/nv50_evo.h ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_evo.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_evo.h 2011-02-22 14:16:21.600230075 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_evo.h linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_evo.h +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_evo.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_evo.h 2011-03-09 18:30:58.000000000 +0100 @@ -27,12 +27,6 @@ #ifndef __NV50_EVO_H__ #define __NV50_EVO_H__ @@ -3769,9 +3964,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_evo.h linux-2.6/drivers +#define NV50_EVO_CRTC_UNK904 0x00000904 #endif -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_fb.c linux-2.6/drivers/gpu/drm/nouveau/nv50_fb.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_fb.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_fb.c 2011-02-22 14:16:21.600230075 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_fb.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_fb.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_fb.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_fb.c 2011-03-09 18:30:58.000000000 +0100 @@ -8,31 +8,61 @@ dma_addr_t r100c08; }; @@ -3838,29 +4033,198 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_fb.c linux-2.6/drivers/ return 0; } -@@ -81,18 +111,7 @@ +@@ -81,26 +111,112 @@ void nv50_fb_takedown(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nv50_fb_priv *priv; -- ++ nv50_fb_destroy(dev); ++} + - priv = dev_priv->engine.fb.priv; - if (!priv) - return; - dev_priv->engine.fb.priv = NULL; -- ++static struct nouveau_enum vm_dispatch_subclients[] = { ++ { 0x00000000, "GRCTX", NULL }, ++ { 0x00000001, "NOTIFY", NULL }, ++ { 0x00000002, "QUERY", NULL }, ++ { 0x00000003, "COND", NULL }, ++ { 0x00000004, "M2M_IN", NULL }, ++ { 0x00000005, "M2M_OUT", NULL }, ++ { 0x00000006, "M2M_NOTIFY", NULL }, ++ {} ++}; + - pci_unmap_page(dev->pdev, priv->r100c08, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - __free_page(priv->r100c08_page); - kfree(priv); -+ nv50_fb_destroy(dev); - } +-} ++static struct nouveau_enum vm_ccache_subclients[] = { ++ { 0x00000000, "CB", NULL }, ++ { 0x00000001, "TIC", NULL }, ++ { 0x00000002, "TSC", NULL }, ++ {} ++}; ++ ++static struct nouveau_enum vm_prop_subclients[] = { ++ { 0x00000000, "RT0", NULL }, ++ { 0x00000001, "RT1", NULL }, ++ { 0x00000002, "RT2", NULL }, ++ { 0x00000003, "RT3", NULL }, ++ { 0x00000004, "RT4", NULL }, ++ { 0x00000005, "RT5", NULL }, ++ { 0x00000006, "RT6", NULL }, ++ { 0x00000007, "RT7", NULL }, ++ { 0x00000008, "ZETA", NULL }, ++ { 0x00000009, "LOCAL", NULL }, ++ { 0x0000000a, "GLOBAL", NULL }, ++ { 0x0000000b, "STACK", NULL }, ++ { 0x0000000c, "DST2D", NULL }, ++ {} ++}; ++ ++static struct nouveau_enum vm_pfifo_subclients[] = { ++ { 0x00000000, "PUSHBUF", NULL }, ++ { 0x00000001, "SEMAPHORE", NULL }, ++ {} ++}; ++ ++static struct nouveau_enum vm_bar_subclients[] = { ++ { 0x00000000, "FB", NULL }, ++ { 0x00000001, "IN", NULL }, ++ {} ++}; ++ ++static struct nouveau_enum vm_client[] = { ++ { 0x00000000, "STRMOUT", NULL }, ++ { 0x00000003, "DISPATCH", vm_dispatch_subclients }, ++ { 0x00000004, "PFIFO_WRITE", NULL }, ++ { 0x00000005, "CCACHE", vm_ccache_subclients }, ++ { 0x00000006, "PPPP", NULL }, ++ { 0x00000007, "CLIPID", NULL }, ++ { 0x00000008, "PFIFO_READ", NULL }, ++ { 0x00000009, "VFETCH", NULL }, ++ { 0x0000000a, "TEXTURE", NULL }, ++ { 0x0000000b, "PROP", vm_prop_subclients }, ++ { 0x0000000c, "PVP", NULL }, ++ { 0x0000000d, "PBSP", NULL }, ++ { 0x0000000e, "PCRYPT", NULL }, ++ { 0x0000000f, "PCOUNTER", NULL }, ++ { 0x00000011, "PDAEMON", NULL }, ++ {} ++}; ++ ++static struct nouveau_enum vm_engine[] = { ++ { 0x00000000, "PGRAPH", NULL }, ++ { 0x00000001, "PVP", NULL }, ++ { 0x00000004, "PEEPHOLE", NULL }, ++ { 0x00000005, "PFIFO", vm_pfifo_subclients }, ++ { 0x00000006, "BAR", vm_bar_subclients }, ++ { 0x00000008, "PPPP", NULL }, ++ { 0x00000009, "PBSP", NULL }, ++ { 0x0000000a, "PCRYPT", NULL }, ++ { 0x0000000b, "PCOUNTER", NULL }, ++ { 0x0000000c, "SEMAPHORE_BG", NULL }, ++ { 0x0000000d, "PCOPY", NULL }, ++ { 0x0000000e, "PDAEMON", NULL }, ++ {} ++}; ++ ++static struct nouveau_enum vm_fault[] = { ++ { 0x00000000, "PT_NOT_PRESENT", NULL }, ++ { 0x00000001, "PT_TOO_SHORT", NULL }, ++ { 0x00000002, "PAGE_NOT_PRESENT", NULL }, ++ { 0x00000003, "PAGE_SYSTEM_ONLY", NULL }, ++ { 0x00000004, "PAGE_READ_ONLY", NULL }, ++ { 0x00000006, "NULL_DMAOBJ", NULL }, ++ { 0x00000007, "WRONG_MEMTYPE", NULL }, ++ { 0x0000000b, "VRAM_LIMIT", NULL }, ++ { 0x0000000f, "DMAOBJ_LIMIT", NULL }, ++ {} ++}; void -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_fifo.c linux-2.6/drivers/gpu/drm/nouveau/nv50_fifo.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_fifo.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_fifo.c 2011-02-22 14:16:21.600230075 +0100 +-nv50_fb_vm_trap(struct drm_device *dev, int display, const char *name) ++nv50_fb_vm_trap(struct drm_device *dev, int display) + { + struct drm_nouveau_private *dev_priv = dev->dev_private; ++ const struct nouveau_enum *en, *cl; + unsigned long flags; + u32 trap[6], idx, chinst; ++ u8 st0, st1, st2, st3; + int i, ch; + + idx = nv_rd32(dev, 0x100c90); +@@ -117,8 +233,8 @@ + if (!display) + return; + ++ /* lookup channel id */ + chinst = (trap[2] << 16) | trap[1]; +- + spin_lock_irqsave(&dev_priv->channels.lock, flags); + for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) { + struct nouveau_channel *chan = dev_priv->channels.ptr[ch]; +@@ -131,9 +247,48 @@ + } + spin_unlock_irqrestore(&dev_priv->channels.lock, flags); + +- NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x " +- "channel %d (0x%08x)\n", +- name, (trap[5] & 0x100 ? "read" : "write"), +- trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, +- trap[0], ch, chinst); ++ /* decode status bits into something more useful */ ++ if (dev_priv->chipset < 0xa3 || ++ dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) { ++ st0 = (trap[0] & 0x0000000f) >> 0; ++ st1 = (trap[0] & 0x000000f0) >> 4; ++ st2 = (trap[0] & 0x00000f00) >> 8; ++ st3 = (trap[0] & 0x0000f000) >> 12; ++ } else { ++ st0 = (trap[0] & 0x000000ff) >> 0; ++ st1 = (trap[0] & 0x0000ff00) >> 8; ++ st2 = (trap[0] & 0x00ff0000) >> 16; ++ st3 = (trap[0] & 0xff000000) >> 24; ++ } ++ ++ NV_INFO(dev, "VM: trapped %s at 0x%02x%04x%04x on ch %d [0x%08x] ", ++ (trap[5] & 0x00000100) ? "read" : "write", ++ trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, ch, chinst); ++ ++ en = nouveau_enum_find(vm_engine, st0); ++ if (en) ++ printk("%s/", en->name); ++ else ++ printk("%02x/", st0); ++ ++ cl = nouveau_enum_find(vm_client, st2); ++ if (cl) ++ printk("%s/", cl->name); ++ else ++ printk("%02x/", st2); ++ ++ if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3); ++ else if (en && en->data) cl = nouveau_enum_find(en->data, st3); ++ else cl = NULL; ++ if (cl) ++ printk("%s", cl->name); ++ else ++ printk("%02x", st3); ++ ++ printk(" reason: "); ++ en = nouveau_enum_find(vm_fault, st1); ++ if (en) ++ printk("%s\n", en->name); ++ else ++ printk("0x%08x\n", st1); + } +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_fifo.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_fifo.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_fifo.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_fifo.c 2011-03-09 18:30:58.000000000 +0100 @@ -149,6 +149,7 @@ nv_wr32(dev, 0x3204, 0); nv_wr32(dev, 0x3210, 0); @@ -3878,9 +4242,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_fifo.c linux-2.6/driver nv_wo32(ramfc, 0x60, 0x7fffffff); nv_wo32(ramfc, 0x40, 0x00000000); nv_wo32(ramfc, 0x7c, 0x30000001); -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_gpio.c linux-2.6/drivers/gpu/drm/nouveau/nv50_gpio.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_gpio.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_gpio.c 2011-02-22 14:16:21.600230075 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_gpio.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_gpio.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_gpio.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_gpio.c 2011-03-09 18:30:58.000000000 +0100 @@ -137,6 +137,7 @@ struct nv50_gpio_priv *priv = pgpio->priv; struct nv50_gpio_handler *gpioh, *tmp; @@ -3931,10 +4295,73 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_gpio.c linux-2.6/driver } spin_unlock(&priv->lock); } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_graph.c linux-2.6/drivers/gpu/drm/nouveau/nv50_graph.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_graph.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_graph.c 2011-02-22 14:16:21.601230054 +0100 -@@ -409,12 +409,7 @@ +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_graph.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_graph.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_graph.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_graph.c 2011-03-09 18:30:58.000000000 +0100 +@@ -95,13 +95,41 @@ + } + + static void +-nv50_graph_init_regs(struct drm_device *dev) ++nv50_graph_init_zcull(struct drm_device *dev) + { ++ struct drm_nouveau_private *dev_priv = dev->dev_private; ++ int i; ++ + NV_DEBUG(dev, "\n"); + +- nv_wr32(dev, NV04_PGRAPH_DEBUG_3, +- (1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */); +- nv_wr32(dev, 0x402ca8, 0x800); ++ switch (dev_priv->chipset & 0xf0) { ++ case 0x50: ++ case 0x80: ++ case 0x90: ++ nv_wr32(dev, 0x402ca8, 0x00000800); ++ break; ++ case 0xa0: ++ default: ++ nv_wr32(dev, 0x402cc0, 0x00000000); ++ if (dev_priv->chipset == 0xa0 || ++ dev_priv->chipset == 0xaa || ++ dev_priv->chipset == 0xac) { ++ nv_wr32(dev, 0x402ca8, 0x00000802); ++ } else { ++ nv_wr32(dev, 0x402cc0, 0x00000000); ++ nv_wr32(dev, 0x402ca8, 0x00000002); ++ } ++ ++ break; ++ } ++ ++ /* zero out zcull regions */ ++ for (i = 0; i < 8; i++) { ++ nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000); ++ nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000); ++ nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000); ++ nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000); ++ } + } + + static int +@@ -136,6 +164,7 @@ + } + kfree(cp); + ++ nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */ + nv_wr32(dev, 0x400320, 4); + nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); + nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0); +@@ -151,7 +180,7 @@ + + nv50_graph_init_reset(dev); + nv50_graph_init_regs__nv(dev); +- nv50_graph_init_regs(dev); ++ nv50_graph_init_zcull(dev); + + ret = nv50_graph_init_ctxctl(dev); + if (ret) +@@ -409,12 +438,7 @@ nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) { @@ -3948,7 +4375,129 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_graph.c linux-2.6/drive return 0; } -@@ -912,10 +907,10 @@ +@@ -526,11 +550,11 @@ + + static struct nouveau_enum nv50_mp_exec_error_names[] = + { +- { 3, "STACK_UNDERFLOW" }, +- { 4, "QUADON_ACTIVE" }, +- { 8, "TIMEOUT" }, +- { 0x10, "INVALID_OPCODE" }, +- { 0x40, "BREAKPOINT" }, ++ { 3, "STACK_UNDERFLOW", NULL }, ++ { 4, "QUADON_ACTIVE", NULL }, ++ { 8, "TIMEOUT", NULL }, ++ { 0x10, "INVALID_OPCODE", NULL }, ++ { 0x40, "BREAKPOINT", NULL }, + {} + }; + +@@ -558,47 +582,47 @@ + + /* There must be a *lot* of these. Will take some time to gather them up. */ + struct nouveau_enum nv50_data_error_names[] = { +- { 0x00000003, "INVALID_QUERY_OR_TEXTURE" }, +- { 0x00000004, "INVALID_VALUE" }, +- { 0x00000005, "INVALID_ENUM" }, +- { 0x00000008, "INVALID_OBJECT" }, +- { 0x00000009, "READ_ONLY_OBJECT" }, +- { 0x0000000a, "SUPERVISOR_OBJECT" }, +- { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT" }, +- { 0x0000000c, "INVALID_BITFIELD" }, +- { 0x0000000d, "BEGIN_END_ACTIVE" }, +- { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT" }, +- { 0x0000000f, "VIEWPORT_ID_NEEDS_GP" }, +- { 0x00000010, "RT_DOUBLE_BIND" }, +- { 0x00000011, "RT_TYPES_MISMATCH" }, +- { 0x00000012, "RT_LINEAR_WITH_ZETA" }, +- { 0x00000015, "FP_TOO_FEW_REGS" }, +- { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH" }, +- { 0x00000017, "RT_LINEAR_WITH_MSAA" }, +- { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT" }, +- { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT" }, +- { 0x0000001a, "RT_INVALID_ALIGNMENT" }, +- { 0x0000001b, "SAMPLER_OVER_LIMIT" }, +- { 0x0000001c, "TEXTURE_OVER_LIMIT" }, +- { 0x0000001e, "GP_TOO_MANY_OUTPUTS" }, +- { 0x0000001f, "RT_BPP128_WITH_MS8" }, +- { 0x00000021, "Z_OUT_OF_BOUNDS" }, +- { 0x00000023, "XY_OUT_OF_BOUNDS" }, +- { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED" }, +- { 0x00000028, "CP_NO_REG_SPACE_STRIPED" }, +- { 0x00000029, "CP_NO_REG_SPACE_PACKED" }, +- { 0x0000002a, "CP_NOT_ENOUGH_WARPS" }, +- { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH" }, +- { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS" }, +- { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS" }, +- { 0x0000002e, "CP_NO_BLOCKDIM_LATCH" }, +- { 0x00000031, "ENG2D_FORMAT_MISMATCH" }, +- { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP" }, +- { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT" }, +- { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT" }, +- { 0x00000046, "LAYER_ID_NEEDS_GP" }, +- { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT" }, +- { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT" }, ++ { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL }, ++ { 0x00000004, "INVALID_VALUE", NULL }, ++ { 0x00000005, "INVALID_ENUM", NULL }, ++ { 0x00000008, "INVALID_OBJECT", NULL }, ++ { 0x00000009, "READ_ONLY_OBJECT", NULL }, ++ { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, ++ { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, ++ { 0x0000000c, "INVALID_BITFIELD", NULL }, ++ { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, ++ { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, ++ { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, ++ { 0x00000010, "RT_DOUBLE_BIND", NULL }, ++ { 0x00000011, "RT_TYPES_MISMATCH", NULL }, ++ { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, ++ { 0x00000015, "FP_TOO_FEW_REGS", NULL }, ++ { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, ++ { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, ++ { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, ++ { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, ++ { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, ++ { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, ++ { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, ++ { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, ++ { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, ++ { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, ++ { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, ++ { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, ++ { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, ++ { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, ++ { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, ++ { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, ++ { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, ++ { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, ++ { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, ++ { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, ++ { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, ++ { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, ++ { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, ++ { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, ++ { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, ++ { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, + {} + }; + +@@ -678,7 +702,6 @@ + tps++; + switch (type) { + case 6: /* texture error... unknown for now */ +- nv50_fb_vm_trap(dev, display, name); + if (display) { + NV_ERROR(dev, "magic set %d:\n", i); + for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) +@@ -701,7 +724,6 @@ + uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14); + uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18); + uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c); +- nv50_fb_vm_trap(dev, display, name); + /* 2d engine destination */ + if (ustatus & 0x00000010) { + if (display) { +@@ -912,10 +934,10 @@ printk("\n"); NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x" " %08x %08x %08x\n", @@ -3963,9 +4512,17 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_graph.c linux-2.6/drive } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_instmem.c linux-2.6/drivers/gpu/drm/nouveau/nv50_instmem.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_instmem.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_instmem.c 2011-02-22 14:16:21.602230033 +0100 +@@ -1044,6 +1066,7 @@ + NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d " + "class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, inst, subc, class, mthd, data); ++ nv50_fb_vm_trap(dev, 1); + } + } + +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_instmem.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_instmem.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_instmem.c 2011-03-12 22:37:55.428744375 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_instmem.c 2011-03-09 18:30:58.000000000 +0100 @@ -300,7 +300,7 @@ } @@ -3975,9 +4532,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_instmem.c linux-2.6/dri struct nouveau_vma chan_vma; u32 align; }; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_sor.c linux-2.6/drivers/gpu/drm/nouveau/nv50_sor.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_sor.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_sor.c 2011-02-22 14:16:21.603230013 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_sor.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_sor.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_sor.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_sor.c 2011-03-09 18:30:58.000000000 +0100 @@ -41,8 +41,7 @@ { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); @@ -3998,9 +4555,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_sor.c linux-2.6/drivers struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct drm_device *dev = encoder->dev; struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc); -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_vm.c linux-2.6/drivers/gpu/drm/nouveau/nv50_vm.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_vm.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_vm.c 2011-02-22 14:16:21.603230013 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_vm.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_vm.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_vm.c 2011-03-12 22:37:55.430744335 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_vm.c 2011-03-09 18:30:58.000000000 +0100 @@ -31,7 +31,6 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, struct nouveau_gpuobj *pgt[2]) @@ -4064,9 +4621,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_vm.c linux-2.6/drivers/ nv_wo32(pgt, pte + 0, lower_32_bits(phys)); nv_wo32(pgt, pte + 4, upper_32_bits(phys)); pte += 8; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_vram.c linux-2.6/drivers/gpu/drm/nouveau/nv50_vram.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_vram.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nv50_vram.c 2011-02-22 14:16:21.603230013 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_vram.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_vram.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv50_vram.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv50_vram.c 2011-03-09 18:30:58.000000000 +0100 @@ -48,42 +48,49 @@ } @@ -4186,9 +4743,19 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nv50_vram.c linux-2.6/driver return 0; } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_fifo.c linux-2.6/drivers/gpu/drm/nouveau/nvc0_fifo.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_fifo.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nvc0_fifo.c 2011-02-22 14:16:21.604229993 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv84_crypt.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv84_crypt.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nv84_crypt.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nv84_crypt.c 2011-03-09 18:30:58.000000000 +0100 +@@ -136,5 +136,5 @@ + nv_wr32(dev, 0x102130, stat); + nv_wr32(dev, 0x10200c, 0x10); + +- nv50_fb_vm_trap(dev, show, "PCRYPT"); ++ nv50_fb_vm_trap(dev, show); + } +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_fifo.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_fifo.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_fifo.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_fifo.c 2011-03-09 18:30:58.000000000 +0100 @@ -116,7 +116,7 @@ /* allocate vram for control regs, map into polling area */ @@ -4229,9 +4796,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_fifo.c linux-2.6/driver - - nv_wr32(dev, 0x2140, 0); } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_graph.c linux-2.6/drivers/gpu/drm/nouveau/nvc0_graph.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_graph.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nvc0_graph.c 2011-02-22 14:16:21.604229993 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_graph.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_graph.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_graph.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_graph.c 2011-03-09 18:30:58.000000000 +0100 @@ -299,6 +299,14 @@ } @@ -4287,9 +4854,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_graph.c linux-2.6/drive nv_wr32(dev, 0x400100, 0x00000010); stat &= ~0x00000010; } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_vm.c linux-2.6/drivers/gpu/drm/nouveau/nvc0_vm.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_vm.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nvc0_vm.c 2011-02-22 14:16:21.606229953 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_vm.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_vm.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_vm.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_vm.c 2011-03-09 18:30:58.000000000 +0100 @@ -59,7 +59,7 @@ void @@ -4313,9 +4880,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_vm.c linux-2.6/drivers/ nv_wo32(pgt, pte + 0, lower_32_bits(phys)); nv_wo32(pgt, pte + 4, upper_32_bits(phys)); pte += 8; -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_vram.c linux-2.6/drivers/gpu/drm/nouveau/nvc0_vram.c ---- linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_vram.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/nouveau/nvc0_vram.c 2011-02-22 14:16:21.606229953 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_vram.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_vram.c +--- linux-2.6.38-rc7/drivers/gpu/drm/nouveau/nvc0_vram.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/nouveau/nvc0_vram.c 2011-03-09 18:30:58.000000000 +0100 @@ -26,64 +26,78 @@ #include "nouveau_drv.h" #include "nouveau_mm.h" @@ -4419,9 +4986,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/nouveau/nvc0_vram.c linux-2.6/driver return 0; } -diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/ttm/ttm_bo.c linux-2.6/drivers/gpu/drm/ttm/ttm_bo.c ---- linux-2.6.38-rc5/drivers/gpu/drm/ttm/ttm_bo.c 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/drivers/gpu/drm/ttm/ttm_bo.c 2011-02-22 14:16:21.822225582 +0100 +diff -Naur linux-2.6.38-rc7/drivers/gpu/drm/ttm/ttm_bo.c linux-2.6.38-rc7.nouveau/drivers/gpu/drm/ttm/ttm_bo.c +--- linux-2.6.38-rc7/drivers/gpu/drm/ttm/ttm_bo.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/drivers/gpu/drm/ttm/ttm_bo.c 2011-03-09 18:30:58.000000000 +0100 @@ -406,11 +406,12 @@ } @@ -4436,9 +5003,9 @@ diff -Naur linux-2.6.38-rc5/drivers/gpu/drm/ttm/ttm_bo.c linux-2.6/drivers/gpu/d } if (bdev->driver->move_notify) -diff -Naur linux-2.6.38-rc5/include/drm/nouveau_drm.h linux-2.6/include/drm/nouveau_drm.h ---- linux-2.6.38-rc5/include/drm/nouveau_drm.h 2011-02-16 04:23:45.000000000 +0100 -+++ linux-2.6/include/drm/nouveau_drm.h 2011-02-22 14:16:28.891082551 +0100 +diff -Naur linux-2.6.38-rc7/include/drm/nouveau_drm.h linux-2.6.38-rc7.nouveau/include/drm/nouveau_drm.h +--- linux-2.6.38-rc7/include/drm/nouveau_drm.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7.nouveau/include/drm/nouveau_drm.h 2011-03-09 18:30:58.000000000 +0100 @@ -94,6 +94,7 @@ #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) diff --git a/packages/linux/patches/linux-2.6.38-rc8-300-linux_omap_dss2_20110309.patch b/packages/linux/patches/linux-2.6.38-rc8-300-linux_omap_dss2_20110309.patch new file mode 100644 index 0000000000..6ccc3f801e --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-300-linux_omap_dss2_20110309.patch @@ -0,0 +1,29939 @@ +diff -Naur linux-2.6.38-rc7/arch/arm/configs/omap2plus_defconfig linux-2.6.38-rc7-linux-omap-dss2/arch/arm/configs/omap2plus_defconfig +--- linux-2.6.38-rc7/arch/arm/configs/omap2plus_defconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/configs/omap2plus_defconfig 2011-03-09 13:19:09.493514052 +0100 +@@ -58,6 +58,7 @@ + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_SMP=y ++CONFIG_NR_CPUS=2 + # CONFIG_LOCAL_TIMERS is not set + CONFIG_AEABI=y + CONFIG_LEDS=y +@@ -192,6 +193,17 @@ + CONFIG_FB_MODE_HELPERS=y + CONFIG_FB_TILEBLITTING=y + CONFIG_FB_OMAP_LCD_VGA=y ++CONFIG_OMAP2_DSS=m ++CONFIG_OMAP2_DSS_RFBI=y ++CONFIG_OMAP2_DSS_SDI=y ++CONFIG_OMAP2_DSS_DSI=y ++CONFIG_FB_OMAP2=m ++CONFIG_PANEL_GENERIC_DPI=m ++CONFIG_PANEL_SHARP_LS037V7DW01=m ++CONFIG_PANEL_NEC_NL8048HL11_01B=m ++CONFIG_PANEL_TAAL=m ++CONFIG_PANEL_TPO_TD043MTEA1=m ++CONFIG_PANEL_ACX565AKM=m + CONFIG_BACKLIGHT_LCD_SUPPORT=y + CONFIG_LCD_CLASS_DEVICE=y + CONFIG_LCD_PLATFORM=y +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-ams-delta.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-ams-delta.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-ams-delta.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-ams-delta.c 2011-03-09 13:19:09.778508271 +0100 +@@ -165,7 +165,7 @@ + } + }; + +-static struct omap_lcd_config ams_delta_lcd_config __initdata = { ++static struct omap_lcd_config ams_delta_lcd_config = { + .ctrl_name = "internal", + }; + +@@ -175,7 +175,7 @@ + .pins[0] = 2, + }; + +-static struct omap_board_config_kernel ams_delta_config[] = { ++static struct omap_board_config_kernel ams_delta_config[] __initdata = { + { OMAP_TAG_LCD, &ams_delta_lcd_config }, + }; + +@@ -208,14 +208,14 @@ + .keymap_size = ARRAY_SIZE(ams_delta_keymap), + }; + +-static struct omap_kp_platform_data ams_delta_kp_data = { ++static struct omap_kp_platform_data ams_delta_kp_data __initdata = { + .rows = 8, + .cols = 8, + .keymap_data = &ams_delta_keymap_data, + .delay = 9, + }; + +-static struct platform_device ams_delta_kp_device = { ++static struct platform_device ams_delta_kp_device __initdata = { + .name = "omap-keypad", + .id = -1, + .dev = { +@@ -225,12 +225,12 @@ + .resource = ams_delta_kp_resources, + }; + +-static struct platform_device ams_delta_lcd_device = { ++static struct platform_device ams_delta_lcd_device __initdata = { + .name = "lcd_ams_delta", + .id = -1, + }; + +-static struct platform_device ams_delta_led_device = { ++static struct platform_device ams_delta_led_device __initdata = { + .name = "ams-delta-led", + .id = -1 + }; +@@ -259,7 +259,7 @@ + #define ams_delta_camera_power NULL + #endif + +-static struct soc_camera_link __initdata ams_delta_iclink = { ++static struct soc_camera_link ams_delta_iclink = { + .bus_id = 0, /* OMAP1 SoC camera bus */ + .i2c_adapter_id = 1, + .board_info = &ams_delta_camera_board_info[0], +@@ -267,7 +267,7 @@ + .power = ams_delta_camera_power, + }; + +-static struct platform_device ams_delta_camera_device = { ++static struct platform_device ams_delta_camera_device __initdata = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-fsample.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-fsample.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-fsample.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-fsample.c 2011-03-09 13:19:09.779508251 +0100 +@@ -287,11 +287,11 @@ + &lcd_device, + }; + +-static struct omap_lcd_config fsample_lcd_config __initdata = { ++static struct omap_lcd_config fsample_lcd_config = { + .ctrl_name = "internal", + }; + +-static struct omap_board_config_kernel fsample_config[] = { ++static struct omap_board_config_kernel fsample_config[] __initdata = { + { OMAP_TAG_LCD, &fsample_lcd_config }, + }; + +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-h2.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h2.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-h2.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h2.c 2011-03-09 13:19:09.779508251 +0100 +@@ -202,7 +202,7 @@ + + static const char *h2_part_probes[] = { "cmdlinepart", NULL }; + +-struct platform_nand_data h2_nand_platdata = { ++static struct platform_nand_data h2_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-h3.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h3.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-h3.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h3.c 2011-03-09 13:19:09.780508231 +0100 +@@ -204,7 +204,7 @@ + + static const char *part_probes[] = { "cmdlinepart", NULL }; + +-struct platform_nand_data nand_platdata = { ++static struct platform_nand_data nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-htcherald.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-htcherald.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-htcherald.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-htcherald.c 2011-03-09 13:19:09.780508231 +0100 +@@ -331,7 +331,7 @@ + }, + }; + +-struct htcpld_chip_platform_data htcpld_chips[] = { ++static struct htcpld_chip_platform_data htcpld_chips[] = { + [0] = { + .addr = 0x03, + .reset = 0x04, +@@ -366,7 +366,7 @@ + }, + }; + +-struct htcpld_core_platform_data htcpld_pfdata = { ++static struct htcpld_core_platform_data htcpld_pfdata = { + .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, + .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, + .i2c_adapter_id = 1, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-innovator.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-innovator.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-innovator.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-innovator.c 2011-03-09 13:19:09.781508211 +0100 +@@ -365,7 +365,7 @@ + + static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; + +-void __init innovator_mmc_init(void) ++static void __init innovator_mmc_init(void) + { + mmc_data[0] = &mmc1_data; + omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-nokia770.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-nokia770.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-nokia770.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-nokia770.c 2011-03-09 13:19:09.781508211 +0100 +@@ -115,7 +115,7 @@ + .shutdown = mipid_shutdown, + }; + +-static void mipid_dev_init(void) ++static void __init mipid_dev_init(void) + { + const struct omap_lcd_config *conf; + +@@ -126,7 +126,7 @@ + } + } + +-static void ads7846_dev_init(void) ++static void __init ads7846_dev_init(void) + { + if (gpio_request(ADS7846_PENDOWN_GPIO, "ADS7846 pendown") < 0) + printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); +@@ -170,7 +170,7 @@ + .te_connected = 1, + }; + +-static void hwa742_dev_init(void) ++static void __init hwa742_dev_init(void) + { + clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL); + omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-palmte.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-palmte.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-palmte.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-palmte.c 2011-03-09 13:19:09.781508211 +0100 +@@ -230,19 +230,6 @@ + }, + }; + +-static void palmte_headphones_detect(void *data, int state) +-{ +- if (state) { +- /* Headphones connected, disable speaker */ +- gpio_set_value(PALMTE_SPEAKER_GPIO, 0); +- printk(KERN_INFO "PM: speaker off\n"); +- } else { +- /* Headphones unplugged, re-enable speaker */ +- gpio_set_value(PALMTE_SPEAKER_GPIO, 1); +- printk(KERN_INFO "PM: speaker on\n"); +- } +-} +- + static void __init palmte_misc_gpio_setup(void) + { + /* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */ +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-voiceblue.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-voiceblue.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/board-voiceblue.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-voiceblue.c 2011-03-09 13:19:09.783508169 +0100 +@@ -26,10 +26,12 @@ + #include + + #include ++#include + #include + #include + #include + ++#include + #include + #include + #include +@@ -163,52 +165,6 @@ + omap_init_irq(); + } + +-static void __init voiceblue_init(void) +-{ +- /* mux pins for uarts */ +- omap_cfg_reg(UART1_TX); +- omap_cfg_reg(UART1_RTS); +- omap_cfg_reg(UART2_TX); +- omap_cfg_reg(UART2_RTS); +- omap_cfg_reg(UART3_TX); +- omap_cfg_reg(UART3_RX); +- +- /* Watchdog */ +- gpio_request(0, "Watchdog"); +- /* smc91x reset */ +- gpio_request(7, "SMC91x reset"); +- gpio_direction_output(7, 1); +- udelay(2); /* wait at least 100ns */ +- gpio_set_value(7, 0); +- mdelay(50); /* 50ms until PHY ready */ +- /* smc91x interrupt pin */ +- gpio_request(8, "SMC91x irq"); +- /* 16C554 reset*/ +- gpio_request(6, "16C554 reset"); +- gpio_direction_output(6, 0); +- /* 16C554 interrupt pins */ +- gpio_request(12, "16C554 irq"); +- gpio_request(13, "16C554 irq"); +- gpio_request(14, "16C554 irq"); +- gpio_request(15, "16C554 irq"); +- set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); +- set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); +- set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); +- set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); +- +- platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); +- omap_board_config = voiceblue_config; +- omap_board_config_size = ARRAY_SIZE(voiceblue_config); +- omap_serial_init(); +- omap1_usb_init(&voiceblue_usb_config); +- omap_register_i2c_bus(1, 100, NULL, 0); +- +- /* There is a good chance board is going up, so enable power LED +- * (it is connected through invertor) */ +- omap_writeb(0x00, OMAP_LPG1_LCR); +- omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ +-} +- + static void __init voiceblue_map_io(void) + { + omap1_map_common_io(); +@@ -275,8 +231,17 @@ + gpio_set_value(0, wdt_gpio_state); + } + +-void voiceblue_reset(void) ++static void voiceblue_reset(char mode, const char *cmd) + { ++ /* ++ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 ++ * "Global Software Reset Affects Traffic Controller Frequency". ++ */ ++ if (cpu_is_omap5912()) { ++ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); ++ omap_writew(0x8, ARM_RSTCT1); ++ } ++ + set_bit(MACHINE_REBOOT, &machine_state); + voiceblue_wdt_enable(); + while (1) ; +@@ -286,6 +251,54 @@ + EXPORT_SYMBOL(voiceblue_wdt_disable); + EXPORT_SYMBOL(voiceblue_wdt_ping); + ++static void __init voiceblue_init(void) ++{ ++ /* mux pins for uarts */ ++ omap_cfg_reg(UART1_TX); ++ omap_cfg_reg(UART1_RTS); ++ omap_cfg_reg(UART2_TX); ++ omap_cfg_reg(UART2_RTS); ++ omap_cfg_reg(UART3_TX); ++ omap_cfg_reg(UART3_RX); ++ ++ /* Watchdog */ ++ gpio_request(0, "Watchdog"); ++ /* smc91x reset */ ++ gpio_request(7, "SMC91x reset"); ++ gpio_direction_output(7, 1); ++ udelay(2); /* wait at least 100ns */ ++ gpio_set_value(7, 0); ++ mdelay(50); /* 50ms until PHY ready */ ++ /* smc91x interrupt pin */ ++ gpio_request(8, "SMC91x irq"); ++ /* 16C554 reset*/ ++ gpio_request(6, "16C554 reset"); ++ gpio_direction_output(6, 0); ++ /* 16C554 interrupt pins */ ++ gpio_request(12, "16C554 irq"); ++ gpio_request(13, "16C554 irq"); ++ gpio_request(14, "16C554 irq"); ++ gpio_request(15, "16C554 irq"); ++ set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); ++ set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); ++ set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); ++ set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); ++ ++ platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); ++ omap_board_config = voiceblue_config; ++ omap_board_config_size = ARRAY_SIZE(voiceblue_config); ++ omap_serial_init(); ++ omap1_usb_init(&voiceblue_usb_config); ++ omap_register_i2c_bus(1, 100, NULL, 0); ++ ++ /* There is a good chance board is going up, so enable power LED ++ * (it is connected through invertor) */ ++ omap_writeb(0x00, OMAP_LPG1_LCR); ++ omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ ++ ++ arch_reset = voiceblue_reset; ++} ++ + MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") + /* Maintainer: Ladislav Michl */ + .boot_params = 0x10000100, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/Makefile linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/Makefile +--- linux-2.6.38-rc7/arch/arm/mach-omap1/Makefile 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/Makefile 2011-03-09 13:19:09.778508271 +0100 +@@ -4,7 +4,7 @@ + + # Common support + obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o +-obj-y += clock.o clock_data.o opp_data.o ++obj-y += clock.o clock_data.o opp_data.o reset.o + + obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o + +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/mcbsp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/mcbsp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/mcbsp.c 2011-03-09 13:19:09.789508048 +0100 +@@ -10,6 +10,7 @@ + * + * Multichannel mode not supported. + */ ++#include + #include + #include + #include +@@ -78,100 +79,288 @@ + }; + + #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) ++struct resource omap7xx_mcbsp_res[][6] = { ++ { ++ { ++ .start = OMAP7XX_MCBSP1_BASE, ++ .end = OMAP7XX_MCBSP1_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_7XX_McBSP1RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_7XX_McBSP1TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP1_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP1_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++ { ++ { ++ .start = OMAP7XX_MCBSP2_BASE, ++ .end = OMAP7XX_MCBSP2_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_7XX_McBSP2RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_7XX_McBSP2TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP3_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP3_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++}; ++ + static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { + { +- .phys_base = OMAP7XX_MCBSP1_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP1_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP1_TX, +- .rx_irq = INT_7XX_McBSP1RX, +- .tx_irq = INT_7XX_McBSP1TX, + .ops = &omap1_mcbsp_ops, + }, + { +- .phys_base = OMAP7XX_MCBSP2_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP3_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP3_TX, +- .rx_irq = INT_7XX_McBSP2RX, +- .tx_irq = INT_7XX_McBSP2TX, + .ops = &omap1_mcbsp_ops, + }, + }; +-#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) +-#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) ++#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1]) ++#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res) + #else ++#define omap7xx_mcbsp_res NULL + #define omap7xx_mcbsp_pdata NULL +-#define OMAP7XX_MCBSP_PDATA_SZ 0 +-#define OMAP7XX_MCBSP_REG_NUM 0 ++#define OMAP7XX_MCBSP_RES_SZ 0 ++#define OMAP7XX_MCBSP_COUNT 0 + #endif + + #ifdef CONFIG_ARCH_OMAP15XX ++struct resource omap15xx_mcbsp_res[][6] = { ++ { ++ { ++ .start = OMAP1510_MCBSP1_BASE, ++ .end = OMAP1510_MCBSP1_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_McBSP1RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_McBSP1TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP1_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP1_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++ { ++ { ++ .start = OMAP1510_MCBSP2_BASE, ++ .end = OMAP1510_MCBSP2_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_1510_SPI_RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_1510_SPI_TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP2_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP2_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++ { ++ { ++ .start = OMAP1510_MCBSP3_BASE, ++ .end = OMAP1510_MCBSP3_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_McBSP3RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_McBSP3TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP3_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP3_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++}; ++ + static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { + { +- .phys_base = OMAP1510_MCBSP1_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP1_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP1_TX, +- .rx_irq = INT_McBSP1RX, +- .tx_irq = INT_McBSP1TX, + .ops = &omap1_mcbsp_ops, + }, + { +- .phys_base = OMAP1510_MCBSP2_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP2_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP2_TX, +- .rx_irq = INT_1510_SPI_RX, +- .tx_irq = INT_1510_SPI_TX, + .ops = &omap1_mcbsp_ops, + }, + { +- .phys_base = OMAP1510_MCBSP3_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP3_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP3_TX, +- .rx_irq = INT_McBSP3RX, +- .tx_irq = INT_McBSP3TX, + .ops = &omap1_mcbsp_ops, + }, + }; +-#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) +-#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) ++#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1]) ++#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res) + #else ++#define omap15xx_mcbsp_res NULL + #define omap15xx_mcbsp_pdata NULL +-#define OMAP15XX_MCBSP_PDATA_SZ 0 +-#define OMAP15XX_MCBSP_REG_NUM 0 ++#define OMAP15XX_MCBSP_RES_SZ 0 ++#define OMAP15XX_MCBSP_COUNT 0 + #endif + + #ifdef CONFIG_ARCH_OMAP16XX ++struct resource omap16xx_mcbsp_res[][6] = { ++ { ++ { ++ .start = OMAP1610_MCBSP1_BASE, ++ .end = OMAP1610_MCBSP1_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_McBSP1RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_McBSP1TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP1_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP1_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++ { ++ { ++ .start = OMAP1610_MCBSP2_BASE, ++ .end = OMAP1610_MCBSP2_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_1610_McBSP2_RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_1610_McBSP2_TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP2_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP2_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++ { ++ { ++ .start = OMAP1610_MCBSP3_BASE, ++ .end = OMAP1610_MCBSP3_BASE + SZ_256, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "rx", ++ .start = INT_McBSP3RX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "tx", ++ .start = INT_McBSP3TX, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "rx", ++ .start = OMAP_DMA_MCBSP3_RX, ++ .flags = IORESOURCE_DMA, ++ }, ++ { ++ .name = "tx", ++ .start = OMAP_DMA_MCBSP3_TX, ++ .flags = IORESOURCE_DMA, ++ }, ++ }, ++}; ++ + static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { + { +- .phys_base = OMAP1610_MCBSP1_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP1_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP1_TX, +- .rx_irq = INT_McBSP1RX, +- .tx_irq = INT_McBSP1TX, + .ops = &omap1_mcbsp_ops, + }, + { +- .phys_base = OMAP1610_MCBSP2_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP2_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP2_TX, +- .rx_irq = INT_1610_McBSP2_RX, +- .tx_irq = INT_1610_McBSP2_TX, + .ops = &omap1_mcbsp_ops, + }, + { +- .phys_base = OMAP1610_MCBSP3_BASE, +- .dma_rx_sync = OMAP_DMA_MCBSP3_RX, +- .dma_tx_sync = OMAP_DMA_MCBSP3_TX, +- .rx_irq = INT_McBSP3RX, +- .tx_irq = INT_McBSP3TX, + .ops = &omap1_mcbsp_ops, + }, + }; +-#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) +-#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) ++#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1]) ++#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res) + #else ++#define omap16xx_mcbsp_res NULL + #define omap16xx_mcbsp_pdata NULL +-#define OMAP16XX_MCBSP_PDATA_SZ 0 +-#define OMAP16XX_MCBSP_REG_NUM 0 ++#define OMAP16XX_MCBSP_RES_SZ 0 ++#define OMAP16XX_MCBSP_COUNT 0 + #endif + + static int __init omap1_mcbsp_init(void) +@@ -179,16 +368,12 @@ + if (!cpu_class_is_omap1()) + return -ENODEV; + +- if (cpu_is_omap7xx()) { +- omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; +- omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); +- } else if (cpu_is_omap15xx()) { +- omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; +- omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); +- } else if (cpu_is_omap16xx()) { +- omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; +- omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16); +- } ++ if (cpu_is_omap7xx()) ++ omap_mcbsp_count = OMAP7XX_MCBSP_COUNT; ++ else if (cpu_is_omap15xx()) ++ omap_mcbsp_count = OMAP15XX_MCBSP_COUNT; ++ else if (cpu_is_omap16xx()) ++ omap_mcbsp_count = OMAP16XX_MCBSP_COUNT; + + mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), + GFP_KERNEL); +@@ -196,16 +381,22 @@ + return -ENOMEM; + + if (cpu_is_omap7xx()) +- omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, +- OMAP7XX_MCBSP_PDATA_SZ); ++ omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0], ++ OMAP7XX_MCBSP_RES_SZ, ++ omap7xx_mcbsp_pdata, ++ OMAP7XX_MCBSP_COUNT); + + if (cpu_is_omap15xx()) +- omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, +- OMAP15XX_MCBSP_PDATA_SZ); ++ omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0], ++ OMAP15XX_MCBSP_RES_SZ, ++ omap15xx_mcbsp_pdata, ++ OMAP15XX_MCBSP_COUNT); + + if (cpu_is_omap16xx()) +- omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, +- OMAP16XX_MCBSP_PDATA_SZ); ++ omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0], ++ OMAP16XX_MCBSP_RES_SZ, ++ omap16xx_mcbsp_pdata, ++ OMAP16XX_MCBSP_COUNT); + + return omap_mcbsp_init(); + } +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/reset.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/reset.c +--- linux-2.6.38-rc7/arch/arm/mach-omap1/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/reset.c 2011-03-09 13:19:09.791508008 +0100 +@@ -0,0 +1,25 @@ ++/* ++ * OMAP1 reset support ++ */ ++#include ++#include ++ ++#include ++#include ++#include ++ ++void omap1_arch_reset(char mode, const char *cmd) ++{ ++ /* ++ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 ++ * "Global Software Reset Affects Traffic Controller Frequency". ++ */ ++ if (cpu_is_omap5912()) { ++ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); ++ omap_writew(0x8, ARM_RSTCT1); ++ } ++ ++ omap_writew(1, ARM_RSTCT1); ++} ++ ++void (*arch_reset)(char, const char *) = omap1_arch_reset; +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-2430sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-2430sdp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-2430sdp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-2430sdp.c 2011-03-09 13:19:09.793507967 +0100 +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -139,15 +140,31 @@ + {OMAP_TAG_LCD, &sdp2430_lcd_config}, + }; + +-static void __init omap_2430sdp_init_irq(void) ++static void __init omap_2430sdp_init_early(void) + { +- omap_board_config = sdp2430_config; +- omap_board_config_size = ARRAY_SIZE(sdp2430_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + ++static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), ++}; ++ ++/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ ++static struct regulator_init_data sdp2430_vmmc1 = { ++ .constraints = { ++ .min_uV = 1850000, ++ .max_uV = 3150000, ++ .valid_modes_mask = REGULATOR_MODE_NORMAL ++ | REGULATOR_MODE_STANDBY, ++ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE ++ | REGULATOR_CHANGE_MODE ++ | REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies), ++ .consumer_supplies = &sdp2430_vmmc1_supplies[0], ++}; ++ + static struct twl4030_gpio_platform_data sdp2430_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, +@@ -160,6 +177,7 @@ + + /* platform_data for children goes here */ + .gpio = &sdp2430_gpio_data, ++ .vmmc1 = &sdp2430_vmmc1, + }; + + static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = { +@@ -226,6 +244,9 @@ + + omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); + ++ omap_board_config = sdp2430_config; ++ omap_board_config_size = ARRAY_SIZE(sdp2430_config); ++ + omap2430_i2c_init(); + + platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); +@@ -253,9 +274,10 @@ + MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") + /* Maintainer: Syed Khasim - Texas Instruments Inc */ + .boot_params = 0x80000100, +- .map_io = omap_2430sdp_map_io, + .reserve = omap_reserve, +- .init_irq = omap_2430sdp_init_irq, ++ .map_io = omap_2430sdp_map_io, ++ .init_early = omap_2430sdp_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_2430sdp_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-3430sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3430sdp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-3430sdp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3430sdp.c 2011-03-09 13:19:09.793507967 +0100 +@@ -307,34 +307,13 @@ + .default_device = &sdp3430_lcd_device, + }; + +-static struct platform_device sdp3430_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &sdp3430_dss_data, +- }, +-}; +- +-static struct regulator_consumer_supply sdp3430_vdda_dac_supply = { +- .supply = "vdda_dac", +- .dev = &sdp3430_dss_device.dev, +-}; +- +-static struct platform_device *sdp3430_devices[] __initdata = { +- &sdp3430_dss_device, +-}; +- + static struct omap_board_config_kernel sdp3430_config[] __initdata = { + }; + +-static void __init omap_3430sdp_init_irq(void) ++static void __init omap_3430sdp_init_early(void) + { +- omap_board_config = sdp3430_config; +- omap_board_config_size = ARRAY_SIZE(sdp3430_config); +- omap3_pm_init_cpuidle(omap3_cpuidle_params_table); + omap2_init_common_infrastructure(); + omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); +- omap_init_irq(); + } + + static int sdp3430_batt_table[] = { +@@ -370,18 +349,6 @@ + {} /* Terminator */ + }; + +-static struct regulator_consumer_supply sdp3430_vmmc1_supply = { +- .supply = "vmmc", +-}; +- +-static struct regulator_consumer_supply sdp3430_vsim_supply = { +- .supply = "vmmc_aux", +-}; +- +-static struct regulator_consumer_supply sdp3430_vmmc2_supply = { +- .supply = "vmmc", +-}; +- + static int sdp3430_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) + { +@@ -392,13 +359,6 @@ + mmc[1].gpio_cd = gpio + 1; + omap2_hsmmc_init(mmc); + +- /* link regulators to MMC adapters ... we "know" the +- * regulators will be set up only *after* we return. +- */ +- sdp3430_vmmc1_supply.dev = mmc[0].dev; +- sdp3430_vsim_supply.dev = mmc[0].dev; +- sdp3430_vmmc2_supply.dev = mmc[1].dev; +- + /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ + gpio_request(gpio + 7, "sub_lcd_en_bkl"); + gpio_direction_output(gpio + 7, 0); +@@ -427,6 +387,35 @@ + .irq_line = 1, + }; + ++/* regulator consumer mappings */ ++ ++/* ads7846 on SPI */ ++static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { ++ REGULATOR_SUPPLY("vcc", "spi1.0"), ++}; ++ ++static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = { ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), ++}; ++ ++/* VPLL2 for digital video outputs */ ++static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), ++}; ++ ++static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), ++}; ++ ++static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { ++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), ++}; ++ ++static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), ++}; ++ + /* + * Apply all the fixed voltages since most versions of U-Boot + * don't bother with that initialization. +@@ -469,6 +458,8 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, ++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies), ++ .consumer_supplies = sdp3430_vaux3_supplies, + }; + + /* VAUX4 for OMAP VDD_CSI2 (camera) */ +@@ -495,8 +486,8 @@ + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &sdp3430_vmmc1_supply, ++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies), ++ .consumer_supplies = sdp3430_vmmc1_supplies, + }; + + /* VMMC2 for MMC2 card */ +@@ -510,8 +501,8 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &sdp3430_vmmc2_supply, ++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies), ++ .consumer_supplies = sdp3430_vmmc2_supplies, + }; + + /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ +@@ -525,8 +516,8 @@ + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &sdp3430_vsim_supply, ++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies), ++ .consumer_supplies = sdp3430_vsim_supplies, + }; + + /* VDAC for DSS driving S-Video */ +@@ -540,16 +531,8 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &sdp3430_vdda_dac_supply, +-}; +- +-/* VPLL2 for digital video outputs */ +-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { +- { +- .supply = "vdds_dsi", +- .dev = &sdp3430_dss_device.dev, +- } ++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies), ++ .consumer_supplies = sdp3430_vdda_dac_supplies, + }; + + static struct regulator_init_data sdp3430_vpll2 = { +@@ -567,9 +550,7 @@ + .consumer_supplies = sdp3430_vpll2_supplies, + }; + +-static struct twl4030_codec_audio_data sdp3430_audio = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data sdp3430_audio; + + static struct twl4030_codec_data sdp3430_codec = { + .audio_mclk = 26000000, +@@ -800,8 +781,11 @@ + static void __init omap_3430sdp_init(void) + { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); ++ omap_board_config = sdp3430_config; ++ omap_board_config_size = ARRAY_SIZE(sdp3430_config); ++ omap3_pm_init_cpuidle(omap3_cpuidle_params_table); + omap3430_i2c_init(); +- platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); ++ omap_display_init(&sdp3430_dss_data); + if (omap_rev() > OMAP3430_REV_ES1_0) + ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2; + else +@@ -813,7 +797,7 @@ + omap_serial_init(); + usb_musb_init(&musb_board_data); + board_smc91x_init(); +- board_flash_init(sdp_flash_partitions, chip_sel_3430); ++ board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); + sdp3430_display_init(); + enable_board_wakeup_source(); + usb_ehci_init(&ehci_pdata); +@@ -822,9 +806,10 @@ + MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") + /* Maintainer: Syed Khasim - Texas Instruments Inc */ + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = omap_3430sdp_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = omap_3430sdp_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_3430sdp_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-3630sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3630sdp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-3630sdp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3630sdp.c 2011-03-09 13:19:09.793507967 +0100 +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -69,14 +70,11 @@ + static struct omap_board_config_kernel sdp_config[] __initdata = { + }; + +-static void __init omap_sdp_init_irq(void) ++static void __init omap_sdp_init_early(void) + { +- omap_board_config = sdp_config; +- omap_board_config_size = ARRAY_SIZE(sdp_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); +- omap_init_irq(); + } + + #ifdef CONFIG_OMAP_MUX +@@ -206,19 +204,22 @@ + static void __init omap_sdp_init(void) + { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); ++ omap_board_config = sdp_config; ++ omap_board_config_size = ARRAY_SIZE(sdp_config); + zoom_peripherals_init(); + zoom_display_init(); + board_smc91x_init(); +- board_flash_init(sdp_flash_partitions, chip_sel_sdp); ++ board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16); + enable_board_wakeup_source(); + usb_ehci_init(&ehci_pdata); + } + + MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = omap_sdp_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = omap_sdp_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_sdp_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-4430sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-4430sdp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-4430sdp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-4430sdp.c 2011-03-09 13:19:09.794507946 +0100 +@@ -35,6 +35,7 @@ + #include + #include + #include ++#include + + #include "mux.h" + #include "hsmmc.h" +@@ -44,10 +45,93 @@ + #define ETH_KS8851_IRQ 34 + #define ETH_KS8851_POWER_ON 48 + #define ETH_KS8851_QUART 138 +-#define OMAP4SDP_MDM_PWR_EN_GPIO 157 + #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 + #define OMAP4_SFH7741_ENABLE_GPIO 188 + ++static const int sdp4430_keymap[] = { ++ KEY(0, 0, KEY_E), ++ KEY(0, 1, KEY_R), ++ KEY(0, 2, KEY_T), ++ KEY(0, 3, KEY_HOME), ++ KEY(0, 4, KEY_F5), ++ KEY(0, 5, KEY_UNKNOWN), ++ KEY(0, 6, KEY_I), ++ KEY(0, 7, KEY_LEFTSHIFT), ++ ++ KEY(1, 0, KEY_D), ++ KEY(1, 1, KEY_F), ++ KEY(1, 2, KEY_G), ++ KEY(1, 3, KEY_SEND), ++ KEY(1, 4, KEY_F6), ++ KEY(1, 5, KEY_UNKNOWN), ++ KEY(1, 6, KEY_K), ++ KEY(1, 7, KEY_ENTER), ++ ++ KEY(2, 0, KEY_X), ++ KEY(2, 1, KEY_C), ++ KEY(2, 2, KEY_V), ++ KEY(2, 3, KEY_END), ++ KEY(2, 4, KEY_F7), ++ KEY(2, 5, KEY_UNKNOWN), ++ KEY(2, 6, KEY_DOT), ++ KEY(2, 7, KEY_CAPSLOCK), ++ ++ KEY(3, 0, KEY_Z), ++ KEY(3, 1, KEY_KPPLUS), ++ KEY(3, 2, KEY_B), ++ KEY(3, 3, KEY_F1), ++ KEY(3, 4, KEY_F8), ++ KEY(3, 5, KEY_UNKNOWN), ++ KEY(3, 6, KEY_O), ++ KEY(3, 7, KEY_SPACE), ++ ++ KEY(4, 0, KEY_W), ++ KEY(4, 1, KEY_Y), ++ KEY(4, 2, KEY_U), ++ KEY(4, 3, KEY_F2), ++ KEY(4, 4, KEY_VOLUMEUP), ++ KEY(4, 5, KEY_UNKNOWN), ++ KEY(4, 6, KEY_L), ++ KEY(4, 7, KEY_LEFT), ++ ++ KEY(5, 0, KEY_S), ++ KEY(5, 1, KEY_H), ++ KEY(5, 2, KEY_J), ++ KEY(5, 3, KEY_F3), ++ KEY(5, 4, KEY_F9), ++ KEY(5, 5, KEY_VOLUMEDOWN), ++ KEY(5, 6, KEY_M), ++ KEY(5, 7, KEY_RIGHT), ++ ++ KEY(6, 0, KEY_Q), ++ KEY(6, 1, KEY_A), ++ KEY(6, 2, KEY_N), ++ KEY(6, 3, KEY_BACK), ++ KEY(6, 4, KEY_BACKSPACE), ++ KEY(6, 5, KEY_UNKNOWN), ++ KEY(6, 6, KEY_P), ++ KEY(6, 7, KEY_UP), ++ ++ KEY(7, 0, KEY_PROG1), ++ KEY(7, 1, KEY_PROG2), ++ KEY(7, 2, KEY_PROG3), ++ KEY(7, 3, KEY_PROG4), ++ KEY(7, 4, KEY_F4), ++ KEY(7, 5, KEY_UNKNOWN), ++ KEY(7, 6, KEY_OK), ++ KEY(7, 7, KEY_DOWN), ++}; ++ ++static struct matrix_keymap_data sdp4430_keymap_data = { ++ .keymap = sdp4430_keymap, ++ .keymap_size = ARRAY_SIZE(sdp4430_keymap), ++}; ++ ++static struct omap4_keypad_platform_data sdp4430_keypad_data = { ++ .keymap_data = &sdp4430_keymap_data, ++ .rows = 8, ++ .cols = 8, ++}; + static struct gpio_led sdp4430_gpio_leds[] = { + { + .name = "omap4:green:debug0", +@@ -239,28 +323,15 @@ + { OMAP_TAG_LCD, &sdp4430_lcd_config }, + }; + +-static void __init omap_4430sdp_init_irq(void) ++static void __init omap_4430sdp_init_early(void) + { +- omap_board_config = sdp4430_config; +- omap_board_config_size = ARRAY_SIZE(sdp4430_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); + #ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(1); + #endif +- gic_init_irq(); + } + +-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +- .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, +- .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, +- .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +- .phy_reset = false, +- .reset_gpio_port[0] = -EINVAL, +- .reset_gpio_port[1] = -EINVAL, +- .reset_gpio_port[2] = -EINVAL, +-}; +- + static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_UTMI, + .mode = MUSB_OTG, +@@ -276,11 +347,6 @@ + + static struct omap2_hsmmc_info mmc[] = { + { +- .mmc = 1, +- .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, +- .gpio_wp = -EINVAL, +- }, +- { + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .gpio_cd = -EINVAL, +@@ -288,19 +354,24 @@ + .nonremovable = true, + .ocr_mask = MMC_VDD_29_30, + }, ++ { ++ .mmc = 1, ++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, ++ .gpio_wp = -EINVAL, ++ }, + {} /* Terminator */ + }; + + static struct regulator_consumer_supply sdp4430_vaux_supply[] = { + { + .supply = "vmmc", +- .dev_name = "mmci-omap-hs.1", ++ .dev_name = "omap_hsmmc.1", + }, + }; + static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { + { + .supply = "vmmc", +- .dev_name = "mmci-omap-hs.0", ++ .dev_name = "omap_hsmmc.0", + }, + }; + +@@ -434,7 +505,6 @@ + .constraints = { + .min_uV = 2100000, + .max_uV = 2100000, +- .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE +@@ -446,7 +516,6 @@ + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, +- .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE +@@ -458,7 +527,6 @@ + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, +- .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE +@@ -570,20 +638,15 @@ + package = OMAP_PACKAGE_CBL; + omap4_mux_init(board_mux, package); + ++ omap_board_config = sdp4430_config; ++ omap_board_config_size = ARRAY_SIZE(sdp4430_config); ++ + omap4_i2c_init(); + omap_sfh7741prox_init(); + platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); + omap_serial_init(); + omap4_twl6030_hsmmc_init(mmc); + +- /* Power on the ULPI PHY */ +- status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); +- if (status) +- pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__); +- else +- gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); +- +- usb_ehci_init(&ehci_pdata); + usb_musb_init(&musb_board_data); + + status = omap_ethernet_init(); +@@ -594,6 +657,10 @@ + spi_register_board_info(sdp4430_spi_board_info, + ARRAY_SIZE(sdp4430_spi_board_info)); + } ++ ++ status = omap4_keyboard_init(&sdp4430_keypad_data); ++ if (status) ++ pr_err("Keypad initialization failed: %d\n", status); + } + + static void __init omap_4430sdp_map_io(void) +@@ -605,9 +672,10 @@ + MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") + /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ + .boot_params = 0x80000100, +- .map_io = omap_4430sdp_map_io, + .reserve = omap_reserve, +- .init_irq = omap_4430sdp_init_irq, ++ .map_io = omap_4430sdp_map_io, ++ .init_early = omap_4430sdp_init_early, ++ .init_irq = gic_init_irq, + .init_machine = omap_4430sdp_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517crane.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517crane.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517crane.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517crane.c 2011-03-09 13:19:09.794507946 +0100 +@@ -49,14 +49,10 @@ + #define board_mux NULL + #endif + +-static void __init am3517_crane_init_irq(void) ++static void __init am3517_crane_init_early(void) + { +- omap_board_config = am3517_crane_config; +- omap_board_config_size = ARRAY_SIZE(am3517_crane_config); +- + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { +@@ -77,6 +73,9 @@ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); + ++ omap_board_config = am3517_crane_config; ++ omap_board_config_size = ARRAY_SIZE(am3517_crane_config); ++ + /* Configure GPIO for EHCI port */ + if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { + pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", +@@ -108,9 +107,10 @@ + + MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = am3517_crane_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = am3517_crane_init_early, ++ .init_irq = omap_init_irq, + .init_machine = am3517_crane_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517evm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517evm.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517evm.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517evm.c 2011-03-09 13:19:09.794507946 +0100 +@@ -378,37 +378,23 @@ + .default_device = &am3517_evm_lcd_device, + }; + +-static struct platform_device am3517_evm_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &am3517_evm_dss_data, +- }, +-}; +- + /* + * Board initialization + */ +-static struct omap_board_config_kernel am3517_evm_config[] __initdata = { +-}; +- +-static struct platform_device *am3517_evm_devices[] __initdata = { +- &am3517_evm_dss_device, +-}; +- +-static void __init am3517_evm_init_irq(void) ++static void __init am3517_evm_init_early(void) + { +- omap_board_config = am3517_evm_config; +- omap_board_config_size = ARRAY_SIZE(am3517_evm_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 500, ++ .set_phy_power = am35x_musb_phy_power, ++ .clear_irq = am35x_musb_clear_irq, ++ .set_mode = am35x_musb_set_mode, ++ .reset = am35x_musb_reset, + }; + + static __init void am3517_evm_musb_init(void) +@@ -490,14 +476,17 @@ + platform_device_register(&am3517_hecc_device); + } + ++static struct omap_board_config_kernel am3517_evm_config[] __initdata = { ++}; ++ + static void __init am3517_evm_init(void) + { ++ omap_board_config = am3517_evm_config; ++ omap_board_config_size = ARRAY_SIZE(am3517_evm_config); + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + am3517_evm_i2c_init(); +- platform_add_devices(am3517_evm_devices, +- ARRAY_SIZE(am3517_evm_devices)); +- ++ omap_display_init(&am3517_evm_dss_data); + omap_serial_init(); + + /* Configure GPIO for EHCI port */ +@@ -521,9 +510,10 @@ + + MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = am3517_evm_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = am3517_evm_init_early, ++ .init_irq = omap_init_irq, + .init_machine = am3517_evm_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-apollon.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-apollon.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-apollon.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-apollon.c 2011-03-09 13:19:09.794507946 +0100 +@@ -274,13 +274,10 @@ + { OMAP_TAG_LCD, &apollon_lcd_config }, + }; + +-static void __init omap_apollon_init_irq(void) ++static void __init omap_apollon_init_early(void) + { +- omap_board_config = apollon_config; +- omap_board_config_size = ARRAY_SIZE(apollon_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + static void __init apollon_led_init(void) +@@ -320,6 +317,8 @@ + u32 v; + + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); ++ omap_board_config = apollon_config; ++ omap_board_config_size = ARRAY_SIZE(apollon_config); + + apollon_init_smc91x(); + apollon_led_init(); +@@ -355,9 +354,10 @@ + MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") + /* Maintainer: Kyungmin Park */ + .boot_params = 0x80000100, +- .map_io = omap_apollon_map_io, + .reserve = omap_reserve, +- .init_irq = omap_apollon_init_irq, ++ .map_io = omap_apollon_map_io, ++ .init_early = omap_apollon_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_apollon_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t3517.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t3517.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t3517.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t3517.c 2011-03-09 13:19:09.795507925 +0100 +@@ -254,14 +254,10 @@ + static struct omap_board_config_kernel cm_t3517_config[] __initdata = { + }; + +-static void __init cm_t3517_init_irq(void) ++static void __init cm_t3517_init_early(void) + { +- omap_board_config = cm_t3517_config; +- omap_board_config_size = ARRAY_SIZE(cm_t3517_config); +- + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + static struct omap_board_mux board_mux[] __initdata = { +@@ -294,6 +290,8 @@ + { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); ++ omap_board_config = cm_t3517_config; ++ omap_board_config_size = ARRAY_SIZE(cm_t3517_config); + cm_t3517_init_leds(); + cm_t3517_init_nand(); + cm_t3517_init_rtc(); +@@ -303,9 +301,10 @@ + + MACHINE_START(CM_T3517, "Compulab CM-T3517") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = cm_t3517_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = cm_t3517_init_early, ++ .init_irq = omap_init_irq, + .init_machine = cm_t3517_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t35.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t35.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t35.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t35.c 2011-03-09 13:19:09.795507925 +0100 +@@ -401,14 +401,6 @@ + .default_device = &cm_t35_dvi_device, + }; + +-static struct platform_device cm_t35_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &cm_t35_dss_data, +- }, +-}; +- + static struct omap2_mcspi_device_config tdo24m_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, /* 0: slave, 1: master */ +@@ -468,7 +460,7 @@ + msleep(50); + gpio_set_value(lcd_en_gpio, 1); + +- err = platform_device_register(&cm_t35_dss_device); ++ err = omap_display_init(&cm_t35_dss_data); + if (err) { + pr_err("CM-T35: failed to register DSS device\n"); + goto err_dev_reg; +@@ -495,15 +487,11 @@ + .supply = "vmmc_aux", + }; + +-static struct regulator_consumer_supply cm_t35_vdac_supply = { +- .supply = "vdda_dac", +- .dev = &cm_t35_dss_device.dev, +-}; ++static struct regulator_consumer_supply cm_t35_vdac_supply = ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + +-static struct regulator_consumer_supply cm_t35_vdvi_supply = { +- .supply = "vdvi", +- .dev = &cm_t35_dss_device.dev, +-}; ++static struct regulator_consumer_supply cm_t35_vdvi_supply = ++ REGULATOR_SUPPLY("vdvi", "omapdss"); + + /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ + static struct regulator_init_data cm_t35_vmmc1 = { +@@ -680,18 +668,11 @@ + ARRAY_SIZE(cm_t35_i2c_boardinfo)); + } + +-static struct omap_board_config_kernel cm_t35_config[] __initdata = { +-}; +- +-static void __init cm_t35_init_irq(void) ++static void __init cm_t35_init_early(void) + { +- omap_board_config = cm_t35_config; +- omap_board_config_size = ARRAY_SIZE(cm_t35_config); +- + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); +- omap_init_irq(); + } + + static struct omap_board_mux board_mux[] __initdata = { +@@ -798,8 +779,13 @@ + .power = 100, + }; + ++static struct omap_board_config_kernel cm_t35_config[] __initdata = { ++}; ++ + static void __init cm_t35_init(void) + { ++ omap_board_config = cm_t35_config; ++ omap_board_config_size = ARRAY_SIZE(cm_t35_config); + omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); + omap_serial_init(); + cm_t35_init_i2c(); +@@ -815,9 +801,10 @@ + + MACHINE_START(CM_T35, "Compulab CM-T35") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = cm_t35_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = cm_t35_init_early, ++ .init_irq = omap_init_irq, + .init_machine = cm_t35_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-devkit8000.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-devkit8000.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-devkit8000.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-devkit8000.c 2011-03-09 13:19:09.795507925 +0100 +@@ -140,7 +140,7 @@ + } + + static struct regulator_consumer_supply devkit8000_vmmc1_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); + + + /* ads7846 on SPI */ +@@ -195,16 +195,8 @@ + .default_device = &devkit8000_lcd_device, + }; + +-static struct platform_device devkit8000_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &devkit8000_dss_data, +- }, +-}; +- + static struct regulator_consumer_supply devkit8000_vdda_dac_supply = +- REGULATOR_SUPPLY("vdda_dac", "omapdss"); ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + + static uint32_t board_keymap[] = { + KEY(0, 0, KEY_1), +@@ -285,8 +277,10 @@ + .setup = devkit8000_twl_gpio_setup, + }; + +-static struct regulator_consumer_supply devkit8000_vpll1_supply = +- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); ++static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), ++}; + + /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ + static struct regulator_init_data devkit8000_vmmc1 = { +@@ -327,8 +321,8 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &devkit8000_vpll1_supply, ++ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll1_supplies), ++ .consumer_supplies = devkit8000_vpll1_supplies, + }; + + /* VAUX4 for ads7846 and nubs */ +@@ -350,9 +344,7 @@ + .usb_mode = T2_USB_MODE_ULPI, + }; + +-static struct twl4030_codec_audio_data devkit8000_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data devkit8000_audio_data; + + static struct twl4030_codec_data devkit8000_codec_data = { + .audio_mclk = 26000000, +@@ -456,11 +448,15 @@ + }; + + +-static void __init devkit8000_init_irq(void) ++static void __init devkit8000_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); ++} ++ ++static void __init devkit8000_init_irq(void) ++{ + omap_init_irq(); + #ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +@@ -575,7 +571,6 @@ + } + + static struct platform_device *devkit8000_devices[] __initdata = { +- &devkit8000_dss_device, + &leds_gpio, + &keys_gpio, + &omap_dm9000_dev, +@@ -797,6 +792,7 @@ + platform_add_devices(devkit8000_devices, + ARRAY_SIZE(devkit8000_devices)); + ++ omap_display_init(&devkit8000_dss_data); + spi_register_board_info(devkit8000_spi_board_info, + ARRAY_SIZE(devkit8000_spi_board_info)); + +@@ -813,8 +809,9 @@ + + MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, ++ .map_io = omap3_map_io, ++ .init_early = devkit8000_init_early, + .init_irq = devkit8000_init_irq, + .init_machine = devkit8000_init, + .timer = &omap_timer, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.c 2011-03-09 13:19:09.796507904 +0100 +@@ -1,5 +1,5 @@ + /* +- * board-sdp-flash.c ++ * board-flash.c + * Modified from mach-omap2/board-3430sdp-flash.c + * + * Copyright (C) 2009 Nokia Corporation +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -73,11 +74,11 @@ + + FLASH_SIZE_SDPV1 - 1; + } + if (err < 0) { +- printk(KERN_ERR "NOR: Can't request GPMC CS\n"); ++ pr_err("NOR: Can't request GPMC CS\n"); + return; + } + if (platform_device_register(&board_nor_device) < 0) +- printk(KERN_ERR "Unable to register NOR device\n"); ++ pr_err("Unable to register NOR device\n"); + } + + #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ +@@ -139,17 +140,21 @@ + }; + + void +-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) ++__init board_nand_init(struct mtd_partition *nand_parts, ++ u8 nr_parts, u8 cs, int nand_type) + { + board_nand_data.cs = cs; + board_nand_data.parts = nand_parts; +- board_nand_data.nr_parts = nr_parts; ++ board_nand_data.nr_parts = nr_parts; ++ board_nand_data.devsize = nand_type; + ++ board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; ++ board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; + gpmc_nand_init(&board_nand_data); + } + #else + void +-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) ++__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type) + { + } + #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ +@@ -189,12 +194,12 @@ + } + + /** +- * sdp3430_flash_init - Identify devices connected to GPMC and register. ++ * board_flash_init - Identify devices connected to GPMC and register. + * + * @return - void. + */ + void board_flash_init(struct flash_partitions partition_info[], +- char chip_sel_board[][GPMC_CS_NUM]) ++ char chip_sel_board[][GPMC_CS_NUM], int nand_type) + { + u8 cs = 0; + u8 norcs = GPMC_CS_NUM + 1; +@@ -208,7 +213,7 @@ + */ + idx = get_gpmc0_type(); + if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { +- printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); ++ pr_err("%s: Invalid chip select: %d\n", __func__, cs); + return; + } + config_sel = (unsigned char *)(chip_sel_board[idx]); +@@ -232,23 +237,20 @@ + } + + if (norcs > GPMC_CS_NUM) +- printk(KERN_INFO "NOR: Unable to find configuration " +- "in GPMC\n"); ++ pr_err("NOR: Unable to find configuration in GPMC\n"); + else + board_nor_init(partition_info[0].parts, + partition_info[0].nr_parts, norcs); + + if (onenandcs > GPMC_CS_NUM) +- printk(KERN_INFO "OneNAND: Unable to find configuration " +- "in GPMC\n"); ++ pr_err("OneNAND: Unable to find configuration in GPMC\n"); + else + board_onenand_init(partition_info[1].parts, + partition_info[1].nr_parts, onenandcs); + + if (nandcs > GPMC_CS_NUM) +- printk(KERN_INFO "NAND: Unable to find configuration " +- "in GPMC\n"); ++ pr_err("NAND: Unable to find configuration in GPMC\n"); + else + board_nand_init(partition_info[2].parts, +- partition_info[2].nr_parts, nandcs); ++ partition_info[2].nr_parts, nandcs, nand_type); + } +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.h +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.h 2011-03-09 13:19:09.796507904 +0100 +@@ -25,6 +25,6 @@ + }; + + extern void board_flash_init(struct flash_partitions [], +- char chip_sel[][GPMC_CS_NUM]); ++ char chip_sel[][GPMC_CS_NUM], int nand_type); + extern void board_nand_init(struct mtd_partition *nand_parts, +- u8 nr_parts, u8 cs); ++ u8 nr_parts, u8 cs, int nand_type); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-generic.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-generic.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-generic.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-generic.c 2011-03-09 13:19:09.796507904 +0100 +@@ -33,18 +33,17 @@ + static struct omap_board_config_kernel generic_config[] = { + }; + +-static void __init omap_generic_init_irq(void) ++static void __init omap_generic_init_early(void) + { +- omap_board_config = generic_config; +- omap_board_config_size = ARRAY_SIZE(generic_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + static void __init omap_generic_init(void) + { + omap_serial_init(); ++ omap_board_config = generic_config; ++ omap_board_config_size = ARRAY_SIZE(generic_config); + } + + static void __init omap_generic_map_io(void) +@@ -68,9 +67,10 @@ + MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") + /* Maintainer: Paul Mundt */ + .boot_params = 0x80000100, +- .map_io = omap_generic_map_io, + .reserve = omap_reserve, +- .init_irq = omap_generic_init_irq, ++ .map_io = omap_generic_map_io, ++ .init_early = omap_generic_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_generic_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-h4.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-h4.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-h4.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-h4.c 2011-03-09 13:19:09.796507904 +0100 +@@ -290,12 +290,14 @@ + { OMAP_TAG_LCD, &h4_lcd_config }, + }; + +-static void __init omap_h4_init_irq(void) ++static void __init omap_h4_init_early(void) + { +- omap_board_config = h4_config; +- omap_board_config_size = ARRAY_SIZE(h4_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); ++} ++ ++static void __init omap_h4_init_irq(void) ++{ + omap_init_irq(); + h4_init_flash(); + } +@@ -330,6 +332,9 @@ + { + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); + ++ omap_board_config = h4_config; ++ omap_board_config_size = ARRAY_SIZE(h4_config); ++ + /* + * Make sure the serial ports are muxed on at this point. + * You have to mux them off in device drivers later on +@@ -378,8 +383,9 @@ + MACHINE_START(OMAP_H4, "OMAP2420 H4 board") + /* Maintainer: Paul Mundt */ + .boot_params = 0x80000100, +- .map_io = omap_h4_map_io, + .reserve = omap_reserve, ++ .map_io = omap_h4_map_io, ++ .init_early = omap_h4_init_early, + .init_irq = omap_h4_init_irq, + .init_machine = omap_h4_init, + .timer = &omap_timer, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0020.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0020.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0020.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0020.c 2011-03-09 13:19:09.796507904 +0100 +@@ -250,7 +250,7 @@ + #endif + + static struct regulator_consumer_supply igep2_vmmc1_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); + + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ + static struct regulator_init_data igep2_vmmc1 = { +@@ -268,7 +268,7 @@ + }; + + static struct regulator_consumer_supply igep2_vio_supply = +- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); ++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); + + static struct regulator_init_data igep2_vio = { + .constraints = { +@@ -286,7 +286,7 @@ + }; + + static struct regulator_consumer_supply igep2_vmmc2_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); + + static struct regulator_init_data igep2_vmmc2 = { + .constraints = { +@@ -485,17 +485,9 @@ + .default_device = &igep2_dvi_device, + }; + +-static struct platform_device igep2_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &igep2_dss_data, +- }, +-}; +- +-static struct regulator_consumer_supply igep2_vpll2_supply = { +- .supply = "vdds_dsi", +- .dev = &igep2_dss_device.dev, ++static struct regulator_consumer_supply igep2_vpll2_supplies[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + }; + + static struct regulator_init_data igep2_vpll2 = { +@@ -509,8 +501,8 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &igep2_vpll2_supply, ++ .num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies), ++ .consumer_supplies = igep2_vpll2_supplies, + }; + + static void __init igep2_display_init(void) +@@ -521,21 +513,17 @@ + } + + static struct platform_device *igep2_devices[] __initdata = { +- &igep2_dss_device, + &igep2_vwlan_device, + }; + +-static void __init igep2_init_irq(void) ++static void __init igep2_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(m65kxxxxam_sdrc_params, + m65kxxxxam_sdrc_params); +- omap_init_irq(); + } + +-static struct twl4030_codec_audio_data igep2_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data igep2_audio_data; + + static struct twl4030_codec_data igep2_codec_data = { + .audio_mclk = 26000000, +@@ -697,6 +685,7 @@ + /* Register I2C busses and drivers */ + igep2_i2c_init(); + platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); ++ omap_display_init(&igep2_dss_data); + omap_serial_init(); + usb_musb_init(&musb_board_data); + usb_ehci_init(&ehci_pdata); +@@ -716,9 +705,10 @@ + + MACHINE_START(IGEP0020, "IGEP v2 board") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = igep2_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = igep2_init_early, ++ .init_irq = omap_init_irq, + .init_machine = igep2_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0030.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0030.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0030.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0030.c 2011-03-09 13:19:09.797507884 +0100 +@@ -142,7 +142,7 @@ + #endif + + static struct regulator_consumer_supply igep3_vmmc1_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); + + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ + static struct regulator_init_data igep3_vmmc1 = { +@@ -160,7 +160,7 @@ + }; + + static struct regulator_consumer_supply igep3_vio_supply = +- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); ++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); + + static struct regulator_init_data igep3_vio = { + .constraints = { +@@ -178,7 +178,7 @@ + }; + + static struct regulator_consumer_supply igep3_vmmc2_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); + + static struct regulator_init_data igep3_vmmc2 = { + .constraints = { +@@ -331,12 +331,11 @@ + &igep3_vwlan_device, + }; + +-static void __init igep3_init_irq(void) ++static void __init igep3_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(m65kxxxxam_sdrc_params, + m65kxxxxam_sdrc_params); +- omap_init_irq(); + } + + static struct twl4030_platform_data igep3_twl4030_pdata = { +@@ -452,7 +451,8 @@ + .boot_params = 0x80000100, + .reserve = omap_reserve, + .map_io = omap3_map_io, +- .init_irq = igep3_init_irq, ++ .init_early = igep3_init_early, ++ .init_irq = omap_init_irq, + .init_machine = igep3_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-ldp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ldp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-ldp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ldp.c 2011-03-09 13:19:09.797507884 +0100 +@@ -288,13 +288,10 @@ + { OMAP_TAG_LCD, &ldp_lcd_config }, + }; + +-static void __init omap_ldp_init_irq(void) ++static void __init omap_ldp_init_early(void) + { +- omap_board_config = ldp_config; +- omap_board_config_size = ARRAY_SIZE(ldp_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + static struct twl4030_usb_data ldp_usb_data = { +@@ -330,6 +327,26 @@ + .consumer_supplies = &ldp_vmmc1_supply, + }; + ++/* ads7846 on SPI */ ++static struct regulator_consumer_supply ldp_vaux1_supplies[] = { ++ REGULATOR_SUPPLY("vcc", "spi1.0"), ++}; ++ ++/* VAUX1 */ ++static struct regulator_init_data ldp_vaux1 = { ++ .constraints = { ++ .min_uV = 3000000, ++ .max_uV = 3000000, ++ .apply_uV = true, ++ .valid_modes_mask = REGULATOR_MODE_NORMAL ++ | REGULATOR_MODE_STANDBY, ++ .valid_ops_mask = REGULATOR_CHANGE_MODE ++ | REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies), ++ .consumer_supplies = ldp_vaux1_supplies, ++}; ++ + static struct twl4030_platform_data ldp_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, +@@ -338,6 +355,7 @@ + .madc = &ldp_madc_data, + .usb = &ldp_usb_data, + .vmmc1 = &ldp_vmmc1, ++ .vaux1 = &ldp_vaux1, + .gpio = &ldp_gpio_data, + .keypad = &ldp_kp_twl4030_data, + }; +@@ -423,6 +441,8 @@ + static void __init omap_ldp_init(void) + { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); ++ omap_board_config = ldp_config; ++ omap_board_config_size = ARRAY_SIZE(ldp_config); + ldp_init_smsc911x(); + omap_i2c_init(); + platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); +@@ -434,7 +454,7 @@ + omap_serial_init(); + usb_musb_init(&musb_board_data); + board_nand_init(ldp_nand_partitions, +- ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); ++ ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); + + omap2_hsmmc_init(mmc); + /* link regulators to MMC adapters */ +@@ -443,9 +463,10 @@ + + MACHINE_START(OMAP_LDP, "OMAP LDP board") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = omap_ldp_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = omap_ldp_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_ldp_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-n8x0.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-n8x0.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-n8x0.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-n8x0.c 2011-03-09 13:19:09.797507884 +0100 +@@ -536,7 +536,7 @@ + } + + mmc_data[0] = &mmc1_data; +- omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC); ++ omap242x_init_mmc(mmc_data); + } + #else + +@@ -628,11 +628,10 @@ + omap242x_map_common_io(); + } + +-static void __init n8x0_init_irq(void) ++static void __init n8x0_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + #ifdef CONFIG_OMAP_MUX +@@ -703,27 +702,30 @@ + + MACHINE_START(NOKIA_N800, "Nokia N800") + .boot_params = 0x80000100, +- .map_io = n8x0_map_io, + .reserve = omap_reserve, +- .init_irq = n8x0_init_irq, ++ .map_io = n8x0_map_io, ++ .init_early = n8x0_init_early, ++ .init_irq = omap_init_irq, + .init_machine = n8x0_init_machine, + .timer = &omap_timer, + MACHINE_END + + MACHINE_START(NOKIA_N810, "Nokia N810") + .boot_params = 0x80000100, +- .map_io = n8x0_map_io, + .reserve = omap_reserve, +- .init_irq = n8x0_init_irq, ++ .map_io = n8x0_map_io, ++ .init_early = n8x0_init_early, ++ .init_irq = omap_init_irq, + .init_machine = n8x0_init_machine, + .timer = &omap_timer, + MACHINE_END + + MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") + .boot_params = 0x80000100, +- .map_io = n8x0_map_io, + .reserve = omap_reserve, +- .init_irq = n8x0_init_irq, ++ .map_io = n8x0_map_io, ++ .init_early = n8x0_init_early, ++ .init_irq = omap_init_irq, + .init_machine = n8x0_init_machine, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3beagle.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3beagle.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3beagle.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3beagle.c 2011-03-09 13:19:09.797507884 +0100 +@@ -228,19 +228,13 @@ + .default_device = &beagle_dvi_device, + }; + +-static struct platform_device beagle_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &beagle_dss_data, +- }, +-}; +- + static struct regulator_consumer_supply beagle_vdac_supply = +- REGULATOR_SUPPLY("vdda_dac", "omapdss"); ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + +-static struct regulator_consumer_supply beagle_vdvi_supply = +- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); ++static struct regulator_consumer_supply beagle_vdvi_supplies[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), ++}; + + static void __init beagle_display_init(void) + { +@@ -427,17 +421,15 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &beagle_vdvi_supply, ++ .num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies), ++ .consumer_supplies = beagle_vdvi_supplies, + }; + + static struct twl4030_usb_data beagle_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, + }; + +-static struct twl4030_codec_audio_data beagle_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data beagle_audio_data; + + static struct twl4030_codec_data beagle_codec_data = { + .audio_mclk = 26000000, +@@ -536,11 +528,15 @@ + }, + }; + +-static void __init omap3_beagle_init_irq(void) ++static void __init omap3_beagle_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); ++} ++ ++static void __init omap3_beagle_init_irq(void) ++{ + omap_init_irq(); + #ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +@@ -550,7 +546,6 @@ + static struct platform_device *omap3_beagle_devices[] __initdata = { + &leds_gpio, + &keys_gpio, +- &beagle_dss_device, + }; + + static void __init omap3beagle_flash_init(void) +@@ -617,6 +612,7 @@ + omap3_beagle_i2c_init(); + platform_add_devices(omap3_beagle_devices, + ARRAY_SIZE(omap3_beagle_devices)); ++ omap_display_init(&beagle_dss_data); + omap_serial_init(); + + omap_mux_init_gpio(170, OMAP_PIN_INPUT); +@@ -638,8 +634,9 @@ + MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") + /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, ++ .map_io = omap3_map_io, ++ .init_early = omap3_beagle_init_early, + .init_irq = omap3_beagle_init_irq, + .init_machine = omap3_beagle_init, + .timer = &omap_timer, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3evm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3evm.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3evm.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3evm.c 2011-03-09 13:19:09.798507865 +0100 +@@ -30,6 +30,8 @@ + #include + #include + ++#include ++#include + #include + #include + +@@ -58,6 +60,13 @@ + #define OMAP3EVM_ETHR_ID_REV 0x50 + #define OMAP3EVM_ETHR_GPIO_IRQ 176 + #define OMAP3EVM_SMSC911X_CS 5 ++/* ++ * Eth Reset signal ++ * 64 = Generation 1 (<=RevD) ++ * 7 = Generation 2 (>=RevE) ++ */ ++#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 ++#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 + + static u8 omap3_evm_version; + +@@ -124,10 +133,15 @@ + + static inline void __init omap3evm_init_smsc911x(void) + { +- int eth_cs; ++ int eth_cs, eth_rst; + struct clk *l3ck; + unsigned int rate; + ++ if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) ++ eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST; ++ else ++ eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST; ++ + eth_cs = OMAP3EVM_SMSC911X_CS; + + l3ck = clk_get(NULL, "l3_ck"); +@@ -136,6 +150,27 @@ + else + rate = clk_get_rate(l3ck); + ++ /* Configure ethernet controller reset gpio */ ++ if (cpu_is_omap3430()) { ++ if (gpio_request(eth_rst, "SMSC911x gpio") < 0) { ++ pr_err(KERN_ERR "Failed to request %d for smsc911x\n", ++ eth_rst); ++ return; ++ } ++ ++ if (gpio_direction_output(eth_rst, 1) < 0) { ++ pr_err(KERN_ERR "Failed to set direction of %d for" \ ++ " smsc911x\n", eth_rst); ++ return; ++ } ++ /* reset pulse to ethernet controller*/ ++ usleep_range(150, 220); ++ gpio_set_value(eth_rst, 0); ++ usleep_range(150, 220); ++ gpio_set_value(eth_rst, 1); ++ usleep_range(1, 2); ++ } ++ + if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", + OMAP3EVM_ETHR_GPIO_IRQ); +@@ -235,9 +270,9 @@ + gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) +- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); ++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); + else +- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); ++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); + + lcd_enabled = 1; + return 0; +@@ -248,9 +283,9 @@ + gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) +- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); ++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); + else +- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); ++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); + + lcd_enabled = 0; + } +@@ -289,7 +324,7 @@ + return -EINVAL; + } + +- gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); ++ gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); + + dvi_enabled = 1; + return 0; +@@ -297,7 +332,7 @@ + + static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) + { +- gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); ++ gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); + + dvi_enabled = 0; + } +@@ -328,14 +363,6 @@ + .default_device = &omap3_evm_lcd_device, + }; + +-static struct platform_device omap3_evm_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &omap3_evm_dss_data, +- }, +-}; +- + static struct regulator_consumer_supply omap3evm_vmmc1_supply = { + .supply = "vmmc", + }; +@@ -381,6 +408,16 @@ + .gpio_cd = -EINVAL, + .gpio_wp = 63, + }, ++#ifdef CONFIG_WL12XX_PLATFORM_DATA ++ { ++ .name = "wl1271", ++ .mmc = 2, ++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, ++ .gpio_wp = -EINVAL, ++ .gpio_cd = -EINVAL, ++ .nonremovable = true, ++ }, ++#endif + {} /* Terminator */ + }; + +@@ -411,6 +448,8 @@ + static int omap3evm_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) + { ++ int r; ++ + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + omap_mux_init_gpio(63, OMAP_PIN_INPUT); + mmc[0].gpio_cd = gpio + 0; +@@ -426,8 +465,12 @@ + */ + + /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ +- gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); +- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); ++ r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); ++ if (!r) ++ r = gpio_direction_output(gpio + TWL4030_GPIO_MAX, ++ (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0); ++ if (r) ++ printk(KERN_ERR "failed to get/set lcd_bkl gpio\n"); + + /* gpio + 7 == DVI Enable */ + gpio_request(gpio + 7, "EN_DVI"); +@@ -491,19 +534,15 @@ + .irq_line = 1, + }; + +-static struct twl4030_codec_audio_data omap3evm_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data omap3evm_audio_data; + + static struct twl4030_codec_data omap3evm_codec_data = { + .audio_mclk = 26000000, + .audio = &omap3evm_audio_data, + }; + +-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = { +- .supply = "vdda_dac", +- .dev = &omap3_evm_dss_device.dev, +-}; ++static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + + /* VDAC for DSS driving S-Video */ + static struct regulator_init_data omap3_evm_vdac = { +@@ -521,8 +560,10 @@ + }; + + /* VPLL2 for digital video outputs */ +-static struct regulator_consumer_supply omap3_evm_vpll2_supply = +- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); ++static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), ++}; + + static struct regulator_init_data omap3_evm_vpll2 = { + .constraints = { +@@ -534,10 +575,70 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, ++ .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies), ++ .consumer_supplies = omap3_evm_vpll2_supplies, ++}; ++ ++/* ads7846 on SPI */ ++static struct regulator_consumer_supply omap3evm_vio_supply = ++ REGULATOR_SUPPLY("vcc", "spi1.0"); ++ ++/* VIO for ads7846 */ ++static struct regulator_init_data omap3evm_vio = { ++ .constraints = { ++ .min_uV = 1800000, ++ .max_uV = 1800000, ++ .apply_uV = true, ++ .valid_modes_mask = REGULATOR_MODE_NORMAL ++ | REGULATOR_MODE_STANDBY, ++ .valid_ops_mask = REGULATOR_CHANGE_MODE ++ | REGULATOR_CHANGE_STATUS, ++ }, + .num_consumer_supplies = 1, +- .consumer_supplies = &omap3_evm_vpll2_supply, ++ .consumer_supplies = &omap3evm_vio_supply, + }; + ++#ifdef CONFIG_WL12XX_PLATFORM_DATA ++ ++#define OMAP3EVM_WLAN_PMENA_GPIO (150) ++#define OMAP3EVM_WLAN_IRQ_GPIO (149) ++ ++static struct regulator_consumer_supply omap3evm_vmmc2_supply = ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); ++ ++/* VMMC2 for driving the WL12xx module */ ++static struct regulator_init_data omap3evm_vmmc2 = { ++ .constraints = { ++ .valid_ops_mask = REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = 1, ++ .consumer_supplies = &omap3evm_vmmc2_supply, ++}; ++ ++static struct fixed_voltage_config omap3evm_vwlan = { ++ .supply_name = "vwl1271", ++ .microvolts = 1800000, /* 1.80V */ ++ .gpio = OMAP3EVM_WLAN_PMENA_GPIO, ++ .startup_delay = 70000, /* 70ms */ ++ .enable_high = 1, ++ .enabled_at_boot = 0, ++ .init_data = &omap3evm_vmmc2, ++}; ++ ++static struct platform_device omap3evm_wlan_regulator = { ++ .name = "reg-fixed-voltage", ++ .id = 1, ++ .dev = { ++ .platform_data = &omap3evm_vwlan, ++ }, ++}; ++ ++struct wl12xx_platform_data omap3evm_wlan_data __initdata = { ++ .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO), ++ .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ ++}; ++#endif ++ + static struct twl4030_platform_data omap3evm_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, +@@ -550,6 +651,7 @@ + .codec = &omap3evm_codec_data, + .vdac = &omap3_evm_vdac, + .vpll2 = &omap3_evm_vpll2, ++ .vio = &omap3evm_vio, + }; + + static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { +@@ -625,19 +727,12 @@ + static struct omap_board_config_kernel omap3_evm_config[] __initdata = { + }; + +-static void __init omap3_evm_init_irq(void) ++static void __init omap3_evm_init_early(void) + { +- omap_board_config = omap3_evm_config; +- omap_board_config_size = ARRAY_SIZE(omap3_evm_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); +- omap_init_irq(); + } + +-static struct platform_device *omap3_evm_devices[] __initdata = { +- &omap3_evm_dss_device, +-}; +- + static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { + + .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, +@@ -652,14 +747,76 @@ + }; + + #ifdef CONFIG_OMAP_MUX +-static struct omap_board_mux board_mux[] __initdata = { ++static struct omap_board_mux omap35x_board_mux[] __initdata = { ++ OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | ++ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | ++ OMAP_PIN_OFF_WAKEUPENABLE), ++ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | ++ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | ++ OMAP_PIN_OFF_WAKEUPENABLE), ++ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | ++ OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | ++ OMAP_PIN_OFF_NONE), ++#ifdef CONFIG_WL12XX_PLATFORM_DATA ++ /* WLAN IRQ - GPIO 149 */ ++ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), ++ ++ /* WLAN POWER ENABLE - GPIO 150 */ ++ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), ++ ++ /* MMC2 SDIO pin muxes for WL12xx */ ++ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++#endif ++ { .reg_offset = OMAP_MUX_TERMINATOR }, ++}; ++ ++static struct omap_board_mux omap36x_board_mux[] __initdata = { + OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | +- OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), ++ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | ++ OMAP_PIN_OFF_WAKEUPENABLE), ++ /* AM/DM37x EVM: DSS data bus muxed with sys_boot */ ++ OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++ OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), ++#ifdef CONFIG_WL12XX_PLATFORM_DATA ++ /* WLAN IRQ - GPIO 149 */ ++ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), ++ ++ /* WLAN POWER ENABLE - GPIO 150 */ ++ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), ++ ++ /* MMC2 SDIO pin muxes for WL12xx */ ++ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++#endif ++ + { .reg_offset = OMAP_MUX_TERMINATOR }, + }; ++#else ++#define omap35x_board_mux NULL ++#define omap36x_board_mux NULL + #endif + + static struct omap_musb_board_data musb_board_data = { +@@ -671,11 +828,18 @@ + static void __init omap3_evm_init(void) + { + omap3_evm_get_revision(); +- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); ++ ++ if (cpu_is_omap3630()) ++ omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB); ++ else ++ omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB); ++ ++ omap_board_config = omap3_evm_config; ++ omap_board_config_size = ARRAY_SIZE(omap3_evm_config); + + omap3_evm_i2c_init(); + +- platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices)); ++ omap_display_init(&omap3_evm_dss_data); + + spi_register_board_info(omap3evm_spi_board_info, + ARRAY_SIZE(omap3evm_spi_board_info)); +@@ -715,14 +879,22 @@ + ads7846_dev_init(); + omap3evm_init_smsc911x(); + omap3_evm_display_init(); ++ ++#ifdef CONFIG_WL12XX_PLATFORM_DATA ++ /* WL12xx WLAN Init */ ++ if (wl12xx_set_platform_data(&omap3evm_wlan_data)) ++ pr_err("error setting wl12xx data\n"); ++ platform_device_register(&omap3evm_wlan_regulator); ++#endif + } + + MACHINE_START(OMAP3EVM, "OMAP3 EVM") + /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = omap3_evm_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = omap3_evm_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap3_evm_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3logic.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3logic.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3logic.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3logic.c 2011-03-09 13:19:09.798507865 +0100 +@@ -195,11 +195,10 @@ + gpmc_smsc911x_init(&board_smsc911x_data); + } + +-static void __init omap3logic_init_irq(void) ++static void __init omap3logic_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- omap_init_irq(); + } + + #ifdef CONFIG_OMAP_MUX +@@ -225,7 +224,8 @@ + MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") + .boot_params = 0x80000100, + .map_io = omap3_map_io, +- .init_irq = omap3logic_init_irq, ++ .init_early = omap3logic_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap3logic_init, + .timer = &omap_timer, + MACHINE_END +@@ -233,7 +233,8 @@ + MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") + .boot_params = 0x80000100, + .map_io = omap3_map_io, +- .init_irq = omap3logic_init_irq, ++ .init_early = omap3logic_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap3logic_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3pandora.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3pandora.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3pandora.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3pandora.c 2011-03-09 13:19:09.798507865 +0100 +@@ -253,14 +253,6 @@ + .default_device = &pandora_lcd_device, + }; + +-static struct platform_device pandora_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &pandora_dss_data, +- }, +-}; +- + static void pandora_wl1251_init_card(struct mmc_card *card) + { + /* +@@ -341,20 +333,21 @@ + }; + + static struct regulator_consumer_supply pandora_vmmc1_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); + + static struct regulator_consumer_supply pandora_vmmc2_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); + + static struct regulator_consumer_supply pandora_vmmc3_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"); + + static struct regulator_consumer_supply pandora_vdda_dac_supply = +- REGULATOR_SUPPLY("vdda_dac", "omapdss"); ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + + static struct regulator_consumer_supply pandora_vdds_supplies[] = { + REGULATOR_SUPPLY("vdds_sdi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + }; + + static struct regulator_consumer_supply pandora_vcc_lcd_supply = +@@ -524,9 +517,7 @@ + .usb_mode = T2_USB_MODE_ULPI, + }; + +-static struct twl4030_codec_audio_data omap3pandora_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data omap3pandora_audio_data; + + static struct twl4030_codec_data omap3pandora_codec_data = { + .audio_mclk = 26000000, +@@ -634,12 +625,11 @@ + } + }; + +-static void __init omap3pandora_init_irq(void) ++static void __init omap3pandora_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); +- omap_init_irq(); + } + + static void __init pandora_wl1251_init(void) +@@ -677,7 +667,6 @@ + static struct platform_device *omap3pandora_devices[] __initdata = { + &pandora_leds_gpio, + &pandora_keys_gpio, +- &pandora_dss_device, + &pandora_vwlan_device, + }; + +@@ -712,6 +701,7 @@ + pandora_wl1251_init(); + platform_add_devices(omap3pandora_devices, + ARRAY_SIZE(omap3pandora_devices)); ++ omap_display_init(&pandora_dss_data); + omap_serial_init(); + spi_register_board_info(omap3pandora_spi_board_info, + ARRAY_SIZE(omap3pandora_spi_board_info)); +@@ -727,9 +717,10 @@ + + MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = omap3pandora_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = omap3pandora_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap3pandora_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3stalker.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3stalker.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3stalker.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3stalker.c 2011-03-09 13:19:09.799507845 +0100 +@@ -240,14 +240,6 @@ + .default_device = &omap3_stalker_dvi_device, + }; + +-static struct platform_device omap3_stalker_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &omap3_stalker_dss_data, +- }, +-}; +- + static struct regulator_consumer_supply omap3stalker_vmmc1_supply = { + .supply = "vmmc", + }; +@@ -439,19 +431,15 @@ + .irq_line = 1, + }; + +-static struct twl4030_codec_audio_data omap3stalker_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data omap3stalker_audio_data; + + static struct twl4030_codec_data omap3stalker_codec_data = { + .audio_mclk = 26000000, + .audio = &omap3stalker_audio_data, + }; + +-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = { +- .supply = "vdda_dac", +- .dev = &omap3_stalker_dss_device.dev, +-}; ++static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + + /* VDAC for DSS driving S-Video */ + static struct regulator_init_data omap3_stalker_vdac = { +@@ -469,9 +457,9 @@ + }; + + /* VPLL2 for digital video outputs */ +-static struct regulator_consumer_supply omap3_stalker_vpll2_supply = { +- .supply = "vdds_dsi", +- .dev = &omap3_stalker_lcd_device.dev, ++static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + }; + + static struct regulator_init_data omap3_stalker_vpll2 = { +@@ -485,8 +473,8 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &omap3_stalker_vpll2_supply, ++ .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies), ++ .consumer_supplies = omap3_stalker_vpll2_supplies, + }; + + static struct twl4030_platform_data omap3stalker_twldata = { +@@ -591,12 +579,14 @@ + static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { + }; + +-static void __init omap3_stalker_init_irq(void) ++static void __init omap3_stalker_init_early(void) + { +- omap_board_config = omap3_stalker_config; +- omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); ++} ++ ++static void __init omap3_stalker_init_irq(void) ++{ + omap_init_irq(); + #ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +@@ -604,7 +594,6 @@ + } + + static struct platform_device *omap3_stalker_devices[] __initdata = { +- &omap3_stalker_dss_device, + &keys_gpio, + }; + +@@ -638,12 +627,15 @@ + static void __init omap3_stalker_init(void) + { + omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); ++ omap_board_config = omap3_stalker_config; ++ omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); + + omap3_stalker_i2c_init(); + + platform_add_devices(omap3_stalker_devices, + ARRAY_SIZE(omap3_stalker_devices)); + ++ omap_display_init(&omap3_stalker_dss_data); + spi_register_board_info(omap3stalker_spi_board_info, + ARRAY_SIZE(omap3stalker_spi_board_info)); + +@@ -666,6 +658,7 @@ + /* Maintainer: Jason Lam -lzg@ema-tech.com */ + .boot_params = 0x80000100, + .map_io = omap3_map_io, ++ .init_early = omap3_stalker_init_early, + .init_irq = omap3_stalker_init_irq, + .init_machine = omap3_stalker_init, + .timer = &omap_timer, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3touchbook.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3touchbook.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3touchbook.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3touchbook.c 2011-03-09 13:19:09.799507845 +0100 +@@ -252,9 +252,7 @@ + .usb_mode = T2_USB_MODE_ULPI, + }; + +-static struct twl4030_codec_audio_data touchbook_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data touchbook_audio_data; + + static struct twl4030_codec_data touchbook_codec_data = { + .audio_mclk = 26000000, +@@ -415,14 +413,15 @@ + }; + #endif + +-static void __init omap3_touchbook_init_irq(void) ++static void __init omap3_touchbook_init_early(void) + { +- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); +- omap_board_config = omap3_touchbook_config; +- omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); ++} ++ ++static void __init omap3_touchbook_init_irq(void) ++{ + omap_init_irq(); + #ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +@@ -510,6 +509,10 @@ + + static void __init omap3_touchbook_init(void) + { ++ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); ++ omap_board_config = omap3_touchbook_config; ++ omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); ++ + pm_power_off = omap3_touchbook_poweroff; + + omap3_touchbook_i2c_init(); +@@ -538,8 +541,9 @@ + MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") + /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, ++ .map_io = omap3_map_io, ++ .init_early = omap3_touchbook_init_early, + .init_irq = omap3_touchbook_init_irq, + .init_machine = omap3_touchbook_init, + .timer = &omap_timer, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap4panda.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap4panda.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap4panda.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap4panda.c 2011-03-09 13:19:09.799507845 +0100 +@@ -26,6 +26,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -45,6 +47,18 @@ + + #define GPIO_HUB_POWER 1 + #define GPIO_HUB_NRESET 62 ++#define GPIO_WIFI_PMENA 43 ++#define GPIO_WIFI_IRQ 53 ++ ++/* wl127x BT, FM, GPS connectivity chip */ ++static int wl1271_gpios[] = {46, -1, -1}; ++static struct platform_device wl1271_device = { ++ .name = "kim", ++ .id = -1, ++ .dev = { ++ .platform_data = &wl1271_gpios, ++ }, ++}; + + static struct gpio_led gpio_leds[] = { + { +@@ -74,13 +88,13 @@ + + static struct platform_device *panda_devices[] __initdata = { + &leds_gpio, ++ &wl1271_device, + }; + +-static void __init omap4_panda_init_irq(void) ++static void __init omap4_panda_init_early(void) + { + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); +- gic_init_irq(); + } + + static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +@@ -162,16 +176,62 @@ + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + }, ++ { ++ .name = "wl1271", ++ .mmc = 5, ++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, ++ .gpio_wp = -EINVAL, ++ .gpio_cd = -EINVAL, ++ .ocr_mask = MMC_VDD_165_195, ++ .nonremovable = true, ++ }, + {} /* Terminator */ + }; + + static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { + { + .supply = "vmmc", +- .dev_name = "mmci-omap-hs.0", ++ .dev_name = "omap_hsmmc.0", ++ }, ++}; ++ ++static struct regulator_consumer_supply omap4_panda_vmmc5_supply = { ++ .supply = "vmmc", ++ .dev_name = "omap_hsmmc.4", ++}; ++ ++static struct regulator_init_data panda_vmmc5 = { ++ .constraints = { ++ .valid_ops_mask = REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = 1, ++ .consumer_supplies = &omap4_panda_vmmc5_supply, ++}; ++ ++static struct fixed_voltage_config panda_vwlan = { ++ .supply_name = "vwl1271", ++ .microvolts = 1800000, /* 1.8V */ ++ .gpio = GPIO_WIFI_PMENA, ++ .startup_delay = 70000, /* 70msec */ ++ .enable_high = 1, ++ .enabled_at_boot = 0, ++ .init_data = &panda_vmmc5, ++}; ++ ++static struct platform_device omap_vwlan_device = { ++ .name = "reg-fixed-voltage", ++ .id = 1, ++ .dev = { ++ .platform_data = &panda_vwlan, + }, + }; + ++struct wl12xx_platform_data omap_panda_wlan_data __initdata = { ++ .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ), ++ /* PANDA ref clock is 38.4 MHz */ ++ .board_ref_clock = 2, ++}; ++ + static int omap4_twl6030_hsmmc_late_init(struct device *dev) + { + int ret = 0; +@@ -305,7 +365,6 @@ + .constraints = { + .min_uV = 2100000, + .max_uV = 2100000, +- .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE +@@ -317,7 +376,6 @@ + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, +- .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE +@@ -329,7 +387,6 @@ + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, +- .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE +@@ -391,6 +448,19 @@ + + #ifdef CONFIG_OMAP_MUX + static struct omap_board_mux board_mux[] __initdata = { ++ /* WLAN IRQ - GPIO 53 */ ++ OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), ++ /* WLAN POWER ENABLE - GPIO 43 */ ++ OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), ++ /* WLAN SDIO: MMC5 CMD */ ++ OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ /* WLAN SDIO: MMC5 CLK */ ++ OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ /* WLAN SDIO: MMC5 DAT[0-3] */ ++ OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), ++ OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + { .reg_offset = OMAP_MUX_TERMINATOR }, + }; + #else +@@ -405,8 +475,12 @@ + package = OMAP_PACKAGE_CBL; + omap4_mux_init(board_mux, package); + ++ if (wl12xx_set_platform_data(&omap_panda_wlan_data)) ++ pr_err("error setting wl12xx data\n"); ++ + omap4_panda_i2c_init(); + platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); ++ platform_device_register(&omap_vwlan_device); + omap_serial_init(); + omap4_twl6030_hsmmc_init(mmc); + omap4_ehci_init(); +@@ -424,7 +498,8 @@ + .boot_params = 0x80000100, + .reserve = omap_reserve, + .map_io = omap4_panda_map_io, +- .init_irq = omap4_panda_init_irq, ++ .init_early = omap4_panda_init_early, ++ .init_irq = gic_init_irq, + .init_machine = omap4_panda_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-overo.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-overo.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-overo.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-overo.c 2011-03-09 13:19:09.799507845 +0100 +@@ -28,6 +28,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -41,10 +43,14 @@ + + #include + #include ++#include ++#include + #include + #include + #include + #include ++#include ++#include + #include + + #include "mux.h" +@@ -68,8 +74,6 @@ + #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ + defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + +-#include +-#include + #include + + static struct omap2_mcspi_device_config ads7846_mcspi_config = { +@@ -94,16 +98,32 @@ + .keep_vref_on = 1, + }; + +-static struct spi_board_info overo_spi_board_info[] __initdata = { +- { +- .modalias = "ads7846", +- .bus_num = 1, +- .chip_select = 0, +- .max_speed_hz = 1500000, +- .controller_data = &ads7846_mcspi_config, +- .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), +- .platform_data = &ads7846_config, +- } ++/* fixed regulator for ads7846 */ ++static struct regulator_consumer_supply ads7846_supply = ++ REGULATOR_SUPPLY("vcc", "spi1.0"); ++ ++static struct regulator_init_data vads7846_regulator = { ++ .constraints = { ++ .valid_ops_mask = REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = 1, ++ .consumer_supplies = &ads7846_supply, ++}; ++ ++static struct fixed_voltage_config vads7846 = { ++ .supply_name = "vads7846", ++ .microvolts = 3300000, /* 3.3V */ ++ .gpio = -EINVAL, ++ .startup_delay = 0, ++ .init_data = &vads7846_regulator, ++}; ++ ++static struct platform_device vads7846_device = { ++ .name = "reg-fixed-voltage", ++ .id = 1, ++ .dev = { ++ .platform_data = &vads7846, ++ }, + }; + + static void __init overo_ads7846_init(void) +@@ -116,8 +136,7 @@ + return; + } + +- spi_register_board_info(overo_spi_board_info, +- ARRAY_SIZE(overo_spi_board_info)); ++ platform_device_register(&vads7846_device); + } + + #else +@@ -233,6 +252,137 @@ + static inline void __init overo_init_smsc911x(void) { return; } + #endif + ++/* DSS */ ++static int lcd_enabled; ++static int dvi_enabled; ++ ++#define OVERO_GPIO_LCD_EN 144 ++#define OVERO_GPIO_LCD_BL 145 ++ ++static void __init overo_display_init(void) ++{ ++ if ((gpio_request(OVERO_GPIO_LCD_EN, "OVERO_GPIO_LCD_EN") == 0) && ++ (gpio_direction_output(OVERO_GPIO_LCD_EN, 1) == 0)) ++ gpio_export(OVERO_GPIO_LCD_EN, 0); ++ else ++ printk(KERN_ERR "could not obtain gpio for " ++ "OVERO_GPIO_LCD_EN\n"); ++ ++ if ((gpio_request(OVERO_GPIO_LCD_BL, "OVERO_GPIO_LCD_BL") == 0) && ++ (gpio_direction_output(OVERO_GPIO_LCD_BL, 1) == 0)) ++ gpio_export(OVERO_GPIO_LCD_BL, 0); ++ else ++ printk(KERN_ERR "could not obtain gpio for " ++ "OVERO_GPIO_LCD_BL\n"); ++} ++ ++static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) ++{ ++ if (lcd_enabled) { ++ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); ++ return -EINVAL; ++ } ++ dvi_enabled = 1; ++ ++ return 0; ++} ++ ++static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) ++{ ++ dvi_enabled = 0; ++} ++ ++static struct panel_generic_dpi_data dvi_panel = { ++ .name = "generic", ++ .platform_enable = overo_panel_enable_dvi, ++ .platform_disable = overo_panel_disable_dvi, ++}; ++ ++static struct omap_dss_device overo_dvi_device = { ++ .name = "dvi", ++ .type = OMAP_DISPLAY_TYPE_DPI, ++ .driver_name = "generic_dpi_panel", ++ .data = &dvi_panel, ++ .phy.dpi.data_lines = 24, ++}; ++ ++static struct omap_dss_device overo_tv_device = { ++ .name = "tv", ++ .driver_name = "venc", ++ .type = OMAP_DISPLAY_TYPE_VENC, ++ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, ++}; ++ ++static int overo_panel_enable_lcd(struct omap_dss_device *dssdev) ++{ ++ if (dvi_enabled) { ++ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); ++ return -EINVAL; ++ } ++ ++ gpio_set_value(OVERO_GPIO_LCD_EN, 1); ++ gpio_set_value(OVERO_GPIO_LCD_BL, 1); ++ lcd_enabled = 1; ++ return 0; ++} ++ ++static void overo_panel_disable_lcd(struct omap_dss_device *dssdev) ++{ ++ gpio_set_value(OVERO_GPIO_LCD_EN, 0); ++ gpio_set_value(OVERO_GPIO_LCD_BL, 0); ++ lcd_enabled = 0; ++} ++ ++static struct panel_generic_dpi_data lcd43_panel = { ++ .name = "samsung_lte430wq_f0c", ++ .platform_enable = overo_panel_enable_lcd, ++ .platform_disable = overo_panel_disable_lcd, ++}; ++ ++static struct omap_dss_device overo_lcd43_device = { ++ .name = "lcd43", ++ .type = OMAP_DISPLAY_TYPE_DPI, ++ .driver_name = "generic_dpi_panel", ++ .data = &lcd43_panel, ++ .phy.dpi.data_lines = 24, ++}; ++ ++#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ ++ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) ++static struct omap_dss_device overo_lcd35_device = { ++ .type = OMAP_DISPLAY_TYPE_DPI, ++ .name = "lcd35", ++ .driver_name = "lgphilips_lb035q02_panel", ++ .phy.dpi.data_lines = 24, ++ .platform_enable = overo_panel_enable_lcd, ++ .platform_disable = overo_panel_disable_lcd, ++}; ++#endif ++ ++static struct omap_dss_device *overo_dss_devices[] = { ++ &overo_dvi_device, ++ &overo_tv_device, ++#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ ++ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) ++ &overo_lcd35_device, ++#endif ++ &overo_lcd43_device, ++}; ++ ++static struct omap_dss_board_info overo_dss_data = { ++ .num_devices = ARRAY_SIZE(overo_dss_devices), ++ .devices = overo_dss_devices, ++ .default_device = &overo_dvi_device, ++}; ++ ++static struct regulator_consumer_supply overo_vdda_dac_supply = ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); ++ ++static struct regulator_consumer_supply overo_vdds_dsi_supply[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), ++}; ++ + static struct mtd_partition overo_nand_partitions[] = { + { + .name = "xloader", +@@ -358,17 +508,42 @@ + .consumer_supplies = &overo_vmmc1_supply, + }; + +-static struct twl4030_codec_audio_data overo_audio_data = { +- .audio_mclk = 26000000, ++/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ ++static struct regulator_init_data overo_vdac = { ++ .constraints = { ++ .min_uV = 1800000, ++ .max_uV = 1800000, ++ .valid_modes_mask = REGULATOR_MODE_NORMAL ++ | REGULATOR_MODE_STANDBY, ++ .valid_ops_mask = REGULATOR_CHANGE_MODE ++ | REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = 1, ++ .consumer_supplies = &overo_vdda_dac_supply, + }; + ++/* VPLL2 for digital video outputs */ ++static struct regulator_init_data overo_vpll2 = { ++ .constraints = { ++ .name = "VDVI", ++ .min_uV = 1800000, ++ .max_uV = 1800000, ++ .valid_modes_mask = REGULATOR_MODE_NORMAL ++ | REGULATOR_MODE_STANDBY, ++ .valid_ops_mask = REGULATOR_CHANGE_MODE ++ | REGULATOR_CHANGE_STATUS, ++ }, ++ .num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply), ++ .consumer_supplies = overo_vdds_dsi_supply, ++}; ++ ++static struct twl4030_codec_audio_data overo_audio_data; ++ + static struct twl4030_codec_data overo_codec_data = { + .audio_mclk = 26000000, + .audio = &overo_audio_data, + }; + +-/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */ +- + static struct twl4030_platform_data overo_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, +@@ -376,6 +551,8 @@ + .usb = &overo_usb_data, + .codec = &overo_codec_data, + .vmmc1 = &overo_vmmc1, ++ .vdac = &overo_vdac, ++ .vpll2 = &overo_vpll2, + }; + + static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { +@@ -396,33 +573,46 @@ + return 0; + } + +-static struct platform_device overo_lcd_device = { +- .name = "overo_lcd", +- .id = -1, +-}; +- +-static struct omap_lcd_config overo_lcd_config __initdata = { +- .ctrl_name = "internal", ++static struct spi_board_info overo_spi_board_info[] __initdata = { ++#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ ++ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) ++ { ++ .modalias = "ads7846", ++ .bus_num = 1, ++ .chip_select = 0, ++ .max_speed_hz = 1500000, ++ .controller_data = &ads7846_mcspi_config, ++ .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), ++ .platform_data = &ads7846_config, ++ }, ++#endif ++#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ ++ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) ++ { ++ .modalias = "lgphilips_lb035q02_panel-spi", ++ .bus_num = 1, ++ .chip_select = 1, ++ .max_speed_hz = 500000, ++ .mode = SPI_MODE_3, ++ }, ++#endif + }; + +-static struct omap_board_config_kernel overo_config[] __initdata = { +- { OMAP_TAG_LCD, &overo_lcd_config }, +-}; ++static int __init overo_spi_init(void) ++{ ++ overo_ads7846_init(); ++ spi_register_board_info(overo_spi_board_info, ++ ARRAY_SIZE(overo_spi_board_info)); ++ return 0; ++} + +-static void __init overo_init_irq(void) ++static void __init overo_init_early(void) + { +- omap_board_config = overo_config; +- omap_board_config_size = ARRAY_SIZE(overo_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); +- omap_init_irq(); + } + +-static struct platform_device *overo_devices[] __initdata = { +- &overo_lcd_device, +-}; +- + static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, +@@ -450,13 +640,14 @@ + { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + overo_i2c_init(); +- platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); ++ omap_display_init(&overo_dss_data); + omap_serial_init(); + overo_flash_init(); + usb_musb_init(&musb_board_data); + usb_ehci_init(&ehci_pdata); +- overo_ads7846_init(); ++ overo_spi_init(); + overo_init_smsc911x(); ++ overo_display_init(); + + /* Ensure SDRC pins are mux'd for self-refresh */ + omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); +@@ -501,9 +692,10 @@ + + MACHINE_START(OVERO, "Gumstix Overo") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = overo_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = overo_init_early, ++ .init_irq = omap_init_irq, + .init_machine = overo_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rm680.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rm680.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rm680.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rm680.c 2011-03-09 13:19:09.800507825 +0100 +@@ -33,7 +33,7 @@ + #include "sdram-nokia.h" + + static struct regulator_consumer_supply rm680_vemmc_consumers[] = { +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), + }; + + /* Fixed regulator for internal eMMC */ +@@ -138,14 +138,13 @@ + omap2_hsmmc_init(mmc); + } + +-static void __init rm680_init_irq(void) ++static void __init rm680_init_early(void) + { + struct omap_sdrc_params *sdrc_params; + + omap2_init_common_infrastructure(); + sdrc_params = nokia_get_sdram_timings(); + omap2_init_common_devices(sdrc_params, sdrc_params); +- omap_init_irq(); + } + + #ifdef CONFIG_OMAP_MUX +@@ -176,9 +175,10 @@ + + MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") + .boot_params = 0x80000100, +- .map_io = rm680_map_io, + .reserve = omap_reserve, +- .init_irq = rm680_init_irq, ++ .map_io = rm680_map_io, ++ .init_early = rm680_init_early, ++ .init_irq = omap_init_irq, + .init_machine = rm680_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51.c 2011-03-09 13:19:09.800507825 +0100 +@@ -98,17 +98,13 @@ + { OMAP_TAG_LCD, &rx51_lcd_config }, + }; + +-static void __init rx51_init_irq(void) ++static void __init rx51_init_early(void) + { + struct omap_sdrc_params *sdrc_params; + +- omap_board_config = rx51_config; +- omap_board_config_size = ARRAY_SIZE(rx51_config); +- omap3_pm_init_cpuidle(rx51_cpuidle_params); + omap2_init_common_infrastructure(); + sdrc_params = nokia_get_sdram_timings(); + omap2_init_common_devices(sdrc_params, sdrc_params); +- omap_init_irq(); + } + + extern void __init rx51_peripherals_init(void); +@@ -128,6 +124,9 @@ + static void __init rx51_init(void) + { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); ++ omap_board_config = rx51_config; ++ omap_board_config_size = ARRAY_SIZE(rx51_config); ++ omap3_pm_init_cpuidle(rx51_cpuidle_params); + omap_serial_init(); + usb_musb_init(&musb_board_data); + rx51_peripherals_init(); +@@ -149,9 +148,10 @@ + MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") + /* Maintainer: Lauri Leukkunen */ + .boot_params = 0x80000100, +- .map_io = rx51_map_io, + .reserve = omap_reserve, +- .init_irq = rx51_init_irq, ++ .map_io = rx51_map_io, ++ .init_early = rx51_init_early, ++ .init_irq = omap_init_irq, + .init_machine = rx51_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-peripherals.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-peripherals.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-peripherals.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-peripherals.c 2011-03-09 13:19:09.800507825 +0100 +@@ -36,6 +36,8 @@ + + #include + #include ++#include ++#include + + #include <../drivers/staging/iio/light/tsl2563.h> + +@@ -47,6 +49,8 @@ + + #define RX51_WL1251_POWER_GPIO 87 + #define RX51_WL1251_IRQ_GPIO 42 ++#define RX51_FMTX_RESET_GPIO 163 ++#define RX51_FMTX_IRQ 53 + + /* list all spi devices here */ + enum { +@@ -331,13 +335,13 @@ + }; + + static struct regulator_consumer_supply rx51_vmmc1_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); + + static struct regulator_consumer_supply rx51_vaux3_supply = +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); + + static struct regulator_consumer_supply rx51_vsim_supply = +- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); ++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); + + static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { + /* tlv320aic3x analog supplies */ +@@ -348,7 +352,7 @@ + /* tpa6130a2 */ + REGULATOR_SUPPLY("Vdd", "2-0060"), + /* Keep vmmc as last item. It is not iterated for newer boards */ +- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), ++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), + }; + + static struct regulator_consumer_supply rx51_vio_supplies[] = { +@@ -357,14 +361,18 @@ + REGULATOR_SUPPLY("DVDD", "2-0018"), + REGULATOR_SUPPLY("IOVDD", "2-0019"), + REGULATOR_SUPPLY("DVDD", "2-0019"), ++ /* Si4713 IO supply */ ++ REGULATOR_SUPPLY("vio", "2-0063"), + }; + + static struct regulator_consumer_supply rx51_vaux1_consumers[] = { + REGULATOR_SUPPLY("vdds_sdi", "omapdss"), ++ /* Si4713 supply */ ++ REGULATOR_SUPPLY("vdd", "2-0063"), + }; + + static struct regulator_consumer_supply rx51_vdac_supply[] = { +- REGULATOR_SUPPLY("vdda_dac", "omapdss"), ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), + }; + + static struct regulator_init_data rx51_vaux1 = { +@@ -511,6 +519,41 @@ + .consumer_supplies = rx51_vio_supplies, + }; + ++static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = { ++ .gpio_reset = RX51_FMTX_RESET_GPIO, ++}; ++ ++static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = { ++ I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH), ++ .platform_data = &rx51_si4713_i2c_data, ++}; ++ ++static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = { ++ .i2c_bus = 2, ++ .subdev_board_info = &rx51_si4713_board_info, ++}; ++ ++static struct platform_device rx51_si4713_dev __initdata_or_module = { ++ .name = "radio-si4713", ++ .id = -1, ++ .dev = { ++ .platform_data = &rx51_si4713_data, ++ }, ++}; ++ ++static __init void rx51_init_si4713(void) ++{ ++ int err; ++ ++ err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq"); ++ if (err) { ++ printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err); ++ return; ++ } ++ rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ); ++ platform_device_register(&rx51_si4713_dev); ++} ++ + static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) + { + /* FIXME this gpio setup is just a placeholder for now */ +@@ -699,6 +742,14 @@ + .resource_config = twl4030_rconfig, + }; + ++struct twl4030_codec_vibra_data rx51_vibra_data __initdata = { ++ .coexist = 0, ++}; ++ ++struct twl4030_codec_data rx51_codec_data __initdata = { ++ .audio_mclk = 26000000, ++ .vibra = &rx51_vibra_data, ++}; + + static struct twl4030_platform_data rx51_twldata __initdata = { + .irq_base = TWL4030_IRQ_BASE, +@@ -710,6 +761,7 @@ + .madc = &rx51_madc_data, + .usb = &rx51_usb_data, + .power = &rx51_t2scripts_data, ++ .codec = &rx51_codec_data, + + .vaux1 = &rx51_vaux1, + .vaux2 = &rx51_vaux2, +@@ -921,6 +973,7 @@ + board_smc91x_init(); + rx51_add_gpio_keys(); + rx51_init_wl1251(); ++ rx51_init_si4713(); + spi_register_board_info(rx51_peripherals_spi_board_info, + ARRAY_SIZE(rx51_peripherals_spi_board_info)); + +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-video.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-video.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-video.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-video.c 2011-03-09 13:19:09.800507825 +0100 +@@ -66,18 +66,6 @@ + .default_device = &rx51_lcd_device, + }; + +-struct platform_device rx51_display_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &rx51_dss_board_info, +- }, +-}; +- +-static struct platform_device *rx51_video_devices[] __initdata = { +- &rx51_display_device, +-}; +- + static int __init rx51_video_init(void) + { + if (!machine_is_nokia_rx51()) +@@ -95,8 +83,7 @@ + + gpio_direction_output(RX51_LCD_RESET_GPIO, 1); + +- platform_add_devices(rx51_video_devices, +- ARRAY_SIZE(rx51_video_devices)); ++ omap_display_init(&rx51_dss_board_info); + return 0; + } + +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-ti8168evm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ti8168evm.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-ti8168evm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ti8168evm.c 2011-03-09 13:19:09.800507825 +0100 +@@ -0,0 +1,62 @@ ++/* ++ * Code for TI8168 EVM. ++ * ++ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++static struct omap_board_config_kernel ti8168_evm_config[] __initdata = { ++}; ++ ++static void __init ti8168_init_early(void) ++{ ++ omap2_init_common_infrastructure(); ++ omap2_init_common_devices(NULL, NULL); ++} ++ ++static void __init ti8168_evm_init_irq(void) ++{ ++ omap_init_irq(); ++} ++ ++static void __init ti8168_evm_init(void) ++{ ++ omap_serial_init(); ++ omap_board_config = ti8168_evm_config; ++ omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); ++} ++ ++static void __init ti8168_evm_map_io(void) ++{ ++ omap2_set_globals_ti816x(); ++ omapti816x_map_common_io(); ++} ++ ++MACHINE_START(TI8168EVM, "ti8168evm") ++ /* Maintainer: Texas Instruments */ ++ .boot_params = 0x80000100, ++ .map_io = ti8168_evm_map_io, ++ .init_early = ti8168_init_early, ++ .init_irq = ti8168_evm_init_irq, ++ .timer = &omap_timer, ++ .init_machine = ti8168_evm_init, ++MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom.c 2011-03-09 13:19:09.801507805 +0100 +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -33,7 +34,7 @@ + + #define ZOOM3_EHCI_RESET_GPIO 64 + +-static void __init omap_zoom_init_irq(void) ++static void __init omap_zoom_init_early(void) + { + omap2_init_common_infrastructure(); + if (machine_is_omap_zoom2()) +@@ -42,8 +43,6 @@ + else if (machine_is_omap_zoom3()) + omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); +- +- omap_init_irq(); + } + + #ifdef CONFIG_OMAP_MUX +@@ -126,8 +125,8 @@ + usb_ehci_init(&ehci_pdata); + } + +- board_nand_init(zoom_nand_partitions, +- ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); ++ board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions), ++ ZOOM_NAND_CS, NAND_BUSWIDTH_16); + zoom_debugboard_init(); + zoom_peripherals_init(); + zoom_display_init(); +@@ -135,18 +134,20 @@ + + MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = omap_zoom_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = omap_zoom_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_zoom_init, + .timer = &omap_timer, + MACHINE_END + + MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") + .boot_params = 0x80000100, +- .map_io = omap3_map_io, + .reserve = omap_reserve, +- .init_irq = omap_zoom_init_irq, ++ .map_io = omap3_map_io, ++ .init_early = omap_zoom_init_early, ++ .init_irq = omap_init_irq, + .init_machine = omap_zoom_init, + .timer = &omap_timer, + MACHINE_END +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-display.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-display.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-display.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-display.c 2011-03-09 13:19:09.801507805 +0100 +@@ -130,14 +130,6 @@ + .default_device = &zoom_lcd_device, + }; + +-static struct platform_device zoom_dss_device = { +- .name = "omapdss", +- .id = -1, +- .dev = { +- .platform_data = &zoom_dss_data, +- }, +-}; +- + static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { + .turbo_mode = 1, + .single_channel = 1, /* 0: slave, 1: master */ +@@ -153,14 +145,9 @@ + }, + }; + +-static struct platform_device *zoom_display_devices[] __initdata = { +- &zoom_dss_device, +-}; +- + void __init zoom_display_init(void) + { +- platform_add_devices(zoom_display_devices, +- ARRAY_SIZE(zoom_display_devices)); ++ omap_display_init(&zoom_dss_data); + spi_register_board_info(nec_8048_spi_board_info, + ARRAY_SIZE(nec_8048_spi_board_info)); + zoom_lcd_panel_init(); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-peripherals.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-peripherals.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-peripherals.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-peripherals.c 2011-03-09 13:19:09.801507805 +0100 +@@ -118,7 +118,7 @@ + + static struct regulator_consumer_supply zoom_vmmc3_supply = { + .supply = "vmmc", +- .dev_name = "mmci-omap-hs.2", ++ .dev_name = "omap_hsmmc.2", + }; + + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +@@ -226,11 +226,13 @@ + {} /* Terminator */ + }; + +-static struct regulator_consumer_supply zoom_vpll2_supply = +- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); ++static struct regulator_consumer_supply zoom_vpll2_supplies[] = { ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), ++ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), ++}; + + static struct regulator_consumer_supply zoom_vdda_dac_supply = +- REGULATOR_SUPPLY("vdda_dac", "omapdss"); ++ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); + + static struct regulator_init_data zoom_vpll2 = { + .constraints = { +@@ -241,8 +243,8 @@ + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +- .num_consumer_supplies = 1, +- .consumer_supplies = &zoom_vpll2_supply, ++ .num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies), ++ .consumer_supplies = zoom_vpll2_supplies, + }; + + static struct regulator_init_data zoom_vdac = { +@@ -322,9 +324,7 @@ + .irq_line = 1, + }; + +-static struct twl4030_codec_audio_data zoom_audio_data = { +- .audio_mclk = 26000000, +-}; ++static struct twl4030_codec_audio_data zoom_audio_data; + + static struct twl4030_codec_data zoom_codec_data = { + .audio_mclk = 26000000, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clkt_clksel.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clkt_clksel.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/clkt_clksel.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clkt_clksel.c 2011-03-09 13:19:09.802507785 +0100 +@@ -97,7 +97,7 @@ + u32 *field_val) + { + const struct clksel *clks; +- const struct clksel_rate *clkr, *max_clkr; ++ const struct clksel_rate *clkr, *max_clkr = NULL; + u8 max_div = 0; + + clks = _get_clksel_by_parent(clk, src_clk); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock2420_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2420_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/clock2420_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2420_data.c 2011-03-09 13:19:09.804507743 +0100 +@@ -1786,10 +1786,10 @@ + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), + /* DSS domain clocks */ +- CLK("omapdss", "ick", &dss_ick, CK_242X), +- CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), +- CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), +- CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), ++ CLK("omapdss_dss", "ick", &dss_ick, CK_242X), ++ CLK("omapdss_dss", "fck", &dss1_fck, CK_242X), ++ CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X), ++ CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock2430_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2430_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/clock2430_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2430_data.c 2011-03-09 13:19:09.804507743 +0100 +@@ -1890,10 +1890,10 @@ + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), + /* DSS domain clocks */ +- CLK("omapdss", "ick", &dss_ick, CK_243X), +- CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), +- CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), +- CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), ++ CLK("omapdss_dss", "ick", &dss_ick, CK_243X), ++ CLK("omapdss_dss", "fck", &dss1_fck, CK_243X), ++ CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X), ++ CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), +@@ -1984,15 +1984,15 @@ + CLK(NULL, "pka_ick", &pka_ick, CK_243X), + CLK(NULL, "usb_fck", &usb_fck, CK_243X), + CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), +- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), +- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), +- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), +- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), ++ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), ++ CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X), ++ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), ++ CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), +- CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), +- CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), ++ CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), ++ CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + }; + + /* +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2xxx.h +--- linux-2.6.38-rc7/arch/arm/mach-omap2/clock2xxx.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2xxx.h 2011-03-09 13:19:09.805507722 +0100 +@@ -20,13 +20,13 @@ + u32 omap2xxx_get_sysclkdiv(void); + void omap2xxx_clk_prepare_for_reboot(void); + +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + int omap2420_clk_init(void); + #else + #define omap2420_clk_init() 0 + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + int omap2430_clk_init(void); + #else + #define omap2430_clk_init() 0 +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock3xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock3xxx_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/clock3xxx_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock3xxx_data.c 2011-03-09 13:19:09.807507681 +0100 +@@ -3290,10 +3290,10 @@ + CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), + CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), + CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), +- CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), +- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), ++ CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), ++ CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX), + CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), +- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), ++ CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX), + CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), + CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), + CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), +@@ -3323,13 +3323,13 @@ + CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), + CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), +- CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), ++ CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), + CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), + CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), + CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), +- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), +- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), ++ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), ++ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), + CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), + CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), +@@ -3357,13 +3357,13 @@ + CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), + CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), + CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), +- CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), +- CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), +- CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), +- CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), +- CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), +- CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), +- CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), ++ CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1), ++ CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), ++ CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX), ++ CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX), ++ CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX), ++ CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), ++ CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), + CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), + CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), +@@ -3471,6 +3471,9 @@ + } else if (cpu_is_omap3630()) { + cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); + cpu_clkflg = CK_36XX; ++ } else if (cpu_is_ti816x()) { ++ cpu_mask = RATE_IN_TI816X; ++ cpu_clkflg = CK_TI816X; + } else if (cpu_is_omap34xx()) { + if (omap_rev() == OMAP3430_REV_ES1_0) { + cpu_mask = RATE_IN_3430ES1; +@@ -3550,7 +3553,7 @@ + /* + * Lock DPLL5 and put it in autoidle. + */ +- if (omap_rev() >= OMAP3430_REV_ES2_0) ++ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) + omap3_clk_lock_dpll5(); + + /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock44xx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock44xx_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/clock44xx_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock44xx_data.c 2011-03-09 13:19:09.808507662 +0100 +@@ -3106,11 +3106,16 @@ + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), + CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), +- CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), +- CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), +- CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), +- CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), +- CLK(NULL, "dss_fck", &dss_fck, CK_443X), ++ CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), ++ CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), ++ CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X), ++ CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), ++ CLK("omapdss_dss", "fck", &dss_fck, CK_443X), ++ /* ++ * On OMAP4, DSS ick is a dummy clock; this is needed for compatibility ++ * with OMAP2/3. ++ */ ++ CLK("omapdss_dss", "ick", &dummy_ck, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), +@@ -3158,11 +3163,11 @@ + CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), + CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), + CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), +- CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), +- CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), +- CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), +- CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), +- CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), ++ CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), ++ CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), ++ CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), ++ CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), ++ CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), +@@ -3245,11 +3250,11 @@ + CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), +- CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), +- CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), +- CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), +- CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), +- CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), ++ CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), ++ CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), ++ CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), ++ CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), ++ CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c 2011-03-09 13:19:09.809507642 +0100 +@@ -171,7 +171,7 @@ + + /* 2430-specific possible wakeup dependencies */ + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + + /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ + static struct clkdm_dep mdm_2430_wkdeps[] = { +@@ -194,7 +194,7 @@ + { NULL }, + }; + +-#endif /* CONFIG_ARCH_OMAP2430 */ ++#endif /* CONFIG_SOC_OMAP2430 */ + + + /* OMAP3-specific possible dependencies */ +@@ -450,7 +450,7 @@ + * 2420-only clockdomains + */ + +-#if defined(CONFIG_ARCH_OMAP2420) ++#if defined(CONFIG_SOC_OMAP2420) + + static struct clockdomain mpu_2420_clkdm = { + .name = "mpu_clkdm", +@@ -514,14 +514,14 @@ + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + }; + +-#endif /* CONFIG_ARCH_OMAP2420 */ ++#endif /* CONFIG_SOC_OMAP2420 */ + + + /* + * 2430-only clockdomains + */ + +-#if defined(CONFIG_ARCH_OMAP2430) ++#if defined(CONFIG_SOC_OMAP2430) + + static struct clockdomain mpu_2430_clkdm = { + .name = "mpu_clkdm", +@@ -600,7 +600,7 @@ + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + }; + +-#endif /* CONFIG_ARCH_OMAP2430 */ ++#endif /* CONFIG_SOC_OMAP2430 */ + + + /* +@@ -811,7 +811,7 @@ + &cm_clkdm, + &prm_clkdm, + +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + &mpu_2420_clkdm, + &iva1_2420_clkdm, + &dsp_2420_clkdm, +@@ -821,7 +821,7 @@ + &dss_2420_clkdm, + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + &mpu_2430_clkdm, + &mdm_clkdm, + &dsp_2430_clkdm, +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/common.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/common.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/common.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/common.c 2011-03-09 13:19:09.813507562 +0100 +@@ -40,7 +40,7 @@ + + #endif + +-#if defined(CONFIG_ARCH_OMAP2420) ++#if defined(CONFIG_SOC_OMAP2420) + + static struct omap_globals omap242x_globals = { + .class = OMAP242X_CLASS, +@@ -61,7 +61,7 @@ + } + #endif + +-#if defined(CONFIG_ARCH_OMAP2430) ++#if defined(CONFIG_SOC_OMAP2430) + + static struct omap_globals omap243x_globals = { + .class = OMAP243X_CLASS, +@@ -108,6 +108,27 @@ + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); + } ++ ++/* ++ * Adjust TAP register base such that omap3_check_revision accesses the correct ++ * TI816X register for checking device ID (it adds 0x204 to tap base while ++ * TI816X DEVICE ID register is at offset 0x600 from control base). ++ */ ++#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \ ++ TI816X_CONTROL_DEVICE_ID - 0x204) ++ ++static struct omap_globals ti816x_globals = { ++ .class = OMAP343X_CLASS, ++ .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), ++ .ctrl = TI816X_CTRL_BASE, ++ .prm = TI816X_PRCM_BASE, ++ .cm = TI816X_PRCM_BASE, ++}; ++ ++void __init omap2_set_globals_ti816x(void) ++{ ++ __omap2_set_globals(&ti816x_globals); ++} + #endif + + #if defined(CONFIG_ARCH_OMAP4) +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/control.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/control.h +--- linux-2.6.38-rc7/arch/arm/mach-omap2/control.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/control.h 2011-03-09 13:19:09.813507562 +0100 +@@ -52,6 +52,9 @@ + #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 + #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 + ++/* TI816X spefic control submodules */ ++#define TI816X_CONTROL_DEVCONF 0x600 ++ + /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ + + #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) +@@ -241,6 +244,9 @@ + #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 + #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 + ++/* TI816X CONTROL_DEVCONF register offsets */ ++#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000) ++ + /* + * REVISIT: This list of registers is not comprehensive - there are more + * that should be added. +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/devices.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/devices.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/devices.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/devices.c 2011-03-09 13:19:09.814507541 +0100 +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -30,6 +31,7 @@ + #include + #include + #include ++#include + + #include "mux.h" + #include "control.h" +@@ -141,96 +143,70 @@ + } + #endif + +-#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) +- +-#define MBOX_REG_SIZE 0x120 +- +-#ifdef CONFIG_ARCH_OMAP2 +-static struct resource omap2_mbox_resources[] = { ++struct omap_device_pm_latency omap_keyboard_latency[] = { + { +- .start = OMAP24XX_MAILBOX_BASE, +- .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, +- { +- .start = INT_24XX_MAIL_U0_MPU, +- .flags = IORESOURCE_IRQ, +- .name = "dsp", +- }, +- { +- .start = INT_24XX_MAIL_U3_MPU, +- .flags = IORESOURCE_IRQ, +- .name = "iva", ++ .deactivate_func = omap_device_idle_hwmods, ++ .activate_func = omap_device_enable_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, + }; +-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); +-#else +-#define omap2_mbox_resources NULL +-#define omap2_mbox_resources_sz 0 +-#endif + +-#ifdef CONFIG_ARCH_OMAP3 +-static struct resource omap3_mbox_resources[] = { +- { +- .start = OMAP34XX_MAILBOX_BASE, +- .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, +- { +- .start = INT_24XX_MAIL_U0_MPU, +- .flags = IORESOURCE_IRQ, +- .name = "dsp", +- }, +-}; +-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); +-#else +-#define omap3_mbox_resources NULL +-#define omap3_mbox_resources_sz 0 +-#endif ++int __init omap4_keyboard_init(struct omap4_keypad_platform_data ++ *sdp4430_keypad_data) ++{ ++ struct omap_device *od; ++ struct omap_hwmod *oh; ++ struct omap4_keypad_platform_data *keypad_data; ++ unsigned int id = -1; ++ char *oh_name = "kbd"; ++ char *name = "omap4-keypad"; + +-#ifdef CONFIG_ARCH_OMAP4 ++ oh = omap_hwmod_lookup(oh_name); ++ if (!oh) { ++ pr_err("Could not look up %s\n", oh_name); ++ return -ENODEV; ++ } + +-#define OMAP4_MBOX_REG_SIZE 0x130 +-static struct resource omap4_mbox_resources[] = { +- { +- .start = OMAP44XX_MAILBOX_BASE, +- .end = OMAP44XX_MAILBOX_BASE + +- OMAP4_MBOX_REG_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, +- { +- .start = OMAP44XX_IRQ_MAIL_U0, +- .flags = IORESOURCE_IRQ, +- .name = "mbox", +- }, +-}; +-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); +-#else +-#define omap4_mbox_resources NULL +-#define omap4_mbox_resources_sz 0 +-#endif ++ keypad_data = sdp4430_keypad_data; + +-static struct platform_device mbox_device = { +- .name = "omap-mailbox", +- .id = -1, ++ od = omap_device_build(name, id, oh, keypad_data, ++ sizeof(struct omap4_keypad_platform_data), ++ omap_keyboard_latency, ++ ARRAY_SIZE(omap_keyboard_latency), 0); ++ ++ if (IS_ERR(od)) { ++ WARN(1, "Cant build omap_device for %s:%s.\n", ++ name, oh->name); ++ return PTR_ERR(od); ++ } ++ ++ return 0; ++} ++ ++#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) ++static struct omap_device_pm_latency mbox_latencies[] = { ++ [0] = { ++ .activate_func = omap_device_enable_hwmods, ++ .deactivate_func = omap_device_idle_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, ++ }, + }; + + static inline void omap_init_mbox(void) + { +- if (cpu_is_omap24xx()) { +- mbox_device.resource = omap2_mbox_resources; +- mbox_device.num_resources = omap2_mbox_resources_sz; +- } else if (cpu_is_omap34xx()) { +- mbox_device.resource = omap3_mbox_resources; +- mbox_device.num_resources = omap3_mbox_resources_sz; +- } else if (cpu_is_omap44xx()) { +- mbox_device.resource = omap4_mbox_resources; +- mbox_device.num_resources = omap4_mbox_resources_sz; +- } else { +- pr_err("%s: platform not supported\n", __func__); ++ struct omap_hwmod *oh; ++ struct omap_device *od; ++ ++ oh = omap_hwmod_lookup("mailbox"); ++ if (!oh) { ++ pr_err("%s: unable to find hwmod\n", __func__); + return; + } +- platform_device_register(&mbox_device); ++ ++ od = omap_device_build("omap-mailbox", -1, oh, NULL, 0, ++ mbox_latencies, ARRAY_SIZE(mbox_latencies), 0); ++ WARN(IS_ERR(od), "%s: could not build device, err %ld\n", ++ __func__, PTR_ERR(od)); + } + #else + static inline void omap_init_mbox(void) { } +@@ -279,163 +255,55 @@ + + #include + +-#define OMAP2_MCSPI1_BASE 0x48098000 +-#define OMAP2_MCSPI2_BASE 0x4809a000 +-#define OMAP2_MCSPI3_BASE 0x480b8000 +-#define OMAP2_MCSPI4_BASE 0x480ba000 +- +-#define OMAP4_MCSPI1_BASE 0x48098100 +-#define OMAP4_MCSPI2_BASE 0x4809a100 +-#define OMAP4_MCSPI3_BASE 0x480b8100 +-#define OMAP4_MCSPI4_BASE 0x480ba100 +- +-static struct omap2_mcspi_platform_config omap2_mcspi1_config = { +- .num_cs = 4, +-}; +- +-static struct resource omap2_mcspi1_resources[] = { +- { +- .start = OMAP2_MCSPI1_BASE, +- .end = OMAP2_MCSPI1_BASE + 0xff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device omap2_mcspi1 = { +- .name = "omap2_mcspi", +- .id = 1, +- .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), +- .resource = omap2_mcspi1_resources, +- .dev = { +- .platform_data = &omap2_mcspi1_config, +- }, +-}; +- +-static struct omap2_mcspi_platform_config omap2_mcspi2_config = { +- .num_cs = 2, +-}; +- +-static struct resource omap2_mcspi2_resources[] = { +- { +- .start = OMAP2_MCSPI2_BASE, +- .end = OMAP2_MCSPI2_BASE + 0xff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device omap2_mcspi2 = { +- .name = "omap2_mcspi", +- .id = 2, +- .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), +- .resource = omap2_mcspi2_resources, +- .dev = { +- .platform_data = &omap2_mcspi2_config, +- }, +-}; +- +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ +- defined(CONFIG_ARCH_OMAP4) +-static struct omap2_mcspi_platform_config omap2_mcspi3_config = { +- .num_cs = 2, +-}; +- +-static struct resource omap2_mcspi3_resources[] = { +- { +- .start = OMAP2_MCSPI3_BASE, +- .end = OMAP2_MCSPI3_BASE + 0xff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device omap2_mcspi3 = { +- .name = "omap2_mcspi", +- .id = 3, +- .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), +- .resource = omap2_mcspi3_resources, +- .dev = { +- .platform_data = &omap2_mcspi3_config, +- }, +-}; +-#endif +- +-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) +-static struct omap2_mcspi_platform_config omap2_mcspi4_config = { +- .num_cs = 1, +-}; +- +-static struct resource omap2_mcspi4_resources[] = { +- { +- .start = OMAP2_MCSPI4_BASE, +- .end = OMAP2_MCSPI4_BASE + 0xff, +- .flags = IORESOURCE_MEM, +- }, +-}; +- +-static struct platform_device omap2_mcspi4 = { +- .name = "omap2_mcspi", +- .id = 4, +- .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), +- .resource = omap2_mcspi4_resources, +- .dev = { +- .platform_data = &omap2_mcspi4_config, ++struct omap_device_pm_latency omap_mcspi_latency[] = { ++ [0] = { ++ .deactivate_func = omap_device_idle_hwmods, ++ .activate_func = omap_device_enable_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, + }; +-#endif + +-#ifdef CONFIG_ARCH_OMAP4 +-static inline void omap4_mcspi_fixup(void) +-{ +- omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; +- omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; +- omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; +- omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; +- omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; +- omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; +- omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; +- omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; +-} +-#else +-static inline void omap4_mcspi_fixup(void) +-{ +-} +-#endif +- +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ +- defined(CONFIG_ARCH_OMAP4) +-static inline void omap2_mcspi3_init(void) +-{ +- platform_device_register(&omap2_mcspi3); +-} +-#else +-static inline void omap2_mcspi3_init(void) ++static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) + { +-} +-#endif ++ struct omap_device *od; ++ char *name = "omap2_mcspi"; ++ struct omap2_mcspi_platform_config *pdata; ++ static int spi_num; ++ struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; ++ ++ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); ++ if (!pdata) { ++ pr_err("Memory allocation for McSPI device failed\n"); ++ return -ENOMEM; ++ } ++ ++ pdata->num_cs = mcspi_attrib->num_chipselect; ++ switch (oh->class->rev) { ++ case OMAP2_MCSPI_REV: ++ case OMAP3_MCSPI_REV: ++ pdata->regs_offset = 0; ++ break; ++ case OMAP4_MCSPI_REV: ++ pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; ++ break; ++ default: ++ pr_err("Invalid McSPI Revision value\n"); ++ return -EINVAL; ++ } + +-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) +-static inline void omap2_mcspi4_init(void) +-{ +- platform_device_register(&omap2_mcspi4); +-} +-#else +-static inline void omap2_mcspi4_init(void) +-{ ++ spi_num++; ++ od = omap_device_build(name, spi_num, oh, pdata, ++ sizeof(*pdata), omap_mcspi_latency, ++ ARRAY_SIZE(omap_mcspi_latency), 0); ++ WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", ++ name, oh->name); ++ kfree(pdata); ++ return 0; + } +-#endif + + static void omap_init_mcspi(void) + { +- if (cpu_is_omap44xx()) +- omap4_mcspi_fixup(); +- +- platform_device_register(&omap2_mcspi1); +- platform_device_register(&omap2_mcspi2); +- +- if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) +- omap2_mcspi3_init(); +- +- if (cpu_is_omap343x() || cpu_is_omap44xx()) +- omap2_mcspi4_init(); ++ omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); + } + + #else +@@ -610,117 +478,10 @@ + + /*-------------------------------------------------------------------------*/ + +-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) +- +-#define MMCHS_SYSCONFIG 0x0010 +-#define MMCHS_SYSCONFIG_SWRESET (1 << 1) +-#define MMCHS_SYSSTATUS 0x0014 +-#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) +- +-static struct platform_device dummy_pdev = { +- .dev = { +- .bus = &platform_bus_type, +- }, +-}; ++#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + +-/** +- * omap_hsmmc_reset() - Full reset of each HS-MMC controller +- * +- * Ensure that each MMC controller is fully reset. Controllers +- * left in an unknown state (by bootloader) may prevent retention +- * or OFF-mode. This is especially important in cases where the +- * MMC driver is not enabled, _or_ built as a module. +- * +- * In order for reset to work, interface, functional and debounce +- * clocks must be enabled. The debounce clock comes from func_32k_clk +- * and is not under SW control, so we only enable i- and f-clocks. +- **/ +-static void __init omap_hsmmc_reset(void) +-{ +- u32 i, nr_controllers; +- struct clk *iclk, *fclk; +- +- if (cpu_is_omap242x()) +- return; +- +- nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : +- (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); +- +- for (i = 0; i < nr_controllers; i++) { +- u32 v, base = 0; +- struct device *dev = &dummy_pdev.dev; +- +- switch (i) { +- case 0: +- base = OMAP2_MMC1_BASE; +- break; +- case 1: +- base = OMAP2_MMC2_BASE; +- break; +- case 2: +- base = OMAP3_MMC3_BASE; +- break; +- case 3: +- if (!cpu_is_omap44xx()) +- return; +- base = OMAP4_MMC4_BASE; +- break; +- case 4: +- if (!cpu_is_omap44xx()) +- return; +- base = OMAP4_MMC5_BASE; +- break; +- } +- +- if (cpu_is_omap44xx()) +- base += OMAP4_MMC_REG_OFFSET; +- +- dummy_pdev.id = i; +- dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); +- iclk = clk_get(dev, "ick"); +- if (IS_ERR(iclk)) +- goto err1; +- if (clk_enable(iclk)) +- goto err2; +- +- fclk = clk_get(dev, "fck"); +- if (IS_ERR(fclk)) +- goto err3; +- if (clk_enable(fclk)) +- goto err4; +- +- omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); +- v = omap_readl(base + MMCHS_SYSSTATUS); +- while (!(omap_readl(base + MMCHS_SYSSTATUS) & +- MMCHS_SYSSTATUS_RESETDONE)) +- cpu_relax(); +- +- clk_disable(fclk); +- clk_put(fclk); +- clk_disable(iclk); +- clk_put(iclk); +- } +- return; +- +-err4: +- clk_put(fclk); +-err3: +- clk_disable(iclk); +-err2: +- clk_put(iclk); +-err1: +- printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " +- "cannot reset.\n", __func__, i); +-} +-#else +-static inline void omap_hsmmc_reset(void) {} +-#endif +- +-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ +- defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) +- +-static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, +- int controller_nr) ++static inline void omap242x_mmc_mux(struct omap_mmc_platform_data ++ *mmc_controller) + { + if ((mmc_controller->slots[0].switch_pin > 0) && \ + (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) +@@ -731,163 +492,44 @@ + omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, + OMAP_PIN_INPUT_PULLUP); + +- if (cpu_is_omap2420() && controller_nr == 0) { +- omap_mux_init_signal("sdmmc_cmd", 0); +- omap_mux_init_signal("sdmmc_clki", 0); +- omap_mux_init_signal("sdmmc_clko", 0); +- omap_mux_init_signal("sdmmc_dat0", 0); +- omap_mux_init_signal("sdmmc_dat_dir0", 0); +- omap_mux_init_signal("sdmmc_cmd_dir", 0); +- if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { +- omap_mux_init_signal("sdmmc_dat1", 0); +- omap_mux_init_signal("sdmmc_dat2", 0); +- omap_mux_init_signal("sdmmc_dat3", 0); +- omap_mux_init_signal("sdmmc_dat_dir1", 0); +- omap_mux_init_signal("sdmmc_dat_dir2", 0); +- omap_mux_init_signal("sdmmc_dat_dir3", 0); +- } +- +- /* +- * Use internal loop-back in MMC/SDIO Module Input Clock +- * selection +- */ +- if (mmc_controller->slots[0].internal_clock) { +- u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); +- v |= (1 << 24); +- omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); +- } +- } +- +- if (cpu_is_omap34xx()) { +- if (controller_nr == 0) { +- omap_mux_init_signal("sdmmc1_clk", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc1_cmd", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc1_dat0", +- OMAP_PIN_INPUT_PULLUP); +- if (mmc_controller->slots[0].caps & +- (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { +- omap_mux_init_signal("sdmmc1_dat1", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc1_dat2", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc1_dat3", +- OMAP_PIN_INPUT_PULLUP); +- } +- if (mmc_controller->slots[0].caps & +- MMC_CAP_8_BIT_DATA) { +- omap_mux_init_signal("sdmmc1_dat4", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc1_dat5", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc1_dat6", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc1_dat7", +- OMAP_PIN_INPUT_PULLUP); +- } +- } +- if (controller_nr == 1) { +- /* MMC2 */ +- omap_mux_init_signal("sdmmc2_clk", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc2_cmd", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc2_dat0", +- OMAP_PIN_INPUT_PULLUP); +- +- /* +- * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed +- * in the board-*.c files +- */ +- if (mmc_controller->slots[0].caps & +- (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { +- omap_mux_init_signal("sdmmc2_dat1", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc2_dat2", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc2_dat3", +- OMAP_PIN_INPUT_PULLUP); +- } +- if (mmc_controller->slots[0].caps & +- MMC_CAP_8_BIT_DATA) { +- omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", +- OMAP_PIN_INPUT_PULLUP); +- omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", +- OMAP_PIN_INPUT_PULLUP); +- } +- } ++ omap_mux_init_signal("sdmmc_cmd", 0); ++ omap_mux_init_signal("sdmmc_clki", 0); ++ omap_mux_init_signal("sdmmc_clko", 0); ++ omap_mux_init_signal("sdmmc_dat0", 0); ++ omap_mux_init_signal("sdmmc_dat_dir0", 0); ++ omap_mux_init_signal("sdmmc_cmd_dir", 0); ++ if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { ++ omap_mux_init_signal("sdmmc_dat1", 0); ++ omap_mux_init_signal("sdmmc_dat2", 0); ++ omap_mux_init_signal("sdmmc_dat3", 0); ++ omap_mux_init_signal("sdmmc_dat_dir1", 0); ++ omap_mux_init_signal("sdmmc_dat_dir2", 0); ++ omap_mux_init_signal("sdmmc_dat_dir3", 0); ++ } + +- /* +- * For MMC3 the pins need to be muxed in the board-*.c files +- */ ++ /* ++ * Use internal loop-back in MMC/SDIO Module Input Clock ++ * selection ++ */ ++ if (mmc_controller->slots[0].internal_clock) { ++ u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); ++ v |= (1 << 24); ++ omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + } + } + +-void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, +- int nr_controllers) ++void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) + { +- int i; +- char *name; +- +- for (i = 0; i < nr_controllers; i++) { +- unsigned long base, size; +- unsigned int irq = 0; +- +- if (!mmc_data[i]) +- continue; ++ char *name = "mmci-omap"; + +- omap2_mmc_mux(mmc_data[i], i); ++ if (!mmc_data[0]) { ++ pr_err("%s fails: Incomplete platform data\n", __func__); ++ return; ++ } + +- switch (i) { +- case 0: +- base = OMAP2_MMC1_BASE; +- irq = INT_24XX_MMC_IRQ; +- break; +- case 1: +- base = OMAP2_MMC2_BASE; +- irq = INT_24XX_MMC2_IRQ; +- break; +- case 2: +- if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) +- return; +- base = OMAP3_MMC3_BASE; +- irq = INT_34XX_MMC3_IRQ; +- break; +- case 3: +- if (!cpu_is_omap44xx()) +- return; +- base = OMAP4_MMC4_BASE; +- irq = OMAP44XX_IRQ_MMC4; +- break; +- case 4: +- if (!cpu_is_omap44xx()) +- return; +- base = OMAP4_MMC5_BASE; +- irq = OMAP44XX_IRQ_MMC5; +- break; +- default: +- continue; +- } +- +- if (cpu_is_omap2420()) { +- size = OMAP2420_MMC_SIZE; +- name = "mmci-omap"; +- } else if (cpu_is_omap44xx()) { +- if (i < 3) +- irq += OMAP44XX_IRQ_GIC_START; +- size = OMAP4_HSMMC_SIZE; +- name = "mmci-omap-hs"; +- } else { +- size = OMAP3_HSMMC_SIZE; +- name = "mmci-omap-hs"; +- } +- omap_mmc_add(name, i, base, size, irq, mmc_data[i]); +- }; ++ omap242x_mmc_mux(mmc_data[0]); ++ omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, ++ INT_24XX_MMC_IRQ, mmc_data[0]); + } + + #endif +@@ -895,7 +537,7 @@ + /*-------------------------------------------------------------------------*/ + + #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) ++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) + #define OMAP_HDQ_BASE 0x480B2000 + #endif + static struct resource omap_hdq_resources[] = { +@@ -961,7 +603,6 @@ + * please keep these calls, and their implementations above, + * in alphabetical order so they're easier to sort through. + */ +- omap_hsmmc_reset(); + omap_init_audio(); + omap_init_camera(); + omap_init_mbox(); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/display.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/display.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/display.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/display.c 2011-03-09 13:19:09.814507541 +0100 +@@ -0,0 +1,125 @@ ++/* ++ * OMAP2plus display device setup / initialization. ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ ++ * Senthilvadivu Guruswamy ++ * Sumit Semwal ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++static struct platform_device omap_display_device = { ++ .name = "omapdss", ++ .id = -1, ++ .dev = { ++ .platform_data = NULL, ++ }, ++}; ++ ++static struct omap_device_pm_latency omap_dss_latency[] = { ++ [0] = { ++ .deactivate_func = omap_device_idle_hwmods, ++ .activate_func = omap_device_enable_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, ++ }, ++}; ++ ++/* oh_core is used for getting opt-clocks */ ++static struct omap_hwmod *oh_core; ++ ++static bool opt_clock_available(const char *clk_role) ++{ ++ int i; ++ ++ for (i = 0; i < oh_core->opt_clks_cnt; i++) { ++ if (!strcmp(oh_core->opt_clks[i].role, clk_role)) ++ return true; ++ } ++ return false; ++} ++ ++int __init omap_display_init(struct omap_dss_board_info *board_data) ++{ ++ int r = 0; ++ struct omap_hwmod *oh; ++ struct omap_device *od; ++ int i; ++ struct omap_display_platform_data pdata; ++ ++ /* ++ * omap: valid DSS hwmod names ++ * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc ++ * omap3,4: dss_dsi1 ++ * omap4: dss_dsi2, dss_hdmi ++ */ ++ char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc", ++ "dss_dsi1", "dss_dsi2", "dss_hdmi" }; ++ char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi", ++ "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2", ++ "omapdss_hdmi" }; ++ int oh_count; ++ ++ memset(&pdata, 0, sizeof(pdata)); ++ ++ if (cpu_is_omap24xx()) ++ oh_count = ARRAY_SIZE(oh_name) - 3; ++ /* last 3 hwmod dev in oh_name are not available for omap2 */ ++ else if (cpu_is_omap44xx()) ++ oh_count = ARRAY_SIZE(oh_name); ++ else ++ oh_count = ARRAY_SIZE(oh_name) - 2; ++ /* last 2 hwmod dev in oh_name are not available for omap3 */ ++ ++ /* opt_clks are always associated with dss hwmod */ ++ oh_core = omap_hwmod_lookup("dss_core"); ++ if (!oh_core) { ++ pr_err("Could not look up dss_core.\n"); ++ return -ENODEV; ++ } ++ ++ pdata.board_data = board_data; ++ pdata.board_data->get_last_off_on_transaction_id = NULL; ++ pdata.opt_clock_available = opt_clock_available; ++ ++ for (i = 0; i < oh_count; i++) { ++ oh = omap_hwmod_lookup(oh_name[i]); ++ if (!oh) { ++ pr_err("Could not look up %s\n", oh_name[i]); ++ return -ENODEV; ++ } ++ ++ od = omap_device_build(dev_name[i], -1, oh, &pdata, ++ sizeof(struct omap_display_platform_data), ++ omap_dss_latency, ++ ARRAY_SIZE(omap_dss_latency), 0); ++ ++ if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n", ++ oh_name[i])) ++ return -ENODEV; ++ } ++ omap_display_device.dev.platform_data = board_data; ++ ++ r = platform_device_register(&omap_display_device); ++ if (r < 0) ++ printk(KERN_ERR "Unable to register OMAP-Display device\n"); ++ ++ return r; ++} +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc.c 2011-03-09 13:19:09.816507499 +0100 +@@ -14,6 +14,7 @@ + */ + #undef DEBUG + ++#include + #include + #include + #include +@@ -22,6 +23,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -58,7 +60,6 @@ + #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ + #define GPMC_SECTION_SHIFT 28 /* 128 MB */ + +-#define PREFETCH_FIFOTHRESHOLD (0x40 << 8) + #define CS_NUM_SHIFT 24 + #define ENABLE_PREFETCH (0x1 << 7) + #define DMA_MPU_MODE 2 +@@ -100,6 +101,8 @@ + + static struct clk *gpmc_l3_clk; + ++static irqreturn_t gpmc_handle_irq(int irq, void *dev); ++ + static void gpmc_write_reg(int idx, u32 val) + { + __raw_writel(val, gpmc_base + idx); +@@ -497,6 +500,10 @@ + u32 regval = 0; + + switch (cmd) { ++ case GPMC_ENABLE_IRQ: ++ gpmc_write_reg(GPMC_IRQENABLE, wval); ++ break; ++ + case GPMC_SET_IRQ_STATUS: + gpmc_write_reg(GPMC_IRQSTATUS, wval); + break; +@@ -598,15 +605,19 @@ + /** + * gpmc_prefetch_enable - configures and starts prefetch transfer + * @cs: cs (chip select) number ++ * @fifo_th: fifo threshold to be used for read/ write + * @dma_mode: dma mode enable (1) or disable (0) + * @u32_count: number of bytes to be transferred + * @is_write: prefetch read(0) or write post(1) mode + */ +-int gpmc_prefetch_enable(int cs, int dma_mode, ++int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, + unsigned int u32_count, int is_write) + { + +- if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { ++ if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { ++ pr_err("gpmc: fifo threshold is not supported\n"); ++ return -1; ++ } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { + /* Set the amount of bytes to be prefetched */ + gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); + +@@ -614,7 +625,7 @@ + * enable the engine. Set which cs is has requested for. + */ + gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | +- PREFETCH_FIFOTHRESHOLD | ++ PREFETCH_FIFOTHRESHOLD(fifo_th) | + ENABLE_PREFETCH | + (dma_mode << DMA_MPU_MODE) | + (0x1 & is_write))); +@@ -678,9 +689,10 @@ + } + } + +-void __init gpmc_init(void) ++static int __init gpmc_init(void) + { +- u32 l; ++ u32 l, irq; ++ int cs, ret = -EINVAL; + char *ck = NULL; + + if (cpu_is_omap24xx()) { +@@ -698,7 +710,7 @@ + } + + if (WARN_ON(!ck)) +- return; ++ return ret; + + gpmc_l3_clk = clk_get(NULL, ck); + if (IS_ERR(gpmc_l3_clk)) { +@@ -723,6 +735,36 @@ + l |= (0x02 << 3) | (1 << 0); + gpmc_write_reg(GPMC_SYSCONFIG, l); + gpmc_mem_init(); ++ ++ /* initalize the irq_chained */ ++ irq = OMAP_GPMC_IRQ_BASE; ++ for (cs = 0; cs < GPMC_CS_NUM; cs++) { ++ set_irq_handler(irq, handle_simple_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ irq++; ++ } ++ ++ ret = request_irq(INT_34XX_GPMC_IRQ, ++ gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); ++ if (ret) ++ pr_err("gpmc: irq-%d could not claim: err %d\n", ++ INT_34XX_GPMC_IRQ, ret); ++ return ret; ++} ++postcore_initcall(gpmc_init); ++ ++static irqreturn_t gpmc_handle_irq(int irq, void *dev) ++{ ++ u8 cs; ++ ++ if (irq != INT_34XX_GPMC_IRQ) ++ return IRQ_HANDLED; ++ /* check cs to invoke the irq */ ++ cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; ++ if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) ++ generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); ++ ++ return IRQ_HANDLED; + } + + #ifdef CONFIG_ARCH_OMAP3 +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-nand.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-nand.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-nand.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-nand.c 2011-03-09 13:19:09.815507520 +0100 +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + #include + +@@ -69,8 +70,10 @@ + t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); + + /* Configure GPMC */ +- gpmc_cs_configure(gpmc_nand_data->cs, +- GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); ++ if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) ++ gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); ++ else ++ gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); + gpmc_cs_configure(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); + err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-onenand.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-onenand.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-onenand.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-onenand.c 2011-03-09 13:19:09.815507520 +0100 +@@ -94,7 +94,7 @@ + } + + static void set_onenand_cfg(void __iomem *onenand_base, int latency, +- int sync_read, int sync_write, int hf) ++ int sync_read, int sync_write, int hf, int vhf) + { + u32 reg; + +@@ -114,12 +114,57 @@ + reg |= ONENAND_SYS_CFG1_HF; + else + reg &= ~ONENAND_SYS_CFG1_HF; ++ if (vhf) ++ reg |= ONENAND_SYS_CFG1_VHF; ++ else ++ reg &= ~ONENAND_SYS_CFG1_VHF; + writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); + } + ++static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, ++ void __iomem *onenand_base, bool *clk_dep) ++{ ++ u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); ++ int freq = 0; ++ ++ if (cfg->get_freq) { ++ struct onenand_freq_info fi; ++ ++ fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID); ++ fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID); ++ fi.ver_id = ver; ++ freq = cfg->get_freq(&fi, clk_dep); ++ if (freq) ++ return freq; ++ } ++ ++ switch ((ver >> 4) & 0xf) { ++ case 0: ++ freq = 40; ++ break; ++ case 1: ++ freq = 54; ++ break; ++ case 2: ++ freq = 66; ++ break; ++ case 3: ++ freq = 83; ++ break; ++ case 4: ++ freq = 104; ++ break; ++ default: ++ freq = 54; ++ break; ++ } ++ ++ return freq; ++} ++ + static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, + void __iomem *onenand_base, +- int freq) ++ int *freq_ptr) + { + struct gpmc_timings t; + const int t_cer = 15; +@@ -130,10 +175,11 @@ + const int t_wph = 30; + int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; + int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; +- int first_time = 0, hf = 0, sync_read = 0, sync_write = 0; ++ int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; + int err, ticks_cez; +- int cs = cfg->cs; ++ int cs = cfg->cs, freq = *freq_ptr; + u32 reg; ++ bool clk_dep = false; + + if (cfg->flags & ONENAND_SYNC_READ) { + sync_read = 1; +@@ -148,27 +194,7 @@ + err = omap2_onenand_set_async_mode(cs, onenand_base); + if (err) + return err; +- reg = readw(onenand_base + ONENAND_REG_VERSION_ID); +- switch ((reg >> 4) & 0xf) { +- case 0: +- freq = 40; +- break; +- case 1: +- freq = 54; +- break; +- case 2: +- freq = 66; +- break; +- case 3: +- freq = 83; +- break; +- case 4: +- freq = 104; +- break; +- default: +- freq = 54; +- break; +- } ++ freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep); + first_time = 1; + } + +@@ -180,7 +206,7 @@ + t_avdh = 2; + t_ach = 3; + t_aavdh = 6; +- t_rdyo = 9; ++ t_rdyo = 6; + break; + case 83: + min_gpmc_clk_period = 12000; /* 83 MHz */ +@@ -217,16 +243,36 @@ + gpmc_clk_ns = gpmc_ticks_to_ns(div); + if (gpmc_clk_ns < 15) /* >66Mhz */ + hf = 1; +- if (hf) ++ if (gpmc_clk_ns < 12) /* >83Mhz */ ++ vhf = 1; ++ if (vhf) ++ latency = 8; ++ else if (hf) + latency = 6; + else if (gpmc_clk_ns >= 25) /* 40 MHz*/ + latency = 3; + else + latency = 4; + ++ if (clk_dep) { ++ if (gpmc_clk_ns < 12) { /* >83Mhz */ ++ t_ces = 3; ++ t_avds = 4; ++ } else if (gpmc_clk_ns < 15) { /* >66Mhz */ ++ t_ces = 5; ++ t_avds = 4; ++ } else if (gpmc_clk_ns < 25) { /* >40Mhz */ ++ t_ces = 6; ++ t_avds = 5; ++ } else { ++ t_ces = 7; ++ t_avds = 7; ++ } ++ } ++ + if (first_time) + set_onenand_cfg(onenand_base, latency, +- sync_read, sync_write, hf); ++ sync_read, sync_write, hf, vhf); + + if (div == 1) { + reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); +@@ -264,6 +310,9 @@ + /* Read */ + t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); + t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); ++ /* Force at least 1 clk between AVD High to OE Low */ ++ if (t.oe_on <= t.adv_rd_off) ++ t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1); + t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); + t.oe_off = t.access + gpmc_round_ns_to_ticks(1); + t.cs_rd_off = t.oe_off; +@@ -317,18 +366,20 @@ + if (err) + return err; + +- set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf); ++ set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); ++ ++ *freq_ptr = freq; + + return 0; + } + +-static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) ++static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) + { + struct device *dev = &gpmc_onenand_device.dev; + + /* Set sync timings in GPMC */ + if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, +- freq) < 0) { ++ freq_ptr) < 0) { + dev_err(dev, "Unable to set synchronous mode\n"); + return -EINVAL; + } +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/hsmmc.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hsmmc.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/hsmmc.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hsmmc.c 2011-03-09 13:19:09.816507499 +0100 +@@ -16,7 +16,10 @@ + #include + #include + #include ++#include ++#include + ++#include "mux.h" + #include "hsmmc.h" + #include "control.h" + +@@ -28,10 +31,6 @@ + + #define HSMMC_NAME_LEN 9 + +-static struct hsmmc_controller { +- char name[HSMMC_NAME_LEN + 1]; +-} hsmmc[OMAP34XX_NR_MMC]; +- + #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) + + static int hsmmc_get_context_loss(struct device *dev) +@@ -204,13 +203,284 @@ + return 0; + } + +-static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; ++static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, ++ int controller_nr) ++{ ++ if ((mmc_controller->slots[0].switch_pin > 0) && \ ++ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) ++ omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, ++ OMAP_PIN_INPUT_PULLUP); ++ if ((mmc_controller->slots[0].gpio_wp > 0) && \ ++ (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) ++ omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, ++ OMAP_PIN_INPUT_PULLUP); ++ if (cpu_is_omap34xx()) { ++ if (controller_nr == 0) { ++ omap_mux_init_signal("sdmmc1_clk", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc1_cmd", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc1_dat0", ++ OMAP_PIN_INPUT_PULLUP); ++ if (mmc_controller->slots[0].caps & ++ (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { ++ omap_mux_init_signal("sdmmc1_dat1", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc1_dat2", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc1_dat3", ++ OMAP_PIN_INPUT_PULLUP); ++ } ++ if (mmc_controller->slots[0].caps & ++ MMC_CAP_8_BIT_DATA) { ++ omap_mux_init_signal("sdmmc1_dat4", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc1_dat5", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc1_dat6", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc1_dat7", ++ OMAP_PIN_INPUT_PULLUP); ++ } ++ } ++ if (controller_nr == 1) { ++ /* MMC2 */ ++ omap_mux_init_signal("sdmmc2_clk", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc2_cmd", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc2_dat0", ++ OMAP_PIN_INPUT_PULLUP); ++ ++ /* ++ * For 8 wire configurations, Lines DAT4, 5, 6 and 7 ++ * need to be muxed in the board-*.c files ++ */ ++ if (mmc_controller->slots[0].caps & ++ (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { ++ omap_mux_init_signal("sdmmc2_dat1", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc2_dat2", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc2_dat3", ++ OMAP_PIN_INPUT_PULLUP); ++ } ++ if (mmc_controller->slots[0].caps & ++ MMC_CAP_8_BIT_DATA) { ++ omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", ++ OMAP_PIN_INPUT_PULLUP); ++ } ++ } ++ ++ /* ++ * For MMC3 the pins need to be muxed in the board-*.c files ++ */ ++ } ++} ++ ++static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, ++ struct omap_mmc_platform_data *mmc) ++{ ++ char *hc_name; ++ ++ hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); ++ if (!hc_name) { ++ pr_err("Cannot allocate memory for controller slot name\n"); ++ kfree(hc_name); ++ return -ENOMEM; ++ } ++ ++ if (c->name) ++ strncpy(hc_name, c->name, HSMMC_NAME_LEN); ++ else ++ snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", ++ c->mmc, 1); ++ mmc->slots[0].name = hc_name; ++ mmc->nr_slots = 1; ++ mmc->slots[0].caps = c->caps; ++ mmc->slots[0].internal_clock = !c->ext_clock; ++ mmc->dma_mask = 0xffffffff; ++ if (cpu_is_omap44xx()) ++ mmc->reg_offset = OMAP4_MMC_REG_OFFSET; ++ else ++ mmc->reg_offset = 0; ++ ++ mmc->get_context_loss_count = hsmmc_get_context_loss; ++ ++ mmc->slots[0].switch_pin = c->gpio_cd; ++ mmc->slots[0].gpio_wp = c->gpio_wp; ++ ++ mmc->slots[0].remux = c->remux; ++ mmc->slots[0].init_card = c->init_card; ++ ++ if (c->cover_only) ++ mmc->slots[0].cover = 1; ++ ++ if (c->nonremovable) ++ mmc->slots[0].nonremovable = 1; ++ ++ if (c->power_saving) ++ mmc->slots[0].power_saving = 1; ++ ++ if (c->no_off) ++ mmc->slots[0].no_off = 1; ++ ++ if (c->vcc_aux_disable_is_sleep) ++ mmc->slots[0].vcc_aux_disable_is_sleep = 1; ++ ++ /* ++ * NOTE: MMC slots should have a Vcc regulator set up. ++ * This may be from a TWL4030-family chip, another ++ * controllable regulator, or a fixed supply. ++ * ++ * temporary HACK: ocr_mask instead of fixed supply ++ */ ++ mmc->slots[0].ocr_mask = c->ocr_mask; ++ ++ if (cpu_is_omap3517() || cpu_is_omap3505()) ++ mmc->slots[0].set_power = nop_mmc_set_power; ++ else ++ mmc->slots[0].features |= HSMMC_HAS_PBIAS; ++ ++ if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ++ mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; ++ ++ switch (c->mmc) { ++ case 1: ++ if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { ++ /* on-chip level shifting via PBIAS0/PBIAS1 */ ++ if (cpu_is_omap44xx()) { ++ mmc->slots[0].before_set_reg = ++ omap4_hsmmc1_before_set_reg; ++ mmc->slots[0].after_set_reg = ++ omap4_hsmmc1_after_set_reg; ++ } else { ++ mmc->slots[0].before_set_reg = ++ omap_hsmmc1_before_set_reg; ++ mmc->slots[0].after_set_reg = ++ omap_hsmmc1_after_set_reg; ++ } ++ } ++ ++ /* OMAP3630 HSMMC1 supports only 4-bit */ ++ if (cpu_is_omap3630() && ++ (c->caps & MMC_CAP_8_BIT_DATA)) { ++ c->caps &= ~MMC_CAP_8_BIT_DATA; ++ c->caps |= MMC_CAP_4_BIT_DATA; ++ mmc->slots[0].caps = c->caps; ++ } ++ break; ++ case 2: ++ if (c->ext_clock) ++ c->transceiver = 1; ++ if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { ++ c->caps &= ~MMC_CAP_8_BIT_DATA; ++ c->caps |= MMC_CAP_4_BIT_DATA; ++ } ++ /* FALLTHROUGH */ ++ case 3: ++ if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { ++ /* off-chip level shifting, or none */ ++ mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; ++ mmc->slots[0].after_set_reg = NULL; ++ } ++ break; ++ case 4: ++ case 5: ++ mmc->slots[0].before_set_reg = NULL; ++ mmc->slots[0].after_set_reg = NULL; ++ break; ++ default: ++ pr_err("MMC%d configuration not supported!\n", c->mmc); ++ kfree(hc_name); ++ return -ENODEV; ++ } ++ return 0; ++} ++ ++static struct omap_device_pm_latency omap_hsmmc_latency[] = { ++ [0] = { ++ .deactivate_func = omap_device_idle_hwmods, ++ .activate_func = omap_device_enable_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, ++ }, ++ /* ++ * XXX There should also be an entry here to power off/on the ++ * MMC regulators/PBIAS cells, etc. ++ */ ++}; ++ ++#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 ++ ++void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) ++{ ++ struct omap_hwmod *oh; ++ struct omap_device *od; ++ struct omap_device_pm_latency *ohl; ++ char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; ++ struct omap_mmc_platform_data *mmc_data; ++ struct omap_mmc_dev_attr *mmc_dev_attr; ++ char *name; ++ int l; ++ int ohl_cnt = 0; ++ ++ mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); ++ if (!mmc_data) { ++ pr_err("Cannot allocate memory for mmc device!\n"); ++ goto done; ++ } ++ ++ if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) { ++ pr_err("%s fails!\n", __func__); ++ goto done; ++ } ++ omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); ++ ++ name = "omap_hsmmc"; ++ ohl = omap_hsmmc_latency; ++ ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency); ++ ++ l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, ++ "mmc%d", ctrl_nr); ++ WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN, ++ "String buffer overflow in MMC%d device setup\n", ctrl_nr); ++ oh = omap_hwmod_lookup(oh_name); ++ if (!oh) { ++ pr_err("Could not look up %s\n", oh_name); ++ kfree(mmc_data->slots[0].name); ++ goto done; ++ } ++ ++ if (oh->dev_attr != NULL) { ++ mmc_dev_attr = oh->dev_attr; ++ mmc_data->controller_flags = mmc_dev_attr->flags; ++ } ++ ++ od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, ++ sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); ++ if (IS_ERR(od)) { ++ WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name); ++ kfree(mmc_data->slots[0].name); ++ goto done; ++ } ++ /* ++ * return device handle to board setup code ++ * required to populate for regulator framework structure ++ */ ++ hsmmcinfo->dev = &od->pdev.dev; ++ ++done: ++ kfree(mmc_data); ++} + + void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) + { +- struct omap2_hsmmc_info *c; +- int nr_hsmmc = ARRAY_SIZE(hsmmc_data); +- int i; + u32 reg; + + if (!cpu_is_omap44xx()) { +@@ -236,142 +506,9 @@ + omap4_ctrl_pad_writel(reg, control_mmc1); + } + +- for (c = controllers; c->mmc; c++) { +- struct hsmmc_controller *hc = hsmmc + c->mmc - 1; +- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; +- +- if (!c->mmc || c->mmc > nr_hsmmc) { +- pr_debug("MMC%d: no such controller\n", c->mmc); +- continue; +- } +- if (mmc) { +- pr_debug("MMC%d: already configured\n", c->mmc); +- continue; +- } +- +- mmc = kzalloc(sizeof(struct omap_mmc_platform_data), +- GFP_KERNEL); +- if (!mmc) { +- pr_err("Cannot allocate memory for mmc device!\n"); +- goto done; +- } +- +- if (c->name) +- strncpy(hc->name, c->name, HSMMC_NAME_LEN); +- else +- snprintf(hc->name, ARRAY_SIZE(hc->name), +- "mmc%islot%i", c->mmc, 1); +- mmc->slots[0].name = hc->name; +- mmc->nr_slots = 1; +- mmc->slots[0].caps = c->caps; +- mmc->slots[0].internal_clock = !c->ext_clock; +- mmc->dma_mask = 0xffffffff; +- if (cpu_is_omap44xx()) +- mmc->reg_offset = OMAP4_MMC_REG_OFFSET; +- else +- mmc->reg_offset = 0; +- +- mmc->get_context_loss_count = hsmmc_get_context_loss; +- +- mmc->slots[0].switch_pin = c->gpio_cd; +- mmc->slots[0].gpio_wp = c->gpio_wp; +- +- mmc->slots[0].remux = c->remux; +- mmc->slots[0].init_card = c->init_card; +- +- if (c->cover_only) +- mmc->slots[0].cover = 1; +- +- if (c->nonremovable) +- mmc->slots[0].nonremovable = 1; +- +- if (c->power_saving) +- mmc->slots[0].power_saving = 1; +- +- if (c->no_off) +- mmc->slots[0].no_off = 1; +- +- if (c->vcc_aux_disable_is_sleep) +- mmc->slots[0].vcc_aux_disable_is_sleep = 1; +- +- /* NOTE: MMC slots should have a Vcc regulator set up. +- * This may be from a TWL4030-family chip, another +- * controllable regulator, or a fixed supply. +- * +- * temporary HACK: ocr_mask instead of fixed supply +- */ +- mmc->slots[0].ocr_mask = c->ocr_mask; +- +- if (cpu_is_omap3517() || cpu_is_omap3505()) +- mmc->slots[0].set_power = nop_mmc_set_power; +- else +- mmc->slots[0].features |= HSMMC_HAS_PBIAS; +- +- if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) +- mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; +- +- switch (c->mmc) { +- case 1: +- if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { +- /* on-chip level shifting via PBIAS0/PBIAS1 */ +- if (cpu_is_omap44xx()) { +- mmc->slots[0].before_set_reg = +- omap4_hsmmc1_before_set_reg; +- mmc->slots[0].after_set_reg = +- omap4_hsmmc1_after_set_reg; +- } else { +- mmc->slots[0].before_set_reg = +- omap_hsmmc1_before_set_reg; +- mmc->slots[0].after_set_reg = +- omap_hsmmc1_after_set_reg; +- } +- } +- +- /* Omap3630 HSMMC1 supports only 4-bit */ +- if (cpu_is_omap3630() && +- (c->caps & MMC_CAP_8_BIT_DATA)) { +- c->caps &= ~MMC_CAP_8_BIT_DATA; +- c->caps |= MMC_CAP_4_BIT_DATA; +- mmc->slots[0].caps = c->caps; +- } +- break; +- case 2: +- if (c->ext_clock) +- c->transceiver = 1; +- if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { +- c->caps &= ~MMC_CAP_8_BIT_DATA; +- c->caps |= MMC_CAP_4_BIT_DATA; +- } +- /* FALLTHROUGH */ +- case 3: +- if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { +- /* off-chip level shifting, or none */ +- mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; +- mmc->slots[0].after_set_reg = NULL; +- } +- break; +- default: +- pr_err("MMC%d configuration not supported!\n", c->mmc); +- kfree(mmc); +- continue; +- } +- hsmmc_data[c->mmc - 1] = mmc; +- } +- +- omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); +- +- /* pass the device nodes back to board setup code */ +- for (c = controllers; c->mmc; c++) { +- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; ++ for (; controllers->mmc; controllers++) ++ omap_init_hsmmc(controllers, controllers->mmc); + +- if (!c->mmc || c->mmc > nr_hsmmc) +- continue; +- c->dev = mmc->dev; +- } +- +-done: +- for (i = 0; i < nr_hsmmc; i++) +- kfree(hsmmc_data[i]); + } + + #endif +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/hwspinlock.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hwspinlock.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/hwspinlock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hwspinlock.c 2011-03-09 13:19:09.817507478 +0100 +@@ -0,0 +1,63 @@ ++/* ++ * OMAP hardware spinlock device initialization ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com ++ * ++ * Contact: Simon Que ++ * Hari Kanigeri ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct omap_device_pm_latency omap_spinlock_latency[] = { ++ { ++ .deactivate_func = omap_device_idle_hwmods, ++ .activate_func = omap_device_enable_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, ++ } ++}; ++ ++int __init hwspinlocks_init(void) ++{ ++ int retval = 0; ++ struct omap_hwmod *oh; ++ struct omap_device *od; ++ const char *oh_name = "spinlock"; ++ const char *dev_name = "omap_hwspinlock"; ++ ++ /* ++ * Hwmod lookup will fail in case our platform doesn't support the ++ * hardware spinlock module, so it is safe to run this initcall ++ * on all omaps ++ */ ++ oh = omap_hwmod_lookup(oh_name); ++ if (oh == NULL) ++ return -EINVAL; ++ ++ od = omap_device_build(dev_name, 0, oh, NULL, 0, ++ omap_spinlock_latency, ++ ARRAY_SIZE(omap_spinlock_latency), false); ++ if (IS_ERR(od)) { ++ pr_err("Can't build omap_device for %s:%s\n", dev_name, ++ oh_name); ++ retval = PTR_ERR(od); ++ } ++ ++ return retval; ++} ++/* early board code might need to reserve specific hwspinlock instances */ ++postcore_initcall(hwspinlocks_init); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/id.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/id.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/id.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/id.c 2011-03-09 13:19:09.817507478 +0100 +@@ -6,7 +6,7 @@ + * Copyright (C) 2005 Nokia Corporation + * Written by Tony Lindgren + * +- * Copyright (C) 2009 Texas Instruments ++ * Copyright (C) 2009-11 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar + * + * This program is free software; you can redistribute it and/or modify +@@ -191,12 +191,19 @@ + if (!cpu_is_omap3505() && !cpu_is_omap3517()) + omap3_features |= OMAP3_HAS_IO_WAKEUP; + ++ omap3_features |= OMAP3_HAS_SDRC; ++ + /* + * TODO: Get additional info (where applicable) + * e.g. Size of L2 cache. + */ + } + ++static void __init ti816x_check_features(void) ++{ ++ omap3_features = OMAP3_HAS_NEON; ++} ++ + static void __init omap3_check_revision(void) + { + u32 cpuid, idcode; +@@ -287,6 +294,20 @@ + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + } + break; ++ case 0xb81e: ++ omap_chip.oc = CHIP_IS_TI816X; ++ ++ switch (rev) { ++ case 0: ++ omap_revision = TI8168_REV_ES1_0; ++ break; ++ case 1: ++ omap_revision = TI8168_REV_ES1_1; ++ break; ++ default: ++ omap_revision = TI8168_REV_ES1_1; ++ } ++ break; + default: + /* Unknown default to latest silicon rev as default*/ + omap_revision = OMAP3630_REV_ES1_2; +@@ -307,7 +328,7 @@ + */ + idcode = read_tap_reg(OMAP_TAP_IDCODE); + hawkeye = (idcode >> 12) & 0xffff; +- rev = (idcode >> 28) & 0xff; ++ rev = (idcode >> 28) & 0xf; + + /* + * Few initial ES2.0 samples IDCODE is same as ES1.0 +@@ -326,22 +347,31 @@ + omap_chip.oc |= CHIP_IS_OMAP4430ES1; + break; + case 1: ++ default: + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; ++ } ++ break; ++ case 0xb95c: ++ switch (rev) { ++ case 3: ++ omap_revision = OMAP4430_REV_ES2_1; ++ omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; + break; ++ case 4: + default: +- omap_revision = OMAP4430_REV_ES2_0; +- omap_chip.oc |= CHIP_IS_OMAP4430ES2; +- } +- break; ++ omap_revision = OMAP4430_REV_ES2_2; ++ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; ++ } ++ break; + default: +- /* Unknown default to latest silicon rev as default*/ +- omap_revision = OMAP4430_REV_ES2_0; +- omap_chip.oc |= CHIP_IS_OMAP4430ES2; ++ /* Unknown default to latest silicon rev as default */ ++ omap_revision = OMAP4430_REV_ES2_2; ++ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; + } + +- pr_info("OMAP%04x ES%d.0\n", +- omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); ++ pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, ++ ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); + } + + #define OMAP3_SHOW_FEATURE(feat) \ +@@ -372,6 +402,8 @@ + /* Already set in omap3_check_revision() */ + strcpy(cpu_name, "AM3505"); + } ++ } else if (cpu_is_ti816x()) { ++ strcpy(cpu_name, "TI816X"); + } else if (omap3_has_iva() && omap3_has_sgx()) { + /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ + strcpy(cpu_name, "OMAP3430/3530"); +@@ -386,7 +418,7 @@ + strcpy(cpu_name, "OMAP3503"); + } + +- if (cpu_is_omap3630()) { ++ if (cpu_is_omap3630() || cpu_is_ti816x()) { + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); +@@ -462,7 +494,13 @@ + omap24xx_check_revision(); + } else if (cpu_is_omap34xx()) { + omap3_check_revision(); +- omap3_check_features(); ++ ++ /* TI816X doesn't have feature register */ ++ if (!cpu_is_ti816x()) ++ omap3_check_features(); ++ else ++ ti816x_check_features(); ++ + omap3_cpuinfo(); + return; + } else if (cpu_is_omap44xx()) { +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/debug-macro.S linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/debug-macro.S +--- linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/debug-macro.S 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/debug-macro.S 2011-03-09 13:19:09.819507439 +0100 +@@ -69,6 +69,12 @@ + beq 34f @ configure OMAP3UART4 + cmp \rp, #OMAP4UART4 @ only on 44xx + beq 44f @ configure OMAP4UART4 ++ cmp \rp, #TI816XUART1 @ ti816x UART offsets different ++ beq 81f @ configure UART1 ++ cmp \rp, #TI816XUART2 @ ti816x UART offsets different ++ beq 82f @ configure UART2 ++ cmp \rp, #TI816XUART3 @ ti816x UART offsets different ++ beq 83f @ configure UART3 + cmp \rp, #ZOOM_UART @ only on zoom2/3 + beq 95f @ configure ZOOM_UART + +@@ -91,6 +97,12 @@ + b 98f + 44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) + b 98f ++81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE) ++ b 98f ++82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE) ++ b 98f ++83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) ++ b 98f + 95: ldr \rp, =ZOOM_UART_BASE + mrc p15, 0, \rv, c1, c0 + tst \rv, #1 @ MMU enabled? +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/entry-macro.S linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/entry-macro.S +--- linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/entry-macro.S 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/entry-macro.S 2011-03-09 13:19:09.819507439 +0100 +@@ -61,6 +61,14 @@ + bne 9998f + ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ + cmp \irqnr, #0x0 ++ bne 9998f ++ ++ /* ++ * ti816x has additional IRQ pending register. Checking this ++ * register on omap2 & omap3 has no effect (read as 0). ++ */ ++ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ ++ cmp \irqnr, #0x0 + 9998: + ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] + and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ +@@ -133,6 +141,11 @@ + bne 9999f + ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ + cmp \irqnr, #0x0 ++#ifdef CONFIG_SOC_OMAPTI816X ++ bne 9999f ++ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ ++ cmp \irqnr, #0x0 ++#endif + 9999: + ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] + and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/io.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/io.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/io.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/io.c 2011-03-09 13:19:09.820507420 +0100 +@@ -30,7 +30,6 @@ + + #include + #include +-#include + #include + + #include "clock2xxx.h" +@@ -66,7 +65,7 @@ + }, + }; + +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + static struct map_desc omap242x_io_desc[] __initdata = { + { + .virtual = DSP_MEM_2420_VIRT, +@@ -90,7 +89,7 @@ + + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + static struct map_desc omap243x_io_desc[] __initdata = { + { + .virtual = L4_WK_243X_VIRT, +@@ -175,6 +174,18 @@ + #endif + }; + #endif ++ ++#ifdef CONFIG_SOC_OMAPTI816X ++static struct map_desc omapti816x_io_desc[] __initdata = { ++ { ++ .virtual = L4_34XX_VIRT, ++ .pfn = __phys_to_pfn(L4_34XX_PHYS), ++ .length = L4_34XX_SIZE, ++ .type = MT_DEVICE ++ }, ++}; ++#endif ++ + #ifdef CONFIG_ARCH_OMAP4 + static struct map_desc omap44xx_io_desc[] __initdata = { + { +@@ -241,7 +252,7 @@ + omap_sram_init(); + } + +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + void __init omap242x_map_common_io(void) + { + iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); +@@ -250,7 +261,7 @@ + } + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + void __init omap243x_map_common_io(void) + { + iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); +@@ -267,6 +278,14 @@ + } + #endif + ++#ifdef CONFIG_SOC_OMAPTI816X ++void __init omapti816x_map_common_io(void) ++{ ++ iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); ++ _omap2_map_common_io(); ++} ++#endif ++ + #ifdef CONFIG_ARCH_OMAP4 + void __init omap44xx_map_common_io(void) + { +@@ -398,15 +417,10 @@ + void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1) + { +- omap_serial_early_init(); +- +- omap_hwmod_late_init(); +- +- if (cpu_is_omap24xx() || cpu_is_omap34xx()) { ++ if (cpu_is_omap24xx() || omap3_has_sdrc()) { + omap2_sdrc_init(sdrc_cs0, sdrc_cs1); + _omap2_init_reprogram_sdrc(); + } +- gpmc_init(); + + omap_irq_base_init(); + } +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/iommu2.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/iommu2.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/iommu2.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/iommu2.c 2011-03-09 13:19:09.821507400 +0100 +@@ -145,35 +145,32 @@ + + static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) + { +- int i; + u32 stat, da; +- const char *err_msg[] = { +- "tlb miss", +- "translation fault", +- "emulation miss", +- "table walk fault", +- "multi hit fault", +- }; ++ u32 errs = 0; + + stat = iommu_read_reg(obj, MMU_IRQSTATUS); + stat &= MMU_IRQ_MASK; +- if (!stat) ++ if (!stat) { ++ *ra = 0; + return 0; ++ } + + da = iommu_read_reg(obj, MMU_FAULT_AD); + *ra = da; + +- dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); +- +- for (i = 0; i < ARRAY_SIZE(err_msg); i++) { +- if (stat & (1 << i)) +- printk("%s ", err_msg[i]); +- } +- printk("\n"); +- ++ if (stat & MMU_IRQ_TLBMISS) ++ errs |= OMAP_IOMMU_ERR_TLB_MISS; ++ if (stat & MMU_IRQ_TRANSLATIONFAULT) ++ errs |= OMAP_IOMMU_ERR_TRANS_FAULT; ++ if (stat & MMU_IRQ_EMUMISS) ++ errs |= OMAP_IOMMU_ERR_EMU_MISS; ++ if (stat & MMU_IRQ_TABLEWALKFAULT) ++ errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT; ++ if (stat & MMU_IRQ_MULTIHITFAULT) ++ errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT; + iommu_write_reg(obj, stat, MMU_IRQSTATUS); + +- return stat; ++ return errs; + } + + static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/irq.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/irq.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/irq.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/irq.c 2011-03-09 13:19:09.821507400 +0100 +@@ -61,8 +61,6 @@ + u32 mir[INTCPS_NR_MIR_REGS]; + }; + +-static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; +- + /* INTC bank register get/set */ + + static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) +@@ -110,7 +108,7 @@ + unsigned int irq = d->irq; + int offset = irq & (~(IRQ_BITS_PER_REG - 1)); + +- if (cpu_is_omap34xx()) { ++ if (cpu_is_omap34xx() && !cpu_is_ti816x()) { + int spurious = 0; + + /* +@@ -205,6 +203,9 @@ + + BUG_ON(!base); + ++ if (cpu_is_ti816x()) ++ bank->nr_irqs = 128; ++ + /* Static mapping, never released */ + bank->base_reg = ioremap(base, SZ_4K); + if (!bank->base_reg) { +@@ -229,6 +230,8 @@ + } + + #ifdef CONFIG_ARCH_OMAP3 ++static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; ++ + void omap_intc_save_context(void) + { + int ind = 0, i = 0; +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/Kconfig linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Kconfig +--- linux-2.6.38-rc7/arch/arm/mach-omap2/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Kconfig 2011-03-09 13:19:09.792507988 +0100 +@@ -53,25 +53,30 @@ + comment "OMAP Core Type" + depends on ARCH_OMAP2 + +-config ARCH_OMAP2420 ++config SOC_OMAP2420 + bool "OMAP2420 support" + depends on ARCH_OMAP2 + default y + select OMAP_DM_TIMER + select ARCH_OMAP_OTG + +-config ARCH_OMAP2430 ++config SOC_OMAP2430 + bool "OMAP2430 support" + depends on ARCH_OMAP2 + default y + select ARCH_OMAP_OTG + +-config ARCH_OMAP3430 ++config SOC_OMAP3430 + bool "OMAP3430 support" + depends on ARCH_OMAP3 + default y + select ARCH_OMAP_OTG + ++config SOC_OMAPTI816X ++ bool "TI816X support" ++ depends on ARCH_OMAP3 ++ default y ++ + config OMAP_PACKAGE_ZAF + bool + +@@ -106,25 +111,25 @@ + + config MACH_OMAP2_TUSB6010 + bool +- depends on ARCH_OMAP2 && ARCH_OMAP2420 ++ depends on ARCH_OMAP2 && SOC_OMAP2420 + default y if MACH_NOKIA_N8X0 + + config MACH_OMAP_H4 + bool "OMAP 2420 H4 board" +- depends on ARCH_OMAP2420 ++ depends on SOC_OMAP2420 + default y + select OMAP_PACKAGE_ZAF + select OMAP_DEBUG_DEVICES + + config MACH_OMAP_APOLLON + bool "OMAP 2420 Apollon board" +- depends on ARCH_OMAP2420 ++ depends on SOC_OMAP2420 + default y + select OMAP_PACKAGE_ZAC + + config MACH_OMAP_2430SDP + bool "OMAP 2430 SDP board" +- depends on ARCH_OMAP2430 ++ depends on SOC_OMAP2430 + default y + select OMAP_PACKAGE_ZAC + +@@ -219,7 +224,7 @@ + + config MACH_NOKIA_N8X0 + bool "Nokia N800/N810" +- depends on ARCH_OMAP2420 ++ depends on SOC_OMAP2420 + default y + select OMAP_PACKAGE_ZAC + select MACH_NOKIA_N800 +@@ -294,12 +299,18 @@ + default y + select OMAP_PACKAGE_CBP + ++config MACH_TI8168EVM ++ bool "TI8168 Evaluation Module" ++ depends on SOC_OMAPTI816X ++ default y ++ + config MACH_OMAP_4430SDP + bool "OMAP 4430 SDP board" + default y + depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS ++ select REGULATOR_FIXED_VOLTAGE + + config MACH_OMAP4_PANDA + bool "OMAP4 Panda Board" +@@ -307,6 +318,7 @@ + depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS ++ select REGULATOR_FIXED_VOLTAGE + + config OMAP3_EMU + bool "OMAP3 debugging peripherals" +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/mailbox.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mailbox.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/mailbox.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mailbox.c 2011-03-09 13:19:09.821507400 +0100 +@@ -14,12 +14,11 @@ + #include + #include + #include ++#include + #include + #include + + #define MAILBOX_REVISION 0x000 +-#define MAILBOX_SYSCONFIG 0x010 +-#define MAILBOX_SYSSTATUS 0x014 + #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) + #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) + #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) +@@ -33,17 +32,6 @@ + #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) + #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) + +-/* SYSCONFIG: register bit definition */ +-#define AUTOIDLE (1 << 0) +-#define SOFTRESET (1 << 1) +-#define SMARTIDLE (2 << 3) +-#define OMAP4_SOFTRESET (1 << 0) +-#define OMAP4_NOIDLE (1 << 2) +-#define OMAP4_SMARTIDLE (2 << 2) +- +-/* SYSSTATUS: register bit definition */ +-#define RESETDONE (1 << 0) +- + #define MBOX_REG_SIZE 0x120 + + #define OMAP4_MBOX_REG_SIZE 0x130 +@@ -70,8 +58,6 @@ + unsigned long irqdisable; + }; + +-static struct clk *mbox_ick_handle; +- + static void omap2_mbox_enable_irq(struct omap_mbox *mbox, + omap_mbox_type_t irq); + +@@ -89,53 +75,13 @@ + static int omap2_mbox_startup(struct omap_mbox *mbox) + { + u32 l; +- unsigned long timeout; + +- mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); +- if (IS_ERR(mbox_ick_handle)) { +- printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", +- PTR_ERR(mbox_ick_handle)); +- return PTR_ERR(mbox_ick_handle); +- } +- clk_enable(mbox_ick_handle); +- +- if (cpu_is_omap44xx()) { +- mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG); +- timeout = jiffies + msecs_to_jiffies(20); +- do { +- l = mbox_read_reg(MAILBOX_SYSCONFIG); +- if (!(l & OMAP4_SOFTRESET)) +- break; +- } while (!time_after(jiffies, timeout)); +- +- if (l & OMAP4_SOFTRESET) { +- pr_err("Can't take mailbox out of reset\n"); +- return -ENODEV; +- } +- } else { +- mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG); +- timeout = jiffies + msecs_to_jiffies(20); +- do { +- l = mbox_read_reg(MAILBOX_SYSSTATUS); +- if (l & RESETDONE) +- break; +- } while (!time_after(jiffies, timeout)); +- +- if (!(l & RESETDONE)) { +- pr_err("Can't take mailbox out of reset\n"); +- return -ENODEV; +- } +- } ++ pm_runtime_enable(mbox->dev->parent); ++ pm_runtime_get_sync(mbox->dev->parent); + + l = mbox_read_reg(MAILBOX_REVISION); + pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); + +- if (cpu_is_omap44xx()) +- l = OMAP4_SMARTIDLE; +- else +- l = SMARTIDLE | AUTOIDLE; +- mbox_write_reg(l, MAILBOX_SYSCONFIG); +- + omap2_mbox_enable_irq(mbox, IRQ_RX); + + return 0; +@@ -143,9 +89,8 @@ + + static void omap2_mbox_shutdown(struct omap_mbox *mbox) + { +- clk_disable(mbox_ick_handle); +- clk_put(mbox_ick_handle); +- mbox_ick_handle = NULL; ++ pm_runtime_put_sync(mbox->dev->parent); ++ pm_runtime_disable(mbox->dev->parent); + } + + /* Mailbox FIFO handle functions */ +@@ -310,7 +255,7 @@ + struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; + #endif + +-#if defined(CONFIG_ARCH_OMAP2420) ++#if defined(CONFIG_SOC_OMAP2420) + /* IVA */ + static struct omap_mbox2_priv omap2_mbox_iva_priv = { + .tx_fifo = { +@@ -398,14 +343,14 @@ + else if (cpu_is_omap34xx()) { + list = omap3_mboxes; + +- list[0]->irq = platform_get_irq_byname(pdev, "dsp"); ++ list[0]->irq = platform_get_irq(pdev, 0); + } + #endif + #if defined(CONFIG_ARCH_OMAP2) + else if (cpu_is_omap2430()) { + list = omap2_mboxes; + +- list[0]->irq = platform_get_irq_byname(pdev, "dsp"); ++ list[0]->irq = platform_get_irq(pdev, 0); + } else if (cpu_is_omap2420()) { + list = omap2_mboxes; + +@@ -417,8 +362,7 @@ + else if (cpu_is_omap44xx()) { + list = omap4_mboxes; + +- list[0]->irq = list[1]->irq = +- platform_get_irq_byname(pdev, "mbox"); ++ list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0); + } + #endif + else { +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/Makefile linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Makefile +--- linux-2.6.38-rc7/arch/arm/mach-omap2/Makefile 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Makefile 2011-03-09 13:19:09.793507967 +0100 +@@ -31,8 +31,8 @@ + AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec) + + # Functions loaded to SRAM +-obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o +-obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o ++obj-$(CONFIG_SOC_OMAP2420) += sram242x.o ++obj-$(CONFIG_SOC_OMAP2430) += sram243x.o + obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o + + AFLAGS_sram242x.o :=-Wa,-march=armv6 +@@ -40,8 +40,8 @@ + AFLAGS_sram34xx.o :=-Wa,-march=armv7-a + + # Pin multiplexing +-obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o +-obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o ++obj-$(CONFIG_SOC_OMAP2420) += mux2420.o ++obj-$(CONFIG_SOC_OMAP2430) += mux2430.o + obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o + obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o + +@@ -113,8 +113,8 @@ + clkt2xxx_dpllcore.o \ + clkt2xxx_virt_prcm_set.o \ + clkt2xxx_apll.o clkt2xxx_osc.o +-obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o +-obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o ++obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o ++obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o + obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ + clock34xx.o clkt34xx_dpll3m2.o \ + clock3517.o clock36xx.o \ +@@ -123,12 +123,12 @@ + dpll3xxx.o + + # OMAP2 clock rate set data (old "OPP" data) +-obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o +-obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o ++obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o ++obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o + + # hwmod data +-obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o +-obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o ++obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o ++obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o + obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o + obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o + +@@ -218,12 +218,14 @@ + hsmmc.o \ + omap_phy_internal.o + +-obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o ++obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \ ++ omap_phy_internal.o \ + + obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o + + obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ + hsmmc.o ++obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o + # Platform specific device init code + usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o + obj-y += $(usbfs-m) $(usbfs-y) +@@ -242,3 +244,7 @@ + + smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o + obj-y += $(smsc911x-m) $(smsc911x-y) ++obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o ++ ++disp-$(CONFIG_OMAP2_DSS) := display.o ++obj-y += $(disp-m) $(disp-y) +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mcbsp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/mcbsp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mcbsp.c 2011-03-09 13:19:09.821507400 +0100 +@@ -22,10 +22,11 @@ + #include + #include + #include ++#include ++#include + + #include "control.h" + +- + /* McBSP internal signal muxing functions */ + + void omap2_mcbsp1_mux_clkr_src(u8 mux) +@@ -83,7 +84,7 @@ + return -EINVAL; + } + +- clk_disable(mcbsp->fclk); ++ pm_runtime_put_sync(mcbsp->dev); + + r = clk_set_parent(mcbsp->fclk, fck_src); + if (IS_ERR_VALUE(r)) { +@@ -93,7 +94,7 @@ + return -EINVAL; + } + +- clk_enable(mcbsp->fclk); ++ pm_runtime_get_sync(mcbsp->dev); + + clk_put(fck_src); + +@@ -101,196 +102,70 @@ + } + EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); + +- +-/* Platform data */ +- +-#ifdef CONFIG_ARCH_OMAP2420 +-static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { ++struct omap_device_pm_latency omap2_mcbsp_latency[] = { + { +- .phys_base = OMAP24XX_MCBSP1_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, +- .rx_irq = INT_24XX_MCBSP1_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP1_IRQ_TX, +- }, +- { +- .phys_base = OMAP24XX_MCBSP2_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, +- .rx_irq = INT_24XX_MCBSP2_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP2_IRQ_TX, ++ .deactivate_func = omap_device_idle_hwmods, ++ .activate_func = omap_device_enable_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, + }; +-#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) +-#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +-#else +-#define omap2420_mcbsp_pdata NULL +-#define OMAP2420_MCBSP_PDATA_SZ 0 +-#define OMAP2420_MCBSP_REG_NUM 0 +-#endif + +-#ifdef CONFIG_ARCH_OMAP2430 +-static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { +- { +- .phys_base = OMAP24XX_MCBSP1_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, +- .rx_irq = INT_24XX_MCBSP1_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP1_IRQ_TX, +- }, +- { +- .phys_base = OMAP24XX_MCBSP2_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, +- .rx_irq = INT_24XX_MCBSP2_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP2_IRQ_TX, +- }, +- { +- .phys_base = OMAP2430_MCBSP3_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, +- .rx_irq = INT_24XX_MCBSP3_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP3_IRQ_TX, +- }, +- { +- .phys_base = OMAP2430_MCBSP4_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, +- .rx_irq = INT_24XX_MCBSP4_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP4_IRQ_TX, +- }, +- { +- .phys_base = OMAP2430_MCBSP5_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, +- .rx_irq = INT_24XX_MCBSP5_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP5_IRQ_TX, +- }, +-}; +-#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) +-#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +-#else +-#define omap2430_mcbsp_pdata NULL +-#define OMAP2430_MCBSP_PDATA_SZ 0 +-#define OMAP2430_MCBSP_REG_NUM 0 +-#endif ++static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) ++{ ++ int id, count = 1; ++ char *name = "omap-mcbsp"; ++ struct omap_hwmod *oh_device[2]; ++ struct omap_mcbsp_platform_data *pdata = NULL; ++ struct omap_device *od; ++ ++ sscanf(oh->name, "mcbsp%d", &id); ++ ++ pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL); ++ if (!pdata) { ++ pr_err("%s: No memory for mcbsp\n", __func__); ++ return -ENOMEM; ++ } + +-#ifdef CONFIG_ARCH_OMAP3 +-static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { +- { +- .phys_base = OMAP34XX_MCBSP1_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, +- .rx_irq = INT_24XX_MCBSP1_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP1_IRQ_TX, +- .buffer_size = 0x80, /* The FIFO has 128 locations */ +- }, +- { +- .phys_base = OMAP34XX_MCBSP2_BASE, +- .phys_base_st = OMAP34XX_MCBSP2_ST_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, +- .rx_irq = INT_24XX_MCBSP2_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP2_IRQ_TX, +- .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ +- }, +- { +- .phys_base = OMAP34XX_MCBSP3_BASE, +- .phys_base_st = OMAP34XX_MCBSP3_ST_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, +- .rx_irq = INT_24XX_MCBSP3_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP3_IRQ_TX, +- .buffer_size = 0x80, /* The FIFO has 128 locations */ +- }, +- { +- .phys_base = OMAP34XX_MCBSP4_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, +- .rx_irq = INT_24XX_MCBSP4_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP4_IRQ_TX, +- .buffer_size = 0x80, /* The FIFO has 128 locations */ +- }, +- { +- .phys_base = OMAP34XX_MCBSP5_BASE, +- .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, +- .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, +- .rx_irq = INT_24XX_MCBSP5_IRQ_RX, +- .tx_irq = INT_24XX_MCBSP5_IRQ_TX, +- .buffer_size = 0x80, /* The FIFO has 128 locations */ +- }, +-}; +-#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) +-#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +-#else +-#define omap34xx_mcbsp_pdata NULL +-#define OMAP34XX_MCBSP_PDATA_SZ 0 +-#define OMAP34XX_MCBSP_REG_NUM 0 +-#endif ++ pdata->mcbsp_config_type = oh->class->rev; + +-static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { +- { +- .phys_base = OMAP44XX_MCBSP1_BASE, +- .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, +- .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, +- .tx_irq = OMAP44XX_IRQ_MCBSP1, +- }, +- { +- .phys_base = OMAP44XX_MCBSP2_BASE, +- .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, +- .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, +- .tx_irq = OMAP44XX_IRQ_MCBSP2, +- }, +- { +- .phys_base = OMAP44XX_MCBSP3_BASE, +- .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, +- .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, +- .tx_irq = OMAP44XX_IRQ_MCBSP3, +- }, +- { +- .phys_base = OMAP44XX_MCBSP4_BASE, +- .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, +- .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, +- .tx_irq = OMAP44XX_IRQ_MCBSP4, +- }, +-}; +-#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) +-#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) ++ if (oh->class->rev == MCBSP_CONFIG_TYPE3) { ++ if (id == 2) ++ /* The FIFO has 1024 + 256 locations */ ++ pdata->buffer_size = 0x500; ++ else ++ /* The FIFO has 128 locations */ ++ pdata->buffer_size = 0x80; ++ } ++ ++ oh_device[0] = oh; ++ ++ if (oh->dev_attr) { ++ oh_device[1] = omap_hwmod_lookup(( ++ (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); ++ count++; ++ } ++ od = omap_device_build_ss(name, id, oh_device, count, pdata, ++ sizeof(*pdata), omap2_mcbsp_latency, ++ ARRAY_SIZE(omap2_mcbsp_latency), false); ++ kfree(pdata); ++ if (IS_ERR(od)) { ++ pr_err("%s: Cant build omap_device for %s:%s.\n", __func__, ++ name, oh->name); ++ return PTR_ERR(od); ++ } ++ omap_mcbsp_count++; ++ return 0; ++} + + static int __init omap2_mcbsp_init(void) + { +- if (cpu_is_omap2420()) { +- omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; +- omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); +- } else if (cpu_is_omap2430()) { +- omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; +- omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); +- } else if (cpu_is_omap34xx()) { +- omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; +- omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32); +- } else if (cpu_is_omap44xx()) { +- omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; +- omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32); +- } ++ omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); + + mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), + GFP_KERNEL); + if (!mcbsp_ptr) + return -ENOMEM; + +- if (cpu_is_omap2420()) +- omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, +- OMAP2420_MCBSP_PDATA_SZ); +- if (cpu_is_omap2430()) +- omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, +- OMAP2430_MCBSP_PDATA_SZ); +- if (cpu_is_omap34xx()) +- omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, +- OMAP34XX_MCBSP_PDATA_SZ); +- if (cpu_is_omap44xx()) +- omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, +- OMAP44XX_MCBSP_PDATA_SZ); +- + return omap_mcbsp_init(); + } + arch_initcall(omap2_mcbsp_init); +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2420_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2420_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2420_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2420_data.c 2011-03-09 13:19:09.827507277 +0100 +@@ -18,6 +18,10 @@ + #include + #include + #include ++#include ++#include ++#include ++#include + + #include "omap_hwmod_common_data.h" + +@@ -38,12 +42,18 @@ + static struct omap_hwmod omap2420_iva_hwmod; + static struct omap_hwmod omap2420_l3_main_hwmod; + static struct omap_hwmod omap2420_l4_core_hwmod; ++static struct omap_hwmod omap2420_dss_core_hwmod; ++static struct omap_hwmod omap2420_dss_dispc_hwmod; ++static struct omap_hwmod omap2420_dss_rfbi_hwmod; ++static struct omap_hwmod omap2420_dss_venc_hwmod; + static struct omap_hwmod omap2420_wd_timer2_hwmod; + static struct omap_hwmod omap2420_gpio1_hwmod; + static struct omap_hwmod omap2420_gpio2_hwmod; + static struct omap_hwmod omap2420_gpio3_hwmod; + static struct omap_hwmod omap2420_gpio4_hwmod; + static struct omap_hwmod omap2420_dma_system_hwmod; ++static struct omap_hwmod omap2420_mcspi1_hwmod; ++static struct omap_hwmod omap2420_mcspi2_hwmod; + + /* L3 -> L4_CORE interface */ + static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { +@@ -64,6 +74,19 @@ + &omap2420_mpu__l3_main, + }; + ++/* DSS -> l3 */ ++static struct omap_hwmod_ocp_if omap2420_dss__l3 = { ++ .master = &omap2420_dss_core_hwmod, ++ .slave = &omap2420_l3_main_hwmod, ++ .fw = { ++ .omap2 = { ++ .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, ++ .flags = OMAP_FIREWALL_L3, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* Master interfaces on the L3 interconnect */ + static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { + &omap2420_l3_main__l4_core, +@@ -87,6 +110,44 @@ + static struct omap_hwmod omap2420_uart3_hwmod; + static struct omap_hwmod omap2420_i2c1_hwmod; + static struct omap_hwmod omap2420_i2c2_hwmod; ++static struct omap_hwmod omap2420_mcbsp1_hwmod; ++static struct omap_hwmod omap2420_mcbsp2_hwmod; ++ ++/* l4 core -> mcspi1 interface */ ++static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { ++ { ++ .pa_start = 0x48098000, ++ .pa_end = 0x480980ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_mcspi1_hwmod, ++ .clk = "mcspi1_ick", ++ .addr = omap2420_mcspi1_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4 core -> mcspi2 interface */ ++static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { ++ { ++ .pa_start = 0x4809a000, ++ .pa_end = 0x4809a0ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_mcspi2_hwmod, ++ .clk = "mcspi2_ick", ++ .addr = omap2420_mcspi2_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; + + /* L4_CORE -> L4_WKUP interface */ + static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { +@@ -279,6 +340,625 @@ + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) + }; + ++/* Timer Common */ ++static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2420_timer_hwmod_class = { ++ .name = "timer", ++ .sysc = &omap2420_timer_sysc, ++ .rev = OMAP_TIMER_IP_VERSION_1, ++}; ++ ++/* timer1 */ ++static struct omap_hwmod omap2420_timer1_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { ++ { .irq = 37, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { ++ { ++ .pa_start = 0x48028000, ++ .pa_end = 0x48028000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_wkup -> timer1 */ ++static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { ++ .master = &omap2420_l4_wkup_hwmod, ++ .slave = &omap2420_timer1_hwmod, ++ .clk = "gpt1_ick", ++ .addr = omap2420_timer1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer1 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { ++ &omap2420_l4_wkup__timer1, ++}; ++ ++/* timer1 hwmod */ ++static struct omap_hwmod omap2420_timer1_hwmod = { ++ .name = "timer1", ++ .mpu_irqs = omap2420_timer1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs), ++ .main_clk = "gpt1_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT1_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer2 */ ++static struct omap_hwmod omap2420_timer2_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { ++ { .irq = 38, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = { ++ { ++ .pa_start = 0x4802a000, ++ .pa_end = 0x4802a000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer2 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer2_hwmod, ++ .clk = "gpt2_ick", ++ .addr = omap2420_timer2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer2 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { ++ &omap2420_l4_core__timer2, ++}; ++ ++/* timer2 hwmod */ ++static struct omap_hwmod omap2420_timer2_hwmod = { ++ .name = "timer2", ++ .mpu_irqs = omap2420_timer2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs), ++ .main_clk = "gpt2_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT2_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer3 */ ++static struct omap_hwmod omap2420_timer3_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { ++ { .irq = 39, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = { ++ { ++ .pa_start = 0x48078000, ++ .pa_end = 0x48078000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer3 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer3_hwmod, ++ .clk = "gpt3_ick", ++ .addr = omap2420_timer3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer3 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { ++ &omap2420_l4_core__timer3, ++}; ++ ++/* timer3 hwmod */ ++static struct omap_hwmod omap2420_timer3_hwmod = { ++ .name = "timer3", ++ .mpu_irqs = omap2420_timer3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs), ++ .main_clk = "gpt3_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT3_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer4 */ ++static struct omap_hwmod omap2420_timer4_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { ++ { .irq = 40, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = { ++ { ++ .pa_start = 0x4807a000, ++ .pa_end = 0x4807a000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer4 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer4_hwmod, ++ .clk = "gpt4_ick", ++ .addr = omap2420_timer4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer4 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { ++ &omap2420_l4_core__timer4, ++}; ++ ++/* timer4 hwmod */ ++static struct omap_hwmod omap2420_timer4_hwmod = { ++ .name = "timer4", ++ .mpu_irqs = omap2420_timer4_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs), ++ .main_clk = "gpt4_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT4_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer5 */ ++static struct omap_hwmod omap2420_timer5_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { ++ { .irq = 41, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = { ++ { ++ .pa_start = 0x4807c000, ++ .pa_end = 0x4807c000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer5 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer5_hwmod, ++ .clk = "gpt5_ick", ++ .addr = omap2420_timer5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer5 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { ++ &omap2420_l4_core__timer5, ++}; ++ ++/* timer5 hwmod */ ++static struct omap_hwmod omap2420_timer5_hwmod = { ++ .name = "timer5", ++ .mpu_irqs = omap2420_timer5_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs), ++ .main_clk = "gpt5_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT5_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++ ++/* timer6 */ ++static struct omap_hwmod omap2420_timer6_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { ++ { .irq = 42, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = { ++ { ++ .pa_start = 0x4807e000, ++ .pa_end = 0x4807e000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer6 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer6_hwmod, ++ .clk = "gpt6_ick", ++ .addr = omap2420_timer6_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer6 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { ++ &omap2420_l4_core__timer6, ++}; ++ ++/* timer6 hwmod */ ++static struct omap_hwmod omap2420_timer6_hwmod = { ++ .name = "timer6", ++ .mpu_irqs = omap2420_timer6_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs), ++ .main_clk = "gpt6_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT6_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer6_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer7 */ ++static struct omap_hwmod omap2420_timer7_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { ++ { .irq = 43, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = { ++ { ++ .pa_start = 0x48080000, ++ .pa_end = 0x48080000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer7 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer7_hwmod, ++ .clk = "gpt7_ick", ++ .addr = omap2420_timer7_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer7 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { ++ &omap2420_l4_core__timer7, ++}; ++ ++/* timer7 hwmod */ ++static struct omap_hwmod omap2420_timer7_hwmod = { ++ .name = "timer7", ++ .mpu_irqs = omap2420_timer7_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs), ++ .main_clk = "gpt7_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT7_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer7_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer8 */ ++static struct omap_hwmod omap2420_timer8_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { ++ { .irq = 44, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = { ++ { ++ .pa_start = 0x48082000, ++ .pa_end = 0x48082000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer8 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer8_hwmod, ++ .clk = "gpt8_ick", ++ .addr = omap2420_timer8_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer8 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { ++ &omap2420_l4_core__timer8, ++}; ++ ++/* timer8 hwmod */ ++static struct omap_hwmod omap2420_timer8_hwmod = { ++ .name = "timer8", ++ .mpu_irqs = omap2420_timer8_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs), ++ .main_clk = "gpt8_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT8_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer8_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer9 */ ++static struct omap_hwmod omap2420_timer9_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { ++ { .irq = 45, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = { ++ { ++ .pa_start = 0x48084000, ++ .pa_end = 0x48084000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer9 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer9_hwmod, ++ .clk = "gpt9_ick", ++ .addr = omap2420_timer9_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer9 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { ++ &omap2420_l4_core__timer9, ++}; ++ ++/* timer9 hwmod */ ++static struct omap_hwmod omap2420_timer9_hwmod = { ++ .name = "timer9", ++ .mpu_irqs = omap2420_timer9_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs), ++ .main_clk = "gpt9_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT9_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer9_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer10 */ ++static struct omap_hwmod omap2420_timer10_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { ++ { .irq = 46, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = { ++ { ++ .pa_start = 0x48086000, ++ .pa_end = 0x48086000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer10 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer10_hwmod, ++ .clk = "gpt10_ick", ++ .addr = omap2420_timer10_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer10 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { ++ &omap2420_l4_core__timer10, ++}; ++ ++/* timer10 hwmod */ ++static struct omap_hwmod omap2420_timer10_hwmod = { ++ .name = "timer10", ++ .mpu_irqs = omap2420_timer10_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs), ++ .main_clk = "gpt10_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT10_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer10_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer11 */ ++static struct omap_hwmod omap2420_timer11_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { ++ { .irq = 47, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = { ++ { ++ .pa_start = 0x48088000, ++ .pa_end = 0x48088000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer11 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer11_hwmod, ++ .clk = "gpt11_ick", ++ .addr = omap2420_timer11_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer11 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { ++ &omap2420_l4_core__timer11, ++}; ++ ++/* timer11 hwmod */ ++static struct omap_hwmod omap2420_timer11_hwmod = { ++ .name = "timer11", ++ .mpu_irqs = omap2420_timer11_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs), ++ .main_clk = "gpt11_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT11_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer11_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ ++/* timer12 */ ++static struct omap_hwmod omap2420_timer12_hwmod; ++static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { ++ { .irq = 48, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = { ++ { ++ .pa_start = 0x4808a000, ++ .pa_end = 0x4808a000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer12 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_timer12_hwmod, ++ .clk = "gpt12_ick", ++ .addr = omap2420_timer12_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer12 slave port */ ++static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { ++ &omap2420_l4_core__timer12, ++}; ++ ++/* timer12 hwmod */ ++static struct omap_hwmod omap2420_timer12_hwmod = { ++ .name = "timer12", ++ .mpu_irqs = omap2420_timer12_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs), ++ .main_clk = "gpt12_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT12_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_timer12_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), ++ .class = &omap2420_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) ++}; ++ + /* l4_wkup -> wd_timer2 */ + static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { + { +@@ -354,120 +1034,404 @@ + .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_class uart_class = { +- .name = "uart", +- .sysc = &uart_sysc, ++static struct omap_hwmod_class uart_class = { ++ .name = "uart", ++ .sysc = &uart_sysc, ++}; ++ ++/* UART1 */ ++ ++static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { ++ { .irq = INT_24XX_UART1_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { ++ &omap2_l4_core__uart1, ++}; ++ ++static struct omap_hwmod omap2420_uart1_hwmod = { ++ .name = "uart1", ++ .mpu_irqs = uart1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), ++ .sdma_reqs = uart1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), ++ .main_clk = "uart1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_UART1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_uart1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ ++/* UART2 */ ++ ++static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { ++ { .irq = INT_24XX_UART2_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { ++ &omap2_l4_core__uart2, ++}; ++ ++static struct omap_hwmod omap2420_uart2_hwmod = { ++ .name = "uart2", ++ .mpu_irqs = uart2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), ++ .sdma_reqs = uart2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), ++ .main_clk = "uart2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_UART2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_uart2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ ++/* UART3 */ ++ ++static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { ++ { .irq = INT_24XX_UART3_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { ++ &omap2_l4_core__uart3, ++}; ++ ++static struct omap_hwmod omap2420_uart3_hwmod = { ++ .name = "uart3", ++ .mpu_irqs = uart3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), ++ .sdma_reqs = uart3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), ++ .main_clk = "uart3_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 2, ++ .module_bit = OMAP24XX_EN_UART3_SHIFT, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_uart3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ ++/* ++ * 'dss' class ++ * display sub-system ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2420_dss_hwmod_class = { ++ .name = "dss", ++ .sysc = &omap2420_dss_sysc, ++}; ++ ++static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { ++ { .name = "dispc", .dma_req = 5 }, ++}; ++ ++/* dss */ ++/* dss master ports */ ++static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { ++ &omap2420_dss__l3, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_dss_addrs[] = { ++ { ++ .pa_start = 0x48050000, ++ .pa_end = 0x480503FF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_dss_core_hwmod, ++ .clk = "dss_ick", ++ .addr = omap2420_dss_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss slave ports */ ++static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { ++ &omap2420_l4_core__dss, ++}; ++ ++static struct omap_hwmod_opt_clk dss_opt_clks[] = { ++ { .role = "tv_clk", .clk = "dss_54m_fck" }, ++ { .role = "sys_clk", .clk = "dss2_fck" }, ++}; ++ ++static struct omap_hwmod omap2420_dss_core_hwmod = { ++ .name = "dss_core", ++ .class = &omap2420_dss_hwmod_class, ++ .main_clk = "dss1_fck", /* instead of dss_fck */ ++ .sdma_reqs = omap2420_dss_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, ++ }, ++ }, ++ .opt_clks = dss_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), ++ .slaves = omap2420_dss_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), ++ .masters = omap2420_dss_masters, ++ .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'dispc' class ++ * display controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2420_dispc_hwmod_class = { ++ .name = "dispc", ++ .sysc = &omap2420_dispc_sysc, + }; + +-/* UART1 */ ++static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = { ++ { .irq = 25 }, ++}; + +-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { +- { .irq = INT_24XX_UART1_IRQ, }, ++static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { ++ { ++ .pa_start = 0x48050400, ++ .pa_end = 0x480507FF, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, ++/* l4_core -> dss_dispc */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_dss_dispc_hwmod, ++ .clk = "dss_ick", ++ .addr = omap2420_dss_dispc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { +- &omap2_l4_core__uart1, ++/* dss_dispc slave ports */ ++static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { ++ &omap2420_l4_core__dss_dispc, + }; + +-static struct omap_hwmod omap2420_uart1_hwmod = { +- .name = "uart1", +- .mpu_irqs = uart1_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), +- .sdma_reqs = uart1_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), +- .main_clk = "uart1_fck", ++static struct omap_hwmod omap2420_dss_dispc_hwmod = { ++ .name = "dss_dispc", ++ .class = &omap2420_dispc_hwmod_class, ++ .mpu_irqs = omap2420_dispc_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs), ++ .main_clk = "dss1_fck", + .prcm = { + .omap2 = { +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_UART1_SHIFT, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, ++ .module_offs = CORE_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, ++ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, +- .slaves = omap2420_uart1_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), +- .class = &uart_class, ++ .slaves = omap2420_dss_dispc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++ .flags = HWMOD_NO_IDLEST, + }; + +-/* UART2 */ ++/* ++ * 'rfbi' class ++ * remote frame buffer interface ++ */ + +-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { +- { .irq = INT_24XX_UART2_IRQ, }, ++static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, ++static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { ++ .name = "rfbi", ++ .sysc = &omap2420_rfbi_sysc, + }; + +-static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { +- &omap2_l4_core__uart2, ++static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = { ++ { ++ .pa_start = 0x48050800, ++ .pa_end = 0x48050BFF, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod omap2420_uart2_hwmod = { +- .name = "uart2", +- .mpu_irqs = uart2_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), +- .sdma_reqs = uart2_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), +- .main_clk = "uart2_fck", ++/* l4_core -> dss_rfbi */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_dss_rfbi_hwmod, ++ .clk = "dss_ick", ++ .addr = omap2420_dss_rfbi_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_rfbi slave ports */ ++static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { ++ &omap2420_l4_core__dss_rfbi, ++}; ++ ++static struct omap_hwmod omap2420_dss_rfbi_hwmod = { ++ .name = "dss_rfbi", ++ .class = &omap2420_rfbi_hwmod_class, ++ .main_clk = "dss1_fck", + .prcm = { + .omap2 = { +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_UART2_SHIFT, +- .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, ++ .module_offs = CORE_MOD, + }, + }, +- .slaves = omap2420_uart2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), +- .class = &uart_class, ++ .slaves = omap2420_dss_rfbi_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++ .flags = HWMOD_NO_IDLEST, + }; + +-/* UART3 */ ++/* ++ * 'venc' class ++ * video encoder ++ */ + +-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { +- { .irq = INT_24XX_UART3_IRQ, }, ++static struct omap_hwmod_class omap2420_venc_hwmod_class = { ++ .name = "venc", + }; + +-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, ++/* dss_venc */ ++static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = { ++ { ++ .pa_start = 0x48050C00, ++ .pa_end = 0x48050FFF, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { +- &omap2_l4_core__uart3, ++/* l4_core -> dss_venc */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_dss_venc_hwmod, ++ .clk = "dss_54m_fck", ++ .addr = omap2420_dss_venc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod omap2420_uart3_hwmod = { +- .name = "uart3", +- .mpu_irqs = uart3_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), +- .sdma_reqs = uart3_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), +- .main_clk = "uart3_fck", ++/* dss_venc slave ports */ ++static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { ++ &omap2420_l4_core__dss_venc, ++}; ++ ++static struct omap_hwmod omap2420_dss_venc_hwmod = { ++ .name = "dss_venc", ++ .class = &omap2420_venc_hwmod_class, ++ .main_clk = "dss1_fck", + .prcm = { + .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, +- .prcm_reg_id = 2, +- .module_bit = OMAP24XX_EN_UART3_SHIFT, +- .idlest_reg_id = 2, +- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, +- .slaves = omap2420_uart3_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), +- .class = &uart_class, ++ .slaves = omap2420_dss_venc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++ .flags = HWMOD_NO_IDLEST, + }; + + /* I2C common */ +@@ -864,16 +1828,342 @@ + .flags = HWMOD_NO_IDLEST, + }; + ++/* ++ * 'mailbox' class ++ * mailbox module allowing communication between the on-chip processors ++ * using a queued mailbox-interrupt mechanism. ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = { ++ .rev_offs = 0x000, ++ .sysc_offs = 0x010, ++ .syss_offs = 0x014, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2420_mailbox_hwmod_class = { ++ .name = "mailbox", ++ .sysc = &omap2420_mailbox_sysc, ++}; ++ ++/* mailbox */ ++static struct omap_hwmod omap2420_mailbox_hwmod; ++static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { ++ { .name = "dsp", .irq = 26 }, ++ { .name = "iva", .irq = 34 }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = { ++ { ++ .pa_start = 0x48094000, ++ .pa_end = 0x480941ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++/* l4_core -> mailbox */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_mailbox_hwmod, ++ .addr = omap2420_mailbox_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mailbox slave ports */ ++static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { ++ &omap2420_l4_core__mailbox, ++}; ++ ++static struct omap_hwmod omap2420_mailbox_hwmod = { ++ .name = "mailbox", ++ .class = &omap2420_mailbox_hwmod_class, ++ .mpu_irqs = omap2420_mailbox_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs), ++ .main_clk = "mailboxes_ick", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_mailbox_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ ++/* ++ * 'mcspi' class ++ * multichannel serial port interface (mcspi) / master/slave synchronous serial ++ * bus ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2420_mcspi_class = { ++ .name = "mcspi", ++ .sysc = &omap2420_mcspi_sysc, ++ .rev = OMAP2_MCSPI_REV, ++}; ++ ++/* mcspi1 */ ++static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { ++ { .irq = 65 }, ++}; ++ ++static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ ++ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ ++ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ ++ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ ++ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ ++ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ ++ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ ++ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { ++ &omap2420_l4_core__mcspi1, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { ++ .num_chipselect = 4, ++}; ++ ++static struct omap_hwmod omap2420_mcspi1_hwmod = { ++ .name = "mcspi1_hwmod", ++ .mpu_irqs = omap2420_mcspi1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), ++ .sdma_reqs = omap2420_mcspi1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), ++ .main_clk = "mcspi1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_mcspi1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), ++ .class = &omap2420_mcspi_class, ++ .dev_attr = &omap_mcspi1_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ ++/* mcspi2 */ ++static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { ++ { .irq = 66 }, ++}; ++ ++static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ ++ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ ++ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ ++ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { ++ &omap2420_l4_core__mcspi2, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { ++ .num_chipselect = 2, ++}; ++ ++static struct omap_hwmod omap2420_mcspi2_hwmod = { ++ .name = "mcspi2_hwmod", ++ .mpu_irqs = omap2420_mcspi2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), ++ .sdma_reqs = omap2420_mcspi2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), ++ .main_clk = "mcspi2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_mcspi2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), ++ .class = &omap2420_mcspi_class, ++ .dev_attr = &omap_mcspi2_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ ++/* ++ * 'mcbsp' class ++ * multi channel buffered serial port controller ++ */ ++ ++static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { ++ .name = "mcbsp", ++}; ++ ++/* mcbsp1 */ ++static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { ++ { .name = "tx", .irq = 59 }, ++ { .name = "rx", .irq = 60 }, ++}; ++ ++static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = { ++ { .name = "rx", .dma_req = 32 }, ++ { .name = "tx", .dma_req = 31 }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x48074000, ++ .pa_end = 0x480740ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp1 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_mcbsp1_hwmod, ++ .clk = "mcbsp1_ick", ++ .addr = omap2420_mcbsp1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp1 slave ports */ ++static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { ++ &omap2420_l4_core__mcbsp1, ++}; ++ ++static struct omap_hwmod omap2420_mcbsp1_hwmod = { ++ .name = "mcbsp1", ++ .class = &omap2420_mcbsp_hwmod_class, ++ .mpu_irqs = omap2420_mcbsp1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), ++ .sdma_reqs = omap2420_mcbsp1_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs), ++ .main_clk = "mcbsp1_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_mcbsp1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ ++/* mcbsp2 */ ++static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { ++ { .name = "tx", .irq = 62 }, ++ { .name = "rx", .irq = 63 }, ++}; ++ ++static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = { ++ { .name = "rx", .dma_req = 34 }, ++ { .name = "tx", .dma_req = 33 }, ++}; ++ ++static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x48076000, ++ .pa_end = 0x480760ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp2 */ ++static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { ++ .master = &omap2420_l4_core_hwmod, ++ .slave = &omap2420_mcbsp2_hwmod, ++ .clk = "mcbsp2_ick", ++ .addr = omap2420_mcbsp2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp2 slave ports */ ++static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { ++ &omap2420_l4_core__mcbsp2, ++}; ++ ++static struct omap_hwmod omap2420_mcbsp2_hwmod = { ++ .name = "mcbsp2", ++ .class = &omap2420_mcbsp_hwmod_class, ++ .mpu_irqs = omap2420_mcbsp2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), ++ .sdma_reqs = omap2420_mcbsp2_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs), ++ .main_clk = "mcbsp2_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, ++ }, ++ }, ++ .slaves = omap2420_mcbsp2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), ++}; ++ + static __initdata struct omap_hwmod *omap2420_hwmods[] = { + &omap2420_l3_main_hwmod, + &omap2420_l4_core_hwmod, + &omap2420_l4_wkup_hwmod, + &omap2420_mpu_hwmod, + &omap2420_iva_hwmod, ++ ++ &omap2420_timer1_hwmod, ++ &omap2420_timer2_hwmod, ++ &omap2420_timer3_hwmod, ++ &omap2420_timer4_hwmod, ++ &omap2420_timer5_hwmod, ++ &omap2420_timer6_hwmod, ++ &omap2420_timer7_hwmod, ++ &omap2420_timer8_hwmod, ++ &omap2420_timer9_hwmod, ++ &omap2420_timer10_hwmod, ++ &omap2420_timer11_hwmod, ++ &omap2420_timer12_hwmod, ++ + &omap2420_wd_timer2_hwmod, + &omap2420_uart1_hwmod, + &omap2420_uart2_hwmod, + &omap2420_uart3_hwmod, ++ /* dss class */ ++ &omap2420_dss_core_hwmod, ++ &omap2420_dss_dispc_hwmod, ++ &omap2420_dss_rfbi_hwmod, ++ &omap2420_dss_venc_hwmod, ++ /* i2c class */ + &omap2420_i2c1_hwmod, + &omap2420_i2c2_hwmod, + +@@ -885,10 +2175,21 @@ + + /* dma_system class*/ + &omap2420_dma_system_hwmod, ++ ++ /* mailbox class */ ++ &omap2420_mailbox_hwmod, ++ ++ /* mcbsp class */ ++ &omap2420_mcbsp1_hwmod, ++ &omap2420_mcbsp2_hwmod, ++ ++ /* mcspi class */ ++ &omap2420_mcspi1_hwmod, ++ &omap2420_mcspi2_hwmod, + NULL, + }; + + int __init omap2420_hwmod_init(void) + { +- return omap_hwmod_init(omap2420_hwmods); ++ return omap_hwmod_register(omap2420_hwmods); + } +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2430_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2430_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2430_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2430_data.c 2011-03-09 13:19:09.828507257 +0100 +@@ -18,6 +18,11 @@ + #include + #include + #include ++#include ++#include ++#include ++#include ++#include + + #include "omap_hwmod_common_data.h" + +@@ -38,6 +43,10 @@ + static struct omap_hwmod omap2430_iva_hwmod; + static struct omap_hwmod omap2430_l3_main_hwmod; + static struct omap_hwmod omap2430_l4_core_hwmod; ++static struct omap_hwmod omap2430_dss_core_hwmod; ++static struct omap_hwmod omap2430_dss_dispc_hwmod; ++static struct omap_hwmod omap2430_dss_rfbi_hwmod; ++static struct omap_hwmod omap2430_dss_venc_hwmod; + static struct omap_hwmod omap2430_wd_timer2_hwmod; + static struct omap_hwmod omap2430_gpio1_hwmod; + static struct omap_hwmod omap2430_gpio2_hwmod; +@@ -45,6 +54,16 @@ + static struct omap_hwmod omap2430_gpio4_hwmod; + static struct omap_hwmod omap2430_gpio5_hwmod; + static struct omap_hwmod omap2430_dma_system_hwmod; ++static struct omap_hwmod omap2430_mcbsp1_hwmod; ++static struct omap_hwmod omap2430_mcbsp2_hwmod; ++static struct omap_hwmod omap2430_mcbsp3_hwmod; ++static struct omap_hwmod omap2430_mcbsp4_hwmod; ++static struct omap_hwmod omap2430_mcbsp5_hwmod; ++static struct omap_hwmod omap2430_mcspi1_hwmod; ++static struct omap_hwmod omap2430_mcspi2_hwmod; ++static struct omap_hwmod omap2430_mcspi3_hwmod; ++static struct omap_hwmod omap2430_mmc1_hwmod; ++static struct omap_hwmod omap2430_mmc2_hwmod; + + /* L3 -> L4_CORE interface */ + static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { +@@ -65,6 +84,19 @@ + &omap2430_mpu__l3_main, + }; + ++/* DSS -> l3 */ ++static struct omap_hwmod_ocp_if omap2430_dss__l3 = { ++ .master = &omap2430_dss_core_hwmod, ++ .slave = &omap2430_l3_main_hwmod, ++ .fw = { ++ .omap2 = { ++ .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, ++ .flags = OMAP_FIREWALL_L3, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* Master interfaces on the L3 interconnect */ + static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { + &omap2430_l3_main__l4_core, +@@ -89,6 +121,16 @@ + static struct omap_hwmod omap2430_i2c1_hwmod; + static struct omap_hwmod omap2430_i2c2_hwmod; + ++static struct omap_hwmod omap2430_usbhsotg_hwmod; ++ ++/* l3_core -> usbhsotg interface */ ++static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { ++ .master = &omap2430_usbhsotg_hwmod, ++ .slave = &omap2430_l3_main_hwmod, ++ .clk = "core_l3_ck", ++ .user = OCP_USER_MPU, ++}; ++ + /* I2C IP block address space length (in bytes) */ + #define OMAP2_I2C_AS_LEN 128 + +@@ -189,6 +231,71 @@ + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + ++/* ++* usbhsotg interface data ++*/ ++static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { ++ { ++ .pa_start = OMAP243X_HS_BASE, ++ .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core ->usbhsotg interface */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_usbhsotg_hwmod, ++ .clk = "usb_l4_ick", ++ .addr = omap2430_usbhsotg_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { ++ &omap2430_usbhsotg__l3, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { ++ &omap2430_l4_core__usbhsotg, ++}; ++ ++/* L4 CORE -> MMC1 interface */ ++static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = { ++ { ++ .pa_start = 0x4809c000, ++ .pa_end = 0x4809c1ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mmc1_hwmod, ++ .clk = "mmchs1_ick", ++ .addr = omap2430_mmc1_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* L4 CORE -> MMC2 interface */ ++static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = { ++ { ++ .pa_start = 0x480b4000, ++ .pa_end = 0x480b41ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mmc2_hwmod, ++ .addr = omap2430_mmc2_addr_space, ++ .clk = "mmchs2_ick", ++ .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* Slave interfaces on the L4_CORE interconnect */ + static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { + &omap2430_l3_main__l4_core, +@@ -197,6 +304,8 @@ + /* Master interfaces on the L4_CORE interconnect */ + static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { + &omap2430_l4_core__l4_wkup, ++ &omap2430_l4_core__mmc1, ++ &omap2430_l4_core__mmc2, + }; + + /* L4 CORE */ +@@ -223,6 +332,60 @@ + static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { + }; + ++/* l4 core -> mcspi1 interface */ ++static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = { ++ { ++ .pa_start = 0x48098000, ++ .pa_end = 0x480980ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcspi1_hwmod, ++ .clk = "mcspi1_ick", ++ .addr = omap2430_mcspi1_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4 core -> mcspi2 interface */ ++static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = { ++ { ++ .pa_start = 0x4809a000, ++ .pa_end = 0x4809a0ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcspi2_hwmod, ++ .clk = "mcspi2_ick", ++ .addr = omap2430_mcspi2_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4 core -> mcspi3 interface */ ++static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = { ++ { ++ .pa_start = 0x480b8000, ++ .pa_end = 0x480b80ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcspi3_hwmod, ++ .clk = "mcspi3_ick", ++ .addr = omap2430_mcspi3_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* L4 WKUP */ + static struct omap_hwmod omap2430_l4_wkup_hwmod = { + .name = "l4_wkup", +@@ -278,645 +441,2224 @@ + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-/* l4_wkup -> wd_timer2 */ +-static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { +- { +- .pa_start = 0x49016000, +- .pa_end = 0x4901607f, +- .flags = ADDR_TYPE_RT +- }, ++/* Timer Common */ ++static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { +- .master = &omap2430_l4_wkup_hwmod, +- .slave = &omap2430_wd_timer2_hwmod, +- .clk = "mpu_wdt_ick", +- .addr = omap2430_wd_timer2_addrs, +- .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++static struct omap_hwmod_class omap2430_timer_hwmod_class = { ++ .name = "timer", ++ .sysc = &omap2430_timer_sysc, ++ .rev = OMAP_TIMER_IP_VERSION_1, + }; + +-/* +- * 'wd_timer' class +- * 32-bit watchdog upward counter that generates a pulse on the reset pin on +- * overflow condition +- */ ++/* timer1 */ ++static struct omap_hwmod omap2430_timer1_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = { ++ { .irq = 37, }, ++}; + +-static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { +- .rev_offs = 0x0, +- .sysc_offs = 0x0010, +- .syss_offs = 0x0014, +- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | +- SYSC_HAS_AUTOIDLE), +- .sysc_fields = &omap_hwmod_sysc_type1, ++static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { ++ { ++ .pa_start = 0x49018000, ++ .pa_end = 0x49018000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { +- .name = "wd_timer", +- .sysc = &omap2430_wd_timer_sysc, +- .pre_shutdown = &omap2_wd_timer_disable ++/* l4_wkup -> timer1 */ ++static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { ++ .master = &omap2430_l4_wkup_hwmod, ++ .slave = &omap2430_timer1_hwmod, ++ .clk = "gpt1_ick", ++ .addr = omap2430_timer1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* wd_timer2 */ +-static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { +- &omap2430_l4_wkup__wd_timer2, ++/* timer1 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { ++ &omap2430_l4_wkup__timer1, + }; + +-static struct omap_hwmod omap2430_wd_timer2_hwmod = { +- .name = "wd_timer2", +- .class = &omap2430_wd_timer_hwmod_class, +- .main_clk = "mpu_wdt_fck", ++/* timer1 hwmod */ ++static struct omap_hwmod omap2430_timer1_hwmod = { ++ .name = "timer1", ++ .mpu_irqs = omap2430_timer1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs), ++ .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, ++ .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, ++ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, + }, + }, +- .slaves = omap2430_wd_timer2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +-}; +- +-/* UART */ +- +-static struct omap_hwmod_class_sysconfig uart_sysc = { +- .rev_offs = 0x50, +- .sysc_offs = 0x54, +- .syss_offs = 0x58, +- .sysc_flags = (SYSC_HAS_SIDLEMODE | +- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | +- SYSC_HAS_AUTOIDLE), +- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), +- .sysc_fields = &omap_hwmod_sysc_type1, ++ .slaves = omap2430_timer1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-static struct omap_hwmod_class uart_class = { +- .name = "uart", +- .sysc = &uart_sysc, ++/* timer2 */ ++static struct omap_hwmod omap2430_timer2_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = { ++ { .irq = 38, }, + }; + +-/* UART1 */ +- +-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { +- { .irq = INT_24XX_UART1_IRQ, }, ++static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = { ++ { ++ .pa_start = 0x4802a000, ++ .pa_end = 0x4802a000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, ++/* l4_core -> timer2 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer2_hwmod, ++ .clk = "gpt2_ick", ++ .addr = omap2430_timer2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { +- &omap2_l4_core__uart1, ++/* timer2 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { ++ &omap2430_l4_core__timer2, + }; + +-static struct omap_hwmod omap2430_uart1_hwmod = { +- .name = "uart1", +- .mpu_irqs = uart1_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), +- .sdma_reqs = uart1_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), +- .main_clk = "uart1_fck", ++/* timer2 hwmod */ ++static struct omap_hwmod omap2430_timer2_hwmod = { ++ .name = "timer2", ++ .mpu_irqs = omap2430_timer2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs), ++ .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_UART1_SHIFT, ++ .module_bit = OMAP24XX_EN_GPT2_SHIFT, ++ .module_offs = CORE_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, ++ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, + }, + }, +- .slaves = omap2430_uart1_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), +- .class = &uart_class, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .slaves = omap2430_timer2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-/* UART2 */ ++/* timer3 */ ++static struct omap_hwmod omap2430_timer3_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = { ++ { .irq = 39, }, ++}; + +-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { +- { .irq = INT_24XX_UART2_IRQ, }, ++static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = { ++ { ++ .pa_start = 0x48078000, ++ .pa_end = 0x48078000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, ++/* l4_core -> timer3 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer3_hwmod, ++ .clk = "gpt3_ick", ++ .addr = omap2430_timer3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { +- &omap2_l4_core__uart2, ++/* timer3 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { ++ &omap2430_l4_core__timer3, + }; + +-static struct omap_hwmod omap2430_uart2_hwmod = { +- .name = "uart2", +- .mpu_irqs = uart2_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), +- .sdma_reqs = uart2_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), +- .main_clk = "uart2_fck", ++/* timer3 hwmod */ ++static struct omap_hwmod omap2430_timer3_hwmod = { ++ .name = "timer3", ++ .mpu_irqs = omap2430_timer3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs), ++ .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_UART2_SHIFT, ++ .module_bit = OMAP24XX_EN_GPT3_SHIFT, ++ .module_offs = CORE_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, ++ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + }, + }, +- .slaves = omap2430_uart2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), +- .class = &uart_class, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .slaves = omap2430_timer3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-/* UART3 */ ++/* timer4 */ ++static struct omap_hwmod omap2430_timer4_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = { ++ { .irq = 40, }, ++}; + +-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { +- { .irq = INT_24XX_UART3_IRQ, }, ++static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = { ++ { ++ .pa_start = 0x4807a000, ++ .pa_end = 0x4807a000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, ++/* l4_core -> timer4 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer4_hwmod, ++ .clk = "gpt4_ick", ++ .addr = omap2430_timer4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { +- &omap2_l4_core__uart3, ++/* timer4 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { ++ &omap2430_l4_core__timer4, + }; + +-static struct omap_hwmod omap2430_uart3_hwmod = { +- .name = "uart3", +- .mpu_irqs = uart3_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), +- .sdma_reqs = uart3_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), +- .main_clk = "uart3_fck", ++/* timer4 hwmod */ ++static struct omap_hwmod omap2430_timer4_hwmod = { ++ .name = "timer4", ++ .mpu_irqs = omap2430_timer4_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs), ++ .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, +- .prcm_reg_id = 2, +- .module_bit = OMAP24XX_EN_UART3_SHIFT, +- .idlest_reg_id = 2, +- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, + }, + }, +- .slaves = omap2430_uart3_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), +- .class = &uart_class, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .slaves = omap2430_timer4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-/* I2C common */ +-static struct omap_hwmod_class_sysconfig i2c_sysc = { +- .rev_offs = 0x00, +- .sysc_offs = 0x20, +- .syss_offs = 0x10, +- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), +- .sysc_fields = &omap_hwmod_sysc_type1, ++/* timer5 */ ++static struct omap_hwmod omap2430_timer5_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = { ++ { .irq = 41, }, + }; + +-static struct omap_hwmod_class i2c_class = { +- .name = "i2c", +- .sysc = &i2c_sysc, ++static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = { ++ { ++ .pa_start = 0x4807c000, ++ .pa_end = 0x4807c000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_i2c_dev_attr i2c_dev_attr = { +- .fifo_depth = 8, /* bytes */ ++/* l4_core -> timer5 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer5_hwmod, ++ .clk = "gpt5_ick", ++ .addr = omap2430_timer5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* I2C1 */ +- +-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { +- { .irq = INT_24XX_I2C1_IRQ, }, ++/* timer5 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { ++ &omap2430_l4_core__timer5, + }; + +-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { +- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, +- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, ++/* timer5 hwmod */ ++static struct omap_hwmod omap2430_timer5_hwmod = { ++ .name = "timer5", ++ .mpu_irqs = omap2430_timer5_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs), ++ .main_clk = "gpt5_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT5_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_timer5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { +- &omap2430_l4_core__i2c1, ++/* timer6 */ ++static struct omap_hwmod omap2430_timer6_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = { ++ { .irq = 42, }, + }; + +-static struct omap_hwmod omap2430_i2c1_hwmod = { +- .name = "i2c1", +- .mpu_irqs = i2c1_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), +- .sdma_reqs = i2c1_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), +- .main_clk = "i2chs1_fck", ++static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = { ++ { ++ .pa_start = 0x4807e000, ++ .pa_end = 0x4807e000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer6 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer6_hwmod, ++ .clk = "gpt6_ick", ++ .addr = omap2430_timer6_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer6 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { ++ &omap2430_l4_core__timer6, ++}; ++ ++/* timer6 hwmod */ ++static struct omap_hwmod omap2430_timer6_hwmod = { ++ .name = "timer6", ++ .mpu_irqs = omap2430_timer6_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs), ++ .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { +- /* +- * NOTE: The CM_FCLKEN* and CM_ICLKEN* for +- * I2CHS IP's do not follow the usual pattern. +- * prcm_reg_id alone cannot be used to program +- * the iclk and fclk. Needs to be handled using +- * additonal flags when clk handling is moved +- * to hwmod framework. +- */ +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP2430_EN_I2CHS1_SHIFT, ++ .module_bit = OMAP24XX_EN_GPT6_SHIFT, ++ .module_offs = CORE_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, ++ .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, + }, + }, +- .slaves = omap2430_i2c1_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), +- .class = &i2c_class, +- .dev_attr = &i2c_dev_attr, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .slaves = omap2430_timer6_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-/* I2C2 */ ++/* timer7 */ ++static struct omap_hwmod omap2430_timer7_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = { ++ { .irq = 43, }, ++}; + +-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { +- { .irq = INT_24XX_I2C2_IRQ, }, ++static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = { ++ { ++ .pa_start = 0x48080000, ++ .pa_end = 0x48080000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { +- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, +- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, ++/* l4_core -> timer7 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer7_hwmod, ++ .clk = "gpt7_ick", ++ .addr = omap2430_timer7_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { +- &omap2430_l4_core__i2c2, ++/* timer7 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { ++ &omap2430_l4_core__timer7, + }; + +-static struct omap_hwmod omap2430_i2c2_hwmod = { +- .name = "i2c2", +- .mpu_irqs = i2c2_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), +- .sdma_reqs = i2c2_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), +- .main_clk = "i2chs2_fck", ++/* timer7 hwmod */ ++static struct omap_hwmod omap2430_timer7_hwmod = { ++ .name = "timer7", ++ .mpu_irqs = omap2430_timer7_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs), ++ .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP2430_EN_I2CHS2_SHIFT, ++ .module_bit = OMAP24XX_EN_GPT7_SHIFT, ++ .module_offs = CORE_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, ++ .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + }, + }, +- .slaves = omap2430_i2c2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), +- .class = &i2c_class, +- .dev_attr = &i2c_dev_attr, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .slaves = omap2430_timer7_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }; + +-/* l4_wkup -> gpio1 */ +-static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { ++/* timer8 */ ++static struct omap_hwmod omap2430_timer8_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = { ++ { .irq = 44, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = { + { +- .pa_start = 0x4900C000, +- .pa_end = 0x4900C1ff, ++ .pa_start = 0x48082000, ++ .pa_end = 0x48082000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + }; + +-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { +- .master = &omap2430_l4_wkup_hwmod, +- .slave = &omap2430_gpio1_hwmod, +- .clk = "gpios_ick", +- .addr = omap2430_gpio1_addr_space, +- .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), ++/* l4_core -> timer8 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer8_hwmod, ++ .clk = "gpt8_ick", ++ .addr = omap2430_timer8_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* l4_wkup -> gpio2 */ +-static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { ++/* timer8 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { ++ &omap2430_l4_core__timer8, ++}; ++ ++/* timer8 hwmod */ ++static struct omap_hwmod omap2430_timer8_hwmod = { ++ .name = "timer8", ++ .mpu_irqs = omap2430_timer8_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs), ++ .main_clk = "gpt8_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT8_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_timer8_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) ++}; ++ ++/* timer9 */ ++static struct omap_hwmod omap2430_timer9_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = { ++ { .irq = 45, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = { + { +- .pa_start = 0x4900E000, +- .pa_end = 0x4900E1ff, ++ .pa_start = 0x48084000, ++ .pa_end = 0x48084000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + }; + +-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { +- .master = &omap2430_l4_wkup_hwmod, +- .slave = &omap2430_gpio2_hwmod, +- .clk = "gpios_ick", +- .addr = omap2430_gpio2_addr_space, +- .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), ++/* l4_core -> timer9 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer9_hwmod, ++ .clk = "gpt9_ick", ++ .addr = omap2430_timer9_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* l4_wkup -> gpio3 */ +-static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { ++/* timer9 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { ++ &omap2430_l4_core__timer9, ++}; ++ ++/* timer9 hwmod */ ++static struct omap_hwmod omap2430_timer9_hwmod = { ++ .name = "timer9", ++ .mpu_irqs = omap2430_timer9_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs), ++ .main_clk = "gpt9_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT9_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_timer9_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) ++}; ++ ++/* timer10 */ ++static struct omap_hwmod omap2430_timer10_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = { ++ { .irq = 46, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = { + { +- .pa_start = 0x49010000, +- .pa_end = 0x490101ff, ++ .pa_start = 0x48086000, ++ .pa_end = 0x48086000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + }; + +-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { +- .master = &omap2430_l4_wkup_hwmod, +- .slave = &omap2430_gpio3_hwmod, +- .clk = "gpios_ick", +- .addr = omap2430_gpio3_addr_space, +- .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), ++/* l4_core -> timer10 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer10_hwmod, ++ .clk = "gpt10_ick", ++ .addr = omap2430_timer10_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* l4_wkup -> gpio4 */ +-static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { ++/* timer10 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { ++ &omap2430_l4_core__timer10, ++}; ++ ++/* timer10 hwmod */ ++static struct omap_hwmod omap2430_timer10_hwmod = { ++ .name = "timer10", ++ .mpu_irqs = omap2430_timer10_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs), ++ .main_clk = "gpt10_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT10_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_timer10_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) ++}; ++ ++/* timer11 */ ++static struct omap_hwmod omap2430_timer11_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = { ++ { .irq = 47, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = { + { +- .pa_start = 0x49012000, +- .pa_end = 0x490121ff, ++ .pa_start = 0x48088000, ++ .pa_end = 0x48088000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + }; + +-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { +- .master = &omap2430_l4_wkup_hwmod, +- .slave = &omap2430_gpio4_hwmod, +- .clk = "gpios_ick", +- .addr = omap2430_gpio4_addr_space, +- .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), ++/* l4_core -> timer11 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_timer11_hwmod, ++ .clk = "gpt11_ick", ++ .addr = omap2430_timer11_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* l4_core -> gpio5 */ +-static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { ++/* timer11 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { ++ &omap2430_l4_core__timer11, ++}; ++ ++/* timer11 hwmod */ ++static struct omap_hwmod omap2430_timer11_hwmod = { ++ .name = "timer11", ++ .mpu_irqs = omap2430_timer11_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs), ++ .main_clk = "gpt11_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT11_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_timer11_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) ++}; ++ ++/* timer12 */ ++static struct omap_hwmod omap2430_timer12_hwmod; ++static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = { ++ { .irq = 48, }, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = { + { +- .pa_start = 0x480B6000, +- .pa_end = 0x480B61ff, ++ .pa_start = 0x4808a000, ++ .pa_end = 0x4808a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + }; + +-static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { ++/* l4_core -> timer12 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { + .master = &omap2430_l4_core_hwmod, +- .slave = &omap2430_gpio5_hwmod, +- .clk = "gpio5_ick", +- .addr = omap2430_gpio5_addr_space, +- .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), ++ .slave = &omap2430_timer12_hwmod, ++ .clk = "gpt12_ick", ++ .addr = omap2430_timer12_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer12 slave port */ ++static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { ++ &omap2430_l4_core__timer12, ++}; ++ ++/* timer12 hwmod */ ++static struct omap_hwmod omap2430_timer12_hwmod = { ++ .name = "timer12", ++ .mpu_irqs = omap2430_timer12_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs), ++ .main_clk = "gpt12_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPT12_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_timer12_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), ++ .class = &omap2430_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) ++}; ++ ++/* l4_wkup -> wd_timer2 */ ++static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { ++ { ++ .pa_start = 0x49016000, ++ .pa_end = 0x4901607f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { ++ .master = &omap2430_l4_wkup_hwmod, ++ .slave = &omap2430_wd_timer2_hwmod, ++ .clk = "mpu_wdt_ick", ++ .addr = omap2430_wd_timer2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* gpio dev_attr */ +-static struct omap_gpio_dev_attr gpio_dev_attr = { +- .bank_width = 32, +- .dbck_flag = false, ++/* ++ * 'wd_timer' class ++ * 32-bit watchdog upward counter that generates a pulse on the reset pin on ++ * overflow condition ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { ++ .rev_offs = 0x0, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { ++ .name = "wd_timer", ++ .sysc = &omap2430_wd_timer_sysc, ++ .pre_shutdown = &omap2_wd_timer_disable ++}; ++ ++/* wd_timer2 */ ++static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { ++ &omap2430_l4_wkup__wd_timer2, ++}; ++ ++static struct omap_hwmod omap2430_wd_timer2_hwmod = { ++ .name = "wd_timer2", ++ .class = &omap2430_wd_timer_hwmod_class, ++ .main_clk = "mpu_wdt_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_wd_timer2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* UART */ ++ ++static struct omap_hwmod_class_sysconfig uart_sysc = { ++ .rev_offs = 0x50, ++ .sysc_offs = 0x54, ++ .syss_offs = 0x58, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class uart_class = { ++ .name = "uart", ++ .sysc = &uart_sysc, ++}; ++ ++/* UART1 */ ++ ++static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { ++ { .irq = INT_24XX_UART1_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { ++ &omap2_l4_core__uart1, ++}; ++ ++static struct omap_hwmod omap2430_uart1_hwmod = { ++ .name = "uart1", ++ .mpu_irqs = uart1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), ++ .sdma_reqs = uart1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), ++ .main_clk = "uart1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_UART1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_uart1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* UART2 */ ++ ++static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { ++ { .irq = INT_24XX_UART2_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { ++ &omap2_l4_core__uart2, ++}; ++ ++static struct omap_hwmod omap2430_uart2_hwmod = { ++ .name = "uart2", ++ .mpu_irqs = uart2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), ++ .sdma_reqs = uart2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), ++ .main_clk = "uart2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_UART2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_uart2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* UART3 */ ++ ++static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { ++ { .irq = INT_24XX_UART3_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { ++ &omap2_l4_core__uart3, ++}; ++ ++static struct omap_hwmod omap2430_uart3_hwmod = { ++ .name = "uart3", ++ .mpu_irqs = uart3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), ++ .sdma_reqs = uart3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), ++ .main_clk = "uart3_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 2, ++ .module_bit = OMAP24XX_EN_UART3_SHIFT, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_uart3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* ++ * 'dss' class ++ * display sub-system ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_dss_hwmod_class = { ++ .name = "dss", ++ .sysc = &omap2430_dss_sysc, ++}; ++ ++static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { ++ { .name = "dispc", .dma_req = 5 }, ++}; ++ ++/* dss */ ++/* dss master ports */ ++static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { ++ &omap2430_dss__l3, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_dss_addrs[] = { ++ { ++ .pa_start = 0x48050000, ++ .pa_end = 0x480503FF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_dss_core_hwmod, ++ .clk = "dss_ick", ++ .addr = omap2430_dss_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { ++ &omap2430_l4_core__dss, ++}; ++ ++static struct omap_hwmod_opt_clk dss_opt_clks[] = { ++ { .role = "tv_clk", .clk = "dss_54m_fck" }, ++ { .role = "sys_clk", .clk = "dss2_fck" }, ++}; ++ ++static struct omap_hwmod omap2430_dss_core_hwmod = { ++ .name = "dss_core", ++ .class = &omap2430_dss_hwmod_class, ++ .main_clk = "dss1_fck", /* instead of dss_fck */ ++ .sdma_reqs = omap2430_dss_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, ++ }, ++ }, ++ .opt_clks = dss_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), ++ .slaves = omap2430_dss_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), ++ .masters = omap2430_dss_masters, ++ .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'dispc' class ++ * display controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_dispc_hwmod_class = { ++ .name = "dispc", ++ .sysc = &omap2430_dispc_sysc, ++}; ++ ++static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = { ++ { .irq = 25 }, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { ++ { ++ .pa_start = 0x48050400, ++ .pa_end = 0x480507FF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss_dispc */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_dss_dispc_hwmod, ++ .clk = "dss_ick", ++ .addr = omap2430_dss_dispc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_dispc slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { ++ &omap2430_l4_core__dss_dispc, ++}; ++ ++static struct omap_hwmod omap2430_dss_dispc_hwmod = { ++ .name = "dss_dispc", ++ .class = &omap2430_dispc_hwmod_class, ++ .mpu_irqs = omap2430_dispc_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs), ++ .main_clk = "dss1_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_dss_dispc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'rfbi' class ++ * remote frame buffer interface ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_rfbi_hwmod_class = { ++ .name = "rfbi", ++ .sysc = &omap2430_rfbi_sysc, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = { ++ { ++ .pa_start = 0x48050800, ++ .pa_end = 0x48050BFF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss_rfbi */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_dss_rfbi_hwmod, ++ .clk = "dss_ick", ++ .addr = omap2430_dss_rfbi_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_rfbi slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { ++ &omap2430_l4_core__dss_rfbi, ++}; ++ ++static struct omap_hwmod omap2430_dss_rfbi_hwmod = { ++ .name = "dss_rfbi", ++ .class = &omap2430_rfbi_hwmod_class, ++ .main_clk = "dss1_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, ++ .module_offs = CORE_MOD, ++ }, ++ }, ++ .slaves = omap2430_dss_rfbi_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'venc' class ++ * video encoder ++ */ ++ ++static struct omap_hwmod_class omap2430_venc_hwmod_class = { ++ .name = "venc", ++}; ++ ++/* dss_venc */ ++static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = { ++ { ++ .pa_start = 0x48050C00, ++ .pa_end = 0x48050FFF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss_venc */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_dss_venc_hwmod, ++ .clk = "dss_54m_fck", ++ .addr = omap2430_dss_venc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_venc slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { ++ &omap2430_l4_core__dss_venc, ++}; ++ ++static struct omap_hwmod omap2430_dss_venc_hwmod = { ++ .name = "dss_venc", ++ .class = &omap2430_venc_hwmod_class, ++ .main_clk = "dss1_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_DSS1_SHIFT, ++ .module_offs = CORE_MOD, ++ }, ++ }, ++ .slaves = omap2430_dss_venc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* I2C common */ ++static struct omap_hwmod_class_sysconfig i2c_sysc = { ++ .rev_offs = 0x00, ++ .sysc_offs = 0x20, ++ .syss_offs = 0x10, ++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class i2c_class = { ++ .name = "i2c", ++ .sysc = &i2c_sysc, ++}; ++ ++static struct omap_i2c_dev_attr i2c_dev_attr = { ++ .fifo_depth = 8, /* bytes */ ++}; ++ ++/* I2C1 */ ++ ++static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { ++ { .irq = INT_24XX_I2C1_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { ++ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, ++ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { ++ &omap2430_l4_core__i2c1, ++}; ++ ++static struct omap_hwmod omap2430_i2c1_hwmod = { ++ .name = "i2c1", ++ .mpu_irqs = i2c1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), ++ .sdma_reqs = i2c1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), ++ .main_clk = "i2chs1_fck", ++ .prcm = { ++ .omap2 = { ++ /* ++ * NOTE: The CM_FCLKEN* and CM_ICLKEN* for ++ * I2CHS IP's do not follow the usual pattern. ++ * prcm_reg_id alone cannot be used to program ++ * the iclk and fclk. Needs to be handled using ++ * additonal flags when clk handling is moved ++ * to hwmod framework. ++ */ ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP2430_EN_I2CHS1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_i2c1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), ++ .class = &i2c_class, ++ .dev_attr = &i2c_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* I2C2 */ ++ ++static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { ++ { .irq = INT_24XX_I2C2_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { ++ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, ++ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { ++ &omap2430_l4_core__i2c2, ++}; ++ ++static struct omap_hwmod omap2430_i2c2_hwmod = { ++ .name = "i2c2", ++ .mpu_irqs = i2c2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), ++ .sdma_reqs = i2c2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), ++ .main_clk = "i2chs2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP2430_EN_I2CHS2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_i2c2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), ++ .class = &i2c_class, ++ .dev_attr = &i2c_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* l4_wkup -> gpio1 */ ++static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { ++ { ++ .pa_start = 0x4900C000, ++ .pa_end = 0x4900C1ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { ++ .master = &omap2430_l4_wkup_hwmod, ++ .slave = &omap2430_gpio1_hwmod, ++ .clk = "gpios_ick", ++ .addr = omap2430_gpio1_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4_wkup -> gpio2 */ ++static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { ++ { ++ .pa_start = 0x4900E000, ++ .pa_end = 0x4900E1ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { ++ .master = &omap2430_l4_wkup_hwmod, ++ .slave = &omap2430_gpio2_hwmod, ++ .clk = "gpios_ick", ++ .addr = omap2430_gpio2_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4_wkup -> gpio3 */ ++static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { ++ { ++ .pa_start = 0x49010000, ++ .pa_end = 0x490101ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { ++ .master = &omap2430_l4_wkup_hwmod, ++ .slave = &omap2430_gpio3_hwmod, ++ .clk = "gpios_ick", ++ .addr = omap2430_gpio3_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4_wkup -> gpio4 */ ++static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { ++ { ++ .pa_start = 0x49012000, ++ .pa_end = 0x490121ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { ++ .master = &omap2430_l4_wkup_hwmod, ++ .slave = &omap2430_gpio4_hwmod, ++ .clk = "gpios_ick", ++ .addr = omap2430_gpio4_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4_core -> gpio5 */ ++static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { ++ { ++ .pa_start = 0x480B6000, ++ .pa_end = 0x480B61ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_gpio5_hwmod, ++ .clk = "gpio5_ick", ++ .addr = omap2430_gpio5_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* gpio dev_attr */ ++static struct omap_gpio_dev_attr gpio_dev_attr = { ++ .bank_width = 32, ++ .dbck_flag = false, ++}; ++ ++static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++/* ++ * 'gpio' class ++ * general purpose io module ++ */ ++static struct omap_hwmod_class omap243x_gpio_hwmod_class = { ++ .name = "gpio", ++ .sysc = &omap243x_gpio_sysc, ++ .rev = 0, ++}; ++ ++/* gpio1 */ ++static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { ++ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { ++ &omap2430_l4_wkup__gpio1, ++}; ++ ++static struct omap_hwmod omap2430_gpio1_hwmod = { ++ .name = "gpio1", ++ .mpu_irqs = omap243x_gpio1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), ++ .main_clk = "gpios_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_gpio1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), ++ .class = &omap243x_gpio_hwmod_class, ++ .dev_attr = &gpio_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* gpio2 */ ++static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { ++ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { ++ &omap2430_l4_wkup__gpio2, ++}; ++ ++static struct omap_hwmod omap2430_gpio2_hwmod = { ++ .name = "gpio2", ++ .mpu_irqs = omap243x_gpio2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), ++ .main_clk = "gpios_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_gpio2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), ++ .class = &omap243x_gpio_hwmod_class, ++ .dev_attr = &gpio_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* gpio3 */ ++static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { ++ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { ++ &omap2430_l4_wkup__gpio3, ++}; ++ ++static struct omap_hwmod omap2430_gpio3_hwmod = { ++ .name = "gpio3", ++ .mpu_irqs = omap243x_gpio3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), ++ .main_clk = "gpios_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_gpio3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), ++ .class = &omap243x_gpio_hwmod_class, ++ .dev_attr = &gpio_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* gpio4 */ ++static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { ++ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { ++ &omap2430_l4_wkup__gpio4, ++}; ++ ++static struct omap_hwmod omap2430_gpio4_hwmod = { ++ .name = "gpio4", ++ .mpu_irqs = omap243x_gpio4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), ++ .main_clk = "gpios_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_gpio4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), ++ .class = &omap243x_gpio_hwmod_class, ++ .dev_attr = &gpio_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* gpio5 */ ++static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { ++ { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { ++ &omap2430_l4_core__gpio5, ++}; ++ ++static struct omap_hwmod omap2430_gpio5_hwmod = { ++ .name = "gpio5", ++ .mpu_irqs = omap243x_gpio5_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), ++ .main_clk = "gpio5_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 2, ++ .module_bit = OMAP2430_EN_GPIO5_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_gpio5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), ++ .class = &omap243x_gpio_hwmod_class, ++ .dev_attr = &gpio_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* dma_system */ ++static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x002c, ++ .syss_offs = 0x0028, ++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | ++ SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_dma_hwmod_class = { ++ .name = "dma", ++ .sysc = &omap2430_dma_sysc, ++}; ++ ++/* dma attributes */ ++static struct omap_dma_dev_attr dma_dev_attr = { ++ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | ++ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, ++ .lch_count = 32, ++}; ++ ++static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { ++ { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ ++ { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ ++ { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ ++ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ ++}; ++ ++static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { ++ { ++ .pa_start = 0x48056000, ++ .pa_end = 0x4a0560ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* dma_system -> L3 */ ++static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { ++ .master = &omap2430_dma_system_hwmod, ++ .slave = &omap2430_l3_main_hwmod, ++ .clk = "core_l3_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dma_system master ports */ ++static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { ++ &omap2430_dma_system__l3, ++}; ++ ++/* l4_core -> dma_system */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_dma_system_hwmod, ++ .clk = "sdma_ick", ++ .addr = omap2430_dma_system_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dma_system slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { ++ &omap2430_l4_core__dma_system, ++}; ++ ++static struct omap_hwmod omap2430_dma_system_hwmod = { ++ .name = "dma", ++ .class = &omap2430_dma_hwmod_class, ++ .mpu_irqs = omap2430_dma_system_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), ++ .main_clk = "core_l3_ck", ++ .slaves = omap2430_dma_system_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), ++ .masters = omap2430_dma_system_masters, ++ .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), ++ .dev_attr = &dma_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'mailbox' class ++ * mailbox module allowing communication between the on-chip processors ++ * using a queued mailbox-interrupt mechanism. ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = { ++ .rev_offs = 0x000, ++ .sysc_offs = 0x010, ++ .syss_offs = 0x014, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_mailbox_hwmod_class = { ++ .name = "mailbox", ++ .sysc = &omap2430_mailbox_sysc, ++}; ++ ++/* mailbox */ ++static struct omap_hwmod omap2430_mailbox_hwmod; ++static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { ++ { .irq = 26 }, ++}; ++ ++static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = { ++ { ++ .pa_start = 0x48094000, ++ .pa_end = 0x480941ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++/* l4_core -> mailbox */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mailbox_hwmod, ++ .addr = omap2430_mailbox_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mailbox slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { ++ &omap2430_l4_core__mailbox, ++}; ++ ++static struct omap_hwmod omap2430_mailbox_hwmod = { ++ .name = "mailbox", ++ .class = &omap2430_mailbox_hwmod_class, ++ .mpu_irqs = omap2430_mailbox_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs), ++ .main_clk = "mailboxes_ick", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_mailbox_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* ++ * 'mcspi' class ++ * multichannel serial port interface (mcspi) / master/slave synchronous serial ++ * bus ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_mcspi_class = { ++ .name = "mcspi", ++ .sysc = &omap2430_mcspi_sysc, ++ .rev = OMAP2_MCSPI_REV, ++}; ++ ++/* mcspi1 */ ++static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { ++ { .irq = 65 }, ++}; ++ ++static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ ++ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ ++ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ ++ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ ++ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ ++ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ ++ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ ++ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { ++ &omap2430_l4_core__mcspi1, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { ++ .num_chipselect = 4, ++}; ++ ++static struct omap_hwmod omap2430_mcspi1_hwmod = { ++ .name = "mcspi1_hwmod", ++ .mpu_irqs = omap2430_mcspi1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), ++ .sdma_reqs = omap2430_mcspi1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), ++ .main_clk = "mcspi1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_mcspi1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), ++ .class = &omap2430_mcspi_class, ++ .dev_attr = &omap_mcspi1_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* mcspi2 */ ++static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { ++ { .irq = 66 }, ++}; ++ ++static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ ++ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ ++ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ ++ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { ++ &omap2430_l4_core__mcspi2, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { ++ .num_chipselect = 2, ++}; ++ ++static struct omap_hwmod omap2430_mcspi2_hwmod = { ++ .name = "mcspi2_hwmod", ++ .mpu_irqs = omap2430_mcspi2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), ++ .sdma_reqs = omap2430_mcspi2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), ++ .main_clk = "mcspi2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_mcspi2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), ++ .class = &omap2430_mcspi_class, ++ .dev_attr = &omap_mcspi2_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* mcspi3 */ ++static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { ++ { .irq = 91 }, ++}; ++ ++static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ ++ { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ ++ { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ ++ { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { ++ &omap2430_l4_core__mcspi3, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { ++ .num_chipselect = 2, ++}; ++ ++static struct omap_hwmod omap2430_mcspi3_hwmod = { ++ .name = "mcspi3_hwmod", ++ .mpu_irqs = omap2430_mcspi3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), ++ .sdma_reqs = omap2430_mcspi3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), ++ .main_clk = "mcspi3_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 2, ++ .module_bit = OMAP2430_EN_MCSPI3_SHIFT, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_mcspi3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), ++ .class = &omap2430_mcspi_class, ++ .dev_attr = &omap_mcspi3_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), ++}; ++ ++/* ++ * usbhsotg ++ */ ++static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { ++ .rev_offs = 0x0400, ++ .sysc_offs = 0x0404, ++ .syss_offs = 0x0408, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class usbotg_class = { ++ .name = "usbotg", ++ .sysc = &omap2430_usbhsotg_sysc, ++}; ++ ++/* usb_otg_hs */ ++static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { ++ ++ { .name = "mc", .irq = 92 }, ++ { .name = "dma", .irq = 93 }, ++}; ++ ++static struct omap_hwmod omap2430_usbhsotg_hwmod = { ++ .name = "usb_otg_hs", ++ .mpu_irqs = omap2430_usbhsotg_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs), ++ .main_clk = "usbhs_ick", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP2430_EN_USBHS_MASK, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, ++ }, ++ }, ++ .masters = omap2430_usbhsotg_masters, ++ .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), ++ .slaves = omap2430_usbhsotg_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), ++ .class = &usbotg_class, ++ /* ++ * Erratum ID: i479 idle_req / idle_ack mechanism potentially ++ * broken when autoidle is enabled ++ * workaround is to disable the autoidle bit at module level. ++ */ ++ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE ++ | HWMOD_SWSUP_MSTANDBY, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) ++}; ++ ++/* ++ * 'mcbsp' class ++ * multi channel buffered serial port controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { ++ .rev_offs = 0x007C, ++ .sysc_offs = 0x008C, ++ .sysc_flags = (SYSC_HAS_SOFTRESET), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { ++ .name = "mcbsp", ++ .sysc = &omap2430_mcbsp_sysc, ++ .rev = MCBSP_CONFIG_TYPE2, + }; + +-static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { +- .rev_offs = 0x0000, +- .sysc_offs = 0x0010, +- .syss_offs = 0x0014, +- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | +- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), +- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), +- .sysc_fields = &omap_hwmod_sysc_type1, ++/* mcbsp1 */ ++static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { ++ { .name = "tx", .irq = 59 }, ++ { .name = "rx", .irq = 60 }, ++ { .name = "ovr", .irq = 61 }, ++ { .name = "common", .irq = 64 }, + }; + +-/* +- * 'gpio' class +- * general purpose io module +- */ +-static struct omap_hwmod_class omap243x_gpio_hwmod_class = { +- .name = "gpio", +- .sysc = &omap243x_gpio_sysc, +- .rev = 0, ++static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = { ++ { .name = "rx", .dma_req = 32 }, ++ { .name = "tx", .dma_req = 31 }, + }; + +-/* gpio1 */ +-static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { +- { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ ++static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x48074000, ++ .pa_end = 0x480740ff, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { +- &omap2430_l4_wkup__gpio1, ++/* l4_core -> mcbsp1 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcbsp1_hwmod, ++ .clk = "mcbsp1_ick", ++ .addr = omap2430_mcbsp1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod omap2430_gpio1_hwmod = { +- .name = "gpio1", +- .mpu_irqs = omap243x_gpio1_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), +- .main_clk = "gpios_fck", ++/* mcbsp1 slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { ++ &omap2430_l4_core__mcbsp1, ++}; ++ ++static struct omap_hwmod omap2430_mcbsp1_hwmod = { ++ .name = "mcbsp1", ++ .class = &omap2430_mcbsp_hwmod_class, ++ .mpu_irqs = omap2430_mcbsp1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), ++ .sdma_reqs = omap2430_mcbsp1_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs), ++ .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, +- .module_offs = WKUP_MOD, ++ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, ++ .module_offs = CORE_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, ++ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + }, + }, +- .slaves = omap2430_gpio1_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), +- .class = &omap243x_gpio_hwmod_class, +- .dev_attr = &gpio_dev_attr, ++ .slaves = omap2430_mcbsp1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + }; + +-/* gpio2 */ +-static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { +- { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ ++/* mcbsp2 */ ++static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { ++ { .name = "tx", .irq = 62 }, ++ { .name = "rx", .irq = 63 }, ++ { .name = "common", .irq = 16 }, + }; + +-static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { +- &omap2430_l4_wkup__gpio2, ++static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = { ++ { .name = "rx", .dma_req = 34 }, ++ { .name = "tx", .dma_req = 33 }, + }; + +-static struct omap_hwmod omap2430_gpio2_hwmod = { +- .name = "gpio2", +- .mpu_irqs = omap243x_gpio2_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), +- .main_clk = "gpios_fck", ++static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x48076000, ++ .pa_end = 0x480760ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp2 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcbsp2_hwmod, ++ .clk = "mcbsp2_ick", ++ .addr = omap2430_mcbsp2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp2 slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { ++ &omap2430_l4_core__mcbsp2, ++}; ++ ++static struct omap_hwmod omap2430_mcbsp2_hwmod = { ++ .name = "mcbsp2", ++ .class = &omap2430_mcbsp_hwmod_class, ++ .mpu_irqs = omap2430_mcbsp2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs), ++ .sdma_reqs = omap2430_mcbsp2_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs), ++ .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, +- .module_offs = WKUP_MOD, ++ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, ++ .module_offs = CORE_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, ++ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + }, + }, +- .slaves = omap2430_gpio2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), +- .class = &omap243x_gpio_hwmod_class, +- .dev_attr = &gpio_dev_attr, ++ .slaves = omap2430_mcbsp2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + }; + +-/* gpio3 */ +-static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { +- { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ ++/* mcbsp3 */ ++static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { ++ { .name = "tx", .irq = 89 }, ++ { .name = "rx", .irq = 90 }, ++ { .name = "common", .irq = 17 }, + }; + +-static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { +- &omap2430_l4_wkup__gpio3, ++static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = { ++ { .name = "rx", .dma_req = 18 }, ++ { .name = "tx", .dma_req = 17 }, + }; + +-static struct omap_hwmod omap2430_gpio3_hwmod = { +- .name = "gpio3", +- .mpu_irqs = omap243x_gpio3_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), +- .main_clk = "gpios_fck", ++static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x4808C000, ++ .pa_end = 0x4808C0ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp3 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcbsp3_hwmod, ++ .clk = "mcbsp3_ick", ++ .addr = omap2430_mcbsp3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp3 slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { ++ &omap2430_l4_core__mcbsp3, ++}; ++ ++static struct omap_hwmod omap2430_mcbsp3_hwmod = { ++ .name = "mcbsp3", ++ .class = &omap2430_mcbsp_hwmod_class, ++ .mpu_irqs = omap2430_mcbsp3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs), ++ .sdma_reqs = omap2430_mcbsp3_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs), ++ .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, +- .module_offs = WKUP_MOD, +- .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, ++ .module_bit = OMAP2430_EN_MCBSP3_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, + }, + }, +- .slaves = omap2430_gpio3_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), +- .class = &omap243x_gpio_hwmod_class, +- .dev_attr = &gpio_dev_attr, ++ .slaves = omap2430_mcbsp3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + }; + +-/* gpio4 */ +-static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { +- { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ ++/* mcbsp4 */ ++static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { ++ { .name = "tx", .irq = 54 }, ++ { .name = "rx", .irq = 55 }, ++ { .name = "common", .irq = 18 }, + }; + +-static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { +- &omap2430_l4_wkup__gpio4, ++static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { ++ { .name = "rx", .dma_req = 20 }, ++ { .name = "tx", .dma_req = 19 }, + }; + +-static struct omap_hwmod omap2430_gpio4_hwmod = { +- .name = "gpio4", +- .mpu_irqs = omap243x_gpio4_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), +- .main_clk = "gpios_fck", ++static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x4808E000, ++ .pa_end = 0x4808E0ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp4 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcbsp4_hwmod, ++ .clk = "mcbsp4_ick", ++ .addr = omap2430_mcbsp4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp4 slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { ++ &omap2430_l4_core__mcbsp4, ++}; ++ ++static struct omap_hwmod omap2430_mcbsp4_hwmod = { ++ .name = "mcbsp4", ++ .class = &omap2430_mcbsp_hwmod_class, ++ .mpu_irqs = omap2430_mcbsp4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs), ++ .sdma_reqs = omap2430_mcbsp4_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs), ++ .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, +- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, +- .module_offs = WKUP_MOD, +- .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, ++ .module_bit = OMAP2430_EN_MCBSP4_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, + }, + }, +- .slaves = omap2430_gpio4_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), +- .class = &omap243x_gpio_hwmod_class, +- .dev_attr = &gpio_dev_attr, ++ .slaves = omap2430_mcbsp4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + }; + +-/* gpio5 */ +-static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { +- { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ ++/* mcbsp5 */ ++static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { ++ { .name = "tx", .irq = 81 }, ++ { .name = "rx", .irq = 82 }, ++ { .name = "common", .irq = 19 }, + }; + +-static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { +- &omap2430_l4_core__gpio5, ++static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { ++ { .name = "rx", .dma_req = 22 }, ++ { .name = "tx", .dma_req = 21 }, + }; + +-static struct omap_hwmod omap2430_gpio5_hwmod = { +- .name = "gpio5", +- .mpu_irqs = omap243x_gpio5_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), +- .main_clk = "gpio5_fck", ++static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x48096000, ++ .pa_end = 0x480960ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp5 */ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { ++ .master = &omap2430_l4_core_hwmod, ++ .slave = &omap2430_mcbsp5_hwmod, ++ .clk = "mcbsp5_ick", ++ .addr = omap2430_mcbsp5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp5 slave ports */ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { ++ &omap2430_l4_core__mcbsp5, ++}; ++ ++static struct omap_hwmod omap2430_mcbsp5_hwmod = { ++ .name = "mcbsp5", ++ .class = &omap2430_mcbsp_hwmod_class, ++ .mpu_irqs = omap2430_mcbsp5_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs), ++ .sdma_reqs = omap2430_mcbsp5_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs), ++ .main_clk = "mcbsp5_fck", + .prcm = { + .omap2 = { +- .prcm_reg_id = 2, +- .module_bit = OMAP2430_EN_GPIO5_SHIFT, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP2430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, +- .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, ++ .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, + }, + }, +- .slaves = omap2430_gpio5_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), +- .class = &omap243x_gpio_hwmod_class, +- .dev_attr = &gpio_dev_attr, ++ .slaves = omap2430_mcbsp5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + }; + +-/* dma_system */ +-static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { +- .rev_offs = 0x0000, +- .sysc_offs = 0x002c, +- .syss_offs = 0x0028, +- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | +- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | +- SYSC_HAS_AUTOIDLE), +- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), +- .sysc_fields = &omap_hwmod_sysc_type1, ++/* MMC/SD/SDIO common */ ++ ++static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { ++ .rev_offs = 0x1fc, ++ .sysc_offs = 0x10, ++ .syss_offs = 0x14, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_class omap2430_dma_hwmod_class = { +- .name = "dma", +- .sysc = &omap2430_dma_sysc, ++static struct omap_hwmod_class omap2430_mmc_class = { ++ .name = "mmc", ++ .sysc = &omap2430_mmc_sysc, + }; + +-/* dma attributes */ +-static struct omap_dma_dev_attr dma_dev_attr = { +- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | +- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, +- .lch_count = 32, ++/* MMC/SD/SDIO1 */ ++ ++static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { ++ { .irq = 83 }, + }; + +-static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { +- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ +- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ +- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ +- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ ++static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ ++ { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ + }; + +-static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { +- { +- .pa_start = 0x48056000, +- .pa_end = 0x4a0560ff, +- .flags = ADDR_TYPE_RT ++static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { ++ { .role = "dbck", .clk = "mmchsdb1_fck" }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { ++ &omap2430_l4_core__mmc1, ++}; ++ ++static struct omap_mmc_dev_attr mmc1_dev_attr = { ++ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, ++}; ++ ++static struct omap_hwmod omap2430_mmc1_hwmod = { ++ .name = "mmc1", ++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, ++ .mpu_irqs = omap2430_mmc1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs), ++ .sdma_reqs = omap2430_mmc1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs), ++ .opt_clks = omap2430_mmc1_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), ++ .main_clk = "mmchs1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 2, ++ .module_bit = OMAP2430_EN_MMCHS1_SHIFT, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, ++ }, + }, ++ .dev_attr = &mmc1_dev_attr, ++ .slaves = omap2430_mmc1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), ++ .class = &omap2430_mmc_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + }; + +-/* dma_system -> L3 */ +-static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { +- .master = &omap2430_dma_system_hwmod, +- .slave = &omap2430_l3_main_hwmod, +- .clk = "core_l3_ck", +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++/* MMC/SD/SDIO2 */ ++ ++static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { ++ { .irq = 86 }, + }; + +-/* dma_system master ports */ +-static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { +- &omap2430_dma_system__l3, ++static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ ++ { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ + }; + +-/* l4_core -> dma_system */ +-static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { +- .master = &omap2430_l4_core_hwmod, +- .slave = &omap2430_dma_system_hwmod, +- .clk = "sdma_ick", +- .addr = omap2430_dma_system_addrs, +- .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { ++ { .role = "dbck", .clk = "mmchsdb2_fck" }, + }; + +-/* dma_system slave ports */ +-static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { +- &omap2430_l4_core__dma_system, ++static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { ++ &omap2430_l4_core__mmc2, + }; + +-static struct omap_hwmod omap2430_dma_system_hwmod = { +- .name = "dma", +- .class = &omap2430_dma_hwmod_class, +- .mpu_irqs = omap2430_dma_system_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), +- .main_clk = "core_l3_ck", +- .slaves = omap2430_dma_system_slaves, +- .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), +- .masters = omap2430_dma_system_masters, +- .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), +- .dev_attr = &dma_dev_attr, ++static struct omap_hwmod omap2430_mmc2_hwmod = { ++ .name = "mmc2", ++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, ++ .mpu_irqs = omap2430_mmc2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs), ++ .sdma_reqs = omap2430_mmc2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs), ++ .opt_clks = omap2430_mmc2_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), ++ .main_clk = "mmchs2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 2, ++ .module_bit = OMAP2430_EN_MMCHS2_SHIFT, ++ .idlest_reg_id = 2, ++ .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, ++ }, ++ }, ++ .slaves = omap2430_mmc2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), ++ .class = &omap2430_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +- .flags = HWMOD_NO_IDLEST, + }; + + static __initdata struct omap_hwmod *omap2430_hwmods[] = { +@@ -925,12 +2667,34 @@ + &omap2430_l4_wkup_hwmod, + &omap2430_mpu_hwmod, + &omap2430_iva_hwmod, ++ ++ &omap2430_timer1_hwmod, ++ &omap2430_timer2_hwmod, ++ &omap2430_timer3_hwmod, ++ &omap2430_timer4_hwmod, ++ &omap2430_timer5_hwmod, ++ &omap2430_timer6_hwmod, ++ &omap2430_timer7_hwmod, ++ &omap2430_timer8_hwmod, ++ &omap2430_timer9_hwmod, ++ &omap2430_timer10_hwmod, ++ &omap2430_timer11_hwmod, ++ &omap2430_timer12_hwmod, ++ + &omap2430_wd_timer2_hwmod, + &omap2430_uart1_hwmod, + &omap2430_uart2_hwmod, + &omap2430_uart3_hwmod, ++ /* dss class */ ++ &omap2430_dss_core_hwmod, ++ &omap2430_dss_dispc_hwmod, ++ &omap2430_dss_rfbi_hwmod, ++ &omap2430_dss_venc_hwmod, ++ /* i2c class */ + &omap2430_i2c1_hwmod, + &omap2430_i2c2_hwmod, ++ &omap2430_mmc1_hwmod, ++ &omap2430_mmc2_hwmod, + + /* gpio class */ + &omap2430_gpio1_hwmod, +@@ -941,10 +2705,29 @@ + + /* dma_system class*/ + &omap2430_dma_system_hwmod, ++ ++ /* mcbsp class */ ++ &omap2430_mcbsp1_hwmod, ++ &omap2430_mcbsp2_hwmod, ++ &omap2430_mcbsp3_hwmod, ++ &omap2430_mcbsp4_hwmod, ++ &omap2430_mcbsp5_hwmod, ++ ++ /* mailbox class */ ++ &omap2430_mailbox_hwmod, ++ ++ /* mcspi class */ ++ &omap2430_mcspi1_hwmod, ++ &omap2430_mcspi2_hwmod, ++ &omap2430_mcspi3_hwmod, ++ ++ /* usbotg class*/ ++ &omap2430_usbhsotg_hwmod, ++ + NULL, + }; + + int __init omap2430_hwmod_init(void) + { +- return omap_hwmod_init(omap2430_hwmods); ++ return omap_hwmod_register(omap2430_hwmods); + } +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2011-03-09 13:19:09.829507237 +0100 +@@ -18,16 +18,22 @@ + #include + #include + #include ++#include + #include + #include + #include ++#include + #include ++#include ++#include ++#include + + #include "omap_hwmod_common_data.h" + + #include "prm-regbits-34xx.h" + #include "cm-regbits-34xx.h" + #include "wd_timer.h" ++#include + + /* + * OMAP3xxx hardware module integration data +@@ -44,6 +50,12 @@ + static struct omap_hwmod omap3xxx_l4_core_hwmod; + static struct omap_hwmod omap3xxx_l4_per_hwmod; + static struct omap_hwmod omap3xxx_wd_timer2_hwmod; ++static struct omap_hwmod omap3430es1_dss_core_hwmod; ++static struct omap_hwmod omap3xxx_dss_core_hwmod; ++static struct omap_hwmod omap3xxx_dss_dispc_hwmod; ++static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; ++static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; ++static struct omap_hwmod omap3xxx_dss_venc_hwmod; + static struct omap_hwmod omap3xxx_i2c1_hwmod; + static struct omap_hwmod omap3xxx_i2c2_hwmod; + static struct omap_hwmod omap3xxx_i2c3_hwmod; +@@ -55,9 +67,25 @@ + static struct omap_hwmod omap3xxx_gpio6_hwmod; + static struct omap_hwmod omap34xx_sr1_hwmod; + static struct omap_hwmod omap34xx_sr2_hwmod; ++static struct omap_hwmod omap34xx_mcspi1; ++static struct omap_hwmod omap34xx_mcspi2; ++static struct omap_hwmod omap34xx_mcspi3; ++static struct omap_hwmod omap34xx_mcspi4; ++static struct omap_hwmod omap3xxx_mmc1_hwmod; ++static struct omap_hwmod omap3xxx_mmc2_hwmod; ++static struct omap_hwmod omap3xxx_mmc3_hwmod; ++static struct omap_hwmod am35xx_usbhsotg_hwmod; + + static struct omap_hwmod omap3xxx_dma_system_hwmod; + ++static struct omap_hwmod omap3xxx_mcbsp1_hwmod; ++static struct omap_hwmod omap3xxx_mcbsp2_hwmod; ++static struct omap_hwmod omap3xxx_mcbsp3_hwmod; ++static struct omap_hwmod omap3xxx_mcbsp4_hwmod; ++static struct omap_hwmod omap3xxx_mcbsp5_hwmod; ++static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; ++static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; ++ + /* L3 -> L4_CORE interface */ + static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { + .master = &omap3xxx_l3_main_hwmod, +@@ -84,6 +112,19 @@ + &omap3xxx_mpu__l3_main, + }; + ++/* DSS -> l3 */ ++static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { ++ .master = &omap3xxx_dss_core_hwmod, ++ .slave = &omap3xxx_l3_main_hwmod, ++ .fw = { ++ .omap2 = { ++ .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, ++ .flags = OMAP_FIREWALL_L3, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* Master interfaces on the L3 interconnect */ + static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { + &omap3xxx_l3_main__l4_core, +@@ -107,7 +148,23 @@ + static struct omap_hwmod omap3xxx_uart2_hwmod; + static struct omap_hwmod omap3xxx_uart3_hwmod; + static struct omap_hwmod omap3xxx_uart4_hwmod; ++static struct omap_hwmod omap3xxx_usbhsotg_hwmod; ++ ++/* l3_core -> usbhsotg interface */ ++static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { ++ .master = &omap3xxx_usbhsotg_hwmod, ++ .slave = &omap3xxx_l3_main_hwmod, ++ .clk = "core_l3_ick", ++ .user = OCP_USER_MPU, ++}; + ++/* l3_core -> am35xx_usbhsotg interface */ ++static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { ++ .master = &am35xx_usbhsotg_hwmod, ++ .slave = &omap3xxx_l3_main_hwmod, ++ .clk = "core_l3_ick", ++ .user = OCP_USER_MPU, ++}; + /* L4_CORE -> L4_WKUP interface */ + static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { + .master = &omap3xxx_l4_core_hwmod, +@@ -115,6 +172,63 @@ + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + ++/* L4 CORE -> MMC1 interface */ ++static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = { ++ { ++ .pa_start = 0x4809c000, ++ .pa_end = 0x4809c1ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_mmc1_hwmod, ++ .clk = "mmchs1_ick", ++ .addr = omap3xxx_mmc1_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++ .flags = OMAP_FIREWALL_L4 ++}; ++ ++/* L4 CORE -> MMC2 interface */ ++static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = { ++ { ++ .pa_start = 0x480b4000, ++ .pa_end = 0x480b41ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_mmc2_hwmod, ++ .clk = "mmchs2_ick", ++ .addr = omap3xxx_mmc2_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++ .flags = OMAP_FIREWALL_L4 ++}; ++ ++/* L4 CORE -> MMC3 interface */ ++static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { ++ { ++ .pa_start = 0x480ad000, ++ .pa_end = 0x480ad1ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_mmc3_hwmod, ++ .clk = "mmchs3_ick", ++ .addr = omap3xxx_mmc3_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++ .flags = OMAP_FIREWALL_L4 ++}; ++ + /* L4 CORE -> UART1 interface */ + static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { + { +@@ -301,6 +415,61 @@ + .user = OCP_USER_MPU, + }; + ++/* ++* usbhsotg interface data ++*/ ++ ++static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { ++ { ++ .pa_start = OMAP34XX_HSUSB_OTG_BASE, ++ .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> usbhsotg */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_usbhsotg_hwmod, ++ .clk = "l4_ick", ++ .addr = omap3xxx_usbhsotg_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { ++ &omap3xxx_usbhsotg__l3, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { ++ &omap3xxx_l4_core__usbhsotg, ++}; ++ ++static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { ++ { ++ .pa_start = AM35XX_IPSS_USBOTGSS_BASE, ++ .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> usbhsotg */ ++static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &am35xx_usbhsotg_hwmod, ++ .clk = "l4_ick", ++ .addr = am35xx_usbhsotg_addrs, ++ .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { ++ &am35xx_usbhsotg__l3, ++}; ++ ++static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { ++ &am35xx_l4_core__usbhsotg, ++}; + /* Slave interfaces on the L4_CORE interconnect */ + static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { + &omap3xxx_l3_main__l4_core, +@@ -417,251 +586,1292 @@ + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }; + +-/* l4_wkup -> wd_timer2 */ +-static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { +- { +- .pa_start = 0x48314000, +- .pa_end = 0x4831407f, +- .flags = ADDR_TYPE_RT +- }, ++/* timer class */ ++static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { +- .master = &omap3xxx_l4_wkup_hwmod, +- .slave = &omap3xxx_wd_timer2_hwmod, +- .clk = "wdt2_ick", +- .addr = omap3xxx_wd_timer2_addrs, +- .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { ++ .name = "timer", ++ .sysc = &omap3xxx_timer_1ms_sysc, ++ .rev = OMAP_TIMER_IP_VERSION_1, + }; + +-/* +- * 'wd_timer' class +- * 32-bit watchdog upward counter that generates a pulse on the reset pin on +- * overflow condition +- */ +- +-static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { ++static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, +- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | +- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | +- SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), +- .sysc_fields = &omap_hwmod_sysc_type1, ++ .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-/* I2C common */ +-static struct omap_hwmod_class_sysconfig i2c_sysc = { +- .rev_offs = 0x00, +- .sysc_offs = 0x20, +- .syss_offs = 0x10, +- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | +- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | +- SYSC_HAS_AUTOIDLE), +- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), +- .sysc_fields = &omap_hwmod_sysc_type1, ++static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { ++ .name = "timer", ++ .sysc = &omap3xxx_timer_sysc, ++ .rev = OMAP_TIMER_IP_VERSION_1, + }; + +-static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { +- .name = "wd_timer", +- .sysc = &omap3xxx_wd_timer_sysc, +- .pre_shutdown = &omap2_wd_timer_disable ++/* timer1 */ ++static struct omap_hwmod omap3xxx_timer1_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = { ++ { .irq = 37, }, + }; + +-/* wd_timer2 */ +-static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { +- &omap3xxx_l4_wkup__wd_timer2, ++static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { ++ { ++ .pa_start = 0x48318000, ++ .pa_end = 0x48318000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { +- .name = "wd_timer2", +- .class = &omap3xxx_wd_timer_hwmod_class, +- .main_clk = "wdt2_fck", ++/* l4_wkup -> timer1 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { ++ .master = &omap3xxx_l4_wkup_hwmod, ++ .slave = &omap3xxx_timer1_hwmod, ++ .clk = "gpt1_ick", ++ .addr = omap3xxx_timer1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer1 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { ++ &omap3xxx_l4_wkup__timer1, ++}; ++ ++/* timer1 hwmod */ ++static struct omap_hwmod omap3xxx_timer1_hwmod = { ++ .name = "timer1", ++ .mpu_irqs = omap3xxx_timer1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs), ++ .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, +- .module_bit = OMAP3430_EN_WDT2_SHIFT, ++ .module_bit = OMAP3430_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, ++ .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, + }, + }, +- .slaves = omap3xxx_wd_timer2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +-}; +- +-/* UART common */ +- +-static struct omap_hwmod_class_sysconfig uart_sysc = { +- .rev_offs = 0x50, +- .sysc_offs = 0x54, +- .syss_offs = 0x58, +- .sysc_flags = (SYSC_HAS_SIDLEMODE | +- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | +- SYSC_HAS_AUTOIDLE), +- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), +- .sysc_fields = &omap_hwmod_sysc_type1, ++ .slaves = omap3xxx_timer1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), ++ .class = &omap3xxx_timer_1ms_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }; + +-static struct omap_hwmod_class uart_class = { +- .name = "uart", +- .sysc = &uart_sysc, ++/* timer2 */ ++static struct omap_hwmod omap3xxx_timer2_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = { ++ { .irq = 38, }, + }; + +-/* UART1 */ +- +-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { +- { .irq = INT_24XX_UART1_IRQ, }, ++static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { ++ { ++ .pa_start = 0x49032000, ++ .pa_end = 0x49032000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, ++/* l4_per -> timer2 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer2_hwmod, ++ .clk = "gpt2_ick", ++ .addr = omap3xxx_timer2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { +- &omap3_l4_core__uart1, ++/* timer2 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { ++ &omap3xxx_l4_per__timer2, + }; + +-static struct omap_hwmod omap3xxx_uart1_hwmod = { +- .name = "uart1", +- .mpu_irqs = uart1_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), +- .sdma_reqs = uart1_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), +- .main_clk = "uart1_fck", ++/* timer2 hwmod */ ++static struct omap_hwmod omap3xxx_timer2_hwmod = { ++ .name = "timer2", ++ .mpu_irqs = omap3xxx_timer2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs), ++ .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP3430_EN_UART1_SHIFT, ++ .module_bit = OMAP3430_EN_GPT2_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, ++ .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, + }, + }, +- .slaves = omap3xxx_uart1_slaves, +- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), +- .class = &uart_class, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .slaves = omap3xxx_timer2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), ++ .class = &omap3xxx_timer_1ms_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }; + +-/* UART2 */ ++/* timer3 */ ++static struct omap_hwmod omap3xxx_timer3_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = { ++ { .irq = 39, }, ++}; + +-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { +- { .irq = INT_24XX_UART2_IRQ, }, ++static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { ++ { ++ .pa_start = 0x49034000, ++ .pa_end = 0x49034000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, ++/* l4_per -> timer3 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer3_hwmod, ++ .clk = "gpt3_ick", ++ .addr = omap3xxx_timer3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { +- &omap3_l4_core__uart2, ++/* timer3 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { ++ &omap3xxx_l4_per__timer3, + }; + +-static struct omap_hwmod omap3xxx_uart2_hwmod = { +- .name = "uart2", +- .mpu_irqs = uart2_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), +- .sdma_reqs = uart2_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), +- .main_clk = "uart2_fck", ++/* timer3 hwmod */ ++static struct omap_hwmod omap3xxx_timer3_hwmod = { ++ .name = "timer3", ++ .mpu_irqs = omap3xxx_timer3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs), ++ .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { +- .module_offs = CORE_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP3430_EN_UART2_SHIFT, ++ .module_bit = OMAP3430_EN_GPT3_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, ++ .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, + }, + }, +- .slaves = omap3xxx_uart2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), +- .class = &uart_class, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .slaves = omap3xxx_timer3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }; + +-/* UART3 */ ++/* timer4 */ ++static struct omap_hwmod omap3xxx_timer4_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = { ++ { .irq = 40, }, ++}; + +-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { +- { .irq = INT_24XX_UART3_IRQ, }, ++static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { ++ { ++ .pa_start = 0x49036000, ++ .pa_end = 0x49036000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { +- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, +- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, ++/* l4_per -> timer4 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer4_hwmod, ++ .clk = "gpt4_ick", ++ .addr = omap3xxx_timer4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { +- &omap3_l4_per__uart3, ++/* timer4 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { ++ &omap3xxx_l4_per__timer4, + }; + +-static struct omap_hwmod omap3xxx_uart3_hwmod = { +- .name = "uart3", +- .mpu_irqs = uart3_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), +- .sdma_reqs = uart3_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), +- .main_clk = "uart3_fck", ++/* timer4 hwmod */ ++static struct omap_hwmod omap3xxx_timer4_hwmod = { ++ .name = "timer4", ++ .mpu_irqs = omap3xxx_timer4_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs), ++ .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { +- .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP3430_EN_UART3_SHIFT, ++ .module_bit = OMAP3430_EN_GPT4_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, ++ .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, + }, + }, +- .slaves = omap3xxx_uart3_slaves, +- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), +- .class = &uart_class, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .slaves = omap3xxx_timer4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }; + +-/* UART4 */ ++/* timer5 */ ++static struct omap_hwmod omap3xxx_timer5_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = { ++ { .irq = 41, }, ++}; + +-static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { +- { .irq = INT_36XX_UART4_IRQ, }, ++static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { ++ { ++ .pa_start = 0x49038000, ++ .pa_end = 0x49038000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { +- { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, ++/* l4_per -> timer5 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer5_hwmod, ++ .clk = "gpt5_ick", ++ .addr = omap3xxx_timer5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer5 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { ++ &omap3xxx_l4_per__timer5, ++}; ++ ++/* timer5 hwmod */ ++static struct omap_hwmod omap3xxx_timer5_hwmod = { ++ .name = "timer5", ++ .mpu_irqs = omap3xxx_timer5_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs), ++ .main_clk = "gpt5_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT5_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* timer6 */ ++static struct omap_hwmod omap3xxx_timer6_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = { ++ { .irq = 42, }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { ++ { ++ .pa_start = 0x4903A000, ++ .pa_end = 0x4903A000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> timer6 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer6_hwmod, ++ .clk = "gpt6_ick", ++ .addr = omap3xxx_timer6_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer6 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { ++ &omap3xxx_l4_per__timer6, ++}; ++ ++/* timer6 hwmod */ ++static struct omap_hwmod omap3xxx_timer6_hwmod = { ++ .name = "timer6", ++ .mpu_irqs = omap3xxx_timer6_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs), ++ .main_clk = "gpt6_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT6_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer6_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* timer7 */ ++static struct omap_hwmod omap3xxx_timer7_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = { ++ { .irq = 43, }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { ++ { ++ .pa_start = 0x4903C000, ++ .pa_end = 0x4903C000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> timer7 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer7_hwmod, ++ .clk = "gpt7_ick", ++ .addr = omap3xxx_timer7_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer7 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { ++ &omap3xxx_l4_per__timer7, ++}; ++ ++/* timer7 hwmod */ ++static struct omap_hwmod omap3xxx_timer7_hwmod = { ++ .name = "timer7", ++ .mpu_irqs = omap3xxx_timer7_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs), ++ .main_clk = "gpt7_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT7_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer7_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* timer8 */ ++static struct omap_hwmod omap3xxx_timer8_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = { ++ { .irq = 44, }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { ++ { ++ .pa_start = 0x4903E000, ++ .pa_end = 0x4903E000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> timer8 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer8_hwmod, ++ .clk = "gpt8_ick", ++ .addr = omap3xxx_timer8_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer8 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { ++ &omap3xxx_l4_per__timer8, ++}; ++ ++/* timer8 hwmod */ ++static struct omap_hwmod omap3xxx_timer8_hwmod = { ++ .name = "timer8", ++ .mpu_irqs = omap3xxx_timer8_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs), ++ .main_clk = "gpt8_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT8_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer8_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* timer9 */ ++static struct omap_hwmod omap3xxx_timer9_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = { ++ { .irq = 45, }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { ++ { ++ .pa_start = 0x49040000, ++ .pa_end = 0x49040000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> timer9 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_timer9_hwmod, ++ .clk = "gpt9_ick", ++ .addr = omap3xxx_timer9_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer9 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { ++ &omap3xxx_l4_per__timer9, ++}; ++ ++/* timer9 hwmod */ ++static struct omap_hwmod omap3xxx_timer9_hwmod = { ++ .name = "timer9", ++ .mpu_irqs = omap3xxx_timer9_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs), ++ .main_clk = "gpt9_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT9_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer9_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* timer10 */ ++static struct omap_hwmod omap3xxx_timer10_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = { ++ { .irq = 46, }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = { ++ { ++ .pa_start = 0x48086000, ++ .pa_end = 0x48086000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer10 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_timer10_hwmod, ++ .clk = "gpt10_ick", ++ .addr = omap3xxx_timer10_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer10 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { ++ &omap3xxx_l4_core__timer10, ++}; ++ ++/* timer10 hwmod */ ++static struct omap_hwmod omap3xxx_timer10_hwmod = { ++ .name = "timer10", ++ .mpu_irqs = omap3xxx_timer10_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs), ++ .main_clk = "gpt10_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT10_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer10_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), ++ .class = &omap3xxx_timer_1ms_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* timer11 */ ++static struct omap_hwmod omap3xxx_timer11_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = { ++ { .irq = 47, }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = { ++ { ++ .pa_start = 0x48088000, ++ .pa_end = 0x48088000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer11 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_timer11_hwmod, ++ .clk = "gpt11_ick", ++ .addr = omap3xxx_timer11_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer11 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { ++ &omap3xxx_l4_core__timer11, ++}; ++ ++/* timer11 hwmod */ ++static struct omap_hwmod omap3xxx_timer11_hwmod = { ++ .name = "timer11", ++ .mpu_irqs = omap3xxx_timer11_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs), ++ .main_clk = "gpt11_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT11_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer11_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* timer12*/ ++static struct omap_hwmod omap3xxx_timer12_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { ++ { .irq = 95, }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { ++ { ++ .pa_start = 0x48304000, ++ .pa_end = 0x48304000 + SZ_1K - 1, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> timer12 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_timer12_hwmod, ++ .clk = "gpt12_ick", ++ .addr = omap3xxx_timer12_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* timer12 slave port */ ++static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { ++ &omap3xxx_l4_core__timer12, ++}; ++ ++/* timer12 hwmod */ ++static struct omap_hwmod omap3xxx_timer12_hwmod = { ++ .name = "timer12", ++ .mpu_irqs = omap3xxx_timer12_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs), ++ .main_clk = "gpt12_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_GPT12_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_timer12_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), ++ .class = &omap3xxx_timer_hwmod_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* l4_wkup -> wd_timer2 */ ++static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { ++ { ++ .pa_start = 0x48314000, ++ .pa_end = 0x4831407f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { ++ .master = &omap3xxx_l4_wkup_hwmod, ++ .slave = &omap3xxx_wd_timer2_hwmod, ++ .clk = "wdt2_ick", ++ .addr = omap3xxx_wd_timer2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* ++ * 'wd_timer' class ++ * 32-bit watchdog upward counter that generates a pulse on the reset pin on ++ * overflow condition ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++/* I2C common */ ++static struct omap_hwmod_class_sysconfig i2c_sysc = { ++ .rev_offs = 0x00, ++ .sysc_offs = 0x20, ++ .syss_offs = 0x10, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { ++ .name = "wd_timer", ++ .sysc = &omap3xxx_wd_timer_sysc, ++ .pre_shutdown = &omap2_wd_timer_disable ++}; ++ ++/* wd_timer2 */ ++static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { ++ &omap3xxx_l4_wkup__wd_timer2, ++}; ++ ++static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { ++ .name = "wd_timer2", ++ .class = &omap3xxx_wd_timer_hwmod_class, ++ .main_clk = "wdt2_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_WDT2_SHIFT, ++ .module_offs = WKUP_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_wd_timer2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* UART common */ ++ ++static struct omap_hwmod_class_sysconfig uart_sysc = { ++ .rev_offs = 0x50, ++ .sysc_offs = 0x54, ++ .syss_offs = 0x58, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class uart_class = { ++ .name = "uart", ++ .sysc = &uart_sysc, ++}; ++ ++/* UART1 */ ++ ++static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { ++ { .irq = INT_24XX_UART1_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { ++ &omap3_l4_core__uart1, ++}; ++ ++static struct omap_hwmod omap3xxx_uart1_hwmod = { ++ .name = "uart1", ++ .mpu_irqs = uart1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), ++ .sdma_reqs = uart1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), ++ .main_clk = "uart1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_UART1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_uart1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* UART2 */ ++ ++static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { ++ { .irq = INT_24XX_UART2_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { ++ &omap3_l4_core__uart2, ++}; ++ ++static struct omap_hwmod omap3xxx_uart2_hwmod = { ++ .name = "uart2", ++ .mpu_irqs = uart2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), ++ .sdma_reqs = uart2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), ++ .main_clk = "uart2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_UART2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_uart2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* UART3 */ ++ ++static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { ++ { .irq = INT_24XX_UART3_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { ++ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, ++ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { ++ &omap3_l4_per__uart3, ++}; ++ ++static struct omap_hwmod omap3xxx_uart3_hwmod = { ++ .name = "uart3", ++ .mpu_irqs = uart3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), ++ .sdma_reqs = uart3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), ++ .main_clk = "uart3_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = OMAP3430_PER_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_UART3_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_uart3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* UART4 */ ++ ++static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { ++ { .irq = INT_36XX_UART4_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { ++ { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, + }; + +-static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { +- &omap3_l4_per__uart4, ++static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { ++ &omap3_l4_per__uart4, ++}; ++ ++static struct omap_hwmod omap3xxx_uart4_hwmod = { ++ .name = "uart4", ++ .mpu_irqs = uart4_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), ++ .sdma_reqs = uart4_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), ++ .main_clk = "uart4_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = OMAP3430_PER_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3630_EN_UART4_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_uart4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), ++ .class = &uart_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), ++}; ++ ++static struct omap_hwmod_class i2c_class = { ++ .name = "i2c", ++ .sysc = &i2c_sysc, ++}; ++ ++/* ++ * 'dss' class ++ * display sub-system ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { ++ .name = "dss", ++ .sysc = &omap3xxx_dss_sysc, ++}; ++ ++static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { ++ { .name = "dispc", .dma_req = 5 }, ++ { .name = "dsi1", .dma_req = 74 }, ++}; ++ ++/* dss */ ++/* dss master ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { ++ &omap3xxx_dss__l3, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = { ++ { ++ .pa_start = 0x48050000, ++ .pa_end = 0x480503FF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss */ ++static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3430es1_dss_core_hwmod, ++ .clk = "dss_ick", ++ .addr = omap3xxx_dss_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, ++ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_dss_core_hwmod, ++ .clk = "dss_ick", ++ .addr = omap3xxx_dss_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, ++ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss slave ports */ ++static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { ++ &omap3430es1_l4_core__dss, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { ++ &omap3xxx_l4_core__dss, ++}; ++ ++static struct omap_hwmod_opt_clk dss_opt_clks[] = { ++ { .role = "tv_clk", .clk = "dss_tv_fck" }, ++ { .role = "video_clk", .clk = "dss_96m_fck" }, ++ { .role = "sys_clk", .clk = "dss2_alwon_fck" }, ++}; ++ ++static struct omap_hwmod omap3430es1_dss_core_hwmod = { ++ .name = "dss_core", ++ .class = &omap3xxx_dss_hwmod_class, ++ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ ++ .sdma_reqs = omap3xxx_dss_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), ++ ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_DSS1_SHIFT, ++ .module_offs = OMAP3430_DSS_MOD, ++ .idlest_reg_id = 1, ++ .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, ++ }, ++ }, ++ .opt_clks = dss_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), ++ .slaves = omap3430es1_dss_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), ++ .masters = omap3xxx_dss_masters, ++ .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++static struct omap_hwmod omap3xxx_dss_core_hwmod = { ++ .name = "dss_core", ++ .class = &omap3xxx_dss_hwmod_class, ++ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ ++ .sdma_reqs = omap3xxx_dss_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), ++ ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_DSS1_SHIFT, ++ .module_offs = OMAP3430_DSS_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, ++ .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, ++ }, ++ }, ++ .opt_clks = dss_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), ++ .slaves = omap3xxx_dss_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), ++ .masters = omap3xxx_dss_masters, ++ .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | ++ CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), ++}; ++ ++/* ++ * 'dispc' class ++ * display controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { ++ .name = "dispc", ++ .sysc = &omap3xxx_dispc_sysc, ++}; ++ ++static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = { ++ { .irq = 25 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { ++ { ++ .pa_start = 0x48050400, ++ .pa_end = 0x480507FF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss_dispc */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_dss_dispc_hwmod, ++ .clk = "dss_ick", ++ .addr = omap3xxx_dss_dispc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, ++ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_dispc slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { ++ &omap3xxx_l4_core__dss_dispc, ++}; ++ ++static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { ++ .name = "dss_dispc", ++ .class = &omap3xxx_dispc_hwmod_class, ++ .mpu_irqs = omap3xxx_dispc_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs), ++ .main_clk = "dss1_alwon_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_DSS1_SHIFT, ++ .module_offs = OMAP3430_DSS_MOD, ++ }, ++ }, ++ .slaves = omap3xxx_dss_dispc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | ++ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | ++ CHIP_GE_OMAP3630ES1_1), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'dsi' class ++ * display serial interface controller ++ */ ++ ++static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { ++ .name = "dsi", ++}; ++ ++static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { ++ { .irq = 25 }, ++}; ++ ++/* dss_dsi1 */ ++static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { ++ { ++ .pa_start = 0x4804FC00, ++ .pa_end = 0x4804FFFF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss_dsi1 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_dss_dsi1_hwmod, ++ .addr = omap3xxx_dss_dsi1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, ++ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_dsi1 slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { ++ &omap3xxx_l4_core__dss_dsi1, ++}; ++ ++static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { ++ .name = "dss_dsi1", ++ .class = &omap3xxx_dsi_hwmod_class, ++ .mpu_irqs = omap3xxx_dsi1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs), ++ .main_clk = "dss1_alwon_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_DSS1_SHIFT, ++ .module_offs = OMAP3430_DSS_MOD, ++ }, ++ }, ++ .slaves = omap3xxx_dss_dsi1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | ++ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | ++ CHIP_GE_OMAP3630ES1_1), ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'rfbi' class ++ * remote frame buffer interface ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = { ++ .name = "rfbi", ++ .sysc = &omap3xxx_rfbi_sysc, + }; + +-static struct omap_hwmod omap3xxx_uart4_hwmod = { +- .name = "uart4", +- .mpu_irqs = uart4_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), +- .sdma_reqs = uart4_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), +- .main_clk = "uart4_fck", ++static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = { ++ { ++ .pa_start = 0x48050800, ++ .pa_end = 0x48050BFF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss_rfbi */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_dss_rfbi_hwmod, ++ .clk = "dss_ick", ++ .addr = omap3xxx_dss_rfbi_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, ++ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_rfbi slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { ++ &omap3xxx_l4_core__dss_rfbi, ++}; ++ ++static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { ++ .name = "dss_rfbi", ++ .class = &omap3xxx_rfbi_hwmod_class, ++ .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { +- .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, +- .module_bit = OMAP3630_EN_UART4_SHIFT, +- .idlest_reg_id = 1, +- .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, ++ .module_bit = OMAP3430_EN_DSS1_SHIFT, ++ .module_offs = OMAP3430_DSS_MOD, + }, + }, +- .slaves = omap3xxx_uart4_slaves, +- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), +- .class = &uart_class, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), ++ .slaves = omap3xxx_dss_rfbi_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | ++ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | ++ CHIP_GE_OMAP3630ES1_1), ++ .flags = HWMOD_NO_IDLEST, + }; + +-static struct omap_hwmod_class i2c_class = { +- .name = "i2c", +- .sysc = &i2c_sysc, ++/* ++ * 'venc' class ++ * video encoder ++ */ ++ ++static struct omap_hwmod_class omap3xxx_venc_hwmod_class = { ++ .name = "venc", ++}; ++ ++/* dss_venc */ ++static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = { ++ { ++ .pa_start = 0x48050C00, ++ .pa_end = 0x48050FFF, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> dss_venc */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_dss_venc_hwmod, ++ .clk = "dss_tv_fck", ++ .addr = omap3xxx_dss_venc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs), ++ .fw = { ++ .omap2 = { ++ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, ++ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, ++ .flags = OMAP_FIREWALL_L4, ++ } ++ }, ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* dss_venc slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { ++ &omap3xxx_l4_core__dss_venc, ++}; ++ ++static struct omap_hwmod omap3xxx_dss_venc_hwmod = { ++ .name = "dss_venc", ++ .class = &omap3xxx_venc_hwmod_class, ++ .main_clk = "dss1_alwon_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_DSS1_SHIFT, ++ .module_offs = OMAP3430_DSS_MOD, ++ }, ++ }, ++ .slaves = omap3xxx_dss_venc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | ++ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | ++ CHIP_GE_OMAP3630ES1_1), ++ .flags = HWMOD_NO_IDLEST, + }; + + /* I2C1 */ +@@ -1224,9 +2434,440 @@ + .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +- .flags = HWMOD_NO_IDLEST, ++ .flags = HWMOD_NO_IDLEST, ++}; ++ ++/* ++ * 'mcbsp' class ++ * multi channel buffered serial port controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { ++ .sysc_offs = 0x008c, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++ .clockact = 0x2, ++}; ++ ++static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { ++ .name = "mcbsp", ++ .sysc = &omap3xxx_mcbsp_sysc, ++ .rev = MCBSP_CONFIG_TYPE3, ++}; ++ ++/* mcbsp1 */ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { ++ { .name = "irq", .irq = 16 }, ++ { .name = "tx", .irq = 59 }, ++ { .name = "rx", .irq = 60 }, ++}; ++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = { ++ { .name = "rx", .dma_req = 32 }, ++ { .name = "tx", .dma_req = 31 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x48074000, ++ .pa_end = 0x480740ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp1 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_mcbsp1_hwmod, ++ .clk = "mcbsp1_ick", ++ .addr = omap3xxx_mcbsp1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp1 slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { ++ &omap3xxx_l4_core__mcbsp1, ++}; ++ ++static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { ++ .name = "mcbsp1", ++ .class = &omap3xxx_mcbsp_hwmod_class, ++ .mpu_irqs = omap3xxx_mcbsp1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), ++ .sdma_reqs = omap3xxx_mcbsp1_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs), ++ .main_clk = "mcbsp1_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCBSP1_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mcbsp1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* mcbsp2 */ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { ++ { .name = "irq", .irq = 17 }, ++ { .name = "tx", .irq = 62 }, ++ { .name = "rx", .irq = 63 }, ++}; ++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = { ++ { .name = "rx", .dma_req = 34 }, ++ { .name = "tx", .dma_req = 33 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x49022000, ++ .pa_end = 0x490220ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcbsp2 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_mcbsp2_hwmod, ++ .clk = "mcbsp2_ick", ++ .addr = omap3xxx_mcbsp2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp2 slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { ++ &omap3xxx_l4_per__mcbsp2, ++}; ++ ++static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { ++ .sidetone = "mcbsp2_sidetone", ++}; ++ ++static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { ++ .name = "mcbsp2", ++ .class = &omap3xxx_mcbsp_hwmod_class, ++ .mpu_irqs = omap3xxx_mcbsp2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), ++ .sdma_reqs = omap3xxx_mcbsp2_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs), ++ .main_clk = "mcbsp2_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCBSP2_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mcbsp2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), ++ .dev_attr = &omap34xx_mcbsp2_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* mcbsp3 */ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { ++ { .name = "irq", .irq = 22 }, ++ { .name = "tx", .irq = 89 }, ++ { .name = "rx", .irq = 90 }, ++}; ++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = { ++ { .name = "rx", .dma_req = 18 }, ++ { .name = "tx", .dma_req = 17 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x49024000, ++ .pa_end = 0x490240ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcbsp3 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_mcbsp3_hwmod, ++ .clk = "mcbsp3_ick", ++ .addr = omap3xxx_mcbsp3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp3 slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { ++ &omap3xxx_l4_per__mcbsp3, ++}; ++ ++static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { ++ .sidetone = "mcbsp3_sidetone", ++}; ++ ++static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { ++ .name = "mcbsp3", ++ .class = &omap3xxx_mcbsp_hwmod_class, ++ .mpu_irqs = omap3xxx_mcbsp3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), ++ .sdma_reqs = omap3xxx_mcbsp3_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs), ++ .main_clk = "mcbsp3_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCBSP3_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mcbsp3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), ++ .dev_attr = &omap34xx_mcbsp3_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* mcbsp4 */ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { ++ { .name = "irq", .irq = 23 }, ++ { .name = "tx", .irq = 54 }, ++ { .name = "rx", .irq = 55 }, ++}; ++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { ++ { .name = "rx", .dma_req = 20 }, ++ { .name = "tx", .dma_req = 19 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x49026000, ++ .pa_end = 0x490260ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcbsp4 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_mcbsp4_hwmod, ++ .clk = "mcbsp4_ick", ++ .addr = omap3xxx_mcbsp4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp4 slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { ++ &omap3xxx_l4_per__mcbsp4, ++}; ++ ++static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { ++ .name = "mcbsp4", ++ .class = &omap3xxx_mcbsp_hwmod_class, ++ .mpu_irqs = omap3xxx_mcbsp4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs), ++ .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs), ++ .main_clk = "mcbsp4_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCBSP4_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mcbsp4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* mcbsp5 */ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { ++ { .name = "irq", .irq = 27 }, ++ { .name = "tx", .irq = 81 }, ++ { .name = "rx", .irq = 82 }, ++}; ++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { ++ { .name = "rx", .dma_req = 22 }, ++ { .name = "tx", .dma_req = 21 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x48096000, ++ .pa_end = 0x480960ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_core -> mcbsp5 */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_mcbsp5_hwmod, ++ .clk = "mcbsp5_ick", ++ .addr = omap3xxx_mcbsp5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp5 slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { ++ &omap3xxx_l4_core__mcbsp5, ++}; ++ ++static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { ++ .name = "mcbsp5", ++ .class = &omap3xxx_mcbsp_hwmod_class, ++ .mpu_irqs = omap3xxx_mcbsp5_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs), ++ .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs), ++ .main_clk = "mcbsp5_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCBSP5_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mcbsp5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++/* 'mcbsp sidetone' class */ ++ ++static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { ++ .sysc_offs = 0x0010, ++ .sysc_flags = SYSC_HAS_AUTOIDLE, ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { ++ .name = "mcbsp_sidetone", ++ .sysc = &omap3xxx_mcbsp_sidetone_sysc, ++}; ++ ++/* mcbsp2_sidetone */ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { ++ { .name = "irq", .irq = 4 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { ++ { ++ .name = "sidetone", ++ .pa_start = 0x49028000, ++ .pa_end = 0x490280ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcbsp2_sidetone */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_mcbsp2_sidetone_hwmod, ++ .clk = "mcbsp2_ick", ++ .addr = omap3xxx_mcbsp2_sidetone_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++/* mcbsp2_sidetone slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { ++ &omap3xxx_l4_per__mcbsp2_sidetone, ++}; ++ ++static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { ++ .name = "mcbsp2_sidetone", ++ .class = &omap3xxx_mcbsp_sidetone_hwmod_class, ++ .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs), ++ .main_clk = "mcbsp2_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCBSP2_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mcbsp2_sidetone_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* mcbsp3_sidetone */ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { ++ { .name = "irq", .irq = 5 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { ++ { ++ .name = "sidetone", ++ .pa_start = 0x4902A000, ++ .pa_end = 0x4902A0ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcbsp3_sidetone */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { ++ .master = &omap3xxx_l4_per_hwmod, ++ .slave = &omap3xxx_mcbsp3_sidetone_hwmod, ++ .clk = "mcbsp3_ick", ++ .addr = omap3xxx_mcbsp3_sidetone_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++/* mcbsp3_sidetone slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { ++ &omap3xxx_l4_per__mcbsp3_sidetone, ++}; ++ ++static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { ++ .name = "mcbsp3_sidetone", ++ .class = &omap3xxx_mcbsp_sidetone_hwmod_class, ++ .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs), ++ .main_clk = "mcbsp3_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCBSP3_SHIFT, ++ .module_offs = OMAP3430_PER_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mcbsp3_sidetone_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + }; + ++ + /* SR common */ + static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { + .clkact_shift = 20, +@@ -1356,18 +2997,617 @@ + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), + }; + ++/* ++ * 'mailbox' class ++ * mailbox module allowing communication between the on-chip processors ++ * using a queued mailbox-interrupt mechanism. ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { ++ .rev_offs = 0x000, ++ .sysc_offs = 0x010, ++ .syss_offs = 0x014, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { ++ .name = "mailbox", ++ .sysc = &omap3xxx_mailbox_sysc, ++}; ++ ++static struct omap_hwmod omap3xxx_mailbox_hwmod; ++static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { ++ { .irq = 26 }, ++}; ++ ++static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { ++ { ++ .pa_start = 0x48094000, ++ .pa_end = 0x480941ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++/* l4_core -> mailbox */ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap3xxx_mailbox_hwmod, ++ .addr = omap3xxx_mailbox_addrs, ++ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mailbox slave ports */ ++static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { ++ &omap3xxx_l4_core__mailbox, ++}; ++ ++static struct omap_hwmod omap3xxx_mailbox_hwmod = { ++ .name = "mailbox", ++ .class = &omap3xxx_mailbox_hwmod_class, ++ .mpu_irqs = omap3xxx_mailbox_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs), ++ .main_clk = "mailboxes_ick", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mailbox_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* l4 core -> mcspi1 interface */ ++static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { ++ { ++ .pa_start = 0x48098000, ++ .pa_end = 0x480980ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap34xx_mcspi1, ++ .clk = "mcspi1_ick", ++ .addr = omap34xx_mcspi1_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4 core -> mcspi2 interface */ ++static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = { ++ { ++ .pa_start = 0x4809a000, ++ .pa_end = 0x4809a0ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap34xx_mcspi2, ++ .clk = "mcspi2_ick", ++ .addr = omap34xx_mcspi2_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4 core -> mcspi3 interface */ ++static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = { ++ { ++ .pa_start = 0x480b8000, ++ .pa_end = 0x480b80ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap34xx_mcspi3, ++ .clk = "mcspi3_ick", ++ .addr = omap34xx_mcspi3_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* l4 core -> mcspi4 interface */ ++static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { ++ { ++ .pa_start = 0x480ba000, ++ .pa_end = 0x480ba0ff, ++ .flags = ADDR_TYPE_RT, ++ }, ++}; ++ ++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { ++ .master = &omap3xxx_l4_core_hwmod, ++ .slave = &omap34xx_mcspi4, ++ .clk = "mcspi4_ick", ++ .addr = omap34xx_mcspi4_addr_space, ++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* ++ * 'mcspi' class ++ * multichannel serial port interface (mcspi) / master/slave synchronous serial ++ * bus ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap34xx_mcspi_class = { ++ .name = "mcspi", ++ .sysc = &omap34xx_mcspi_sysc, ++ .rev = OMAP3_MCSPI_REV, ++}; ++ ++/* mcspi1 */ ++static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = { ++ { .name = "irq", .irq = 65 }, ++}; ++ ++static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 35 }, ++ { .name = "rx0", .dma_req = 36 }, ++ { .name = "tx1", .dma_req = 37 }, ++ { .name = "rx1", .dma_req = 38 }, ++ { .name = "tx2", .dma_req = 39 }, ++ { .name = "rx2", .dma_req = 40 }, ++ { .name = "tx3", .dma_req = 41 }, ++ { .name = "rx3", .dma_req = 42 }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { ++ &omap34xx_l4_core__mcspi1, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { ++ .num_chipselect = 4, ++}; ++ ++static struct omap_hwmod omap34xx_mcspi1 = { ++ .name = "mcspi1", ++ .mpu_irqs = omap34xx_mcspi1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), ++ .sdma_reqs = omap34xx_mcspi1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs), ++ .main_clk = "mcspi1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCSPI1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, ++ }, ++ }, ++ .slaves = omap34xx_mcspi1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), ++ .class = &omap34xx_mcspi_class, ++ .dev_attr = &omap_mcspi1_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* mcspi2 */ ++static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = { ++ { .name = "irq", .irq = 66 }, ++}; ++ ++static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 43 }, ++ { .name = "rx0", .dma_req = 44 }, ++ { .name = "tx1", .dma_req = 45 }, ++ { .name = "rx1", .dma_req = 46 }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { ++ &omap34xx_l4_core__mcspi2, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { ++ .num_chipselect = 2, ++}; ++ ++static struct omap_hwmod omap34xx_mcspi2 = { ++ .name = "mcspi2", ++ .mpu_irqs = omap34xx_mcspi2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), ++ .sdma_reqs = omap34xx_mcspi2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs), ++ .main_clk = "mcspi2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCSPI2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, ++ }, ++ }, ++ .slaves = omap34xx_mcspi2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), ++ .class = &omap34xx_mcspi_class, ++ .dev_attr = &omap_mcspi2_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* mcspi3 */ ++static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { ++ { .name = "irq", .irq = 91 }, /* 91 */ ++}; ++ ++static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 15 }, ++ { .name = "rx0", .dma_req = 16 }, ++ { .name = "tx1", .dma_req = 23 }, ++ { .name = "rx1", .dma_req = 24 }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { ++ &omap34xx_l4_core__mcspi3, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { ++ .num_chipselect = 2, ++}; ++ ++static struct omap_hwmod omap34xx_mcspi3 = { ++ .name = "mcspi3", ++ .mpu_irqs = omap34xx_mcspi3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs), ++ .sdma_reqs = omap34xx_mcspi3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs), ++ .main_clk = "mcspi3_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCSPI3_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, ++ }, ++ }, ++ .slaves = omap34xx_mcspi3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), ++ .class = &omap34xx_mcspi_class, ++ .dev_attr = &omap_mcspi3_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* SPI4 */ ++static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { ++ { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ ++}; ++ ++static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ ++ { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ ++}; ++ ++static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { ++ &omap34xx_l4_core__mcspi4, ++}; ++ ++static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { ++ .num_chipselect = 1, ++}; ++ ++static struct omap_hwmod omap34xx_mcspi4 = { ++ .name = "mcspi4", ++ .mpu_irqs = omap34xx_mcspi4_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs), ++ .sdma_reqs = omap34xx_mcspi4_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs), ++ .main_clk = "mcspi4_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MCSPI4_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, ++ }, ++ }, ++ .slaves = omap34xx_mcspi4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), ++ .class = &omap34xx_mcspi_class, ++ .dev_attr = &omap_mcspi4_dev_attr, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* ++ * usbhsotg ++ */ ++static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { ++ .rev_offs = 0x0400, ++ .sysc_offs = 0x0404, ++ .syss_offs = 0x0408, ++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class usbotg_class = { ++ .name = "usbotg", ++ .sysc = &omap3xxx_usbhsotg_sysc, ++}; ++/* usb_otg_hs */ ++static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { ++ ++ { .name = "mc", .irq = 92 }, ++ { .name = "dma", .irq = 93 }, ++}; ++ ++static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { ++ .name = "usb_otg_hs", ++ .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs), ++ .main_clk = "hsotgusb_ick", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, ++ .module_offs = CORE_MOD, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, ++ .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT ++ }, ++ }, ++ .masters = omap3xxx_usbhsotg_masters, ++ .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), ++ .slaves = omap3xxx_usbhsotg_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), ++ .class = &usbotg_class, ++ ++ /* ++ * Erratum ID: i479 idle_req / idle_ack mechanism potentially ++ * broken when autoidle is enabled ++ * workaround is to disable the autoidle bit at module level. ++ */ ++ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE ++ | HWMOD_SWSUP_MSTANDBY, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) ++}; ++ ++/* usb_otg_hs */ ++static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { ++ ++ { .name = "mc", .irq = 71 }, ++}; ++ ++static struct omap_hwmod_class am35xx_usbotg_class = { ++ .name = "am35xx_usbotg", ++ .sysc = NULL, ++}; ++ ++static struct omap_hwmod am35xx_usbhsotg_hwmod = { ++ .name = "am35x_otg_hs", ++ .mpu_irqs = am35xx_usbhsotg_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs), ++ .main_clk = NULL, ++ .prcm = { ++ .omap2 = { ++ }, ++ }, ++ .masters = am35xx_usbhsotg_masters, ++ .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), ++ .slaves = am35xx_usbhsotg_slaves, ++ .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), ++ .class = &am35xx_usbotg_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) ++}; ++ ++/* MMC/SD/SDIO common */ ++ ++static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { ++ .rev_offs = 0x1fc, ++ .sysc_offs = 0x10, ++ .syss_offs = 0x14, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap34xx_mmc_class = { ++ .name = "mmc", ++ .sysc = &omap34xx_mmc_sysc, ++}; ++ ++/* MMC/SD/SDIO1 */ ++ ++static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { ++ { .irq = 83, }, ++}; ++ ++static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 61, }, ++ { .name = "rx", .dma_req = 62, }, ++}; ++ ++static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { ++ { .role = "dbck", .clk = "omap_32k_fck", }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { ++ &omap3xxx_l4_core__mmc1, ++}; ++ ++static struct omap_mmc_dev_attr mmc1_dev_attr = { ++ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, ++}; ++ ++static struct omap_hwmod omap3xxx_mmc1_hwmod = { ++ .name = "mmc1", ++ .mpu_irqs = omap34xx_mmc1_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs), ++ .sdma_reqs = omap34xx_mmc1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs), ++ .opt_clks = omap34xx_mmc1_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), ++ .main_clk = "mmchs1_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MMC1_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, ++ }, ++ }, ++ .dev_attr = &mmc1_dev_attr, ++ .slaves = omap3xxx_mmc1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), ++ .class = &omap34xx_mmc_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* MMC/SD/SDIO2 */ ++ ++static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { ++ { .irq = INT_24XX_MMC2_IRQ, }, ++}; ++ ++static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 47, }, ++ { .name = "rx", .dma_req = 48, }, ++}; ++ ++static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { ++ { .role = "dbck", .clk = "omap_32k_fck", }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { ++ &omap3xxx_l4_core__mmc2, ++}; ++ ++static struct omap_hwmod omap3xxx_mmc2_hwmod = { ++ .name = "mmc2", ++ .mpu_irqs = omap34xx_mmc2_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs), ++ .sdma_reqs = omap34xx_mmc2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs), ++ .opt_clks = omap34xx_mmc2_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), ++ .main_clk = "mmchs2_fck", ++ .prcm = { ++ .omap2 = { ++ .module_offs = CORE_MOD, ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MMC2_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mmc2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), ++ .class = &omap34xx_mmc_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ ++/* MMC/SD/SDIO3 */ ++ ++static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { ++ { .irq = 94, }, ++}; ++ ++static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 77, }, ++ { .name = "rx", .dma_req = 78, }, ++}; ++ ++static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { ++ { .role = "dbck", .clk = "omap_32k_fck", }, ++}; ++ ++static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { ++ &omap3xxx_l4_core__mmc3, ++}; ++ ++static struct omap_hwmod omap3xxx_mmc3_hwmod = { ++ .name = "mmc3", ++ .mpu_irqs = omap34xx_mmc3_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs), ++ .sdma_reqs = omap34xx_mmc3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs), ++ .opt_clks = omap34xx_mmc3_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), ++ .main_clk = "mmchs3_fck", ++ .prcm = { ++ .omap2 = { ++ .prcm_reg_id = 1, ++ .module_bit = OMAP3430_EN_MMC3_SHIFT, ++ .idlest_reg_id = 1, ++ .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, ++ }, ++ }, ++ .slaves = omap3xxx_mmc3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), ++ .class = &omap34xx_mmc_class, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++}; ++ + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { + &omap3xxx_l3_main_hwmod, + &omap3xxx_l4_core_hwmod, + &omap3xxx_l4_per_hwmod, + &omap3xxx_l4_wkup_hwmod, ++ &omap3xxx_mmc1_hwmod, ++ &omap3xxx_mmc2_hwmod, ++ &omap3xxx_mmc3_hwmod, + &omap3xxx_mpu_hwmod, + &omap3xxx_iva_hwmod, ++ ++ &omap3xxx_timer1_hwmod, ++ &omap3xxx_timer2_hwmod, ++ &omap3xxx_timer3_hwmod, ++ &omap3xxx_timer4_hwmod, ++ &omap3xxx_timer5_hwmod, ++ &omap3xxx_timer6_hwmod, ++ &omap3xxx_timer7_hwmod, ++ &omap3xxx_timer8_hwmod, ++ &omap3xxx_timer9_hwmod, ++ &omap3xxx_timer10_hwmod, ++ &omap3xxx_timer11_hwmod, ++ &omap3xxx_timer12_hwmod, ++ + &omap3xxx_wd_timer2_hwmod, + &omap3xxx_uart1_hwmod, + &omap3xxx_uart2_hwmod, + &omap3xxx_uart3_hwmod, + &omap3xxx_uart4_hwmod, ++ /* dss class */ ++ &omap3430es1_dss_core_hwmod, ++ &omap3xxx_dss_core_hwmod, ++ &omap3xxx_dss_dispc_hwmod, ++ &omap3xxx_dss_dsi1_hwmod, ++ &omap3xxx_dss_rfbi_hwmod, ++ &omap3xxx_dss_venc_hwmod, ++ ++ /* i2c class */ + &omap3xxx_i2c1_hwmod, + &omap3xxx_i2c2_hwmod, + &omap3xxx_i2c3_hwmod, +@@ -1387,10 +3627,35 @@ + + /* dma_system class*/ + &omap3xxx_dma_system_hwmod, ++ ++ /* mcbsp class */ ++ &omap3xxx_mcbsp1_hwmod, ++ &omap3xxx_mcbsp2_hwmod, ++ &omap3xxx_mcbsp3_hwmod, ++ &omap3xxx_mcbsp4_hwmod, ++ &omap3xxx_mcbsp5_hwmod, ++ &omap3xxx_mcbsp2_sidetone_hwmod, ++ &omap3xxx_mcbsp3_sidetone_hwmod, ++ ++ /* mailbox class */ ++ &omap3xxx_mailbox_hwmod, ++ ++ /* mcspi class */ ++ &omap34xx_mcspi1, ++ &omap34xx_mcspi2, ++ &omap34xx_mcspi3, ++ &omap34xx_mcspi4, ++ ++ /* usbotg class */ ++ &omap3xxx_usbhsotg_hwmod, ++ ++ /* usbotg for am35x */ ++ &am35xx_usbhsotg_hwmod, ++ + NULL, + }; + + int __init omap3xxx_hwmod_init(void) + { +- return omap_hwmod_init(omap3xxx_hwmods); ++ return omap_hwmod_register(omap3xxx_hwmods); + } +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_44xx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2011-03-09 13:19:09.830507217 +0100 +@@ -1,7 +1,7 @@ + /* + * Hardware modules present on the OMAP44xx chips + * +- * Copyright (C) 2009-2010 Texas Instruments, Inc. ++ * Copyright (C) 2009-2011 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley +@@ -24,6 +24,9 @@ + #include + #include + #include ++#include ++#include ++#include + + #include "omap_hwmod_common_data.h" + +@@ -40,10 +43,15 @@ + #define OMAP44XX_DMA_REQ_START 1 + + /* Backward references (IPs with Bus Master capability) */ ++static struct omap_hwmod omap44xx_aess_hwmod; + static struct omap_hwmod omap44xx_dma_system_hwmod; + static struct omap_hwmod omap44xx_dmm_hwmod; + static struct omap_hwmod omap44xx_dsp_hwmod; ++static struct omap_hwmod omap44xx_dss_hwmod; + static struct omap_hwmod omap44xx_emif_fw_hwmod; ++static struct omap_hwmod omap44xx_hsi_hwmod; ++static struct omap_hwmod omap44xx_ipu_hwmod; ++static struct omap_hwmod omap44xx_iss_hwmod; + static struct omap_hwmod omap44xx_iva_hwmod; + static struct omap_hwmod omap44xx_l3_instr_hwmod; + static struct omap_hwmod omap44xx_l3_main_1_hwmod; +@@ -53,8 +61,11 @@ + static struct omap_hwmod omap44xx_l4_cfg_hwmod; + static struct omap_hwmod omap44xx_l4_per_hwmod; + static struct omap_hwmod omap44xx_l4_wkup_hwmod; ++static struct omap_hwmod omap44xx_mmc1_hwmod; ++static struct omap_hwmod omap44xx_mmc2_hwmod; + static struct omap_hwmod omap44xx_mpu_hwmod; + static struct omap_hwmod omap44xx_mpu_private_hwmod; ++static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; + + /* + * Interconnects omap_hwmod structures +@@ -213,6 +224,14 @@ + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + ++/* dss -> l3_main_1 */ ++static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { ++ .master = &omap44xx_dss_hwmod, ++ .slave = &omap44xx_l3_main_1_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* l3_main_2 -> l3_main_1 */ + static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { + .master = &omap44xx_l3_main_2_hwmod, +@@ -229,6 +248,22 @@ + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + ++/* mmc1 -> l3_main_1 */ ++static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { ++ .master = &omap44xx_mmc1_hwmod, ++ .slave = &omap44xx_l3_main_1_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mmc2 -> l3_main_1 */ ++static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { ++ .master = &omap44xx_mmc2_hwmod, ++ .slave = &omap44xx_l3_main_1_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* mpu -> l3_main_1 */ + static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { + .master = &omap44xx_mpu_hwmod, +@@ -240,8 +275,11 @@ + /* l3_main_1 slave ports */ + static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { + &omap44xx_dsp__l3_main_1, ++ &omap44xx_dss__l3_main_1, + &omap44xx_l3_main_2__l3_main_1, + &omap44xx_l4_cfg__l3_main_1, ++ &omap44xx_mmc1__l3_main_1, ++ &omap44xx_mmc2__l3_main_1, + &omap44xx_mpu__l3_main_1, + }; + +@@ -262,6 +300,30 @@ + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + ++/* hsi -> l3_main_2 */ ++static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { ++ .master = &omap44xx_hsi_hwmod, ++ .slave = &omap44xx_l3_main_2_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* ipu -> l3_main_2 */ ++static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { ++ .master = &omap44xx_ipu_hwmod, ++ .slave = &omap44xx_l3_main_2_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* iss -> l3_main_2 */ ++static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { ++ .master = &omap44xx_iss_hwmod, ++ .slave = &omap44xx_l3_main_2_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* iva -> l3_main_2 */ + static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { + .master = &omap44xx_iva_hwmod, +@@ -286,12 +348,24 @@ + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + ++/* usb_otg_hs -> l3_main_2 */ ++static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { ++ .master = &omap44xx_usb_otg_hs_hwmod, ++ .slave = &omap44xx_l3_main_2_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* l3_main_2 slave ports */ + static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { + &omap44xx_dma_system__l3_main_2, ++ &omap44xx_hsi__l3_main_2, ++ &omap44xx_ipu__l3_main_2, ++ &omap44xx_iss__l3_main_2, + &omap44xx_iva__l3_main_2, + &omap44xx_l3_main_1__l3_main_2, + &omap44xx_l4_cfg__l3_main_2, ++ &omap44xx_usb_otg_hs__l3_main_2, + }; + + static struct omap_hwmod omap44xx_l3_main_2_hwmod = { +@@ -351,6 +425,14 @@ + }; + + /* l4_abe interface data */ ++/* aess -> l4_abe */ ++static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { ++ .master = &omap44xx_aess_hwmod, ++ .slave = &omap44xx_l4_abe_hwmod, ++ .clk = "ocp_abe_iclk", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ + /* dsp -> l4_abe */ + static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { + .master = &omap44xx_dsp_hwmod, +@@ -377,6 +459,7 @@ + + /* l4_abe slave ports */ + static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { ++ &omap44xx_aess__l4_abe, + &omap44xx_dsp__l4_abe, + &omap44xx_l3_main_1__l4_abe, + &omap44xx_mpu__l4_abe, +@@ -494,26 +577,15 @@ + * - They still need to be validated with the driver + * properly adapted to omap_hwmod / omap_device + * +- * aess +- * bandgap + * c2c + * c2c_target_fw + * cm_core + * cm_core_aon +- * counter_32k + * ctrl_module_core + * ctrl_module_pad_core + * ctrl_module_pad_wkup + * ctrl_module_wkup + * debugss +- * dmic +- * dss +- * dss_dispc +- * dss_dsi1 +- * dss_dsi2 +- * dss_hdmi +- * dss_rfbi +- * dss_venc + * efuse_ctrl_cust + * efuse_ctrl_std + * elm +@@ -524,58 +596,211 @@ + * gpu + * hdq1w + * hsi +- * ipu +- * iss +- * kbd +- * mailbox +- * mcasp +- * mcbsp1 +- * mcbsp2 +- * mcbsp3 +- * mcbsp4 +- * mcpdm +- * mcspi1 +- * mcspi2 +- * mcspi3 +- * mcspi4 +- * mmc1 +- * mmc2 +- * mmc3 +- * mmc4 +- * mmc5 +- * mpu_c0 +- * mpu_c1 + * ocmc_ram + * ocp2scp_usb_phy + * ocp_wp_noc +- * prcm + * prcm_mpu + * prm + * scrm + * sl2if + * slimbus1 + * slimbus2 +- * spinlock +- * timer1 +- * timer10 +- * timer11 +- * timer2 +- * timer3 +- * timer4 +- * timer5 +- * timer6 +- * timer7 +- * timer8 +- * timer9 + * usb_host_fs + * usb_host_hs +- * usb_otg_hs + * usb_phy_cm + * usb_tll_hs + * usim + */ + + /* ++ * 'aess' class ++ * audio engine sub system ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type2, ++}; ++ ++static struct omap_hwmod_class omap44xx_aess_hwmod_class = { ++ .name = "aess", ++ .sysc = &omap44xx_aess_sysc, ++}; ++ ++/* aess */ ++static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { ++ { .irq = 99 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { ++ { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, ++ { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, ++ { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, ++ { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, ++ { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, ++ { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, ++ { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, ++ { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++/* aess master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { ++ &omap44xx_aess__l4_abe, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { ++ { ++ .pa_start = 0x401f1000, ++ .pa_end = 0x401f13ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> aess */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_aess_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_aess_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { ++ { ++ .pa_start = 0x490f1000, ++ .pa_end = 0x490f13ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> aess (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_aess_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_aess_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++/* aess slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { ++ &omap44xx_l4_abe__aess, ++ &omap44xx_l4_abe__aess_dma, ++}; ++ ++static struct omap_hwmod omap44xx_aess_hwmod = { ++ .name = "aess", ++ .class = &omap44xx_aess_hwmod_class, ++ .mpu_irqs = omap44xx_aess_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs), ++ .sdma_reqs = omap44xx_aess_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs), ++ .main_clk = "aess_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_aess_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), ++ .masters = omap44xx_aess_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'bandgap' class ++ * bangap reference for ldo regulators ++ */ ++ ++static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { ++ .name = "bandgap", ++}; ++ ++/* bandgap */ ++static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { ++ { .role = "fclk", .clk = "bandgap_fclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_bandgap_hwmod = { ++ .name = "bandgap", ++ .class = &omap44xx_bandgap_hwmod_class, ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, ++ }, ++ }, ++ .opt_clks = bandgap_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'counter' class ++ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0004, ++ .sysc_flags = SYSC_HAS_SIDLEMODE, ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_counter_hwmod_class = { ++ .name = "counter", ++ .sysc = &omap44xx_counter_sysc, ++}; ++ ++/* counter_32k */ ++static struct omap_hwmod omap44xx_counter_32k_hwmod; ++static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { ++ { ++ .pa_start = 0x4a304000, ++ .pa_end = 0x4a30401f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_wkup -> counter_32k */ ++static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { ++ .master = &omap44xx_l4_wkup_hwmod, ++ .slave = &omap44xx_counter_32k_hwmod, ++ .clk = "l4_wkup_clk_mux_ck", ++ .addr = omap44xx_counter_32k_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* counter_32k slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { ++ &omap44xx_l4_wkup__counter_32k, ++}; ++ ++static struct omap_hwmod omap44xx_counter_32k_hwmod = { ++ .name = "counter_32k", ++ .class = &omap44xx_counter_hwmod_class, ++ .flags = HWMOD_SWSUP_SIDLE, ++ .main_clk = "sys_32k_ck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_counter_32k_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* + * 'dma' class + * dma controller for data exchange between memory to memory (i.e. internal or + * external memory) and gp peripherals to memory or memory to gp peripherals +@@ -662,6 +887,96 @@ + }; + + /* ++ * 'dmic' class ++ * digital microphone controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type2, ++}; ++ ++static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { ++ .name = "dmic", ++ .sysc = &omap44xx_dmic_sysc, ++}; ++ ++/* dmic */ ++static struct omap_hwmod omap44xx_dmic_hwmod; ++static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { ++ { .irq = 114 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { ++ { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { ++ { ++ .pa_start = 0x4012e000, ++ .pa_end = 0x4012e07f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> dmic */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_dmic_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_dmic_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { ++ { ++ .pa_start = 0x4902e000, ++ .pa_end = 0x4902e07f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> dmic (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_dmic_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_dmic_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++/* dmic slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { ++ &omap44xx_l4_abe__dmic, ++ &omap44xx_l4_abe__dmic_dma, ++}; ++ ++static struct omap_hwmod omap44xx_dmic_hwmod = { ++ .name = "dmic", ++ .class = &omap44xx_dmic_hwmod_class, ++ .mpu_irqs = omap44xx_dmic_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs), ++ .sdma_reqs = omap44xx_dmic_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs), ++ .main_clk = "dmic_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_dmic_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* + * 'dsp' class + * dsp sub-system + */ +@@ -747,894 +1062,3485 @@ + }; + + /* +- * 'gpio' class +- * general purpose io module ++ * 'dss' class ++ * display sub-system + */ + +-static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { ++static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { + .rev_offs = 0x0000, +- .sysc_offs = 0x0010, +- .syss_offs = 0x0114, +- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | +- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | +- SYSS_HAS_RESET_STATUS), +- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | +- SIDLE_SMART_WKUP), +- .sysc_fields = &omap_hwmod_sysc_type1, +-}; +- +-static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { +- .name = "gpio", +- .sysc = &omap44xx_gpio_sysc, +- .rev = 2, ++ .syss_offs = 0x0014, ++ .sysc_flags = SYSS_HAS_RESET_STATUS, + }; + +-/* gpio dev_attr */ +-static struct omap_gpio_dev_attr gpio_dev_attr = { +- .bank_width = 32, +- .dbck_flag = true, ++static struct omap_hwmod_class omap44xx_dss_hwmod_class = { ++ .name = "dss", ++ .sysc = &omap44xx_dss_sysc, + }; + +-/* gpio1 */ +-static struct omap_hwmod omap44xx_gpio1_hwmod; +-static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { +- { .irq = 29 + OMAP44XX_IRQ_GIC_START }, ++/* dss */ ++/* dss master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { ++ &omap44xx_dss__l3_main_1, + }; + +-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { ++static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { + { +- .pa_start = 0x4a310000, +- .pa_end = 0x4a3101ff, ++ .pa_start = 0x58000000, ++ .pa_end = 0x5800007f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_wkup -> gpio1 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { +- .master = &omap44xx_l4_wkup_hwmod, +- .slave = &omap44xx_gpio1_hwmod, +- .clk = "l4_wkup_clk_mux_ck", +- .addr = omap44xx_gpio1_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++/* l3_main_2 -> dss */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_dss_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_dss_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs), ++ .user = OCP_USER_SDMA, + }; + +-/* gpio1 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { +- &omap44xx_l4_wkup__gpio1, ++static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { ++ { ++ .pa_start = 0x48040000, ++ .pa_end = 0x4804007f, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { +- { .role = "dbclk", .clk = "gpio1_dbclk" }, ++/* l4_per -> dss */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_dss_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_dss_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs), ++ .user = OCP_USER_MPU, + }; + +-static struct omap_hwmod omap44xx_gpio1_hwmod = { +- .name = "gpio1", +- .class = &omap44xx_gpio_hwmod_class, +- .mpu_irqs = omap44xx_gpio1_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), +- .main_clk = "gpio1_ick", ++/* dss slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { ++ &omap44xx_l3_main_2__dss, ++ &omap44xx_l4_per__dss, ++}; ++ ++static struct omap_hwmod_opt_clk dss_opt_clks[] = { ++ { .role = "sys_clk", .clk = "dss_sys_clk" }, ++ { .role = "tv_clk", .clk = "dss_tv_clk" }, ++ { .role = "dss_clk", .clk = "dss_dss_clk" }, ++ { .role = "video_clk", .clk = "dss_48mhz_clk" }, ++}; ++ ++static struct omap_hwmod omap44xx_dss_hwmod = { ++ .name = "dss_core", ++ .class = &omap44xx_dss_hwmod_class, ++ .main_clk = "dss_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, +- .opt_clks = gpio1_opt_clks, +- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), +- .dev_attr = &gpio_dev_attr, +- .slaves = omap44xx_gpio1_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), ++ .opt_clks = dss_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), ++ .slaves = omap44xx_dss_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), ++ .masters = omap44xx_dss_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* gpio2 */ +-static struct omap_hwmod omap44xx_gpio2_hwmod; +-static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { +- { .irq = 30 + OMAP44XX_IRQ_GIC_START }, ++/* ++ * 'dispc' class ++ * display controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | ++ SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { +- { +- .pa_start = 0x48055000, +- .pa_end = 0x480551ff, +- .flags = ADDR_TYPE_RT +- }, ++static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { ++ .name = "dispc", ++ .sysc = &omap44xx_dispc_sysc, + }; + +-/* l4_per -> gpio2 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { +- .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_gpio2_hwmod, +- .clk = "l4_div_ck", +- .addr = omap44xx_gpio2_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++/* dss_dispc */ ++static struct omap_hwmod omap44xx_dss_dispc_hwmod; ++static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { ++ { .irq = 25 + OMAP44XX_IRQ_GIC_START }, + }; + +-/* gpio2 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { +- &omap44xx_l4_per__gpio2, ++static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { ++ { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, + }; + +-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { +- { .role = "dbclk", .clk = "gpio2_dbclk" }, ++static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { ++ { ++ .pa_start = 0x58001000, ++ .pa_end = 0x58001fff, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod omap44xx_gpio2_hwmod = { +- .name = "gpio2", +- .class = &omap44xx_gpio_hwmod_class, +- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, +- .mpu_irqs = omap44xx_gpio2_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), +- .main_clk = "gpio2_ick", ++/* l3_main_2 -> dss_dispc */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_dss_dispc_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_dss_dispc_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { ++ { ++ .pa_start = 0x48041000, ++ .pa_end = 0x48041fff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> dss_dispc */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_dss_dispc_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_dss_dispc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++/* dss_dispc slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { ++ &omap44xx_l3_main_2__dss_dispc, ++ &omap44xx_l4_per__dss_dispc, ++}; ++ ++static struct omap_hwmod omap44xx_dss_dispc_hwmod = { ++ .name = "dss_dispc", ++ .class = &omap44xx_dispc_hwmod_class, ++ .mpu_irqs = omap44xx_dss_dispc_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs), ++ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), ++ .main_clk = "dss_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, +- .opt_clks = gpio2_opt_clks, +- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), +- .dev_attr = &gpio_dev_attr, +- .slaves = omap44xx_gpio2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), ++ .slaves = omap44xx_dss_dispc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* gpio3 */ +-static struct omap_hwmod omap44xx_gpio3_hwmod; +-static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { +- { .irq = 31 + OMAP44XX_IRQ_GIC_START }, ++/* ++ * 'dsi' class ++ * display serial interface controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { ++static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { ++ .name = "dsi", ++ .sysc = &omap44xx_dsi_sysc, ++}; ++ ++/* dss_dsi1 */ ++static struct omap_hwmod omap44xx_dss_dsi1_hwmod; ++static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { ++ { .irq = 53 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { ++ { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { + { +- .pa_start = 0x48057000, +- .pa_end = 0x480571ff, ++ .pa_start = 0x58004000, ++ .pa_end = 0x580041ff, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> gpio3 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { +- .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_gpio3_hwmod, +- .clk = "l4_div_ck", +- .addr = omap44xx_gpio3_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++/* l3_main_2 -> dss_dsi1 */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_dss_dsi1_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_dss_dsi1_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs), ++ .user = OCP_USER_SDMA, + }; + +-/* gpio3 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { +- &omap44xx_l4_per__gpio3, ++static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { ++ { ++ .pa_start = 0x48044000, ++ .pa_end = 0x480441ff, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { +- { .role = "dbclk", .clk = "gpio3_dbclk" }, ++/* l4_per -> dss_dsi1 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_dss_dsi1_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_dss_dsi1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs), ++ .user = OCP_USER_MPU, + }; + +-static struct omap_hwmod omap44xx_gpio3_hwmod = { +- .name = "gpio3", +- .class = &omap44xx_gpio_hwmod_class, +- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, +- .mpu_irqs = omap44xx_gpio3_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), +- .main_clk = "gpio3_ick", ++/* dss_dsi1 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { ++ &omap44xx_l3_main_2__dss_dsi1, ++ &omap44xx_l4_per__dss_dsi1, ++}; ++ ++static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { ++ .name = "dss_dsi1", ++ .class = &omap44xx_dsi_hwmod_class, ++ .mpu_irqs = omap44xx_dss_dsi1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs), ++ .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), ++ .main_clk = "dss_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, +- .opt_clks = gpio3_opt_clks, +- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), +- .dev_attr = &gpio_dev_attr, +- .slaves = omap44xx_gpio3_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), ++ .slaves = omap44xx_dss_dsi1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* gpio4 */ +-static struct omap_hwmod omap44xx_gpio4_hwmod; +-static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { +- { .irq = 32 + OMAP44XX_IRQ_GIC_START }, ++/* dss_dsi2 */ ++static struct omap_hwmod omap44xx_dss_dsi2_hwmod; ++static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { ++ { .irq = 84 + OMAP44XX_IRQ_GIC_START }, + }; + +-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { ++static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { ++ { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { + { +- .pa_start = 0x48059000, +- .pa_end = 0x480591ff, ++ .pa_start = 0x58005000, ++ .pa_end = 0x580051ff, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> gpio4 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { +- .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_gpio4_hwmod, +- .clk = "l4_div_ck", +- .addr = omap44xx_gpio4_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++/* l3_main_2 -> dss_dsi2 */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_dss_dsi2_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_dss_dsi2_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs), ++ .user = OCP_USER_SDMA, + }; + +-/* gpio4 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { +- &omap44xx_l4_per__gpio4, ++static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { ++ { ++ .pa_start = 0x48045000, ++ .pa_end = 0x480451ff, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { +- { .role = "dbclk", .clk = "gpio4_dbclk" }, ++/* l4_per -> dss_dsi2 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_dss_dsi2_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_dss_dsi2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs), ++ .user = OCP_USER_MPU, + }; + +-static struct omap_hwmod omap44xx_gpio4_hwmod = { +- .name = "gpio4", +- .class = &omap44xx_gpio_hwmod_class, +- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, +- .mpu_irqs = omap44xx_gpio4_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), +- .main_clk = "gpio4_ick", ++/* dss_dsi2 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { ++ &omap44xx_l3_main_2__dss_dsi2, ++ &omap44xx_l4_per__dss_dsi2, ++}; ++ ++static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { ++ .name = "dss_dsi2", ++ .class = &omap44xx_dsi_hwmod_class, ++ .mpu_irqs = omap44xx_dss_dsi2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs), ++ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), ++ .main_clk = "dss_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, +- .opt_clks = gpio4_opt_clks, +- .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), +- .dev_attr = &gpio_dev_attr, +- .slaves = omap44xx_gpio4_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), ++ .slaves = omap44xx_dss_dsi2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* gpio5 */ +-static struct omap_hwmod omap44xx_gpio5_hwmod; +-static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { +- { .irq = 33 + OMAP44XX_IRQ_GIC_START }, ++/* ++ * 'hdmi' class ++ * hdmi controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type2, + }; + +-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { ++static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { ++ .name = "hdmi", ++ .sysc = &omap44xx_hdmi_sysc, ++}; ++ ++/* dss_hdmi */ ++static struct omap_hwmod omap44xx_dss_hdmi_hwmod; ++static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { ++ { .irq = 101 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { ++ { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { + { +- .pa_start = 0x4805b000, +- .pa_end = 0x4805b1ff, ++ .pa_start = 0x58006000, ++ .pa_end = 0x58006fff, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> gpio5 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { ++/* l3_main_2 -> dss_hdmi */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_dss_hdmi_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_dss_hdmi_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { ++ { ++ .pa_start = 0x48046000, ++ .pa_end = 0x48046fff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> dss_hdmi */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { + .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_gpio5_hwmod, ++ .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_gpio5_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), +- .user = OCP_USER_MPU | OCP_USER_SDMA, ++ .addr = omap44xx_dss_hdmi_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs), ++ .user = OCP_USER_MPU, + }; + +-/* gpio5 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { +- &omap44xx_l4_per__gpio5, ++/* dss_hdmi slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { ++ &omap44xx_l3_main_2__dss_hdmi, ++ &omap44xx_l4_per__dss_hdmi, + }; + +-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { +- { .role = "dbclk", .clk = "gpio5_dbclk" }, ++static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { ++ .name = "dss_hdmi", ++ .class = &omap44xx_hdmi_hwmod_class, ++ .mpu_irqs = omap44xx_dss_hdmi_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs), ++ .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), ++ .main_clk = "dss_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_dss_hdmi_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-static struct omap_hwmod omap44xx_gpio5_hwmod = { +- .name = "gpio5", +- .class = &omap44xx_gpio_hwmod_class, +- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, +- .mpu_irqs = omap44xx_gpio5_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), +- .main_clk = "gpio5_ick", ++/* ++ * 'rfbi' class ++ * remote frame buffer interface ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { ++ .name = "rfbi", ++ .sysc = &omap44xx_rfbi_sysc, ++}; ++ ++/* dss_rfbi */ ++static struct omap_hwmod omap44xx_dss_rfbi_hwmod; ++static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { ++ { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { ++ { ++ .pa_start = 0x58002000, ++ .pa_end = 0x580020ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l3_main_2 -> dss_rfbi */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_dss_rfbi_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_dss_rfbi_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { ++ { ++ .pa_start = 0x48042000, ++ .pa_end = 0x480420ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> dss_rfbi */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_dss_rfbi_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_dss_rfbi_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++/* dss_rfbi slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { ++ &omap44xx_l3_main_2__dss_rfbi, ++ &omap44xx_l4_per__dss_rfbi, ++}; ++ ++static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { ++ .name = "dss_rfbi", ++ .class = &omap44xx_rfbi_hwmod_class, ++ .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs), ++ .main_clk = "dss_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, +- .opt_clks = gpio5_opt_clks, +- .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), +- .dev_attr = &gpio_dev_attr, +- .slaves = omap44xx_gpio5_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), ++ .slaves = omap44xx_dss_rfbi_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* gpio6 */ +-static struct omap_hwmod omap44xx_gpio6_hwmod; +-static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { +- { .irq = 34 + OMAP44XX_IRQ_GIC_START }, ++/* ++ * 'venc' class ++ * video encoder ++ */ ++ ++static struct omap_hwmod_class omap44xx_venc_hwmod_class = { ++ .name = "venc", ++}; ++ ++/* dss_venc */ ++static struct omap_hwmod omap44xx_dss_venc_hwmod; ++static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { ++ { ++ .pa_start = 0x58003000, ++ .pa_end = 0x580030ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l3_main_2 -> dss_venc */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_dss_venc_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_dss_venc_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { ++ { ++ .pa_start = 0x48043000, ++ .pa_end = 0x480430ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> dss_venc */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_dss_venc_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_dss_venc_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++/* dss_venc slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { ++ &omap44xx_l3_main_2__dss_venc, ++ &omap44xx_l4_per__dss_venc, ++}; ++ ++static struct omap_hwmod omap44xx_dss_venc_hwmod = { ++ .name = "dss_venc", ++ .class = &omap44xx_venc_hwmod_class, ++ .main_clk = "dss_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_dss_venc_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'gpio' class ++ * general purpose io module ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0114, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | ++ SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { ++ .name = "gpio", ++ .sysc = &omap44xx_gpio_sysc, ++ .rev = 2, ++}; ++ ++/* gpio dev_attr */ ++static struct omap_gpio_dev_attr gpio_dev_attr = { ++ .bank_width = 32, ++ .dbck_flag = true, ++}; ++ ++/* gpio1 */ ++static struct omap_hwmod omap44xx_gpio1_hwmod; ++static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { ++ { .irq = 29 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { ++ { ++ .pa_start = 0x4a310000, ++ .pa_end = 0x4a3101ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_wkup -> gpio1 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { ++ .master = &omap44xx_l4_wkup_hwmod, ++ .slave = &omap44xx_gpio1_hwmod, ++ .clk = "l4_wkup_clk_mux_ck", ++ .addr = omap44xx_gpio1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* gpio1 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { ++ &omap44xx_l4_wkup__gpio1, ++}; ++ ++static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { ++ { .role = "dbclk", .clk = "gpio1_dbclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_gpio1_hwmod = { ++ .name = "gpio1", ++ .class = &omap44xx_gpio_hwmod_class, ++ .mpu_irqs = omap44xx_gpio1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), ++ .main_clk = "gpio1_ick", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, ++ }, ++ }, ++ .opt_clks = gpio1_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), ++ .dev_attr = &gpio_dev_attr, ++ .slaves = omap44xx_gpio1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* gpio2 */ ++static struct omap_hwmod omap44xx_gpio2_hwmod; ++static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { ++ { .irq = 30 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { ++ { ++ .pa_start = 0x48055000, ++ .pa_end = 0x480551ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> gpio2 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_gpio2_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_gpio2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* gpio2 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { ++ &omap44xx_l4_per__gpio2, ++}; ++ ++static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { ++ { .role = "dbclk", .clk = "gpio2_dbclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_gpio2_hwmod = { ++ .name = "gpio2", ++ .class = &omap44xx_gpio_hwmod_class, ++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, ++ .mpu_irqs = omap44xx_gpio2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), ++ .main_clk = "gpio2_ick", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, ++ }, ++ }, ++ .opt_clks = gpio2_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), ++ .dev_attr = &gpio_dev_attr, ++ .slaves = omap44xx_gpio2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* gpio3 */ ++static struct omap_hwmod omap44xx_gpio3_hwmod; ++static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { ++ { .irq = 31 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { ++ { ++ .pa_start = 0x48057000, ++ .pa_end = 0x480571ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> gpio3 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_gpio3_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_gpio3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* gpio3 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { ++ &omap44xx_l4_per__gpio3, ++}; ++ ++static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { ++ { .role = "dbclk", .clk = "gpio3_dbclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_gpio3_hwmod = { ++ .name = "gpio3", ++ .class = &omap44xx_gpio_hwmod_class, ++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, ++ .mpu_irqs = omap44xx_gpio3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), ++ .main_clk = "gpio3_ick", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, ++ }, ++ }, ++ .opt_clks = gpio3_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), ++ .dev_attr = &gpio_dev_attr, ++ .slaves = omap44xx_gpio3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* gpio4 */ ++static struct omap_hwmod omap44xx_gpio4_hwmod; ++static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { ++ { .irq = 32 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { ++ { ++ .pa_start = 0x48059000, ++ .pa_end = 0x480591ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> gpio4 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_gpio4_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_gpio4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* gpio4 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { ++ &omap44xx_l4_per__gpio4, ++}; ++ ++static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { ++ { .role = "dbclk", .clk = "gpio4_dbclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_gpio4_hwmod = { ++ .name = "gpio4", ++ .class = &omap44xx_gpio_hwmod_class, ++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, ++ .mpu_irqs = omap44xx_gpio4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), ++ .main_clk = "gpio4_ick", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, ++ }, ++ }, ++ .opt_clks = gpio4_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), ++ .dev_attr = &gpio_dev_attr, ++ .slaves = omap44xx_gpio4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* gpio5 */ ++static struct omap_hwmod omap44xx_gpio5_hwmod; ++static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { ++ { .irq = 33 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { ++ { ++ .pa_start = 0x4805b000, ++ .pa_end = 0x4805b1ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> gpio5 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_gpio5_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_gpio5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* gpio5 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { ++ &omap44xx_l4_per__gpio5, ++}; ++ ++static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { ++ { .role = "dbclk", .clk = "gpio5_dbclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_gpio5_hwmod = { ++ .name = "gpio5", ++ .class = &omap44xx_gpio_hwmod_class, ++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, ++ .mpu_irqs = omap44xx_gpio5_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), ++ .main_clk = "gpio5_ick", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, ++ }, ++ }, ++ .opt_clks = gpio5_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), ++ .dev_attr = &gpio_dev_attr, ++ .slaves = omap44xx_gpio5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* gpio6 */ ++static struct omap_hwmod omap44xx_gpio6_hwmod; ++static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { ++ { .irq = 34 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { ++ { ++ .pa_start = 0x4805d000, ++ .pa_end = 0x4805d1ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> gpio6 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_gpio6_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_gpio6_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* gpio6 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { ++ &omap44xx_l4_per__gpio6, ++}; ++ ++static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { ++ { .role = "dbclk", .clk = "gpio6_dbclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_gpio6_hwmod = { ++ .name = "gpio6", ++ .class = &omap44xx_gpio_hwmod_class, ++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, ++ .mpu_irqs = omap44xx_gpio6_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), ++ .main_clk = "gpio6_ick", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, ++ }, ++ }, ++ .opt_clks = gpio6_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), ++ .dev_attr = &gpio_dev_attr, ++ .slaves = omap44xx_gpio6_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'hsi' class ++ * mipi high-speed synchronous serial interface (multichannel and full-duplex ++ * serial if) ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | ++ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | ++ MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { ++ .name = "hsi", ++ .sysc = &omap44xx_hsi_sysc, ++}; ++ ++/* hsi */ ++static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { ++ { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, ++ { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, ++ { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++/* hsi master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { ++ &omap44xx_hsi__l3_main_2, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { ++ { ++ .pa_start = 0x4a058000, ++ .pa_end = 0x4a05bfff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_cfg -> hsi */ ++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { ++ .master = &omap44xx_l4_cfg_hwmod, ++ .slave = &omap44xx_hsi_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_hsi_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* hsi slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { ++ &omap44xx_l4_cfg__hsi, ++}; ++ ++static struct omap_hwmod omap44xx_hsi_hwmod = { ++ .name = "hsi", ++ .class = &omap44xx_hsi_hwmod_class, ++ .mpu_irqs = omap44xx_hsi_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs), ++ .main_clk = "hsi_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_hsi_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), ++ .masters = omap44xx_hsi_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'i2c' class ++ * multimaster high-speed i2c controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0090, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { ++ .name = "i2c", ++ .sysc = &omap44xx_i2c_sysc, ++}; ++ ++/* i2c1 */ ++static struct omap_hwmod omap44xx_i2c1_hwmod; ++static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { ++ { .irq = 56 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { ++ { ++ .pa_start = 0x48070000, ++ .pa_end = 0x480700ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> i2c1 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_i2c1_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_i2c1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* i2c1 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { ++ &omap44xx_l4_per__i2c1, ++}; ++ ++static struct omap_hwmod omap44xx_i2c1_hwmod = { ++ .name = "i2c1", ++ .class = &omap44xx_i2c_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .mpu_irqs = omap44xx_i2c1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), ++ .sdma_reqs = omap44xx_i2c1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), ++ .main_clk = "i2c1_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_i2c1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* i2c2 */ ++static struct omap_hwmod omap44xx_i2c2_hwmod; ++static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { ++ { .irq = 57 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { ++ { ++ .pa_start = 0x48072000, ++ .pa_end = 0x480720ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> i2c2 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_i2c2_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_i2c2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* i2c2 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { ++ &omap44xx_l4_per__i2c2, ++}; ++ ++static struct omap_hwmod omap44xx_i2c2_hwmod = { ++ .name = "i2c2", ++ .class = &omap44xx_i2c_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .mpu_irqs = omap44xx_i2c2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), ++ .sdma_reqs = omap44xx_i2c2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), ++ .main_clk = "i2c2_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_i2c2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* i2c3 */ ++static struct omap_hwmod omap44xx_i2c3_hwmod; ++static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { ++ { .irq = 61 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { ++ { ++ .pa_start = 0x48060000, ++ .pa_end = 0x480600ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> i2c3 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_i2c3_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_i2c3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* i2c3 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { ++ &omap44xx_l4_per__i2c3, ++}; ++ ++static struct omap_hwmod omap44xx_i2c3_hwmod = { ++ .name = "i2c3", ++ .class = &omap44xx_i2c_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .mpu_irqs = omap44xx_i2c3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), ++ .sdma_reqs = omap44xx_i2c3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), ++ .main_clk = "i2c3_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_i2c3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* i2c4 */ ++static struct omap_hwmod omap44xx_i2c4_hwmod; ++static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { ++ { .irq = 62 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { ++ { ++ .pa_start = 0x48350000, ++ .pa_end = 0x483500ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> i2c4 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_i2c4_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_i2c4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* i2c4 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { ++ &omap44xx_l4_per__i2c4, ++}; ++ ++static struct omap_hwmod omap44xx_i2c4_hwmod = { ++ .name = "i2c4", ++ .class = &omap44xx_i2c_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .mpu_irqs = omap44xx_i2c4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), ++ .sdma_reqs = omap44xx_i2c4_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), ++ .main_clk = "i2c4_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_i2c4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'ipu' class ++ * imaging processor unit ++ */ ++ ++static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { ++ .name = "ipu", ++}; ++ ++/* ipu */ ++static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { ++ { .irq = 100 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { ++ { .name = "cpu0", .rst_shift = 0 }, ++}; ++ ++static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { ++ { .name = "cpu1", .rst_shift = 1 }, ++}; ++ ++static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { ++ { .name = "mmu_cache", .rst_shift = 2 }, ++}; ++ ++/* ipu master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { ++ &omap44xx_ipu__l3_main_2, ++}; ++ ++/* l3_main_2 -> ipu */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_ipu_hwmod, ++ .clk = "l3_div_ck", ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* ipu slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { ++ &omap44xx_l3_main_2__ipu, ++}; ++ ++/* Pseudo hwmod for reset control purpose only */ ++static struct omap_hwmod omap44xx_ipu_c0_hwmod = { ++ .name = "ipu_c0", ++ .class = &omap44xx_ipu_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .rst_lines = omap44xx_ipu_c0_resets, ++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), ++ .prcm = { ++ .omap4 = { ++ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, ++ }, ++ }, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* Pseudo hwmod for reset control purpose only */ ++static struct omap_hwmod omap44xx_ipu_c1_hwmod = { ++ .name = "ipu_c1", ++ .class = &omap44xx_ipu_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .rst_lines = omap44xx_ipu_c1_resets, ++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), ++ .prcm = { ++ .omap4 = { ++ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, ++ }, ++ }, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++static struct omap_hwmod omap44xx_ipu_hwmod = { ++ .name = "ipu", ++ .class = &omap44xx_ipu_hwmod_class, ++ .mpu_irqs = omap44xx_ipu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs), ++ .rst_lines = omap44xx_ipu_resets, ++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), ++ .main_clk = "ipu_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, ++ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, ++ }, ++ }, ++ .slaves = omap44xx_ipu_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), ++ .masters = omap44xx_ipu_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'iss' class ++ * external images sensor pixel data processor ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | ++ MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type2, ++}; ++ ++static struct omap_hwmod_class omap44xx_iss_hwmod_class = { ++ .name = "iss", ++ .sysc = &omap44xx_iss_sysc, ++}; ++ ++/* iss */ ++static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { ++ { .irq = 24 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { ++ { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, ++ { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, ++ { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, ++ { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++/* iss master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { ++ &omap44xx_iss__l3_main_2, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { ++ { ++ .pa_start = 0x52000000, ++ .pa_end = 0x520000ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l3_main_2 -> iss */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_iss_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_iss_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* iss slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { ++ &omap44xx_l3_main_2__iss, ++}; ++ ++static struct omap_hwmod_opt_clk iss_opt_clks[] = { ++ { .role = "ctrlclk", .clk = "iss_ctrlclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_iss_hwmod = { ++ .name = "iss", ++ .class = &omap44xx_iss_hwmod_class, ++ .mpu_irqs = omap44xx_iss_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs), ++ .sdma_reqs = omap44xx_iss_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs), ++ .main_clk = "iss_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, ++ }, ++ }, ++ .opt_clks = iss_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), ++ .slaves = omap44xx_iss_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), ++ .masters = omap44xx_iss_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'iva' class ++ * multi-standard video encoder/decoder hardware accelerator ++ */ ++ ++static struct omap_hwmod_class omap44xx_iva_hwmod_class = { ++ .name = "iva", ++}; ++ ++/* iva */ ++static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { ++ { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, ++ { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, ++ { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { ++ { .name = "logic", .rst_shift = 2 }, ++}; ++ ++static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { ++ { .name = "seq0", .rst_shift = 0 }, ++}; ++ ++static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { ++ { .name = "seq1", .rst_shift = 1 }, ++}; ++ ++/* iva master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { ++ &omap44xx_iva__l3_main_2, ++ &omap44xx_iva__l3_instr, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { ++ { ++ .pa_start = 0x5a000000, ++ .pa_end = 0x5a07ffff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l3_main_2 -> iva */ ++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { ++ .master = &omap44xx_l3_main_2_hwmod, ++ .slave = &omap44xx_iva_hwmod, ++ .clk = "l3_div_ck", ++ .addr = omap44xx_iva_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++/* iva slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { ++ &omap44xx_dsp__iva, ++ &omap44xx_l3_main_2__iva, ++}; ++ ++/* Pseudo hwmod for reset control purpose only */ ++static struct omap_hwmod omap44xx_iva_seq0_hwmod = { ++ .name = "iva_seq0", ++ .class = &omap44xx_iva_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .rst_lines = omap44xx_iva_seq0_resets, ++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), ++ .prcm = { ++ .omap4 = { ++ .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, ++ }, ++ }, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* Pseudo hwmod for reset control purpose only */ ++static struct omap_hwmod omap44xx_iva_seq1_hwmod = { ++ .name = "iva_seq1", ++ .class = &omap44xx_iva_hwmod_class, ++ .flags = HWMOD_INIT_NO_RESET, ++ .rst_lines = omap44xx_iva_seq1_resets, ++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), ++ .prcm = { ++ .omap4 = { ++ .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, ++ }, ++ }, ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++static struct omap_hwmod omap44xx_iva_hwmod = { ++ .name = "iva", ++ .class = &omap44xx_iva_hwmod_class, ++ .mpu_irqs = omap44xx_iva_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), ++ .rst_lines = omap44xx_iva_resets, ++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), ++ .main_clk = "iva_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, ++ .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, ++ }, ++ }, ++ .slaves = omap44xx_iva_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), ++ .masters = omap44xx_iva_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'kbd' class ++ * keyboard controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | ++ SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { ++ .name = "kbd", ++ .sysc = &omap44xx_kbd_sysc, ++}; ++ ++/* kbd */ ++static struct omap_hwmod omap44xx_kbd_hwmod; ++static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { ++ { .irq = 120 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { ++ { ++ .pa_start = 0x4a31c000, ++ .pa_end = 0x4a31c07f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_wkup -> kbd */ ++static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { ++ .master = &omap44xx_l4_wkup_hwmod, ++ .slave = &omap44xx_kbd_hwmod, ++ .clk = "l4_wkup_clk_mux_ck", ++ .addr = omap44xx_kbd_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* kbd slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { ++ &omap44xx_l4_wkup__kbd, ++}; ++ ++static struct omap_hwmod omap44xx_kbd_hwmod = { ++ .name = "kbd", ++ .class = &omap44xx_kbd_hwmod_class, ++ .mpu_irqs = omap44xx_kbd_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs), ++ .main_clk = "kbd_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_kbd_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'mailbox' class ++ * mailbox module allowing communication between the on-chip processors using a ++ * queued mailbox-interrupt mechanism. ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type2, ++}; ++ ++static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { ++ .name = "mailbox", ++ .sysc = &omap44xx_mailbox_sysc, ++}; ++ ++/* mailbox */ ++static struct omap_hwmod omap44xx_mailbox_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { ++ { .irq = 26 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { ++ { ++ .pa_start = 0x4a0f4000, ++ .pa_end = 0x4a0f41ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_cfg -> mailbox */ ++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { ++ .master = &omap44xx_l4_cfg_hwmod, ++ .slave = &omap44xx_mailbox_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mailbox_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mailbox slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { ++ &omap44xx_l4_cfg__mailbox, ++}; ++ ++static struct omap_hwmod omap44xx_mailbox_hwmod = { ++ .name = "mailbox", ++ .class = &omap44xx_mailbox_hwmod_class, ++ .mpu_irqs = omap44xx_mailbox_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs), ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mailbox_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'mcbsp' class ++ * multi channel buffered serial port controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { ++ .sysc_offs = 0x008c, ++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { ++ .name = "mcbsp", ++ .sysc = &omap44xx_mcbsp_sysc, ++ .rev = MCBSP_CONFIG_TYPE4, ++}; ++ ++/* mcbsp1 */ ++static struct omap_hwmod omap44xx_mcbsp1_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { ++ { .irq = 17 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x40122000, ++ .pa_end = 0x401220ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcbsp1 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcbsp1_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcbsp1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { ++ { ++ .name = "dma", ++ .pa_start = 0x49022000, ++ .pa_end = 0x490220ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcbsp1 (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcbsp1_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcbsp1_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++/* mcbsp1 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { ++ &omap44xx_l4_abe__mcbsp1, ++ &omap44xx_l4_abe__mcbsp1_dma, ++}; ++ ++static struct omap_hwmod omap44xx_mcbsp1_hwmod = { ++ .name = "mcbsp1", ++ .class = &omap44xx_mcbsp_hwmod_class, ++ .mpu_irqs = omap44xx_mcbsp1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs), ++ .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs), ++ .main_clk = "mcbsp1_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mcbsp1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mcbsp2 */ ++static struct omap_hwmod omap44xx_mcbsp2_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { ++ { .irq = 22 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x40124000, ++ .pa_end = 0x401240ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcbsp2 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcbsp2_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcbsp2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { ++ { ++ .name = "dma", ++ .pa_start = 0x49024000, ++ .pa_end = 0x490240ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcbsp2 (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcbsp2_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcbsp2_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++/* mcbsp2 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { ++ &omap44xx_l4_abe__mcbsp2, ++ &omap44xx_l4_abe__mcbsp2_dma, ++}; ++ ++static struct omap_hwmod omap44xx_mcbsp2_hwmod = { ++ .name = "mcbsp2", ++ .class = &omap44xx_mcbsp_hwmod_class, ++ .mpu_irqs = omap44xx_mcbsp2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs), ++ .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs), ++ .main_clk = "mcbsp2_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mcbsp2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mcbsp3 */ ++static struct omap_hwmod omap44xx_mcbsp3_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { ++ { .irq = 23 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { ++ { ++ .name = "mpu", ++ .pa_start = 0x40126000, ++ .pa_end = 0x401260ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcbsp3 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcbsp3_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcbsp3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { ++ { ++ .name = "dma", ++ .pa_start = 0x49026000, ++ .pa_end = 0x490260ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcbsp3 (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcbsp3_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcbsp3_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++/* mcbsp3 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { ++ &omap44xx_l4_abe__mcbsp3, ++ &omap44xx_l4_abe__mcbsp3_dma, ++}; ++ ++static struct omap_hwmod omap44xx_mcbsp3_hwmod = { ++ .name = "mcbsp3", ++ .class = &omap44xx_mcbsp_hwmod_class, ++ .mpu_irqs = omap44xx_mcbsp3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs), ++ .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs), ++ .main_clk = "mcbsp3_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mcbsp3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mcbsp4 */ ++static struct omap_hwmod omap44xx_mcbsp4_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { ++ { .irq = 16 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { ++ { ++ .pa_start = 0x48096000, ++ .pa_end = 0x480960ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcbsp4 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mcbsp4_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mcbsp4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcbsp4 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { ++ &omap44xx_l4_per__mcbsp4, ++}; ++ ++static struct omap_hwmod omap44xx_mcbsp4_hwmod = { ++ .name = "mcbsp4", ++ .class = &omap44xx_mcbsp_hwmod_class, ++ .mpu_irqs = omap44xx_mcbsp4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs), ++ .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs), ++ .main_clk = "mcbsp4_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mcbsp4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'mcpdm' class ++ * multi channel pdm controller (proprietary interface with phoenix power ++ * ic) ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type2, ++}; ++ ++static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { ++ .name = "mcpdm", ++ .sysc = &omap44xx_mcpdm_sysc, ++}; ++ ++/* mcpdm */ ++static struct omap_hwmod omap44xx_mcpdm_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { ++ { .irq = 112 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { ++ { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, ++ { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { ++ { ++ .pa_start = 0x40132000, ++ .pa_end = 0x4013207f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcpdm */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcpdm_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcpdm_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs), ++ .user = OCP_USER_MPU, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { ++ { ++ .pa_start = 0x49032000, ++ .pa_end = 0x4903207f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> mcpdm (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_mcpdm_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_mcpdm_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++/* mcpdm slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { ++ &omap44xx_l4_abe__mcpdm, ++ &omap44xx_l4_abe__mcpdm_dma, ++}; ++ ++static struct omap_hwmod omap44xx_mcpdm_hwmod = { ++ .name = "mcpdm", ++ .class = &omap44xx_mcpdm_hwmod_class, ++ .mpu_irqs = omap44xx_mcpdm_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs), ++ .sdma_reqs = omap44xx_mcpdm_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs), ++ .main_clk = "mcpdm_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mcpdm_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'mcspi' class ++ * multichannel serial port interface (mcspi) / master/slave synchronous serial ++ * bus ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type2, ++}; ++ ++static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { ++ .name = "mcspi", ++ .sysc = &omap44xx_mcspi_sysc, ++ .rev = OMAP4_MCSPI_REV, ++}; ++ ++/* mcspi1 */ ++static struct omap_hwmod omap44xx_mcspi1_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { ++ { .irq = 65 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, ++ { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, ++ { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, ++ { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { ++ { ++ .pa_start = 0x48098000, ++ .pa_end = 0x480981ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcspi1 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mcspi1_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mcspi1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcspi1 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { ++ &omap44xx_l4_per__mcspi1, ++}; ++ ++/* mcspi1 dev_attr */ ++static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { ++ .num_chipselect = 4, ++}; ++ ++static struct omap_hwmod omap44xx_mcspi1_hwmod = { ++ .name = "mcspi1", ++ .class = &omap44xx_mcspi_hwmod_class, ++ .mpu_irqs = omap44xx_mcspi1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs), ++ .sdma_reqs = omap44xx_mcspi1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs), ++ .main_clk = "mcspi1_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, ++ }, ++ }, ++ .dev_attr = &mcspi1_dev_attr, ++ .slaves = omap44xx_mcspi1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mcspi2 */ ++static struct omap_hwmod omap44xx_mcspi2_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { ++ { .irq = 66 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, ++ { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { ++ { ++ .pa_start = 0x4809a000, ++ .pa_end = 0x4809a1ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcspi2 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mcspi2_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mcspi2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcspi2 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { ++ &omap44xx_l4_per__mcspi2, ++}; ++ ++/* mcspi2 dev_attr */ ++static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { ++ .num_chipselect = 2, ++}; ++ ++static struct omap_hwmod omap44xx_mcspi2_hwmod = { ++ .name = "mcspi2", ++ .class = &omap44xx_mcspi_hwmod_class, ++ .mpu_irqs = omap44xx_mcspi2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs), ++ .sdma_reqs = omap44xx_mcspi2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs), ++ .main_clk = "mcspi2_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, ++ }, ++ }, ++ .dev_attr = &mcspi2_dev_attr, ++ .slaves = omap44xx_mcspi2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mcspi3 */ ++static struct omap_hwmod omap44xx_mcspi3_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { ++ { .irq = 91 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, ++ { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { ++ { ++ .pa_start = 0x480b8000, ++ .pa_end = 0x480b81ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcspi3 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mcspi3_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mcspi3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcspi3 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { ++ &omap44xx_l4_per__mcspi3, ++}; ++ ++/* mcspi3 dev_attr */ ++static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { ++ .num_chipselect = 2, ++}; ++ ++static struct omap_hwmod omap44xx_mcspi3_hwmod = { ++ .name = "mcspi3", ++ .class = &omap44xx_mcspi_hwmod_class, ++ .mpu_irqs = omap44xx_mcspi3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs), ++ .sdma_reqs = omap44xx_mcspi3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs), ++ .main_clk = "mcspi3_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, ++ }, ++ }, ++ .dev_attr = &mcspi3_dev_attr, ++ .slaves = omap44xx_mcspi3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mcspi4 */ ++static struct omap_hwmod omap44xx_mcspi4_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { ++ { .irq = 48 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { ++ { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { ++ { ++ .pa_start = 0x480ba000, ++ .pa_end = 0x480ba1ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mcspi4 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mcspi4_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mcspi4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mcspi4 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { ++ &omap44xx_l4_per__mcspi4, ++}; ++ ++/* mcspi4 dev_attr */ ++static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { ++ .num_chipselect = 1, ++}; ++ ++static struct omap_hwmod omap44xx_mcspi4_hwmod = { ++ .name = "mcspi4", ++ .class = &omap44xx_mcspi_hwmod_class, ++ .mpu_irqs = omap44xx_mcspi4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs), ++ .sdma_reqs = omap44xx_mcspi4_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs), ++ .main_clk = "mcspi4_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, ++ }, ++ }, ++ .dev_attr = &mcspi4_dev_attr, ++ .slaves = omap44xx_mcspi4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'mmc' class ++ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | ++ SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | ++ MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type2, ++}; ++ ++static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { ++ .name = "mmc", ++ .sysc = &omap44xx_mmc_sysc, ++}; ++ ++/* mmc1 */ ++ ++static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { ++ { .irq = 83 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++/* mmc1 master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { ++ &omap44xx_mmc1__l3_main_1, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { ++ { ++ .pa_start = 0x4809c000, ++ .pa_end = 0x4809c3ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mmc1 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mmc1_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mmc1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mmc1 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { ++ &omap44xx_l4_per__mmc1, ++}; ++ ++/* mmc1 dev_attr */ ++static struct omap_mmc_dev_attr mmc1_dev_attr = { ++ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, ++}; ++ ++static struct omap_hwmod omap44xx_mmc1_hwmod = { ++ .name = "mmc1", ++ .class = &omap44xx_mmc_hwmod_class, ++ .mpu_irqs = omap44xx_mmc1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs), ++ .sdma_reqs = omap44xx_mmc1_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs), ++ .main_clk = "mmc1_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, ++ }, ++ }, ++ .dev_attr = &mmc1_dev_attr, ++ .slaves = omap44xx_mmc1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), ++ .masters = omap44xx_mmc1_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mmc2 */ ++static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { ++ { .irq = 86 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++/* mmc2 master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { ++ &omap44xx_mmc2__l3_main_1, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { ++ { ++ .pa_start = 0x480b4000, ++ .pa_end = 0x480b43ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mmc2 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mmc2_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mmc2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mmc2 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { ++ &omap44xx_l4_per__mmc2, ++}; ++ ++static struct omap_hwmod omap44xx_mmc2_hwmod = { ++ .name = "mmc2", ++ .class = &omap44xx_mmc_hwmod_class, ++ .mpu_irqs = omap44xx_mmc2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs), ++ .sdma_reqs = omap44xx_mmc2_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs), ++ .main_clk = "mmc2_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mmc2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), ++ .masters = omap44xx_mmc2_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mmc3 */ ++static struct omap_hwmod omap44xx_mmc3_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { ++ { .irq = 94 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { ++ { ++ .pa_start = 0x480ad000, ++ .pa_end = 0x480ad3ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mmc3 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mmc3_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mmc3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mmc3 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { ++ &omap44xx_l4_per__mmc3, ++}; ++ ++static struct omap_hwmod omap44xx_mmc3_hwmod = { ++ .name = "mmc3", ++ .class = &omap44xx_mmc_hwmod_class, ++ .mpu_irqs = omap44xx_mmc3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs), ++ .sdma_reqs = omap44xx_mmc3_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs), ++ .main_clk = "mmc3_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mmc3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mmc4 */ ++static struct omap_hwmod omap44xx_mmc4_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { ++ { .irq = 96 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { ++ { ++ .pa_start = 0x480d1000, ++ .pa_end = 0x480d13ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mmc4 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mmc4_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mmc4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mmc4 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { ++ &omap44xx_l4_per__mmc4, ++}; ++ ++static struct omap_hwmod omap44xx_mmc4_hwmod = { ++ .name = "mmc4", ++ .class = &omap44xx_mmc_hwmod_class, ++ .mpu_irqs = omap44xx_mmc4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs), ++ .sdma_reqs = omap44xx_mmc4_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs), ++ .main_clk = "mmc4_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mmc4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* mmc5 */ ++static struct omap_hwmod omap44xx_mmc5_hwmod; ++static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { ++ { .irq = 59 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { ++ { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, ++ { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { ++ { ++ .pa_start = 0x480d5000, ++ .pa_end = 0x480d53ff, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_per -> mmc5 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_mmc5_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_mmc5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* mmc5 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { ++ &omap44xx_l4_per__mmc5, ++}; ++ ++static struct omap_hwmod omap44xx_mmc5_hwmod = { ++ .name = "mmc5", ++ .class = &omap44xx_mmc_hwmod_class, ++ .mpu_irqs = omap44xx_mmc5_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs), ++ .sdma_reqs = omap44xx_mmc5_sdma_reqs, ++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs), ++ .main_clk = "mmc5_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_mmc5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'mpu' class ++ * mpu sub-system ++ */ ++ ++static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { ++ .name = "mpu", ++}; ++ ++/* mpu */ ++static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { ++ { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, ++ { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, ++ { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++/* mpu master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { ++ &omap44xx_mpu__l3_main_1, ++ &omap44xx_mpu__l4_abe, ++ &omap44xx_mpu__dmm, ++}; ++ ++static struct omap_hwmod omap44xx_mpu_hwmod = { ++ .name = "mpu", ++ .class = &omap44xx_mpu_hwmod_class, ++ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), ++ .mpu_irqs = omap44xx_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), ++ .main_clk = "dpll_mpu_m2_ck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, ++ }, ++ }, ++ .masters = omap44xx_mpu_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'smartreflex' class ++ * smartreflex module (monitor silicon performance and outputs a measure of ++ * performance error) ++ */ ++ ++/* The IP is not compliant to type1 / type2 scheme */ ++static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { ++ .sidle_shift = 24, ++ .enwkup_shift = 26, ++}; ++ ++static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { ++ .sysc_offs = 0x0038, ++ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type_smartreflex, ++}; ++ ++static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { ++ .name = "smartreflex", ++ .sysc = &omap44xx_smartreflex_sysc, ++ .rev = 2, ++}; ++ ++/* smartreflex_core */ ++static struct omap_hwmod omap44xx_smartreflex_core_hwmod; ++static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { ++ { .irq = 19 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { ++ { ++ .pa_start = 0x4a0dd000, ++ .pa_end = 0x4a0dd03f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_cfg -> smartreflex_core */ ++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { ++ .master = &omap44xx_l4_cfg_hwmod, ++ .slave = &omap44xx_smartreflex_core_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_smartreflex_core_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* smartreflex_core slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { ++ &omap44xx_l4_cfg__smartreflex_core, ++}; ++ ++static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { ++ .name = "smartreflex_core", ++ .class = &omap44xx_smartreflex_hwmod_class, ++ .mpu_irqs = omap44xx_smartreflex_core_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), ++ .main_clk = "smartreflex_core_fck", ++ .vdd_name = "core", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_smartreflex_core_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* smartreflex_iva */ ++static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; ++static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { ++ { .irq = 102 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { ++ { ++ .pa_start = 0x4a0db000, ++ .pa_end = 0x4a0db03f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_cfg -> smartreflex_iva */ ++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { ++ .master = &omap44xx_l4_cfg_hwmod, ++ .slave = &omap44xx_smartreflex_iva_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_smartreflex_iva_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* smartreflex_iva slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { ++ &omap44xx_l4_cfg__smartreflex_iva, ++}; ++ ++static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { ++ .name = "smartreflex_iva", ++ .class = &omap44xx_smartreflex_hwmod_class, ++ .mpu_irqs = omap44xx_smartreflex_iva_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), ++ .main_clk = "smartreflex_iva_fck", ++ .vdd_name = "iva", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_smartreflex_iva_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* smartreflex_mpu */ ++static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; ++static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { ++ { .irq = 18 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { ++ { ++ .pa_start = 0x4a0d9000, ++ .pa_end = 0x4a0d903f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_cfg -> smartreflex_mpu */ ++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { ++ .master = &omap44xx_l4_cfg_hwmod, ++ .slave = &omap44xx_smartreflex_mpu_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_smartreflex_mpu_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* smartreflex_mpu slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { ++ &omap44xx_l4_cfg__smartreflex_mpu, ++}; ++ ++static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { ++ .name = "smartreflex_mpu", ++ .class = &omap44xx_smartreflex_hwmod_class, ++ .mpu_irqs = omap44xx_smartreflex_mpu_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), ++ .main_clk = "smartreflex_mpu_fck", ++ .vdd_name = "mpu", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_smartreflex_mpu_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* ++ * 'spinlock' class ++ * spinlock provides hardware assistance for synchronizing the processes ++ * running on multiple processors ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .syss_offs = 0x0014, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | ++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { ++ .name = "spinlock", ++ .sysc = &omap44xx_spinlock_sysc, + }; + +-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { ++/* spinlock */ ++static struct omap_hwmod omap44xx_spinlock_hwmod; ++static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { + { +- .pa_start = 0x4805d000, +- .pa_end = 0x4805d1ff, ++ .pa_start = 0x4a0f6000, ++ .pa_end = 0x4a0f6fff, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> gpio6 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { +- .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_gpio6_hwmod, ++/* l4_cfg -> spinlock */ ++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { ++ .master = &omap44xx_l4_cfg_hwmod, ++ .slave = &omap44xx_spinlock_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_gpio6_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), ++ .addr = omap44xx_spinlock_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* gpio6 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { +- &omap44xx_l4_per__gpio6, +-}; +- +-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { +- { .role = "dbclk", .clk = "gpio6_dbclk" }, ++/* spinlock slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { ++ &omap44xx_l4_cfg__spinlock, + }; + +-static struct omap_hwmod omap44xx_gpio6_hwmod = { +- .name = "gpio6", +- .class = &omap44xx_gpio_hwmod_class, +- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, +- .mpu_irqs = omap44xx_gpio6_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), +- .main_clk = "gpio6_ick", ++static struct omap_hwmod omap44xx_spinlock_hwmod = { ++ .name = "spinlock", ++ .class = &omap44xx_spinlock_hwmod_class, + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, + }, + }, +- .opt_clks = gpio6_opt_clks, +- .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), +- .dev_attr = &gpio_dev_attr, +- .slaves = omap44xx_gpio6_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), ++ .slaves = omap44xx_spinlock_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + + /* +- * 'i2c' class +- * multimaster high-speed i2c controller ++ * 'timer' class ++ * general purpose timer module with accurate 1ms tick ++ * This class contains several variants: ['timer_1ms', 'timer'] + */ + +-static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { ++static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { ++ .rev_offs = 0x0000, + .sysc_offs = 0x0010, +- .syss_offs = 0x0090, ++ .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | +- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | +- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), +- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | +- SIDLE_SMART_WKUP), ++ SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | ++ SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, + }; + +-static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { +- .name = "i2c", +- .sysc = &omap44xx_i2c_sysc, ++static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { ++ .name = "timer", ++ .sysc = &omap44xx_timer_1ms_sysc, + }; + +-/* i2c1 */ +-static struct omap_hwmod omap44xx_i2c1_hwmod; +-static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { +- { .irq = 56 + OMAP44XX_IRQ_GIC_START }, ++static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { ++ .rev_offs = 0x0000, ++ .sysc_offs = 0x0010, ++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | ++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP), ++ .sysc_fields = &omap_hwmod_sysc_type2, + }; + +-static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { +- { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, +- { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, ++static struct omap_hwmod_class omap44xx_timer_hwmod_class = { ++ .name = "timer", ++ .sysc = &omap44xx_timer_sysc, + }; + +-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { ++/* timer1 */ ++static struct omap_hwmod omap44xx_timer1_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { ++ { .irq = 37 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { + { +- .pa_start = 0x48070000, +- .pa_end = 0x480700ff, ++ .pa_start = 0x4a318000, ++ .pa_end = 0x4a31807f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> i2c1 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { +- .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_i2c1_hwmod, +- .clk = "l4_div_ck", +- .addr = omap44xx_i2c1_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), ++/* l4_wkup -> timer1 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { ++ .master = &omap44xx_l4_wkup_hwmod, ++ .slave = &omap44xx_timer1_hwmod, ++ .clk = "l4_wkup_clk_mux_ck", ++ .addr = omap44xx_timer1_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* i2c1 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { +- &omap44xx_l4_per__i2c1, ++/* timer1 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { ++ &omap44xx_l4_wkup__timer1, + }; + +-static struct omap_hwmod omap44xx_i2c1_hwmod = { +- .name = "i2c1", +- .class = &omap44xx_i2c_hwmod_class, +- .flags = HWMOD_INIT_NO_RESET, +- .mpu_irqs = omap44xx_i2c1_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), +- .sdma_reqs = omap44xx_i2c1_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), +- .main_clk = "i2c1_fck", ++static struct omap_hwmod omap44xx_timer1_hwmod = { ++ .name = "timer1", ++ .class = &omap44xx_timer_1ms_hwmod_class, ++ .mpu_irqs = omap44xx_timer1_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), ++ .main_clk = "timer1_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + }, + }, +- .slaves = omap44xx_i2c1_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), ++ .slaves = omap44xx_timer1_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* i2c2 */ +-static struct omap_hwmod omap44xx_i2c2_hwmod; +-static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { +- { .irq = 57 + OMAP44XX_IRQ_GIC_START }, +-}; +- +-static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { +- { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, +- { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, ++/* timer2 */ ++static struct omap_hwmod omap44xx_timer2_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { ++ { .irq = 38 + OMAP44XX_IRQ_GIC_START }, + }; + +-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { ++static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { + { +- .pa_start = 0x48072000, +- .pa_end = 0x480720ff, ++ .pa_start = 0x48032000, ++ .pa_end = 0x4803207f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> i2c2 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { ++/* l4_per -> timer2 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { + .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_i2c2_hwmod, ++ .slave = &omap44xx_timer2_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_i2c2_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), ++ .addr = omap44xx_timer2_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* i2c2 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { +- &omap44xx_l4_per__i2c2, ++/* timer2 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { ++ &omap44xx_l4_per__timer2, + }; + +-static struct omap_hwmod omap44xx_i2c2_hwmod = { +- .name = "i2c2", +- .class = &omap44xx_i2c_hwmod_class, +- .flags = HWMOD_INIT_NO_RESET, +- .mpu_irqs = omap44xx_i2c2_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), +- .sdma_reqs = omap44xx_i2c2_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), +- .main_clk = "i2c2_fck", ++static struct omap_hwmod omap44xx_timer2_hwmod = { ++ .name = "timer2", ++ .class = &omap44xx_timer_1ms_hwmod_class, ++ .mpu_irqs = omap44xx_timer2_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs), ++ .main_clk = "timer2_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + }, + }, +- .slaves = omap44xx_i2c2_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), ++ .slaves = omap44xx_timer2_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* i2c3 */ +-static struct omap_hwmod omap44xx_i2c3_hwmod; +-static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { +- { .irq = 61 + OMAP44XX_IRQ_GIC_START }, +-}; +- +-static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { +- { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, +- { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, ++/* timer3 */ ++static struct omap_hwmod omap44xx_timer3_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { ++ { .irq = 39 + OMAP44XX_IRQ_GIC_START }, + }; + +-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { ++static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { + { +- .pa_start = 0x48060000, +- .pa_end = 0x480600ff, ++ .pa_start = 0x48034000, ++ .pa_end = 0x4803407f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> i2c3 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { ++/* l4_per -> timer3 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { + .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_i2c3_hwmod, ++ .slave = &omap44xx_timer3_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_i2c3_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), ++ .addr = omap44xx_timer3_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* i2c3 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { +- &omap44xx_l4_per__i2c3, ++/* timer3 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { ++ &omap44xx_l4_per__timer3, + }; + +-static struct omap_hwmod omap44xx_i2c3_hwmod = { +- .name = "i2c3", +- .class = &omap44xx_i2c_hwmod_class, +- .flags = HWMOD_INIT_NO_RESET, +- .mpu_irqs = omap44xx_i2c3_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), +- .sdma_reqs = omap44xx_i2c3_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), +- .main_clk = "i2c3_fck", ++static struct omap_hwmod omap44xx_timer3_hwmod = { ++ .name = "timer3", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer3_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs), ++ .main_clk = "timer3_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + }, + }, +- .slaves = omap44xx_i2c3_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), ++ .slaves = omap44xx_timer3_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* i2c4 */ +-static struct omap_hwmod omap44xx_i2c4_hwmod; +-static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { +- { .irq = 62 + OMAP44XX_IRQ_GIC_START }, +-}; +- +-static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { +- { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, +- { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, ++/* timer4 */ ++static struct omap_hwmod omap44xx_timer4_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { ++ { .irq = 40 + OMAP44XX_IRQ_GIC_START }, + }; + +-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { ++static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { + { +- .pa_start = 0x48350000, +- .pa_end = 0x483500ff, ++ .pa_start = 0x48036000, ++ .pa_end = 0x4803607f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_per -> i2c4 */ +-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { ++/* l4_per -> timer4 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { + .master = &omap44xx_l4_per_hwmod, +- .slave = &omap44xx_i2c4_hwmod, ++ .slave = &omap44xx_timer4_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_i2c4_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), ++ .addr = omap44xx_timer4_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* i2c4 slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { +- &omap44xx_l4_per__i2c4, ++/* timer4 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { ++ &omap44xx_l4_per__timer4, + }; + +-static struct omap_hwmod omap44xx_i2c4_hwmod = { +- .name = "i2c4", +- .class = &omap44xx_i2c_hwmod_class, +- .flags = HWMOD_INIT_NO_RESET, +- .mpu_irqs = omap44xx_i2c4_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), +- .sdma_reqs = omap44xx_i2c4_sdma_reqs, +- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), +- .main_clk = "i2c4_fck", ++static struct omap_hwmod omap44xx_timer4_hwmod = { ++ .name = "timer4", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer4_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs), ++ .main_clk = "timer4_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + }, + }, +- .slaves = omap44xx_i2c4_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), ++ .slaves = omap44xx_timer4_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* +- * 'iva' class +- * multi-standard video encoder/decoder hardware accelerator +- */ ++/* timer5 */ ++static struct omap_hwmod omap44xx_timer5_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { ++ { .irq = 41 + OMAP44XX_IRQ_GIC_START }, ++}; + +-static struct omap_hwmod_class omap44xx_iva_hwmod_class = { +- .name = "iva", ++static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { ++ { ++ .pa_start = 0x40138000, ++ .pa_end = 0x4013807f, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-/* iva */ +-static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { +- { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, +- { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, +- { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, ++/* l4_abe -> timer5 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer5_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer5_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs), ++ .user = OCP_USER_MPU, + }; + +-static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { +- { .name = "logic", .rst_shift = 2 }, ++static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { ++ { ++ .pa_start = 0x49038000, ++ .pa_end = 0x4903807f, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { +- { .name = "seq0", .rst_shift = 0 }, ++/* l4_abe -> timer5 (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer5_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer5_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs), ++ .user = OCP_USER_SDMA, + }; + +-static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { +- { .name = "seq1", .rst_shift = 1 }, ++/* timer5 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { ++ &omap44xx_l4_abe__timer5, ++ &omap44xx_l4_abe__timer5_dma, + }; + +-/* iva master ports */ +-static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { +- &omap44xx_iva__l3_main_2, +- &omap44xx_iva__l3_instr, ++static struct omap_hwmod omap44xx_timer5_hwmod = { ++ .name = "timer5", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer5_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs), ++ .main_clk = "timer5_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_timer5_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { ++/* timer6 */ ++static struct omap_hwmod omap44xx_timer6_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { ++ { .irq = 42 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { + { +- .pa_start = 0x5a000000, +- .pa_end = 0x5a07ffff, ++ .pa_start = 0x4013a000, ++ .pa_end = 0x4013a07f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l3_main_2 -> iva */ +-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { +- .master = &omap44xx_l3_main_2_hwmod, +- .slave = &omap44xx_iva_hwmod, +- .clk = "l3_div_ck", +- .addr = omap44xx_iva_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs), ++/* l4_abe -> timer6 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer6_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer6_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs), + .user = OCP_USER_MPU, + }; + +-/* iva slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { +- &omap44xx_dsp__iva, +- &omap44xx_l3_main_2__iva, ++static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { ++ { ++ .pa_start = 0x4903a000, ++ .pa_end = 0x4903a07f, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_abe -> timer6 (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer6_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer6_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs), ++ .user = OCP_USER_SDMA, ++}; ++ ++/* timer6 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { ++ &omap44xx_l4_abe__timer6, ++ &omap44xx_l4_abe__timer6_dma, + }; + +-/* Pseudo hwmod for reset control purpose only */ +-static struct omap_hwmod omap44xx_iva_seq0_hwmod = { +- .name = "iva_seq0", +- .class = &omap44xx_iva_hwmod_class, +- .flags = HWMOD_INIT_NO_RESET, +- .rst_lines = omap44xx_iva_seq0_resets, +- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), ++static struct omap_hwmod omap44xx_timer6_hwmod = { ++ .name = "timer6", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer6_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), ++ .main_clk = "timer6_fck", + .prcm = { + .omap4 = { +- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, ++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + }, + }, ++ .slaves = omap44xx_timer6_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* Pseudo hwmod for reset control purpose only */ +-static struct omap_hwmod omap44xx_iva_seq1_hwmod = { +- .name = "iva_seq1", +- .class = &omap44xx_iva_hwmod_class, +- .flags = HWMOD_INIT_NO_RESET, +- .rst_lines = omap44xx_iva_seq1_resets, +- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), +- .prcm = { +- .omap4 = { +- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, +- }, +- }, +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++/* timer7 */ ++static struct omap_hwmod omap44xx_timer7_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { ++ { .irq = 43 + OMAP44XX_IRQ_GIC_START }, + }; + +-static struct omap_hwmod omap44xx_iva_hwmod = { +- .name = "iva", +- .class = &omap44xx_iva_hwmod_class, +- .mpu_irqs = omap44xx_iva_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), +- .rst_lines = omap44xx_iva_resets, +- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), +- .main_clk = "iva_fck", +- .prcm = { +- .omap4 = { +- .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, +- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, +- }, ++static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { ++ { ++ .pa_start = 0x4013c000, ++ .pa_end = 0x4013c07f, ++ .flags = ADDR_TYPE_RT + }, +- .slaves = omap44xx_iva_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), +- .masters = omap44xx_iva_masters, +- .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), +- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* +- * 'mpu' class +- * mpu sub-system +- */ ++/* l4_abe -> timer7 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer7_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer7_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs), ++ .user = OCP_USER_MPU, ++}; + +-static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { +- .name = "mpu", ++static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { ++ { ++ .pa_start = 0x4903c000, ++ .pa_end = 0x4903c07f, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-/* mpu */ +-static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { +- { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, +- { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, +- { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, ++/* l4_abe -> timer7 (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer7_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer7_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs), ++ .user = OCP_USER_SDMA, + }; + +-/* mpu master ports */ +-static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { +- &omap44xx_mpu__l3_main_1, +- &omap44xx_mpu__l4_abe, +- &omap44xx_mpu__dmm, ++/* timer7 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { ++ &omap44xx_l4_abe__timer7, ++ &omap44xx_l4_abe__timer7_dma, + }; + +-static struct omap_hwmod omap44xx_mpu_hwmod = { +- .name = "mpu", +- .class = &omap44xx_mpu_hwmod_class, +- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), +- .mpu_irqs = omap44xx_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), +- .main_clk = "dpll_mpu_m2_ck", ++static struct omap_hwmod omap44xx_timer7_hwmod = { ++ .name = "timer7", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer7_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs), ++ .main_clk = "timer7_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + }, + }, +- .masters = omap44xx_mpu_masters, +- .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), ++ .slaves = omap44xx_timer7_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* +- * 'smartreflex' class +- * smartreflex module (monitor silicon performance and outputs a measure of +- * performance error) +- */ ++/* timer8 */ ++static struct omap_hwmod omap44xx_timer8_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { ++ { .irq = 44 + OMAP44XX_IRQ_GIC_START }, ++}; + +-/* The IP is not compliant to type1 / type2 scheme */ +-static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { +- .sidle_shift = 24, +- .enwkup_shift = 26, ++static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { ++ { ++ .pa_start = 0x4013e000, ++ .pa_end = 0x4013e07f, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { +- .sysc_offs = 0x0038, +- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), +- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | +- SIDLE_SMART_WKUP), +- .sysc_fields = &omap_hwmod_sysc_type_smartreflex, ++/* l4_abe -> timer8 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer8_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer8_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs), ++ .user = OCP_USER_MPU, + }; + +-static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { +- .name = "smartreflex", +- .sysc = &omap44xx_smartreflex_sysc, +- .rev = 2, ++static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { ++ { ++ .pa_start = 0x4903e000, ++ .pa_end = 0x4903e07f, ++ .flags = ADDR_TYPE_RT ++ }, + }; + +-/* smartreflex_core */ +-static struct omap_hwmod omap44xx_smartreflex_core_hwmod; +-static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { +- { .irq = 19 + OMAP44XX_IRQ_GIC_START }, ++/* l4_abe -> timer8 (dma) */ ++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { ++ .master = &omap44xx_l4_abe_hwmod, ++ .slave = &omap44xx_timer8_hwmod, ++ .clk = "ocp_abe_iclk", ++ .addr = omap44xx_timer8_dma_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs), ++ .user = OCP_USER_SDMA, + }; + +-static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { ++/* timer8 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { ++ &omap44xx_l4_abe__timer8, ++ &omap44xx_l4_abe__timer8_dma, ++}; ++ ++static struct omap_hwmod omap44xx_timer8_hwmod = { ++ .name = "timer8", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer8_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs), ++ .main_clk = "timer8_fck", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, ++ }, ++ }, ++ .slaves = omap44xx_timer8_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* timer9 */ ++static struct omap_hwmod omap44xx_timer9_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { ++ { .irq = 45 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { + { +- .pa_start = 0x4a0dd000, +- .pa_end = 0x4a0dd03f, ++ .pa_start = 0x4803e000, ++ .pa_end = 0x4803e07f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_cfg -> smartreflex_core */ +-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { +- .master = &omap44xx_l4_cfg_hwmod, +- .slave = &omap44xx_smartreflex_core_hwmod, ++/* l4_per -> timer9 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_timer9_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_smartreflex_core_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs), ++ .addr = omap44xx_timer9_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* smartreflex_core slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { +- &omap44xx_l4_cfg__smartreflex_core, ++/* timer9 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { ++ &omap44xx_l4_per__timer9, + }; + +-static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { +- .name = "smartreflex_core", +- .class = &omap44xx_smartreflex_hwmod_class, +- .mpu_irqs = omap44xx_smartreflex_core_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), +- .main_clk = "smartreflex_core_fck", +- .vdd_name = "core", ++static struct omap_hwmod omap44xx_timer9_hwmod = { ++ .name = "timer9", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer9_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs), ++ .main_clk = "timer9_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + }, + }, +- .slaves = omap44xx_smartreflex_core_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), ++ .slaves = omap44xx_timer9_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* smartreflex_iva */ +-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; +-static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { +- { .irq = 102 + OMAP44XX_IRQ_GIC_START }, ++/* timer10 */ ++static struct omap_hwmod omap44xx_timer10_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { ++ { .irq = 46 + OMAP44XX_IRQ_GIC_START }, + }; + +-static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { ++static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { + { +- .pa_start = 0x4a0db000, +- .pa_end = 0x4a0db03f, ++ .pa_start = 0x48086000, ++ .pa_end = 0x4808607f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_cfg -> smartreflex_iva */ +-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { +- .master = &omap44xx_l4_cfg_hwmod, +- .slave = &omap44xx_smartreflex_iva_hwmod, ++/* l4_per -> timer10 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_timer10_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_smartreflex_iva_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs), ++ .addr = omap44xx_timer10_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* smartreflex_iva slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { +- &omap44xx_l4_cfg__smartreflex_iva, ++/* timer10 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { ++ &omap44xx_l4_per__timer10, + }; + +-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { +- .name = "smartreflex_iva", +- .class = &omap44xx_smartreflex_hwmod_class, +- .mpu_irqs = omap44xx_smartreflex_iva_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), +- .main_clk = "smartreflex_iva_fck", +- .vdd_name = "iva", ++static struct omap_hwmod omap44xx_timer10_hwmod = { ++ .name = "timer10", ++ .class = &omap44xx_timer_1ms_hwmod_class, ++ .mpu_irqs = omap44xx_timer10_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs), ++ .main_clk = "timer10_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + }, + }, +- .slaves = omap44xx_smartreflex_iva_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), ++ .slaves = omap44xx_timer10_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +-/* smartreflex_mpu */ +-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; +-static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { +- { .irq = 18 + OMAP44XX_IRQ_GIC_START }, ++/* timer11 */ ++static struct omap_hwmod omap44xx_timer11_hwmod; ++static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { ++ { .irq = 47 + OMAP44XX_IRQ_GIC_START }, + }; + +-static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { ++static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { + { +- .pa_start = 0x4a0d9000, +- .pa_end = 0x4a0d903f, ++ .pa_start = 0x48088000, ++ .pa_end = 0x4808807f, + .flags = ADDR_TYPE_RT + }, + }; + +-/* l4_cfg -> smartreflex_mpu */ +-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { +- .master = &omap44xx_l4_cfg_hwmod, +- .slave = &omap44xx_smartreflex_mpu_hwmod, ++/* l4_per -> timer11 */ ++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { ++ .master = &omap44xx_l4_per_hwmod, ++ .slave = &omap44xx_timer11_hwmod, + .clk = "l4_div_ck", +- .addr = omap44xx_smartreflex_mpu_addrs, +- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs), ++ .addr = omap44xx_timer11_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, + }; + +-/* smartreflex_mpu slave ports */ +-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { +- &omap44xx_l4_cfg__smartreflex_mpu, ++/* timer11 slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { ++ &omap44xx_l4_per__timer11, + }; + +-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { +- .name = "smartreflex_mpu", +- .class = &omap44xx_smartreflex_hwmod_class, +- .mpu_irqs = omap44xx_smartreflex_mpu_irqs, +- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), +- .main_clk = "smartreflex_mpu_fck", +- .vdd_name = "mpu", ++static struct omap_hwmod omap44xx_timer11_hwmod = { ++ .name = "timer11", ++ .class = &omap44xx_timer_hwmod_class, ++ .mpu_irqs = omap44xx_timer11_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs), ++ .main_clk = "timer11_fck", + .prcm = { + .omap4 = { +- .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, ++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + }, + }, +- .slaves = omap44xx_smartreflex_mpu_slaves, +- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), ++ .slaves = omap44xx_timer11_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + }; + +@@ -1870,6 +4776,88 @@ + }; + + /* ++ * 'usb_otg_hs' class ++ * high-speed on-the-go universal serial bus (usb_otg_hs) controller ++ */ ++ ++static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { ++ .rev_offs = 0x0400, ++ .sysc_offs = 0x0404, ++ .syss_offs = 0x0408, ++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | ++ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | ++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), ++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | ++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | ++ MSTANDBY_SMART), ++ .sysc_fields = &omap_hwmod_sysc_type1, ++}; ++ ++static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { ++ .name = "usb_otg_hs", ++ .sysc = &omap44xx_usb_otg_hs_sysc, ++}; ++ ++/* usb_otg_hs */ ++static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { ++ { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, ++ { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, ++}; ++ ++/* usb_otg_hs master ports */ ++static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { ++ &omap44xx_usb_otg_hs__l3_main_2, ++}; ++ ++static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { ++ { ++ .pa_start = 0x4a0ab000, ++ .pa_end = 0x4a0ab003, ++ .flags = ADDR_TYPE_RT ++ }, ++}; ++ ++/* l4_cfg -> usb_otg_hs */ ++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { ++ .master = &omap44xx_l4_cfg_hwmod, ++ .slave = &omap44xx_usb_otg_hs_hwmod, ++ .clk = "l4_div_ck", ++ .addr = omap44xx_usb_otg_hs_addrs, ++ .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs), ++ .user = OCP_USER_MPU | OCP_USER_SDMA, ++}; ++ ++/* usb_otg_hs slave ports */ ++static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { ++ &omap44xx_l4_cfg__usb_otg_hs, ++}; ++ ++static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { ++ { .role = "xclk", .clk = "usb_otg_hs_xclk" }, ++}; ++ ++static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { ++ .name = "usb_otg_hs", ++ .class = &omap44xx_usb_otg_hs_hwmod_class, ++ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, ++ .mpu_irqs = omap44xx_usb_otg_hs_irqs, ++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs), ++ .main_clk = "usb_otg_hs_ick", ++ .prcm = { ++ .omap4 = { ++ .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, ++ }, ++ }, ++ .opt_clks = usb_otg_hs_opt_clks, ++ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), ++ .slaves = omap44xx_usb_otg_hs_slaves, ++ .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), ++ .masters = omap44xx_usb_otg_hs_masters, ++ .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), ++}; ++ ++/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition +@@ -2024,13 +5012,34 @@ + /* mpu_bus class */ + &omap44xx_mpu_private_hwmod, + ++ /* aess class */ ++/* &omap44xx_aess_hwmod, */ ++ ++ /* bandgap class */ ++ &omap44xx_bandgap_hwmod, ++ ++ /* counter class */ ++/* &omap44xx_counter_32k_hwmod, */ ++ + /* dma class */ + &omap44xx_dma_system_hwmod, + ++ /* dmic class */ ++ &omap44xx_dmic_hwmod, ++ + /* dsp class */ + &omap44xx_dsp_hwmod, + &omap44xx_dsp_c0_hwmod, + ++ /* dss class */ ++ &omap44xx_dss_hwmod, ++ &omap44xx_dss_dispc_hwmod, ++ &omap44xx_dss_dsi1_hwmod, ++ &omap44xx_dss_dsi2_hwmod, ++ &omap44xx_dss_hdmi_hwmod, ++ &omap44xx_dss_rfbi_hwmod, ++ &omap44xx_dss_venc_hwmod, ++ + /* gpio class */ + &omap44xx_gpio1_hwmod, + &omap44xx_gpio2_hwmod, +@@ -2039,17 +5048,56 @@ + &omap44xx_gpio5_hwmod, + &omap44xx_gpio6_hwmod, + ++ /* hsi class */ ++/* &omap44xx_hsi_hwmod, */ ++ + /* i2c class */ + &omap44xx_i2c1_hwmod, + &omap44xx_i2c2_hwmod, + &omap44xx_i2c3_hwmod, + &omap44xx_i2c4_hwmod, + ++ /* ipu class */ ++ &omap44xx_ipu_hwmod, ++ &omap44xx_ipu_c0_hwmod, ++ &omap44xx_ipu_c1_hwmod, ++ ++ /* iss class */ ++/* &omap44xx_iss_hwmod, */ ++ + /* iva class */ + &omap44xx_iva_hwmod, + &omap44xx_iva_seq0_hwmod, + &omap44xx_iva_seq1_hwmod, + ++ /* kbd class */ ++/* &omap44xx_kbd_hwmod, */ ++ ++ /* mailbox class */ ++ &omap44xx_mailbox_hwmod, ++ ++ /* mcbsp class */ ++ &omap44xx_mcbsp1_hwmod, ++ &omap44xx_mcbsp2_hwmod, ++ &omap44xx_mcbsp3_hwmod, ++ &omap44xx_mcbsp4_hwmod, ++ ++ /* mcpdm class */ ++/* &omap44xx_mcpdm_hwmod, */ ++ ++ /* mcspi class */ ++ &omap44xx_mcspi1_hwmod, ++ &omap44xx_mcspi2_hwmod, ++ &omap44xx_mcspi3_hwmod, ++ &omap44xx_mcspi4_hwmod, ++ ++ /* mmc class */ ++ &omap44xx_mmc1_hwmod, ++ &omap44xx_mmc2_hwmod, ++ &omap44xx_mmc3_hwmod, ++ &omap44xx_mmc4_hwmod, ++ &omap44xx_mmc5_hwmod, ++ + /* mpu class */ + &omap44xx_mpu_hwmod, + +@@ -2058,12 +5106,31 @@ + &omap44xx_smartreflex_iva_hwmod, + &omap44xx_smartreflex_mpu_hwmod, + ++ /* spinlock class */ ++ &omap44xx_spinlock_hwmod, ++ ++ /* timer class */ ++ &omap44xx_timer1_hwmod, ++ &omap44xx_timer2_hwmod, ++ &omap44xx_timer3_hwmod, ++ &omap44xx_timer4_hwmod, ++ &omap44xx_timer5_hwmod, ++ &omap44xx_timer6_hwmod, ++ &omap44xx_timer7_hwmod, ++ &omap44xx_timer8_hwmod, ++ &omap44xx_timer9_hwmod, ++ &omap44xx_timer10_hwmod, ++ &omap44xx_timer11_hwmod, ++ + /* uart class */ + &omap44xx_uart1_hwmod, + &omap44xx_uart2_hwmod, + &omap44xx_uart3_hwmod, + &omap44xx_uart4_hwmod, + ++ /* usb_otg_hs class */ ++ &omap44xx_usb_otg_hs_hwmod, ++ + /* wd_timer class */ + &omap44xx_wd_timer2_hwmod, + &omap44xx_wd_timer3_hwmod, +@@ -2073,6 +5140,6 @@ + + int __init omap44xx_hwmod_init(void) + { +- return omap_hwmod_init(omap44xx_hwmods); ++ return omap_hwmod_register(omap44xx_hwmods); + } + +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod.c 2011-03-09 13:19:09.827507277 +0100 +@@ -1,7 +1,7 @@ + /* + * omap_hwmod implementation for OMAP2/3/4 + * +- * Copyright (C) 2009-2010 Nokia Corporation ++ * Copyright (C) 2009-2011 Nokia Corporation + * + * Paul Walmsley, Benoît Cousson, Kevin Hilman + * +@@ -162,9 +162,6 @@ + /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ + static struct omap_hwmod *mpu_oh; + +-/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ +-static u8 inited; +- + + /* Private functions */ + +@@ -904,18 +901,16 @@ + * @oh: struct omap_hwmod * + * @data: not used; pass NULL + * +- * Called by omap_hwmod_late_init() (after omap2_clk_init()). +- * Resolves all clock names embedded in the hwmod. Returns -EINVAL if +- * the omap_hwmod has not yet been registered or if the clocks have +- * already been initialized, 0 on success, or a non-zero error on +- * failure. ++ * Called by omap_hwmod_setup_*() (after omap2_clk_init()). ++ * Resolves all clock names embedded in the hwmod. Returns 0 on ++ * success, or a negative error code on failure. + */ + static int _init_clocks(struct omap_hwmod *oh, void *data) + { + int ret = 0; + +- if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) +- return -EINVAL; ++ if (oh->_state != _HWMOD_STATE_REGISTERED) ++ return 0; + + pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); + +@@ -1354,14 +1349,16 @@ + * @oh: struct omap_hwmod * + * + * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh +- * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the +- * wrong state or returns 0. ++ * OCP_SYSCONFIG register. Returns 0. + */ + static int _setup(struct omap_hwmod *oh, void *data) + { + int i, r; + u8 postsetup_state; + ++ if (oh->_state != _HWMOD_STATE_CLKS_INITED) ++ return 0; ++ + /* Set iclk autoidle mode */ + if (oh->slaves_cnt > 0) { + for (i = 0; i < oh->slaves_cnt; i++) { +@@ -1455,7 +1452,7 @@ + */ + static int __init _register(struct omap_hwmod *oh) + { +- int ret, ms_id; ++ int ms_id; + + if (!oh || !oh->name || !oh->class || !oh->class->name || + (oh->_state != _HWMOD_STATE_UNKNOWN)) +@@ -1467,12 +1464,10 @@ + return -EEXIST; + + ms_id = _find_mpu_port_index(oh); +- if (!IS_ERR_VALUE(ms_id)) { ++ if (!IS_ERR_VALUE(ms_id)) + oh->_mpu_port_index = ms_id; +- oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); +- } else { ++ else + oh->_int_flags |= _HWMOD_NO_MPU_PORT; +- } + + list_add_tail(&oh->node, &omap_hwmod_list); + +@@ -1480,9 +1475,14 @@ + + oh->_state = _HWMOD_STATE_REGISTERED; + +- ret = 0; ++ /* ++ * XXX Rather than doing a strcmp(), this should test a flag ++ * set in the hwmod data, inserted by the autogenerator code. ++ */ ++ if (!strcmp(oh->name, MPU_INITIATOR_NAME)) ++ mpu_oh = oh; + +- return ret; ++ return 0; + } + + +@@ -1585,65 +1585,132 @@ + return ret; + } + +- + /** +- * omap_hwmod_init - init omap_hwmod code and register hwmods ++ * omap_hwmod_register - register an array of hwmods + * @ohs: pointer to an array of omap_hwmods to register + * + * Intended to be called early in boot before the clock framework is + * initialized. If @ohs is not null, will register all omap_hwmods +- * listed in @ohs that are valid for this chip. Returns -EINVAL if +- * omap_hwmod_init() has already been called or 0 otherwise. ++ * listed in @ohs that are valid for this chip. Returns 0. ++ */ ++int __init omap_hwmod_register(struct omap_hwmod **ohs) ++{ ++ int r, i; ++ ++ if (!ohs) ++ return 0; ++ ++ i = 0; ++ do { ++ if (!omap_chip_is(ohs[i]->omap_chip)) ++ continue; ++ ++ r = _register(ohs[i]); ++ WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, ++ r); ++ } while (ohs[++i]); ++ ++ return 0; ++} ++ ++/* ++ * _populate_mpu_rt_base - populate the virtual address for a hwmod ++ * ++ * Must be called only from omap_hwmod_setup_*() so ioremap works properly. ++ * Assumes the caller takes care of locking if needed. + */ +-int __init omap_hwmod_init(struct omap_hwmod **ohs) ++static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) ++{ ++ if (oh->_state != _HWMOD_STATE_REGISTERED) ++ return 0; ++ ++ if (oh->_int_flags & _HWMOD_NO_MPU_PORT) ++ return 0; ++ ++ oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); ++ if (!oh->_mpu_rt_va) ++ pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n", ++ __func__, oh->name); ++ ++ return 0; ++} ++ ++/** ++ * omap_hwmod_setup_one - set up a single hwmod ++ * @oh_name: const char * name of the already-registered hwmod to set up ++ * ++ * Must be called after omap2_clk_init(). Resolves the struct clk ++ * names to struct clk pointers for each registered omap_hwmod. Also ++ * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon ++ * success. ++ */ ++int __init omap_hwmod_setup_one(const char *oh_name) + { + struct omap_hwmod *oh; + int r; + +- if (inited) ++ pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); ++ ++ if (!mpu_oh) { ++ pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", ++ oh_name, MPU_INITIATOR_NAME); + return -EINVAL; ++ } + +- inited = 1; ++ oh = _lookup(oh_name); ++ if (!oh) { ++ WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); ++ return -EINVAL; ++ } + +- if (!ohs) +- return 0; ++ if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) ++ omap_hwmod_setup_one(MPU_INITIATOR_NAME); + +- oh = *ohs; +- while (oh) { +- if (omap_chip_is(oh->omap_chip)) { +- r = _register(oh); +- WARN(r, "omap_hwmod: %s: _register returned " +- "%d\n", oh->name, r); +- } +- oh = *++ohs; ++ r = _populate_mpu_rt_base(oh, NULL); ++ if (IS_ERR_VALUE(r)) { ++ WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); ++ return -EINVAL; ++ } ++ ++ r = _init_clocks(oh, NULL); ++ if (IS_ERR_VALUE(r)) { ++ WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); ++ return -EINVAL; + } + ++ _setup(oh, NULL); ++ + return 0; + } + + /** +- * omap_hwmod_late_init - do some post-clock framework initialization ++ * omap_hwmod_setup - do some post-clock framework initialization + * + * Must be called after omap2_clk_init(). Resolves the struct clk names + * to struct clk pointers for each registered omap_hwmod. Also calls +- * _setup() on each hwmod. Returns 0. ++ * _setup() on each hwmod. Returns 0 upon success. + */ +-int omap_hwmod_late_init(void) ++static int __init omap_hwmod_setup_all(void) + { + int r; + +- /* XXX check return value */ +- r = omap_hwmod_for_each(_init_clocks, NULL); +- WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); ++ if (!mpu_oh) { ++ pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", ++ __func__, MPU_INITIATOR_NAME); ++ return -EINVAL; ++ } ++ ++ r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); + +- mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); +- WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", +- MPU_INITIATOR_NAME); ++ r = omap_hwmod_for_each(_init_clocks, NULL); ++ WARN(IS_ERR_VALUE(r), ++ "omap_hwmod: %s: _init_clocks failed\n", __func__); + + omap_hwmod_for_each(_setup, NULL); + + return 0; + } ++core_initcall(omap_hwmod_setup_all); + + /** + * omap_hwmod_enable - enable an omap_hwmod +@@ -1862,6 +1929,7 @@ + os = oh->slaves[i]; + + for (j = 0; j < os->addr_cnt; j++) { ++ (res + r)->name = (os->addr + j)->name; + (res + r)->start = (os->addr + j)->pa_start; + (res + r)->end = (os->addr + j)->pa_end; + (res + r)->flags = IORESOURCE_MEM; +@@ -2162,11 +2230,11 @@ + * @oh: struct omap_hwmod * + * @state: state that _setup() should leave the hwmod in + * +- * Sets the hwmod state that @oh will enter at the end of _setup() (called by +- * omap_hwmod_late_init()). Only valid to call between calls to +- * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or +- * -EINVAL if there is a problem with the arguments or if the hwmod is +- * in the wrong state. ++ * Sets the hwmod state that @oh will enter at the end of _setup() ++ * (called by omap_hwmod_setup_*()). Only valid to call between ++ * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns ++ * 0 upon success or -EINVAL if there is a problem with the arguments ++ * or if the hwmod is in the wrong state. + */ + int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) + { +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_phy_internal.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_phy_internal.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_phy_internal.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_phy_internal.c 2011-03-09 13:19:09.830507217 +0100 +@@ -29,6 +29,7 @@ + #include + + #include ++#include "control.h" + + /* OMAP control module register for UTMI PHY */ + #define CONTROL_DEV_CONF 0x300 +@@ -147,3 +148,95 @@ + + return 0; + } ++ ++void am35x_musb_reset(void) ++{ ++ u32 regval; ++ ++ /* Reset the musb interface */ ++ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); ++ ++ regval |= AM35XX_USBOTGSS_SW_RST; ++ omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); ++ ++ regval &= ~AM35XX_USBOTGSS_SW_RST; ++ omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); ++ ++ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); ++} ++ ++void am35x_musb_phy_power(u8 on) ++{ ++ unsigned long timeout = jiffies + msecs_to_jiffies(100); ++ u32 devconf2; ++ ++ if (on) { ++ /* ++ * Start the on-chip PHY and its PLL. ++ */ ++ devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); ++ ++ devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); ++ devconf2 |= CONF2_PHY_PLLON; ++ ++ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); ++ ++ pr_info(KERN_INFO "Waiting for PHY clock good...\n"); ++ while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) ++ & CONF2_PHYCLKGD)) { ++ cpu_relax(); ++ ++ if (time_after(jiffies, timeout)) { ++ pr_err(KERN_ERR "musb PHY clock good timed out\n"); ++ break; ++ } ++ } ++ } else { ++ /* ++ * Power down the on-chip PHY. ++ */ ++ devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); ++ ++ devconf2 &= ~CONF2_PHY_PLLON; ++ devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; ++ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); ++ } ++} ++ ++void am35x_musb_clear_irq(void) ++{ ++ u32 regval; ++ ++ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); ++ regval |= AM35XX_USBOTGSS_INT_CLR; ++ omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); ++ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); ++} ++ ++void am35x_musb_set_mode(u8 musb_mode) ++{ ++ u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); ++ ++ devconf2 &= ~CONF2_OTGMODE; ++ switch (musb_mode) { ++#ifdef CONFIG_USB_MUSB_HDRC_HCD ++ case MUSB_HOST: /* Force VBUS valid, ID = 0 */ ++ devconf2 |= CONF2_FORCE_HOST; ++ break; ++#endif ++#ifdef CONFIG_USB_GADGET_MUSB_HDRC ++ case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ ++ devconf2 |= CONF2_FORCE_DEVICE; ++ break; ++#endif ++#ifdef CONFIG_USB_MUSB_OTG ++ case MUSB_OTG: /* Don't override the VBUS/ID comparators */ ++ devconf2 |= CONF2_NO_OVERRIDE; ++ break; ++#endif ++ default: ++ pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); ++ } ++ ++ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); ++} +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/opp2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/opp2xxx.h +--- linux-2.6.38-rc7/arch/arm/mach-omap2/opp2xxx.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/opp2xxx.h 2011-03-09 13:19:09.831507196 +0100 +@@ -418,7 +418,7 @@ + + extern const struct prcm_config omap2420_rate_table[]; + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + extern const struct prcm_config omap2430_rate_table[]; + #else + #define omap2430_rate_table NULL +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/powerdomains2xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/powerdomains2xxx_data.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/powerdomains2xxx_data.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/powerdomains2xxx_data.c 2011-03-09 13:19:09.835507113 +0100 +@@ -78,7 +78,7 @@ + * 2430-specific powerdomains + */ + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + + /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ + +@@ -97,7 +97,7 @@ + }, + }; + +-#endif /* CONFIG_ARCH_OMAP2430 */ ++#endif /* CONFIG_SOC_OMAP2430 */ + + /* As powerdomains are added or removed above, this list must also be changed */ + static struct powerdomain *powerdomains_omap2xxx[] __initdata = { +@@ -111,7 +111,7 @@ + &core_24xx_pwrdm, + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + &mdm_pwrdm, + #endif + NULL +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/prcm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/prcm.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm.c 2011-03-09 13:19:09.836507094 +0100 +@@ -24,6 +24,7 @@ + #include + #include + ++#include + #include + #include + #include +@@ -57,7 +58,7 @@ + EXPORT_SYMBOL(omap_prcm_get_reset_sources); + + /* Resets clock rates and reboots the system. Only called from system.h */ +-void omap_prcm_arch_reset(char mode, const char *cmd) ++static void omap_prcm_arch_reset(char mode, const char *cmd) + { + s16 prcm_offs = 0; + +@@ -108,6 +109,8 @@ + omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ + } + ++void (*arch_reset)(char, const char *) = omap_prcm_arch_reset; ++ + /** + * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness + * @reg: physical address of module IDLEST register +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/prcm-common.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm-common.h +--- linux-2.6.38-rc7/arch/arm/mach-omap2/prcm-common.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm-common.h 2011-03-09 13:19:09.836507094 +0100 +@@ -121,6 +121,10 @@ + #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) + #define OMAP24XX_ST_MCSPI1_SHIFT 17 + #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) ++#define OMAP24XX_ST_MCBSP2_SHIFT 16 ++#define OMAP24XX_ST_MCBSP2_MASK (1 << 16) ++#define OMAP24XX_ST_MCBSP1_SHIFT 15 ++#define OMAP24XX_ST_MCBSP1_MASK (1 << 15) + #define OMAP24XX_ST_GPT12_SHIFT 14 + #define OMAP24XX_ST_GPT12_MASK (1 << 14) + #define OMAP24XX_ST_GPT11_SHIFT 13 +@@ -191,6 +195,8 @@ + #define OMAP3430_AUTOIDLE_MASK (1 << 0) + + /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ ++#define OMAP3430_EN_MMC3_MASK (1 << 30) ++#define OMAP3430_EN_MMC3_SHIFT 30 + #define OMAP3430_EN_MMC2_MASK (1 << 25) + #define OMAP3430_EN_MMC2_SHIFT 25 + #define OMAP3430_EN_MMC1_MASK (1 << 24) +@@ -231,6 +237,8 @@ + #define OMAP3430_EN_HSOTGUSB_SHIFT 4 + + /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ ++#define OMAP3430_ST_MMC3_SHIFT 30 ++#define OMAP3430_ST_MMC3_MASK (1 << 30) + #define OMAP3430_ST_MMC2_SHIFT 25 + #define OMAP3430_ST_MMC2_MASK (1 << 25) + #define OMAP3430_ST_MMC1_SHIFT 24 +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/serial.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/serial.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/serial.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/serial.c 2011-03-09 13:19:09.841506993 +0100 +@@ -486,7 +486,7 @@ + mod_timer(&uart->timer, jiffies + uart->timeout); + omap_uart_smart_idle_enable(uart, 0); + +- if (cpu_is_omap34xx()) { ++ if (cpu_is_omap34xx() && !cpu_is_ti816x()) { + u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; + u32 wk_mask = 0; + u32 padconf = 0; +@@ -655,7 +655,7 @@ + } + #endif + +-void __init omap_serial_early_init(void) ++static int __init omap_serial_early_init(void) + { + int i = 0; + +@@ -672,7 +672,7 @@ + + uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); + if (WARN_ON(!uart)) +- return; ++ return -ENODEV; + + uart->oh = oh; + uart->num = i++; +@@ -680,7 +680,7 @@ + num_uarts++; + + /* +- * NOTE: omap_hwmod_init() has not yet been called, ++ * NOTE: omap_hwmod_setup*() has not yet been called, + * so no hwmod functions will work yet. + */ + +@@ -691,7 +691,10 @@ + */ + uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; + } while (1); ++ ++ return 0; + } ++core_initcall(omap_serial_early_init); + + /** + * omap_serial_init_port() - initialize single serial port +@@ -759,13 +762,13 @@ + p->private_data = uart; + + /* +- * omap44xx: Never read empty UART fifo ++ * omap44xx, ti816x: Never read empty UART fifo + * omap3xxx: Never read empty UART fifo on UARTs + * with IP rev >=0x52 + */ + uart->regshift = p->regshift; + uart->membase = p->membase; +- if (cpu_is_omap44xx()) ++ if (cpu_is_omap44xx() || cpu_is_ti816x()) + uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; + else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) + >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) +@@ -847,7 +850,7 @@ + } + + /* Enable the MDR1 errata for OMAP3 */ +- if (cpu_is_omap34xx()) ++ if (cpu_is_omap34xx() && !cpu_is_ti816x()) + uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; + } + +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/timer-gp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/timer-gp.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/timer-gp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/timer-gp.c 2011-03-09 13:19:09.844506932 +0100 +@@ -40,10 +40,11 @@ + #include + #include + #include ++#include ++#include + + #include "timer-gp.h" + +-#include + + /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ + #define MAX_GPTIMER_ID 12 +@@ -133,9 +134,13 @@ + { + u32 tick_rate; + int src; ++ char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */ + + inited = 1; + ++ sprintf(clockevent_hwmod_name, "timer%d", gptimer_id); ++ omap_hwmod_setup_one(clockevent_hwmod_name); ++ + gptimer = omap_dm_timer_request_specific(gptimer_id); + BUG_ON(gptimer == NULL); + gptimer_wakeup = gptimer; +diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/usb-musb.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/usb-musb.c +--- linux-2.6.38-rc7/arch/arm/mach-omap2/usb-musb.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/usb-musb.c 2011-03-09 13:19:09.844506932 +0100 +@@ -30,118 +30,11 @@ + #include + #include + #include +-#include "control.h" ++#include ++#include "mux.h" + + #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) + +-static void am35x_musb_reset(void) +-{ +- u32 regval; +- +- /* Reset the musb interface */ +- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); +- +- regval |= AM35XX_USBOTGSS_SW_RST; +- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); +- +- regval &= ~AM35XX_USBOTGSS_SW_RST; +- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); +- +- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); +-} +- +-static void am35x_musb_phy_power(u8 on) +-{ +- unsigned long timeout = jiffies + msecs_to_jiffies(100); +- u32 devconf2; +- +- if (on) { +- /* +- * Start the on-chip PHY and its PLL. +- */ +- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); +- +- devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); +- devconf2 |= CONF2_PHY_PLLON; +- +- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); +- +- pr_info(KERN_INFO "Waiting for PHY clock good...\n"); +- while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) +- & CONF2_PHYCLKGD)) { +- cpu_relax(); +- +- if (time_after(jiffies, timeout)) { +- pr_err(KERN_ERR "musb PHY clock good timed out\n"); +- break; +- } +- } +- } else { +- /* +- * Power down the on-chip PHY. +- */ +- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); +- +- devconf2 &= ~CONF2_PHY_PLLON; +- devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; +- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); +- } +-} +- +-static void am35x_musb_clear_irq(void) +-{ +- u32 regval; +- +- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +- regval |= AM35XX_USBOTGSS_INT_CLR; +- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); +- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +-} +- +-static void am35x_musb_set_mode(u8 musb_mode) +-{ +- u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); +- +- devconf2 &= ~CONF2_OTGMODE; +- switch (musb_mode) { +-#ifdef CONFIG_USB_MUSB_HDRC_HCD +- case MUSB_HOST: /* Force VBUS valid, ID = 0 */ +- devconf2 |= CONF2_FORCE_HOST; +- break; +-#endif +-#ifdef CONFIG_USB_GADGET_MUSB_HDRC +- case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ +- devconf2 |= CONF2_FORCE_DEVICE; +- break; +-#endif +-#ifdef CONFIG_USB_MUSB_OTG +- case MUSB_OTG: /* Don't override the VBUS/ID comparators */ +- devconf2 |= CONF2_NO_OVERRIDE; +- break; +-#endif +- default: +- pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); +- } +- +- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); +-} +- +-static struct resource musb_resources[] = { +- [0] = { /* start and end set dynamically */ +- .flags = IORESOURCE_MEM, +- }, +- [1] = { /* general IRQ */ +- .start = INT_243X_HS_USB_MC, +- .flags = IORESOURCE_IRQ, +- .name = "mc", +- }, +- [2] = { /* DMA IRQ */ +- .start = INT_243X_HS_USB_DMA, +- .flags = IORESOURCE_IRQ, +- .name = "dma", +- }, +-}; +- + static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, +@@ -169,38 +62,65 @@ + + static u64 musb_dmamask = DMA_BIT_MASK(32); + +-static struct platform_device musb_device = { +- .name = "musb-omap2430", +- .id = -1, +- .dev = { +- .dma_mask = &musb_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- .platform_data = &musb_plat, ++static struct omap_device_pm_latency omap_musb_latency[] = { ++ { ++ .deactivate_func = omap_device_idle_hwmods, ++ .activate_func = omap_device_enable_hwmods, ++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +- .num_resources = ARRAY_SIZE(musb_resources), +- .resource = musb_resources, + }; + ++static void usb_musb_mux_init(struct omap_musb_board_data *board_data) ++{ ++ switch (board_data->interface_type) { ++ case MUSB_INTERFACE_UTMI: ++ omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT); ++ omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT); ++ break; ++ case MUSB_INTERFACE_ULPI: ++ omap_mux_init_signal("usba0_ulpiphy_clk", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_stp", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dir", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_nxt", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat0", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat1", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat2", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat3", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat4", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat5", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat6", ++ OMAP_PIN_INPUT_PULLDOWN); ++ omap_mux_init_signal("usba0_ulpiphy_dat7", ++ OMAP_PIN_INPUT_PULLDOWN); ++ break; ++ default: ++ break; ++ } ++} ++ + void __init usb_musb_init(struct omap_musb_board_data *board_data) + { +- if (cpu_is_omap243x()) { +- musb_resources[0].start = OMAP243X_HS_BASE; +- } else if (cpu_is_omap3517() || cpu_is_omap3505()) { +- musb_device.name = "musb-am35x"; +- musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; +- musb_resources[1].start = INT_35XX_USBOTG_IRQ; +- board_data->set_phy_power = am35x_musb_phy_power; +- board_data->clear_irq = am35x_musb_clear_irq; +- board_data->set_mode = am35x_musb_set_mode; +- board_data->reset = am35x_musb_reset; +- } else if (cpu_is_omap34xx()) { +- musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; ++ struct omap_hwmod *oh; ++ struct omap_device *od; ++ struct platform_device *pdev; ++ struct device *dev; ++ int bus_id = -1; ++ const char *oh_name, *name; ++ ++ if (cpu_is_omap3517() || cpu_is_omap3505()) { + } else if (cpu_is_omap44xx()) { +- musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; +- musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; +- musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; ++ usb_musb_mux_init(board_data); + } +- musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; + + /* + * REVISIT: This line can be removed once all the platforms using +@@ -212,8 +132,35 @@ + musb_plat.mode = board_data->mode; + musb_plat.extvbus = board_data->extvbus; + +- if (platform_device_register(&musb_device) < 0) +- printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); ++ if (cpu_is_omap3517() || cpu_is_omap3505()) { ++ oh_name = "am35x_otg_hs"; ++ name = "musb-am35x"; ++ } else { ++ oh_name = "usb_otg_hs"; ++ name = "musb-omap2430"; ++ } ++ ++ oh = omap_hwmod_lookup(oh_name); ++ if (!oh) { ++ pr_err("Could not look up %s\n", oh_name); ++ return; ++ } ++ ++ od = omap_device_build(name, bus_id, oh, &musb_plat, ++ sizeof(musb_plat), omap_musb_latency, ++ ARRAY_SIZE(omap_musb_latency), false); ++ if (IS_ERR(od)) { ++ pr_err("Could not build omap_device for %s %s\n", ++ name, oh_name); ++ return; ++ } ++ ++ pdev = &od->pdev; ++ dev = &pdev->dev; ++ get_device(dev); ++ dev->dma_mask = &musb_dmamask; ++ dev->coherent_dma_mask = musb_dmamask; ++ put_device(dev); + } + + #else +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/common.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/common.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/common.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/common.c 2011-03-09 13:19:10.088501983 +0100 +@@ -24,10 +24,11 @@ + + #define NO_LENGTH_CHECK 0xffffffff + +-struct omap_board_config_kernel *omap_board_config; ++struct omap_board_config_kernel *omap_board_config __initdata; + int omap_board_config_size; + +-static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) ++static const void *__init get_config(u16 tag, size_t len, ++ int skip, size_t *len_out) + { + struct omap_board_config_kernel *kinfo = NULL; + int i; +@@ -49,17 +50,15 @@ + return kinfo->data; + } + +-const void *__omap_get_config(u16 tag, size_t len, int nr) ++const void *__init __omap_get_config(u16 tag, size_t len, int nr) + { + return get_config(tag, len, nr, NULL); + } +-EXPORT_SYMBOL(__omap_get_config); + +-const void *omap_get_var_config(u16 tag, size_t *len) ++const void *__init omap_get_var_config(u16 tag, size_t *len) + { + return get_config(tag, NO_LENGTH_CHECK, 0, len); + } +-EXPORT_SYMBOL(omap_get_var_config); + + void __init omap_reserve(void) + { +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/counter_32k.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/counter_32k.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/counter_32k.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/counter_32k.c 2011-03-09 13:19:10.088501983 +0100 +@@ -54,7 +54,7 @@ + #define omap16xx_32k_read NULL + #endif + +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + static cycle_t notrace omap2420_32k_read(struct clocksource *cs) + { + return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; +@@ -63,7 +63,7 @@ + #define omap2420_32k_read NULL + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + static cycle_t notrace omap2430_32k_read(struct clocksource *cs) + { + return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/cpu-omap.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/cpu-omap.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/cpu-omap.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/cpu-omap.c 2011-03-09 13:19:10.088501983 +0100 +@@ -101,7 +101,7 @@ + return ret; + } + +-static int __init omap_cpu_init(struct cpufreq_policy *policy) ++static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) + { + int result = 0; + +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/devices.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/devices.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/devices.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/devices.c 2011-03-09 13:19:10.089501963 +0100 +@@ -35,8 +35,8 @@ + + static struct platform_device **omap_mcbsp_devices; + +-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, +- int size) ++void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, ++ struct omap_mcbsp_platform_data *config, int size) + { + int i; + +@@ -54,6 +54,8 @@ + new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); + if (!new_mcbsp) + continue; ++ platform_device_add_resources(new_mcbsp, &res[i * res_count], ++ res_count); + new_mcbsp->dev.platform_data = &config[i]; + ret = platform_device_add(new_mcbsp); + if (ret) { +@@ -65,8 +67,8 @@ + } + + #else +-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, +- int size) ++void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, ++ struct omap_mcbsp_platform_data *config, int size) + { } + #endif + +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/dma.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/dma.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/dma.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/dma.c 2011-03-09 13:19:10.090501943 +0100 +@@ -134,7 +134,7 @@ + + #ifdef CONFIG_ARCH_OMAP15XX + /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ +-int omap_dma_in_1510_mode(void) ++static int omap_dma_in_1510_mode(void) + { + return enable_1510_mode; + } +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/i2c.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/i2c.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/i2c.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/i2c.c 2011-03-09 13:19:10.091501922 +0100 +@@ -112,6 +112,7 @@ + } + + ++#ifdef CONFIG_ARCH_OMAP2PLUS + /* + * XXX This function is a temporary compatibility wrapper - only + * needed until the I2C driver can be converted to call +@@ -130,7 +131,6 @@ + }, + }; + +-#ifdef CONFIG_ARCH_OMAP2PLUS + static inline int omap2_i2c_add_bus(int bus_id) + { + int l; +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/board.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/board.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/board.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/board.h 2011-03-09 13:19:10.092501901 +0100 +@@ -151,14 +151,14 @@ + const void *data; + }; + +-extern const void *__omap_get_config(u16 tag, size_t len, int nr); ++extern const void *__init __omap_get_config(u16 tag, size_t len, int nr); + + #define omap_get_config(tag, type) \ + ((const type *) __omap_get_config((tag), sizeof(type), 0)) + #define omap_get_nr_config(tag, type, nr) \ + ((const type *) __omap_get_config((tag), sizeof(type), (nr))) + +-extern const void *omap_get_var_config(u16 tag, size_t *len); ++extern const void *__init omap_get_var_config(u16 tag, size_t *len); + + extern struct omap_board_config_kernel *omap_board_config; + extern int omap_board_config_size; +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clkdev_omap.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clkdev_omap.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clkdev_omap.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clkdev_omap.h 2011-03-09 13:19:10.093501880 +0100 +@@ -38,6 +38,7 @@ + #define CK_3517 (1 << 9) + #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ + #define CK_443X (1 << 11) ++#define CK_TI816X (1 << 12) + + + #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clock.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clock.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clock.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clock.h 2011-03-09 13:19:10.093501880 +0100 +@@ -53,6 +53,7 @@ + #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ + #define RATE_IN_36XX (1 << 4) + #define RATE_IN_4430 (1 << 5) ++#define RATE_IN_TI816X (1 << 6) + + #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) + #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/common.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/common.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/common.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/common.h 2011-03-09 13:19:10.093501880 +0100 +@@ -66,6 +66,7 @@ + void omap2_set_globals_243x(void); + void omap2_set_globals_3xxx(void); + void omap2_set_globals_443x(void); ++void omap2_set_globals_ti816x(void); + + /* These get called from omap2_set_globals_xxxx(), do not call these */ + void omap2_set_globals_tap(struct omap_globals *); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/cpu.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/cpu.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/cpu.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/cpu.h 2011-03-09 13:19:10.093501880 +0100 +@@ -5,7 +5,7 @@ + * + * Copyright (C) 2004, 2008 Nokia Corporation + * +- * Copyright (C) 2009 Texas Instruments. ++ * Copyright (C) 2009-11 Texas Instruments. + * + * Written by Tony Lindgren + * +@@ -105,6 +105,12 @@ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ + } + ++#define IS_TI_SUBCLASS(subclass, id) \ ++static inline int is_ti ##subclass (void) \ ++{ \ ++ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ ++} ++ + IS_OMAP_CLASS(7xx, 0x07) + IS_OMAP_CLASS(15xx, 0x15) + IS_OMAP_CLASS(16xx, 0x16) +@@ -118,6 +124,8 @@ + IS_OMAP_SUBCLASS(363x, 0x363) + IS_OMAP_SUBCLASS(443x, 0x443) + ++IS_TI_SUBCLASS(816x, 0x816) ++ + #define cpu_is_omap7xx() 0 + #define cpu_is_omap15xx() 0 + #define cpu_is_omap16xx() 0 +@@ -126,6 +134,7 @@ + #define cpu_is_omap243x() 0 + #define cpu_is_omap34xx() 0 + #define cpu_is_omap343x() 0 ++#define cpu_is_ti816x() 0 + #define cpu_is_omap44xx() 0 + #define cpu_is_omap443x() 0 + +@@ -170,11 +179,11 @@ + # undef cpu_is_omap24xx + # define cpu_is_omap24xx() is_omap24xx() + # endif +-# if defined (CONFIG_ARCH_OMAP2420) ++# if defined (CONFIG_SOC_OMAP2420) + # undef cpu_is_omap242x + # define cpu_is_omap242x() is_omap242x() + # endif +-# if defined (CONFIG_ARCH_OMAP2430) ++# if defined (CONFIG_SOC_OMAP2430) + # undef cpu_is_omap243x + # define cpu_is_omap243x() is_omap243x() + # endif +@@ -189,11 +198,11 @@ + # undef cpu_is_omap24xx + # define cpu_is_omap24xx() 1 + # endif +-# if defined(CONFIG_ARCH_OMAP2420) ++# if defined(CONFIG_SOC_OMAP2420) + # undef cpu_is_omap242x + # define cpu_is_omap242x() 1 + # endif +-# if defined(CONFIG_ARCH_OMAP2430) ++# if defined(CONFIG_SOC_OMAP2430) + # undef cpu_is_omap243x + # define cpu_is_omap243x() 1 + # endif +@@ -201,7 +210,7 @@ + # undef cpu_is_omap34xx + # define cpu_is_omap34xx() 1 + # endif +-# if defined(CONFIG_ARCH_OMAP3430) ++# if defined(CONFIG_SOC_OMAP3430) + # undef cpu_is_omap343x + # define cpu_is_omap343x() 1 + # endif +@@ -330,6 +339,7 @@ + # undef cpu_is_omap3530 + # undef cpu_is_omap3505 + # undef cpu_is_omap3517 ++# undef cpu_is_ti816x + # define cpu_is_omap3430() is_omap3430() + # define cpu_is_omap3503() (cpu_is_omap3430() && \ + (!omap3_has_iva()) && \ +@@ -345,6 +355,7 @@ + # define cpu_is_omap3517() is_omap3517() + # undef cpu_is_omap3630 + # define cpu_is_omap3630() is_omap363x() ++# define cpu_is_ti816x() is_ti816x() + #endif + + # if defined(CONFIG_ARCH_OMAP4) +@@ -389,9 +400,15 @@ + #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) + #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) + ++#define TI816X_CLASS 0x81600034 ++#define TI8168_REV_ES1_0 TI816X_CLASS ++#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) ++ + #define OMAP443X_CLASS 0x44300044 +-#define OMAP4430_REV_ES1_0 OMAP443X_CLASS +-#define OMAP4430_REV_ES2_0 0x44301044 ++#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) ++#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) ++#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) ++#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) + + /* + * omap_chip bits +@@ -419,11 +436,16 @@ + #define CHIP_IS_OMAP3630ES1_1 (1 << 9) + #define CHIP_IS_OMAP3630ES1_2 (1 << 10) + #define CHIP_IS_OMAP4430ES2 (1 << 11) ++#define CHIP_IS_OMAP4430ES2_1 (1 << 12) ++#define CHIP_IS_OMAP4430ES2_2 (1 << 13) ++#define CHIP_IS_TI816X (1 << 14) + + #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) + +-#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ +- CHIP_IS_OMAP4430ES2) ++#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ ++ CHIP_IS_OMAP4430ES2 | \ ++ CHIP_IS_OMAP4430ES2_1 | \ ++ CHIP_IS_OMAP4430ES2_2) + + /* + * "GE" here represents "greater than or equal to" in terms of ES +@@ -455,6 +477,7 @@ + #define OMAP3_HAS_ISP BIT(4) + #define OMAP3_HAS_192MHZ_CLK BIT(5) + #define OMAP3_HAS_IO_WAKEUP BIT(6) ++#define OMAP3_HAS_SDRC BIT(7) + + #define OMAP3_HAS_FEATURE(feat,flag) \ + static inline unsigned int omap3_has_ ##feat(void) \ +@@ -469,5 +492,6 @@ + OMAP3_HAS_FEATURE(isp, ISP) + OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) + OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) ++OMAP3_HAS_FEATURE(sdrc, SDRC) + + #endif +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/display.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/display.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/display.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/display.h 2011-03-09 13:19:10.094501859 +0100 +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + #include + + #define DISPC_IRQ_FRAMEDONE (1 << 0) +@@ -226,6 +227,23 @@ + struct omap_dss_device *default_device; + }; + ++#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS) ++/* Init with the board info */ ++extern int omap_display_init(struct omap_dss_board_info *board_data); ++#else ++static inline int omap_display_init(struct omap_dss_board_info *board_data) ++{ ++ return 0; ++} ++#endif ++ ++struct omap_display_platform_data { ++ struct omap_dss_board_info *board_data; ++ /* TODO: Additional members to be added when PM is considered */ ++ ++ bool (*opt_clock_available)(const char *clk_role); ++}; ++ + struct omap_video_timings { + /* Unit: pixels */ + u16 x_res; +@@ -385,8 +403,8 @@ + struct { + u16 regn; + u16 regm; +- u16 regm3; +- u16 regm4; ++ u16 regm_dispc; ++ u16 regm_dsi; + + u16 lp_clk_div; + +@@ -544,6 +562,9 @@ + int channel, + u16 x, u16 y, u16 w, u16 h, + void (*callback)(int, void *), void *data); ++int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); ++int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); ++void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); + + int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); + void omapdss_dsi_display_disable(struct omap_dss_device *dssdev); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/dmtimer.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/dmtimer.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/dmtimer.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/dmtimer.h 2011-03-09 13:19:10.094501859 +0100 +@@ -3,6 +3,12 @@ + * + * OMAP Dual-Mode Timers + * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ ++ * Tarun Kanti DebBarma ++ * Thara Gopinath ++ * ++ * Platform device conversion and hwmod support. ++ * + * Copyright (C) 2005 Nokia Corporation + * Author: Lauri Leukkunen + * PWM and clock framwork support by Timo Teras. +@@ -44,6 +50,11 @@ + #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 + #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 + ++/* ++ * IP revision identifier so that Highlander IP ++ * in OMAP4 can be distinguished. ++ */ ++#define OMAP_TIMER_IP_VERSION_1 0x1 + struct omap_dm_timer; + extern struct omap_dm_timer *gptimer_wakeup; + extern struct sys_timer omap_timer; +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/fpga.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/fpga.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/fpga.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/fpga.h 2011-03-09 13:19:10.095501839 +0100 +@@ -30,18 +30,18 @@ + * --------------------------------------------------------------------------- + */ + /* maps in the FPGA registers and the ETHR registers */ +-#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */ ++#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ + #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ + #define H2P2_DBG_FPGA_START 0x04000000 /* PA */ + + #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) +-#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ +-#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ +-#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ +-#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ +-#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ +-#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ +-#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ ++#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ ++#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ ++#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ ++#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ ++#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ ++#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ ++#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ + + /* NOTE: most boards don't have a static mapping for the FPGA ... */ + struct h2p2_dbg_fpga { +@@ -81,55 +81,55 @@ + * OMAP-1510 FPGA + * --------------------------------------------------------------------------- + */ +-#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */ ++#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ + #define OMAP1510_FPGA_SIZE SZ_4K + #define OMAP1510_FPGA_START 0x08000000 /* PA */ + + /* Revision */ +-#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) +-#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) ++#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) ++#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) + +-#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) +-#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) +-#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) +-#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) ++#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) ++#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) ++#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) ++#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) + + /* Interrupt status */ +-#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) +-#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) ++#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) ++#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) + + /* Interrupt mask */ +-#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) +-#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) ++#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) ++#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) + + /* Reset registers */ +-#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) +-#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) ++#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) ++#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) + +-#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) +-#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) +-#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) +-#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) +-#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) +-#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) +-#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) +-#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) +-#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) +-#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) +- +-#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) +- +-#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) +-#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) +-#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) +-#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) +-#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) +-#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) +-#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) +-#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) +-#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) +-#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) +-#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) ++#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) ++#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) ++#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) ++#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) ++#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) ++#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) ++#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) ++#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) ++#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) ++#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) ++ ++#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) ++ ++#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) ++#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) ++#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) ++#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) ++#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) ++#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) ++#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) ++#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) ++#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) ++#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) ++#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) + + #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) + +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/gpmc.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/gpmc.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/gpmc.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/gpmc.h 2011-03-09 13:19:10.095501839 +0100 +@@ -41,6 +41,8 @@ + #define GPMC_NAND_ADDRESS 0x0000000b + #define GPMC_NAND_DATA 0x0000000c + ++#define GPMC_ENABLE_IRQ 0x0000000d ++ + /* ECC commands */ + #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ + #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ +@@ -78,6 +80,19 @@ + #define WR_RD_PIN_MONITORING 0x00600000 + #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) + #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) ++#define GPMC_IRQ_FIFOEVENTENABLE 0x01 ++#define GPMC_IRQ_COUNT_EVENT 0x02 ++ ++#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 ++#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) ++ ++enum omap_ecc { ++ /* 1-bit ecc: stored at end of spare area */ ++ OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ ++ OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ ++ /* 1-bit ecc: stored at begining of spare area as romcode */ ++ OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */ ++}; + + /* + * Note that all values in this struct are in nanoseconds except sync_clk +@@ -130,12 +145,11 @@ + extern void gpmc_cs_free(int cs); + extern int gpmc_cs_set_reserved(int cs, int reserved); + extern int gpmc_cs_reserved(int cs); +-extern int gpmc_prefetch_enable(int cs, int dma_mode, ++extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, + unsigned int u32_count, int is_write); + extern int gpmc_prefetch_reset(int cs); + extern void omap3_gpmc_save_context(void); + extern void omap3_gpmc_restore_context(void); +-extern void gpmc_init(void); + extern int gpmc_read_status(int cmd); + extern int gpmc_cs_configure(int cs, int cmd, int wval); + extern int gpmc_nand_read(int cs, int cmd); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/hardware.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/hardware.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/hardware.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/hardware.h 2011-03-09 13:19:10.096501820 +0100 +@@ -286,5 +286,6 @@ + #include + #include + #include ++#include + + #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/io.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/io.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/io.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/io.h 2011-03-09 13:19:10.096501820 +0100 +@@ -259,7 +259,7 @@ + extern void omap1_map_common_io(void); + extern void omap1_init_common_hw(void); + +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + extern void omap242x_map_common_io(void); + #else + static inline void omap242x_map_common_io(void) +@@ -267,7 +267,7 @@ + } + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + extern void omap243x_map_common_io(void); + #else + static inline void omap243x_map_common_io(void) +@@ -283,6 +283,14 @@ + } + #endif + ++#ifdef CONFIG_SOC_OMAPTI816X ++extern void omapti816x_map_common_io(void); ++#else ++static inline void omapti816x_map_common_io(void) ++{ ++} ++#endif ++ + #ifdef CONFIG_ARCH_OMAP4 + extern void omap44xx_map_common_io(void); + #else +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/iommu.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/iommu.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/iommu.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/iommu.h 2011-03-09 13:19:10.096501820 +0100 +@@ -31,6 +31,7 @@ + struct clk *clk; + void __iomem *regbase; + struct device *dev; ++ void *isr_priv; + + unsigned int refcount; + struct mutex iommu_lock; /* global for this whole object */ +@@ -47,7 +48,7 @@ + struct list_head mmap; + struct mutex mmap_lock; /* protect mmap */ + +- int (*isr)(struct iommu *obj); ++ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv); + + void *ctx; /* iommu context: registres saved area */ + u32 da_start; +@@ -109,6 +110,13 @@ + u32 da_end; + }; + ++/* IOMMU errors */ ++#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0) ++#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1) ++#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2) ++#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3) ++#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4) ++ + #if defined(CONFIG_ARCH_OMAP1) + #error "iommu for this processor not implemented yet" + #else +@@ -154,11 +162,17 @@ + extern void flush_iotlb_all(struct iommu *obj); + + extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); ++extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, ++ u32 **ppte); + extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); + + extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); + extern struct iommu *iommu_get(const char *name); + extern void iommu_put(struct iommu *obj); ++extern int iommu_set_isr(const char *name, ++ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, ++ void *priv), ++ void *isr_priv); + + extern void iommu_save_ctx(struct iommu *obj); + extern void iommu_restore_ctx(struct iommu *obj); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/irqs.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/irqs.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/irqs.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/irqs.h 2011-03-09 13:19:10.097501800 +0100 +@@ -318,6 +318,7 @@ + #define INT_34XX_PRCM_MPU_IRQ 11 + #define INT_34XX_MCBSP1_IRQ 16 + #define INT_34XX_MCBSP2_IRQ 17 ++#define INT_34XX_GPMC_IRQ 20 + #define INT_34XX_MCBSP3_IRQ 22 + #define INT_34XX_MCBSP4_IRQ 23 + #define INT_34XX_CAM_IRQ 24 +@@ -411,7 +412,13 @@ + #define TWL_IRQ_END TWL6030_IRQ_END + #endif + +-#define NR_IRQS TWL_IRQ_END ++/* GPMC related */ ++#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END) ++#define OMAP_GPMC_NR_IRQS 7 ++#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) ++ ++ ++#define NR_IRQS OMAP_GPMC_IRQ_END + + #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) + +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_2xxx.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_2xxx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_2xxx.h 2011-03-09 13:19:10.097501800 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ ++ * Sumit Semwal ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H ++#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H ++ ++/* L3 CONNIDs */ ++/* Display Sub system (DSS) */ ++#define OMAP2_L3_CORE_FW_CONNID_DSS 8 ++ ++#endif +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_3xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_3xxx.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_3xxx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_3xxx.h 2011-03-09 13:19:10.098501780 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ ++ * Sumit Semwal ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H ++#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H ++ ++/* L3 Initiator IDs */ ++/* Display Sub system (DSS) */ ++#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29 ++ ++#endif +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_2xxx.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_2xxx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_2xxx.h 2011-03-09 13:19:10.098501780 +0100 +@@ -0,0 +1,24 @@ ++/* ++ * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ ++ * Sumit Semwal ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H ++#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H ++ ++/* L4 CORE */ ++/* Display Sub system (DSS) */ ++#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28 ++#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29 ++#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30 ++#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31 ++#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32 ++ ++#endif +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_3xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_3xxx.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_3xxx.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_3xxx.h 2011-03-09 13:19:10.098501780 +0100 +@@ -21,4 +21,14 @@ + #define OMAP3_L4_CORE_FW_I2C3_REGION 73 + #define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 + ++/* Display Sub system (DSS) */ ++#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2 ++ ++#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104 ++#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3 ++#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4 ++#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4 ++#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5 ++#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6 ++#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7 + #endif +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcbsp.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcbsp.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcbsp.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcbsp.h 2011-03-09 13:19:10.098501780 +0100 +@@ -37,6 +37,10 @@ + .id = OMAP_MCBSP##port_nr, \ + } + ++#define MCBSP_CONFIG_TYPE2 0x2 ++#define MCBSP_CONFIG_TYPE3 0x3 ++#define MCBSP_CONFIG_TYPE4 0x4 ++ + #define OMAP7XX_MCBSP1_BASE 0xfffb1000 + #define OMAP7XX_MCBSP2_BASE 0xfffb1800 + +@@ -48,32 +52,14 @@ + #define OMAP1610_MCBSP2_BASE 0xfffb1000 + #define OMAP1610_MCBSP3_BASE 0xe1017000 + +-#define OMAP24XX_MCBSP1_BASE 0x48074000 +-#define OMAP24XX_MCBSP2_BASE 0x48076000 +-#define OMAP2430_MCBSP3_BASE 0x4808c000 +-#define OMAP2430_MCBSP4_BASE 0x4808e000 +-#define OMAP2430_MCBSP5_BASE 0x48096000 +- +-#define OMAP34XX_MCBSP1_BASE 0x48074000 +-#define OMAP34XX_MCBSP2_BASE 0x49022000 +-#define OMAP34XX_MCBSP2_ST_BASE 0x49028000 +-#define OMAP34XX_MCBSP3_BASE 0x49024000 +-#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000 +-#define OMAP34XX_MCBSP3_BASE 0x49024000 +-#define OMAP34XX_MCBSP4_BASE 0x49026000 +-#define OMAP34XX_MCBSP5_BASE 0x48096000 +- +-#define OMAP44XX_MCBSP1_BASE 0x49022000 +-#define OMAP44XX_MCBSP2_BASE 0x49024000 +-#define OMAP44XX_MCBSP3_BASE 0x49026000 +-#define OMAP44XX_MCBSP4_BASE 0x48096000 +- +-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) ++#ifdef CONFIG_ARCH_OMAP1 + + #define OMAP_MCBSP_REG_DRR2 0x00 + #define OMAP_MCBSP_REG_DRR1 0x02 + #define OMAP_MCBSP_REG_DXR2 0x04 + #define OMAP_MCBSP_REG_DXR1 0x06 ++#define OMAP_MCBSP_REG_DRR 0x02 ++#define OMAP_MCBSP_REG_DXR 0x06 + #define OMAP_MCBSP_REG_SPCR2 0x08 + #define OMAP_MCBSP_REG_SPCR1 0x0a + #define OMAP_MCBSP_REG_RCR2 0x0c +@@ -106,13 +92,6 @@ + #define OMAP_MCBSP_REG_XCCR 0x00 + #define OMAP_MCBSP_REG_RCCR 0x00 + +-#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) +-#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) +- +-#define AUDIO_MCBSP OMAP_MCBSP1 +-#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX +-#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX +- + #else + + #define OMAP_MCBSP_REG_DRR2 0x00 +@@ -168,13 +147,6 @@ + #define OMAP_ST_REG_SFIRCR 0x28 + #define OMAP_ST_REG_SSELCR 0x2C + +-#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) +-#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) +- +-#define AUDIO_MCBSP OMAP_MCBSP2 +-#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX +-#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX +- + #endif + + /************************** McBSP SPCR1 bit definitions ***********************/ +@@ -428,8 +400,9 @@ + #ifdef CONFIG_ARCH_OMAP3 + /* Sidetone block for McBSP 2 and 3 */ + unsigned long phys_base_st; +- u16 buffer_size; + #endif ++ u16 buffer_size; ++ unsigned int mcbsp_config_type; + }; + + struct omap_mcbsp_st_data { +@@ -445,6 +418,7 @@ + struct omap_mcbsp { + struct device *dev; + unsigned long phys_base; ++ unsigned long phys_dma_base; + void __iomem *io_base; + u8 id; + u8 free; +@@ -471,7 +445,6 @@ + /* Protect the field .free, while checking if the mcbsp is in use */ + spinlock_t lock; + struct omap_mcbsp_platform_data *pdata; +- struct clk *iclk; + struct clk *fclk; + #ifdef CONFIG_ARCH_OMAP3 + struct omap_mcbsp_st_data *st_data; +@@ -480,7 +453,17 @@ + u16 max_rx_thres; + #endif + void *reg_cache; ++ unsigned int mcbsp_config_type; ++}; ++ ++/** ++ * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod ++ * @sidetone: name of the sidetone device ++ */ ++struct omap_mcbsp_dev_attr { ++ const char *sidetone; + }; ++ + extern struct omap_mcbsp **mcbsp_ptr; + extern int omap_mcbsp_count, omap_mcbsp_cache_size; + +@@ -488,8 +471,8 @@ + #define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; + + int omap_mcbsp_init(void); +-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, +- int size); ++void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, ++ struct omap_mcbsp_platform_data *config, int size); + void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); + #ifdef CONFIG_ARCH_OMAP3 + void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); +@@ -539,6 +522,9 @@ + void omap2_mcbsp1_mux_clkr_src(u8 mux); + void omap2_mcbsp1_mux_fsr_src(u8 mux); + ++int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); ++int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); ++ + #ifdef CONFIG_ARCH_OMAP3 + /* Sidetone specific API */ + int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcspi.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcspi.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcspi.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcspi.h 2011-03-09 13:19:10.098501780 +0100 +@@ -1,8 +1,19 @@ + #ifndef _OMAP2_MCSPI_H + #define _OMAP2_MCSPI_H + ++#define OMAP2_MCSPI_REV 0 ++#define OMAP3_MCSPI_REV 1 ++#define OMAP4_MCSPI_REV 2 ++ ++#define OMAP4_MCSPI_REG_OFFSET 0x100 ++ + struct omap2_mcspi_platform_config { + unsigned short num_cs; ++ unsigned int regs_offset; ++}; ++ ++struct omap2_mcspi_dev_attr { ++ unsigned short num_chipselect; + }; + + struct omap2_mcspi_device_config { +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mmc.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mmc.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mmc.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mmc.h 2011-03-09 13:19:10.099501760 +0100 +@@ -24,25 +24,19 @@ + #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ + + #define OMAP24XX_NR_MMC 2 +-#define OMAP34XX_NR_MMC 3 +-#define OMAP44XX_NR_MMC 5 + #define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE +-#define OMAP3_HSMMC_SIZE 0x200 +-#define OMAP4_HSMMC_SIZE 0x1000 + #define OMAP2_MMC1_BASE 0x4809c000 +-#define OMAP2_MMC2_BASE 0x480b4000 +-#define OMAP3_MMC3_BASE 0x480ad000 +-#define OMAP4_MMC4_BASE 0x480d1000 +-#define OMAP4_MMC5_BASE 0x480d5000 ++ + #define OMAP4_MMC_REG_OFFSET 0x100 +-#define HSMMC5 (1 << 4) +-#define HSMMC4 (1 << 3) +-#define HSMMC3 (1 << 2) +-#define HSMMC2 (1 << 1) +-#define HSMMC1 (1 << 0) + + #define OMAP_MMC_MAX_SLOTS 2 + ++#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1) ++ ++struct omap_mmc_dev_attr { ++ u8 flags; ++}; ++ + struct omap_mmc_platform_data { + /* back-link to device */ + struct device *dev; +@@ -71,6 +65,9 @@ + + u64 dma_mask; + ++ /* Integrating attributes from the omap_hwmod layer */ ++ u8 controller_flags; ++ + /* Register offset deviation */ + u16 reg_offset; + +@@ -159,8 +156,7 @@ + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) + void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers); +-void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, +- int nr_controllers); ++void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); + int omap_mmc_add(const char *name, int id, unsigned long base, + unsigned long size, unsigned int irq, + struct omap_mmc_platform_data *data); +@@ -169,8 +165,7 @@ + int nr_controllers) + { + } +-static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, +- int nr_controllers) ++static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) + { + } + static inline int omap_mmc_add(const char *name, int id, unsigned long base, +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/multi.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/multi.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/multi.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/multi.h 2011-03-09 13:19:10.099501760 +0100 +@@ -66,7 +66,7 @@ + # error "OMAP1 and OMAP2PLUS can't be selected at the same time" + # endif + #endif +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + # ifdef OMAP_NAME + # undef MULTI_OMAP2 + # define MULTI_OMAP2 +@@ -74,7 +74,7 @@ + # define OMAP_NAME omap2420 + # endif + #endif +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + # ifdef OMAP_NAME + # undef MULTI_OMAP2 + # define MULTI_OMAP2 +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/nand.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/nand.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/nand.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/nand.h 2011-03-09 13:19:10.100501740 +0100 +@@ -8,8 +8,16 @@ + * published by the Free Software Foundation. + */ + ++#include + #include + ++enum nand_io { ++ NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ ++ NAND_OMAP_POLLED, /* polled mode, without prefetch */ ++ NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */ ++ NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */ ++}; ++ + struct omap_nand_platform_data { + unsigned int options; + int cs; +@@ -20,8 +28,11 @@ + int (*nand_setup)(void); + int (*dev_ready)(struct omap_nand_platform_data *); + int dma_channel; ++ int gpmc_irq; ++ enum nand_io xfer_type; + unsigned long phys_base; + int devsize; ++ enum omap_ecc ecc_opt; + }; + + /* minimum size for IO mapping */ +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/omap_hwmod.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/omap_hwmod.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/omap_hwmod.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/omap_hwmod.h 2011-03-09 13:19:10.102501700 +0100 +@@ -1,7 +1,7 @@ + /* + * omap_hwmod macros, structures + * +- * Copyright (C) 2009-2010 Nokia Corporation ++ * Copyright (C) 2009-2011 Nokia Corporation + * Paul Walmsley + * + * Created in collaboration with (alphabetical order): Benoît Cousson, +@@ -30,6 +30,7 @@ + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H + + #include ++#include + #include + #include + #include +@@ -178,7 +179,8 @@ + #define ADDR_TYPE_RT (1 << 1) + + /** +- * struct omap_hwmod_addr_space - MPU address space handled by the hwmod ++ * struct omap_hwmod_addr_space - address space handled by the hwmod ++ * @name: name of the address space + * @pa_start: starting physical address + * @pa_end: ending physical address + * @flags: (see omap_hwmod_addr_space.flags macros above) +@@ -187,6 +189,7 @@ + * structure. GPMC is one example. + */ + struct omap_hwmod_addr_space { ++ const char *name; + u32 pa_start; + u32 pa_end; + u8 flags; +@@ -370,8 +373,10 @@ + * of standby, rather than relying on module smart-standby + * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for + * SDRAM controller, etc. XXX probably belongs outside the main hwmod file ++ * XXX Should be HWMOD_SETUP_NO_RESET + * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM + * controller, etc. XXX probably belongs outside the main hwmod file ++ * XXX Should be HWMOD_SETUP_NO_IDLE + * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) + * when module is enabled, rather than the default, which is to + * enable autoidle +@@ -535,11 +540,12 @@ + const struct omap_chip_id omap_chip; + }; + +-int omap_hwmod_init(struct omap_hwmod **ohs); ++int omap_hwmod_register(struct omap_hwmod **ohs); + struct omap_hwmod *omap_hwmod_lookup(const char *name); + int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), + void *data); +-int omap_hwmod_late_init(void); ++ ++int __init omap_hwmod_setup_one(const char *name); + + int omap_hwmod_enable(struct omap_hwmod *oh); + int _omap_hwmod_enable(struct omap_hwmod *oh); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/onenand.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/onenand.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/onenand.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/onenand.h 2011-03-09 13:19:10.102501700 +0100 +@@ -15,12 +15,20 @@ + #define ONENAND_SYNC_READ (1 << 0) + #define ONENAND_SYNC_READWRITE (1 << 1) + ++struct onenand_freq_info { ++ u16 maf_id; ++ u16 dev_id; ++ u16 ver_id; ++}; ++ + struct omap_onenand_platform_data { + int cs; + int gpio_irq; + struct mtd_partition *parts; + int nr_parts; +- int (*onenand_setup)(void __iomem *, int freq); ++ int (*onenand_setup)(void __iomem *, int *freq_ptr); ++ int (*get_freq)(const struct onenand_freq_info *freq_info, ++ bool *clk_dep); + int dma_channel; + u8 flags; + u8 regulator_can_sleep; +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/prcm.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/prcm.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/prcm.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/prcm.h 2011-03-09 13:19:10.102501700 +0100 +@@ -28,7 +28,6 @@ + #define __ASM_ARM_ARCH_OMAP_PRCM_H + + u32 omap_prcm_get_reset_sources(void); +-void omap_prcm_arch_reset(char mode, const char *cmd); + int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, + const char *name); + +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/sdrc.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/sdrc.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/sdrc.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/sdrc.h 2011-03-09 13:19:10.102501700 +0100 +@@ -124,8 +124,14 @@ + u32 mr; + }; + +-void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, ++#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) ++void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1); ++#else ++static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, ++ struct omap_sdrc_params *sdrc_cs1) {}; ++#endif ++ + int omap2_sdrc_get_params(unsigned long r, + struct omap_sdrc_params **sdrc_cs0, + struct omap_sdrc_params **sdrc_cs1); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/serial.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/serial.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/serial.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/serial.h 2011-03-09 13:19:10.103501679 +0100 +@@ -51,6 +51,11 @@ + #define OMAP4_UART3_BASE 0x48020000 + #define OMAP4_UART4_BASE 0x4806e000 + ++/* TI816X serial ports */ ++#define TI816X_UART1_BASE 0x48020000 ++#define TI816X_UART2_BASE 0x48022000 ++#define TI816X_UART3_BASE 0x48024000 ++ + /* External port on Zoom2/3 */ + #define ZOOM_UART_BASE 0x10000000 + #define ZOOM_UART_VIRT 0xfa400000 +@@ -81,6 +86,9 @@ + #define OMAP4UART2 OMAP2UART2 + #define OMAP4UART3 43 + #define OMAP4UART4 44 ++#define TI816XUART1 81 ++#define TI816XUART2 82 ++#define TI816XUART3 83 + #define ZOOM_UART 95 /* Only on zoom2/3 */ + + /* This is only used by 8250.c for omap1510 */ +@@ -96,7 +104,6 @@ + + struct omap_board_data; + +-extern void __init omap_serial_early_init(void); + extern void omap_serial_init(void); + extern void omap_serial_init_port(struct omap_board_data *bdata); + extern int omap_uart_can_sleep(void); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/system.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/system.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/system.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/system.h 2011-03-09 13:19:10.103501679 +0100 +@@ -4,48 +4,14 @@ + */ + #ifndef __ASM_ARCH_SYSTEM_H + #define __ASM_ARCH_SYSTEM_H +-#include + +-#include +-#include +- +-#include +- +-#ifndef CONFIG_MACH_VOICEBLUE +-#define voiceblue_reset() do {} while (0) +-#else +-extern void voiceblue_reset(void); +-#endif ++#include + + static inline void arch_idle(void) + { + cpu_do_idle(); + } + +-static inline void omap1_arch_reset(char mode, const char *cmd) +-{ +- /* +- * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 +- * "Global Software Reset Affects Traffic Controller Frequency". +- */ +- if (cpu_is_omap5912()) { +- omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), +- DPLL_CTL); +- omap_writew(0x8, ARM_RSTCT1); +- } +- +- if (machine_is_voiceblue()) +- voiceblue_reset(); +- else +- omap_writew(1, ARM_RSTCT1); +-} +- +-static inline void arch_reset(char mode, const char *cmd) +-{ +- if (!cpu_class_is_omap2()) +- omap1_arch_reset(mode, cmd); +- else +- omap_prcm_arch_reset(mode, cmd); +-} ++extern void (*arch_reset)(char, const char *); + + #endif +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/ti816x.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/ti816x.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/ti816x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/ti816x.h 2011-03-09 13:19:10.103501679 +0100 +@@ -0,0 +1,27 @@ ++/* ++ * This file contains the address data for various TI816X modules. ++ * ++ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __ASM_ARCH_TI816X_H ++#define __ASM_ARCH_TI816X_H ++ ++#define L4_SLOW_TI816X_BASE 0x48000000 ++ ++#define TI816X_SCM_BASE 0x48140000 ++#define TI816X_CTRL_BASE TI816X_SCM_BASE ++#define TI816X_PRCM_BASE 0x48180000 ++ ++#define TI816X_ARM_INTC_BASE 0x48200000 ++ ++#endif /* __ASM_ARCH_TI816X_H */ +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/uncompress.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/uncompress.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/uncompress.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/uncompress.h 2011-03-09 13:19:10.104501658 +0100 +@@ -93,6 +93,10 @@ + #define DEBUG_LL_ZOOM(mach) \ + _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) + ++#define DEBUG_LL_TI816X(p, mach) \ ++ _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \ ++ TI816XUART##p) ++ + static inline void __arch_decomp_setup(unsigned long arch_id) + { + int port = 0; +@@ -166,6 +170,9 @@ + DEBUG_LL_ZOOM(omap_zoom2); + DEBUG_LL_ZOOM(omap_zoom3); + ++ /* TI8168 base boards using UART3 */ ++ DEBUG_LL_TI816X(3, ti8168evm); ++ + } while (0); + } + +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/usb.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/usb.h +--- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/usb.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/usb.h 2011-03-09 13:19:10.104501658 +0100 +@@ -91,6 +91,10 @@ + + #endif + ++extern void am35x_musb_reset(void); ++extern void am35x_musb_phy_power(u8 on); ++extern void am35x_musb_clear_irq(void); ++extern void am35x_musb_set_mode(u8 musb_mode); + + /* + * FIXME correct answer depends on hmc_mode, +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/io.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/io.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/io.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/io.c 2011-03-09 13:19:10.104501658 +0100 +@@ -85,7 +85,10 @@ + } + #endif + #ifdef CONFIG_ARCH_OMAP3 +- if (cpu_is_omap34xx()) { ++ if (cpu_is_ti816x()) { ++ if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) ++ return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); ++ } else if (cpu_is_omap34xx()) { + if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE)) + return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); + if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/iommu.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/iommu.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/iommu.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/iommu.c 2011-03-09 13:19:10.105501637 +0100 +@@ -104,6 +104,9 @@ + if (!obj) + return -EINVAL; + ++ if (!arch_iommu) ++ return -ENODEV; ++ + clk_enable(obj->clk); + + err = arch_iommu->enable(obj); +@@ -780,25 +783,19 @@ + */ + static irqreturn_t iommu_fault_handler(int irq, void *data) + { +- u32 stat, da; ++ u32 da, errs; + u32 *iopgd, *iopte; +- int err = -EIO; + struct iommu *obj = data; + + if (!obj->refcount) + return IRQ_NONE; + +- /* Dynamic loading TLB or PTE */ +- if (obj->isr) +- err = obj->isr(obj); +- +- if (!err) +- return IRQ_HANDLED; +- + clk_enable(obj->clk); +- stat = iommu_report_fault(obj, &da); ++ errs = iommu_report_fault(obj, &da); + clk_disable(obj->clk); +- if (!stat) ++ ++ /* Fault callback or TLB/PTE Dynamic loading */ ++ if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) + return IRQ_HANDLED; + + iommu_disable(obj); +@@ -806,15 +803,16 @@ + iopgd = iopgd_offset(obj, da); + + if (!iopgd_is_table(*iopgd)) { +- dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, +- da, iopgd, *iopgd); ++ dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " ++ "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); + return IRQ_NONE; + } + + iopte = iopte_offset(iopgd, da); + +- dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", +- __func__, da, iopgd, *iopgd, iopte, *iopte); ++ dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " ++ "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, ++ iopte, *iopte); + + return IRQ_NONE; + } +@@ -917,6 +915,33 @@ + } + EXPORT_SYMBOL_GPL(iommu_put); + ++int iommu_set_isr(const char *name, ++ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, ++ void *priv), ++ void *isr_priv) ++{ ++ struct device *dev; ++ struct iommu *obj; ++ ++ dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, ++ device_match_by_alias); ++ if (!dev) ++ return -ENODEV; ++ ++ obj = to_iommu(dev); ++ mutex_lock(&obj->iommu_lock); ++ if (obj->refcount != 0) { ++ mutex_unlock(&obj->iommu_lock); ++ return -EBUSY; ++ } ++ obj->isr = isr; ++ obj->isr_priv = isr_priv; ++ mutex_unlock(&obj->iommu_lock); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(iommu_set_isr); ++ + /* + * OMAP Device MMU(IOMMU) detection + */ +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/mcbsp.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/mcbsp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/mcbsp.c 2011-03-09 13:19:10.106501616 +0100 +@@ -27,6 +27,8 @@ + + #include + #include ++#include ++#include + + /* XXX These "sideways" includes are a sign that something is wrong */ + #include "../mach-omap2/cm2xxx_3xxx.h" +@@ -227,10 +229,83 @@ + } + EXPORT_SYMBOL(omap_mcbsp_config); + ++/** ++ * omap_mcbsp_dma_params - returns the dma channel number ++ * @id - mcbsp id ++ * @stream - indicates the direction of data flow (rx or tx) ++ * ++ * Returns the dma channel number for the rx channel or tx channel ++ * based on the value of @stream for the requested mcbsp given by @id ++ */ ++int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream) ++{ ++ struct omap_mcbsp *mcbsp; ++ ++ if (!omap_mcbsp_check_valid_id(id)) { ++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); ++ return -ENODEV; ++ } ++ mcbsp = id_to_mcbsp_ptr(id); ++ ++ if (stream) ++ return mcbsp->dma_rx_sync; ++ else ++ return mcbsp->dma_tx_sync; ++} ++EXPORT_SYMBOL(omap_mcbsp_dma_ch_params); ++ ++/** ++ * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register ++ * @id - mcbsp id ++ * @stream - indicates the direction of data flow (rx or tx) ++ * ++ * Returns the address of mcbsp data transmit register or data receive register ++ * to be used by DMA for transferring/receiving data based on the value of ++ * @stream for the requested mcbsp given by @id ++ */ ++int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream) ++{ ++ struct omap_mcbsp *mcbsp; ++ int data_reg; ++ ++ if (!omap_mcbsp_check_valid_id(id)) { ++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); ++ return -ENODEV; ++ } ++ mcbsp = id_to_mcbsp_ptr(id); ++ ++ data_reg = mcbsp->phys_dma_base; ++ ++ if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) { ++ if (stream) ++ data_reg += OMAP_MCBSP_REG_DRR1; ++ else ++ data_reg += OMAP_MCBSP_REG_DXR1; ++ } else { ++ if (stream) ++ data_reg += OMAP_MCBSP_REG_DRR; ++ else ++ data_reg += OMAP_MCBSP_REG_DXR; ++ } ++ ++ return data_reg; ++} ++EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); ++ + #ifdef CONFIG_ARCH_OMAP3 ++static struct omap_device *find_omap_device_by_dev(struct device *dev) ++{ ++ struct platform_device *pdev = container_of(dev, ++ struct platform_device, dev); ++ return container_of(pdev, struct omap_device, pdev); ++} ++ + static void omap_st_on(struct omap_mcbsp *mcbsp) + { + unsigned int w; ++ struct omap_device *od; ++ ++ od = find_omap_device_by_dev(mcbsp->dev); + + /* + * Sidetone uses McBSP ICLK - which must not idle when sidetones +@@ -244,9 +319,6 @@ + w = MCBSP_READ(mcbsp, SSELCR); + MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN); + +- w = MCBSP_ST_READ(mcbsp, SYSCONFIG); +- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); +- + /* Enable Sidetone from Sidetone Core */ + w = MCBSP_ST_READ(mcbsp, SSELCR); + MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN); +@@ -255,13 +327,13 @@ + static void omap_st_off(struct omap_mcbsp *mcbsp) + { + unsigned int w; ++ struct omap_device *od; ++ ++ od = find_omap_device_by_dev(mcbsp->dev); + + w = MCBSP_ST_READ(mcbsp, SSELCR); + MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); + +- w = MCBSP_ST_READ(mcbsp, SYSCONFIG); +- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE); +- + w = MCBSP_READ(mcbsp, SSELCR); + MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); + +@@ -273,9 +345,9 @@ + static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) + { + u16 val, i; ++ struct omap_device *od; + +- val = MCBSP_ST_READ(mcbsp, SYSCONFIG); +- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE)); ++ od = find_omap_device_by_dev(mcbsp->dev); + + val = MCBSP_ST_READ(mcbsp, SSELCR); + +@@ -303,9 +375,9 @@ + { + u16 w; + struct omap_mcbsp_st_data *st_data = mcbsp->st_data; ++ struct omap_device *od; + +- w = MCBSP_ST_READ(mcbsp, SYSCONFIG); +- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); ++ od = find_omap_device_by_dev(mcbsp->dev); + + w = MCBSP_ST_READ(mcbsp, SSELCR); + +@@ -648,48 +720,33 @@ + + static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) + { ++ struct omap_device *od; ++ ++ od = find_omap_device_by_dev(mcbsp->dev); + /* + * Enable wakup behavior, smart idle and all wakeups + * REVISIT: some wakeups may be unnecessary + */ + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { +- u16 syscon; +- +- syscon = MCBSP_READ(mcbsp, SYSCON); +- syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); +- +- if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { +- syscon |= (ENAWAKEUP | SIDLEMODE(0x02) | +- CLOCKACTIVITY(0x02)); +- MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); +- } else { +- syscon |= SIDLEMODE(0x01); +- } +- +- MCBSP_WRITE(mcbsp, SYSCON, syscon); ++ MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); + } + } + + static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) + { ++ struct omap_device *od; ++ ++ od = find_omap_device_by_dev(mcbsp->dev); ++ + /* + * Disable wakup behavior, smart idle and all wakeups + */ + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { +- u16 syscon; +- +- syscon = MCBSP_READ(mcbsp, SYSCON); +- syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); + /* + * HW bug workaround - If no_idle mode is taken, we need to + * go to smart_idle before going to always_idle, or the + * device will not hit retention anymore. + */ +- syscon |= SIDLEMODE(0x02); +- MCBSP_WRITE(mcbsp, SYSCON, syscon); +- +- syscon &= ~(SIDLEMODE(0x03)); +- MCBSP_WRITE(mcbsp, SYSCON, syscon); + + MCBSP_WRITE(mcbsp, WAKEUPEN, 0); + } +@@ -764,8 +821,7 @@ + if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) + mcbsp->pdata->ops->request(id); + +- clk_enable(mcbsp->iclk); +- clk_enable(mcbsp->fclk); ++ pm_runtime_get_sync(mcbsp->dev); + + /* Do procedure specific to omap34xx arch, if applicable */ + omap34xx_mcbsp_request(mcbsp); +@@ -813,8 +869,7 @@ + /* Do procedure specific to omap34xx arch, if applicable */ + omap34xx_mcbsp_free(mcbsp); + +- clk_disable(mcbsp->fclk); +- clk_disable(mcbsp->iclk); ++ pm_runtime_put_sync(mcbsp->dev); + + spin_lock(&mcbsp->lock); + mcbsp->free = true; +@@ -844,8 +899,7 @@ + /* Do procedure specific to omap34xx arch, if applicable */ + omap34xx_mcbsp_free(mcbsp); + +- clk_disable(mcbsp->fclk); +- clk_disable(mcbsp->iclk); ++ pm_runtime_put_sync(mcbsp->dev); + + if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { + /* Free IRQs */ +@@ -1649,7 +1703,8 @@ + + static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) + { +- struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; ++ struct platform_device *pdev; ++ struct resource *res; + struct omap_mcbsp_st_data *st_data; + int err; + +@@ -1659,7 +1714,10 @@ + goto err1; + } + +- st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); ++ pdev = container_of(mcbsp->dev, struct platform_device, dev); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); ++ st_data->io_base_st = ioremap(res->start, resource_size(res)); + if (!st_data->io_base_st) { + err = -ENOMEM; + goto err2; +@@ -1748,6 +1806,7 @@ + struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; + struct omap_mcbsp *mcbsp; + int id = pdev->id - 1; ++ struct resource *res; + int ret = 0; + + if (!pdata) { +@@ -1777,47 +1836,78 @@ + mcbsp->dma_tx_lch = -1; + mcbsp->dma_rx_lch = -1; + +- mcbsp->phys_base = pdata->phys_base; +- mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); ++ if (!res) { ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory" ++ "resource\n", __func__, pdev->id); ++ ret = -ENOMEM; ++ goto exit; ++ } ++ } ++ mcbsp->phys_base = res->start; ++ omap_mcbsp_cache_size = resource_size(res); ++ mcbsp->io_base = ioremap(res->start, resource_size(res)); + if (!mcbsp->io_base) { + ret = -ENOMEM; + goto err_ioremap; + } + ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); ++ if (!res) ++ mcbsp->phys_dma_base = mcbsp->phys_base; ++ else ++ mcbsp->phys_dma_base = res->start; ++ + /* Default I/O is IRQ based */ + mcbsp->io_type = OMAP_MCBSP_IRQ_IO; +- mcbsp->tx_irq = pdata->tx_irq; +- mcbsp->rx_irq = pdata->rx_irq; +- mcbsp->dma_rx_sync = pdata->dma_rx_sync; +- mcbsp->dma_tx_sync = pdata->dma_tx_sync; +- +- mcbsp->iclk = clk_get(&pdev->dev, "ick"); +- if (IS_ERR(mcbsp->iclk)) { +- ret = PTR_ERR(mcbsp->iclk); +- dev_err(&pdev->dev, "unable to get ick: %d\n", ret); +- goto err_iclk; ++ ++ mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); ++ mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); ++ ++ /* From OMAP4 there will be a single irq line */ ++ if (mcbsp->tx_irq == -ENXIO) ++ mcbsp->tx_irq = platform_get_irq(pdev, 0); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); ++ if (!res) { ++ dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n", ++ __func__, pdev->id); ++ ret = -ENODEV; ++ goto err_res; ++ } ++ mcbsp->dma_rx_sync = res->start; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); ++ if (!res) { ++ dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n", ++ __func__, pdev->id); ++ ret = -ENODEV; ++ goto err_res; + } ++ mcbsp->dma_tx_sync = res->start; + + mcbsp->fclk = clk_get(&pdev->dev, "fck"); + if (IS_ERR(mcbsp->fclk)) { + ret = PTR_ERR(mcbsp->fclk); + dev_err(&pdev->dev, "unable to get fck: %d\n", ret); +- goto err_fclk; ++ goto err_res; + } + + mcbsp->pdata = pdata; + mcbsp->dev = &pdev->dev; + mcbsp_ptr[id] = mcbsp; ++ mcbsp->mcbsp_config_type = pdata->mcbsp_config_type; + platform_set_drvdata(pdev, mcbsp); ++ pm_runtime_enable(mcbsp->dev); + + /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ + omap34xx_device_init(mcbsp); + + return 0; + +-err_fclk: +- clk_put(mcbsp->iclk); +-err_iclk: ++err_res: + iounmap(mcbsp->io_base); + err_ioremap: + kfree(mcbsp); +@@ -1839,7 +1929,6 @@ + omap34xx_device_exit(mcbsp); + + clk_put(mcbsp->fclk); +- clk_put(mcbsp->iclk); + + iounmap(mcbsp->io_base); + kfree(mcbsp); +diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/sram.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/sram.c +--- linux-2.6.38-rc7/arch/arm/plat-omap/sram.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/sram.c 2011-03-09 13:19:10.107501596 +0100 +@@ -312,7 +312,7 @@ + } + #endif + +-#ifdef CONFIG_ARCH_OMAP2420 ++#ifdef CONFIG_SOC_OMAP2420 + static int __init omap242x_sram_init(void) + { + _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, +@@ -333,7 +333,7 @@ + } + #endif + +-#ifdef CONFIG_ARCH_OMAP2430 ++#ifdef CONFIG_SOC_OMAP2430 + static int __init omap243x_sram_init(void) + { + _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, +@@ -405,20 +405,6 @@ + } + #endif + +-#ifdef CONFIG_ARCH_OMAP4 +-static int __init omap44xx_sram_init(void) +-{ +- printk(KERN_ERR "FIXME: %s not implemented\n", __func__); +- +- return -ENODEV; +-} +-#else +-static inline int omap44xx_sram_init(void) +-{ +- return 0; +-} +-#endif +- + int __init omap_sram_init(void) + { + omap_detect_sram(); +@@ -432,8 +418,6 @@ + omap243x_sram_init(); + else if (cpu_is_omap34xx()) + omap34xx_sram_init(); +- else if (cpu_is_omap44xx()) +- omap44xx_sram_init(); + + return 0; + } +diff -Naur linux-2.6.38-rc7/Documentation/hwspinlock.txt linux-2.6.38-rc7-linux-omap-dss2/Documentation/hwspinlock.txt +--- linux-2.6.38-rc7/Documentation/hwspinlock.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/Documentation/hwspinlock.txt 2011-03-09 13:19:09.179520421 +0100 +@@ -0,0 +1,293 @@ ++Hardware Spinlock Framework ++ ++1. Introduction ++ ++Hardware spinlock modules provide hardware assistance for synchronization ++and mutual exclusion between heterogeneous processors and those not operating ++under a single, shared operating system. ++ ++For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP, ++each of which is running a different Operating System (the master, A9, ++is usually running Linux and the slave processors, the M3 and the DSP, ++are running some flavor of RTOS). ++ ++A generic hwspinlock framework allows platform-independent drivers to use ++the hwspinlock device in order to access data structures that are shared ++between remote processors, that otherwise have no alternative mechanism ++to accomplish synchronization and mutual exclusion operations. ++ ++This is necessary, for example, for Inter-processor communications: ++on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the ++remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink). ++ ++To achieve fast message-based communications, a minimal kernel support ++is needed to deliver messages arriving from a remote processor to the ++appropriate user process. ++ ++This communication is based on simple data structures that is shared between ++the remote processors, and access to it is synchronized using the hwspinlock ++module (remote processor directly places new messages in this shared data ++structure). ++ ++A common hwspinlock interface makes it possible to have generic, platform- ++independent, drivers. ++ ++2. User API ++ ++ struct hwspinlock *hwspin_lock_request(void); ++ - dynamically assign an hwspinlock and return its address, or NULL ++ in case an unused hwspinlock isn't available. Users of this ++ API will usually want to communicate the lock's id to the remote core ++ before it can be used to achieve synchronization. ++ Can be called from an atomic context (this function will not sleep) but ++ not from within interrupt context. ++ ++ struct hwspinlock *hwspin_lock_request_specific(unsigned int id); ++ - assign a specific hwspinlock id and return its address, or NULL ++ if that hwspinlock is already in use. Usually board code will ++ be calling this function in order to reserve specific hwspinlock ++ ids for predefined purposes. ++ Can be called from an atomic context (this function will not sleep) but ++ not from within interrupt context. ++ ++ int hwspin_lock_free(struct hwspinlock *hwlock); ++ - free a previously-assigned hwspinlock; returns 0 on success, or an ++ appropriate error code on failure (e.g. -EINVAL if the hwspinlock ++ is already free). ++ Can be called from an atomic context (this function will not sleep) but ++ not from within interrupt context. ++ ++ int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int timeout); ++ - lock a previously-assigned hwspinlock with a timeout limit (specified in ++ msecs). If the hwspinlock is already taken, the function will busy loop ++ waiting for it to be released, but give up when the timeout elapses. ++ Upon a successful return from this function, preemption is disabled so ++ the caller must not sleep, and is advised to release the hwspinlock as ++ soon as possible, in order to minimize remote cores polling on the ++ hardware interconnect. ++ Returns 0 when successful and an appropriate error code otherwise (most ++ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs). ++ The function will never sleep. ++ ++ int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int timeout); ++ - lock a previously-assigned hwspinlock with a timeout limit (specified in ++ msecs). If the hwspinlock is already taken, the function will busy loop ++ waiting for it to be released, but give up when the timeout elapses. ++ Upon a successful return from this function, preemption and the local ++ interrupts are disabled, so the caller must not sleep, and is advised to ++ release the hwspinlock as soon as possible. ++ Returns 0 when successful and an appropriate error code otherwise (most ++ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs). ++ The function will never sleep. ++ ++ int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock, unsigned int to, ++ unsigned long *flags); ++ - lock a previously-assigned hwspinlock with a timeout limit (specified in ++ msecs). If the hwspinlock is already taken, the function will busy loop ++ waiting for it to be released, but give up when the timeout elapses. ++ Upon a successful return from this function, preemption is disabled, ++ local interrupts are disabled and their previous state is saved at the ++ given flags placeholder. The caller must not sleep, and is advised to ++ release the hwspinlock as soon as possible. ++ Returns 0 when successful and an appropriate error code otherwise (most ++ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs). ++ The function will never sleep. ++ ++ int hwspin_trylock(struct hwspinlock *hwlock); ++ - attempt to lock a previously-assigned hwspinlock, but immediately fail if ++ it is already taken. ++ Upon a successful return from this function, preemption is disabled so ++ caller must not sleep, and is advised to release the hwspinlock as soon as ++ possible, in order to minimize remote cores polling on the hardware ++ interconnect. ++ Returns 0 on success and an appropriate error code otherwise (most ++ notably -EBUSY if the hwspinlock was already taken). ++ The function will never sleep. ++ ++ int hwspin_trylock_irq(struct hwspinlock *hwlock); ++ - attempt to lock a previously-assigned hwspinlock, but immediately fail if ++ it is already taken. ++ Upon a successful return from this function, preemption and the local ++ interrupts are disabled so caller must not sleep, and is advised to ++ release the hwspinlock as soon as possible. ++ Returns 0 on success and an appropriate error code otherwise (most ++ notably -EBUSY if the hwspinlock was already taken). ++ The function will never sleep. ++ ++ int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags); ++ - attempt to lock a previously-assigned hwspinlock, but immediately fail if ++ it is already taken. ++ Upon a successful return from this function, preemption is disabled, ++ the local interrupts are disabled and their previous state is saved ++ at the given flags placeholder. The caller must not sleep, and is advised ++ to release the hwspinlock as soon as possible. ++ Returns 0 on success and an appropriate error code otherwise (most ++ notably -EBUSY if the hwspinlock was already taken). ++ The function will never sleep. ++ ++ void hwspin_unlock(struct hwspinlock *hwlock); ++ - unlock a previously-locked hwspinlock. Always succeed, and can be called ++ from any context (the function never sleeps). Note: code should _never_ ++ unlock an hwspinlock which is already unlocked (there is no protection ++ against this). ++ ++ void hwspin_unlock_irq(struct hwspinlock *hwlock); ++ - unlock a previously-locked hwspinlock and enable local interrupts. ++ The caller should _never_ unlock an hwspinlock which is already unlocked. ++ Doing so is considered a bug (there is no protection against this). ++ Upon a successful return from this function, preemption and local ++ interrupts are enabled. This function will never sleep. ++ ++ void ++ hwspin_unlock_irqrestore(struct hwspinlock *hwlock, unsigned long *flags); ++ - unlock a previously-locked hwspinlock. ++ The caller should _never_ unlock an hwspinlock which is already unlocked. ++ Doing so is considered a bug (there is no protection against this). ++ Upon a successful return from this function, preemption is reenabled, ++ and the state of the local interrupts is restored to the state saved at ++ the given flags. This function will never sleep. ++ ++ int hwspin_lock_get_id(struct hwspinlock *hwlock); ++ - retrieve id number of a given hwspinlock. This is needed when an ++ hwspinlock is dynamically assigned: before it can be used to achieve ++ mutual exclusion with a remote cpu, the id number should be communicated ++ to the remote task with which we want to synchronize. ++ Returns the hwspinlock id number, or -EINVAL if hwlock is null. ++ ++3. Typical usage ++ ++#include ++#include ++ ++int hwspinlock_example1(void) ++{ ++ struct hwspinlock *hwlock; ++ int ret; ++ ++ /* dynamically assign a hwspinlock */ ++ hwlock = hwspin_lock_request(); ++ if (!hwlock) ++ ... ++ ++ id = hwspin_lock_get_id(hwlock); ++ /* probably need to communicate id to a remote processor now */ ++ ++ /* take the lock, spin for 1 sec if it's already taken */ ++ ret = hwspin_lock_timeout(hwlock, 1000); ++ if (ret) ++ ... ++ ++ /* ++ * we took the lock, do our thing now, but do NOT sleep ++ */ ++ ++ /* release the lock */ ++ hwspin_unlock(hwlock); ++ ++ /* free the lock */ ++ ret = hwspin_lock_free(hwlock); ++ if (ret) ++ ... ++ ++ return ret; ++} ++ ++int hwspinlock_example2(void) ++{ ++ struct hwspinlock *hwlock; ++ int ret; ++ ++ /* ++ * assign a specific hwspinlock id - this should be called early ++ * by board init code. ++ */ ++ hwlock = hwspin_lock_request_specific(PREDEFINED_LOCK_ID); ++ if (!hwlock) ++ ... ++ ++ /* try to take it, but don't spin on it */ ++ ret = hwspin_trylock(hwlock); ++ if (!ret) { ++ pr_info("lock is already taken\n"); ++ return -EBUSY; ++ } ++ ++ /* ++ * we took the lock, do our thing now, but do NOT sleep ++ */ ++ ++ /* release the lock */ ++ hwspin_unlock(hwlock); ++ ++ /* free the lock */ ++ ret = hwspin_lock_free(hwlock); ++ if (ret) ++ ... ++ ++ return ret; ++} ++ ++ ++4. API for implementors ++ ++ int hwspin_lock_register(struct hwspinlock *hwlock); ++ - to be called from the underlying platform-specific implementation, in ++ order to register a new hwspinlock instance. Can be called from an atomic ++ context (this function will not sleep) but not from within interrupt ++ context. Returns 0 on success, or appropriate error code on failure. ++ ++ struct hwspinlock *hwspin_lock_unregister(unsigned int id); ++ - to be called from the underlying vendor-specific implementation, in order ++ to unregister an existing (and unused) hwspinlock instance. ++ Can be called from an atomic context (will not sleep) but not from ++ within interrupt context. ++ Returns the address of hwspinlock on success, or NULL on error (e.g. ++ if the hwspinlock is sill in use). ++ ++5. struct hwspinlock ++ ++This struct represents an hwspinlock instance. It is registered by the ++underlying hwspinlock implementation using the hwspin_lock_register() API. ++ ++/** ++ * struct hwspinlock - vendor-specific hwspinlock implementation ++ * ++ * @dev: underlying device, will be used with runtime PM api ++ * @ops: vendor-specific hwspinlock handlers ++ * @id: a global, unique, system-wide, index of the lock. ++ * @lock: initialized and used by hwspinlock core ++ * @owner: underlying implementation module, used to maintain module ref count ++ */ ++struct hwspinlock { ++ struct device *dev; ++ const struct hwspinlock_ops *ops; ++ int id; ++ spinlock_t lock; ++ struct module *owner; ++}; ++ ++The underlying implementation is responsible to assign the dev, ops, id and ++owner members. The lock member, OTOH, is initialized and used by the hwspinlock ++core. ++ ++6. Implementation callbacks ++ ++There are three possible callbacks defined in 'struct hwspinlock_ops': ++ ++struct hwspinlock_ops { ++ int (*trylock)(struct hwspinlock *lock); ++ void (*unlock)(struct hwspinlock *lock); ++ void (*relax)(struct hwspinlock *lock); ++}; ++ ++The first two callbacks are mandatory: ++ ++The ->trylock() callback should make a single attempt to take the lock, and ++return 0 on failure and 1 on success. This callback may _not_ sleep. ++ ++The ->unlock() callback releases the lock. It always succeed, and it, too, ++may _not_ sleep. ++ ++The ->relax() callback is optional. It is called by hwspinlock core while ++spinning on a lock, and can be used by the underlying implementation to force ++a delay between two successive invocations of ->trylock(). It may _not_ sleep. +diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_core.c linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_core.c +--- linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_core.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_core.c 2011-03-09 13:19:13.374435328 +0100 +@@ -0,0 +1,548 @@ ++/* ++ * Hardware spinlock framework ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com ++ * ++ * Contact: Ohad Ben-Cohen ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#define pr_fmt(fmt) "%s: " fmt, __func__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "hwspinlock_internal.h" ++ ++/* radix tree tags */ ++#define HWSPINLOCK_UNUSED (0) /* tags an hwspinlock as unused */ ++ ++/* ++ * A radix tree is used to maintain the available hwspinlock instances. ++ * The tree associates hwspinlock pointers with their integer key id, ++ * and provides easy-to-use API which makes the hwspinlock core code simple ++ * and easy to read. ++ * ++ * Radix trees are quick on lookups, and reasonably efficient in terms of ++ * storage, especially with high density usages such as this framework ++ * requires (a continuous range of integer keys, beginning with zero, is ++ * used as the ID's of the hwspinlock instances). ++ * ++ * The radix tree API supports tagging items in the tree, which this ++ * framework uses to mark unused hwspinlock instances (see the ++ * HWSPINLOCK_UNUSED tag above). As a result, the process of querying the ++ * tree, looking for an unused hwspinlock instance, is now reduced to a ++ * single radix tree API call. ++ */ ++static RADIX_TREE(hwspinlock_tree, GFP_KERNEL); ++ ++/* ++ * Synchronization of access to the tree is achieved using this spinlock, ++ * as the radix-tree API requires that users provide all synchronisation. ++ */ ++static DEFINE_SPINLOCK(hwspinlock_tree_lock); ++ ++/** ++ * __hwspin_trylock() - attempt to lock a specific hwspinlock ++ * @hwlock: an hwspinlock which we want to trylock ++ * @mode: controls whether local interrupts are disabled or not ++ * @flags: a pointer where the caller's interrupt state will be saved at (if ++ * requested) ++ * ++ * This function attempts to lock an hwspinlock, and will immediately ++ * fail if the hwspinlock is already taken. ++ * ++ * Upon a successful return from this function, preemption (and possibly ++ * interrupts) is disabled, so the caller must not sleep, and is advised to ++ * release the hwspinlock as soon as possible. This is required in order to ++ * minimize remote cores polling on the hardware interconnect. ++ * ++ * The user decides whether local interrupts are disabled or not, and if yes, ++ * whether he wants their previous state to be saved. It is up to the user ++ * to choose the appropriate @mode of operation, exactly the same way users ++ * should decide between spin_trylock, spin_trylock_irq and ++ * spin_trylock_irqsave. ++ * ++ * Returns 0 if we successfully locked the hwspinlock or -EBUSY if ++ * the hwspinlock was already taken. ++ * This function will never sleep. ++ */ ++int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags) ++{ ++ int ret; ++ ++ BUG_ON(!hwlock); ++ BUG_ON(!flags && mode == HWLOCK_IRQSTATE); ++ ++ /* ++ * This spin_lock{_irq, _irqsave} serves three purposes: ++ * ++ * 1. Disable preemption, in order to minimize the period of time ++ * in which the hwspinlock is taken. This is important in order ++ * to minimize the possible polling on the hardware interconnect ++ * by a remote user of this lock. ++ * 2. Make the hwspinlock SMP-safe (so we can take it from ++ * additional contexts on the local host). ++ * 3. Ensure that in_atomic/might_sleep checks catch potential ++ * problems with hwspinlock usage (e.g. scheduler checks like ++ * 'scheduling while atomic' etc.) ++ */ ++ if (mode == HWLOCK_IRQSTATE) ++ ret = spin_trylock_irqsave(&hwlock->lock, *flags); ++ else if (mode == HWLOCK_IRQ) ++ ret = spin_trylock_irq(&hwlock->lock); ++ else ++ ret = spin_trylock(&hwlock->lock); ++ ++ /* is lock already taken by another context on the local cpu ? */ ++ if (!ret) ++ return -EBUSY; ++ ++ /* try to take the hwspinlock device */ ++ ret = hwlock->ops->trylock(hwlock); ++ ++ /* if hwlock is already taken, undo spin_trylock_* and exit */ ++ if (!ret) { ++ if (mode == HWLOCK_IRQSTATE) ++ spin_unlock_irqrestore(&hwlock->lock, *flags); ++ else if (mode == HWLOCK_IRQ) ++ spin_unlock_irq(&hwlock->lock); ++ else ++ spin_unlock(&hwlock->lock); ++ ++ return -EBUSY; ++ } ++ ++ /* ++ * We can be sure the other core's memory operations ++ * are observable to us only _after_ we successfully take ++ * the hwspinlock, and we must make sure that subsequent memory ++ * operations (both reads and writes) will not be reordered before ++ * we actually took the hwspinlock. ++ * ++ * Note: the implicit memory barrier of the spinlock above is too ++ * early, so we need this additional explicit memory barrier. ++ */ ++ mb(); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(__hwspin_trylock); ++ ++/** ++ * __hwspin_lock_timeout() - lock an hwspinlock with timeout limit ++ * @hwlock: the hwspinlock to be locked ++ * @timeout: timeout value in msecs ++ * @mode: mode which controls whether local interrupts are disabled or not ++ * @flags: a pointer to where the caller's interrupt state will be saved at (if ++ * requested) ++ * ++ * This function locks the given @hwlock. If the @hwlock ++ * is already taken, the function will busy loop waiting for it to ++ * be released, but give up after @timeout msecs have elapsed. ++ * ++ * Upon a successful return from this function, preemption is disabled ++ * (and possibly local interrupts, too), so the caller must not sleep, ++ * and is advised to release the hwspinlock as soon as possible. ++ * This is required in order to minimize remote cores polling on the ++ * hardware interconnect. ++ * ++ * The user decides whether local interrupts are disabled or not, and if yes, ++ * whether he wants their previous state to be saved. It is up to the user ++ * to choose the appropriate @mode of operation, exactly the same way users ++ * should decide between spin_lock, spin_lock_irq and spin_lock_irqsave. ++ * ++ * Returns 0 when the @hwlock was successfully taken, and an appropriate ++ * error code otherwise (most notably -ETIMEDOUT if the @hwlock is still ++ * busy after @timeout msecs). The function will never sleep. ++ */ ++int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to, ++ int mode, unsigned long *flags) ++{ ++ int ret; ++ unsigned long expire; ++ ++ expire = msecs_to_jiffies(to) + jiffies; ++ ++ for (;;) { ++ /* Try to take the hwspinlock */ ++ ret = __hwspin_trylock(hwlock, mode, flags); ++ if (ret != -EBUSY) ++ break; ++ ++ /* ++ * The lock is already taken, let's check if the user wants ++ * us to try again ++ */ ++ if (time_is_before_eq_jiffies(expire)) ++ return -ETIMEDOUT; ++ ++ /* ++ * Allow platform-specific relax handlers to prevent ++ * hogging the interconnect (no sleeping, though) ++ */ ++ if (hwlock->ops->relax) ++ hwlock->ops->relax(hwlock); ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(__hwspin_lock_timeout); ++ ++/** ++ * __hwspin_unlock() - unlock a specific hwspinlock ++ * @hwlock: a previously-acquired hwspinlock which we want to unlock ++ * @mode: controls whether local interrupts needs to be restored or not ++ * @flags: previous caller's interrupt state to restore (if requested) ++ * ++ * This function will unlock a specific hwspinlock, enable preemption and ++ * (possibly) enable interrupts or restore their previous state. ++ * @hwlock must be already locked before calling this function: it is a bug ++ * to call unlock on a @hwlock that is already unlocked. ++ * ++ * The user decides whether local interrupts should be enabled or not, and ++ * if yes, whether he wants their previous state to be restored. It is up ++ * to the user to choose the appropriate @mode of operation, exactly the ++ * same way users decide between spin_unlock, spin_unlock_irq and ++ * spin_unlock_irqrestore. ++ * ++ * The function will never sleep. ++ */ ++void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags) ++{ ++ BUG_ON(!hwlock); ++ BUG_ON(!flags && mode == HWLOCK_IRQSTATE); ++ ++ /* ++ * We must make sure that memory operations (both reads and writes), ++ * done before unlocking the hwspinlock, will not be reordered ++ * after the lock is released. ++ * ++ * That's the purpose of this explicit memory barrier. ++ * ++ * Note: the memory barrier induced by the spin_unlock below is too ++ * late; the other core is going to access memory soon after it will ++ * take the hwspinlock, and by then we want to be sure our memory ++ * operations are already observable. ++ */ ++ mb(); ++ ++ hwlock->ops->unlock(hwlock); ++ ++ /* Undo the spin_trylock{_irq, _irqsave} called while locking */ ++ if (mode == HWLOCK_IRQSTATE) ++ spin_unlock_irqrestore(&hwlock->lock, *flags); ++ else if (mode == HWLOCK_IRQ) ++ spin_unlock_irq(&hwlock->lock); ++ else ++ spin_unlock(&hwlock->lock); ++} ++EXPORT_SYMBOL_GPL(__hwspin_unlock); ++ ++/** ++ * hwspin_lock_register() - register a new hw spinlock ++ * @hwlock: hwspinlock to register. ++ * ++ * This function should be called from the underlying platform-specific ++ * implementation, to register a new hwspinlock instance. ++ * ++ * Can be called from an atomic context (will not sleep) but not from ++ * within interrupt context. ++ * ++ * Returns 0 on success, or an appropriate error code on failure ++ */ ++int hwspin_lock_register(struct hwspinlock *hwlock) ++{ ++ struct hwspinlock *tmp; ++ int ret; ++ ++ if (!hwlock || !hwlock->ops || ++ !hwlock->ops->trylock || !hwlock->ops->unlock) { ++ pr_err("invalid parameters\n"); ++ return -EINVAL; ++ } ++ ++ spin_lock_init(&hwlock->lock); ++ ++ spin_lock(&hwspinlock_tree_lock); ++ ++ ret = radix_tree_insert(&hwspinlock_tree, hwlock->id, hwlock); ++ if (ret) ++ goto out; ++ ++ /* mark this hwspinlock as available */ ++ tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id, ++ HWSPINLOCK_UNUSED); ++ ++ /* self-sanity check which should never fail */ ++ WARN_ON(tmp != hwlock); ++ ++out: ++ spin_unlock(&hwspinlock_tree_lock); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(hwspin_lock_register); ++ ++/** ++ * hwspin_lock_unregister() - unregister an hw spinlock ++ * @id: index of the specific hwspinlock to unregister ++ * ++ * This function should be called from the underlying platform-specific ++ * implementation, to unregister an existing (and unused) hwspinlock. ++ * ++ * Can be called from an atomic context (will not sleep) but not from ++ * within interrupt context. ++ * ++ * Returns the address of hwspinlock @id on success, or NULL on failure ++ */ ++struct hwspinlock *hwspin_lock_unregister(unsigned int id) ++{ ++ struct hwspinlock *hwlock = NULL; ++ int ret; ++ ++ spin_lock(&hwspinlock_tree_lock); ++ ++ /* make sure the hwspinlock is not in use (tag is set) */ ++ ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); ++ if (ret == 0) { ++ pr_err("hwspinlock %d still in use (or not present)\n", id); ++ goto out; ++ } ++ ++ hwlock = radix_tree_delete(&hwspinlock_tree, id); ++ if (!hwlock) { ++ pr_err("failed to delete hwspinlock %d\n", id); ++ goto out; ++ } ++ ++out: ++ spin_unlock(&hwspinlock_tree_lock); ++ return hwlock; ++} ++EXPORT_SYMBOL_GPL(hwspin_lock_unregister); ++ ++/** ++ * __hwspin_lock_request() - tag an hwspinlock as used and power it up ++ * ++ * This is an internal function that prepares an hwspinlock instance ++ * before it is given to the user. The function assumes that ++ * hwspinlock_tree_lock is taken. ++ * ++ * Returns 0 or positive to indicate success, and a negative value to ++ * indicate an error (with the appropriate error code) ++ */ ++static int __hwspin_lock_request(struct hwspinlock *hwlock) ++{ ++ struct hwspinlock *tmp; ++ int ret; ++ ++ /* prevent underlying implementation from being removed */ ++ if (!try_module_get(hwlock->owner)) { ++ dev_err(hwlock->dev, "%s: can't get owner\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* notify PM core that power is now needed */ ++ ret = pm_runtime_get_sync(hwlock->dev); ++ if (ret < 0) { ++ dev_err(hwlock->dev, "%s: can't power on device\n", __func__); ++ return ret; ++ } ++ ++ /* mark hwspinlock as used, should not fail */ ++ tmp = radix_tree_tag_clear(&hwspinlock_tree, hwlock->id, ++ HWSPINLOCK_UNUSED); ++ ++ /* self-sanity check that should never fail */ ++ WARN_ON(tmp != hwlock); ++ ++ return ret; ++} ++ ++/** ++ * hwspin_lock_get_id() - retrieve id number of a given hwspinlock ++ * @hwlock: a valid hwspinlock instance ++ * ++ * Returns the id number of a given @hwlock, or -EINVAL if @hwlock is invalid. ++ */ ++int hwspin_lock_get_id(struct hwspinlock *hwlock) ++{ ++ if (!hwlock) { ++ pr_err("invalid hwlock\n"); ++ return -EINVAL; ++ } ++ ++ return hwlock->id; ++} ++EXPORT_SYMBOL_GPL(hwspin_lock_get_id); ++ ++/** ++ * hwspin_lock_request() - request an hwspinlock ++ * ++ * This function should be called by users of the hwspinlock device, ++ * in order to dynamically assign them an unused hwspinlock. ++ * Usually the user of this lock will then have to communicate the lock's id ++ * to the remote core before it can be used for synchronization (to get the ++ * id of a given hwlock, use hwspin_lock_get_id()). ++ * ++ * Can be called from an atomic context (will not sleep) but not from ++ * within interrupt context (simply because there is no use case for ++ * that yet). ++ * ++ * Returns the address of the assigned hwspinlock, or NULL on error ++ */ ++struct hwspinlock *hwspin_lock_request(void) ++{ ++ struct hwspinlock *hwlock; ++ int ret; ++ ++ spin_lock(&hwspinlock_tree_lock); ++ ++ /* look for an unused lock */ ++ ret = radix_tree_gang_lookup_tag(&hwspinlock_tree, (void **)&hwlock, ++ 0, 1, HWSPINLOCK_UNUSED); ++ if (ret == 0) { ++ pr_warn("a free hwspinlock is not available\n"); ++ hwlock = NULL; ++ goto out; ++ } ++ ++ /* sanity check that should never fail */ ++ WARN_ON(ret > 1); ++ ++ /* mark as used and power up */ ++ ret = __hwspin_lock_request(hwlock); ++ if (ret < 0) ++ hwlock = NULL; ++ ++out: ++ spin_unlock(&hwspinlock_tree_lock); ++ return hwlock; ++} ++EXPORT_SYMBOL_GPL(hwspin_lock_request); ++ ++/** ++ * hwspin_lock_request_specific() - request for a specific hwspinlock ++ * @id: index of the specific hwspinlock that is requested ++ * ++ * This function should be called by users of the hwspinlock module, ++ * in order to assign them a specific hwspinlock. ++ * Usually early board code will be calling this function in order to ++ * reserve specific hwspinlock ids for predefined purposes. ++ * ++ * Can be called from an atomic context (will not sleep) but not from ++ * within interrupt context (simply because there is no use case for ++ * that yet). ++ * ++ * Returns the address of the assigned hwspinlock, or NULL on error ++ */ ++struct hwspinlock *hwspin_lock_request_specific(unsigned int id) ++{ ++ struct hwspinlock *hwlock; ++ int ret; ++ ++ spin_lock(&hwspinlock_tree_lock); ++ ++ /* make sure this hwspinlock exists */ ++ hwlock = radix_tree_lookup(&hwspinlock_tree, id); ++ if (!hwlock) { ++ pr_warn("hwspinlock %u does not exist\n", id); ++ goto out; ++ } ++ ++ /* sanity check (this shouldn't happen) */ ++ WARN_ON(hwlock->id != id); ++ ++ /* make sure this hwspinlock is unused */ ++ ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); ++ if (ret == 0) { ++ pr_warn("hwspinlock %u is already in use\n", id); ++ hwlock = NULL; ++ goto out; ++ } ++ ++ /* mark as used and power up */ ++ ret = __hwspin_lock_request(hwlock); ++ if (ret < 0) ++ hwlock = NULL; ++ ++out: ++ spin_unlock(&hwspinlock_tree_lock); ++ return hwlock; ++} ++EXPORT_SYMBOL_GPL(hwspin_lock_request_specific); ++ ++/** ++ * hwspin_lock_free() - free a specific hwspinlock ++ * @hwlock: the specific hwspinlock to free ++ * ++ * This function mark @hwlock as free again. ++ * Should only be called with an @hwlock that was retrieved from ++ * an earlier call to omap_hwspin_lock_request{_specific}. ++ * ++ * Can be called from an atomic context (will not sleep) but not from ++ * within interrupt context (simply because there is no use case for ++ * that yet). ++ * ++ * Returns 0 on success, or an appropriate error code on failure ++ */ ++int hwspin_lock_free(struct hwspinlock *hwlock) ++{ ++ struct hwspinlock *tmp; ++ int ret; ++ ++ if (!hwlock) { ++ pr_err("invalid hwlock\n"); ++ return -EINVAL; ++ } ++ ++ spin_lock(&hwspinlock_tree_lock); ++ ++ /* make sure the hwspinlock is used */ ++ ret = radix_tree_tag_get(&hwspinlock_tree, hwlock->id, ++ HWSPINLOCK_UNUSED); ++ if (ret == 1) { ++ dev_err(hwlock->dev, "%s: hwlock is already free\n", __func__); ++ dump_stack(); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ /* notify the underlying device that power is not needed */ ++ ret = pm_runtime_put(hwlock->dev); ++ if (ret < 0) ++ goto out; ++ ++ /* mark this hwspinlock as available */ ++ tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id, ++ HWSPINLOCK_UNUSED); ++ ++ /* sanity check (this shouldn't happen) */ ++ WARN_ON(tmp != hwlock); ++ ++ module_put(hwlock->owner); ++ ++out: ++ spin_unlock(&hwspinlock_tree_lock); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(hwspin_lock_free); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Hardware spinlock interface"); ++MODULE_AUTHOR("Ohad Ben-Cohen "); +diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_internal.h linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_internal.h +--- linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_internal.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_internal.h 2011-03-09 13:19:13.374435328 +0100 +@@ -0,0 +1,61 @@ ++/* ++ * Hardware spinlocks internal header ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com ++ * ++ * Contact: Ohad Ben-Cohen ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __HWSPINLOCK_HWSPINLOCK_H ++#define __HWSPINLOCK_HWSPINLOCK_H ++ ++#include ++#include ++ ++/** ++ * struct hwspinlock_ops - platform-specific hwspinlock handlers ++ * ++ * @trylock: make a single attempt to take the lock. returns 0 on ++ * failure and true on success. may _not_ sleep. ++ * @unlock: release the lock. always succeed. may _not_ sleep. ++ * @relax: optional, platform-specific relax handler, called by hwspinlock ++ * core while spinning on a lock, between two successive ++ * invocations of @trylock. may _not_ sleep. ++ */ ++struct hwspinlock_ops { ++ int (*trylock)(struct hwspinlock *lock); ++ void (*unlock)(struct hwspinlock *lock); ++ void (*relax)(struct hwspinlock *lock); ++}; ++ ++/** ++ * struct hwspinlock - this struct represents a single hwspinlock instance ++ * ++ * @dev: underlying device, will be used to invoke runtime PM api ++ * @ops: platform-specific hwspinlock handlers ++ * @id: a global, unique, system-wide, index of the lock. ++ * @lock: initialized and used by hwspinlock core ++ * @owner: underlying implementation module, used to maintain module ref count ++ * ++ * Note: currently simplicity was opted for, but later we can squeeze some ++ * memory bytes by grouping the dev, ops and owner members in a single ++ * per-platform struct, and have all hwspinlocks point at it. ++ */ ++struct hwspinlock { ++ struct device *dev; ++ const struct hwspinlock_ops *ops; ++ int id; ++ spinlock_t lock; ++ struct module *owner; ++}; ++ ++#endif /* __HWSPINLOCK_HWSPINLOCK_H */ +diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Kconfig +--- linux-2.6.38-rc7/drivers/hwspinlock/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Kconfig 2011-03-09 13:19:13.373435348 +0100 +@@ -0,0 +1,22 @@ ++# ++# Generic HWSPINLOCK framework ++# ++ ++config HWSPINLOCK ++ tristate "Generic Hardware Spinlock framework" ++ help ++ Say y here to support the generic hardware spinlock framework. ++ You only need to enable this if you have hardware spinlock module ++ on your system (usually only relevant if your system has remote slave ++ coprocessors). ++ ++ If unsure, say N. ++ ++config HWSPINLOCK_OMAP ++ tristate "OMAP Hardware Spinlock device" ++ depends on HWSPINLOCK && ARCH_OMAP4 ++ help ++ Say y here to support the OMAP Hardware Spinlock device (firstly ++ introduced in OMAP4). ++ ++ If unsure, say N. +diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/Makefile linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Makefile +--- linux-2.6.38-rc7/drivers/hwspinlock/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Makefile 2011-03-09 13:19:13.374435328 +0100 +@@ -0,0 +1,6 @@ ++# ++# Generic Hardware Spinlock framework ++# ++ ++obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o ++obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o +diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/omap_hwspinlock.c linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/omap_hwspinlock.c +--- linux-2.6.38-rc7/drivers/hwspinlock/omap_hwspinlock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/omap_hwspinlock.c 2011-03-09 13:19:13.374435328 +0100 +@@ -0,0 +1,231 @@ ++/* ++ * OMAP hardware spinlock driver ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com ++ * ++ * Contact: Simon Que ++ * Hari Kanigeri ++ * Ohad Ben-Cohen ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "hwspinlock_internal.h" ++ ++/* Spinlock register offsets */ ++#define SYSSTATUS_OFFSET 0x0014 ++#define LOCK_BASE_OFFSET 0x0800 ++ ++#define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) ++ ++/* Possible values of SPINLOCK_LOCK_REG */ ++#define SPINLOCK_NOTTAKEN (0) /* free */ ++#define SPINLOCK_TAKEN (1) /* locked */ ++ ++#define to_omap_hwspinlock(lock) \ ++ container_of(lock, struct omap_hwspinlock, lock) ++ ++struct omap_hwspinlock { ++ struct hwspinlock lock; ++ void __iomem *addr; ++}; ++ ++struct omap_hwspinlock_state { ++ int num_locks; /* Total number of locks in system */ ++ void __iomem *io_base; /* Mapped base address */ ++}; ++ ++static int omap_hwspinlock_trylock(struct hwspinlock *lock) ++{ ++ struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); ++ ++ /* attempt to acquire the lock by reading its value */ ++ return (SPINLOCK_NOTTAKEN == readl(omap_lock->addr)); ++} ++ ++static void omap_hwspinlock_unlock(struct hwspinlock *lock) ++{ ++ struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); ++ ++ /* release the lock by writing 0 to it */ ++ writel(SPINLOCK_NOTTAKEN, omap_lock->addr); ++} ++ ++/* ++ * relax the OMAP interconnect while spinning on it. ++ * ++ * The specs recommended that the retry delay time will be ++ * just over half of the time that a requester would be ++ * expected to hold the lock. ++ * ++ * The number below is taken from an hardware specs example, ++ * obviously it is somewhat arbitrary. ++ */ ++static void omap_hwspinlock_relax(struct hwspinlock *lock) ++{ ++ ndelay(50); ++} ++ ++static const struct hwspinlock_ops omap_hwspinlock_ops = { ++ .trylock = omap_hwspinlock_trylock, ++ .unlock = omap_hwspinlock_unlock, ++ .relax = omap_hwspinlock_relax, ++}; ++ ++static int __devinit omap_hwspinlock_probe(struct platform_device *pdev) ++{ ++ struct omap_hwspinlock *omap_lock; ++ struct omap_hwspinlock_state *state; ++ struct hwspinlock *lock; ++ struct resource *res; ++ void __iomem *io_base; ++ int i, ret; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -ENODEV; ++ ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return -ENOMEM; ++ ++ io_base = ioremap(res->start, resource_size(res)); ++ if (!io_base) { ++ ret = -ENOMEM; ++ goto free_state; ++ } ++ ++ /* Determine number of locks */ ++ i = readl(io_base + SYSSTATUS_OFFSET); ++ i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; ++ ++ /* one of the four lsb's must be set, and nothing else */ ++ if (hweight_long(i & 0xf) != 1 || i > 8) { ++ ret = -EINVAL; ++ goto iounmap_base; ++ } ++ ++ state->num_locks = i * 32; ++ state->io_base = io_base; ++ ++ platform_set_drvdata(pdev, state); ++ ++ /* ++ * runtime PM will make sure the clock of this module is ++ * enabled iff at least one lock is requested ++ */ ++ pm_runtime_enable(&pdev->dev); ++ ++ for (i = 0; i < state->num_locks; i++) { ++ omap_lock = kzalloc(sizeof(*omap_lock), GFP_KERNEL); ++ if (!omap_lock) { ++ ret = -ENOMEM; ++ goto free_locks; ++ } ++ ++ omap_lock->lock.dev = &pdev->dev; ++ omap_lock->lock.owner = THIS_MODULE; ++ omap_lock->lock.id = i; ++ omap_lock->lock.ops = &omap_hwspinlock_ops; ++ omap_lock->addr = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; ++ ++ ret = hwspin_lock_register(&omap_lock->lock); ++ if (ret) { ++ kfree(omap_lock); ++ goto free_locks; ++ } ++ } ++ ++ return 0; ++ ++free_locks: ++ while (--i >= 0) { ++ lock = hwspin_lock_unregister(i); ++ /* this should't happen, but let's give our best effort */ ++ if (!lock) { ++ dev_err(&pdev->dev, "%s: cleanups failed\n", __func__); ++ continue; ++ } ++ omap_lock = to_omap_hwspinlock(lock); ++ kfree(omap_lock); ++ } ++ pm_runtime_disable(&pdev->dev); ++iounmap_base: ++ iounmap(io_base); ++free_state: ++ kfree(state); ++ return ret; ++} ++ ++static int omap_hwspinlock_remove(struct platform_device *pdev) ++{ ++ struct omap_hwspinlock_state *state = platform_get_drvdata(pdev); ++ struct hwspinlock *lock; ++ struct omap_hwspinlock *omap_lock; ++ int i; ++ ++ for (i = 0; i < state->num_locks; i++) { ++ lock = hwspin_lock_unregister(i); ++ /* this shouldn't happen at this point. if it does, at least ++ * don't continue with the remove */ ++ if (!lock) { ++ dev_err(&pdev->dev, "%s: failed on %d\n", __func__, i); ++ return -EBUSY; ++ } ++ ++ omap_lock = to_omap_hwspinlock(lock); ++ kfree(omap_lock); ++ } ++ ++ pm_runtime_disable(&pdev->dev); ++ iounmap(state->io_base); ++ kfree(state); ++ ++ return 0; ++} ++ ++static struct platform_driver omap_hwspinlock_driver = { ++ .probe = omap_hwspinlock_probe, ++ .remove = omap_hwspinlock_remove, ++ .driver = { ++ .name = "omap_hwspinlock", ++ }, ++}; ++ ++static int __init omap_hwspinlock_init(void) ++{ ++ return platform_driver_register(&omap_hwspinlock_driver); ++} ++/* board init code might need to reserve hwspinlocks for predefined purposes */ ++postcore_initcall(omap_hwspinlock_init); ++ ++static void __exit omap_hwspinlock_exit(void) ++{ ++ platform_driver_unregister(&omap_hwspinlock_driver); ++} ++module_exit(omap_hwspinlock_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); ++MODULE_AUTHOR("Simon Que "); ++MODULE_AUTHOR("Hari Kanigeri "); ++MODULE_AUTHOR("Ohad Ben-Cohen "); +diff -Naur linux-2.6.38-rc7/drivers/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/Kconfig +--- linux-2.6.38-rc7/drivers/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/Kconfig 2011-03-09 13:19:12.865445652 +0100 +@@ -117,4 +117,6 @@ + source "drivers/platform/Kconfig" + + source "drivers/clk/Kconfig" ++ ++source "drivers/hwspinlock/Kconfig" + endmenu +diff -Naur linux-2.6.38-rc7/drivers/Makefile linux-2.6.38-rc7-linux-omap-dss2/drivers/Makefile +--- linux-2.6.38-rc7/drivers/Makefile 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/Makefile 2011-03-09 13:19:12.865445652 +0100 +@@ -117,3 +117,5 @@ + obj-y += ieee802154/ + #common clk code + obj-y += clk/ ++ ++obj-$(CONFIG_HWSPINLOCK) += hwspinlock/ +diff -Naur linux-2.6.38-rc7/drivers/mmc/host/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/Kconfig +--- linux-2.6.38-rc7/drivers/mmc/host/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/Kconfig 2011-03-09 13:19:15.003402284 +0100 +@@ -225,7 +225,7 @@ + + config MMC_OMAP_HS + tristate "TI OMAP High Speed Multimedia Card Interface support" +- depends on ARCH_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4 ++ depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4 + help + This selects the TI OMAP High Speed Multimedia card Interface. + If you have an OMAP2430 or OMAP3 board or OMAP4 board with a +diff -Naur linux-2.6.38-rc7/drivers/mmc/host/omap_hsmmc.c linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/omap_hsmmc.c +--- linux-2.6.38-rc7/drivers/mmc/host/omap_hsmmc.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/omap_hsmmc.c 2011-03-09 13:19:15.011402121 +0100 +@@ -118,7 +118,7 @@ + + #define MMC_TIMEOUT_MS 20 + #define OMAP_MMC_MASTER_CLOCK 96000000 +-#define DRIVER_NAME "mmci-omap-hs" ++#define DRIVER_NAME "omap_hsmmc" + + /* Timeouts for entering power saving states on inactivity, msec */ + #define OMAP_MMC_DISABLED_TIMEOUT 100 +@@ -260,7 +260,7 @@ + return ret; + } + +-static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, ++static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, + int vdd) + { + struct omap_hsmmc_host *host = +@@ -316,6 +316,12 @@ + return ret; + } + ++static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, ++ int vdd) ++{ ++ return 0; ++} ++ + static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, + int vdd, int cardsleep) + { +@@ -326,7 +332,7 @@ + return regulator_set_mode(host->vcc, mode); + } + +-static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, ++static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep, + int vdd, int cardsleep) + { + struct omap_hsmmc_host *host = +@@ -365,6 +371,12 @@ + return regulator_enable(host->vcc_aux); + } + ++static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep, ++ int vdd, int cardsleep) ++{ ++ return 0; ++} ++ + static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) + { + struct regulator *reg; +@@ -379,10 +391,14 @@ + break; + case OMAP_MMC2_DEVID: + case OMAP_MMC3_DEVID: ++ case OMAP_MMC5_DEVID: + /* Off-chip level shifting, or none */ +- mmc_slot(host).set_power = omap_hsmmc_23_set_power; +- mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; ++ mmc_slot(host).set_power = omap_hsmmc_235_set_power; ++ mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep; + break; ++ case OMAP_MMC4_DEVID: ++ mmc_slot(host).set_power = omap_hsmmc_4_set_power; ++ mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep; + default: + pr_err("MMC%d configuration not supported!\n", host->id); + return -EINVAL; +@@ -1555,7 +1571,7 @@ + break; + } + +- if (host->id == OMAP_MMC1_DEVID) { ++ if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { + /* Only MMC1 can interface at 3V without some flavor + * of external transceiver; but they all handle 1.8V. + */ +@@ -1647,7 +1663,7 @@ + u32 hctl, capa, value; + + /* Only MMC1 supports 3.0V */ +- if (host->id == OMAP_MMC1_DEVID) { ++ if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { + hctl = SDVS30; + capa = VS30 | VS18; + } else { +diff -Naur linux-2.6.38-rc7/drivers/mtd/nand/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/Kconfig +--- linux-2.6.38-rc7/drivers/mtd/nand/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/Kconfig 2011-03-09 13:19:15.269396887 +0100 +@@ -106,23 +106,6 @@ + help + Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms. + +-config MTD_NAND_OMAP_PREFETCH +- bool "GPMC prefetch support for NAND Flash device" +- depends on MTD_NAND_OMAP2 +- default y +- help +- The NAND device can be accessed for Read/Write using GPMC PREFETCH engine +- to improve the performance. +- +-config MTD_NAND_OMAP_PREFETCH_DMA +- depends on MTD_NAND_OMAP_PREFETCH +- bool "DMA mode" +- default n +- help +- The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode +- or in DMA interrupt mode. +- Say y for DMA mode or MPU mode will be used +- + config MTD_NAND_IDS + tristate + +diff -Naur linux-2.6.38-rc7/drivers/mtd/nand/omap2.c linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/omap2.c +--- linux-2.6.38-rc7/drivers/mtd/nand/omap2.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/omap2.c 2011-03-09 13:19:15.281396643 +0100 +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -24,6 +25,7 @@ + #include + + #define DRIVER_NAME "omap2-nand" ++#define OMAP_NAND_TIMEOUT_MS 5000 + + #define NAND_Ecc_P1e (1 << 0) + #define NAND_Ecc_P2e (1 << 1) +@@ -96,26 +98,19 @@ + static const char *part_probes[] = { "cmdlinepart", NULL }; + #endif + +-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH +-static int use_prefetch = 1; ++/* oob info generated runtime depending on ecc algorithm and layout selected */ ++static struct nand_ecclayout omap_oobinfo; ++/* Define some generic bad / good block scan pattern which are used ++ * while scanning a device for factory marked good / bad blocks ++ */ ++static uint8_t scan_ff_pattern[] = { 0xff }; ++static struct nand_bbt_descr bb_descrip_flashbased = { ++ .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, ++ .offs = 0, ++ .len = 1, ++ .pattern = scan_ff_pattern, ++}; + +-/* "modprobe ... use_prefetch=0" etc */ +-module_param(use_prefetch, bool, 0); +-MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH"); +- +-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA +-static int use_dma = 1; +- +-/* "modprobe ... use_dma=0" etc */ +-module_param(use_dma, bool, 0); +-MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); +-#else +-static const int use_dma; +-#endif +-#else +-const int use_prefetch; +-static const int use_dma; +-#endif + + struct omap_nand_info { + struct nand_hw_control controller; +@@ -129,6 +124,13 @@ + unsigned long phys_base; + struct completion comp; + int dma_ch; ++ int gpmc_irq; ++ enum { ++ OMAP_NAND_IO_READ = 0, /* read */ ++ OMAP_NAND_IO_WRITE, /* write */ ++ } iomode; ++ u_char *buf; ++ int buf_len; + }; + + /** +@@ -256,7 +258,8 @@ + } + + /* configure and start prefetch transfer */ +- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); ++ ret = gpmc_prefetch_enable(info->gpmc_cs, ++ PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); + if (ret) { + /* PFPW engine is busy, use cpu copy method */ + if (info->nand.options & NAND_BUSWIDTH_16) +@@ -288,9 +291,10 @@ + { + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); +- uint32_t pref_count = 0, w_count = 0; ++ uint32_t w_count = 0; + int i = 0, ret = 0; + u16 *p; ++ unsigned long tim, limit; + + /* take care of subpage writes */ + if (len % 2 != 0) { +@@ -300,7 +304,8 @@ + } + + /* configure and start prefetch transfer */ +- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); ++ ret = gpmc_prefetch_enable(info->gpmc_cs, ++ PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); + if (ret) { + /* PFPW engine is busy, use cpu copy method */ + if (info->nand.options & NAND_BUSWIDTH_16) +@@ -316,15 +321,17 @@ + iowrite16(*p++, info->nand.IO_ADDR_W); + } + /* wait for data to flushed-out before reset the prefetch */ +- do { +- pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT); +- } while (pref_count); ++ tim = 0; ++ limit = (loops_per_jiffy * ++ msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); ++ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) ++ cpu_relax(); ++ + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + } + } + +-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA + /* + * omap_nand_dma_cb: callback on the completion of dma transfer + * @lch: logical channel +@@ -348,14 +355,15 @@ + { + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); +- uint32_t prefetch_status = 0; + enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : + DMA_FROM_DEVICE; + dma_addr_t dma_addr; + int ret; ++ unsigned long tim, limit; + +- /* The fifo depth is 64 bytes. We have a sync at each frame and frame +- * length is 64 bytes. ++ /* The fifo depth is 64 bytes max. ++ * But configure the FIFO-threahold to 32 to get a sync at each frame ++ * and frame length is 32 bytes. + */ + int buf_len = len >> 6; + +@@ -396,9 +404,10 @@ + OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); + } + /* configure and start prefetch transfer */ +- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); ++ ret = gpmc_prefetch_enable(info->gpmc_cs, ++ PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write); + if (ret) +- /* PFPW engine is busy, use cpu copy methode */ ++ /* PFPW engine is busy, use cpu copy method */ + goto out_copy; + + init_completion(&info->comp); +@@ -407,10 +416,11 @@ + + /* setup and start DMA using dma_addr */ + wait_for_completion(&info->comp); ++ tim = 0; ++ limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); ++ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) ++ cpu_relax(); + +- do { +- prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT); +- } while (prefetch_status); + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + +@@ -426,14 +436,6 @@ + : omap_write_buf8(mtd, (u_char *) addr, len); + return 0; + } +-#else +-static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {} +-static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, +- unsigned int len, int is_write) +-{ +- return 0; +-} +-#endif + + /** + * omap_read_buf_dma_pref - read data from NAND controller into buffer +@@ -466,6 +468,157 @@ + omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); + } + ++/* ++ * omap_nand_irq - GMPC irq handler ++ * @this_irq: gpmc irq number ++ * @dev: omap_nand_info structure pointer is passed here ++ */ ++static irqreturn_t omap_nand_irq(int this_irq, void *dev) ++{ ++ struct omap_nand_info *info = (struct omap_nand_info *) dev; ++ u32 bytes; ++ u32 irq_stat; ++ ++ irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); ++ bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); ++ bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ ++ if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ ++ if (irq_stat & 0x2) ++ goto done; ++ ++ if (info->buf_len && (info->buf_len < bytes)) ++ bytes = info->buf_len; ++ else if (!info->buf_len) ++ bytes = 0; ++ iowrite32_rep(info->nand.IO_ADDR_W, ++ (u32 *)info->buf, bytes >> 2); ++ info->buf = info->buf + bytes; ++ info->buf_len -= bytes; ++ ++ } else { ++ ioread32_rep(info->nand.IO_ADDR_R, ++ (u32 *)info->buf, bytes >> 2); ++ info->buf = info->buf + bytes; ++ ++ if (irq_stat & 0x2) ++ goto done; ++ } ++ gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); ++ ++ return IRQ_HANDLED; ++ ++done: ++ complete(&info->comp); ++ /* disable irq */ ++ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); ++ ++ /* clear status */ ++ gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * omap_read_buf_irq_pref - read data from NAND controller into buffer ++ * @mtd: MTD device structure ++ * @buf: buffer to store date ++ * @len: number of bytes to read ++ */ ++static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ struct omap_nand_info *info = container_of(mtd, ++ struct omap_nand_info, mtd); ++ int ret = 0; ++ ++ if (len <= mtd->oobsize) { ++ omap_read_buf_pref(mtd, buf, len); ++ return; ++ } ++ ++ info->iomode = OMAP_NAND_IO_READ; ++ info->buf = buf; ++ init_completion(&info->comp); ++ ++ /* configure and start prefetch transfer */ ++ ret = gpmc_prefetch_enable(info->gpmc_cs, ++ PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); ++ if (ret) ++ /* PFPW engine is busy, use cpu copy method */ ++ goto out_copy; ++ ++ info->buf_len = len; ++ /* enable irq */ ++ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, ++ (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); ++ ++ /* waiting for read to complete */ ++ wait_for_completion(&info->comp); ++ ++ /* disable and stop the PFPW engine */ ++ gpmc_prefetch_reset(info->gpmc_cs); ++ return; ++ ++out_copy: ++ if (info->nand.options & NAND_BUSWIDTH_16) ++ omap_read_buf16(mtd, buf, len); ++ else ++ omap_read_buf8(mtd, buf, len); ++} ++ ++/* ++ * omap_write_buf_irq_pref - write buffer to NAND controller ++ * @mtd: MTD device structure ++ * @buf: data buffer ++ * @len: number of bytes to write ++ */ ++static void omap_write_buf_irq_pref(struct mtd_info *mtd, ++ const u_char *buf, int len) ++{ ++ struct omap_nand_info *info = container_of(mtd, ++ struct omap_nand_info, mtd); ++ int ret = 0; ++ unsigned long tim, limit; ++ ++ if (len <= mtd->oobsize) { ++ omap_write_buf_pref(mtd, buf, len); ++ return; ++ } ++ ++ info->iomode = OMAP_NAND_IO_WRITE; ++ info->buf = (u_char *) buf; ++ init_completion(&info->comp); ++ ++ /* configure and start prefetch transfer : size=24 */ ++ ret = gpmc_prefetch_enable(info->gpmc_cs, ++ (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1); ++ if (ret) ++ /* PFPW engine is busy, use cpu copy method */ ++ goto out_copy; ++ ++ info->buf_len = len; ++ /* enable irq */ ++ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, ++ (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); ++ ++ /* waiting for write to complete */ ++ wait_for_completion(&info->comp); ++ /* wait for data to flushed-out before reset the prefetch */ ++ tim = 0; ++ limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); ++ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) ++ cpu_relax(); ++ ++ /* disable and stop the PFPW engine */ ++ gpmc_prefetch_reset(info->gpmc_cs); ++ return; ++ ++out_copy: ++ if (info->nand.options & NAND_BUSWIDTH_16) ++ omap_write_buf16(mtd, buf, len); ++ else ++ omap_write_buf8(mtd, buf, len); ++} ++ + /** + * omap_verify_buf - Verify chip data against buffer + * @mtd: MTD device structure +@@ -487,8 +640,6 @@ + return 0; + } + +-#ifdef CONFIG_MTD_NAND_OMAP_HWECC +- + /** + * gen_true_ecc - This function will generate true ECC value + * @ecc_buf: buffer to store ecc code +@@ -708,8 +859,6 @@ + gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); + } + +-#endif +- + /** + * omap_wait - wait until the command is done + * @mtd: MTD device structure +@@ -779,6 +928,7 @@ + struct omap_nand_info *info; + struct omap_nand_platform_data *pdata; + int err; ++ int i, offset; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) { +@@ -804,7 +954,7 @@ + info->mtd.name = dev_name(&pdev->dev); + info->mtd.owner = THIS_MODULE; + +- info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0; ++ info->nand.options = pdata->devsize; + info->nand.options |= NAND_SKIP_BBTSCAN; + + /* NAND write protect off */ +@@ -842,28 +992,13 @@ + info->nand.chip_delay = 50; + } + +- if (use_prefetch) { +- ++ switch (pdata->xfer_type) { ++ case NAND_OMAP_PREFETCH_POLLED: + info->nand.read_buf = omap_read_buf_pref; + info->nand.write_buf = omap_write_buf_pref; +- if (use_dma) { +- err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", +- omap_nand_dma_cb, &info->comp, &info->dma_ch); +- if (err < 0) { +- info->dma_ch = -1; +- printk(KERN_WARNING "DMA request failed." +- " Non-dma data transfer mode\n"); +- } else { +- omap_set_dma_dest_burst_mode(info->dma_ch, +- OMAP_DMA_DATA_BURST_16); +- omap_set_dma_src_burst_mode(info->dma_ch, +- OMAP_DMA_DATA_BURST_16); +- +- info->nand.read_buf = omap_read_buf_dma_pref; +- info->nand.write_buf = omap_write_buf_dma_pref; +- } +- } +- } else { ++ break; ++ ++ case NAND_OMAP_POLLED: + if (info->nand.options & NAND_BUSWIDTH_16) { + info->nand.read_buf = omap_read_buf16; + info->nand.write_buf = omap_write_buf16; +@@ -871,20 +1006,61 @@ + info->nand.read_buf = omap_read_buf8; + info->nand.write_buf = omap_write_buf8; + } ++ break; ++ ++ case NAND_OMAP_PREFETCH_DMA: ++ err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", ++ omap_nand_dma_cb, &info->comp, &info->dma_ch); ++ if (err < 0) { ++ info->dma_ch = -1; ++ dev_err(&pdev->dev, "DMA request failed!\n"); ++ goto out_release_mem_region; ++ } else { ++ omap_set_dma_dest_burst_mode(info->dma_ch, ++ OMAP_DMA_DATA_BURST_16); ++ omap_set_dma_src_burst_mode(info->dma_ch, ++ OMAP_DMA_DATA_BURST_16); ++ ++ info->nand.read_buf = omap_read_buf_dma_pref; ++ info->nand.write_buf = omap_write_buf_dma_pref; ++ } ++ break; ++ ++ case NAND_OMAP_PREFETCH_IRQ: ++ err = request_irq(pdata->gpmc_irq, ++ omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); ++ if (err) { ++ dev_err(&pdev->dev, "requesting irq(%d) error:%d", ++ pdata->gpmc_irq, err); ++ goto out_release_mem_region; ++ } else { ++ info->gpmc_irq = pdata->gpmc_irq; ++ info->nand.read_buf = omap_read_buf_irq_pref; ++ info->nand.write_buf = omap_write_buf_irq_pref; ++ } ++ break; ++ ++ default: ++ dev_err(&pdev->dev, ++ "xfer_type(%d) not supported!\n", pdata->xfer_type); ++ err = -EINVAL; ++ goto out_release_mem_region; + } +- info->nand.verify_buf = omap_verify_buf; + +-#ifdef CONFIG_MTD_NAND_OMAP_HWECC +- info->nand.ecc.bytes = 3; +- info->nand.ecc.size = 512; +- info->nand.ecc.calculate = omap_calculate_ecc; +- info->nand.ecc.hwctl = omap_enable_hwecc; +- info->nand.ecc.correct = omap_correct_data; +- info->nand.ecc.mode = NAND_ECC_HW; ++ info->nand.verify_buf = omap_verify_buf; + +-#else +- info->nand.ecc.mode = NAND_ECC_SOFT; +-#endif ++ /* selsect the ecc type */ ++ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) ++ info->nand.ecc.mode = NAND_ECC_SOFT; ++ else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || ++ (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { ++ info->nand.ecc.bytes = 3; ++ info->nand.ecc.size = 512; ++ info->nand.ecc.calculate = omap_calculate_ecc; ++ info->nand.ecc.hwctl = omap_enable_hwecc; ++ info->nand.ecc.correct = omap_correct_data; ++ info->nand.ecc.mode = NAND_ECC_HW; ++ } + + /* DIP switches on some boards change between 8 and 16 bit + * bus widths for flash. Try the other width if the first try fails. +@@ -897,6 +1073,26 @@ + } + } + ++ /* rom code layout */ ++ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { ++ ++ if (info->nand.options & NAND_BUSWIDTH_16) ++ offset = 2; ++ else { ++ offset = 1; ++ info->nand.badblock_pattern = &bb_descrip_flashbased; ++ } ++ omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); ++ for (i = 0; i < omap_oobinfo.eccbytes; i++) ++ omap_oobinfo.eccpos[i] = i+offset; ++ ++ omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; ++ omap_oobinfo.oobfree->length = info->mtd.oobsize - ++ (offset + omap_oobinfo.eccbytes); ++ ++ info->nand.ecc.layout = &omap_oobinfo; ++ } ++ + #ifdef CONFIG_MTD_PARTITIONS + err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); + if (err > 0) +@@ -926,9 +1122,12 @@ + mtd); + + platform_set_drvdata(pdev, NULL); +- if (use_dma) ++ if (info->dma_ch != -1) + omap_free_dma(info->dma_ch); + ++ if (info->gpmc_irq) ++ free_irq(info->gpmc_irq, info); ++ + /* Release NAND device, its internal structures and partitions */ + nand_release(&info->mtd); + iounmap(info->nand.IO_ADDR_R); +@@ -947,16 +1146,8 @@ + + static int __init omap_nand_init(void) + { +- printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME); ++ pr_info("%s driver initializing\n", DRIVER_NAME); + +- /* This check is required if driver is being +- * loaded run time as a module +- */ +- if ((1 == use_dma) && (0 == use_prefetch)) { +- printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 " +- "without use_prefetch'. Prefetch will not be" +- " used in either mode (mpu or dma)\n"); +- } + return platform_driver_register(&omap_nand_driver); + } + +diff -Naur linux-2.6.38-rc7/drivers/mtd/onenand/omap2.c linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/onenand/omap2.c +--- linux-2.6.38-rc7/drivers/mtd/onenand/omap2.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/onenand/omap2.c 2011-03-09 13:19:15.286396542 +0100 +@@ -63,7 +63,7 @@ + struct completion dma_done; + int dma_channel; + int freq; +- int (*setup)(void __iomem *base, int freq); ++ int (*setup)(void __iomem *base, int *freq_ptr); + struct regulator *regulator; + }; + +@@ -148,11 +148,9 @@ + wait_err("controller error", state, ctrl, intr); + return -EIO; + } +- if ((intr & intr_flags) != intr_flags) { +- wait_err("timeout", state, ctrl, intr); +- return -EIO; +- } +- return 0; ++ if ((intr & intr_flags) == intr_flags) ++ return 0; ++ /* Continue in wait for interrupt branch */ + } + + if (state != FL_READING) { +@@ -581,7 +579,7 @@ + + /* DMA is not in use so this is all that is needed */ + /* Revisit for OMAP3! */ +- ret = c->setup(c->onenand.base, c->freq); ++ ret = c->setup(c->onenand.base, &c->freq); + + return ret; + } +@@ -673,7 +671,7 @@ + } + + if (pdata->onenand_setup != NULL) { +- r = pdata->onenand_setup(c->onenand.base, c->freq); ++ r = pdata->onenand_setup(c->onenand.base, &c->freq); + if (r < 0) { + dev_err(&pdev->dev, "Onenand platform setup failed: " + "%d\n", r); +@@ -718,8 +716,8 @@ + } + + dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual " +- "base %p\n", c->gpmc_cs, c->phys_base, +- c->onenand.base); ++ "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base, ++ c->onenand.base, c->freq); + + c->pdev = pdev; + c->mtd.name = dev_name(&pdev->dev); +@@ -754,24 +752,6 @@ + if ((r = onenand_scan(&c->mtd, 1)) < 0) + goto err_release_regulator; + +- switch ((c->onenand.version_id >> 4) & 0xf) { +- case 0: +- c->freq = 40; +- break; +- case 1: +- c->freq = 54; +- break; +- case 2: +- c->freq = 66; +- break; +- case 3: +- c->freq = 83; +- break; +- case 4: +- c->freq = 104; +- break; +- } +- + #ifdef CONFIG_MTD_PARTITIONS + r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0); + if (r > 0) +diff -Naur linux-2.6.38-rc7/drivers/spi/omap2_mcspi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/spi/omap2_mcspi.c +--- linux-2.6.38-rc7/drivers/spi/omap2_mcspi.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/spi/omap2_mcspi.c 2011-03-09 13:19:17.550350615 +0100 +@@ -3,7 +3,7 @@ + * + * Copyright (C) 2005, 2006 Nokia Corporation + * Author: Samuel Ortiz and +- * Juha Yrjölä ++ * Juha Yrj�l� + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + + #include + +@@ -46,7 +47,6 @@ + #define OMAP2_MCSPI_MAX_CTRL 4 + + #define OMAP2_MCSPI_REVISION 0x00 +-#define OMAP2_MCSPI_SYSCONFIG 0x10 + #define OMAP2_MCSPI_SYSSTATUS 0x14 + #define OMAP2_MCSPI_IRQSTATUS 0x18 + #define OMAP2_MCSPI_IRQENABLE 0x1c +@@ -63,13 +63,6 @@ + + /* per-register bitmasks: */ + +-#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4) +-#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) +-#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) +-#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1) +- +-#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0) +- + #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) + #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) + #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) +@@ -122,13 +115,12 @@ + spinlock_t lock; + struct list_head msg_queue; + struct spi_master *master; +- struct clk *ick; +- struct clk *fck; + /* Virtual base address of the controller */ + void __iomem *base; + unsigned long phys; + /* SPI1 has 4 channels, while SPI2 has 2 */ + struct omap2_mcspi_dma *dma_channels; ++ struct device *dev; + }; + + struct omap2_mcspi_cs { +@@ -144,7 +136,6 @@ + * corresponding registers are modified. + */ + struct omap2_mcspi_regs { +- u32 sysconfig; + u32 modulctrl; + u32 wakeupenable; + struct list_head cs; +@@ -268,9 +259,6 @@ + mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, + omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); + +- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG, +- omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig); +- + mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, + omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); + +@@ -280,20 +268,12 @@ + } + static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) + { +- clk_disable(mcspi->ick); +- clk_disable(mcspi->fck); ++ pm_runtime_put_sync(mcspi->dev); + } + + static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) + { +- if (clk_enable(mcspi->ick)) +- return -ENODEV; +- if (clk_enable(mcspi->fck)) +- return -ENODEV; +- +- omap2_mcspi_restore_ctx(mcspi); +- +- return 0; ++ return pm_runtime_get_sync(mcspi->dev); + } + + static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) +@@ -819,8 +799,9 @@ + return ret; + } + +- if (omap2_mcspi_enable_clocks(mcspi)) +- return -ENODEV; ++ ret = omap2_mcspi_enable_clocks(mcspi); ++ if (ret < 0) ++ return ret; + + ret = omap2_mcspi_setup_transfer(spi, NULL); + omap2_mcspi_disable_clocks(mcspi); +@@ -863,10 +844,11 @@ + struct omap2_mcspi *mcspi; + + mcspi = container_of(work, struct omap2_mcspi, work); +- spin_lock_irq(&mcspi->lock); + +- if (omap2_mcspi_enable_clocks(mcspi)) +- goto out; ++ if (omap2_mcspi_enable_clocks(mcspi) < 0) ++ return; ++ ++ spin_lock_irq(&mcspi->lock); + + /* We only enable one channel at a time -- the one whose message is + * at the head of the queue -- although this controller would gladly +@@ -979,10 +961,9 @@ + spin_lock_irq(&mcspi->lock); + } + +- omap2_mcspi_disable_clocks(mcspi); +- +-out: + spin_unlock_irq(&mcspi->lock); ++ ++ omap2_mcspi_disable_clocks(mcspi); + } + + static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) +@@ -1058,25 +1039,15 @@ + return 0; + } + +-static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) ++static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) + { + struct spi_master *master = mcspi->master; + u32 tmp; ++ int ret = 0; + +- if (omap2_mcspi_enable_clocks(mcspi)) +- return -1; +- +- mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, +- OMAP2_MCSPI_SYSCONFIG_SOFTRESET); +- do { +- tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS); +- } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE)); +- +- tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE | +- OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP | +- OMAP2_MCSPI_SYSCONFIG_SMARTIDLE; +- mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp); +- omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp; ++ ret = omap2_mcspi_enable_clocks(mcspi); ++ if (ret < 0) ++ return ret; + + tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; + mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); +@@ -1087,91 +1058,26 @@ + return 0; + } + +-static u8 __initdata spi1_rxdma_id [] = { +- OMAP24XX_DMA_SPI1_RX0, +- OMAP24XX_DMA_SPI1_RX1, +- OMAP24XX_DMA_SPI1_RX2, +- OMAP24XX_DMA_SPI1_RX3, +-}; +- +-static u8 __initdata spi1_txdma_id [] = { +- OMAP24XX_DMA_SPI1_TX0, +- OMAP24XX_DMA_SPI1_TX1, +- OMAP24XX_DMA_SPI1_TX2, +- OMAP24XX_DMA_SPI1_TX3, +-}; +- +-static u8 __initdata spi2_rxdma_id[] = { +- OMAP24XX_DMA_SPI2_RX0, +- OMAP24XX_DMA_SPI2_RX1, +-}; +- +-static u8 __initdata spi2_txdma_id[] = { +- OMAP24XX_DMA_SPI2_TX0, +- OMAP24XX_DMA_SPI2_TX1, +-}; +- +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ +- || defined(CONFIG_ARCH_OMAP4) +-static u8 __initdata spi3_rxdma_id[] = { +- OMAP24XX_DMA_SPI3_RX0, +- OMAP24XX_DMA_SPI3_RX1, +-}; ++static int omap_mcspi_runtime_resume(struct device *dev) ++{ ++ struct omap2_mcspi *mcspi; ++ struct spi_master *master; + +-static u8 __initdata spi3_txdma_id[] = { +- OMAP24XX_DMA_SPI3_TX0, +- OMAP24XX_DMA_SPI3_TX1, +-}; +-#endif ++ master = dev_get_drvdata(dev); ++ mcspi = spi_master_get_devdata(master); ++ omap2_mcspi_restore_ctx(mcspi); + +-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) +-static u8 __initdata spi4_rxdma_id[] = { +- OMAP34XX_DMA_SPI4_RX0, +-}; ++ return 0; ++} + +-static u8 __initdata spi4_txdma_id[] = { +- OMAP34XX_DMA_SPI4_TX0, +-}; +-#endif + + static int __init omap2_mcspi_probe(struct platform_device *pdev) + { + struct spi_master *master; ++ struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data; + struct omap2_mcspi *mcspi; + struct resource *r; + int status = 0, i; +- const u8 *rxdma_id, *txdma_id; +- unsigned num_chipselect; +- +- switch (pdev->id) { +- case 1: +- rxdma_id = spi1_rxdma_id; +- txdma_id = spi1_txdma_id; +- num_chipselect = 4; +- break; +- case 2: +- rxdma_id = spi2_rxdma_id; +- txdma_id = spi2_txdma_id; +- num_chipselect = 2; +- break; +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ +- || defined(CONFIG_ARCH_OMAP4) +- case 3: +- rxdma_id = spi3_rxdma_id; +- txdma_id = spi3_txdma_id; +- num_chipselect = 2; +- break; +-#endif +-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) +- case 4: +- rxdma_id = spi4_rxdma_id; +- txdma_id = spi4_txdma_id; +- num_chipselect = 1; +- break; +-#endif +- default: +- return -EINVAL; +- } + + master = spi_alloc_master(&pdev->dev, sizeof *mcspi); + if (master == NULL) { +@@ -1188,7 +1094,7 @@ + master->setup = omap2_mcspi_setup; + master->transfer = omap2_mcspi_transfer; + master->cleanup = omap2_mcspi_cleanup; +- master->num_chipselect = num_chipselect; ++ master->num_chipselect = pdata->num_cs; + + dev_set_drvdata(&pdev->dev, master); + +@@ -1206,49 +1112,62 @@ + goto err1; + } + ++ r->start += pdata->regs_offset; ++ r->end += pdata->regs_offset; + mcspi->phys = r->start; + mcspi->base = ioremap(r->start, r->end - r->start + 1); + if (!mcspi->base) { + dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); + status = -ENOMEM; +- goto err1aa; ++ goto err2; + } + ++ mcspi->dev = &pdev->dev; + INIT_WORK(&mcspi->work, omap2_mcspi_work); + + spin_lock_init(&mcspi->lock); + INIT_LIST_HEAD(&mcspi->msg_queue); + INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); + +- mcspi->ick = clk_get(&pdev->dev, "ick"); +- if (IS_ERR(mcspi->ick)) { +- dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); +- status = PTR_ERR(mcspi->ick); +- goto err1a; +- } +- mcspi->fck = clk_get(&pdev->dev, "fck"); +- if (IS_ERR(mcspi->fck)) { +- dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); +- status = PTR_ERR(mcspi->fck); +- goto err2; +- } +- + mcspi->dma_channels = kcalloc(master->num_chipselect, + sizeof(struct omap2_mcspi_dma), + GFP_KERNEL); + + if (mcspi->dma_channels == NULL) +- goto err3; ++ goto err2; ++ ++ for (i = 0; i < master->num_chipselect; i++) { ++ char dma_ch_name[14]; ++ struct resource *dma_res; ++ ++ sprintf(dma_ch_name, "rx%d", i); ++ dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, ++ dma_ch_name); ++ if (!dma_res) { ++ dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); ++ status = -ENODEV; ++ break; ++ } + +- for (i = 0; i < num_chipselect; i++) { + mcspi->dma_channels[i].dma_rx_channel = -1; +- mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; ++ mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; ++ sprintf(dma_ch_name, "tx%d", i); ++ dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, ++ dma_ch_name); ++ if (!dma_res) { ++ dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); ++ status = -ENODEV; ++ break; ++ } ++ + mcspi->dma_channels[i].dma_tx_channel = -1; +- mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; ++ mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; + } + +- if (omap2_mcspi_reset(mcspi) < 0) +- goto err4; ++ pm_runtime_enable(&pdev->dev); ++ ++ if (status || omap2_mcspi_master_setup(mcspi) < 0) ++ goto err3; + + status = spi_register_master(master); + if (status < 0) +@@ -1257,17 +1176,13 @@ + return status; + + err4: +- kfree(mcspi->dma_channels); ++ spi_master_put(master); + err3: +- clk_put(mcspi->fck); ++ kfree(mcspi->dma_channels); + err2: +- clk_put(mcspi->ick); +-err1a: +- iounmap(mcspi->base); +-err1aa: + release_mem_region(r->start, (r->end - r->start) + 1); ++ iounmap(mcspi->base); + err1: +- spi_master_put(master); + return status; + } + +@@ -1283,9 +1198,7 @@ + mcspi = spi_master_get_devdata(master); + dma_channels = mcspi->dma_channels; + +- clk_put(mcspi->fck); +- clk_put(mcspi->ick); +- ++ omap2_mcspi_disable_clocks(mcspi); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, (r->end - r->start) + 1); + +@@ -1336,6 +1249,7 @@ + + static const struct dev_pm_ops omap2_mcspi_pm_ops = { + .resume = omap2_mcspi_resume, ++ .runtime_resume = omap_mcspi_runtime_resume, + }; + + static struct platform_driver omap2_mcspi_driver = { +diff -Naur linux-2.6.38-rc7/drivers/usb/musb/musb_core.c linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.c +--- linux-2.6.38-rc7/drivers/usb/musb/musb_core.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.c 2011-03-09 13:19:19.480311463 +0100 +@@ -1530,7 +1530,7 @@ + + /*-------------------------------------------------------------------------*/ + +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \ ++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ + defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \ + defined(CONFIG_ARCH_U5500) + +diff -Naur linux-2.6.38-rc7/drivers/usb/musb/musb_core.h linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.h +--- linux-2.6.38-rc7/drivers/usb/musb/musb_core.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.h 2011-03-09 13:19:19.480311463 +0100 +@@ -212,8 +212,8 @@ + * directly with the "flat" model, or after setting up an index register. + */ + +-#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \ +- || defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN) \ ++#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \ ++ || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \ + || defined(CONFIG_ARCH_OMAP4) + /* REVISIT indexed access seemed to + * misbehave (on DaVinci) for at least peripheral IN ... +@@ -358,7 +358,7 @@ + + struct musb_context_registers { + +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ ++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) + u32 otg_sysconfig, otg_forcestandby; + #endif +diff -Naur linux-2.6.38-rc7/drivers/usb/musb/musbhsdma.h linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musbhsdma.h +--- linux-2.6.38-rc7/drivers/usb/musb/musbhsdma.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musbhsdma.h 2011-03-09 13:19:19.484311381 +0100 +@@ -31,7 +31,7 @@ + * + */ + +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) ++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) + #include "omap2430.h" + #endif + +diff -Naur linux-2.6.38-rc7/drivers/usb/otg/isp1301_omap.c linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/otg/isp1301_omap.c +--- linux-2.6.38-rc7/drivers/usb/otg/isp1301_omap.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/otg/isp1301_omap.c 2011-03-09 13:19:19.487311321 +0100 +@@ -1510,7 +1510,7 @@ + + /*-------------------------------------------------------------------------*/ + +-static int __init ++static int __devinit + isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id) + { + int status; +diff -Naur linux-2.6.38-rc7/drivers/video/omap/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap/Kconfig +--- linux-2.6.38-rc7/drivers/video/omap/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap/Kconfig 2011-03-09 13:19:21.072279166 +0100 +@@ -5,13 +5,18 @@ + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT ++ select TWL4030_CORE if MACH_OMAP_2430SDP + help + Frame buffer driver for OMAP based boards. + + config FB_OMAP_LCD_VGA + bool "Use LCD in VGA mode" + depends on MACH_OMAP_3430SDP || MACH_OMAP_LDP +- ++ help ++ Set LCD resolution as VGA (640 X 480). ++ Default resolution without this option is QVGA(320 X 240). ++ Please take a look at drivers/video/omap/lcd_ldp.c file ++ for lcd driver code. + choice + depends on FB_OMAP && MACH_OVERO + prompt "Screen resolution" +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Kconfig +--- linux-2.6.38-rc7/drivers/video/omap2/displays/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Kconfig 2011-03-09 13:19:21.079279025 +0100 +@@ -9,6 +9,12 @@ + Supports LCD Panel used in TI SDP3430 and EVM boards, + OMAP3517 EVM boards and CM-T35. + ++config PANEL_LGPHILIPS_LB035Q02 ++ tristate "LG.Philips LB035Q02 LCD Panel" ++ depends on OMAP2_DSS && SPI ++ help ++ LCD Panel used on the Gumstix Overo Palo35 ++ + config PANEL_SHARP_LS037V7DW01 + tristate "Sharp LS037V7DW01 LCD Panel" + depends on OMAP2_DSS +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/Makefile linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Makefile +--- linux-2.6.38-rc7/drivers/video/omap2/displays/Makefile 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Makefile 2011-03-09 13:19:21.079279025 +0100 +@@ -1,4 +1,5 @@ + obj-$(CONFIG_PANEL_GENERIC_DPI) += panel-generic-dpi.o ++obj-$(CONFIG_PANEL_LGPHILIPS_LB035Q02) += panel-lgphilips-lb035q02.o + obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o + obj-$(CONFIG_PANEL_NEC_NL8048HL11_01B) += panel-nec-nl8048hl11-01b.o + +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/panel-generic-dpi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-generic-dpi.c +--- linux-2.6.38-rc7/drivers/video/omap2/displays/panel-generic-dpi.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-generic-dpi.c 2011-03-09 13:19:21.080279004 +0100 +@@ -156,6 +156,31 @@ + .power_off_delay = 0, + .name = "toppoly_tdo35s", + }, ++ ++ /* Samsung LTE430WQ-F0C */ ++ { ++ { ++ .x_res = 480, ++ .y_res = 272, ++ ++ .pixel_clock = 9200, ++ ++ .hfp = 8, ++ .hsw = 41, ++ .hbp = 45 - 41, ++ ++ .vfp = 4, ++ .vsw = 10, ++ .vbp = 12 - 10, ++ }, ++ .acbi = 0x0, ++ .acb = 0x0, ++ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | ++ OMAP_DSS_LCD_IHS, ++ .power_on_delay = 0, ++ .power_off_delay = 0, ++ .name = "samsung_lte430wq_f0c", ++ }, + }; + + struct panel_drv_data { +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c +--- linux-2.6.38-rc7/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c 2011-03-09 13:19:21.080279004 +0100 +@@ -0,0 +1,279 @@ ++/* ++ * LCD panel driver for LG.Philips LB035Q02 ++ * ++ * Author: Steve Sakoman ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++struct lb035q02_data { ++ struct mutex lock; ++}; ++ ++static struct omap_video_timings lb035q02_timings = { ++ .x_res = 320, ++ .y_res = 240, ++ ++ .pixel_clock = 6500, ++ ++ .hsw = 2, ++ .hfp = 20, ++ .hbp = 68, ++ ++ .vsw = 2, ++ .vfp = 4, ++ .vbp = 18, ++}; ++ ++static int lb035q02_panel_power_on(struct omap_dss_device *dssdev) ++{ ++ int r; ++ ++ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) ++ return 0; ++ ++ r = omapdss_dpi_display_enable(dssdev); ++ if (r) ++ goto err0; ++ ++ if (dssdev->platform_enable) { ++ r = dssdev->platform_enable(dssdev); ++ if (r) ++ goto err1; ++ } ++ ++ return 0; ++err1: ++ omapdss_dpi_display_disable(dssdev); ++err0: ++ return r; ++} ++ ++static void lb035q02_panel_power_off(struct omap_dss_device *dssdev) ++{ ++ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) ++ return; ++ ++ if (dssdev->platform_disable) ++ dssdev->platform_disable(dssdev); ++ ++ omapdss_dpi_display_disable(dssdev); ++} ++ ++static int lb035q02_panel_probe(struct omap_dss_device *dssdev) ++{ ++ struct lb035q02_data *ld; ++ int r; ++ ++ dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | ++ OMAP_DSS_LCD_IHS; ++ dssdev->panel.timings = lb035q02_timings; ++ ++ ld = kzalloc(sizeof(*ld), GFP_KERNEL); ++ if (!ld) { ++ r = -ENOMEM; ++ goto err; ++ } ++ mutex_init(&ld->lock); ++ dev_set_drvdata(&dssdev->dev, ld); ++ return 0; ++err: ++ return r; ++} ++ ++static void lb035q02_panel_remove(struct omap_dss_device *dssdev) ++{ ++ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); ++ ++ kfree(ld); ++} ++ ++static int lb035q02_panel_enable(struct omap_dss_device *dssdev) ++{ ++ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); ++ int r; ++ ++ mutex_lock(&ld->lock); ++ ++ r = lb035q02_panel_power_on(dssdev); ++ if (r) ++ goto err; ++ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; ++ ++ mutex_unlock(&ld->lock); ++ return 0; ++err: ++ mutex_unlock(&ld->lock); ++ return r; ++} ++ ++static void lb035q02_panel_disable(struct omap_dss_device *dssdev) ++{ ++ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); ++ ++ mutex_lock(&ld->lock); ++ ++ lb035q02_panel_power_off(dssdev); ++ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; ++ ++ mutex_unlock(&ld->lock); ++} ++ ++static int lb035q02_panel_suspend(struct omap_dss_device *dssdev) ++{ ++ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); ++ ++ mutex_lock(&ld->lock); ++ ++ lb035q02_panel_power_off(dssdev); ++ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; ++ ++ mutex_unlock(&ld->lock); ++ return 0; ++} ++ ++static int lb035q02_panel_resume(struct omap_dss_device *dssdev) ++{ ++ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); ++ int r; ++ ++ mutex_lock(&ld->lock); ++ ++ r = lb035q02_panel_power_on(dssdev); ++ if (r) ++ goto err; ++ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; ++ ++ mutex_unlock(&ld->lock); ++ return 0; ++err: ++ mutex_unlock(&ld->lock); ++ return r; ++} ++ ++static struct omap_dss_driver lb035q02_driver = { ++ .probe = lb035q02_panel_probe, ++ .remove = lb035q02_panel_remove, ++ ++ .enable = lb035q02_panel_enable, ++ .disable = lb035q02_panel_disable, ++ .suspend = lb035q02_panel_suspend, ++ .resume = lb035q02_panel_resume, ++ ++ .driver = { ++ .name = "lgphilips_lb035q02_panel", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int lb035q02_write_reg(struct spi_device *spi, u8 reg, u16 val) ++{ ++ struct spi_message msg; ++ struct spi_transfer index_xfer = { ++ .len = 3, ++ .cs_change = 1, ++ }; ++ struct spi_transfer value_xfer = { ++ .len = 3, ++ }; ++ u8 buffer[16]; ++ ++ spi_message_init(&msg); ++ ++ /* register index */ ++ buffer[0] = 0x70; ++ buffer[1] = 0x00; ++ buffer[2] = reg & 0x7f; ++ index_xfer.tx_buf = buffer; ++ spi_message_add_tail(&index_xfer, &msg); ++ ++ /* register value */ ++ buffer[4] = 0x72; ++ buffer[5] = val >> 8; ++ buffer[6] = val; ++ value_xfer.tx_buf = buffer + 4; ++ spi_message_add_tail(&value_xfer, &msg); ++ ++ return spi_sync(spi, &msg); ++} ++ ++static void init_lb035q02_panel(struct spi_device *spi) ++{ ++ /* Init sequence from page 28 of the lb035q02 spec */ ++ lb035q02_write_reg(spi, 0x01, 0x6300); ++ lb035q02_write_reg(spi, 0x02, 0x0200); ++ lb035q02_write_reg(spi, 0x03, 0x0177); ++ lb035q02_write_reg(spi, 0x04, 0x04c7); ++ lb035q02_write_reg(spi, 0x05, 0xffc0); ++ lb035q02_write_reg(spi, 0x06, 0xe806); ++ lb035q02_write_reg(spi, 0x0a, 0x4008); ++ lb035q02_write_reg(spi, 0x0b, 0x0000); ++ lb035q02_write_reg(spi, 0x0d, 0x0030); ++ lb035q02_write_reg(spi, 0x0e, 0x2800); ++ lb035q02_write_reg(spi, 0x0f, 0x0000); ++ lb035q02_write_reg(spi, 0x16, 0x9f80); ++ lb035q02_write_reg(spi, 0x17, 0x0a0f); ++ lb035q02_write_reg(spi, 0x1e, 0x00c1); ++ lb035q02_write_reg(spi, 0x30, 0x0300); ++ lb035q02_write_reg(spi, 0x31, 0x0007); ++ lb035q02_write_reg(spi, 0x32, 0x0000); ++ lb035q02_write_reg(spi, 0x33, 0x0000); ++ lb035q02_write_reg(spi, 0x34, 0x0707); ++ lb035q02_write_reg(spi, 0x35, 0x0004); ++ lb035q02_write_reg(spi, 0x36, 0x0302); ++ lb035q02_write_reg(spi, 0x37, 0x0202); ++ lb035q02_write_reg(spi, 0x3a, 0x0a0d); ++ lb035q02_write_reg(spi, 0x3b, 0x0806); ++} ++ ++static int __devinit lb035q02_panel_spi_probe(struct spi_device *spi) ++{ ++ init_lb035q02_panel(spi); ++ return omap_dss_register_driver(&lb035q02_driver); ++} ++ ++static int __devexit lb035q02_panel_spi_remove(struct spi_device *spi) ++{ ++ omap_dss_unregister_driver(&lb035q02_driver); ++ return 0; ++} ++ ++static struct spi_driver lb035q02_spi_driver = { ++ .driver = { ++ .name = "lgphilips_lb035q02_panel-spi", ++ .owner = THIS_MODULE, ++ }, ++ .probe = lb035q02_panel_spi_probe, ++ .remove = __devexit_p(lb035q02_panel_spi_remove), ++}; ++ ++static int __init lb035q02_panel_drv_init(void) ++{ ++ return spi_register_driver(&lb035q02_spi_driver); ++} ++ ++static void __exit lb035q02_panel_drv_exit(void) ++{ ++ spi_unregister_driver(&lb035q02_spi_driver); ++} ++ ++module_init(lb035q02_panel_drv_init); ++module_exit(lb035q02_panel_drv_exit); ++MODULE_LICENSE("GPL"); +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/panel-taal.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-taal.c +--- linux-2.6.38-rc7/drivers/video/omap2/displays/panel-taal.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-taal.c 2011-03-09 13:19:21.081278983 +0100 +@@ -218,6 +218,8 @@ + u16 w; + u16 h; + } update_region; ++ int channel; ++ + struct delayed_work te_timeout_work; + + bool use_dsi_bl; +@@ -257,12 +259,12 @@ + } + } + +-static int taal_dcs_read_1(u8 dcs_cmd, u8 *data) ++static int taal_dcs_read_1(struct taal_data *td, u8 dcs_cmd, u8 *data) + { + int r; + u8 buf[1]; + +- r = dsi_vc_dcs_read(TCH, dcs_cmd, buf, 1); ++ r = dsi_vc_dcs_read(td->channel, dcs_cmd, buf, 1); + + if (r < 0) + return r; +@@ -272,17 +274,17 @@ + return 0; + } + +-static int taal_dcs_write_0(u8 dcs_cmd) ++static int taal_dcs_write_0(struct taal_data *td, u8 dcs_cmd) + { +- return dsi_vc_dcs_write(TCH, &dcs_cmd, 1); ++ return dsi_vc_dcs_write(td->channel, &dcs_cmd, 1); + } + +-static int taal_dcs_write_1(u8 dcs_cmd, u8 param) ++static int taal_dcs_write_1(struct taal_data *td, u8 dcs_cmd, u8 param) + { + u8 buf[2]; + buf[0] = dcs_cmd; + buf[1] = param; +- return dsi_vc_dcs_write(TCH, buf, 2); ++ return dsi_vc_dcs_write(td->channel, buf, 2); + } + + static int taal_sleep_in(struct taal_data *td) +@@ -294,7 +296,7 @@ + hw_guard_wait(td); + + cmd = DCS_SLEEP_IN; +- r = dsi_vc_dcs_write_nosync(TCH, &cmd, 1); ++ r = dsi_vc_dcs_write_nosync(td->channel, &cmd, 1); + if (r) + return r; + +@@ -312,7 +314,7 @@ + + hw_guard_wait(td); + +- r = taal_dcs_write_0(DCS_SLEEP_OUT); ++ r = taal_dcs_write_0(td, DCS_SLEEP_OUT); + if (r) + return r; + +@@ -324,30 +326,30 @@ + return 0; + } + +-static int taal_get_id(u8 *id1, u8 *id2, u8 *id3) ++static int taal_get_id(struct taal_data *td, u8 *id1, u8 *id2, u8 *id3) + { + int r; + +- r = taal_dcs_read_1(DCS_GET_ID1, id1); ++ r = taal_dcs_read_1(td, DCS_GET_ID1, id1); + if (r) + return r; +- r = taal_dcs_read_1(DCS_GET_ID2, id2); ++ r = taal_dcs_read_1(td, DCS_GET_ID2, id2); + if (r) + return r; +- r = taal_dcs_read_1(DCS_GET_ID3, id3); ++ r = taal_dcs_read_1(td, DCS_GET_ID3, id3); + if (r) + return r; + + return 0; + } + +-static int taal_set_addr_mode(u8 rotate, bool mirror) ++static int taal_set_addr_mode(struct taal_data *td, u8 rotate, bool mirror) + { + int r; + u8 mode; + int b5, b6, b7; + +- r = taal_dcs_read_1(DCS_READ_MADCTL, &mode); ++ r = taal_dcs_read_1(td, DCS_READ_MADCTL, &mode); + if (r) + return r; + +@@ -381,10 +383,11 @@ + mode &= ~((1<<7) | (1<<6) | (1<<5)); + mode |= (b7 << 7) | (b6 << 6) | (b5 << 5); + +- return taal_dcs_write_1(DCS_MEM_ACC_CTRL, mode); ++ return taal_dcs_write_1(td, DCS_MEM_ACC_CTRL, mode); + } + +-static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h) ++static int taal_set_update_window(struct taal_data *td, ++ u16 x, u16 y, u16 w, u16 h) + { + int r; + u16 x1 = x; +@@ -399,7 +402,7 @@ + buf[3] = (x2 >> 8) & 0xff; + buf[4] = (x2 >> 0) & 0xff; + +- r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); ++ r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf)); + if (r) + return r; + +@@ -409,11 +412,11 @@ + buf[3] = (y2 >> 8) & 0xff; + buf[4] = (y2 >> 0) & 0xff; + +- r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); ++ r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf)); + if (r) + return r; + +- dsi_vc_send_bta_sync(TCH); ++ dsi_vc_send_bta_sync(td->channel); + + return r; + } +@@ -439,7 +442,7 @@ + if (td->use_dsi_bl) { + if (td->enabled) { + dsi_bus_lock(); +- r = taal_dcs_write_1(DCS_BRIGHTNESS, level); ++ r = taal_dcs_write_1(td, DCS_BRIGHTNESS, level); + dsi_bus_unlock(); + } else { + r = 0; +@@ -502,7 +505,7 @@ + + if (td->enabled) { + dsi_bus_lock(); +- r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors); ++ r = taal_dcs_read_1(td, DCS_READ_NUM_ERRORS, &errors); + dsi_bus_unlock(); + } else { + r = -ENODEV; +@@ -528,7 +531,7 @@ + + if (td->enabled) { + dsi_bus_lock(); +- r = taal_get_id(&id1, &id2, &id3); ++ r = taal_get_id(td, &id1, &id2, &id3); + dsi_bus_unlock(); + } else { + r = -ENODEV; +@@ -590,7 +593,7 @@ + if (td->enabled) { + dsi_bus_lock(); + if (!td->cabc_broken) +- taal_dcs_write_1(DCS_WRITE_CABC, i); ++ taal_dcs_write_1(td, DCS_WRITE_CABC, i); + dsi_bus_unlock(); + } + +@@ -774,14 +777,29 @@ + dev_dbg(&dssdev->dev, "Using GPIO TE\n"); + } + ++ r = omap_dsi_request_vc(dssdev, &td->channel); ++ if (r) { ++ dev_err(&dssdev->dev, "failed to get virtual channel\n"); ++ goto err_req_vc; ++ } ++ ++ r = omap_dsi_set_vc_id(dssdev, td->channel, TCH); ++ if (r) { ++ dev_err(&dssdev->dev, "failed to set VC_ID\n"); ++ goto err_vc_id; ++ } ++ + r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group); + if (r) { + dev_err(&dssdev->dev, "failed to create sysfs files\n"); +- goto err_sysfs; ++ goto err_vc_id; + } + + return 0; +-err_sysfs: ++ ++err_vc_id: ++ omap_dsi_release_vc(dssdev, td->channel); ++err_req_vc: + if (panel_data->use_ext_te) + free_irq(gpio_to_irq(panel_data->ext_te_gpio), dssdev); + err_irq: +@@ -808,6 +826,7 @@ + dev_dbg(&dssdev->dev, "remove\n"); + + sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group); ++ omap_dsi_release_vc(dssdev, td->channel); + + if (panel_data->use_ext_te) { + int gpio = panel_data->ext_te_gpio; +@@ -846,13 +865,13 @@ + + taal_hw_reset(dssdev); + +- omapdss_dsi_vc_enable_hs(TCH, false); ++ omapdss_dsi_vc_enable_hs(td->channel, false); + + r = taal_sleep_out(td); + if (r) + goto err; + +- r = taal_get_id(&id1, &id2, &id3); ++ r = taal_get_id(td, &id1, &id2, &id3); + if (r) + goto err; + +@@ -861,30 +880,30 @@ + (id2 == 0x00 || id2 == 0xff || id2 == 0x81)) + td->cabc_broken = true; + +- r = taal_dcs_write_1(DCS_BRIGHTNESS, 0xff); ++ r = taal_dcs_write_1(td, DCS_BRIGHTNESS, 0xff); + if (r) + goto err; + +- r = taal_dcs_write_1(DCS_CTRL_DISPLAY, ++ r = taal_dcs_write_1(td, DCS_CTRL_DISPLAY, + (1<<2) | (1<<5)); /* BL | BCTRL */ + if (r) + goto err; + +- r = taal_dcs_write_1(DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */ ++ r = taal_dcs_write_1(td, DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */ + if (r) + goto err; + +- r = taal_set_addr_mode(td->rotate, td->mirror); ++ r = taal_set_addr_mode(td, td->rotate, td->mirror); + if (r) + goto err; + + if (!td->cabc_broken) { +- r = taal_dcs_write_1(DCS_WRITE_CABC, td->cabc_mode); ++ r = taal_dcs_write_1(td, DCS_WRITE_CABC, td->cabc_mode); + if (r) + goto err; + } + +- r = taal_dcs_write_0(DCS_DISPLAY_ON); ++ r = taal_dcs_write_0(td, DCS_DISPLAY_ON); + if (r) + goto err; + +@@ -903,7 +922,7 @@ + td->intro_printed = true; + } + +- omapdss_dsi_vc_enable_hs(TCH, true); ++ omapdss_dsi_vc_enable_hs(td->channel, true); + + return 0; + err: +@@ -921,7 +940,7 @@ + struct taal_data *td = dev_get_drvdata(&dssdev->dev); + int r; + +- r = taal_dcs_write_0(DCS_DISPLAY_OFF); ++ r = taal_dcs_write_0(td, DCS_DISPLAY_OFF); + if (!r) { + r = taal_sleep_in(td); + /* HACK: wait a bit so that the message goes through */ +@@ -1089,7 +1108,7 @@ + if (old) { + cancel_delayed_work(&td->te_timeout_work); + +- r = omap_dsi_update(dssdev, TCH, ++ r = omap_dsi_update(dssdev, td->channel, + td->update_region.x, + td->update_region.y, + td->update_region.w, +@@ -1139,7 +1158,7 @@ + if (r) + goto err; + +- r = taal_set_update_window(x, y, w, h); ++ r = taal_set_update_window(td, x, y, w, h); + if (r) + goto err; + +@@ -1153,7 +1172,7 @@ + msecs_to_jiffies(250)); + atomic_set(&td->do_update, 1); + } else { +- r = omap_dsi_update(dssdev, TCH, x, y, w, h, ++ r = omap_dsi_update(dssdev, td->channel, x, y, w, h, + taal_framedone_cb, dssdev); + if (r) + goto err; +@@ -1191,9 +1210,9 @@ + int r; + + if (enable) +- r = taal_dcs_write_1(DCS_TEAR_ON, 0); ++ r = taal_dcs_write_1(td, DCS_TEAR_ON, 0); + else +- r = taal_dcs_write_0(DCS_TEAR_OFF); ++ r = taal_dcs_write_0(td, DCS_TEAR_OFF); + + if (!panel_data->use_ext_te) + omapdss_dsi_enable_te(dssdev, enable); +@@ -1263,7 +1282,7 @@ + dsi_bus_lock(); + + if (td->enabled) { +- r = taal_set_addr_mode(rotate, td->mirror); ++ r = taal_set_addr_mode(td, rotate, td->mirror); + if (r) + goto err; + } +@@ -1306,7 +1325,7 @@ + + dsi_bus_lock(); + if (td->enabled) { +- r = taal_set_addr_mode(td->rotate, enable); ++ r = taal_set_addr_mode(td, td->rotate, enable); + if (r) + goto err; + } +@@ -1350,13 +1369,13 @@ + + dsi_bus_lock(); + +- r = taal_dcs_read_1(DCS_GET_ID1, &id1); ++ r = taal_dcs_read_1(td, DCS_GET_ID1, &id1); + if (r) + goto err2; +- r = taal_dcs_read_1(DCS_GET_ID2, &id2); ++ r = taal_dcs_read_1(td, DCS_GET_ID2, &id2); + if (r) + goto err2; +- r = taal_dcs_read_1(DCS_GET_ID3, &id3); ++ r = taal_dcs_read_1(td, DCS_GET_ID3, &id3); + if (r) + goto err2; + +@@ -1404,9 +1423,9 @@ + else + plen = 2; + +- taal_set_update_window(x, y, w, h); ++ taal_set_update_window(td, x, y, w, h); + +- r = dsi_vc_set_max_rx_packet_size(TCH, plen); ++ r = dsi_vc_set_max_rx_packet_size(td->channel, plen); + if (r) + goto err2; + +@@ -1414,7 +1433,7 @@ + u8 dcs_cmd = first ? 0x2e : 0x3e; + first = 0; + +- r = dsi_vc_dcs_read(TCH, dcs_cmd, ++ r = dsi_vc_dcs_read(td->channel, dcs_cmd, + buf + buf_used, size - buf_used); + + if (r < 0) { +@@ -1440,7 +1459,7 @@ + r = buf_used; + + err3: +- dsi_vc_set_max_rx_packet_size(TCH, 1); ++ dsi_vc_set_max_rx_packet_size(td->channel, 1); + err2: + dsi_bus_unlock(); + err1: +@@ -1466,7 +1485,7 @@ + + dsi_bus_lock(); + +- r = taal_dcs_read_1(DCS_RDDSDR, &state1); ++ r = taal_dcs_read_1(td, DCS_RDDSDR, &state1); + if (r) { + dev_err(&dssdev->dev, "failed to read Taal status\n"); + goto err; +@@ -1479,7 +1498,7 @@ + goto err; + } + +- r = taal_dcs_read_1(DCS_RDDSDR, &state2); ++ r = taal_dcs_read_1(td, DCS_RDDSDR, &state2); + if (r) { + dev_err(&dssdev->dev, "failed to read Taal status\n"); + goto err; +@@ -1495,7 +1514,7 @@ + /* Self-diagnostics result is also shown on TE GPIO line. We need + * to re-enable TE after self diagnostics */ + if (td->te_enabled && panel_data->use_ext_te) { +- r = taal_dcs_write_1(DCS_TEAR_ON, 0); ++ r = taal_dcs_write_1(td, DCS_TEAR_ON, 0); + if (r) + goto err; + } +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/core.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/core.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/core.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/core.c 2011-03-09 13:19:21.083278942 +0100 +@@ -34,332 +34,26 @@ + #include + + #include +-#include + + #include "dss.h" + #include "dss_features.h" + + static struct { + struct platform_device *pdev; +- int ctx_id; +- +- struct clk *dss_ick; +- struct clk *dss1_fck; +- struct clk *dss2_fck; +- struct clk *dss_54m_fck; +- struct clk *dss_96m_fck; +- unsigned num_clks_enabled; + + struct regulator *vdds_dsi_reg; + struct regulator *vdds_sdi_reg; +- struct regulator *vdda_dac_reg; + } core; + +-static void dss_clk_enable_all_no_ctx(void); +-static void dss_clk_disable_all_no_ctx(void); +-static void dss_clk_enable_no_ctx(enum dss_clock clks); +-static void dss_clk_disable_no_ctx(enum dss_clock clks); +- + static char *def_disp_name; + module_param_named(def_disp, def_disp_name, charp, 0); +-MODULE_PARM_DESC(def_disp_name, "default display name"); ++MODULE_PARM_DESC(def_disp, "default display name"); + + #ifdef DEBUG + unsigned int dss_debug; + module_param_named(debug, dss_debug, bool, 0644); + #endif + +-/* CONTEXT */ +-static int dss_get_ctx_id(void) +-{ +- struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; +- int r; +- +- if (!pdata->get_last_off_on_transaction_id) +- return 0; +- r = pdata->get_last_off_on_transaction_id(&core.pdev->dev); +- if (r < 0) { +- dev_err(&core.pdev->dev, "getting transaction ID failed, " +- "will force context restore\n"); +- r = -1; +- } +- return r; +-} +- +-int dss_need_ctx_restore(void) +-{ +- int id = dss_get_ctx_id(); +- +- if (id < 0 || id != core.ctx_id) { +- DSSDBG("ctx id %d -> id %d\n", +- core.ctx_id, id); +- core.ctx_id = id; +- return 1; +- } else { +- return 0; +- } +-} +- +-static void save_all_ctx(void) +-{ +- DSSDBG("save context\n"); +- +- dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); +- +- dss_save_context(); +- dispc_save_context(); +-#ifdef CONFIG_OMAP2_DSS_DSI +- dsi_save_context(); +-#endif +- +- dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); +-} +- +-static void restore_all_ctx(void) +-{ +- DSSDBG("restore context\n"); +- +- dss_clk_enable_all_no_ctx(); +- +- dss_restore_context(); +- dispc_restore_context(); +-#ifdef CONFIG_OMAP2_DSS_DSI +- dsi_restore_context(); +-#endif +- +- dss_clk_disable_all_no_ctx(); +-} +- +-#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) +-/* CLOCKS */ +-static void core_dump_clocks(struct seq_file *s) +-{ +- int i; +- struct clk *clocks[5] = { +- core.dss_ick, +- core.dss1_fck, +- core.dss2_fck, +- core.dss_54m_fck, +- core.dss_96m_fck +- }; +- +- seq_printf(s, "- CORE -\n"); +- +- seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled); +- +- for (i = 0; i < 5; i++) { +- if (!clocks[i]) +- continue; +- seq_printf(s, "%-15s\t%lu\t%d\n", +- clocks[i]->name, +- clk_get_rate(clocks[i]), +- clocks[i]->usecount); +- } +-} +-#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ +- +-static int dss_get_clock(struct clk **clock, const char *clk_name) +-{ +- struct clk *clk; +- +- clk = clk_get(&core.pdev->dev, clk_name); +- +- if (IS_ERR(clk)) { +- DSSERR("can't get clock %s", clk_name); +- return PTR_ERR(clk); +- } +- +- *clock = clk; +- +- DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); +- +- return 0; +-} +- +-static int dss_get_clocks(void) +-{ +- int r; +- +- core.dss_ick = NULL; +- core.dss1_fck = NULL; +- core.dss2_fck = NULL; +- core.dss_54m_fck = NULL; +- core.dss_96m_fck = NULL; +- +- r = dss_get_clock(&core.dss_ick, "ick"); +- if (r) +- goto err; +- +- r = dss_get_clock(&core.dss1_fck, "dss1_fck"); +- if (r) +- goto err; +- +- r = dss_get_clock(&core.dss2_fck, "dss2_fck"); +- if (r) +- goto err; +- +- r = dss_get_clock(&core.dss_54m_fck, "tv_fck"); +- if (r) +- goto err; +- +- r = dss_get_clock(&core.dss_96m_fck, "video_fck"); +- if (r) +- goto err; +- +- return 0; +- +-err: +- if (core.dss_ick) +- clk_put(core.dss_ick); +- if (core.dss1_fck) +- clk_put(core.dss1_fck); +- if (core.dss2_fck) +- clk_put(core.dss2_fck); +- if (core.dss_54m_fck) +- clk_put(core.dss_54m_fck); +- if (core.dss_96m_fck) +- clk_put(core.dss_96m_fck); +- +- return r; +-} +- +-static void dss_put_clocks(void) +-{ +- if (core.dss_96m_fck) +- clk_put(core.dss_96m_fck); +- clk_put(core.dss_54m_fck); +- clk_put(core.dss1_fck); +- clk_put(core.dss2_fck); +- clk_put(core.dss_ick); +-} +- +-unsigned long dss_clk_get_rate(enum dss_clock clk) +-{ +- switch (clk) { +- case DSS_CLK_ICK: +- return clk_get_rate(core.dss_ick); +- case DSS_CLK_FCK1: +- return clk_get_rate(core.dss1_fck); +- case DSS_CLK_FCK2: +- return clk_get_rate(core.dss2_fck); +- case DSS_CLK_54M: +- return clk_get_rate(core.dss_54m_fck); +- case DSS_CLK_96M: +- return clk_get_rate(core.dss_96m_fck); +- } +- +- BUG(); +- return 0; +-} +- +-static unsigned count_clk_bits(enum dss_clock clks) +-{ +- unsigned num_clks = 0; +- +- if (clks & DSS_CLK_ICK) +- ++num_clks; +- if (clks & DSS_CLK_FCK1) +- ++num_clks; +- if (clks & DSS_CLK_FCK2) +- ++num_clks; +- if (clks & DSS_CLK_54M) +- ++num_clks; +- if (clks & DSS_CLK_96M) +- ++num_clks; +- +- return num_clks; +-} +- +-static void dss_clk_enable_no_ctx(enum dss_clock clks) +-{ +- unsigned num_clks = count_clk_bits(clks); +- +- if (clks & DSS_CLK_ICK) +- clk_enable(core.dss_ick); +- if (clks & DSS_CLK_FCK1) +- clk_enable(core.dss1_fck); +- if (clks & DSS_CLK_FCK2) +- clk_enable(core.dss2_fck); +- if (clks & DSS_CLK_54M) +- clk_enable(core.dss_54m_fck); +- if (clks & DSS_CLK_96M) +- clk_enable(core.dss_96m_fck); +- +- core.num_clks_enabled += num_clks; +-} +- +-void dss_clk_enable(enum dss_clock clks) +-{ +- bool check_ctx = core.num_clks_enabled == 0; +- +- dss_clk_enable_no_ctx(clks); +- +- if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) +- restore_all_ctx(); +-} +- +-static void dss_clk_disable_no_ctx(enum dss_clock clks) +-{ +- unsigned num_clks = count_clk_bits(clks); +- +- if (clks & DSS_CLK_ICK) +- clk_disable(core.dss_ick); +- if (clks & DSS_CLK_FCK1) +- clk_disable(core.dss1_fck); +- if (clks & DSS_CLK_FCK2) +- clk_disable(core.dss2_fck); +- if (clks & DSS_CLK_54M) +- clk_disable(core.dss_54m_fck); +- if (clks & DSS_CLK_96M) +- clk_disable(core.dss_96m_fck); +- +- core.num_clks_enabled -= num_clks; +-} +- +-void dss_clk_disable(enum dss_clock clks) +-{ +- if (cpu_is_omap34xx()) { +- unsigned num_clks = count_clk_bits(clks); +- +- BUG_ON(core.num_clks_enabled < num_clks); +- +- if (core.num_clks_enabled == num_clks) +- save_all_ctx(); +- } +- +- dss_clk_disable_no_ctx(clks); +-} +- +-static void dss_clk_enable_all_no_ctx(void) +-{ +- enum dss_clock clks; +- +- clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; +- if (cpu_is_omap34xx()) +- clks |= DSS_CLK_96M; +- dss_clk_enable_no_ctx(clks); +-} +- +-static void dss_clk_disable_all_no_ctx(void) +-{ +- enum dss_clock clks; +- +- clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; +- if (cpu_is_omap34xx()) +- clks |= DSS_CLK_96M; +- dss_clk_disable_no_ctx(clks); +-} +- +-static void dss_clk_disable_all(void) +-{ +- enum dss_clock clks; +- +- clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; +- if (cpu_is_omap34xx()) +- clks |= DSS_CLK_96M; +- dss_clk_disable(clks); +-} +- + /* REGULATORS */ + + struct regulator *dss_get_vdds_dsi(void) +@@ -390,32 +84,7 @@ + return reg; + } + +-struct regulator *dss_get_vdda_dac(void) +-{ +- struct regulator *reg; +- +- if (core.vdda_dac_reg != NULL) +- return core.vdda_dac_reg; +- +- reg = regulator_get(&core.pdev->dev, "vdda_dac"); +- if (!IS_ERR(reg)) +- core.vdda_dac_reg = reg; +- +- return reg; +-} +- +-/* DEBUGFS */ + #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) +-static void dss_debug_dump_clocks(struct seq_file *s) +-{ +- core_dump_clocks(s); +- dss_dump_clocks(s); +- dispc_dump_clocks(s); +-#ifdef CONFIG_OMAP2_DSS_DSI +- dsi_dump_clocks(s); +-#endif +-} +- + static int dss_debug_show(struct seq_file *s, void *unused) + { + void (*func)(struct seq_file *) = s->private; +@@ -497,7 +166,6 @@ + static int omap_dss_probe(struct platform_device *pdev) + { + struct omap_dss_board_info *pdata = pdev->dev.platform_data; +- int skip_init = 0; + int r; + int i; + +@@ -508,63 +176,37 @@ + dss_init_overlay_managers(pdev); + dss_init_overlays(pdev); + +- r = dss_get_clocks(); +- if (r) +- goto err_clocks; +- +- dss_clk_enable_all_no_ctx(); +- +- core.ctx_id = dss_get_ctx_id(); +- DSSDBG("initial ctx id %u\n", core.ctx_id); +- +-#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT +- /* DISPC_CONTROL */ +- if (omap_readl(0x48050440) & 1) /* LCD enabled? */ +- skip_init = 1; +-#endif +- +- r = dss_init(skip_init); ++ r = dss_init_platform_driver(); + if (r) { +- DSSERR("Failed to initialize DSS\n"); ++ DSSERR("Failed to initialize DSS platform driver\n"); + goto err_dss; + } + +- r = rfbi_init(); +- if (r) { +- DSSERR("Failed to initialize rfbi\n"); +- goto err_rfbi; +- } ++ /* keep clocks enabled to prevent context saves/restores during init */ ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + +- r = dpi_init(pdev); ++ r = rfbi_init_platform_driver(); + if (r) { +- DSSERR("Failed to initialize dpi\n"); +- goto err_dpi; ++ DSSERR("Failed to initialize rfbi platform driver\n"); ++ goto err_rfbi; + } + +- r = dispc_init(); ++ r = dispc_init_platform_driver(); + if (r) { +- DSSERR("Failed to initialize dispc\n"); ++ DSSERR("Failed to initialize dispc platform driver\n"); + goto err_dispc; + } + +- r = venc_init(pdev); ++ r = venc_init_platform_driver(); + if (r) { +- DSSERR("Failed to initialize venc\n"); ++ DSSERR("Failed to initialize venc platform driver\n"); + goto err_venc; + } + +- if (cpu_is_omap34xx()) { +- r = sdi_init(skip_init); +- if (r) { +- DSSERR("Failed to initialize SDI\n"); +- goto err_sdi; +- } +- +- r = dsi_init(pdev); +- if (r) { +- DSSERR("Failed to initialize DSI\n"); +- goto err_dsi; +- } ++ r = dsi_init_platform_driver(); ++ if (r) { ++ DSSERR("Failed to initialize DSI platform driver\n"); ++ goto err_dsi; + } + + r = dss_initialize_debugfs(); +@@ -589,32 +231,23 @@ + pdata->default_device = dssdev; + } + +- dss_clk_disable_all(); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + + return 0; + + err_register: + dss_uninitialize_debugfs(); + err_debugfs: +- if (cpu_is_omap34xx()) +- dsi_exit(); ++ dsi_uninit_platform_driver(); + err_dsi: +- if (cpu_is_omap34xx()) +- sdi_exit(); +-err_sdi: +- venc_exit(); ++ venc_uninit_platform_driver(); + err_venc: +- dispc_exit(); ++ dispc_uninit_platform_driver(); + err_dispc: +- dpi_exit(); +-err_dpi: +- rfbi_exit(); ++ rfbi_uninit_platform_driver(); + err_rfbi: +- dss_exit(); ++ dss_uninit_platform_driver(); + err_dss: +- dss_clk_disable_all_no_ctx(); +- dss_put_clocks(); +-err_clocks: + + return r; + } +@@ -623,61 +256,14 @@ + { + struct omap_dss_board_info *pdata = pdev->dev.platform_data; + int i; +- int c; + + dss_uninitialize_debugfs(); + +- venc_exit(); +- dispc_exit(); +- dpi_exit(); +- rfbi_exit(); +- if (cpu_is_omap34xx()) { +- dsi_exit(); +- sdi_exit(); +- } +- +- dss_exit(); +- +- /* these should be removed at some point */ +- c = core.dss_ick->usecount; +- if (c > 0) { +- DSSERR("warning: dss_ick usecount %d, disabling\n", c); +- while (c-- > 0) +- clk_disable(core.dss_ick); +- } +- +- c = core.dss1_fck->usecount; +- if (c > 0) { +- DSSERR("warning: dss1_fck usecount %d, disabling\n", c); +- while (c-- > 0) +- clk_disable(core.dss1_fck); +- } +- +- c = core.dss2_fck->usecount; +- if (c > 0) { +- DSSERR("warning: dss2_fck usecount %d, disabling\n", c); +- while (c-- > 0) +- clk_disable(core.dss2_fck); +- } +- +- c = core.dss_54m_fck->usecount; +- if (c > 0) { +- DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c); +- while (c-- > 0) +- clk_disable(core.dss_54m_fck); +- } +- +- if (core.dss_96m_fck) { +- c = core.dss_96m_fck->usecount; +- if (c > 0) { +- DSSERR("warning: dss_96m_fck usecount %d, disabling\n", +- c); +- while (c-- > 0) +- clk_disable(core.dss_96m_fck); +- } +- } +- +- dss_put_clocks(); ++ venc_uninit_platform_driver(); ++ dispc_uninit_platform_driver(); ++ rfbi_uninit_platform_driver(); ++ dsi_uninit_platform_driver(); ++ dss_uninit_platform_driver(); + + dss_uninit_overlays(pdev); + dss_uninit_overlay_managers(pdev); +@@ -965,11 +551,6 @@ + core.vdds_sdi_reg = NULL; + } + +- if (core.vdda_dac_reg != NULL) { +- regulator_put(core.vdda_dac_reg); +- core.vdda_dac_reg = NULL; +- } +- + platform_driver_unregister(&omap_dss_driver); + + omap_dss_bus_unregister(); +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dispc.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dispc.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/dispc.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dispc.c 2011-03-09 13:19:21.083278942 +0100 +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -42,8 +43,6 @@ + #include "dss_features.h" + + /* DISPC */ +-#define DISPC_BASE 0x48050400 +- + #define DISPC_SZ_REGS SZ_4K + + struct dispc_reg { u16 idx; }; +@@ -74,7 +73,7 @@ + #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400) + #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404) + #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408) +-#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C) ++#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C) + #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074) + #define DISPC_SIZE_DIG DISPC_REG(0x0078) + #define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC) +@@ -129,6 +128,7 @@ + + #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) + ++#define DISPC_DIVISOR DISPC_REG(0x0804) + + #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ + DISPC_IRQ_OCP_ERR | \ +@@ -178,7 +178,9 @@ + }; + + static struct { ++ struct platform_device *pdev; + void __iomem *base; ++ int irq; + + u32 fifo_size[3]; + +@@ -230,7 +232,7 @@ + SR(TIMING_H(0)); + SR(TIMING_V(0)); + SR(POL_FREQ(0)); +- SR(DIVISOR(0)); ++ SR(DIVISORo(0)); + SR(GLOBAL_ALPHA); + SR(SIZE_DIG); + SR(SIZE_LCD(0)); +@@ -242,7 +244,7 @@ + SR(TIMING_H(2)); + SR(TIMING_V(2)); + SR(POL_FREQ(2)); +- SR(DIVISOR(2)); ++ SR(DIVISORo(2)); + SR(CONFIG2); + } + +@@ -373,6 +375,9 @@ + SR(VID_FIR_COEF_V(1, 7)); + + SR(VID_PRELOAD(1)); ++ ++ if (dss_has_feature(FEAT_CORE_CLK_DIV)) ++ SR(DIVISOR); + } + + void dispc_restore_context(void) +@@ -389,7 +394,7 @@ + RR(TIMING_H(0)); + RR(TIMING_V(0)); + RR(POL_FREQ(0)); +- RR(DIVISOR(0)); ++ RR(DIVISORo(0)); + RR(GLOBAL_ALPHA); + RR(SIZE_DIG); + RR(SIZE_LCD(0)); +@@ -400,7 +405,7 @@ + RR(TIMING_H(2)); + RR(TIMING_V(2)); + RR(POL_FREQ(2)); +- RR(DIVISOR(2)); ++ RR(DIVISORo(2)); + RR(CONFIG2); + } + +@@ -532,6 +537,9 @@ + + RR(VID_PRELOAD(1)); + ++ if (dss_has_feature(FEAT_CORE_CLK_DIV)) ++ RR(DIVISOR); ++ + /* enable last, because LCD & DIGIT enable are here */ + RR(CONTROL); + if (dss_has_feature(FEAT_MGR_LCD2)) +@@ -552,9 +560,9 @@ + static inline void enable_clocks(bool enable) + { + if (enable) +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + else +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + } + + bool dispc_go_busy(enum omap_channel channel) +@@ -1129,10 +1137,16 @@ + u32 val; + const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), + DISPC_VID_ACCU0(1) }; ++ u8 hor_start, hor_end, vert_start, vert_end; + + BUG_ON(plane == OMAP_DSS_GFX); + +- val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); ++ dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); ++ dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); ++ ++ val = FLD_VAL(vaccu, vert_start, vert_end) | ++ FLD_VAL(haccu, hor_start, hor_end); ++ + dispc_write_reg(ac0_reg[plane-1], val); + } + +@@ -1141,10 +1155,16 @@ + u32 val; + const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), + DISPC_VID_ACCU1(1) }; ++ u8 hor_start, hor_end, vert_start, vert_end; + + BUG_ON(plane == OMAP_DSS_GFX); + +- val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); ++ dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); ++ dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); ++ ++ val = FLD_VAL(vaccu, vert_start, vert_end) | ++ FLD_VAL(haccu, hor_start, hor_end); ++ + dispc_write_reg(ac1_reg[plane-1], val); + } + +@@ -1182,16 +1202,25 @@ + _dispc_set_fir(plane, fir_hinc, fir_vinc); + + l = dispc_read_reg(dispc_reg_att[plane]); +- l &= ~((0x0f << 5) | (0x3 << 21)); + ++ /* RESIZEENABLE and VERTICALTAPS */ ++ l &= ~((0x3 << 5) | (0x1 << 21)); + l |= fir_hinc ? (1 << 5) : 0; + l |= fir_vinc ? (1 << 6) : 0; ++ l |= five_taps ? (1 << 21) : 0; + +- l |= hscaleup ? 0 : (1 << 7); +- l |= vscaleup ? 0 : (1 << 8); ++ /* VRESIZECONF and HRESIZECONF */ ++ if (dss_has_feature(FEAT_RESIZECONF)) { ++ l &= ~(0x3 << 7); ++ l |= hscaleup ? 0 : (1 << 7); ++ l |= vscaleup ? 0 : (1 << 8); ++ } + +- l |= five_taps ? (1 << 21) : 0; +- l |= five_taps ? (1 << 22) : 0; ++ /* LINEBUFFERSPLIT */ ++ if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { ++ l &= ~(0x1 << 22); ++ l |= five_taps ? (1 << 22) : 0; ++ } + + dispc_write_reg(dispc_reg_att[plane], l); + +@@ -1215,9 +1244,11 @@ + static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation, + bool mirroring, enum omap_color_mode color_mode) + { ++ bool row_repeat = false; ++ int vidrot = 0; ++ + if (color_mode == OMAP_DSS_COLOR_YUV2 || + color_mode == OMAP_DSS_COLOR_UYVY) { +- int vidrot = 0; + + if (mirroring) { + switch (rotation) { +@@ -1251,16 +1282,15 @@ + } + } + +- REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); +- + if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) +- REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18); ++ row_repeat = true; + else +- REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18); +- } else { +- REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12); +- REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18); ++ row_repeat = false; + } ++ ++ REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); ++ if (dss_has_feature(FEAT_ROWREPEATENABLE)) ++ REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18); + } + + static int color_mode_to_bpp(enum omap_color_mode color_mode) +@@ -2293,7 +2323,7 @@ + BUG_ON(pck_div < 2); + + enable_clocks(1); +- dispc_write_reg(DISPC_DIVISOR(channel), ++ dispc_write_reg(DISPC_DIVISORo(channel), + FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); + enable_clocks(0); + } +@@ -2302,7 +2332,7 @@ + int *pck_div) + { + u32 l; +- l = dispc_read_reg(DISPC_DIVISOR(channel)); ++ l = dispc_read_reg(DISPC_DIVISORo(channel)); + *lck_div = FLD_GET(l, 23, 16); + *pck_div = FLD_GET(l, 7, 0); + } +@@ -2311,14 +2341,17 @@ + { + unsigned long r = 0; + +- if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) +- r = dss_clk_get_rate(DSS_CLK_FCK1); +- else +-#ifdef CONFIG_OMAP2_DSS_DSI +- r = dsi_get_dsi1_pll_rate(); +-#else +- BUG(); +-#endif ++ switch (dss_get_dispc_clk_source()) { ++ case DSS_CLK_SRC_FCK: ++ r = dss_clk_get_rate(DSS_CLK_FCK); ++ break; ++ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: ++ r = dsi_get_pll_hsdiv_dispc_rate(); ++ break; ++ default: ++ BUG(); ++ } ++ + return r; + } + +@@ -2328,47 +2361,72 @@ + unsigned long r; + u32 l; + +- l = dispc_read_reg(DISPC_DIVISOR(channel)); ++ l = dispc_read_reg(DISPC_DIVISORo(channel)); + + lcd = FLD_GET(l, 23, 16); + +- r = dispc_fclk_rate(); ++ switch (dss_get_lcd_clk_source(channel)) { ++ case DSS_CLK_SRC_FCK: ++ r = dss_clk_get_rate(DSS_CLK_FCK); ++ break; ++ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: ++ r = dsi_get_pll_hsdiv_dispc_rate(); ++ break; ++ default: ++ BUG(); ++ } + + return r / lcd; + } + + unsigned long dispc_pclk_rate(enum omap_channel channel) + { +- int lcd, pcd; ++ int pcd; + unsigned long r; + u32 l; + +- l = dispc_read_reg(DISPC_DIVISOR(channel)); ++ l = dispc_read_reg(DISPC_DIVISORo(channel)); + +- lcd = FLD_GET(l, 23, 16); + pcd = FLD_GET(l, 7, 0); + +- r = dispc_fclk_rate(); ++ r = dispc_lclk_rate(channel); + +- return r / lcd / pcd; ++ return r / pcd; + } + + void dispc_dump_clocks(struct seq_file *s) + { + int lcd, pcd; ++ u32 l; ++ enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); ++ enum dss_clk_source lcd_clk_src; + + enable_clocks(1); + + seq_printf(s, "- DISPC -\n"); + +- seq_printf(s, "dispc fclk source = %s\n", +- dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? +- "dss1_alwon_fclk" : "dsi1_pll_fclk"); ++ seq_printf(s, "dispc fclk source = %s (%s)\n", ++ dss_get_generic_clk_source_name(dispc_clk_src), ++ dss_feat_get_clk_source_name(dispc_clk_src)); + + seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); + ++ if (dss_has_feature(FEAT_CORE_CLK_DIV)) { ++ seq_printf(s, "- DISPC-CORE-CLK -\n"); ++ l = dispc_read_reg(DISPC_DIVISOR); ++ lcd = FLD_GET(l, 23, 16); ++ ++ seq_printf(s, "lck\t\t%-16lulck div\t%u\n", ++ (dispc_fclk_rate()/lcd), lcd); ++ } + seq_printf(s, "- LCD1 -\n"); + ++ lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD); ++ ++ seq_printf(s, "lcd1_clk source = %s (%s)\n", ++ dss_get_generic_clk_source_name(lcd_clk_src), ++ dss_feat_get_clk_source_name(lcd_clk_src)); ++ + dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd); + + seq_printf(s, "lck\t\t%-16lulck div\t%u\n", +@@ -2378,6 +2436,12 @@ + if (dss_has_feature(FEAT_MGR_LCD2)) { + seq_printf(s, "- LCD2 -\n"); + ++ lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2); ++ ++ seq_printf(s, "lcd2_clk source = %s (%s)\n", ++ dss_get_generic_clk_source_name(lcd_clk_src), ++ dss_feat_get_clk_source_name(lcd_clk_src)); ++ + dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd); + + seq_printf(s, "lck\t\t%-16lulck div\t%u\n", +@@ -2440,7 +2504,7 @@ + { + #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r)) + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + DUMPREG(DISPC_REVISION); + DUMPREG(DISPC_SYSCONFIG); +@@ -2459,7 +2523,7 @@ + DUMPREG(DISPC_TIMING_H(0)); + DUMPREG(DISPC_TIMING_V(0)); + DUMPREG(DISPC_POL_FREQ(0)); +- DUMPREG(DISPC_DIVISOR(0)); ++ DUMPREG(DISPC_DIVISORo(0)); + DUMPREG(DISPC_GLOBAL_ALPHA); + DUMPREG(DISPC_SIZE_DIG); + DUMPREG(DISPC_SIZE_LCD(0)); +@@ -2471,7 +2535,7 @@ + DUMPREG(DISPC_TIMING_H(2)); + DUMPREG(DISPC_TIMING_V(2)); + DUMPREG(DISPC_POL_FREQ(2)); +- DUMPREG(DISPC_DIVISOR(2)); ++ DUMPREG(DISPC_DIVISORo(2)); + DUMPREG(DISPC_SIZE_LCD(2)); + } + +@@ -2597,7 +2661,7 @@ + DUMPREG(DISPC_VID_PRELOAD(0)); + DUMPREG(DISPC_VID_PRELOAD(1)); + +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + #undef DUMPREG + } + +@@ -2713,8 +2777,8 @@ + + fck = dispc_fclk_rate(); + +- cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16); +- cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0); ++ cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); ++ cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); + + cinfo->lck = fck / cinfo->lck_div; + cinfo->pck = cinfo->lck / cinfo->pck_div; +@@ -2791,6 +2855,9 @@ + break; + } + ++ if (ret) ++ goto err; ++ + _omap_dispc_set_irqs(); + + spin_unlock_irqrestore(&dispc.irq_lock, flags); +@@ -2866,10 +2933,10 @@ + * but we presume they are on because we got an IRQ. However, + * an irq handler may turn the clocks off, so we may not have + * clock later in the function. */ +-void dispc_irq_handler(void) ++static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) + { + int i; +- u32 irqstatus; ++ u32 irqstatus, irqenable; + u32 handledirqs = 0; + u32 unhandled_errors; + struct omap_dispc_isr_data *isr_data; +@@ -2878,6 +2945,13 @@ + spin_lock(&dispc.irq_lock); + + irqstatus = dispc_read_reg(DISPC_IRQSTATUS); ++ irqenable = dispc_read_reg(DISPC_IRQENABLE); ++ ++ /* IRQ is not for us */ ++ if (!(irqstatus & irqenable)) { ++ spin_unlock(&dispc.irq_lock); ++ return IRQ_NONE; ++ } + + #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS + spin_lock(&dispc.irq_stats_lock); +@@ -2929,6 +3003,8 @@ + } + + spin_unlock(&dispc.irq_lock); ++ ++ return IRQ_HANDLED; + } + + static void dispc_error_worker(struct work_struct *work) +@@ -3253,6 +3329,15 @@ + l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */ + dispc_write_reg(DISPC_SYSCONFIG, l); + ++ /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ ++ if (dss_has_feature(FEAT_CORE_CLK_DIV)) { ++ l = dispc_read_reg(DISPC_DIVISOR); ++ /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ ++ l = FLD_MOD(l, 1, 0, 0); ++ l = FLD_MOD(l, 1, 23, 16); ++ dispc_write_reg(DISPC_DIVISOR, l); ++ } ++ + /* FUNCGATED */ + if (dss_has_feature(FEAT_FUNCGATED)) + REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); +@@ -3269,47 +3354,6 @@ + dispc_read_plane_fifo_sizes(); + } + +-int dispc_init(void) +-{ +- u32 rev; +- +- spin_lock_init(&dispc.irq_lock); +- +-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS +- spin_lock_init(&dispc.irq_stats_lock); +- dispc.irq_stats.last_reset = jiffies; +-#endif +- +- INIT_WORK(&dispc.error_work, dispc_error_worker); +- +- dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS); +- if (!dispc.base) { +- DSSERR("can't ioremap DISPC\n"); +- return -ENOMEM; +- } +- +- enable_clocks(1); +- +- _omap_dispc_initial_config(); +- +- _omap_dispc_initialize_irq(); +- +- dispc_save_context(); +- +- rev = dispc_read_reg(DISPC_REVISION); +- printk(KERN_INFO "OMAP DISPC rev %d.%d\n", +- FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); +- +- enable_clocks(0); +- +- return 0; +-} +- +-void dispc_exit(void) +-{ +- iounmap(dispc.base); +-} +- + int dispc_enable_plane(enum omap_plane plane, bool enable) + { + DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); +@@ -3359,3 +3403,94 @@ + + return r; + } ++ ++/* DISPC HW IP initialisation */ ++static int omap_dispchw_probe(struct platform_device *pdev) ++{ ++ u32 rev; ++ int r = 0; ++ struct resource *dispc_mem; ++ ++ dispc.pdev = pdev; ++ ++ spin_lock_init(&dispc.irq_lock); ++ ++#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS ++ spin_lock_init(&dispc.irq_stats_lock); ++ dispc.irq_stats.last_reset = jiffies; ++#endif ++ ++ INIT_WORK(&dispc.error_work, dispc_error_worker); ++ ++ dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); ++ if (!dispc_mem) { ++ DSSERR("can't get IORESOURCE_MEM DISPC\n"); ++ r = -EINVAL; ++ goto fail0; ++ } ++ dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem)); ++ if (!dispc.base) { ++ DSSERR("can't ioremap DISPC\n"); ++ r = -ENOMEM; ++ goto fail0; ++ } ++ dispc.irq = platform_get_irq(dispc.pdev, 0); ++ if (dispc.irq < 0) { ++ DSSERR("platform_get_irq failed\n"); ++ r = -ENODEV; ++ goto fail1; ++ } ++ ++ r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED, ++ "OMAP DISPC", dispc.pdev); ++ if (r < 0) { ++ DSSERR("request_irq failed\n"); ++ goto fail1; ++ } ++ ++ enable_clocks(1); ++ ++ _omap_dispc_initial_config(); ++ ++ _omap_dispc_initialize_irq(); ++ ++ dispc_save_context(); ++ ++ rev = dispc_read_reg(DISPC_REVISION); ++ dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", ++ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); ++ ++ enable_clocks(0); ++ ++ return 0; ++fail1: ++ iounmap(dispc.base); ++fail0: ++ return r; ++} ++ ++static int omap_dispchw_remove(struct platform_device *pdev) ++{ ++ free_irq(dispc.irq, dispc.pdev); ++ iounmap(dispc.base); ++ return 0; ++} ++ ++static struct platform_driver omap_dispchw_driver = { ++ .probe = omap_dispchw_probe, ++ .remove = omap_dispchw_remove, ++ .driver = { ++ .name = "omapdss_dispc", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int dispc_init_platform_driver(void) ++{ ++ return platform_driver_register(&omap_dispchw_driver); ++} ++ ++void dispc_uninit_platform_driver(void) ++{ ++ return platform_driver_unregister(&omap_dispchw_driver); ++} +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/display.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/display.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/display.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/display.c 2011-03-09 13:19:21.083278943 +0100 +@@ -25,14 +25,11 @@ + #include + #include + #include +-#include + #include + + #include + #include "dss.h" + +-static LIST_HEAD(display_list); +- + static ssize_t display_enabled_show(struct device *dev, + struct device_attribute *attr, char *buf) + { +@@ -396,29 +393,6 @@ + switch (dssdev->type) { + #ifdef CONFIG_OMAP2_DSS_DPI + case OMAP_DISPLAY_TYPE_DPI: +-#endif +-#ifdef CONFIG_OMAP2_DSS_RFBI +- case OMAP_DISPLAY_TYPE_DBI: +-#endif +-#ifdef CONFIG_OMAP2_DSS_SDI +- case OMAP_DISPLAY_TYPE_SDI: +-#endif +-#ifdef CONFIG_OMAP2_DSS_DSI +- case OMAP_DISPLAY_TYPE_DSI: +-#endif +-#ifdef CONFIG_OMAP2_DSS_VENC +- case OMAP_DISPLAY_TYPE_VENC: +-#endif +- break; +- default: +- DSSERR("Support for display '%s' not compiled in.\n", +- dssdev->name); +- return; +- } +- +- switch (dssdev->type) { +-#ifdef CONFIG_OMAP2_DSS_DPI +- case OMAP_DISPLAY_TYPE_DPI: + r = dpi_init_display(dssdev); + break; + #endif +@@ -443,7 +417,9 @@ + break; + #endif + default: +- BUG(); ++ DSSERR("Support for display '%s' not compiled in.\n", ++ dssdev->name); ++ return; + } + + if (r) { +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dpi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dpi.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/dpi.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dpi.c 2011-03-09 13:19:21.083278943 +0100 +@@ -57,13 +57,13 @@ + if (r) + return r; + +- dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); ++ dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC); + + r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); + if (r) + return r; + +- *fck = dsi_cinfo.dsi1_pll_fclk; ++ *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; + *lck_div = dispc_cinfo.lck_div; + *pck_div = dispc_cinfo.pck_div; + +@@ -107,7 +107,7 @@ + bool is_tft; + int r = 0; + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, + dssdev->panel.acbi, dssdev->panel.acb); +@@ -137,7 +137,7 @@ + dispc_set_lcd_timings(dssdev->manager->id, t); + + err0: +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + return r; + } + +@@ -173,14 +173,14 @@ + goto err1; + } + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + r = dpi_basic_init(dssdev); + if (r) + goto err2; + + #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL +- dss_clk_enable(DSS_CLK_FCK2); ++ dss_clk_enable(DSS_CLK_SYSCK); + r = dsi_pll_init(dssdev, 0, 1); + if (r) + goto err3; +@@ -199,10 +199,10 @@ + #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL + dsi_pll_uninit(); + err3: +- dss_clk_disable(DSS_CLK_FCK2); ++ dss_clk_disable(DSS_CLK_SYSCK); + #endif + err2: +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + if (cpu_is_omap34xx()) + regulator_disable(dpi.vdds_dsi_reg); + err1: +@@ -217,12 +217,12 @@ + dssdev->manager->disable(dssdev->manager); + + #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL +- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); ++ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); + dsi_pll_uninit(); +- dss_clk_disable(DSS_CLK_FCK2); ++ dss_clk_disable(DSS_CLK_SYSCK); + #endif + +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + + if (cpu_is_omap34xx()) + regulator_disable(dpi.vdds_dsi_reg); +@@ -271,7 +271,7 @@ + if (r) + return r; + +- fck = dsi_cinfo.dsi1_pll_fclk; ++ fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; + lck_div = dispc_cinfo.lck_div; + pck_div = dispc_cinfo.pck_div; + } +@@ -303,22 +303,27 @@ + { + DSSDBG("init_display\n"); + +- return 0; +-} ++ if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) { ++ struct regulator *vdds_dsi; + +-int dpi_init(struct platform_device *pdev) +-{ +- if (cpu_is_omap34xx()) { +- dpi.vdds_dsi_reg = dss_get_vdds_dsi(); +- if (IS_ERR(dpi.vdds_dsi_reg)) { ++ vdds_dsi = dss_get_vdds_dsi(); ++ ++ if (IS_ERR(vdds_dsi)) { + DSSERR("can't get VDDS_DSI regulator\n"); +- return PTR_ERR(dpi.vdds_dsi_reg); ++ return PTR_ERR(vdds_dsi); + } ++ ++ dpi.vdds_dsi_reg = vdds_dsi; + } + + return 0; + } + ++int dpi_init(void) ++{ ++ return 0; ++} ++ + void dpi_exit(void) + { + } +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dsi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dsi.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/dsi.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dsi.c 2011-03-09 13:19:21.084278923 +0100 +@@ -38,12 +38,11 @@ + #include + + #include "dss.h" ++#include "dss_features.h" + + /*#define VERBOSE_IRQ*/ + #define DSI_CATCH_MISSING_TE + +-#define DSI_BASE 0x4804FC00 +- + struct dsi_reg { u16 idx; }; + + #define DSI_REG(idx) ((const struct dsi_reg) { idx }) +@@ -190,8 +189,8 @@ + #define FINT_MIN 750000 + #define REGN_MAX (1 << 7) + #define REGM_MAX ((1 << 11) - 1) +-#define REGM3_MAX (1 << 4) +-#define REGM4_MAX (1 << 4) ++#define REGM_DISPC_MAX (1 << 4) ++#define REGM_DSI_MAX (1 << 4) + #define LP_DIV_MAX ((1 << 13) - 1) + + enum fifo_size { +@@ -222,7 +221,9 @@ + + static struct + { ++ struct platform_device *pdev; + void __iomem *base; ++ int irq; + + struct dsi_clock_info current_cinfo; + +@@ -232,6 +233,7 @@ + enum dsi_vc_mode mode; + struct omap_dss_device *dssdev; + enum fifo_size fifo_size; ++ int vc_id; + } vc[4]; + + struct mutex lock; +@@ -481,13 +483,17 @@ + static int debug_irq; + + /* called from dss */ +-void dsi_irq_handler(void) ++static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) + { + u32 irqstatus, vcstatus, ciostatus; + int i; + + irqstatus = dsi_read_reg(DSI_IRQSTATUS); + ++ /* IRQ is not for us */ ++ if (!irqstatus) ++ return IRQ_NONE; ++ + #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS + spin_lock(&dsi.irq_stats_lock); + dsi.irq_stats.irq_count++; +@@ -565,9 +571,9 @@ + #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS + spin_unlock(&dsi.irq_stats_lock); + #endif ++ return IRQ_HANDLED; + } + +- + static void _dsi_initialize_irq(void) + { + u32 l; +@@ -637,22 +643,22 @@ + dsi_write_reg(DSI_VC_IRQENABLE(channel), l); + } + +-/* DSI func clock. this could also be DSI2_PLL_FCLK */ ++/* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ + static inline void enable_clocks(bool enable) + { + if (enable) +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + else +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + } + + /* source clock for DSI PLL. this could also be PCLKFREE */ + static inline void dsi_enable_pll_clock(bool enable) + { + if (enable) +- dss_clk_enable(DSS_CLK_FCK2); ++ dss_clk_enable(DSS_CLK_SYSCK); + else +- dss_clk_disable(DSS_CLK_FCK2); ++ dss_clk_disable(DSS_CLK_SYSCK); + + if (enable && dsi.pll_locked) { + if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) +@@ -707,14 +713,14 @@ + return 0; + } + +-unsigned long dsi_get_dsi1_pll_rate(void) ++unsigned long dsi_get_pll_hsdiv_dispc_rate(void) + { +- return dsi.current_cinfo.dsi1_pll_fclk; ++ return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk; + } + +-static unsigned long dsi_get_dsi2_pll_rate(void) ++static unsigned long dsi_get_pll_hsdiv_dsi_rate(void) + { +- return dsi.current_cinfo.dsi2_pll_fclk; ++ return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk; + } + + static unsigned long dsi_get_txbyteclkhs(void) +@@ -726,12 +732,12 @@ + { + unsigned long r; + +- if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) { +- /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ +- r = dss_clk_get_rate(DSS_CLK_FCK1); ++ if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) { ++ /* DSI FCLK source is DSS_CLK_FCK */ ++ r = dss_clk_get_rate(DSS_CLK_FCK); + } else { +- /* DSI FCLK source is DSI2_PLL_FCLK */ +- r = dsi_get_dsi2_pll_rate(); ++ /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ ++ r = dsi_get_pll_hsdiv_dsi_rate(); + } + + return r; +@@ -801,16 +807,16 @@ + if (cinfo->regm == 0 || cinfo->regm > REGM_MAX) + return -EINVAL; + +- if (cinfo->regm3 > REGM3_MAX) ++ if (cinfo->regm_dispc > REGM_DISPC_MAX) + return -EINVAL; + +- if (cinfo->regm4 > REGM4_MAX) ++ if (cinfo->regm_dsi > REGM_DSI_MAX) + return -EINVAL; + +- if (cinfo->use_dss2_fck) { +- cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2); ++ if (cinfo->use_sys_clk) { ++ cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); + /* XXX it is unclear if highfreq should be used +- * with DSS2_FCK source also */ ++ * with DSS_SYS_CLK source also */ + cinfo->highfreq = 0; + } else { + cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); +@@ -831,15 +837,17 @@ + if (cinfo->clkin4ddr > 1800 * 1000 * 1000) + return -EINVAL; + +- if (cinfo->regm3 > 0) +- cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3; ++ if (cinfo->regm_dispc > 0) ++ cinfo->dsi_pll_hsdiv_dispc_clk = ++ cinfo->clkin4ddr / cinfo->regm_dispc; + else +- cinfo->dsi1_pll_fclk = 0; ++ cinfo->dsi_pll_hsdiv_dispc_clk = 0; + +- if (cinfo->regm4 > 0) +- cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4; ++ if (cinfo->regm_dsi > 0) ++ cinfo->dsi_pll_hsdiv_dsi_clk = ++ cinfo->clkin4ddr / cinfo->regm_dsi; + else +- cinfo->dsi2_pll_fclk = 0; ++ cinfo->dsi_pll_hsdiv_dsi_clk = 0; + + return 0; + } +@@ -852,23 +860,25 @@ + struct dispc_clock_info best_dispc; + int min_fck_per_pck; + int match = 0; +- unsigned long dss_clk_fck2; ++ unsigned long dss_sys_clk, max_dss_fck; + +- dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); ++ dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); ++ ++ max_dss_fck = dss_feat_get_max_dss_fck(); + + if (req_pck == dsi.cache_req_pck && +- dsi.cache_cinfo.clkin == dss_clk_fck2) { ++ dsi.cache_cinfo.clkin == dss_sys_clk) { + DSSDBG("DSI clock info found from cache\n"); + *dsi_cinfo = dsi.cache_cinfo; +- dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk, +- dispc_cinfo); ++ dispc_find_clk_divs(is_tft, req_pck, ++ dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); + return 0; + } + + min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; + + if (min_fck_per_pck && +- req_pck * min_fck_per_pck > DISPC_MAX_FCK) { ++ req_pck * min_fck_per_pck > max_dss_fck) { + DSSERR("Requested pixel clock not possible with the current " + "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " + "the constraint off.\n"); +@@ -882,8 +892,8 @@ + memset(&best_dispc, 0, sizeof(best_dispc)); + + memset(&cur, 0, sizeof(cur)); +- cur.clkin = dss_clk_fck2; +- cur.use_dss2_fck = 1; ++ cur.clkin = dss_sys_clk; ++ cur.use_sys_clk = 1; + cur.highfreq = 0; + + /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ +@@ -909,30 +919,32 @@ + if (cur.clkin4ddr > 1800 * 1000 * 1000) + break; + +- /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ +- for (cur.regm3 = 1; cur.regm3 < REGM3_MAX; +- ++cur.regm3) { ++ /* dsi_pll_hsdiv_dispc_clk(MHz) = ++ * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ ++ for (cur.regm_dispc = 1; cur.regm_dispc < REGM_DISPC_MAX; ++ ++cur.regm_dispc) { + struct dispc_clock_info cur_dispc; +- cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3; ++ cur.dsi_pll_hsdiv_dispc_clk = ++ cur.clkin4ddr / cur.regm_dispc; + + /* this will narrow down the search a bit, + * but still give pixclocks below what was + * requested */ +- if (cur.dsi1_pll_fclk < req_pck) ++ if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) + break; + +- if (cur.dsi1_pll_fclk > DISPC_MAX_FCK) ++ if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) + continue; + + if (min_fck_per_pck && +- cur.dsi1_pll_fclk < ++ cur.dsi_pll_hsdiv_dispc_clk < + req_pck * min_fck_per_pck) + continue; + + match = 1; + + dispc_find_clk_divs(is_tft, req_pck, +- cur.dsi1_pll_fclk, ++ cur.dsi_pll_hsdiv_dispc_clk, + &cur_dispc); + + if (abs(cur_dispc.pck - req_pck) < +@@ -961,9 +973,9 @@ + return -EINVAL; + } + +- /* DSI2_PLL_FCLK (regm4) is not used */ +- best.regm4 = 0; +- best.dsi2_pll_fclk = 0; ++ /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ ++ best.regm_dsi = 0; ++ best.dsi_pll_hsdiv_dsi_clk = 0; + + if (dsi_cinfo) + *dsi_cinfo = best; +@@ -987,18 +999,20 @@ + + dsi.current_cinfo.fint = cinfo->fint; + dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; +- dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk; +- dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk; ++ dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk = ++ cinfo->dsi_pll_hsdiv_dispc_clk; ++ dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk = ++ cinfo->dsi_pll_hsdiv_dsi_clk; + + dsi.current_cinfo.regn = cinfo->regn; + dsi.current_cinfo.regm = cinfo->regm; +- dsi.current_cinfo.regm3 = cinfo->regm3; +- dsi.current_cinfo.regm4 = cinfo->regm4; ++ dsi.current_cinfo.regm_dispc = cinfo->regm_dispc; ++ dsi.current_cinfo.regm_dsi = cinfo->regm_dsi; + + DSSDBG("DSI Fint %ld\n", cinfo->fint); + + DSSDBG("clkin (%s) rate %ld, highfreq %d\n", +- cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree", ++ cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", + cinfo->clkin, + cinfo->highfreq); + +@@ -1015,10 +1029,14 @@ + + DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); + +- DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", +- cinfo->regm3, cinfo->dsi1_pll_fclk); +- DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", +- cinfo->regm4, cinfo->dsi2_pll_fclk); ++ DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, ++ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), ++ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), ++ cinfo->dsi_pll_hsdiv_dispc_clk); ++ DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, ++ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), ++ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), ++ cinfo->dsi_pll_hsdiv_dsi_clk); + + REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ + +@@ -1026,9 +1044,9 @@ + l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ + l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ + l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ +- l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0, ++ l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, + 22, 19); /* DSI_CLOCK_DIV */ +- l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0, ++ l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, + 26, 23); /* DSIPROTO_CLOCK_DIV */ + dsi_write_reg(DSI_PLL_CONFIGURATION1, l); + +@@ -1046,7 +1064,7 @@ + + l = dsi_read_reg(DSI_PLL_CONFIGURATION2); + l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ +- l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, ++ l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, + 11, 11); /* DSI_PLL_CLKSEL */ + l = FLD_MOD(l, cinfo->highfreq, + 12, 12); /* DSI_PLL_HIGHFREQ */ +@@ -1101,6 +1119,26 @@ + + DSSDBG("PLL init\n"); + ++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL ++ /* ++ * HACK: this is just a quick hack to get the USE_DSI_PLL ++ * option working. USE_DSI_PLL is itself a big hack, and ++ * should be removed. ++ */ ++ if (dsi.vdds_dsi_reg == NULL) { ++ struct regulator *vdds_dsi; ++ ++ vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); ++ ++ if (IS_ERR(vdds_dsi)) { ++ DSSERR("can't get VDDS_DSI regulator\n"); ++ return PTR_ERR(vdds_dsi); ++ } ++ ++ dsi.vdds_dsi_reg = vdds_dsi; ++ } ++#endif ++ + enable_clocks(1); + dsi_enable_pll_clock(1); + +@@ -1162,6 +1200,10 @@ + { + int clksel; + struct dsi_clock_info *cinfo = &dsi.current_cinfo; ++ enum dss_clk_source dispc_clk_src, dsi_clk_src; ++ ++ dispc_clk_src = dss_get_dispc_clk_source(); ++ dsi_clk_src = dss_get_dsi_clk_source(); + + enable_clocks(1); + +@@ -1171,30 +1213,34 @@ + + seq_printf(s, "dsi pll source = %s\n", + clksel == 0 ? +- "dss2_alwon_fclk" : "pclkfree"); ++ "dss_sys_clk" : "pclkfree"); + + seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); + + seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", + cinfo->clkin4ddr, cinfo->regm); + +- seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", +- cinfo->dsi1_pll_fclk, +- cinfo->regm3, +- dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? ++ seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", ++ dss_get_generic_clk_source_name(dispc_clk_src), ++ dss_feat_get_clk_source_name(dispc_clk_src), ++ cinfo->dsi_pll_hsdiv_dispc_clk, ++ cinfo->regm_dispc, ++ dispc_clk_src == DSS_CLK_SRC_FCK ? + "off" : "on"); + +- seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", +- cinfo->dsi2_pll_fclk, +- cinfo->regm4, +- dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? ++ seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", ++ dss_get_generic_clk_source_name(dsi_clk_src), ++ dss_feat_get_clk_source_name(dsi_clk_src), ++ cinfo->dsi_pll_hsdiv_dsi_clk, ++ cinfo->regm_dsi, ++ dsi_clk_src == DSS_CLK_SRC_FCK ? + "off" : "on"); + + seq_printf(s, "- DSI -\n"); + +- seq_printf(s, "dsi fclk source = %s\n", +- dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? +- "dss1_alwon_fclk" : "dsi2_pll_fclk"); ++ seq_printf(s, "dsi fclk source = %s (%s)\n", ++ dss_get_generic_clk_source_name(dsi_clk_src), ++ dss_feat_get_clk_source_name(dsi_clk_src)); + + seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); + +@@ -1306,7 +1352,7 @@ + { + #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + DUMPREG(DSI_REVISION); + DUMPREG(DSI_SYSCONFIG); +@@ -1378,7 +1424,7 @@ + DUMPREG(DSI_PLL_CONFIGURATION1); + DUMPREG(DSI_PLL_CONFIGURATION2); + +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + #undef DUMPREG + } + +@@ -1622,20 +1668,6 @@ + return _dsi_wait_reset(); + } + +-static void dsi_reset_tx_fifo(int channel) +-{ +- u32 mask; +- u32 l; +- +- /* set fifosize of the channel to 0, then return the old size */ +- l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE); +- +- mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4); +- dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask); +- +- dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l); +-} +- + static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, + enum fifo_size size3, enum fifo_size size4) + { +@@ -1753,8 +1785,6 @@ + r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ + + dsi_write_reg(DSI_VC_CTRL(channel), r); +- +- dsi.vc[channel].mode = DSI_VC_MODE_L4; + } + + static int dsi_vc_config_l4(int channel) +@@ -1961,7 +1991,7 @@ + + WARN_ON(!dsi_bus_is_locked()); + +- data_id = data_type | channel << 6; ++ data_id = data_type | dsi.vc[channel].vc_id << 6; + + val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | + FLD_VAL(ecc, 31, 24); +@@ -2064,7 +2094,7 @@ + return -EINVAL; + } + +- data_id = data_type | channel << 6; ++ data_id = data_type | dsi.vc[channel].vc_id << 6; + + r = (data_id << 0) | (data << 8) | (ecc << 24); + +@@ -2984,12 +3014,12 @@ + struct dsi_clock_info cinfo; + int r; + +- /* we always use DSS2_FCK as input clock */ +- cinfo.use_dss2_fck = true; ++ /* we always use DSS_CLK_SYSCK as input clock */ ++ cinfo.use_sys_clk = true; + cinfo.regn = dssdev->phy.dsi.div.regn; + cinfo.regm = dssdev->phy.dsi.div.regm; +- cinfo.regm3 = dssdev->phy.dsi.div.regm3; +- cinfo.regm4 = dssdev->phy.dsi.div.regm4; ++ cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc; ++ cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi; + r = dsi_calc_clock_rates(dssdev, &cinfo); + if (r) { + DSSERR("Failed to calc dsi clocks\n"); +@@ -3011,7 +3041,7 @@ + int r; + unsigned long long fck; + +- fck = dsi_get_dsi1_pll_rate(); ++ fck = dsi_get_pll_hsdiv_dispc_rate(); + + dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div; + dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div; +@@ -3045,8 +3075,8 @@ + if (r) + goto err1; + +- dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); +- dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK); ++ dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC); ++ dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI); + + DSSDBG("PLL OK\n"); + +@@ -3082,8 +3112,8 @@ + err3: + dsi_complexio_uninit(); + err2: +- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); +- dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); ++ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); ++ dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); + err1: + dsi_pll_uninit(); + err0: +@@ -3099,8 +3129,8 @@ + dsi_vc_enable(2, 0); + dsi_vc_enable(3, 0); + +- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); +- dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); ++ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); ++ dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); + dsi_complexio_uninit(); + dsi_pll_uninit(); + } +@@ -3220,28 +3250,94 @@ + dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | + OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; + +- dsi.vc[0].dssdev = dssdev; +- dsi.vc[1].dssdev = dssdev; ++ if (dsi.vdds_dsi_reg == NULL) { ++ struct regulator *vdds_dsi; ++ ++ vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); ++ ++ if (IS_ERR(vdds_dsi)) { ++ DSSERR("can't get VDDS_DSI regulator\n"); ++ return PTR_ERR(vdds_dsi); ++ } ++ ++ dsi.vdds_dsi_reg = vdds_dsi; ++ } ++ ++ return 0; ++} ++ ++int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { ++ if (!dsi.vc[i].dssdev) { ++ dsi.vc[i].dssdev = dssdev; ++ *channel = i; ++ return 0; ++ } ++ } ++ ++ DSSERR("cannot get VC for display %s", dssdev->name); ++ return -ENOSPC; ++} ++EXPORT_SYMBOL(omap_dsi_request_vc); ++ ++int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) ++{ ++ if (vc_id < 0 || vc_id > 3) { ++ DSSERR("VC ID out of range\n"); ++ return -EINVAL; ++ } ++ ++ if (channel < 0 || channel > 3) { ++ DSSERR("Virtual Channel out of range\n"); ++ return -EINVAL; ++ } ++ ++ if (dsi.vc[channel].dssdev != dssdev) { ++ DSSERR("Virtual Channel not allocated to display %s\n", ++ dssdev->name); ++ return -EINVAL; ++ } ++ ++ dsi.vc[channel].vc_id = vc_id; + + return 0; + } ++EXPORT_SYMBOL(omap_dsi_set_vc_id); + +-void dsi_wait_dsi1_pll_active(void) ++void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) ++{ ++ if ((channel >= 0 && channel <= 3) && ++ dsi.vc[channel].dssdev == dssdev) { ++ dsi.vc[channel].dssdev = NULL; ++ dsi.vc[channel].vc_id = 0; ++ } ++} ++EXPORT_SYMBOL(omap_dsi_release_vc); ++ ++void dsi_wait_pll_hsdiv_dispc_active(void) + { + if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) +- DSSERR("DSI1 PLL clock not active\n"); ++ DSSERR("%s (%s) not active\n", ++ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), ++ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); + } + +-void dsi_wait_dsi2_pll_active(void) ++void dsi_wait_pll_hsdiv_dsi_active(void) + { + if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) +- DSSERR("DSI2 PLL clock not active\n"); ++ DSSERR("%s (%s) not active\n", ++ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), ++ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); + } + +-int dsi_init(struct platform_device *pdev) ++static int dsi_init(struct platform_device *pdev) + { + u32 rev; +- int r; ++ int r, i; ++ struct resource *dsi_mem; + + spin_lock_init(&dsi.errors_lock); + dsi.errors = 0; +@@ -3268,24 +3364,43 @@ + dsi.te_timer.function = dsi_te_timeout; + dsi.te_timer.data = 0; + #endif +- dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS); ++ dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0); ++ if (!dsi_mem) { ++ DSSERR("can't get IORESOURCE_MEM DSI\n"); ++ r = -EINVAL; ++ goto err1; ++ } ++ dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem)); + if (!dsi.base) { + DSSERR("can't ioremap DSI\n"); + r = -ENOMEM; + goto err1; + } ++ dsi.irq = platform_get_irq(dsi.pdev, 0); ++ if (dsi.irq < 0) { ++ DSSERR("platform_get_irq failed\n"); ++ r = -ENODEV; ++ goto err2; ++ } + +- dsi.vdds_dsi_reg = dss_get_vdds_dsi(); +- if (IS_ERR(dsi.vdds_dsi_reg)) { +- DSSERR("can't get VDDS_DSI regulator\n"); +- r = PTR_ERR(dsi.vdds_dsi_reg); ++ r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED, ++ "OMAP DSI1", dsi.pdev); ++ if (r < 0) { ++ DSSERR("request_irq failed\n"); + goto err2; + } + ++ /* DSI VCs initialization */ ++ for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { ++ dsi.vc[i].mode = DSI_VC_MODE_L4; ++ dsi.vc[i].dssdev = NULL; ++ dsi.vc[i].vc_id = 0; ++ } ++ + enable_clocks(1); + + rev = dsi_read_reg(DSI_REVISION); +- printk(KERN_INFO "OMAP DSI rev %d.%d\n", ++ dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n", + FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); + + enable_clocks(0); +@@ -3298,8 +3413,14 @@ + return r; + } + +-void dsi_exit(void) ++static void dsi_exit(void) + { ++ if (dsi.vdds_dsi_reg != NULL) { ++ regulator_put(dsi.vdds_dsi_reg); ++ dsi.vdds_dsi_reg = NULL; ++ } ++ ++ free_irq(dsi.irq, dsi.pdev); + iounmap(dsi.base); + + destroy_workqueue(dsi.workqueue); +@@ -3307,3 +3428,41 @@ + DSSDBG("omap_dsi_exit\n"); + } + ++/* DSI1 HW IP initialisation */ ++static int omap_dsi1hw_probe(struct platform_device *pdev) ++{ ++ int r; ++ dsi.pdev = pdev; ++ r = dsi_init(pdev); ++ if (r) { ++ DSSERR("Failed to initialize DSI\n"); ++ goto err_dsi; ++ } ++err_dsi: ++ return r; ++} ++ ++static int omap_dsi1hw_remove(struct platform_device *pdev) ++{ ++ dsi_exit(); ++ return 0; ++} ++ ++static struct platform_driver omap_dsi1hw_driver = { ++ .probe = omap_dsi1hw_probe, ++ .remove = omap_dsi1hw_remove, ++ .driver = { ++ .name = "omapdss_dsi1", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int dsi_init_platform_driver(void) ++{ ++ return platform_driver_register(&omap_dsi1hw_driver); ++} ++ ++void dsi_uninit_platform_driver(void) ++{ ++ return platform_driver_unregister(&omap_dsi1hw_driver); ++} +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/dss.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.c 2011-03-09 13:19:21.085278903 +0100 +@@ -26,14 +26,13 @@ + #include + #include + #include +-#include + #include + #include + + #include ++#include + #include "dss.h" +- +-#define DSS_BASE 0x48050000 ++#include "dss_features.h" + + #define DSS_SZ_REGS SZ_512 + +@@ -59,9 +58,17 @@ + dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) + + static struct { ++ struct platform_device *pdev; + void __iomem *base; ++ int ctx_id; + + struct clk *dpll4_m4_ck; ++ struct clk *dss_ick; ++ struct clk *dss_fck; ++ struct clk *dss_sys_clk; ++ struct clk *dss_tv_fck; ++ struct clk *dss_video_fck; ++ unsigned num_clks_enabled; + + unsigned long cache_req_pck; + unsigned long cache_prate; +@@ -70,10 +77,22 @@ + + enum dss_clk_source dsi_clk_source; + enum dss_clk_source dispc_clk_source; ++ enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; + + u32 ctx[DSS_SZ_REGS / sizeof(u32)]; + } dss; + ++static const struct dss_clk_source_name dss_generic_clk_source_names[] = { ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" }, ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" }, ++ { DSS_CLK_SRC_FCK, "DSS_FCK" }, ++}; ++ ++static void dss_clk_enable_all_no_ctx(void); ++static void dss_clk_disable_all_no_ctx(void); ++static void dss_clk_enable_no_ctx(enum dss_clock clks); ++static void dss_clk_disable_no_ctx(enum dss_clock clks); ++ + static int _omap_dss_wait_reset(void); + + static inline void dss_write_reg(const struct dss_reg idx, u32 val) +@@ -99,10 +118,11 @@ + SR(SYSCONFIG); + SR(CONTROL); + +-#ifdef CONFIG_OMAP2_DSS_SDI +- SR(SDI_CONTROL); +- SR(PLL_CONTROL); +-#endif ++ if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & ++ OMAP_DISPLAY_TYPE_SDI) { ++ SR(SDI_CONTROL); ++ SR(PLL_CONTROL); ++ } + } + + void dss_restore_context(void) +@@ -113,10 +133,11 @@ + RR(SYSCONFIG); + RR(CONTROL); + +-#ifdef CONFIG_OMAP2_DSS_SDI +- RR(SDI_CONTROL); +- RR(PLL_CONTROL); +-#endif ++ if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & ++ OMAP_DISPLAY_TYPE_SDI) { ++ RR(SDI_CONTROL); ++ RR(PLL_CONTROL); ++ } + } + + #undef SR +@@ -209,12 +230,17 @@ + REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ + } + ++const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src) ++{ ++ return dss_generic_clk_source_names[clk_src].clksrc_name; ++} ++ + void dss_dump_clocks(struct seq_file *s) + { + unsigned long dpll4_ck_rate; + unsigned long dpll4_m4_ck_rate; + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); + dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); +@@ -224,51 +250,66 @@ + seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); + + if (cpu_is_omap3630()) +- seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", ++ seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", ++ dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), ++ dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), + dpll4_ck_rate, + dpll4_ck_rate / dpll4_m4_ck_rate, +- dss_clk_get_rate(DSS_CLK_FCK1)); ++ dss_clk_get_rate(DSS_CLK_FCK)); + else +- seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", ++ seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", ++ dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), ++ dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), + dpll4_ck_rate, + dpll4_ck_rate / dpll4_m4_ck_rate, +- dss_clk_get_rate(DSS_CLK_FCK1)); ++ dss_clk_get_rate(DSS_CLK_FCK)); + +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + } + + void dss_dump_regs(struct seq_file *s) + { + #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + DUMPREG(DSS_REVISION); + DUMPREG(DSS_SYSCONFIG); + DUMPREG(DSS_SYSSTATUS); + DUMPREG(DSS_IRQSTATUS); + DUMPREG(DSS_CONTROL); +- DUMPREG(DSS_SDI_CONTROL); +- DUMPREG(DSS_PLL_CONTROL); +- DUMPREG(DSS_SDI_STATUS); + +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & ++ OMAP_DISPLAY_TYPE_SDI) { ++ DUMPREG(DSS_SDI_CONTROL); ++ DUMPREG(DSS_PLL_CONTROL); ++ DUMPREG(DSS_SDI_STATUS); ++ } ++ ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + #undef DUMPREG + } + + void dss_select_dispc_clk_source(enum dss_clk_source clk_src) + { + int b; ++ u8 start, end; + +- BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && +- clk_src != DSS_SRC_DSS1_ALWON_FCLK); +- +- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; ++ switch (clk_src) { ++ case DSS_CLK_SRC_FCK: ++ b = 0; ++ break; ++ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: ++ b = 1; ++ dsi_wait_pll_hsdiv_dispc_active(); ++ break; ++ default: ++ BUG(); ++ } + +- if (clk_src == DSS_SRC_DSI1_PLL_FCLK) +- dsi_wait_dsi1_pll_active(); ++ dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); + +- REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ ++ REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ + + dss.dispc_clk_source = clk_src; + } +@@ -277,19 +318,51 @@ + { + int b; + +- BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && +- clk_src != DSS_SRC_DSS1_ALWON_FCLK); +- +- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; +- +- if (clk_src == DSS_SRC_DSI2_PLL_FCLK) +- dsi_wait_dsi2_pll_active(); ++ switch (clk_src) { ++ case DSS_CLK_SRC_FCK: ++ b = 0; ++ break; ++ case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: ++ b = 1; ++ dsi_wait_pll_hsdiv_dsi_active(); ++ break; ++ default: ++ BUG(); ++ } + + REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ + + dss.dsi_clk_source = clk_src; + } + ++void dss_select_lcd_clk_source(enum omap_channel channel, ++ enum dss_clk_source clk_src) ++{ ++ int b, ix, pos; ++ ++ if (!dss_has_feature(FEAT_LCD_CLK_SRC)) ++ return; ++ ++ switch (clk_src) { ++ case DSS_CLK_SRC_FCK: ++ b = 0; ++ break; ++ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: ++ BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); ++ b = 1; ++ dsi_wait_pll_hsdiv_dispc_active(); ++ break; ++ default: ++ BUG(); ++ } ++ ++ pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; ++ REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ ++ ++ ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; ++ dss.lcd_clk_source[ix] = clk_src; ++} ++ + enum dss_clk_source dss_get_dispc_clk_source(void) + { + return dss.dispc_clk_source; +@@ -300,6 +373,12 @@ + return dss.dsi_clk_source; + } + ++enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) ++{ ++ int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; ++ return dss.lcd_clk_source[ix]; ++} ++ + /* calculate clock rates using dividers in cinfo */ + int dss_calc_clock_rates(struct dss_clock_info *cinfo) + { +@@ -337,7 +416,7 @@ + + int dss_get_clock_div(struct dss_clock_info *cinfo) + { +- cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1); ++ cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); + + if (cpu_is_omap34xx()) { + unsigned long prate; +@@ -369,7 +448,7 @@ + struct dss_clock_info best_dss; + struct dispc_clock_info best_dispc; + +- unsigned long fck; ++ unsigned long fck, max_dss_fck; + + u16 fck_div; + +@@ -378,7 +457,9 @@ + + prate = dss_get_dpll4_rate(); + +- fck = dss_clk_get_rate(DSS_CLK_FCK1); ++ max_dss_fck = dss_feat_get_max_dss_fck(); ++ ++ fck = dss_clk_get_rate(DSS_CLK_FCK); + if (req_pck == dss.cache_req_pck && + ((cpu_is_omap34xx() && prate == dss.cache_prate) || + dss.cache_dss_cinfo.fck == fck)) { +@@ -391,7 +472,7 @@ + min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; + + if (min_fck_per_pck && +- req_pck * min_fck_per_pck > DISPC_MAX_FCK) { ++ req_pck * min_fck_per_pck > max_dss_fck) { + DSSERR("Requested pixel clock not possible with the current " + "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " + "the constraint off.\n"); +@@ -405,7 +486,7 @@ + if (cpu_is_omap24xx()) { + struct dispc_clock_info cur_dispc; + /* XXX can we change the clock on omap2? */ +- fck = dss_clk_get_rate(DSS_CLK_FCK1); ++ fck = dss_clk_get_rate(DSS_CLK_FCK); + fck_div = 1; + + dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); +@@ -427,7 +508,7 @@ + else + fck = prate / fck_div * 2; + +- if (fck > DISPC_MAX_FCK) ++ if (fck > max_dss_fck) + continue; + + if (min_fck_per_pck && +@@ -482,31 +563,6 @@ + return 0; + } + +- +- +-static irqreturn_t dss_irq_handler_omap2(int irq, void *arg) +-{ +- dispc_irq_handler(); +- +- return IRQ_HANDLED; +-} +- +-static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) +-{ +- u32 irqstatus; +- +- irqstatus = dss_read_reg(DSS_IRQSTATUS); +- +- if (irqstatus & (1<<0)) /* DISPC_IRQ */ +- dispc_irq_handler(); +-#ifdef CONFIG_OMAP2_DSS_DSI +- if (irqstatus & (1<<1)) /* DSI_IRQ */ +- dsi_irq_handler(); +-#endif +- +- return IRQ_HANDLED; +-} +- + static int _omap_dss_wait_reset(void) + { + int t = 0; +@@ -549,34 +605,39 @@ + REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ + } + +-int dss_init(bool skip_init) ++static int dss_init(void) + { + int r; + u32 rev; ++ struct resource *dss_mem; + +- dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); ++ dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); ++ if (!dss_mem) { ++ DSSERR("can't get IORESOURCE_MEM DSS\n"); ++ r = -EINVAL; ++ goto fail0; ++ } ++ dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); + if (!dss.base) { + DSSERR("can't ioremap DSS\n"); + r = -ENOMEM; + goto fail0; + } + +- if (!skip_init) { +- /* disable LCD and DIGIT output. This seems to fix the synclost +- * problem that we get, if the bootloader starts the DSS and +- * the kernel resets it */ +- omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); +- +- /* We need to wait here a bit, otherwise we sometimes start to +- * get synclost errors, and after that only power cycle will +- * restore DSS functionality. I have no idea why this happens. +- * And we have to wait _before_ resetting the DSS, but after +- * enabling clocks. +- */ +- msleep(50); ++ /* disable LCD and DIGIT output. This seems to fix the synclost ++ * problem that we get, if the bootloader starts the DSS and ++ * the kernel resets it */ ++ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); ++ ++ /* We need to wait here a bit, otherwise we sometimes start to ++ * get synclost errors, and after that only power cycle will ++ * restore DSS functionality. I have no idea why this happens. ++ * And we have to wait _before_ resetting the DSS, but after ++ * enabling clocks. ++ */ ++ msleep(50); + +- _omap_dss_reset(); +- } ++ _omap_dss_reset(); + + /* autoidle */ + REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); +@@ -590,28 +651,19 @@ + REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ + #endif + +- r = request_irq(INT_24XX_DSS_IRQ, +- cpu_is_omap24xx() +- ? dss_irq_handler_omap2 +- : dss_irq_handler_omap3, +- 0, "OMAP DSS", NULL); +- +- if (r < 0) { +- DSSERR("omap2 dss: request_irq failed\n"); +- goto fail1; +- } +- + if (cpu_is_omap34xx()) { + dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); + if (IS_ERR(dss.dpll4_m4_ck)) { + DSSERR("Failed to get dpll4_m4_ck\n"); + r = PTR_ERR(dss.dpll4_m4_ck); +- goto fail2; ++ goto fail1; + } + } + +- dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; +- dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; ++ dss.dsi_clk_source = DSS_CLK_SRC_FCK; ++ dss.dispc_clk_source = DSS_CLK_SRC_FCK; ++ dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; ++ dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; + + dss_save_context(); + +@@ -621,21 +673,416 @@ + + return 0; + +-fail2: +- free_irq(INT_24XX_DSS_IRQ, NULL); + fail1: + iounmap(dss.base); + fail0: + return r; + } + +-void dss_exit(void) ++static void dss_exit(void) + { + if (cpu_is_omap34xx()) + clk_put(dss.dpll4_m4_ck); + +- free_irq(INT_24XX_DSS_IRQ, NULL); +- + iounmap(dss.base); + } + ++/* CONTEXT */ ++static int dss_get_ctx_id(void) ++{ ++ struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; ++ int r; ++ ++ if (!pdata->board_data->get_last_off_on_transaction_id) ++ return 0; ++ r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev); ++ if (r < 0) { ++ dev_err(&dss.pdev->dev, "getting transaction ID failed, " ++ "will force context restore\n"); ++ r = -1; ++ } ++ return r; ++} ++ ++int dss_need_ctx_restore(void) ++{ ++ int id = dss_get_ctx_id(); ++ ++ if (id < 0 || id != dss.ctx_id) { ++ DSSDBG("ctx id %d -> id %d\n", ++ dss.ctx_id, id); ++ dss.ctx_id = id; ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++static void save_all_ctx(void) ++{ ++ DSSDBG("save context\n"); ++ ++ dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); ++ ++ dss_save_context(); ++ dispc_save_context(); ++#ifdef CONFIG_OMAP2_DSS_DSI ++ dsi_save_context(); ++#endif ++ ++ dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); ++} ++ ++static void restore_all_ctx(void) ++{ ++ DSSDBG("restore context\n"); ++ ++ dss_clk_enable_all_no_ctx(); ++ ++ dss_restore_context(); ++ dispc_restore_context(); ++#ifdef CONFIG_OMAP2_DSS_DSI ++ dsi_restore_context(); ++#endif ++ ++ dss_clk_disable_all_no_ctx(); ++} ++ ++static int dss_get_clock(struct clk **clock, const char *clk_name) ++{ ++ struct clk *clk; ++ ++ clk = clk_get(&dss.pdev->dev, clk_name); ++ ++ if (IS_ERR(clk)) { ++ DSSERR("can't get clock %s", clk_name); ++ return PTR_ERR(clk); ++ } ++ ++ *clock = clk; ++ ++ DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); ++ ++ return 0; ++} ++ ++static int dss_get_clocks(void) ++{ ++ int r; ++ struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; ++ ++ dss.dss_ick = NULL; ++ dss.dss_fck = NULL; ++ dss.dss_sys_clk = NULL; ++ dss.dss_tv_fck = NULL; ++ dss.dss_video_fck = NULL; ++ ++ r = dss_get_clock(&dss.dss_ick, "ick"); ++ if (r) ++ goto err; ++ ++ r = dss_get_clock(&dss.dss_fck, "fck"); ++ if (r) ++ goto err; ++ ++ if (!pdata->opt_clock_available) { ++ r = -ENODEV; ++ goto err; ++ } ++ ++ if (pdata->opt_clock_available("sys_clk")) { ++ r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); ++ if (r) ++ goto err; ++ } ++ ++ if (pdata->opt_clock_available("tv_clk")) { ++ r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); ++ if (r) ++ goto err; ++ } ++ ++ if (pdata->opt_clock_available("video_clk")) { ++ r = dss_get_clock(&dss.dss_video_fck, "video_clk"); ++ if (r) ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ if (dss.dss_ick) ++ clk_put(dss.dss_ick); ++ if (dss.dss_fck) ++ clk_put(dss.dss_fck); ++ if (dss.dss_sys_clk) ++ clk_put(dss.dss_sys_clk); ++ if (dss.dss_tv_fck) ++ clk_put(dss.dss_tv_fck); ++ if (dss.dss_video_fck) ++ clk_put(dss.dss_video_fck); ++ ++ return r; ++} ++ ++static void dss_put_clocks(void) ++{ ++ if (dss.dss_video_fck) ++ clk_put(dss.dss_video_fck); ++ if (dss.dss_tv_fck) ++ clk_put(dss.dss_tv_fck); ++ if (dss.dss_sys_clk) ++ clk_put(dss.dss_sys_clk); ++ clk_put(dss.dss_fck); ++ clk_put(dss.dss_ick); ++} ++ ++unsigned long dss_clk_get_rate(enum dss_clock clk) ++{ ++ switch (clk) { ++ case DSS_CLK_ICK: ++ return clk_get_rate(dss.dss_ick); ++ case DSS_CLK_FCK: ++ return clk_get_rate(dss.dss_fck); ++ case DSS_CLK_SYSCK: ++ return clk_get_rate(dss.dss_sys_clk); ++ case DSS_CLK_TVFCK: ++ return clk_get_rate(dss.dss_tv_fck); ++ case DSS_CLK_VIDFCK: ++ return clk_get_rate(dss.dss_video_fck); ++ } ++ ++ BUG(); ++ return 0; ++} ++ ++static unsigned count_clk_bits(enum dss_clock clks) ++{ ++ unsigned num_clks = 0; ++ ++ if (clks & DSS_CLK_ICK) ++ ++num_clks; ++ if (clks & DSS_CLK_FCK) ++ ++num_clks; ++ if (clks & DSS_CLK_SYSCK) ++ ++num_clks; ++ if (clks & DSS_CLK_TVFCK) ++ ++num_clks; ++ if (clks & DSS_CLK_VIDFCK) ++ ++num_clks; ++ ++ return num_clks; ++} ++ ++static void dss_clk_enable_no_ctx(enum dss_clock clks) ++{ ++ unsigned num_clks = count_clk_bits(clks); ++ ++ if (clks & DSS_CLK_ICK) ++ clk_enable(dss.dss_ick); ++ if (clks & DSS_CLK_FCK) ++ clk_enable(dss.dss_fck); ++ if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) ++ clk_enable(dss.dss_sys_clk); ++ if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) ++ clk_enable(dss.dss_tv_fck); ++ if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) ++ clk_enable(dss.dss_video_fck); ++ ++ dss.num_clks_enabled += num_clks; ++} ++ ++void dss_clk_enable(enum dss_clock clks) ++{ ++ bool check_ctx = dss.num_clks_enabled == 0; ++ ++ dss_clk_enable_no_ctx(clks); ++ ++ /* ++ * HACK: On omap4 the registers may not be accessible right after ++ * enabling the clocks. At some point this will be handled by ++ * pm_runtime, but for the time begin this should make things work. ++ */ ++ if (cpu_is_omap44xx() && check_ctx) ++ udelay(10); ++ ++ if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) ++ restore_all_ctx(); ++} ++ ++static void dss_clk_disable_no_ctx(enum dss_clock clks) ++{ ++ unsigned num_clks = count_clk_bits(clks); ++ ++ if (clks & DSS_CLK_ICK) ++ clk_disable(dss.dss_ick); ++ if (clks & DSS_CLK_FCK) ++ clk_disable(dss.dss_fck); ++ if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) ++ clk_disable(dss.dss_sys_clk); ++ if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) ++ clk_disable(dss.dss_tv_fck); ++ if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) ++ clk_disable(dss.dss_video_fck); ++ ++ dss.num_clks_enabled -= num_clks; ++} ++ ++void dss_clk_disable(enum dss_clock clks) ++{ ++ if (cpu_is_omap34xx()) { ++ unsigned num_clks = count_clk_bits(clks); ++ ++ BUG_ON(dss.num_clks_enabled < num_clks); ++ ++ if (dss.num_clks_enabled == num_clks) ++ save_all_ctx(); ++ } ++ ++ dss_clk_disable_no_ctx(clks); ++} ++ ++static void dss_clk_enable_all_no_ctx(void) ++{ ++ enum dss_clock clks; ++ ++ clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; ++ if (cpu_is_omap34xx()) ++ clks |= DSS_CLK_VIDFCK; ++ dss_clk_enable_no_ctx(clks); ++} ++ ++static void dss_clk_disable_all_no_ctx(void) ++{ ++ enum dss_clock clks; ++ ++ clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; ++ if (cpu_is_omap34xx()) ++ clks |= DSS_CLK_VIDFCK; ++ dss_clk_disable_no_ctx(clks); ++} ++ ++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) ++/* CLOCKS */ ++static void core_dump_clocks(struct seq_file *s) ++{ ++ int i; ++ struct clk *clocks[5] = { ++ dss.dss_ick, ++ dss.dss_fck, ++ dss.dss_sys_clk, ++ dss.dss_tv_fck, ++ dss.dss_video_fck ++ }; ++ ++ seq_printf(s, "- CORE -\n"); ++ ++ seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled); ++ ++ for (i = 0; i < 5; i++) { ++ if (!clocks[i]) ++ continue; ++ seq_printf(s, "%-15s\t%lu\t%d\n", ++ clocks[i]->name, ++ clk_get_rate(clocks[i]), ++ clocks[i]->usecount); ++ } ++} ++#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ ++ ++/* DEBUGFS */ ++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) ++void dss_debug_dump_clocks(struct seq_file *s) ++{ ++ core_dump_clocks(s); ++ dss_dump_clocks(s); ++ dispc_dump_clocks(s); ++#ifdef CONFIG_OMAP2_DSS_DSI ++ dsi_dump_clocks(s); ++#endif ++} ++#endif ++ ++ ++/* DSS HW IP initialisation */ ++static int omap_dsshw_probe(struct platform_device *pdev) ++{ ++ int r; ++ ++ dss.pdev = pdev; ++ ++ r = dss_get_clocks(); ++ if (r) ++ goto err_clocks; ++ ++ dss_clk_enable_all_no_ctx(); ++ ++ dss.ctx_id = dss_get_ctx_id(); ++ DSSDBG("initial ctx id %u\n", dss.ctx_id); ++ ++ r = dss_init(); ++ if (r) { ++ DSSERR("Failed to initialize DSS\n"); ++ goto err_dss; ++ } ++ ++ r = dpi_init(); ++ if (r) { ++ DSSERR("Failed to initialize DPI\n"); ++ goto err_dpi; ++ } ++ ++ r = sdi_init(); ++ if (r) { ++ DSSERR("Failed to initialize SDI\n"); ++ goto err_sdi; ++ } ++ ++ dss_clk_disable_all_no_ctx(); ++ return 0; ++err_sdi: ++ dpi_exit(); ++err_dpi: ++ dss_exit(); ++err_dss: ++ dss_clk_disable_all_no_ctx(); ++ dss_put_clocks(); ++err_clocks: ++ return r; ++} ++ ++static int omap_dsshw_remove(struct platform_device *pdev) ++{ ++ ++ dss_exit(); ++ ++ /* ++ * As part of hwmod changes, DSS is not the only controller of dss ++ * clocks; hwmod framework itself will also enable clocks during hwmod ++ * init for dss, and autoidle is set in h/w for DSS. Hence, there's no ++ * need to disable clocks if their usecounts > 1. ++ */ ++ WARN_ON(dss.num_clks_enabled > 0); ++ ++ dss_put_clocks(); ++ return 0; ++} ++ ++static struct platform_driver omap_dsshw_driver = { ++ .probe = omap_dsshw_probe, ++ .remove = omap_dsshw_remove, ++ .driver = { ++ .name = "omapdss_dss", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int dss_init_platform_driver(void) ++{ ++ return platform_driver_register(&omap_dsshw_driver); ++} ++ ++void dss_uninit_platform_driver(void) ++{ ++ return platform_driver_unregister(&omap_dsshw_driver); ++} +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.c 2011-03-09 13:19:21.085278903 +0100 +@@ -25,6 +25,7 @@ + #include + #include + ++#include "dss.h" + #include "dss_features.h" + + /* Defines a generic omap register field */ +@@ -41,8 +42,10 @@ + + const int num_mgrs; + const int num_ovls; ++ const unsigned long max_dss_fck; + const enum omap_display_type *supported_displays; + const enum omap_color_mode *supported_color_modes; ++ const struct dss_clk_source_name *clksrc_names; + }; + + /* This struct is assigned to one of the below during initialization */ +@@ -54,6 +57,9 @@ + { FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 }, + { FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 }, + { FEAT_REG_FIFOSIZE, 8, 0 }, ++ { FEAT_REG_HORIZONTALACCU, 9, 0 }, ++ { FEAT_REG_VERTICALACCU, 25, 16 }, ++ { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, + }; + + static const struct dss_reg_field omap3_dss_reg_fields[] = { +@@ -62,10 +68,32 @@ + { FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 }, + { FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 }, + { FEAT_REG_FIFOSIZE, 10, 0 }, ++ { FEAT_REG_HORIZONTALACCU, 9, 0 }, ++ { FEAT_REG_VERTICALACCU, 25, 16 }, ++ { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, ++}; ++ ++static const struct dss_reg_field omap4_dss_reg_fields[] = { ++ { FEAT_REG_FIRHINC, 12, 0 }, ++ { FEAT_REG_FIRVINC, 28, 16 }, ++ { FEAT_REG_FIFOLOWTHRESHOLD, 15, 0 }, ++ { FEAT_REG_FIFOHIGHTHRESHOLD, 31, 16 }, ++ { FEAT_REG_FIFOSIZE, 15, 0 }, ++ { FEAT_REG_HORIZONTALACCU, 10, 0 }, ++ { FEAT_REG_VERTICALACCU, 26, 16 }, ++ { FEAT_REG_DISPC_CLK_SWITCH, 9, 8 }, + }; + + static const enum omap_display_type omap2_dss_supported_displays[] = { + /* OMAP_DSS_CHANNEL_LCD */ ++ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI, ++ ++ /* OMAP_DSS_CHANNEL_DIGIT */ ++ OMAP_DISPLAY_TYPE_VENC, ++}; ++ ++static const enum omap_display_type omap3430_dss_supported_displays[] = { ++ /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | + OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, + +@@ -73,10 +101,10 @@ + OMAP_DISPLAY_TYPE_VENC, + }; + +-static const enum omap_display_type omap3_dss_supported_displays[] = { ++static const enum omap_display_type omap3630_dss_supported_displays[] = { + /* OMAP_DSS_CHANNEL_LCD */ + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | +- OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, ++ OMAP_DISPLAY_TYPE_DSI, + + /* OMAP_DSS_CHANNEL_DIGIT */ + OMAP_DISPLAY_TYPE_VENC, +@@ -134,6 +162,24 @@ + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, + }; + ++static const struct dss_clk_source_name omap2_dss_clk_source_names[] = { ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" }, ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" }, ++ { DSS_CLK_SRC_FCK, "DSS_FCLK1" }, ++}; ++ ++static const struct dss_clk_source_name omap3_dss_clk_source_names[] = { ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" }, ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" }, ++ { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" }, ++}; ++ ++static const struct dss_clk_source_name omap4_dss_clk_source_names[] = { ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "PLL1_CLK1" }, ++ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "PLL1_CLK2" }, ++ { DSS_CLK_SRC_FCK, "DSS_FCLK" }, ++}; ++ + /* OMAP2 DSS Features */ + static struct omap_dss_features omap2_dss_features = { + .reg_fields = omap2_dss_reg_fields, +@@ -141,12 +187,15 @@ + + .has_feature = + FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | +- FEAT_PCKFREEENABLE | FEAT_FUNCGATED, ++ FEAT_PCKFREEENABLE | FEAT_FUNCGATED | ++ FEAT_ROWREPEATENABLE | FEAT_RESIZECONF, + + .num_mgrs = 2, + .num_ovls = 3, ++ .max_dss_fck = 173000000, + .supported_displays = omap2_dss_supported_displays, + .supported_color_modes = omap2_dss_supported_color_modes, ++ .clksrc_names = omap2_dss_clk_source_names, + }; + + /* OMAP3 DSS Features */ +@@ -157,12 +206,15 @@ + .has_feature = + FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | + FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | +- FEAT_FUNCGATED, ++ FEAT_FUNCGATED | FEAT_ROWREPEATENABLE | ++ FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF, + + .num_mgrs = 2, + .num_ovls = 3, +- .supported_displays = omap3_dss_supported_displays, ++ .max_dss_fck = 173000000, ++ .supported_displays = omap3430_dss_supported_displays, + .supported_color_modes = omap3_dss_supported_color_modes, ++ .clksrc_names = omap3_dss_clk_source_names, + }; + + static struct omap_dss_features omap3630_dss_features = { +@@ -172,27 +224,34 @@ + .has_feature = + FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | + FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | +- FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED, ++ FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED | ++ FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT | ++ FEAT_RESIZECONF, + + .num_mgrs = 2, + .num_ovls = 3, +- .supported_displays = omap3_dss_supported_displays, ++ .max_dss_fck = 173000000, ++ .supported_displays = omap3630_dss_supported_displays, + .supported_color_modes = omap3_dss_supported_color_modes, ++ .clksrc_names = omap3_dss_clk_source_names, + }; + + /* OMAP4 DSS Features */ + static struct omap_dss_features omap4_dss_features = { +- .reg_fields = omap3_dss_reg_fields, +- .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), ++ .reg_fields = omap4_dss_reg_fields, ++ .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), + + .has_feature = + FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA | +- FEAT_MGR_LCD2, ++ FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 | ++ FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC, + + .num_mgrs = 3, + .num_ovls = 3, ++ .max_dss_fck = 186000000, + .supported_displays = omap4_dss_supported_displays, + .supported_color_modes = omap3_dss_supported_color_modes, ++ .clksrc_names = omap4_dss_clk_source_names, + }; + + /* Functions returning values related to a DSS feature */ +@@ -206,6 +265,12 @@ + return omap_current_dss_features->num_ovls; + } + ++/* Max supported DSS FCK in Hz */ ++unsigned long dss_feat_get_max_dss_fck(void) ++{ ++ return omap_current_dss_features->max_dss_fck; ++} ++ + enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel) + { + return omap_current_dss_features->supported_displays[channel]; +@@ -223,6 +288,11 @@ + color_mode; + } + ++const char *dss_feat_get_clk_source_name(enum dss_clk_source id) ++{ ++ return omap_current_dss_features->clksrc_names[id].clksrc_name; ++} ++ + /* DSS has_feature check */ + bool dss_has_feature(enum dss_feat_id id) + { +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.h linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.h +--- linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.h 2011-03-09 13:19:21.085278903 +0100 +@@ -22,6 +22,7 @@ + + #define MAX_DSS_MANAGERS 3 + #define MAX_DSS_OVERLAYS 3 ++#define MAX_DSS_LCD_MANAGERS 2 + + /* DSS has feature id */ + enum dss_feat_id { +@@ -33,6 +34,12 @@ + FEAT_PCKFREEENABLE = 1 << 5, + FEAT_FUNCGATED = 1 << 6, + FEAT_MGR_LCD2 = 1 << 7, ++ FEAT_LINEBUFFERSPLIT = 1 << 8, ++ FEAT_ROWREPEATENABLE = 1 << 9, ++ FEAT_RESIZECONF = 1 << 10, ++ /* Independent core clk divider */ ++ FEAT_CORE_CLK_DIV = 1 << 11, ++ FEAT_LCD_CLK_SRC = 1 << 12, + }; + + /* DSS register field id */ +@@ -42,15 +49,20 @@ + FEAT_REG_FIFOHIGHTHRESHOLD, + FEAT_REG_FIFOLOWTHRESHOLD, + FEAT_REG_FIFOSIZE, ++ FEAT_REG_HORIZONTALACCU, ++ FEAT_REG_VERTICALACCU, ++ FEAT_REG_DISPC_CLK_SWITCH, + }; + + /* DSS Feature Functions */ + int dss_feat_get_num_mgrs(void); + int dss_feat_get_num_ovls(void); ++unsigned long dss_feat_get_max_dss_fck(void); + enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); + enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); + bool dss_feat_color_mode_supported(enum omap_plane plane, + enum omap_color_mode color_mode); ++const char *dss_feat_get_clk_source_name(enum dss_clk_source id); + + bool dss_has_feature(enum dss_feat_id id); + void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss.h linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.h +--- linux-2.6.38-rc7/drivers/video/omap2/dss/dss.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.h 2011-03-09 13:19:21.085278903 +0100 +@@ -97,8 +97,6 @@ + #define FLD_MOD(orig, val, start, end) \ + (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) + +-#define DISPC_MAX_FCK 173000000 +- + enum omap_burst_size { + OMAP_DSS_BURST_4x32 = 0, + OMAP_DSS_BURST_8x32 = 1, +@@ -112,17 +110,26 @@ + }; + + enum dss_clock { +- DSS_CLK_ICK = 1 << 0, +- DSS_CLK_FCK1 = 1 << 1, +- DSS_CLK_FCK2 = 1 << 2, +- DSS_CLK_54M = 1 << 3, +- DSS_CLK_96M = 1 << 4, ++ DSS_CLK_ICK = 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */ ++ DSS_CLK_FCK = 1 << 1, /* DSS1_ALWON_FCLK */ ++ DSS_CLK_SYSCK = 1 << 2, /* DSS2_ALWON_FCLK */ ++ DSS_CLK_TVFCK = 1 << 3, /* DSS_TV_FCLK */ ++ DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/ + }; + + enum dss_clk_source { +- DSS_SRC_DSI1_PLL_FCLK, +- DSS_SRC_DSI2_PLL_FCLK, +- DSS_SRC_DSS1_ALWON_FCLK, ++ DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK ++ * OMAP4: PLL1_CLK1 */ ++ DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK ++ * OMAP4: PLL1_CLK2 */ ++ DSS_CLK_SRC_FCK, /* OMAP2/3: DSS1_ALWON_FCLK ++ * OMAP4: DSS_FCLK */ ++}; ++ ++/* Correlates clock source name and dss_clk_source member */ ++struct dss_clk_source_name { ++ enum dss_clk_source clksrc; ++ const char *clksrc_name; + }; + + struct dss_clock_info { +@@ -148,36 +155,32 @@ + unsigned long fint; + unsigned long clkin4ddr; + unsigned long clkin; +- unsigned long dsi1_pll_fclk; +- unsigned long dsi2_pll_fclk; +- ++ unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK ++ * OMAP4: PLLx_CLK1 */ ++ unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK ++ * OMAP4: PLLx_CLK2 */ + unsigned long lp_clk; + + /* dividers */ + u16 regn; + u16 regm; +- u16 regm3; +- u16 regm4; +- ++ u16 regm_dispc; /* OMAP3: REGM3 ++ * OMAP4: REGM4 */ ++ u16 regm_dsi; /* OMAP3: REGM4 ++ * OMAP4: REGM5 */ + u16 lp_clk_div; + + u8 highfreq; +- bool use_dss2_fck; ++ bool use_sys_clk; + }; + + struct seq_file; + struct platform_device; + + /* core */ +-void dss_clk_enable(enum dss_clock clks); +-void dss_clk_disable(enum dss_clock clks); +-unsigned long dss_clk_get_rate(enum dss_clock clk); +-int dss_need_ctx_restore(void); +-void dss_dump_clocks(struct seq_file *s); + struct bus_type *dss_get_bus(void); + struct regulator *dss_get_vdds_dsi(void); + struct regulator *dss_get_vdds_sdi(void); +-struct regulator *dss_get_vdda_dac(void); + + /* display */ + int dss_suspend_all_devices(void); +@@ -214,13 +217,22 @@ + void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); + + /* DSS */ +-int dss_init(bool skip_init); +-void dss_exit(void); ++int dss_init_platform_driver(void); ++void dss_uninit_platform_driver(void); + + void dss_save_context(void); + void dss_restore_context(void); ++void dss_clk_enable(enum dss_clock clks); ++void dss_clk_disable(enum dss_clock clks); ++unsigned long dss_clk_get_rate(enum dss_clock clk); ++int dss_need_ctx_restore(void); ++const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src); ++void dss_dump_clocks(struct seq_file *s); + + void dss_dump_regs(struct seq_file *s); ++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) ++void dss_debug_dump_clocks(struct seq_file *s); ++#endif + + void dss_sdi_init(u8 datapairs); + int dss_sdi_enable(void); +@@ -228,8 +240,11 @@ + + void dss_select_dispc_clk_source(enum dss_clk_source clk_src); + void dss_select_dsi_clk_source(enum dss_clk_source clk_src); ++void dss_select_lcd_clk_source(enum omap_channel channel, ++ enum dss_clk_source clk_src); + enum dss_clk_source dss_get_dispc_clk_source(void); + enum dss_clk_source dss_get_dsi_clk_source(void); ++enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); + + void dss_set_venc_output(enum omap_dss_venc_type type); + void dss_set_dac_pwrdn_bgz(bool enable); +@@ -244,11 +259,11 @@ + + /* SDI */ + #ifdef CONFIG_OMAP2_DSS_SDI +-int sdi_init(bool skip_init); ++int sdi_init(void); + void sdi_exit(void); + int sdi_init_display(struct omap_dss_device *display); + #else +-static inline int sdi_init(bool skip_init) ++static inline int sdi_init(void) + { + return 0; + } +@@ -259,8 +274,8 @@ + + /* DSI */ + #ifdef CONFIG_OMAP2_DSS_DSI +-int dsi_init(struct platform_device *pdev); +-void dsi_exit(void); ++int dsi_init_platform_driver(void); ++void dsi_uninit_platform_driver(void); + + void dsi_dump_clocks(struct seq_file *s); + void dsi_dump_irqs(struct seq_file *s); +@@ -271,7 +286,7 @@ + + int dsi_init_display(struct omap_dss_device *display); + void dsi_irq_handler(void); +-unsigned long dsi_get_dsi1_pll_rate(void); ++unsigned long dsi_get_pll_hsdiv_dispc_rate(void); + int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo); + int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, + struct dsi_clock_info *cinfo, +@@ -282,31 +297,36 @@ + void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, + u32 fifo_size, enum omap_burst_size *burst_size, + u32 *fifo_low, u32 *fifo_high); +-void dsi_wait_dsi1_pll_active(void); +-void dsi_wait_dsi2_pll_active(void); ++void dsi_wait_pll_hsdiv_dispc_active(void); ++void dsi_wait_pll_hsdiv_dsi_active(void); + #else +-static inline int dsi_init(struct platform_device *pdev) ++static inline int dsi_init_platform_driver(void) + { + return 0; + } +-static inline void dsi_exit(void) ++static inline void dsi_uninit_platform_driver(void) ++{ ++} ++static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(void) + { ++ WARN("%s: DSI not compiled in, returning rate as 0\n", __func__); ++ return 0; + } +-static inline void dsi_wait_dsi1_pll_active(void) ++static inline void dsi_wait_pll_hsdiv_dispc_active(void) + { + } +-static inline void dsi_wait_dsi2_pll_active(void) ++static inline void dsi_wait_pll_hsdiv_dsi_active(void) + { + } + #endif + + /* DPI */ + #ifdef CONFIG_OMAP2_DSS_DPI +-int dpi_init(struct platform_device *pdev); ++int dpi_init(void); + void dpi_exit(void); + int dpi_init_display(struct omap_dss_device *dssdev); + #else +-static inline int dpi_init(struct platform_device *pdev) ++static inline int dpi_init(void) + { + return 0; + } +@@ -316,8 +336,8 @@ + #endif + + /* DISPC */ +-int dispc_init(void); +-void dispc_exit(void); ++int dispc_init_platform_driver(void); ++void dispc_uninit_platform_driver(void); + void dispc_dump_clocks(struct seq_file *s); + void dispc_dump_irqs(struct seq_file *s); + void dispc_dump_regs(struct seq_file *s); +@@ -409,24 +429,24 @@ + + /* VENC */ + #ifdef CONFIG_OMAP2_DSS_VENC +-int venc_init(struct platform_device *pdev); +-void venc_exit(void); ++int venc_init_platform_driver(void); ++void venc_uninit_platform_driver(void); + void venc_dump_regs(struct seq_file *s); + int venc_init_display(struct omap_dss_device *display); + #else +-static inline int venc_init(struct platform_device *pdev) ++static inline int venc_init_platform_driver(void) + { + return 0; + } +-static inline void venc_exit(void) ++static inline void venc_uninit_platform_driver(void) + { + } + #endif + + /* RFBI */ + #ifdef CONFIG_OMAP2_DSS_RFBI +-int rfbi_init(void); +-void rfbi_exit(void); ++int rfbi_init_platform_driver(void); ++void rfbi_uninit_platform_driver(void); + void rfbi_dump_regs(struct seq_file *s); + + int rfbi_configure(int rfbi_module, int bpp, int lines); +@@ -437,11 +457,11 @@ + unsigned long rfbi_get_max_tx_rate(void); + int rfbi_init_display(struct omap_dss_device *display); + #else +-static inline int rfbi_init(void) ++static inline int rfbi_init_platform_driver(void) + { + return 0; + } +-static inline void rfbi_exit(void) ++static inline void rfbi_uninit_platform_driver(void) + { + } + #endif +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/Kconfig +--- linux-2.6.38-rc7/drivers/video/omap2/dss/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/Kconfig 2011-03-09 13:19:21.081278983 +0100 +@@ -1,8 +1,8 @@ + menuconfig OMAP2_DSS +- tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)" +- depends on ARCH_OMAP2 || ARCH_OMAP3 ++ tristate "OMAP2+ Display Subsystem support (EXPERIMENTAL)" ++ depends on ARCH_OMAP2PLUS + help +- OMAP2/3 Display Subsystem support. ++ OMAP2+ Display Subsystem support. + + if OMAP2_DSS + +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/manager.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/manager.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/manager.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/manager.c 2011-03-09 13:19:21.086278883 +0100 +@@ -1394,7 +1394,7 @@ + } + + r = 0; +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + if (!dss_cache.irq_enabled) { + u32 mask; + +@@ -1407,7 +1407,7 @@ + dss_cache.irq_enabled = true; + } + configure_dispc(); +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + + spin_unlock_irqrestore(&dss_cache.lock, flags); + +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/overlay.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/overlay.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/overlay.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/overlay.c 2011-03-09 13:19:21.086278883 +0100 +@@ -490,7 +490,7 @@ + + ovl->manager = mgr; + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + /* XXX: on manual update display, in auto update mode, a bug happens + * here. When an overlay is first enabled on LCD, then it's disabled, + * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT +@@ -499,7 +499,7 @@ + * but I don't understand how or why. */ + msleep(40); + dispc_set_channel_out(ovl->id, mgr->id); +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + + return 0; + } +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/rfbi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/rfbi.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/rfbi.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/rfbi.c 2011-03-09 13:19:21.086278883 +0100 +@@ -36,8 +36,6 @@ + #include + #include "dss.h" + +-#define RFBI_BASE 0x48050800 +- + struct rfbi_reg { u16 idx; }; + + #define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) +@@ -100,6 +98,7 @@ + static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); + + static struct { ++ struct platform_device *pdev; + void __iomem *base; + + unsigned long l4_khz; +@@ -142,9 +141,9 @@ + static void rfbi_enable_clocks(bool enable) + { + if (enable) +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + else +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + } + + void omap_rfbi_write_command(const void *buf, u32 len) +@@ -497,7 +496,7 @@ + }; + + l4_rate = rfbi.l4_khz / 1000; +- dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000; ++ dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000; + + for (i = 0; i < ARRAY_SIZE(ftab); i++) { + /* Use a window instead of an exact match, to account +@@ -922,7 +921,7 @@ + { + #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) + +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + DUMPREG(RFBI_REVISION); + DUMPREG(RFBI_SYSCONFIG); +@@ -953,54 +952,10 @@ + DUMPREG(RFBI_VSYNC_WIDTH); + DUMPREG(RFBI_HSYNC_WIDTH); + +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + #undef DUMPREG + } + +-int rfbi_init(void) +-{ +- u32 rev; +- u32 l; +- +- spin_lock_init(&rfbi.cmd_lock); +- +- init_completion(&rfbi.cmd_done); +- atomic_set(&rfbi.cmd_fifo_full, 0); +- atomic_set(&rfbi.cmd_pending, 0); +- +- rfbi.base = ioremap(RFBI_BASE, SZ_256); +- if (!rfbi.base) { +- DSSERR("can't ioremap RFBI\n"); +- return -ENOMEM; +- } +- +- rfbi_enable_clocks(1); +- +- msleep(10); +- +- rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; +- +- /* Enable autoidle and smart-idle */ +- l = rfbi_read_reg(RFBI_SYSCONFIG); +- l |= (1 << 0) | (2 << 3); +- rfbi_write_reg(RFBI_SYSCONFIG, l); +- +- rev = rfbi_read_reg(RFBI_REVISION); +- printk(KERN_INFO "OMAP RFBI rev %d.%d\n", +- FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); +- +- rfbi_enable_clocks(0); +- +- return 0; +-} +- +-void rfbi_exit(void) +-{ +- DSSDBG("rfbi_exit\n"); +- +- iounmap(rfbi.base); +-} +- + int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev) + { + int r; +@@ -1056,3 +1011,74 @@ + dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; + return 0; + } ++ ++/* RFBI HW IP initialisation */ ++static int omap_rfbihw_probe(struct platform_device *pdev) ++{ ++ u32 rev; ++ u32 l; ++ struct resource *rfbi_mem; ++ ++ rfbi.pdev = pdev; ++ ++ spin_lock_init(&rfbi.cmd_lock); ++ ++ init_completion(&rfbi.cmd_done); ++ atomic_set(&rfbi.cmd_fifo_full, 0); ++ atomic_set(&rfbi.cmd_pending, 0); ++ ++ rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0); ++ if (!rfbi_mem) { ++ DSSERR("can't get IORESOURCE_MEM RFBI\n"); ++ return -EINVAL; ++ } ++ rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem)); ++ if (!rfbi.base) { ++ DSSERR("can't ioremap RFBI\n"); ++ return -ENOMEM; ++ } ++ ++ rfbi_enable_clocks(1); ++ ++ msleep(10); ++ ++ rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; ++ ++ /* Enable autoidle and smart-idle */ ++ l = rfbi_read_reg(RFBI_SYSCONFIG); ++ l |= (1 << 0) | (2 << 3); ++ rfbi_write_reg(RFBI_SYSCONFIG, l); ++ ++ rev = rfbi_read_reg(RFBI_REVISION); ++ dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n", ++ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); ++ ++ rfbi_enable_clocks(0); ++ ++ return 0; ++} ++ ++static int omap_rfbihw_remove(struct platform_device *pdev) ++{ ++ iounmap(rfbi.base); ++ return 0; ++} ++ ++static struct platform_driver omap_rfbihw_driver = { ++ .probe = omap_rfbihw_probe, ++ .remove = omap_rfbihw_remove, ++ .driver = { ++ .name = "omapdss_rfbi", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int rfbi_init_platform_driver(void) ++{ ++ return platform_driver_register(&omap_rfbihw_driver); ++} ++ ++void rfbi_uninit_platform_driver(void) ++{ ++ return platform_driver_unregister(&omap_rfbihw_driver); ++} +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/sdi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/sdi.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/sdi.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/sdi.c 2011-03-09 13:19:21.086278883 +0100 +@@ -30,7 +30,6 @@ + #include "dss.h" + + static struct { +- bool skip_init; + bool update_enabled; + struct regulator *vdds_sdi_reg; + } sdi; +@@ -68,9 +67,7 @@ + if (r) + goto err1; + +- /* In case of skip_init sdi_init has already enabled the clocks */ +- if (!sdi.skip_init) +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); + + sdi_basic_init(dssdev); + +@@ -80,14 +77,8 @@ + dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, + dssdev->panel.acbi, dssdev->panel.acb); + +- if (!sdi.skip_init) { +- r = dss_calc_clock_div(1, t->pixel_clock * 1000, +- &dss_cinfo, &dispc_cinfo); +- } else { +- r = dss_get_clock_div(&dss_cinfo); +- r = dispc_get_clock_div(dssdev->manager->id, &dispc_cinfo); +- } +- ++ r = dss_calc_clock_div(1, t->pixel_clock * 1000, ++ &dss_cinfo, &dispc_cinfo); + if (r) + goto err2; + +@@ -116,21 +107,17 @@ + if (r) + goto err2; + +- if (!sdi.skip_init) { +- dss_sdi_init(dssdev->phy.sdi.datapairs); +- r = dss_sdi_enable(); +- if (r) +- goto err1; +- mdelay(2); +- } ++ dss_sdi_init(dssdev->phy.sdi.datapairs); ++ r = dss_sdi_enable(); ++ if (r) ++ goto err1; ++ mdelay(2); + + dssdev->manager->enable(dssdev->manager); + +- sdi.skip_init = 0; +- + return 0; + err2: +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + regulator_disable(sdi.vdds_sdi_reg); + err1: + omap_dss_stop_device(dssdev); +@@ -145,7 +132,7 @@ + + dss_sdi_disable(); + +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); + + regulator_disable(sdi.vdds_sdi_reg); + +@@ -157,25 +144,24 @@ + { + DSSDBG("SDI init\n"); + ++ if (sdi.vdds_sdi_reg == NULL) { ++ struct regulator *vdds_sdi; ++ ++ vdds_sdi = dss_get_vdds_sdi(); ++ ++ if (IS_ERR(vdds_sdi)) { ++ DSSERR("can't get VDDS_SDI regulator\n"); ++ return PTR_ERR(vdds_sdi); ++ } ++ ++ sdi.vdds_sdi_reg = vdds_sdi; ++ } ++ + return 0; + } + +-int sdi_init(bool skip_init) ++int sdi_init(void) + { +- /* we store this for first display enable, then clear it */ +- sdi.skip_init = skip_init; +- +- sdi.vdds_sdi_reg = dss_get_vdds_sdi(); +- if (IS_ERR(sdi.vdds_sdi_reg)) { +- DSSERR("can't get VDDS_SDI regulator\n"); +- return PTR_ERR(sdi.vdds_sdi_reg); +- } +- /* +- * Enable clocks already here, otherwise there would be a toggle +- * of them until sdi_display_enable is called. +- */ +- if (skip_init) +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); + return 0; + } + +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/venc.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/venc.c +--- linux-2.6.38-rc7/drivers/video/omap2/dss/venc.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/venc.c 2011-03-09 13:19:21.087278863 +0100 +@@ -39,8 +39,6 @@ + + #include "dss.h" + +-#define VENC_BASE 0x48050C00 +- + /* Venc registers */ + #define VENC_REV_ID 0x00 + #define VENC_STATUS 0x04 +@@ -289,6 +287,7 @@ + EXPORT_SYMBOL(omap_dss_ntsc_timings); + + static struct { ++ struct platform_device *pdev; + void __iomem *base; + struct mutex venc_lock; + u32 wss_data; +@@ -381,11 +380,11 @@ + static void venc_enable_clocks(int enable) + { + if (enable) +- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | +- DSS_CLK_96M); ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK | ++ DSS_CLK_VIDFCK); + else +- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | +- DSS_CLK_96M); ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK | ++ DSS_CLK_VIDFCK); + } + + static const struct venc_config *venc_timings_to_config( +@@ -641,50 +640,23 @@ + }; + /* driver end */ + +- +- +-int venc_init(struct platform_device *pdev) ++int venc_init_display(struct omap_dss_device *dssdev) + { +- u8 rev_id; ++ DSSDBG("init_display\n"); + +- mutex_init(&venc.venc_lock); ++ if (venc.vdda_dac_reg == NULL) { ++ struct regulator *vdda_dac; + +- venc.wss_data = 0; ++ vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac"); + +- venc.base = ioremap(VENC_BASE, SZ_1K); +- if (!venc.base) { +- DSSERR("can't ioremap VENC\n"); +- return -ENOMEM; +- } ++ if (IS_ERR(vdda_dac)) { ++ DSSERR("can't get VDDA_DAC regulator\n"); ++ return PTR_ERR(vdda_dac); ++ } + +- venc.vdda_dac_reg = dss_get_vdda_dac(); +- if (IS_ERR(venc.vdda_dac_reg)) { +- iounmap(venc.base); +- DSSERR("can't get VDDA_DAC regulator\n"); +- return PTR_ERR(venc.vdda_dac_reg); ++ venc.vdda_dac_reg = vdda_dac; + } + +- venc_enable_clocks(1); +- +- rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); +- printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); +- +- venc_enable_clocks(0); +- +- return omap_dss_register_driver(&venc_driver); +-} +- +-void venc_exit(void) +-{ +- omap_dss_unregister_driver(&venc_driver); +- +- iounmap(venc.base); +-} +- +-int venc_init_display(struct omap_dss_device *dssdev) +-{ +- DSSDBG("init_display\n"); +- + return 0; + } + +@@ -740,3 +712,67 @@ + + #undef DUMPREG + } ++ ++/* VENC HW IP initialisation */ ++static int omap_venchw_probe(struct platform_device *pdev) ++{ ++ u8 rev_id; ++ struct resource *venc_mem; ++ ++ venc.pdev = pdev; ++ ++ mutex_init(&venc.venc_lock); ++ ++ venc.wss_data = 0; ++ ++ venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); ++ if (!venc_mem) { ++ DSSERR("can't get IORESOURCE_MEM VENC\n"); ++ return -EINVAL; ++ } ++ venc.base = ioremap(venc_mem->start, resource_size(venc_mem)); ++ if (!venc.base) { ++ DSSERR("can't ioremap VENC\n"); ++ return -ENOMEM; ++ } ++ ++ venc_enable_clocks(1); ++ ++ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); ++ dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); ++ ++ venc_enable_clocks(0); ++ ++ return omap_dss_register_driver(&venc_driver); ++} ++ ++static int omap_venchw_remove(struct platform_device *pdev) ++{ ++ if (venc.vdda_dac_reg != NULL) { ++ regulator_put(venc.vdda_dac_reg); ++ venc.vdda_dac_reg = NULL; ++ } ++ omap_dss_unregister_driver(&venc_driver); ++ ++ iounmap(venc.base); ++ return 0; ++} ++ ++static struct platform_driver omap_venchw_driver = { ++ .probe = omap_venchw_probe, ++ .remove = omap_venchw_remove, ++ .driver = { ++ .name = "omapdss_venc", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int venc_init_platform_driver(void) ++{ ++ return platform_driver_register(&omap_venchw_driver); ++} ++ ++void venc_uninit_platform_driver(void) ++{ ++ return platform_driver_unregister(&omap_venchw_driver); ++} +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/omapfb/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/Kconfig +--- linux-2.6.38-rc7/drivers/video/omap2/omapfb/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/Kconfig 2011-03-09 13:19:21.087278863 +0100 +@@ -1,5 +1,5 @@ + menuconfig FB_OMAP2 +- tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)" ++ tristate "OMAP2+ frame buffer support (EXPERIMENTAL)" + depends on FB && OMAP2_DSS + + select OMAP2_VRAM +@@ -8,10 +8,10 @@ + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help +- Frame buffer driver for OMAP2/3 based boards. ++ Frame buffer driver for OMAP2+ based boards. + + config FB_OMAP2_DEBUG_SUPPORT +- bool "Debug support for OMAP2/3 FB" ++ bool "Debug support for OMAP2+ FB" + default y + depends on FB_OMAP2 + help +diff -Naur linux-2.6.38-rc7/drivers/video/omap2/omapfb/omapfb-main.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/omapfb-main.c +--- linux-2.6.38-rc7/drivers/video/omap2/omapfb/omapfb-main.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/omapfb-main.c 2011-03-09 13:19:21.088278842 +0100 +@@ -2090,7 +2090,7 @@ + { + int r; + u8 bpp; +- struct omap_video_timings timings; ++ struct omap_video_timings timings, temp_timings; + + r = omapfb_mode_to_timings(mode_str, &timings, &bpp); + if (r) +@@ -2100,14 +2100,23 @@ + fbdev->bpp_overrides[fbdev->num_bpp_overrides].bpp = bpp; + ++fbdev->num_bpp_overrides; + +- if (!display->driver->check_timings || !display->driver->set_timings) +- return -EINVAL; +- +- r = display->driver->check_timings(display, &timings); +- if (r) +- return r; ++ if (display->driver->check_timings) { ++ r = display->driver->check_timings(display, &timings); ++ if (r) ++ return r; ++ } else { ++ /* If check_timings is not present compare xres and yres */ ++ if (display->driver->get_timings) { ++ display->driver->get_timings(display, &temp_timings); ++ ++ if (temp_timings.x_res != timings.x_res || ++ temp_timings.y_res != timings.y_res) ++ return -EINVAL; ++ } ++ } + +- display->driver->set_timings(display, &timings); ++ if (display->driver->set_timings) ++ display->driver->set_timings(display, &timings); + + return 0; + } +diff -Naur linux-2.6.38-rc7/drivers/w1/masters/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/w1/masters/Kconfig +--- linux-2.6.38-rc7/drivers/w1/masters/Kconfig 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/drivers/w1/masters/Kconfig 2011-03-09 13:19:21.142277747 +0100 +@@ -60,7 +60,7 @@ + + config HDQ_MASTER_OMAP + tristate "OMAP HDQ driver" +- depends on ARCH_OMAP2430 || ARCH_OMAP3 ++ depends on SOC_OMAP2430 || ARCH_OMAP3 + help + Say Y here if you want support for the 1-wire or HDQ Interface + on an OMAP processor. +diff -Naur linux-2.6.38-rc7/include/linux/hwspinlock.h linux-2.6.38-rc7-linux-omap-dss2/include/linux/hwspinlock.h +--- linux-2.6.38-rc7/include/linux/hwspinlock.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/include/linux/hwspinlock.h 2011-03-09 13:19:21.851263363 +0100 +@@ -0,0 +1,292 @@ ++/* ++ * Hardware spinlock public header ++ * ++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com ++ * ++ * Contact: Ohad Ben-Cohen ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __LINUX_HWSPINLOCK_H ++#define __LINUX_HWSPINLOCK_H ++ ++#include ++#include ++ ++/* hwspinlock mode argument */ ++#define HWLOCK_IRQSTATE 0x01 /* Disable interrupts, save state */ ++#define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */ ++ ++struct hwspinlock; ++ ++#if defined(CONFIG_HWSPINLOCK) || defined(CONFIG_HWSPINLOCK_MODULE) ++ ++int hwspin_lock_register(struct hwspinlock *lock); ++struct hwspinlock *hwspin_lock_unregister(unsigned int id); ++struct hwspinlock *hwspin_lock_request(void); ++struct hwspinlock *hwspin_lock_request_specific(unsigned int id); ++int hwspin_lock_free(struct hwspinlock *hwlock); ++int hwspin_lock_get_id(struct hwspinlock *hwlock); ++int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int, ++ unsigned long *); ++int __hwspin_trylock(struct hwspinlock *, int, unsigned long *); ++void __hwspin_unlock(struct hwspinlock *, int, unsigned long *); ++ ++#else /* !CONFIG_HWSPINLOCK */ ++ ++/* ++ * We don't want these functions to fail if CONFIG_HWSPINLOCK is not ++ * enabled. We prefer to silently succeed in this case, and let the ++ * code path get compiled away. This way, if CONFIG_HWSPINLOCK is not ++ * required on a given setup, users will still work. ++ * ++ * The only exception is hwspin_lock_register/hwspin_lock_unregister, with which ++ * we _do_ want users to fail (no point in registering hwspinlock instances if ++ * the framework is not available). ++ * ++ * Note: ERR_PTR(-ENODEV) will still be considered a success for NULL-checking ++ * users. Others, which care, can still check this with IS_ERR. ++ */ ++static inline struct hwspinlock *hwspin_lock_request(void) ++{ ++ return ERR_PTR(-ENODEV); ++} ++ ++static inline struct hwspinlock *hwspin_lock_request_specific(unsigned int id) ++{ ++ return ERR_PTR(-ENODEV); ++} ++ ++static inline int hwspin_lock_free(struct hwspinlock *hwlock) ++{ ++ return 0; ++} ++ ++static inline ++int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to, ++ int mode, unsigned long *flags) ++{ ++ return 0; ++} ++ ++static inline ++int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags) ++{ ++ return 0; ++} ++ ++static inline ++void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags) ++{ ++ return 0; ++} ++ ++static inline int hwspin_lock_get_id(struct hwspinlock *hwlock) ++{ ++ return 0; ++} ++ ++static inline int hwspin_lock_register(struct hwspinlock *hwlock) ++{ ++ return -ENODEV; ++} ++ ++static inline struct hwspinlock *hwspin_lock_unregister(unsigned int id) ++{ ++ return NULL; ++} ++ ++#endif /* !CONFIG_HWSPINLOCK */ ++ ++/** ++ * hwspin_trylock_irqsave() - try to lock an hwspinlock, disable interrupts ++ * @hwlock: an hwspinlock which we want to trylock ++ * @flags: a pointer to where the caller's interrupt state will be saved at ++ * ++ * This function attempts to lock the underlying hwspinlock, and will ++ * immediately fail if the hwspinlock is already locked. ++ * ++ * Upon a successful return from this function, preemption and local ++ * interrupts are disabled (previous interrupts state is saved at @flags), ++ * so the caller must not sleep, and is advised to release the hwspinlock ++ * as soon as possible. ++ * ++ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if ++ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid. ++ */ ++static inline ++int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags) ++{ ++ return __hwspin_trylock(hwlock, HWLOCK_IRQSTATE, flags); ++} ++ ++/** ++ * hwspin_trylock_irq() - try to lock an hwspinlock, disable interrupts ++ * @hwlock: an hwspinlock which we want to trylock ++ * ++ * This function attempts to lock the underlying hwspinlock, and will ++ * immediately fail if the hwspinlock is already locked. ++ * ++ * Upon a successful return from this function, preemption and local ++ * interrupts are disabled, so the caller must not sleep, and is advised ++ * to release the hwspinlock as soon as possible. ++ * ++ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if ++ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid. ++ */ ++static inline int hwspin_trylock_irq(struct hwspinlock *hwlock) ++{ ++ return __hwspin_trylock(hwlock, HWLOCK_IRQ, NULL); ++} ++ ++/** ++ * hwspin_trylock() - attempt to lock a specific hwspinlock ++ * @hwlock: an hwspinlock which we want to trylock ++ * ++ * This function attempts to lock an hwspinlock, and will immediately fail ++ * if the hwspinlock is already taken. ++ * ++ * Upon a successful return from this function, preemption is disabled, ++ * so the caller must not sleep, and is advised to release the hwspinlock ++ * as soon as possible. This is required in order to minimize remote cores ++ * polling on the hardware interconnect. ++ * ++ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if ++ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid. ++ */ ++static inline int hwspin_trylock(struct hwspinlock *hwlock) ++{ ++ return __hwspin_trylock(hwlock, 0, NULL); ++} ++ ++/** ++ * hwspin_lock_timeout_irqsave() - lock hwspinlock, with timeout, disable irqs ++ * @hwlock: the hwspinlock to be locked ++ * @to: timeout value in msecs ++ * @flags: a pointer to where the caller's interrupt state will be saved at ++ * ++ * This function locks the underlying @hwlock. If the @hwlock ++ * is already taken, the function will busy loop waiting for it to ++ * be released, but give up when @timeout msecs have elapsed. ++ * ++ * Upon a successful return from this function, preemption and local interrupts ++ * are disabled (plus previous interrupt state is saved), so the caller must ++ * not sleep, and is advised to release the hwspinlock as soon as possible. ++ * ++ * Returns 0 when the @hwlock was successfully taken, and an appropriate ++ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still ++ * busy after @timeout msecs). The function will never sleep. ++ */ ++static inline int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock, ++ unsigned int to, unsigned long *flags) ++{ ++ return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQSTATE, flags); ++} ++ ++/** ++ * hwspin_lock_timeout_irq() - lock hwspinlock, with timeout, disable irqs ++ * @hwlock: the hwspinlock to be locked ++ * @to: timeout value in msecs ++ * ++ * This function locks the underlying @hwlock. If the @hwlock ++ * is already taken, the function will busy loop waiting for it to ++ * be released, but give up when @timeout msecs have elapsed. ++ * ++ * Upon a successful return from this function, preemption and local interrupts ++ * are disabled so the caller must not sleep, and is advised to release the ++ * hwspinlock as soon as possible. ++ * ++ * Returns 0 when the @hwlock was successfully taken, and an appropriate ++ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still ++ * busy after @timeout msecs). The function will never sleep. ++ */ ++static inline ++int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int to) ++{ ++ return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQ, NULL); ++} ++ ++/** ++ * hwspin_lock_timeout() - lock an hwspinlock with timeout limit ++ * @hwlock: the hwspinlock to be locked ++ * @to: timeout value in msecs ++ * ++ * This function locks the underlying @hwlock. If the @hwlock ++ * is already taken, the function will busy loop waiting for it to ++ * be released, but give up when @timeout msecs have elapsed. ++ * ++ * Upon a successful return from this function, preemption is disabled ++ * so the caller must not sleep, and is advised to release the hwspinlock ++ * as soon as possible. ++ * This is required in order to minimize remote cores polling on the ++ * hardware interconnect. ++ * ++ * Returns 0 when the @hwlock was successfully taken, and an appropriate ++ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still ++ * busy after @timeout msecs). The function will never sleep. ++ */ ++static inline ++int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to) ++{ ++ return __hwspin_lock_timeout(hwlock, to, 0, NULL); ++} ++ ++/** ++ * hwspin_unlock_irqrestore() - unlock hwspinlock, restore irq state ++ * @hwlock: a previously-acquired hwspinlock which we want to unlock ++ * @flags: previous caller's interrupt state to restore ++ * ++ * This function will unlock a specific hwspinlock, enable preemption and ++ * restore the previous state of the local interrupts. It should be used ++ * to undo, e.g., hwspin_trylock_irqsave(). ++ * ++ * @hwlock must be already locked before calling this function: it is a bug ++ * to call unlock on a @hwlock that is already unlocked. ++ */ ++static inline void hwspin_unlock_irqrestore(struct hwspinlock *hwlock, ++ unsigned long *flags) ++{ ++ __hwspin_unlock(hwlock, HWLOCK_IRQSTATE, flags); ++} ++ ++/** ++ * hwspin_unlock_irq() - unlock hwspinlock, enable interrupts ++ * @hwlock: a previously-acquired hwspinlock which we want to unlock ++ * ++ * This function will unlock a specific hwspinlock, enable preemption and ++ * enable local interrupts. Should be used to undo hwspin_lock_irq(). ++ * ++ * @hwlock must be already locked (e.g. by hwspin_trylock_irq()) before ++ * calling this function: it is a bug to call unlock on a @hwlock that is ++ * already unlocked. ++ */ ++static inline void hwspin_unlock_irq(struct hwspinlock *hwlock) ++{ ++ __hwspin_unlock(hwlock, HWLOCK_IRQ, NULL); ++} ++ ++/** ++ * hwspin_unlock() - unlock hwspinlock ++ * @hwlock: a previously-acquired hwspinlock which we want to unlock ++ * ++ * This function will unlock a specific hwspinlock and enable preemption ++ * back. ++ * ++ * @hwlock must be already locked (e.g. by hwspin_trylock()) before calling ++ * this function: it is a bug to call unlock on a @hwlock that is already ++ * unlocked. ++ */ ++static inline void hwspin_unlock(struct hwspinlock *hwlock) ++{ ++ __hwspin_unlock(hwlock, 0, NULL); ++} ++ ++#endif /* __LINUX_HWSPINLOCK_H */ +diff -Naur linux-2.6.38-rc7/include/linux/i2c/twl.h linux-2.6.38-rc7-linux-omap-dss2/include/linux/i2c/twl.h +--- linux-2.6.38-rc7/include/linux/i2c/twl.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/include/linux/i2c/twl.h 2011-03-09 13:19:21.857263241 +0100 +@@ -637,7 +637,6 @@ + extern int twl4030_remove_script(u8 flags); + + struct twl4030_codec_audio_data { +- unsigned int audio_mclk; /* not used, will be removed */ + unsigned int digimic_delay; /* in ms */ + unsigned int ramp_delay_value; + unsigned int offset_cncl_path; +@@ -648,7 +647,6 @@ + }; + + struct twl4030_codec_vibra_data { +- unsigned int audio_mclk; + unsigned int coexist; + }; + +diff -Naur linux-2.6.38-rc7/include/linux/mtd/onenand_regs.h linux-2.6.38-rc7-linux-omap-dss2/include/linux/mtd/onenand_regs.h +--- linux-2.6.38-rc7/include/linux/mtd/onenand_regs.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/include/linux/mtd/onenand_regs.h 2011-03-09 13:19:21.975260847 +0100 +@@ -168,6 +168,7 @@ + #define ONENAND_SYS_CFG1_INT (1 << 6) + #define ONENAND_SYS_CFG1_IOBE (1 << 5) + #define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) ++#define ONENAND_SYS_CFG1_VHF (1 << 3) + #define ONENAND_SYS_CFG1_HF (1 << 2) + #define ONENAND_SYS_CFG1_SYNC_WRITE (1 << 1) + +diff -Naur linux-2.6.38-rc7/MAINTAINERS linux-2.6.38-rc7-linux-omap-dss2/MAINTAINERS +--- linux-2.6.38-rc7/MAINTAINERS 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/MAINTAINERS 2011-03-09 13:19:09.391516121 +0100 +@@ -4504,14 +4504,14 @@ + F: sound/soc/omap/ + + OMAP FRAMEBUFFER SUPPORT +-M: Tomi Valkeinen ++M: Tomi Valkeinen + L: linux-fbdev@vger.kernel.org + L: linux-omap@vger.kernel.org + S: Maintained + F: drivers/video/omap/ + + OMAP DISPLAY SUBSYSTEM and FRAMEBUFFER SUPPORT (DSS2) +-M: Tomi Valkeinen ++M: Tomi Valkeinen + L: linux-omap@vger.kernel.org + L: linux-fbdev@vger.kernel.org + S: Maintained +diff -Naur linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.c +--- linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.c 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.c 2011-03-09 13:19:23.525229402 +0100 +@@ -69,110 +69,6 @@ + */ + static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2]; + +-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) +-static const int omap1_dma_reqs[][2] = { +- { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX }, +- { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX }, +- { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX }, +-}; +-static const unsigned long omap1_mcbsp_port[][2] = { +- { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, +- OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, +- { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, +- OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, +- { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1, +- OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 }, +-}; +-#else +-static const int omap1_dma_reqs[][2] = {}; +-static const unsigned long omap1_mcbsp_port[][2] = {}; +-#endif +- +-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +-static const int omap24xx_dma_reqs[][2] = { +- { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, +- { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) +- { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX }, +- { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX }, +- { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX }, +-#endif +-}; +-#else +-static const int omap24xx_dma_reqs[][2] = {}; +-#endif +- +-#if defined(CONFIG_ARCH_OMAP4) +-static const int omap44xx_dma_reqs[][2] = { +- { OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX }, +- { OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX }, +- { OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX }, +- { OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX }, +-}; +-#else +-static const int omap44xx_dma_reqs[][2] = {}; +-#endif +- +-#if defined(CONFIG_ARCH_OMAP2420) +-static const unsigned long omap2420_mcbsp_port[][2] = { +- { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, +- OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, +- { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, +- OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, +-}; +-#else +-static const unsigned long omap2420_mcbsp_port[][2] = {}; +-#endif +- +-#if defined(CONFIG_ARCH_OMAP2430) +-static const unsigned long omap2430_mcbsp_port[][2] = { +- { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, +- OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, +- OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, +- OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, +- OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, +- OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, +-}; +-#else +-static const unsigned long omap2430_mcbsp_port[][2] = {}; +-#endif +- +-#if defined(CONFIG_ARCH_OMAP3) +-static const unsigned long omap34xx_mcbsp_port[][2] = { +- { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, +- OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, +- OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, +- OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, +- OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, +- OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, +-}; +-#else +-static const unsigned long omap34xx_mcbsp_port[][2] = {}; +-#endif +- +-#if defined(CONFIG_ARCH_OMAP4) +-static const unsigned long omap44xx_mcbsp_port[][2] = { +- { OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, +- OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, +- OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, +- OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, +- { OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, +- OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, +-}; +-#else +-static const unsigned long omap44xx_mcbsp_port[][2] = {}; +-#endif +- + static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) + { + struct snd_soc_pcm_runtime *rtd = substream->private_data; +@@ -346,24 +242,10 @@ + unsigned int format, div, framesize, master; + + dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream]; +- if (cpu_class_is_omap1()) { +- dma = omap1_dma_reqs[bus_id][substream->stream]; +- port = omap1_mcbsp_port[bus_id][substream->stream]; +- } else if (cpu_is_omap2420()) { +- dma = omap24xx_dma_reqs[bus_id][substream->stream]; +- port = omap2420_mcbsp_port[bus_id][substream->stream]; +- } else if (cpu_is_omap2430()) { +- dma = omap24xx_dma_reqs[bus_id][substream->stream]; +- port = omap2430_mcbsp_port[bus_id][substream->stream]; +- } else if (cpu_is_omap343x()) { +- dma = omap24xx_dma_reqs[bus_id][substream->stream]; +- port = omap34xx_mcbsp_port[bus_id][substream->stream]; +- } else if (cpu_is_omap44xx()) { +- dma = omap44xx_dma_reqs[bus_id][substream->stream]; +- port = omap44xx_mcbsp_port[bus_id][substream->stream]; +- } else { +- return -ENODEV; +- } ++ ++ dma = omap_mcbsp_dma_ch_params(bus_id, substream->stream); ++ port = omap_mcbsp_dma_reg_params(bus_id, substream->stream); ++ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + dma_data->data_type = OMAP_DMA_DATA_TYPE_S16; +diff -Naur linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.h linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.h +--- linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.h 2011-03-01 22:55:12.000000000 +0100 ++++ linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.h 2011-03-09 13:19:23.525229402 +0100 +@@ -43,7 +43,7 @@ + OMAP_MCBSP_CLKGDV, /* Sample rate generator divider */ + }; + +-#if defined(CONFIG_ARCH_OMAP2420) ++#if defined(CONFIG_SOC_OMAP2420) + #define NUM_LINKS 2 + #endif + #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) +@@ -54,7 +54,7 @@ + #undef NUM_LINKS + #define NUM_LINKS 4 + #endif +-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) ++#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_OMAP2430) + #undef NUM_LINKS + #define NUM_LINKS 5 + #endif diff --git a/packages/linux/patches/linux-2.6.38-rc8-301-V5_Add_display_type_HDMI_to_DSS2.patch b/packages/linux/patches/linux-2.6.38-rc8-301-V5_Add_display_type_HDMI_to_DSS2.patch new file mode 100644 index 0000000000..4a2b1280e4 --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-301-V5_Add_display_type_HDMI_to_DSS2.patch @@ -0,0 +1,123 @@ +Adding HDMI type in dss_features , overlay and +the manager so that HDMI type of display will be recognized. + +Signed-off-by: Mythri P K +--- + arch/arm/plat-omap/include/plat/display.h | 1 + + drivers/video/omap2/dss/display.c | 2 ++ + drivers/video/omap2/dss/dss_features.c | 2 +- + drivers/video/omap2/dss/manager.c | 9 +++++++-- + drivers/video/omap2/dss/overlay.c | 6 ++++-- + 5 files changed, 15 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h +index e81ca66..5e04ddc 100644 +--- a/arch/arm/plat-omap/include/plat/display.h ++++ b/arch/arm/plat-omap/include/plat/display.h +@@ -58,6 +58,7 @@ enum omap_display_type { + OMAP_DISPLAY_TYPE_SDI = 1 << 2, + OMAP_DISPLAY_TYPE_DSI = 1 << 3, + OMAP_DISPLAY_TYPE_VENC = 1 << 4, ++ OMAP_DISPLAY_TYPE_HDMI = 1 << 5, + }; + + enum omap_plane { +diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c +index 7d96b72..c40bcbd 100644 +--- a/drivers/video/omap2/dss/display.c ++++ b/drivers/video/omap2/dss/display.c +@@ -342,6 +342,7 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev) + return 16; + case OMAP_DISPLAY_TYPE_VENC: + case OMAP_DISPLAY_TYPE_SDI: ++ case OMAP_DISPLAY_TYPE_HDMI: + return 24; + default: + BUG(); +@@ -368,6 +369,7 @@ bool dss_use_replication(struct omap_dss_device *dssdev, + case OMAP_DISPLAY_TYPE_DPI: + bpp = dssdev->phy.dpi.data_lines; + break; ++ case OMAP_DISPLAY_TYPE_HDMI: + case OMAP_DISPLAY_TYPE_VENC: + case OMAP_DISPLAY_TYPE_SDI: + bpp = 24; +diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c +index 6eb6ec6..86dc848 100644 +--- a/drivers/video/omap2/dss/dss_features.c ++++ b/drivers/video/omap2/dss/dss_features.c +@@ -115,7 +115,7 @@ static const enum omap_display_type omap4_dss_supported_displays[] = { + OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI, + + /* OMAP_DSS_CHANNEL_DIGIT */ +- OMAP_DISPLAY_TYPE_VENC, ++ OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI, + + /* OMAP_DSS_CHANNEL_LCD2 */ + OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | +diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c +index 1f53bf2..bcd37ec 100644 +--- a/drivers/video/omap2/dss/manager.c ++++ b/drivers/video/omap2/dss/manager.c +@@ -515,6 +515,8 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr) + + if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) { + irq = DISPC_IRQ_EVSYNC_ODD; ++ } else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI) { ++ irq = DISPC_IRQ_EVSYNC_EVEN; + } else { + if (mgr->id == OMAP_DSS_CHANNEL_LCD) + irq = DISPC_IRQ_VSYNC; +@@ -536,7 +538,8 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr) + if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return 0; + +- if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { ++ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC ++ || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { + irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; + } else { + if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { +@@ -613,7 +616,8 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl) + if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) + return 0; + +- if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { ++ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC ++ || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { + irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; + } else { + if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { +@@ -1377,6 +1381,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) + case OMAP_DISPLAY_TYPE_DBI: + case OMAP_DISPLAY_TYPE_SDI: + case OMAP_DISPLAY_TYPE_VENC: ++ case OMAP_DISPLAY_TYPE_HDMI: + default_get_overlay_fifo_thresholds(ovl->id, size, + &oc->burst_size, &oc->fifo_low, + &oc->fifo_high); +diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c +index 996e9a4..f1aca6d 100644 +--- a/drivers/video/omap2/dss/overlay.c ++++ b/drivers/video/omap2/dss/overlay.c +@@ -679,7 +679,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) + lcd2_mgr->set_device(lcd2_mgr, dssdev); + mgr = lcd2_mgr; + } +- } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) { ++ } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC ++ && dssdev->type != OMAP_DISPLAY_TYPE_HDMI) { + if (!lcd_mgr->device || force) { + if (lcd_mgr->device) + lcd_mgr->unset_device(lcd_mgr); +@@ -688,7 +689,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) + } + } + +- if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { ++ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC ++ || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { + if (!tv_mgr->device || force) { + if (tv_mgr->device) + tv_mgr->unset_device(tv_mgr); +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-302-V5_Select_between_HDMI_VENC_clock_source.patch b/packages/linux/patches/linux-2.6.38-rc8-302-V5_Select_between_HDMI_VENC_clock_source.patch new file mode 100644 index 0000000000..663f5fe18e --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-302-V5_Select_between_HDMI_VENC_clock_source.patch @@ -0,0 +1,47 @@ +Signed-off-by: Mythri P K +--- + drivers/video/omap2/dss/dss.c | 5 +++++ + drivers/video/omap2/dss/dss.h | 6 ++++++ + 2 files changed, 11 insertions(+), 0 deletions(-) + +diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c +index aed9345..0be83c8 100644 +--- a/drivers/video/omap2/dss/dss.c ++++ b/drivers/video/omap2/dss/dss.c +@@ -605,6 +605,11 @@ void dss_set_dac_pwrdn_bgz(bool enable) + REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ + } + ++void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) ++{ ++ REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ ++} ++ + static int dss_init(void) + { + int r; +diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h +index b845468..c2c0fcf 100644 +--- a/drivers/video/omap2/dss/dss.h ++++ b/drivers/video/omap2/dss/dss.h +@@ -132,6 +132,11 @@ struct dss_clk_source_name { + const char *clksrc_name; + }; + ++enum dss_hdmi_venc_clk_source_select { ++ DSS_VENC_TV_CLK = 0, ++ DSS_HDMI_M_PCLK = 1, ++}; ++ + struct dss_clock_info { + /* rates that we get with dividers below */ + unsigned long fck; +@@ -220,6 +225,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); + int dss_init_platform_driver(void); + void dss_uninit_platform_driver(void); + ++void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); + void dss_save_context(void); + void dss_restore_context(void); + void dss_clk_enable(enum dss_clock clks); +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-303-V5_Dispc_gamma_enable_set-reset_function_for_TV.patch b/packages/linux/patches/linux-2.6.38-rc8-303-V5_Dispc_gamma_enable_set-reset_function_for_TV.patch new file mode 100644 index 0000000000..60a995f9e1 --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-303-V5_Dispc_gamma_enable_set-reset_function_for_TV.patch @@ -0,0 +1,46 @@ +Adding function to reset/set gamma table bit for TV interface +currentl only support for disabled is added. + +Signed-off-by: Mythri P K +--- + drivers/video/omap2/dss/dispc.c | 13 +++++++++++++ + drivers/video/omap2/dss/dss.h | 1 + + 2 files changed, 14 insertions(+), 0 deletions(-) + +diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c +index b8c576a..9b86f5f 100644 +--- a/drivers/video/omap2/dss/dispc.c ++++ b/drivers/video/omap2/dss/dispc.c +@@ -1008,6 +1008,19 @@ void dispc_set_burst_size(enum omap_plane plane, + enable_clocks(0); + } + ++void dispc_enable_gamma_table(bool enable) ++{ ++ /* This is partially implemented to support only ++ * disabling of the gamma table. ++ */ ++ if (enable) { ++ DSSWARN("Gamma table enabling for TV not yet supported"); ++ return; ++ } ++ ++ REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); ++} ++ + static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable) + { + u32 val; +diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h +index c2c0fcf..9f563a6 100644 +--- a/drivers/video/omap2/dss/dss.h ++++ b/drivers/video/omap2/dss/dss.h +@@ -376,6 +376,7 @@ void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height); + void dispc_set_channel_out(enum omap_plane plane, + enum omap_channel channel_out); + ++void dispc_enable_gamma_table(bool enable); + int dispc_setup_plane(enum omap_plane plane, + u32 paddr, u16 screen_width, + u16 pos_x, u16 pos_y, +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-304-V5_HDMI_driver_header_file_addition.patch b/packages/linux/patches/linux-2.6.38-rc8-304-V5_HDMI_driver_header_file_addition.patch new file mode 100644 index 0000000000..4cde7027ea --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-304-V5_HDMI_driver_header_file_addition.patch @@ -0,0 +1,431 @@ +Adding the hdmi interface driver header file (hdmi.h) to the dss driver. +Register and structure declaration done here. + +Signed-off-by: Mythri P K +--- + drivers/video/omap2/dss/hdmi.h | 415 ++++++++++++++++++++++++++++++++++++++++ + 1 files changed, 415 insertions(+), 0 deletions(-) + create mode 100644 drivers/video/omap2/dss/hdmi.h + +diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h +new file mode 100644 +index 0000000..9887ab9 +--- /dev/null ++++ b/drivers/video/omap2/dss/hdmi.h +@@ -0,0 +1,415 @@ ++/* ++ * hdmi.h ++ * ++ * HDMI driver definition for TI OMAP4 processors. ++ * ++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see . ++ */ ++ ++#ifndef _OMAP4_DSS_HDMI_H_ ++#define _OMAP4_DSS_HDMI_H_ ++ ++#include ++#include ++ ++#define HDMI_WP 0x0 ++#define HDMI_CORE_SYS 0x400 ++#define HDMI_CORE_AV 0x900 ++#define HDMI_PLLCTRL 0x200 ++#define HDMI_PHY 0x300 ++ ++struct hdmi_reg { u16 idx; }; ++ ++#define HDMI_REG(idx) ((const struct hdmi_reg) { idx }) ++ ++/* HDMI Wrapper */ ++#define HDMI_WP_REG(idx) HDMI_REG(HDMI_WP + idx) ++ ++#define HDMI_WP_REVISION HDMI_WP_REG(0x0) ++#define HDMI_WP_SYSCONFIG HDMI_WP_REG(0x10) ++#define HDMI_WP_IRQSTATUS_RAW HDMI_WP_REG(0x24) ++#define HDMI_WP_IRQSTATUS HDMI_WP_REG(0x28) ++#define HDMI_WP_PWR_CTRL HDMI_WP_REG(0x40) ++#define HDMI_WP_IRQENABLE_SET HDMI_WP_REG(0x2C) ++#define HDMI_WP_VIDEO_CFG HDMI_WP_REG(0x50) ++#define HDMI_WP_VIDEO_SIZE HDMI_WP_REG(0x60) ++#define HDMI_WP_VIDEO_TIMING_H HDMI_WP_REG(0x68) ++#define HDMI_WP_VIDEO_TIMING_V HDMI_WP_REG(0x6C) ++#define HDMI_WP_WP_CLK HDMI_WP_REG(0x70) ++ ++/* HDMI IP Core System */ ++#define HDMI_CORE_SYS_REG(idx) HDMI_REG(HDMI_CORE_SYS + idx) ++ ++#define HDMI_CORE_SYS_VND_IDL HDMI_CORE_SYS_REG(0x0) ++#define HDMI_CORE_SYS_DEV_IDL HDMI_CORE_SYS_REG(0x8) ++#define HDMI_CORE_SYS_DEV_IDH HDMI_CORE_SYS_REG(0xC) ++#define HDMI_CORE_SYS_DEV_REV HDMI_CORE_SYS_REG(0x10) ++#define HDMI_CORE_SYS_SRST HDMI_CORE_SYS_REG(0x14) ++#define HDMI_CORE_CTRL1 HDMI_CORE_SYS_REG(0x20) ++#define HDMI_CORE_SYS_SYS_STAT HDMI_CORE_SYS_REG(0x24) ++#define HDMI_CORE_SYS_VID_ACEN HDMI_CORE_SYS_REG(0x124) ++#define HDMI_CORE_SYS_VID_MODE HDMI_CORE_SYS_REG(0x128) ++#define HDMI_CORE_SYS_INTR_STATE HDMI_CORE_SYS_REG(0x1C0) ++#define HDMI_CORE_SYS_INTR1 HDMI_CORE_SYS_REG(0x1C4) ++#define HDMI_CORE_SYS_INTR2 HDMI_CORE_SYS_REG(0x1C8) ++#define HDMI_CORE_SYS_INTR3 HDMI_CORE_SYS_REG(0x1CC) ++#define HDMI_CORE_SYS_INTR4 HDMI_CORE_SYS_REG(0x1D0) ++#define HDMI_CORE_SYS_UMASK1 HDMI_CORE_SYS_REG(0x1D4) ++#define HDMI_CORE_SYS_TMDS_CTRL HDMI_CORE_SYS_REG(0x208) ++#define HDMI_CORE_SYS_DE_DLY HDMI_CORE_SYS_REG(0xC8) ++#define HDMI_CORE_SYS_DE_CTRL HDMI_CORE_SYS_REG(0xCC) ++#define HDMI_CORE_SYS_DE_TOP HDMI_CORE_SYS_REG(0xD0) ++#define HDMI_CORE_SYS_DE_CNTL HDMI_CORE_SYS_REG(0xD8) ++#define HDMI_CORE_SYS_DE_CNTH HDMI_CORE_SYS_REG(0xDC) ++#define HDMI_CORE_SYS_DE_LINL HDMI_CORE_SYS_REG(0xE0) ++#define HDMI_CORE_SYS_DE_LINH_1 HDMI_CORE_SYS_REG(0xE4) ++#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1 ++#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1 ++#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1 ++#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1 ++ ++/* HDMI DDC E-DID */ ++#define HDMI_CORE_DDC_CMD HDMI_CORE_SYS_REG(0x3CC) ++#define HDMI_CORE_DDC_STATUS HDMI_CORE_SYS_REG(0x3C8) ++#define HDMI_CORE_DDC_ADDR HDMI_CORE_SYS_REG(0x3B4) ++#define HDMI_CORE_DDC_OFFSET HDMI_CORE_SYS_REG(0x3BC) ++#define HDMI_CORE_DDC_COUNT1 HDMI_CORE_SYS_REG(0x3C0) ++#define HDMI_CORE_DDC_COUNT2 HDMI_CORE_SYS_REG(0x3C4) ++#define HDMI_CORE_DDC_DATA HDMI_CORE_SYS_REG(0x3D0) ++#define HDMI_CORE_DDC_SEGM HDMI_CORE_SYS_REG(0x3B8) ++ ++/* HDMI IP Core Audio Video */ ++#define HDMI_CORE_AV_REG(idx) HDMI_REG(HDMI_CORE_AV + idx) ++ ++#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) ++#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) ++#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) ++#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) ++#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) ++#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) ++#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) ++#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) ++#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x110) ++#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_CORE_AV_REG(15) ++#define HDMI_CORE_AV_SPD_DBYTE HDMI_CORE_AV_REG(0x190) ++#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_CORE_AV_REG(27) ++#define HDMI_CORE_AV_MPEG_DBYTE HDMI_CORE_AV_REG(0x290) ++#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_CORE_AV_REG(27) ++#define HDMI_CORE_AV_GEN_DBYTE HDMI_CORE_AV_REG(0x300) ++#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_CORE_AV_REG(31) ++#define HDMI_CORE_AV_GEN2_DBYTE HDMI_CORE_AV_REG(0x380) ++#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_CORE_AV_REG(31) ++#define HDMI_CORE_AV_ACR_CTRL HDMI_CORE_AV_REG(0x4) ++#define HDMI_CORE_AV_FREQ_SVAL HDMI_CORE_AV_REG(0x8) ++#define HDMI_CORE_AV_N_SVAL1 HDMI_CORE_AV_REG(0xC) ++#define HDMI_CORE_AV_N_SVAL2 HDMI_CORE_AV_REG(0x10) ++#define HDMI_CORE_AV_N_SVAL3 HDMI_CORE_AV_REG(0x14) ++#define HDMI_CORE_AV_CTS_SVAL1 HDMI_CORE_AV_REG(0x18) ++#define HDMI_CORE_AV_CTS_SVAL2 HDMI_CORE_AV_REG(0x1C) ++#define HDMI_CORE_AV_CTS_SVAL3 HDMI_CORE_AV_REG(0x20) ++#define HDMI_CORE_AV_CTS_HVAL1 HDMI_CORE_AV_REG(0x24) ++#define HDMI_CORE_AV_CTS_HVAL2 HDMI_CORE_AV_REG(0x28) ++#define HDMI_CORE_AV_CTS_HVAL3 HDMI_CORE_AV_REG(0x2C) ++#define HDMI_CORE_AV_AUD_MODE HDMI_CORE_AV_REG(0x50) ++#define HDMI_CORE_AV_SPDIF_CTRL HDMI_CORE_AV_REG(0x54) ++#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_CORE_AV_REG(0x60) ++#define HDMI_CORE_AV_SWAP_I2S HDMI_CORE_AV_REG(0x64) ++#define HDMI_CORE_AV_SPDIF_ERTH HDMI_CORE_AV_REG(0x6C) ++#define HDMI_CORE_AV_I2S_IN_MAP HDMI_CORE_AV_REG(0x70) ++#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_CORE_AV_REG(0x74) ++#define HDMI_CORE_AV_I2S_CHST0 HDMI_CORE_AV_REG(0x78) ++#define HDMI_CORE_AV_I2S_CHST1 HDMI_CORE_AV_REG(0x7C) ++#define HDMI_CORE_AV_I2S_CHST2 HDMI_CORE_AV_REG(0x80) ++#define HDMI_CORE_AV_I2S_CHST4 HDMI_CORE_AV_REG(0x84) ++#define HDMI_CORE_AV_I2S_CHST5 HDMI_CORE_AV_REG(0x88) ++#define HDMI_CORE_AV_ASRC HDMI_CORE_AV_REG(0x8C) ++#define HDMI_CORE_AV_I2S_IN_LEN HDMI_CORE_AV_REG(0x90) ++#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) ++#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_CORE_AV_REG(0xC0) ++#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_CORE_AV_REG(0xCC) ++#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_CORE_AV_REG(0xD0) ++#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_CORE_AV_REG(0xD4) ++#define HDMI_CORE_AV_TEST_TXCTRL HDMI_CORE_AV_REG(0xF0) ++#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) ++#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) ++#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) ++#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) ++#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) ++#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) ++#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) ++#define HDMI_CORE_AV_SPD_TYPE HDMI_CORE_AV_REG(0x180) ++#define HDMI_CORE_AV_SPD_VERS HDMI_CORE_AV_REG(0x184) ++#define HDMI_CORE_AV_SPD_LEN HDMI_CORE_AV_REG(0x188) ++#define HDMI_CORE_AV_SPD_CHSUM HDMI_CORE_AV_REG(0x18C) ++#define HDMI_CORE_AV_MPEG_TYPE HDMI_CORE_AV_REG(0x280) ++#define HDMI_CORE_AV_MPEG_VERS HDMI_CORE_AV_REG(0x284) ++#define HDMI_CORE_AV_MPEG_LEN HDMI_CORE_AV_REG(0x288) ++#define HDMI_CORE_AV_MPEG_CHSUM HDMI_CORE_AV_REG(0x28C) ++#define HDMI_CORE_AV_CP_BYTE1 HDMI_CORE_AV_REG(0x37C) ++#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_CORE_AV_REG(0x3FC) ++#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4 ++#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4 ++#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4 ++#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4 ++ ++/* PLL */ ++#define HDMI_PLL_REG(idx) HDMI_REG(HDMI_PLLCTRL + idx) ++ ++#define PLLCTRL_PLL_CONTROL HDMI_PLL_REG(0x0) ++#define PLLCTRL_PLL_STATUS HDMI_PLL_REG(0x4) ++#define PLLCTRL_PLL_GO HDMI_PLL_REG(0x8) ++#define PLLCTRL_CFG1 HDMI_PLL_REG(0xC) ++#define PLLCTRL_CFG2 HDMI_PLL_REG(0x10) ++#define PLLCTRL_CFG3 HDMI_PLL_REG(0x14) ++#define PLLCTRL_CFG4 HDMI_PLL_REG(0x20) ++ ++/* HDMI PHY */ ++#define HDMI_PHY_REG(idx) HDMI_REG(HDMI_PHY + idx) ++ ++#define HDMI_TXPHY_TX_CTRL HDMI_PHY_REG(0x0) ++#define HDMI_TXPHY_DIGITAL_CTRL HDMI_PHY_REG(0x4) ++#define HDMI_TXPHY_POWER_CTRL HDMI_PHY_REG(0x8) ++#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_PHY_REG(0xC) ++ ++/* HDMI EDID Length */ ++#define HDMI_EDID_MAX_LENGTH 256 ++#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 ++#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 ++#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 ++#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 ++#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 ++ ++#define OMAP_HDMI_TIMINGS_NB 34 ++ ++#define REG_FLD_MOD(idx, val, start, end) \ ++ hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end)) ++#define REG_GET(idx, start, end) \ ++ FLD_GET(hdmi_read_reg(idx), start, end) ++ ++/* HDMI timing structure */ ++struct hdmi_timings { ++ struct omap_video_timings timings; ++ int vsync_pol; ++ int hsync_pol; ++}; ++ ++enum hdmi_phy_pwr { ++ HDMI_PHYPWRCMD_OFF = 0, ++ HDMI_PHYPWRCMD_LDOON = 1, ++ HDMI_PHYPWRCMD_TXON = 2 ++}; ++ ++enum hdmi_pll_pwr { ++ HDMI_PLLPWRCMD_ALLOFF = 0, ++ HDMI_PLLPWRCMD_PLLONLY = 1, ++ HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, ++ HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 ++}; ++ ++enum hdmi_clk_refsel { ++ HDMI_REFSEL_PCLK = 0, ++ HDMI_REFSEL_REF1 = 1, ++ HDMI_REFSEL_REF2 = 2, ++ HDMI_REFSEL_SYSCLK = 3 ++}; ++ ++enum hdmi_core_inputbus_width { ++ HDMI_INPUT_8BIT = 0, ++ HDMI_INPUT_10BIT = 1, ++ HDMI_INPUT_12BIT = 2 ++}; ++ ++enum hdmi_core_dither_trunc { ++ HDMI_OUTPUTTRUNCATION_8BIT = 0, ++ HDMI_OUTPUTTRUNCATION_10BIT = 1, ++ HDMI_OUTPUTTRUNCATION_12BIT = 2, ++ HDMI_OUTPUTDITHER_8BIT = 3, ++ HDMI_OUTPUTDITHER_10BIT = 4, ++ HDMI_OUTPUTDITHER_12BIT = 5 ++}; ++ ++enum hdmi_core_deepcolor_ed { ++ HDMI_DEEPCOLORPACKECTDISABLE = 0, ++ HDMI_DEEPCOLORPACKECTENABLE = 1 ++}; ++ ++enum hdmi_core_packet_mode { ++ HDMI_PACKETMODERESERVEDVALUE = 0, ++ HDMI_PACKETMODE24BITPERPIXEL = 4, ++ HDMI_PACKETMODE30BITPERPIXEL = 5, ++ HDMI_PACKETMODE36BITPERPIXEL = 6, ++ HDMI_PACKETMODE48BITPERPIXEL = 7 ++}; ++ ++enum hdmi_core_hdmi_dvi { ++ HDMI_DVI = 0, ++ HDMI_HDMI = 1 ++}; ++ ++enum hdmi_core_tclkselclkmult { ++ HDMI_FPLL05IDCK = 0, ++ HDMI_FPLL10IDCK = 1, ++ HDMI_FPLL20IDCK = 2, ++ HDMI_FPLL40IDCK = 3 ++}; ++ ++enum hdmi_core_packet_ctrl { ++ HDMI_PACKETENABLE = 1, ++ HDMI_PACKETDISABLE = 0, ++ HDMI_PACKETREPEATON = 1, ++ HDMI_PACKETREPEATOFF = 0 ++}; ++ ++/* INFOFRAME_AVI_ definitions */ ++enum hdmi_core_infoframe { ++ HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, ++ HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, ++ HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, ++ HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, ++ HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, ++ HDMI_INFOFRAME_AVI_DB1B_NO = 0, ++ HDMI_INFOFRAME_AVI_DB1B_VERT = 1, ++ HDMI_INFOFRAME_AVI_DB1B_HORI = 2, ++ HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, ++ HDMI_INFOFRAME_AVI_DB1S_0 = 0, ++ HDMI_INFOFRAME_AVI_DB1S_1 = 1, ++ HDMI_INFOFRAME_AVI_DB1S_2 = 2, ++ HDMI_INFOFRAME_AVI_DB2C_NO = 0, ++ HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, ++ HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, ++ HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, ++ HDMI_INFOFRAME_AVI_DB2M_NO = 0, ++ HDMI_INFOFRAME_AVI_DB2M_43 = 1, ++ HDMI_INFOFRAME_AVI_DB2M_169 = 2, ++ HDMI_INFOFRAME_AVI_DB2R_SAME = 8, ++ HDMI_INFOFRAME_AVI_DB2R_43 = 9, ++ HDMI_INFOFRAME_AVI_DB2R_169 = 10, ++ HDMI_INFOFRAME_AVI_DB2R_149 = 11, ++ HDMI_INFOFRAME_AVI_DB3ITC_NO = 0, ++ HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, ++ HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, ++ HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, ++ HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0, ++ HDMI_INFOFRAME_AVI_DB3Q_LR = 1, ++ HDMI_INFOFRAME_AVI_DB3Q_FR = 2, ++ HDMI_INFOFRAME_AVI_DB3SC_NO = 0, ++ HDMI_INFOFRAME_AVI_DB3SC_HORI = 1, ++ HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, ++ HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, ++ HDMI_INFOFRAME_AVI_DB5PR_NO = 0, ++ HDMI_INFOFRAME_AVI_DB5PR_2 = 1, ++ HDMI_INFOFRAME_AVI_DB5PR_3 = 2, ++ HDMI_INFOFRAME_AVI_DB5PR_4 = 3, ++ HDMI_INFOFRAME_AVI_DB5PR_5 = 4, ++ HDMI_INFOFRAME_AVI_DB5PR_6 = 5, ++ HDMI_INFOFRAME_AVI_DB5PR_7 = 6, ++ HDMI_INFOFRAME_AVI_DB5PR_8 = 7, ++ HDMI_INFOFRAME_AVI_DB5PR_9 = 8, ++ HDMI_INFOFRAME_AVI_DB5PR_10 = 9 ++}; ++ ++enum hdmi_packing_mode { ++ HDMI_PACK_10b_RGB_YUV444 = 0, ++ HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, ++ HDMI_PACK_20b_YUV422 = 2, ++ HDMI_PACK_ALREADYPACKED = 7 ++}; ++ ++struct hdmi_core_video_config { ++ enum hdmi_core_inputbus_width ip_bus_width; ++ enum hdmi_core_dither_trunc op_dither_truc; ++ enum hdmi_core_deepcolor_ed deep_color_pkt; ++ enum hdmi_core_packet_mode pkt_mode; ++ enum hdmi_core_hdmi_dvi hdmi_dvi; ++ enum hdmi_core_tclkselclkmult tclk_sel_clkmult; ++}; ++ ++/* ++ * Refer to section 8.2 in HDMI 1.3 specification for ++ * details about infoframe databytes ++ */ ++struct hdmi_core_infoframe_avi { ++ u8 db1_format; ++ /* Y0, Y1 rgb,yCbCr */ ++ u8 db1_active_info; ++ /* A0 Active information Present */ ++ u8 db1_bar_info_dv; ++ /* B0, B1 Bar info data valid */ ++ u8 db1_scan_info; ++ /* S0, S1 scan information */ ++ u8 db2_colorimetry; ++ /* C0, C1 colorimetry */ ++ u8 db2_aspect_ratio; ++ /* M0, M1 Aspect ratio (4:3, 16:9) */ ++ u8 db2_active_fmt_ar; ++ /* R0...R3 Active format aspect ratio */ ++ u8 db3_itc; ++ /* ITC IT content. */ ++ u8 db3_ec; ++ /* EC0, EC1, EC2 Extended colorimetry */ ++ u8 db3_q_range; ++ /* Q1, Q0 Quantization range */ ++ u8 db3_nup_scaling; ++ /* SC1, SC0 Non-uniform picture scaling */ ++ u8 db4_videocode; ++ /* VIC0..6 Video format identification */ ++ u8 db5_pixel_repeat; ++ /* PR0..PR3 Pixel repetition factor */ ++ u16 db6_7_line_eoftop; ++ /* Line number end of top bar */ ++ u16 db8_9_line_sofbottom; ++ /* Line number start of bottom bar */ ++ u16 db10_11_pixel_eofleft; ++ /* Pixel number end of left bar */ ++ u16 db12_13_pixel_sofright; ++ /* Pixel number start of right bar */ ++}; ++ ++struct hdmi_core_packet_enable_repeat { ++ u32 audio_pkt; ++ u32 audio_pkt_repeat; ++ u32 avi_infoframe; ++ u32 avi_infoframe_repeat; ++ u32 gen_cntrl_pkt; ++ u32 gen_cntrl_pkt_repeat; ++ u32 generic_pkt; ++ u32 generic_pkt_repeat; ++}; ++ ++struct hdmi_video_format { ++ enum hdmi_packing_mode packing_mode; ++ u32 y_res; /* Line per panel */ ++ u32 x_res; /* pixel per line */ ++}; ++ ++struct hdmi_video_interface { ++ int vsp; /* Vsync polarity */ ++ int hsp; /* Hsync polarity */ ++ int interlacing; ++ int tm; /* Timing mode */ ++}; ++ ++struct hdmi_cm { ++ int code; ++ int mode; ++}; ++ ++struct hdmi_config { ++ struct hdmi_timings timings; ++ u16 interlace; ++ struct hdmi_cm cm; ++}; ++ ++#endif +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-305-V5_HDMI_driver_addition_in_the_DSS.patch b/packages/linux/patches/linux-2.6.38-rc8-305-V5_HDMI_driver_addition_in_the_DSS.patch new file mode 100644 index 0000000000..37d58f9b98 --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-305-V5_HDMI_driver_addition_in_the_DSS.patch @@ -0,0 +1,1418 @@ +Adding the hdmi interface driver(hdmi.c) to the dss driver. +It configures the audio and video portion of HDMI based on +functionality called by the panel driver. + +Signed-off-by: Mythri P K + Yong Zhi +--- + drivers/video/omap2/dss/display.c | 3 + + drivers/video/omap2/dss/dss.h | 34 + + drivers/video/omap2/dss/hdmi.c | 1332 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 1369 insertions(+), 0 deletions(-) + create mode 100644 drivers/video/omap2/dss/hdmi.c + +diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c +index c40bcbd..a85a6f3 100644 +--- a/drivers/video/omap2/dss/display.c ++++ b/drivers/video/omap2/dss/display.c +@@ -418,6 +418,9 @@ void dss_init_device(struct platform_device *pdev, + r = dsi_init_display(dssdev); + break; + #endif ++ case OMAP_DISPLAY_TYPE_HDMI: ++ r = hdmi_init_display(dssdev); ++ break; + default: + DSSERR("Support for display '%s' not compiled in.\n", + dssdev->name); +diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h +index 9f563a6..6bf923c 100644 +--- a/drivers/video/omap2/dss/dss.h ++++ b/drivers/video/omap2/dss/dss.h +@@ -179,6 +179,16 @@ struct dsi_clock_info { + bool use_sys_clk; + }; + ++/* HDMI PLL structure */ ++struct hdmi_pll_info { ++ u16 regn; ++ u16 regm; ++ u32 regmf; ++ u16 regm2; ++ u16 regsd; ++ u16 dcofreq; ++}; ++ + struct seq_file; + struct platform_device; + +@@ -450,6 +460,30 @@ static inline void venc_uninit_platform_driver(void) + } + #endif + ++/* HDMI */ ++#ifdef CONFIG_OMAP4_DSS_HDMI ++int hdmi_init_platform_driver(void); ++void hdmi_uninit_platform_driver(void); ++int hdmi_init_display(struct omap_dss_device *dssdev); ++#else ++static inline int hdmi_init_display(struct omap_dss_device *dssdev) ++{ ++ return 0; ++} ++static inline int hdmi_init_platform_driver(void) ++{ ++ return 0; ++} ++static inline void hdmi_uninit_platform_driver(void) ++{ ++} ++#endif ++int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev); ++void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev); ++void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev); ++int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, ++ struct omap_video_timings *timings); ++ + /* RFBI */ + #ifdef CONFIG_OMAP2_DSS_RFBI + int rfbi_init_platform_driver(void); +diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c +new file mode 100644 +index 0000000..e0e2cbb +--- /dev/null ++++ b/drivers/video/omap2/dss/hdmi.c +@@ -0,0 +1,1332 @@ ++/* ++ * hdmi.c ++ * ++ * HDMI interface DSS driver setting for TI's OMAP4 family of processor. ++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ ++ * Authors: Yong Zhi ++ * Mythri pk ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see . ++ */ ++ ++#define DSS_SUBSYS_NAME "HDMI" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dss.h" ++#include "hdmi.h" ++ ++static struct { ++ struct mutex lock; ++ struct omap_display_platform_data *pdata; ++ struct platform_device *pdev; ++ void __iomem *base_wp; /* HDMI wrapper */ ++ int code; ++ int mode; ++ u8 edid[HDMI_EDID_MAX_LENGTH]; ++ u8 edid_set; ++ bool custom_set; ++ struct hdmi_config cfg; ++} hdmi; ++ ++/* ++ * Logic for the below structure : ++ * user enters the CEA or VESA timings by specifying the HDMI/DVI code. ++ * There is a correspondence between CEA/VESA timing and code , Please ++ * refer to section 6.3 in HDMI 1.3 specification for timing code. ++ * In the below structure, cea_vesa_timings corresponds to all OMAP4 ++ * supported CEA and VESA timing values. ++ * code_cea corresponds to the CEA code , It is used to get the timing ++ * from cea_vesa_timing array. Similarly with code_vesa. ++ * code_index is used for back mapping, That is once EDID is read from ++ * the TV, EDID is parsed to find the timing values and then map it to ++ * corresponding CEA or VESA index. ++ */ ++ ++static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { ++ { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0}, ++ { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1}, ++ { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}, ++ { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0}, ++ { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0}, ++ { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0}, ++ { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0}, ++ { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1}, ++ { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1}, ++ { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1}, ++ { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0}, ++ { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0}, ++ { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1}, ++ { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0}, ++ { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1}, ++ /* VESA From Here */ ++ { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0}, ++ { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1}, ++ { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1}, ++ { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0}, ++ { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0}, ++ { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1}, ++ { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1}, ++ { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1}, ++ { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0}, ++ { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0}, ++ { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0}, ++ { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0}, ++ { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1}, ++ { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1}, ++ { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1}, ++ { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1}, ++ { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1}, ++ { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1}, ++ { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1} ++}; ++ ++/* ++ * This is a static mapping array which maps the timing values ++ * with corresponding CEA / VESA code ++ */ ++static const int code_index[OMAP_HDMI_TIMINGS_NB] = { ++ 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32, ++ /* <--15 CEA 17--> vesa*/ ++ 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A, ++ 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B ++}; ++ ++/* ++ * This is reverse static mapping which maps the CEA / VESA code ++ * to the corresponding timing values ++ */ ++static const int code_cea[39] = { ++ -1, 0, 3, 3, 2, 8, 5, 5, -1, -1, ++ -1, -1, -1, -1, -1, -1, 9, 10, 10, 1, ++ 7, 6, 6, -1, -1, -1, -1, -1, -1, 11, ++ 11, 12, 14, -1, -1, 13, 13, 4, 4 ++}; ++ ++static const int code_vesa[85] = { ++ -1, -1, -1, -1, 15, -1, -1, -1, -1, 16, ++ -1, -1, -1, -1, 17, -1, 23, -1, -1, -1, ++ -1, -1, 29, 18, -1, -1, -1, 32, 19, -1, ++ -1, -1, 21, -1, -1, 22, -1, -1, -1, 20, ++ -1, 30, 24, -1, -1, -1, -1, 25, -1, -1, ++ -1, -1, -1, -1, -1, -1, -1, 31, 26, -1, ++ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, ++ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, ++ -1, 27, 28, -1, 33}; ++ ++static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; ++ ++static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val) ++{ ++ __raw_writel(val, hdmi.base_wp + idx.idx); ++} ++ ++static inline u32 hdmi_read_reg(const struct hdmi_reg idx) ++{ ++ return __raw_readl(hdmi.base_wp + idx.idx); ++} ++ ++static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx, ++ int b2, int b1, u32 val) ++{ ++ u32 t = 0; ++ while (val != REG_GET(idx, b2, b1)) { ++ udelay(1); ++ if (t++ > 10000) ++ return !val; ++ } ++ return val; ++} ++ ++int hdmi_init_display(struct omap_dss_device *dssdev) ++{ ++ DSSDBG("init_display\n"); ++ ++ return 0; ++} ++ ++static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, ++ struct hdmi_pll_info *fmt, u16 sd) ++{ ++ u32 r; ++ ++ /* PLL start always use manual mode */ ++ REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0); ++ ++ r = hdmi_read_reg(PLLCTRL_CFG1); ++ r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ ++ r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ ++ ++ hdmi_write_reg(PLLCTRL_CFG1, r); ++ ++ r = hdmi_read_reg(PLLCTRL_CFG2); ++ ++ r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ ++ r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ ++ r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ ++ ++ if (dcofreq) { ++ /* divider programming for frequency beyond 1000Mhz */ ++ REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10); ++ r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ ++ } else { ++ r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ ++ } ++ ++ hdmi_write_reg(PLLCTRL_CFG2, r); ++ ++ r = hdmi_read_reg(PLLCTRL_CFG4); ++ r = FLD_MOD(r, fmt->regm2, 24, 18); ++ r = FLD_MOD(r, fmt->regmf, 17, 0); ++ ++ hdmi_write_reg(PLLCTRL_CFG4, r); ++ ++ /* go now */ ++ REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0); ++ ++ /* wait for bit change */ ++ if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) { ++ DSSERR("PLL GO bit not set\n"); ++ return -ETIMEDOUT; ++ } ++ ++ /* Wait till the lock bit is set in PLL status */ ++ if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { ++ DSSWARN("cannot lock PLL\n"); ++ DSSWARN("CFG1 0x%x\n", ++ hdmi_read_reg(PLLCTRL_CFG1)); ++ DSSWARN("CFG2 0x%x\n", ++ hdmi_read_reg(PLLCTRL_CFG2)); ++ DSSWARN("CFG4 0x%x\n", ++ hdmi_read_reg(PLLCTRL_CFG4)); ++ return -ETIMEDOUT; ++ } ++ ++ DSSDBG("PLL locked!\n"); ++ ++ return 0; ++} ++ ++/* PHY_PWR_CMD */ ++static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val) ++{ ++ /* Command for power control of HDMI PHY */ ++ REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6); ++ ++ /* Status of the power control of HDMI PHY */ ++ if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) { ++ DSSERR("Failed to set PHY power mode to %d\n", val); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++/* PLL_PWR_CMD */ ++static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val) ++{ ++ /* Command for power control of HDMI PLL */ ++ REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2); ++ ++ /* wait till PHY_PWR_STATUS is set */ ++ if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) { ++ DSSERR("Failed to set PHY_PWR_STATUS\n"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++static int hdmi_pll_reset(void) ++{ ++ /* SYSRESET controlled by power FSM */ ++ REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3); ++ ++ /* READ 0x0 reset is in progress */ ++ if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { ++ DSSERR("Failed to sysreset PLL\n"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++static int hdmi_phy_init(void) ++{ ++ u16 r = 0; ++ ++ r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON); ++ if (r) ++ return r; ++ ++ r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON); ++ if (r) ++ return r; ++ ++ /* ++ * Read address 0 in order to get the SCP reset done completed ++ * Dummy access performed to make sure reset is done ++ */ ++ hdmi_read_reg(HDMI_TXPHY_TX_CTRL); ++ ++ /* ++ * Write to phy address 0 to configure the clock ++ * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field ++ */ ++ REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); ++ ++ /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ ++ hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); ++ ++ /* Setup max LDO voltage */ ++ REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); ++ ++ /* Write to phy address 3 to change the polarity control */ ++ REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); ++ ++ return 0; ++} ++ ++static int hdmi_wait_softreset(void) ++{ ++ /* reset W1 */ ++ REG_FLD_MOD(HDMI_WP_SYSCONFIG, 0x1, 0, 0); ++ ++ /* wait till SOFTRESET == 0 */ ++ if (hdmi_wait_for_bit_change(HDMI_WP_SYSCONFIG, 0, 0, 0) != 0) { ++ DSSERR("sysconfig reset failed\n"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++static int hdmi_pll_program(struct hdmi_pll_info *fmt) ++{ ++ u16 r = 0; ++ enum hdmi_clk_refsel refsel; ++ ++ /* wait for wrapper reset */ ++ r = hdmi_wait_softreset(); ++ if (r) ++ return r; ++ ++ r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); ++ if (r) ++ return r; ++ ++ r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS); ++ if (r) ++ return r; ++ ++ r = hdmi_pll_reset(); ++ if (r) ++ return r; ++ ++ refsel = HDMI_REFSEL_SYSCLK; ++ ++ r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd); ++ if (r) ++ return r; ++ ++ return 0; ++} ++ ++static void hdmi_phy_off(void) ++{ ++ hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF); ++} ++ ++static int hdmi_core_ddc_edid(u8 *pedid, int ext) ++{ ++ u32 i, j; ++ char checksum = 0; ++ u32 offset = 0; ++ ++ /* Turn on CLK for DDC */ ++ REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0); ++ ++ /* ++ * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / ++ * right shifted values( The behavior is not consistent and seen only ++ * with some TV's) ++ */ ++ usleep_range(800, 1000); ++ ++ if (!ext) { ++ /* Clk SCL Devices */ ++ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0); ++ ++ /* HDMI_CORE_DDC_STATUS_IN_PROG */ ++ if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, ++ 4, 4, 0) != 0) { ++ DSSERR("Failed to program DDC\n"); ++ return -ETIMEDOUT; ++ } ++ ++ /* Clear FIFO */ ++ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0); ++ ++ /* HDMI_CORE_DDC_STATUS_IN_PROG */ ++ if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, ++ 4, 4, 0) != 0) { ++ DSSERR("Failed to program DDC\n"); ++ return -ETIMEDOUT; ++ } ++ ++ } else { ++ if (ext % 2 != 0) ++ offset = 0x80; ++ } ++ ++ /* Load Segment Address Register */ ++ REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0); ++ ++ /* Load Slave Address Register */ ++ REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); ++ ++ /* Load Offset Address Register */ ++ REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0); ++ ++ /* Load Byte Count */ ++ REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); ++ REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); ++ ++ /* Set DDC_CMD */ ++ if (ext) ++ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0); ++ else ++ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0); ++ ++ /* HDMI_CORE_DDC_STATUS_BUS_LOW */ ++ if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) { ++ DSSWARN("I2C Bus Low?\n"); ++ return -EIO; ++ } ++ /* HDMI_CORE_DDC_STATUS_NO_ACK */ ++ if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) { ++ DSSWARN("I2C No Ack\n"); ++ return -EIO; ++ } ++ ++ i = ext * 128; ++ j = 0; ++ while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) || ++ (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && ++ j < 128) { ++ ++ if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) { ++ /* FIFO not empty */ ++ pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0); ++ j++; ++ } ++ } ++ ++ for (j = 0; j < 128; j++) ++ checksum += pedid[j]; ++ ++ if (checksum != 0) { ++ DSSERR("E-EDID checksum failed!!\n"); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static int read_edid(u8 *pedid, u16 max_length) ++{ ++ int r = 0, n = 0, i = 0; ++ int max_ext_blocks = (max_length / 128) - 1; ++ ++ r = hdmi_core_ddc_edid(pedid, 0); ++ if (r) { ++ return r; ++ } else { ++ n = pedid[0x7e]; ++ ++ /* ++ * README: need to comply with max_length set by the caller. ++ * Better implementation should be to allocate necessary ++ * memory to store EDID according to nb_block field found ++ * in first block ++ */ ++ if (n > max_ext_blocks) ++ n = max_ext_blocks; ++ ++ for (i = 1; i <= n; i++) { ++ r = hdmi_core_ddc_edid(pedid, i); ++ if (r) ++ return r; ++ } ++ } ++ return 0; ++} ++ ++static int get_timings_index(void) ++{ ++ int code; ++ ++ if (hdmi.mode == 0) ++ code = code_vesa[hdmi.code]; ++ else ++ code = code_cea[hdmi.code]; ++ ++ if (code == -1) { ++ /* HDMI code 4 corresponds to 640 * 480 VGA */ ++ hdmi.code = 4; ++ /* DVI mode 1 corresponds to HDMI 0 to DVI */ ++ hdmi.mode = HDMI_DVI; ++ ++ code = code_vesa[hdmi.code]; ++ } ++ return code; ++} ++ ++static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) ++{ ++ int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; ++ int timing_vsync = 0, timing_hsync = 0; ++ struct omap_video_timings temp; ++ struct hdmi_cm cm = {-1}; ++ DSSDBG("hdmi_get_code\n"); ++ ++ for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) { ++ temp = cea_vesa_timings[i].timings; ++ if ((temp.pixel_clock == timing->pixel_clock) && ++ (temp.x_res == timing->x_res) && ++ (temp.y_res == timing->y_res)) { ++ ++ temp_hsync = temp.hfp + temp.hsw + temp.hbp; ++ timing_hsync = timing->hfp + timing->hsw + timing->hbp; ++ temp_vsync = temp.vfp + temp.vsw + temp.vbp; ++ timing_vsync = timing->vfp + timing->vsw + timing->vbp; ++ ++ DSSDBG("temp_hsync = %d , temp_vsync = %d" ++ "timing_hsync = %d, timing_vsync = %d\n", ++ temp_hsync, temp_hsync, ++ timing_hsync, timing_vsync); ++ ++ if ((temp_hsync == timing_hsync) && ++ (temp_vsync == timing_vsync)) { ++ code = i; ++ cm.code = code_index[i]; ++ if (code < 14) ++ cm.mode = HDMI_HDMI; ++ else ++ cm.mode = HDMI_DVI; ++ DSSDBG("Hdmi_code = %d mode = %d\n", ++ cm.code, cm.mode); ++ break; ++ } ++ } ++ } ++ ++ return cm; ++} ++ ++static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid , ++ struct omap_video_timings *timings) ++{ ++ /* X and Y resolution */ ++ timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) | ++ edid[current_descriptor_addrs + 2]); ++ timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) | ++ edid[current_descriptor_addrs + 5]); ++ ++ timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) | ++ edid[current_descriptor_addrs]); ++ ++ timings->pixel_clock = 10 * timings->pixel_clock; ++ ++ /* HORIZONTAL FRONT PORCH */ ++ timings->hfp = edid[current_descriptor_addrs + 8] | ++ ((edid[current_descriptor_addrs + 11] & 0xc0) << 2); ++ /* HORIZONTAL SYNC WIDTH */ ++ timings->hsw = edid[current_descriptor_addrs + 9] | ++ ((edid[current_descriptor_addrs + 11] & 0x30) << 4); ++ /* HORIZONTAL BACK PORCH */ ++ timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) | ++ edid[current_descriptor_addrs + 3]) - ++ (timings->hfp + timings->hsw); ++ /* VERTICAL FRONT PORCH */ ++ timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) | ++ ((edid[current_descriptor_addrs + 11] & 0x0f) << 2); ++ /* VERTICAL SYNC WIDTH */ ++ timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) | ++ ((edid[current_descriptor_addrs + 11] & 0x03) << 4); ++ /* VERTICAL BACK PORCH */ ++ timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) | ++ edid[current_descriptor_addrs + 6]) - ++ (timings->vfp + timings->vsw); ++ ++} ++ ++/* Description : This function gets the resolution information from EDID */ ++static void get_edid_timing_data(u8 *edid) ++{ ++ u8 count; ++ u16 current_descriptor_addrs; ++ struct hdmi_cm cm; ++ struct omap_video_timings edid_timings; ++ ++ /* seach block 0, there are 4 DTDs arranged in priority order */ ++ for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) { ++ current_descriptor_addrs = ++ EDID_DESCRIPTOR_BLOCK0_ADDRESS + ++ count * EDID_TIMING_DESCRIPTOR_SIZE; ++ get_horz_vert_timing_info(current_descriptor_addrs, ++ edid, &edid_timings); ++ cm = hdmi_get_code(&edid_timings); ++ DSSDBG("Block0[%d] value matches code = %d , mode = %d\n", ++ count, cm.code, cm.mode); ++ if (cm.code == -1) { ++ continue; ++ } else { ++ hdmi.code = cm.code; ++ hdmi.mode = cm.mode; ++ DSSDBG("code = %d , mode = %d\n", ++ hdmi.code, hdmi.mode); ++ return; ++ } ++ } ++ if (edid[0x7e] != 0x00) { ++ for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR; ++ count++) { ++ current_descriptor_addrs = ++ EDID_DESCRIPTOR_BLOCK1_ADDRESS + ++ count * EDID_TIMING_DESCRIPTOR_SIZE; ++ get_horz_vert_timing_info(current_descriptor_addrs, ++ edid, &edid_timings); ++ cm = hdmi_get_code(&edid_timings); ++ DSSDBG("Block1[%d] value matches code = %d, mode = %d", ++ count, cm.code, cm.mode); ++ if (cm.code == -1) { ++ continue; ++ } else { ++ hdmi.code = cm.code; ++ hdmi.mode = cm.mode; ++ DSSDBG("code = %d , mode = %d\n", ++ hdmi.code, hdmi.mode); ++ return; ++ } ++ } ++ } ++ ++ DSSINFO("no valid timing found , falling back to VGA\n"); ++ hdmi.code = 4; /* setting default value of 640 480 VGA */ ++ hdmi.mode = HDMI_DVI; ++} ++ ++static void hdmi_read_edid(struct omap_video_timings *dp) ++{ ++ int ret = 0, code; ++ ++ memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); ++ ++ if (!hdmi.edid_set) ++ ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH); ++ ++ if (!ret) { ++ if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { ++ /* search for timings of default resolution */ ++ get_edid_timing_data(hdmi.edid); ++ hdmi.edid_set = true; ++ } ++ } else { ++ DSSWARN("failed to read E-EDID\n"); ++ } ++ ++ if (!hdmi.edid_set) { ++ DSSINFO("fallback to VGA\n"); ++ hdmi.code = 4; /* setting default value of 640 480 VGA */ ++ hdmi.mode = HDMI_DVI; ++ } ++ ++ code = get_timings_index(); ++ ++ *dp = cea_vesa_timings[code].timings; ++} ++ ++static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, ++ struct hdmi_core_infoframe_avi *avi_cfg, ++ struct hdmi_core_packet_enable_repeat *repeat_cfg) ++{ ++ DSSDBG("Enter hdmi_core_init\n"); ++ ++ /* video core */ ++ video_cfg->ip_bus_width = HDMI_INPUT_8BIT; ++ video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; ++ video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; ++ video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; ++ video_cfg->hdmi_dvi = HDMI_DVI; ++ video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; ++ ++ /* info frame */ ++ avi_cfg->db1_format = 0; ++ avi_cfg->db1_active_info = 0; ++ avi_cfg->db1_bar_info_dv = 0; ++ avi_cfg->db1_scan_info = 0; ++ avi_cfg->db2_colorimetry = 0; ++ avi_cfg->db2_aspect_ratio = 0; ++ avi_cfg->db2_active_fmt_ar = 0; ++ avi_cfg->db3_itc = 0; ++ avi_cfg->db3_ec = 0; ++ avi_cfg->db3_q_range = 0; ++ avi_cfg->db3_nup_scaling = 0; ++ avi_cfg->db4_videocode = 0; ++ avi_cfg->db5_pixel_repeat = 0; ++ avi_cfg->db6_7_line_eoftop = 0 ; ++ avi_cfg->db8_9_line_sofbottom = 0; ++ avi_cfg->db10_11_pixel_eofleft = 0; ++ avi_cfg->db12_13_pixel_sofright = 0; ++ ++ /* packet enable and repeat */ ++ repeat_cfg->audio_pkt = 0; ++ repeat_cfg->audio_pkt_repeat = 0; ++ repeat_cfg->avi_infoframe = 0; ++ repeat_cfg->avi_infoframe_repeat = 0; ++ repeat_cfg->gen_cntrl_pkt = 0; ++ repeat_cfg->gen_cntrl_pkt_repeat = 0; ++ repeat_cfg->generic_pkt = 0; ++ repeat_cfg->generic_pkt_repeat = 0; ++} ++ ++static void hdmi_core_powerdown_disable(void) ++{ ++ DSSDBG("Enter hdmi_core_powerdown_disable\n"); ++ REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0); ++} ++ ++static void hdmi_core_swreset_release(void) ++{ ++ DSSDBG("Enter hdmi_core_swreset_release\n"); ++ REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0); ++} ++ ++static void hdmi_core_swreset_assert(void) ++{ ++ DSSDBG("Enter hdmi_core_swreset_assert\n"); ++ REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0); ++} ++ ++/* DSS_HDMI_CORE_VIDEO_CONFIG */ ++static void hdmi_core_video_config(struct hdmi_core_video_config *cfg) ++{ ++ u32 r = 0; ++ ++ /* sys_ctrl1 default configuration not tunable */ ++ r = hdmi_read_reg(HDMI_CORE_CTRL1); ++ r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); ++ r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); ++ r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); ++ r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); ++ hdmi_write_reg(HDMI_CORE_CTRL1, r); ++ ++ REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); ++ ++ /* Vid_Mode */ ++ r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE); ++ ++ /* dither truncation configuration */ ++ if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { ++ r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); ++ r = FLD_MOD(r, 1, 5, 5); ++ } else { ++ r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); ++ r = FLD_MOD(r, 0, 5, 5); ++ } ++ hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r); ++ ++ /* HDMI_Ctrl */ ++ r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL); ++ r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); ++ r = FLD_MOD(r, cfg->pkt_mode, 5, 3); ++ r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); ++ hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r); ++ ++ /* TMDS_CTRL */ ++ REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL, ++ cfg->tclk_sel_clkmult, 6, 5); ++} ++ ++static void hdmi_core_aux_infoframe_avi_config( ++ struct hdmi_core_infoframe_avi info_avi) ++{ ++ u32 val; ++ char sum = 0, checksum = 0; ++ ++ sum += 0x82 + 0x002 + 0x00D; ++ hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D); ++ ++ val = (info_avi.db1_format << 5) | ++ (info_avi.db1_active_info << 4) | ++ (info_avi.db1_bar_info_dv << 2) | ++ (info_avi.db1_scan_info); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val); ++ sum += val; ++ ++ val = (info_avi.db2_colorimetry << 6) | ++ (info_avi.db2_aspect_ratio << 4) | ++ (info_avi.db2_active_fmt_ar); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val); ++ sum += val; ++ ++ val = (info_avi.db3_itc << 7) | ++ (info_avi.db3_ec << 4) | ++ (info_avi.db3_q_range << 2) | ++ (info_avi.db3_nup_scaling); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val); ++ sum += val; ++ ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode); ++ sum += info_avi.db4_videocode; ++ ++ val = info_avi.db5_pixel_repeat; ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val); ++ sum += val; ++ ++ val = info_avi.db6_7_line_eoftop & 0x00FF; ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val); ++ sum += val; ++ ++ val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val); ++ sum += val; ++ ++ val = info_avi.db8_9_line_sofbottom & 0x00FF; ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val); ++ sum += val; ++ ++ val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val); ++ sum += val; ++ ++ val = info_avi.db10_11_pixel_eofleft & 0x00FF; ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val); ++ sum += val; ++ ++ val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val); ++ sum += val; ++ ++ val = info_avi.db12_13_pixel_sofright & 0x00FF; ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val); ++ sum += val; ++ ++ val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); ++ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val); ++ sum += val; ++ ++ checksum = 0x100 - sum; ++ hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum); ++} ++ ++static void hdmi_core_av_packet_config( ++ struct hdmi_core_packet_enable_repeat repeat_cfg) ++{ ++ /* enable/repeat the infoframe */ ++ hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1, ++ (repeat_cfg.audio_pkt << 5) | ++ (repeat_cfg.audio_pkt_repeat << 4) | ++ (repeat_cfg.avi_infoframe << 1) | ++ (repeat_cfg.avi_infoframe_repeat)); ++ ++ /* enable/repeat the packet */ ++ hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2, ++ (repeat_cfg.gen_cntrl_pkt << 3) | ++ (repeat_cfg.gen_cntrl_pkt_repeat << 2) | ++ (repeat_cfg.generic_pkt << 1) | ++ (repeat_cfg.generic_pkt_repeat)); ++} ++ ++static void hdmi_wp_init(struct omap_video_timings *timings, ++ struct hdmi_video_format *video_fmt, ++ struct hdmi_video_interface *video_int) ++{ ++ DSSDBG("Enter hdmi_wp_init\n"); ++ ++ timings->hbp = 0; ++ timings->hfp = 0; ++ timings->hsw = 0; ++ timings->vbp = 0; ++ timings->vfp = 0; ++ timings->vsw = 0; ++ ++ video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; ++ video_fmt->y_res = 0; ++ video_fmt->x_res = 0; ++ ++ video_int->vsp = 0; ++ video_int->hsp = 0; ++ ++ video_int->interlacing = 0; ++ video_int->tm = 0; /* HDMI_TIMING_SLAVE */ ++ ++} ++ ++static void hdmi_wp_video_start(bool start) ++{ ++ REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31); ++} ++ ++static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, ++ struct omap_video_timings *timings, struct hdmi_config *param) ++{ ++ DSSDBG("Enter hdmi_wp_video_init_format\n"); ++ ++ video_fmt->y_res = param->timings.timings.y_res; ++ video_fmt->x_res = param->timings.timings.x_res; ++ ++ timings->hbp = param->timings.timings.hbp; ++ timings->hfp = param->timings.timings.hfp; ++ timings->hsw = param->timings.timings.hsw; ++ timings->vbp = param->timings.timings.vbp; ++ timings->vfp = param->timings.timings.vfp; ++ timings->vsw = param->timings.timings.vsw; ++} ++ ++static void hdmi_wp_video_config_format( ++ struct hdmi_video_format *video_fmt) ++{ ++ u32 l = 0; ++ ++ REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8); ++ ++ l |= FLD_VAL(video_fmt->y_res, 31, 16); ++ l |= FLD_VAL(video_fmt->x_res, 15, 0); ++ hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l); ++} ++ ++static void hdmi_wp_video_config_interface( ++ struct hdmi_video_interface *video_int) ++{ ++ u32 r; ++ DSSDBG("Enter hdmi_wp_video_config_interface\n"); ++ ++ r = hdmi_read_reg(HDMI_WP_VIDEO_CFG); ++ r = FLD_MOD(r, video_int->vsp, 7, 7); ++ r = FLD_MOD(r, video_int->hsp, 6, 6); ++ r = FLD_MOD(r, video_int->interlacing, 3, 3); ++ r = FLD_MOD(r, video_int->tm, 1, 0); ++ hdmi_write_reg(HDMI_WP_VIDEO_CFG, r); ++} ++ ++static void hdmi_wp_video_config_timing( ++ struct omap_video_timings *timings) ++{ ++ u32 timing_h = 0; ++ u32 timing_v = 0; ++ ++ DSSDBG("Enter hdmi_wp_video_config_timing\n"); ++ ++ timing_h |= FLD_VAL(timings->hbp, 31, 20); ++ timing_h |= FLD_VAL(timings->hfp, 19, 8); ++ timing_h |= FLD_VAL(timings->hsw, 7, 0); ++ hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h); ++ ++ timing_v |= FLD_VAL(timings->vbp, 31, 20); ++ timing_v |= FLD_VAL(timings->vfp, 19, 8); ++ timing_v |= FLD_VAL(timings->vsw, 7, 0); ++ hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v); ++} ++ ++static void hdmi_basic_configure(struct hdmi_config *cfg) ++{ ++ /* HDMI */ ++ struct omap_video_timings video_timing; ++ struct hdmi_video_format video_format; ++ struct hdmi_video_interface video_interface; ++ /* HDMI core */ ++ struct hdmi_core_infoframe_avi avi_cfg; ++ struct hdmi_core_video_config v_core_cfg; ++ struct hdmi_core_packet_enable_repeat repeat_cfg; ++ ++ hdmi_wp_init(&video_timing, &video_format, ++ &video_interface); ++ ++ hdmi_core_init(&v_core_cfg, ++ &avi_cfg, ++ &repeat_cfg); ++ ++ hdmi_wp_video_init_format(&video_format, ++ &video_timing, cfg); ++ ++ hdmi_wp_video_config_timing(&video_timing); ++ ++ /* video config */ ++ video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; ++ ++ hdmi_wp_video_config_format(&video_format); ++ ++ video_interface.vsp = cfg->timings.vsync_pol; ++ video_interface.hsp = cfg->timings.hsync_pol; ++ video_interface.interlacing = cfg->interlace; ++ video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ ++ ++ hdmi_wp_video_config_interface(&video_interface); ++ ++ /* ++ * configure core video part ++ * set software reset in the core ++ */ ++ hdmi_core_swreset_assert(); ++ ++ /* power down off */ ++ hdmi_core_powerdown_disable(); ++ ++ v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; ++ v_core_cfg.hdmi_dvi = cfg->cm.mode; ++ ++ hdmi_core_video_config(&v_core_cfg); ++ ++ /* release software reset in the core */ ++ hdmi_core_swreset_release(); ++ ++ /* ++ * configure packet ++ * info frame video see doc CEA861-D page 65 ++ */ ++ avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; ++ avi_cfg.db1_active_info = ++ HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; ++ avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; ++ avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; ++ avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; ++ avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; ++ avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; ++ avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; ++ avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; ++ avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; ++ avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; ++ avi_cfg.db4_videocode = cfg->cm.code; ++ avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; ++ avi_cfg.db6_7_line_eoftop = 0; ++ avi_cfg.db8_9_line_sofbottom = 0; ++ avi_cfg.db10_11_pixel_eofleft = 0; ++ avi_cfg.db12_13_pixel_sofright = 0; ++ ++ hdmi_core_aux_infoframe_avi_config(avi_cfg); ++ ++ /* enable/repeat the infoframe */ ++ repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; ++ repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; ++ /* wakeup */ ++ repeat_cfg.audio_pkt = HDMI_PACKETENABLE; ++ repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; ++ hdmi_core_av_packet_config(repeat_cfg); ++} ++ ++static void update_hdmi_timings(struct hdmi_config *cfg, ++ struct omap_video_timings *timings, int code) ++{ ++ cfg->timings.timings.x_res = timings->x_res; ++ cfg->timings.timings.y_res = timings->y_res; ++ cfg->timings.timings.hbp = timings->hbp; ++ cfg->timings.timings.hfp = timings->hfp; ++ cfg->timings.timings.hsw = timings->hsw; ++ cfg->timings.timings.vbp = timings->vbp; ++ cfg->timings.timings.vfp = timings->vfp; ++ cfg->timings.timings.vsw = timings->vsw; ++ cfg->timings.timings.pixel_clock = timings->pixel_clock; ++ cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol; ++ cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; ++} ++ ++static void hdmi_compute_pll(unsigned long clkin, int phy, ++ int n, struct hdmi_pll_info *pi) ++{ ++ unsigned long refclk; ++ u32 mf; ++ ++ /* ++ * Input clock is predivided by N + 1 ++ * out put of which is reference clk ++ */ ++ refclk = clkin / (n + 1); ++ pi->regn = n; ++ ++ /* ++ * multiplier is pixel_clk/ref_clk ++ * Multiplying by 100 to avoid fractional part removal ++ */ ++ pi->regm = (phy * 100/(refclk))/100; ++ pi->regm2 = 1; ++ ++ /* ++ * fractional multiplier is remainder of the difference between ++ * multiplier and actual phy(required pixel clock thus should be ++ * multiplied by 218(262144) divided by the reference clock ++ */ ++ mf = (phy - pi->regm * refclk) * 262144; ++ pi->regmf = mf/(refclk); ++ ++ /* ++ * Dcofreq should be set to 1 if required pixel clock ++ * is greater than 1000MHz ++ */ ++ pi->dcofreq = phy > 1000 * 100; ++ pi->regsd = ((pi->regm * clkin / 10) / ((n + 1) * 250) + 5) / 10; ++ ++ DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); ++ DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); ++} ++ ++static void hdmi_enable_clocks(int enable) ++{ ++ if (enable) ++ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | ++ DSS_CLK_SYSCK | DSS_CLK_VIDFCK); ++ else ++ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | ++ DSS_CLK_SYSCK | DSS_CLK_VIDFCK); ++} ++ ++static int hdmi_power_on(struct omap_dss_device *dssdev) ++{ ++ int r, code = 0; ++ struct hdmi_pll_info pll_data; ++ struct omap_video_timings *p; ++ int clkin, n, phy; ++ ++ hdmi_enable_clocks(1); ++ ++ dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0); ++ ++ p = &dssdev->panel.timings; ++ ++ DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", ++ dssdev->panel.timings.x_res, ++ dssdev->panel.timings.y_res); ++ ++ if (!hdmi.custom_set) { ++ DSSDBG("Read EDID as no EDID is not set on poweron\n"); ++ hdmi_read_edid(p); ++ } ++ code = get_timings_index(); ++ dssdev->panel.timings = cea_vesa_timings[code].timings; ++ update_hdmi_timings(&hdmi.cfg, p, code); ++ ++ clkin = 3840; /* 38.4 MHz */ ++ n = 15; /* this is a constant for our math */ ++ phy = p->pixel_clock; ++ ++ hdmi_compute_pll(clkin, phy, n, &pll_data); ++ ++ hdmi_wp_video_start(0); ++ ++ /* config the PLL and PHY first */ ++ r = hdmi_pll_program(&pll_data); ++ if (r) { ++ DSSDBG("Failed to lock PLL\n"); ++ goto err; ++ } ++ ++ r = hdmi_phy_init(); ++ if (r) { ++ DSSDBG("Failed to start PHY\n"); ++ goto err; ++ } ++ ++ hdmi.cfg.cm.mode = hdmi.mode; ++ hdmi.cfg.cm.code = hdmi.code; ++ hdmi_basic_configure(&hdmi.cfg); ++ ++ /* Make selection of HDMI in DSS */ ++ dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); ++ ++ /* Select the dispc clock source as PRCM clock, to ensure that it is not ++ * DSI PLL source as the clock selected by DSI PLL might not be ++ * sufficient for the resolution selected / that can be changed ++ * dynamically by user. This can be moved to single location , say ++ * Boardfile. ++ */ ++ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); ++ ++ /* bypass TV gamma table */ ++ dispc_enable_gamma_table(0); ++ ++ /* tv size */ ++ dispc_set_digit_size(dssdev->panel.timings.x_res, ++ dssdev->panel.timings.y_res); ++ ++ dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 1); ++ ++ hdmi_wp_video_start(1); ++ ++ return 0; ++err: ++ hdmi_enable_clocks(0); ++ return -EIO; ++} ++ ++static void hdmi_power_off(struct omap_dss_device *dssdev) ++{ ++ dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0); ++ ++ hdmi_wp_video_start(0); ++ hdmi_phy_off(); ++ hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); ++ hdmi_enable_clocks(0); ++ ++ hdmi.edid_set = 0; ++} ++ ++int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, ++ struct omap_video_timings *timings) ++{ ++ struct hdmi_cm cm; ++ ++ cm = hdmi_get_code(timings); ++ if (cm.code == -1) { ++ DSSERR("Invalid timing entered\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++ ++} ++ ++void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) ++{ ++ struct hdmi_cm cm; ++ ++ hdmi.custom_set = 1; ++ cm = hdmi_get_code(&dssdev->panel.timings); ++ hdmi.code = cm.code; ++ hdmi.mode = cm.mode; ++ omapdss_hdmi_display_enable(dssdev); ++ hdmi.custom_set = 0; ++} ++ ++int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) ++{ ++ int r = 0; ++ ++ DSSDBG("ENTER hdmi_display_enable\n"); ++ ++ mutex_lock(&hdmi.lock); ++ ++ r = omap_dss_start_device(dssdev); ++ if (r) { ++ DSSERR("failed to start device\n"); ++ goto err0; ++ } ++ ++ if (dssdev->platform_enable) { ++ r = dssdev->platform_enable(dssdev); ++ if (r) { ++ DSSERR("failed to enable GPIO's\n"); ++ goto err1; ++ } ++ } ++ ++ r = hdmi_power_on(dssdev); ++ if (r) { ++ DSSERR("failed to power on device\n"); ++ goto err2; ++ } ++ ++ mutex_unlock(&hdmi.lock); ++ return 0; ++ ++err2: ++ if (dssdev->platform_disable) ++ dssdev->platform_disable(dssdev); ++err1: ++ omap_dss_stop_device(dssdev); ++err0: ++ mutex_unlock(&hdmi.lock); ++ return r; ++} ++ ++void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) ++{ ++ DSSDBG("Enter hdmi_display_disable\n"); ++ ++ mutex_lock(&hdmi.lock); ++ ++ hdmi_power_off(dssdev); ++ ++ if (dssdev->platform_disable) ++ dssdev->platform_disable(dssdev); ++ ++ omap_dss_stop_device(dssdev); ++ ++ mutex_unlock(&hdmi.lock); ++} ++ ++/* HDMI HW IP initialisation */ ++static int omapdss_hdmihw_probe(struct platform_device *pdev) ++{ ++ struct resource *hdmi_mem; ++ ++ hdmi.pdata = pdev->dev.platform_data; ++ hdmi.pdev = pdev; ++ ++ mutex_init(&hdmi.lock); ++ ++ hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); ++ if (!hdmi_mem) { ++ DSSERR("can't get IORESOURCE_MEM HDMI\n"); ++ return -EINVAL; ++ } ++ ++ /* Base address taken from platform */ ++ hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem)); ++ if (!hdmi.base_wp) { ++ DSSERR("can't ioremap WP\n"); ++ return -ENOMEM; ++ } ++ ++ hdmi_panel_init(); ++ ++ return 0; ++} ++ ++static int omapdss_hdmihw_remove(struct platform_device *pdev) ++{ ++ hdmi_panel_exit(); ++ ++ iounmap(hdmi.base_wp); ++ ++ return 0; ++} ++ ++static struct platform_driver omapdss_hdmihw_driver = { ++ .probe = omapdss_hdmihw_probe, ++ .remove = omapdss_hdmihw_remove, ++ .driver = { ++ .name = "omapdss_hdmi", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int hdmi_init_platform_driver(void) ++{ ++ return platform_driver_register(&omapdss_hdmihw_driver); ++} ++ ++void hdmi_uninit_platform_driver(void) ++{ ++ return platform_driver_unregister(&omapdss_hdmihw_driver); ++} +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-306-V5_HDMI_panel_driver_addition_in_the_DSS.patch b/packages/linux/patches/linux-2.6.38-rc8-306-V5_HDMI_panel_driver_addition_in_the_DSS.patch new file mode 100644 index 0000000000..8d2cdcc739 --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-306-V5_HDMI_panel_driver_addition_in_the_DSS.patch @@ -0,0 +1,252 @@ +The panel driver(hdmi_omap4_panel.c) in omap2/dss acts as a controller +to manage the enable and disable requests and synchronize audio and video. + +Signed-off-by: Mythri P K +--- + drivers/video/omap2/dss/dss.h | 2 + + drivers/video/omap2/dss/hdmi_omap4_panel.c | 222 ++++++++++++++++++++++++++++ + 2 files changed, 224 insertions(+), 0 deletions(-) + create mode 100644 drivers/video/omap2/dss/hdmi_omap4_panel.c + +diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h +index 6bf923c..05ccd00 100644 +--- a/drivers/video/omap2/dss/dss.h ++++ b/drivers/video/omap2/dss/dss.h +@@ -483,6 +483,8 @@ void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev); + void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev); + int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, + struct omap_video_timings *timings); ++int hdmi_panel_init(void); ++void hdmi_panel_exit(void); + + /* RFBI */ + #ifdef CONFIG_OMAP2_DSS_RFBI +diff --git a/drivers/video/omap2/dss/hdmi_omap4_panel.c b/drivers/video/omap2/dss/hdmi_omap4_panel.c +new file mode 100644 +index 0000000..ffb5de9 +--- /dev/null ++++ b/drivers/video/omap2/dss/hdmi_omap4_panel.c +@@ -0,0 +1,222 @@ ++/* ++ * hdmi_omap4_panel.c ++ * ++ * HDMI library support functions for TI OMAP4 processors. ++ * ++ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ ++ * Authors: Mythri P k ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dss.h" ++ ++static struct { ++ struct mutex hdmi_lock; ++} hdmi; ++ ++ ++static int hdmi_panel_probe(struct omap_dss_device *dssdev) ++{ ++ DSSDBG("ENTER hdmi_panel_probe\n"); ++ ++ dssdev->panel.config = OMAP_DSS_LCD_TFT | ++ OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS; ++ ++ /* ++ * Initialize the timings to 640 * 480 ++ * This is only for framebuffer update not for TV timing setting ++ * Setting TV timing will be done only on enable ++ */ ++ dssdev->panel.timings.x_res = 640; ++ dssdev->panel.timings.y_res = 480; ++ ++ DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n", ++ dssdev->panel.timings.x_res, ++ dssdev->panel.timings.y_res); ++ return 0; ++} ++ ++static void hdmi_panel_remove(struct omap_dss_device *dssdev) ++{ ++ ++} ++ ++static int hdmi_panel_enable(struct omap_dss_device *dssdev) ++{ ++ int r = 0; ++ DSSDBG("ENTER hdmi_panel_enable\n"); ++ ++ mutex_lock(&hdmi.hdmi_lock); ++ ++ if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { ++ r = -EINVAL; ++ goto err; ++ } ++ ++ r = omapdss_hdmi_display_enable(dssdev); ++ if (r) { ++ DSSERR("failed to power on\n"); ++ goto err; ++ } ++ ++ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; ++ ++err: ++ mutex_unlock(&hdmi.hdmi_lock); ++ ++ return r; ++} ++ ++static void hdmi_panel_disable(struct omap_dss_device *dssdev) ++{ ++ mutex_lock(&hdmi.hdmi_lock); ++ ++ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) ++ omapdss_hdmi_display_disable(dssdev); ++ ++ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; ++ ++ mutex_unlock(&hdmi.hdmi_lock); ++} ++ ++static int hdmi_panel_suspend(struct omap_dss_device *dssdev) ++{ ++ int r = 0; ++ ++ mutex_lock(&hdmi.hdmi_lock); ++ ++ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) { ++ r = -EINVAL; ++ goto err; ++ } ++ ++ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; ++ ++ omapdss_hdmi_display_disable(dssdev); ++ ++err: ++ mutex_unlock(&hdmi.hdmi_lock); ++ ++ return r; ++} ++ ++static int hdmi_panel_resume(struct omap_dss_device *dssdev) ++{ ++ int r = 0; ++ ++ mutex_lock(&hdmi.hdmi_lock); ++ ++ if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) { ++ r = -EINVAL; ++ goto err; ++ } ++ ++ r = omapdss_hdmi_display_enable(dssdev); ++ if (r) { ++ DSSERR("failed to power on\n"); ++ goto err; ++ } ++ ++ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; ++ ++err: ++ mutex_unlock(&hdmi.hdmi_lock); ++ ++ return r; ++} ++ ++static void hdmi_get_timings(struct omap_dss_device *dssdev, ++ struct omap_video_timings *timings) ++{ ++ mutex_lock(&hdmi.hdmi_lock); ++ ++ *timings = dssdev->panel.timings; ++ ++ mutex_unlock(&hdmi.hdmi_lock); ++} ++ ++static void hdmi_set_timings(struct omap_dss_device *dssdev, ++ struct omap_video_timings *timings) ++{ ++ DSSDBG("hdmi_set_timings\n"); ++ ++ mutex_lock(&hdmi.hdmi_lock); ++ ++ dssdev->panel.timings = *timings; ++ ++ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { ++ /* turn the hdmi off and on to get new timings to use */ ++ omapdss_hdmi_display_disable(dssdev); ++ omapdss_hdmi_display_set_timing(dssdev); ++ } ++ ++ mutex_unlock(&hdmi.hdmi_lock); ++} ++ ++static int hdmi_check_timings(struct omap_dss_device *dssdev, ++ struct omap_video_timings *timings) ++{ ++ int r = 0; ++ ++ DSSDBG("hdmi_check_timings\n"); ++ ++ mutex_lock(&hdmi.hdmi_lock); ++ ++ r = omapdss_hdmi_display_check_timing(dssdev, timings); ++ if (r) { ++ DSSERR("Timing cannot be applied\n"); ++ goto err; ++ } ++err: ++ mutex_unlock(&hdmi.hdmi_lock); ++ return r; ++} ++ ++static struct omap_dss_driver hdmi_driver = { ++ .probe = hdmi_panel_probe, ++ .remove = hdmi_panel_remove, ++ .enable = hdmi_panel_enable, ++ .disable = hdmi_panel_disable, ++ .suspend = hdmi_panel_suspend, ++ .resume = hdmi_panel_resume, ++ .get_timings = hdmi_get_timings, ++ .set_timings = hdmi_set_timings, ++ .check_timings = hdmi_check_timings, ++ .driver = { ++ .name = "hdmi_panel", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int hdmi_panel_init(void) ++{ ++ mutex_init(&hdmi.hdmi_lock); ++ ++ omap_dss_register_driver(&hdmi_driver); ++ ++ return 0; ++} ++ ++void hdmi_panel_exit(void) ++{ ++ omap_dss_unregister_driver(&hdmi_driver); ++ ++} +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-307-V5_Add_makefile_and_kconfig_changes_to_enable_HDMI_in_OMAP4.patch b/packages/linux/patches/linux-2.6.38-rc8-307-V5_Add_makefile_and_kconfig_changes_to_enable_HDMI_in_OMAP4.patch new file mode 100644 index 0000000000..f95348bc66 --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-307-V5_Add_makefile_and_kconfig_changes_to_enable_HDMI_in_OMAP4.patch @@ -0,0 +1,36 @@ +Signed-off-by: Mythri P K +--- + drivers/video/omap2/dss/Kconfig | 8 ++++++++ + drivers/video/omap2/dss/Makefile | 2 ++ + 2 files changed, 10 insertions(+), 0 deletions(-) + +diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig +index db01473..bfc5da0 100644 +--- a/drivers/video/omap2/dss/Kconfig ++++ b/drivers/video/omap2/dss/Kconfig +@@ -60,6 +60,14 @@ config OMAP2_DSS_VENC + help + OMAP Video Encoder support for S-Video and composite TV-out. + ++config OMAP4_DSS_HDMI ++ bool "HDMI support" ++ depends on ARCH_OMAP4 ++ default y ++ help ++ HDMI Interface. This adds the High Definition Multimedia Interface. ++ See http://www.hdmi.org/ for HDMI specification. ++ + config OMAP2_DSS_SDI + bool "SDI support" + depends on ARCH_OMAP3 +diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile +index 7db17b5..10d9d3b 100644 +--- a/drivers/video/omap2/dss/Makefile ++++ b/drivers/video/omap2/dss/Makefile +@@ -5,3 +5,5 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o + omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o + omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o + omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o ++omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \ ++ hdmi_omap4_panel.o +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-308-V5_Call_to_HDMI_module_init_to_register_driver.patch b/packages/linux/patches/linux-2.6.38-rc8-308-V5_Call_to_HDMI_module_init_to_register_driver.patch new file mode 100644 index 0000000000..75ca4de0c8 --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-308-V5_Call_to_HDMI_module_init_to_register_driver.patch @@ -0,0 +1,43 @@ +calling the platform registration of HDMI driver from core +during initialization. + +Signed-off-by: Mythri P K +--- + drivers/video/omap2/dss/core.c | 9 +++++++++ + 1 files changed, 9 insertions(+), 0 deletions(-) + +diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c +index c2f930b..1aa2ed1 100644 +--- a/drivers/video/omap2/dss/core.c ++++ b/drivers/video/omap2/dss/core.c +@@ -209,6 +209,12 @@ static int omap_dss_probe(struct platform_device *pdev) + goto err_dsi; + } + ++ r = hdmi_init_platform_driver(); ++ if (r) { ++ DSSERR("Failed to initialize hdmi\n"); ++ goto err_hdmi; ++ } ++ + r = dss_initialize_debugfs(); + if (r) + goto err_debugfs; +@@ -238,6 +244,8 @@ static int omap_dss_probe(struct platform_device *pdev) + err_register: + dss_uninitialize_debugfs(); + err_debugfs: ++ hdmi_uninit_platform_driver(); ++err_hdmi: + dsi_uninit_platform_driver(); + err_dsi: + venc_uninit_platform_driver(); +@@ -263,6 +271,7 @@ static int omap_dss_remove(struct platform_device *pdev) + dispc_uninit_platform_driver(); + rfbi_uninit_platform_driver(); + dsi_uninit_platform_driver(); ++ hdmi_uninit_platform_driver(); + dss_uninit_platform_driver(); + + dss_uninit_overlays(pdev); +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-309-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4_SDP.patch b/packages/linux/patches/linux-2.6.38-rc8-309-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4_SDP.patch new file mode 100644 index 0000000000..491cc89a66 --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-309-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4_SDP.patch @@ -0,0 +1,118 @@ +Adding board file structure for display which adds the display +structure with HDMI as the default driver when the display init +is called. +HDMI GPIO configurations are also done in this file. + +Signed-off-by: Mythri P K +--- + arch/arm/mach-omap2/board-4430sdp.c | 75 +++++++++++++++++++++++++++++++++++ + 1 files changed, 75 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c +index 85805d4..f5fcc5f 100644 +--- a/arch/arm/mach-omap2/board-4430sdp.c ++++ b/arch/arm/mach-omap2/board-4430sdp.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include "mux.h" + #include "hsmmc.h" +@@ -47,6 +48,8 @@ + #define ETH_KS8851_QUART 138 + #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 + #define OMAP4_SFH7741_ENABLE_GPIO 188 ++#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ ++#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ + + static const int sdp4430_keymap[] = { + KEY(0, 0, KEY_E), +@@ -620,6 +623,76 @@ static void __init omap_sfh7741prox_init(void) + } + } + ++static void sdp4430_hdmi_mux_init(void) ++{ ++ /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ ++ omap_mux_init_signal("hdmi_hpd", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("hdmi_cec", ++ OMAP_PIN_INPUT_PULLUP); ++ /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ ++ omap_mux_init_signal("hdmi_ddc_scl", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("hdmi_ddc_sda", ++ OMAP_PIN_INPUT_PULLUP); ++} ++ ++static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) ++{ ++ int status; ++ ++ status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, ++ "hdmi_gpio_hpd"); ++ if (status) { ++ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); ++ return status; ++ } ++ status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, ++ "hdmi_gpio_ls_oe"); ++ if (status) { ++ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); ++ goto error1; ++ } ++ ++ return 0; ++ ++error1: ++ gpio_free(HDMI_GPIO_HPD); ++ ++ return status; ++} ++ ++static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) ++{ ++ gpio_free(HDMI_GPIO_LS_OE); ++ gpio_free(HDMI_GPIO_HPD); ++} ++ ++static struct omap_dss_device sdp4430_hdmi_device = { ++ .name = "hdmi", ++ .driver_name = "hdmi_panel", ++ .type = OMAP_DISPLAY_TYPE_HDMI, ++ .platform_enable = sdp4430_panel_enable_hdmi, ++ .platform_disable = sdp4430_panel_disable_hdmi, ++ .channel = OMAP_DSS_CHANNEL_DIGIT, ++}; ++ ++static struct omap_dss_device *sdp4430_dss_devices[] = { ++ &sdp4430_hdmi_device, ++}; ++ ++static struct omap_dss_board_info sdp4430_dss_data = { ++ .num_devices = ARRAY_SIZE(sdp4430_dss_devices), ++ .devices = sdp4430_dss_devices, ++ .default_device = &sdp4430_hdmi_device, ++}; ++ ++void omap_4430sdp_display_init(void) ++{ ++ sdp4430_hdmi_mux_init(); ++ omap_display_init(&sdp4430_dss_data); ++} ++ + #ifdef CONFIG_OMAP_MUX + static struct omap_board_mux board_mux[] __initdata = { + OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), +@@ -661,6 +734,8 @@ static void __init omap_4430sdp_init(void) + status = omap4_keyboard_init(&sdp4430_keypad_data); + if (status) + pr_err("Keypad initialization failed: %d\n", status); ++ ++ omap_4430sdp_display_init(); + } + + static void __init omap_4430sdp_map_io(void) +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-310-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4__PANDA.patch b/packages/linux/patches/linux-2.6.38-rc8-310-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4__PANDA.patch new file mode 100644 index 0000000000..9c4b26ec9e --- /dev/null +++ b/packages/linux/patches/linux-2.6.38-rc8-310-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4__PANDA.patch @@ -0,0 +1,117 @@ +Adding board file structure for display which adds the display +structure with HDMI as the default driver when the display init +is called. +HDMI GPIO configurations are also done in this file. + +Signed-off-by: Mythri P K +--- + arch/arm/mach-omap2/board-omap4panda.c | 74 ++++++++++++++++++++++++++++++++ + 1 files changed, 74 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c +index a94ce07..4869c0f 100644 +--- a/arch/arm/mach-omap2/board-omap4panda.c ++++ b/arch/arm/mach-omap2/board-omap4panda.c +@@ -34,6 +34,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -49,6 +50,8 @@ + #define GPIO_HUB_NRESET 62 + #define GPIO_WIFI_PMENA 43 + #define GPIO_WIFI_IRQ 53 ++#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ ++#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ + + /* wl127x BT, FM, GPS connectivity chip */ + static int wl1271_gpios[] = {46, -1, -1}; +@@ -467,6 +470,76 @@ static struct omap_board_mux board_mux[] __initdata = { + #define board_mux NULL + #endif + ++static void sdp4430_hdmi_mux_init(void) ++{ ++ /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ ++ omap_mux_init_signal("hdmi_hpd", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("hdmi_cec", ++ OMAP_PIN_INPUT_PULLUP); ++ /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ ++ omap_mux_init_signal("hdmi_ddc_scl", ++ OMAP_PIN_INPUT_PULLUP); ++ omap_mux_init_signal("hdmi_ddc_sda", ++ OMAP_PIN_INPUT_PULLUP); ++} ++ ++static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) ++{ ++ int status; ++ ++ status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, ++ "hdmi_gpio_hpd"); ++ if (status) { ++ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); ++ return status; ++ } ++ status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, ++ "hdmi_gpio_ls_oe"); ++ if (status) { ++ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); ++ goto error1; ++ } ++ ++ return 0; ++ ++error1: ++ gpio_free(HDMI_GPIO_HPD); ++ ++ return status; ++} ++ ++static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) ++{ ++ gpio_free(HDMI_GPIO_LS_OE); ++ gpio_free(HDMI_GPIO_HPD); ++} ++ ++static struct omap_dss_device sdp4430_hdmi_device = { ++ .name = "hdmi", ++ .driver_name = "hdmi_panel", ++ .type = OMAP_DISPLAY_TYPE_HDMI, ++ .platform_enable = sdp4430_panel_enable_hdmi, ++ .platform_disable = sdp4430_panel_disable_hdmi, ++ .channel = OMAP_DSS_CHANNEL_DIGIT, ++}; ++ ++static struct omap_dss_device *sdp4430_dss_devices[] = { ++ &sdp4430_hdmi_device, ++}; ++ ++static struct omap_dss_board_info sdp4430_dss_data = { ++ .num_devices = ARRAY_SIZE(sdp4430_dss_devices), ++ .devices = sdp4430_dss_devices, ++ .default_device = &sdp4430_hdmi_device, ++}; ++ ++void omap_panda_display_init(void) ++{ ++ sdp4430_hdmi_mux_init(); ++ omap_display_init(&sdp4430_dss_data); ++} ++ + static void __init omap4_panda_init(void) + { + int package = OMAP_PACKAGE_CBS; +@@ -485,6 +558,7 @@ static void __init omap4_panda_init(void) + omap4_twl6030_hsmmc_init(mmc); + omap4_ehci_init(); + usb_musb_init(&musb_board_data); ++ omap_panda_display_init(); + } + + static void __init omap4_panda_map_io(void) +-- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc7-716_mm-zero_swappiness.patch b/packages/linux/patches/linux-2.6.38-rc8-716_mm-zero_swappiness.patch similarity index 100% rename from packages/linux/patches/linux-2.6.38-rc7-716_mm-zero_swappiness.patch rename to packages/linux/patches/linux-2.6.38-rc8-716_mm-zero_swappiness.patch diff --git a/packages/mediacenter/xbmc-addon-settings/source/addon.xml b/packages/mediacenter/xbmc-addon-settings/source/addon.xml index 762ef3bdf9..619195bc94 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/addon.xml +++ b/packages/mediacenter/xbmc-addon-settings/source/addon.xml @@ -1,7 +1,7 @@ diff --git a/packages/mediacenter/xbmc-addon-settings/source/default.py b/packages/mediacenter/xbmc-addon-settings/source/default.py index 3b53988753..7a63754c0a 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/default.py +++ b/packages/mediacenter/xbmc-addon-settings/source/default.py @@ -27,7 +27,7 @@ __author__ = "OpenELEC" __url__ = "http://www.openelec.tv" __svn_url__ = "" __credits__ = "" -__version__ = "0.0.5" +__version__ = "0.0.6" __XBMC_Revision__ = "22240" __settings__ = xbmcaddon.Addon(id='os.openelec.settings') diff --git a/packages/mediacenter/xbmc-addon-settings/source/resources/language/Dutch/strings.xml b/packages/mediacenter/xbmc-addon-settings/source/resources/language/Dutch/strings.xml index b70575ba49..d6011553c9 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/resources/language/Dutch/strings.xml +++ b/packages/mediacenter/xbmc-addon-settings/source/resources/language/Dutch/strings.xml @@ -6,7 +6,7 @@ Toetsenbord Toetsenbord layout Systeem update - Auto update + Systeem update LCD/VFD Driver Te gebruiken LCD Driver Services na slaapstand diff --git a/packages/mediacenter/xbmc-addon-settings/source/resources/language/English/strings.xml b/packages/mediacenter/xbmc-addon-settings/source/resources/language/English/strings.xml index 68a83ae828..18fd4a628c 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/resources/language/English/strings.xml +++ b/packages/mediacenter/xbmc-addon-settings/source/resources/language/English/strings.xml @@ -6,7 +6,7 @@ Keyboard Keyboardlayout System Update - Auto update + System Update LCD/VFD LCD Driver to use Wakeup diff --git a/packages/mediacenter/xbmc-addon-settings/source/resources/language/French/strings.xml b/packages/mediacenter/xbmc-addon-settings/source/resources/language/French/strings.xml index de677a2ebd..8487fb6cc3 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/resources/language/French/strings.xml +++ b/packages/mediacenter/xbmc-addon-settings/source/resources/language/French/strings.xml @@ -6,7 +6,7 @@ Clavier Clavier Mise à jour du système - Mise à jour automatique + Mise à jour du système LCD/VFD Pilote LCD Retour de veille diff --git a/packages/mediacenter/xbmc-addon-settings/source/resources/language/German/strings.xml b/packages/mediacenter/xbmc-addon-settings/source/resources/language/German/strings.xml index df4dd6ead1..3f059bbe89 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/resources/language/German/strings.xml +++ b/packages/mediacenter/xbmc-addon-settings/source/resources/language/German/strings.xml @@ -6,7 +6,7 @@ Tastatur Tastaturlayout System Aktualisierung -Automatische Aktualisierung +System Aktualisierung LCD/VFD LCD Treiber Beim Aufwachen diff --git a/packages/mediacenter/xbmc-addon-settings/source/resources/language/Norwegian/strings.xml b/packages/mediacenter/xbmc-addon-settings/source/resources/language/Norwegian/strings.xml index 82f8579082..b38dab9841 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/resources/language/Norwegian/strings.xml +++ b/packages/mediacenter/xbmc-addon-settings/source/resources/language/Norwegian/strings.xml @@ -6,7 +6,7 @@ Tastatur SprÃ¥klayout Systemoppdateringer - Oppdater Automatisk + Systemoppdateringer LCD/VFD LCD Driver Vekke diff --git a/packages/mediacenter/xbmc-addon-settings/source/resources/settings.xml b/packages/mediacenter/xbmc-addon-settings/source/resources/settings.xml index 2cd1eb8625..07b64addd9 100644 --- a/packages/mediacenter/xbmc-addon-settings/source/resources/settings.xml +++ b/packages/mediacenter/xbmc-addon-settings/source/resources/settings.xml @@ -3,9 +3,9 @@ - - - + + + @@ -44,11 +44,11 @@ - - - - - + + + + + diff --git a/packages/mediacenter/xbmc-theme-Confluence/meta b/packages/mediacenter/xbmc-theme-Confluence/meta index 69685816f1..54db05951f 100644 --- a/packages/mediacenter/xbmc-theme-Confluence/meta +++ b/packages/mediacenter/xbmc-theme-Confluence/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="xbmc-theme-Confluence" -PKG_VERSION="Dharma-10.1-c8405db" +PKG_VERSION="10.1-Dharma" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/mediacenter/xbmc/meta b/packages/mediacenter/xbmc/meta index bccdf12252..4173fb3d3a 100644 --- a/packages/mediacenter/xbmc/meta +++ b/packages/mediacenter/xbmc/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="xbmc" -PKG_VERSION="Dharma-10.1-c8405db" +PKG_VERSION="10.1-Dharma" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-001-add_support_to_specify_GIT_REV-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-001-add_support_to_specify_GIT_REV-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-001-add_support_to_specify_GIT_REV-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-001-add_support_to_specify_GIT_REV-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-002-arm_fixes-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-002-arm_fixes-0.1.patch new file mode 100644 index 0000000000..a5dd29e7ff --- /dev/null +++ b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-002-arm_fixes-0.1.patch @@ -0,0 +1,56 @@ +diff -Naur xbmc-Dharma-10.1-c8405db/configure.in xbmc-Dharma-10.1-c8405db.patch/configure.in +--- xbmc-Dharma-10.1-c8405db/configure.in 2011-02-15 13:30:17.000000000 +0100 ++++ xbmc-Dharma-10.1-c8405db.patch/configure.in 2011-03-06 21:19:57.004648466 +0100 +@@ -448,30 +448,6 @@ + LIBS="$LIBS -framework CoreFoundation" + LIBS="$LIBS -framework DiskArbitration" + LIBS="$LIBS -framework ApplicationServices" +-elif expr "X$host_cpu" : 'Xarm.*' > /dev/null; then +- use_arch=arm +- CFLAGS="$CFLAGS -mfloat-abi=softfp -mno-apcs-stack-check" +- CXXFLAGS="$CXXFLAGS -mfloat-abi=softfp -mno-apcs-stack-check" +- FFMPEG_EXTRACFLAGS="-mfloat-abi=softfp" +- if test "$use_tegra" = "yes"; then +- # Compile for ARMv7a architecture, need to test gcc for vfpv3-d16 support +- SAVE_CFLAGS="$CFLAGS" +- CFLAGS="-mfpu=vfpv3-d16" +- AC_COMPILE_IFELSE( +- [int foo;], +- [ CFLAGS="$SAVE_CFLAGS -Wno-psabi -Wa,-march=armv7a -mtune=cortex-a9 -mfpu=vfpv3-d16 -mthumb-interwork" +- CXXFLAGS="$CXXFLAGS -Wno-psabi -Wa,-march=armv7a -mtune=cortex-a9 -mfpu=vfpv3-d16 -mthumb-interwork" +- FFMPEG_EXTRACFLAGS+=" -mtune=cortex-a9 -mfpu=vfpv3-d16" +- use_cpu=cortex-a9], +- [ CFLAGS="$SAVE_CFLAGS -Wa,-march=armv6 -mtune=cortex-a8 -mthumb-interwork" +- CXXFLAGS="$CXXFLAGS -Wa,-march=armv6 -mtune=cortex-a8 -mthumb-interwork" +- use_cpu=cortex-a8]) +- else +- # Compile for ARMv7a architecture, CortexA8 cpu and NEON coprocessor +- CFLAGS+=" -Wa,-march=armv7a -mcpu=cortex-a8 -mfpu=neon -mvectorize-with-neon-quad" +- CXXFLAGS+=" -Wa,-march=armv7a -mcpu=cortex-a8 -mfpu=neon -mvectorize-with-neon-quad" +- FFMPEG_EXTRACFLAGS+=" -mfpu=neon" +- fi + fi + + # Checks for library functions. +@@ -1646,6 +1622,7 @@ + --disable-static \ + `if test "$use_debug" = "no"; then echo --disable-debug; fi` \ + `if test "$cross_compiling" = "yes"; then echo --enable-cross-compile; fi` \ ++ `if test -n "$host_alias"; then echo --cross-prefix="${host_alias}-"; fi`\ + `if test "$use_arch" != "no"; then echo --arch=$use_arch; fi`\ + `if test "$use_cpu" != "no"; then echo --cpu=$use_cpu; fi`\ + --target-os=$(tolower $(uname -s)) \ +diff -Naur xbmc-Dharma-10.1-c8405db/Makefile.in xbmc-Dharma-10.1-c8405db.patch/Makefile.in +--- xbmc-Dharma-10.1-c8405db/Makefile.in 2011-02-15 13:30:17.000000000 +0100 ++++ xbmc-Dharma-10.1-c8405db.patch/Makefile.in 2011-03-04 19:52:52.500328225 +0100 +@@ -467,8 +467,8 @@ + xbmc/cores/DllLoader/exports/exports.a + + ifeq (arm, $(ARCH)) +-# Force external python2.5 for now! +-LIBS +=-lpython2.5 ++# Force external python2.6 for now! ++LIBS +=-lpython2.6 + endif + + xbmc.bin: $(OBJSXBMC) $(DYNOBJSXBMC) diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-011-add_xbmcvfs_module-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-011-add_xbmcvfs_module-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-011-add_xbmcvfs_module-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-011-add_xbmcvfs_module-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-201-let_select_XBMCProjectM-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-201-let_select_XBMCProjectM-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-201-let_select_XBMCProjectM-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-201-let_select_XBMCProjectM-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-202-let_select_RSXS-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-202-let_select_RSXS-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-202-let_select_RSXS-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-202-let_select_RSXS-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-301-correct_lzo_include-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-301-correct_lzo_include-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-301-correct_lzo_include-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-301-correct_lzo_include-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-302-dont_hardcode_usr_include-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-302-dont_hardcode_usr_include-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-302-dont_hardcode_usr_include-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-302-dont_hardcode_usr_include-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-303-WiiRemote_crosscompiling-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-303-WiiRemote_crosscompiling-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-303-WiiRemote_crosscompiling-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-303-WiiRemote_crosscompiling-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-303-fix_libdvd_xFLAGS-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-303-fix_libdvd_xFLAGS-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-303-fix_libdvd_xFLAGS-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-303-fix_libdvd_xFLAGS-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-321-CrystalHD_use_yuy2_to_yv12-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-321-CrystalHD_use_yuy2_to_yv12-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-321-CrystalHD_use_yuy2_to_yv12-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-321-CrystalHD_use_yuy2_to_yv12-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-401-we_dont_need_libXinerama-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-401-we_dont_need_libXinerama-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-401-we_dont_need_libXinerama-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-401-we_dont_need_libXinerama-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-402-enable_yasm_in_ffmpeg-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-402-enable_yasm_in_ffmpeg-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-402-enable_yasm_in_ffmpeg-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-402-enable_yasm_in_ffmpeg-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-403-openssl_only_needed_for_internal_python-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-403-openssl_only_needed_for_internal_python-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-403-openssl_only_needed_for_internal_python-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-403-openssl_only_needed_for_internal_python-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-451-full_splash-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-451-full_splash-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-451-full_splash-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-451-full_splash-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-452-change_lcd_content-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-452-change_lcd_content-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-452-change_lcd_content-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-452-change_lcd_content-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-452-ps3_remote_be_more_quiet-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-452-ps3_remote_be_more_quiet-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-452-ps3_remote_be_more_quiet-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-452-ps3_remote_be_more_quiet-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-462-add_remote_irtrans_mediacenter-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-462-add_remote_irtrans_mediacenter-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-462-add_remote_irtrans_mediacenter-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-462-add_remote_irtrans_mediacenter-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-463-add_remote_devinput-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-463-add_remote_devinput-0.1.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-463-add_remote_devinput-0.1.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-463-add_remote_devinput-0.1.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-901-advancedsettings_alwaysextractflags.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-901-advancedsettings_alwaysextractflags.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-901-advancedsettings_alwaysextractflags.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-901-advancedsettings_alwaysextractflags.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-902-advancedsettings_videolibrary.flattenmoviesets.patch b/packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-902-advancedsettings_videolibrary.flattenmoviesets.patch similarity index 100% rename from packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-902-advancedsettings_videolibrary.flattenmoviesets.patch rename to packages/mediacenter/xbmc/patches/xbmc-10.1-Dharma-902-advancedsettings_videolibrary.flattenmoviesets.patch diff --git a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-002-arm_remove_forced_python2.5-0.1.patch b/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-002-arm_remove_forced_python2.5-0.1.patch deleted file mode 100644 index dd64a43cc7..0000000000 --- a/packages/mediacenter/xbmc/patches/xbmc-Dharma-10.1-c8405db-002-arm_remove_forced_python2.5-0.1.patch +++ /dev/null @@ -1,15 +0,0 @@ -diff -Naur xbmc-Dharma-10.1-c8405db/Makefile.in xbmc-Dharma-10.1-c8405db.patch/Makefile.in ---- xbmc-Dharma-10.1-c8405db/Makefile.in 2011-02-15 13:30:17.000000000 +0100 -+++ xbmc-Dharma-10.1-c8405db.patch/Makefile.in 2011-02-15 13:55:18.511016755 +0100 -@@ -466,11 +466,6 @@ - xbmc/cores/DllLoader/exports/util/exports_utils.a \ - xbmc/cores/DllLoader/exports/exports.a - --ifeq (arm, $(ARCH)) --# Force external python2.5 for now! --LIBS +=-lpython2.5 --endif -- - xbmc.bin: $(OBJSXBMC) $(DYNOBJSXBMC) - ifeq ($(findstring osx,$(ARCH)), osx) - $(CXX) $(LDFLAGS) -o xbmc.bin -Wl,-all_load,-ObjC $(DYNOBJSXBMC) $(OBJSXBMC) $(LIBS) -rdynamic diff --git a/packages/mediacenter/xbmc/scripts/cputemp b/packages/mediacenter/xbmc/scripts/cputemp index 4e5d1a0721..0466da2272 100755 --- a/packages/mediacenter/xbmc/scripts/cputemp +++ b/packages/mediacenter/xbmc/scripts/cputemp @@ -25,8 +25,7 @@ TEMP="0" if [ -f /sys/class/thermal/thermal_zone0/temp ]; then TEMP=`echo "$(cat /sys/class/thermal/thermal_zone0/temp)/1000" |bc` elif [ -f /usr/bin/sensors ]; then -# TEMP=`/usr/bin/sensors -u | head -6 |grep "temp1_input"| awk '{print $2 }' |awk '{printf("%d\n",$1 + 0.5);}'` - TEMP=`/usr/bin/sensors -u | tail -n4 | grep temp1_input | awk '{print $2 }' |awk '{printf("%d\n",$1 + 0.5);}'` + TEMP=`/usr/bin/sensors -u | tail -n6 | grep temp1_input | awk '{print $2 }' |awk '{printf("%d\n",$1 + 0.5);}'` fi echo "${TEMP} C" diff --git a/packages/mediacenter/xbmc/sleep.d/01_update_videodb b/packages/mediacenter/xbmc/sleep.d/01_update_videodb index ee72bfee67..7b509b0c12 100755 --- a/packages/mediacenter/xbmc/sleep.d/01_update_videodb +++ b/packages/mediacenter/xbmc/sleep.d/01_update_videodb @@ -22,14 +22,13 @@ . /etc/profile -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - case "$1" in thaw|resume) ( - if [ -f "$OPENELEC_SETTINGS" ]; then - VIDEODBUPDATE=`grep WAKEUP_VIDEODBUPDATE $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - if [ "$VIDEODBUPDATE" = "true" ]; then + if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf + + if [ "$WAKEUP_VIDEODBUPDATE" = "true" ]; then usleep 5000000 xbmc-send --host=127.0.0.1 -a "UpdateLibrary(video)" fi diff --git a/packages/mediacenter/xbmc/sleep.d/02_update_musicdb b/packages/mediacenter/xbmc/sleep.d/02_update_musicdb index 7abc8c90da..22ab151a7b 100755 --- a/packages/mediacenter/xbmc/sleep.d/02_update_musicdb +++ b/packages/mediacenter/xbmc/sleep.d/02_update_musicdb @@ -22,14 +22,13 @@ . /etc/profile -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - case "$1" in thaw|resume) ( - if [ -f "$OPENELEC_SETTINGS" ]; then - MUSICDBUPDATE=`grep WAKEUP_MUSICDBUPDATE $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - if [ "$MUSICDBUPDATE" = "true" ]; then + if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf + + if [ "$WAKEUP_MUSICDBUPDATE" = "true" ]; then usleep 5000000 xbmc-send --host=127.0.0.1 -a "UpdateLibrary(music)" fi diff --git a/packages/mediacenter/xbmc/sleep.d/61xbmc_lirc b/packages/mediacenter/xbmc/sleep.d/61_xbmc_lirc similarity index 100% rename from packages/mediacenter/xbmc/sleep.d/61xbmc_lirc rename to packages/mediacenter/xbmc/sleep.d/61_xbmc_lirc diff --git a/packages/mediacenter/xbmc/sleep.d/62xbmc-lcd b/packages/mediacenter/xbmc/sleep.d/62_xbmc_lcd similarity index 100% rename from packages/mediacenter/xbmc/sleep.d/62xbmc-lcd rename to packages/mediacenter/xbmc/sleep.d/62_xbmc_lcd diff --git a/packages/multimedia/hts-tvheadend/init.d/81_tvheadend b/packages/multimedia/hts-tvheadend/init.d/81_tvheadend deleted file mode 100644 index f3076fa93a..0000000000 --- a/packages/multimedia/hts-tvheadend/init.d/81_tvheadend +++ /dev/null @@ -1,36 +0,0 @@ -################################################################################ -# Copyright (C) 2009-2010 OpenELEC.tv -# http://www.openelec.tv -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -# start tvheadend tv server -# -# runlevels: openelec, textmode - -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - -( - if [ -f "$OPENELEC_SETTINGS" ]; then - TVHEADEND_START=`grep TVHEADEND_START $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - - if [ "$TVHEADEND_START" = "true" ]; then - progress "starting TV Server" - tvheadend -C -s -f -u root -g root - fi - fi -)& diff --git a/packages/multimedia/hts-tvheadend/sleep.d/50tvheadend b/packages/multimedia/hts-tvheadend/sleep.d/50_tvheadend similarity index 81% rename from packages/multimedia/hts-tvheadend/sleep.d/50tvheadend rename to packages/multimedia/hts-tvheadend/sleep.d/50_tvheadend index e82b06300a..91f3a2fb0e 100755 --- a/packages/multimedia/hts-tvheadend/sleep.d/50tvheadend +++ b/packages/multimedia/hts-tvheadend/sleep.d/50_tvheadend @@ -22,16 +22,27 @@ . /etc/profile +LOCKDIR="/var/lock/" +LOCKFILE="tvheadend" + case "$1" in hibernate|suspend) if [ $(pidof tvheadend) ];then progress "Shutting down HTS TVHeadend for suspending..." + mkdir -p "$LOCKDIR" + touch "$LOCKDIR/$LOCKFILE" killall tvheadend fi ;; + thaw|resume) - . /etc/init.d/81_tvheadend + if [ -f "$LOCKDIR/$LOCKFILE" ];then + progress "Restarting HTS TVHeadend for wakeup..." + tvheadend -C -s -f -u root -g root + rm -rf "$LOCKDIR/$LOCKFILE" + fi ;; + *) exit $NA ;; esac diff --git a/packages/devel/talloc/build b/packages/multimedia/hts-tvheadend/udev.d/76-tvheadend.rules old mode 100755 new mode 100644 similarity index 75% rename from packages/devel/talloc/build rename to packages/multimedia/hts-tvheadend/udev.d/76-tvheadend.rules index 29759376ee..441b76235b --- a/packages/devel/talloc/build +++ b/packages/multimedia/hts-tvheadend/udev.d/76-tvheadend.rules @@ -1,5 +1,3 @@ -#!/bin/sh - ################################################################################ # This file is part of OpenELEC - http://www.openelec.tv # Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) @@ -20,17 +18,13 @@ # http://www.gnu.org/copyleft/gpl.html ################################################################################ -. config/options $1 +# only does something with adding "dvb" subsystem devices. +ACTION!="add|remove", GOTO="end" +SUBSYSTEM!="dvb", GOTO="end" +ENV{DVB_DEVICE_TYPE}!="frontend", GOTO="end" -cd $PKG_BUILD +# Start TVHeadend if dvb frontend is starting +ACTION=="add", RUN+="/usr/bin/tvheadend -C -s -f -u root -g root" +ACTION=="remove", RUN+="/usr/bin/killall tvheadend" -do_autoreconf -I libreplace -./configure --host=$TARGET_NAME \ - --build=$HOST_NAME \ - --prefix=/usr \ - --sysconfdir=/etc \ - --localstatedir=/var \ - -make - -$MAKEINSTALL +LABEL="end" diff --git a/packages/multimedia/libva/meta b/packages/multimedia/libva/meta index 8b1000bca5..9a79cf4eec 100644 --- a/packages/multimedia/libva/meta +++ b/packages/multimedia/libva/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="libva" -PKG_VERSION="20110214" +PKG_VERSION="bdc106e" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/network/SABnzbd/init.d/57_SABnzbd b/packages/network/SABnzbd/init.d/57_SABnzbd index 9a629b739d..a3ea66c28b 100644 --- a/packages/network/SABnzbd/init.d/57_SABnzbd +++ b/packages/network/SABnzbd/init.d/57_SABnzbd @@ -22,11 +22,10 @@ # # runlevels: openelec, textmode -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" ( - if [ -f "$OPENELEC_SETTINGS" ]; then - SABNZBD_START=`grep SABNZBD_START $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` + if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf if [ "$SABNZBD_START" = "true" ]; then diff --git a/packages/network/avahi/meta b/packages/network/avahi/meta index 3a211f3914..29d362d40d 100644 --- a/packages/network/avahi/meta +++ b/packages/network/avahi/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="avahi" -PKG_VERSION="0.6.28" +PKG_VERSION="0.6.29" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/network/cifs-utils/build b/packages/network/cifs-utils/build deleted file mode 100755 index 45000a9a45..0000000000 --- a/packages/network/cifs-utils/build +++ /dev/null @@ -1,37 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. config/options - -cd $PKG_BUILD -ac_cv_func_malloc_0_nonnull=yes \ -./configure --host=$TARGET_NAME \ - --build=$HOST_NAME \ - --prefix=/usr \ - --sysconfdir=/etc \ - --libexecdir=/usr/lib \ - --localstatedir=/var \ - --disable-cifsupcall \ - --disable-cifscreds \ - --with-libcap \ - -make diff --git a/packages/network/cifs-utils/install b/packages/network/cifs-utils/install deleted file mode 100755 index 2cfcc0c72a..0000000000 --- a/packages/network/cifs-utils/install +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. config/options $1 - -mkdir -p $INSTALL/sbin - cp $PKG_BUILD/mount.cifs $INSTALL/sbin diff --git a/packages/network/cifs-utils/meta b/packages/network/cifs-utils/meta deleted file mode 100644 index 5df114a051..0000000000 --- a/packages/network/cifs-utils/meta +++ /dev/null @@ -1,36 +0,0 @@ -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -PKG_NAME="cifs-utils" -PKG_VERSION="4.8.1" -PKG_REV="1" -PKG_ARCH="any" -PKG_LICENSE="GPL" -PKG_SITE="http://www.samba.org" -PKG_URL="ftp://ftp.samba.org/pub/linux-cifs/cifs-utils/$PKG_NAME-$PKG_VERSION.tar.bz2" -PKG_DEPENDS="libcap" -PKG_BUILD_DEPENDS="toolchain libcap" -PKG_PRIORITY="optional" -PKG_SECTION="network" -PKG_SHORTDESC="cifs-utils: a set of user-space tools to mount/umount CIFS filesystems" -PKG_LONGDESC="The in-kernel CIFS filesystem relies on a set of user-space tools. That package of tools is called cifs-utils. Although not really part of Samba proper, these tools were originally part of the Samba package. For several reasons, shipping these tools as part of Samba was problematic and it was deemed better to split them off into their own package." -PKG_IS_ADDON="no" - -PKG_AUTORECONF="yes" diff --git a/packages/network/connman/init.d/21_network b/packages/network/connman/init.d/21_network index 04fd72937d..83ba39a828 100644 --- a/packages/network/connman/init.d/21_network +++ b/packages/network/connman/init.d/21_network @@ -22,33 +22,19 @@ # # runlevels: openelec, installer, textmode -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - -if [ -f "$OPENELEC_SETTINGS" ]; then - HOSTNAME=`grep NET_HOSTNAME $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - NETWORK=`grep NET_NETWORK $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - IFACE=`grep NET_IFACE $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - IPADDRESS=`grep NET_IPADDRESS $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - PREFIXLEN=`grep NET_PREFIXLEN $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - GATEWAY=`grep NET_GATEWAY $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - DNS1=`grep NET_DNS1 $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - DNS2=`grep NET_DNS2 $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - DNS3=`grep NET_DNS3 $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - HIDDEN=`grep NET_HIDDEN $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - SSID=`grep NET_SSID $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - SECURITY=`grep NET_SECURITY $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - PASSPHRASE=`grep NET_PASSPHRASE $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` +if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf fi -[ -z "$HOSTNAME" ] && HOSTNAME="openelec" +[ -z "$NET_HOSTNAME" ] && NET_HOSTNAME="openelec" # setup hostname progress "Setup hostname" - echo "$HOSTNAME" > /proc/sys/kernel/hostname + echo "$NET_HOSTNAME" > /proc/sys/kernel/hostname # create /etc/hosts file, useful for gethostbyname(localhost) progress "creating /etc/hosts" - echo -e "127.0.0.1\tlocalhost $HOSTNAME" > /etc/hosts + echo -e "127.0.0.1\tlocalhost $NET_HOSTNAME" > /etc/hosts # add user defined hosts.conf entry's [ -f $HOME/.config/hosts.conf ] && cat $HOME/.config/hosts.conf >> /etc/hosts @@ -65,58 +51,58 @@ fi # NETWORK: ( LAN / WLAN ) for i in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19; do - if [ ! -f /sys/class/net/$IFACE/address ]; then - logger -t Connman "### [$i] cannot find /sys/class/net/$IFACE/address ###" + if [ ! -f /sys/class/net/$NET_IFACE/address ]; then + logger -t Connman "### [$i] cannot find /sys/class/net/$NET_IFACE/address ###" else - logger -t Connman "### [$i] found /sys/class/net/$IFACE/address, continue ###" - IFACE=`cat /sys/class/net/$IFACE/address | sed 's/://g'` + logger -t Connman "### [$i] found /sys/class/net/$NET_IFACE/address, continue ###" + NET_IFACE=`cat /sys/class/net/$NET_IFACE/address | sed 's/://g'` break fi usleep 500000 done - if [ "$NETWORK" = "WLAN" -a -n "$SSID" ]; then - SSID_HEX=`echo -n "$SSID" | od -tx1 | cut -c8-| tr -d ' \n'` + if [ "$NET_NETWORK" = "WLAN" -a -n "$NET_SSID" ]; then + NET_SSID_HEX=`echo -n "$NET_SSID" | od -tx1 | cut -c8-| tr -d ' \n'` - # SECURITY: ( NONE / WEP / PSK ) - if [ "$SECURITY" = "WEP" -a -n "$PASSPHRASE" ]; then + # NET_SECURITY: ( NONE / WEP / PSK ) + if [ "$NET_SECURITY" = "WEP" -a -n "$NET_PASSPHRASE" ]; then MODE="managed_wep" - elif [ "$SECURITY" = "PSK" -a -n "$PASSPHRASE" ]; then + elif [ "$NET_SECURITY" = "PSK" -a -n "$NET_PASSPHRASE" ]; then MODE="managed_psk" else MODE="managed_none" fi - if [ "$HIDDEN" = "true" ]; then - echo "[wifi_${IFACE}_hidden_${MODE}]" > $CONNMAN_PROFILE + if [ "$NET_HIDDEN" = "true" ]; then + echo "[wifi_${NET_IFACE}_hidden_${MODE}]" > $CONNMAN_PROFILE else - echo "[wifi_${IFACE}_${SSID_HEX}_${MODE}]" > $CONNMAN_PROFILE + echo "[wifi_${NET_IFACE}_${NET_SSID_HEX}_${MODE}]" > $CONNMAN_PROFILE fi - echo "Name=$SSID" >> $CONNMAN_PROFILE - echo "SSID=$SSID_HEX" >> $CONNMAN_PROFILE - [ -n "$PASSPHRASE" ] && echo "Passphrase=$PASSPHRASE" >> $CONNMAN_PROFILE + echo "Name=$NET_SSID" >> $CONNMAN_PROFILE + echo "SSID=$NET_SSID_HEX" >> $CONNMAN_PROFILE + [ -n "$NET_PASSPHRASE" ] && echo "Passphrase=$NET_PASSPHRASE" >> $CONNMAN_PROFILE echo "Favorite=true" >> $CONNMAN_PROFILE echo "AutoConnect=true" >> $CONNMAN_PROFILE else MODE="cable" - echo "[ethernet_${IFACE}_${MODE}]" > $CONNMAN_PROFILE + echo "[ethernet_${NET_IFACE}_${MODE}]" > $CONNMAN_PROFILE fi # IP settings - if [ -z "$IPADDRESS" ]; then + if [ -z "$NET_IPADDRESS" ]; then echo "IPv4.method=dhcp" >> $CONNMAN_PROFILE else echo "IPv4.method=manual" >> $CONNMAN_PROFILE - echo "IPv4.local_address=$IPADDRESS" >> $CONNMAN_PROFILE - [ -n "$PREFIXLEN" ] && echo "IPv4.netmask_prefixlen=$PREFIXLEN" >> $CONNMAN_PROFILE - [ -n "$GATEWAY" ] && echo "IPv4.gateway=$GATEWAY" >> $CONNMAN_PROFILE + echo "IPv4.local_address=$NET_IPADDRESS" >> $CONNMAN_PROFILE + [ -n "$NET_PREFIXLEN" ] && echo "IPv4.netmask_prefixlen=$NET_PREFIXLEN" >> $CONNMAN_PROFILE + [ -n "$NET_GATEWAY" ] && echo "IPv4.gateway=$NET_GATEWAY" >> $CONNMAN_PROFILE - [ -n "$DNS1" ] && NAMESERVER="$DNS1" - [ -n "$DNS2" ] && NAMESERVER="$NAMESERVER;$DNS2" - [ -n "$DNS3" ] && NAMESERVER="$NAMESERVER;$DNS3" - [ -n "$NAMESERVER" ] && echo "Nameservers=$NAMESERVER;" >> $CONNMAN_PROFILE + [ -n "$NET_DNS1" ] && NET_NAMESERVER="$NET_DNS1" + [ -n "$NET_DNS2" ] && NET_NAMESERVER="$NET_NAMESERVER;$NET_DNS2" + [ -n "$NET_DNS3" ] && NET_NAMESERVER="$NET_NAMESERVER;$NET_DNS3" + [ -n "$NET_NAMESERVER" ] && echo "Nameservers=$NET_NAMESERVER;" >> $CONNMAN_PROFILE fi # starting Connection manager diff --git a/packages/network/connman/install b/packages/network/connman/install index fa2f81ae9d..45d241328b 100755 --- a/packages/network/connman/install +++ b/packages/network/connman/install @@ -32,9 +32,6 @@ mkdir -p $INSTALL/etc mkdir -p $INSTALL/etc/dbus-1/system.d cp $PKG_BUILD/src/connman.conf $INSTALL/etc/dbus-1/system.d -mkdir -p $INSTALL/etc/pm/sleep.d - cp $PKG_DIR/sleep.d/* $INSTALL/etc/pm/sleep.d - mkdir -p $INSTALL/usr/sbin cp -P $PKG_BUILD/src/connmand $INSTALL/usr/sbin diff --git a/packages/network/connman/sleep.d/50connman b/packages/network/connman/sleep.d/50connman deleted file mode 100755 index 42e242a3a2..0000000000 --- a/packages/network/connman/sleep.d/50connman +++ /dev/null @@ -1,37 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. /etc/profile - -case "$1" in - hibernate|suspend) - if [ $(pidof connmand) ];then - progress "Shutting down Connection Manager for suspending..." - killall connmand - fi - ;; - thaw|resume) - . /etc/init.d/21_network - ;; - *) exit $NA - ;; -esac diff --git a/packages/network/dropbear/meta b/packages/network/dropbear/meta index 081bb6a460..c021700e9e 100644 --- a/packages/network/dropbear/meta +++ b/packages/network/dropbear/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="dropbear" -PKG_VERSION="0.52" +PKG_VERSION="0.53.1" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="MIT" diff --git a/packages/network/libnfsidmap/meta b/packages/network/libnfsidmap/meta deleted file mode 100644 index 59fccacb85..0000000000 --- a/packages/network/libnfsidmap/meta +++ /dev/null @@ -1,36 +0,0 @@ -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -PKG_NAME="libnfsidmap" -PKG_VERSION="0.24" -PKG_REV="1" -PKG_ARCH="any" -PKG_LICENSE="OSS" -PKG_SITE="http://www.citi.umich.edu/projects/nfsv4/linux/" -PKG_URL="http://www.citi.umich.edu/projects/nfsv4/linux/libnfsidmap/$PKG_NAME-$PKG_VERSION.tar.gz" -PKG_DEPENDS="" -PKG_BUILD_DEPENDS="toolchain" -PKG_PRIORITY="optional" -PKG_SECTION="network" -PKG_SHORTDESC="libnfsidmap: Library to help mapping id's, mainly for NFSv4" -PKG_LONGDESC="Library to help mapping id's, mainly for NFSv4." -PKG_IS_ADDON="no" - -PKG_AUTORECONF="yes" diff --git a/packages/network/netmount/config/netmount.conf.sample b/packages/network/netmount/config/netmount.conf.sample index d475827566..d11f0a4c9e 100644 --- a/packages/network/netmount/config/netmount.conf.sample +++ b/packages/network/netmount/config/netmount.conf.sample @@ -30,12 +30,12 @@ # # - "service" can be "nfs" for NFS mounts or "cifs" for CIFS (Samba) mounts # - Please use an "|" as delimiter +# - Please use an "," as delimiter for mountoptions # - Don't use spaces in usernames, passwords and options -# - for NFS mounts there is no support for options # - be aware of the different syntax for NFS shares # - Local mountpoints should only be on /storage # # Examples: # cifs | //192.168.1.44/videos | /storage/mount/videos | username=user,pass=secret # cifs | //192.168.1.44/tv shows | /storage/mount/tvshows | username=user,pass=secret -# nfs | 192.168.1.44:/videos | /storage/mount/videos +# nfs | 192.168.1.44:/videos | /storage/mount/videos | rw diff --git a/packages/network/netmount/meta b/packages/network/netmount/meta index b03d47fae3..f28a5ba08b 100644 --- a/packages/network/netmount/meta +++ b/packages/network/netmount/meta @@ -25,7 +25,7 @@ PKG_ARCH="any" PKG_LICENSE="GPL" PKG_SITE="http://www.openelec.tv" PKG_URL="" -PKG_DEPENDS="cifs-utils nfs-utils sshfs-fuse connman" +PKG_DEPENDS="sshfs-fuse connman" PKG_BUILD_DEPENDS="toolchain" PKG_PRIORITY="optional" PKG_SECTION="tools" diff --git a/packages/network/netmount/scripts/netmount b/packages/network/netmount/scripts/netmount index 49487d93da..bcf2b9da89 100755 --- a/packages/network/netmount/scripts/netmount +++ b/packages/network/netmount/scripts/netmount @@ -39,10 +39,10 @@ IFS=" mkdir -p $MOUNTPOINT case "$SERVICE" in cifs) - mount.cifs "$SHARE" "$MOUNTPOINT" -o "$OPTIONS" > /dev/null 2>&1 & + mount "$SHARE" "$MOUNTPOINT" -o "$OPTIONS" > /dev/null 2>&1 & ;; nfs) - mount.nfs "$SHARE" "$MOUNTPOINT" > /dev/null 2>&1 & + mount "$SHARE" "$MOUNTPOINT" -o nolock,"$OPTIONS" > /dev/null 2>&1 & ;; esac done diff --git a/packages/network/nfs-utils/build b/packages/network/nfs-utils/build deleted file mode 100755 index 2c0ce5791e..0000000000 --- a/packages/network/nfs-utils/build +++ /dev/null @@ -1,58 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. config/options $1 - -CFLAGS_FOR_BUILD="$HOST_CFLAGS" -CXXFLAGS_FOR_BUILD="$HOST_CXXFLAGS" -CPPFLAGS_FOR_BUILD="$HOST_CPPFLAGS" -LDFLAGS_FOR_BUILD="$HOST_LDFLAGS" - -cd $PKG_BUILD -libblkid_is_recent="yes" \ -./configure --host=$TARGET_NAME \ - --build=$HOST_NAME \ - --prefix=/usr \ - --sysconfdir=/etc \ - --disable-static \ - --enable-shared \ - --with-sysroot="$SYSROOT_PREFIX/usr" \ - --enable-nfsv3 \ - --enable-nfsv4 \ - --disable-nfsv41 \ - --disable-gss \ - --disable-kprefix \ - --enable-uuid \ - --enable-mount \ - --disable-tirpc \ - --disable-ipv6 \ - --enable-mountconfig \ - --without-tcp-wrappers \ - --without-krb5 \ - --disable-caps \ - --enable-largefile \ - --with-mountfile=/etc/nfsmounts.conf \ - --with-gnu-ld - -make - -sed -e "s,#!/bin/sh -p,#!/bin/sh,g" -i utils/statd/start-statd \ No newline at end of file diff --git a/packages/network/nfs-utils/config/protocols b/packages/network/nfs-utils/config/protocols deleted file mode 100644 index 97f366d24a..0000000000 --- a/packages/network/nfs-utils/config/protocols +++ /dev/null @@ -1,154 +0,0 @@ -# /etc/protocols: -# $Id: protocols,v 1.5 2006/10/11 15:39:11 pknirsch Exp $ -# -# Internet (IP) protocols -# -# from: @(#)protocols 5.1 (Berkeley) 4/17/89 -# -# Updated for NetBSD based on RFC 1340, Assigned Numbers (July 1992). -# -# See also http://www.iana.org/assignments/protocol-numbers - -ip 0 IP # internet protocol, pseudo protocol number -hopopt 0 HOPOPT # hop-by-hop options for ipv6 -icmp 1 ICMP # internet control message protocol -igmp 2 IGMP # internet group management protocol -ggp 3 GGP # gateway-gateway protocol -ipencap 4 IP-ENCAP # IP encapsulated in IP (officially ``IP'') -st 5 ST # ST datagram mode -tcp 6 TCP # transmission control protocol -cbt 7 CBT # CBT, Tony Ballardie -egp 8 EGP # exterior gateway protocol -igp 9 IGP # any private interior gateway (Cisco: for IGRP) -bbn-rcc 10 BBN-RCC-MON # BBN RCC Monitoring -nvp 11 NVP-II # Network Voice Protocol -pup 12 PUP # PARC universal packet protocol -argus 13 ARGUS # ARGUS -emcon 14 EMCON # EMCON -xnet 15 XNET # Cross Net Debugger -chaos 16 CHAOS # Chaos -udp 17 UDP # user datagram protocol -mux 18 MUX # Multiplexing protocol -dcn 19 DCN-MEAS # DCN Measurement Subsystems -hmp 20 HMP # host monitoring protocol -prm 21 PRM # packet radio measurement protocol -xns-idp 22 XNS-IDP # Xerox NS IDP -trunk-1 23 TRUNK-1 # Trunk-1 -trunk-2 24 TRUNK-2 # Trunk-2 -leaf-1 25 LEAF-1 # Leaf-1 -leaf-2 26 LEAF-2 # Leaf-2 -rdp 27 RDP # "reliable datagram" protocol -irtp 28 IRTP # Internet Reliable Transaction Protocol -iso-tp4 29 ISO-TP4 # ISO Transport Protocol Class 4 -netblt 30 NETBLT # Bulk Data Transfer Protocol -mfe-nsp 31 MFE-NSP # MFE Network Services Protocol -merit-inp 32 MERIT-INP # MERIT Internodal Protocol -dccp 33 DCCP # Datagram Congestion Control Protocol -3pc 34 3PC # Third Party Connect Protocol -idpr 35 IDPR # Inter-Domain Policy Routing Protocol -xtp 36 XTP # Xpress Tranfer Protocol -ddp 37 DDP # Datagram Delivery Protocol -idpr-cmtp 38 IDPR-CMTP # IDPR Control Message Transport Proto -tp++ 39 TP++ # TP++ Transport Protocol -il 40 IL # IL Transport Protocol -ipv6 41 IPv6 # IPv6 -sdrp 42 SDRP # Source Demand Routing Protocol -ipv6-route 43 IPv6-Route # Routing Header for IPv6 -ipv6-frag 44 IPv6-Frag # Fragment Header for IPv6 -idrp 45 IDRP # Inter-Domain Routing Protocol -rsvp 46 RSVP # Resource ReSerVation Protocol -gre 47 GRE # Generic Routing Encapsulation -dsr 48 DSR # Dynamic Source Routing Protocol -bna 49 BNA # BNA -esp 50 ESP # Encap Security Payload -ah 51 AH # Authentication Header -i-nlsp 52 I-NLSP # Integrated Net Layer Security TUBA -swipe 53 SWIPE # IP with Encryption -narp 54 NARP # NBMA Address Resolution Protocol -mobile 55 MOBILE # IP Mobility -tlsp 56 TLSP # Transport Layer Security Protocol -skip 57 SKIP # SKIP -ipv6-icmp 58 IPv6-ICMP # ICMP for IPv6 -ipv6-nonxt 59 IPv6-NoNxt # No Next Header for IPv6 -ipv6-opts 60 IPv6-Opts # Destination Options for IPv6 -# 61 # any host internal protocol -cftp 62 CFTP # CFTP -# 63 # any local network -sat-expak 64 SAT-EXPAK # SATNET and Backroom EXPAK -kryptolan 65 KRYPTOLAN # Kryptolan -rvd 66 RVD # MIT Remote Virtual Disk Protocol -ippc 67 IPPC # Internet Pluribus Packet Core -# 68 # any distributed file system -sat-mon 69 SAT-MON # SATNET Monitoring -visa 70 VISA # VISA Protocol -ipcv 71 IPCV # Internet Packet Core Utility -cpnx 72 CPNX # Computer Protocol Network Executive -cphb 73 CPHB # Computer Protocol Heart Beat -wsn 74 WSN # Wang Span Network -pvp 75 PVP # Packet Video Protocol -br-sat-mon 76 BR-SAT-MON # Backroom SATNET Monitoring -sun-nd 77 SUN-ND # SUN ND PROTOCOL-Temporary -wb-mon 78 WB-MON # WIDEBAND Monitoring -wb-expak 79 WB-EXPAK # WIDEBAND EXPAK -iso-ip 80 ISO-IP # ISO Internet Protocol -vmtp 81 VMTP # Versatile Message Transport -secure-vmtp 82 SECURE-VMTP # SECURE-VMTP -vines 83 VINES # VINES -ttp 84 TTP # TTP -nsfnet-igp 85 NSFNET-IGP # NSFNET-IGP -dgp 86 DGP # Dissimilar Gateway Protocol -tcf 87 TCF # TCF -eigrp 88 EIGRP # Enhanced Interior Routing Protocol (Cisco) -ospf 89 OSPFIGP # Open Shortest Path First IGP -sprite-rpc 90 Sprite-RPC # Sprite RPC Protocol -larp 91 LARP # Locus Address Resolution Protocol -mtp 92 MTP # Multicast Transport Protocol -ax.25 93 AX.25 # AX.25 Frames -ipip 94 IPIP # Yet Another IP encapsulation -micp 95 MICP # Mobile Internetworking Control Pro. -scc-sp 96 SCC-SP # Semaphore Communications Sec. Pro. -etherip 97 ETHERIP # Ethernet-within-IP Encapsulation -encap 98 ENCAP # Yet Another IP encapsulation -# 99 # any private encryption scheme -gmtp 100 GMTP # GMTP -ifmp 101 IFMP # Ipsilon Flow Management Protocol -pnni 102 PNNI # PNNI over IP -pim 103 PIM # Protocol Independent Multicast -aris 104 ARIS # ARIS -scps 105 SCPS # SCPS -qnx 106 QNX # QNX -a/n 107 A/N # Active Networks -ipcomp 108 IPComp # IP Payload Compression Protocol -snp 109 SNP # Sitara Networks Protocol -compaq-peer 110 Compaq-Peer # Compaq Peer Protocol -ipx-in-ip 111 IPX-in-IP # IPX in IP -vrrp 112 VRRP # Virtual Router Redundancy Protocol -pgm 113 PGM # PGM Reliable Transport Protocol -# 114 # any 0-hop protocol -l2tp 115 L2TP # Layer Two Tunneling Protocol -ddx 116 DDX # D-II Data Exchange -iatp 117 IATP # Interactive Agent Transfer Protocol -stp 118 STP # Schedule Transfer -srp 119 SRP # SpectraLink Radio Protocol -uti 120 UTI # UTI -smp 121 SMP # Simple Message Protocol -sm 122 SM # SM -ptp 123 PTP # Performance Transparency Protocol -isis 124 ISIS # ISIS over IPv4 -fire 125 FIRE -crtp 126 CRTP # Combat Radio Transport Protocol -crdup 127 CRUDP # Combat Radio User Datagram -sscopmce 128 SSCOPMCE -iplt 129 IPLT -sps 130 SPS # Secure Packet Shield -pipe 131 PIPE # Private IP Encapsulation within IP -sctp 132 SCTP # Stream Control Transmission Protocol -fc 133 FC # Fibre Channel -rsvp-e2e-ignore 134 RSVP-E2E-IGNORE -# 135 # Mobility Header -udplite 136 UDPLite -mpls-in-ip 137 MPLS-in-IP -# 138-252 Unassigned [IANA] -# 253 Use for experimentation and testing [RFC3692] -# 254 Use for experimentation and testing [RFC3692] -# 255 Reserved [IANA] diff --git a/packages/network/nfs-utils/init.d/05_nfsutils b/packages/network/nfs-utils/init.d/05_nfsutils deleted file mode 100644 index 48aeaf3924..0000000000 --- a/packages/network/nfs-utils/init.d/05_nfsutils +++ /dev/null @@ -1,35 +0,0 @@ -################################################################################ -# Copyright (C) 2009-2010 OpenELEC.tv -# http://www.openelec.tv -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -# create directories needed for nfs-utils -# -# runlevels: openelec, textmode - -( - progress "create directories needed for nfs-utils" - - install -m 755 -o rpcuser -g rpcuser -d /var/lib/nfs - install -m 755 -o rpcuser -g rpcuser -d /var/lib/nfs/sm - install -m 755 -o rpcuser -g rpcuser -d /var/lib/nfs/sm.bak - touch /var/lib/nfs/etab && chown rpcuser:rpcuser /var/lib/nfs/etab - touch /var/lib/nfs/rmtab && chown rpcuser:rpcuser /var/lib/nfs/rmtab - touch /var/lib/nfs/state && chown rpcuser:rpcuser /var/lib/nfs/state - touch /var/lib/nfs/xtab && chown rpcuser:rpcuser /var/lib/nfs/xtab -)& diff --git a/packages/network/nfs-utils/install b/packages/network/nfs-utils/install deleted file mode 100755 index e5dd29e39c..0000000000 --- a/packages/network/nfs-utils/install +++ /dev/null @@ -1,40 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. config/options $1 - -add_user rpcuser x 29 29 "RPC Service User" "/var/lib/nfs" "/bin/sh" -add_group rpcuser 29 - -mkdir -p $INSTALL/sbin - cp $PKG_BUILD/utils/mount/mount.nfs $INSTALL/sbin/ - ln -sf mount.nfs $INSTALL/sbin/mount.nfs4 - ln -sf mount.nfs $INSTALL/sbin/umount.nfs - ln -sf mount.nfs $INSTALL/sbin/umount.nfs4 - -mkdir -p $INSTALL/usr/sbin - cp $PKG_BUILD/utils/statd/statd $INSTALL/usr/sbin/rpc.statd - cp $PKG_BUILD/utils/statd/start-statd $INSTALL/usr/sbin/ - chmod +x $INSTALL/usr/sbin/start-statd - -mkdir -p $INSTALL/etc - cp $PKG_DIR/config/protocols $INSTALL/etc diff --git a/packages/network/nfs-utils/meta b/packages/network/nfs-utils/meta deleted file mode 100644 index f2c1cdc748..0000000000 --- a/packages/network/nfs-utils/meta +++ /dev/null @@ -1,36 +0,0 @@ -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -PKG_NAME="nfs-utils" -PKG_VERSION="1.2.3" -PKG_REV="1" -PKG_ARCH="any" -PKG_LICENSE="OSS" -PKG_SITE="http://nfs.sourceforge.net/" -PKG_URL="$SOURCEFORGE_SRC/nfs/nfs-utils/$PKG_VERSION/$PKG_NAME-$PKG_VERSION.tar.bz2" -PKG_DEPENDS="libevent libnfsidmap portmap util-linux" -PKG_BUILD_DEPENDS="toolchain libevent libnfsidmap util-linux" -PKG_PRIORITY="optional" -PKG_SECTION="network" -PKG_SHORTDESC="nfs-utils: Linux NFS client and server utilities" -PKG_LONGDESC="The nfs-utils package provides a daemon for the kernel NFS server and related tools, which provides a much higher level of performance than the traditional Linux NFS server used by most users. This package also contains the showmount program. Showmount queries the mount daemon on a remote host for information about the NFS (Network File System) server on the remote host. For example, showmount can display the clients which are mounted on that host." -PKG_IS_ADDON="no" - -PKG_AUTORECONF="yes" diff --git a/packages/network/nfs-utils/patches/nfs-utils-1.2.3-cross.patch b/packages/network/nfs-utils/patches/nfs-utils-1.2.3-cross.patch deleted file mode 100644 index 57c2f035c1..0000000000 --- a/packages/network/nfs-utils/patches/nfs-utils-1.2.3-cross.patch +++ /dev/null @@ -1,46 +0,0 @@ -diff -Naur nfs-utils-1.1.0-old/tools/locktest/Makefile.am nfs-utils-1.1.0-new/tools/locktest/Makefile.am ---- nfs-utils-1.1.0-old/tools/locktest/Makefile.am 2007-05-10 20:40:57.000000000 -0700 -+++ nfs-utils-1.1.0-new/tools/locktest/Makefile.am 2007-08-11 19:18:59.000000000 -0700 -@@ -5,8 +5,8 @@ - - noinst_PROGRAMS = testlk - testlk_SOURCES = testlk.c --testlk_CFLAGS=$(CFLAGS_FOR_BUILD) --testlk_CPPFLAGS=$(CPPFLAGS_FOR_BUILD) --testlk_LDFLAGS=$(LDFLAGS_FOR_BUILD) -+CFLAGS=$(CFLAGS_FOR_BUILD) -+CPPFLAGS=$(CPPFLAGS_FOR_BUILD) -+LDFLAGS=$(LDFLAGS_FOR_BUILD) - - MAINTAINERCLEANFILES = Makefile.in -diff -Naur nfs-utils-1.1.0-old/tools/rpcdebug/Makefile.am nfs-utils-1.1.0-new/tools/rpcdebug/Makefile.am ---- nfs-utils-1.1.0-old/tools/rpcdebug/Makefile.am 2007-05-10 20:40:57.000000000 -0700 -+++ nfs-utils-1.1.0-new/tools/rpcdebug/Makefile.am 2007-08-11 19:19:37.000000000 -0700 -@@ -8,8 +8,8 @@ - - sbin_PROGRAMS = rpcdebug - rpcdebug_SOURCES = rpcdebug.c --rpcdebug_CFLAGS=$(CFLAGS_FOR_BUILD) --rpcdebug_CPPFLAGS=$(CPPFLAGS_FOR_BUILD) -I$(top_srcdir)/support/include --rpcdebug_LDFLAGS=$(LDFLAGS_FOR_BUILD) -+CFLAGS=$(CFLAGS_FOR_BUILD) -+CPPFLAGS=$(CPPFLAGS_FOR_BUILD) -I$(top_srcdir)/support/include -+LDFLAGS=$(LDFLAGS_FOR_BUILD) - - MAINTAINERCLEANFILES = Makefile.in -diff -Naur nfs-utils-1.1.0-old/tools/rpcgen/Makefile.am nfs-utils-1.1.0-new/tools/rpcgen/Makefile.am ---- nfs-utils-1.1.0-old/tools/rpcgen/Makefile.am 2007-05-10 20:40:57.000000000 -0700 -+++ nfs-utils-1.1.0-new/tools/rpcgen/Makefile.am 2007-08-11 19:19:57.000000000 -0700 -@@ -9,9 +9,9 @@ - rpc_util.c rpc_sample.c rpc_output.h rpc_parse.h \ - rpc_scan.h rpc_util.h - --rpcgen_CFLAGS=$(CFLAGS_FOR_BUILD) --rpcgen_CPPLAGS=$(CPPFLAGS_FOR_BUILD) --rpcgen_LDFLAGS=$(LDFLAGS_FOR_BUILD) -+CFLAGS=$(CFLAGS_FOR_BUILD) -+CPPLAGS=$(CPPFLAGS_FOR_BUILD) -+LDFLAGS=$(LDFLAGS_FOR_BUILD) - - MAINTAINERCLEANFILES = Makefile.in - diff --git a/packages/network/portmap/build b/packages/network/portmap/build deleted file mode 100755 index 5efb4d6557..0000000000 --- a/packages/network/portmap/build +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. config/options $1 - -cd $PKG_BUILD -make FACILITY=LOG_AUTH \ - ZOMBIES='-DIGNORE_SIGCHLD -Dlint' \ - LIBS="-lnsl" \ - AUX="" \ - HOSTS_ACCESS="" \ - diff --git a/packages/network/portmap/init.d/54_portmap b/packages/network/portmap/init.d/54_portmap deleted file mode 100644 index 08ee2a7b26..0000000000 --- a/packages/network/portmap/init.d/54_portmap +++ /dev/null @@ -1,28 +0,0 @@ -################################################################################ -# Copyright (C) 2009-2010 OpenELEC.tv -# http://www.openelec.tv -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -# starting portmap -# -# runlevels: openelec, textmode - -( - progress "starting portmap" - portmap -)& \ No newline at end of file diff --git a/packages/network/portmap/install b/packages/network/portmap/install deleted file mode 100755 index 5afa135c98..0000000000 --- a/packages/network/portmap/install +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -################################################################################ -# This file is part of OpenELEC - http://www.openelec.tv -# Copyright (C) 2009-2011 Stephan Raue (stephan@openelec.tv) -# -# This Program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This Program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with OpenELEC.tv; see the file COPYING. If not, write to -# the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. -# http://www.gnu.org/copyleft/gpl.html -################################################################################ - -. config/options $1 - -mkdir -p $INSTALL/sbin - cp $PKG_BUILD/portmap $INSTALL/sbin/ - -mkdir -p $INSTALL/usr/sbin - cp $PKG_BUILD/pmap_set $INSTALL/usr/sbin/ - cp $PKG_BUILD/pmap_dump $INSTALL/usr/sbin/ diff --git a/packages/network/portmap/patches/portmap-4-errno.patch b/packages/network/portmap/patches/portmap-4-errno.patch deleted file mode 100644 index bd83ac863e..0000000000 --- a/packages/network/portmap/patches/portmap-4-errno.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- portmap_4/portmap.c.old 1996-05-31 09:52:59.000000000 -0400 -+++ portmap_4/portmap.c 2002-12-13 11:44:16.000000000 -0500 -@@ -94,6 +94,7 @@ - #ifdef SYSV40 - #include - #endif -+#include - - extern char *strerror(); - #include -@@ -124,7 +125,6 @@ - static void callit(); - struct pmaplist *pmaplist; - int debugging = 0; --extern int errno; - - #include "pmap_check.h" - diff --git a/packages/network/portmap/patches/portmap-4-linux.patch b/packages/network/portmap/patches/portmap-4-linux.patch deleted file mode 100644 index c29b3d570f..0000000000 --- a/packages/network/portmap/patches/portmap-4-linux.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- portmap_4/Makefile.orig Fri May 31 09:50:40 1996 -+++ portmap_4/Makefile Fri Aug 9 17:40:43 1996 -@@ -67,9 +67,9 @@ - - SHELL = /bin/sh - --COPT = -Dconst= -Dperror=xperror $(HOSTS_ACCESS) $(CHECK_PORT) \ -+COPT = -Dconst= $(HOSTS_ACCESS) $(CHECK_PORT) \ - $(SYS) -DFACILITY=$(FACILITY) $(ULONG) $(ZOMBIES) $(SA_LEN) --CFLAGS = $(COPT) -O $(NSARCHS) $(SETPGRP) -+CFLAGS = $(COPT) $(RPM_OPT_FLAGS) $(NSARCHS) $(SETPGRP) - OBJECTS = portmap.o pmap_check.o from_local.o $(AUX) - - all: portmap pmap_dump pmap_set ---- portmap_4/Makefile.bad 1996-05-31 09:50:40.000000000 -0400 -+++ portmap_4/Makefile 2002-12-12 09:54:00.000000000 -0500 -@@ -74,8 +74,8 @@ - - all: portmap pmap_dump pmap_set - --portmap: $(OBJECTS) $(WRAP_DIR)/libwrap.a -- $(CC) $(CFLAGS) -o $@ $(OBJECTS) $(WRAP_DIR)/libwrap.a $(LIBS) -+portmap: $(OBJECTS) -+ $(CC) $(CFLAGS) -o $@ $(OBJECTS) $(LIBS) - - pmap_dump: pmap_dump.c - $(CC) $(CFLAGS) -o $@ $? $(LIBS) diff --git a/packages/network/portmap/patches/portmap-4-loopback.patch b/packages/network/portmap/patches/portmap-4-loopback.patch deleted file mode 100644 index 5234e7ef56..0000000000 --- a/packages/network/portmap/patches/portmap-4-loopback.patch +++ /dev/null @@ -1,51 +0,0 @@ ---- portmap_4/portmap.c.orig 2004-08-12 10:48:13.405000000 -0400 -+++ portmap_4/portmap.c 2004-08-12 10:58:13.666000000 -0400 -@@ -126,6 +126,7 @@ - static void callit(); - struct pmaplist *pmaplist; - int debugging = 0; -+int localhost_only = 0; - - #include "pmap_check.h" - -@@ -140,13 +141,17 @@ - int len = sizeof(struct sockaddr_in); - register struct pmaplist *pml; - -- while ((c = getopt(argc, argv, "dv")) != EOF) { -+ while ((c = getopt(argc, argv, "dlv")) != EOF) { - switch (c) { - - case 'd': - debugging = 1; - break; - -+ case 'l': -+ localhost_only = 1; -+ break; -+ - case 'v': - verboselog = 1; - break; -@@ -154,6 +159,7 @@ - default: - (void) fprintf(stderr, "usage: %s [-dv]\n", argv[0]); - (void) fprintf(stderr, "-d: debugging mode\n"); -+ (void) fprintf(stderr, "-l: listen on localhost only\n"); - (void) fprintf(stderr, "-v: verbose logging\n"); - exit(1); - } -@@ -176,7 +182,12 @@ - exit(1); - } - -- addr.sin_addr.s_addr = 0; -+ if (localhost_only) { -+ addr.sin_addr.s_addr = htonl(INADDR_LOOPBACK); -+ syslog(LOG_NOTICE, "Only binding to LOOPBACK address!"); -+ } else { -+ addr.sin_addr.s_addr = 0; -+ } - addr.sin_family = AF_INET; - addr.sin_port = htons(PMAPPORT); - if (bind(sock, (struct sockaddr *)&addr, len) != 0) { diff --git a/packages/network/portmap/patches/portmap-4-pie.patch b/packages/network/portmap/patches/portmap-4-pie.patch deleted file mode 100644 index ee22eb769e..0000000000 --- a/packages/network/portmap/patches/portmap-4-pie.patch +++ /dev/null @@ -1,42 +0,0 @@ ---- portmap_4/Makefile.pie 2003-10-28 20:18:32.000000000 -0800 -+++ portmap_4/Makefile 2003-10-28 20:18:32.000000000 -0800 -@@ -74,8 +74,11 @@ - - all: portmap pmap_dump pmap_set - -+$(OBJECTS): %.o: %.c -+ $(CC) $(CFLAGS) -fpie -c $< -+ - portmap: $(OBJECTS) -- $(CC) $(CFLAGS) -o $@ $(OBJECTS) $(LIBS) -+ $(CC) $(CFLAGS) -o $@ -pie $(OBJECTS) $(LIBS) - - pmap_dump: pmap_dump.c - $(CC) $(CFLAGS) -o $@ $? $(LIBS) ---- portmap_4/pmap_check.h.pie 2003-10-28 20:26:34.000000000 -0800 -+++ portmap_4/pmap_check.h 2003-10-28 20:26:49.000000000 -0800 -@@ -6,6 +6,6 @@ - extern int check_setunset(); - extern int check_privileged_port(); - extern int check_callit(); --extern int verboselog; --extern int allow_severity; --extern int deny_severity; -+extern int verboselog __attribute__ ((visibility ("hidden"))); -+extern int allow_severity __attribute__ ((visibility ("hidden"))); -+extern int deny_severity __attribute__ ((visibility ("hidden"))); ---- portmap_4/pmap_check.c.pie 2003-10-28 20:27:38.000000000 -0800 -+++ portmap_4/pmap_check.c 2003-10-28 20:27:40.000000000 -0800 -@@ -63,9 +63,9 @@ - - static void logit(); - static void toggle_verboselog(); --int verboselog = 0; --int allow_severity = LOG_INFO; --int deny_severity = LOG_WARNING; -+int verboselog __attribute ((visibility ("hidden"))) = 0; -+int allow_severity __attribute ((visibility ("hidden"))) = LOG_INFO; -+int deny_severity __attribute ((visibility ("hidden"))) = LOG_WARNING; - - /* A handful of macros for "readability". */ - diff --git a/packages/network/portmap/patches/portmap-4-sigpipe.patch b/packages/network/portmap/patches/portmap-4-sigpipe.patch deleted file mode 100644 index dba7cf4bb1..0000000000 --- a/packages/network/portmap/patches/portmap-4-sigpipe.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- portmap_4/portmap.c.sigpipe Sun Feb 11 17:45:11 2001 -+++ portmap_4/portmap.c Sun Feb 11 17:45:51 2001 -@@ -228,6 +228,9 @@ - #else - (void)signal(SIGCHLD, reap); - #endif -+ /* Dying on SIGPIPE doesn't help anyone */ -+ (void)signal(SIGPIPE, SIG_IGN); -+ - svc_run(); - syslog(LOG_ERR, "run_svc returned unexpectedly"); - abort(); diff --git a/packages/network/samba/build b/packages/network/samba/build index 6e80cd6550..481a8ef616 100755 --- a/packages/network/samba/build +++ b/packages/network/samba/build @@ -55,7 +55,7 @@ sh autogen.sh --enable-pie \ --enable-relro \ --enable-shared-libs \ - --enable-external-libtalloc \ + --disable-external-libtalloc \ --disable-external-libtdb \ --disable-fam \ --disable-dnssd \ @@ -65,7 +65,7 @@ sh autogen.sh --disable-netapi \ --disable-dmalloc \ --with-fhs \ - --with-libtalloc \ + --without-libtalloc \ --without-libtdb \ --without-libnetapi \ --with-libsmbclient \ diff --git a/packages/network/samba/meta b/packages/network/samba/meta index bb8bb4822d..7186b06586 100644 --- a/packages/network/samba/meta +++ b/packages/network/samba/meta @@ -19,14 +19,14 @@ ################################################################################ PKG_NAME="samba" -PKG_VERSION="3.5.6" +PKG_VERSION="3.5.8" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" PKG_SITE="http://www.samba.org" PKG_URL="http://samba.org/samba/ftp/stable/$PKG_NAME-$PKG_VERSION.tar.gz" -PKG_DEPENDS="libiconv sqlite talloc connman" -PKG_BUILD_DEPENDS="toolchain libiconv sqlite talloc" +PKG_DEPENDS="libiconv sqlite connman" +PKG_BUILD_DEPENDS="toolchain libiconv sqlite" PKG_PRIORITY="optional" PKG_SECTION="network" PKG_SHORTDESC="samba: The free SMB / CIFS fileserver and client" diff --git a/packages/network/samba/patches/samba-3.5.6-010_crosscompile-0.1.patch b/packages/network/samba/patches/samba-3.5.8-010_crosscompile-0.1.patch similarity index 100% rename from packages/network/samba/patches/samba-3.5.6-010_crosscompile-0.1.patch rename to packages/network/samba/patches/samba-3.5.8-010_crosscompile-0.1.patch diff --git a/packages/network/samba/scripts/52_samba b/packages/network/samba/scripts/52_samba index 1b3475be6a..62ea24a57f 100644 --- a/packages/network/samba/scripts/52_samba +++ b/packages/network/samba/scripts/52_samba @@ -22,11 +22,9 @@ # # runlevels: openelec, textmode -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - ( - if [ -f "$OPENELEC_SETTINGS" ]; then - SAMBA_START=`grep SAMBA_START $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` + if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf if [ "$SAMBA_START" = "true" ]; then diff --git a/packages/network/transmission/init.d/58_transmission b/packages/network/transmission/init.d/58_transmission index 06b937c427..741e9051b7 100644 --- a/packages/network/transmission/init.d/58_transmission +++ b/packages/network/transmission/init.d/58_transmission @@ -22,15 +22,9 @@ # # runlevels: openelec, textmode -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - ( - if [ -f "$OPENELEC_SETTINGS" ]; then - TRANSMISSION_START=`grep TRANSMISSION_START $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - TRANSMISSION_AUTH=`grep TRANSMISSION_AUTH $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - TRANSMISSION_USER=`grep TRANSMISSION_USER $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - TRANSMISSION_PWD=`grep TRANSMISSION_PWD $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` - TRANSMISSION_IP=`grep TRANSMISSION_IP $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` + if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf if [ "$TRANSMISSION_START" = "true" ]; then diff --git a/packages/python/devel/pygobject/meta b/packages/python/devel/pygobject/meta index e78fb815e0..42262e0942 100644 --- a/packages/python/devel/pygobject/meta +++ b/packages/python/devel/pygobject/meta @@ -19,12 +19,12 @@ ################################################################################ PKG_NAME="pygobject" -PKG_VERSION="2.26.0" +PKG_VERSION="2.28.0" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="LGPL" PKG_SITE="http://www.pygtk.org/" -PKG_URL="http://ftp.gnome.org/pub/GNOME/sources/pygobject/2.26/$PKG_NAME-$PKG_VERSION.tar.bz2" +PKG_URL="http://ftp.gnome.org/pub/GNOME/sources/pygobject/2.28/$PKG_NAME-$PKG_VERSION.tar.bz2" PKG_DEPENDS="Python glib libffi" PKG_BUILD_DEPENDS="toolchain Python glib libffi" PKG_PRIORITY="optional" diff --git a/packages/security/gnutls/meta b/packages/security/gnutls/meta index 75d7c82126..3dc3f8e862 100644 --- a/packages/security/gnutls/meta +++ b/packages/security/gnutls/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="gnutls" -PKG_VERSION="2.10.4" +PKG_VERSION="2.10.5" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="LGPL" diff --git a/packages/security/openssl/build b/packages/security/openssl/build index 9e1d3b03c7..30e7976668 100755 --- a/packages/security/openssl/build +++ b/packages/security/openssl/build @@ -31,6 +31,9 @@ case $TARGET_ARCH in x86_64) TARGET=linux-x86_64 ;; + arm) + TARGET=linux-armv4 + ;; powerpc) TARGET=linux-ppc ;; diff --git a/packages/security/polkit/install b/packages/security/polkit/install index 17f35c598e..22081bb06d 100755 --- a/packages/security/polkit/install +++ b/packages/security/polkit/install @@ -55,7 +55,6 @@ mkdir -p $INSTALL/usr/lib mkdir -p $INSTALL/usr/lib/polkit-1/extensions cp -P $PKG_BUILD/src/nullbackend/.libs/*.so $INSTALL/usr/lib/polkit-1/extensions - cp -P $PKG_BUILD/src/programs/.libs/*.so $INSTALL/usr/lib/polkit-1/extensions mkdir -p $INSTALL/usr/lib/polkit-1 cp -P $PKG_BUILD/src/polkitagent/.libs/polkit-agent-helper-1 $INSTALL/usr/lib/polkit-1 diff --git a/packages/security/polkit/meta b/packages/security/polkit/meta index b108f3e7d6..396aff420d 100644 --- a/packages/security/polkit/meta +++ b/packages/security/polkit/meta @@ -19,14 +19,14 @@ ################################################################################ PKG_NAME="polkit" -PKG_VERSION="0.99" +PKG_VERSION="0.101" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="MIT" PKG_SITE="http://gitweb.freedesktop.org/?p=PolicyKit.git;a=summary" PKG_URL="http://hal.freedesktop.org/releases/$PKG_NAME-$PKG_VERSION.tar.gz" PKG_DEPENDS="zlib sg3_utils glib udev eggdbus expat" -PKG_BUILD_DEPENDS="toolchain zlib sg3_utils glib udev eggdbus expat" +PKG_BUILD_DEPENDS="toolchain zlib sg3_utils glib udev eggdbus expat gobject-introspection" PKG_PRIORITY="optional" PKG_SECTION="security" PKG_SHORTDESC="polkit: Authorization Toolkit" diff --git a/packages/sysutils/ConsoleKit/meta b/packages/sysutils/ConsoleKit/meta index 834192ea6c..e05f57d946 100644 --- a/packages/sysutils/ConsoleKit/meta +++ b/packages/sysutils/ConsoleKit/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="ConsoleKit" -PKG_VERSION="0.4.3" +PKG_VERSION="0.4.4" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/sysutils/busybox/config/busybox.conf b/packages/sysutils/busybox/config/busybox.conf index 892bea5fa3..8b78bc8847 100644 --- a/packages/sysutils/busybox/config/busybox.conf +++ b/packages/sysutils/busybox/config/busybox.conf @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Busybox version: 1.18.3 -# Sat Feb 19 14:18:19 2011 +# Tue Mar 8 17:11:29 2011 # CONFIG_HAVE_DOT_CONFIG=y @@ -49,7 +49,7 @@ CONFIG_FEATURE_SUID=y # CONFIG_FEATURE_PREFER_APPLETS is not set CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe" CONFIG_FEATURE_SYSLOG=y -# CONFIG_FEATURE_HAVE_RPC is not set +CONFIG_FEATURE_HAVE_RPC=y # # Build Options @@ -558,14 +558,14 @@ CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y CONFIG_MKSWAP=y CONFIG_FEATURE_MKSWAP_UUID=y CONFIG_MORE=y -# CONFIG_MOUNT is not set -# CONFIG_FEATURE_MOUNT_FAKE is not set -# CONFIG_FEATURE_MOUNT_VERBOSE is not set -# CONFIG_FEATURE_MOUNT_HELPERS is not set -# CONFIG_FEATURE_MOUNT_LABEL is not set -# CONFIG_FEATURE_MOUNT_NFS is not set -# CONFIG_FEATURE_MOUNT_CIFS is not set -# CONFIG_FEATURE_MOUNT_FLAGS is not set +CONFIG_MOUNT=y +CONFIG_FEATURE_MOUNT_FAKE=y +CONFIG_FEATURE_MOUNT_VERBOSE=y +CONFIG_FEATURE_MOUNT_HELPERS=y +CONFIG_FEATURE_MOUNT_LABEL=y +CONFIG_FEATURE_MOUNT_NFS=y +CONFIG_FEATURE_MOUNT_CIFS=y +CONFIG_FEATURE_MOUNT_FLAGS=y # CONFIG_FEATURE_MOUNT_FSTAB is not set # CONFIG_PIVOT_ROOT is not set CONFIG_RDATE=y @@ -578,10 +578,14 @@ CONFIG_RDATE=y # CONFIG_SWAPONOFF is not set # CONFIG_FEATURE_SWAPON_PRI is not set # CONFIG_SWITCH_ROOT is not set -# CONFIG_UMOUNT is not set -# CONFIG_FEATURE_UMOUNT_ALL is not set -# CONFIG_FEATURE_MOUNT_LOOP is not set -# CONFIG_FEATURE_MOUNT_LOOP_CREATE is not set +CONFIG_UMOUNT=y +CONFIG_FEATURE_UMOUNT_ALL=y + +# +# Common options for mount/umount +# +CONFIG_FEATURE_MOUNT_LOOP=y +CONFIG_FEATURE_MOUNT_LOOP_CREATE=y # CONFIG_FEATURE_MTAB_SUPPORT is not set CONFIG_VOLUMEID=y diff --git a/packages/sysutils/busybox/init.d/00__base__ b/packages/sysutils/busybox/init.d/00__base__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/03_debugshell b/packages/sysutils/busybox/init.d/03_debugshell index ddd9df8803..b82564e271 100644 --- a/packages/sysutils/busybox/init.d/03_debugshell +++ b/packages/sysutils/busybox/init.d/03_debugshell @@ -32,6 +32,6 @@ if [ "$DEBUG" = "yes" ]; then echo "## ...... switch with ctrl-alt-f$TTY ...... ##" echo "###########################################" - exec /sbin/getty -n -l /bin/bash 38400 tty$TTY & + exec /sbin/getty -n -l /bin/sh 38400 tty$TTY & fi diff --git a/packages/sysutils/busybox/init.d/04_userconfig b/packages/sysutils/busybox/init.d/04_userconfig index 1a57c214b6..3467e4796b 100644 --- a/packages/sysutils/busybox/init.d/04_userconfig +++ b/packages/sysutils/busybox/init.d/04_userconfig @@ -23,19 +23,28 @@ # # runlevels: openelec, textmode -progress "copy userconfig and samples" +OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" if [ -d /usr/config ]; then - cd /usr/config - $IONICE mkdir -p /storage/.config + progress "copy userconfig and samples" - for dir in `find . -type d`; do - mkdir -p /storage/.config/$dir - done + cd /usr/config + mkdir -p /storage/.config - for file in `find . -type f`; do - if [ ! -f /storage/.config/$file ]; then - cp $file /storage/.config/$file - fi - done + for dir in `find . -type d`; do + mkdir -p /storage/.config/$dir + done + + for file in `find . -type f`; do + if [ ! -f /storage/.config/$file ]; then + cp $file /storage/.config/$file + fi + done +fi + +if [ -f "$OPENELEC_SETTINGS" ]; then + progress "creating system settings" + + mkdir -p /var/config + cat "$OPENELEC_SETTINGS" | awk -F\" '{print $2"=\""$4"\""}' | sed '/^=/d' > /var/config/settings.conf fi diff --git a/packages/sysutils/busybox/init.d/10__drivers__ b/packages/sysutils/busybox/init.d/10__drivers__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/20__network__ b/packages/sysutils/busybox/init.d/20__network__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/30__services__ b/packages/sysutils/busybox/init.d/30__services__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/50__netservices__ b/packages/sysutils/busybox/init.d/50__netservices__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/60__input__ b/packages/sysutils/busybox/init.d/60__input__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/70__xorg__ b/packages/sysutils/busybox/init.d/70__xorg__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/80__media__ b/packages/sysutils/busybox/init.d/80__media__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/90__target__ b/packages/sysutils/busybox/init.d/90__target__ deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/packages/sysutils/busybox/init.d/99_shell b/packages/sysutils/busybox/init.d/99_shell index 0d73433493..155d8ce538 100644 --- a/packages/sysutils/busybox/init.d/99_shell +++ b/packages/sysutils/busybox/init.d/99_shell @@ -31,5 +31,5 @@ echo "## ...... switch with ctrl-alt-f$TTY ...... ##" echo "###########################################" while true; do - exec /sbin/getty -n -l /bin/bash 38400 tty$TTY + exec /sbin/getty -n -l /bin/sh 38400 tty$TTY done diff --git a/packages/sysutils/busybox/meta b/packages/sysutils/busybox/meta index dae1ba2ff2..fdad569d3f 100644 --- a/packages/sysutils/busybox/meta +++ b/packages/sysutils/busybox/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="busybox" -PKG_VERSION="1.18.3" +PKG_VERSION="1.18.4" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/sysutils/busybox/patches/busybox-1.18.3-buildsys.patch b/packages/sysutils/busybox/patches/busybox-1.18.3-buildsys.patch deleted file mode 100644 index 330b73fbb8..0000000000 --- a/packages/sysutils/busybox/patches/busybox-1.18.3-buildsys.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- busybox-1.18.3/Config.in -+++ busybox-1.18.3-buildsys/Config.in -@@ -126,7 +126,6 @@ config FEATURE_INSTALLER - config INSTALL_NO_USR - bool "Don't use /usr" - default n -- depends on FEATURE_INSTALLER - help - Disable use of /usr. busybox --install and "make install" - will install applets only to /bin and /sbin, diff --git a/packages/sysutils/busybox/patches/busybox-1.18.3-modutils24.patch b/packages/sysutils/busybox/patches/busybox-1.18.3-modutils24.patch deleted file mode 100644 index 2b13787f38..0000000000 --- a/packages/sysutils/busybox/patches/busybox-1.18.3-modutils24.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- busybox-1.18.3/modutils/modutils-24.c -+++ busybox-1.18.3-modutils24/modutils/modutils-24.c -@@ -2474,6 +2474,7 @@ new_process_module_arguments(struct obj_ - n = 0; - p = val; - while (*p != 0) { -+ char sv_ch; - char *endp; - - if (++n > max) -@@ -2482,14 +2483,17 @@ new_process_module_arguments(struct obj_ - switch (*pinfo) { - case 's': - len = strcspn(p, ","); -+ sv_ch = p[len]; - p[len] = 0; - obj_string_patch(f, sym->secidx, - loc - contents, p); - loc += tgt_sizeof_char_p; - p += len; -+ *p = sv_ch; - break; - case 'c': - len = strcspn(p, ","); -+ sv_ch = p[len]; - p[len] = 0; - if (len >= charssize) - bb_error_msg_and_die("string too long for %s (max %ld)", param, -@@ -2497,6 +2501,7 @@ new_process_module_arguments(struct obj_ - strcpy((char *) loc, p); - loc += charssize; - p += len; -+ *p = sv_ch; - break; - case 'b': - *loc++ = strtoul(p, &endp, 0); diff --git a/packages/sysutils/busybox/patches/busybox-1.18.3-wget.patch b/packages/sysutils/busybox/patches/busybox-1.18.3-wget.patch deleted file mode 100644 index 88cfc918ca..0000000000 --- a/packages/sysutils/busybox/patches/busybox-1.18.3-wget.patch +++ /dev/null @@ -1,128 +0,0 @@ ---- busybox-1.18.3/networking/wget.c -+++ busybox-1.18.3-wget/networking/wget.c -@@ -446,7 +446,7 @@ static FILE* prepare_ftp_session(FILE ** - - static void NOINLINE retrieve_file_data(FILE *dfp, int output_fd) - { -- char buf[512]; -+ char buf[4*1024]; /* made bigger to speed up local xfers */ - #if ENABLE_FEATURE_WGET_STATUSBAR || ENABLE_FEATURE_WGET_TIMEOUT - # if ENABLE_FEATURE_WGET_TIMEOUT - unsigned second_cnt; -@@ -455,7 +455,6 @@ static void NOINLINE retrieve_file_data( - - polldata.fd = fileno(dfp); - polldata.events = POLLIN | POLLPRI; -- ndelay_on(polldata.fd); - #endif - progress_meter(PROGRESS_START); - -@@ -464,6 +463,10 @@ static void NOINLINE retrieve_file_data( - - /* Loops only if chunked */ - while (1) { -+ -+#if ENABLE_FEATURE_WGET_STATUSBAR || ENABLE_FEATURE_WGET_TIMEOUT -+ ndelay_on(polldata.fd); -+#endif - while (1) { - int n; - unsigned rdsz; -@@ -493,22 +496,46 @@ static void NOINLINE retrieve_file_data( - progress_meter(PROGRESS_BUMP); - } - #endif -+ /* fread internally uses read loop, which in our case -+ * is usually exited when we get EAGAIN. -+ * In this case, libc sets error marker on the stream. -+ * Need to clear it before next fread to avoid possible -+ * rare false positive ferror below. Rare because usually -+ * fread gets more than zero bytes, and we don't fall -+ * into if (n <= 0) ... -+ */ -+ clearerr(dfp); -+ errno = 0; - n = safe_fread(buf, rdsz, dfp); -+ /* man fread: -+ * If error occurs, or EOF is reached, the return value -+ * is a short item count (or zero). -+ * fread does not distinguish between EOF and error. -+ */ - if (n <= 0) { -- if (ferror(dfp)) { -- /* perror will not work: ferror doesn't set errno */ -- bb_error_msg_and_die(bb_msg_read_error); -- } -- break; -+#if ENABLE_FEATURE_WGET_STATUSBAR || ENABLE_FEATURE_WGET_TIMEOUT -+ if (errno == EAGAIN) /* poll lied, there is no data? */ -+ continue; /* yes */ -+#endif -+ if (ferror(dfp)) -+ bb_perror_msg_and_die(bb_msg_read_error); -+ break; /* EOF, not error */ - } -+ - xwrite(output_fd, buf, n); - #if ENABLE_FEATURE_WGET_STATUSBAR - G.transferred += n; - progress_meter(PROGRESS_BUMP); - #endif -- if (G.got_clen) -+ if (G.got_clen) { - G.content_len -= n; -+ if (G.content_len == 0) -+ break; -+ } - } -+#if ENABLE_FEATURE_WGET_STATUSBAR || ENABLE_FEATURE_WGET_TIMEOUT -+ ndelay_off(polldata.fd); -+#endif - - if (!G.chunked) - break; -@@ -706,6 +733,11 @@ int wget_main(int argc UNUSED_PARAM, cha - fprintf(sfp, "Host: %s\r\nUser-Agent: %s\r\n", - target.host, user_agent); - -+ /* Ask server to close the connection as soon as we are done -+ * (IOW: we do not intend to send more requests) -+ */ -+ fprintf(sfp, "Connection: close\r\n"); -+ - #if ENABLE_FEATURE_WGET_AUTHENTICATION - if (target.user) { - fprintf(sfp, "Proxy-Authorization: Basic %s\r\n"+6, -@@ -719,22 +751,25 @@ int wget_main(int argc UNUSED_PARAM, cha - - if (G.beg_range) - fprintf(sfp, "Range: bytes=%"OFF_FMT"u-\r\n", G.beg_range); -+ - #if ENABLE_FEATURE_WGET_LONG_OPTIONS - if (extra_headers) - fputs(extra_headers, sfp); - - if (opt & WGET_OPT_POST_DATA) { - char *estr = URL_escape(post_data); -- fprintf(sfp, "Content-Type: application/x-www-form-urlencoded\r\n"); -- fprintf(sfp, "Content-Length: %u\r\n" "\r\n" "%s", -- (int) strlen(estr), estr); -- /*fprintf(sfp, "Connection: Keep-Alive\r\n\r\n");*/ -- /*fprintf(sfp, "%s\r\n", estr);*/ -+ fprintf(sfp, -+ "Content-Type: application/x-www-form-urlencoded\r\n" -+ "Content-Length: %u\r\n" -+ "\r\n" -+ "%s", -+ (int) strlen(estr), estr -+ ); - free(estr); - } else - #endif -- { /* If "Connection:" is needed, document why */ -- fprintf(sfp, /* "Connection: close\r\n" */ "\r\n"); -+ { -+ fprintf(sfp, "\r\n"); - } - - fflush(sfp); diff --git a/packages/sysutils/busybox/patches/busybox-1.18.3-00_halt_no_init.patch b/packages/sysutils/busybox/patches/busybox-1.18.4-00_halt_no_init.patch similarity index 100% rename from packages/sysutils/busybox/patches/busybox-1.18.3-00_halt_no_init.patch rename to packages/sysutils/busybox/patches/busybox-1.18.4-00_halt_no_init.patch diff --git a/packages/sysutils/busybox/patches/busybox-1.18.3-01_check_cc.patch b/packages/sysutils/busybox/patches/busybox-1.18.4-01_check_cc.patch similarity index 100% rename from packages/sysutils/busybox/patches/busybox-1.18.3-01_check_cc.patch rename to packages/sysutils/busybox/patches/busybox-1.18.4-01_check_cc.patch diff --git a/packages/sysutils/busybox/patches/busybox-1.18.3-02_user_modprobe.d_dir-0.1.patch b/packages/sysutils/busybox/patches/busybox-1.18.4-02_user_modprobe.d_dir-0.1.patch similarity index 100% rename from packages/sysutils/busybox/patches/busybox-1.18.3-02_user_modprobe.d_dir-0.1.patch rename to packages/sysutils/busybox/patches/busybox-1.18.4-02_user_modprobe.d_dir-0.1.patch diff --git a/packages/sysutils/grep/build b/packages/sysutils/grep/build index 3083fba999..1165217f0e 100755 --- a/packages/sysutils/grep/build +++ b/packages/sysutils/grep/build @@ -22,6 +22,8 @@ . config/options $1 +export LIBS="-liconv" + cd $PKG_BUILD ./configure --host=$TARGET_NAME \ --build=$HOST_NAME \ diff --git a/packages/sysutils/grep/meta b/packages/sysutils/grep/meta index 177abc7c77..6eaeac3b9b 100644 --- a/packages/sysutils/grep/meta +++ b/packages/sysutils/grep/meta @@ -25,8 +25,8 @@ PKG_ARCH="any" PKG_LICENSE="GPL" PKG_SITE="http://www.gnu.org/software/grep/" PKG_URL="ftp://sunsite.cnlab-switch.ch/mirror/gnu/grep/$PKG_NAME-$PKG_VERSION.tar.gz" -PKG_DEPENDS="pcre" -PKG_BUILD_DEPENDS="toolchain pcre" +PKG_DEPENDS="libiconv pcre" +PKG_BUILD_DEPENDS="toolchain libiconv pcre" PKG_PRIORITY="optional" PKG_SECTION="system" PKG_SHORTDESC="grep: This is GNU grep, the fastest grep in the west" diff --git a/packages/sysutils/lcdproc/init.d/63_lcdproc b/packages/sysutils/lcdproc/init.d/63_lcdproc index 8e7faff21b..68974c315c 100644 --- a/packages/sysutils/lcdproc/init.d/63_lcdproc +++ b/packages/sysutils/lcdproc/init.d/63_lcdproc @@ -22,11 +22,9 @@ # # runlevels: openelec, textmode -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - ( - if [ -f "$OPENELEC_SETTINGS" ]; then - LCD_DRIVER=`grep LCD_DRIVER $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` + if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf if [ ! "$LCD_DRIVER" = none ]; then diff --git a/packages/sysutils/sshfs-fuse/patches/sshfs-fuse-2.2_add_dropbear_compatibility-0.1.patch b/packages/sysutils/sshfs-fuse/patches/sshfs-fuse-2.2_add_dropbear_compatibility-0.1.patch new file mode 100644 index 0000000000..9df53d775a --- /dev/null +++ b/packages/sysutils/sshfs-fuse/patches/sshfs-fuse-2.2_add_dropbear_compatibility-0.1.patch @@ -0,0 +1,25 @@ +diff -Naur sshfs-fuse-2.2/sshfs.c sshfs-fuse-2.2.patch/sshfs.c +--- sshfs-fuse-2.2/sshfs.c 2008-10-20 14:10:09.000000000 +0200 ++++ sshfs-fuse-2.2.patch/sshfs.c 2011-03-03 21:23:02.721900708 +0100 +@@ -2920,7 +2920,7 @@ + return 1; + + case KEY_PORT: +- tmp = g_strdup_printf("-oPort=%s", arg + 2); ++ tmp = g_strdup_printf("-p %s", arg + 2); + ssh_add_arg(tmp); + g_free(tmp); + return 0; +@@ -3183,9 +3183,9 @@ + sshfs.ptyfd = -1; + sshfs.ptyslavefd = -1; + ssh_add_arg("ssh"); +- ssh_add_arg("-x"); +- ssh_add_arg("-a"); +- ssh_add_arg("-oClearAllForwardings=yes"); ++// ssh_add_arg("-x"); ++// ssh_add_arg("-a"); ++// ssh_add_arg("-oClearAllForwardings=yes"); + + if (fuse_opt_parse(&args, &sshfs, sshfs_opts, sshfs_opt_proc) == -1 || + parse_workarounds() == -1) diff --git a/packages/sysutils/udisks/patches/udisks-1.0.2-01-busybox_mount-0.1.patch b/packages/sysutils/udisks/patches/udisks-1.0.2-01-busybox_mount-0.1.patch new file mode 100644 index 0000000000..24567e8c35 --- /dev/null +++ b/packages/sysutils/udisks/patches/udisks-1.0.2-01-busybox_mount-0.1.patch @@ -0,0 +1,12 @@ +diff -Naur udisks-1.0.2/src/device.c udisks-1.0.2.patch/src/device.c +--- udisks-1.0.2/src/device.c 2010-11-06 17:41:23.000000000 +0100 ++++ udisks-1.0.2.patch/src/device.c 2011-03-08 23:25:46.382977610 +0100 +@@ -6307,7 +6307,7 @@ + options = prepend_default_mount_options (fsmo, caller_uid, given_options); + + /* validate mount options and check for authorizations */ +- s = g_string_new ("uhelper=udisks,nodev,nosuid"); ++ s = g_string_new ("nodev,nosuid"); + for (n = 0; options[n] != NULL; n++) + { + const char *option = options[n]; diff --git a/packages/sysutils/util-linux/build b/packages/sysutils/util-linux/build index a608be4f31..1f0997d61d 100755 --- a/packages/sysutils/util-linux/build +++ b/packages/sysutils/util-linux/build @@ -76,8 +76,6 @@ gt_cv_func_gnugettext1_libintl=no \ --without-selinux \ --without-audit -make -C mount mount -make -C mount umount make -C mount swapon make -C misc-utils blkid make -C sys-utils fstrim diff --git a/packages/sysutils/util-linux/install b/packages/sysutils/util-linux/install index 94eee4e547..f8b93f3987 100755 --- a/packages/sysutils/util-linux/install +++ b/packages/sysutils/util-linux/install @@ -22,10 +22,6 @@ . config/options $1 -mkdir -p $INSTALL/bin - cp $PKG_BUILD/mount/.libs/mount $INSTALL/bin - cp $PKG_BUILD/mount/.libs/umount $INSTALL/bin - mkdir -p $INSTALL/sbin cp $PKG_BUILD/misc-utils/.libs/blkid $INSTALL/sbin cp $PKG_BUILD/sys-utils/fstrim $INSTALL/sbin diff --git a/packages/tools/autoupdate/scripts/autoupdate.devel b/packages/tools/autoupdate/scripts/autoupdate.devel index 2e76ccbc35..2873fdfcc9 100755 --- a/packages/tools/autoupdate/scripts/autoupdate.devel +++ b/packages/tools/autoupdate/scripts/autoupdate.devel @@ -20,13 +20,13 @@ # http://www.gnu.org/copyleft/gpl.html ################################################################################ -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" TMP_DIR="$HOME/.xbmc/temp" if [ -f /etc/update.conf ]; then . /etc/update.conf -elif [ -f "$OPENELEC_SETTINGS" ]; then - AUTOUPDATE=`grep UPDATE_AUTO $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` +elif [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf + AUTOUPDATE="$UPDATE_AUTO" else exit 0 fi diff --git a/packages/tools/autoupdate/scripts/autoupdate.release b/packages/tools/autoupdate/scripts/autoupdate.release index e16401805e..2e67e1fcb5 100755 --- a/packages/tools/autoupdate/scripts/autoupdate.release +++ b/packages/tools/autoupdate/scripts/autoupdate.release @@ -20,13 +20,13 @@ # http://www.gnu.org/copyleft/gpl.html ################################################################################ -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" TMP_DIR="$HOME/.xbmc/temp" if [ -f /etc/update.conf ]; then . /etc/update.conf -elif [ -f "$OPENELEC_SETTINGS" ]; then - AUTOUPDATE=`grep UPDATE_AUTO $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` +elif [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf + AUTOUPDATE="$UPDATE_AUTO" else exit 0 fi diff --git a/packages/tools/autoupdate/sleep.d/90autoupdate b/packages/tools/autoupdate/sleep.d/90_autoupdate similarity index 100% rename from packages/tools/autoupdate/sleep.d/90autoupdate rename to packages/tools/autoupdate/sleep.d/90_autoupdate diff --git a/packages/tools/dialog/meta b/packages/tools/dialog/meta index 6e7f719728..53ee2998e2 100644 --- a/packages/tools/dialog/meta +++ b/packages/tools/dialog/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="dialog" -PKG_VERSION="1.1-20100428" +PKG_VERSION="1.1-20110302" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="GPL" diff --git a/packages/tools/installer/meta b/packages/tools/installer/meta index 01a10a9a8e..5f404cc573 100644 --- a/packages/tools/installer/meta +++ b/packages/tools/installer/meta @@ -25,7 +25,7 @@ PKG_ARCH="any" PKG_LICENSE="GPL" PKG_SITE="http://www.openelec.tv/" PKG_URL="" -PKG_DEPENDS="busybox dialog parted e2fsprogs syslinux flashrom" +PKG_DEPENDS="busybox dialog parted e2fsprogs $BOOTLOADER" PKG_BUILD_DEPENDS="toolchain" PKG_PRIORITY="optional" PKG_SECTION="tools" @@ -34,3 +34,7 @@ PKG_LONGDESC="OpenELEC.tv Install manager to install the system on any disk" PKG_IS_ADDON="no" PKG_AUTORECONF="no" + +if [ "$TARGET_ARCH" = "i386" -o "$TARGET_ARCH" = "x86_64" ]; then + PKG_DEPENDS="$PKG_DEPENDS flashrom" +fi \ No newline at end of file diff --git a/packages/network/libnfsidmap/build b/packages/tools/u-boot/build similarity index 57% rename from packages/network/libnfsidmap/build rename to packages/tools/u-boot/build index 2c2acbb431..cdb391d8ae 100755 --- a/packages/network/libnfsidmap/build +++ b/packages/tools/u-boot/build @@ -22,14 +22,34 @@ . config/options $1 +BOOT_CFG="$PROJECT_DIR/$PROJECT/bootloader/boot.cfg" + +unset LDFLAGS + +# dont use some optimizations because of problems + MAKEFLAGS=-j1 + +if [ -z "$UBOOT_CONFIG" ]; then + echo "$TARGET_PLATFORM does not define any u-boot configuration, aborting." + echo "Please add MACHINE_UBOOT_CONFIG to your platform meta file" + exit 1 +fi + cd $PKG_BUILD -./configure --host=$TARGET_NAME \ - --build=$HOST_NAME \ - --prefix=/usr \ - --sysconfdir=/etc \ - --disable-static \ - --enable-shared \ -make +make CROSS_COMPILE="$TARGET_PREFIX" ARCH="$TARGET_ARCH" "$UBOOT_CONFIG" +make CROSS_COMPILE="$TARGET_PREFIX" ARCH="$TARGET_ARCH" HOSTCC="$HOST_CC" HOSTSTRIP="true" -$MAKEINSTALL +mkdir -p $ROOT/$TOOLCHAIN/bin + cp tools/mkimage $ROOT/$TOOLCHAIN/bin + +if [ -r "$BOOT_CFG" ]; then + cp $BOOT_CFG boot.cfg + mkimage -A "$TARGET_ARCH" \ + -O u-boot \ + -T script \ + -C none \ + -n "$DISTRONAME Boot" \ + -d boot.cfg \ + boot.ini +fi diff --git a/packages/network/libnfsidmap/install b/packages/tools/u-boot/install similarity index 69% rename from packages/network/libnfsidmap/install rename to packages/tools/u-boot/install index 396345a7fa..031d04d25c 100755 --- a/packages/network/libnfsidmap/install +++ b/packages/tools/u-boot/install @@ -22,9 +22,19 @@ . config/options $1 -mkdir -p $INSTALL/usr/lib - cp -P $PKG_BUILD/.libs/libnfsidmap.so* $INSTALL/usr/lib/ +mkdir -p $INSTALL/usr/share/u-boot + cp $PKG_BUILD/u-boot.bin $INSTALL/usr/share/u-boot -mkdir -p $INSTALL/usr/lib/libnfsidmap - cp -P $PKG_BUILD/.libs/nsswitch.so $INSTALL/usr/lib/libnfsidmap/ - cp -P $PKG_BUILD/.libs/static.so $INSTALL/usr/lib/libnfsidmap/ +if [ -f "$PKG_BUILD/MLO" ]; then + cp $PKG_BUILD/MLO $INSTALL/usr/share/u-boot +fi + +if [ -f "$PKG_BUILD/boot.cfg" ]; then + cp $PKG_BUILD/boot.cfg $INSTALL/usr/share/u-boot +fi + +if [ -f "$PKG_BUILD/boot.ini" ]; then + cp $PKG_BUILD/boot.ini $INSTALL/usr/share/u-boot + # some boards read boot.scr by default + cp $PKG_BUILD/boot.ini $INSTALL/usr/share/u-boot/boot.scr +fi diff --git a/packages/network/portmap/meta b/packages/tools/u-boot/meta similarity index 67% rename from packages/network/portmap/meta rename to packages/tools/u-boot/meta index c8e8eab2d4..599bce607b 100644 --- a/packages/network/portmap/meta +++ b/packages/tools/u-boot/meta @@ -18,19 +18,19 @@ # http://www.gnu.org/copyleft/gpl.html ################################################################################ -PKG_NAME="portmap" -PKG_VERSION="4" +PKG_NAME="u-boot" +PKG_VERSION="2011.03-rc1" PKG_REV="1" -PKG_ARCH="any" -PKG_LICENSE="OSS" -PKG_SITE="ftp://ftp.porcupine.org/pub/security/" -PKG_URL="ftp://ftp.porcupine.org/pub/security/${PKG_NAME}_${PKG_VERSION}.tar.gz" +PKG_ARCH="arm" +PKG_LICENSE="GPL" +PKG_SITE="http://www.denx.de/wiki/U-Boot/WebHome" +PKG_URL="ftp://ftp.denx.de/pub/u-boot/$PKG_NAME-$PKG_VERSION.tar.bz2" PKG_DEPENDS="" PKG_BUILD_DEPENDS="toolchain" PKG_PRIORITY="optional" -PKG_SECTION="network" -PKG_SHORTDESC="portmap: RPC portmapper" -PKG_LONGDESC="This is an RPC portmapper that prevents theft of NIS (YP), NFS, and other sensitive information via the portmapper. As an option, the program supports access control in the style of the tcp wrapper (log_tcp) package." +PKG_SECTION="tools" +PKG_SHORTDESC="u-boot: Universal Bootloader project" +PKG_LONGDESC="Das U-Boot is a cross-platform bootloader for embedded systems, used as the default boot loader by several board vendors. It is intended to be easy to port and to debug, and runs on many supported architectures, including PPC, ARM, MIPS, x86, m68k, NIOS, and Microblaze." PKG_IS_ADDON="no" PKG_AUTORECONF="no" diff --git a/packages/tools/u-boot/patches/README b/packages/tools/u-boot/patches/README new file mode 100644 index 0000000000..18082d8db1 --- /dev/null +++ b/packages/tools/u-boot/patches/README @@ -0,0 +1,4 @@ +u-boot: add MMC SPL for OMAP4 patches by Aneesh V + +http://groups.google.com/group/x-loader/browse_frm/thread/ffa060e158ae220e +http://dev.omapzoom.org/?p=bootloader/u-boot.git;a=shortlog;h=refs/heads/omap_upstream_next \ No newline at end of file diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0001-mkimage-Add-OMAP-boot-image-support.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0001-mkimage-Add-OMAP-boot-image-support.patch new file mode 100644 index 0000000000..2373a86443 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0001-mkimage-Add-OMAP-boot-image-support.patch @@ -0,0 +1,380 @@ +From b295d8676ccb5b01d4ea7ba75ec6321a3c8837b7 Mon Sep 17 00:00:00 2001 +From: John Rigby +Date: Thu, 17 Feb 2011 19:43:43 +0530 +Subject: [PATCH 01/22] mkimage: Add OMAP boot image support + +Signed-off-by: John Rigby +--- + common/image.c | 1 + + include/image.h | 1 + + tools/Makefile | 2 + + tools/mkimage.c | 2 + + tools/mkimage.h | 1 + + tools/omapimage.c | 229 +++++++++++++++++++++++++++++++++++++++++++++++++++++ + tools/omapimage.h | 50 ++++++++++++ + 7 files changed, 286 insertions(+), 0 deletions(-) + create mode 100644 tools/omapimage.c + create mode 100644 tools/omapimage.h + +diff --git a/common/image.c b/common/image.c +index f63a2ff..4198d76 100644 +--- a/common/image.c ++++ b/common/image.c +@@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = { + { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, + { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, + { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, ++ { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP CH/GP Boot Image",}, + { -1, "", "", }, + }; + +diff --git a/include/image.h b/include/image.h +index 005e0d2..f74e2b9 100644 +--- a/include/image.h ++++ b/include/image.h +@@ -157,6 +157,7 @@ + #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ + #define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ + #define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ ++#define IH_TYPE_OMAPIMAGE 11 /* TI OMAP Config Header Image */ + + /* + * Compression Types +diff --git a/tools/Makefile b/tools/Makefile +index 623f908..a1c4ed7 100644 +--- a/tools/Makefile ++++ b/tools/Makefile +@@ -84,6 +84,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o + OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o + NOPED_OBJ_FILES-y += kwbimage.o + NOPED_OBJ_FILES-y += imximage.o ++NOPED_OBJ_FILES-y += omapimage.o + NOPED_OBJ_FILES-y += mkimage.o + OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o + NOPED_OBJ_FILES-y += os_support.o +@@ -180,6 +181,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ + $(obj)fit_image.o \ + $(obj)image.o \ + $(obj)imximage.o \ ++ $(obj)omapimage.o \ + $(obj)kwbimage.o \ + $(obj)md5.o \ + $(obj)mkimage.o \ +diff --git a/tools/mkimage.c b/tools/mkimage.c +index f5859d7..ec6d75e 100644 +--- a/tools/mkimage.c ++++ b/tools/mkimage.c +@@ -155,6 +155,8 @@ main (int argc, char **argv) + init_imx_image_type (); + /* Init FIT image generation/list support */ + init_fit_image_type (); ++ /* Init TI OMAP Boot image generation/list support */ ++ init_omap_image_type(); + /* Init Default image generation/list support */ + init_default_image_type (); + +diff --git a/tools/mkimage.h b/tools/mkimage.h +index 9033a7d..3b49645 100644 +--- a/tools/mkimage.h ++++ b/tools/mkimage.h +@@ -143,5 +143,6 @@ void init_kwb_image_type (void); + void init_imx_image_type (void); + void init_default_image_type (void); + void init_fit_image_type (void); ++void init_omap_image_type(void); + + #endif /* _MKIIMAGE_H_ */ +diff --git a/tools/omapimage.c b/tools/omapimage.c +new file mode 100644 +index 0000000..67fa056 +--- /dev/null ++++ b/tools/omapimage.c +@@ -0,0 +1,229 @@ ++/* ++ * (C) Copyright 2010 ++ * Linaro LTD, www.linaro.org ++ * Author: John Rigby ++ * Based on TI's signGP.c ++ * ++ * (C) Copyright 2009 ++ * Stefano Babic, DENX Software Engineering, sbabic@denx.de. ++ * ++ * (C) Copyright 2008 ++ * Marvell Semiconductor ++ * Written-by: Prafulla Wadaskar ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* Required to obtain the getline prototype from stdio.h */ ++#define _GNU_SOURCE ++ ++#include "mkimage.h" ++#include ++#include "omapimage.h" ++ ++/* Header size is CH header rounded up to 512 bytes plus GP header */ ++#define OMAP_CH_HDR_SIZE 512 ++#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header)) ++#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE) ++ ++static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE]; ++ ++static int omapimage_check_image_types(uint8_t type) ++{ ++ if (type == IH_TYPE_OMAPIMAGE) ++ return EXIT_SUCCESS; ++ else ++ return EXIT_FAILURE; ++} ++ ++/* ++ * Only the simplest image type is currently supported: ++ * TOC pointing to CHSETTINGS ++ * TOC terminator ++ * CHSETTINGS ++ * ++ * padding to OMAP_CH_HDR_SIZE bytes ++ * ++ * gp header ++ * size ++ * load_addr ++ */ ++static int valid_gph_size(uint32_t size) ++{ ++ return size; ++} ++ ++static int valid_gph_load_addr(uint32_t load_addr) ++{ ++ return load_addr; ++} ++ ++static int omapimage_verify_header(unsigned char *ptr, int image_size, ++ struct mkimage_params *params) ++{ ++ struct ch_toc *toc = (struct ch_toc *)ptr; ++ struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); ++ uint32_t offset, size; ++ ++ while (toc->section_offset != 0xffffffff ++ && toc->section_size != 0xffffffff) { ++ offset = toc->section_offset; ++ size = toc->section_size; ++ if (!offset || !size) ++ return -1; ++ if (offset >= OMAP_CH_HDR_SIZE || ++ offset+size >= OMAP_CH_HDR_SIZE) ++ return -1; ++ toc++; ++ } ++ if (!valid_gph_size(gph->size)) ++ return -1; ++ if (!valid_gph_load_addr(gph->load_addr)) ++ return -1; ++ ++ return 0; ++} ++ ++static void omapimage_print_section(struct ch_settings *chs) ++{ ++ switch (chs->section_key) { ++ case KEY_CHSETTINGS: ++ printf("CHSETTINGS (%x) " ++ "valid:%x " ++ "version:%x " ++ "reserved:%x " ++ "flags:%x\n", ++ chs->section_key, ++ chs->valid, ++ chs->version, ++ chs->reserved, ++ chs->flags); ++ break; ++ default: ++ printf("UNKNOWNKEY (%x) " ++ "valid:%x " ++ "version:%x " ++ "reserved:%x " ++ "flags:%x\n", ++ chs->section_key, ++ chs->valid, ++ chs->version, ++ chs->reserved, ++ chs->flags); ++ break; ++ } ++} ++ ++static void omapimage_print_header(const void *ptr) ++{ ++ struct ch_toc *toc = (struct ch_toc *)ptr; ++ struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); ++ uint32_t offset, size; ++ ++ while (toc->section_offset != 0xffffffff ++ && toc->section_size != 0xffffffff) { ++ offset = toc->section_offset; ++ size = toc->section_size; ++ ++ if (offset >= OMAP_CH_HDR_SIZE || ++ offset+size >= OMAP_CH_HDR_SIZE) ++ exit(EXIT_FAILURE); ++ ++ printf("Section %s offset %x length %x\n", ++ toc->section_name, ++ toc->section_offset, ++ toc->section_size); ++ ++ omapimage_print_section((struct ch_settings *)(ptr+offset)); ++ toc++; ++ } ++ ++ if (!valid_gph_size(gph->size)) { ++ fprintf(stderr, ++ "Error: invalid image size %x\n", ++ gph->size); ++ exit(EXIT_FAILURE); ++ } ++ ++ if (!valid_gph_load_addr(gph->load_addr)) { ++ fprintf(stderr, ++ "Error: invalid image load address %x\n", ++ gph->size); ++ exit(EXIT_FAILURE); ++ } ++ ++ printf("GP Header: Size %x LoadAddr %x\n", ++ gph->size, gph->load_addr); ++} ++ ++static int toc_offset(void *hdr, void *member) ++{ ++ return member - hdr; ++} ++ ++static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, ++ struct mkimage_params *params) ++{ ++ struct ch_toc *toc = (struct ch_toc *)ptr; ++ struct ch_settings *chs = (struct ch_settings *) ++ (ptr + 2 * sizeof(*toc)); ++ struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE); ++ ++ toc->section_offset = toc_offset(ptr, chs); ++ toc->section_size = sizeof(struct ch_settings); ++ strcpy((char *)toc->section_name, "CHSETTINGS"); ++ ++ chs->section_key = KEY_CHSETTINGS; ++ chs->valid = 0; ++ chs->version = 1; ++ chs->reserved = 0; ++ chs->flags = 0; ++ ++ toc++; ++ memset(toc, 0xff, sizeof(*toc)); ++ ++ gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE; ++ gph->load_addr = params->addr; ++} ++ ++int omapimage_check_params(struct mkimage_params *params) ++{ ++ return (params->dflag && (params->fflag || params->lflag)) || ++ (params->fflag && (params->dflag || params->lflag)) || ++ (params->lflag && (params->dflag || params->fflag)); ++} ++ ++/* ++ * omapimage parameters ++ */ ++static struct image_type_params omapimage_params = { ++ .name = "TI OMAP CH/GP Boot Image support", ++ .header_size = OMAP_FILE_HDR_SIZE, ++ .hdr = (void *)&omapimage_header, ++ .check_image_type = omapimage_check_image_types, ++ .verify_header = omapimage_verify_header, ++ .print_header = omapimage_print_header, ++ .set_header = omapimage_set_header, ++ .check_params = omapimage_check_params, ++}; ++ ++void init_omap_image_type(void) ++{ ++ mkimage_register(&omapimage_params); ++} +diff --git a/tools/omapimage.h b/tools/omapimage.h +new file mode 100644 +index 0000000..7ff5404 +--- /dev/null ++++ b/tools/omapimage.h +@@ -0,0 +1,50 @@ ++/* ++ * (C) Copyright 2010 ++ * Linaro LTD, www.linaro.org ++ * Author John Rigby ++ * Based on TI's signGP.c ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef _OMAPIMAGE_H_ ++#define _OMAPIMAGE_H_ ++ ++struct ch_toc { ++ uint32_t section_offset; ++ uint32_t section_size; ++ uint8_t unused[12]; ++ uint8_t section_name[12]; ++} __attribute__ ((__packed__)); ++ ++struct ch_settings { ++ uint32_t section_key; ++ uint8_t valid; ++ uint8_t version; ++ uint16_t reserved; ++ uint32_t flags; ++} __attribute__ ((__packed__)); ++ ++struct gp_header { ++ uint32_t size; ++ uint32_t load_addr; ++} __attribute__ ((__packed__)); ++ ++#define KEY_CHSETTINGS 0xC0C0C0C1 ++#endif /* _OMAPIMAGE_H_ */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0002-omap-add-miscellaneous-utility-macros-for-bit-field-.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0002-omap-add-miscellaneous-utility-macros-for-bit-field-.patch new file mode 100644 index 0000000000..31fcded64f --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0002-omap-add-miscellaneous-utility-macros-for-bit-field-.patch @@ -0,0 +1,71 @@ +From d8a745be3a5d821ac9ab06a0899163681767941b Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Wed, 16 Feb 2011 23:45:35 +0530 +Subject: [PATCH 02/22] omap: add miscellaneous utility macros for bit-field operations + +Signed-off-by: Aneesh V +--- + arch/arm/include/asm/omap_common.h | 51 ++++++++++++++++++++++++++++++++++++ + 1 files changed, 51 insertions(+), 0 deletions(-) + create mode 100644 arch/arm/include/asm/omap_common.h + +diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h +new file mode 100644 +index 0000000..03db2f5 +--- /dev/null ++++ b/arch/arm/include/asm/omap_common.h +@@ -0,0 +1,51 @@ ++/* ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef _OMAP_COMMON_H_ ++#define _OMAP_COMMON_H_ ++ ++/* extract a bit field from a bit vector */ ++#define get_bit_field(nr, start, mask)\ ++ (((nr) & (mask)) >> (start)) ++ ++/* Set a field in a bit vector */ ++#define set_bit_field(nr, start, mask, val)\ ++ do { \ ++ (nr) = ((nr) & ~(mask)) | (((val) << (start)) & (mask));\ ++ } while (0); ++ ++/* ++ * Utility macro for read-modify-write of a hardware register ++ * addr - address of the register ++ * shift - starting bit position of the field to be modified ++ * msk - mask for the field ++ * val - value to be shifted masked and written to the field ++ */ ++#define modify_reg_32(addr, shift, msk, val) \ ++ do {\ ++ writel(((readl(addr) & ~(msk))|(((val) << (shift)) & (msk))),\ ++ (addr));\ ++ } while (0); ++ ++#endif /* _OMAP_COMMON_H_ */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0003-omap4-add-OMAP4430-revision-check.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0003-omap4-add-OMAP4430-revision-check.patch new file mode 100644 index 0000000000..2ad6af9a5c --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0003-omap4-add-OMAP4430-revision-check.patch @@ -0,0 +1,137 @@ +From 3130b153ed6d6d1e486973a5d782e0480db748d6 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Wed, 16 Feb 2011 23:51:21 +0530 +Subject: [PATCH 03/22] omap4: add OMAP4430 revision check + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap4/board.c | 35 +++++++++++++++++++++++++++++++ + arch/arm/include/asm/arch-omap4/omap4.h | 17 +++++++++----- + arch/arm/include/asm/armv7.h | 31 +++++++++++++++++++++++++++ + 3 files changed, 77 insertions(+), 6 deletions(-) + create mode 100644 arch/arm/include/asm/armv7.h + +diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c +index fcd29a7..7583a0d 100644 +--- a/arch/arm/cpu/armv7/omap4/board.c ++++ b/arch/arm/cpu/armv7/omap4/board.c +@@ -28,6 +28,7 @@ + * MA 02111-1307 USA + */ + #include ++#include + #include + #include + #include +@@ -127,3 +128,37 @@ int arch_cpu_init(void) + set_muxconf_regs(); + return 0; + } ++ ++static u32 cortex_a9_rev(void) ++{ ++ ++ unsigned int rev; ++ ++ /* Read Main ID Register (MIDR) */ ++ asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); ++ ++ return rev; ++} ++ ++u32 omap4_revision(void) ++{ ++ if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_1) ++ return OMAP4430_ES2_1; ++ else if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_2) ++ return OMAP4430_ES2_2; ++ /* ++ * For some of the ES2/ES1 boards ID_CODE is not reliable: ++ * Also, ES1 and ES2 have different ARM revisions ++ * So use ARM revision for identification ++ */ ++ unsigned int rev = cortex_a9_rev(); ++ ++ switch (rev) { ++ case MIDR_CORTEX_A9_R0P1: ++ return OMAP4430_ES1_0; ++ case MIDR_CORTEX_A9_R1P2: ++ return OMAP4430_ES2_0; ++ default: ++ return OMAP4430_SILICON_ID_INVALID; ++ } ++} +diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h +index a30bb33..1f88732 100644 +--- a/arch/arm/include/asm/arch-omap4/omap4.h ++++ b/arch/arm/include/asm/arch-omap4/omap4.h +@@ -51,6 +51,11 @@ + #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) + #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) + ++/* CONTROL_ID_CODE */ ++#define CONTROL_ID_CODE (CTRL_BASE + 0x204) ++ ++#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F ++#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F + /* UART */ + #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) + #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) +@@ -121,11 +126,11 @@ struct s32ktimer { + /* Temporary SRAM stack used while low level init is done */ + #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END + +-/* +- * OMAP4 real hardware: +- * TODO: Change this to the IDCODE in the hw regsiter +- */ +-#define CPU_OMAP4430_ES10 1 +-#define CPU_OMAP4430_ES20 2 ++/* Silicon revisions */ ++#define OMAP4430_SILICON_ID_INVALID 0 ++#define OMAP4430_ES1_0 1 ++#define OMAP4430_ES2_0 2 ++#define OMAP4430_ES2_1 3 ++#define OMAP4430_ES2_2 4 + + #endif +diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h +new file mode 100644 +index 0000000..6c24a80 +--- /dev/null ++++ b/arch/arm/include/asm/armv7.h +@@ -0,0 +1,31 @@ ++/* ++ * (C) Copyright 2010 ++ * Texas Instruments Incorporated - http://www.ti.com/ ++ * ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef ARMV7_H ++#define ARMV7_H ++ ++#define MIDR_CORTEX_A9_R0P1 0x410FC091 ++#define MIDR_CORTEX_A9_R1P2 0x411FC092 ++ ++#endif /* ARMV7_H */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0004-armv7-start.S-provide-a-hook-for-saving-boot-params.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0004-armv7-start.S-provide-a-hook-for-saving-boot-params.patch new file mode 100644 index 0000000000..7dc0a596ef --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0004-armv7-start.S-provide-a-hook-for-saving-boot-params.patch @@ -0,0 +1,51 @@ +From 19eb02e3bb2e569b7269019eb0e116220daac23f Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 16:49:05 +0530 +Subject: [PATCH 04/22] armv7: start.S: provide a hook for saving boot params + +Provide a means by which u-boot/SPL can save parameters passed +to it by ROM code or the pre-loader. + +A new function 'save_boot_params' has been defined and a default +implentation provided. Please note that we do not have a stack yet. +So, any implementation of this function should not use stack. + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/cpu.c | 7 +++++++ + arch/arm/cpu/armv7/start.S | 1 + + 2 files changed, 8 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c +index a01e0d6..54533fc 100644 +--- a/arch/arm/cpu/armv7/cpu.c ++++ b/arch/arm/cpu/armv7/cpu.c +@@ -41,6 +41,13 @@ + + static void cache_flush(void); + ++void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) ++{ ++} ++ ++void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) ++ __attribute__((weak, alias("save_boot_params_default"))); ++ + int cleanup_before_linux(void) + { + unsigned int i; +diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S +index cb4f92f..3618190 100644 +--- a/arch/arm/cpu/armv7/start.S ++++ b/arch/arm/cpu/armv7/start.S +@@ -103,6 +103,7 @@ IRQ_STACK_START_IN: + */ + + reset: ++ bl save_boot_params + /* + * set the cpu to SVC32 mode + */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0005-omap4-save-parameters-passed-by-ROM-code-to-SPL.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0005-omap4-save-parameters-passed-by-ROM-code-to-SPL.patch new file mode 100644 index 0000000000..a1a8c235fa --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0005-omap4-save-parameters-passed-by-ROM-code-to-SPL.patch @@ -0,0 +1,151 @@ +From de5b300f43e95b8b73252147a3ea492a8647d27d Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Sun, 27 Feb 2011 19:25:16 +0530 +Subject: [PATCH 05/22] omap4: save parameters passed by ROM code to SPL + +Save boot device information passed by OMAP4 rom code + +ROM code in OMAP4 passes information such as the media from +which it picked up the first boot image(SPL in our case), +the mode(raw mode/FAT mode) etc. + +Save this information in SPL so that we can use the same media +and mode to bootload u-boot. + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap4/board.c | 14 ++++++++++++ + arch/arm/cpu/armv7/omap4/lowlevel_init.S | 31 +++++++++++++++++++++++++++ + arch/arm/include/asm/arch-omap4/omap4.h | 8 +++++++ + arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + + arch/arm/include/asm/omap_common.h | 20 +++++++++++++++++ + 5 files changed, 74 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c +index 7583a0d..a5d585b 100644 +--- a/arch/arm/cpu/armv7/omap4/board.c ++++ b/arch/arm/cpu/armv7/omap4/board.c +@@ -35,6 +35,20 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#ifdef CONFIG_PRELOADER ++u32 omap4_boot_device = BOOT_DEVICE_MMC1; ++u32 omap4_boot_mode = MMCSD_MODE_FAT; ++u32 omap_boot_device(void) ++{ ++ return omap4_boot_device; ++} ++ ++u32 omap_boot_mode(void) ++{ ++ return omap4_boot_mode; ++} ++#endif ++ + /* + * Routine: s_init + * Description: Does early system init of muxing and clocks. +diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S +index 026dfa4..250c73d 100644 +--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S ++++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S +@@ -27,6 +27,37 @@ + */ + + #include ++#ifdef CONFIG_PRELOADER ++.global save_boot_params ++save_boot_params: ++ /* ++ * See if the rom code passed pointer is valid: ++ * It is not valid if it is not in non-secure SRAM ++ * This may happen if you are booting with the help of ++ * debugger ++ */ ++ ldr r2, =NON_SECURE_SRAM_START ++ cmp r2, r0 ++ bgt 1f ++ ldr r2, =NON_SECURE_SRAM_END ++ cmp r2, r0 ++ blt 1f ++ ++ /* Store the boot device in omap4_boot_device */ ++ ldr r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device ++ and r2, #BOOT_DEVICE_MASK ++ ldr r3, =omap4_boot_device ++ str r2, [r3] @ omap4_boot_device <- r1 ++ ++ /* Store the boot mode (raw/FAT) in omap4_boot_mode */ ++ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr ++ ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr ++ ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode ++ ldr r3, =omap4_boot_mode ++ str r2, [r3] ++1: ++ bx lr ++#endif + + .globl lowlevel_init + lowlevel_init: +diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h +index 1f88732..740ca9d 100644 +--- a/arch/arm/include/asm/arch-omap4/omap4.h ++++ b/arch/arm/include/asm/arch-omap4/omap4.h +@@ -133,4 +133,12 @@ struct s32ktimer { + #define OMAP4430_ES2_1 3 + #define OMAP4430_ES2_2 4 + ++/* ROM code defines */ ++/* Boot device */ ++#define BOOT_DEVICE_MASK 0xFF ++#define BOOT_DEVICE_OFFSET 0x8 ++#define DEV_DESC_PTR_OFFSET 0x4 ++#define DEV_DATA_PTR_OFFSET 0x18 ++#define BOOT_MODE_OFFSET 0x8 ++ + #endif +diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h +index 4813e9e..ce86b36 100644 +--- a/arch/arm/include/asm/arch-omap4/sys_proto.h ++++ b/arch/arm/include/asm/arch-omap4/sys_proto.h +@@ -23,6 +23,7 @@ + + #include + #include ++#include + + struct omap_sysinfo { + char *board_string; +diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h +index 03db2f5..06c511c 100644 +--- a/arch/arm/include/asm/omap_common.h ++++ b/arch/arm/include/asm/omap_common.h +@@ -48,4 +48,24 @@ + (addr));\ + } while (0); + ++/* Boot device */ ++#define BOOT_DEVICE_NONE 0 ++#define BOOT_DEVICE_XIP 1 ++#define BOOT_DEVICE_XIPWAIT 2 ++#define BOOT_DEVICE_NAND 3 ++#define BOOT_DEVICE_ONE_NAND 4 ++#define BOOT_DEVICE_MMC1 5 ++#define BOOT_DEVICE_MMC2 6 ++ ++/* Boot type */ ++#define MMCSD_MODE_UNDEFINED 0 ++#define MMCSD_MODE_RAW 1 ++#define MMCSD_MODE_FAT 2 ++ ++/* Magic number passed from SPL to U-Boot */ ++#define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER 0xDEADBEEF ++ ++u32 omap_boot_device(void); ++u32 omap_boot_mode(void); ++ + #endif /* _OMAP_COMMON_H_ */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0006-arm-new-labels-in-the-linker-script-file.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0006-arm-new-labels-in-the-linker-script-file.patch new file mode 100644 index 0000000000..dfcc7732bf --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0006-arm-new-labels-in-the-linker-script-file.patch @@ -0,0 +1,72 @@ +From 230ff2d889e392b64ce3bc86541bb4591aeabad2 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 03:16:38 +0530 +Subject: [PATCH 06/22] arm: new labels in the linker script file + +_bss_start_ofs is used in start.S to indicate end of copied +image. This may not be correct when we have a discontiguous +memory map. For instance, .bss may be placed in SDRAM for +some SPLS while rest of the image is placed in SRAM. + +Define a new label in linker script to indicate the end of the +image copied during relocation and use it appropriately in +start.S. + +Also, add a new label to indicate the end of flash image. +This will be useful in identifying the size of flash image + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/start.S | 6 +++++- + arch/arm/cpu/armv7/u-boot.lds | 4 ++++ + 2 files changed, 9 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S +index 3618190..8215d26 100644 +--- a/arch/arm/cpu/armv7/start.S ++++ b/arch/arm/cpu/armv7/start.S +@@ -77,6 +77,10 @@ _TEXT_BASE: + _bss_start_ofs: + .word __bss_start - _start + ++.global _image_copy_end_ofs ++_image_copy_end_ofs: ++ .word __image_copy_end - _start ++ + .globl _bss_end_ofs + _bss_end_ofs: + .word _end - _start +@@ -172,7 +176,7 @@ stack_setup: + beq clear_bss /* skip relocation */ + #endif + mov r1, r6 /* r1 <- scratch for copy_loop */ +- ldr r3, _bss_start_ofs ++ ldr r3, _image_copy_end_ofs + add r2, r0, r3 /* r2 <- source end address */ + + copy_loop: +diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds +index 5725c30..c3ad587 100644 +--- a/arch/arm/cpu/armv7/u-boot.lds ++++ b/arch/arm/cpu/armv7/u-boot.lds +@@ -55,6 +55,8 @@ SECTIONS + + . = ALIGN(4); + ++ __image_copy_end = .; ++ + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) +@@ -66,6 +68,8 @@ SECTIONS + *(.dynsym) + } + ++ __flash_image_end = .; ++ + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0007-Add-generic-spl-infrastructure.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0007-Add-generic-spl-infrastructure.patch new file mode 100644 index 0000000000..5ac6bba9f9 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0007-Add-generic-spl-infrastructure.patch @@ -0,0 +1,91 @@ +From 9b4dfdc49a0e88f6a5292dbcb6c4260888258380 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 01:23:29 +0530 +Subject: [PATCH 07/22] Add generic spl infrastructure + +Define a new type of SPL that is not tied to any particular media. +- Create a top level directory 'spl' that has a structure similar + to the existing 'nand_spl' +- Make necessary changes to top-level Makefile to build such an spl + +Rationale for this approach: +- There may be SPLs(like the OMAP x-loader) that support booting from + multiple media. +- Also, there is no harm in keeping SPLs specific to a particular media + also under this directory. In fact it makes sense to merge all the + different spl directories into this one. + +Signed-off-by: Aneesh V +--- + Makefile | 11 +++++++++++ + arch/arm/include/asm/global_data.h | 5 +++++ + 2 files changed, 16 insertions(+), 0 deletions(-) + +diff --git a/Makefile b/Makefile +index dc2e3d8..21e51c8 100644 +--- a/Makefile ++++ b/Makefile +@@ -293,6 +293,11 @@ NAND_SPL = nand_spl + U_BOOT_NAND = $(obj)u-boot-nand.bin + endif + ++ifeq ($(CONFIG_SPL),y) ++.PHONEY : SPL ++ALL += SPL ++endif ++ + ifeq ($(CONFIG_ONENAND_U_BOOT),y) + ONENAND_IPL = onenand_ipl + U_BOOT_ONENAND = $(obj)u-boot-onenand.bin +@@ -402,6 +407,9 @@ $(LDSCRIPT): depend + $(obj)u-boot.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + ++SPL :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools ++ $(MAKE) -C spl/board/$(BOARDDIR) all ++ + $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend + $(MAKE) -C nand_spl/board/$(BOARDDIR) all + +@@ -1138,6 +1146,7 @@ clean: + @rm -f $(obj)include/bmp_logo.h + @rm -f $(obj)lib/asm-offsets.s + @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map} ++ @rm -f $(obj)spl/{u-boot-spl-generated.lds,u-boot-spl,u-boot-spl.map} + @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} + @rm -f $(ONENAND_BIN) + @rm -f $(obj)onenand_ipl/u-boot.lds +@@ -1157,12 +1166,14 @@ clobber: clean + @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) + @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.imx ++ @rm -f $(obj)MLO + @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} + @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c + @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm + @rm -fr $(obj)include/generated + @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f + @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f ++ @[ ! -d $(obj)spl ] || find $(obj)spl -name "*" -type l -print | xargs rm -f + + ifeq ($(OBJTREE),$(SRCTREE)) + mrproper \ +diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h +index 2a84d27..2ce020e 100644 +--- a/arch/arm/include/asm/global_data.h ++++ b/arch/arm/include/asm/global_data.h +@@ -89,6 +89,11 @@ typedef struct global_data { + #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ + #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ + ++#ifdef CONFIG_PRELOADER ++/* SPL works from internal RAM. gd pointer can be in .data section */ ++#define DECLARE_GLOBAL_DATA_PTR extern gd_t *gd ++#else + #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") ++#endif + + #endif /* __ASM_GBL_DATA_H */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0008-armv7-start.S-add-SPL-support.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0008-armv7-start.S-add-SPL-support.patch new file mode 100644 index 0000000000..bb6de4a068 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0008-armv7-start.S-add-SPL-support.patch @@ -0,0 +1,110 @@ +From cd0fbadb46f30c0630519d7b3e4388dc5a5c7baf Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 15:47:21 +0530 +Subject: [PATCH 08/22] armv7: start.S: add SPL support + +Changes for supporting SPL + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/start.S | 36 +++++++++++++++++++++++++----------- + 1 files changed, 25 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S +index 8215d26..f5f08d9 100644 +--- a/arch/arm/cpu/armv7/start.S ++++ b/arch/arm/cpu/armv7/start.S +@@ -42,7 +42,16 @@ _start: b reset + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq +- ++#ifdef CONFIG_PRELOADER ++_undefined_instruction: .word _undefined_instruction ++_software_interrupt: .word _software_interrupt ++_prefetch_abort: .word _prefetch_abort ++_data_abort: .word _data_abort ++_not_used: .word _not_used ++_irq: .word _irq ++_fiq: .word _fiq ++_pad: .word 0x12345678 /* now 16*4=64 */ ++#else + _undefined_instruction: .word undefined_instruction + _software_interrupt: .word software_interrupt + _prefetch_abort: .word prefetch_abort +@@ -51,6 +60,8 @@ _not_used: .word not_used + _irq: .word irq + _fiq: .word fiq + _pad: .word 0x12345678 /* now 16*4=64 */ ++#endif /* CONFIG_PRELOADER */ ++ + .global _end_vect + _end_vect: + +@@ -171,10 +182,9 @@ stack_setup: + mov sp, r4 + + adr r0, _start +-#ifndef CONFIG_PRELOADER + cmp r0, r6 ++ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + beq clear_bss /* skip relocation */ +-#endif + mov r1, r6 /* r1 <- scratch for copy_loop */ + ldr r3, _image_copy_end_ofs + add r2, r0, r3 /* r2 <- source end address */ +@@ -224,6 +234,15 @@ fixnext: + add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ + cmp r2, r3 + blo fixloop ++ b clear_bss ++_rel_dyn_start_ofs: ++ .word __rel_dyn_start - _start ++_rel_dyn_end_ofs: ++ .word __rel_dyn_end - _start ++_dynsym_start_ofs: ++ .word __dynsym_start - _start ++ ++#endif /* #ifndef CONFIG_PRELOADER */ + + clear_bss: + ldr r0, _bss_start_ofs +@@ -237,7 +256,6 @@ clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +-#endif /* #ifndef CONFIG_PRELOADER */ + + /* + * We are done. Do not return, instead branch to second part of board +@@ -257,13 +275,6 @@ jump_2_ram: + _board_init_r_ofs: + .word board_init_r - _start + +-_rel_dyn_start_ofs: +- .word __rel_dyn_start - _start +-_rel_dyn_end_ofs: +- .word __rel_dyn_end - _start +-_dynsym_start_ofs: +- .word __dynsym_start - _start +- + /************************************************************************* + * + * CPU_init_critical registers +@@ -300,6 +311,8 @@ cpu_init_crit: + bl lowlevel_init @ go setup pll,mux,memory + mov lr, ip @ restore link + mov pc, lr @ back to my caller ++ ++#ifndef CONFIG_PRELOADER + /* + ************************************************************************* + * +@@ -488,3 +501,4 @@ fiq: + bl do_fiq + + #endif ++#endif /* CONFIG_PRELOADER */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0009-omap-add-spl-support.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0009-omap-add-spl-support.patch new file mode 100644 index 0000000000..9bf74fa33e --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0009-omap-add-spl-support.patch @@ -0,0 +1,140 @@ +From 973a64f88d69d1c50409beaf83987f258b19cf8d Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 17:50:06 +0530 +Subject: [PATCH 09/22] omap: add spl support + +Add the basic spl framework and linker script common for OMAP3/4 +platforms. + +Signed-off-by: Aneesh V +--- + spl/board/ti/spl-omap.c | 47 ++++++++++++++++++++++++++++++++++ + spl/board/ti/spl-omap.lds | 62 +++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 109 insertions(+), 0 deletions(-) + create mode 100644 spl/board/ti/spl-omap.c + create mode 100644 spl/board/ti/spl-omap.lds + +diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c +new file mode 100644 +index 0000000..0e08f4f +--- /dev/null ++++ b/spl/board/ti/spl-omap.c +@@ -0,0 +1,47 @@ ++/* ++ * ++ * Clock initialization for OMAP4 ++ * ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++ ++/* Define global data structure pointer to it*/ ++gd_t gdata __attribute__ ((section(".data"))); ++bd_t bdata __attribute__ ((section(".data"))); ++gd_t *gd = &gdata; ++ ++void board_init_f(ulong dummy) ++{ ++ relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE); ++} ++ ++void board_init_r(gd_t *id, ulong dummy) ++{ ++ for (;;) ++ ; ++} +diff --git a/spl/board/ti/spl-omap.lds b/spl/board/ti/spl-omap.lds +new file mode 100644 +index 0000000..27b5295 +--- /dev/null ++++ b/spl/board/ti/spl-omap.lds +@@ -0,0 +1,62 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\ ++ LENGTH = CONFIG_SYS_SPL_MAX_SIZE } ++MEMORY { .sdram : ORIGIN = CONFIG_SYS_SPL_BSS_START_ADDR, \ ++ LENGTH = CONFIG_SYS_SPL_BSS_MAX_SIZE } ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ .text : ++ { ++ . = ALIGN(32); ++ __start = .; ++ start.o (.text) ++ *(.text*) ++ } >.sram ++ ++ . = ALIGN(4); ++ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram ++ ++ . = ALIGN(4); ++ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram ++ . = ALIGN(4); ++ __image_copy_end = .; ++ ++ .bss : ++ { ++ . = ALIGN(4); ++ __bss_start = .; ++ *(.bss*) ++ . = ALIGN(4); ++ _end = .; ++ } >.sdram ++} +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0010-omap4-add-spl-support-for-OMAP4-SDP.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0010-omap4-add-spl-support-for-OMAP4-SDP.patch new file mode 100644 index 0000000000..1dedf5c3dd --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0010-omap4-add-spl-support-for-OMAP4-SDP.patch @@ -0,0 +1,194 @@ +From ec08ceb0d0ed2e6c2deb5c6d81ebf0087e6fc5f8 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 18:23:31 +0530 +Subject: [PATCH 10/22] omap4: add spl support for OMAP4 SDP + +Adapted from: nand_spl/board/samsung/smdk6400/Makefile + +- Add the SPL makefile for OMAP4430 SDP +- Add the necessary CONFIG flags in the board config file + +Signed-off-by: Aneesh V +--- + board/ti/sdp4430/config.mk | 3 +- + include/configs/omap4_sdp4430.h | 19 ++++++ + spl/board/ti/sdp4430/Makefile | 120 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 141 insertions(+), 1 deletions(-) + create mode 100644 spl/board/ti/sdp4430/Makefile + +diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk +index 33901a7..c62965d 100644 +--- a/board/ti/sdp4430/config.mk ++++ b/board/ti/sdp4430/config.mk +@@ -28,4 +28,5 @@ + # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 + # (mem base + reserved) + +-CONFIG_SYS_TEXT_BASE = 0x80e80000 ++# 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM ++CONFIG_SYS_TEXT_BASE = 0x80100000 +diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h +index 9a8bb73..5b20841 100644 +--- a/include/configs/omap4_sdp4430.h ++++ b/include/configs/omap4_sdp4430.h +@@ -122,7 +122,9 @@ + + /* USB device configuration */ + #define CONFIG_USB_DEVICE 1 ++#ifndef CONFIG_PRELOADER + #define CONFIG_USB_TTY 1 ++#endif + #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + + /* Flash */ +@@ -240,4 +242,21 @@ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + ++/* Defines for Clock init */ ++#define CONFIG_SYS_OMAP4_ABE_SYSCK ++ ++/* Defines for SDRAM init */ ++#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 ++#define CONFIG_SYS_EMIF_UPDATE_TIMINGS 1 ++#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 ++ ++/* Defines for SPL */ ++#define CONFIG_SPL ++#define CONFIG_SYS_SPL_TEXT_BASE 0x40304360 ++#define CONFIG_SYS_SPL_MAX_SIZE 0x7800 /* 30 K */ ++#define CONFIG_SYS_SPL_STACK LOW_LEVEL_SRAM_STACK ++ ++#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 ++#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ ++ + #endif /* __CONFIG_H */ +diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile +new file mode 100644 +index 0000000..dd56a40 +--- /dev/null ++++ b/spl/board/ti/sdp4430/Makefile +@@ -0,0 +1,120 @@ ++# ++# (C) Copyright 2006-2007 ++# Stefan Roese, DENX Software Engineering, sr@denx.de. ++# ++# (C) Copyright 2008 ++# Guennadi Liakhovetki, DENX Software Engineering, ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++splobj := $(OBJTREE)/spl/ ++include $(TOPDIR)/config.mk ++SOBJS = ++COBJS = ++ ++# armv7 ++$(obj)start.S: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@ ++ ++$(obj)syslib.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@ ++ ++SOBJS += start.o ++COBJS += syslib.o ++ ++# omap-common ++$(obj)timer.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@ ++ ++$(obj)reset.S: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/reset.S $@ ++ ++$(obj)spl-omap.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@ ++ ++SOBJS += reset.o ++COBJS += timer.o spl-omap.o ++ ++$(OBJTREE)/MLO: $(splobj)u-boot-spl.bin ++ $(OBJTREE)/tools/mkimage -T omapimage \ ++ -a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@ ++ ++LDSCRIPT_SOURCE = $(TOPDIR)/spl/board/ti/spl-omap.lds ++ ++# omap4 ++$(obj)lowlevel_init.S: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/lowlevel_init.S $@ ++ ++$(obj)omap4_mux_data.h: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/omap4_mux_data.h $@ ++ ++$(obj)board.c:$(obj)omap4_mux_data.h ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@ ++ ++SOBJS += lowlevel_init.o ++COBJS += board.o ++ ++# rules ++LDPPFLAGS += -include $(TOPDIR)/include/config.h ++LDSCRIPT = $(splobj)u-boot-spl-generated.lds ++$(LDSCRIPT): $(LDSCRIPT_SOURCE) ++ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ ++LDFLAGS = -Bstatic -T $(LDSCRIPT) \ ++ $(PLATFORM_LDFLAGS) --gc-sections ++AFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 ++CFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 -ffunction-sections \ ++ -fdata-sections -march=armv7-a -mthumb ++PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) \ ++ -print-libgcc-file-name`) -lgcc ++ ++$(obj)%.o: $(obj)%.S ++ $(CC) $(AFLAGS) -c -o $@ $< ++ ++$(obj)%.o: $(obj)%.c ++ $(CC) $(CFLAGS) -c -o $@ $< ++ ++SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) ++OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) ++__OBJS := $(SOBJS) $(COBJS) ++LNDIR := $(OBJTREE)/spl/board/$(BOARDDIR) ++ ++$(splobj)u-boot-spl.bin: $(splobj)u-boot-spl ++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ ++ ++$(splobj)u-boot-spl: $(OBJS) $(LDSCRIPT) ++ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ ++ $(PLATFORM_LIBGCC) \ ++ -Map $(splobj)u-boot-spl.map \ ++ -o $(splobj)u-boot-spl ++ ++ALL = $(OBJTREE)/MLO ++all: $(obj).depend $(ALL) ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0011-omap4-add-serial-console-support-to-SPL.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0011-omap4-add-serial-console-support-to-SPL.patch new file mode 100644 index 0000000000..e22a91d59c --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0011-omap4-add-serial-console-support-to-SPL.patch @@ -0,0 +1,110 @@ +From eb26c57b60b026cd827be2470697111418b5ca61 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Sun, 27 Feb 2011 19:45:01 +0530 +Subject: [PATCH 11/22] omap4: add serial console support to SPL + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap4/board.c | 3 ++ + arch/arm/include/asm/omap_common.h | 1 + + spl/board/ti/sdp4430/Makefile | 40 ++++++++++++++++++++++++++++++++++++ + spl/board/ti/spl-omap.c | 10 +++++++++ + 4 files changed, 54 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c +index a5d585b..da79669 100644 +--- a/arch/arm/cpu/armv7/omap4/board.c ++++ b/arch/arm/cpu/armv7/omap4/board.c +@@ -57,6 +57,9 @@ u32 omap_boot_mode(void) + void s_init(void) + { + watchdog_init(); ++#ifdef CONFIG_PRELOADER ++ preloader_console_init(); ++#endif + } + + /* +diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h +index 06c511c..95116f4 100644 +--- a/arch/arm/include/asm/omap_common.h ++++ b/arch/arm/include/asm/omap_common.h +@@ -67,5 +67,6 @@ + + u32 omap_boot_device(void); + u32 omap_boot_mode(void); ++void preloader_console_init(void); + + #endif /* _OMAP_COMMON_H_ */ +diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile +index dd56a40..6a6aa42 100644 +--- a/spl/board/ti/sdp4430/Makefile ++++ b/spl/board/ti/sdp4430/Makefile +@@ -28,6 +28,46 @@ include $(TOPDIR)/config.mk + SOBJS = + COBJS = + ++# serial console ++$(obj)eabi_compat.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/lib/eabi_compat.c $@ ++ ++$(obj)string.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/string.c $@ ++ ++$(obj)vsprintf.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/vsprintf.c $@ ++ ++$(obj)console.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/common/console.c $@ ++ ++$(obj)stdio.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/common/stdio.c $@ ++ ++$(obj)serial.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/serial/serial.c $@ ++ ++$(obj)ns16550.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/serial/ns16550.c $@ ++ ++$(obj)div64.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/div64.c $@ ++ ++$(obj)ctype.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/ctype.c $@ ++ ++COBJS += serial.o ns16550.o string.o vsprintf.o console.o stdio.o ++COBJS += ctype.o eabi_compat.o div64.o ++ + # armv7 + $(obj)start.S: + @rm -f $@ +diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c +index 0e08f4f..57ddb7d 100644 +--- a/spl/board/ti/spl-omap.c ++++ b/spl/board/ti/spl-omap.c +@@ -45,3 +45,13 @@ void board_init_r(gd_t *id, ulong dummy) + for (;;) + ; + } ++ ++void preloader_console_init(void) ++{ ++ gd->bd = &bdata; ++ gd->flags |= GD_FLG_RELOC; ++ gd->baudrate = CONFIG_BAUDRATE; ++ serial_init(); /* serial communications setup */ ++ printf("\nU-Boot SPL for Texas Instruments OMAP4 (%s - %s)\n", ++ U_BOOT_DATE, U_BOOT_TIME); ++} +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0012-omap4-utility-function-to-identify-the-context-of-hw.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0012-omap4-utility-function-to-identify-the-context-of-hw.patch new file mode 100644 index 0000000000..2bf6ad0a47 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0012-omap4-utility-function-to-identify-the-context-of-hw.patch @@ -0,0 +1,100 @@ +From 4ddea7506c79c6309e65baf0484650b816f6e3c9 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Sun, 20 Feb 2011 16:15:42 +0530 +Subject: [PATCH 12/22] omap4: utility function to identify the context of hw init + +The basic hardware init of OMAP4(s_init()) can happen in 4 +different contexts: + 1. SPL running from SRAM + 2. U-Boot running from FLASH + 3. Non-XIP U-Boot loaded to SDRAM by SPL + 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + Configuration Header feature + +What level of hw initialization gets done depends on this +context. Add a utility function to find this context. + +Signed-off-by: Aneesh V +--- + arch/arm/include/asm/arch-omap4/sys_proto.h | 47 +++++++++++++++++++++++++++ + arch/arm/include/asm/omap_common.h | 6 +++ + 2 files changed, 53 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h +index ce86b36..19da2e1 100644 +--- a/arch/arm/include/asm/arch-omap4/sys_proto.h ++++ b/arch/arm/include/asm/arch-omap4/sys_proto.h +@@ -38,6 +38,53 @@ void sr32(void *, u32, u32, u32); + u32 wait_on_value(u32, u32, void *, u32); + void sdelay(unsigned long); + ++static inline u32 running_from_sdram(void) ++{ ++ u32 pc; ++ asm volatile ("mov %0, pc" : "=r" (pc)); ++ return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && ++ (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); ++} ++ ++static inline u8 uboot_loaded_by_spl(void) ++{ ++ /* ++ * Configuration Header is not supported yet, so u-boot init running ++ * from SDRAM implies that it was loaded by SPL. When this situation ++ * changes one of these approaches could be taken: ++ * i. Pass a magic from SPL to U-Boot and U-Boot save it at a known ++ * location. ++ * ii. Check the OPP. CH can support only 50% OPP while SPL initializes ++ * the DPLLs at 100% OPP. ++ */ ++ return running_from_sdram(); ++} ++/* ++ * The basic hardware init of OMAP(s_init()) can happen in 4 ++ * different contexts: ++ * 1. SPL running from SRAM ++ * 2. U-Boot running from FLASH ++ * 3. Non-XIP U-Boot loaded to SDRAM by SPL ++ * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the ++ * Configuration Header feature ++ * ++ * This function finds this context. ++ * Defining as inline may help in compiling out unused functions in SPL ++ */ ++static inline u32 omap4_hw_init_context(void) ++{ ++#ifdef CONFIG_PRELOADER ++ return OMAP_INIT_CONTEXT_SPL; ++#else ++ if (uboot_loaded_by_spl()) ++ return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL; ++ else if (running_from_sdram()) ++ return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH; ++ else ++ return OMAP_INIT_CONTEXT_XIP_UBOOT; ++#endif ++} ++ + extern const struct omap_sysinfo sysinfo; + + #endif +diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h +index 95116f4..50247af 100644 +--- a/arch/arm/include/asm/omap_common.h ++++ b/arch/arm/include/asm/omap_common.h +@@ -65,6 +65,12 @@ + /* Magic number passed from SPL to U-Boot */ + #define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER 0xDEADBEEF + ++/* HW Init Context */ ++#define OMAP_INIT_CONTEXT_SPL 0 ++#define OMAP_INIT_CONTEXT_XIP_UBOOT 1 ++#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL 2 ++#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH 3 ++ + u32 omap_boot_device(void); + u32 omap_boot_mode(void); + void preloader_console_init(void); +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0013-omap4-separate-mux-settings-into-essential-and-non-e.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0013-omap4-separate-mux-settings-into-essential-and-non-e.patch new file mode 100644 index 0000000000..3f9c7845b3 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0013-omap4-separate-mux-settings-into-essential-and-non-e.patch @@ -0,0 +1,1328 @@ +From c46103152b4875805e05752b3684038798ffaf32 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 01:48:11 +0530 +Subject: [PATCH 13/22] omap4: separate mux settings into essential and non essential parts + +Do the essential part from SPL and non-essential part from U-Boot +- Essential part is what is essential for u-boot to function +- Essential part is also largely board independent(at least + as of now) +- So essential part is moved out to SoC directory instead of + keeping in board directory. This helps in having single SPL + that works for Panda and SDP. +- Non-essential part is what is set by u-boot for kernel to + function correctly +- Ideally non-essential part should be phased out eventually + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap4/board.c | 53 +++++- + arch/arm/cpu/armv7/omap4/omap4_mux_data.h | 76 ++++++++ + arch/arm/include/asm/arch-omap4/sys_proto.h | 4 +- + board/ti/panda/panda.c | 25 +-- + board/ti/panda/panda.h | 264 --------------------------- + board/ti/panda/panda_mux_data.h | 229 +++++++++++++++++++++++ + board/ti/sdp4430/sdp.c | 25 +-- + board/ti/sdp4430/sdp.h | 264 --------------------------- + board/ti/sdp4430/sdp4430_mux_data.h | 227 +++++++++++++++++++++++ + 9 files changed, 597 insertions(+), 570 deletions(-) + create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h + delete mode 100644 board/ti/panda/panda.h + create mode 100644 board/ti/panda/panda_mux_data.h + delete mode 100644 board/ti/sdp4430/sdp.h + create mode 100644 board/ti/sdp4430/sdp4430_mux_data.h + +diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c +index da79669..95b6a96 100644 +--- a/arch/arm/cpu/armv7/omap4/board.c ++++ b/arch/arm/cpu/armv7/omap4/board.c +@@ -32,9 +32,30 @@ + #include + #include + #include ++#include "omap4_mux_data.h" + + DECLARE_GLOBAL_DATA_PTR; + ++void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) ++{ ++ int i; ++ struct pad_conf_entry *pad = (struct pad_conf_entry *) array; ++ ++ for (i = 0; i < size; i++, pad++) ++ writew(pad->val, base + pad->offset); ++} ++ ++static void set_muxconf_regs_essential(void) ++{ ++ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, ++ sizeof(core_padconf_array_essential) / ++ sizeof(struct pad_conf_entry)); ++ ++ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, ++ sizeof(wkup_padconf_array_essential) / ++ sizeof(struct pad_conf_entry)); ++} ++ + #ifdef CONFIG_PRELOADER + u32 omap4_boot_device = BOOT_DEVICE_MMC1; + u32 omap4_boot_mode = MMCSD_MODE_FAT; +@@ -49,14 +70,41 @@ u32 omap_boot_mode(void) + } + #endif + ++static void set_mux_conf_regs(void) ++{ ++ switch (omap4_hw_init_context()) { ++ case OMAP_INIT_CONTEXT_SPL: ++ set_muxconf_regs_essential(); ++ break; ++ case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL: ++ set_muxconf_regs_non_essential(); ++ break; ++ case OMAP_INIT_CONTEXT_XIP_UBOOT: ++ case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH: ++ set_muxconf_regs_essential(); ++ set_muxconf_regs_non_essential(); ++ break; ++ } ++} ++ + /* + * Routine: s_init +- * Description: Does early system init of muxing and clocks. +- * - Called path is with SRAM stack. ++ * Description: Does early system init of watchdog, muxing, clocks, and ++ * sdram. Watchdog disable is done always. For the rest what gets done ++ * depends on the boot mode in which this function is executed ++ * 1. s_init of SPL running from SRAM ++ * 2. s_init of U-Boot running from FLASH ++ * 3. s_init of U-Boot loaded to SDRAM by SPL ++ * 4. s_init of U-Boot loaded to SDRAM by ROM code using the Configuration ++ * Header feature ++ * Please have a look at the respective functions to see what gets done in ++ * each of these cases ++ * This function is called with SRAM stack. + */ + void s_init(void) + { + watchdog_init(); ++ set_mux_conf_regs(); + #ifdef CONFIG_PRELOADER + preloader_console_init(); + #endif +@@ -142,7 +190,6 @@ int checkboard(void) + */ + int arch_cpu_init(void) + { +- set_muxconf_regs(); + return 0; + } + +diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h +new file mode 100644 +index 0000000..00c52f8 +--- /dev/null ++++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h +@@ -0,0 +1,76 @@ ++ /* ++ * (C) Copyright 2010 ++ * Texas Instruments Incorporated, ++ * ++ * Balaji Krishnamoorthy ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef _OMAP4_MUX_DATA_H_ ++#define _OMAP4_MUX_DATA_H_ ++ ++#include ++ ++const struct pad_conf_entry core_padconf_array_essential[] = { ++ ++{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ ++{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ ++{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ ++{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ ++{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ ++{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ ++{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ ++{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ ++{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ ++{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ ++{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ ++{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ ++{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ ++{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ ++{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ ++{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ ++{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ ++{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ ++{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ ++{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ ++{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ ++{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ ++{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ ++{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ ++{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ ++{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ ++{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ ++{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ ++{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ ++{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ ++{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ ++{UART3_TX_IRTX, (M0)} /* uart3_tx */ ++ ++}; ++ ++const struct pad_conf_entry wkup_padconf_array_essential[] = { ++ ++{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ ++{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ ++{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ ++ ++}; ++ ++#endif /* _OMAP4_MUX_DATA_H_ */ +diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h +index 19da2e1..33a1666 100644 +--- a/arch/arm/include/asm/arch-omap4/sys_proto.h ++++ b/arch/arm/include/asm/arch-omap4/sys_proto.h +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + struct omap_sysinfo { + char *board_string; +@@ -33,7 +34,8 @@ void gpmc_init(void); + void watchdog_init(void); + u32 get_device_type(void); + void invalidate_dcache(u32); +-void set_muxconf_regs(void); ++void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); ++void set_muxconf_regs_non_essential(void); + void sr32(void *, u32, u32, u32); + u32 wait_on_value(u32, u32, void *, u32); + void sdelay(unsigned long); +diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c +index 78e1910..9afed80 100644 +--- a/board/ti/panda/panda.c ++++ b/board/ti/panda/panda.c +@@ -25,7 +25,7 @@ + #include + #include + +-#include "panda.h" ++#include "panda_mux_data.h" + + DECLARE_GLOBAL_DATA_PTR; + +@@ -65,27 +65,14 @@ int misc_init_r(void) + return 0; + } + +-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) ++void set_muxconf_regs_non_essential(void) + { +- int i; +- struct pad_conf_entry *pad = (struct pad_conf_entry *) array; +- +- for (i = 0; i < size; i++, pad++) +- writew(pad->val, base + pad->offset); +-} +- +-/** +- * @brief set_muxconf_regs Setting up the configuration Mux registers +- * specific to the board. +- */ +-void set_muxconf_regs(void) +-{ +- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, +- sizeof(core_padconf_array) / ++ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, ++ sizeof(core_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + +- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, +- sizeof(wkup_padconf_array) / ++ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, ++ sizeof(wkup_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + } + +diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda.h +deleted file mode 100644 +index e3d090e..0000000 +--- a/board/ti/panda/panda.h ++++ /dev/null +@@ -1,264 +0,0 @@ +-/* +- * (C) Copyright 2010 +- * Texas Instruments Incorporated, +- * +- * Balaji Krishnamoorthy +- * Aneesh V +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-#ifndef _PANDA_H_ +-#define _PANDA_H_ +- +-#include +-#include +- +-const struct pad_conf_entry core_padconf_array[] = { +- {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +- {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +- {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +- {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +- {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +- {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +- {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +- {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +- {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ +- {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ +- {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ +- {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ +- {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ +- {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ +- {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ +- {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ +- {GPMC_A16, (M3)}, /* gpio_40 */ +- {GPMC_A17, (PTD | M3)}, /* gpio_41 */ +- {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ +- {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ +- {GPMC_A20, (IEN | M3)}, /* gpio_44 */ +- {GPMC_A21, (M3)}, /* gpio_45 */ +- {GPMC_A22, (M3)}, /* gpio_46 */ +- {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ +- {GPMC_A24, (PTD | M3)}, /* gpio_48 */ +- {GPMC_A25, (PTD | M3)}, /* gpio_49 */ +- {GPMC_NCS0, (M3)}, /* gpio_50 */ +- {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ +- {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ +- {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ +- {GPMC_NWP, (M3)}, /* gpio_54 */ +- {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ +- {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ +- {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +- {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +- {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ +- {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ +- {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ +- {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ +- {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ +- {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ +- {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ +- {C2C_DATA14, (M1)}, /* dsi2_te0 */ +- {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ +- {HDMI_HPD, (M0)}, /* hdmi_hpd */ +- {HDMI_CEC, (M0)}, /* hdmi_cec */ +- {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ +- {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ +- {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ +- {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ +- {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ +- {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ +- {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ +- {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ +- {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ +- {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ +- {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ +- {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ +- {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ +- {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ +- {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ +- {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ +- {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ +- {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ +- {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ +- {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ +- {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ +- {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ +- {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ +- {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ +- {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ +- {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ +- {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ +- {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ +- {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ +- {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +- {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ +- {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ +- {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ +- {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ +- {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ +- {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +- {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +- {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +- {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +- {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +- {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +- {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +- {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +- {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +- {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +- {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ +- {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ +- {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ +- {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ +- {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ +- {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ +- {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ +- {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ +- {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ +- {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ +- {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ +- {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ +- {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ +- {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ +- {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ +- {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ +- {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ +- {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ +- {UART2_RTS, (M0)}, /* uart2_rts */ +- {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ +- {UART2_TX, (M0)}, /* uart2_tx */ +- {HDQ_SIO, (M3)}, /* gpio_127 */ +- {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ +- {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ +- {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ +- {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ +- {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ +- {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ +- {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ +- {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ +- {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ +- {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ +- {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ +- {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ +- {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ +- {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ +- {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ +- {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +- {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +- {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +- {UART3_TX_IRTX, (M0)}, /* uart3_tx */ +- {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ +- {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ +- {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ +- {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ +- {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ +- {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ +- {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ +- {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ +- {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ +- {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ +- {UART4_RX, (IEN | M0)}, /* uart4_rx */ +- {UART4_TX, (M0)}, /* uart4_tx */ +- {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ +- {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ +- {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ +- {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ +- {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ +- {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ +- {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ +- {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ +- {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ +- {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ +- {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ +- {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ +- {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ +- {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ +- {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ +- {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ +- {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ +- {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ +- {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ +- {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ +- {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ +- {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ +- {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ +- {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ +- {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ +- {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ +- {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ +- {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ +- {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ +- {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ +- {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ +- {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ +- {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ +- {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ +- {SYS_BOOT1, (M3)}, /* gpio_185 */ +- {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ +- {SYS_BOOT3, (M3)}, /* gpio_187 */ +- {SYS_BOOT4, (M3)}, /* gpio_188 */ +- {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ +- {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ +- {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ +- {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ +- {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ +- {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ +- {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ +- {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ +- {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ +- {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ +- {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ +- {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ +- {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ +- {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ +- {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ +- {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ +- {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ +- {DPM_EMU16, (M3)}, /* gpio_27 */ +- {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ +- {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ +- {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ +-}; +- +-const struct pad_conf_entry wkup_padconf_array[] = { +- {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ +- {PAD1_SIM_CLK, (M0)}, /* sim_clk */ +- {PAD0_SIM_RESET, (M0)}, /* sim_reset */ +- {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ +- {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ +- {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +- {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +- {PAD1_FREF_XTAL_IN, (M0)}, /* # */ +- {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ +- {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ +- {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ +- {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ +- {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ +- {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ +- {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */ +- {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ +- {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ +- {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ +- {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ +- {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ +- {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ +- {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ +-}; +- +-#endif +diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h +new file mode 100644 +index 0000000..8bb7fe5 +--- /dev/null ++++ b/board/ti/panda/panda_mux_data.h +@@ -0,0 +1,229 @@ ++/* ++ * (C) Copyright 2010 ++ * Texas Instruments Incorporated, ++ * ++ * Balaji Krishnamoorthy ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef _PANDA_MUX_DATA_H_ ++#define _PANDA_MUX_DATA_H_ ++ ++#include ++#include ++ ++const struct pad_conf_entry core_padconf_array_non_essential[] = { ++ {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ ++ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ ++ {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ ++ {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ ++ {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ ++ {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ ++ {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ ++ {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ ++ {GPMC_A16, (M3)}, /* gpio_40 */ ++ {GPMC_A17, (PTD | M3)}, /* gpio_41 */ ++ {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ ++ {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ ++ {GPMC_A20, (IEN | M3)}, /* gpio_44 */ ++ {GPMC_A21, (M3)}, /* gpio_45 */ ++ {GPMC_A22, (M3)}, /* gpio_46 */ ++ {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ ++ {GPMC_A24, (PTD | M3)}, /* gpio_48 */ ++ {GPMC_A25, (PTD | M3)}, /* gpio_49 */ ++ {GPMC_NCS0, (M3)}, /* gpio_50 */ ++ {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ ++ {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ ++ {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ ++ {GPMC_NWP, (M3)}, /* gpio_54 */ ++ {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ ++ {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ ++ {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ ++ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ ++ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ ++ {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ ++ {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ ++ {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ ++ {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ ++ {C2C_DATA14, (M1)}, /* dsi2_te0 */ ++ {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ ++ {HDMI_HPD, (M0)}, /* hdmi_hpd */ ++ {HDMI_CEC, (M0)}, /* hdmi_cec */ ++ {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ ++ {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ ++ {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ ++ {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ ++ {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ ++ {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ ++ {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ ++ {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ ++ {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ ++ {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ ++ {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ ++ {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ ++ {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ ++ {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ ++ {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ ++ {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ ++ {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ ++ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ ++ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ ++ {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ ++ {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ ++ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ ++ {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ ++ {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ ++ {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ ++ {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ ++ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ ++ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ ++ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ ++ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ ++ {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ ++ {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ ++ {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ ++ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ ++ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ ++ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ ++ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ ++ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ ++ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ ++ {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ ++ {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ ++ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ ++ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ ++ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ ++ {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ ++ {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ ++ {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ ++ {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ ++ {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ ++ {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ ++ {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ ++ {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ ++ {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ ++ {UART2_RTS, (M0)}, /* uart2_rts */ ++ {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ ++ {UART2_TX, (M0)}, /* uart2_tx */ ++ {HDQ_SIO, (M3)}, /* gpio_127 */ ++ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ ++ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ ++ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ ++ {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ ++ {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ ++ {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ ++ {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ ++ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ ++ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ ++ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ ++ {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ ++ {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ ++ {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ ++ {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ ++ {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ ++ {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ ++ {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ ++ {UART4_RX, (IEN | M0)}, /* uart4_rx */ ++ {UART4_TX, (M0)}, /* uart4_tx */ ++ {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ ++ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ ++ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ ++ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ ++ {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ ++ {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ ++ {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ ++ {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ ++ {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ ++ {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ ++ {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ ++ {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ ++ {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ ++ {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ ++ {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ ++ {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ ++ {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ ++ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ ++ {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ ++ {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ ++ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ ++ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ ++ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ ++ {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ ++ {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ ++ {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ ++ {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ ++ {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ ++ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ ++ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ ++ {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ ++ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ ++ {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ ++ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ ++ {SYS_BOOT1, (M3)}, /* gpio_185 */ ++ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ ++ {SYS_BOOT3, (M3)}, /* gpio_187 */ ++ {SYS_BOOT4, (M3)}, /* gpio_188 */ ++ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ ++ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ ++ {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ ++ {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ ++ {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ ++ {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ ++ {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ ++ {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ ++ {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ ++ {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ ++ {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ ++ {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ ++ {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ ++ {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ ++ {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ ++ {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ ++ {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ ++ {DPM_EMU16, (M3)}, /* gpio_27 */ ++ {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ ++ {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ ++ {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ ++}; ++ ++const struct pad_conf_entry wkup_padconf_array_non_essential[] = { ++ {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ ++ {PAD1_SIM_CLK, (M0)}, /* sim_clk */ ++ {PAD0_SIM_RESET, (M0)}, /* sim_reset */ ++ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ ++ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ ++ {PAD1_FREF_XTAL_IN, (M0)}, /* # */ ++ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ ++ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ ++ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ ++ {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ ++ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ ++ {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ ++ {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */ ++ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ ++ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ ++ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ ++ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ ++ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ ++ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ ++}; ++ ++#endif /* _PANDA_MUX_DATA_H_ */ +diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c +index b13c4c5..a5ea682 100644 +--- a/board/ti/sdp4430/sdp.c ++++ b/board/ti/sdp4430/sdp.c +@@ -27,7 +27,7 @@ + #include + #include + +-#include "sdp.h" ++#include "sdp4430_mux_data.h" + + DECLARE_GLOBAL_DATA_PTR; + +@@ -70,27 +70,14 @@ int misc_init_r(void) + return 0; + } + +-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) ++void set_muxconf_regs_non_essential(void) + { +- int i; +- struct pad_conf_entry *pad = (struct pad_conf_entry *) array; +- +- for (i = 0; i < size; i++, pad++) +- writew(pad->val, base + pad->offset); +-} +- +-/** +- * @brief set_muxconf_regs Setting up the configuration Mux registers +- * specific to the board. +- */ +-void set_muxconf_regs(void) +-{ +- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, +- sizeof(core_padconf_array) / ++ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, ++ sizeof(core_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + +- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, +- sizeof(wkup_padconf_array) / ++ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, ++ sizeof(wkup_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + } + +diff --git a/board/ti/sdp4430/sdp.h b/board/ti/sdp4430/sdp.h +deleted file mode 100644 +index bf41067..0000000 +--- a/board/ti/sdp4430/sdp.h ++++ /dev/null +@@ -1,264 +0,0 @@ +-/* +- * (C) Copyright 2010 +- * Texas Instruments Incorporated, +- * +- * Balaji Krishnamoorthy +- * Aneesh V +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-#ifndef _SDP_H_ +-#define _SDP_H_ +- +-#include +-#include +- +-const struct pad_conf_entry core_padconf_array[] = { +- {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +- {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +- {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +- {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +- {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +- {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +- {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +- {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +- {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ +- {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ +- {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ +- {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ +- {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ +- {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ +- {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ +- {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ +- {GPMC_A16, (M3)}, /* gpio_40 */ +- {GPMC_A17, (PTD | M3)}, /* gpio_41 */ +- {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ +- {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ +- {GPMC_A20, (IEN | M3)}, /* gpio_44 */ +- {GPMC_A21, (M3)}, /* gpio_45 */ +- {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ +- {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ +- {GPMC_A24, (PTD | M3)}, /* gpio_48 */ +- {GPMC_A25, (PTD | M3)}, /* gpio_49 */ +- {GPMC_NCS0, (M3)}, /* gpio_50 */ +- {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ +- {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ +- {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ +- {GPMC_NWP, (M3)}, /* gpio_54 */ +- {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ +- {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ +- {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +- {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +- {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ +- {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ +- {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ +- {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ +- {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ +- {C2C_DATA12, (M1)}, /* dsi1_te0 */ +- {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ +- {C2C_DATA14, (M1)}, /* dsi2_te0 */ +- {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ +- {HDMI_HPD, (M0)}, /* hdmi_hpd */ +- {HDMI_CEC, (M0)}, /* hdmi_cec */ +- {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ +- {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ +- {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ +- {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ +- {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ +- {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ +- {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ +- {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ +- {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ +- {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ +- {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ +- {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ +- {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ +- {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ +- {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ +- {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ +- {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ +- {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ +- {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ +- {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ +- {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ +- {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ +- {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ +- {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ +- {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ +- {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ +- {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ +- {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ +- {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ +- {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +- {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ +- {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ +- {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ +- {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ +- {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ +- {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +- {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +- {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +- {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +- {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +- {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +- {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +- {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +- {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +- {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +- {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ +- {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ +- {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ +- {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ +- {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ +- {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ +- {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ +- {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ +- {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ +- {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ +- {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ +- {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ +- {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ +- {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ +- {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ +- {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ +- {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ +- {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ +- {UART2_RTS, (M0)}, /* uart2_rts */ +- {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ +- {UART2_TX, (M0)}, /* uart2_tx */ +- {HDQ_SIO, (M3)}, /* gpio_127 */ +- {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ +- {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ +- {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ +- {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ +- {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ +- {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ +- {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ +- {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ +- {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ +- {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ +- {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ +- {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ +- {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ +- {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ +- {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ +- {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +- {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +- {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +- {UART3_TX_IRTX, (M0)}, /* uart3_tx */ +- {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ +- {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ +- {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ +- {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ +- {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ +- {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ +- {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ +- {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ +- {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ +- {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ +- {UART4_RX, (IEN | M0)}, /* uart4_rx */ +- {UART4_TX, (M0)}, /* uart4_tx */ +- {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ +- {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ +- {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ +- {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ +- {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ +- {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ +- {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ +- {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ +- {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ +- {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ +- {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ +- {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ +- {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ +- {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ +- {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ +- {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ +- {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ +- {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ +- {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ +- {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ +- {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ +- {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ +- {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ +- {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ +- {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ +- {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ +- {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ +- {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ +- {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ +- {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ +- {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ +- {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ +- {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ +- {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ +- {SYS_BOOT1, (M3)}, /* gpio_185 */ +- {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ +- {SYS_BOOT3, (M3)}, /* gpio_187 */ +- {SYS_BOOT4, (M3)}, /* gpio_188 */ +- {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ +- {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ +- {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ +- {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ +- {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ +- {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ +- {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ +- {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ +- {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ +- {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ +- {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ +- {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ +- {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ +- {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ +- {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ +- {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ +- {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ +- {DPM_EMU16, (M3)}, /* gpio_27 */ +- {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ +- {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ +- {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ +-}; +- +-const struct pad_conf_entry wkup_padconf_array[] = { +- {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ +- {PAD1_SIM_CLK, (M0)}, /* sim_clk */ +- {PAD0_SIM_RESET, (M0)}, /* sim_reset */ +- {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ +- {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ +- {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +- {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +- {PAD1_FREF_XTAL_IN, (M0)}, /* # */ +- {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ +- {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ +- {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ +- {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ +- {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ +- {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ +- {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ +- {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ +- {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ +- {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ +- {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ +- {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ +- {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ +- {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ +-}; +- +-#endif +diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h +new file mode 100644 +index 0000000..e6081dc +--- /dev/null ++++ b/board/ti/sdp4430/sdp4430_mux_data.h +@@ -0,0 +1,227 @@ ++/* ++ * (C) Copyright 2010 ++ * Texas Instruments Incorporated, ++ * ++ * Balaji Krishnamoorthy ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef _SDP4430_MUX_DATA_H ++#define _SDP4430_MUX_DATA_H ++ ++#include ++ ++const struct pad_conf_entry core_padconf_array_non_essential[] = { ++ {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ ++ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ ++ {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ ++ {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ ++ {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ ++ {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ ++ {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ ++ {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ ++ {GPMC_A16, (M3)}, /* gpio_40 */ ++ {GPMC_A17, (PTD | M3)}, /* gpio_41 */ ++ {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ ++ {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ ++ {GPMC_A20, (IEN | M3)}, /* gpio_44 */ ++ {GPMC_A21, (M3)}, /* gpio_45 */ ++ {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ ++ {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ ++ {GPMC_A24, (PTD | M3)}, /* gpio_48 */ ++ {GPMC_A25, (PTD | M3)}, /* gpio_49 */ ++ {GPMC_NCS0, (M3)}, /* gpio_50 */ ++ {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ ++ {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ ++ {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ ++ {GPMC_NWP, (M3)}, /* gpio_54 */ ++ {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ ++ {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ ++ {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ ++ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ ++ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ ++ {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ ++ {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ ++ {C2C_DATA12, (M1)}, /* dsi1_te0 */ ++ {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ ++ {C2C_DATA14, (M1)}, /* dsi2_te0 */ ++ {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ ++ {HDMI_HPD, (M0)}, /* hdmi_hpd */ ++ {HDMI_CEC, (M0)}, /* hdmi_cec */ ++ {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ ++ {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ ++ {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ ++ {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ ++ {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ ++ {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ ++ {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ ++ {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ ++ {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ ++ {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ ++ {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ ++ {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ ++ {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ ++ {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ ++ {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ ++ {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ ++ {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ ++ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ ++ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ ++ {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ ++ {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ ++ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ ++ {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ ++ {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ ++ {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ ++ {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ ++ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ ++ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ ++ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ ++ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ ++ {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ ++ {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ ++ {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ ++ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ ++ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ ++ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ ++ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ ++ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ ++ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ ++ {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ ++ {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ ++ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ ++ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ ++ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ ++ {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ ++ {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ ++ {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ ++ {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ ++ {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ ++ {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ ++ {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ ++ {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ ++ {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ ++ {UART2_RTS, (M0)}, /* uart2_rts */ ++ {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ ++ {UART2_TX, (M0)}, /* uart2_tx */ ++ {HDQ_SIO, (M3)}, /* gpio_127 */ ++ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ ++ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ ++ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ ++ {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ ++ {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ ++ {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ ++ {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ ++ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ ++ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ ++ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ ++ {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ ++ {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ ++ {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ ++ {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ ++ {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ ++ {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ ++ {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ ++ {UART4_RX, (IEN | M0)}, /* uart4_rx */ ++ {UART4_TX, (M0)}, /* uart4_tx */ ++ {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ ++ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ ++ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ ++ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ ++ {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ ++ {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ ++ {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ ++ {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ ++ {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ ++ {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ ++ {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ ++ {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ ++ {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ ++ {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ ++ {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ ++ {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ ++ {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ ++ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ ++ {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ ++ {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ ++ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ ++ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ ++ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ ++ {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ ++ {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ ++ {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ ++ {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ ++ {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ ++ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ ++ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ ++ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ ++ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ ++ {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ ++ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ ++ {SYS_BOOT1, (M3)}, /* gpio_185 */ ++ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ ++ {SYS_BOOT3, (M3)}, /* gpio_187 */ ++ {SYS_BOOT4, (M3)}, /* gpio_188 */ ++ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ ++ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ ++ {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ ++ {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ ++ {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ ++ {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ ++ {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ ++ {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ ++ {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ ++ {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ ++ {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ ++ {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ ++ {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ ++ {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ ++ {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ ++ {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ ++ {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ ++ {DPM_EMU16, (M3)}, /* gpio_27 */ ++ {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ ++ {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ ++ {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ ++}; ++ ++const struct pad_conf_entry wkup_padconf_array_non_essential[] = { ++ {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ ++ {PAD1_SIM_CLK, (M0)}, /* sim_clk */ ++ {PAD0_SIM_RESET, (M0)}, /* sim_reset */ ++ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ ++ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ ++ {PAD1_FREF_XTAL_IN, (M0)}, /* # */ ++ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ ++ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ ++ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ ++ {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ ++ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ ++ {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ ++ {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ ++ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ ++ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ ++ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ ++ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ ++ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ ++ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ ++}; ++ ++#endif /* _SDP4430_MUX_DATA_H */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0014-omap4-correct-mux-data-for-sdp4430.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0014-omap4-correct-mux-data-for-sdp4430.patch new file mode 100644 index 0000000000..ad616ae20c --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0014-omap4-correct-mux-data-for-sdp4430.patch @@ -0,0 +1,251 @@ +From 984aa865e9cc09a61c3238c6493ae3f845c38da6 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Sat, 19 Feb 2011 18:31:42 +0530 +Subject: [PATCH 14/22] omap4: correct mux data for sdp4430 + +sync up mux settings with the latest in x-loader + +Signed-off-by: Aneesh V +--- + board/ti/panda/panda_mux_data.h | 89 ++++++++++++++++++----------------- + board/ti/sdp4430/sdp4430_mux_data.h | 29 ++++++----- + 2 files changed, 61 insertions(+), 57 deletions(-) + +diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h +index 8bb7fe5..16cc0ad 100644 +--- a/board/ti/panda/panda_mux_data.h ++++ b/board/ti/panda/panda_mux_data.h +@@ -23,11 +23,9 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ ++#ifndef _SDP4430_MUX_DATA_H ++#define _SDP4430_MUX_DATA_H + +-#ifndef _PANDA_MUX_DATA_H_ +-#define _PANDA_MUX_DATA_H_ +- +-#include + #include + + const struct pad_conf_entry core_padconf_array_non_essential[] = { +@@ -45,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ + {GPMC_A20, (IEN | M3)}, /* gpio_44 */ + {GPMC_A21, (M3)}, /* gpio_45 */ +- {GPMC_A22, (M3)}, /* gpio_46 */ ++ {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ + {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ + {GPMC_A24, (PTD | M3)}, /* gpio_48 */ + {GPMC_A25, (PTD | M3)}, /* gpio_49 */ +@@ -59,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ + {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ + {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ +- {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ ++ {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ + {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ +- {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ ++ {C2C_DATA12, (M1)}, /* dsi1_te0 */ + {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ + {C2C_DATA14, (M1)}, /* dsi2_te0 */ + {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ +@@ -86,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ +- {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ +- {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ +- {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ +- {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ +- {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ +- {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ +- {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ +- {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ ++ {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ ++ {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ ++ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ ++ {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ ++ {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ ++ {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ ++ {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ ++ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +@@ -106,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ +- {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ +- {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ ++ {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ ++ {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ +@@ -143,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ +- {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ ++ {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ +@@ -157,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ +- {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ ++ {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ + {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ + {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ + {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ +- {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ +- {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ ++ {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ ++ {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ + {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ + {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ + {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ +@@ -173,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ +- {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ ++ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ +- {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ ++ {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ +- {SYS_BOOT3, (M3)}, /* gpio_187 */ ++ {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ +@@ -205,25 +203,28 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + }; + + const struct pad_conf_entry wkup_padconf_array_non_essential[] = { +- {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ +- {PAD1_SIM_CLK, (M0)}, /* sim_clk */ +- {PAD0_SIM_RESET, (M0)}, /* sim_reset */ +- {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ +- {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ +- {PAD1_FREF_XTAL_IN, (M0)}, /* # */ +- {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ +- {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ +- {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ +- {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ +- {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ +- {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ +- {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */ +- {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ +- {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ +- {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ +- {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ +- {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ +- {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ ++ {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ ++ {PAD1_SIM_CLK, (M0)}, /* sim_clk */ ++ {PAD0_SIM_RESET, (M0)}, /* sim_reset */ ++ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ ++ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ ++ {PAD1_FREF_XTAL_IN, (M0)}, /* # */ ++ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ ++ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ ++ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ ++ {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ ++ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ ++ {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ ++ {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ ++ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ ++ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ ++ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ ++ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ ++ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ ++ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ ++ {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ ++ {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ ++ {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ + }; + +-#endif /* _PANDA_MUX_DATA_H_ */ ++#endif /* _SDP4430_MUX_DATA_H */ +diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h +index e6081dc..16cc0ad 100644 +--- a/board/ti/sdp4430/sdp4430_mux_data.h ++++ b/board/ti/sdp4430/sdp4430_mux_data.h +@@ -84,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ +- {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ +- {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ +- {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ +- {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ +- {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ +- {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ +- {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ +- {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ ++ {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ ++ {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ ++ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ ++ {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ ++ {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ ++ {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ ++ {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ ++ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +@@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ +- {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ +- {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ ++ {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ ++ {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ +@@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ +- {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ ++ {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ +@@ -173,11 +173,11 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ + {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ +- {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ ++ {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ +- {SYS_BOOT3, (M3)}, /* gpio_187 */ ++ {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ +@@ -222,6 +222,9 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ ++ {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ ++ {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ ++ {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ + }; + + #endif /* _SDP4430_MUX_DATA_H */ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0015-omap4-add-clock-support.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0015-omap4-add-clock-support.patch new file mode 100644 index 0000000000..abd279af02 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0015-omap4-add-clock-support.patch @@ -0,0 +1,1335 @@ +From d669bac9f088cb5b0291e1c059c54ba95d527112 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Wed, 16 Feb 2011 23:25:54 +0530 +Subject: [PATCH 15/22] omap4: add clock support + +Add support for: +1. DPLL locking +2. Initialization of clock domains and clock modules + +This work draws upon previous work done for x-loader mainly by: + Santosh Shilimkar + Rajendra Nayak + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap4/Makefile | 1 + + arch/arm/cpu/armv7/omap4/board.c | 1 + + arch/arm/cpu/armv7/omap4/clocks.c | 717 +++++++++++++++++++++++++++ + arch/arm/include/asm/arch-omap4/clocks.h | 504 +++++++++++++++++++ + arch/arm/include/asm/arch-omap4/sys_proto.h | 6 + + arch/arm/include/asm/omap_common.h | 3 + + spl/board/ti/sdp4430/Makefile | 6 +- + 7 files changed, 1237 insertions(+), 1 deletions(-) + create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c + create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h + +diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile +index 987dc9d..6154e86 100644 +--- a/arch/arm/cpu/armv7/omap4/Makefile ++++ b/arch/arm/cpu/armv7/omap4/Makefile +@@ -30,6 +30,7 @@ SOBJS += lowlevel_init.o + COBJS += board.o + COBJS += mem.o + COBJS += sys_info.o ++COBJS += clocks.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c +index 95b6a96..62a59ad 100644 +--- a/arch/arm/cpu/armv7/omap4/board.c ++++ b/arch/arm/cpu/armv7/omap4/board.c +@@ -105,6 +105,7 @@ void s_init(void) + { + watchdog_init(); + set_mux_conf_regs(); ++ prcm_init(); + #ifdef CONFIG_PRELOADER + preloader_console_init(); + #endif +diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c +new file mode 100644 +index 0000000..317f30f +--- /dev/null ++++ b/arch/arm/cpu/armv7/omap4/clocks.c +@@ -0,0 +1,717 @@ ++/* ++ * ++ * Clock initialization for OMAP4 ++ * ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * ++ * Aneesh V ++ * ++ * Based on previous work by: ++ * Santosh Shilimkar ++ * Rajendra Nayak ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++ ++#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) ++ ++static const u32 sys_clk_array[8] = { ++ 0, /* Uninitialized */ ++ 12000000, /* 12 MHz */ ++ 13000000, /* 13 MHz */ ++ 16800000, /* 16.8 MHz */ ++ 19200000, /* 19.2 MHz */ ++ 26000000, /* 26 MHz */ ++ 27000000, /* 27 MHz */ ++ 38400000, /* 38.4 MHz */ ++}; ++ ++static const struct dpll_params core_dpll_params_opp100 = { ++ 0, 0, 1600000, 1, 5, 8, 4, 6, 5 ++}; ++ ++static const struct dpll_params core_dpll_params_opp100_ddr200 = { ++ 0, 0, 1600000, 2, 5, 8, 4, 6, 5 ++}; ++ ++static const struct dpll_params core_dpll_params_es1_l3_190 = { ++ 0, 0, 1523712, 1, 5, 8, 4, 6, 5 ++}; ++ ++static const struct dpll_params per_dpll_params_opp100 = { ++ 0, 0, 1536000, 8, 6, 12, 9, 4, 5 ++}; ++ ++/* TODO - fix MPU mult */ ++static const struct dpll_params mpu_dpll_params_600mhz = { ++ 0, 0, 1200000, 1, -1, -1, -1, -1, -1 ++}; ++ ++static const struct dpll_params mpu_dpll_params_1000mhz = { ++ 0, 0, 2000000, 1, -1, -1, -1, -1, -1 ++}; ++ ++static const struct dpll_params usb_dpll_params = { ++ 0, 0, 1920000, 2, -1, -1, -1, -1, -1 ++}; ++ ++static const struct dpll_params iva_dpll_params = { ++ 0, 0, 1862000, -1, -1, 4, 7, -1, -1 ++}; ++ ++static const struct dpll_params abe_dpll_params = { ++ 0, 0, 196608, 1, 1, -1, -1, -1, -1 ++}; ++ ++static const u32 clk_domains_essential[] = { ++ CM_L4PER_CLKSTCTRL, ++ CM_L3INIT_CLKSTCTRL, ++ CM_MEMIF_CLKSTCTRL, ++ CM_L4CFG_CLKSTCTRL, ++ 0 ++}; ++ ++static const u32 clk_domains_non_essential[] = { ++ CM_MPU_M3_CLKSTCTRL, ++ CM_IVAHD_CLKSTCTRL, ++ CM_DSP_CLKSTCTRL, ++ CM_DSS_CLKSTCTRL, ++ CM_SGX_CLKSTCTRL, ++ CM1_ABE_CLKSTCTRL, ++ CM_C2C_CLKSTCTRL, ++ CM_CAM_CLKSTCTRL, ++ CM_DSS_CLKSTCTRL, ++ CM_SDMA_CLKSTCTRL, ++ 0 ++}; ++ ++static const u32 clk_modules_hw_auto_essential[] = { ++ CM_WKUP_GPIO1_CLKCTRL, ++ CM_L4PER_GPIO2_CLKCTRL, ++ CM_L4PER_GPIO3_CLKCTRL, ++ CM_L4PER_GPIO4_CLKCTRL, ++ CM_L4PER_GPIO5_CLKCTRL, ++ CM_L4PER_GPIO6_CLKCTRL, ++ CM_MEMIF_EMIF_1_CLKCTRL, ++ CM_MEMIF_EMIF_2_CLKCTRL, ++ CM_L3INIT_HSUSBOTG_CLKCTRL, ++ CM_L3INIT_USBPHY_CLKCTRL, ++ CM_L4CFG_L4_CFG_CLKCTRL, ++ 0 ++}; ++ ++static const u32 clk_modules_hw_auto_non_essential[] = { ++ CM_MPU_M3_MPU_M3_CLKCTRL, ++ CM_IVAHD_IVAHD_CLKCTRL, ++ CM_IVAHD_SL2_CLKCTRL, ++ CM_DSP_DSP_CLKCTRL, ++ CM_L3_2_GPMC_CLKCTRL, ++ CM_L3INSTR_L3_3_CLKCTRL, ++ CM_L3INSTR_L3_INSTR_CLKCTRL, ++ CM_L3INSTR_INTRCONN_WP1_CLKCTRL, ++ CM_L3INIT_HSI_CLKCTRL, ++ CM_L3INIT_HSUSBTLL_CLKCTRL, ++ 0 ++}; ++ ++static const u32 clk_modules_explicit_en_essential[] = { ++ CM_L4PER_GPTIMER2_CLKCTRL, ++ CM_L3INIT_HSMMC1_CLKCTRL, ++ CM_L3INIT_HSMMC2_CLKCTRL, ++ CM_L4PER_MCSPI1_CLKCTRL, ++ CM_WKUP_GPTIMER1_CLKCTRL, ++ CM_L4PER_I2C1_CLKCTRL, ++ CM_L4PER_I2C2_CLKCTRL, ++ CM_L4PER_I2C3_CLKCTRL, ++ CM_L4PER_I2C4_CLKCTRL, ++ CM_WKUP_WDTIMER2_CLKCTRL, ++ CM_L4PER_UART3_CLKCTRL, ++ 0 ++}; ++ ++static const u32 clk_modules_explicit_en_non_essential[] = { ++ CM1_ABE_AESS_CLKCTRL, ++ CM1_ABE_PDM_CLKCTRL, ++ CM1_ABE_DMIC_CLKCTRL, ++ CM1_ABE_MCASP_CLKCTRL, ++ CM1_ABE_MCBSP1_CLKCTRL, ++ CM1_ABE_MCBSP2_CLKCTRL, ++ CM1_ABE_MCBSP3_CLKCTRL, ++ CM1_ABE_SLIMBUS_CLKCTRL, ++ CM1_ABE_TIMER5_CLKCTRL, ++ CM1_ABE_TIMER6_CLKCTRL, ++ CM1_ABE_TIMER7_CLKCTRL, ++ CM1_ABE_TIMER8_CLKCTRL, ++ CM1_ABE_WDT3_CLKCTRL, ++ CM_L4PER_GPTIMER9_CLKCTRL, ++ CM_L4PER_GPTIMER10_CLKCTRL, ++ CM_L4PER_GPTIMER11_CLKCTRL, ++ CM_L4PER_GPTIMER3_CLKCTRL, ++ CM_L4PER_GPTIMER4_CLKCTRL, ++ CM_L4PER_HDQ1W_CLKCTRL, ++ CM_L4PER_MCBSP4_CLKCTRL, ++ CM_L4PER_MCSPI2_CLKCTRL, ++ CM_L4PER_MCSPI3_CLKCTRL, ++ CM_L4PER_MCSPI4_CLKCTRL, ++ CM_L4PER_MMCSD3_CLKCTRL, ++ CM_L4PER_MMCSD4_CLKCTRL, ++ CM_L4PER_MMCSD5_CLKCTRL, ++ CM_L4PER_UART1_CLKCTRL, ++ CM_L4PER_UART2_CLKCTRL, ++ CM_L4PER_UART4_CLKCTRL, ++ CM_WKUP_KEYBOARD_CLKCTRL, ++ CM_WKUP_WDTIMER2_CLKCTRL, ++ CM_CAM_ISS_CLKCTRL, ++ CM_CAM_FDIF_CLKCTRL, ++ CM_DSS_DSS_CLKCTRL, ++ CM_SGX_SGX_CLKCTRL, ++ CM_L3INIT_HSUSBHOST_CLKCTRL, ++ CM_L3INIT_FSUSB_CLKCTRL, ++ 0 ++}; ++ ++static u32 get_m_n(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n, ++ u32 tolerance_khz) ++{ ++ u32 min_freq = target_freq_khz - tolerance_khz; ++ u32 max_freq = target_freq_khz; ++ u32 freq, freq_old; ++ *n = 1; ++ while (1) { ++ *m = min_freq / ref_freq_khz / 2 * (*n); ++ freq_old = 0; ++ while (1) { ++ freq = ref_freq_khz * 2 * (*m) / (*n); ++ if (abs(target_freq_khz - freq_old) <= ++ abs(target_freq_khz - freq)) { ++ freq = freq_old; ++ (*m)--; ++ break; ++ } ++ (*m)++; ++ freq_old = freq; ++ } ++ if (freq >= min_freq && freq <= max_freq) ++ break; ++ (*n)++; ++ if ((*n) > OMAP_DPLL_MAX_N + 1) ++ return 1; ++ } ++ (*n)--; ++ return 0; ++} ++ ++static u32 __get_syc_clk_freq(void) ++{ ++ /* ++ * For ES1 the ROM code calibration of sys clock is not reliable ++ * due to hw issue. So, use hard-coded value. If this value is not ++ * correct for any board over-ride this function in board file ++ * From ES2.0 onwards you will get this information from ++ * CM_SYS_CLKSEL ++ */ ++ if (omap4_revision() == OMAP4430_ES1_0) ++ return OMAP_SYS_CLK_FREQ_38_4_MHZ; ++ else { ++ u32 sys_clk_ind = readl(CM_SYS_CLKSEL) & ++ CM_SYS_CLKSEL_SYS_CLKSEL_MASK; ++ return sys_clk_array[sys_clk_ind]; ++ } ++} ++ ++static inline void do_bypass_dpll(u32 base) ++{ ++ struct dpll_regs *dpll_regs = (struct dpll_regs *)base; ++ ++ modify_reg_32(&dpll_regs->cm_clkmode_dpll, ++ CM_CLKMODE_DPLL_DPLL_EN_SHIFT, ++ CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_FAST_RELOCK_BYPASS); ++} ++ ++static inline void wait_for_bypass(u32 base) ++{ ++ struct dpll_regs *dpll_regs = (struct dpll_regs *)base; ++ ++ while (readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK) ++ ; ++} ++ ++static inline void do_lock_dpll(u32 base) ++{ ++ struct dpll_regs *dpll_regs = (struct dpll_regs *)base; ++ ++ modify_reg_32(&dpll_regs->cm_clkmode_dpll, ++ CM_CLKMODE_DPLL_DPLL_EN_SHIFT, ++ CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_LOCK); ++} ++ ++static inline void wait_for_lock(u32 base) ++{ ++ struct dpll_regs *dpll_regs = (struct dpll_regs *)base; ++ ++ while (!(readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK)) ++ ; ++} ++ ++static void do_setup_dpll(u32 base, const struct dpll_params *params, ++ u32 ref_clk_khz, u32 tolerance, u8 lock) ++{ ++ u32 temp, m, n; ++ struct dpll_regs *dpll_regs = (struct dpll_regs *)base; ++ ++ do_bypass_dpll(base); ++ ++ /* Get the M & N values */ ++ m = params->m; ++ n = params->n; ++ /* if m & n are not specified calculate them */ ++ if (!(m && n)) { ++ if (get_m_n(params->locked_freq_khz, ref_clk_khz, ++ &m, &n, tolerance)) { ++ /* DPLL locking is critical if it fails just hang */ ++ for (;;) ++ ; ++ return; ++ } ++ } ++ ++ /* Wait till the DPLL is in BYPASS */ ++ wait_for_bypass(base); ++ ++ /* Set M & N */ ++ temp = readl(&dpll_regs->cm_clksel_dpll); ++ set_bit_field(temp, CM_CLKSEL_DPLL_M_SHIFT, CM_CLKSEL_DPLL_M_MASK, m); ++ set_bit_field(temp, CM_CLKSEL_DPLL_N_SHIFT, CM_CLKSEL_DPLL_N_MASK, n); ++ writel(temp, &dpll_regs->cm_clksel_dpll); ++ ++ /* Lock */ ++ if (lock) ++ do_lock_dpll(base); ++ ++ /* Setup post-dividers */ ++ if (params->m2 >= 0) ++ writel(params->m2, &dpll_regs->cm_div_m2_dpll); ++ if (params->m3 >= 0) ++ writel(params->m3, &dpll_regs->cm_div_m3_dpll); ++ if (params->m4 >= 0) ++ writel(params->m4, &dpll_regs->cm_div_m4_dpll); ++ if (params->m5 >= 0) ++ writel(params->m5, &dpll_regs->cm_div_m5_dpll); ++ if (params->m6 >= 0) ++ writel(params->m6, &dpll_regs->cm_div_m6_dpll); ++ if (params->m7 >= 0) ++ writel(params->m7, &dpll_regs->cm_div_m7_dpll); ++ ++ /* Wait till the DPLL locks */ ++ if (lock) ++ wait_for_lock(base); ++} ++ ++const struct dpll_params *get_core_dpll_params(void) ++{ ++ switch (omap4_revision()) { ++ case OMAP4430_ES1_0: ++ return &core_dpll_params_es1_l3_190; ++ case OMAP4430_ES2_0: ++ case OMAP4430_SILICON_ID_INVALID: ++ return &core_dpll_params_opp100_ddr200; /* safest */ ++ case OMAP4430_ES2_1: ++ case OMAP4430_ES2_2: ++ return &core_dpll_params_opp100; ++ default: ++ return NULL; ++ } ++} ++ ++u32 omap4_ddr_clk(void) ++{ ++ u32 ddr_clk; ++ const struct dpll_params *core_dpll_params; ++ ++ core_dpll_params = get_core_dpll_params(); ++ /* ++ * DDR frequency is PHY_ROOT_CLK/2 ++ * PHY_ROOT_CLK = Fdpll/2/M2 ++ */ ++ ddr_clk = core_dpll_params->locked_freq_khz / 4 / core_dpll_params->m2; ++ ddr_clk *= 1000; /* convert to Hz */ ++ return ddr_clk; ++} ++ ++static void setup_dplls(void) ++{ ++ u32 sys_clk_khz, temp; ++ const struct dpll_params *params; ++ ++ sys_clk_khz = get_syc_clk_freq() / 1000; ++ ++ /* CORE dpll */ ++ params = get_core_dpll_params(); /* default - safest */ ++ /* ++ * Do not lock the core DPLL now. Just set it up. ++ * Core DPLL will be locked after setting up EMIF ++ * using the FREQ_UPDATE method(freq_update_core()) ++ */ ++ do_setup_dpll(CM_CLKMODE_DPLL_CORE, params, sys_clk_khz, ++ DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_NO_LOCK); ++ /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ ++ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | ++ (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | ++ (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); ++ writel(temp, CM_CLKSEL_CORE); ++ ++ /* lock PER dpll */ ++ do_setup_dpll(CM_CLKMODE_DPLL_PER, &per_dpll_params_opp100, sys_clk_khz, ++ DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK); ++ ++ /* MPU dpll */ ++ if (omap4_revision() == OMAP4430_ES1_0) ++ params = &mpu_dpll_params_600mhz; ++ else ++ params = &mpu_dpll_params_1000mhz; ++ do_setup_dpll(CM_CLKMODE_DPLL_MPU, params, sys_clk_khz, ++ DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK); ++} ++ ++static void setup_non_essential_dplls(void) ++{ ++ u32 sys_clk_khz, temp, abe_ref_clk; ++ u32 m, n, sd_div, num, den; ++ struct dpll_params tmp_params; ++ ++ sys_clk_khz = get_syc_clk_freq() / 1000; ++ ++ /* IVA */ ++ do_setup_dpll(CM_CLKMODE_DPLL_IVA, &iva_dpll_params, sys_clk_khz, ++ DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ, CONFIGURE_AND_LOCK); ++ ++ /* USB */ ++ tmp_params = usb_dpll_params; ++ get_m_n(tmp_params.locked_freq_khz, sys_clk_khz, &m, &n, ++ DPLL_LOCKED_FREQ_TOLERANCE_0); ++ /* ++ * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction ++ * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) ++ * - where CLKINP is sys_clk in MHz ++ * Use CLKINP in KHz and adjust the denominator accordingly so ++ * that we have enough accuracy and at the same time no overflow ++ */ ++ num = m * sys_clk_khz; ++ den = (n + 1) * 250 * 1000; ++ num += den - 1; ++ sd_div = num / den; ++ temp = readl(CM_CLKSEL_DPLL_USB); ++ set_bit_field(temp, CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT, ++ CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div); ++ writel(temp, CM_CLKSEL_DPLL_USB); ++ /* Now setup the dpll with the regular function */ ++ tmp_params.m = m; ++ tmp_params.n = n; ++ do_setup_dpll(CM_CLKMODE_DPLL_USB, &tmp_params, sys_clk_khz, ++ DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK); ++ ++ /* ABE dpll */ ++ tmp_params = abe_dpll_params; ++#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK ++ abe_ref_clk = sys_clk_khz; ++#else ++ /* Enable REGM4XEN to achieve 196.608MHz from 32768 Hz */ ++ writel(readl(CM_CLKMODE_DPLL_ABE) | CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK, ++ CM_CLKMODE_DPLL_ABE); ++ ++ /* ++ * Converting the input clock 32768 Hz to KHz would result in accuracy ++ * loss. Instead make both target frequency and reference clock to be ++ * in terms of Hz. ++ * ++ * Also, REGM4XEN is enabled so there is an additional ++ * multiplier of 4 for M. So adjust for this while passing target ++ * frequency to get_m_n() ++ */ ++ tmp_params.locked_freq_khz = tmp_params.locked_freq_khz * 1000 / 4; ++ abe_ref_clk = OMAP_32K_CLK_FREQ; ++#endif ++ temp = (abe_ref_clk == OMAP_32K_CLK_FREQ) ? ++ CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK : ++ CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; ++ /* Select the right reference clk */ ++ modify_reg_32(CM_ABE_PLL_REF_CLKSEL, ++ CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT, ++ CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, ++ temp); ++ /* Lock the dpll */ ++ do_setup_dpll(CM_CLKMODE_DPLL_ABE, &tmp_params, abe_ref_clk, ++ DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK); ++} ++ ++static void do_scale_vcore(u32 vcore_reg, u32 volt) ++{ ++ u32 temp; ++ ++ temp = SMPS_I2C_SLAVE_ADDR | ++ (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | ++ (volt << PRM_VC_VAL_BYPASS_DATA_SHIFT) | ++ PRM_VC_VAL_BYPASS_VALID_BIT; ++ writel(temp, PRM_VC_VAL_BYPASS); ++ while (readl(PRM_VC_VAL_BYPASS) & PRM_VC_VAL_BYPASS_VALID_BIT) ++ ; ++} ++ ++static void scale_vcores(void) ++{ ++ u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp; ++ u32 omap4_rev = omap4_revision(); ++ ++ sys_clk_khz = get_syc_clk_freq() / 1000; ++ ++ /* ++ * Setup the dedicated I2C controller for Voltage Control ++ * I2C clk - high period 40% low period 60% ++ */ ++ cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; ++ cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; ++ /* values to be set in register - less by 5 & 7 respectively */ ++ cycles_hi -= 5; ++ cycles_low -= 7; ++ temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | ++ (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); ++ writel(temp, PRM_VC_CFG_I2C_CLK); ++ ++ /* Disable high speed mode and all advanced features */ ++ writel(0x0, PRM_VC_CFG_I2C_MODE); ++ ++ /* VCORE 1 */ ++ if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1)) ++ volt = SMPS_VOLT_1_3500_V; ++ else ++ volt = SMPS_VOLT_1_5000_V; ++ do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); ++ ++ /* VCORE 2 */ ++ if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1)) ++ volt = SMPS_VOLT_1_1000_V; ++ else ++ volt = SMPS_VOLT_1_2000_V; ++ do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); ++ ++ /* VCORE 3 */ ++ if (omap4_rev == OMAP4430_ES2_0) ++ volt = SMPS_VOLT_1_1000_V; ++ else if (omap4_rev == OMAP4430_ES2_1) ++ volt = SMPS_VOLT_1_1125_V; ++ else ++ volt = SMPS_VOLT_1_2000_V; ++ ++ do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); ++} ++ ++static void enable_clock_domain(u32 clkctrl_reg, u32 enable_mode) ++{ ++ modify_reg_32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_SHIFT, ++ CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode); ++} ++ ++static inline void wait_for_clk_enable(u32 clkctrl_addr) ++{ ++ u32 idlest = MODULE_CLKCTRL_IDLEST_DISABLED; ++ ++ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || ++ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { ++ idlest = readl(clkctrl_addr); ++ idlest = get_bit_field(idlest, MODULE_CLKCTRL_IDLEST_SHIFT, ++ MODULE_CLKCTRL_IDLEST_MASK); ++ } ++} ++ ++static void enable_clock_module(u32 clkctrl_addr, u32 enable_mode, ++ u32 wait_for_enable) ++{ ++ modify_reg_32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_SHIFT, ++ MODULE_CLKCTRL_MODULEMODE_MASK, enable_mode); ++ if (wait_for_enable) ++ wait_for_clk_enable(clkctrl_addr); ++} ++ ++/* ++ * Enable a set of clock domains and clock modules associated with them ++ */ ++static void enable_clocks(const u32 *clock_domains, ++ const u32 *clock_modules_hw_auto, ++ const u32 *clock_modules_explicit_en, ++ u32 wait_for_enable) ++{ ++ int i = 0, max = 100; ++ /* Put the clock domains in SW_WKUP mode */ ++ for (i = 0; (i < max) && clock_domains[i]; i++) { ++ enable_clock_domain(clock_domains[i], ++ CD_CLKCTRL_CLKTRCTRL_SW_WKUP); ++ } ++ ++ /* Clock modules that need to be put in HW_AUTO */ ++ for (i = 0; (i < max) && clock_modules_hw_auto[i]; i++) { ++ enable_clock_module(clock_modules_hw_auto[i], ++ MODULE_CLKCTRL_MODULEMODE_HW_AUTO, ++ wait_for_enable); ++ }; ++ ++ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ ++ for (i = 0; (i < max) && clock_modules_explicit_en[i]; i++) { ++ enable_clock_module(clock_modules_explicit_en[i], ++ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, ++ wait_for_enable); ++ }; ++ ++ /* Put the clock domains in HW_AUTO mode now */ ++ for (i = 0; (i < max) && clock_domains[i]; i++) { ++ enable_clock_domain(clock_domains[i], ++ CD_CLKCTRL_CLKTRCTRL_HW_AUTO); ++ } ++} ++ ++/* ++ * Enable essential clock domains, modules and ++ * do some additional special settings needed ++ */ ++static void enable_basic_clocks(void) ++{ ++ /* Enable optional additional functional clock for GPIO4 */ ++ writel(readl(CM_L4PER_GPIO4_CLKCTRL) | GPIO4_CLKCTRL_OPTFCLKEN_SHIFT, ++ CM_L4PER_GPIO4_CLKCTRL); ++ ++ /* Enable 96 MHz clock for MMC1 & MMC2 */ ++ writel(readl(CM_L3INIT_HSMMC1_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_SHIFT, ++ CM_L3INIT_HSMMC1_CLKCTRL); ++ writel(readl(CM_L3INIT_HSMMC2_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_SHIFT, ++ CM_L3INIT_HSMMC2_CLKCTRL); ++ ++ /* Select 32KHz clock as the source of GPTIMER1 */ ++ writel(readl(CM_WKUP_GPTIMER1_CLKCTRL) | GPTIMER1_CLKCTRL_CLKSEL_SHIFT, ++ CM_WKUP_GPTIMER1_CLKCTRL); ++ ++ /* Enable optional 48M functional clock for USB PHY */ ++ writel(readl(CM_L3INIT_USBPHY_CLKCTRL) | ++ USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK, CM_L3INIT_USBPHY_CLKCTRL); ++ ++ /* Enable all essential clock domains and modules */ ++ enable_clocks(clk_domains_essential, ++ clk_modules_hw_auto_essential, ++ clk_modules_explicit_en_essential, 1); ++} ++ ++/* ++ * Enable non-essential clock domains, modules and ++ * do some additional special settings needed ++ */ ++static void enable_non_essential_clocks(void) ++{ ++ u32 tmp; ++ /* Enable optional functional clock for ISS */ ++ writel(readl(CM_CAM_ISS_CLKCTRL) | ISS_CLKCTRL_OPTFCLKEN_SHIFT, ++ CM_CAM_ISS_CLKCTRL); ++ ++ /* Enable all optional functional clocks of DSS */ ++ writel(readl(CM_DSS_DSS_CLKCTRL) | DSS_CLKCTRL_OPTFCLKEN_MASK, ++ CM_DSS_DSS_CLKCTRL); ++ ++ /* Enable all non-essential clock domains and modules */ ++ enable_clocks(clk_domains_non_essential, ++ clk_modules_hw_auto_non_essential, ++ clk_modules_explicit_en_non_essential, 0); ++ ++ /* Put camera module in no sleep mode */ ++ tmp = readl(CM_CAM_CLKSTCTRL); ++ set_bit_field(tmp, MODULE_CLKCTRL_MODULEMODE_SHIFT, ++ MODULE_CLKCTRL_MODULEMODE_MASK, ++ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP); ++ writel(tmp, CM_CAM_CLKSTCTRL); ++} ++ ++void freq_update_core(void) ++{ ++ u32 freq_config1 = 0; ++ const struct dpll_params *core_dpll_params; ++ ++ core_dpll_params = get_core_dpll_params(); ++ /* Put EMIF clock domain in sw wakeup mode */ ++ enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_SW_WKUP); ++ wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL); ++ wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL); ++ ++ freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | ++ SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; ++ ++ set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT, ++ SHADOW_FREQ_CONFIG1_DPLL_EN_MASK, DPLL_EN_LOCK); ++ ++ set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT, ++ SHADOW_FREQ_CONFIG1_M2_DIV_MASK, core_dpll_params->m2); ++ ++ writel(freq_config1, CM_SHADOW_FREQ_CONFIG1); ++ while (readl(CM_SHADOW_FREQ_CONFIG1) & ++ SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK) ++ ; ++ ++ /* Put EMIF clock domain back in hw auto mode */ ++ enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_HW_AUTO); ++ wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL); ++ wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL); ++} ++ ++void bypass_dpll(u32 base) ++{ ++ do_bypass_dpll(base); ++ wait_for_bypass(base); ++} ++ ++void lock_dpll(u32 base) ++{ ++ do_lock_dpll(base); ++ wait_for_lock(base); ++} ++ ++u32 get_syc_clk_freq(void) ++ __attribute__ ((weak, alias("__get_syc_clk_freq"))); ++ ++void prcm_init(void) ++{ ++ switch (omap4_hw_init_context()) { ++ case OMAP_INIT_CONTEXT_SPL: ++ scale_vcores(); ++ setup_dplls(); ++ enable_basic_clocks(); ++ break; ++ case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL: ++ setup_non_essential_dplls(); ++ enable_non_essential_clocks(); ++ break; ++ case OMAP_INIT_CONTEXT_XIP_UBOOT: ++ case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH: ++ scale_vcores(); ++ setup_dplls(); ++ enable_basic_clocks(); ++ setup_non_essential_dplls(); ++ enable_non_essential_clocks(); ++ break; ++ } ++} +diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h +new file mode 100644 +index 0000000..fdbe632 +--- /dev/null ++++ b/arch/arm/include/asm/arch-omap4/clocks.h +@@ -0,0 +1,504 @@ ++/* ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef _CLOCKS_OMAP4_H_ ++#define _CLOCKS_OMAP4_H_ ++#include ++ ++#define CM_CLKMODE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4120) ++#define CM_CLKMODE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8140) ++#define CM_CLKMODE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4160) ++#define CM_CLKSEL_CORE (OMAP44XX_L4_CORE_BASE + 0x4100) ++ ++/* PRM.CKGEN module registers */ ++#define CM_ABE_PLL_REF_CLKSEL (OMAP44XX_L4_WKUP_BASE + 0x610C) ++#define CM_SYS_CLKSEL (OMAP44XX_L4_WKUP_BASE + 0x6110) ++ ++/* PRM.WKUP_CM module registers */ ++#define CM_WKUP_CLKSTCTRL (OMAP44XX_L4_WKUP_BASE + 0x7800) ++#define CM_WKUP_L4WKUP_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7820) ++#define CM_WKUP_WDTIMER1_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7828) ++#define CM_WKUP_WDTIMER2_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7830) ++#define CM_WKUP_GPIO1_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7838) ++#define CM_WKUP_GPTIMER1_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7840) ++#define CM_WKUP_GPTIMER12_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7848) ++#define CM_WKUP_SYNCTIMER_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7850) ++#define CM_WKUP_USIM_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7858) ++#define CM_WKUP_SARRAM_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7860) ++#define CM_WKUP_KEYBOARD_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7878) ++#define CM_WKUP_RTC_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7880) ++#define CM_WKUP_BANDGAP_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7888) ++ ++/* DEVICE_PRM Registers */ ++#define PRM_VC_VAL_BYPASS (OMAP44XX_L4_WKUP_BASE + 0x7BA0) ++#define PRM_VC_CFG_CHANNEL (OMAP44XX_L4_WKUP_BASE + 0x7BA4) ++#define PRM_VC_CFG_I2C_MODE (OMAP44XX_L4_WKUP_BASE + 0x7BA8) ++#define PRM_VC_CFG_I2C_CLK (OMAP44XX_L4_WKUP_BASE + 0x7BAC) ++ ++/* CM1.CKGEN module registers */ ++#define CM_CLKSEL_CORE (OMAP44XX_L4_CORE_BASE + 0x4100) ++#define CM_CLKSEL_ABE (OMAP44XX_L4_CORE_BASE + 0x4108) ++#define CM_DLL_CTRL (OMAP44XX_L4_CORE_BASE + 0x4110) ++#define CM_CLKMODE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4120) ++#define CM_IDLEST_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4124) ++#define CM_AUTOIDLE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4128) ++#define CM_CLKSEL_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x412c) ++#define CM_DIV_M2_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4130) ++#define CM_DIV_M3_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4134) ++#define CM_DIV_M4_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4138) ++#define CM_DIV_M5_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x413c) ++#define CM_DIV_M6_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4140) ++#define CM_DIV_M7_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4144) ++#define CM_SSC_DELTAMSTEP_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4148) ++#define CM_SSC_MODFREQDIV_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x414c) ++#define CM_EMU_OVERRIDE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4150) ++#define CM_CLKMODE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4160) ++#define CM_IDLEST_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4164) ++#define CM_AUTOIDLE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4168) ++#define CM_CLKSEL_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x416c) ++#define CM_DIV_M2_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4170) ++#define CM_SSC_DELTAMSTEP_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4188) ++#define CM_SSC_MODFREQDIV_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x418c) ++#define CM_BYPCLK_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x419c) ++#define CM_CLKMODE_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41a0) ++#define CM_IDLEST_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41a4) ++#define CM_AUTOIDLE_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41a8) ++#define CM_CLKSEL_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41ac) ++#define CM_DIV_M4_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41b8) ++#define CM_DIV_M5_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41bc) ++#define CM_SSC_DELTAMSTEP_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41c8) ++#define CM_SSC_MODFREQDIV_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41cc) ++#define CM_BYPCLK_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41dc) ++#define CM_CLKMODE_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41e0) ++#define CM_IDLEST_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41e4) ++#define CM_AUTOIDLE_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41e8) ++#define CM_CLKSEL_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41ec) ++#define CM_DIV_M2_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41f0) ++#define CM_DIV_M3_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41f4) ++#define CM_SSC_DELTAMSTEP_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x4208) ++#define CM_SSC_MODFREQDIV_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x420c) ++#define CM_CLKMODE_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4220) ++#define CM_IDLEST_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4224) ++#define CM_AUTOIDLE_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4228) ++#define CM_CLKSEL_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x422c) ++#define CM_DIV_M2_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4230) ++#define CM_DIV_M4_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4238) ++#define CM_DIV_M5_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x423c) ++#define CM_DIV_M6_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4240) ++#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4248) ++#define CM_SHADOW_FREQ_CONFIG1 (OMAP44XX_L4_CORE_BASE + 0x4260) ++ ++/* CM1.ABE register offsets */ ++#define CM1_ABE_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x4500) ++#define CM1_ABE_L4ABE_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4520) ++#define CM1_ABE_AESS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4528) ++#define CM1_ABE_PDM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4530) ++#define CM1_ABE_DMIC_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4538) ++#define CM1_ABE_MCASP_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4540) ++#define CM1_ABE_MCBSP1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4548) ++#define CM1_ABE_MCBSP2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4550) ++#define CM1_ABE_MCBSP3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4558) ++#define CM1_ABE_SLIMBUS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4560) ++#define CM1_ABE_TIMER5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4568) ++#define CM1_ABE_TIMER6_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4570) ++#define CM1_ABE_TIMER7_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4578) ++#define CM1_ABE_TIMER8_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4580) ++#define CM1_ABE_WDT3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4588) ++ ++/* CM1.DSP register offsets */ ++#define CM_DSP_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x4400) ++#define CM_DSP_DSP_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4420) ++ ++/* CM2.CKGEN module registers */ ++#define CM_CLKSEL_MPU_M3_ISS_ROOT (OMAP44XX_L4_CORE_BASE + 0x8100) ++#define CM_CLKSEL_USB_60MHz (OMAP44XX_L4_CORE_BASE + 0x8104) ++#define CM_SCALE_FCLK (OMAP44XX_L4_CORE_BASE + 0x8108) ++#define CM_CORE_DVFS_PERF1 (OMAP44XX_L4_CORE_BASE + 0x8110) ++#define CM_CORE_DVFS_PERF2 (OMAP44XX_L4_CORE_BASE + 0x8114) ++#define CM_CORE_DVFS_PERF3 (OMAP44XX_L4_CORE_BASE + 0x8118) ++#define CM_CORE_DVFS_PERF4 (OMAP44XX_L4_CORE_BASE + 0x811c) ++#define CM_CORE_DVFS_CURRENT (OMAP44XX_L4_CORE_BASE + 0x8124) ++#define CM_IVA_DVFS_PERF_TESLA (OMAP44XX_L4_CORE_BASE + 0x8128) ++#define CM_IVA_DVFS_PERF_IVAHD (OMAP44XX_L4_CORE_BASE + 0x812c) ++#define CM_IVA_DVFS_PERF_ABE (OMAP44XX_L4_CORE_BASE + 0x8130) ++#define CM_IVA_DVFS_CURRENT (OMAP44XX_L4_CORE_BASE + 0x8138) ++#define CM_CLKMODE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8140) ++#define CM_IDLEST_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8144) ++#define CM_AUTOIDLE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8148) ++#define CM_CLKSEL_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x814c) ++#define CM_DIV_M2_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8150) ++#define CM_DIV_M3_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8154) ++#define CM_DIV_M4_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8158) ++#define CM_DIV_M5_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x815c) ++#define CM_DIV_M6_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8160) ++#define CM_DIV_M7_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8164) ++#define CM_SSC_DELTAMSTEP_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8168) ++#define CM_SSC_MODFREQDIV_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x816c) ++#define CM_EMU_OVERRIDE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8170) ++#define CM_CLKMODE_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8180) ++#define CM_IDLEST_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8184) ++#define CM_AUTOIDLE_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8188) ++#define CM_CLKSEL_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x818c) ++#define CM_DIV_M2_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8190) ++#define CM_SSC_DELTAMSTEP_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x81a8) ++#define CM_SSC_MODFREQDIV_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x81ac) ++#define CM_CLKDCOLDO_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x81b4) ++#define CM_CLKMODE_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81c0) ++#define CM_IDLEST_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81c4) ++#define CM_AUTOIDLE_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81c8) ++#define CM_CLKSEL_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81cc) ++#define CM_DIV_M2_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81d0) ++#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81e8) ++#define CM_SSC_MODFREQDIV_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81ec) ++ ++/* CM2.CORE module registers */ ++#define CM_L3_1_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8700) ++#define CM_L3_1_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8708) ++#define CM_L3_1_L3_1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8720) ++#define CM_L3_2_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8800) ++#define CM_L3_2_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8808) ++#define CM_L3_2_L3_2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8820) ++#define CM_L3_2_GPMC_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8828) ++#define CM_L3_2_OCMC_RAM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8830) ++#define CM_MPU_M3_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8900) ++#define CM_MPU_M3_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x8904) ++#define CM_MPU_M3_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8908) ++#define CM_MPU_M3_MPU_M3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8920) ++#define CM_SDMA_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8a00) ++#define CM_SDMA_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x8a04) ++#define CM_SDMA_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8a08) ++#define CM_SDMA_SDMA_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8a20) ++#define CM_MEMIF_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8b00) ++#define CM_MEMIF_DMM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b20) ++#define CM_MEMIF_EMIF_FW_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b28) ++#define CM_MEMIF_EMIF_1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b30) ++#define CM_MEMIF_EMIF_2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b38) ++#define CM_MEMIF_DLL_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b40) ++#define CM_MEMIF_EMIF_H1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b50) ++#define CM_MEMIF_EMIF_H2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b58) ++#define CM_MEMIF_DLL_H_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b60) ++#define CM_C2C_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8c00) ++#define CM_C2C_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x8c04) ++#define CM_C2C_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8c08) ++#define CM_C2C_SAD2D_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8c20) ++#define CM_C2C_MODEM_ICR_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8c28) ++#define CM_C2C_SAD2D_FW_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8c30) ++#define CM_L4CFG_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8d00) ++#define CM_L4CFG_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8d08) ++#define CM_L4CFG_L4_CFG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d20) ++#define CM_L4CFG_HW_SEM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d28) ++#define CM_L4CFG_MAILBOX_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d30) ++#define CM_L4CFG_SAR_ROM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d38) ++#define CM_L3INSTR_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8e00) ++#define CM_L3INSTR_L3_3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8e20) ++#define CM_L3INSTR_L3_INSTR_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8e28) ++#define CM_L3INSTR_INTRCONN_WP1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8e40) ++ ++/* CM2.L3INIT register offsets */ ++#define CM_L3INIT_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9300) ++ ++/* CM2.L4PER register offsets */ ++#define CM_L4PER_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9400) ++#define CM_L4PER_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x9408) ++#define CM_L4PER_ADC_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9420) ++#define CM_L4PER_GPTIMER10_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9428) ++#define CM_L4PER_GPTIMER11_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9430) ++#define CM_L4PER_GPTIMER2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9438) ++#define CM_L4PER_GPTIMER3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9440) ++#define CM_L4PER_GPTIMER4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9448) ++#define CM_L4PER_GPTIMER9_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9450) ++#define CM_L4PER_ELM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9458) ++#define CM_L4PER_GPIO2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9460) ++#define CM_L4PER_GPIO3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9468) ++#define CM_L4PER_GPIO4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9470) ++#define CM_L4PER_GPIO5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9478) ++#define CM_L4PER_GPIO6_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9480) ++#define CM_L4PER_HDQ1W_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9488) ++#define CM_L4PER_HECC1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9490) ++#define CM_L4PER_HECC2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9498) ++#define CM_L4PER_I2C1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94a0) ++#define CM_L4PER_I2C2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94a8) ++#define CM_L4PER_I2C3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94b0) ++#define CM_L4PER_I2C4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94b8) ++#define CM_L4PER_L4PER_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94c0) ++#define CM_L4PER_MCASP2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94d0) ++#define CM_L4PER_MCASP3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94d8) ++#define CM_L4PER_MCBSP4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94e0) ++#define CM_L4PER_MGATE_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94e8) ++#define CM_L4PER_MCSPI1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94f0) ++#define CM_L4PER_MCSPI2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94f8) ++#define CM_L4PER_MCSPI3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9500) ++#define CM_L4PER_MCSPI4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9508) ++#define CM_L4PER_MMCSD3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9520) ++#define CM_L4PER_MMCSD4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9528) ++#define CM_L4PER_MSPROHG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9530) ++#define CM_L4PER_SLIMBUS2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9538) ++#define CM_L4PER_UART1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9540) ++#define CM_L4PER_UART2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9548) ++#define CM_L4PER_UART3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9550) ++#define CM_L4PER_UART4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9558) ++#define CM_L4PER_MMCSD5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9560) ++#define CM_L4PER_I2C5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9568) ++#define CM_L4SEC_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9580) ++#define CM_L4SEC_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x9584) ++#define CM_L4SEC_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x9588) ++#define CM_L4SEC_AES1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95a0) ++#define CM_L4SEC_AES2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95a8) ++#define CM_L4SEC_DES3DES_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95b0) ++#define CM_L4SEC_PKAEIP29_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95b8) ++#define CM_L4SEC_RNG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95c0) ++#define CM_L4SEC_SHA2MD51_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95c8) ++#define CM_L4SEC_CRYPTODMA_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95d8) ++ ++/* CM2.IVAHD */ ++#define CM_IVAHD_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8f00) ++#define CM_IVAHD_IVAHD_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8f20) ++#define CM_IVAHD_SL2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8f28) ++ ++/* CM2.L3INIT */ ++#define CM_L3INIT_HSMMC1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9328) ++#define CM_L3INIT_HSMMC2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9330) ++#define CM_L3INIT_HSI_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9338) ++#define CM_L3INIT_HSUSBHOST_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9358) ++#define CM_L3INIT_HSUSBOTG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9360) ++#define CM_L3INIT_HSUSBTLL_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9368) ++#define CM_L3INIT_P1500_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9378) ++#define CM_L3INIT_FSUSB_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x93d0) ++#define CM_L3INIT_USBPHY_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x93e0) ++ ++/* CM2.CAM */ ++#define CM_CAM_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9000) ++#define CM_CAM_ISS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9020) ++#define CM_CAM_FDIF_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9028) ++ ++/* CM2.DSS */ ++#define CM_DSS_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9100) ++#define CM_DSS_DSS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9120) ++ ++/* CM2.SGX */ ++#define CM_SGX_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9200) ++#define CM_SGX_SGX_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9220) ++ ++/* DPLL register offsets */ ++#define CM_CLKMODE_DPLL 0 ++#define CM_IDLEST_DPLL 0x4 ++#define CM_AUTOIDLE_DPLL 0x8 ++#define CM_CLKSEL_DPLL 0xC ++#define CM_DIV_M2_DPLL 0x10 ++#define CM_DIV_M3_DPLL 0x14 ++#define CM_DIV_M4_DPLL 0x18 ++#define CM_DIV_M5_DPLL 0x1C ++#define CM_DIV_M6_DPLL 0x20 ++#define CM_DIV_M7_DPLL 0x24 ++ ++#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ ++ ++/* CM_CLKMODE_DPLL */ ++#define CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK 11 ++#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 ++#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 ++#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 ++ ++#define DPLL_EN_STOP 1 ++#define DPLL_EN_MN_BYPASS 4 ++#define DPLL_EN_LOW_POWER_BYPASS 5 ++#define DPLL_EN_FAST_RELOCK_BYPASS 6 ++#define DPLL_EN_LOCK 7 ++ ++/* CM_IDLEST_DPLL fields */ ++#define ST_DPLL_CLK_MASK 1 ++ ++/* CM_CLKSEL_DPLL */ ++#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 ++#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) ++#define CM_CLKSEL_DPLL_M_SHIFT 8 ++#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) ++#define CM_CLKSEL_DPLL_N_SHIFT 0 ++#define CM_CLKSEL_DPLL_N_MASK 0x7F ++ ++#define OMAP4_DPLL_MAX_N 127 ++ ++/* CM_SYS_CLKSEL */ ++#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 ++ ++/* CM_CLKSEL_CORE */ ++#define CLKSEL_CORE_SHIFT 0 ++#define CLKSEL_L3_SHIFT 4 ++#define CLKSEL_L4_SHIFT 8 ++ ++#define CLKSEL_CORE_X2_DIV_1 0 ++#define CLKSEL_L3_CORE_DIV_2 1 ++#define CLKSEL_L4_L3_DIV_2 1 ++ ++/* CM_ABE_PLL_REF_CLKSEL */ ++#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 ++#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 ++#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 ++#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 ++ ++ ++/* CM_SHADOW_FREQ_CONFIG1 */ ++#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 ++#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 ++#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 ++ ++#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 ++#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) ++ ++#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 ++#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) ++ ++/*CM___CLKCTRL */ ++#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 ++#define CD_CLKCTRL_CLKTRCTRL_MASK 3 ++ ++#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 ++#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 ++#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 ++#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 ++ ++ ++/* CM___CLKCTRL */ ++#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 ++#define MODULE_CLKCTRL_MODULEMODE_MASK 3 ++#define MODULE_CLKCTRL_IDLEST_SHIFT 16 ++#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) ++ ++#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 ++#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 ++#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 ++ ++#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 ++#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 ++#define MODULE_CLKCTRL_IDLEST_IDLE 2 ++#define MODULE_CLKCTRL_IDLEST_DISABLED 3 ++ ++/* CM_L4PER_GPIO4_CLKCTRL */ ++#define GPIO4_CLKCTRL_OPTFCLKEN_SHIFT 8 ++ ++/* CM_L3INIT_HSMMCn_CLKCTRL */ ++#define HSMMC_CLKCTRL_CLKSEL_SHIFT 24 ++ ++/* CM_WKUP_GPTIMER1_CLKCTRL */ ++#define GPTIMER1_CLKCTRL_CLKSEL_SHIFT 24 ++ ++/* CM_CAM_ISS_CLKCTRL */ ++#define ISS_CLKCTRL_OPTFCLKEN_SHIFT 8 ++ ++/* CM_DSS_DSS_CLKCTRL */ ++#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 ++ ++/* CM_L3INIT_USBPHY_CLKCTRL */ ++#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 ++ ++/* Clock frequencies */ ++#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 ++#define OMAP_32K_CLK_FREQ 32768 ++ ++/* PRM_VC_CFG_I2C_CLK */ ++#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 ++#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF ++#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 ++#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) ++ ++/* PRM_VC_VAL_BYPASS */ ++#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 ++ ++#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 ++#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 ++#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F ++#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 ++#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF ++#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 ++#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF ++ ++#define SMPS_I2C_SLAVE_ADDR 0x12 ++#define SMPS_REG_ADDR_VCORE1 0x55 ++#define SMPS_REG_ADDR_VCORE2 0x5B ++#define SMPS_REG_ADDR_VCORE3 0x61 ++ ++#define SMPS_VOLT_1_0000_V 0x21 ++#define SMPS_VOLT_1_0125_V 0x22 ++#define SMPS_VOLT_1_0250_V 0x23 ++#define SMPS_VOLT_1_0375_V 0x24 ++#define SMPS_VOLT_1_0500_V 0x25 ++#define SMPS_VOLT_1_0625_V 0x26 ++#define SMPS_VOLT_1_0750_V 0x27 ++#define SMPS_VOLT_1_0875_V 0x28 ++#define SMPS_VOLT_1_1000_V 0x29 ++#define SMPS_VOLT_1_1125_V 0x2A ++#define SMPS_VOLT_1_1250_V 0x2B ++#define SMPS_VOLT_1_1375_V 0x2C ++#define SMPS_VOLT_1_1500_V 0x2D ++#define SMPS_VOLT_1_1625_V 0x2E ++#define SMPS_VOLT_1_1750_V 0x2F ++#define SMPS_VOLT_1_1875_V 0x30 ++#define SMPS_VOLT_1_2000_V 0x31 ++#define SMPS_VOLT_1_2125_V 0x32 ++#define SMPS_VOLT_1_2250_V 0x33 ++#define SMPS_VOLT_1_2375_V 0x34 ++#define SMPS_VOLT_1_2500_V 0x35 ++#define SMPS_VOLT_1_2625_V 0x36 ++#define SMPS_VOLT_1_2750_V 0x37 ++#define SMPS_VOLT_1_2875_V 0x38 ++#define SMPS_VOLT_1_3000_V 0x39 ++#define SMPS_VOLT_1_3500_V 0x3A ++#define SMPS_VOLT_1_5000_V 0x3B ++#define SMPS_VOLT_1_5000_V 0x3B ++ ++/* Defines for DPLL setup */ ++#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 ++#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 ++#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 ++ ++#define CONFIGURE_NO_LOCK 0 ++#define CONFIGURE_AND_LOCK 1 ++ ++struct dpll_regs { ++ u32 cm_clkmode_dpll; ++ u32 cm_idlest_dpll; ++ u32 cm_autoidle_dpll; ++ u32 cm_clksel_dpll; ++ u32 cm_div_m2_dpll; ++ u32 cm_div_m3_dpll; ++ u32 cm_div_m4_dpll; ++ u32 cm_div_m5_dpll; ++ u32 cm_div_m6_dpll; ++ u32 cm_div_m7_dpll; ++}; ++ ++/* DPLL parameter table */ ++struct dpll_params { ++ s32 m; ++ s32 n; ++ u32 locked_freq_khz; ++ s32 m2; ++ s32 m3; ++ s32 m4; ++ s32 m5; ++ s32 m6; ++ s32 m7; ++}; ++ ++#endif /* _CLOCKS_OMAP4_H_ */ +diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h +index 33a1666..fd21afd 100644 +--- a/arch/arm/include/asm/arch-omap4/sys_proto.h ++++ b/arch/arm/include/asm/arch-omap4/sys_proto.h +@@ -39,6 +39,12 @@ void set_muxconf_regs_non_essential(void); + void sr32(void *, u32, u32, u32); + u32 wait_on_value(u32, u32, void *, u32); + void sdelay(unsigned long); ++void prcm_init(void); ++void bypass_dpll(u32 base); ++void freq_update_core(void); ++u32 get_syc_clk_freq(void); ++u32 omap4_ddr_clk(void); ++u32 omap4_revision(void); + + static inline u32 running_from_sdram(void) + { +diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h +index 50247af..49daa85 100644 +--- a/arch/arm/include/asm/omap_common.h ++++ b/arch/arm/include/asm/omap_common.h +@@ -25,6 +25,9 @@ + #ifndef _OMAP_COMMON_H_ + #define _OMAP_COMMON_H_ + ++/* Max value for DPLL multiplier M */ ++#define OMAP_DPLL_MAX_N 127 ++ + /* extract a bit field from a bit vector */ + #define get_bit_field(nr, start, mask)\ + (((nr) & (mask)) >> (start)) +diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile +index 6a6aa42..40e3e79 100644 +--- a/spl/board/ti/sdp4430/Makefile ++++ b/spl/board/ti/sdp4430/Makefile +@@ -115,8 +115,12 @@ $(obj)board.c:$(obj)omap4_mux_data.h + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@ + ++$(obj)clocks.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@ ++ + SOBJS += lowlevel_init.o +-COBJS += board.o ++COBJS += board.o clocks.o + + # rules + LDPPFLAGS += -include $(TOPDIR)/include/config.h +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0016-omap4-add-sdram-init-support.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0016-omap4-add-sdram-init-support.patch new file mode 100644 index 0000000000..40d85ac0be --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0016-omap4-add-sdram-init-support.patch @@ -0,0 +1,1272 @@ +From c978b5c00d5b6c19364a171c9c44a65bc0c96c59 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Fri, 25 Feb 2011 16:30:28 +0530 +Subject: [PATCH 16/22] omap4: add sdram init support + +Add support for the SDRAM controller (EMIF). + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap4/Makefile | 3 + + arch/arm/cpu/armv7/omap4/board.c | 2 +- + arch/arm/cpu/armv7/omap4/emif.c | 281 +++++++++++ + arch/arm/cpu/armv7/omap4/sdram_elpida.c | 118 +++++ + arch/arm/include/asm/arch-omap4/emif.h | 719 +++++++++++++++++++++++++++ + arch/arm/include/asm/arch-omap4/omap4.h | 11 + + arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + + include/configs/omap4_sdp4430.h | 5 - + spl/board/ti/sdp4430/Makefile | 10 +- + 9 files changed, 1143 insertions(+), 7 deletions(-) + create mode 100644 arch/arm/cpu/armv7/omap4/emif.c + create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c + create mode 100644 arch/arm/include/asm/arch-omap4/emif.h + +diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile +index 6154e86..d9714fe 100644 +--- a/arch/arm/cpu/armv7/omap4/Makefile ++++ b/arch/arm/cpu/armv7/omap4/Makefile +@@ -31,6 +31,9 @@ COBJS += board.o + COBJS += mem.o + COBJS += sys_info.o + COBJS += clocks.o ++COBJS += emif.o ++COBJS += sdram_elpida.o ++ + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c +index 62a59ad..89b1213 100644 +--- a/arch/arm/cpu/armv7/omap4/board.c ++++ b/arch/arm/cpu/armv7/omap4/board.c +@@ -109,6 +109,7 @@ void s_init(void) + #ifdef CONFIG_PRELOADER + preloader_console_init(); + #endif ++ sdram_init(); + } + + /* +@@ -169,7 +170,6 @@ u32 sdram_size(void) + */ + int dram_init(void) + { +- + gd->ram_size = sdram_size(); + + return 0; +diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c +new file mode 100644 +index 0000000..ee77743 +--- /dev/null ++++ b/arch/arm/cpu/armv7/omap4/emif.c +@@ -0,0 +1,281 @@ ++/* ++ * EMIF programming ++ * ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++static inline u32 emif_num(u32 base) ++{ ++ if (base == OMAP44XX_EMIF1) ++ return 1; ++ else if (base == OMAP44XX_EMIF2) ++ return 2; ++ else ++ return 0; ++} ++ ++static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) ++{ ++ u32 mr; ++ struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ++ ++ mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; ++ writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); ++ if (omap4_revision() == OMAP4430_ES2_0) ++ mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); ++ else ++ mr = readl(&emif->emif_lpddr2_mode_reg_data); ++ debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), ++ cs, mr_addr, mr); ++ return mr; ++} ++ ++static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) ++{ ++ struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ++ ++ mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; ++ writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); ++ writel(mr_val, &emif->emif_lpddr2_mode_reg_data); ++} ++void emif_reset_phy(u32 base) ++{ ++ struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ++ u32 iodft; ++ ++ iodft = readl(&emif->emif_iodft_tlgc); ++ iodft |= OMAP44XX_REG_RESET_PHY_MASK; ++ writel(iodft, &emif->emif_iodft_tlgc); ++} ++ ++static void do_lpddr2_init(u32 base, u32 cs) ++{ ++ u32 mr_addr; ++ ++ /* Wait till device auto initialization is complete */ ++ while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) ++ ; ++ set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); ++ sdelay(10); ++ set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); ++ set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); ++ /* ++ * Enable refresh along with writing MR2 ++ * Encoding of RL in MR2 is (RL - 2) ++ */ ++ mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK; ++ set_mr(base, cs, mr_addr, RL_FINAL - 2); ++} ++ ++static void lpddr2_init(u32 base, const struct emif_regs *regs) ++{ ++ struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ++ u32 nvm; ++ ++ /* Not NVM */ ++ nvm = readl(&emif->emif_lpddr2_nvm_config); ++ nvm &= (~OMAP44XX_REG_CS1NVMEN_MASK); ++ writel(nvm, &emif->emif_lpddr2_nvm_config); ++ /* ++ * Set the SDRAM_CONFIG and PHY_CTRL for the ++ * un-locked frequency & default RL ++ */ ++ writel(regs->sdram_config_init, &emif->emif_sdram_config); ++ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); ++ ++ do_lpddr2_init(base, CS0); ++ if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK) ++ do_lpddr2_init(base, CS1); ++ ++ writel(regs->sdram_config, &emif->emif_sdram_config); ++ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); ++} ++ ++static void emif_update_timings(u32 base, const struct emif_regs *regs) ++{ ++ struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ++ ++ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); ++ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); ++ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); ++ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); ++ if (omap4_revision() == OMAP4430_ES1_0) { ++ /* ES1 bug EMIF should be in force idle during freq_update */ ++ writel(0, &emif->emif_pwr_mgmt_ctrl); ++ } else { ++ writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); ++ writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); ++ } ++ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); ++ writel(regs->zq_config, &emif->emif_zq_config); ++ writel(regs->temp_alert_config, &emif->emif_temp_alert_config); ++ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); ++ /* ++ * Workaround: ++ * In a specific situation, the OCP interface between the DMM and ++ * EMIF may hang. ++ * 1. A TILER port is used to perform 2D burst writes of ++ * width 1 and height 8 ++ * 2. ELLAn port is used to perform reads ++ * 3. All accesses are routed to the same EMIF controller ++ * ++ * Work around to avoid this issue REG_SYS_THRESH_MAX value should ++ * be kept higher than default 0x7. As per recommondation 0x0A will ++ * be used for better performance with REG_LL_THRESH_MAX = 0x00 ++ */ ++ if (omap4_revision() == OMAP4430_ES1_0) { ++ writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00, ++ &emif->emif_l3_config); ++ } ++} ++ ++static void do_sdram_init(u32 base) ++{ ++ const struct emif_regs *regs, *tmp_regs; ++ u32 in_sdram, emif_nr; ++ ++ in_sdram = running_from_sdram(); ++ emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2; ++ ++ emif_get_reg_dump(®s, &tmp_regs); ++ regs = (emif_nr == 1) ? regs : tmp_regs; ++ ++ /* ++ * Initializing the LPDDR2 device can not happen from SDRAM. ++ * Changing the timing registers in EMIF can happen(going from one ++ * OPP to another) ++ */ ++ if (!in_sdram) ++ lpddr2_init(base, regs); ++ ++ /* Write to the shadow registers */ ++ emif_update_timings(base, regs); ++} ++ ++void sdram_init_pads(void) ++{ ++ u32 lpddr2io; ++ u32 omap4_rev = omap4_revision(); ++ ++ if (omap4_rev == OMAP4430_ES1_0) ++ lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; ++ else if (omap4_rev == OMAP4430_ES2_0) ++ lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; ++ else ++ return; /* Post ES2.1 reset values will work */ ++ ++ writel(lpddr2io, CONTROL_LPDDR2IO1_0); ++ writel(lpddr2io, CONTROL_LPDDR2IO1_1); ++ writel(lpddr2io, CONTROL_LPDDR2IO1_2); ++ writel(lpddr2io, CONTROL_LPDDR2IO2_0); ++ writel(lpddr2io, CONTROL_LPDDR2IO2_1); ++ writel(lpddr2io, CONTROL_LPDDR2IO2_2); ++ ++ writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2); ++} ++ ++static void emif_post_init_config(u32 base) ++{ ++ struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ++ u32 omap4_rev = omap4_revision(); ++ ++ /* reset phy on ES2.0 */ ++ if (omap4_rev == OMAP4430_ES2_0) ++ emif_reset_phy(base); ++ ++ /* Put EMIF back in smart idle on ES1.0 */ ++ if (omap4_rev == OMAP4430_ES1_0) ++ writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); ++} ++ ++static void dmm_init(u32 base) ++{ ++ const struct dmm_lisa_map_regs *lisa_map_regs; ++ ++ emif_get_dmm_regs(&lisa_map_regs); ++ ++ struct dmm_lisa_map_regs *hw_lisa_map_regs = ++ (struct dmm_lisa_map_regs *)base; ++ ++ writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); ++ writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); ++ writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); ++ writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); ++ ++ writel(lisa_map_regs->dmm_lisa_map_3, ++ &hw_lisa_map_regs->dmm_lisa_map_3); ++ writel(lisa_map_regs->dmm_lisa_map_2, ++ &hw_lisa_map_regs->dmm_lisa_map_2); ++ writel(lisa_map_regs->dmm_lisa_map_1, ++ &hw_lisa_map_regs->dmm_lisa_map_1); ++ writel(lisa_map_regs->dmm_lisa_map_0, ++ &hw_lisa_map_regs->dmm_lisa_map_0); ++} ++ ++/* ++ * SDRAM initialization: ++ * SDRAM initialization has two parts: ++ * 1. Configuring the SDRAM device ++ * 2. Update the AC timings related parameters in the EMIF module ++ * (1) should be done only once and should not be done while we are ++ * running from SDRAM. ++ * (2) can and should be done more than once if OPP changes. ++ * Particularly, this may be needed when we boot without SPL and ++ * and using Configuration Header(CH). ROM code supports only at 50% OPP ++ * at boot (low power boot). So u-boot has to switch to OPP100 and update ++ * the frequency. So, ++ * Doing (1) and (2) makes sense - first time initialization ++ * Doing (2) and not (1) makes sense - OPP change (when using CH) ++ * Doing (1) and not (2) doen't make sense ++ * See do_sdram_init() for the details ++ */ ++void sdram_init(void) ++{ ++ u32 in_sdram; ++ ++ in_sdram = running_from_sdram(); ++ ++ if (!in_sdram) { ++ sdram_init_pads(); ++ bypass_dpll(CM_CLKMODE_DPLL_CORE); ++ } ++ ++ do_sdram_init(OMAP44XX_EMIF1); ++ do_sdram_init(OMAP44XX_EMIF2); ++ ++ if (!in_sdram) { ++ dmm_init(OMAP44XX_DMM_LISA_MAP_BASE); ++ emif_post_init_config(OMAP44XX_EMIF1); ++ emif_post_init_config(OMAP44XX_EMIF2); ++ } ++ ++ /* for the shadow registers to take effect */ ++ freq_update_core(); ++} +diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c +new file mode 100644 +index 0000000..37e808c +--- /dev/null ++++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c +@@ -0,0 +1,118 @@ ++/* ++ * Timing and Organization details of the Elpida parts used in OMAP4 ++ * SDPs and Panda ++ * ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { ++ .sdram_config_init = 0x80000eb9, ++ .sdram_config = 0x80001ab9, ++ .ref_ctrl = 0x0000030c, ++ .sdram_tim1 = 0x08648311, ++ .sdram_tim2 = 0x101b06ca, ++ .sdram_tim3 = 0x0048a19f, ++ .read_idle_ctrl = 0x000501ff, ++ .zq_config = 0x500b3214, ++ .temp_alert_config = 0xd8016893, ++ .emif_ddr_phy_ctlr_1_init = 0x049ffff5, ++ .emif_ddr_phy_ctlr_1 = 0x049ff808 ++}; ++ ++static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { ++ .sdram_config_init = 0x80000eb1, ++ .sdram_config = 0x80001ab1, ++ .ref_ctrl = 0x000005cd, ++ .sdram_tim1 = 0x10cb0622, ++ .sdram_tim2 = 0x20350d52, ++ .sdram_tim3 = 0x00b1431f, ++ .read_idle_ctrl = 0x000501ff, ++ .zq_config = 0x500b3214, ++ .temp_alert_config = 0x58016893, ++ .emif_ddr_phy_ctlr_1_init = 0x049ffff5, ++ .emif_ddr_phy_ctlr_1 = 0x049ff418 ++}; ++ ++const struct emif_regs emif_regs_elpida_400_mhz_2cs = { ++ .sdram_config_init = 0x80000eb9, ++ .sdram_config = 0x80001ab9, ++ .ref_ctrl = 0x00000618, ++ .sdram_tim1 = 0x10eb0662, ++ .sdram_tim2 = 0x20370dd2, ++ .sdram_tim3 = 0x00b1c33f, ++ .read_idle_ctrl = 0x000501ff, ++ .zq_config = 0xd00b3214, ++ .temp_alert_config = 0xd8016893, ++ .emif_ddr_phy_ctlr_1_init = 0x049ffff5, ++ .emif_ddr_phy_ctlr_1 = 0x049ff418 ++}; ++const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { ++ .dmm_lisa_map_0 = 0xFF020100, ++ .dmm_lisa_map_1 = 0, ++ .dmm_lisa_map_2 = 0, ++ .dmm_lisa_map_3 = 0x80540300 ++}; ++ ++const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { ++ .dmm_lisa_map_0 = 0xFF020100, ++ .dmm_lisa_map_1 = 0, ++ .dmm_lisa_map_2 = 0, ++ .dmm_lisa_map_3 = 0x80640300 ++}; ++ ++void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs, ++ const struct emif_regs **emif2_regs) ++{ ++ u32 omap4_rev = omap4_revision(); ++ ++ if (omap4_rev == OMAP4430_ES1_0) { ++ *emif1_regs = &emif_regs_elpida_380_mhz_1cs; ++ *emif2_regs = &emif_regs_elpida_380_mhz_1cs; ++ } else if (omap4_rev == OMAP4430_ES2_0) { ++ *emif1_regs = &emif_regs_elpida_200_mhz_2cs; ++ *emif2_regs = &emif_regs_elpida_200_mhz_2cs; ++ } else { ++ *emif1_regs = &emif_regs_elpida_400_mhz_2cs; ++ *emif2_regs = &emif_regs_elpida_400_mhz_2cs; ++ } ++} ++void emif_get_reg_dump(const struct emif_regs **emif1_regs, ++ const struct emif_regs **emif2_regs) ++ __attribute__((weak, alias("emif_get_reg_dump_sdp"))); ++ ++void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) ++{ ++ u32 omap_rev = omap4_revision(); ++ ++ if (omap_rev == OMAP4430_ES1_0) ++ *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; ++ else ++ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; ++} ++ ++void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) ++ __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); +diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h +new file mode 100644 +index 0000000..f2d54cb +--- /dev/null ++++ b/arch/arm/include/asm/arch-omap4/emif.h +@@ -0,0 +1,719 @@ ++/* ++ * OMAP44xx EMIF header ++ * ++ * Copyright (C) 2009-2010 Texas Instruments, Inc. ++ * ++ * Aneesh V ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _EMIF_H_ ++#define _EMIF_H_ ++#include ++#include ++ ++/* Base address */ ++#define OMAP44XX_EMIF1 0x4c000000 ++#define OMAP44XX_EMIF2 0x4d000000 ++ ++/* Registers shifts and masks */ ++ ++/* EMIF_MOD_ID_REV */ ++#define OMAP44XX_REG_SCHEME_SHIFT 30 ++#define OMAP44XX_REG_SCHEME_MASK (0x3 << 30) ++#define OMAP44XX_REG_MODULE_ID_SHIFT 16 ++#define OMAP44XX_REG_MODULE_ID_MASK (0xfff << 16) ++#define OMAP44XX_REG_RTL_VERSION_SHIFT 11 ++#define OMAP44XX_REG_RTL_VERSION_MASK (0x1f << 11) ++#define OMAP44XX_REG_MAJOR_REVISION_SHIFT 8 ++#define OMAP44XX_REG_MAJOR_REVISION_MASK (0x7 << 8) ++#define OMAP44XX_REG_MINOR_REVISION_SHIFT 0 ++#define OMAP44XX_REG_MINOR_REVISION_MASK (0x3f << 0) ++ ++/* STATUS */ ++#define OMAP44XX_REG_BE_SHIFT 31 ++#define OMAP44XX_REG_BE_MASK (1 << 31) ++#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT 30 ++#define OMAP44XX_REG_DUAL_CLK_MODE_MASK (1 << 30) ++#define OMAP44XX_REG_FAST_INIT_SHIFT 29 ++#define OMAP44XX_REG_FAST_INIT_MASK (1 << 29) ++#define OMAP44XX_REG_PHY_DLL_READY_SHIFT 2 ++#define OMAP44XX_REG_PHY_DLL_READY_MASK (1 << 2) ++ ++/* SDRAM_CONFIG */ ++#define OMAP44XX_REG_SDRAM_TYPE_SHIFT 29 ++#define OMAP44XX_REG_SDRAM_TYPE_MASK (0x7 << 29) ++#define OMAP44XX_REG_IBANK_POS_SHIFT 27 ++#define OMAP44XX_REG_IBANK_POS_MASK (0x3 << 27) ++#define OMAP44XX_REG_DDR_TERM_SHIFT 24 ++#define OMAP44XX_REG_DDR_TERM_MASK (0x7 << 24) ++#define OMAP44XX_REG_DDR2_DDQS_SHIFT 23 ++#define OMAP44XX_REG_DDR2_DDQS_MASK (1 << 23) ++#define OMAP44XX_REG_DYN_ODT_SHIFT 21 ++#define OMAP44XX_REG_DYN_ODT_MASK (0x3 << 21) ++#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT 20 ++#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK (1 << 20) ++#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT 18 ++#define OMAP44XX_REG_SDRAM_DRIVE_MASK (0x3 << 18) ++#define OMAP44XX_REG_CWL_SHIFT 16 ++#define OMAP44XX_REG_CWL_MASK (0x3 << 16) ++#define OMAP44XX_REG_NARROW_MODE_SHIFT 14 ++#define OMAP44XX_REG_NARROW_MODE_MASK (0x3 << 14) ++#define OMAP44XX_REG_CL_SHIFT 10 ++#define OMAP44XX_REG_CL_MASK (0xf << 10) ++#define OMAP44XX_REG_ROWSIZE_SHIFT 7 ++#define OMAP44XX_REG_ROWSIZE_MASK (0x7 << 7) ++#define OMAP44XX_REG_IBANK_SHIFT 4 ++#define OMAP44XX_REG_IBANK_MASK (0x7 << 4) ++#define OMAP44XX_REG_EBANK_SHIFT 3 ++#define OMAP44XX_REG_EBANK_MASK (1 << 3) ++#define OMAP44XX_REG_PAGESIZE_SHIFT 0 ++#define OMAP44XX_REG_PAGESIZE_MASK (0x7 << 0) ++ ++/* SDRAM_CONFIG_2 */ ++#define OMAP44XX_REG_CS1NVMEN_SHIFT 30 ++#define OMAP44XX_REG_CS1NVMEN_MASK (1 << 30) ++#define OMAP44XX_REG_EBANK_POS_SHIFT 27 ++#define OMAP44XX_REG_EBANK_POS_MASK (1 << 27) ++#define OMAP44XX_REG_RDBNUM_SHIFT 4 ++#define OMAP44XX_REG_RDBNUM_MASK (0x3 << 4) ++#define OMAP44XX_REG_RDBSIZE_SHIFT 0 ++#define OMAP44XX_REG_RDBSIZE_MASK (0x7 << 0) ++ ++/* SDRAM_REF_CTRL */ ++#define OMAP44XX_REG_INITREF_DIS_SHIFT 31 ++#define OMAP44XX_REG_INITREF_DIS_MASK (1 << 31) ++#define OMAP44XX_REG_SRT_SHIFT 29 ++#define OMAP44XX_REG_SRT_MASK (1 << 29) ++#define OMAP44XX_REG_ASR_SHIFT 28 ++#define OMAP44XX_REG_ASR_MASK (1 << 28) ++#define OMAP44XX_REG_PASR_SHIFT 24 ++#define OMAP44XX_REG_PASR_MASK (0x7 << 24) ++#define OMAP44XX_REG_REFRESH_RATE_SHIFT 0 ++#define OMAP44XX_REG_REFRESH_RATE_MASK (0xffff << 0) ++ ++/* SDRAM_REF_CTRL_SHDW */ ++#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT 0 ++#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) ++ ++/* SDRAM_TIM_1 */ ++#define OMAP44XX_REG_T_RP_SHIFT 25 ++#define OMAP44XX_REG_T_RP_MASK (0xf << 25) ++#define OMAP44XX_REG_T_RCD_SHIFT 21 ++#define OMAP44XX_REG_T_RCD_MASK (0xf << 21) ++#define OMAP44XX_REG_T_WR_SHIFT 17 ++#define OMAP44XX_REG_T_WR_MASK (0xf << 17) ++#define OMAP44XX_REG_T_RAS_SHIFT 12 ++#define OMAP44XX_REG_T_RAS_MASK (0x1f << 12) ++#define OMAP44XX_REG_T_RC_SHIFT 6 ++#define OMAP44XX_REG_T_RC_MASK (0x3f << 6) ++#define OMAP44XX_REG_T_RRD_SHIFT 3 ++#define OMAP44XX_REG_T_RRD_MASK (0x7 << 3) ++#define OMAP44XX_REG_T_WTR_SHIFT 0 ++#define OMAP44XX_REG_T_WTR_MASK (0x7 << 0) ++ ++/* SDRAM_TIM_1_SHDW */ ++#define OMAP44XX_REG_T_RP_SHDW_SHIFT 25 ++#define OMAP44XX_REG_T_RP_SHDW_MASK (0xf << 25) ++#define OMAP44XX_REG_T_RCD_SHDW_SHIFT 21 ++#define OMAP44XX_REG_T_RCD_SHDW_MASK (0xf << 21) ++#define OMAP44XX_REG_T_WR_SHDW_SHIFT 17 ++#define OMAP44XX_REG_T_WR_SHDW_MASK (0xf << 17) ++#define OMAP44XX_REG_T_RAS_SHDW_SHIFT 12 ++#define OMAP44XX_REG_T_RAS_SHDW_MASK (0x1f << 12) ++#define OMAP44XX_REG_T_RC_SHDW_SHIFT 6 ++#define OMAP44XX_REG_T_RC_SHDW_MASK (0x3f << 6) ++#define OMAP44XX_REG_T_RRD_SHDW_SHIFT 3 ++#define OMAP44XX_REG_T_RRD_SHDW_MASK (0x7 << 3) ++#define OMAP44XX_REG_T_WTR_SHDW_SHIFT 0 ++#define OMAP44XX_REG_T_WTR_SHDW_MASK (0x7 << 0) ++ ++/* SDRAM_TIM_2 */ ++#define OMAP44XX_REG_T_XP_SHIFT 28 ++#define OMAP44XX_REG_T_XP_MASK (0x7 << 28) ++#define OMAP44XX_REG_T_ODT_SHIFT 25 ++#define OMAP44XX_REG_T_ODT_MASK (0x7 << 25) ++#define OMAP44XX_REG_T_XSNR_SHIFT 16 ++#define OMAP44XX_REG_T_XSNR_MASK (0x1ff << 16) ++#define OMAP44XX_REG_T_XSRD_SHIFT 6 ++#define OMAP44XX_REG_T_XSRD_MASK (0x3ff << 6) ++#define OMAP44XX_REG_T_RTP_SHIFT 3 ++#define OMAP44XX_REG_T_RTP_MASK (0x7 << 3) ++#define OMAP44XX_REG_T_CKE_SHIFT 0 ++#define OMAP44XX_REG_T_CKE_MASK (0x7 << 0) ++ ++/* SDRAM_TIM_2_SHDW */ ++#define OMAP44XX_REG_T_XP_SHDW_SHIFT 28 ++#define OMAP44XX_REG_T_XP_SHDW_MASK (0x7 << 28) ++#define OMAP44XX_REG_T_ODT_SHDW_SHIFT 25 ++#define OMAP44XX_REG_T_ODT_SHDW_MASK (0x7 << 25) ++#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT 16 ++#define OMAP44XX_REG_T_XSNR_SHDW_MASK (0x1ff << 16) ++#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT 6 ++#define OMAP44XX_REG_T_XSRD_SHDW_MASK (0x3ff << 6) ++#define OMAP44XX_REG_T_RTP_SHDW_SHIFT 3 ++#define OMAP44XX_REG_T_RTP_SHDW_MASK (0x7 << 3) ++#define OMAP44XX_REG_T_CKE_SHDW_SHIFT 0 ++#define OMAP44XX_REG_T_CKE_SHDW_MASK (0x7 << 0) ++ ++/* SDRAM_TIM_3 */ ++#define OMAP44XX_REG_T_CKESR_SHIFT 21 ++#define OMAP44XX_REG_T_CKESR_MASK (0x7 << 21) ++#define OMAP44XX_REG_ZQ_ZQCS_SHIFT 15 ++#define OMAP44XX_REG_ZQ_ZQCS_MASK (0x3f << 15) ++#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT 13 ++#define OMAP44XX_REG_T_TDQSCKMAX_MASK (0x3 << 13) ++#define OMAP44XX_REG_T_RFC_SHIFT 4 ++#define OMAP44XX_REG_T_RFC_MASK (0x1ff << 4) ++#define OMAP44XX_REG_T_RAS_MAX_SHIFT 0 ++#define OMAP44XX_REG_T_RAS_MAX_MASK (0xf << 0) ++ ++/* SDRAM_TIM_3_SHDW */ ++#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT 21 ++#define OMAP44XX_REG_T_CKESR_SHDW_MASK (0x7 << 21) ++#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT 15 ++#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) ++#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT 13 ++#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) ++#define OMAP44XX_REG_T_RFC_SHDW_SHIFT 4 ++#define OMAP44XX_REG_T_RFC_SHDW_MASK (0x1ff << 4) ++#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT 0 ++#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) ++ ++/* LPDDR2_NVM_TIM */ ++#define OMAP44XX_REG_NVM_T_XP_SHIFT 28 ++#define OMAP44XX_REG_NVM_T_XP_MASK (0x7 << 28) ++#define OMAP44XX_REG_NVM_T_WTR_SHIFT 24 ++#define OMAP44XX_REG_NVM_T_WTR_MASK (0x7 << 24) ++#define OMAP44XX_REG_NVM_T_RP_SHIFT 20 ++#define OMAP44XX_REG_NVM_T_RP_MASK (0xf << 20) ++#define OMAP44XX_REG_NVM_T_WRA_SHIFT 16 ++#define OMAP44XX_REG_NVM_T_WRA_MASK (0xf << 16) ++#define OMAP44XX_REG_NVM_T_RRD_SHIFT 8 ++#define OMAP44XX_REG_NVM_T_RRD_MASK (0xff << 8) ++#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT 0 ++#define OMAP44XX_REG_NVM_T_RCDMIN_MASK (0xff << 0) ++ ++/* LPDDR2_NVM_TIM_SHDW */ ++#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT 28 ++#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) ++#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT 24 ++#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) ++#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT 20 ++#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK (0xf << 20) ++#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT 16 ++#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) ++#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT 8 ++#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) ++#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 ++#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) ++ ++/* PWR_MGMT_CTRL */ ++#define OMAP44XX_REG_IDLEMODE_SHIFT 30 ++#define OMAP44XX_REG_IDLEMODE_MASK (0x3 << 30) ++#define OMAP44XX_REG_PD_TIM_SHIFT 12 ++#define OMAP44XX_REG_PD_TIM_MASK (0xf << 12) ++#define OMAP44XX_REG_DPD_EN_SHIFT 11 ++#define OMAP44XX_REG_DPD_EN_MASK (1 << 11) ++#define OMAP44XX_REG_LP_MODE_SHIFT 8 ++#define OMAP44XX_REG_LP_MODE_MASK (0x7 << 8) ++#define OMAP44XX_REG_SR_TIM_SHIFT 4 ++#define OMAP44XX_REG_SR_TIM_MASK (0xf << 4) ++#define OMAP44XX_REG_CS_TIM_SHIFT 0 ++#define OMAP44XX_REG_CS_TIM_MASK (0xf << 0) ++ ++/* PWR_MGMT_CTRL_SHDW */ ++#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT 8 ++#define OMAP44XX_REG_PD_TIM_SHDW_MASK (0xf << 8) ++#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT 4 ++#define OMAP44XX_REG_SR_TIM_SHDW_MASK (0xf << 4) ++#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT 0 ++#define OMAP44XX_REG_CS_TIM_SHDW_MASK (0xf << 0) ++ ++/* LPDDR2_MODE_REG_DATA */ ++#define OMAP44XX_REG_VALUE_0_SHIFT 0 ++#define OMAP44XX_REG_VALUE_0_MASK (0x7f << 0) ++ ++/* LPDDR2_MODE_REG_CFG */ ++#define OMAP44XX_REG_CS_SHIFT 31 ++#define OMAP44XX_REG_CS_MASK (1 << 31) ++#define OMAP44XX_REG_REFRESH_EN_SHIFT 30 ++#define OMAP44XX_REG_REFRESH_EN_MASK (1 << 30) ++#define OMAP44XX_REG_ADDRESS_SHIFT 0 ++#define OMAP44XX_REG_ADDRESS_MASK (0xff << 0) ++ ++/* OCP_CONFIG */ ++#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT 24 ++#define OMAP44XX_REG_SYS_THRESH_MAX_MASK (0xf << 24) ++#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT 16 ++#define OMAP44XX_REG_LL_THRESH_MAX_MASK (0xf << 16) ++#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT 0 ++#define OMAP44XX_REG_PR_OLD_COUNT_MASK (0xff << 0) ++ ++/* OCP_CFG_VAL_1 */ ++#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT 30 ++#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) ++#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT 28 ++#define OMAP44XX_REG_LL_BUS_WIDTH_MASK (0x3 << 28) ++#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT 8 ++#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK (0xff << 8) ++#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT 0 ++#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) ++ ++/* OCP_CFG_VAL_2 */ ++#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT 16 ++#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) ++#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT 8 ++#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) ++#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT 0 ++#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) ++ ++/* IODFT_TLGC */ ++#define OMAP44XX_REG_TLEC_SHIFT 16 ++#define OMAP44XX_REG_TLEC_MASK (0xffff << 16) ++#define OMAP44XX_REG_MT_SHIFT 14 ++#define OMAP44XX_REG_MT_MASK (1 << 14) ++#define OMAP44XX_REG_ACT_CAP_EN_SHIFT 13 ++#define OMAP44XX_REG_ACT_CAP_EN_MASK (1 << 13) ++#define OMAP44XX_REG_OPG_LD_SHIFT 12 ++#define OMAP44XX_REG_OPG_LD_MASK (1 << 12) ++#define OMAP44XX_REG_RESET_PHY_SHIFT 10 ++#define OMAP44XX_REG_RESET_PHY_MASK (1 << 10) ++#define OMAP44XX_REG_MMS_SHIFT 8 ++#define OMAP44XX_REG_MMS_MASK (1 << 8) ++#define OMAP44XX_REG_MC_SHIFT 4 ++#define OMAP44XX_REG_MC_MASK (0x3 << 4) ++#define OMAP44XX_REG_PC_SHIFT 1 ++#define OMAP44XX_REG_PC_MASK (0x7 << 1) ++#define OMAP44XX_REG_TM_SHIFT 0 ++#define OMAP44XX_REG_TM_MASK (1 << 0) ++ ++/* IODFT_CTRL_MISR_RSLT */ ++#define OMAP44XX_REG_DQM_TLMR_SHIFT 16 ++#define OMAP44XX_REG_DQM_TLMR_MASK (0x3ff << 16) ++#define OMAP44XX_REG_CTL_TLMR_SHIFT 0 ++#define OMAP44XX_REG_CTL_TLMR_MASK (0x7ff << 0) ++ ++/* IODFT_ADDR_MISR_RSLT */ ++#define OMAP44XX_REG_ADDR_TLMR_SHIFT 0 ++#define OMAP44XX_REG_ADDR_TLMR_MASK (0x1fffff << 0) ++ ++/* IODFT_DATA_MISR_RSLT_1 */ ++#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT 0 ++#define OMAP44XX_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) ++ ++/* IODFT_DATA_MISR_RSLT_2 */ ++#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT 0 ++#define OMAP44XX_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) ++ ++/* IODFT_DATA_MISR_RSLT_3 */ ++#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT 0 ++#define OMAP44XX_REG_DATA_TLMR_66_64_MASK (0x7 << 0) ++ ++/* PERF_CNT_1 */ ++#define OMAP44XX_REG_COUNTER1_SHIFT 0 ++#define OMAP44XX_REG_COUNTER1_MASK (0xffffffff << 0) ++ ++/* PERF_CNT_2 */ ++#define OMAP44XX_REG_COUNTER2_SHIFT 0 ++#define OMAP44XX_REG_COUNTER2_MASK (0xffffffff << 0) ++ ++/* PERF_CNT_CFG */ ++#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT 31 ++#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK (1 << 31) ++#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT 30 ++#define OMAP44XX_REG_CNTR2_REGION_EN_MASK (1 << 30) ++#define OMAP44XX_REG_CNTR2_CFG_SHIFT 16 ++#define OMAP44XX_REG_CNTR2_CFG_MASK (0xf << 16) ++#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT 15 ++#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK (1 << 15) ++#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT 14 ++#define OMAP44XX_REG_CNTR1_REGION_EN_MASK (1 << 14) ++#define OMAP44XX_REG_CNTR1_CFG_SHIFT 0 ++#define OMAP44XX_REG_CNTR1_CFG_MASK (0xf << 0) ++ ++/* PERF_CNT_SEL */ ++#define OMAP44XX_REG_MCONNID2_SHIFT 24 ++#define OMAP44XX_REG_MCONNID2_MASK (0xff << 24) ++#define OMAP44XX_REG_REGION_SEL2_SHIFT 16 ++#define OMAP44XX_REG_REGION_SEL2_MASK (0x3 << 16) ++#define OMAP44XX_REG_MCONNID1_SHIFT 8 ++#define OMAP44XX_REG_MCONNID1_MASK (0xff << 8) ++#define OMAP44XX_REG_REGION_SEL1_SHIFT 0 ++#define OMAP44XX_REG_REGION_SEL1_MASK (0x3 << 0) ++ ++/* PERF_CNT_TIM */ ++#define OMAP44XX_REG_TOTAL_TIME_SHIFT 0 ++#define OMAP44XX_REG_TOTAL_TIME_MASK (0xffffffff << 0) ++ ++/* READ_IDLE_CTRL */ ++#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT 16 ++#define OMAP44XX_REG_READ_IDLE_LEN_MASK (0xf << 16) ++#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT 0 ++#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) ++ ++/* READ_IDLE_CTRL_SHDW */ ++#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT 16 ++#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) ++#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 ++#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) ++ ++/* IRQ_EOI */ ++#define OMAP44XX_REG_EOI_SHIFT 0 ++#define OMAP44XX_REG_EOI_MASK (1 << 0) ++ ++/* IRQSTATUS_RAW_SYS */ ++#define OMAP44XX_REG_DNV_SYS_SHIFT 2 ++#define OMAP44XX_REG_DNV_SYS_MASK (1 << 2) ++#define OMAP44XX_REG_TA_SYS_SHIFT 1 ++#define OMAP44XX_REG_TA_SYS_MASK (1 << 1) ++#define OMAP44XX_REG_ERR_SYS_SHIFT 0 ++#define OMAP44XX_REG_ERR_SYS_MASK (1 << 0) ++ ++/* IRQSTATUS_RAW_LL */ ++#define OMAP44XX_REG_DNV_LL_SHIFT 2 ++#define OMAP44XX_REG_DNV_LL_MASK (1 << 2) ++#define OMAP44XX_REG_TA_LL_SHIFT 1 ++#define OMAP44XX_REG_TA_LL_MASK (1 << 1) ++#define OMAP44XX_REG_ERR_LL_SHIFT 0 ++#define OMAP44XX_REG_ERR_LL_MASK (1 << 0) ++ ++/* IRQSTATUS_SYS */ ++ ++/* IRQSTATUS_LL */ ++ ++/* IRQENABLE_SET_SYS */ ++#define OMAP44XX_REG_EN_DNV_SYS_SHIFT 2 ++#define OMAP44XX_REG_EN_DNV_SYS_MASK (1 << 2) ++#define OMAP44XX_REG_EN_TA_SYS_SHIFT 1 ++#define OMAP44XX_REG_EN_TA_SYS_MASK (1 << 1) ++#define OMAP44XX_REG_EN_ERR_SYS_SHIFT 0 ++#define OMAP44XX_REG_EN_ERR_SYS_MASK (1 << 0) ++ ++/* IRQENABLE_SET_LL */ ++#define OMAP44XX_REG_EN_DNV_LL_SHIFT 2 ++#define OMAP44XX_REG_EN_DNV_LL_MASK (1 << 2) ++#define OMAP44XX_REG_EN_TA_LL_SHIFT 1 ++#define OMAP44XX_REG_EN_TA_LL_MASK (1 << 1) ++#define OMAP44XX_REG_EN_ERR_LL_SHIFT 0 ++#define OMAP44XX_REG_EN_ERR_LL_MASK (1 << 0) ++ ++/* IRQENABLE_CLR_SYS */ ++ ++/* IRQENABLE_CLR_LL */ ++ ++/* ZQ_CONFIG */ ++#define OMAP44XX_REG_ZQ_CS1EN_SHIFT 31 ++#define OMAP44XX_REG_ZQ_CS1EN_MASK (1 << 31) ++#define OMAP44XX_REG_ZQ_CS0EN_SHIFT 30 ++#define OMAP44XX_REG_ZQ_CS0EN_MASK (1 << 30) ++#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT 29 ++#define OMAP44XX_REG_ZQ_DUALCALEN_MASK (1 << 29) ++#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT 28 ++#define OMAP44XX_REG_ZQ_SFEXITEN_MASK (1 << 28) ++#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT 18 ++#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) ++#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT 16 ++#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) ++#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT 0 ++#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) ++ ++/* TEMP_ALERT_CONFIG */ ++#define OMAP44XX_REG_TA_CS1EN_SHIFT 31 ++#define OMAP44XX_REG_TA_CS1EN_MASK (1 << 31) ++#define OMAP44XX_REG_TA_CS0EN_SHIFT 30 ++#define OMAP44XX_REG_TA_CS0EN_MASK (1 << 30) ++#define OMAP44XX_REG_TA_SFEXITEN_SHIFT 28 ++#define OMAP44XX_REG_TA_SFEXITEN_MASK (1 << 28) ++#define OMAP44XX_REG_TA_DEVWDT_SHIFT 26 ++#define OMAP44XX_REG_TA_DEVWDT_MASK (0x3 << 26) ++#define OMAP44XX_REG_TA_DEVCNT_SHIFT 24 ++#define OMAP44XX_REG_TA_DEVCNT_MASK (0x3 << 24) ++#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT 0 ++#define OMAP44XX_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) ++ ++/* OCP_ERR_LOG */ ++#define OMAP44XX_REG_MADDRSPACE_SHIFT 14 ++#define OMAP44XX_REG_MADDRSPACE_MASK (0x3 << 14) ++#define OMAP44XX_REG_MBURSTSEQ_SHIFT 11 ++#define OMAP44XX_REG_MBURSTSEQ_MASK (0x7 << 11) ++#define OMAP44XX_REG_MCMD_SHIFT 8 ++#define OMAP44XX_REG_MCMD_MASK (0x7 << 8) ++#define OMAP44XX_REG_MCONNID_SHIFT 0 ++#define OMAP44XX_REG_MCONNID_MASK (0xff << 0) ++ ++/* DDR_PHY_CTRL_1 */ ++#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT 4 ++#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) ++#define OMAP44XX_REG_READ_LATENCY_SHIFT 0 ++#define OMAP44XX_REG_READ_LATENCY_MASK (0xf << 0) ++#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 ++#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) ++#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 ++#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) ++ ++/* DDR_PHY_CTRL_1_SHDW */ ++#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 ++#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) ++#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT 0 ++#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK (0xf << 0) ++#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 ++#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) ++#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 ++#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) ++ ++/* DDR_PHY_CTRL_2 */ ++#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT 0 ++#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) ++ ++/* DMM */ ++#define OMAP44XX_DMM_BASE 0x4E000000 ++#define OMAP44XX_DMM_LISA_MAP_BASE (0x4E000000 + 0x40) ++ ++/* DMM_LISA_MAP */ ++#define OMAP44XX_SYS_ADDR_SHIFT 24 ++#define OMAP44XX_SYS_ADDR_MASK (0xff << 24) ++#define OMAP44XX_SYS_SIZE_SHIFT 20 ++#define OMAP44XX_SYS_SIZE_MASK (0x7 << 20) ++#define OMAP44XX_SDRC_INTL_SHIFT 18 ++#define OMAP44XX_SDRC_INTL_MASK (0x3 << 18) ++#define OMAP44XX_SDRC_ADDRSPC_SHIFT 16 ++#define OMAP44XX_SDRC_ADDRSPC_MASK (0x3 << 16) ++#define OMAP44XX_SDRC_MAP_SHIFT 8 ++#define OMAP44XX_SDRC_MAP_MASK (0x3 << 8) ++#define OMAP44XX_SDRC_ADDR_SHIFT 0 ++#define OMAP44XX_SDRC_ADDR_MASK (0xff << 0) ++ ++/* DMM_LISA_MAP fields */ ++#define DMM_SDRC_MAP_UNMAPPED 0 ++#define DMM_SDRC_MAP_EMIF1_ONLY 1 ++#define DMM_SDRC_MAP_EMIF2_ONLY 2 ++#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 ++ ++#define DMM_SDRC_INTL_NONE 0 ++#define DMM_SDRC_INTL_128B 1 ++#define DMM_SDRC_INTL_256B 2 ++#define DMM_SDRC_INTL_512 3 ++ ++#define DMM_SDRC_ADDR_SPC_SDRAM 0 ++#define DMM_SDRC_ADDR_SPC_NVM 1 ++#define DMM_SDRC_ADDR_SPC_INVALID 2 ++ ++#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ ++ (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\ ++ (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\ ++ (DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\ ++ (CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT)) ++ ++#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ ++ (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ ++ (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ ++ (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) ++ ++#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ ++ (DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ ++ (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ ++ (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) ++ ++/* Trap for invalid TILER PAT entries */ ++#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ ++ (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ ++ (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ ++ (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ ++ (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ ++ (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) ++ ++ ++/* Reg mapping structure */ ++struct __attribute__ ((__packed__)) emif_reg_struct{ ++ u32 emif_mod_id_rev; ++ u32 emif_status; ++ u32 emif_sdram_config; ++ u32 emif_lpddr2_nvm_config; ++ u32 emif_sdram_ref_ctrl; ++ u32 emif_sdram_ref_ctrl_shdw; ++ u32 emif_sdram_tim_1; ++ u32 emif_sdram_tim_1_shdw; ++ u32 emif_sdram_tim_2; ++ u32 emif_sdram_tim_2_shdw; ++ u32 emif_sdram_tim_3; ++ u32 emif_sdram_tim_3_shdw; ++ u32 emif_lpddr2_nvm_tim; ++ u32 emif_lpddr2_nvm_tim_shdw; ++ u32 emif_pwr_mgmt_ctrl; ++ u32 emif_pwr_mgmt_ctrl_shdw; ++ u32 emif_lpddr2_mode_reg_data; ++ u32 padding1[1]; ++ u32 emif_lpddr2_mode_reg_data_es2; ++ u32 padding11[1]; ++ u32 emif_lpddr2_mode_reg_cfg; ++ u32 emif_l3_config; ++ u32 emif_l3_cfg_val_1; ++ u32 emif_l3_cfg_val_2; ++ u32 emif_iodft_tlgc; ++ u32 padding2[7]; ++ u32 emif_perf_cnt_1; ++ u32 emif_perf_cnt_2; ++ u32 emif_perf_cnt_cfg; ++ u32 emif_perf_cnt_sel; ++ u32 emif_perf_cnt_tim; ++ u32 padding3; ++ u32 emif_read_idlectrl; ++ u32 emif_read_idlectrl_shdw; ++ u32 padding4; ++ u32 emif_irqstatus_raw_sys; ++ u32 emif_irqstatus_raw_ll; ++ u32 emif_irqstatus_sys; ++ u32 emif_irqstatus_ll; ++ u32 emif_irqenable_set_sys; ++ u32 emif_irqenable_set_ll; ++ u32 emif_irqenable_clr_sys; ++ u32 emif_irqenable_clr_ll; ++ u32 padding5; ++ u32 emif_zq_config; ++ u32 emif_temp_alert_config; ++ u32 emif_l3_err_log; ++ u32 padding6[4]; ++ u32 emif_ddr_phy_ctrl_1; ++ u32 emif_ddr_phy_ctrl_1_shdw; ++ u32 emif_ddr_phy_ctrl_2; ++}; ++ ++struct __attribute__ ((__packed__)) dmm_lisa_map_regs { ++ u32 dmm_lisa_map_0; ++ u32 dmm_lisa_map_1; ++ u32 dmm_lisa_map_2; ++ u32 dmm_lisa_map_3; ++}; ++ ++#define CS0 0 ++#define CS1 1 ++/* Read Latency used by the device at reset */ ++#define RL_BOOT 3 ++/* Read Latency for the highest frequency you want to use */ ++#define RL_FINAL 6 ++/* EMIF_PWR_MGMT_CTRL register */ ++/* Low power modes */ ++#define LP_MODE_DISABLE 0 ++#define LP_MODE_CLOCK_STOP 1 ++#define LP_MODE_SELF_REFRESH 2 ++#define LP_MODE_PWR_DN 3 ++ ++/* REG_DPD_EN */ ++#define DPD_DISABLE 0 ++#define DPD_ENABLE 1 ++ ++/* Maximum delay before Low Power Modes */ ++#define REG_CS_TIM 0xF ++#define REG_SR_TIM 0xF ++#define REG_PD_TIM 0xF ++ ++/* EMIF_PWR_MGMT_CTRL register */ ++#define EMIF_PWR_MGMT_CTRL (\ ++ ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\ ++ ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\ ++ ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ ++ ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ ++ ((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\ ++ & OMAP44XX_REG_LP_MODE_MASK) |\ ++ ((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\ ++ & OMAP44XX_REG_DPD_EN_MASK))\ ++ ++#define EMIF_PWR_MGMT_CTRL_SHDW (\ ++ ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\ ++ & OMAP44XX_REG_CS_TIM_SHDW_MASK) |\ ++ ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\ ++ & OMAP44XX_REG_SR_TIM_SHDW_MASK) |\ ++ ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ ++ & OMAP44XX_REG_PD_TIM_SHDW_MASK) |\ ++ ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ ++ & OMAP44XX_REG_PD_TIM_SHDW_MASK)) ++ ++/* EMIF_L3_CONFIG register value for ES1*/ ++#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00 0x0A0000FF ++ ++/* ++* MR1 value: ++* Burst length : 8 ++* Burst type : sequential ++* Wrap : enabled ++* nWR : 3(default). EMIF does not do pre-charge. ++* : So nWR is don't care ++*/ ++#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 ++ ++/* MR2 */ ++#define MR2_RL3_WL1 1 ++#define MR2_RL4_WL2 2 ++#define MR2_RL5_WL2 3 ++#define MR2_RL6_WL3 4 ++ ++/* MR10: ZQ calibration codes */ ++#define MR10_ZQ_ZQCS 0x56 ++#define MR10_ZQ_ZQCL 0xAB ++#define MR10_ZQ_ZQINIT 0xFF ++#define MR10_ZQ_ZQRESET 0xC3 ++ ++/* MR16 value: refresh full array(no partial array self refresh) */ ++#define MR16_REF_FULL_ARRAY 0 ++ ++/* LPDDR2 IO reg values */ ++#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C ++#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E ++ ++/* CONTROL_EFUSE_2 */ ++#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 ++ ++/* Mode register numbers */ ++#define LPDDR2_MR0 0 ++#define LPDDR2_MR1 1 ++#define LPDDR2_MR2 2 ++#define LPDDR2_MR3 3 ++#define LPDDR2_MR4 4 ++#define LPDDR2_MR5 5 ++#define LPDDR2_MR6 6 ++#define LPDDR2_MR7 7 ++#define LPDDR2_MR8 8 ++#define LPDDR2_MR9 9 ++#define LPDDR2_MR10 10 ++#define LPDDR2_MR11 11 ++#define LPDDR2_MR16 16 ++#define LPDDR2_MR17 17 ++#define LPDDR2_MR18 18 ++ ++/* MR0 */ ++#define LPDDR2_MR0_DAI_SHIFT 0 ++#define LPDDR2_MR0_DAI_MASK 1 ++#define LPDDR2_MR0_DI_SHIFT 1 ++#define LPDDR2_MR0_DI_MASK (1 << 1) ++#define LPDDR2_MR0_DNVI_SHIFT 2 ++#define LPDDR2_MR0_DNVI_MASK (1 << 2) ++ ++/* ++ * Structure containing shadow of important registers in EMIF ++ * The calculation function fills in this structure to be later used for ++ * initialization and DVFS ++ */ ++struct emif_regs { ++ u32 freq; ++ u32 sdram_config_init; ++ u32 sdram_config; ++ u32 ref_ctrl; ++ u32 sdram_tim1; ++ u32 sdram_tim2; ++ u32 sdram_tim3; ++ u32 read_idle_ctrl; ++ u32 zq_config; ++ u32 temp_alert_config; ++ u32 emif_ddr_phy_ctlr_1_init; ++ u32 emif_ddr_phy_ctlr_1; ++}; ++ ++void emif_get_reg_dump(const struct emif_regs **emif1_regs, ++ const struct emif_regs **emif2_regs); ++void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); ++ ++#endif +diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h +index 740ca9d..a1c4883 100644 +--- a/arch/arm/include/asm/arch-omap4/omap4.h ++++ b/arch/arm/include/asm/arch-omap4/omap4.h +@@ -51,6 +51,17 @@ + #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) + #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) + ++/* LPDDR2 IO regs */ ++#define CONTROL_LPDDR2IO1_0 (CONTROL_PADCONF_CORE + 0x0638) ++#define CONTROL_LPDDR2IO1_1 (CONTROL_PADCONF_CORE + 0x063C) ++#define CONTROL_LPDDR2IO1_2 (CONTROL_PADCONF_CORE + 0x0640) ++#define CONTROL_LPDDR2IO1_3 (CONTROL_PADCONF_CORE + 0x0644) ++#define CONTROL_LPDDR2IO2_0 (CONTROL_PADCONF_CORE + 0x0648) ++#define CONTROL_LPDDR2IO2_1 (CONTROL_PADCONF_CORE + 0x064C) ++#define CONTROL_LPDDR2IO2_2 (CONTROL_PADCONF_CORE + 0x0650) ++#define CONTROL_LPDDR2IO2_3 (CONTROL_PADCONF_CORE + 0x0654) ++#define CONTROL_EFUSE_2 (CONTROL_PADCONF_CORE + 0x0704) ++ + /* CONTROL_ID_CODE */ + #define CONTROL_ID_CODE (CTRL_BASE + 0x204) + +diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h +index fd21afd..4beff42 100644 +--- a/arch/arm/include/asm/arch-omap4/sys_proto.h ++++ b/arch/arm/include/asm/arch-omap4/sys_proto.h +@@ -44,6 +44,7 @@ void bypass_dpll(u32 base); + void freq_update_core(void); + u32 get_syc_clk_freq(void); + u32 omap4_ddr_clk(void); ++void sdram_init(void); + u32 omap4_revision(void); + + static inline u32 running_from_sdram(void) +diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h +index 5b20841..07d45a0 100644 +--- a/include/configs/omap4_sdp4430.h ++++ b/include/configs/omap4_sdp4430.h +@@ -245,11 +245,6 @@ + /* Defines for Clock init */ + #define CONFIG_SYS_OMAP4_ABE_SYSCK + +-/* Defines for SDRAM init */ +-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 +-#define CONFIG_SYS_EMIF_UPDATE_TIMINGS 1 +-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 +- + /* Defines for SPL */ + #define CONFIG_SPL + #define CONFIG_SYS_SPL_TEXT_BASE 0x40304360 +diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile +index 40e3e79..1f25f77 100644 +--- a/spl/board/ti/sdp4430/Makefile ++++ b/spl/board/ti/sdp4430/Makefile +@@ -115,12 +115,20 @@ $(obj)board.c:$(obj)omap4_mux_data.h + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@ + ++$(obj)emif.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/emif.c $@ ++ ++$(obj)sdram_elpida.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/sdram_elpida.c $@ ++ + $(obj)clocks.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@ + + SOBJS += lowlevel_init.o +-COBJS += board.o clocks.o ++COBJS += board.o clocks.o emif.o sdram_elpida.o + + # rules + LDPPFLAGS += -include $(TOPDIR)/include/config.h +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0017-omap4-calculate-EMIF-register-values.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0017-omap4-calculate-EMIF-register-values.patch new file mode 100644 index 0000000000..9e450604b8 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0017-omap4-calculate-EMIF-register-values.patch @@ -0,0 +1,1728 @@ +From 7c2a9cc0c7311f4251b067f03912fa5996234ca2 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Fri, 25 Feb 2011 17:27:15 +0530 +Subject: [PATCH 17/22] omap4: calculate EMIF register values + +Calculate EMIF register values based on AC timing parameters +from the SDRAM datasheet and the DDR frequency rather than +using the hard-coded values. + +For a new board the user doen't have to go through the tedious +process of calculating the register values. Instead, just +provide the AC timings from the device data sheet as input +and the driver will automatically calculate the register values. + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap-common/Makefile | 1 + + arch/arm/cpu/armv7/omap-common/utils.c | 61 ++ + arch/arm/cpu/armv7/omap4/Makefile | 1 - + arch/arm/cpu/armv7/omap4/board.c | 9 +- + arch/arm/cpu/armv7/omap4/emif.c | 861 ++++++++++++++++++++++++++- + arch/arm/cpu/armv7/omap4/sdram_elpida.c | 152 +++++- + arch/arm/include/asm/arch-omap4/emif.h | 304 ++++++++++- + arch/arm/include/asm/arch-omap4/omap4.h | 18 +- + arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + + arch/arm/include/asm/omap_common.h | 21 + + include/configs/omap4_sdp4430.h | 5 + + spl/board/ti/sdp4430/Makefile | 6 +- + 12 files changed, 1424 insertions(+), 16 deletions(-) + create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c + +diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile +index dc01ee5..8f698f8 100644 +--- a/arch/arm/cpu/armv7/omap-common/Makefile ++++ b/arch/arm/cpu/armv7/omap-common/Makefile +@@ -28,6 +28,7 @@ LIB = $(obj)libomap-common.o + SOBJS := reset.o + + COBJS := timer.o ++COBJS += utils.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c +new file mode 100644 +index 0000000..7dce7f1 +--- /dev/null ++++ b/arch/arm/cpu/armv7/omap-common/utils.c +@@ -0,0 +1,61 @@ ++/* ++ * Utility functions for OMAP4 ++ * ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * ++ * Aneesh V ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++static void do_cancel_out(u32 *num, u32 *den, u32 factor) ++{ ++ while (1) { ++ if (((*num)/factor*factor == (*num)) && ++ ((*den)/factor*factor == (*den))) { ++ (*num) /= factor; ++ (*den) /= factor; ++ } else ++ break; ++ } ++} ++ ++/* ++ * Cancel out the denominator and numerator of a fraction ++ * to get smaller numerator and denominator. ++ */ ++void cancel_out(u32 *num, u32 *den, u32 den_limit) ++{ ++ do_cancel_out(num, den, 2); ++ do_cancel_out(num, den, 3); ++ do_cancel_out(num, den, 5); ++ do_cancel_out(num, den, 7); ++ do_cancel_out(num, den, 11); ++ do_cancel_out(num, den, 13); ++ do_cancel_out(num, den, 17); ++ while ((*den) > den_limit) { ++ *num /= 2; ++ /* ++ * Round up the denominator so that the final fraction ++ * (num/den) is always <= the desired value ++ */ ++ *den = (*den + 1) / 2; ++ } ++} +diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile +index d9714fe..0b525e1 100644 +--- a/arch/arm/cpu/armv7/omap4/Makefile ++++ b/arch/arm/cpu/armv7/omap4/Makefile +@@ -34,7 +34,6 @@ COBJS += clocks.o + COBJS += emif.o + COBJS += sdram_elpida.o + +- + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c +index 89b1213..925601d 100644 +--- a/arch/arm/cpu/armv7/omap4/board.c ++++ b/arch/arm/cpu/armv7/omap4/board.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + #include "omap4_mux_data.h" + + DECLARE_GLOBAL_DATA_PTR; +@@ -148,13 +149,13 @@ u32 sdram_size(void) + { + u32 section, i, total_size = 0, size, addr; + for (i = 0; i < 4; i++) { +- section = __raw_readl(DMM_LISA_MAP_BASE + i*4); +- addr = section & DMM_LISA_MAP_SYS_ADDR_MASK; ++ section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4); ++ addr = section & OMAP44XX_SYS_ADDR_MASK; + /* See if the address is valid */ + if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) && + (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) { +- size = ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >> +- DMM_LISA_MAP_SYS_SIZE_SHIFT); ++ size = ((section & OMAP44XX_SYS_SIZE_MASK) >> ++ OMAP44XX_SYS_SIZE_SHIFT); + size = 1 << size; + size *= SZ_16M; + total_size += size; +diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c +index ee77743..1bdb1d2 100644 +--- a/arch/arm/cpu/armv7/omap4/emif.c ++++ b/arch/arm/cpu/armv7/omap4/emif.c +@@ -31,6 +31,589 @@ + #include + #include + ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) ++ ++static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; ++static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; ++static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE; ++ ++/* ++ * Organization and refresh requirements for LPDDR2 devices of different ++ * types and densities. Derived from JESD209-2 section 2.4 ++ */ ++const struct lpddr2_addressing addressing_table[] = { ++ /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ ++ {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ ++ {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ ++ {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ ++ {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ ++ {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ ++ {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ ++ {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ ++ {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ ++ {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ ++ {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ ++}; ++ ++static const u32 lpddr2_density_2_size_in_mbytes[] = { ++ 8, /* 64Mb */ ++ 16, /* 128Mb */ ++ 32, /* 256Mb */ ++ 64, /* 512Mb */ ++ 128, /* 1Gb */ ++ 256, /* 2Gb */ ++ 512, /* 4Gb */ ++ 1024, /* 8Gb */ ++ 2048, /* 16Gb */ ++ 4096 /* 32Gb */ ++}; ++ ++#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS ++/* Base AC Timing values specified by JESD209-2 for 400MHz operation */ ++static const struct lpddr2_ac_timings timings_jedec_400_mhz = { ++ .max_freq = 400000000, ++ .RL = 6, ++ .tRPab = 21, ++ .tRCD = 18, ++ .tWR = 15, ++ .tRASmin = 42, ++ .tRRD = 10, ++ .tWTRx2 = 15, ++ .tXSR = 140, ++ .tXPx2 = 15, ++ .tRFCab = 130, ++ .tRTPx2 = 15, ++ .tCKE = 3, ++ .tCKESR = 15, ++ .tZQCS = 90, ++ .tZQCL = 360, ++ .tZQINIT = 1000, ++ .tDQSCKMAXx2 = 11, ++ .tRASmax = 70, ++ .tFAW = 50 ++}; ++ ++/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */ ++static const struct lpddr2_ac_timings timings_jedec_333_mhz = { ++ .max_freq = 333000000, ++ .RL = 5, ++ .tRPab = 21, ++ .tRCD = 18, ++ .tWR = 15, ++ .tRASmin = 42, ++ .tRRD = 10, ++ .tWTRx2 = 15, ++ .tXSR = 140, ++ .tXPx2 = 15, ++ .tRFCab = 130, ++ .tRTPx2 = 15, ++ .tCKE = 3, ++ .tCKESR = 15, ++ .tZQCS = 90, ++ .tZQCL = 360, ++ .tZQINIT = 1000, ++ .tDQSCKMAXx2 = 11, ++ .tRASmax = 70, ++ .tFAW = 50 ++}; ++ ++/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */ ++static const struct lpddr2_ac_timings timings_jedec_200_mhz = { ++ .max_freq = 200000000, ++ .RL = 3, ++ .tRPab = 21, ++ .tRCD = 18, ++ .tWR = 15, ++ .tRASmin = 42, ++ .tRRD = 10, ++ .tWTRx2 = 20, ++ .tXSR = 140, ++ .tXPx2 = 15, ++ .tRFCab = 130, ++ .tRTPx2 = 15, ++ .tCKE = 3, ++ .tCKESR = 15, ++ .tZQCS = 90, ++ .tZQCL = 360, ++ .tZQINIT = 1000, ++ .tDQSCKMAXx2 = 11, ++ .tRASmax = 70, ++ .tFAW = 50 ++}; ++ ++/* ++ * Min tCK values specified by JESD209-2 ++ * Min tCK specifies the minimum duration of some AC timing parameters in terms ++ * of the number of cycles. If the calculated number of cycles based on the ++ * absolute time value is less than the min tCK value, min tCK value should ++ * be used instead. This typically happens at low frequencies. ++ */ ++static const struct lpddr2_min_tck min_tck_jedec = { ++ .tRL = 3, ++ .tRP_AB = 3, ++ .tRCD = 3, ++ .tWR = 3, ++ .tRAS_MIN = 3, ++ .tRRD = 2, ++ .tWTR = 2, ++ .tXP = 2, ++ .tRTP = 2, ++ .tCKE = 3, ++ .tCKESR = 3, ++ .tFAW = 8 ++}; ++ ++static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = { ++ &timings_jedec_200_mhz, ++ &timings_jedec_333_mhz, ++ &timings_jedec_400_mhz ++}; ++ ++static const struct lpddr2_device_timings jedec_default_timings = { ++ .ac_timings = jedec_ac_timings, ++ .min_tck = &min_tck_jedec ++}; ++#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ ++ ++/* ++ * Calculate the period of DDR clock from frequency value and set the ++ * denominator and numerator in global variables for easy access later ++ */ ++static void set_ddr_clk_period(u32 freq) ++{ ++ /* ++ * period = 1/freq ++ * period_in_ns = 10^9/freq ++ */ ++ *T_num = 1000000000; ++ *T_den = freq; ++ cancel_out(T_num, T_den, 200); ++ ++} ++ ++/* ++ * Convert time in nano seconds to number of cycles of DDR clock ++ */ ++static inline u32 ns_2_cycles(u32 ns) ++{ ++ return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); ++} ++ ++/* ++ * ns_2_cycles with the difference that the time passed is 2 times the actual ++ * value(to avoid fractions). The cycles returned is for the original value of ++ * the timing parameter ++ */ ++static inline u32 ns_x2_2_cycles(u32 ns) ++{ ++ return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); ++} ++ ++/* ++ * Find addressing table index based on the device's type(S2 or S4) and ++ * density ++ */ ++s8 addressing_table_index(u8 type, u8 density, u8 width) ++{ ++ u8 index; ++ if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) ++ return -1; ++ ++ /* ++ * Look at the way ADDR_TABLE_INDEX* values have been defined ++ * in emif.h compared to LPDDR2_DENSITY_* values ++ * The table is layed out in the increasing order of density ++ * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed ++ * at the end ++ */ ++ if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) ++ index = ADDR_TABLE_INDEX1GS2; ++ else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) ++ index = ADDR_TABLE_INDEX2GS2; ++ else ++ index = density; ++ ++ debug("emif: addressing table index %d\n", index); ++ ++ return index; ++} ++ ++/* ++ * Find the the right timing table from the array of timing ++ * tables of the device using DDR clock frequency ++ */ ++static const struct lpddr2_ac_timings *get_timings_table(const struct ++ lpddr2_ac_timings const *const *device_timings, ++ u32 freq) ++{ ++ u32 i, temp, freq_nearest; ++ const struct lpddr2_ac_timings *timings = 0; ++ ++ emif_assert(freq <= MAX_LPDDR2_FREQ); ++ emif_assert(device_timings); ++ ++ /* ++ * Start with the maximum allowed frequency - that is always safe ++ */ ++ freq_nearest = MAX_LPDDR2_FREQ; ++ /* ++ * Find the timings table that has the max frequency value: ++ * i. Above or equal to the DDR frequency - safe ++ * ii. The lowest that satisfies condition (i) - optimal ++ */ ++ for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { ++ temp = device_timings[i]->max_freq; ++ if ((temp >= freq) && (temp <= freq_nearest)) { ++ freq_nearest = temp; ++ timings = device_timings[i]; ++ } ++ } ++ debug("emif: timings table: %d\n", freq_nearest); ++ return timings; ++} ++ ++/* ++ * Finds the value of emif_sdram_config_reg ++ * All parameters are programmed based on the device on CS0. ++ * If there is a device on CS1, it will be same as that on CS0 or ++ * it will be NVM. We don't support NVM yet. ++ * If cs1_device pointer is NULL it is assumed that there is no device ++ * on CS1 ++ */ ++static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, ++ const struct lpddr2_device_details *cs1_device, ++ const struct lpddr2_addressing *addressing, ++ u8 RL) ++{ ++ u32 config_reg = 0; ++ ++ set_bit_field(config_reg, OMAP44XX_REG_SDRAM_TYPE_SHIFT, ++ OMAP44XX_REG_SDRAM_TYPE_MASK, cs0_device->type + 4); ++ ++ set_bit_field(config_reg, OMAP44XX_REG_IBANK_POS_SHIFT, ++ OMAP44XX_REG_IBANK_POS_MASK, ++ EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING); ++ ++ set_bit_field(config_reg, OMAP44XX_REG_NARROW_MODE_SHIFT, ++ OMAP44XX_REG_NARROW_MODE_MASK, cs0_device->io_width); ++ ++ set_bit_field(config_reg, OMAP44XX_REG_CL_SHIFT, OMAP44XX_REG_CL_MASK, ++ RL); ++ ++ set_bit_field(config_reg, OMAP44XX_REG_ROWSIZE_SHIFT, ++ OMAP44XX_REG_ROWSIZE_MASK, ++ addressing->row_sz[cs0_device->io_width]); ++ ++ set_bit_field(config_reg, OMAP44XX_REG_IBANK_SHIFT, ++ OMAP44XX_REG_IBANK_MASK, addressing->num_banks); ++ ++ set_bit_field(config_reg, OMAP44XX_REG_EBANK_SHIFT, ++ OMAP44XX_REG_EBANK_MASK, ++ (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS)); ++ ++ set_bit_field(config_reg, OMAP44XX_REG_PAGESIZE_SHIFT, ++ OMAP44XX_REG_PAGESIZE_MASK, ++ addressing->col_sz[cs0_device->io_width]); ++ ++ return config_reg; ++} ++ ++static u32 get_sdram_ref_ctrl(u32 freq, ++ const struct lpddr2_addressing *addressing) ++{ ++ u32 ref_ctrl = 0, val = 0, freq_khz; ++ freq_khz = freq / 1000; ++ /* ++ * refresh rate to be set is 'tREFI * freq in MHz ++ * division by 10000 to account for khz and x10 in t_REFI_us_x10 ++ */ ++ val = addressing->t_REFI_us_x10 * freq_khz / 10000; ++ set_bit_field(ref_ctrl, OMAP44XX_REG_REFRESH_RATE_SHIFT, ++ OMAP44XX_REG_REFRESH_RATE_MASK, val); ++ ++ return ref_ctrl; ++} ++ ++static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, ++ const struct lpddr2_min_tck *min_tck, ++ const struct lpddr2_addressing *addressing) ++{ ++ u32 tim1 = 0, val = 0; ++ val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; ++ set_bit_field(tim1, OMAP44XX_REG_T_WTR_SHIFT, OMAP44XX_REG_T_WTR_MASK, ++ val); ++ ++ if (addressing->num_banks == BANKS8) ++ val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / ++ (4 * (*T_num)) - 1; ++ else ++ val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; ++ ++ set_bit_field(tim1, OMAP44XX_REG_T_RRD_SHIFT, OMAP44XX_REG_T_RRD_MASK, ++ val); ++ ++ val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; ++ set_bit_field(tim1, OMAP44XX_REG_T_RC_SHIFT, OMAP44XX_REG_T_RC_MASK, ++ val); ++ ++ val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; ++ set_bit_field(tim1, OMAP44XX_REG_T_RAS_SHIFT, OMAP44XX_REG_T_RAS_MASK, ++ val); ++ ++ val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; ++ set_bit_field(tim1, OMAP44XX_REG_T_WR_SHIFT, OMAP44XX_REG_T_WR_MASK, ++ val); ++ ++ val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; ++ set_bit_field(tim1, OMAP44XX_REG_T_RCD_SHIFT, OMAP44XX_REG_T_RCD_MASK, ++ val); ++ val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; ++ set_bit_field(tim1, OMAP44XX_REG_T_RP_SHIFT, OMAP44XX_REG_T_RP_MASK, ++ val); ++ ++ return tim1; ++} ++ ++static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, ++ const struct lpddr2_min_tck *min_tck) ++{ ++ u32 tim2 = 0, val = 0; ++ val = max(min_tck->tCKE, timings->tCKE) - 1; ++ set_bit_field(tim2, OMAP44XX_REG_T_CKE_SHIFT, OMAP44XX_REG_T_CKE_MASK, ++ val); ++ ++ val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; ++ set_bit_field(tim2, OMAP44XX_REG_T_RTP_SHIFT, OMAP44XX_REG_T_RTP_MASK, ++ val); ++ ++ /* ++ * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the ++ * same value ++ */ ++ val = ns_2_cycles(timings->tXSR) - 1; ++ set_bit_field(tim2, OMAP44XX_REG_T_XSRD_SHIFT, OMAP44XX_REG_T_XSRD_MASK, ++ val); ++ set_bit_field(tim2, OMAP44XX_REG_T_XSNR_SHIFT, OMAP44XX_REG_T_XSNR_MASK, ++ val); ++ ++ val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; ++ set_bit_field(tim2, OMAP44XX_REG_T_XP_SHIFT, OMAP44XX_REG_T_XP_MASK, ++ val); ++ ++ return tim2; ++} ++ ++static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, ++ const struct lpddr2_min_tck *min_tck, ++ const struct lpddr2_addressing *addressing) ++{ ++ u32 tim3 = 0, val = 0; ++ val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); ++ set_bit_field(tim3, OMAP44XX_REG_T_RAS_MAX_SHIFT, ++ OMAP44XX_REG_T_RAS_MAX_MASK, val); ++ ++ val = ns_2_cycles(timings->tRFCab) - 1; ++ set_bit_field(tim3, OMAP44XX_REG_T_RFC_SHIFT, OMAP44XX_REG_T_RFC_MASK, ++ val); ++ ++ val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; ++ set_bit_field(tim3, OMAP44XX_REG_T_TDQSCKMAX_SHIFT, ++ OMAP44XX_REG_T_TDQSCKMAX_MASK, val); ++ ++ val = ns_2_cycles(timings->tZQCS) - 1; ++ set_bit_field(tim3, OMAP44XX_REG_ZQ_ZQCS_SHIFT, ++ OMAP44XX_REG_ZQ_ZQCS_MASK, val); ++ ++ val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; ++ set_bit_field(tim3, OMAP44XX_REG_T_CKESR_SHIFT, ++ OMAP44XX_REG_T_CKESR_MASK, val); ++ ++ return tim3; ++} ++ ++static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, ++ const struct lpddr2_addressing *addressing, ++ u8 volt_ramp) ++{ ++ u32 zq = 0, val = 0; ++ if (volt_ramp) ++ val = ++ EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / ++ addressing->t_REFI_us_x10; ++ else ++ val = ++ EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / ++ addressing->t_REFI_us_x10; ++ set_bit_field(zq, OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT, ++ OMAP44XX_REG_ZQ_REFINTERVAL_MASK, val); ++ ++ set_bit_field(zq, OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT, ++ OMAP44XX_REG_ZQ_ZQCL_MULT_MASK, REG_ZQ_ZQCL_MULT - 1); ++ ++ set_bit_field(zq, OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT, ++ OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK, REG_ZQ_ZQINIT_MULT - 1); ++ ++ set_bit_field(zq, OMAP44XX_REG_ZQ_SFEXITEN_SHIFT, ++ OMAP44XX_REG_ZQ_SFEXITEN_MASK, REG_ZQ_SFEXITEN_ENABLE); ++ ++ /* ++ * Assuming that two chipselects have a single calibration resistor ++ * If there are indeed two calibration resistors, then this flag should ++ * be enabled to take advantage of dual calibration feature. ++ * This data should ideally come from board files. But considering ++ * that none of the boards today have calibration resistors per CS, ++ * it would be an unnecessary overhead. ++ */ ++ set_bit_field(zq, OMAP44XX_REG_ZQ_DUALCALEN_SHIFT, ++ OMAP44XX_REG_ZQ_DUALCALEN_MASK, REG_ZQ_DUALCALEN_DISABLE); ++ ++ set_bit_field(zq, OMAP44XX_REG_ZQ_CS0EN_SHIFT, ++ OMAP44XX_REG_ZQ_CS0EN_MASK, REG_ZQ_CS0EN_ENABLE); ++ ++ set_bit_field(zq, OMAP44XX_REG_ZQ_CS1EN_SHIFT, ++ OMAP44XX_REG_ZQ_CS1EN_MASK, (cs1_device ? 1 : 0)); ++ ++ return zq; ++} ++ ++static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, ++ const struct lpddr2_addressing *addressing, ++ u8 is_derated) ++{ ++ u32 alert = 0, interval; ++ interval = ++ TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; ++ if (is_derated) ++ interval *= 4; ++ set_bit_field(alert, OMAP44XX_REG_TA_REFINTERVAL_SHIFT, ++ OMAP44XX_REG_TA_REFINTERVAL_MASK, interval); ++ ++ set_bit_field(alert, OMAP44XX_REG_TA_DEVCNT_SHIFT, ++ OMAP44XX_REG_TA_DEVCNT_MASK, TEMP_ALERT_CONFIG_DEVCT_1); ++ ++ set_bit_field(alert, OMAP44XX_REG_TA_DEVWDT_SHIFT, ++ OMAP44XX_REG_TA_DEVWDT_MASK, TEMP_ALERT_CONFIG_DEVWDT_32); ++ ++ set_bit_field(alert, OMAP44XX_REG_TA_SFEXITEN_SHIFT, ++ OMAP44XX_REG_TA_SFEXITEN_MASK, 1); ++ ++ set_bit_field(alert, OMAP44XX_REG_TA_CS0EN_SHIFT, ++ OMAP44XX_REG_TA_CS0EN_MASK, 1); ++ ++ set_bit_field(alert, OMAP44XX_REG_TA_CS1EN_SHIFT, ++ OMAP44XX_REG_TA_CS1EN_MASK, (cs1_device ? 1 : 0)); ++ ++ return alert; ++} ++ ++static u32 get_read_idle_ctrl_reg(u8 volt_ramp) ++{ ++ u32 idle = 0, val = 0; ++ if (volt_ramp) ++ val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1; ++ else ++ /*Maximum value in normal conditions - suggested by hw team */ ++ val = 0x1FF; ++ set_bit_field(idle, OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT, ++ OMAP44XX_REG_READ_IDLE_INTERVAL_MASK, val); ++ ++ set_bit_field(idle, OMAP44XX_REG_READ_IDLE_LEN_SHIFT, ++ OMAP44XX_REG_READ_IDLE_LEN_MASK, ++ EMIF_REG_READ_IDLE_LEN_VAL); ++ ++ return idle; ++} ++ ++static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) ++{ ++ u32 phy = 0, val = 0; ++ ++ set_bit_field(phy, OMAP44XX_REG_READ_LATENCY_SHIFT, ++ OMAP44XX_REG_READ_LATENCY_MASK, RL + 2); ++ ++ if (freq <= 100000000) ++ val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; ++ else if (freq <= 200000000) ++ val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; ++ else ++ val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; ++ set_bit_field(phy, OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT, ++ OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK, val); ++ ++ /* Other fields are constant magic values. Hardcode them together */ ++ set_bit_field(phy, OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT, ++ OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK, ++ EMIF_DDR_PHY_CTRL_1_BASE_VAL); ++ ++ return phy; ++} ++ ++const char *get_lpddr2_type(u8 type_id) ++{ ++ switch (type_id) { ++ case LPDDR2_TYPE_S4: ++ return "LPDDR2-S4"; ++ case LPDDR2_TYPE_S2: ++ return "LPDDR2-S2"; ++ default: ++ return NULL; ++ } ++} ++ ++const char *get_lpddr2_io_width(u8 width_id) ++{ ++ switch (width_id) { ++ case LPDDR2_IO_WIDTH_8: ++ return "x8"; ++ case LPDDR2_IO_WIDTH_16: ++ return "x16"; ++ case LPDDR2_IO_WIDTH_32: ++ return "x32"; ++ default: ++ return NULL; ++ } ++} ++ ++const char *get_lpddr2_manufacturer(u32 manufacturer) ++{ ++ switch (manufacturer) { ++ case LPDDR2_MANUFACTURER_SAMSUNG: ++ return "Samsung"; ++ case LPDDR2_MANUFACTURER_QIMONDA: ++ return "Qimonda"; ++ case LPDDR2_MANUFACTURER_ELPIDA: ++ return "Elpida"; ++ case LPDDR2_MANUFACTURER_ETRON: ++ return "Etron"; ++ case LPDDR2_MANUFACTURER_NANYA: ++ return "Nanya"; ++ case LPDDR2_MANUFACTURER_HYNIX: ++ return "Hynix"; ++ case LPDDR2_MANUFACTURER_MOSEL: ++ return "Mosel"; ++ case LPDDR2_MANUFACTURER_WINBOND: ++ return "Winbond"; ++ case LPDDR2_MANUFACTURER_ESMT: ++ return "ESMT"; ++ case LPDDR2_MANUFACTURER_SPANSION: ++ return "Spansion"; ++ case LPDDR2_MANUFACTURER_SST: ++ return "SST"; ++ case LPDDR2_MANUFACTURER_ZMOS: ++ return "ZMOS"; ++ case LPDDR2_MANUFACTURER_INTEL: ++ return "Intel"; ++ case LPDDR2_MANUFACTURER_NUMONYX: ++ return "Numonyx"; ++ case LPDDR2_MANUFACTURER_MICRON: ++ return "Micron"; ++ default: ++ return NULL; ++ } ++} ++ + static inline u32 emif_num(u32 base) + { + if (base == OMAP44XX_EMIF1) +@@ -65,6 +648,127 @@ static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif->emif_lpddr2_mode_reg_data); + } ++ ++static void emif_calculate_regs( ++ const struct emif_device_details *emif_dev_details, ++ u32 freq, struct emif_regs *regs) ++{ ++ u32 temp, sys_freq; ++ const struct lpddr2_addressing *addressing; ++ const struct lpddr2_ac_timings *timings; ++ const struct lpddr2_min_tck *min_tck; ++ const struct lpddr2_device_details *cs0_dev_details = ++ emif_dev_details->cs0_device_details; ++ const struct lpddr2_device_details *cs1_dev_details = ++ emif_dev_details->cs1_device_details; ++ const struct lpddr2_device_timings *cs0_dev_timings = ++ emif_dev_details->cs0_device_timings; ++ ++ emif_assert(emif_dev_details); ++ emif_assert(regs); ++ /* ++ * You can not have a device on CS1 without one on CS0 ++ * So configuring EMIF without a device on CS0 doesn't ++ * make sense ++ */ ++ emif_assert(cs0_dev_details); ++ emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); ++ /* ++ * If there is a device on CS1 it should be same type as CS0 ++ * (or NVM. But NVM is not supported in this driver yet) ++ */ ++ emif_assert((cs1_dev_details == NULL) || ++ (cs1_dev_details->type == LPDDR2_TYPE_NVM) || ++ (cs0_dev_details->type == cs1_dev_details->type)); ++ emif_assert(freq <= MAX_LPDDR2_FREQ); ++ ++ set_ddr_clk_period(freq); ++ ++ /* ++ * The device on CS0 is used for all timing calculations ++ * There is only one set of registers for timings per EMIF. So, if the ++ * second CS(CS1) has a device, it should have the same timings as the ++ * device on CS0 ++ */ ++ timings = get_timings_table(cs0_dev_timings->ac_timings, freq); ++ emif_assert(timings); ++ min_tck = cs0_dev_timings->min_tck; ++ ++ temp = addressing_table_index(cs0_dev_details->type, ++ cs0_dev_details->density, ++ cs0_dev_details->io_width); ++ ++ emif_assert((temp >= 0)); ++ addressing = &(addressing_table[temp]); ++ emif_assert(addressing); ++ ++ sys_freq = get_syc_clk_freq(); ++ ++ regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, ++ cs1_dev_details, ++ addressing, RL_BOOT); ++ ++ regs->sdram_config = get_sdram_config_reg(cs0_dev_details, ++ cs1_dev_details, ++ addressing, RL_FINAL); ++ ++ regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); ++ ++ regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); ++ ++ regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); ++ ++ regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); ++ ++ regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); ++ ++ regs->temp_alert_config = ++ get_temp_alert_config(cs1_dev_details, addressing, 0); ++ ++ regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, ++ LPDDR2_VOLTAGE_STABLE); ++ ++ regs->emif_ddr_phy_ctlr_1_init = ++ get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); ++ ++ regs->emif_ddr_phy_ctlr_1 = ++ get_ddr_phy_ctrl_1(freq, RL_FINAL); ++ ++ regs->freq = freq; ++ ++ print_timing_reg(regs->sdram_config_init); ++ print_timing_reg(regs->sdram_config); ++ print_timing_reg(regs->ref_ctrl); ++ print_timing_reg(regs->sdram_tim1); ++ print_timing_reg(regs->sdram_tim2); ++ print_timing_reg(regs->sdram_tim3); ++ print_timing_reg(regs->read_idle_ctrl); ++ print_timing_reg(regs->temp_alert_config); ++ print_timing_reg(regs->zq_config); ++ print_timing_reg(regs->emif_ddr_phy_ctlr_1); ++ print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); ++} ++ ++static u32 get_emif_mem_size(struct emif_device_details *devices) ++{ ++ u32 size_mbytes = 0, temp; ++ ++ if (!devices) ++ return 0; ++ ++ if (devices->cs0_device_details) { ++ temp = devices->cs0_device_details->density; ++ size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; ++ } ++ ++ if (devices->cs1_device_details) { ++ temp = devices->cs1_device_details->density; ++ size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; ++ } ++ /* convert to bytes */ ++ return size_mbytes << 20; ++} ++ + void emif_reset_phy(u32 base) + { + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; +@@ -158,14 +862,66 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs) + + static void do_sdram_init(u32 base) + { +- const struct emif_regs *regs, *tmp_regs; ++ struct emif_device_details dev_details; ++ const struct emif_regs *regs; ++ + u32 in_sdram, emif_nr; + + in_sdram = running_from_sdram(); + emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2; + ++#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS ++ const struct emif_regs *tmp_regs; + emif_get_reg_dump(®s, &tmp_regs); + regs = (emif_nr == 1) ? regs : tmp_regs; ++#else ++ /* ++ * The user has not provided the register values. We need to ++ * calculate it based on the timings and the DDR frequency ++ */ ++ ++ const struct emif_device_details *dev_details_user_provided; ++ const struct emif_device_details *tmp_details; ++ struct emif_regs calculated_regs; ++ ++ /* We need some input about the devices from the user */ ++ emif_get_device_details(&dev_details_user_provided, &tmp_details); ++ dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided ++ : tmp_details; ++ if (!dev_details_user_provided) ++ return; ++ ++ dev_details.cs0_device_details = ++ dev_details_user_provided->cs0_device_details; ++ dev_details.cs1_device_details = ++ dev_details_user_provided->cs1_device_details; ++ ++ /* Return if no devices on this EMIF */ ++ if (!dev_details.cs0_device_details && ++ !dev_details.cs1_device_details) { ++ emif_sizes[emif_nr - 1] = 0; ++ return; ++ } ++ ++ if (!in_sdram) ++ emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details); ++ ++#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS ++ /* Use the base timings specified by JESD209-2 */ ++ dev_details.cs0_device_timings = &jedec_default_timings; ++ dev_details.cs1_device_timings = &jedec_default_timings; ++ ++#else /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ ++ dev_details.cs0_device_timings = ++ dev_details_user_provided->cs0_device_timings; ++ dev_details.cs1_device_timings = ++ dev_details_user_provided->cs1_device_timings; ++#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ ++ /* Calculate the register values */ ++ emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs); ++ regs = &calculated_regs; ++ ++#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + + /* + * Initializing the LPDDR2 device can not happen from SDRAM. +@@ -215,12 +971,111 @@ static void emif_post_init_config(u32 base) + writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); + } + ++/* Gets the encoding corresponding to a given DMM section size */ ++u32 get_dmm_section_size_map(u32 section_size) ++{ ++ /* ++ * Section size mapping: ++ * 0x0: 16-MiB section ++ * 0x1: 32-MiB section ++ * 0x2: 64-MiB section ++ * 0x3: 128-MiB section ++ * 0x4: 256-MiB section ++ * 0x5: 512-MiB section ++ * 0x6: 1-GiB section ++ * 0x7: 2-GiB section ++ */ ++ section_size >>= 24; /* divide by 16 MB */ ++ return log_2_n_round_down(section_size); ++} ++ + static void dmm_init(u32 base) + { + const struct dmm_lisa_map_regs *lisa_map_regs; + ++#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + emif_get_dmm_regs(&lisa_map_regs); ++#else ++ u32 emif1_size, emif2_size, mapped_size, section_map; ++ u32 section_cnt, sys_addr; ++ struct dmm_lisa_map_regs lis_map_regs_calculated; ++ ++ mapped_size = 0; ++ section_cnt = 3; ++ sys_addr = CONFIG_SYS_SDRAM_BASE; ++ emif1_size = emif_sizes[0]; ++ emif2_size = emif_sizes[1]; ++ debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); + ++ if (!emif1_size && !emif2_size) ++ return; ++ ++ /* symmetric interleaved section */ ++ if (emif1_size && emif2_size) { ++ mapped_size = min(emif1_size, emif2_size); ++ section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; ++ set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT, ++ OMAP44XX_SDRC_ADDR_MASK, ++ 0); ++ set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT, ++ OMAP44XX_SYS_ADDR_MASK, ++ sys_addr >> 24); /* only MSB */ ++ set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT, ++ OMAP44XX_SYS_SIZE_MASK, ++ get_dmm_section_size_map(mapped_size * 2)); ++ lis_map_regs_calculated.dmm_lisa_map_3 = section_map; ++ emif1_size -= mapped_size; ++ emif2_size -= mapped_size; ++ sys_addr += (mapped_size * 2); ++ section_cnt--; ++ } ++ ++ /* ++ * Single EMIF section(we can have a maximum of 1 single EMIF ++ * section- either EMIF1 or EMIF2 or none, but not both) ++ */ ++ if (emif1_size) { ++ section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; ++ set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT, ++ OMAP44XX_SYS_SIZE_MASK, ++ get_dmm_section_size_map(emif1_size)); ++ set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT, ++ OMAP44XX_SDRC_ADDR_MASK, ++ mapped_size >> 24); /* only MSB */ ++ set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT, ++ OMAP44XX_SYS_ADDR_MASK, ++ sys_addr >> 24); /* only MSB */ ++ section_cnt--; ++ } ++ if (emif2_size) { ++ section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; ++ set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT, ++ OMAP44XX_SYS_SIZE_MASK, ++ get_dmm_section_size_map(emif2_size)); ++ set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT, ++ OMAP44XX_SDRC_ADDR_MASK, ++ mapped_size >> 24); /* only MSB */ ++ set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT, ++ OMAP44XX_SYS_ADDR_MASK, ++ sys_addr >> 24); /* only MSB */ ++ section_cnt--; ++ } ++ ++ if (section_cnt == 2) { ++ /* Only 1 section - either symmetric or single EMIF */ ++ lis_map_regs_calculated.dmm_lisa_map_3 = section_map; ++ lis_map_regs_calculated.dmm_lisa_map_2 = 0; ++ lis_map_regs_calculated.dmm_lisa_map_1 = 0; ++ } else { ++ /* 2 sections - 1 symmetric, 1 single EMIF */ ++ lis_map_regs_calculated.dmm_lisa_map_2 = section_map; ++ lis_map_regs_calculated.dmm_lisa_map_1 = 0; ++ } ++ /* TRAP for invalid TILER mappings in section 0 */ ++ lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; ++ ++ lisa_map_regs = &lis_map_regs_calculated; ++#endif + struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)base; + +@@ -258,8 +1113,10 @@ static void dmm_init(u32 base) + */ + void sdram_init(void) + { +- u32 in_sdram; ++ if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL) ++ return; + ++ u32 in_sdram; + in_sdram = running_from_sdram(); + + if (!in_sdram) { +diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c +index 37e808c..e7d2bd5 100644 +--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c ++++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c +@@ -29,6 +29,8 @@ + #include + #include + ++#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS ++ + static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, +@@ -86,6 +88,131 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + + void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs, + const struct emif_regs **emif2_regs) ++ ++#else ++ ++static const struct lpddr2_ac_timings timings_elpida_400_mhz = { ++ .max_freq = 400000000, ++ .RL = 6, ++ .tRPab = 21, ++ .tRCD = 18, ++ .tWR = 15, ++ .tRASmin = 42, ++ .tRRD = 10, ++ .tWTRx2 = 15, ++ .tXSR = 140, ++ .tXPx2 = 15, ++ .tRFCab = 130, ++ .tRTPx2 = 15, ++ .tCKE = 3, ++ .tCKESR = 15, ++ .tZQCS = 90, ++ .tZQCL = 360, ++ .tZQINIT = 1000, ++ .tDQSCKMAXx2 = 11, ++ .tRASmax = 70, ++ .tFAW = 50 ++}; ++ ++static const struct lpddr2_ac_timings timings_elpida_333_mhz = { ++ .max_freq = 333000000, ++ .RL = 5, ++ .tRPab = 21, ++ .tRCD = 18, ++ .tWR = 15, ++ .tRASmin = 42, ++ .tRRD = 10, ++ .tWTRx2 = 15, ++ .tXSR = 140, ++ .tXPx2 = 15, ++ .tRFCab = 130, ++ .tRTPx2 = 15, ++ .tCKE = 3, ++ .tCKESR = 15, ++ .tZQCS = 90, ++ .tZQCL = 360, ++ .tZQINIT = 1000, ++ .tDQSCKMAXx2 = 11, ++ .tRASmax = 70, ++ .tFAW = 50 ++}; ++ ++static const struct lpddr2_ac_timings timings_elpida_200_mhz = { ++ .max_freq = 200000000, ++ .RL = 3, ++ .tRPab = 21, ++ .tRCD = 18, ++ .tWR = 15, ++ .tRASmin = 42, ++ .tRRD = 10, ++ .tWTRx2 = 20, ++ .tXSR = 140, ++ .tXPx2 = 15, ++ .tRFCab = 130, ++ .tRTPx2 = 15, ++ .tCKE = 3, ++ .tCKESR = 15, ++ .tZQCS = 90, ++ .tZQCL = 360, ++ .tZQINIT = 1000, ++ .tDQSCKMAXx2 = 11, ++ .tRASmax = 70, ++ .tFAW = 50 ++}; ++ ++static const struct lpddr2_min_tck min_tck_elpida = { ++ .tRL = 3, ++ .tRP_AB = 3, ++ .tRCD = 3, ++ .tWR = 3, ++ .tRAS_MIN = 3, ++ .tRRD = 2, ++ .tWTR = 2, ++ .tXP = 2, ++ .tRTP = 2, ++ .tCKE = 3, ++ .tCKESR = 3, ++ .tFAW = 8 ++}; ++ ++static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { ++ &timings_elpida_200_mhz, ++ &timings_elpida_333_mhz, ++ &timings_elpida_400_mhz, ++}; ++ ++static const struct lpddr2_device_details elpida_2G_S4_details = { ++ .type = LPDDR2_TYPE_S4, ++ .density = LPDDR2_DENSITY_2Gb, ++ .io_width = LPDDR2_IO_WIDTH_32, ++ .manufacturer = LPDDR2_MANUFACTURER_ELPIDA ++}; ++ ++static const struct lpddr2_device_timings elpida_2G_S4_timings = { ++ .ac_timings = elpida_ac_timings, ++ .min_tck = &min_tck_elpida, ++}; ++ ++static const struct emif_device_details elpida_2G_S4_x_2 = { ++ .cs0_device_details = &elpida_2G_S4_details, ++ .cs1_device_details = &elpida_2G_S4_details, ++ .cs0_device_timings = &elpida_2G_S4_timings, ++ .cs1_device_timings = &elpida_2G_S4_timings ++}; ++ ++static const struct emif_device_details elpida_2G_S4_x_1 = { ++ .cs0_device_details = &elpida_2G_S4_details, ++ .cs1_device_details = NULL, ++ .cs0_device_timings = &elpida_2G_S4_timings, ++ .cs1_device_timings = NULL ++}; ++ ++#endif /* ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ ++ ++#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS ++ ++static void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs, ++ const struct emif_regs **emif2_regs) + { + u32 omap4_rev = omap4_revision(); + +@@ -104,7 +231,8 @@ void emif_get_reg_dump(const struct emif_regs **emif1_regs, + const struct emif_regs **emif2_regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +-void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) ++static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs ++ **dmm_lisa_regs) + { + u32 omap_rev = omap4_revision(); + +@@ -116,3 +244,25 @@ void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) + + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); ++ ++#else ++ ++static void emif_get_device_details_sdp( ++ const struct emif_device_details **emif1_details, ++ const struct emif_device_details **emif2_details) ++{ ++ u32 omap_rev = omap4_revision(); ++ ++ if (omap_rev == OMAP4430_ES1_0) { ++ *emif1_details = &elpida_2G_S4_x_1; ++ *emif2_details = &elpida_2G_S4_x_1; ++ } else { ++ *emif1_details = &elpida_2G_S4_x_2; ++ *emif2_details = &elpida_2G_S4_x_2; ++ } ++} ++ ++void emif_get_device_details(const struct emif_device_details **emif1_details, ++ const struct emif_device_details **emif2_details) ++ __attribute__((weak, alias("emif_get_device_details_sdp"))); ++#endif +diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h +index f2d54cb..8cc3230 100644 +--- a/arch/arm/include/asm/arch-omap4/emif.h ++++ b/arch/arm/include/asm/arch-omap4/emif.h +@@ -591,10 +591,142 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs { + + #define CS0 0 + #define CS1 1 ++/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ ++#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ ++ ++/* ++ * The period of DDR clk is represented as numerator and denominator for ++ * better accuracy in integer based calculations. However, if the numerator ++ * and denominator are very huge there may be chances of overflow in ++ * calculations. So, as a trade-off keep denominator(and consequently ++ * numerator) within a limit sacrificing some accuracy - but not much ++ * If denominator and numerator are already small (such as at 400 MHz) ++ * no adjustment is needed ++ */ ++#define EMIF_PERIOD_DEN_LIMIT 1000 ++/* ++ * Maximum number of different frequencies supported by EMIF driver ++ * Determines the number of entries in the pointer array for register ++ * cache ++ */ ++#define EMIF_MAX_NUM_FREQUENCIES 6 ++/* ++ * Indices into the Addressing Table array. ++ * One entry each for all the different types of devices with different ++ * addressing schemes ++ */ ++#define ADDR_TABLE_INDEX64M 0 ++#define ADDR_TABLE_INDEX128M 1 ++#define ADDR_TABLE_INDEX256M 2 ++#define ADDR_TABLE_INDEX512M 3 ++#define ADDR_TABLE_INDEX1GS4 4 ++#define ADDR_TABLE_INDEX2GS4 5 ++#define ADDR_TABLE_INDEX4G 6 ++#define ADDR_TABLE_INDEX8G 7 ++#define ADDR_TABLE_INDEX1GS2 8 ++#define ADDR_TABLE_INDEX2GS2 9 ++#define ADDR_TABLE_INDEXMAX 10 ++ ++/* Number of Row bits */ ++#define ROW_9 0 ++#define ROW_10 1 ++#define ROW_11 2 ++#define ROW_12 3 ++#define ROW_13 4 ++#define ROW_14 5 ++#define ROW_15 6 ++#define ROW_16 7 ++ ++/* Number of Column bits */ ++#define COL_8 0 ++#define COL_9 1 ++#define COL_10 2 ++#define COL_11 3 ++#define COL_7 4 /*Not supported by OMAP included for completeness */ ++ ++/* Number of Banks*/ ++#define BANKS1 0 ++#define BANKS2 1 ++#define BANKS4 2 ++#define BANKS8 3 ++ ++/* Refresh rate in micro seconds x 10 */ ++#define T_REFI_15_6 156 ++#define T_REFI_7_8 78 ++#define T_REFI_3_9 39 ++ ++#define EBANK_CS1_DIS 0 ++#define EBANK_CS1_EN 1 ++ + /* Read Latency used by the device at reset */ + #define RL_BOOT 3 + /* Read Latency for the highest frequency you want to use */ + #define RL_FINAL 6 ++ ++/* Interleaving policies at EMIF level- between banks and Chip Selects */ ++#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 ++#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 ++ ++/* ++ * Interleaving policy to be used ++ * Currently set to MAX interleaving for better performance ++ */ ++#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING ++ ++/* State of the core voltage: ++ * This is important for some parameters such as read idle control and ++ * ZQ calibration timings. Timings are much stricter when voltage ramp ++ * is happening compared to when the voltage is stable. ++ * We need to calculate two sets of values for these parameters and use ++ * them accordingly ++ */ ++#define LPDDR2_VOLTAGE_STABLE 0 ++#define LPDDR2_VOLTAGE_RAMPING 1 ++ ++/* Length of the forced read idle period in terms of cycles */ ++#define EMIF_REG_READ_IDLE_LEN_VAL 5 ++ ++/* Interval between forced 'read idles' */ ++/* To be used when voltage is changed for DPS/DVFS - 1us */ ++#define READ_IDLE_INTERVAL_DVFS (1*1000) ++/* ++ * To be used when voltage is not scaled except by Smart Reflex ++ * 50us - or maximum value will do ++ */ ++#define READ_IDLE_INTERVAL_NORMAL (50*1000) ++ ++ ++/* ++ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should ++ * be enough. This shoule be enough also in the case when voltage is changing ++ * due to smart-reflex. ++ */ ++#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) ++/* ++ * If voltage is changing due to DVFS ZQCS should be performed more ++ * often(every 50us) ++ */ ++#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 ++ ++/* The interval between ZQCL commands as a multiple of ZQCS interval */ ++#define REG_ZQ_ZQCL_MULT 4 ++/* The interval between ZQINIT commands as a multiple of ZQCL interval */ ++#define REG_ZQ_ZQINIT_MULT 3 ++/* Enable ZQ Calibration on exiting Self-refresh */ ++#define REG_ZQ_SFEXITEN_ENABLE 1 ++/* ++ * ZQ Calibration simultaneously on both chip-selects: ++ * Needs one calibration resistor per CS ++ * None of the boards that we know of have this capability ++ * So disabled by default ++ */ ++#define REG_ZQ_DUALCALEN_DISABLE 0 ++/* ++ * Enable ZQ Calibration by default on CS0. If we are asked to program ++ * the EMIF there will be something connected to CS0 for sure ++ */ ++#define REG_ZQ_CS0EN_ENABLE 1 ++ + /* EMIF_PWR_MGMT_CTRL register */ + /* Low power modes */ + #define LP_MODE_DISABLE 0 +@@ -634,6 +766,16 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs { + + /* EMIF_L3_CONFIG register value for ES1*/ + #define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00 0x0A0000FF ++/* ++ * Value of bits 12:31 of DDR_PHY_CTRL_1 register: ++ * All these fields have magic values dependent on frequency and ++ * determined by PHY and DLL integration with EMIF. Setting the magic ++ * values suggested by hw team. ++ */ ++#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF ++#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 ++#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 ++#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF + + /* + * MR1 value: +@@ -657,16 +799,51 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs { + #define MR10_ZQ_ZQINIT 0xFF + #define MR10_ZQ_ZQRESET 0xC3 + ++/* TEMP_ALERT_CONFIG */ ++#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ ++#define TEMP_ALERT_CONFIG_DEVCT_1 0 ++#define TEMP_ALERT_CONFIG_DEVWDT_32 2 ++ + /* MR16 value: refresh full array(no partial array self refresh) */ + #define MR16_REF_FULL_ARRAY 0 + +-/* LPDDR2 IO reg values */ ++/* LPDDR2 IO regs */ + #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C + #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E + + /* CONTROL_EFUSE_2 */ + #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + ++/* ++ * Maximum number of entries we keep in our array of timing tables ++ * We need not keep all the speed bins supported by the device ++ * We need to keep timing tables for only the speed bins that we ++ * are interested in ++ */ ++#define MAX_NUM_SPEEDBINS 4 ++ ++/* LPDDR2 Densities */ ++#define LPDDR2_DENSITY_64Mb 0 ++#define LPDDR2_DENSITY_128Mb 1 ++#define LPDDR2_DENSITY_256Mb 2 ++#define LPDDR2_DENSITY_512Mb 3 ++#define LPDDR2_DENSITY_1Gb 4 ++#define LPDDR2_DENSITY_2Gb 5 ++#define LPDDR2_DENSITY_4Gb 6 ++#define LPDDR2_DENSITY_8Gb 7 ++#define LPDDR2_DENSITY_16Gb 8 ++#define LPDDR2_DENSITY_32Gb 9 ++ ++/* LPDDR2 type */ ++#define LPDDR2_TYPE_S4 0 ++#define LPDDR2_TYPE_S2 1 ++#define LPDDR2_TYPE_NVM 2 ++ ++/* LPDDR2 IO width */ ++#define LPDDR2_IO_WIDTH_32 0 ++#define LPDDR2_IO_WIDTH_16 1 ++#define LPDDR2_IO_WIDTH_8 2 ++ + /* Mode register numbers */ + #define LPDDR2_MR0 0 + #define LPDDR2_MR1 1 +@@ -692,6 +869,119 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs { + #define LPDDR2_MR0_DNVI_SHIFT 2 + #define LPDDR2_MR0_DNVI_MASK (1 << 2) + ++/* MR4 */ ++#define MR4_SDRAM_REF_RATE_SHIFT 0 ++#define MR4_SDRAM_REF_RATE_MASK 7 ++#define MR4_TUF_SHIFT 7 ++#define MR4_TUF_MASK (1 << 7) ++ ++/* MR4 SDRAM Refresh Rate field values */ ++#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 ++#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 ++#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 ++#define SDRAM_TEMP_NOMINAL 0x3 ++#define SDRAM_TEMP_RESERVED_4 0x4 ++#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 ++#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 ++#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 ++ ++#define LPDDR2_MANUFACTURER_SAMSUNG 1 ++#define LPDDR2_MANUFACTURER_QIMONDA 2 ++#define LPDDR2_MANUFACTURER_ELPIDA 3 ++#define LPDDR2_MANUFACTURER_ETRON 4 ++#define LPDDR2_MANUFACTURER_NANYA 5 ++#define LPDDR2_MANUFACTURER_HYNIX 6 ++#define LPDDR2_MANUFACTURER_MOSEL 7 ++#define LPDDR2_MANUFACTURER_WINBOND 8 ++#define LPDDR2_MANUFACTURER_ESMT 9 ++#define LPDDR2_MANUFACTURER_SPANSION 11 ++#define LPDDR2_MANUFACTURER_SST 12 ++#define LPDDR2_MANUFACTURER_ZMOS 13 ++#define LPDDR2_MANUFACTURER_INTEL 14 ++#define LPDDR2_MANUFACTURER_NUMONYX 254 ++#define LPDDR2_MANUFACTURER_MICRON 255 ++ ++/* MR8 register fields */ ++#define MR8_TYPE_SHIFT 0x0 ++#define MR8_TYPE_MASK 0x3 ++#define MR8_DENSITY_SHIFT 0x2 ++#define MR8_DENSITY_MASK (0xF << 0x2) ++#define MR8_IO_WIDTH_SHIFT 0x6 ++#define MR8_IO_WIDTH_MASK (0x3 << 0x6) ++ ++struct lpddr2_addressing { ++ u8 num_banks; ++ u8 t_REFI_us_x10; ++ u8 row_sz[2]; /* One entry each for x32 and x16 */ ++ u8 col_sz[2]; /* One entry each for x32 and x16 */ ++}; ++ ++/* Structure for timings from the DDR datasheet */ ++struct lpddr2_ac_timings { ++ u32 max_freq; ++ u8 RL; ++ u8 tRPab; ++ u8 tRCD; ++ u8 tWR; ++ u8 tRASmin; ++ u8 tRRD; ++ u8 tWTRx2; ++ u8 tXSR; ++ u8 tXPx2; ++ u8 tRFCab; ++ u8 tRTPx2; ++ u8 tCKE; ++ u8 tCKESR; ++ u8 tZQCS; ++ u32 tZQCL; ++ u32 tZQINIT; ++ u8 tDQSCKMAXx2; ++ u8 tRASmax; ++ u8 tFAW; ++ ++}; ++ ++/* ++ * Min tCK values for some of the parameters: ++ * If the calculated clock cycles for the respective parameter is ++ * less than the corresponding min tCK value, we need to set the min ++ * tCK value. This may happen at lower frequencies. ++ */ ++struct lpddr2_min_tck { ++ u32 tRL; ++ u32 tRP_AB; ++ u32 tRCD; ++ u32 tWR; ++ u32 tRAS_MIN; ++ u32 tRRD; ++ u32 tWTR; ++ u32 tXP; ++ u32 tRTP; ++ u8 tCKE; ++ u32 tCKESR; ++ u32 tFAW; ++}; ++ ++struct lpddr2_device_details { ++ u8 type; ++ u8 density; ++ u8 io_width; ++ u8 manufacturer; ++}; ++ ++struct lpddr2_device_timings { ++ const struct lpddr2_ac_timings **ac_timings; ++ const struct lpddr2_min_tck *min_tck; ++}; ++ ++/* Details of the devices connected to each chip-select of an EMIF instance */ ++struct emif_device_details { ++ const struct lpddr2_device_details *cs0_device_details; ++ const struct lpddr2_device_details *cs1_device_details; ++ const struct lpddr2_device_timings *cs0_device_timings; ++ const struct lpddr2_device_timings *cs1_device_timings; ++}; ++ + /* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for +@@ -712,8 +1002,20 @@ struct emif_regs { + u32 emif_ddr_phy_ctlr_1; + }; + ++/* assert macros */ ++#if defined(DEBUG) ++#define emif_assert(c) ({ if (!(c)) for (;;); }) ++#else ++#define emif_assert(c) ({ if (0) hang(); }) ++#endif ++ ++#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + void emif_get_reg_dump(const struct emif_regs **emif1_regs, + const struct emif_regs **emif2_regs); + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); ++#else ++void emif_get_device_details(const struct emif_device_details **emif1_details, ++ const struct emif_device_details **emif2_details); ++#endif + + #endif +diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h +index a1c4883..fd8fb10 100644 +--- a/arch/arm/include/asm/arch-omap4/omap4.h ++++ b/arch/arm/include/asm/arch-omap4/omap4.h +@@ -86,12 +86,7 @@ + /* GPMC */ + #define OMAP44XX_GPMC_BASE 0x50000000 + +-/* DMM */ +-#define OMAP44XX_DMM_BASE 0x4E000000 +-#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40) +-#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) +-#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 +-#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) ++ + /* + * Hardware Register Details + */ +@@ -137,6 +132,17 @@ struct s32ktimer { + /* Temporary SRAM stack used while low level init is done */ + #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END + ++#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START ++ ++/* ++ * SRAM scratch space entries ++ */ ++ ++/* Boot parameter passed from SPL to U-Boot */ ++#define OMAP4_SRAM_SCRATCH_EMIF_SIZE SRAM_SCRATCH_SPACE_ADDR ++#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0x8) ++#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0xC) ++ + /* Silicon revisions */ + #define OMAP4430_SILICON_ID_INVALID 0 + #define OMAP4430_ES1_0 1 +diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h +index 4beff42..211d3b8 100644 +--- a/arch/arm/include/asm/arch-omap4/sys_proto.h ++++ b/arch/arm/include/asm/arch-omap4/sys_proto.h +@@ -44,6 +44,7 @@ void bypass_dpll(u32 base); + void freq_update_core(void); + u32 get_syc_clk_freq(void); + u32 omap4_ddr_clk(void); ++void cancel_out(u32 *num, u32 *den, u32 den_limit); + void sdram_init(void); + u32 omap4_revision(void); + +diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h +index 49daa85..9f2616c 100644 +--- a/arch/arm/include/asm/omap_common.h ++++ b/arch/arm/include/asm/omap_common.h +@@ -51,6 +51,27 @@ + (addr));\ + } while (0); + ++/* find log2 of number n - rounded up */ ++static inline u32 log_2_n_round_up(u32 n) ++{ ++ u32 clz; ++ /* count leading zeros */ ++ asm volatile ("CLZ %0, %1" : "=r" (clz) : "r" (n)); ++ if (n & (n - 1)) ++ return 31 - clz; /* power of 2 */ ++ else ++ return 32 - clz; /* not power of 2 - round up */ ++} ++ ++/* find log2 of number n - rounded down */ ++static inline u32 log_2_n_round_down(u32 n) ++{ ++ u32 clz; ++ /* count leading zeros */ ++ asm volatile ("CLZ %0, %1" : "=r" (clz) : "r" (n)); ++ return 31 - clz; ++} ++ + /* Boot device */ + #define BOOT_DEVICE_NONE 0 + #define BOOT_DEVICE_XIP 1 +diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h +index 07d45a0..c29b184 100644 +--- a/include/configs/omap4_sdp4430.h ++++ b/include/configs/omap4_sdp4430.h +@@ -245,6 +245,11 @@ + /* Defines for Clock init */ + #define CONFIG_SYS_OMAP4_ABE_SYSCK + ++/* Defines for SDRAM init */ ++#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS ++#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 ++#endif ++ + /* Defines for SPL */ + #define CONFIG_SPL + #define CONFIG_SYS_SPL_TEXT_BASE 0x40304360 +diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile +index 1f25f77..d89dea0 100644 +--- a/spl/board/ti/sdp4430/Makefile ++++ b/spl/board/ti/sdp4430/Makefile +@@ -81,6 +81,10 @@ SOBJS += start.o + COBJS += syslib.o + + # omap-common ++$(obj)utils.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/utils.c $@ ++ + $(obj)timer.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@ +@@ -94,7 +98,7 @@ $(obj)spl-omap.c: + @ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@ + + SOBJS += reset.o +-COBJS += timer.o spl-omap.o ++COBJS += utils.o timer.o spl-omap.o + + $(OBJTREE)/MLO: $(splobj)u-boot-spl.bin + $(OBJTREE)/tools/mkimage -T omapimage \ +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0018-omap4-automatic-sdram-detection.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0018-omap4-automatic-sdram-detection.patch new file mode 100644 index 0000000000..c7bda75fc8 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0018-omap4-automatic-sdram-detection.patch @@ -0,0 +1,304 @@ +From e7c2c0d5c3834c6ddfc826f1ae9f07406265afcf Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Fri, 25 Feb 2011 18:07:13 +0530 +Subject: [PATCH 18/22] omap4: automatic sdram detection + +Identify SDRAM devices connected to EMIF automatically: +LPDDR2 devices have some Mode Registers that provide details +about the device such as the type, density, bus width +etc. EMIF has the capability to read these registers. If there +are not devices connected to a given chip-select reading mode +registers will return junk values. After reading as many such +registers as possible and matching with expected ranges of +values the driver can identify if there is a device connected +to the respective CS. If we identify that a device is connected +the values read give us complete details about the device. + +This along with the base AC timings specified by JESD209-2 +allows us to do a complete automatic initialization of +SDRAM that works on all boards. + +Please note that the default AC timings specified by JESD209-2 +will be safe for all devices but not necessarily optimal. However, +for the Elpida devices used on Panda and SDP the default timings +are both safe and optimal. + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/omap4/emif.c | 177 +++++++++++++++++++++++++++++- + arch/arm/cpu/armv7/omap4/sdram_elpida.c | 9 +- + include/configs/omap4_sdp4430.h | 1 + + 3 files changed, 176 insertions(+), 11 deletions(-) + +diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c +index 1bdb1d2..006d065 100644 +--- a/arch/arm/cpu/armv7/omap4/emif.c ++++ b/arch/arm/cpu/armv7/omap4/emif.c +@@ -165,7 +165,8 @@ static const struct lpddr2_min_tck min_tck_jedec = { + .tFAW = 8 + }; + +-static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = { ++static const struct lpddr2_ac_timings const* ++ jedec_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_jedec_200_mhz, + &timings_jedec_333_mhz, + &timings_jedec_400_mhz +@@ -779,6 +780,146 @@ void emif_reset_phy(u32 base) + writel(iodft, &emif->emif_iodft_tlgc); + } + ++#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION ++static void display_sdram_details(u32 emif_nr, u32 cs, ++ struct lpddr2_device_details *device) ++{ ++ const char *mfg_str; ++ const char *type_str; ++ char density_str[10]; ++ u32 density; ++ ++ debug("EMIF%d CS%d\t", emif_nr, cs); ++ ++ if (!device) { ++ debug("None\n"); ++ return; ++ } ++ ++ mfg_str = get_lpddr2_manufacturer(device->manufacturer); ++ type_str = get_lpddr2_type(device->type); ++ ++ density = lpddr2_density_2_size_in_mbytes[device->density]; ++ if ((density / 1024 * 1024) == density) { ++ density /= 1024; ++ sprintf(density_str, "%d GB", density); ++ } else ++ sprintf(density_str, "%d MB", density); ++ if (mfg_str && type_str) ++ debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); ++} ++ ++static u8 is_lpddr2_sdram_present(u32 base, u32 cs, ++ struct lpddr2_device_details *lpddr2_device) ++{ ++ u32 mr = 0, temp; ++ ++ mr = get_mr(base, cs, LPDDR2_MR0); ++ if (mr > 0xFF) { ++ /* Mode register value bigger than 8 bit */ ++ return 0; ++ } ++ ++ temp = get_bit_field(mr, LPDDR2_MR0_DI_SHIFT, LPDDR2_MR0_DI_MASK); ++ if (temp) { ++ /* Not SDRAM */ ++ return 0; ++ } ++ temp = get_bit_field(mr, LPDDR2_MR0_DNVI_SHIFT, LPDDR2_MR0_DNVI_MASK); ++ ++ if (temp) { ++ /* DNV supported - But DNV is only supported for NVM */ ++ return 0; ++ } ++ ++ mr = get_mr(base, cs, LPDDR2_MR4); ++ if (mr > 0xFF) { ++ /* Mode register value bigger than 8 bit */ ++ return 0; ++ } ++ ++ mr = get_mr(base, cs, LPDDR2_MR5); ++ if (mr >= 0xFF) { ++ /* Mode register value bigger than 8 bit */ ++ return 0; ++ } ++ ++ if (!get_lpddr2_manufacturer(mr)) { ++ /* Manufacturer not identified */ ++ return 0; ++ } ++ lpddr2_device->manufacturer = mr; ++ ++ mr = get_mr(base, cs, LPDDR2_MR6); ++ if (mr >= 0xFF) { ++ /* Mode register value bigger than 8 bit */ ++ return 0; ++ } ++ ++ mr = get_mr(base, cs, LPDDR2_MR7); ++ if (mr >= 0xFF) { ++ /* Mode register value bigger than 8 bit */ ++ return 0; ++ } ++ ++ mr = get_mr(base, cs, LPDDR2_MR8); ++ if (mr >= 0xFF) { ++ /* Mode register value bigger than 8 bit */ ++ return 0; ++ } ++ ++ temp = get_bit_field(mr, MR8_TYPE_SHIFT, MR8_TYPE_MASK); ++ if (!get_lpddr2_type(temp)) { ++ /* Not SDRAM */ ++ return 0; ++ } ++ lpddr2_device->type = temp; ++ ++ temp = get_bit_field(mr, MR8_DENSITY_SHIFT, MR8_DENSITY_MASK); ++ if (temp > LPDDR2_DENSITY_32Gb) { ++ /* Density not supported */ ++ return 0; ++ } ++ lpddr2_device->density = temp; ++ ++ temp = get_bit_field(mr, MR8_IO_WIDTH_SHIFT, MR8_IO_WIDTH_MASK); ++ if (!get_lpddr2_io_width(temp)) { ++ /* IO width unsupported value */ ++ return 0; ++ } ++ lpddr2_device->io_width = temp; ++ ++ /* ++ * If all the above tests pass we should ++ * have a device on this chip-select ++ */ ++ return 1; ++} ++ ++static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs, ++ struct lpddr2_device_details *lpddr2_dev_details) ++{ ++ u32 phy; ++ struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ++ ++ if (!lpddr2_dev_details) ++ return NULL; ++ ++ /* Do the minimum init for mode register accesses */ ++ if (!running_from_sdram()) { ++ phy = get_ddr_phy_ctrl_1(get_syc_clk_freq() / 2, RL_BOOT); ++ writel(phy, &emif->emif_ddr_phy_ctrl_1); ++ } ++ ++ if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) ++ return NULL; ++ ++ display_sdram_details(emif_num(base), cs, lpddr2_dev_details); ++ ++ return lpddr2_dev_details; ++} ++#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ ++ + static void do_lpddr2_init(u32 base, u32 cs) + { + u32 mr_addr; +@@ -862,9 +1003,7 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs) + + static void do_sdram_init(u32 base) + { +- struct emif_device_details dev_details; + const struct emif_regs *regs; +- + u32 in_sdram, emif_nr; + + in_sdram = running_from_sdram(); +@@ -872,6 +1011,7 @@ static void do_sdram_init(u32 base) + + #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + const struct emif_regs *tmp_regs; ++ + emif_get_reg_dump(®s, &tmp_regs); + regs = (emif_nr == 1) ? regs : tmp_regs; + #else +@@ -879,23 +1019,48 @@ static void do_sdram_init(u32 base) + * The user has not provided the register values. We need to + * calculate it based on the timings and the DDR frequency + */ ++ struct emif_device_details dev_details = { NULL, NULL }; ++ struct emif_regs calculated_regs; + ++#if !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \ ++ !defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS) ++ ++ /* We need some input about the devices from the user */ + const struct emif_device_details *dev_details_user_provided; + const struct emif_device_details *tmp_details; +- struct emif_regs calculated_regs; + +- /* We need some input about the devices from the user */ + emif_get_device_details(&dev_details_user_provided, &tmp_details); + dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided + : tmp_details; + if (!dev_details_user_provided) + return; ++#endif + ++#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION ++ struct lpddr2_device_details cs0_dev_details, cs1_dev_details; ++ ++ /* Automatically find the device details */ ++ if (!in_sdram) { ++ dev_details.cs0_device_details = ++ get_lpddr2_details(base, CS0, &cs0_dev_details); ++ dev_details.cs1_device_details = ++ get_lpddr2_details(base, CS1, &cs1_dev_details); ++ /* ++ * Reset the PHY - if there is nothing connected on any ++ * of the chip selects(typically CS1) mode register reads ++ * will mess up with the PHY state and subsequent ++ * initialization won't work. PHY reset brings back PHY to ++ * a good state. ++ */ ++ emif_reset_phy(base); ++ } ++#else + dev_details.cs0_device_details = + dev_details_user_provided->cs0_device_details; + dev_details.cs1_device_details = + dev_details_user_provided->cs1_device_details; + ++#endif + /* Return if no devices on this EMIF */ + if (!dev_details.cs0_device_details && + !dev_details.cs1_device_details) { +diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c +index e7d2bd5..8dfe6f9 100644 +--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c ++++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c +@@ -86,10 +86,8 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_3 = 0x80640300 + }; + +-void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs, +- const struct emif_regs **emif2_regs) +- +-#else ++#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \ ++ !defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS) + + static const struct lpddr2_ac_timings timings_elpida_400_mhz = { + .max_freq = 400000000, +@@ -245,7 +243,8 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); + +-#else ++#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \ ++ !defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS) + + static void emif_get_device_details_sdp( + const struct emif_device_details **emif1_details, +diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h +index c29b184..a4332b7 100644 +--- a/include/configs/omap4_sdp4430.h ++++ b/include/configs/omap4_sdp4430.h +@@ -247,6 +247,7 @@ + + /* Defines for SDRAM init */ + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS ++#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 + #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 + #endif + +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0019-armv7-embed-u-boot-size-within-u-boot-for-use-from-S.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0019-armv7-embed-u-boot-size-within-u-boot-for-use-from-S.patch new file mode 100644 index 0000000000..eda823cf53 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0019-armv7-embed-u-boot-size-within-u-boot-for-use-from-S.patch @@ -0,0 +1,48 @@ +From fe036a666363c51905cdf9a88d3c21f5e702b35c Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Sat, 26 Feb 2011 17:15:11 +0530 +Subject: [PATCH 19/22] armv7: embed u-boot size within u-boot for use from SPL + +Embed the u-boot flash image size at a known offset from the +start of u-boot so that SPL can use it while loading u-boot +from a non-XIP media. + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/start.S | 6 +++++- + spl/board/ti/spl-omap.lds | 1 + + 2 files changed, 6 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S +index f5f08d9..1cbd128 100644 +--- a/arch/arm/cpu/armv7/start.S ++++ b/arch/arm/cpu/armv7/start.S +@@ -64,8 +64,12 @@ _pad: .word 0x12345678 /* now 16*4=64 */ + + .global _end_vect + _end_vect: ++.global _u_boot_size ++_u_boot_size: ++ .word 0xDEADBEEF ++ .word __flash_image_end - _start + +- .balignl 16,0xdeadbeef ++.balignl 16,0xdeadbeef + /************************************************************************* + * + * Startup Code (reset vector) +diff --git a/spl/board/ti/spl-omap.lds b/spl/board/ti/spl-omap.lds +index 27b5295..64eb4c9 100644 +--- a/spl/board/ti/spl-omap.lds ++++ b/spl/board/ti/spl-omap.lds +@@ -50,6 +50,7 @@ SECTIONS + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + __image_copy_end = .; ++ __flash_image_end = .; + + .bss : + { +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0020-omap-add-MMC-support-to-SPL.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0020-omap-add-MMC-support-to-SPL.patch new file mode 100644 index 0000000000..8d5a437f8b --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0020-omap-add-MMC-support-to-SPL.patch @@ -0,0 +1,245 @@ +From 8ead31f9eee7c63b1679c387af98b834f2123b6d Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 18:02:44 +0530 +Subject: [PATCH 20/22] omap: add MMC support to SPL + +Signed-off-by: Aneesh V +--- + arch/arm/cpu/armv7/start.S | 1 + + arch/arm/include/asm/omap_common.h | 4 + + include/configs/omap4_sdp4430.h | 7 ++- + spl/board/ti/sdp4430/Makefile | 35 +++++++++++ + spl/board/ti/spl-omap.c | 112 +++++++++++++++++++++++++++++++++++- + 5 files changed, 156 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S +index 1cbd128..927476c 100644 +--- a/arch/arm/cpu/armv7/start.S ++++ b/arch/arm/cpu/armv7/start.S +@@ -64,6 +64,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */ + + .global _end_vect + _end_vect: ++/* This label should be at the same location for SPL and U-Boot */ + .global _u_boot_size + _u_boot_size: + .word 0xDEADBEEF +diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h +index 9f2616c..c2efa7c 100644 +--- a/arch/arm/include/asm/omap_common.h ++++ b/arch/arm/include/asm/omap_common.h +@@ -99,4 +99,8 @@ u32 omap_boot_device(void); + u32 omap_boot_mode(void); + void preloader_console_init(void); + ++/* symbols from start.S */ ++extern u32 _u_boot_size; ++extern u32 _start; ++ + #endif /* _OMAP_COMMON_H_ */ +diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h +index a4332b7..0ed474d 100644 +--- a/include/configs/omap4_sdp4430.h ++++ b/include/configs/omap4_sdp4430.h +@@ -257,7 +257,10 @@ + #define CONFIG_SYS_SPL_MAX_SIZE 0x7800 /* 30 K */ + #define CONFIG_SYS_SPL_STACK LOW_LEVEL_SRAM_STACK + +-#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 +-#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ ++#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ ++#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ ++ ++#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 ++#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + + #endif /* __CONFIG_H */ +diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile +index d89dea0..18c5b8e 100644 +--- a/spl/board/ti/sdp4430/Makefile ++++ b/spl/board/ti/sdp4430/Makefile +@@ -68,6 +68,41 @@ $(obj)ctype.c: + COBJS += serial.o ns16550.o string.o vsprintf.o console.o stdio.o + COBJS += ctype.o eabi_compat.o div64.o + ++ ++# mmc ++$(obj)mmc.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/mmc/mmc.c $@ ++ ++$(obj)omap_hsmmc.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/mmc/omap_hsmmc.c $@ ++ ++$(obj)omap24xx_i2c.c: $(obj)omap24xx_i2c.h ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.c $@ ++ ++$(obj)omap24xx_i2c.h: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.h $@ ++ ++$(obj)time.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/time.c $@ ++ ++$(obj)part.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/disk/part.c $@ ++ ++$(obj)part_dos.c: $(obj)part_dos.h ++ @rm -f $@ ++ @ln -s $(TOPDIR)/disk/part_dos.c $@ ++ ++$(obj)part_dos.h: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/disk/part_dos.h $@ ++ ++COBJS += omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o + # armv7 + $(obj)start.S: + @rm -f $@ +diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c +index 57ddb7d..b64eac9 100644 +--- a/spl/board/ti/spl-omap.c ++++ b/spl/board/ti/spl-omap.c +@@ -28,24 +28,134 @@ + #include + #include + #include ++#include + #include ++#include ++#include ++#include + + /* Define global data structure pointer to it*/ + gd_t gdata __attribute__ ((section(".data"))); + bd_t bdata __attribute__ ((section(".data"))); + gd_t *gd = &gdata; + ++typedef void (*u_boot_entry_t)(void)__attribute__ ((noreturn)); ++ + void board_init_f(ulong dummy) + { + relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE); + } + +-void board_init_r(gd_t *id, ulong dummy) ++inline void hang(void) + { ++ puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; + } + ++#ifdef CONFIG_GENERIC_MMC ++int board_mmc_init(bd_t *bis) ++{ ++ omap_mmc_init(0); ++ omap_mmc_init(1); ++ return 0; ++} ++#endif ++ ++static void mmc_load_uboot_raw(struct mmc *mmc, u32 mmc_dev) ++{ ++ u32 u_boot_size_sectors, err; ++ u32 *u_boot_size = (u32 *)(CONFIG_SYS_TEXT_BASE + ++ (u32) &_u_boot_size - (u32) &_start); ++ ++ /* read one sector first to find u-boot size */ ++ err = mmc->block_dev.block_read(mmc_dev, ++ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1, ++ (void *)CONFIG_SYS_TEXT_BASE); ++ if (err <= 0) ++ goto end; ++ ++ if (*u_boot_size != 0xDEADBEEF) { ++ err = 0xDEADBEEF; ++ goto end; ++ } ++ ++ /* move to the next word that has size */ ++ u_boot_size++; ++ ++ /* ++ * convert size to sectors - round down is fine because we have ++ * already read 1 sector ++ */ ++ u_boot_size_sectors = *u_boot_size/MMCSD_SECTOR_SIZE; ++ debug("spl: u-boot raw sectors - %d\n", u_boot_size_sectors + 1); ++ /* read one sector first to find u-boot size */ ++ err = mmc->block_dev.block_read(mmc_dev, ++ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + 1, ++ u_boot_size_sectors, ++ (void *)(CONFIG_SYS_TEXT_BASE + MMCSD_SECTOR_SIZE)); ++end: ++ if (err <= 0) { ++ printf("spl: mmc blk read err - %d\n", err); ++ hang(); ++ } ++} ++ ++static void mmc_load_uboot(u32 mmc_dev) ++{ ++ struct mmc *mmc; ++ int err; ++ u32 boot_mode; ++ ++ mmc_initialize(gd->bd); ++ mmc = find_mmc_device(mmc_dev); ++ if (!mmc) { ++ puts("spl: mmc device not found!!\n"); ++ hang(); ++ } ++ ++ err = mmc_init(mmc); ++ if (err) { ++ printf("spl: mmc init failed: mmc_dev - %d err - %d\n", ++ mmc_dev, err); ++ hang(); ++ } ++ ++ boot_mode = omap_boot_mode(); ++ if (boot_mode == MMCSD_MODE_RAW) ++ mmc_load_uboot_raw(mmc, mmc_dev); ++ else { ++ puts("spl: wrong MMC boot mode\n"); ++ hang(); ++ } ++} ++ ++void board_init_r(gd_t *id, ulong dummy) ++{ ++ u32 boot_device; ++ u_boot_entry_t u_boot_entry = (u_boot_entry_t) CONFIG_SYS_TEXT_BASE; ++ ++ timer_init(); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ++ boot_device = omap_boot_device(); ++ switch (boot_device) { ++ case BOOT_DEVICE_MMC1: ++ case BOOT_DEVICE_MMC2: ++ mmc_load_uboot(boot_device - BOOT_DEVICE_MMC1); ++ break; ++ default: ++ printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device); ++ hang(); ++ break; ++ } ++ ++ /* ++ * Jump to u-boot with magic number as input to indicate that it ++ * was loaded by SPL ++ */ ++ u_boot_entry(); ++} ++ + void preloader_console_init(void) + { + gd->bd = &bdata; +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0021-omap-spl-add-FAT-support-over-MMC.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0021-omap-spl-add-FAT-support-over-MMC.patch new file mode 100644 index 0000000000..4213fe26a1 --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0021-omap-spl-add-FAT-support-over-MMC.patch @@ -0,0 +1,93 @@ +From 2b9e1ea9f94b94388345a1b74d2ecf6b4f9be1c1 Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Thu, 17 Feb 2011 18:07:08 +0530 +Subject: [PATCH 21/22] omap: spl: add FAT support over MMC + +Signed-off-by: Aneesh V +--- + include/configs/omap4_sdp4430.h | 1 + + spl/board/ti/sdp4430/Makefile | 8 ++++++++ + spl/board/ti/spl-omap.c | 22 ++++++++++++++++++++++ + 3 files changed, 31 insertions(+), 0 deletions(-) + +diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h +index 0ed474d..dcc9e39 100644 +--- a/include/configs/omap4_sdp4430.h ++++ b/include/configs/omap4_sdp4430.h +@@ -259,6 +259,7 @@ + + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ + #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ ++#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 + + #define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 + #define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile +index 18c5b8e..8310db9 100644 +--- a/spl/board/ti/sdp4430/Makefile ++++ b/spl/board/ti/sdp4430/Makefile +@@ -103,6 +103,14 @@ $(obj)part_dos.h: + @ln -s $(TOPDIR)/disk/part_dos.h $@ + + COBJS += omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o ++ ++# fat ++$(obj)fat.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/fs/fat/fat.c $@ ++ ++COBJS += fat.o ++ + # armv7 + $(obj)start.S: + @rm -f $@ +diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c +index b64eac9..3612434 100644 +--- a/spl/board/ti/spl-omap.c ++++ b/spl/board/ti/spl-omap.c +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -101,6 +102,25 @@ end: + } + } + ++static void mmc_load_uboot_fat(struct mmc *mmc) ++{ ++ s32 err; ++ ++ err = fat_register_device(&mmc->block_dev, ++ CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION); ++ if (err) { ++ printf("spl: fat register err - %d\n", err); ++ hang(); ++ } ++ ++ err = file_fat_read("u-boot.bin", (u8 *)CONFIG_SYS_TEXT_BASE, 0); ++ ++ if (err <= 0) { ++ printf("spl: error reading u-boot.bin - %d\n", err); ++ hang(); ++ } ++} ++ + static void mmc_load_uboot(u32 mmc_dev) + { + struct mmc *mmc; +@@ -124,6 +144,8 @@ static void mmc_load_uboot(u32 mmc_dev) + boot_mode = omap_boot_mode(); + if (boot_mode == MMCSD_MODE_RAW) + mmc_load_uboot_raw(mmc, mmc_dev); ++ else if (boot_mode == MMCSD_MODE_FAT) ++ mmc_load_uboot_fat(mmc); + else { + puts("spl: wrong MMC boot mode\n"); + hang(); +-- +1.7.2.3 + diff --git a/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0022-omap4-add-spl-support-for-OMAP4-Panda.patch b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0022-omap4-add-spl-support-for-OMAP4-Panda.patch new file mode 100644 index 0000000000..262599afce --- /dev/null +++ b/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0022-omap4-add-spl-support-for-OMAP4-Panda.patch @@ -0,0 +1,303 @@ +From 1f516cf960c96e77f722706726f273cf3f117d9c Mon Sep 17 00:00:00 2001 +From: Aneesh V +Date: Fri, 18 Feb 2011 03:24:01 +0530 +Subject: [PATCH 22/22] omap4: add spl support for OMAP4 Panda + +Signed-off-by: Aneesh V +--- + arch/arm/include/asm/arch-omap4/emif.h | 10 +- + include/configs/omap4_panda.h | 24 ++++ + spl/board/ti/panda/Makefile | 219 ++++++++++++++++++++++++++++++++ + 3 files changed, 248 insertions(+), 5 deletions(-) + create mode 100644 spl/board/ti/panda/Makefile + +diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h +index 8cc3230..b95e545 100644 +--- a/arch/arm/include/asm/arch-omap4/emif.h ++++ b/arch/arm/include/asm/arch-omap4/emif.h +@@ -520,11 +520,11 @@ + + /* Trap for invalid TILER PAT entries */ + #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ +- (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ +- (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ +- (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ +- (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ +- (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) ++ (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ ++ (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ ++ (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ ++ (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ ++ (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) + + + /* Reg mapping structure */ +diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h +index 2b03b0f..b389035 100644 +--- a/include/configs/omap4_panda.h ++++ b/include/configs/omap4_panda.h +@@ -117,7 +117,9 @@ + + /* USB device configuration */ + #define CONFIG_USB_DEVICE 1 ++#ifndef CONFIG_PRELOADER + #define CONFIG_USB_TTY 1 ++#endif + #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + + /* Flash */ +@@ -234,4 +236,26 @@ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + ++/* Defines for Clock init */ ++#define CONFIG_SYS_OMAP4_ABE_SYSCK ++ ++/* Defines for SDRAM init */ ++#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS ++#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 ++#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 ++#endif ++ ++/* Defines for SPL */ ++#define CONFIG_SPL ++#define CONFIG_SYS_SPL_TEXT_BASE 0x40304360 ++#define CONFIG_SYS_SPL_MAX_SIZE 0x7800 /* 30 K */ ++#define CONFIG_SYS_SPL_STACK LOW_LEVEL_SRAM_STACK ++ ++#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ ++#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ ++#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 ++ ++#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 ++#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ ++ + #endif /* __CONFIG_H */ +diff --git a/spl/board/ti/panda/Makefile b/spl/board/ti/panda/Makefile +new file mode 100644 +index 0000000..8310db9 +--- /dev/null ++++ b/spl/board/ti/panda/Makefile +@@ -0,0 +1,219 @@ ++# ++# (C) Copyright 2006-2007 ++# Stefan Roese, DENX Software Engineering, sr@denx.de. ++# ++# (C) Copyright 2008 ++# Guennadi Liakhovetki, DENX Software Engineering, ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++splobj := $(OBJTREE)/spl/ ++include $(TOPDIR)/config.mk ++SOBJS = ++COBJS = ++ ++# serial console ++$(obj)eabi_compat.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/lib/eabi_compat.c $@ ++ ++$(obj)string.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/string.c $@ ++ ++$(obj)vsprintf.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/vsprintf.c $@ ++ ++$(obj)console.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/common/console.c $@ ++ ++$(obj)stdio.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/common/stdio.c $@ ++ ++$(obj)serial.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/serial/serial.c $@ ++ ++$(obj)ns16550.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/serial/ns16550.c $@ ++ ++$(obj)div64.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/div64.c $@ ++ ++$(obj)ctype.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/ctype.c $@ ++ ++COBJS += serial.o ns16550.o string.o vsprintf.o console.o stdio.o ++COBJS += ctype.o eabi_compat.o div64.o ++ ++ ++# mmc ++$(obj)mmc.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/mmc/mmc.c $@ ++ ++$(obj)omap_hsmmc.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/mmc/omap_hsmmc.c $@ ++ ++$(obj)omap24xx_i2c.c: $(obj)omap24xx_i2c.h ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.c $@ ++ ++$(obj)omap24xx_i2c.h: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.h $@ ++ ++$(obj)time.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/lib/time.c $@ ++ ++$(obj)part.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/disk/part.c $@ ++ ++$(obj)part_dos.c: $(obj)part_dos.h ++ @rm -f $@ ++ @ln -s $(TOPDIR)/disk/part_dos.c $@ ++ ++$(obj)part_dos.h: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/disk/part_dos.h $@ ++ ++COBJS += omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o ++ ++# fat ++$(obj)fat.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/fs/fat/fat.c $@ ++ ++COBJS += fat.o ++ ++# armv7 ++$(obj)start.S: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@ ++ ++$(obj)syslib.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@ ++ ++SOBJS += start.o ++COBJS += syslib.o ++ ++# omap-common ++$(obj)utils.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/utils.c $@ ++ ++$(obj)timer.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@ ++ ++$(obj)reset.S: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/reset.S $@ ++ ++$(obj)spl-omap.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@ ++ ++SOBJS += reset.o ++COBJS += utils.o timer.o spl-omap.o ++ ++$(OBJTREE)/MLO: $(splobj)u-boot-spl.bin ++ $(OBJTREE)/tools/mkimage -T omapimage \ ++ -a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@ ++ ++LDSCRIPT_SOURCE = $(TOPDIR)/spl/board/ti/spl-omap.lds ++ ++# omap4 ++$(obj)lowlevel_init.S: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/lowlevel_init.S $@ ++ ++$(obj)omap4_mux_data.h: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/omap4_mux_data.h $@ ++ ++$(obj)board.c:$(obj)omap4_mux_data.h ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@ ++ ++$(obj)emif.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/emif.c $@ ++ ++$(obj)sdram_elpida.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/sdram_elpida.c $@ ++ ++$(obj)clocks.c: ++ @rm -f $@ ++ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@ ++ ++SOBJS += lowlevel_init.o ++COBJS += board.o clocks.o emif.o sdram_elpida.o ++ ++# rules ++LDPPFLAGS += -include $(TOPDIR)/include/config.h ++LDSCRIPT = $(splobj)u-boot-spl-generated.lds ++$(LDSCRIPT): $(LDSCRIPT_SOURCE) ++ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ ++LDFLAGS = -Bstatic -T $(LDSCRIPT) \ ++ $(PLATFORM_LDFLAGS) --gc-sections ++AFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 ++CFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 -ffunction-sections \ ++ -fdata-sections -march=armv7-a -mthumb ++PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) \ ++ -print-libgcc-file-name`) -lgcc ++ ++$(obj)%.o: $(obj)%.S ++ $(CC) $(AFLAGS) -c -o $@ $< ++ ++$(obj)%.o: $(obj)%.c ++ $(CC) $(CFLAGS) -c -o $@ $< ++ ++SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) ++OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) ++__OBJS := $(SOBJS) $(COBJS) ++LNDIR := $(OBJTREE)/spl/board/$(BOARDDIR) ++ ++$(splobj)u-boot-spl.bin: $(splobj)u-boot-spl ++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ ++ ++$(splobj)u-boot-spl: $(OBJS) $(LDSCRIPT) ++ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ ++ $(PLATFORM_LIBGCC) \ ++ -Map $(splobj)u-boot-spl.map \ ++ -o $(splobj)u-boot-spl ++ ++ALL = $(OBJTREE)/MLO ++all: $(obj).depend $(ALL) ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend +-- +1.7.2.3 + diff --git a/packages/x11/app/setxkbmap/init.d/72_keyboard b/packages/x11/app/setxkbmap/init.d/72_keyboard index dc1c643800..5279e95762 100644 --- a/packages/x11/app/setxkbmap/init.d/72_keyboard +++ b/packages/x11/app/setxkbmap/init.d/72_keyboard @@ -22,11 +22,9 @@ # # runlevels: openelec -OPENELEC_SETTINGS="$HOME/.xbmc/userdata/addon_data/os.openelec.settings/settings.xml" - ( - if [ -f "$OPENELEC_SETTINGS" ]; then - X11_KEYMAP=`grep X11_KEYMAP $OPENELEC_SETTINGS | awk '{print $3 }' | sed -e "s,value=,," -e "s,\",,g"` + if [ -f /var/config/settings.conf ]; then + . /var/config/settings.conf progress "setup keyboard layout" diff --git a/packages/x11/driver/xf86-video-ati/patches/xf86-video-ati-6.14.0-01-fix_build_with_xorg-server-1.10.patch b/packages/x11/driver/xf86-video-ati/patches/xf86-video-ati-6.14.0-01-fix_build_with_xorg-server-1.10.patch new file mode 100644 index 0000000000..5b47bc05a3 --- /dev/null +++ b/packages/x11/driver/xf86-video-ati/patches/xf86-video-ati-6.14.0-01-fix_build_with_xorg-server-1.10.patch @@ -0,0 +1,33 @@ +From ecfdb209afe2aafc378baab8c511f5df7b000270 Mon Sep 17 00:00:00 2001 +From: Sedat Dilek +Date: Fri, 25 Feb 2011 20:48:14 +0000 +Subject: UMS: Fix build against xserver 1.10-rc3 + +This issue was introduced due to last minute backout of RandR-1.4 +in xserver 1.10-rc3. + +Switch to "#ifdef RANDR_14_INTERFACE" as suggested by Keith Packard. +See also . + +Note: +The ddx needs a rebuild as the X video driver ABI changed to version 10.0. + +Reported-by: Alex Deucher +CC: Keith Packard +Signed-off-by: Sedat Dilek +--- +diff --git a/src/radeon_output.c b/src/radeon_output.c +index 15cef06..ccde346 100644 +--- a/src/radeon_output.c ++++ b/src/radeon_output.c +@@ -1622,7 +1622,7 @@ radeon_set_mode_for_property(xf86OutputPtr output) + xf86CrtcPtr crtc = output->crtc; + + if (crtc->enabled) { +-#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0) ++#ifdef RANDR_14_INTERFACE + xf86CrtcSetRec crtc_set_rec; + + crtc_set_rec.flags = (XF86CrtcSetMode | +-- +cgit v0.8.3-6-g21f6 diff --git a/packages/x11/driver/xf86-video-nouveau/meta b/packages/x11/driver/xf86-video-nouveau/meta index db6f13934b..f4d94cce17 100644 --- a/packages/x11/driver/xf86-video-nouveau/meta +++ b/packages/x11/driver/xf86-video-nouveau/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="xf86-video-nouveau" -PKG_VERSION="20110222" +PKG_VERSION="20110312" PKG_REV="1" PKG_ARCH="i386 x86_64" PKG_LICENSE="OSS" diff --git a/packages/x11/lib/libX11/build b/packages/x11/lib/libX11/build index 0610fe5876..11b2aa087c 100755 --- a/packages/x11/lib/libX11/build +++ b/packages/x11/lib/libX11/build @@ -39,7 +39,7 @@ cd $PKG_BUILD --disable-static \ --enable-shared \ --disable-secure-rpc \ - --disable-loadable-i18n \ + --enable-loadable-i18n \ --enable-xthreads \ --disable-xcms \ --enable-xlocale \ diff --git a/packages/x11/lib/libX11/install b/packages/x11/lib/libX11/install index cda14143f6..c6c3b2fb1e 100755 --- a/packages/x11/lib/libX11/install +++ b/packages/x11/lib/libX11/install @@ -26,3 +26,35 @@ mkdir -p $INSTALL/usr/lib cp -P $PKG_BUILD/src/.libs/libX11*.so* $INSTALL/usr/lib rm -rf $INSTALL/usr/lib/libX11*.so*T +mkdir -p $INSTALL/usr/lib/X11 + cp -P $PKG_BUILD/src/xcms/Xcms.txt $INSTALL/usr/lib/X11 + +mkdir -p $INSTALL/usr/lib/X11/locale/common + cp -P $PKG_BUILD/modules/im/ximcp/.libs/ximcp.so* $INSTALL/usr/lib/X11/locale/common + rm -rf $INSTALL/usr/lib/X11/locale/common/ximcp.so*T + cp -P $PKG_BUILD/modules/lc/Utf8/.libs/xlcUTF8Load.so* $INSTALL/usr/lib/X11/locale/common + rm -rf $INSTALL/usr/lib/X11/locale/common/xlcUTF8Load.so*T + cp -P $PKG_BUILD/modules/lc/def/.libs/xlcDef.so* $INSTALL/usr/lib/X11/locale/common + rm -rf $INSTALL/usr/lib/X11/locale/common/xlcDef.so*T + cp -P $PKG_BUILD/modules/lc/gen/.libs/xlibi18n.so* $INSTALL/usr/lib/X11/locale/common + rm -rf $INSTALL/usr/lib/X11/locale/common/xlibi18n.so*T + cp -P $PKG_BUILD/modules/lc/xlocale/.libs/xlocale.so* $INSTALL/usr/lib/X11/locale/common + rm -rf $INSTALL/usr/lib/X11/locale/common/xlocale.so*T + cp -P $PKG_BUILD/modules/om/generic/.libs/xomGeneric.so* $INSTALL/usr/lib/X11/locale/common + rm -rf $INSTALL/usr/lib/X11/locale/common/xomGeneric.so*T + +mkdir -p $INSTALL/usr/share/X11/locale + cp $PKG_BUILD/src/XErrorDB $INSTALL/usr/share/X11/ + +mkdir -p $INSTALL/usr/share/X11/locale + cp $PKG_BUILD/nls/compose.dir $INSTALL/usr/share/X11/locale + cp $PKG_BUILD/nls/locale.alias $INSTALL/usr/share/X11/locale + cp $PKG_BUILD/nls/locale.dir $INSTALL/usr/share/X11/locale + + for i in `find $PKG_BUILD/nls/* -type d`; do + LOCALE=`basename $i` + mkdir -p $INSTALL/usr/share/X11/locale/$LOCALE + cp $PKG_BUILD/nls/$LOCALE/Compose $INSTALL/usr/share/X11/locale/$LOCALE + cp $PKG_BUILD/nls/$LOCALE/XI18N_OBJS $INSTALL/usr/share/X11/locale/$LOCALE + cp $PKG_BUILD/nls/$LOCALE/XLC_LOCALE $INSTALL/usr/share/X11/locale/$LOCALE + done diff --git a/packages/x11/lib/libXfixes/meta b/packages/x11/lib/libXfixes/meta index cf82ff1499..698c713cbd 100644 --- a/packages/x11/lib/libXfixes/meta +++ b/packages/x11/lib/libXfixes/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="libXfixes" -PKG_VERSION="4.0.5" +PKG_VERSION="5.0" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="OSS" diff --git a/packages/x11/lib/libXt/meta b/packages/x11/lib/libXt/meta index 08231b5dcb..0886c9c024 100644 --- a/packages/x11/lib/libXt/meta +++ b/packages/x11/lib/libXt/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="libXt" -PKG_VERSION="1.0.9" +PKG_VERSION="1.1.1" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="OSS" diff --git a/packages/x11/lib/pixman/build b/packages/x11/lib/pixman/build index f92e188ac0..6ad2fe3d5a 100755 --- a/packages/x11/lib/pixman/build +++ b/packages/x11/lib/pixman/build @@ -22,6 +22,17 @@ . config/options $1 +if [ "$TARGET_ARCH" = arm ]; then + if [ "$TARGET_FPU" = neon -o "$TARGET_FPU" = neon-fp16 ]; then + CFG_NEON="--enable-arm-neon" + else + CFG_NEON="--disable-arm-neon" + fi + ARCH_CONFIG="--disable-mmx --disable-sse2 --disable-vmx --enable-arm-simd $CFG_NEON" +elif [ "$TARGET_ARCH" = i386 -o "$TARGET_ARCH" = x86_64 ]; then + ARCH_CONFIG="--enable-mmx --enable-sse2 --disable-vmx --disable-arm-simd --disable-arm-neon" +fi + cd $PKG_BUILD ./configure --host=$TARGET_NAME \ --build=$HOST_NAME \ @@ -31,11 +42,7 @@ cd $PKG_BUILD --enable-shared \ --disable-static \ --disable-openmp \ - --enable-mmx \ - --enable-sse2 \ - --disable-vmx \ - --disable-arm-simd \ - --disable-arm-neon \ + $ARCH_CONFIG \ --enable-gcc-inline-asm \ --disable-timers \ --disable-gtk \ diff --git a/packages/x11/other/fontconfig/build b/packages/x11/other/fontconfig/build index 12aeeb36ea..570d39e1a9 100755 --- a/packages/x11/other/fontconfig/build +++ b/packages/x11/other/fontconfig/build @@ -22,6 +22,9 @@ . config/options $1 +# fontconfig dont build with LTO support on ARM + strip_lto + # ensure we dont use '-O3' optimization. CFLAGS=`echo $CFLAGS | sed -e "s|-O3|-O2|"` CXXFLAGS=`echo $CXXFLAGS | sed -e "s|-O3|-O2|"` diff --git a/packages/x11/proto/fixesproto/meta b/packages/x11/proto/fixesproto/meta index f6aa8084ef..74ff3c617e 100644 --- a/packages/x11/proto/fixesproto/meta +++ b/packages/x11/proto/fixesproto/meta @@ -19,7 +19,7 @@ ################################################################################ PKG_NAME="fixesproto" -PKG_VERSION="4.1.2" +PKG_VERSION="5.0" PKG_REV="1" PKG_ARCH="any" PKG_LICENSE="OSS" diff --git a/projects/ATV/linux/linux.i386.conf b/projects/ATV/linux/linux.i386.conf index d544fe3f7c..eae201c9bc 100644 --- a/projects/ATV/linux/linux.i386.conf +++ b/projects/ATV/linux/linux.i386.conf @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux/i386 2.6.38-rc6-ck2 Kernel Configuration +# Linux/i386 2.6.38-rc8 Kernel Configuration # # CONFIG_64BIT is not set CONFIG_X86_32=y @@ -402,17 +402,10 @@ CONFIG_EFI=y CONFIG_SECCOMP=y # CONFIG_CC_STACKPROTECTOR is not set # CONFIG_HZ_100 is not set -# CONFIG_HZ_250_NODEFAULT is not set -# CONFIG_HZ_300 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1500 is not set -# CONFIG_HZ_2000 is not set -# CONFIG_HZ_3000 is not set -# CONFIG_HZ_4000 is not set -# CONFIG_HZ_5000 is not set -# CONFIG_HZ_7500 is not set -# CONFIG_HZ_10000 is not set -CONFIG_HZ=1000 +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y # CONFIG_KEXEC is not set CONFIG_PHYSICAL_START=0x1000000 @@ -743,7 +736,7 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -942,7 +935,19 @@ CONFIG_USB_ZD1201=m # CONFIG_ADM8211 is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_MWL8K is not set -# CONFIG_ATH_COMMON is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K=m +CONFIG_ATH9K_RATE_CONTROL=y +CONFIG_ATH9K_HTC=m +CONFIG_AR9170_USB=m +CONFIG_AR9170_LEDS=y +# CONFIG_CARL9170 is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set CONFIG_HOSTAP=m @@ -1333,7 +1338,7 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # # Supported USB Adapters # -CONFIG_DVB_USB=m +CONFIG_DVB_USB=y # CONFIG_DVB_USB_DEBUG is not set # CONFIG_DVB_USB_A800 is not set CONFIG_DVB_USB_DIBUSB_MB=m @@ -2090,6 +2095,7 @@ CONFIG_MACH_NO_WESTBRIDGE=y # CONFIG_SPEAKUP is not set # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set # CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_HWSPINLOCK is not set # # Firmware Drivers diff --git a/projects/ATV/options b/projects/ATV/options index a3d822a6b9..fa368909e5 100644 --- a/projects/ATV/options +++ b/projects/ATV/options @@ -43,7 +43,31 @@ # athlon-fx amdfam10 barcelona # (Intel CPUs) atom core2 nocona # - TARGET_CPU="i686" + TARGET_CPU="core2" + ;; + + arm) + # TARGET_CPU: + # arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm7m arm7d + # arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710c + # arm7100 arm720 arm7500 arm7500fe arm7tdmi arm7tdmi-s arm710t + # arm720t arm740t strongarm strongarm110 strongarm1100 + # strongarm1110 arm8 arm810 arm9 arm9e arm920 arm920t arm922t + # arm946e-s arm966e-s arm968e-s arm926ej-s arm940t arm9tdmi + # arm10tdmi arm1020t arm1026ej-s arm10e arm1020e arm1022e + # arm1136j-s arm1136jf-s mpcore mpcorenovfp arm1156t2-s + # arm1176jz-s arm1176jzf-s cortex-a8 cortex-a9 cortex-r4 + # cortex-r4f cortex-m3 cortex-m1 xscale iwmmxt iwmmxt2 ep9312. + # + TARGET_CPU="cortex-a9" + + # TARGET_FPU: + # This specifies what floating point hardware (or hardware emulation) is + # available on the target. Permissible names are: + # fpa fpe2 fpe3 maverick vfp vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16 + # vfpv3xd vfpv3xd-fp16 neon neon-fp16 vfpv4 vfpv4-d16 fpv4-sp-d16 + # neon-vfpv4. + TARGET_FPU="neon" ;; esac @@ -53,6 +77,12 @@ # Project CFLAGS PROJECT_CFLAGS="" +# Bootloader to use (syslinux / u-boot) + BOOTLOADER="" + +# Configuration for u-boot + UBOOT_CONFIG="" + # Mediacenter to use (xbmc / xbmc-pvr / no) MEDIACENTER="xbmc-pvr" @@ -139,7 +169,7 @@ GRAPHIC_DRIVERS="nouveau" # use libdrm-master (latest git) instead latest released version - LIBDRM_MASTER="yes" + LIBDRM_MASTER="no" # use Mesa-master (latest git) instead latest released version MESA_MASTER="yes" diff --git a/projects/Generic/linux/linux.i386.conf b/projects/Generic/linux/linux.i386.conf index 72b28f82db..23130f3b62 100644 --- a/projects/Generic/linux/linux.i386.conf +++ b/projects/Generic/linux/linux.i386.conf @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux/i386 2.6.38-rc6-ck2 Kernel Configuration +# Linux/i386 2.6.38-rc8 Kernel Configuration # # CONFIG_64BIT is not set CONFIG_X86_32=y @@ -389,17 +389,10 @@ CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_SECCOMP=y CONFIG_CC_STACKPROTECTOR=y # CONFIG_HZ_100 is not set -# CONFIG_HZ_250_NODEFAULT is not set -# CONFIG_HZ_300 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1500 is not set -# CONFIG_HZ_2000 is not set -# CONFIG_HZ_3000 is not set -# CONFIG_HZ_4000 is not set -# CONFIG_HZ_5000 is not set -# CONFIG_HZ_7500 is not set -# CONFIG_HZ_10000 is not set -CONFIG_HZ=1000 +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set @@ -803,7 +796,7 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -1073,7 +1066,7 @@ CONFIG_ATH9K_HW=m CONFIG_ATH9K_COMMON=m CONFIG_ATH9K=m CONFIG_ATH9K_RATE_CONTROL=y -# CONFIG_ATH9K_HTC is not set +CONFIG_ATH9K_HTC=m CONFIG_AR9170_USB=m CONFIG_AR9170_LEDS=y # CONFIG_CARL9170 is not set @@ -1637,7 +1630,7 @@ CONFIG_DVB_BUDGET_CI=m # # Supported USB Adapters # -CONFIG_DVB_USB=m +CONFIG_DVB_USB=y # CONFIG_DVB_USB_DEBUG is not set # CONFIG_DVB_USB_A800 is not set CONFIG_DVB_USB_DIBUSB_MB=m @@ -2482,6 +2475,7 @@ CONFIG_MACH_NO_WESTBRIDGE=y # CONFIG_SPEAKUP is not set # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set # CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_HWSPINLOCK is not set # # Firmware Drivers diff --git a/projects/Generic/options b/projects/Generic/options index 84fed478f9..f4c183d30b 100644 --- a/projects/Generic/options +++ b/projects/Generic/options @@ -43,7 +43,31 @@ # athlon-fx amdfam10 barcelona # (Intel CPUs) atom core2 nocona # - TARGET_CPU="i686" + TARGET_CPU="core2" + ;; + + arm) + # TARGET_CPU: + # arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm7m arm7d + # arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710c + # arm7100 arm720 arm7500 arm7500fe arm7tdmi arm7tdmi-s arm710t + # arm720t arm740t strongarm strongarm110 strongarm1100 + # strongarm1110 arm8 arm810 arm9 arm9e arm920 arm920t arm922t + # arm946e-s arm966e-s arm968e-s arm926ej-s arm940t arm9tdmi + # arm10tdmi arm1020t arm1026ej-s arm10e arm1020e arm1022e + # arm1136j-s arm1136jf-s mpcore mpcorenovfp arm1156t2-s + # arm1176jz-s arm1176jzf-s cortex-a8 cortex-a9 cortex-r4 + # cortex-r4f cortex-m3 cortex-m1 xscale iwmmxt iwmmxt2 ep9312. + # + TARGET_CPU="cortex-a9" + + # TARGET_FPU: + # This specifies what floating point hardware (or hardware emulation) is + # available on the target. Permissible names are: + # fpa fpe2 fpe3 maverick vfp vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16 + # vfpv3xd vfpv3xd-fp16 neon neon-fp16 vfpv4 vfpv4-d16 fpv4-sp-d16 + # neon-vfpv4. + TARGET_FPU="neon" ;; esac @@ -53,6 +77,12 @@ # Project CFLAGS PROJECT_CFLAGS="-mmmx -msse -msse2 -mfpmath=sse" +# Bootloader to use (syslinux / u-boot) + BOOTLOADER="syslinux" + +# Configuration for u-boot + UBOOT_CONFIG="" + # Mediacenter to use (xbmc / xbmc-pvr / no) MEDIACENTER="xbmc-pvr" diff --git a/projects/ION/linux/linux.i386.conf b/projects/ION/linux/linux.i386.conf index 75fcba4968..5e27eb0aa5 100644 --- a/projects/ION/linux/linux.i386.conf +++ b/projects/ION/linux/linux.i386.conf @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux/i386 2.6.38-rc6-ck2 Kernel Configuration +# Linux/i386 2.6.38-rc8 Kernel Configuration # # CONFIG_64BIT is not set CONFIG_X86_32=y @@ -388,17 +388,10 @@ CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_SECCOMP=y CONFIG_CC_STACKPROTECTOR=y # CONFIG_HZ_100 is not set -# CONFIG_HZ_250_NODEFAULT is not set -# CONFIG_HZ_300 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1500 is not set -# CONFIG_HZ_2000 is not set -# CONFIG_HZ_3000 is not set -# CONFIG_HZ_4000 is not set -# CONFIG_HZ_5000 is not set -# CONFIG_HZ_7500 is not set -# CONFIG_HZ_10000 is not set -CONFIG_HZ=1000 +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set @@ -799,7 +792,7 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -1028,8 +1021,9 @@ CONFIG_ATH9K_HW=m CONFIG_ATH9K_COMMON=m CONFIG_ATH9K=m CONFIG_ATH9K_RATE_CONTROL=y -# CONFIG_ATH9K_HTC is not set -# CONFIG_AR9170_USB is not set +CONFIG_ATH9K_HTC=m +CONFIG_AR9170_USB=m +CONFIG_AR9170_LEDS=y # CONFIG_CARL9170 is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set @@ -1539,7 +1533,7 @@ CONFIG_DVB_BUDGET_CI=m # # Supported USB Adapters # -CONFIG_DVB_USB=m +CONFIG_DVB_USB=y # CONFIG_DVB_USB_DEBUG is not set # CONFIG_DVB_USB_A800 is not set CONFIG_DVB_USB_DIBUSB_MB=m @@ -2346,6 +2340,7 @@ CONFIG_MACH_NO_WESTBRIDGE=y # CONFIG_SPEAKUP is not set # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set # CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_HWSPINLOCK is not set # # Firmware Drivers diff --git a/projects/ION/linux/linux.x86_64.conf b/projects/ION/linux/linux.x86_64.conf index 5c59fe3b07..09ce547ec6 100644 --- a/projects/ION/linux/linux.x86_64.conf +++ b/projects/ION/linux/linux.x86_64.conf @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux/x86_64 2.6.38-rc6-ck2 Kernel Configuration +# Linux/x86_64 2.6.38-rc8 Kernel Configuration # CONFIG_64BIT=y # CONFIG_X86_32 is not set @@ -352,17 +352,10 @@ CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_SECCOMP=y CONFIG_CC_STACKPROTECTOR=y # CONFIG_HZ_100 is not set -# CONFIG_HZ_250_NODEFAULT is not set -# CONFIG_HZ_300 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1500 is not set -# CONFIG_HZ_2000 is not set -# CONFIG_HZ_3000 is not set -# CONFIG_HZ_4000 is not set -# CONFIG_HZ_5000 is not set -# CONFIG_HZ_7500 is not set -# CONFIG_HZ_10000 is not set -CONFIG_HZ=1000 +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set @@ -748,7 +741,7 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -976,8 +969,9 @@ CONFIG_ATH9K_HW=m CONFIG_ATH9K_COMMON=m CONFIG_ATH9K=m CONFIG_ATH9K_RATE_CONTROL=y -# CONFIG_ATH9K_HTC is not set -# CONFIG_AR9170_USB is not set +CONFIG_ATH9K_HTC=m +CONFIG_AR9170_USB=m +CONFIG_AR9170_LEDS=y # CONFIG_CARL9170 is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set @@ -1481,7 +1475,7 @@ CONFIG_DVB_BUDGET_CI=m # # Supported USB Adapters # -CONFIG_DVB_USB=m +CONFIG_DVB_USB=y # CONFIG_DVB_USB_DEBUG is not set # CONFIG_DVB_USB_A800 is not set CONFIG_DVB_USB_DIBUSB_MB=m @@ -2289,6 +2283,7 @@ CONFIG_MACH_NO_WESTBRIDGE=y # CONFIG_SPEAKUP is not set # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set # CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_HWSPINLOCK is not set # # Firmware Drivers diff --git a/projects/ION/options b/projects/ION/options index 00bce9770c..498ee472a7 100644 --- a/projects/ION/options +++ b/projects/ION/options @@ -45,6 +45,30 @@ # TARGET_CPU="atom" ;; + + arm) + # TARGET_CPU: + # arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm7m arm7d + # arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710c + # arm7100 arm720 arm7500 arm7500fe arm7tdmi arm7tdmi-s arm710t + # arm720t arm740t strongarm strongarm110 strongarm1100 + # strongarm1110 arm8 arm810 arm9 arm9e arm920 arm920t arm922t + # arm946e-s arm966e-s arm968e-s arm926ej-s arm940t arm9tdmi + # arm10tdmi arm1020t arm1026ej-s arm10e arm1020e arm1022e + # arm1136j-s arm1136jf-s mpcore mpcorenovfp arm1156t2-s + # arm1176jz-s arm1176jzf-s cortex-a8 cortex-a9 cortex-r4 + # cortex-r4f cortex-m3 cortex-m1 xscale iwmmxt iwmmxt2 ep9312. + # + TARGET_CPU="cortex-a9" + + # TARGET_FPU: + # This specifies what floating point hardware (or hardware emulation) is + # available on the target. Permissible names are: + # fpa fpe2 fpe3 maverick vfp vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16 + # vfpv3xd vfpv3xd-fp16 neon neon-fp16 vfpv4 vfpv4-d16 fpv4-sp-d16 + # neon-vfpv4. + TARGET_FPU="neon" + ;; esac # Build optimizations (size/normal/speed) @@ -53,6 +77,12 @@ # Project CFLAGS PROJECT_CFLAGS="-mfpmath=sse -ftree-vectorize -mmovbe" +# Bootloader to use (syslinux / u-boot) + BOOTLOADER="syslinux" + +# Configuration for u-boot + UBOOT_CONFIG="" + # Mediacenter to use (xbmc / xbmc-pvr / no) MEDIACENTER="xbmc-pvr" @@ -179,7 +209,7 @@ # 'all' compiles all drivers; # 'all,!xxx,!yyy' de-selects previously selected drivers # "none" for disable LCD support - LCD_DRIVER="irtrans,imon" + LCD_DRIVER="irtrans,imon,imonlcd" # additional Firmware to use (dvb-firmware, wlan-firmware) # Space separated list is supported, diff --git a/projects/Intel/linux/linux.i386.conf b/projects/Intel/linux/linux.i386.conf index d3365d98d1..c90c1923f6 100644 --- a/projects/Intel/linux/linux.i386.conf +++ b/projects/Intel/linux/linux.i386.conf @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux/i386 2.6.38-rc6-ck2 Kernel Configuration +# Linux/i386 2.6.38-rc8 Kernel Configuration # # CONFIG_64BIT is not set CONFIG_X86_32=y @@ -389,17 +389,10 @@ CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_SECCOMP=y CONFIG_CC_STACKPROTECTOR=y # CONFIG_HZ_100 is not set -# CONFIG_HZ_250_NODEFAULT is not set -# CONFIG_HZ_300 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1500 is not set -# CONFIG_HZ_2000 is not set -# CONFIG_HZ_3000 is not set -# CONFIG_HZ_4000 is not set -# CONFIG_HZ_5000 is not set -# CONFIG_HZ_7500 is not set -# CONFIG_HZ_10000 is not set -CONFIG_HZ=1000 +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set @@ -679,7 +672,7 @@ CONFIG_MAC80211_RC_MINSTREL_HT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set -# CONFIG_MAC80211_LEDS is not set +CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set CONFIG_RFKILL=y @@ -801,7 +794,7 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -983,7 +976,19 @@ CONFIG_WLAN=y # CONFIG_ADM8211 is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_MWL8K is not set -# CONFIG_ATH_COMMON is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K=m +CONFIG_ATH9K_RATE_CONTROL=y +CONFIG_ATH9K_HTC=m +CONFIG_AR9170_USB=m +CONFIG_AR9170_LEDS=y +# CONFIG_CARL9170 is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set CONFIG_HOSTAP=m @@ -1499,7 +1504,7 @@ CONFIG_DVB_BUDGET_CI=m # # Supported USB Adapters # -CONFIG_DVB_USB=m +CONFIG_DVB_USB=y # CONFIG_DVB_USB_DEBUG is not set # CONFIG_DVB_USB_A800 is not set CONFIG_DVB_USB_DIBUSB_MB=m @@ -2327,6 +2332,7 @@ CONFIG_MACH_NO_WESTBRIDGE=y # CONFIG_SPEAKUP is not set # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set # CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_HWSPINLOCK is not set # # Firmware Drivers diff --git a/projects/Intel/linux/linux.x86_64.conf b/projects/Intel/linux/linux.x86_64.conf index 2e6c5e8e02..2c691f0c31 100644 --- a/projects/Intel/linux/linux.x86_64.conf +++ b/projects/Intel/linux/linux.x86_64.conf @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux/x86_64 2.6.38-rc6-ck2 Kernel Configuration +# Linux/x86_64 2.6.38-rc8 Kernel Configuration # CONFIG_64BIT=y # CONFIG_X86_32 is not set @@ -354,17 +354,10 @@ CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_SECCOMP=y CONFIG_CC_STACKPROTECTOR=y # CONFIG_HZ_100 is not set -# CONFIG_HZ_250_NODEFAULT is not set -# CONFIG_HZ_300 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1500 is not set -# CONFIG_HZ_2000 is not set -# CONFIG_HZ_3000 is not set -# CONFIG_HZ_4000 is not set -# CONFIG_HZ_5000 is not set -# CONFIG_HZ_7500 is not set -# CONFIG_HZ_10000 is not set -CONFIG_HZ=1000 +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set @@ -629,7 +622,7 @@ CONFIG_MAC80211_RC_MINSTREL_HT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set -# CONFIG_MAC80211_LEDS is not set +CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set CONFIG_RFKILL=y @@ -751,7 +744,7 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -932,7 +925,19 @@ CONFIG_WLAN=y # CONFIG_ADM8211 is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_MWL8K is not set -# CONFIG_ATH_COMMON is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K=m +CONFIG_ATH9K_RATE_CONTROL=y +CONFIG_ATH9K_HTC=m +CONFIG_AR9170_USB=m +CONFIG_AR9170_LEDS=y +# CONFIG_CARL9170 is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set CONFIG_HOSTAP=m @@ -1445,7 +1450,7 @@ CONFIG_DVB_BUDGET_CI=m # # Supported USB Adapters # -CONFIG_DVB_USB=m +CONFIG_DVB_USB=y # CONFIG_DVB_USB_DEBUG is not set # CONFIG_DVB_USB_A800 is not set CONFIG_DVB_USB_DIBUSB_MB=m @@ -2265,6 +2270,7 @@ CONFIG_MACH_NO_WESTBRIDGE=y # CONFIG_SPEAKUP is not set # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set # CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_HWSPINLOCK is not set # # Firmware Drivers diff --git a/projects/Intel/options b/projects/Intel/options index 78594b1113..033c53b298 100644 --- a/projects/Intel/options +++ b/projects/Intel/options @@ -45,6 +45,30 @@ # TARGET_CPU="core2" ;; + + arm) + # TARGET_CPU: + # arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm7m arm7d + # arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710c + # arm7100 arm720 arm7500 arm7500fe arm7tdmi arm7tdmi-s arm710t + # arm720t arm740t strongarm strongarm110 strongarm1100 + # strongarm1110 arm8 arm810 arm9 arm9e arm920 arm920t arm922t + # arm946e-s arm966e-s arm968e-s arm926ej-s arm940t arm9tdmi + # arm10tdmi arm1020t arm1026ej-s arm10e arm1020e arm1022e + # arm1136j-s arm1136jf-s mpcore mpcorenovfp arm1156t2-s + # arm1176jz-s arm1176jzf-s cortex-a8 cortex-a9 cortex-r4 + # cortex-r4f cortex-m3 cortex-m1 xscale iwmmxt iwmmxt2 ep9312. + # + TARGET_CPU="cortex-a9" + + # TARGET_FPU: + # This specifies what floating point hardware (or hardware emulation) is + # available on the target. Permissible names are: + # fpa fpe2 fpe3 maverick vfp vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16 + # vfpv3xd vfpv3xd-fp16 neon neon-fp16 vfpv4 vfpv4-d16 fpv4-sp-d16 + # neon-vfpv4. + TARGET_FPU="neon" + ;; esac # Build optimizations (size/speed) @@ -53,6 +77,12 @@ # Project CFLAGS PROJECT_CFLAGS="" +# Bootloader to use (syslinux / u-boot) + BOOTLOADER="syslinux" + +# Configuration for u-boot + UBOOT_CONFIG="" + # Mediacenter to use (xbmc / xbmc-pvr / no) MEDIACENTER="xbmc-pvr" diff --git a/scripts/image_squashfs b/scripts/image_squashfs index 94ac5feb7e..abf205f707 100755 --- a/scripts/image_squashfs +++ b/scripts/image_squashfs @@ -34,7 +34,19 @@ get_version mkdir -p $TARGET_IMG rm -rf $TARGET_IMG/$DISTRONAME-$TARGET_VERSION.kernel - cp -PR $BUILD/linux-*/arch/x86/boot/bzImage $TARGET_IMG/$DISTRONAME-$TARGET_VERSION.kernel + if [ "$BOOTLOADER" = "u-boot" ]; then + KERNEL_IMAGE="uImage" + else + KERNEL_IMAGE="bzImage" + fi + + if [ "$TARGET_ARCH" = i386 -o "$TARGET_ARCH" = x86_64 ]; then + KERNEL_ARCH="x86" + elif [ "$TARGET_ARCH" = arm ]; then + KERNEL_ARCH="arm" + fi + + cp -PR $BUILD/linux-*/arch/$KERNEL_ARCH/boot/$KERNEL_IMAGE $TARGET_IMG/$DISTRONAME-$TARGET_VERSION.kernel echo "rm -rf $TARGET_IMG/$DISTRONAME-$TARGET_VERSION.system" >> $FAKEROOT_SCRIPT # echo "$ROOT/$TOOLCHAIN/bin/mksquashfs $BUILD/image/system $TARGET_IMG/$DISTRONAME-$TARGET_VERSION.system -noappend -comp xz" >> $FAKEROOT_SCRIPT diff --git a/tools/mkpkg/mkpkg_xbmc-dharma-10.1 b/tools/mkpkg/mkpkg_xbmc-10.1-dharma similarity index 60% rename from tools/mkpkg/mkpkg_xbmc-dharma-10.1 rename to tools/mkpkg/mkpkg_xbmc-10.1-dharma index 1f7a2c2241..49b37be8d3 100755 --- a/tools/mkpkg/mkpkg_xbmc-dharma-10.1 +++ b/tools/mkpkg/mkpkg_xbmc-10.1-dharma @@ -20,8 +20,8 @@ ################################################################################ PKG_NAME="xbmc" -PKG_VERSION="Dharma-10.1" -GIT_REPO="-b $PKG_VERSION git://github.com/theuni/xbmc.git" +PKG_VERSION="10.1-Dharma" +GIT_REPO="-b Dharma git@github.com:xbmc/xbmc.git" DEST_DIR="$PKG_NAME-$PKG_VERSION" echo "getting sources..." @@ -39,40 +39,40 @@ echo "getting version..." cd .. echo "copying sources..." - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV - cp -R $DEST_DIR-latest $PKG_NAME-$PKG_VERSION-$GIT_REV - echo "$GIT_REV" > $PKG_NAME-$PKG_VERSION-$GIT_REV/git.version + rm -rf $PKG_NAME-$PKG_VERSION + cp -R $DEST_DIR-latest $PKG_NAME-$PKG_VERSION + echo "$GIT_REV" > $PKG_NAME-$PKG_VERSION/git.version echo "cleaning sources..." - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV/.git + rm -rf $PKG_NAME-$PKG_VERSION/.git echo "seperating theme..." - rm -rf $PKG_NAME-theme-Confluence-$PKG_VERSION-$GIT_REV - mv $PKG_NAME-$PKG_VERSION-$GIT_REV/addons/skin.confluence $PKG_NAME-theme-Confluence-$PKG_VERSION-$GIT_REV + rm -rf $PKG_NAME-theme-Confluence-$PKG_VERSION + mv $PKG_NAME-$PKG_VERSION/addons/skin.confluence $PKG_NAME-theme-Confluence-$PKG_VERSION echo "cleaning sources..." - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV/visualisations - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV/lib/libSDL-* - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV/lib/libcurl-* - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV/project + rm -rf $PKG_NAME-$PKG_VERSION/visualisations + rm -rf $PKG_NAME-$PKG_VERSION/lib/libSDL-* + rm -rf $PKG_NAME-$PKG_VERSION/lib/libcurl-* + rm -rf $PKG_NAME-$PKG_VERSION/project for i in "Changelog" "Fake\ Episode\ Maker" "MingwBuildEnvironment" \ "PackageMaker" "Translator" "XBMCLive" "XprPack" \ "HardwareConfigure" "Mach5" "osx" "UpdateThumbs.py" "XBMCTex"; do - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV/tools/$i + rm -rf $PKG_NAME-$PKG_VERSION/tools/$i done for i in dll a lib so bat; do - find $PKG_NAME-$PKG_VERSION-$GIT_REV -name *.$i -exec rm -rf {} ";" + find $PKG_NAME-$PKG_VERSION -name *.$i -exec rm -rf {} ";" done # bundled win32 binaries - rm -r $PKG_NAME-$PKG_VERSION-$GIT_REV/xbmc/visualizations/XBMCProjectM/win32 + rm -r $PKG_NAME-$PKG_VERSION/xbmc/visualizations/XBMCProjectM/win32 echo "packing sources..." - tar cvjf $PKG_NAME-$PKG_VERSION-$GIT_REV.tar.bz2 $PKG_NAME-$PKG_VERSION-$GIT_REV - tar cvjf $PKG_NAME-theme-Confluence-$PKG_VERSION-$GIT_REV.tar.bz2 $PKG_NAME-theme-Confluence-$PKG_VERSION-$GIT_REV + tar cvjf $PKG_NAME-$PKG_VERSION.tar.bz2 $PKG_NAME-$PKG_VERSION + tar cvjf $PKG_NAME-theme-Confluence-$PKG_VERSION.tar.bz2 $PKG_NAME-theme-Confluence-$PKG_VERSION echo "remove temporary sourcedir..." - rm -rf $PKG_NAME-$PKG_VERSION-$GIT_REV - rm -rf $PKG_NAME-theme-Confluence-$PKG_VERSION-$GIT_REV + rm -rf $PKG_NAME-$PKG_VERSION + rm -rf $PKG_NAME-theme-Confluence-$PKG_VERSION