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linux (Rockchip): rebase and drop dw_hdmi-rockchip patches for linux 6.4-rc1
in projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch need to review drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c in line with - https://github.com/torvalds/linux/commits/master/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -d13b10ec66-de13db32b0Drop these patches - later patch to reinstate downstream changes vop_crtc_mode_valid updated.
This commit is contained in:
Rudi Heitbaum
parent
3d3206af6f
commit
dd5dae32e9
@ -83,7 +83,7 @@ index dbe4d411b30f..fac23d370ee0 100644
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+ */
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+#define CLOCK_TOLERANCE_PER_MILLE 5
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+
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+static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
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+static enum drm_mode_status vop_crtc_mode_valid5(struct drm_crtc *crtc,
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+ const struct drm_display_mode *mode)
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+{
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+ struct vop *vop = to_vop(crtc);
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@ -552,53 +552,6 @@ index 72c1d65c7b75..0370bb247fcb 100644
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}
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};
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 8 Jan 2020 21:07:52 +0000
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Subject: [PATCH] drm/rockchip: dw-hdmi: limit tmds to 340mhz
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RK3228/RK3328 does not provide a stable hdmi signal at TMDS rates
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above 371.25MHz (340MHz pixel clock).
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Limit the pixel clock rate to 340MHz to provide a stable signal.
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Also limit the pixel clock to the display reported max tmds clock.
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This also enables use of pixel clocks up to 340MHz on RK3288/RK3399.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++------------
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1 file changed, 4 insertions(+), 12 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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index 0370bb247fcb..55c0b8dddad5 100644
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -242,19 +242,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
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- int pclk = mode->clock * 1000;
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- bool valid = false;
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- int i;
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-
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- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
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- if (pclk == mpll_cfg[i].mpixelclock) {
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- valid = true;
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- break;
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- }
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- }
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+ if (mode->clock > 340000 ||
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+ (info->max_tmds_clock && mode->clock > info->max_tmds_clock))
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+ return MODE_CLOCK_HIGH;
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- return (valid) ? MODE_OK : MODE_BAD;
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+ return MODE_OK;
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}
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static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 8 Jan 2020 21:07:49 +0000
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@ -1001,39 +954,6 @@ index 48fb72f9614f..02554d324b4b 100644
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const struct dw_hdmi_phy_config *phy_config;
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int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 15 Jul 2020 09:49:21 +0000
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Subject: [PATCH] drm/rockchip: dw-hdmi: mode_valid: allow 420 clock rate
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 12 ++++++++++--
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1 file changed, 10 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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index 9e460b7e14a4..d42ac9fa3246 100644
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -242,8 +242,15 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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- if (mode->clock > 340000 ||
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- (info->max_tmds_clock && mode->clock > info->max_tmds_clock))
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+ struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data;
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+ int clock = mode->clock;
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+
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+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
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+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420))
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+ clock /= 2;
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+
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+ if (clock > 340000 ||
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+ (info->max_tmds_clock && clock > info->max_tmds_clock))
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Mon, 20 Jul 2020 22:26:19 +0000
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@ -2672,57 +2592,6 @@ index cb201612199f..8627f6826bfe 100644
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static struct rockchip_hdmi_chip_data rk3288_chip_data = {
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Mon, 4 Jan 2021 22:38:26 +0100
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Subject: [PATCH] drm/rockchip: seperate mode clock validation
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seperate mode clock validation between internal and external
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phy types.
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this will allow modes >= 2160p@50Hz on RK3288/RK3399 (RGB444)
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 17 +++++++++++++++--
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1 file changed, 15 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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index 8627f6826bfe..e259362f6414 100644
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -326,16 +326,29 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_mode *mode)
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{
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struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data;
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+ const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg;
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int clock = mode->clock;
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+ unsigned int i = 0;
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if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
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- (info->color_formats & DRM_COLOR_FORMAT_YCBCR420))
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+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) {
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clock /= 2;
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+ mpll_cfg = pdata->mpll_cfg_420;
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+ }
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- if (clock > 340000 ||
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+ if ((!mpll_cfg && clock > 340000) ||
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(info->max_tmds_clock && clock > info->max_tmds_clock))
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return MODE_CLOCK_HIGH;
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+ if (mpll_cfg) {
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+ while ((clock * 1000) < mpll_cfg[i].mpixelclock &&
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+ mpll_cfg[i].mpixelclock != (~0UL))
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+ i++;
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+
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+ if (mpll_cfg[i].mpixelclock == (~0UL))
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+ return MODE_CLOCK_HIGH;
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+ }
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+
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return MODE_OK;
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}
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static void
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sat, 18 Nov 2017 11:09:39 +0100
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