mirror of
https://github.com/LibreELEC/LibreELEC.tv.git
synced 2025-07-24 11:16:51 +00:00
Stefan Saraev
commit
dd7eaaf6e3
@ -0,0 +1,47 @@
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From 35a905282b20e556cd09f348f9c2bc8a22ea26d5 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
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Date: Mon, 23 Dec 2013 17:11:35 +0100
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Subject: [PATCH 2/4] drm/radeon: set correct pipe config for Hawaii in DCE
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: Marek Olšák <marek.olsak@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/atombios_crtc.c | 19 ++++++-------------
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1 file changed, 6 insertions(+), 13 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
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index b197059..ec97bad 100644
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--- a/drivers/gpu/drm/radeon/atombios_crtc.c
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+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
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@@ -1180,19 +1180,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
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fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
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if (rdev->family >= CHIP_BONAIRE) {
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- u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;
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- u32 num_rb = rdev->config.cik.max_backends_per_se;
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- if (num_pipe_configs > 8)
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- num_pipe_configs = 8;
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- if (num_pipe_configs == 8)
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- fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);
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- else if (num_pipe_configs == 4) {
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- if (num_rb == 4)
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- fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);
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- else if (num_rb < 4)
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- fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);
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- } else if (num_pipe_configs == 2)
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- fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);
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+ /* Read the pipe config from the 2D TILED SCANOUT mode.
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+ * It should be the same for the other modes too, but not all
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+ * modes set the pipe config field. */
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+ u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
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+
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+ fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
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} else if ((rdev->family == CHIP_TAHITI) ||
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(rdev->family == CHIP_PITCAIRN))
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fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
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--
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1.8.3.2
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@ -0,0 +1,106 @@
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From 439a1cfffe2c1a06e5a6394ccd5d18a8e89b15d3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
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Date: Sun, 22 Dec 2013 02:18:01 +0100
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Subject: [PATCH 1/4] drm/radeon: expose render backend mask to the userspace
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This will allow userspace to correctly program the PA_SC_RASTER_CONFIG
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register, so it can be considered a fix.
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Signed-off-by: Marek Olšák <marek.olsak@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Cc: stable@vger.kernel.org
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---
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drivers/gpu/drm/radeon/cik.c | 2 ++
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drivers/gpu/drm/radeon/radeon.h | 4 ++--
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drivers/gpu/drm/radeon/radeon_kms.c | 9 +++++++++
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drivers/gpu/drm/radeon/si.c | 2 ++
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include/uapi/drm/radeon_drm.h | 2 ++
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5 files changed, 17 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
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index 138a776..e950fab 100644
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--- a/drivers/gpu/drm/radeon/cik.c
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+++ b/drivers/gpu/drm/radeon/cik.c
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@@ -3114,6 +3114,8 @@ static void cik_setup_rb(struct radeon_device *rdev,
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mask <<= 1;
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}
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+ rdev->config.cik.backend_enable_mask = enabled_rbs;
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+
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for (i = 0; i < se_num; i++) {
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cik_select_se_sh(rdev, i, 0xffffffff);
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data = 0;
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diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
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index b1f990d..45e1f44 100644
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--- a/drivers/gpu/drm/radeon/radeon.h
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+++ b/drivers/gpu/drm/radeon/radeon.h
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@@ -1940,7 +1940,7 @@ struct si_asic {
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_tile_pipes;
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- unsigned num_backends_per_se;
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+ unsigned backend_enable_mask;
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unsigned backend_disable_mask_per_asic;
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unsigned backend_map;
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unsigned num_texture_channel_caches;
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@@ -1970,7 +1970,7 @@ struct cik_asic {
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_tile_pipes;
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- unsigned num_backends_per_se;
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+ unsigned backend_enable_mask;
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unsigned backend_disable_mask_per_asic;
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unsigned backend_map;
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unsigned num_texture_channel_caches;
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diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
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index 55d0b47..21d593c 100644
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--- a/drivers/gpu/drm/radeon/radeon_kms.c
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+++ b/drivers/gpu/drm/radeon/radeon_kms.c
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@@ -461,6 +461,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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case RADEON_INFO_SI_CP_DMA_COMPUTE:
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*value = 1;
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break;
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+ case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
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+ if (rdev->family >= CHIP_BONAIRE) {
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+ *value = rdev->config.cik.backend_enable_mask;
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+ } else if (rdev->family >= CHIP_TAHITI) {
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+ *value = rdev->config.si.backend_enable_mask;
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+ } else {
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+ DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
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+ }
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+ break;
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default:
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DRM_DEBUG_KMS("Invalid request %d\n", info->request);
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return -EINVAL;
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diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
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index 3eed9a1..85e1edf 100644
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--- a/drivers/gpu/drm/radeon/si.c
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+++ b/drivers/gpu/drm/radeon/si.c
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@@ -2855,6 +2855,8 @@ static void si_setup_rb(struct radeon_device *rdev,
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mask <<= 1;
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}
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+ rdev->config.si.backend_enable_mask = enabled_rbs;
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+
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for (i = 0; i < se_num; i++) {
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si_select_se_sh(rdev, i, 0xffffffff);
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data = 0;
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diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
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index 2f3f7ea..fe421e8 100644
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--- a/include/uapi/drm/radeon_drm.h
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+++ b/include/uapi/drm/radeon_drm.h
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@@ -983,6 +983,8 @@ struct drm_radeon_cs {
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#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
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/* CIK macrotile mode array */
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#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
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+/* query the number of render backends */
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+#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
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struct drm_radeon_info {
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--
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1.8.3.2
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@ -0,0 +1,102 @@
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From e3ea94a60f12025a3a547964c31245e71ac8fa77 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
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Date: Mon, 23 Dec 2013 17:11:36 +0100
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Subject: [PATCH 3/4] drm/radeon: set correct number of banks for CIK chips in
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DCE
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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We don't have the NUM_BANKS parameter, so we have to calculate it
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from the other parameters. NUM_BANKS is not constant on CIK.
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This fixes 2D tiling for the display engine on CIK.
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Signed-off-by: Marek Olšák <marek.olsak@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/atombios_crtc.c | 64 +++++++++++++++++++++++-----------
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1 file changed, 43 insertions(+), 21 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
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index ec97bad..0b9621c 100644
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--- a/drivers/gpu/drm/radeon/atombios_crtc.c
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+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
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@@ -1143,31 +1143,53 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
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}
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if (tiling_flags & RADEON_TILING_MACRO) {
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- if (rdev->family >= CHIP_BONAIRE)
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- tmp = rdev->config.cik.tile_config;
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- else if (rdev->family >= CHIP_TAHITI)
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- tmp = rdev->config.si.tile_config;
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- else if (rdev->family >= CHIP_CAYMAN)
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- tmp = rdev->config.cayman.tile_config;
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- else
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- tmp = rdev->config.evergreen.tile_config;
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+ evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
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- switch ((tmp & 0xf0) >> 4) {
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- case 0: /* 4 banks */
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- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
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- break;
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- case 1: /* 8 banks */
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- default:
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- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
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- break;
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- case 2: /* 16 banks */
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- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
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- break;
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+ /* Set NUM_BANKS. */
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+ if (rdev->family >= CHIP_BONAIRE) {
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+ unsigned tileb, index, num_banks, tile_split_bytes;
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+
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+ /* Calculate the macrotile mode index. */
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+ tile_split_bytes = 64 << tile_split;
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+ tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
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+ tileb = min(tile_split_bytes, tileb);
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+
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+ for (index = 0; tileb > 64; index++) {
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+ tileb >>= 1;
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+ }
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+
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+ if (index >= 16) {
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+ DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
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+ target_fb->bits_per_pixel, tile_split);
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+ return -EINVAL;
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+ }
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+
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+ num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
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+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
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+ } else {
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+ /* SI and older. */
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+ if (rdev->family >= CHIP_TAHITI)
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+ tmp = rdev->config.si.tile_config;
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+ else if (rdev->family >= CHIP_CAYMAN)
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+ tmp = rdev->config.cayman.tile_config;
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+ else
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+ tmp = rdev->config.evergreen.tile_config;
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+
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+ switch ((tmp & 0xf0) >> 4) {
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+ case 0: /* 4 banks */
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+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
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+ break;
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+ case 1: /* 8 banks */
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+ default:
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+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
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+ break;
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+ case 2: /* 16 banks */
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+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
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+ break;
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+ }
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}
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fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
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-
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- evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
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fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
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fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
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fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
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--
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1.8.3.2
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@ -0,0 +1,31 @@
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From 9482d0d37b46d2bd968d357bbd912cae49caf163 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Mon, 23 Dec 2013 11:31:44 -0500
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Subject: [PATCH 4/4] drm/radeon: Bump version for CIK DCE tiling fix
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Note when CIK DCE tiling was fixed.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
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index 1958b36a..db39ea3 100644
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--- a/drivers/gpu/drm/radeon/radeon_drv.c
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+++ b/drivers/gpu/drm/radeon/radeon_drv.c
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@@ -77,9 +77,10 @@
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* 2.33.0 - Add SI tiling mode array query
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* 2.34.0 - Add CIK tiling mode array query
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* 2.35.0 - Add CIK macrotile mode array query
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+ * 2.36.0 - Fix CIK DCE tiling setup
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*/
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#define KMS_DRIVER_MAJOR 2
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-#define KMS_DRIVER_MINOR 35
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+#define KMS_DRIVER_MINOR 36
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#define KMS_DRIVER_PATCHLEVEL 0
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
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int radeon_driver_unload_kms(struct drm_device *dev);
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--
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1.8.3.2
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