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Merge pull request #8392 from jernejsk/le11-fixes
[LE11] Allwinner: Backport fixes
This commit is contained in:
CvH
GitHub
commit
ddb1c65c1a
@ -0,0 +1,65 @@
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From 6fba61d436ed9d610e1001860e2fcdf2ccf96803 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Sat, 7 Oct 2023 08:36:47 +0200
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Subject: [PATCH 14/23] media: cedrus: h265: Fix configuring bitstream size
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bit_size field holds size of slice, not slice + header. Because of HW
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quirks, driver can't program in just slice, but also preceeding header.
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But that means that currently used bit_size is wrong (too small).
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Instead, just use size of whole buffer. There is no harm in doing this.
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Fixes: 86caab29da78 ("media: cedrus: Add HEVC/H.265 decoding support")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 10 ++++------
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1 file changed, 4 insertions(+), 6 deletions(-)
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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index fc9297232456..16c822637dc6 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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@@ -454,11 +454,11 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
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unsigned int ctb_addr_x, ctb_addr_y;
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struct cedrus_buffer *cedrus_buf;
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dma_addr_t src_buf_addr;
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- dma_addr_t src_buf_end_addr;
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u32 chroma_log2_weight_denom;
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u32 num_entry_point_offsets;
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u32 output_pic_list_index;
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u32 pic_order_cnt[2];
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+ size_t slice_bytes;
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u8 padding;
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int count;
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u32 reg;
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@@ -468,6 +468,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
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decode_params = run->h265.decode_params;
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pred_weight_table = &slice_params->pred_weight_table;
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num_entry_point_offsets = slice_params->num_entry_point_offsets;
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+ slice_bytes = vb2_get_plane_payload(&run->src->vb2_buf, 0);
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/*
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* If entry points offsets are present, we should get them
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@@ -490,7 +491,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
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cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0);
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- reg = slice_params->bit_size;
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+ reg = slice_bytes * 8;
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cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg);
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/* Source beginning and end addresses. */
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@@ -504,10 +505,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
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cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg);
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- src_buf_end_addr = src_buf_addr +
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- DIV_ROUND_UP(slice_params->bit_size, 8);
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-
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- reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr);
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+ reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_addr + slice_bytes);
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cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
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/* Coding tree block address */
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--
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2.42.0
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@ -0,0 +1,150 @@
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From 239ce64f28fce7cc035a857bb5ed6f51ad6795c8 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Thu, 19 Oct 2023 19:16:18 +0200
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Subject: [PATCH] wip: media: sunxi: sun8i-di: fix race condition
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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.../media/platform/sunxi/sun8i-di/sun8i-di.c | 69 ++++++++++---------
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1 file changed, 35 insertions(+), 34 deletions(-)
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diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
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index 90ab1d77b6a5..f7ff0937828c 100644
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--- a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
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+++ b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
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@@ -66,6 +66,7 @@ static void deinterlace_device_run(void *priv)
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struct vb2_v4l2_buffer *src, *dst;
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unsigned int hstep, vstep;
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dma_addr_t addr;
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+ int i;
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src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
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dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
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@@ -160,6 +161,26 @@ static void deinterlace_device_run(void *priv)
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deinterlace_write(dev, DEINTERLACE_CH1_HORZ_FACT, hstep);
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deinterlace_write(dev, DEINTERLACE_CH1_VERT_FACT, vstep);
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+ /* neutral filter coefficients */
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+ deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL,
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+ DEINTERLACE_FRM_CTRL_COEF_ACCESS);
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+ readl_poll_timeout(dev->base + DEINTERLACE_STATUS, val,
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+ val & DEINTERLACE_STATUS_COEF_STATUS, 2, 40);
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+
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+ for (i = 0; i < 32; i++) {
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+ deinterlace_write(dev, DEINTERLACE_CH0_HORZ_COEF0 + i * 4,
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+ DEINTERLACE_IDENTITY_COEF);
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+ deinterlace_write(dev, DEINTERLACE_CH0_VERT_COEF + i * 4,
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+ DEINTERLACE_IDENTITY_COEF);
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+ deinterlace_write(dev, DEINTERLACE_CH1_HORZ_COEF0 + i * 4,
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+ DEINTERLACE_IDENTITY_COEF);
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+ deinterlace_write(dev, DEINTERLACE_CH1_VERT_COEF + i * 4,
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+ DEINTERLACE_IDENTITY_COEF);
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+ }
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+
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+ deinterlace_clr_set_bits(dev, DEINTERLACE_FRM_CTRL,
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+ DEINTERLACE_FRM_CTRL_COEF_ACCESS, 0);
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+
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deinterlace_clr_set_bits(dev, DEINTERLACE_FIELD_CTRL,
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DEINTERLACE_FIELD_CTRL_FIELD_CNT_MSK,
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DEINTERLACE_FIELD_CTRL_FIELD_CNT(ctx->field));
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@@ -248,7 +269,6 @@ static irqreturn_t deinterlace_irq(int irq, void *data)
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static void deinterlace_init(struct deinterlace_dev *dev)
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{
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u32 val;
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- int i;
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deinterlace_write(dev, DEINTERLACE_BYPASS,
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DEINTERLACE_BYPASS_CSC);
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@@ -284,27 +304,7 @@ static void deinterlace_init(struct deinterlace_dev *dev)
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deinterlace_clr_set_bits(dev, DEINTERLACE_CHROMA_DIFF,
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DEINTERLACE_CHROMA_DIFF_TH_MSK,
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- DEINTERLACE_CHROMA_DIFF_TH(5));
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-
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- /* neutral filter coefficients */
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- deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL,
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- DEINTERLACE_FRM_CTRL_COEF_ACCESS);
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- readl_poll_timeout(dev->base + DEINTERLACE_STATUS, val,
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- val & DEINTERLACE_STATUS_COEF_STATUS, 2, 40);
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-
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- for (i = 0; i < 32; i++) {
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- deinterlace_write(dev, DEINTERLACE_CH0_HORZ_COEF0 + i * 4,
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- DEINTERLACE_IDENTITY_COEF);
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- deinterlace_write(dev, DEINTERLACE_CH0_VERT_COEF + i * 4,
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- DEINTERLACE_IDENTITY_COEF);
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- deinterlace_write(dev, DEINTERLACE_CH1_HORZ_COEF0 + i * 4,
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- DEINTERLACE_IDENTITY_COEF);
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- deinterlace_write(dev, DEINTERLACE_CH1_VERT_COEF + i * 4,
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- DEINTERLACE_IDENTITY_COEF);
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- }
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-
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- deinterlace_clr_set_bits(dev, DEINTERLACE_FRM_CTRL,
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- DEINTERLACE_FRM_CTRL_COEF_ACCESS, 0);
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+ DEINTERLACE_CHROMA_DIFF_TH(31));
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}
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static inline struct deinterlace_ctx *deinterlace_file2ctx(struct file *file)
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@@ -929,11 +929,18 @@ static int deinterlace_runtime_resume(struct device *device)
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return ret;
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}
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+ ret = reset_control_deassert(dev->rstc);
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+ if (ret) {
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+ dev_err(dev->dev, "Failed to apply reset\n");
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+
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+ goto err_exclusive_rate;
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+ }
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+
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ret = clk_prepare_enable(dev->bus_clk);
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if (ret) {
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dev_err(dev->dev, "Failed to enable bus clock\n");
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- goto err_exclusive_rate;
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+ goto err_rst;
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}
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ret = clk_prepare_enable(dev->mod_clk);
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@@ -950,23 +957,16 @@ static int deinterlace_runtime_resume(struct device *device)
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goto err_mod_clk;
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}
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- ret = reset_control_deassert(dev->rstc);
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- if (ret) {
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- dev_err(dev->dev, "Failed to apply reset\n");
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-
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- goto err_ram_clk;
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- }
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-
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deinterlace_init(dev);
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return 0;
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-err_ram_clk:
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- clk_disable_unprepare(dev->ram_clk);
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err_mod_clk:
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clk_disable_unprepare(dev->mod_clk);
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err_bus_clk:
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clk_disable_unprepare(dev->bus_clk);
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+err_rst:
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+ reset_control_assert(dev->rstc);
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err_exclusive_rate:
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clk_rate_exclusive_put(dev->mod_clk);
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@@ -977,11 +977,12 @@ static int deinterlace_runtime_suspend(struct device *device)
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{
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struct deinterlace_dev *dev = dev_get_drvdata(device);
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- reset_control_assert(dev->rstc);
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-
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clk_disable_unprepare(dev->ram_clk);
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clk_disable_unprepare(dev->mod_clk);
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clk_disable_unprepare(dev->bus_clk);
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+
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+ reset_control_assert(dev->rstc);
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+
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clk_rate_exclusive_put(dev->mod_clk);
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return 0;
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--
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2.42.0
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@ -0,0 +1,46 @@
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From: Gunjan Gupta <viraniac@gmail.com>
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Subject: [PATCH 1/1] sunxi: dram: Fix incorrect ram size detection for some H6
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boards
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Date: Sun, 1 Oct 2023 21:43:32 +0530
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On some H6 boards like Orange Pi 3 LTS, some times U-Boot fails to detect
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ram size correctly. Instead of 2GB thats available, it detects 4GB of ram
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and then SPL just hangs there making board not to boot further.
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On debugging, I found that the rows value were being determined correctly,
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but columns were sometimes off by one value. I found that adding some
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delay after the mctl_core_init call along with making use of dsb in the
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start of the mctl_mem_matches solves the issue.
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Signed-off-by: Gunjan Gupta <viraniac@gmail.com>
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---
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arch/arm/mach-sunxi/dram_helpers.c | 1 +
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arch/arm/mach-sunxi/dram_sun50i_h6.c | 2 ++
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2 files changed, 3 insertions(+)
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diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
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index cdf2750f1c..5758c58e07 100644
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--- a/arch/arm/mach-sunxi/dram_helpers.c
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+++ b/arch/arm/mach-sunxi/dram_helpers.c
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@@ -32,6 +32,7 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val)
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#ifndef CONFIG_MACH_SUNIV
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bool mctl_mem_matches(u32 offset)
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{
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+ dsb();
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/* Try to write different values to RAM at two addresses */
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writel(0, CFG_SYS_SDRAM_BASE);
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writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
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diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
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index bff2e42513..a031a845f5 100644
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--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
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+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
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@@ -623,6 +623,8 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
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para->cols = 11;
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mctl_core_init(para);
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+ udelay(50);
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+
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for (para->cols = 8; para->cols < 11; para->cols++) {
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/* 8 bits per byte and 16/32 bit width */
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if (mctl_mem_matches(1 << (para->cols + 1 +
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@ -1,40 +0,0 @@
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From: megous@megous.com
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Date: Mon, 29 Jul 2019 01:39:42 +0200
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Subject: [U-Boot] [PATCH] Fix unreliable detection of DRAM size on Orange Pi 3
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From: Ondrej Jirman <megous@megous.com>
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Orange Pi 3 has 2 GiB of DRAM, that sometime get misdetected
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as 4 GiB, due to false negative result from mctl_mem_matches()
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when detecting number of column address bits. This leads to
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u-boot detecting more address bits than there are and the
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boot process hangs shortly after.
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In mctl_mem_matches() we need to wait for each write to finish,
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separately. Without this, the check is not reliable for some
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unknown reason, probably having to do with unpredictable memory
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access ordering.
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Patch was made with help from André Przywara, who noticed that
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my original idea about detection failing due to read-back from
|
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cache without involving DRAM was false, because data cache is
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still of at the time of the DRAM size autodetection.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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Cc: André Przywara <andre.przywara@arm.com>
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---
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arch/arm/mach-sunxi/dram_helpers.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
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index 239ab421a8..6dba448638 100644
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--- a/arch/arm/mach-sunxi/dram_helpers.c
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+++ b/arch/arm/mach-sunxi/dram_helpers.c
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@@ -30,6 +30,7 @@ bool mctl_mem_matches(u32 offset)
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{
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/* Try to write different values to RAM at two addresses */
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writel(0, CONFIG_SYS_SDRAM_BASE);
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+ dsb();
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writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
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dsb();
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/* Check if the same value is actually observed when reading back */
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