diff --git a/packages/linux/patches/3.15-rc6/linux-221-ngene-octopus.patch b/packages/linux/patches/3.15-rc6/linux-221-ngene-octopus.patch index f07493194f..d540c56061 100644 --- a/packages/linux/patches/3.15-rc6/linux-221-ngene-octopus.patch +++ b/packages/linux/patches/3.15-rc6/linux-221-ngene-octopus.patch @@ -1,60 +1,75 @@ -From 60d2d7edcf158030337b7b11a5db9ca2c8414987 Mon Sep 17 00:00:00 2001 +From e5d98e8b261526ab41234b2fbc090c99bd009631 Mon Sep 17 00:00:00 2001 From: Stefan Saraev -Date: Tue, 22 Apr 2014 11:55:29 +0300 +Date: Thu, 22 May 2014 20:00:40 +0300 Subject: [PATCH] dvb: ngene/octopus source: http://linuxtv.org/hg/~endriss/media_build_experimental/ note: SYS_DVBC2 not added. ci extensions (en50221) not added. --- + drivers/media/dvb-core/Makefile | 2 +- drivers/media/dvb-core/dvb_netstream.c | 259 ++ drivers/media/dvb-core/dvb_netstream.h | 94 + drivers/media/dvb-core/dvbdev.c | 11 +- drivers/media/dvb-core/dvbdev.h | 4 + drivers/media/dvb-frontends/Kconfig | 27 + drivers/media/dvb-frontends/Makefile | 3 + - drivers/media/dvb-frontends/cxd2843.c | 1721 ++++++++++++ - drivers/media/dvb-frontends/cxd2843.h | 15 + - drivers/media/dvb-frontends/drxk_hard.c | 3601 ++++++++++++-------------- - drivers/media/dvb-frontends/drxk_hard.h | 298 +-- + drivers/media/dvb-frontends/cxd2843.c | 2021 +++++++++++++ + drivers/media/dvb-frontends/cxd2843.h | 30 + + drivers/media/dvb-frontends/drxk_hard.c | 3602 ++++++++++------------- + drivers/media/dvb-frontends/drxk_hard.h | 298 +- drivers/media/dvb-frontends/drxk_map.h | 3 - - drivers/media/dvb-frontends/stv0367dd.c | 2331 +++++++++++++++++ + drivers/media/dvb-frontends/lnbh25.c | 133 + + drivers/media/dvb-frontends/lnbh25.h | 28 + + drivers/media/dvb-frontends/stv0367dd.c | 2331 +++++++++++++++ drivers/media/dvb-frontends/stv0367dd.h | 17 + - drivers/media/dvb-frontends/stv0367dd_regs.h | 3431 ++++++++++++++++++++++++ - drivers/media/dvb-frontends/tda18212dd.c | 945 +++++++ + drivers/media/dvb-frontends/stv0367dd_regs.h | 3431 ++++++++++++++++++++++ + drivers/media/dvb-frontends/stv0910.c | 1368 +++++++++ + drivers/media/dvb-frontends/stv0910.h | 31 + + drivers/media/dvb-frontends/stv0910_regs.h | 3998 ++++++++++++++++++++++++++ + drivers/media/dvb-frontends/stv6111.c | 450 +++ + drivers/media/dvb-frontends/stv6111.h | 5 + + drivers/media/dvb-frontends/tda18212dd.c | 974 +++++++ drivers/media/dvb-frontends/tda18212dd.h | 5 + drivers/media/dvb-frontends/tda18271c2dd.c | 15 +- drivers/media/dvb-frontends/tda18271c2dd.h | 6 +- drivers/media/pci/ddbridge/Kconfig | 11 +- drivers/media/pci/ddbridge/Makefile | 2 - - drivers/media/pci/ddbridge/ddbridge-core.c | 3562 ++++++++++++++++++------- + drivers/media/pci/ddbridge/ddbridge-core.c | 3707 ++++++++++++++++++------ drivers/media/pci/ddbridge/ddbridge-i2c.c | 257 ++ drivers/media/pci/ddbridge/ddbridge-i2c.h | 105 + - drivers/media/pci/ddbridge/ddbridge-mod.c | 1110 ++++++++ - drivers/media/pci/ddbridge/ddbridge-ns.c | 490 ++++ - drivers/media/pci/ddbridge/ddbridge-regs.h | 318 ++- - drivers/media/pci/ddbridge/ddbridge.c | 439 ++++ - drivers/media/pci/ddbridge/ddbridge.h | 374 ++- - drivers/media/pci/ddbridge/octonet.c | 198 ++ + drivers/media/pci/ddbridge/ddbridge-mod.c | 1131 ++++++++ + drivers/media/pci/ddbridge/ddbridge-ns.c | 489 ++++ + drivers/media/pci/ddbridge/ddbridge-regs.h | 322 ++- + drivers/media/pci/ddbridge/ddbridge.c | 449 +++ + drivers/media/pci/ddbridge/ddbridge.h | 399 ++- + drivers/media/pci/ddbridge/octonet.c | 191 ++ drivers/media/pci/ngene/Kconfig | 3 + drivers/media/pci/ngene/Makefile | 3 +- drivers/media/pci/ngene/ngene-av.c | 348 +++ - drivers/media/pci/ngene/ngene-cards.c | 778 ++++-- + drivers/media/pci/ngene/ngene-cards.c | 778 +++-- drivers/media/pci/ngene/ngene-core.c | 382 ++- drivers/media/pci/ngene/ngene-dvb.c | 372 +++ drivers/media/pci/ngene/ngene-eeprom.c | 284 ++ drivers/media/pci/ngene/ngene-i2c.c | 113 + drivers/media/pci/ngene/ngene.h | 40 + - include/uapi/linux/dvb/mod.h | 23 + + include/uapi/linux/dvb/mod.h | 22 + include/uapi/linux/dvb/ns.h | 68 + - 40 files changed, 18634 insertions(+), 3432 deletions(-) + 48 files changed, 25191 insertions(+), 3431 deletions(-) create mode 100644 drivers/media/dvb-core/dvb_netstream.c create mode 100644 drivers/media/dvb-core/dvb_netstream.h create mode 100644 drivers/media/dvb-frontends/cxd2843.c create mode 100644 drivers/media/dvb-frontends/cxd2843.h + create mode 100644 drivers/media/dvb-frontends/lnbh25.c + create mode 100644 drivers/media/dvb-frontends/lnbh25.h create mode 100644 drivers/media/dvb-frontends/stv0367dd.c create mode 100644 drivers/media/dvb-frontends/stv0367dd.h create mode 100644 drivers/media/dvb-frontends/stv0367dd_regs.h + create mode 100644 drivers/media/dvb-frontends/stv0910.c + create mode 100644 drivers/media/dvb-frontends/stv0910.h + create mode 100644 drivers/media/dvb-frontends/stv0910_regs.h + create mode 100644 drivers/media/dvb-frontends/stv6111.c + create mode 100644 drivers/media/dvb-frontends/stv6111.h create mode 100644 drivers/media/dvb-frontends/tda18212dd.c create mode 100644 drivers/media/dvb-frontends/tda18212dd.h create mode 100644 drivers/media/pci/ddbridge/ddbridge-i2c.c @@ -68,6 +83,18 @@ note: SYS_DVBC2 not added. ci extensions (en50221) not added. create mode 100644 include/uapi/linux/dvb/mod.h create mode 100644 include/uapi/linux/dvb/ns.h +diff --git a/drivers/media/dvb-core/Makefile b/drivers/media/dvb-core/Makefile +index 8f22bcd..5ff851a 100644 +--- a/drivers/media/dvb-core/Makefile ++++ b/drivers/media/dvb-core/Makefile +@@ -6,6 +6,6 @@ dvb-net-$(CONFIG_DVB_NET) := dvb_net.o + + dvb-core-objs := dvbdev.o dmxdev.o dvb_demux.o dvb_filter.o \ + dvb_ca_en50221.o dvb_frontend.o \ +- $(dvb-net-y) dvb_ringbuffer.o dvb_math.o ++ $(dvb-net-y) dvb_ringbuffer.o dvb_math.o dvb_netstream.o + + obj-$(CONFIG_DVB_CORE) += dvb-core.o diff --git a/drivers/media/dvb-core/dvb_netstream.c b/drivers/media/dvb-core/dvb_netstream.c new file mode 100644 index 0000000..43322c7 @@ -558,10 +585,10 @@ index 282aba2..fac3f5f 100644 obj-$(CONFIG_DVB_RTL2830) += rtl2830.o diff --git a/drivers/media/dvb-frontends/cxd2843.c b/drivers/media/dvb-frontends/cxd2843.c new file mode 100644 -index 0000000..5feea53 +index 0000000..40595dd --- /dev/null +++ b/drivers/media/dvb-frontends/cxd2843.c -@@ -0,0 +1,1721 @@ +@@ -0,0 +1,2021 @@ +/* + * Driver for the Sony CXD2843ER DVB-T/T2/C/C2 demodulator. + * Also supports the CXD2837ER DVB-T/T2/C and the @@ -604,10 +631,11 @@ index 0000000..5feea53 +#define USE_ALGO 1 + +enum EDemodType { CXD2843, CXD2837, CXD2838 }; -+enum EDemodState { Unknown, Shutdown, Sleep, ActiveT, ++enum EDemodState { Unknown, Shutdown, Sleep, ActiveT, + ActiveT2, ActiveC, ActiveC2, ActiveIT }; -+enum omode { OM_NONE, OM_DVBT, OM_DVBT2, OM_DVBC, -+ OM_QAM_ITU_C, OM_ISDBT }; ++enum ET2Profile { T2P_Base, T2P_Lite }; ++enum omode { OM_NONE, OM_DVBT, OM_DVBT2, OM_DVBC, ++ OM_QAM_ITU_C, OM_DVBC2, OM_ISDBT }; + +struct cxd_state { + struct dvb_frontend frontend; @@ -622,34 +650,39 @@ index 0000000..5feea53 + + enum EDemodType type; + enum EDemodState state; ++ enum ET2Profile T2Profile; + enum omode omode; + + u8 IF_FS; + int ContinuousClock; + int SerialMode; + u8 SerialClockFrequency; -+ ++ + u32 LockTimeout; + u32 TSLockTimeout; + u32 L1PostTimeout; -+ u32 DataSliceID; ++ u32 DataSliceID; + int FirstTimeLock; + u32 plp; + u32 last_status; -+ ++ + u32 bandwidth; + u32 bw; + + unsigned long tune_time; ++ ++ u32 LastBERNominator; ++ u32 LastBERDenominator; ++ u8 BERScaleMax; +}; + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ -+ struct i2c_msg msg = -+ {.addr = adr, .flags = 0, .buf = data, .len = len}; ++ struct i2c_msg msg = { ++ .addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { -+ printk("cxd2843: i2c_write error\n"); ++ pr_err("cxd2843: i2c_write error\n"); + return -1; + } + return 0; @@ -680,7 +713,7 @@ index 0000000..5feea53 + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { -+ printk("cxd2843: i2c_read error\n"); ++ pr_err("cxd2843: i2c_read error\n"); + return -1; + } + return 0; @@ -689,14 +722,14 @@ index 0000000..5feea53 +static int readregs(struct cxd_state *state, u8 adr, u8 reg, + u8 *val, int count) +{ -+ return i2c_read(state->i2c, adr, ®, 1, val, count); ++ return i2c_read(state->i2c, adr, ®, 1, val, count); +} + +static int readregst_unlocked(struct cxd_state *cxd, u8 bank, + u8 Address, u8 *pValue, u16 count) +{ + int status = 0; -+ ++ + if (bank != 0xFF && cxd->curbankt != bank) { + status = writereg(cxd, cxd->adrt, 0, bank); + if (status < 0) { @@ -713,7 +746,7 @@ index 0000000..5feea53 + u8 Address, u8 *pValue, u16 count) +{ + int status; -+ ++ + mutex_lock(&cxd->mutex); + status = readregst_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); @@ -724,7 +757,7 @@ index 0000000..5feea53 + u8 Address, u8 *pValue, u16 count) +{ + int status = 0; -+ ++ + if (Bank != 0xFF && cxd->curbankx != Bank) { + status = writereg(cxd, cxd->adrx, 0, Bank); + if (status < 0) { @@ -741,7 +774,7 @@ index 0000000..5feea53 + u8 Address, u8 *pValue, u16 count) +{ + int status; -+ ++ + mutex_lock(&cxd->mutex); + status = readregsx_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); @@ -752,7 +785,7 @@ index 0000000..5feea53 + u8 Address, u8 *pValue, u16 count) +{ + int status = 0; -+ ++ + if (Bank != 0xFF && cxd->curbankx != Bank) { + status = writereg(cxd, cxd->adrx, 0, Bank); + if (status < 0) { @@ -769,7 +802,7 @@ index 0000000..5feea53 + u8 *pValue, u16 count) +{ + int status; -+ ++ + mutex_lock(&cxd->mutex); + status = writeregsx_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); @@ -785,7 +818,7 @@ index 0000000..5feea53 + u8 Address, u8 *pValue, u16 count) +{ + int status = 0; -+ ++ + if (Bank != 0xFF && cxd->curbankt != Bank) { + status = writereg(cxd, cxd->adrt, 0, Bank); + if (status < 0) { @@ -802,7 +835,7 @@ index 0000000..5feea53 + u8 *pValue, u16 count) +{ + int status; -+ ++ + mutex_lock(&cxd->mutex); + status = writeregst_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); @@ -822,7 +855,7 @@ index 0000000..5feea53 + + mutex_lock(&cxd->mutex); + status = readregsx_unlocked(cxd, Bank, Address, &tmp, 1); -+ if (status < 0) ++ if (status < 0) + return status; + tmp = (tmp & ~Mask) | Value; + status = writeregsx_unlocked(cxd, Bank, Address, &tmp, 1); @@ -838,7 +871,7 @@ index 0000000..5feea53 + + mutex_lock(&cxd->mutex); + status = readregst_unlocked(cxd, Bank, Address, &Tmp, 1); -+ if (status < 0) ++ if (status < 0) + return status; + Tmp = (Tmp & ~Mask) | Value; + status = writeregst_unlocked(cxd, Bank, Address, &Tmp, 1); @@ -871,117 +904,142 @@ index 0000000..5feea53 + return (u32) tmp64; +} + ++/* TPSData[0] [7:6] CNST[1:0] */ ++/* TPSData[0] [5:3] HIER[2:0] */ ++/* TPSData[0] [2:0] HRATE[2:0] */ ++/* TPSData[1] [7:5] LRATE[2:0] */ ++/* TPSData[1] [4:3] GI[1:0] */ ++/* TPSData[1] [2:1] MODE[1:0] */ ++/* TPSData[2] [7:6] FNUM[1:0] */ ++/* TPSData[2] [5:0] LENGTH_INDICATOR[5:0] */ ++/* TPSData[3] [7:0] CELLID[15:8] */ ++/* TPSData[4] [7:0] CELLID[7:0] */ ++/* TPSData[5] [5:0] RESERVE_EVEN[5:0] */ ++/* TPSData[6] [5:0] RESERVE_ODD[5:0] */ ++ ++static int read_tps(struct cxd_state *state, u8 *tps) ++{ ++ if (state->last_status != 0x1f) ++ return 0; ++ ++ freeze_regst(state); ++ readregst_unlocked(state, 0x10, 0x2f, tps, 7); ++ unfreeze_regst(state); ++ return 0; ++} ++ +static void Active_to_Sleep(struct cxd_state *state) +{ -+ if (state->state <= Sleep ) ++ if (state->state <= Sleep) + return; + + writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */ -+ writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */ -+ writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */ -+ writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */ -+ writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */ -+ writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */ -+ writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */ -+ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */ -+ writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */ ++ writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */ ++ writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */ ++ writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */ ++ writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */ ++ writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */ ++ writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */ + state->state = Sleep; +} + +static void ActiveT2_to_Sleep(struct cxd_state *state) +{ -+ if (state->state <= Sleep ) ++ if (state->state <= Sleep) + return; -+ -+ writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */ -+ writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */ -+ writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */ -+ -+ writeregt(state, 0x13, 0x83, 0x40); -+ writeregt(state, 0x13, 0x86, 0x21); -+ writebitst(state, 0x13, 0x9E, 0x09, 0x0F); -+ writeregt(state, 0x13, 0x9F, 0xFB); + -+ writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */ -+ writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */ -+ writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */ -+ writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */ -+ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */ -+ writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */ -+ state->state = Sleep; ++ writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */ ++ writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */ ++ writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */ ++ ++ writeregt(state, 0x13, 0x83, 0x40); ++ writeregt(state, 0x13, 0x86, 0x21); ++ writebitst(state, 0x13, 0x9E, 0x09, 0x0F); ++ writeregt(state, 0x13, 0x9F, 0xFB); ++ ++ writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */ ++ writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */ ++ writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */ ++ writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */ ++ state->state = Sleep; +} + +static void ActiveC2_to_Sleep(struct cxd_state *state) +{ -+ if (state->state <= Sleep ) ++ if (state->state <= Sleep) + return; -+ -+ writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */ -+ writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */ -+ writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */ + -+ writeregt(state, 0x20, 0xC2, 0x11); -+ writebitst(state, 0x25, 0x6A, 0x02, 0x03); -+ { ++ writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */ ++ writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */ ++ writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */ ++ ++ writeregt(state, 0x20, 0xC2, 0x11); ++ writebitst(state, 0x25, 0x6A, 0x02, 0x03); ++ { + static u8 data[3] = { 0x07, 0x61, 0x36 }; + writeregst(state, 0x25, 0x89, data, sizeof(data)); -+ } ++ } + writebitst(state, 0x25, 0xCB, 0x05, 0x07); -+ { ++ { + static u8 data[4] = { 0x2E, 0xE0, 0x2E, 0xE0 }; + writeregst(state, 0x25, 0xDC, data, sizeof(data)); -+ } ++ } + writeregt(state, 0x25, 0xE2, 0x2F); + writeregt(state, 0x25, 0xE5, 0x2F); -+ writebitst(state, 0x27, 0x20, 0x00, 0x01); -+ writebitst(state, 0x27, 0x35, 0x00, 0x01); -+ writebitst(state, 0x27, 0xD9, 0x19, 0x3F); -+ writebitst(state, 0x2A, 0x78, 0x01, 0x07); -+ writeregt(state, 0x2A, 0x86, 0x08); -+ writeregt(state, 0x2A, 0x88, 0x14); -+ writebitst(state, 0x2B, 0x2B, 0x00, 0x1F); -+ { ++ writebitst(state, 0x27, 0x20, 0x00, 0x01); ++ writebitst(state, 0x27, 0x35, 0x00, 0x01); ++ writebitst(state, 0x27, 0xD9, 0x19, 0x3F); ++ writebitst(state, 0x2A, 0x78, 0x01, 0x07); ++ writeregt(state, 0x2A, 0x86, 0x08); ++ writeregt(state, 0x2A, 0x88, 0x14); ++ writebitst(state, 0x2B, 0x2B, 0x00, 0x1F); ++ { + u8 data[2] = { 0x75, 0x75 }; + writeregst(state, 0x2D, 0x24, data, sizeof(data)); -+ } -+ -+ writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */ ++ } ++ ++ writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */ + writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */ -+ writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */ -+ writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */ -+ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */ -+ writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */ -+ state->state = Sleep; ++ writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */ ++ writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */ ++ state->state = Sleep; +} + +static int ConfigureTS(struct cxd_state *state, + enum EDemodState newDemodState) +{ + int status = 0; -+ u8 OSERCKMODE = 1; -+ u8 OSERDUTYMODE = 1; -+ u8 OTSCKPERIOD = 8; -+ u8 OREG_CKSEL_TSIF = state->SerialClockFrequency; -+ -+ if (state->SerialClockFrequency >= 3 ) { ++ u8 OSERCKMODE = state->SerialMode ? 1 : 0; ++ u8 OSERDUTYMODE = state->SerialMode ? 1 : 0; ++ u8 OTSCKPERIOD = 8; ++ u8 OREG_CKSEL_TSIF = state->SerialMode ? ++ state->SerialClockFrequency : 0; ++ ++ if (state->SerialMode && state->SerialClockFrequency >= 3) { + OSERCKMODE = 2; + OSERDUTYMODE = 2; + OTSCKPERIOD = 16; + OREG_CKSEL_TSIF = state->SerialClockFrequency - 3; -+ } -+ writebitst(state, 0x00, 0xC4, OSERCKMODE, 0x03); /* OSERCKMODE */ ++ } ++ writebitst(state, 0x00, 0xC4, OSERCKMODE, 0x03); /* OSERCKMODE */ + writebitst(state, 0x00, 0xD1, OSERDUTYMODE, 0x03); /* OSERDUTYMODE */ + writeregt(state, 0x00, 0xD9, OTSCKPERIOD); /* OTSCKPERIOD */ -+ writebitst(state, 0x00, 0x32, 0x00, 0x01); /* Disable TS IF */ ++ writebitst(state, 0x00, 0x32, 0x00, 0x01); /* Disable TS IF */ + /* OREG_CKSEL_TSIF */ -+ writebitst(state, 0x00, 0x33, OREG_CKSEL_TSIF, 0x03); -+ writebitst(state, 0x00, 0x32, 0x01, 0x01); /* Enable TS IF */ -+ -+ if (newDemodState == ActiveT) ++ writebitst(state, 0x00, 0x33, OREG_CKSEL_TSIF, 0x03); ++ writebitst(state, 0x00, 0x32, 0x01, 0x01); /* Enable TS IF */ ++ ++ if (newDemodState == ActiveT) + writebitst(state, 0x10, 0x66, 0x01, 0x01); -+ if (newDemodState == ActiveC) ++ if (newDemodState == ActiveC) + writebitst(state, 0x40, 0x66, 0x01, 0x01); -+ ++ + return status; +} + @@ -989,18 +1047,18 @@ index 0000000..5feea53 +{ + u8 IF_data[3] = { (iffreq >> 16) & 0xff, + (iffreq >> 8) & 0xff, iffreq & 0xff}; -+ -+ switch (state->bw) { ++ ++ switch (state->bw) { + default: + case 8: + { + u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; + u8 CL_data[] = { 0x01, 0xE0 }; + u8 NF_data[] = { 0x01, 0x02 }; -+ ++ + writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); -+ writebitst(state, 0x10, 0xD7, 0x00,0x07); ++ writebitst(state, 0x10, 0xD7, 0x00, 0x07); + writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data)); + writeregst(state, 0x17, 0x38, NF_data, sizeof(NF_data)); + break; @@ -1010,7 +1068,7 @@ index 0000000..5feea53 + u8 TR_data[] = { 0x14, 0x80, 0x00, 0x00, 0x00 }; + u8 CL_data[] = { 0x12, 0xF8 }; + u8 NF_data[] = { 0x00, 0x03 }; -+ ++ + writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); + writebitst(state, 0x10, 0xD7, 0x02, 0x07); @@ -1036,47 +1094,49 @@ index 0000000..5feea53 + static u8 TR_data[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 }; + static u8 CL_data[] = { 0x26, 0x3C }; + static u8 NF_data[] = { 0x00, 0x03 }; -+ ++ + writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); + writebitst(state, 0x10, 0xD7, 0x06, 0x07); + writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data)); + writeregst(state, 0x17, 0x38, NF_data, sizeof(NF_data)); -+ break; ++ break; + } + } +} + +static void Sleep_to_ActiveT(struct cxd_state *state, u32 iffreq) +{ -+ ConfigureTS(state, ActiveT); -+ writeregx(state, 0x00,0x17,0x01); /* Mode */ -+ writeregt(state, 0x00,0x2C,0x01); /* Demod Clock */ -+ writeregt(state, 0x00,0x2F,0x00); /* Disable RF Monitor */ -+ writeregt(state, 0x00,0x30,0x00); /* Enable ADC Clock */ -+ writeregt(state, 0x00,0x41,0x1A); /* Enable ADC1 */ ++ ConfigureTS(state, ActiveT); ++ writeregx(state, 0x00, 0x17, 0x01); /* Mode */ ++ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ ++ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ + { -+ u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ -+ /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ -+ writeregst(state, 0x00,0x43,data,2); /* Enable ADC 2+3 */ -+ } -+ writeregx(state, 0x00,0x18,0x00); /* Enable ADC 4 */ -+ -+ writebitst(state, 0x10, 0xD2, 0x0C, 0x1F); /* IF AGC Gain */ -+ writeregt(state, 0x11, 0x6A, 0x48); /* BB AGC Target Level */ ++ u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ ++ /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ ++ writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ ++ } ++ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ + -+ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ ++ writebitst(state, 0x10, 0xD2, 0x0C, 0x1F); /* IF AGC Gain */ ++ writeregt(state, 0x11, 0x6A, 0x48); /* BB AGC Target Level */ + -+ writebitst(state, 0x18, 0x36, 0x40, 0x07); /* Pre RS Monitoring */ -+ writebitst(state, 0x18, 0x30, 0x01, 0x01); /* FEC Autorecover */ -+ writebitst(state, 0x18, 0x31, 0x01, 0x01); /* FEC Autorecover */ ++ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ + -+ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ -+ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ ++ writebitst(state, 0x18, 0x36, 0x40, 0x07); /* Pre RS Monitoring */ ++ writebitst(state, 0x18, 0x30, 0x01, 0x01); /* FEC Autorecover */ ++ writebitst(state, 0x18, 0x31, 0x01, 0x01); /* FEC Autorecover */ + -+ BandSettingT(state, iffreq); ++ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ ++ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ + -+ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ ++ BandSettingT(state, iffreq); ++ ++ writebitst(state, 0x10, 0x60, 0x11, 0x1f); /* BER scaling */ ++ ++ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ + writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ +} + @@ -1085,7 +1145,7 @@ index 0000000..5feea53 + u8 IF_data[3] = {(iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, + iffreq & 0xff}; + -+ switch (state->bw) { ++ switch (state->bw) { + default: + case 8: + { @@ -1095,7 +1155,7 @@ index 0000000..5feea53 + /* Add EQ Optimisation for tuner here */ + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); + /* System Bandwidth */ -+ writebitst(state, 0x10, 0xD7, 0x00, 0x07); ++ writebitst(state, 0x10, 0xD7, 0x00, 0x07); + } + break; + case 7: @@ -1130,89 +1190,93 @@ index 0000000..5feea53 + writebitst(state, 0x10, 0xD7, 0x03, 0x07); + } + break; -+ } ++ } +} + + +static void Sleep_to_ActiveT2(struct cxd_state *state, u32 iffreq) +{ -+ ConfigureTS(state, ActiveT2); -+ -+ writeregx(state, 0x00, 0x17, 0x02); /* Mode */ -+ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ -+ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ -+ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ -+ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ ++ ConfigureTS(state, ActiveT2); + -+ { -+ u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ -+ /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ -+ writeregst(state, 0x00, 0x43,data,2); /* Enable ADC 2+3 */ -+ } -+ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ ++ writeregx(state, 0x00, 0x17, 0x02); /* Mode */ ++ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ ++ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ + -+ writebitst(state, 0x10, 0xD2, 0x0C, 0x1F); /* IFAGC coarse gain */ -+ writeregt(state, 0x11, 0x6A, 0x50); /* BB AGC Target Level */ -+ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ ++ { ++ u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ ++ /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ ++ writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ ++ } ++ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ + -+ writeregt(state, 0x20, 0x8B, 0x3C); /* SNR Good count */ -+ writebitst(state, 0x2B, 0x76, 0x20, 0x70); /* Noise Gain ACQ */ ++ writebitst(state, 0x10, 0xD2, 0x0C, 0x1F); /* IFAGC coarse gain */ ++ writeregt(state, 0x11, 0x6A, 0x50); /* BB AGC Target Level */ ++ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ + -+ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ -+ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ ++ writeregt(state, 0x20, 0x8B, 0x3C); /* SNR Good count */ ++ writebitst(state, 0x2B, 0x76, 0x20, 0x70); /* Noise Gain ACQ */ + -+ writeregt(state, 0x13, 0x83, 0x10); /* T2 Inital settings */ -+ writeregt(state, 0x13, 0x86, 0x34); -+ writebitst(state, 0x13, 0x9E, 0x09, 0x0F); -+ writeregt(state, 0x13, 0x9F, 0xD8); ++ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ ++ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ + -+ BandSettingT2(state, iffreq); ++ writeregt(state, 0x13, 0x83, 0x10); /* T2 Inital settings */ ++ writeregt(state, 0x13, 0x86, 0x34); ++ writebitst(state, 0x13, 0x9E, 0x09, 0x0F); ++ writeregt(state, 0x13, 0x9F, 0xD8); + -+ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ -+ writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ ++ BandSettingT2(state, iffreq); ++ ++ writebitst(state, 0x20, 0x72, 0x08, 0x0f); /* BER scaling */ ++ ++ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ ++ writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ +} + + +static void BandSettingC(struct cxd_state *state, u32 iffreq) +{ -+ u8 data[3]; ++ u8 data[3]; + -+ data[0] = (iffreq >> 16) & 0xFF; -+ data[1] = (iffreq >> 8) & 0xFF; -+ data[2] = (iffreq ) & 0xFF; -+ writeregst(state, 0x10, 0xB6, data, 3); ++ data[0] = (iffreq >> 16) & 0xFF; ++ data[1] = (iffreq >> 8) & 0xFF; ++ data[2] = (iffreq) & 0xFF; ++ writeregst(state, 0x10, 0xB6, data, 3); +} + +static void Sleep_to_ActiveC(struct cxd_state *state, u32 iffreq) +{ -+ ConfigureTS(state, ActiveC); -+ -+ writeregx(state, 0x00, 0x17, 0x04); /* Mode */ -+ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ -+ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ -+ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ -+ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ ++ ConfigureTS(state, ActiveC); + -+ { ++ writeregx(state, 0x00, 0x17, 0x04); /* Mode */ ++ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ ++ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ ++ ++ { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ -+ writeregst(state, 0x00, 0x43,data,2); /* Enable ADC 2+3 */ -+ } -+ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ ++ writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ ++ } ++ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ + -+ writebitst(state, 0x10, 0xD2, 0x09, 0x1F); /* IF AGC Gain */ -+ writeregt(state, 0x11, 0x6A, 0x48); /* BB AGC Target Level */ -+ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ ++ writebitst(state, 0x10, 0xD2, 0x09, 0x1F); /* IF AGC Gain */ ++ writeregt(state, 0x11, 0x6A, 0x48); /* BB AGC Target Level */ ++ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ + -+ writebitst(state, 0x40, 0xC3, 0x00, 0x04); /* OREG_BNDET_EN_64 */ ++ writebitst(state, 0x40, 0xC3, 0x00, 0x04); /* OREG_BNDET_EN_64 */ + -+ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ -+ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ ++ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ ++ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ + -+ BandSettingC(state, iffreq); ++ BandSettingC(state, iffreq); + -+ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ -+ writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ ++ writebitst(state, 0x40, 0x60, 0x11, 0x1f); /* BER scaling */ ++ ++ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ ++ writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ +} + +static void BandSettingC2(struct cxd_state *state, u32 iffreq) @@ -1220,7 +1284,7 @@ index 0000000..5feea53 + u8 IF_data[3] = { (iffreq >> 16) & 0xff, + (iffreq >> 8) & 0xff, iffreq & 0xff}; + -+ switch (state->bw) { ++ switch (state->bw) { + default: + case 8: + { @@ -1242,69 +1306,69 @@ index 0000000..5feea53 + + writeregst(state, 0x20, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); -+ writebitst(state, 0x10, 0xD7, 0x04, 0x07); ++ writebitst(state, 0x10, 0xD7, 0x04, 0x07); + writeregst(state, 0x50, 0xEC, data, sizeof(data)); + writeregt(state, 0x50, 0xEF, 0x17); + writeregt(state, 0x50, 0xF1, 0x70); + } + break; -+ } ++ } +} + +static void Sleep_to_ActiveC2(struct cxd_state *state, u32 iffreq) +{ -+ ConfigureTS(state, ActiveC2); ++ ConfigureTS(state, ActiveC2); + -+ writeregx(state, 0x00, 0x17, 0x05); /* Mode */ -+ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ -+ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ -+ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ -+ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ -+ -+ { ++ writeregx(state, 0x00, 0x17, 0x05); /* Mode */ ++ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ ++ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ ++ ++ { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ + writeregst(state, 0x00, 0x43, data, sizeof(data)); + /* Enable ADC 2+3 */ -+ } -+ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ ++ } ++ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ + + writebitst(state, 0x10, 0xD2, 0x0C, 0x1F); /* IFAGC coarse gain */ + writeregt(state, 0x11, 0x6A, 0x50); /* BB AGC Target Level */ -+ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ ++ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ + -+ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ -+ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ -+ -+ writeregt(state, 0x20, 0xC2, 0x00); -+ writebitst(state, 0x25,0x6A,0x00,0x03); ++ writebitst(state, 0x00, 0xCE, 0x01, 0x01); /* TSIF ONOPARITY */ ++ writebitst(state, 0x00, 0xCF, 0x01, 0x01);/*TSIF ONOPARITY_MANUAL_ON*/ ++ ++ writeregt(state, 0x20, 0xC2, 0x00); ++ writebitst(state, 0x25, 0x6A, 0x00, 0x03); + { + u8 data[3] = { 0x0C, 0xD1, 0x40 }; + writeregst(state, 0x25, 0x89, data, sizeof(data)); -+ } -+ writebitst(state, 0x25, 0xCB, 0x01, 0x07); -+ { ++ } ++ writebitst(state, 0x25, 0xCB, 0x01, 0x07); ++ { + u8 data[4] = { 0x7B, 0x00, 0x7B, 0x00 }; + writeregst(state, 0x25, 0xDC, data, sizeof(data)); -+ } -+ writeregt(state, 0x25, 0xE2, 0x30); -+ writeregt(state, 0x25, 0xE5, 0x30); -+ writebitst(state, 0x27, 0x20, 0x01, 0x01); -+ writebitst(state, 0x27, 0x35, 0x01, 0x01); -+ writebitst(state, 0x27, 0xD9, 0x18, 0x3F); -+ writebitst(state, 0x2A, 0x78, 0x00, 0x07); -+ writeregt(state, 0x2A, 0x86, 0x20); -+ writeregt(state, 0x2A, 0x88, 0x32); -+ writebitst(state, 0x2B, 0x2B, 0x10, 0x1F); -+ { ++ } ++ writeregt(state, 0x25, 0xE2, 0x30); ++ writeregt(state, 0x25, 0xE5, 0x30); ++ writebitst(state, 0x27, 0x20, 0x01, 0x01); ++ writebitst(state, 0x27, 0x35, 0x01, 0x01); ++ writebitst(state, 0x27, 0xD9, 0x18, 0x3F); ++ writebitst(state, 0x2A, 0x78, 0x00, 0x07); ++ writeregt(state, 0x2A, 0x86, 0x20); ++ writeregt(state, 0x2A, 0x88, 0x32); ++ writebitst(state, 0x2B, 0x2B, 0x10, 0x1F); ++ { + u8 data[2] = { 0x01, 0x01 }; + writeregst(state, 0x2D, 0x24, data, sizeof(data)); -+ } ++ } + -+ BandSettingC2(state, iffreq); -+ -+ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ -+ writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ ++ BandSettingC2(state, iffreq); ++ ++ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ ++ writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ +} + + @@ -1313,7 +1377,7 @@ index 0000000..5feea53 + u8 IF_data[3] = { (iffreq >> 16) & 0xff, + (iffreq >> 8) & 0xff, iffreq & 0xff}; + -+ switch (state->bw) { ++ switch (state->bw) { + default: + case 8: + { @@ -1321,13 +1385,13 @@ index 0000000..5feea53 + u8 CL_data[] = { 0x15, 0xA8 }; + + /*u8 TR_data[] = { 0x11, 0xB8, 0x00, 0x00, 0x00 }; */ /* 24 */ -+ writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); ++ writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data)); + /* Add EQ Optimisation for tuner here */ -+ writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); -+ -+ writeregt(state, 0x10,0xD7,0x00); /* System Bandwidth */ ++ writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); ++ ++ writeregt(state, 0x10, 0xD7, 0x00); /* System Bandwidth */ + /*u8 CL_data[] = { 0x13, 0xFC }; */ -+ writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); ++ writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data)); + } + break; + case 7: @@ -1336,12 +1400,12 @@ index 0000000..5feea53 + u8 CL_data[] = { 0x1B, 0x5D }; + + /*u8 TR_data[] = { 0x14, 0x40, 0x00, 0x00, 0x00 }; */ -+ writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); -+ writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); -+ -+ writeregt(state, 0x10,0xD7,0x02); ++ writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data)); ++ writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); ++ ++ writeregt(state, 0x10, 0xD7, 0x02); + /*static u8 CL_data[] = { 0x1A, 0xFA };*/ -+ writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); ++ writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data)); + } + break; + case 6: @@ -1350,148 +1414,150 @@ index 0000000..5feea53 + u8 CL_data[] = { 0x1F, 0xEC }; + /*u8 TR_data[] = { 0x17, 0xA0, 0x00, 0x00, 0x00 }; */ + /*u8 CL_data[] = { 0x1F, 0x79 }; */ -+ -+ writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); -+ writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); -+ writeregt(state, 0x10,0xD7,0x04); ++ ++ writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data)); ++ writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); ++ writeregt(state, 0x10, 0xD7, 0x04); + writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data)); + } + break; -+ } ++ } +} + +static void Sleep_to_ActiveIT(struct cxd_state *state, u32 iffreq) +{ -+ u8 data2[3] = { 0xB9,0xBA,0x63 }; /* 20.5/41 MHz */ -+ /*u8 data2[3] = { 0xB7,0x1B,0x00 }; */ /* 24 MHz */ -+ u8 TSIF_data[2] = { 0x61,0x60 } ; /* 20.5/41 MHz */ -+ /*u8 TSIF_data[2] = { 0x60,0x00 } ; */ /* 24 MHz */ ++ u8 data2[3] = { 0xB9, 0xBA, 0x63 }; /* 20.5/41 MHz */ ++ /*u8 data2[3] = { 0xB7,0x1B,0x00 }; */ /* 24 MHz */ ++ u8 TSIF_data[2] = { 0x61, 0x60 } ; /* 20.5/41 MHz */ ++ /*u8 TSIF_data[2] = { 0x60,0x00 } ; */ /* 24 MHz */ + -+ printk("%s\n", __FUNCTION__); ++ pr_info("%s\n", __func__); + -+ ConfigureTS(state, ActiveIT); -+ -+ /* writeregx(state, 0x00,0x17,0x01); */ /* 2838 has only one Mode */ -+ writeregt(state, 0x00,0x2C,0x01); /* Demod Clock */ -+ writeregt(state, 0x00,0x2F,0x00); /* Disable RF Monitor */ -+ writeregt(state, 0x00,0x30,0x00); /* Enable ADC Clock */ -+ writeregt(state, 0x00,0x41,0x1A); /* Enable ADC1 */ -+ -+ { ++ ConfigureTS(state, ActiveIT); ++ ++ /* writeregx(state, 0x00,0x17,0x01); */ /* 2838 has only one Mode */ ++ writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */ ++ writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */ ++ writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */ ++ writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */ ++ ++ { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz, 24 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ -+ writeregst(state, 0x00,0x43,data,2); /* Enable ADC 2+3 */ -+ } -+ writeregx(state, 0x00,0x18,0x00); /* Enable ADC 4 */ ++ writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ ++ } ++ writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ + -+ writeregst(state, 0x60,0xA8,data2,sizeof(data2)); ++ writeregst(state, 0x60, 0xA8, data2, sizeof(data2)); + -+ writeregst(state, 0x10,0xBF,TSIF_data,sizeof(TSIF_data)); ++ writeregst(state, 0x10, 0xBF, TSIF_data, sizeof(TSIF_data)); + -+ writeregt(state, 0x10,0xE2,0xCE); /* OREG_PNC_DISABLE */ -+ writebitst(state, 0x10,0xA5,0x00,0x01); /* ASCOT Off */ -+ -+ BandSettingIT(state, iffreq); ++ writeregt(state, 0x10, 0xE2, 0xCE); /* OREG_PNC_DISABLE */ ++ writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */ + -+ writeregt(state, 0x00,0x80,0x28); /* Disable HiZ Setting 1 */ -+ writeregt(state, 0x00,0x81,0x00); /* Disable HiZ Setting 2 */ ++ BandSettingIT(state, iffreq); ++ ++ writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */ ++ writeregt(state, 0x00, 0x81, 0x00); /* Disable HiZ Setting 2 */ +} + +static void T2_SetParameters(struct cxd_state *state) +{ -+ u8 Profile = 0x01; /* Profile Base */ -+ u8 notT2time = 12; /* early unlock detection time */ -+ -+ /*u8 Profile = 0x05; Lite */ -+ /*u8 notT2time = 40;*/ -+ -+ /*u8 Profile = 0x00; any*/ -+ /*u8 notT2time = 40;*/ -+ -+ -+ if (state->plp != 0xffffffff) { ++ u8 Profile = 0x01; /* Profile Base */ ++ u8 notT2time = 12; /* early unlock detection time */ ++ ++ if (state->T2Profile == T2P_Lite) { ++ Profile = 0x05; ++ notT2time = 40; ++ } ++ ++ if (state->plp != 0xffffffff) { ++ state->T2Profile = ((state->plp & 0x100) != 0) ? ++ T2P_Lite : T2P_Base; + writeregt(state, 0x23, 0xAF, state->plp); + writeregt(state, 0x23, 0xAD, 0x01); + } else { ++ state->T2Profile = T2P_Base; + writeregt(state, 0x23, 0xAD, 0x00); -+ } -+ -+ writebitst(state, 0x2E, 0x10, Profile, 0x07); ++ } ++ ++ writebitst(state, 0x2E, 0x10, Profile, 0x07); + writeregt(state, 0x2B, 0x19, notT2time); +} + +static void C2_ReleasePreset(struct cxd_state *state) +{ -+ { ++ { + static u8 data[2] = { 0x02, 0x80}; -+ writeregst(state, 0x27,0xF4,data,sizeof(data)); ++ writeregst(state, 0x27, 0xF4, data, sizeof(data)); + } -+ writebitst(state, 0x27,0x51,0x40,0xF0); -+ writebitst(state, 0x27,0x73,0x07,0x0F); -+ writebitst(state, 0x27,0x74,0x19,0x3F); -+ writebitst(state, 0x27,0x75,0x19,0x3F); -+ writebitst(state, 0x27,0x76,0x19,0x3F); -+ if (state->bw == 6 ) { ++ writebitst(state, 0x27, 0x51, 0x40, 0xF0); ++ writebitst(state, 0x27, 0x73, 0x07, 0x0F); ++ writebitst(state, 0x27, 0x74, 0x19, 0x3F); ++ writebitst(state, 0x27, 0x75, 0x19, 0x3F); ++ writebitst(state, 0x27, 0x76, 0x19, 0x3F); ++ if (state->bw == 6) { + static u8 data[5] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA}; + writeregst(state, 0x20, 0x9F, data, sizeof(data)); -+ } else { ++ } else { + static u8 data[5] = { 0x11, 0xF0, 0x00, 0x00, 0x00}; + writeregst(state, 0x20, 0x9F, data, sizeof(data)); -+ } -+ writebitst(state, 0x27,0xC9,0x07,0x07); -+ writebitst(state, 0x20,0xC2,0x11,0x33); -+ { ++ } ++ writebitst(state, 0x27, 0xC9, 0x07, 0x07); ++ writebitst(state, 0x20, 0xC2, 0x11, 0x33); ++ { + static u8 data[10] = { 0x16, 0xF0, 0x2B, 0xD8, + 0x16, 0x16, 0xF0, 0x2C, 0xD8, 0x16 }; + writeregst(state, 0x2A, 0x20, data, sizeof(data)); -+ } -+ { ++ } ++ { + static u8 data[4] = { 0x00, 0x00, 0x00, 0x00 }; + writeregst(state, 0x50, 0x6B, data, sizeof(data)); -+ } -+ writebitst(state, 0x50,0x6F,0x00,0x40); /* Disable Preset */ ++ } ++ writebitst(state, 0x50, 0x6F, 0x00, 0x40); /* Disable Preset */ +} + +static void C2_DemodSetting2(struct cxd_state *state) +{ + u8 data[6]; -+ u32 TunePosition = ++ u32 TunePosition = + state->frontend.dtv_property_cache.frequency / 1000; -+ -+ if (state->bw == 6) ++ ++ if (state->bw == 6) + TunePosition = ((TunePosition * 1792) / 3) / 1000; -+ else ++ else + TunePosition = (TunePosition * 448) / 1000; + -+ TunePosition = ((TunePosition + 6) / 12) * 12; ++ TunePosition = ((TunePosition + 6) / 12) * 12; + -+ printk("TunePosition = %u\n", TunePosition); ++ pr_info("TunePosition = %u\n", TunePosition); + -+ data[0] = ( (TunePosition >> 16) & 0xFF ); -+ data[1] = ( (TunePosition >> 8) & 0xFF ); -+ data[2] = ( (TunePosition ) & 0xFF ); -+ data[3] = 0x02; -+ data[4] = (state->DataSliceID & 0xFF); -+ data[5] = (state->plp & 0xFF); -+ writeregst(state, 0x50, 0x7A, data, sizeof(data)); -+ writebitst(state, 0x50, 0x87, 0x01, 0x01); /* Preset Clear */ ++ data[0] = ((TunePosition >> 16) & 0xFF); ++ data[1] = ((TunePosition >> 8) & 0xFF); ++ data[2] = (TunePosition & 0xFF); ++ data[3] = 0x02; ++ data[4] = (state->DataSliceID & 0xFF); ++ data[5] = (state->plp & 0xFF); ++ writeregst(state, 0x50, 0x7A, data, sizeof(data)); ++ writebitst(state, 0x50, 0x87, 0x01, 0x01); /* Preset Clear */ +} + +static void Stop(struct cxd_state *state) +{ -+ writeregt(state, 0x00,0xC3,0x01); /* Disable TS */ ++ ++ writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */ +} + +static void ShutDown(struct cxd_state *state) +{ + switch (state->state) { -+ case ActiveT2: ++ case ActiveT2: + ActiveT2_to_Sleep(state); + break; -+ case ActiveC2: ++ case ActiveC2: + ActiveC2_to_Sleep(state); + break; -+ default: ++ default: + Active_to_Sleep(state); + break; + } @@ -1500,11 +1566,11 @@ index 0000000..5feea53 +static int gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct cxd_state *state = fe->demodulator_priv; -+ ++ + return writebitsx(state, 0xFF, 0x08, enable ? 0x01 : 0x00, 0x01); +} + -+static void release(struct dvb_frontend* fe) ++static void release(struct dvb_frontend *fe) +{ + struct cxd_state *state = fe->demodulator_priv; + @@ -1517,60 +1583,71 @@ index 0000000..5feea53 +{ + enum EDemodState newDemodState = Unknown; + u32 iffreq; -+ -+ if (state->state < Sleep ) { ++ ++ if (state->state < Sleep) + return -EINVAL; -+ } -+ ++ + iffreq = MulDiv32(IntermediateFrequency, 16777216, 41000000); + -+ switch(state->omode) { -+ case OM_DVBT: -+ if (state->type == CXD2838 ) ++ switch (state->omode) { ++ case OM_DVBT: ++ if (state->type == CXD2838) + return -EINVAL; -+ newDemodState = ActiveT; ++ newDemodState = ActiveT; + break; -+ case OM_DVBT2: -+ if (state->type == CXD2838 ) ++ case OM_DVBT2: ++ if (state->type == CXD2838) + return -EINVAL; -+ newDemodState = ActiveT2; ++ newDemodState = ActiveT2; + break; -+ case OM_DVBC: -+ case OM_QAM_ITU_C: -+ if (state->type == CXD2838 ) ++ case OM_DVBC: ++ case OM_QAM_ITU_C: ++ if (state->type == CXD2838) + return -EINVAL; -+ newDemodState = ActiveC; ++ newDemodState = ActiveC; + break; -+ case OM_ISDBT: -+ if (state->type != CXD2838 ) ++ case OM_DVBC2: ++ if (state->type != CXD2843) + return -EINVAL; -+ newDemodState = ActiveIT; ++ newDemodState = ActiveC2; + break; -+ default: ++ case OM_ISDBT: ++ if (state->type != CXD2838) ++ return -EINVAL; ++ newDemodState = ActiveIT; ++ break; ++ default: + return -EINVAL; + } -+ ++ + state->LockTimeout = 0; + state->TSLockTimeout = 0; + state->L1PostTimeout = 0; ++ state->last_status = 0; + state->FirstTimeLock = 1; -+ -+ if (state->state == newDemodState ) { ++ state->LastBERNominator = 0; ++ state->LastBERDenominator = 1; ++ state->BERScaleMax = 19; ++ ++ if (state->state == newDemodState) { + writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS Output */ + switch (newDemodState) { -+ case ActiveT: ++ case ActiveT: + /* Stick with HP ( 0x01 = LP ) */ -+ writeregt(state, 0x10,0x67, 0x00); -+ BandSettingT(state, iffreq); ++ writeregt(state, 0x10, 0x67, 0x00); ++ BandSettingT(state, iffreq); ++ state->BERScaleMax = 18; + break; -+ case ActiveT2: ++ case ActiveT2: + T2_SetParameters(state); + BandSettingT2(state, iffreq); ++ state->BERScaleMax = 12; + break; + case ActiveC: + BandSettingC(state, iffreq); ++ state->BERScaleMax = 19; + break; -+ case ActiveC2: ++ case ActiveC2: + BandSettingC2(state, iffreq); + C2_ReleasePreset(state); + C2_DemodSetting2(state); @@ -1582,12 +1659,12 @@ index 0000000..5feea53 + break; + } + } else { -+ if (state->state > Sleep ) { ++ if (state->state > Sleep) { + switch (state->state) { -+ case ActiveT2: ++ case ActiveT2: + ActiveT2_to_Sleep(state); + break; -+ case ActiveC2: ++ case ActiveC2: + ActiveC2_to_Sleep(state); + break; + default: @@ -1596,17 +1673,20 @@ index 0000000..5feea53 + } + } + switch (newDemodState) { -+ case ActiveT: ++ case ActiveT: + /* Stick with HP ( 0x01 = LP ) */ -+ writeregt(state, 0x10,0x67, 0x00); -+ Sleep_to_ActiveT(state, iffreq); ++ writeregt(state, 0x10, 0x67, 0x00); ++ Sleep_to_ActiveT(state, iffreq); ++ state->BERScaleMax = 18; + break; -+ case ActiveT2: ++ case ActiveT2: + T2_SetParameters(state); + Sleep_to_ActiveT2(state, iffreq); ++ state->BERScaleMax = 12; + break; -+ case ActiveC: ++ case ActiveC: + Sleep_to_ActiveC(state, iffreq); ++ state->BERScaleMax = 19; + break; + case ActiveC2: + Sleep_to_ActiveC2(state, iffreq); @@ -1619,11 +1699,11 @@ index 0000000..5feea53 + default: + break; + } -+ } ++ } + state->state = newDemodState; + writeregt(state, 0x00, 0xFE, 0x01); /* SW Reset */ + writeregt(state, 0x00, 0xC3, 0x00); /* Enable TS Output */ -+ ++ + return 0; +} + @@ -1661,7 +1741,7 @@ index 0000000..5feea53 + & 0xff; + state->plp = fe->dtv_property_cache.stream_id & 0xff; + } -+ //printk("PLP = %08x, bw = %u\n", state->plp, state->bw); ++ /* printk("PLP = %08x, bw = %u\n", state->plp, state->bw); */ + fe->ops.tuner_ops.get_if_frequency(fe, &IF); + stat = Start(state, IF); + return stat; @@ -1670,42 +1750,49 @@ index 0000000..5feea53 + +static void init(struct cxd_state *state) +{ -+ u8 data[2] = {0x00, 0x00}; /* 20.5 MHz */ ++ u8 data[2] = {0x00, 0x00}; /* 20.5 MHz */ + + state->omode = OM_NONE; + state->state = Unknown; + + writeregx(state, 0xFF, 0x02, 0x00); -+ msleep(4); ++ usleep_range(4000, 5000); ++ writeregx(state, 0x00, 0x15, 0x01); ++ writeregx(state, 0x00, 0x17, 0x01); ++ usleep_range(4000, 5000); ++ + writeregx(state, 0x00, 0x10, 0x01); -+ ++ + writeregsx(state, 0x00, 0x13, data, 2); -+ writeregx(state, 0x00, 0x10, 0x00); -+ msleep(2); -+ state->curbankx = 0xFF; -+ state->curbankt = 0xFF; -+ -+ writeregt(state, 0x00, 0x43, 0x0A); -+ writeregt(state, 0x00, 0x41, 0x0A); -+ if (state->type == CXD2838) ++ writeregx(state, 0x00, 0x15, 0x00); ++ usleep_range(3000, 4000); ++ writeregx(state, 0x00, 0x10, 0x00); ++ usleep_range(2000, 3000); ++ ++ state->curbankx = 0xFF; ++ state->curbankt = 0xFF; ++ ++ writeregt(state, 0x00, 0x43, 0x0A); ++ writeregt(state, 0x00, 0x41, 0x0A); ++ if (state->type == CXD2838) + writeregt(state, 0x60, 0x5A, 0x00); -+ -+ writebitst(state, 0x10, 0xCB, 0x00, 0x40); -+ writeregt(state, 0x10, 0xCD, state->IF_FS); + -+ writebitst(state, 0x00, 0xC4, 0x80, 0x98); -+ writebitst(state, 0x00, 0xC5, 0x00, 0x07); -+ writebitst(state, 0x00, 0xCB, 0x00, 0x01); -+ writebitst(state, 0x00, 0xC6, 0x00, 0x1D); -+ writebitst(state, 0x00, 0xC8, 0x00, 0x1D); -+ writebitst(state, 0x00, 0xC9, 0x00, 0x1D); -+ writebitst(state, 0x00, 0x83, 0x00, 0x07); ++ writebitst(state, 0x10, 0xCB, 0x00, 0x40); ++ writeregt(state, 0x10, 0xCD, state->IF_FS); ++ ++ writebitst(state, 0x00, 0xC4, state->SerialMode ? 0x80 : 0x00, 0x98); ++ writebitst(state, 0x00, 0xC5, 0x01, 0x07); ++ writebitst(state, 0x00, 0xCB, 0x00, 0x01); ++ writebitst(state, 0x00, 0xC6, 0x00, 0x1D); ++ writebitst(state, 0x00, 0xC8, 0x01, 0x1D); ++ writebitst(state, 0x00, 0xC9, 0x00, 0x1D); ++ writebitst(state, 0x00, 0x83, 0x00, 0x07); + writeregt(state, 0x00, 0x84, 0x00); -+ writebitst(state, 0x00, 0xD3, ++ writebitst(state, 0x00, 0xD3, + (state->type == CXD2838) ? 0x01 : 0x00, 0x01); -+ writebitst(state, 0x00, 0xDE, 0x00, 0x01); ++ writebitst(state, 0x00, 0xDE, 0x00, 0x01); + -+ state->state = Sleep; ++ state->state = Sleep; +} + + @@ -1715,17 +1802,16 @@ index 0000000..5feea53 + state->adrx = cfg->adr + 0x02; + state->curbankt = 0xff; + state->curbankx = 0xff; -+ + mutex_init(&state->mutex); + -+ state->SerialMode = 1; ++ state->SerialMode = cfg->parallel ? 0 : 1; + state->ContinuousClock = 1; -+ state->SerialClockFrequency = -+ (cfg->ts_clock >= 1 && cfg->ts_clock <= 5) ? ++ state->SerialClockFrequency = ++ (cfg->ts_clock >= 1 && cfg->ts_clock <= 5) ? + cfg->ts_clock : 1; /* 1 = fastest (82 MBit/s), 5 = slowest */ + state->SerialClockFrequency = 1; + /* IF Fullscale 0x50 = 1.4V, 0x39 = 1V, 0x28 = 0.7V */ -+ state->IF_FS = 0x50; ++ state->IF_FS = 0x50; +} + +static int get_tune_settings(struct dvb_frontend *fe, @@ -1745,12 +1831,12 @@ index 0000000..5feea53 +{ + struct cxd_state *state = fe->demodulator_priv; + u8 rdata; -+ -+ *status=0; ++ ++ *status = 0; + switch (state->state) { -+ case ActiveC: ++ case ActiveC: + readregst(state, 0x40, 0x88, &rdata, 1); -+ if (rdata & 0x02) ++ if (rdata & 0x02) + break; + if (rdata & 0x01) { + *status |= 0x07; @@ -1760,8 +1846,8 @@ index 0000000..5feea53 + } + break; + case ActiveT: -+ readregst(state, 0x10, 0x10, &rdata, 1) ; -+ if (rdata & 0x10) ++ readregst(state, 0x10, 0x10, &rdata, 1); ++ if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { + *status |= 0x07; @@ -1771,7 +1857,7 @@ index 0000000..5feea53 + break; + case ActiveT2: + readregst(state, 0x20, 0x10, &rdata, 1); -+ if (rdata & 0x10) ++ if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { + *status |= 0x07; @@ -1786,7 +1872,7 @@ index 0000000..5feea53 + break; + case ActiveC2: + readregst(state, 0x20, 0x10, &rdata, 1); -+ if (rdata & 0x10) ++ if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { + *status |= 0x07; @@ -1795,7 +1881,7 @@ index 0000000..5feea53 + } + if ((*status & 0x10) && state->FirstTimeLock) { + u8 data; -+ ++ + /* Change1stTrial */ + readregst(state, 0x28, 0xE6, &rdata, 1); + data = rdata & 1; @@ -1807,7 +1893,7 @@ index 0000000..5feea53 + break; + case ActiveIT: + readregst(state, 0x60, 0x10, &rdata, 1); -+ if (rdata & 0x10) ++ if (rdata & 0x10) + break; + if (rdata & 0x02) { + *status |= 0x07; @@ -1815,18 +1901,119 @@ index 0000000..5feea53 + *status |= 0x18; + } + break; -+ default: ++ default: + break; + } + state->last_status = *status; + return 0; +} + ++static int get_ber_t(struct cxd_state *state, u32 *n, u32 *d) ++{ ++ u8 BERRegs[3]; ++ u8 Scale; ++ ++ *n = 0; ++ *d = 1; ++ ++ readregst(state, 0x10, 0x62, BERRegs, 3); ++ readregst(state, 0x10, 0x60, &Scale, 1); ++ Scale &= 0x1F; ++ ++ if (BERRegs[0] & 0x80) { ++ state->LastBERNominator = (((u32) BERRegs[0] & 0x3F) << 16) | ++ (((u32) BERRegs[1]) << 8) | BERRegs[2]; ++ state->LastBERDenominator = 1632 << Scale; ++ if (state->LastBERNominator < 256 && ++ Scale < state->BERScaleMax) { ++ writebitst(state, 0x10, 0x60, Scale + 1, 0x1F); ++ } else if (state->LastBERNominator > 512 && Scale > 11) ++ writebitst(state, 0x10, 0x60, Scale - 1, 0x1F); ++ } ++ *n = state->LastBERNominator; ++ *d = state->LastBERDenominator; ++ ++ return 0; ++} ++ ++static int get_ber_t2(struct cxd_state *state, u32 *n, u32 *d) ++{ ++ *n = 0; ++ *d = 1; ++ return 0; ++} ++ ++static int get_ber_c(struct cxd_state *state, u32 *n, u32 *d) ++{ ++ u8 BERRegs[3]; ++ u8 Scale; ++ ++ *n = 0; ++ *d = 1; ++ ++ readregst(state, 0x40, 0x62, BERRegs, 3); ++ readregst(state, 0x40, 0x60, &Scale, 1); ++ Scale &= 0x1F; ++ ++ if (BERRegs[0] & 0x80) { ++ state->LastBERNominator = (((u32) BERRegs[0] & 0x3F) << 16) | ++ (((u32) BERRegs[1]) << 8) | BERRegs[2]; ++ state->LastBERDenominator = 1632 << Scale; ++ if (state->LastBERNominator < 256 && ++ Scale < state->BERScaleMax) { ++ writebitst(state, 0x40, 0x60, Scale + 1, 0x1F); ++ } else if (state->LastBERNominator > 512 && Scale > 11) ++ writebitst(state, 0x40, 0x60, Scale - 1, 0x1F); ++ } ++ *n = state->LastBERNominator; ++ *d = state->LastBERDenominator; ++ ++ return 0; ++} ++ ++static int get_ber_c2(struct cxd_state *state, u32 *n, u32 *d) ++{ ++ *n = 0; ++ *d = 1; ++ return 0; ++} ++ ++static int get_ber_it(struct cxd_state *state, u32 *n, u32 *d) ++{ ++ *n = 0; ++ *d = 1; ++ return 0; ++} ++ +static int read_ber(struct dvb_frontend *fe, u32 *ber) +{ -+ /*struct cxd_state *state = fe->demodulator_priv;*/ ++ struct cxd_state *state = fe->demodulator_priv; ++ u32 n, d; ++ int s = 0; + + *ber = 0; ++ switch (state->state) { ++ case ActiveT: ++ s = get_ber_t(state, &n, &d); ++ break; ++ case ActiveT2: ++ s = get_ber_t2(state, &n, &d); ++ break; ++ case ActiveC: ++ s = get_ber_c(state, &n, &d); ++ break; ++ case ActiveC2: ++ s = get_ber_c2(state, &n, &d); ++ break; ++ case ActiveIT: ++ s = get_ber_it(state, &n, &d); ++ break; ++ default: ++ break; ++ } ++ if (s) ++ return s; ++ + return 0; +} + @@ -1890,29 +2077,29 @@ index 0000000..5feea53 + u8 *Values, u32 *Returned) +{ + u8 nPids = 0; -+ ++ + *Returned = 0; -+ if (state->state != ActiveT2 ) ++ if (state->state != ActiveT2) + return; + if (state->last_status != 0x1f) + return; -+ ++ + freeze_regst(state); + readregst_unlocked(state, 0x22, 0x7F, &nPids, 1); -+ ++ + Values[0] = nPids; -+ if( nPids >= nValues ) ++ if (nPids >= nValues) + nPids = nValues - 1; -+ ++ + readregst_unlocked(state, 0x22, 0x80, &Values[1], + nPids > 128 ? 128 : nPids); -+ -+ if( nPids > 128 ) ++ ++ if (nPids > 128) + readregst_unlocked(state, 0x23, 0x10, &Values[129], + nPids - 128); -+ -+ *Returned = nPids + 1; -+ ++ ++ *Returned = nPids + 1; ++ + unfreeze_regst(state); +} +#endif @@ -1921,21 +2108,21 @@ index 0000000..5feea53 +{ + u8 Data[2]; + u32 reg; -+ ++ + freeze_regst(state); + readregst_unlocked(state, 0x60, 0x28, Data, sizeof(Data)); + unfreeze_regst(state); + -+ reg = (Data[0] << 8) | Data[1]; -+ if (reg > 51441) ++ reg = (Data[0] << 8) | Data[1]; ++ if (reg > 51441) + reg = 51441; + -+ if (state->bw == 8) { ++ if (state->bw == 8) { + if (reg > 1143) + reg = 1143; + *SignalToNoise = (Log10x100(reg) - + Log10x100(1200 - reg)) + 220; -+ } else ++ } else + *SignalToNoise = Log10x100(reg) - 90; +} + @@ -1943,16 +2130,16 @@ index 0000000..5feea53 +{ + u8 Data[2]; + u32 reg; -+ ++ + freeze_regst(state); + readregst_unlocked(state, 0x20, 0x28, Data, sizeof(Data)); + unfreeze_regst(state); + -+ reg = (Data[0] << 8) | Data[1]; -+ if (reg > 51441) ++ reg = (Data[0] << 8) | Data[1]; ++ if (reg > 51441) + reg = 51441; + -+ *SignalToNoise = (Log10x100(reg) - Log10x100(55000 - reg)) + 384; ++ *SignalToNoise = (Log10x100(reg) - Log10x100(55000 - reg)) + 384; +} + + @@ -1960,16 +2147,16 @@ index 0000000..5feea53 +{ + u8 Data[2]; + u32 reg; -+ ++ + freeze_regst(state); + readregst_unlocked(state, 0x20, 0x28, Data, sizeof(Data)); + unfreeze_regst(state); -+ -+ reg = (Data[0] << 8) | Data[1]; -+ if (reg > 10876) ++ ++ reg = (Data[0] << 8) | Data[1]; ++ if (reg > 10876) + reg = 10876; -+ -+ *SignalToNoise = (Log10x100(reg) - Log10x100(12600 - reg)) + 320; ++ ++ *SignalToNoise = (Log10x100(reg) - Log10x100(12600 - reg)) + 320; +} + +static void GetSignalToNoiseT(struct cxd_state *state, u32 *SignalToNoise) @@ -1981,11 +2168,11 @@ index 0000000..5feea53 + readregst_unlocked(state, 0x10, 0x28, Data, sizeof(Data)); + unfreeze_regst(state); + -+ reg = (Data[0] << 8) | Data[1]; -+ if (reg > 4996) ++ reg = (Data[0] << 8) | Data[1]; ++ if (reg > 4996) + reg = 4996; + -+ *SignalToNoise = (Log10x100(reg) - Log10x100(5350 - reg)) + 285; ++ *SignalToNoise = (Log10x100(reg) - Log10x100(5350 - reg)) + 285; +} + +static void GetSignalToNoiseC(struct cxd_state *state, u32 *SignalToNoise) @@ -1995,31 +2182,31 @@ index 0000000..5feea53 + u32 reg; + + *SignalToNoise = 0; -+ ++ + freeze_regst(state); + readregst_unlocked(state, 0x40, 0x19, &Constellation, 1); + readregst_unlocked(state, 0x40, 0x4C, Data, sizeof(Data)); + unfreeze_regst(state); + + reg = ((u32)(Data[0] & 0x1F) << 8) | (Data[1]); -+ if (reg == 0) ++ if (reg == 0) + return; + -+ switch (Constellation & 0x07) { ++ switch (Constellation & 0x07) { + case 0: /* QAM 16 */ + case 2: /* QAM 64 */ + case 4: /* QAM 256 */ -+ if (reg < 126) ++ if (reg < 126) + reg = 126; -+ *SignalToNoise = ((439 - Log10x100(reg)) * 2134 + 500) / 1000; -+ break; ++ *SignalToNoise = ((439 - Log10x100(reg)) * 2134 + 500) / 1000; ++ break; + case 1: /* QAM 32 */ + case 3: /* QAM 128 */ -+ if (reg < 69) ++ if (reg < 69) + reg = 69; -+ *SignalToNoise = ((432 - Log10x100(reg)) * 2015 + 500) / 1000; -+ break; -+ } ++ *SignalToNoise = ((432 - Log10x100(reg)) * 2015 + 500) / 1000; ++ break; ++ } +} + +static int read_snr(struct dvb_frontend *fe, u16 *snr) @@ -2029,22 +2216,22 @@ index 0000000..5feea53 + + *snr = 0; + if (state->last_status != 0x1f) -+ return 0; ++ return 0; + + switch (state->state) { -+ case ActiveC: ++ case ActiveC: + GetSignalToNoiseC(state, &SNR); + break; -+ case ActiveC2: ++ case ActiveC2: + GetSignalToNoiseC2(state, &SNR); + break; -+ case ActiveT: ++ case ActiveT: + GetSignalToNoiseT(state, &SNR); + break; -+ case ActiveT2: ++ case ActiveT2: + GetSignalToNoiseT2(state, &SNR); + break; -+ case ActiveIT: ++ case ActiveIT: + GetSignalToNoiseIT(state, &SNR); + break; + default: @@ -2060,25 +2247,25 @@ index 0000000..5feea53 + return 0; +} + -+static int tune(struct dvb_frontend* fe, bool re_tune, ++static int tune(struct dvb_frontend *fe, bool re_tune, + unsigned int mode_flags, + unsigned int *delay, fe_status_t *status) +{ + struct cxd_state *state = fe->demodulator_priv; + int r; -+ ++ + if (re_tune) { + r = set_parameters(fe); + if (r) + return r; + state->tune_time = jiffies; -+ ++ + } + if (*status & FE_HAS_LOCK) + return 0; + /* *delay = 50; */ + r = read_status(fe, status); -+ if (r) ++ if (r) + return r; + return 0; +} @@ -2094,7 +2281,7 @@ index 0000000..5feea53 + for (i = 0; i < loops; i++) { + msleep(50); + r = read_status(fe, &status); -+ if (r) ++ if (r) + return DVBFE_ALGO_SEARCH_ERROR; + if (status & FE_HAS_LOCK) + break; @@ -2111,6 +2298,147 @@ index 0000000..5feea53 + return DVBFE_ALGO_HW; +} + ++static int get_fe_t(struct cxd_state *state) ++{ ++ struct dvb_frontend *fe = &state->frontend; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ u8 tps[7]; ++ ++ read_tps(state, tps); ++ ++/* TPSData[0] [7:6] CNST[1:0] ++ TPSData[0] [5:3] HIER[2:0] ++ TPSData[0] [2:0] HRATE[2:0] ++*/ ++ switch ((tps[0] >> 6) & 0x03) { ++ case 0: ++ p->modulation = QPSK; ++ break; ++ case 1: ++ p->modulation = QAM_16; ++ break; ++ case 2: ++ p->modulation = QAM_64; ++ break; ++ } ++ switch ((tps[0] >> 3) & 0x07) { ++ case 0: ++ p->hierarchy = HIERARCHY_NONE; ++ break; ++ case 1: ++ p->hierarchy = HIERARCHY_1; ++ break; ++ case 2: ++ p->hierarchy = HIERARCHY_2; ++ break; ++ case 3: ++ p->hierarchy = HIERARCHY_4; ++ break; ++ } ++ switch ((tps[0] >> 0) & 0x07) { ++ case 0: ++ p->code_rate_HP = FEC_1_2; ++ break; ++ case 1: ++ p->code_rate_HP = FEC_2_3; ++ break; ++ case 2: ++ p->code_rate_HP = FEC_3_4; ++ break; ++ case 3: ++ p->code_rate_HP = FEC_5_6; ++ break; ++ case 4: ++ p->code_rate_HP = FEC_7_8; ++ break; ++ } ++ ++/* TPSData[1] [7:5] LRATE[2:0] ++ TPSData[1] [4:3] GI[1:0] ++ TPSData[1] [2:1] MODE[1:0] ++*/ ++ switch ((tps[1] >> 5) & 0x07) { ++ case 0: ++ p->code_rate_LP = FEC_1_2; ++ break; ++ case 1: ++ p->code_rate_LP = FEC_2_3; ++ break; ++ case 2: ++ p->code_rate_LP = FEC_3_4; ++ break; ++ case 3: ++ p->code_rate_LP = FEC_5_6; ++ break; ++ case 4: ++ p->code_rate_LP = FEC_7_8; ++ break; ++ } ++ switch ((tps[1] >> 3) & 0x03) { ++ case 0: ++ p->guard_interval = GUARD_INTERVAL_1_32; ++ break; ++ case 1: ++ p->guard_interval = GUARD_INTERVAL_1_16; ++ break; ++ case 2: ++ p->guard_interval = GUARD_INTERVAL_1_8; ++ break; ++ case 3: ++ p->guard_interval = GUARD_INTERVAL_1_4; ++ break; ++ } ++ switch ((tps[1] >> 1) & 0x03) { ++ case 0: ++ p->transmission_mode = TRANSMISSION_MODE_2K; ++ break; ++ case 1: ++ p->transmission_mode = TRANSMISSION_MODE_8K; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int get_fe_c(struct cxd_state *state) ++{ ++ struct dvb_frontend *fe = &state->frontend; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ u8 qam; ++ ++ freeze_regst(state); ++ readregst_unlocked(state, 0x40, 0x19, &qam, 1); ++ unfreeze_regst(state); ++ p->modulation = qam & 0x07; ++ return 0; ++} ++ ++static int get_frontend(struct dvb_frontend *fe) ++{ ++ struct cxd_state *state = fe->demodulator_priv; ++ ++ if (state->last_status != 0x1f) ++ return 0; ++ ++ switch (state->state) { ++ case ActiveT: ++ get_fe_t(state); ++ break; ++ case ActiveT2: ++ break; ++ case ActiveC: ++ get_fe_c(state); ++ break; ++ case ActiveC2: ++ break; ++ case ActiveIT: ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ +static struct dvb_frontend_ops common_ops_2843 = { + .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2 }, + .info = { @@ -2142,6 +2470,7 @@ index 0000000..5feea53 + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, ++ .get_frontend = get_frontend, +#ifdef USE_ALGO + .get_frontend_algo = get_algo, + .search = search, @@ -2180,6 +2509,7 @@ index 0000000..5feea53 + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, ++ .get_frontend = get_frontend, +#ifdef USE_ALGO + .get_frontend_algo = get_algo, + .search = search, @@ -2222,18 +2552,17 @@ index 0000000..5feea53 + +static int probe(struct cxd_state *state) +{ -+ u8 ChipID = 0x00; ++ u8 ChipID = 0x00; + int status; + -+ status = readregst(state, 0x00, 0xFD, &ChipID, 1); ++ status = readregst(state, 0x00, 0xFD, &ChipID, 1); + -+ if (status) { ++ if (status) + status = readregsx(state, 0x00, 0xFD, &ChipID, 1); -+ } -+ if (status) ++ if (status) + return status; + -+ /*printk("ChipID = %02X\n", ChipID);*/ ++ /*printk("ChipID = %02X\n", ChipID);*/ + switch (ChipID) { + case 0xa4: + state->type = CXD2843; @@ -2272,23 +2601,21 @@ index 0000000..5feea53 + init(state); + return &state->frontend; + } -+ printk("cxd2843: not found\n"); ++ pr_err("cxd2843: not found\n"); + kfree(state); + return NULL; +} ++EXPORT_SYMBOL(cxd2843_attach); + +MODULE_DESCRIPTION("CXD2843/37/38 driver"); +MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); +MODULE_LICENSE("GPL"); -+ -+EXPORT_SYMBOL(cxd2843_attach); -+ diff --git a/drivers/media/dvb-frontends/cxd2843.h b/drivers/media/dvb-frontends/cxd2843.h new file mode 100644 -index 0000000..b6ecac6 +index 0000000..f3e355b --- /dev/null +++ b/drivers/media/dvb-frontends/cxd2843.h -@@ -0,0 +1,15 @@ +@@ -0,0 +1,30 @@ +#ifndef _CXD2843_H_ +#define _CXD2843_H_ + @@ -2298,14 +2625,29 @@ index 0000000..b6ecac6 +struct cxd2843_cfg { + u8 adr; + u32 ts_clock; ++ u8 parallel; +}; + ++#if defined(CONFIG_DVB_CXD2843) || \ ++ (defined(CONFIG_DVB_CXD2843_MODULE) && defined(MODULE)) ++ +extern struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, + struct cxd2843_cfg *cfg); + ++#else ++ ++static inline struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, ++ struct cxd2843_cfg *cfg) ++{ ++ pr_warn("%s: driver disabled by Kconfig\n", __func__); ++ return NULL; ++} ++ ++#endif ++ +#endif diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c -index cce94a7..60b868f 100644 +index cce94a7..91a7f9f 100644 --- a/drivers/media/dvb-frontends/drxk_hard.c +++ b/drivers/media/dvb-frontends/drxk_hard.c @@ -21,8 +21,6 @@ @@ -4393,7 +4735,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; break; -@@ -1823,121 +1872,122 @@ static int setoperation_mode(struct drxk_state *state, +@@ -1823,121 +1872,123 @@ static int setoperation_mode(struct drxk_state *state, } error: if (status < 0) @@ -4512,6 +4854,7 @@ index cce94a7..60b868f 100644 + status = GetDVBTLockStatus(state, pLockStatus); break; default: ++ status = 0; break; } error: @@ -4553,7 +4896,7 @@ index cce94a7..60b868f 100644 { int status; -@@ -1979,68 +2029,68 @@ static int mpegts_dto_init(struct drxk_state *state) +@@ -1979,68 +2030,68 @@ static int mpegts_dto_init(struct drxk_state *state) status = write16(state, FEC_OC_SNC_HWM__A, 12); error: if (status < 0) @@ -4657,7 +5000,7 @@ index cce94a7..60b868f 100644 break; default: status = -EINVAL; -@@ -2049,84 +2099,83 @@ static int mpegts_dto_setup(struct drxk_state *state, +@@ -2049,84 +2100,83 @@ static int mpegts_dto_setup(struct drxk_state *state, goto error; /* Configure DTO's */ @@ -4773,7 +5116,7 @@ index cce94a7..60b868f 100644 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | -@@ -2135,40 +2184,40 @@ static int mpegts_configure_polarity(struct drxk_state *state) +@@ -2135,40 +2185,40 @@ static int mpegts_configure_polarity(struct drxk_state *state) dprintk(1, "\n"); /* Control selective inversion of output bits */ @@ -4836,7 +5179,7 @@ index cce94a7..60b868f 100644 case DRXK_AGC_CTRL_AUTO: /* Enable RF AGC DAC */ status = read16(state, IQM_AF_STDBY__A, &data); -@@ -2186,7 +2235,7 @@ static int set_agc_rf(struct drxk_state *state, +@@ -2186,7 +2236,7 @@ static int set_agc_rf(struct drxk_state *state, data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; /* Polarity */ @@ -4845,7 +5188,7 @@ index cce94a7..60b868f 100644 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; else data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -@@ -2200,7 +2249,7 @@ static int set_agc_rf(struct drxk_state *state, +@@ -2200,7 +2250,7 @@ static int set_agc_rf(struct drxk_state *state, goto error; data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; @@ -4854,7 +5197,7 @@ index cce94a7..60b868f 100644 SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M); -@@ -2208,34 +2257,30 @@ static int set_agc_rf(struct drxk_state *state, +@@ -2208,34 +2258,30 @@ static int set_agc_rf(struct drxk_state *state, if (status < 0) goto error; @@ -4899,7 +5242,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -2256,7 +2301,7 @@ static int set_agc_rf(struct drxk_state *state, +@@ -2256,7 +2302,7 @@ static int set_agc_rf(struct drxk_state *state, if (status < 0) goto error; data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; @@ -4908,7 +5251,7 @@ index cce94a7..60b868f 100644 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; else data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -@@ -2270,8 +2315,7 @@ static int set_agc_rf(struct drxk_state *state, +@@ -2270,8 +2316,7 @@ static int set_agc_rf(struct drxk_state *state, goto error; /* Write value to output pin */ @@ -4918,7 +5261,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; break; -@@ -2302,22 +2346,22 @@ static int set_agc_rf(struct drxk_state *state, +@@ -2302,22 +2347,22 @@ static int set_agc_rf(struct drxk_state *state, } error: if (status < 0) @@ -4946,7 +5289,7 @@ index cce94a7..60b868f 100644 case DRXK_AGC_CTRL_AUTO: /* Enable IF AGC DAC */ -@@ -2337,7 +2381,7 @@ static int set_agc_if(struct drxk_state *state, +@@ -2337,7 +2382,7 @@ static int set_agc_if(struct drxk_state *state, data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; /* Polarity */ @@ -4955,7 +5298,7 @@ index cce94a7..60b868f 100644 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; else data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -@@ -2350,7 +2394,7 @@ static int set_agc_if(struct drxk_state *state, +@@ -2350,7 +2395,7 @@ static int set_agc_if(struct drxk_state *state, if (status < 0) goto error; data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; @@ -4964,7 +5307,7 @@ index cce94a7..60b868f 100644 SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M); -@@ -2358,15 +2402,14 @@ static int set_agc_if(struct drxk_state *state, +@@ -2358,15 +2403,14 @@ static int set_agc_if(struct drxk_state *state, if (status < 0) goto error; @@ -4985,7 +5328,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; break; -@@ -2390,7 +2433,7 @@ static int set_agc_if(struct drxk_state *state, +@@ -2390,7 +2434,7 @@ static int set_agc_if(struct drxk_state *state, data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; /* Polarity */ @@ -4994,7 +5337,7 @@ index cce94a7..60b868f 100644 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; else data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -@@ -2399,8 +2442,7 @@ static int set_agc_if(struct drxk_state *state, +@@ -2399,8 +2443,7 @@ static int set_agc_if(struct drxk_state *state, goto error; /* Write value to output pin */ @@ -5004,7 +5347,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; break; -@@ -2425,181 +2467,207 @@ static int set_agc_if(struct drxk_state *state, +@@ -2425,181 +2468,207 @@ static int set_agc_if(struct drxk_state *state, if (status < 0) goto error; break; @@ -5288,7 +5631,7 @@ index cce94a7..60b868f 100644 default: break; } -@@ -2607,7 +2675,7 @@ static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) +@@ -2607,7 +2676,7 @@ static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) } #if 0 @@ -5297,7 +5640,7 @@ index cce94a7..60b868f 100644 { /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ int status = 0; -@@ -2632,104 +2700,102 @@ static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) +@@ -2632,104 +2701,102 @@ static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) 225, /* 64-QAM 7/8 */ }; @@ -5446,7 +5789,7 @@ index cce94a7..60b868f 100644 default: break; } -@@ -2751,68 +2817,65 @@ static int get_quality(struct drxk_state *state, s32 *p_quality) +@@ -2751,68 +2818,65 @@ static int get_quality(struct drxk_state *state, s32 *p_quality) #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) @@ -5536,7 +5879,7 @@ index cce94a7..60b868f 100644 int status; unsigned long end; -@@ -2828,44 +2891,44 @@ static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, +@@ -2828,44 +2892,44 @@ static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, status = write16(state, SIO_BL_TGT_ADDR__A, offset); if (status < 0) goto error; @@ -5591,7 +5934,7 @@ index cce94a7..60b868f 100644 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); if (status < 0) goto error; -@@ -2892,42 +2955,42 @@ static int adc_sync_measurement(struct drxk_state *state, u16 *count) +@@ -2892,42 +2956,42 @@ static int adc_sync_measurement(struct drxk_state *state, u16 *count) error: if (status < 0) @@ -5647,7 +5990,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; } -@@ -2936,25 +2999,25 @@ static int adc_synchronization(struct drxk_state *state) +@@ -2936,25 +3000,25 @@ static int adc_synchronization(struct drxk_state *state) status = -EINVAL; error: if (status < 0) @@ -5687,7 +6030,7 @@ index cce94a7..60b868f 100644 dprintk(1, "\n"); -@@ -2962,125 +3025,121 @@ static int set_frequency_shifter(struct drxk_state *state, +@@ -2962,125 +3026,121 @@ static int set_frequency_shifter(struct drxk_state *state, Program frequency shifter No need to account for mirroring on RF */ @@ -5881,7 +6224,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); -@@ -3095,22 +3154,20 @@ static int init_agc(struct drxk_state *state, bool is_dtv) +@@ -3095,22 +3155,20 @@ static int init_agc(struct drxk_state *state, bool is_dtv) status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); if (status < 0) goto error; @@ -5909,7 +6252,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -3127,16 +3184,16 @@ static int init_agc(struct drxk_state *state, bool is_dtv) +@@ -3127,16 +3185,16 @@ static int init_agc(struct drxk_state *state, bool is_dtv) status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); if (status < 0) goto error; @@ -5930,7 +6273,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); -@@ -3196,39 +3253,38 @@ static int init_agc(struct drxk_state *state, bool is_dtv) +@@ -3196,39 +3254,38 @@ static int init_agc(struct drxk_state *state, bool is_dtv) status = write16(state, SCU_RAM_AGC_KI__A, data); error: if (status < 0) @@ -5982,7 +6325,7 @@ index cce94a7..60b868f 100644 /* SC is not running */ status = -EINVAL; } -@@ -3236,13 +3292,13 @@ static int dvbt_sc_command(struct drxk_state *state, +@@ -3236,13 +3293,13 @@ static int dvbt_sc_command(struct drxk_state *state, goto error; /* Wait until sc is ready to receive command */ @@ -6002,7 +6345,7 @@ index cce94a7..60b868f 100644 goto error; /* Write sub-command */ -@@ -3288,25 +3344,25 @@ static int dvbt_sc_command(struct drxk_state *state, +@@ -3288,25 +3345,25 @@ static int dvbt_sc_command(struct drxk_state *state, goto error; /* Wait until sc is ready processing command */ @@ -6037,7 +6380,7 @@ index cce94a7..60b868f 100644 switch (cmd) { /* All commands yielding 5 results */ /* All commands yielding 4 results */ -@@ -3331,23 +3387,23 @@ static int dvbt_sc_command(struct drxk_state *state, +@@ -3331,23 +3388,23 @@ static int dvbt_sc_command(struct drxk_state *state, } /* switch (cmd->cmd) */ error: if (status < 0) @@ -6067,7 +6410,7 @@ index cce94a7..60b868f 100644 { int status; -@@ -3357,12 +3413,12 @@ static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) +@@ -3357,12 +3414,12 @@ static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) else status = write16(state, IQM_CF_BYPASSDET__A, 1); if (status < 0) @@ -6082,7 +6425,7 @@ index cce94a7..60b868f 100644 { int status; -@@ -3377,13 +3433,13 @@ static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) +@@ -3377,13 +3434,13 @@ static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); } if (status < 0) @@ -6099,7 +6442,7 @@ index cce94a7..60b868f 100644 { u16 data = 0; int status; -@@ -3393,16 +3449,16 @@ static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, +@@ -3393,16 +3450,16 @@ static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, if (status < 0) goto error; @@ -6119,7 +6462,7 @@ index cce94a7..60b868f 100644 OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); break; -@@ -3413,12 +3469,12 @@ static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, +@@ -3413,12 +3470,12 @@ static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); error: if (status < 0) @@ -6135,7 +6478,7 @@ index cce94a7..60b868f 100644 { int status = -EINVAL; -@@ -3436,7 +3492,7 @@ static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, +@@ -3436,7 +3493,7 @@ static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, (u16) *speed); error: if (status < 0) @@ -6144,7 +6487,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -3450,33 +3506,32 @@ error: +@@ -3450,33 +3507,32 @@ error: * Called in DVBTSetStandard * */ @@ -6187,7 +6530,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -3490,30 +3545,25 @@ error: +@@ -3490,30 +3546,25 @@ error: * For ROM code channel filter taps are loaded from the bootloader. For microcode * the DVB-T taps from the drxk_filters.h are used. */ @@ -6225,7 +6568,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -3545,7 +3595,7 @@ static int set_dvbt_standard(struct drxk_state *state, +@@ -3545,7 +3596,7 @@ static int set_dvbt_standard(struct drxk_state *state, status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); if (status < 0) goto error; @@ -6234,7 +6577,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -3567,7 +3617,7 @@ static int set_dvbt_standard(struct drxk_state *state, +@@ -3567,7 +3618,7 @@ static int set_dvbt_standard(struct drxk_state *state, status = write16(state, IQM_RC_STRETCH__A, 16); if (status < 0) goto error; @@ -6243,7 +6586,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ -@@ -3588,8 +3638,7 @@ static int set_dvbt_standard(struct drxk_state *state, +@@ -3588,8 +3639,7 @@ static int set_dvbt_standard(struct drxk_state *state, if (status < 0) goto error; @@ -6253,7 +6596,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -3608,10 +3657,10 @@ static int set_dvbt_standard(struct drxk_state *state, +@@ -3608,10 +3658,10 @@ static int set_dvbt_standard(struct drxk_state *state, goto error; /* IQM will not be reset from here, sync ADC and update/init AGC */ @@ -6266,7 +6609,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -3620,10 +3669,10 @@ static int set_dvbt_standard(struct drxk_state *state, +@@ -3620,10 +3670,10 @@ static int set_dvbt_standard(struct drxk_state *state, if (status < 0) goto error; @@ -6279,7 +6622,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -3641,10 +3690,9 @@ static int set_dvbt_standard(struct drxk_state *state, +@@ -3641,10 +3691,9 @@ static int set_dvbt_standard(struct drxk_state *state, if (status < 0) goto error; @@ -6293,7 +6636,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; } -@@ -3679,43 +3727,41 @@ static int set_dvbt_standard(struct drxk_state *state, +@@ -3679,43 +3728,41 @@ static int set_dvbt_standard(struct drxk_state *state, goto error; /* Setup MPEG bus */ @@ -6347,7 +6690,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); -@@ -3723,7 +3769,7 @@ static int dvbt_start(struct drxk_state *state) +@@ -3723,7 +3770,7 @@ static int dvbt_start(struct drxk_state *state) goto error; error: if (status < 0) @@ -6356,7 +6699,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -3736,23 +3782,20 @@ error: +@@ -3736,23 +3783,20 @@ error: * \return DRXStatus_t. * // original DVBTSetChannel() */ @@ -6388,7 +6731,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -3775,19 +3818,19 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -3775,19 +3819,19 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, if (status < 0) goto error; @@ -6412,7 +6755,7 @@ index cce94a7..60b868f 100644 break; } -@@ -3795,19 +3838,19 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -3795,19 +3839,19 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, switch (state->props.guard_interval) { default: case GUARD_INTERVAL_AUTO: @@ -6437,7 +6780,7 @@ index cce94a7..60b868f 100644 break; } -@@ -3816,18 +3859,18 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -3816,18 +3860,18 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, case HIERARCHY_AUTO: case HIERARCHY_NONE: default: @@ -6461,7 +6804,7 @@ index cce94a7..60b868f 100644 break; } -@@ -3836,30 +3879,30 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -3836,30 +3880,30 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, switch (state->props.modulation) { case QAM_AUTO: default: @@ -6501,7 +6844,7 @@ index cce94a7..60b868f 100644 OFDM_EC_SB_PRIOR_HI)); break; case DRX_PRIORITY_UNKNOWN: /* fall through */ -@@ -3869,7 +3912,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -3869,7 +3913,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, } #else /* Set Priorty high */ @@ -6510,7 +6853,7 @@ index cce94a7..60b868f 100644 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); if (status < 0) goto error; -@@ -3879,111 +3922,90 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -3879,111 +3923,90 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, switch (state->props.code_rate_HP) { case FEC_AUTO: default: @@ -6648,7 +6991,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; break; -@@ -3992,50 +4014,46 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -3992,50 +4015,46 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, goto error; } @@ -6715,7 +7058,7 @@ index cce94a7..60b868f 100644 /* Activate SCU to enable SCU commands */ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); -@@ -4051,9 +4069,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -4051,9 +4070,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, goto error; @@ -6726,7 +7069,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -4063,16 +4079,16 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -4063,16 +4080,16 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, OFDM_SC_RA_RAM_OP_AUTO_CONST__M | OFDM_SC_RA_RAM_OP_AUTO_HIER__M | OFDM_SC_RA_RAM_OP_AUTO_RATE__M); @@ -6748,7 +7091,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -4081,13 +4097,13 @@ error: +@@ -4081,13 +4098,13 @@ error: /*============================================================================*/ /** @@ -6764,7 +7107,7 @@ index cce94a7..60b868f 100644 { int status; const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | -@@ -4095,58 +4111,58 @@ static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) +@@ -4095,58 +4112,58 @@ static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; @@ -6844,7 +7187,7 @@ index cce94a7..60b868f 100644 int status = 0; dprintk(1, "\n"); -@@ -4162,18 +4178,16 @@ static int power_down_qam(struct drxk_state *state) +@@ -4162,18 +4179,16 @@ static int power_down_qam(struct drxk_state *state) status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); if (status < 0) goto error; @@ -6866,7 +7209,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -4191,20 +4205,20 @@ error: +@@ -4191,20 +4206,20 @@ error: * The implementation does not check this. * */ @@ -6896,7 +7239,7 @@ index cce94a7..60b868f 100644 FrameLenght [ms] * (modulation + 1) * SyncLoss (== 1) * -@@ -4212,19 +4226,19 @@ static int set_qam_measurement(struct drxk_state *state, +@@ -4212,19 +4227,19 @@ static int set_qam_measurement(struct drxk_state *state, */ switch (modulation) { case DRX_CONSTELLATION_QAM16: @@ -6921,7 +7264,7 @@ index cce94a7..60b868f 100644 break; default: status = -EINVAL; -@@ -4232,41 +4246,40 @@ static int set_qam_measurement(struct drxk_state *state, +@@ -4232,41 +4247,40 @@ static int set_qam_measurement(struct drxk_state *state, if (status < 0) goto error; @@ -6978,7 +7321,7 @@ index cce94a7..60b868f 100644 { int status = 0; -@@ -4322,8 +4335,7 @@ static int set_qam16(struct drxk_state *state) +@@ -4322,8 +4336,7 @@ static int set_qam16(struct drxk_state *state) goto error; /* QAM Slicer Settings */ @@ -6988,7 +7331,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -4449,7 +4461,7 @@ static int set_qam16(struct drxk_state *state) +@@ -4449,7 +4462,7 @@ static int set_qam16(struct drxk_state *state) error: if (status < 0) @@ -6997,7 +7340,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -4460,7 +4472,7 @@ error: +@@ -4460,7 +4473,7 @@ error: * \param demod instance of demod. * \return DRXStatus_t. */ @@ -7006,7 +7349,7 @@ index cce94a7..60b868f 100644 { int status = 0; -@@ -4519,8 +4531,7 @@ static int set_qam32(struct drxk_state *state) +@@ -4519,8 +4532,7 @@ static int set_qam32(struct drxk_state *state) /* QAM Slicer Settings */ @@ -7016,7 +7359,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -4645,7 +4656,7 @@ static int set_qam32(struct drxk_state *state) +@@ -4645,7 +4657,7 @@ static int set_qam32(struct drxk_state *state) status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); error: if (status < 0) @@ -7025,7 +7368,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -4656,7 +4667,7 @@ error: +@@ -4656,7 +4668,7 @@ error: * \param demod instance of demod. * \return DRXStatus_t. */ @@ -7034,7 +7377,7 @@ index cce94a7..60b868f 100644 { int status = 0; -@@ -4713,8 +4724,7 @@ static int set_qam64(struct drxk_state *state) +@@ -4713,8 +4725,7 @@ static int set_qam64(struct drxk_state *state) goto error; /* QAM Slicer Settings */ @@ -7044,7 +7387,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -4839,7 +4849,7 @@ static int set_qam64(struct drxk_state *state) +@@ -4839,7 +4850,7 @@ static int set_qam64(struct drxk_state *state) status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); error: if (status < 0) @@ -7053,7 +7396,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -4851,7 +4861,7 @@ error: +@@ -4851,7 +4862,7 @@ error: * \param demod: instance of demod. * \return DRXStatus_t. */ @@ -7062,7 +7405,7 @@ index cce94a7..60b868f 100644 { int status = 0; -@@ -4910,8 +4920,7 @@ static int set_qam128(struct drxk_state *state) +@@ -4910,8 +4921,7 @@ static int set_qam128(struct drxk_state *state) /* QAM Slicer Settings */ @@ -7072,7 +7415,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5036,7 +5045,7 @@ static int set_qam128(struct drxk_state *state) +@@ -5036,7 +5046,7 @@ static int set_qam128(struct drxk_state *state) status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); error: if (status < 0) @@ -7081,7 +7424,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -5048,7 +5057,7 @@ error: +@@ -5048,7 +5058,7 @@ error: * \param demod: instance of demod. * \return DRXStatus_t. */ @@ -7090,7 +7433,7 @@ index cce94a7..60b868f 100644 { int status = 0; -@@ -5106,8 +5115,7 @@ static int set_qam256(struct drxk_state *state) +@@ -5106,8 +5116,7 @@ static int set_qam256(struct drxk_state *state) /* QAM Slicer Settings */ @@ -7100,7 +7443,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5232,7 +5240,7 @@ static int set_qam256(struct drxk_state *state) +@@ -5232,7 +5241,7 @@ static int set_qam256(struct drxk_state *state) status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); error: if (status < 0) @@ -7109,7 +7452,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -5244,10 +5252,10 @@ error: +@@ -5244,10 +5253,10 @@ error: * \param channel: pointer to channel data. * \return DRXStatus_t. */ @@ -7122,7 +7465,7 @@ index cce94a7..60b868f 100644 dprintk(1, "\n"); /* Stop QAM comstate->m_exec */ -@@ -5255,12 +5263,10 @@ static int qam_reset_qam(struct drxk_state *state) +@@ -5255,12 +5264,10 @@ static int qam_reset_qam(struct drxk_state *state) if (status < 0) goto error; @@ -7137,7 +7480,7 @@ index cce94a7..60b868f 100644 return status; } -@@ -5272,18 +5278,18 @@ error: +@@ -5272,18 +5279,18 @@ error: * \param channel: pointer to channel data. * \return DRXStatus_t. */ @@ -7162,7 +7505,7 @@ index cce94a7..60b868f 100644 ratesel = 0; /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ if (state->props.symbol_rate <= 1188750) -@@ -5299,38 +5305,38 @@ static int qam_set_symbolrate(struct drxk_state *state) +@@ -5299,38 +5306,38 @@ static int qam_set_symbolrate(struct drxk_state *state) /* IqmRcRate = ((Fadc / (symbolrate * (4<props.modulation) { case QAM_16: @@ -7508,7 +7851,7 @@ index cce94a7..60b868f 100644 break; default: status = -EINVAL; -@@ -5668,12 +5603,12 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -5668,12 +5604,12 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, /* Re-configure MPEG output, requires knowledge of channel bitrate */ /* extAttr->currentChannel.modulation = channel->modulation; */ /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ @@ -7524,7 +7867,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); -@@ -5687,9 +5622,7 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -5687,9 +5623,7 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, goto error; /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ @@ -7535,7 +7878,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5698,12 +5631,12 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, +@@ -5698,12 +5632,12 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, error: if (status < 0) @@ -7551,7 +7894,7 @@ index cce94a7..60b868f 100644 { int status; #ifdef DRXK_QAM_TAPS -@@ -5715,14 +5648,14 @@ static int set_qam_standard(struct drxk_state *state, +@@ -5715,14 +5649,14 @@ static int set_qam_standard(struct drxk_state *state, dprintk(1, "\n"); /* added antenna switch */ @@ -7569,7 +7912,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5737,24 +5670,15 @@ static int set_qam_standard(struct drxk_state *state, +@@ -5737,24 +5671,15 @@ static int set_qam_standard(struct drxk_state *state, /* Upload IQM Channel Filter settings by boot loader from ROM table */ @@ -7598,7 +7941,7 @@ index cce94a7..60b868f 100644 break; default: status = -EINVAL; -@@ -5762,14 +5686,13 @@ static int set_qam_standard(struct drxk_state *state, +@@ -5762,14 +5687,13 @@ static int set_qam_standard(struct drxk_state *state, if (status < 0) goto error; @@ -7615,7 +7958,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5826,7 +5749,7 @@ static int set_qam_standard(struct drxk_state *state, +@@ -5826,7 +5750,7 @@ static int set_qam_standard(struct drxk_state *state, goto error; /* turn on IQMAF. Must be done before setAgc**() */ @@ -7624,7 +7967,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; status = write16(state, IQM_AF_START_LOCK__A, 0x01); -@@ -5834,7 +5757,7 @@ static int set_qam_standard(struct drxk_state *state, +@@ -5834,7 +5758,7 @@ static int set_qam_standard(struct drxk_state *state, goto error; /* IQM will not be reset from here, sync ADC and update/init AGC */ @@ -7633,7 +7976,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5851,18 +5774,18 @@ static int set_qam_standard(struct drxk_state *state, +@@ -5851,18 +5775,18 @@ static int set_qam_standard(struct drxk_state *state, /* No more resets of the IQM, current standard correctly set => now AGCs can be configured. */ @@ -7656,7 +7999,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5870,19 +5793,18 @@ static int set_qam_standard(struct drxk_state *state, +@@ -5870,19 +5794,18 @@ static int set_qam_standard(struct drxk_state *state, status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); error: if (status < 0) @@ -7679,7 +8022,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5891,11 +5813,10 @@ static int write_gpio(struct drxk_state *state) +@@ -5891,11 +5814,10 @@ static int write_gpio(struct drxk_state *state) if (status < 0) goto error; @@ -7694,7 +8037,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5903,7 +5824,7 @@ static int write_gpio(struct drxk_state *state) +@@ -5903,7 +5825,7 @@ static int write_gpio(struct drxk_state *state) status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); if (status < 0) goto error; @@ -7703,7 +8046,7 @@ index cce94a7..60b868f 100644 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ else value |= 0x8000; /* write one to 15th bit - 1st UIO */ -@@ -5912,10 +5833,9 @@ static int write_gpio(struct drxk_state *state) +@@ -5912,10 +5834,9 @@ static int write_gpio(struct drxk_state *state) if (status < 0) goto error; } @@ -7716,7 +8059,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5923,7 +5843,7 @@ static int write_gpio(struct drxk_state *state) +@@ -5923,7 +5844,7 @@ static int write_gpio(struct drxk_state *state) status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); if (status < 0) goto error; @@ -7725,7 +8068,7 @@ index cce94a7..60b868f 100644 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ else value |= 0x4000; /* write one to 14th bit - 2st UIO */ -@@ -5932,10 +5852,9 @@ static int write_gpio(struct drxk_state *state) +@@ -5932,10 +5853,9 @@ static int write_gpio(struct drxk_state *state) if (status < 0) goto error; } @@ -7738,7 +8081,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -5943,7 +5862,7 @@ static int write_gpio(struct drxk_state *state) +@@ -5943,7 +5863,7 @@ static int write_gpio(struct drxk_state *state) status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); if (status < 0) goto error; @@ -7747,7 +8090,7 @@ index cce94a7..60b868f 100644 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ else value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ -@@ -5957,11 +5876,11 @@ static int write_gpio(struct drxk_state *state) +@@ -5957,11 +5877,11 @@ static int write_gpio(struct drxk_state *state) status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); error: if (status < 0) @@ -7761,7 +8104,7 @@ index cce94a7..60b868f 100644 { int status = 0; bool gpio_state; -@@ -5971,22 +5890,22 @@ static int switch_antenna_to_qam(struct drxk_state *state) +@@ -5971,22 +5891,22 @@ static int switch_antenna_to_qam(struct drxk_state *state) if (!state->antenna_gpio) return 0; @@ -7790,7 +8133,7 @@ index cce94a7..60b868f 100644 { int status = 0; bool gpio_state; -@@ -5996,23 +5915,23 @@ static int switch_antenna_to_dvbt(struct drxk_state *state) +@@ -5996,23 +5916,23 @@ static int switch_antenna_to_dvbt(struct drxk_state *state) if (!state->antenna_gpio) return 0; @@ -7820,7 +8163,7 @@ index cce94a7..60b868f 100644 { /* Power down to requested mode */ /* Backup some register settings */ -@@ -6023,86 +5942,98 @@ static int power_down_device(struct drxk_state *state) +@@ -6023,86 +5943,98 @@ static int power_down_device(struct drxk_state *state) int status; dprintk(1, "\n"); @@ -7951,7 +8294,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; /* disable various processes */ -@@ -6111,14 +6042,13 @@ static int init_drxk(struct drxk_state *state) +@@ -6111,14 +6043,13 @@ static int init_drxk(struct drxk_state *state) && !(state->m_DRXK_A2_ROM_CODE)) #endif { @@ -7968,7 +8311,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -6131,30 +6061,23 @@ static int init_drxk(struct drxk_state *state) +@@ -6131,30 +6062,23 @@ static int init_drxk(struct drxk_state *state) goto error; /* enable token-ring bus through OFDM block for possible ucode upload */ @@ -8005,7 +8348,7 @@ index cce94a7..60b868f 100644 if (status < 0) goto error; -@@ -6162,55 +6085,50 @@ static int init_drxk(struct drxk_state *state) +@@ -6162,55 +6086,50 @@ static int init_drxk(struct drxk_state *state) status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); if (status < 0) goto error; @@ -8075,7 +8418,7 @@ index cce94a7..60b868f 100644 /* Reset driver debug flags to 0 */ status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); -@@ -6223,95 +6141,45 @@ static int init_drxk(struct drxk_state *state) +@@ -6223,95 +6142,45 @@ static int init_drxk(struct drxk_state *state) if (status < 0) goto error; /* MPEGTS functions are still the same */ @@ -8183,7 +8526,7 @@ index cce94a7..60b868f 100644 kfree(state); } -@@ -6320,13 +6188,7 @@ static int drxk_sleep(struct dvb_frontend *fe) +@@ -6320,13 +6189,7 @@ static int drxk_sleep(struct dvb_frontend *fe) struct drxk_state *state = fe->demodulator_priv; dprintk(1, "\n"); @@ -8198,7 +8541,7 @@ index cce94a7..60b868f 100644 return 0; } -@@ -6334,11 +6196,7 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) +@@ -6334,11 +6197,7 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) { struct drxk_state *state = fe->demodulator_priv; @@ -8211,7 +8554,7 @@ index cce94a7..60b868f 100644 return ConfigureI2CBridge(state, enable ? true : false); } -@@ -6351,14 +6209,9 @@ static int drxk_set_parameters(struct dvb_frontend *fe) +@@ -6351,14 +6210,9 @@ static int drxk_set_parameters(struct dvb_frontend *fe) dprintk(1, "\n"); @@ -8228,7 +8571,7 @@ index cce94a7..60b868f 100644 return -EINVAL; } -@@ -6373,23 +6226,22 @@ static int drxk_set_parameters(struct dvb_frontend *fe) +@@ -6373,23 +6227,22 @@ static int drxk_set_parameters(struct dvb_frontend *fe) state->props = *p; if (old_delsys != delsys) { @@ -8259,7 +8602,7 @@ index cce94a7..60b868f 100644 break; default: return -EINVAL; -@@ -6397,261 +6249,35 @@ static int drxk_set_parameters(struct dvb_frontend *fe) +@@ -6397,261 +6250,35 @@ static int drxk_set_parameters(struct dvb_frontend *fe) } fe->ops.tuner_ops.get_if_frequency(fe, &IF); @@ -8533,7 +8876,7 @@ index cce94a7..60b868f 100644 return 0; } -@@ -6659,16 +6285,11 @@ static int drxk_read_signal_strength(struct dvb_frontend *fe, +@@ -6659,16 +6286,11 @@ static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) { struct drxk_state *state = fe->demodulator_priv; @@ -8553,7 +8896,7 @@ index cce94a7..60b868f 100644 return 0; } -@@ -6678,17 +6299,7 @@ static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) +@@ -6678,17 +6300,7 @@ static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) s32 snr2; dprintk(1, "\n"); @@ -8572,7 +8915,7 @@ index cce94a7..60b868f 100644 *snr = snr2 & 0xffff; return 0; } -@@ -6699,30 +6310,17 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +@@ -6699,30 +6311,17 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) u16 err; dprintk(1, "\n"); @@ -8606,7 +8949,7 @@ index cce94a7..60b868f 100644 switch (p->delivery_system) { case SYS_DVBC_ANNEX_A: case SYS_DVBC_ANNEX_C: -@@ -6764,6 +6362,7 @@ static struct dvb_frontend_ops drxk_ops = { +@@ -6764,6 +6363,7 @@ static struct dvb_frontend_ops drxk_ops = { .get_tune_settings = drxk_get_tune_settings, .read_status = drxk_read_status, @@ -8614,7 +8957,7 @@ index cce94a7..60b868f 100644 .read_signal_strength = drxk_read_signal_strength, .read_snr = drxk_read_snr, .read_ucblocks = drxk_read_ucblocks, -@@ -6772,10 +6371,10 @@ static struct dvb_frontend_ops drxk_ops = { +@@ -6772,10 +6372,10 @@ static struct dvb_frontend_ops drxk_ops = { struct dvb_frontend *drxk_attach(const struct drxk_config *config, struct i2c_adapter *i2c) { @@ -8627,7 +8970,7 @@ index cce94a7..60b868f 100644 dprintk(1, "\n"); state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); -@@ -6786,40 +6385,39 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, +@@ -6786,40 +6386,39 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, state->demod_address = adr; state->single_master = config->single_master; state->microcode_name = config->microcode_name; @@ -8680,7 +9023,7 @@ index cce94a7..60b868f 100644 mutex_init(&state->mutex); -@@ -6827,45 +6425,28 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, +@@ -6827,45 +6426,28 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, state->frontend.demodulator_priv = state; init_state(state); @@ -9193,6 +9536,179 @@ index 761613f..23e16c1 100644 #define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 #define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 +diff --git a/drivers/media/dvb-frontends/lnbh25.c b/drivers/media/dvb-frontends/lnbh25.c +new file mode 100644 +index 0000000..b7c5099 +--- /dev/null ++++ b/drivers/media/dvb-frontends/lnbh25.c +@@ -0,0 +1,133 @@ ++/* ++ * lnbh25.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dvb_frontend.h" ++#include "lnbh25.h" ++ ++struct lnbh25 { ++ struct i2c_adapter *i2c; ++ u8 adr; ++ u8 reg[4]; ++ u8 boost; ++}; ++ ++static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) ++{ ++ struct i2c_msg msg = {.addr = adr, .flags = 0, ++ .buf = data, .len = len}; ++ ++ if (i2c_transfer(adap, &msg, 1) != 1) { ++ pr_err("lnbh25: i2c_write error\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++static int lnbh25_write_regs(struct lnbh25 *lnbh, int reg, int len) ++{ ++ u8 d[5]; ++ ++ memcpy(&d[1], &lnbh->reg[reg], len); ++ d[0] = reg + 2; ++ return i2c_write(lnbh->i2c, lnbh->adr, d, len + 1); ++} ++ ++static int lnbh25_set_voltage(struct dvb_frontend *fe, ++ fe_sec_voltage_t voltage) ++{ ++ struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv; ++ ++ switch (voltage) { ++ case SEC_VOLTAGE_OFF: ++ lnbh->reg[0] = 0x00; ++ lnbh->reg[1] &= ~0x01; /* Disable Tone */ ++ lnbh->reg[2] = 0x00; ++ return lnbh25_write_regs(lnbh, 0, 3); ++ case SEC_VOLTAGE_13: ++ lnbh->reg[0] = lnbh->boost + 1; ++ break; ++ case SEC_VOLTAGE_18: ++ lnbh->reg[0] = lnbh->boost + 8; ++ break; ++ default: ++ return -EINVAL; ++ }; ++ ++ if (lnbh->reg[0] == 0x00) { ++ lnbh->reg[2] = 4; ++ lnbh25_write_regs(lnbh, 2, 2); ++ } else if (lnbh->reg[2] != 0x00) { ++ lnbh->reg[2] = 0; ++ lnbh25_write_regs(lnbh, 2, 2); ++ } ++ lnbh->reg[1] |= 0x01; ++ return lnbh25_write_regs(lnbh, 0, 3); ++} ++ ++static int lnbh25_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg) ++{ ++ struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv; ++ ++ lnbh->boost = arg ? 3 : 0; ++ ++ return 0; ++} ++ ++static int lnbh25_set_tone(struct dvb_frontend *fe, ++ fe_sec_tone_mode_t tone) ++{ ++ /* struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv; */ ++ ++ return 0; ++} ++ ++static int lnbh25_init(struct lnbh25 *lnbh) ++{ ++ return lnbh25_write_regs(lnbh, 0, 2); ++} ++ ++static void lnbh25_release(struct dvb_frontend *fe) ++{ ++ kfree(fe->sec_priv); ++ fe->sec_priv = NULL; ++} ++ ++struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, ++ u8 adr) ++{ ++ struct lnbh25 *lnbh = kzalloc(sizeof(struct lnbh25), GFP_KERNEL); ++ if (!lnbh) ++ return NULL; ++ ++ lnbh->i2c = i2c; ++ lnbh->adr = adr; ++ lnbh->boost = 3; ++ ++ if (lnbh25_init(lnbh)) { ++ kfree(lnbh); ++ return NULL; ++ } ++ fe->sec_priv = lnbh; ++ fe->ops.set_voltage = lnbh25_set_voltage; ++ fe->ops.enable_high_lnb_voltage = lnbh25_enable_high_lnb_voltage; ++ fe->ops.release_sec = lnbh25_release; ++ ++ pr_info("LNB25 on %02x\n", lnbh->adr); ++ ++ return fe; ++} ++EXPORT_SYMBOL(lnbh25_attach); ++ ++MODULE_DESCRIPTION("LNBH25"); ++MODULE_AUTHOR("Ralph Metzler"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/media/dvb-frontends/lnbh25.h b/drivers/media/dvb-frontends/lnbh25.h +new file mode 100644 +index 0000000..4e8b3cc +--- /dev/null ++++ b/drivers/media/dvb-frontends/lnbh25.h +@@ -0,0 +1,28 @@ ++/* ++ * lnbh25.h ++ */ ++ ++#ifndef _LNBH25_H ++#define _LNBH25_H ++ ++#include ++ ++#if defined(CONFIG_DVB_LNBH25) || \ ++ (defined(CONFIG_DVB_LNBH25_MODULE) && defined(MODULE)) ++ ++extern struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, ++ u8 i2c_addr); ++#else ++ ++static inline struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, ++ u8 i2c_addr) ++{ ++ pr_warn("%s: driver disabled by Kconfig\n", __func__); ++ return NULL; ++} ++ ++#endif ++ ++#endif diff --git a/drivers/media/dvb-frontends/stv0367dd.c b/drivers/media/dvb-frontends/stv0367dd.c new file mode 100644 index 0000000..64f7970 @@ -14990,957 +15506,6868 @@ index 0000000..eec0f57 +#define R367_QAM_T_O_ID_3 0xF4D3 +#define F367_QAM_TS_ID_I_H 0xF4D300FF + +diff --git a/drivers/media/dvb-frontends/stv0910.c b/drivers/media/dvb-frontends/stv0910.c +new file mode 100644 +index 0000000..89d7d1f +--- /dev/null ++++ b/drivers/media/dvb-frontends/stv0910.c +@@ -0,0 +1,1368 @@ ++/* ++ * Driver for the ST STV0910 DVB-S/S2 demodulator. ++ * ++ * Copyright (C) 2014 Digital Devices GmbH ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 only, as published by the Free Software Foundation. ++ * ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA ++ * 02110-1301, USA ++ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dvb_frontend.h" ++#include "stv0910.h" ++#include "stv0910_regs.h" ++ ++ ++#define TUNING_DELAY 200 ++#define BER_SRC_S 0x20 ++#define BER_SRC_S2 0x20 ++ ++LIST_HEAD(stvlist); ++ ++enum ReceiveMode { Mode_None, Mode_DVBS, Mode_DVBS2, Mode_Auto }; ++ ++ ++enum DVBS2_FECType { DVBS2_64K, DVBS2_16K }; ++ ++enum DVBS2_ModCod { ++ DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5, ++ DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4, ++ DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10, ++ DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6, ++ DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4, ++ DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10, ++ DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9, ++ DVBS2_32APSK_9_10 ++}; ++ ++enum FE_STV0910_ModCod { ++ FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25, ++ FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34, ++ FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910, ++ FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56, ++ FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34, ++ FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910, ++ FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89, ++ FE_32APSK_910 ++}; ++ ++enum FE_STV0910_RollOff { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 }; ++ ++static inline u32 MulDiv32(u32 a, u32 b, u32 c) ++{ ++ u64 tmp64; ++ ++ tmp64 = (u64)a * (u64)b; ++ do_div(tmp64, c); ++ ++ return (u32) tmp64; ++} ++ ++struct stv_base { ++ struct list_head stvlist; ++ ++ u8 adr; ++ struct i2c_adapter *i2c; ++ struct mutex i2c_lock; ++ struct mutex reg_lock; ++ int count; ++ ++ u32 extclk; ++ u32 mclk; ++}; ++ ++struct stv { ++ struct stv_base *base; ++ struct dvb_frontend fe; ++ int nr; ++ u16 regoff; ++ u8 i2crpt; ++ u8 tscfgh; ++ u8 tsspeed; ++ unsigned long tune_time; ++ ++ s32 SearchRange; ++ u32 Started; ++ u32 DemodLockTime; ++ enum ReceiveMode ReceiveMode; ++ u32 DemodTimeout; ++ u32 FecTimeout; ++ u32 FirstTimeLock; ++ u8 DEMOD; ++ u32 SymbolRate; ++ ++ u8 LastViterbiRate; ++ enum fe_code_rate PunctureRate; ++ enum FE_STV0910_ModCod ModCod; ++ enum DVBS2_FECType FECType; ++ u32 Pilots; ++ enum FE_STV0910_RollOff FERollOff; ++ ++ u32 LastBERNumerator; ++ u32 LastBERDenominator; ++ u8 BERScale; ++}; ++ ++struct SInitTable { ++ u16 Address; ++ u8 Data; ++}; ++ ++struct SLookupSNTable { ++ s16 SignalToNoise; ++ u16 RefValue; ++}; ++ ++static inline int i2c_write(struct i2c_adapter *adap, u8 adr, ++ u8 *data, int len) ++{ ++ struct i2c_msg msg = {.addr = adr, .flags = 0, ++ .buf = data, .len = len}; ++ ++ return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; ++} ++ ++static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, u16 reg, u8 val) ++{ ++ u8 msg[3] = {reg >> 8, reg & 0xff, val}; ++ ++ return i2c_write(adap, adr, msg, 3); ++} ++ ++static int write_reg(struct stv *state, u16 reg, u8 val) ++{ ++ return i2c_write_reg16(state->base->i2c, state->base->adr, reg, val); ++} ++ ++static inline int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, ++ u16 reg, u8 *val) ++{ ++ u8 msg[2] = {reg >> 8, reg & 0xff}; ++ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, ++ .buf = msg, .len = 2}, ++ {.addr = adr, .flags = I2C_M_RD, ++ .buf = val, .len = 1 } }; ++ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; ++} ++ ++static int read_reg(struct stv *state, u16 reg, u8 *val) ++{ ++ return i2c_read_reg16(state->base->i2c, state->base->adr, reg, val); ++} ++ ++ ++static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, ++ u16 reg, u8 *val, int len) ++{ ++ u8 msg[2] = {reg >> 8, reg & 0xff}; ++ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, ++ .buf = msg, .len = 2}, ++ {.addr = adr, .flags = I2C_M_RD, ++ .buf = val, .len = len } }; ++ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; ++} ++ ++static int read_regs(struct stv *state, u16 reg, u8 *val, int len) ++{ ++ return i2c_read_regs16(state->base->i2c, state->base->adr, ++ reg, val, len); ++} ++ ++struct SLookupSNTable S1_SN_Lookup[] = { ++ { 0, 9242 }, /*C/N= 0dB*/ ++ { 05, 9105 }, /*C/N=0.5dB*/ ++ { 10, 8950 }, /*C/N=1.0dB*/ ++ { 15, 8780 }, /*C/N=1.5dB*/ ++ { 20, 8566 }, /*C/N=2.0dB*/ ++ { 25, 8366 }, /*C/N=2.5dB*/ ++ { 30, 8146 }, /*C/N=3.0dB*/ ++ { 35, 7908 }, /*C/N=3.5dB*/ ++ { 40, 7666 }, /*C/N=4.0dB*/ ++ { 45, 7405 }, /*C/N=4.5dB*/ ++ { 50, 7136 }, /*C/N=5.0dB*/ ++ { 55, 6861 }, /*C/N=5.5dB*/ ++ { 60, 6576 }, /*C/N=6.0dB*/ ++ { 65, 6330 }, /*C/N=6.5dB*/ ++ { 70, 6048 }, /*C/N=7.0dB*/ ++ { 75, 5768 }, /*C/N=7.5dB*/ ++ { 80, 5492 }, /*C/N=8.0dB*/ ++ { 85, 5224 }, /*C/N=8.5dB*/ ++ { 90, 4959 }, /*C/N=9.0dB*/ ++ { 95, 4709 }, /*C/N=9.5dB*/ ++ { 100, 4467 }, /*C/N=10.0dB*/ ++ { 105, 4236 }, /*C/N=10.5dB*/ ++ { 110, 4013 }, /*C/N=11.0dB*/ ++ { 115, 3800 }, /*C/N=11.5dB*/ ++ { 120, 3598 }, /*C/N=12.0dB*/ ++ { 125, 3406 }, /*C/N=12.5dB*/ ++ { 130, 3225 }, /*C/N=13.0dB*/ ++ { 135, 3052 }, /*C/N=13.5dB*/ ++ { 140, 2889 }, /*C/N=14.0dB*/ ++ { 145, 2733 }, /*C/N=14.5dB*/ ++ { 150, 2587 }, /*C/N=15.0dB*/ ++ { 160, 2318 }, /*C/N=16.0dB*/ ++ { 170, 2077 }, /*C/N=17.0dB*/ ++ { 180, 1862 }, /*C/N=18.0dB*/ ++ { 190, 1670 }, /*C/N=19.0dB*/ ++ { 200, 1499 }, /*C/N=20.0dB*/ ++ { 210, 1347 }, /*C/N=21.0dB*/ ++ { 220, 1213 }, /*C/N=22.0dB*/ ++ { 230, 1095 }, /*C/N=23.0dB*/ ++ { 240, 992 }, /*C/N=24.0dB*/ ++ { 250, 900 }, /*C/N=25.0dB*/ ++ { 260, 826 }, /*C/N=26.0dB*/ ++ { 270, 758 }, /*C/N=27.0dB*/ ++ { 280, 702 }, /*C/N=28.0dB*/ ++ { 290, 653 }, /*C/N=29.0dB*/ ++ { 300, 613 }, /*C/N=30.0dB*/ ++ { 310, 579 }, /*C/N=31.0dB*/ ++ { 320, 550 }, /*C/N=32.0dB*/ ++ { 330, 526 }, /*C/N=33.0dB*/ ++ { 350, 490 }, /*C/N=33.0dB*/ ++ { 400, 445 }, /*C/N=40.0dB*/ ++ { 450, 430 }, /*C/N=45.0dB*/ ++ { 500, 426 }, /*C/N=50.0dB*/ ++ { 510, 425 } /*C/N=51.0dB*/ ++}; ++ ++struct SLookupSNTable S2_SN_Lookup[] = { ++ { -30, 13950 }, /*C/N=-2.5dB*/ ++ { -25, 13580 }, /*C/N=-2.5dB*/ ++ { -20, 13150 }, /*C/N=-2.0dB*/ ++ { -15, 12760 }, /*C/N=-1.5dB*/ ++ { -10, 12345 }, /*C/N=-1.0dB*/ ++ { -05, 11900 }, /*C/N=-0.5dB*/ ++ { 0, 11520 }, /*C/N= 0dB*/ ++ { 05, 11080 }, /*C/N= 0.5dB*/ ++ { 10, 10630 }, /*C/N= 1.0dB*/ ++ { 15, 10210 }, /*C/N= 1.5dB*/ ++ { 20, 9790 }, /*C/N= 2.0dB*/ ++ { 25, 9390 }, /*C/N= 2.5dB*/ ++ { 30, 8970 }, /*C/N= 3.0dB*/ ++ { 35, 8575 }, /*C/N= 3.5dB*/ ++ { 40, 8180 }, /*C/N= 4.0dB*/ ++ { 45, 7800 }, /*C/N= 4.5dB*/ ++ { 50, 7430 }, /*C/N= 5.0dB*/ ++ { 55, 7080 }, /*C/N= 5.5dB*/ ++ { 60, 6720 }, /*C/N= 6.0dB*/ ++ { 65, 6320 }, /*C/N= 6.5dB*/ ++ { 70, 6060 }, /*C/N= 7.0dB*/ ++ { 75, 5760 }, /*C/N= 7.5dB*/ ++ { 80, 5480 }, /*C/N= 8.0dB*/ ++ { 85, 5200 }, /*C/N= 8.5dB*/ ++ { 90, 4930 }, /*C/N= 9.0dB*/ ++ { 95, 4680 }, /*C/N= 9.5dB*/ ++ { 100, 4425 }, /*C/N=10.0dB*/ ++ { 105, 4210 }, /*C/N=10.5dB*/ ++ { 110, 3980 }, /*C/N=11.0dB*/ ++ { 115, 3765 }, /*C/N=11.5dB*/ ++ { 120, 3570 }, /*C/N=12.0dB*/ ++ { 125, 3315 }, /*C/N=12.5dB*/ ++ { 130, 3140 }, /*C/N=13.0dB*/ ++ { 135, 2980 }, /*C/N=13.5dB*/ ++ { 140, 2820 }, /*C/N=14.0dB*/ ++ { 145, 2670 }, /*C/N=14.5dB*/ ++ { 150, 2535 }, /*C/N=15.0dB*/ ++ { 160, 2270 }, /*C/N=16.0dB*/ ++ { 170, 2035 }, /*C/N=17.0dB*/ ++ { 180, 1825 }, /*C/N=18.0dB*/ ++ { 190, 1650 }, /*C/N=19.0dB*/ ++ { 200, 1485 }, /*C/N=20.0dB*/ ++ { 210, 1340 }, /*C/N=21.0dB*/ ++ { 220, 1212 }, /*C/N=22.0dB*/ ++ { 230, 1100 }, /*C/N=23.0dB*/ ++ { 240, 1000 }, /*C/N=24.0dB*/ ++ { 250, 910 }, /*C/N=25.0dB*/ ++ { 260, 836 }, /*C/N=26.0dB*/ ++ { 270, 772 }, /*C/N=27.0dB*/ ++ { 280, 718 }, /*C/N=28.0dB*/ ++ { 290, 671 }, /*C/N=29.0dB*/ ++ { 300, 635 }, /*C/N=30.0dB*/ ++ { 310, 602 }, /*C/N=31.0dB*/ ++ { 320, 575 }, /*C/N=32.0dB*/ ++ { 330, 550 }, /*C/N=33.0dB*/ ++ { 350, 517 }, /*C/N=35.0dB*/ ++ { 400, 480 }, /*C/N=40.0dB*/ ++ { 450, 466 }, /*C/N=45.0dB*/ ++ { 500, 464 }, /*C/N=50.0dB*/ ++ { 510, 463 }, /*C/N=51.0dB*/ ++}; ++ ++/********************************************************************* ++Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame ++*********************************************************************/ ++static u8 S2CarLoop[] = { ++ /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff ++ 20MPon 20MPoff 30MPon 30MPoff*/ ++ /* FE_QPSK_14 */ ++ 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B, ++ /* FE_QPSK_13 */ ++ 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B, ++ /* FE_QPSK_25 */ ++ 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B, ++ /* FE_QPSK_12 */ ++ 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, ++ /* FE_QPSK_35 */ ++ 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, ++ /* FE_QPSK_23 */ ++ 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B, ++ /* FE_QPSK_34 */ ++ 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B, ++ /* FE_QPSK_45 */ ++ 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B, ++ /* FE_QPSK_56 */ ++ 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B, ++ /* FE_QPSK_89 */ ++ 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B, ++ /* FE_QPSK_910 */ ++ 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B, ++ /* FE_8PSK_35 */ ++ 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27, ++ /* FE_8PSK_23 */ ++ 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09, ++ /* FE_8PSK_34 */ ++ 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A, ++ /* FE_8PSK_56 */ ++ 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A, ++ /* FE_8PSK_89 */ ++ 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A, ++ /* FE_8PSK_910 */ ++ 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A, ++ ++ /********************************************************************** ++ Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame ++ **********************************************************************/ ++ /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon ++ 20MPoff 30MPon 30MPoff*/ ++ /* FE_16APSK_23 */ ++ 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A, ++ /* FE_16APSK_34 */ ++ 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A, ++ /* FE_16APSK_45 */ ++ 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A, ++ /* FE_16APSK_56 */ ++ 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A, ++ /* FE_16APSK_89 */ ++ 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A, ++ /* FE_16APSK_910 */ ++ 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A, ++ /* FE_32APSK_34 */ ++ 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, ++ /* FE_32APSK_45 */ ++ 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, ++ /* FE_32APSK_56 */ ++ 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, ++ /* FE_32APSK_89 */ ++ 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, ++ /* FE_32APSK_910 */ ++ 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, ++}; ++ ++static u8 get_optim_cloop(struct stv *state, ++ enum FE_STV0910_ModCod ModCod, u32 Pilots) ++{ ++ int i = 0; ++ if (ModCod >= FE_32APSK_910) ++ i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10; ++ else if (ModCod >= FE_QPSK_14) ++ i = ((int)ModCod - (int)FE_QPSK_14) * 10; ++ ++ if (state->SymbolRate <= 3000000) ++ i += 0; ++ else if (state->SymbolRate <= 7000000) ++ i += 2; ++ else if (state->SymbolRate <= 15000000) ++ i += 4; ++ else if (state->SymbolRate <= 25000000) ++ i += 6; ++ else ++ i += 8; ++ ++ if (!Pilots) ++ i += 1; ++ ++ return S2CarLoop[i]; ++} ++ ++static int GetCurSymbolRate(struct stv *state, u32 *pSymbolRate) ++{ ++ int status = 0; ++ u8 SymbFreq0; ++ u8 SymbFreq1; ++ u8 SymbFreq2; ++ u8 SymbFreq3; ++ u8 TimOffs0; ++ u8 TimOffs1; ++ u8 TimOffs2; ++ u32 SymbolRate; ++ s32 TimingOffset; ++ ++ *pSymbolRate = 0; ++ if (!state->Started) ++ return status; ++ ++ read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &SymbFreq3); ++ read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &SymbFreq2); ++ read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &SymbFreq1); ++ read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &SymbFreq0); ++ read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &TimOffs2); ++ read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &TimOffs1); ++ read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &TimOffs0); ++ ++ SymbolRate = ((u32) SymbFreq3 << 24) | ((u32) SymbFreq2 << 16) | ++ ((u32) SymbFreq1 << 8) | (u32) SymbFreq0; ++ TimingOffset = ((u32) TimOffs2 << 16) | ((u32) TimOffs1 << 8) | ++ (u32) TimOffs0; ++ ++ if ((TimingOffset & (1<<23)) != 0) ++ TimingOffset |= 0xFF000000; /* Sign extent */ ++ ++ SymbolRate = (u32) (((u64) SymbolRate * state->base->mclk) >> 32); ++ TimingOffset = (s32) (((s64) SymbolRate * (s64) TimingOffset) >> 29); ++ ++ *pSymbolRate = SymbolRate + TimingOffset; ++ ++ return 0; ++} ++ ++static int GetSignalParameters(struct stv *state) ++{ ++ if (!state->Started) ++ return -1; ++ ++ if (state->ReceiveMode == Mode_DVBS2) { ++ u8 tmp; ++ u8 rolloff; ++ ++ read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); ++ state->ModCod = (enum FE_STV0910_ModCod) ((tmp & 0x7c) >> 2); ++ state->Pilots = (tmp & 0x01) != 0; ++ state->FECType = (enum DVBS2_FECType) ((tmp & 0x02) >> 1); ++ ++ read_reg(state, RSTV0910_P2_TMGOBS + state->regoff, &rolloff); ++ rolloff = rolloff >> 6; ++ state->FERollOff = (enum FE_STV0910_RollOff) rolloff; ++ ++ } else if (state->ReceiveMode == Mode_DVBS) { ++ /* todo */ ++ } ++ return 0; ++} ++ ++static int TrackingOptimization(struct stv *state) ++{ ++ u32 SymbolRate = 0; ++ u8 tmp; ++ ++ GetCurSymbolRate(state, &SymbolRate); ++ read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); ++ tmp &= ~0xC0; ++ ++ switch (state->ReceiveMode) { ++ case Mode_DVBS: ++ tmp |= 0x40; break; ++ case Mode_DVBS2: ++ tmp |= 0x80; break; ++ default: ++ tmp |= 0xC0; break; ++ } ++ write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); ++ ++ if (state->ReceiveMode == Mode_DVBS2) { ++ /* force to PRE BCH Rate */ ++ write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, ++ BER_SRC_S2 | state->BERScale); ++ ++ if (state->FECType == DVBS2_64K) { ++ u8 aclc = get_optim_cloop(state, state->ModCod, ++ state->Pilots); ++ ++ if (state->ModCod <= FE_QPSK_910) { ++ write_reg(state, RSTV0910_P2_ACLC2S2Q + ++ state->regoff, aclc); ++ } else if (state->ModCod <= FE_8PSK_910) { ++ write_reg(state, RSTV0910_P2_ACLC2S2Q + ++ state->regoff, 0x2a); ++ write_reg(state, RSTV0910_P2_ACLC2S28 + ++ state->regoff, aclc); ++ } else if (state->ModCod <= FE_16APSK_910) { ++ write_reg(state, RSTV0910_P2_ACLC2S2Q + ++ state->regoff, 0x2a); ++ write_reg(state, RSTV0910_P2_ACLC2S216A + ++ state->regoff, aclc); ++ } else if (state->ModCod <= FE_32APSK_910) { ++ write_reg(state, RSTV0910_P2_ACLC2S2Q + ++ state->regoff, 0x2a); ++ write_reg(state, RSTV0910_P2_ACLC2S232A + ++ state->regoff, aclc); ++ } ++ } ++ } ++ if (state->ReceiveMode == Mode_DVBS) { ++ u8 tmp; ++ ++ read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); ++ state->PunctureRate = FEC_NONE; ++ switch (tmp & 0x1F) { ++ case 0x0d: ++ state->PunctureRate = FEC_1_2; ++ break; ++ case 0x12: ++ state->PunctureRate = FEC_2_3; ++ break; ++ case 0x15: ++ state->PunctureRate = FEC_3_4; ++ break; ++ case 0x18: ++ state->PunctureRate = FEC_5_6; ++ break; ++ case 0x1A: ++ state->PunctureRate = FEC_7_8; ++ break; ++ } ++ } ++ return 0; ++} ++ ++static int GetSignalToNoise(struct stv *state, s32 *SignalToNoise) ++{ ++ int i; ++ u8 Data0; ++ u8 Data1; ++ u16 Data; ++ int nLookup; ++ struct SLookupSNTable *Lookup; ++ ++ *SignalToNoise = 0; ++ ++ if (!state->Started) ++ return 0; ++ ++ if (state->ReceiveMode == Mode_DVBS2) { ++ read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, &Data1); ++ read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, &Data0); ++ nLookup = ARRAY_SIZE(S2_SN_Lookup); ++ Lookup = S2_SN_Lookup; ++ } else { ++ read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, &Data1); ++ read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, &Data0); ++ nLookup = ARRAY_SIZE(S1_SN_Lookup); ++ Lookup = S1_SN_Lookup; ++ } ++ Data = (((u16)Data1) << 8) | (u16) Data0; ++ if (Data > Lookup[0].RefValue) { ++ *SignalToNoise = Lookup[0].SignalToNoise; ++ } else if (Data <= Lookup[nLookup-1].RefValue) { ++ *SignalToNoise = Lookup[nLookup-1].SignalToNoise; ++ } else { ++ for (i = 0; i < nLookup - 1; i += 1) { ++ if (Data <= Lookup[i].RefValue && ++ Data > Lookup[i+1].RefValue) { ++ *SignalToNoise = ++ (s32)(Lookup[i].SignalToNoise) + ++ ((s32)(Data - Lookup[i].RefValue) * ++ (s32)(Lookup[i+1].SignalToNoise - ++ Lookup[i].SignalToNoise)) / ++ ((s32)(Lookup[i+1].RefValue) - ++ (s32)(Lookup[i].RefValue)); ++ break; ++ } ++ } ++ } ++ return 0; ++} ++ ++static int GetBitErrorRateS(struct stv *state, u32 *BERNumerator, ++ u32 *BERDenominator) ++{ ++ u8 Regs[3]; ++ ++ int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, ++ Regs, 3); ++ ++ if (status) ++ return -1; ++ ++ if ((Regs[0] & 0x80) == 0) { ++ state->LastBERDenominator = 1 << ((state->BERScale * 2) + ++ 10 + 3); ++ state->LastBERNumerator = ((u32) (Regs[0] & 0x7F) << 16) | ++ ((u32) Regs[1] << 8) | Regs[2]; ++ if (state->LastBERNumerator < 256 && state->BERScale < 6) { ++ state->BERScale += 1; ++ status = write_reg(state, RSTV0910_P2_ERRCTRL1 + ++ state->regoff, ++ 0x20 | state->BERScale); ++ } else if (state->LastBERNumerator > 1024 && ++ state->BERScale > 2) { ++ state->BERScale -= 1; ++ status = write_reg(state, RSTV0910_P2_ERRCTRL1 + ++ state->regoff, 0x20 | ++ state->BERScale); ++ } ++ } ++ *BERNumerator = state->LastBERNumerator; ++ *BERDenominator = state->LastBERDenominator; ++ return 0; ++} ++ ++static u32 DVBS2_nBCH(enum DVBS2_ModCod ModCod, enum DVBS2_FECType FECType) ++{ ++ static u32 nBCH[][2] = { ++ {16200, 3240}, /* QPSK_1_4, */ ++ {21600, 5400}, /* QPSK_1_3, */ ++ {25920, 6480}, /* QPSK_2_5, */ ++ {32400, 7200}, /* QPSK_1_2, */ ++ {38880, 9720}, /* QPSK_3_5, */ ++ {43200, 10800}, /* QPSK_2_3, */ ++ {48600, 11880}, /* QPSK_3_4, */ ++ {51840, 12600}, /* QPSK_4_5, */ ++ {54000, 13320}, /* QPSK_5_6, */ ++ {57600, 14400}, /* QPSK_8_9, */ ++ {58320, 16000}, /* QPSK_9_10, */ ++ {43200, 9720}, /* 8PSK_3_5, */ ++ {48600, 10800}, /* 8PSK_2_3, */ ++ {51840, 11880}, /* 8PSK_3_4, */ ++ {54000, 13320}, /* 8PSK_5_6, */ ++ {57600, 14400}, /* 8PSK_8_9, */ ++ {58320, 16000}, /* 8PSK_9_10, */ ++ {43200, 10800}, /* 16APSK_2_3, */ ++ {48600, 11880}, /* 16APSK_3_4, */ ++ {51840, 12600}, /* 16APSK_4_5, */ ++ {54000, 13320}, /* 16APSK_5_6, */ ++ {57600, 14400}, /* 16APSK_8_9, */ ++ {58320, 16000}, /* 16APSK_9_10 */ ++ {48600, 11880}, /* 32APSK_3_4, */ ++ {51840, 12600}, /* 32APSK_4_5, */ ++ {54000, 13320}, /* 32APSK_5_6, */ ++ {57600, 14400}, /* 32APSK_8_9, */ ++ {58320, 16000}, /* 32APSK_9_10 */ ++ }; ++ ++ if (ModCod >= DVBS2_QPSK_1_4 && ++ ModCod <= DVBS2_32APSK_9_10 && FECType <= DVBS2_16K) ++ return nBCH[FECType][ModCod]; ++ return 64800; ++} ++ ++static int GetBitErrorRateS2(struct stv *state, u32 *BERNumerator, ++ u32 *BERDenominator) ++{ ++ u8 Regs[3]; ++ ++ int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, ++ Regs, 3); ++ ++ if (status) ++ return -1; ++ ++ if ((Regs[0] & 0x80) == 0) { ++ state->LastBERDenominator = ++ DVBS2_nBCH((enum DVBS2_ModCod) state->ModCod, ++ state->FECType) << ++ (state->BERScale * 2); ++ state->LastBERNumerator = (((u32) Regs[0] & 0x7F) << 16) | ++ ((u32) Regs[1] << 8) | Regs[2]; ++ if (state->LastBERNumerator < 256 && state->BERScale < 6) { ++ state->BERScale += 1; ++ write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, ++ 0x20 | state->BERScale); ++ } else if (state->LastBERNumerator > 1024 && ++ state->BERScale > 2) { ++ state->BERScale -= 1; ++ write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, ++ 0x20 | state->BERScale); ++ } ++ } ++ *BERNumerator = state->LastBERNumerator; ++ *BERDenominator = state->LastBERDenominator; ++ return status; ++} ++ ++static int GetBitErrorRate(struct stv *state, u32 *BERNumerator, ++ u32 *BERDenominator) ++{ ++ *BERNumerator = 0; ++ *BERDenominator = 1; ++ ++ switch (state->ReceiveMode) { ++ case Mode_DVBS: ++ return GetBitErrorRateS(state, BERNumerator, BERDenominator); ++ break; ++ case Mode_DVBS2: ++ return GetBitErrorRateS2(state, BERNumerator, BERDenominator); ++ default: ++ break; ++ } ++ return 0; ++} ++ ++static int init(struct dvb_frontend *fe) ++{ ++ return 0; ++} ++ ++static int set_mclock(struct stv *state, u32 MasterClock) ++{ ++ u32 idf = 1; ++ u32 odf = 4; ++ u32 quartz = state->base->extclk / 1000000; ++ u32 Fphi = MasterClock / 1000000; ++ u32 ndiv = (Fphi * odf * idf) / quartz; ++ u32 cp = 7; ++ u32 fvco; ++ ++ if (ndiv >= 7 && ndiv <= 71) ++ cp = 7; ++ else if (ndiv >= 72 && ndiv <= 79) ++ cp = 8; ++ else if (ndiv >= 80 && ndiv <= 87) ++ cp = 9; ++ else if (ndiv >= 88 && ndiv <= 95) ++ cp = 10; ++ else if (ndiv >= 96 && ndiv <= 103) ++ cp = 11; ++ else if (ndiv >= 104 && ndiv <= 111) ++ cp = 12; ++ else if (ndiv >= 112 && ndiv <= 119) ++ cp = 13; ++ else if (ndiv >= 120 && ndiv <= 127) ++ cp = 14; ++ else if (ndiv >= 128 && ndiv <= 135) ++ cp = 15; ++ else if (ndiv >= 136 && ndiv <= 143) ++ cp = 16; ++ else if (ndiv >= 144 && ndiv <= 151) ++ cp = 17; ++ else if (ndiv >= 152 && ndiv <= 159) ++ cp = 18; ++ else if (ndiv >= 160 && ndiv <= 167) ++ cp = 19; ++ else if (ndiv >= 168 && ndiv <= 175) ++ cp = 20; ++ else if (ndiv >= 176 && ndiv <= 183) ++ cp = 21; ++ else if (ndiv >= 184 && ndiv <= 191) ++ cp = 22; ++ else if (ndiv >= 192 && ndiv <= 199) ++ cp = 23; ++ else if (ndiv >= 200 && ndiv <= 207) ++ cp = 24; ++ else if (ndiv >= 208 && ndiv <= 215) ++ cp = 25; ++ else if (ndiv >= 216 && ndiv <= 223) ++ cp = 26; ++ else if (ndiv >= 224 && ndiv <= 225) ++ cp = 27; ++ ++ write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf); ++ write_reg(state, RSTV0910_NCOARSE2, odf); ++ write_reg(state, RSTV0910_NCOARSE1, ndiv); ++ ++ fvco = (quartz * 2 * ndiv) / idf; ++ state->base->mclk = fvco / (2 * odf) * 1000000; ++ ++ pr_info("ndiv = %d, MasterClock = %d\n", ndiv, state->base->mclk); ++ return 0; ++} ++ ++static int Stop(struct stv *state) ++{ ++ if (state->Started) { ++ u8 tmp; ++ ++ write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, ++ state->tscfgh | 0x01); ++ read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); ++ tmp &= ~0x01; /*release reset DVBS2 packet delin*/ ++ write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); ++ /* Blind optim*/ ++ write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); ++ /* Stop the demod */ ++ write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); ++ state->Started = 0; ++ } ++ state->ReceiveMode = Mode_None; ++ return 0; ++} ++ ++ ++static int Start(struct stv *state, struct dtv_frontend_properties *p) ++{ ++ s32 Freq; ++ u8 regDMDCFGMD; ++ u16 symb; ++ ++ if (p->symbol_rate < 100000 || p->symbol_rate > 70000000) ++ return -EINVAL; ++ ++ state->ReceiveMode = Mode_None; ++ state->DemodLockTime = 0; ++ ++ /* Demod Stop*/ ++ if (state->Started) ++ write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); ++ ++ if (p->symbol_rate <= 1000000) { /*SR <=1Msps*/ ++ state->DemodTimeout = 3000; ++ state->FecTimeout = 2000; ++ } else if (p->symbol_rate <= 2000000) { /*1Msps < SR <=2Msps*/ ++ state->DemodTimeout = 2500; ++ state->FecTimeout = 1300; ++ } else if (p->symbol_rate <= 5000000) { /*2Msps< SR <=5Msps*/ ++ state->DemodTimeout = 1000; ++ state->FecTimeout = 650; ++ } else if (p->symbol_rate <= 10000000) { /*5Msps< SR <=10Msps*/ ++ state->DemodTimeout = 700; ++ state->FecTimeout = 350; ++ } else if (p->symbol_rate < 20000000) { /*10Msps< SR <=20Msps*/ ++ state->DemodTimeout = 400; ++ state->FecTimeout = 200; ++ } else { /*SR >=20Msps*/ ++ state->DemodTimeout = 300; ++ state->FecTimeout = 200; ++ } ++ ++ /* Set the Init Symbol rate*/ ++ symb = MulDiv32(p->symbol_rate, 65536, state->base->mclk); ++ write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, ++ ((symb >> 8) & 0x7F)); ++ write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); ++ ++ pr_info("symb = %u\n", symb); ++ ++ state->DEMOD |= 0x80; ++ write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->DEMOD); ++ ++ /* FE_STV0910_SetSearchStandard */ ++ read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®DMDCFGMD); ++ write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ++ regDMDCFGMD |= 0xC0); ++ ++ /* Disable DSS */ ++ write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); ++ write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); ++ ++ /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA*/ ++ write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); ++ write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); ++ write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); ++ write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); ++ write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); ++ /* Reset demod */ ++ write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); ++ ++ write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); ++ ++ Freq = (state->SearchRange / 2000) + 600; ++ if (p->symbol_rate <= 5000000) ++ Freq -= (600 + 80); ++ Freq = (Freq << 16) / (state->base->mclk / 1000); ++ ++ write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, ++ (Freq >> 8) & 0xff); ++ write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (Freq & 0xff)); ++ /*CFR Low Setting*/ ++ Freq = -Freq; ++ write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, ++ (Freq >> 8) & 0xff); ++ write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (Freq & 0xff)); ++ ++ /* init the demod frequency offset to 0 */ ++ write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); ++ write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); ++ ++ write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); ++ /* Trigger acq */ ++ write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); ++ ++ state->DemodLockTime += TUNING_DELAY; ++ state->Started = 1; ++ ++ return 0; ++} ++ ++static int init_diseqc(struct stv *state) ++{ ++ u16 offs = state->nr ? 0x40 : 0; /* Address offset */ ++ u8 Freq = ((state->base->mclk + 11000 * 32) / (22000 * 32)); ++ ++ /* Disable receiver */ ++ write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00); ++ write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */ ++ write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */ ++ write_reg(state, RSTV0910_P1_DISTXF22 + offs, Freq); ++ return 0; ++} ++ ++static int probe(struct stv *state) ++{ ++ u8 id; ++ ++ state->ReceiveMode = Mode_None; ++ state->Started = 0; ++ ++ if (read_reg(state, RSTV0910_MID, &id) < 0) ++ return -1; ++ ++ if (id != 0x51) ++ return -EINVAL; ++ pr_info("Found STV0910 id=0x%02x\n", id); ++ ++ /* Configure the I2C repeater to off */ ++ write_reg(state, RSTV0910_P1_I2CRPT, 0x24); ++ /* Configure the I2C repeater to off */ ++ write_reg(state, RSTV0910_P2_I2CRPT, 0x24); ++ /* Set the I2C to oversampling ratio */ ++ write_reg(state, RSTV0910_I2CCFG, 0x88); ++ ++ write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ ++ write_reg(state, RSTV0910_PADCFG, 0x05); /* RF AGC Pads Dev = 05 */ ++ write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ ++ write_reg(state, RSTV0910_TSGENERAL, 0x00); /* TSGENERAL */ ++ write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ ++ write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ ++ ++ ++ write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */ ++ write_reg(state, RSTV0910_TSTRES0, 0x00); ++ ++ set_mclock(state, 135000000); ++ ++ /* TS output */ ++ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh); ++ write_reg(state, RSTV0910_P1_TSCFGM , 0xC0); /* Manual speed */ ++ write_reg(state, RSTV0910_P1_TSCFGL , 0x20); ++ ++ /* Speed = 67.5 MHz */ ++ write_reg(state, RSTV0910_P1_TSSPEED , state->tsspeed); ++ ++ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh); ++ write_reg(state, RSTV0910_P2_TSCFGM , 0xC0); /* Manual speed */ ++ write_reg(state, RSTV0910_P2_TSCFGL , 0x20); ++ ++ /* Speed = 67.5 MHz */ ++ write_reg(state, RSTV0910_P2_TSSPEED , state->tsspeed); ++ ++ /* Reset stream merger */ ++ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh); ++ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh); ++ ++ write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt); ++ write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt); ++ ++ init_diseqc(state); ++ return 0; ++} ++ ++ ++static int gate_ctrl(struct dvb_frontend *fe, int enable) ++{ ++ struct stv *state = fe->demodulator_priv; ++ u8 i2crpt = state->i2crpt & ~0x86; ++ ++ if (enable) ++ mutex_lock(&state->base->i2c_lock); ++ ++ if (enable) ++ i2crpt |= 0x80; ++ else ++ i2crpt |= 0x02; ++ ++ if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT : ++ RSTV0910_P1_I2CRPT, i2crpt) < 0) ++ return -EIO; ++ ++ state->i2crpt = i2crpt; ++ ++ if (!enable) ++ mutex_unlock(&state->base->i2c_lock); ++ return 0; ++} ++ ++static void release(struct dvb_frontend *fe) ++{ ++ struct stv *state = fe->demodulator_priv; ++ ++ state->base->count--; ++ if (state->base->count == 0) { ++ pr_info("remove STV base\n"); ++ list_del(&state->base->stvlist); ++ } ++ kfree(state); ++} ++ ++static int set_parameters(struct dvb_frontend *fe) ++{ ++ int stat = 0; ++ struct stv *state = fe->demodulator_priv; ++ u32 IF; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ ++ Stop(state); ++ if (fe->ops.tuner_ops.set_params) ++ fe->ops.tuner_ops.set_params(fe); ++ if (fe->ops.tuner_ops.get_if_frequency) ++ fe->ops.tuner_ops.get_if_frequency(fe, &IF); ++ state->SymbolRate = p->symbol_rate; ++ stat = Start(state, p); ++ return stat; ++} ++ ++ ++static int read_status(struct dvb_frontend *fe, fe_status_t *status) ++{ ++ struct stv *state = fe->demodulator_priv; ++ u8 DmdState = 0; ++ u8 DStatus = 0; ++ enum ReceiveMode CurReceiveMode = Mode_None; ++ u32 FECLock = 0; ++ ++ read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &DmdState); ++ ++ if (DmdState & 0x40) { ++ read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &DStatus); ++ if (DStatus & 0x08) ++ CurReceiveMode = (DmdState & 0x20) ? ++ Mode_DVBS : Mode_DVBS2; ++ } ++ if (CurReceiveMode == Mode_None) { ++ *status = 0; ++ return 0; ++ } ++ ++ *status |= 0x0f; ++ if (state->ReceiveMode == Mode_None) { ++ state->ReceiveMode = CurReceiveMode; ++ state->DemodLockTime = jiffies; ++ state->FirstTimeLock = 0; ++ ++ write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, ++ state->tscfgh); ++ usleep_range(3000, 4000); ++ write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, ++ state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, ++ state->tscfgh); ++ } ++ if (DmdState & 0x40) { ++ if (state->ReceiveMode == Mode_DVBS2) { ++ u8 PDELStatus; ++ read_reg(state, ++ RSTV0910_P2_PDELSTATUS1 + state->regoff, ++ &PDELStatus); ++ FECLock = (PDELStatus & 0x02) != 0; ++ } else { ++ u8 VStatus; ++ read_reg(state, ++ RSTV0910_P2_VSTATUSVIT + state->regoff, ++ &VStatus); ++ FECLock = (VStatus & 0x08) != 0; ++ } ++ } ++ ++ if (!FECLock) ++ return 0; ++ ++ *status |= 0x10; ++ ++ if (state->FirstTimeLock) { ++ u8 tmp; ++ ++ state->FirstTimeLock = 0; ++ GetSignalParameters(state); ++ ++ if (state->ReceiveMode == Mode_DVBS2) { ++ /* FSTV0910_P2_MANUALSX_ROLLOFF, ++ FSTV0910_P2_MANUALS2_ROLLOFF = 0 */ ++ state->DEMOD &= ~0x84; ++ write_reg(state, RSTV0910_P2_DEMOD + state->regoff, ++ state->DEMOD); ++ read_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, ++ &tmp); ++ /*reset DVBS2 packet delinator error counter */ ++ tmp |= 0x40; ++ write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, ++ tmp); ++ /*reset DVBS2 packet delinator error counter */ ++ tmp &= ~0x40; ++ write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, ++ tmp); ++ ++ state->BERScale = 2; ++ state->LastBERNumerator = 0; ++ state->LastBERDenominator = 1; ++ /* force to PRE BCH Rate */ ++ write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, ++ BER_SRC_S2 | state->BERScale); ++ } else { ++ state->BERScale = 2; ++ state->LastBERNumerator = 0; ++ state->LastBERDenominator = 1; ++ /* force to PRE RS Rate */ ++ write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, ++ BER_SRC_S | state->BERScale); ++ } ++ /*Reset the Total packet counter */ ++ write_reg(state, RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); ++ /*Reset the packet Error counter2 (and Set it to ++ infinit error count mode )*/ ++ write_reg(state, RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); ++ ++ TrackingOptimization(state); ++ } ++ return 0; ++} ++ ++static int tune(struct dvb_frontend *fe, bool re_tune, ++ unsigned int mode_flags, ++ unsigned int *delay, fe_status_t *status) ++{ ++ struct stv *state = fe->demodulator_priv; ++ int r; ++ ++ if (re_tune) { ++ r = set_parameters(fe); ++ if (r) ++ return r; ++ state->tune_time = jiffies; ++ } ++ if (*status & FE_HAS_LOCK) ++ return 0; ++ *delay = HZ; ++ ++ r = read_status(fe, status); ++ if (r) ++ return r; ++ return 0; ++} ++ ++ ++static int get_algo(struct dvb_frontend *fe) ++{ ++ return DVBFE_ALGO_HW; ++} ++ ++static int set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) ++{ ++ struct stv *state = fe->demodulator_priv; ++ u16 offs = state->nr ? 0x40 : 0; ++ ++ switch (tone) { ++ case SEC_TONE_ON: ++ return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38); ++ break; ++ case SEC_TONE_OFF: ++ return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a); ++ break; ++ default: ++ break; ++ } ++ return -EINVAL; ++} ++ ++static int send_master_cmd(struct dvb_frontend *fe, ++ struct dvb_diseqc_master_cmd *cmd) ++{ ++ struct stv *state = fe->demodulator_priv; ++ u16 offs = state->nr ? 0x40 : 0; ++ int i; ++ ++ write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E); ++ for (i = 0; i < cmd->msg_len; i++) ++ write_reg(state, RSTV0910_P1_DISTXFIFO + offs, cmd->msg[i]); ++ write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); ++ return 0; ++} ++ ++static int recv_slave_reply(struct dvb_frontend *fe, ++ struct dvb_diseqc_slave_reply *reply) ++{ ++ return 0; ++} ++ ++static int send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) ++{ ++ return 0; ++} ++ ++static int sleep(struct dvb_frontend *fe) ++{ ++ struct stv *state = fe->demodulator_priv; ++ ++ pr_info("sleep %d\n", state->nr); ++ Stop(state); ++ return 0; ++} ++ ++static int read_snr(struct dvb_frontend *fe, u16 *snr) ++{ ++ struct stv *state = fe->demodulator_priv; ++ s32 SNR; ++ ++ *snr = 0; ++ if (GetSignalToNoise(state, &SNR)) ++ return -EIO; ++ *snr = SNR; ++ return 0; ++} ++ ++static int read_ber(struct dvb_frontend *fe, u32 *ber) ++{ ++ struct stv *state = fe->demodulator_priv; ++ u32 n, d; ++ ++ GetBitErrorRate(state, &n, &d); ++ *ber = n / d; ++ ++ return 0; ++} ++ ++static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) ++{ ++ struct stv *state = fe->demodulator_priv; ++ u8 Agc1, Agc0; ++ ++ read_reg(state, RSTV0910_P2_AGCIQIN1 + state->regoff, &Agc1); ++ read_reg(state, RSTV0910_P2_AGCIQIN0 + state->regoff, &Agc0); ++ ++ *strength = ((255 - Agc1) * 3300) / 256; ++ return 0; ++} ++ ++static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) ++{ ++ /* struct stv *state = fe->demodulator_priv; */ ++ ++ ++ return 0; ++} ++ ++static struct dvb_frontend_ops stv0910_ops = { ++ .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, ++ .info = { ++ .name = "STV0910", ++ .frequency_min = 950000, ++ .frequency_max = 2150000, ++ .frequency_stepsize = 0, ++ .frequency_tolerance = 0, ++ .symbol_rate_min = 1000000, ++ .symbol_rate_max = 70000000, ++ .caps = FE_CAN_INVERSION_AUTO | ++ FE_CAN_FEC_AUTO | ++ FE_CAN_QPSK | ++ FE_CAN_2G_MODULATION ++ }, ++ .init = init, ++ .sleep = sleep, ++ .release = release, ++ .i2c_gate_ctrl = gate_ctrl, ++ .get_frontend_algo = get_algo, ++ .tune = tune, ++ .read_status = read_status, ++ .set_tone = set_tone, ++ ++ .diseqc_send_master_cmd = send_master_cmd, ++ .diseqc_send_burst = send_burst, ++ .diseqc_recv_slave_reply = recv_slave_reply, ++ ++ .read_snr = read_snr, ++ .read_ber = read_ber, ++ .read_signal_strength = read_signal_strength, ++ .read_ucblocks = read_ucblocks, ++}; ++ ++static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr) ++{ ++ struct stv_base *p; ++ ++ list_for_each_entry(p, &stvlist, stvlist) ++ if (p->i2c == i2c && p->adr == adr) ++ return p; ++ return NULL; ++} ++ ++struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, ++ struct stv0910_cfg *cfg, ++ int nr) ++{ ++ struct stv *state; ++ struct stv_base *base; ++ ++ state = kzalloc(sizeof(struct stv), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ ++ state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40); ++ state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4); ++ state->tsspeed = 0x40; ++ state->nr = nr; ++ state->regoff = state->nr ? 0 : 0x200; ++ state->SearchRange = 16000000; ++ state->DEMOD = 0x10; /* Inversion : Auto with reset to 0 */ ++ state->ReceiveMode = Mode_None; ++ ++ base = match_base(i2c, cfg->adr); ++ if (base) { ++ base->count++; ++ state->base = base; ++ } else { ++ base = kzalloc(sizeof(struct stv_base), GFP_KERNEL); ++ if (!base) ++ goto fail; ++ base->i2c = i2c; ++ base->adr = cfg->adr; ++ base->count = 1; ++ base->extclk = cfg->clk ? cfg->clk : 30000000; ++ ++ mutex_init(&base->i2c_lock); ++ mutex_init(&base->reg_lock); ++ state->base = base; ++ if (probe(state) < 0) { ++ kfree(base); ++ goto fail; ++ } ++ list_add(&base->stvlist, &stvlist); ++ } ++ state->fe.ops = stv0910_ops; ++ state->fe.demodulator_priv = state; ++ state->nr = nr; ++ ++ return &state->fe; ++ ++fail: ++ kfree(state); ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(stv0910_attach); ++ ++MODULE_DESCRIPTION("STV0910 driver"); ++MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/media/dvb-frontends/stv0910.h b/drivers/media/dvb-frontends/stv0910.h +new file mode 100644 +index 0000000..a6fad29 +--- /dev/null ++++ b/drivers/media/dvb-frontends/stv0910.h +@@ -0,0 +1,31 @@ ++#ifndef _STV0910_H_ ++#define _STV0910_H_ ++ ++#include ++#include ++ ++struct stv0910_cfg { ++ u32 clk; ++ u8 adr; ++ u8 parallel; ++ u8 rptlvl; ++}; ++ ++#if defined(CONFIG_DVB_STV0910) || \ ++ (defined(CONFIG_DVB_STV0910_MODULE) && defined(MODULE)) ++ ++extern struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, ++ struct stv0910_cfg *cfg, int nr); ++#else ++ ++static inline struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, ++ struct stv0910_cfg *cfg, ++ int nr) ++{ ++ pr_warn("%s: driver disabled by Kconfig\n", __func__); ++ return NULL; ++} ++ ++#endif ++ ++#endif +diff --git a/drivers/media/dvb-frontends/stv0910_regs.h b/drivers/media/dvb-frontends/stv0910_regs.h +new file mode 100644 +index 0000000..16e922f +--- /dev/null ++++ b/drivers/media/dvb-frontends/stv0910_regs.h +@@ -0,0 +1,3998 @@ ++// @DVB-S/DVB-S2 STMicroelectronics STV0900 register defintions ++// Author Manfred Völkel, August 2013 ++// (c) 2013 Digital Devices GmbH Germany. All rights reserved ++ ++// $Id: DD_STV0910Register.h 504 2013-09-02 23:02:14Z manfred $ ++ ++/* ======================================================================= ++-- Registers Declaration (Internal ST, All Applications ) ++-- ------------------------- ++-- Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). ++-- ++-- Each field (FSTV0910__XXXXX)is defined as follow: ++-- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] ++ ======================================================================= */ ++ ++/*MID*/ ++#define RSTV0910_MID 0xf100 ++#define FSTV0910_MCHIP_IDENT 0xf10000f0 ++#define FSTV0910_MRELEASE 0xf100000f ++ ++/*DID*/ ++#define RSTV0910_DID 0xf101 ++#define FSTV0910_DEVICE_ID 0xf10100ff ++ ++/*DACR1*/ ++#define RSTV0910_DACR1 0xf113 ++#define FSTV0910_DAC_MODE 0xf11300e0 ++#define FSTV0910_DAC_VALUE1 0xf113000f ++ ++/*DACR2*/ ++#define RSTV0910_DACR2 0xf114 ++#define FSTV0910_DAC_VALUE0 0xf11400ff ++ ++/*PADCFG*/ ++#define RSTV0910_PADCFG 0xf11a ++#define FSTV0910_AGCRF2_OPD 0xf11a0008 ++#define FSTV0910_AGCRF2_XOR 0xf11a0004 ++#define FSTV0910_AGCRF1_OPD 0xf11a0002 ++#define FSTV0910_AGCRF1_XOR 0xf11a0001 ++ ++/*OUTCFG2*/ ++#define RSTV0910_OUTCFG2 0xf11b ++#define FSTV0910_TS2_ERROR_XOR 0xf11b0080 ++#define FSTV0910_TS2_DPN_XOR 0xf11b0040 ++#define FSTV0910_TS2_STROUT_XOR 0xf11b0020 ++#define FSTV0910_TS2_CLOCKOUT_XOR 0xf11b0010 ++#define FSTV0910_TS1_ERROR_XOR 0xf11b0008 ++#define FSTV0910_TS1_DPN_XOR 0xf11b0004 ++#define FSTV0910_TS1_STROUT_XOR 0xf11b0002 ++#define FSTV0910_TS1_CLOCKOUT_XOR 0xf11b0001 ++ ++/*OUTCFG*/ ++#define RSTV0910_OUTCFG 0xf11c ++#define FSTV0910_INV_DATA6 0xf11c0080 ++#define FSTV0910_TS2_OUTSER_HZ 0xf11c0020 ++#define FSTV0910_TS1_OUTSER_HZ 0xf11c0010 ++#define FSTV0910_TS2_OUTPAR_HZ 0xf11c0008 ++#define FSTV0910_TS1_OUTPAR_HZ 0xf11c0004 ++#define FSTV0910_TS_SERDATA0 0xf11c0002 ++ ++/*IRQSTATUS3*/ ++#define RSTV0910_IRQSTATUS3 0xf120 ++#define FSTV0910_SPLL_LOCK 0xf1200020 ++#define FSTV0910_SSTREAM_LCK_1 0xf1200010 ++#define FSTV0910_SSTREAM_LCK_2 0xf1200008 ++#define FSTV0910_SDVBS1_PRF_2 0xf1200002 ++#define FSTV0910_SDVBS1_PRF_1 0xf1200001 ++ ++/*IRQSTATUS2*/ ++#define RSTV0910_IRQSTATUS2 0xf121 ++#define FSTV0910_SSPY_ENDSIM_1 0xf1210080 ++#define FSTV0910_SSPY_ENDSIM_2 0xf1210040 ++#define FSTV0910_SPKTDEL_ERROR_2 0xf1210010 ++#define FSTV0910_SPKTDEL_LOCKB_2 0xf1210008 ++#define FSTV0910_SPKTDEL_LOCK_2 0xf1210004 ++#define FSTV0910_SPKTDEL_ERROR_1 0xf1210002 ++#define FSTV0910_SPKTDEL_LOCKB_1 0xf1210001 ++ ++/*IRQSTATUS1*/ ++#define RSTV0910_IRQSTATUS1 0xf122 ++#define FSTV0910_SPKTDEL_LOCK_1 0xf1220080 ++#define FSTV0910_SFEC_LOCKB_2 0xf1220040 ++#define FSTV0910_SFEC_LOCK_2 0xf1220020 ++#define FSTV0910_SFEC_LOCKB_1 0xf1220010 ++#define FSTV0910_SFEC_LOCK_1 0xf1220008 ++#define FSTV0910_SDEMOD_LOCKB_2 0xf1220004 ++#define FSTV0910_SDEMOD_LOCK_2 0xf1220002 ++#define FSTV0910_SDEMOD_IRQ_2 0xf1220001 ++ ++/*IRQSTATUS0*/ ++#define RSTV0910_IRQSTATUS0 0xf123 ++#define FSTV0910_SDEMOD_LOCKB_1 0xf1230080 ++#define FSTV0910_SDEMOD_LOCK_1 0xf1230040 ++#define FSTV0910_SDEMOD_IRQ_1 0xf1230020 ++#define FSTV0910_SBCH_ERRFLAG 0xf1230010 ++#define FSTV0910_SECW2_IRQ 0xf1230008 ++#define FSTV0910_SDISEQC2_IRQ 0xf1230004 ++#define FSTV0910_SECW1_IRQ 0xf1230002 ++#define FSTV0910_SDISEQC1_IRQ 0xf1230001 ++ ++/*IRQMASK3*/ ++#define RSTV0910_IRQMASK3 0xf124 ++#define FSTV0910_MPLL_LOCK 0xf1240020 ++#define FSTV0910_MSTREAM_LCK_1 0xf1240010 ++#define FSTV0910_MSTREAM_LCK_2 0xf1240008 ++#define FSTV0910_MDVBS1_PRF_2 0xf1240002 ++#define FSTV0910_MDVBS1_PRF_1 0xf1240001 ++ ++/*IRQMASK2*/ ++#define RSTV0910_IRQMASK2 0xf125 ++#define FSTV0910_MSPY_ENDSIM_1 0xf1250080 ++#define FSTV0910_MSPY_ENDSIM_2 0xf1250040 ++#define FSTV0910_MPKTDEL_ERROR_2 0xf1250010 ++#define FSTV0910_MPKTDEL_LOCKB_2 0xf1250008 ++#define FSTV0910_MPKTDEL_LOCK_2 0xf1250004 ++#define FSTV0910_MPKTDEL_ERROR_1 0xf1250002 ++#define FSTV0910_MPKTDEL_LOCKB_1 0xf1250001 ++ ++/*IRQMASK1*/ ++#define RSTV0910_IRQMASK1 0xf126 ++#define FSTV0910_MPKTDEL_LOCK_1 0xf1260080 ++#define FSTV0910_MFEC_LOCKB_2 0xf1260040 ++#define FSTV0910_MFEC_LOCK_2 0xf1260020 ++#define FSTV0910_MFEC_LOCKB_1 0xf1260010 ++#define FSTV0910_MFEC_LOCK_1 0xf1260008 ++#define FSTV0910_MDEMOD_LOCKB_2 0xf1260004 ++#define FSTV0910_MDEMOD_LOCK_2 0xf1260002 ++#define FSTV0910_MDEMOD_IRQ_2 0xf1260001 ++ ++/*IRQMASK0*/ ++#define RSTV0910_IRQMASK0 0xf127 ++#define FSTV0910_MDEMOD_LOCKB_1 0xf1270080 ++#define FSTV0910_MDEMOD_LOCK_1 0xf1270040 ++#define FSTV0910_MDEMOD_IRQ_1 0xf1270020 ++#define FSTV0910_MBCH_ERRFLAG 0xf1270010 ++#define FSTV0910_MECW2_IRQ 0xf1270008 ++#define FSTV0910_MDISEQC2_IRQ 0xf1270004 ++#define FSTV0910_MECW1_IRQ 0xf1270002 ++#define FSTV0910_MDISEQC1_IRQ 0xf1270001 ++ ++/*I2CCFG*/ ++#define RSTV0910_I2CCFG 0xf129 ++#define FSTV0910_I2C2_FASTMODE 0xf1290080 ++#define FSTV0910_STATUS_WR2 0xf1290040 ++#define FSTV0910_I2C2ADDR_INC 0xf1290030 ++#define FSTV0910_I2C_FASTMODE 0xf1290008 ++#define FSTV0910_STATUS_WR 0xf1290004 ++#define FSTV0910_I2CADDR_INC 0xf1290003 ++ ++/*P1_I2CRPT*/ ++#define RSTV0910_P1_I2CRPT 0xf12a ++#define FSTV0910_P1_I2CT_ON 0xf12a0080 ++#define FSTV0910_P1_ENARPT_LEVEL 0xf12a0070 ++#define FSTV0910_P1_SCLT_DELAY 0xf12a0008 ++#define FSTV0910_P1_STOP_ENABLE 0xf12a0004 ++#define FSTV0910_P1_STOP_SDAT2SDA 0xf12a0002 ++ ++/*P2_I2CRPT*/ ++#define RSTV0910_P2_I2CRPT 0xf12b ++#define FSTV0910_P2_I2CT_ON 0xf12b0080 ++#define FSTV0910_P2_ENARPT_LEVEL 0xf12b0070 ++#define FSTV0910_P2_SCLT_DELAY 0xf12b0008 ++#define FSTV0910_P2_STOP_ENABLE 0xf12b0004 ++#define FSTV0910_P2_STOP_SDAT2SDA 0xf12b0002 ++ ++/*GPIO0CFG*/ ++#define RSTV0910_GPIO0CFG 0xf140 ++#define FSTV0910_GPIO0_OPD 0xf1400080 ++#define FSTV0910_GPIO0_CONFIG 0xf140007e ++#define FSTV0910_GPIO0_XOR 0xf1400001 ++ ++/*GPIO1CFG*/ ++#define RSTV0910_GPIO1CFG 0xf141 ++#define FSTV0910_GPIO1_OPD 0xf1410080 ++#define FSTV0910_GPIO1_CONFIG 0xf141007e ++#define FSTV0910_GPIO1_XOR 0xf1410001 ++ ++/*GPIO2CFG*/ ++#define RSTV0910_GPIO2CFG 0xf142 ++#define FSTV0910_GPIO2_OPD 0xf1420080 ++#define FSTV0910_GPIO2_CONFIG 0xf142007e ++#define FSTV0910_GPIO2_XOR 0xf1420001 ++ ++/*GPIO3CFG*/ ++#define RSTV0910_GPIO3CFG 0xf143 ++#define FSTV0910_GPIO3_OPD 0xf1430080 ++#define FSTV0910_GPIO3_CONFIG 0xf143007e ++#define FSTV0910_GPIO3_XOR 0xf1430001 ++ ++/*GPIO4CFG*/ ++#define RSTV0910_GPIO4CFG 0xf144 ++#define FSTV0910_GPIO4_OPD 0xf1440080 ++#define FSTV0910_GPIO4_CONFIG 0xf144007e ++#define FSTV0910_GPIO4_XOR 0xf1440001 ++ ++/*GPIO5CFG*/ ++#define RSTV0910_GPIO5CFG 0xf145 ++#define FSTV0910_GPIO5_OPD 0xf1450080 ++#define FSTV0910_GPIO5_CONFIG 0xf145007e ++#define FSTV0910_GPIO5_XOR 0xf1450001 ++ ++/*GPIO6CFG*/ ++#define RSTV0910_GPIO6CFG 0xf146 ++#define FSTV0910_GPIO6_OPD 0xf1460080 ++#define FSTV0910_GPIO6_CONFIG 0xf146007e ++#define FSTV0910_GPIO6_XOR 0xf1460001 ++ ++/*GPIO7CFG*/ ++#define RSTV0910_GPIO7CFG 0xf147 ++#define FSTV0910_GPIO7_OPD 0xf1470080 ++#define FSTV0910_GPIO7_CONFIG 0xf147007e ++#define FSTV0910_GPIO7_XOR 0xf1470001 ++ ++/*GPIO8CFG*/ ++#define RSTV0910_GPIO8CFG 0xf148 ++#define FSTV0910_GPIO8_OPD 0xf1480080 ++#define FSTV0910_GPIO8_CONFIG 0xf148007e ++#define FSTV0910_GPIO8_XOR 0xf1480001 ++ ++/*GPIO9CFG*/ ++#define RSTV0910_GPIO9CFG 0xf149 ++#define FSTV0910_GPIO9_OPD 0xf1490080 ++#define FSTV0910_GPIO9_CONFIG 0xf149007e ++#define FSTV0910_GPIO9_XOR 0xf1490001 ++ ++/*GPIO10CFG*/ ++#define RSTV0910_GPIO10CFG 0xf14a ++#define FSTV0910_GPIO10_OPD 0xf14a0080 ++#define FSTV0910_GPIO10_CONFIG 0xf14a007e ++#define FSTV0910_GPIO10_XOR 0xf14a0001 ++ ++/*GPIO11CFG*/ ++#define RSTV0910_GPIO11CFG 0xf14b ++#define FSTV0910_GPIO11_OPD 0xf14b0080 ++#define FSTV0910_GPIO11_CONFIG 0xf14b007e ++#define FSTV0910_GPIO11_XOR 0xf14b0001 ++ ++/*GPIO12CFG*/ ++#define RSTV0910_GPIO12CFG 0xf14c ++#define FSTV0910_GPIO12_OPD 0xf14c0080 ++#define FSTV0910_GPIO12_CONFIG 0xf14c007e ++#define FSTV0910_GPIO12_XOR 0xf14c0001 ++ ++/*GPIO13CFG*/ ++#define RSTV0910_GPIO13CFG 0xf14d ++#define FSTV0910_GPIO13_OPD 0xf14d0080 ++#define FSTV0910_GPIO13_CONFIG 0xf14d007e ++#define FSTV0910_GPIO13_XOR 0xf14d0001 ++ ++/*GPIO14CFG*/ ++#define RSTV0910_GPIO14CFG 0xf14e ++#define FSTV0910_GPIO14_OPD 0xf14e0080 ++#define FSTV0910_GPIO14_CONFIG 0xf14e007e ++#define FSTV0910_GPIO14_XOR 0xf14e0001 ++ ++/*GPIO15CFG*/ ++#define RSTV0910_GPIO15CFG 0xf14f ++#define FSTV0910_GPIO15_OPD 0xf14f0080 ++#define FSTV0910_GPIO15_CONFIG 0xf14f007e ++#define FSTV0910_GPIO15_XOR 0xf14f0001 ++ ++/*GPIO16CFG*/ ++#define RSTV0910_GPIO16CFG 0xf150 ++#define FSTV0910_GPIO16_OPD 0xf1500080 ++#define FSTV0910_GPIO16_CONFIG 0xf150007e ++#define FSTV0910_GPIO16_XOR 0xf1500001 ++ ++/*GPIO17CFG*/ ++#define RSTV0910_GPIO17CFG 0xf151 ++#define FSTV0910_GPIO17_OPD 0xf1510080 ++#define FSTV0910_GPIO17_CONFIG 0xf151007e ++#define FSTV0910_GPIO17_XOR 0xf1510001 ++ ++/*GPIO18CFG*/ ++#define RSTV0910_GPIO18CFG 0xf152 ++#define FSTV0910_GPIO18_OPD 0xf1520080 ++#define FSTV0910_GPIO18_CONFIG 0xf152007e ++#define FSTV0910_GPIO18_XOR 0xf1520001 ++ ++/*GPIO19CFG*/ ++#define RSTV0910_GPIO19CFG 0xf153 ++#define FSTV0910_GPIO19_OPD 0xf1530080 ++#define FSTV0910_GPIO19_CONFIG 0xf153007e ++#define FSTV0910_GPIO19_XOR 0xf1530001 ++ ++/*GPIO20CFG*/ ++#define RSTV0910_GPIO20CFG 0xf154 ++#define FSTV0910_GPIO20_OPD 0xf1540080 ++#define FSTV0910_GPIO20_CONFIG 0xf154007e ++#define FSTV0910_GPIO20_XOR 0xf1540001 ++ ++/*GPIO21CFG*/ ++#define RSTV0910_GPIO21CFG 0xf155 ++#define FSTV0910_GPIO21_OPD 0xf1550080 ++#define FSTV0910_GPIO21_CONFIG 0xf155007e ++#define FSTV0910_GPIO21_XOR 0xf1550001 ++ ++/*GPIO22CFG*/ ++#define RSTV0910_GPIO22CFG 0xf156 ++#define FSTV0910_GPIO22_OPD 0xf1560080 ++#define FSTV0910_GPIO22_CONFIG 0xf156007e ++#define FSTV0910_GPIO22_XOR 0xf1560001 ++ ++/*STRSTATUS1*/ ++#define RSTV0910_STRSTATUS1 0xf16a ++#define FSTV0910_STRSTATUS_SEL2 0xf16a00f0 ++#define FSTV0910_STRSTATUS_SEL1 0xf16a000f ++ ++/*STRSTATUS2*/ ++#define RSTV0910_STRSTATUS2 0xf16b ++#define FSTV0910_STRSTATUS_SEL4 0xf16b00f0 ++#define FSTV0910_STRSTATUS_SEL3 0xf16b000f ++ ++/*STRSTATUS3*/ ++#define RSTV0910_STRSTATUS3 0xf16c ++#define FSTV0910_STRSTATUS_SEL6 0xf16c00f0 ++#define FSTV0910_STRSTATUS_SEL5 0xf16c000f ++ ++/*FSKTFC2*/ ++#define RSTV0910_FSKTFC2 0xf170 ++#define FSTV0910_FSKT_KMOD 0xf17000fc ++#define FSTV0910_FSKT_CAR2 0xf1700003 ++ ++/*FSKTFC1*/ ++#define RSTV0910_FSKTFC1 0xf171 ++#define FSTV0910_FSKT_CAR1 0xf17100ff ++ ++/*FSKTFC0*/ ++#define RSTV0910_FSKTFC0 0xf172 ++#define FSTV0910_FSKT_CAR0 0xf17200ff ++ ++/*FSKTDELTAF1*/ ++#define RSTV0910_FSKTDELTAF1 0xf173 ++#define FSTV0910_FSKT_DELTAF1 0xf173000f ++ ++/*FSKTDELTAF0*/ ++#define RSTV0910_FSKTDELTAF0 0xf174 ++#define FSTV0910_FSKT_DELTAF0 0xf17400ff ++ ++/*FSKTCTRL*/ ++#define RSTV0910_FSKTCTRL 0xf175 ++#define FSTV0910_FSKT_PINSEL 0xf1750080 ++#define FSTV0910_FSKT_EN_SGN 0xf1750040 ++#define FSTV0910_FSKT_MOD_SGN 0xf1750020 ++#define FSTV0910_FSKT_MOD_EN 0xf175001c ++#define FSTV0910_FSKT_DACMODE 0xf1750003 ++ ++/*FSKRFC2*/ ++#define RSTV0910_FSKRFC2 0xf176 ++#define FSTV0910_FSKR_DETSGN 0xf1760040 ++#define FSTV0910_FSKR_OUTSGN 0xf1760020 ++#define FSTV0910_FSKR_KAGC 0xf176001c ++#define FSTV0910_FSKR_CAR2 0xf1760003 ++ ++/*FSKRFC1*/ ++#define RSTV0910_FSKRFC1 0xf177 ++#define FSTV0910_FSKR_CAR1 0xf17700ff ++ ++/*FSKRFC0*/ ++#define RSTV0910_FSKRFC0 0xf178 ++#define FSTV0910_FSKR_CAR0 0xf17800ff ++ ++/*FSKRK1*/ ++#define RSTV0910_FSKRK1 0xf179 ++#define FSTV0910_FSKR_K1_EXP 0xf17900e0 ++#define FSTV0910_FSKR_K1_MANT 0xf179001f ++ ++/*FSKRK2*/ ++#define RSTV0910_FSKRK2 0xf17a ++#define FSTV0910_FSKR_K2_EXP 0xf17a00e0 ++#define FSTV0910_FSKR_K2_MANT 0xf17a001f ++ ++/*FSKRAGCR*/ ++#define RSTV0910_FSKRAGCR 0xf17b ++#define FSTV0910_FSKR_OUTCTL 0xf17b00c0 ++#define FSTV0910_FSKR_AGC_REF 0xf17b003f ++ ++/*FSKRAGC*/ ++#define RSTV0910_FSKRAGC 0xf17c ++#define FSTV0910_FSKR_AGC_ACCU 0xf17c00ff ++ ++/*FSKRALPHA*/ ++#define RSTV0910_FSKRALPHA 0xf17d ++#define FSTV0910_FSKR_ALPHA_EXP 0xf17d001c ++#define FSTV0910_FSKR_ALPHA_M 0xf17d0003 ++ ++/*FSKRPLTH1*/ ++#define RSTV0910_FSKRPLTH1 0xf17e ++#define FSTV0910_FSKR_BETA 0xf17e00f0 ++#define FSTV0910_FSKR_PLL_TRESH1 0xf17e000f ++ ++/*FSKRPLTH0*/ ++#define RSTV0910_FSKRPLTH0 0xf17f ++#define FSTV0910_FSKR_PLL_TRESH0 0xf17f00ff ++ ++/*FSKRDF1*/ ++#define RSTV0910_FSKRDF1 0xf180 ++#define FSTV0910_FSKR_OUT 0xf1800080 ++#define FSTV0910_FSKR_STATE 0xf1800060 ++#define FSTV0910_FSKR_DELTAF1 0xf180001f ++ ++/*FSKRDF0*/ ++#define RSTV0910_FSKRDF0 0xf181 ++#define FSTV0910_FSKR_DELTAF0 0xf18100ff ++ ++/*FSKRSTEPP*/ ++#define RSTV0910_FSKRSTEPP 0xf182 ++#define FSTV0910_FSKR_STEP_PLUS 0xf18200ff ++ ++/*FSKRSTEPM*/ ++#define RSTV0910_FSKRSTEPM 0xf183 ++#define FSTV0910_FSKR_STEP_MINUS 0xf18300ff ++ ++/*FSKRDET1*/ ++#define RSTV0910_FSKRDET1 0xf184 ++#define FSTV0910_FSKR_DETECT 0xf1840080 ++#define FSTV0910_FSKR_CARDET_ACCU1 0xf184000f ++ ++/*FSKRDET0*/ ++#define RSTV0910_FSKRDET0 0xf185 ++#define FSTV0910_FSKR_CARDET_ACCU0 0xf18500ff ++ ++/*FSKRDTH1*/ ++#define RSTV0910_FSKRDTH1 0xf186 ++#define FSTV0910_FSKR_CARLOSS_THRESH1 0xf18600f0 ++#define FSTV0910_FSKR_CARDET_THRESH1 0xf186000f ++ ++/*FSKRDTH0*/ ++#define RSTV0910_FSKRDTH0 0xf187 ++#define FSTV0910_FSKR_CARDET_THRESH0 0xf18700ff ++ ++/*FSKRLOSS*/ ++#define RSTV0910_FSKRLOSS 0xf188 ++#define FSTV0910_FSKR_CARLOSS_THRESH0 0xf18800ff ++ ++/*NCOARSE*/ ++#define RSTV0910_NCOARSE 0xf1b3 ++#define FSTV0910_CP 0xf1b300f8 ++#define FSTV0910_IDF 0xf1b30007 ++ ++/*NCOARSE1*/ ++#define RSTV0910_NCOARSE1 0xf1b4 ++#define FSTV0910_N_DIV 0xf1b400ff ++ ++/*NCOARSE2*/ ++#define RSTV0910_NCOARSE2 0xf1b5 ++#define FSTV0910_ODF 0xf1b5003f ++ ++/*SYNTCTRL*/ ++#define RSTV0910_SYNTCTRL 0xf1b6 ++#define FSTV0910_STANDBY 0xf1b60080 ++#define FSTV0910_BYPASSPLLCORE 0xf1b60040 ++#define FSTV0910_STOP_PLL 0xf1b60008 ++#define FSTV0910_OSCI_E 0xf1b60002 ++ ++/*FILTCTRL*/ ++#define RSTV0910_FILTCTRL 0xf1b7 ++#define FSTV0910_INV_CLKFSK 0xf1b70002 ++#define FSTV0910_BYPASS_APPLI 0xf1b70001 ++ ++/*PLLSTAT*/ ++#define RSTV0910_PLLSTAT 0xf1b8 ++#define FSTV0910_PLL_BIST_END 0xf1b80004 ++#define FSTV0910_PLLLOCK 0xf1b80001 ++ ++/*STOPCLK1*/ ++#define RSTV0910_STOPCLK1 0xf1c2 ++#define FSTV0910_INV_CLKADCI2 0xf1c20004 ++#define FSTV0910_INV_CLKADCI1 0xf1c20001 ++ ++/*STOPCLK2*/ ++#define RSTV0910_STOPCLK2 0xf1c3 ++#define FSTV0910_STOP_DVBS2FEC2 0xf1c30020 ++#define FSTV0910_STOP_DVBS2FEC 0xf1c30010 ++#define FSTV0910_STOP_DVBS1FEC2 0xf1c30008 ++#define FSTV0910_STOP_DVBS1FEC 0xf1c30004 ++#define FSTV0910_STOP_DEMOD2 0xf1c30002 ++#define FSTV0910_STOP_DEMOD 0xf1c30001 ++ ++/*PREGCTL*/ ++#define RSTV0910_PREGCTL 0xf1c8 ++#define FSTV0910_REG3V3TO2V5_POFF 0xf1c80080 ++ ++/*TSTTNR0*/ ++#define RSTV0910_TSTTNR0 0xf1df ++#define FSTV0910_FSK_PON 0xf1df0004 ++#define FSTV0910_FSK_OPENLOOP 0xf1df0002 ++ ++/*TSTTNR1*/ ++#define RSTV0910_TSTTNR1 0xf1e0 ++#define FSTV0910_BYPASS_ADC1 0xf1e00080 ++#define FSTV0910_INVADC1_CKOUT 0xf1e00040 ++#define FSTV0910_SELIQSRC1 0xf1e00030 ++#define FSTV0910_DEMOD2_SELADC 0xf1e00008 ++#define FSTV0910_DEMOD1_SELADC 0xf1e00004 ++#define FSTV0910_ADC1_PON 0xf1e00002 ++ ++/*TSTTNR2*/ ++#define RSTV0910_TSTTNR2 0xf1e1 ++#define FSTV0910_I2C_DISEQC_BYPASS 0xf1e10080 ++#define FSTV0910_I2C_DISEQC_ENCH 0xf1e10040 ++#define FSTV0910_I2C_DISEQC_PON 0xf1e10020 ++#define FSTV0910_DISEQC_CLKDIV 0xf1e1000f ++ ++/*TSTTNR3*/ ++#define RSTV0910_TSTTNR3 0xf1e2 ++#define FSTV0910_BYPASS_ADC2 0xf1e20080 ++#define FSTV0910_INVADC2_CKOUT 0xf1e20040 ++#define FSTV0910_SELIQSRC2 0xf1e20030 ++#define FSTV0910_ADC2_PON 0xf1e20002 ++ ++/*P2_IQCONST*/ ++#define RSTV0910_P2_IQCONST 0xf200 ++#define FSTV0910_P2_CONSTEL_SELECT 0xf2000060 ++#define FSTV0910_P2_IQSYMB_SEL 0xf200001f ++ ++/*P2_NOSCFG*/ ++#define RSTV0910_P2_NOSCFG 0xf201 ++#define FSTV0910_P2_DIS_ACMRATIO 0xf2010080 ++#define FSTV0910_P2_NOSIN_EGALSEL 0xf2010040 ++#define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2010020 ++#define FSTV0910_P2_NOSPLH_BETA 0xf2010018 ++#define FSTV0910_P2_NOSDATA_BETA 0xf2010007 ++ ++/*P2_ISYMB*/ ++#define RSTV0910_P2_ISYMB 0xf202 ++#define FSTV0910_P2_I_SYMBOL 0xf20201ff ++ ++/*P2_QSYMB*/ ++#define RSTV0910_P2_QSYMB 0xf203 ++#define FSTV0910_P2_Q_SYMBOL 0xf20301ff ++ ++/*P2_AGC1CFG*/ ++#define RSTV0910_P2_AGC1CFG 0xf204 ++#define FSTV0910_P2_DC_FROZEN 0xf2040080 ++#define FSTV0910_P2_DC_CORRECT 0xf2040040 ++#define FSTV0910_P2_AMM_FROZEN 0xf2040020 ++#define FSTV0910_P2_AMM_CORRECT 0xf2040010 ++#define FSTV0910_P2_QUAD_FROZEN 0xf2040008 ++#define FSTV0910_P2_QUAD_CORRECT 0xf2040004 ++#define FSTV0910_P2_DCCOMP_SLOW 0xf2040002 ++#define FSTV0910_P2_IQMISM_SLOW 0xf2040001 ++ ++/*P2_AGC1CN*/ ++#define RSTV0910_P2_AGC1CN 0xf206 ++#define FSTV0910_P2_AGC1_LOCKED 0xf2060080 ++#define FSTV0910_P2_AGC1_OVERFLOW 0xf2060040 ++#define FSTV0910_P2_AGC1_NOSLOWLK 0xf2060020 ++#define FSTV0910_P2_AGC1_MINPOWER 0xf2060010 ++#define FSTV0910_P2_AGCOUT_FAST 0xf2060008 ++#define FSTV0910_P2_AGCIQ_BETA 0xf2060007 ++ ++/*P2_AGC1REF*/ ++#define RSTV0910_P2_AGC1REF 0xf207 ++#define FSTV0910_P2_AGCIQ_REF 0xf20700ff ++ ++/*P2_IDCCOMP*/ ++#define RSTV0910_P2_IDCCOMP 0xf208 ++#define FSTV0910_P2_IAVERAGE_ADJ 0xf20801ff ++ ++/*P2_QDCCOMP*/ ++#define RSTV0910_P2_QDCCOMP 0xf209 ++#define FSTV0910_P2_QAVERAGE_ADJ 0xf20901ff ++ ++/*P2_POWERI*/ ++#define RSTV0910_P2_POWERI 0xf20a ++#define FSTV0910_P2_POWER_I 0xf20a00ff ++ ++/*P2_POWERQ*/ ++#define RSTV0910_P2_POWERQ 0xf20b ++#define FSTV0910_P2_POWER_Q 0xf20b00ff ++ ++/*P2_AGC1AMM*/ ++#define RSTV0910_P2_AGC1AMM 0xf20c ++#define FSTV0910_P2_AMM_VALUE 0xf20c00ff ++ ++/*P2_AGC1QUAD*/ ++#define RSTV0910_P2_AGC1QUAD 0xf20d ++#define FSTV0910_P2_QUAD_VALUE 0xf20d01ff ++ ++/*P2_AGCIQIN1*/ ++#define RSTV0910_P2_AGCIQIN1 0xf20e ++#define FSTV0910_P2_AGCIQ_VALUE1 0xf20e00ff ++ ++/*P2_AGCIQIN0*/ ++#define RSTV0910_P2_AGCIQIN0 0xf20f ++#define FSTV0910_P2_AGCIQ_VALUE0 0xf20f00ff ++ ++/*P2_DEMOD*/ ++#define RSTV0910_P2_DEMOD 0xf210 ++#define FSTV0910_P2_MANUALS2_ROLLOFF 0xf2100080 ++#define FSTV0910_P2_SPECINV_CONTROL 0xf2100030 ++#define FSTV0910_P2_MANUALSX_ROLLOFF 0xf2100004 ++#define FSTV0910_P2_ROLLOFF_CONTROL 0xf2100003 ++ ++/*P2_DMDMODCOD*/ ++#define RSTV0910_P2_DMDMODCOD 0xf211 ++#define FSTV0910_P2_MANUAL_MODCOD 0xf2110080 ++#define FSTV0910_P2_DEMOD_MODCOD 0xf211007c ++#define FSTV0910_P2_DEMOD_TYPE 0xf2110003 ++ ++/*P2_DSTATUS*/ ++#define RSTV0910_P2_DSTATUS 0xf212 ++#define FSTV0910_P2_CAR_LOCK 0xf2120080 ++#define FSTV0910_P2_TMGLOCK_QUALITY 0xf2120060 ++#define FSTV0910_P2_SDVBS1_ENABLE 0xf2120010 ++#define FSTV0910_P2_LOCK_DEFINITIF 0xf2120008 ++#define FSTV0910_P2_TIMING_IS_LOCKED 0xf2120004 ++#define FSTV0910_P2_DEMOD_SYSCFG 0xf2120002 ++#define FSTV0910_P2_OVADC_DETECT 0xf2120001 ++ ++/*P2_DSTATUS2*/ ++#define RSTV0910_P2_DSTATUS2 0xf213 ++#define FSTV0910_P2_DEMOD_DELOCK 0xf2130080 ++#define FSTV0910_P2_DEMOD_TIMEOUT 0xf2130040 ++#define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2130020 ++#define FSTV0910_P2_POLYPH_SATEVENT 0xf2130010 ++#define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2130008 ++#define FSTV0910_P2_AGC2_OVERFLOW 0xf2130004 ++#define FSTV0910_P2_CFR_OVERFLOW 0xf2130002 ++#define FSTV0910_P2_GAMMA_OVERUNDER 0xf2130001 ++ ++/*P2_DMDCFGMD*/ ++#define RSTV0910_P2_DMDCFGMD 0xf214 ++#define FSTV0910_P2_DVBS2_ENABLE 0xf2140080 ++#define FSTV0910_P2_DVBS1_ENABLE 0xf2140040 ++#define FSTV0910_P2_SCAN_ENABLE 0xf2140010 ++#define FSTV0910_P2_CFR_AUTOSCAN 0xf2140008 ++#define FSTV0910_P2_NOFORCE_RELOCK 0xf2140004 ++#define FSTV0910_P2_TUN_RNG 0xf2140003 ++ ++/*P2_DMDCFG2*/ ++#define RSTV0910_P2_DMDCFG2 0xf215 ++#define FSTV0910_P2_AGC1_WAITLOCK 0xf2150080 ++#define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2150040 ++#define FSTV0910_P2_BLINDPEA_MODE 0xf2150020 ++#define FSTV0910_P2_INFINITE_RELOCK 0xf2150010 ++#define FSTV0910_P2_BWOFFSET_COLDWARM 0xf2150008 ++#define FSTV0910_P2_TMGLOCK_NSCANSTOP 0xf2150004 ++#define FSTV0910_P2_COARSE_LK3MODE 0xf2150002 ++#define FSTV0910_P2_COARSE_LK2MODE 0xf2150001 ++ ++/*P2_DMDISTATE*/ ++#define RSTV0910_P2_DMDISTATE 0xf216 ++#define FSTV0910_P2_I2C_NORESETDMODE 0xf2160080 ++#define FSTV0910_P2_FORCE_ETAPED 0xf2160040 ++#define FSTV0910_P2_SDMDRST_DIRCLK 0xf2160020 ++#define FSTV0910_P2_I2C_DEMOD_MODE 0xf216001f ++ ++/*P2_DMDT0M*/ ++#define RSTV0910_P2_DMDT0M 0xf217 ++#define FSTV0910_P2_DMDT0_MIN 0xf21700ff ++ ++/*P2_DMDSTATE*/ ++#define RSTV0910_P2_DMDSTATE 0xf21b ++#define FSTV0910_P2_DEMOD_LOCKED 0xf21b0080 ++#define FSTV0910_P2_HEADER_MODE 0xf21b0060 ++#define FSTV0910_P2_DEMOD_MODE 0xf21b001f ++ ++/*P2_DMDFLYW*/ ++#define RSTV0910_P2_DMDFLYW 0xf21c ++#define FSTV0910_P2_I2C_IRQVAL 0xf21c00f0 ++#define FSTV0910_P2_FLYWHEEL_CPT 0xf21c000f ++ ++/*P2_DSTATUS3*/ ++#define RSTV0910_P2_DSTATUS3 0xf21d ++#define FSTV0910_P2_CFR_ZIGZAG 0xf21d0080 ++#define FSTV0910_P2_DEMOD_CFGMODE 0xf21d0060 ++#define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d0010 ++#define FSTV0910_P2_RELOCK_MODE 0xf21d0008 ++#define FSTV0910_P2_DEMOD_FAIL 0xf21d0004 ++#define FSTV0910_P2_ETAPE1A_DVBXMEM 0xf21d0003 ++ ++/*P2_DMDCFG3*/ ++#define RSTV0910_P2_DMDCFG3 0xf21e ++#define FSTV0910_P2_DVBS1_TMGWAIT 0xf21e0080 ++#define FSTV0910_P2_NO_BWCENTERING 0xf21e0040 ++#define FSTV0910_P2_INV_SEQSRCH 0xf21e0020 ++#define FSTV0910_P2_DIS_SFRUPLOW_TRK 0xf21e0010 ++#define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e0008 ++#define FSTV0910_P2_LOCKTIME_MODE 0xf21e0007 ++ ++/*P2_DMDCFG4*/ ++#define RSTV0910_P2_DMDCFG4 0xf21f ++#define FSTV0910_P2_DIS_VITLOCK 0xf21f0080 ++#define FSTV0910_P2_S1S2TOUT_FAST 0xf21f0040 ++#define FSTV0910_P2_DEMOD_FASTLOCK 0xf21f0020 ++#define FSTV0910_P2_S1HIER_ENABLE 0xf21f0010 ++#define FSTV0910_P2_TUNER_NRELAUNCH 0xf21f0008 ++#define FSTV0910_P2_DIS_CLKENABLE 0xf21f0004 ++#define FSTV0910_P2_DIS_HDRDIVLOCK 0xf21f0002 ++#define FSTV0910_P2_NO_TNRWBINIT 0xf21f0001 ++ ++/*P2_CORRELMANT*/ ++#define RSTV0910_P2_CORRELMANT 0xf220 ++#define FSTV0910_P2_CORREL_MANT 0xf22000ff ++ ++/*P2_CORRELABS*/ ++#define RSTV0910_P2_CORRELABS 0xf221 ++#define FSTV0910_P2_CORREL_ABS 0xf22100ff ++ ++/*P2_CORRELEXP*/ ++#define RSTV0910_P2_CORRELEXP 0xf222 ++#define FSTV0910_P2_CORREL_ABSEXP 0xf22200f0 ++#define FSTV0910_P2_CORREL_EXP 0xf222000f ++ ++/*P2_PLHMODCOD*/ ++#define RSTV0910_P2_PLHMODCOD 0xf224 ++#define FSTV0910_P2_SPECINV_DEMOD 0xf2240080 ++#define FSTV0910_P2_PLH_MODCOD 0xf224007c ++#define FSTV0910_P2_PLH_TYPE 0xf2240003 ++ ++/*P2_DMDREG*/ ++#define RSTV0910_P2_DMDREG 0xf225 ++#define FSTV0910_P2_EXTPSK_MODE 0xf2250080 ++#define FSTV0910_P2_HIER_SHORTFRAME 0xf2250002 ++#define FSTV0910_P2_DECIM_PLFRAMES 0xf2250001 ++ ++/*P2_AGC2O*/ ++#define RSTV0910_P2_AGC2O 0xf22c ++#define FSTV0910_P2_CSTENV_MODE 0xf22c00c0 ++#define FSTV0910_P2_AGC2_LKSQRT 0xf22c0020 ++#define FSTV0910_P2_AGC2_LKMODE 0xf22c0010 ++#define FSTV0910_P2_AGC2_LKEQUA 0xf22c0008 ++#define FSTV0910_P2_AGC2_COEF 0xf22c0007 ++ ++/*P2_AGC2REF*/ ++#define RSTV0910_P2_AGC2REF 0xf22d ++#define FSTV0910_P2_AGC2_REF 0xf22d00ff ++ ++/*P2_AGC1ADJ*/ ++#define RSTV0910_P2_AGC1ADJ 0xf22e ++#define FSTV0910_P2_AGC1ADJ_MANUAL 0xf22e0080 ++#define FSTV0910_P2_AGC1_ADJUSTED 0xf22e007f ++ ++/*P2_AGC2I1*/ ++#define RSTV0910_P2_AGC2I1 0xf236 ++#define FSTV0910_P2_AGC2_INTEGRATOR1 0xf23600ff ++ ++/*P2_AGC2I0*/ ++#define RSTV0910_P2_AGC2I0 0xf237 ++#define FSTV0910_P2_AGC2_INTEGRATOR0 0xf23700ff ++ ++/*P2_CARCFG*/ ++#define RSTV0910_P2_CARCFG 0xf238 ++#define FSTV0910_P2_CFRUPLOW_AUTO 0xf2380080 ++#define FSTV0910_P2_CFRUPLOW_TEST 0xf2380040 ++#define FSTV0910_P2_WIDE_FREQDET 0xf2380020 ++#define FSTV0910_P2_CARHDR_NODIV8 0xf2380010 ++#define FSTV0910_P2_I2C_ROTA 0xf2380008 ++#define FSTV0910_P2_ROTAON 0xf2380004 ++#define FSTV0910_P2_PH_DET_ALGO 0xf2380003 ++ ++/*P2_ACLC*/ ++#define RSTV0910_P2_ACLC 0xf239 ++#define FSTV0910_P2_CARS1_ANOSAUTO 0xf2390040 ++#define FSTV0910_P2_CAR_ALPHA_MANT 0xf2390030 ++#define FSTV0910_P2_CAR_ALPHA_EXP 0xf239000f ++ ++/*P2_BCLC*/ ++#define RSTV0910_P2_BCLC 0xf23a ++#define FSTV0910_P2_CARS1_BNOSAUTO 0xf23a0040 ++#define FSTV0910_P2_CAR_BETA_MANT 0xf23a0030 ++#define FSTV0910_P2_CAR_BETA_EXP 0xf23a000f ++ ++/*P2_CARFREQ*/ ++#define RSTV0910_P2_CARFREQ 0xf23d ++#define FSTV0910_P2_KC_COARSE_EXP 0xf23d00f0 ++#define FSTV0910_P2_BETA_FREQ 0xf23d000f ++ ++/*P2_CARHDR*/ ++#define RSTV0910_P2_CARHDR 0xf23e ++#define FSTV0910_P2_K_FREQ_HDR 0xf23e00ff ++ ++/*P2_LDT*/ ++#define RSTV0910_P2_LDT 0xf23f ++#define FSTV0910_P2_CARLOCK_THRES 0xf23f01ff ++ ++/*P2_LDT2*/ ++#define RSTV0910_P2_LDT2 0xf240 ++#define FSTV0910_P2_CARLOCK_THRES2 0xf24001ff ++ ++/*P2_CFRICFG*/ ++#define RSTV0910_P2_CFRICFG 0xf241 ++#define FSTV0910_P2_CFRINIT_UNVALRNG 0xf2410080 ++#define FSTV0910_P2_CFRINIT_LUNVALCPT 0xf2410040 ++#define FSTV0910_P2_CFRINIT_ABORTDBL 0xf2410020 ++#define FSTV0910_P2_CFRINIT_ABORTPRED 0xf2410010 ++#define FSTV0910_P2_CFRINIT_UNVALSKIP 0xf2410008 ++#define FSTV0910_P2_CFRINIT_CSTINC 0xf2410004 ++#define FSTV0910_P2_CFRIROLL_GARDER 0xf2410002 ++#define FSTV0910_P2_NEG_CFRSTEP 0xf2410001 ++ ++/*P2_CFRUP1*/ ++#define RSTV0910_P2_CFRUP1 0xf242 ++#define FSTV0910_P2_CFR_UP1 0xf24201ff ++ ++/*P2_CFRUP0*/ ++#define RSTV0910_P2_CFRUP0 0xf243 ++#define FSTV0910_P2_CFR_UP0 0xf24300ff ++ ++/*P2_CFRIBASE1*/ ++#define RSTV0910_P2_CFRIBASE1 0xf244 ++#define FSTV0910_P2_CFRINIT_BASE1 0xf24400ff ++ ++/*P2_CFRIBASE0*/ ++#define RSTV0910_P2_CFRIBASE0 0xf245 ++#define FSTV0910_P2_CFRINIT_BASE0 0xf24500ff ++ ++/*P2_CFRLOW1*/ ++#define RSTV0910_P2_CFRLOW1 0xf246 ++#define FSTV0910_P2_CFR_LOW1 0xf24601ff ++ ++/*P2_CFRLOW0*/ ++#define RSTV0910_P2_CFRLOW0 0xf247 ++#define FSTV0910_P2_CFR_LOW0 0xf24700ff ++ ++/*P2_CFRINIT1*/ ++#define RSTV0910_P2_CFRINIT1 0xf248 ++#define FSTV0910_P2_CFR_INIT1 0xf24801ff ++ ++/*P2_CFRINIT0*/ ++#define RSTV0910_P2_CFRINIT0 0xf249 ++#define FSTV0910_P2_CFR_INIT0 0xf24900ff ++ ++/*P2_CFRINC1*/ ++#define RSTV0910_P2_CFRINC1 0xf24a ++#define FSTV0910_P2_MANUAL_CFRINC 0xf24a0080 ++#define FSTV0910_P2_CFR_INC1 0xf24a003f ++ ++/*P2_CFRINC0*/ ++#define RSTV0910_P2_CFRINC0 0xf24b ++#define FSTV0910_P2_CFR_INC0 0xf24b00ff ++ ++/*P2_CFR2*/ ++#define RSTV0910_P2_CFR2 0xf24c ++#define FSTV0910_P2_CAR_FREQ2 0xf24c01ff ++ ++/*P2_CFR1*/ ++#define RSTV0910_P2_CFR1 0xf24d ++#define FSTV0910_P2_CAR_FREQ1 0xf24d00ff ++ ++/*P2_CFR0*/ ++#define RSTV0910_P2_CFR0 0xf24e ++#define FSTV0910_P2_CAR_FREQ0 0xf24e00ff ++ ++/*P2_LDI*/ ++#define RSTV0910_P2_LDI 0xf24f ++#define FSTV0910_P2_LOCK_DET_INTEGR 0xf24f01ff ++ ++/*P2_TMGCFG*/ ++#define RSTV0910_P2_TMGCFG 0xf250 ++#define FSTV0910_P2_TMGLOCK_BETA 0xf25000c0 ++#define FSTV0910_P2_DO_TIMING_CORR 0xf2500010 ++#define FSTV0910_P2_MANUAL_SCAN 0xf250000c ++#define FSTV0910_P2_TMG_MINFREQ 0xf2500003 ++ ++/*P2_RTC*/ ++#define RSTV0910_P2_RTC 0xf251 ++#define FSTV0910_P2_TMGALPHA_EXP 0xf25100f0 ++#define FSTV0910_P2_TMGBETA_EXP 0xf251000f ++ ++/*P2_RTCS2*/ ++#define RSTV0910_P2_RTCS2 0xf252 ++#define FSTV0910_P2_TMGALPHAS2_EXP 0xf25200f0 ++#define FSTV0910_P2_TMGBETAS2_EXP 0xf252000f ++ ++/*P2_TMGTHRISE*/ ++#define RSTV0910_P2_TMGTHRISE 0xf253 ++#define FSTV0910_P2_TMGLOCK_THRISE 0xf25300ff ++ ++/*P2_TMGTHFALL*/ ++#define RSTV0910_P2_TMGTHFALL 0xf254 ++#define FSTV0910_P2_TMGLOCK_THFALL 0xf25400ff ++ ++/*P2_SFRUPRATIO*/ ++#define RSTV0910_P2_SFRUPRATIO 0xf255 ++#define FSTV0910_P2_SFR_UPRATIO 0xf25500ff ++ ++/*P2_SFRLOWRATIO*/ ++#define RSTV0910_P2_SFRLOWRATIO 0xf256 ++#define FSTV0910_P2_SFR_LOWRATIO 0xf25600ff ++ ++/*P2_KTTMG*/ ++#define RSTV0910_P2_KTTMG 0xf257 ++#define FSTV0910_P2_KT_TMG_EXP 0xf25700f0 ++ ++/*P2_KREFTMG*/ ++#define RSTV0910_P2_KREFTMG 0xf258 ++#define FSTV0910_P2_KREF_TMG 0xf25800ff ++ ++/*P2_SFRSTEP*/ ++#define RSTV0910_P2_SFRSTEP 0xf259 ++#define FSTV0910_P2_SFR_SCANSTEP 0xf25900f0 ++#define FSTV0910_P2_SFR_CENTERSTEP 0xf259000f ++ ++/*P2_TMGCFG2*/ ++#define RSTV0910_P2_TMGCFG2 0xf25a ++#define FSTV0910_P2_KREFTMG2_DECMODE 0xf25a00c0 ++#define FSTV0910_P2_DIS_AUTOSAMP 0xf25a0008 ++#define FSTV0910_P2_SCANINIT_QUART 0xf25a0004 ++#define FSTV0910_P2_NOTMG_DVBS1DERAT 0xf25a0002 ++#define FSTV0910_P2_SFRRATIO_FINE 0xf25a0001 ++ ++/*P2_KREFTMG2*/ ++#define RSTV0910_P2_KREFTMG2 0xf25b ++#define FSTV0910_P2_KREF_TMG2 0xf25b00ff ++ ++/*P2_TMGCFG3*/ ++#define RSTV0910_P2_TMGCFG3 0xf25d ++#define FSTV0910_P2_CFRINC_MODE 0xf25d0070 ++#define FSTV0910_P2_CONT_TMGCENTER 0xf25d0008 ++#define FSTV0910_P2_AUTO_GUP 0xf25d0004 ++#define FSTV0910_P2_AUTO_GLOW 0xf25d0002 ++#define FSTV0910_P2_SFRVAL_MINMODE 0xf25d0001 ++ ++/*P2_SFRINIT1*/ ++#define RSTV0910_P2_SFRINIT1 0xf25e ++#define FSTV0910_P2_SFR_INIT1 0xf25e00ff ++ ++/*P2_SFRINIT0*/ ++#define RSTV0910_P2_SFRINIT0 0xf25f ++#define FSTV0910_P2_SFR_INIT0 0xf25f00ff ++ ++/*P2_SFRUP1*/ ++#define RSTV0910_P2_SFRUP1 0xf260 ++#define FSTV0910_P2_SYMB_FREQ_UP1 0xf26000ff ++ ++/*P2_SFRUP0*/ ++#define RSTV0910_P2_SFRUP0 0xf261 ++#define FSTV0910_P2_SYMB_FREQ_UP0 0xf26100ff ++ ++/*P2_SFRLOW1*/ ++#define RSTV0910_P2_SFRLOW1 0xf262 ++#define FSTV0910_P2_SYMB_FREQ_LOW1 0xf26200ff ++ ++/*P2_SFRLOW0*/ ++#define RSTV0910_P2_SFRLOW0 0xf263 ++#define FSTV0910_P2_SYMB_FREQ_LOW0 0xf26300ff ++ ++/*P2_SFR3*/ ++#define RSTV0910_P2_SFR3 0xf264 ++#define FSTV0910_P2_SYMB_FREQ3 0xf26400ff ++ ++/*P2_SFR2*/ ++#define RSTV0910_P2_SFR2 0xf265 ++#define FSTV0910_P2_SYMB_FREQ2 0xf26500ff ++ ++/*P2_SFR1*/ ++#define RSTV0910_P2_SFR1 0xf266 ++#define FSTV0910_P2_SYMB_FREQ1 0xf26600ff ++ ++/*P2_SFR0*/ ++#define RSTV0910_P2_SFR0 0xf267 ++#define FSTV0910_P2_SYMB_FREQ0 0xf26700ff ++ ++/*P2_TMGREG2*/ ++#define RSTV0910_P2_TMGREG2 0xf268 ++#define FSTV0910_P2_TMGREG2 0xf26800ff ++ ++/*P2_TMGREG1*/ ++#define RSTV0910_P2_TMGREG1 0xf269 ++#define FSTV0910_P2_TMGREG1 0xf26900ff ++ ++/*P2_TMGREG0*/ ++#define RSTV0910_P2_TMGREG0 0xf26a ++#define FSTV0910_P2_TMGREG0 0xf26a00ff ++ ++/*P2_TMGLOCK1*/ ++#define RSTV0910_P2_TMGLOCK1 0xf26b ++#define FSTV0910_P2_TMGLOCK_LEVEL1 0xf26b01ff ++ ++/*P2_TMGLOCK0*/ ++#define RSTV0910_P2_TMGLOCK0 0xf26c ++#define FSTV0910_P2_TMGLOCK_LEVEL0 0xf26c00ff ++ ++/*P2_TMGOBS*/ ++#define RSTV0910_P2_TMGOBS 0xf26d ++#define FSTV0910_P2_ROLLOFF_STATUS 0xf26d00c0 ++#define FSTV0910_P2_SCAN_SIGN 0xf26d0030 ++#define FSTV0910_P2_TMG_SCANNING 0xf26d0008 ++#define FSTV0910_P2_CHCENTERING_MODE 0xf26d0004 ++#define FSTV0910_P2_TMG_SCANFAIL 0xf26d0002 ++ ++/*P2_EQUALCFG*/ ++#define RSTV0910_P2_EQUALCFG 0xf26f ++#define FSTV0910_P2_NOTMG_NEGALWAIT 0xf26f0080 ++#define FSTV0910_P2_EQUAL_ON 0xf26f0040 ++#define FSTV0910_P2_SEL_EQUALCOR 0xf26f0038 ++#define FSTV0910_P2_MU_EQUALDFE 0xf26f0007 ++ ++/*P2_EQUAI1*/ ++#define RSTV0910_P2_EQUAI1 0xf270 ++#define FSTV0910_P2_EQUA_ACCI1 0xf27001ff ++ ++/*P2_EQUAQ1*/ ++#define RSTV0910_P2_EQUAQ1 0xf271 ++#define FSTV0910_P2_EQUA_ACCQ1 0xf27101ff ++ ++/*P2_EQUAI2*/ ++#define RSTV0910_P2_EQUAI2 0xf272 ++#define FSTV0910_P2_EQUA_ACCI2 0xf27201ff ++ ++/*P2_EQUAQ2*/ ++#define RSTV0910_P2_EQUAQ2 0xf273 ++#define FSTV0910_P2_EQUA_ACCQ2 0xf27301ff ++ ++/*P2_EQUAI3*/ ++#define RSTV0910_P2_EQUAI3 0xf274 ++#define FSTV0910_P2_EQUA_ACCI3 0xf27401ff ++ ++/*P2_EQUAQ3*/ ++#define RSTV0910_P2_EQUAQ3 0xf275 ++#define FSTV0910_P2_EQUA_ACCQ3 0xf27501ff ++ ++/*P2_EQUAI4*/ ++#define RSTV0910_P2_EQUAI4 0xf276 ++#define FSTV0910_P2_EQUA_ACCI4 0xf27601ff ++ ++/*P2_EQUAQ4*/ ++#define RSTV0910_P2_EQUAQ4 0xf277 ++#define FSTV0910_P2_EQUA_ACCQ4 0xf27701ff ++ ++/*P2_EQUAI5*/ ++#define RSTV0910_P2_EQUAI5 0xf278 ++#define FSTV0910_P2_EQUA_ACCI5 0xf27801ff ++ ++/*P2_EQUAQ5*/ ++#define RSTV0910_P2_EQUAQ5 0xf279 ++#define FSTV0910_P2_EQUA_ACCQ5 0xf27901ff ++ ++/*P2_EQUAI6*/ ++#define RSTV0910_P2_EQUAI6 0xf27a ++#define FSTV0910_P2_EQUA_ACCI6 0xf27a01ff ++ ++/*P2_EQUAQ6*/ ++#define RSTV0910_P2_EQUAQ6 0xf27b ++#define FSTV0910_P2_EQUA_ACCQ6 0xf27b01ff ++ ++/*P2_EQUAI7*/ ++#define RSTV0910_P2_EQUAI7 0xf27c ++#define FSTV0910_P2_EQUA_ACCI7 0xf27c01ff ++ ++/*P2_EQUAQ7*/ ++#define RSTV0910_P2_EQUAQ7 0xf27d ++#define FSTV0910_P2_EQUA_ACCQ7 0xf27d01ff ++ ++/*P2_EQUAI8*/ ++#define RSTV0910_P2_EQUAI8 0xf27e ++#define FSTV0910_P2_EQUA_ACCI8 0xf27e01ff ++ ++/*P2_EQUAQ8*/ ++#define RSTV0910_P2_EQUAQ8 0xf27f ++#define FSTV0910_P2_EQUA_ACCQ8 0xf27f01ff ++ ++/*P2_NNOSDATAT1*/ ++#define RSTV0910_P2_NNOSDATAT1 0xf280 ++#define FSTV0910_P2_NOSDATAT_NORMED1 0xf28000ff ++ ++/*P2_NNOSDATAT0*/ ++#define RSTV0910_P2_NNOSDATAT0 0xf281 ++#define FSTV0910_P2_NOSDATAT_NORMED0 0xf28100ff ++ ++/*P2_NNOSDATA1*/ ++#define RSTV0910_P2_NNOSDATA1 0xf282 ++#define FSTV0910_P2_NOSDATA_NORMED1 0xf28200ff ++ ++/*P2_NNOSDATA0*/ ++#define RSTV0910_P2_NNOSDATA0 0xf283 ++#define FSTV0910_P2_NOSDATA_NORMED0 0xf28300ff ++ ++/*P2_NNOSPLHT1*/ ++#define RSTV0910_P2_NNOSPLHT1 0xf284 ++#define FSTV0910_P2_NOSPLHT_NORMED1 0xf28400ff ++ ++/*P2_NNOSPLHT0*/ ++#define RSTV0910_P2_NNOSPLHT0 0xf285 ++#define FSTV0910_P2_NOSPLHT_NORMED0 0xf28500ff ++ ++/*P2_NNOSPLH1*/ ++#define RSTV0910_P2_NNOSPLH1 0xf286 ++#define FSTV0910_P2_NOSPLH_NORMED1 0xf28600ff ++ ++/*P2_NNOSPLH0*/ ++#define RSTV0910_P2_NNOSPLH0 0xf287 ++#define FSTV0910_P2_NOSPLH_NORMED0 0xf28700ff ++ ++/*P2_NOSDATAT1*/ ++#define RSTV0910_P2_NOSDATAT1 0xf288 ++#define FSTV0910_P2_NOSDATAT_UNNORMED1 0xf28800ff ++ ++/*P2_NOSDATAT0*/ ++#define RSTV0910_P2_NOSDATAT0 0xf289 ++#define FSTV0910_P2_NOSDATAT_UNNORMED0 0xf28900ff ++ ++/*P2_NNOSFRAME1*/ ++#define RSTV0910_P2_NNOSFRAME1 0xf28a ++#define FSTV0910_P2_NOSFRAME_NORMED1 0xf28a00ff ++ ++/*P2_NNOSFRAME0*/ ++#define RSTV0910_P2_NNOSFRAME0 0xf28b ++#define FSTV0910_P2_NOSFRAME_NORMED0 0xf28b00ff ++ ++/*P2_NNOSRAD1*/ ++#define RSTV0910_P2_NNOSRAD1 0xf28c ++#define FSTV0910_P2_NOSRADIAL_NORMED1 0xf28c00ff ++ ++/*P2_NNOSRAD0*/ ++#define RSTV0910_P2_NNOSRAD0 0xf28d ++#define FSTV0910_P2_NOSRADIAL_NORMED0 0xf28d00ff ++ ++/*P2_NOSCFGF1*/ ++#define RSTV0910_P2_NOSCFGF1 0xf28e ++#define FSTV0910_P2_LOWNOISE_MESURE 0xf28e0080 ++#define FSTV0910_P2_NOS_DELFRAME 0xf28e0040 ++#define FSTV0910_P2_NOSDATA_MODE 0xf28e0030 ++#define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e000c ++#define FSTV0910_P2_FRAMESEL_TYPE 0xf28e0003 ++ ++/*P2_CAR2CFG*/ ++#define RSTV0910_P2_CAR2CFG 0xf290 ++#define FSTV0910_P2_DESCRAMB_OFF 0xf2900080 ++#define FSTV0910_P2_EN_PHNOSRAM 0xf2900020 ++#define FSTV0910_P2_STOP_CFR2UPDATE 0xf2900010 ++#define FSTV0910_P2_STOP_NCO2UPDATE 0xf2900008 ++#define FSTV0910_P2_ROTA2ON 0xf2900004 ++#define FSTV0910_P2_PH_DET_ALGO2 0xf2900003 ++ ++/*P2_CFR2CFR1*/ ++#define RSTV0910_P2_CFR2CFR1 0xf291 ++#define FSTV0910_P2_CFR2_S2CONTROL 0xf29100c0 ++#define FSTV0910_P2_EN_S2CAR2CENTER 0xf2910020 ++#define FSTV0910_P2_BCHERRCFR2_MODE 0xf2910018 ++#define FSTV0910_P2_CFR2TOCFR1_BETA 0xf2910007 ++ ++/*P2_CAR3CFG*/ ++#define RSTV0910_P2_CAR3CFG 0xf292 ++#define FSTV0910_P2_CARRIER23_MODE 0xf29200c0 ++#define FSTV0910_P2_CAR3INTERM_DVBS1 0xf2920020 ++#define FSTV0910_P2_ABAMPLIF_MODE 0xf2920018 ++#define FSTV0910_P2_CARRIER3_ALPHA3DL 0xf2920007 ++ ++/*P2_CFR22*/ ++#define RSTV0910_P2_CFR22 0xf293 ++#define FSTV0910_P2_CAR2_FREQ2 0xf29301ff ++ ++/*P2_CFR21*/ ++#define RSTV0910_P2_CFR21 0xf294 ++#define FSTV0910_P2_CAR2_FREQ1 0xf29400ff ++ ++/*P2_CFR20*/ ++#define RSTV0910_P2_CFR20 0xf295 ++#define FSTV0910_P2_CAR2_FREQ0 0xf29500ff ++ ++/*P2_ACLC2S2Q*/ ++#define RSTV0910_P2_ACLC2S2Q 0xf297 ++#define FSTV0910_P2_ENAB_SPSKSYMB 0xf2970080 ++#define FSTV0910_P2_CAR2S2_QANOSAUTO 0xf2970040 ++#define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2970030 ++#define FSTV0910_P2_CAR2S2_Q_ALPH_E 0xf297000f ++ ++/*P2_ACLC2S28*/ ++#define RSTV0910_P2_ACLC2S28 0xf298 ++#define FSTV0910_P2_OLDI3Q_MODE 0xf2980080 ++#define FSTV0910_P2_CAR2S2_8ANOSAUTO 0xf2980040 ++#define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2980030 ++#define FSTV0910_P2_CAR2S2_8_ALPH_E 0xf298000f ++ ++/*P2_ACLC2S216A*/ ++#define RSTV0910_P2_ACLC2S216A 0xf299 ++#define FSTV0910_P2_CAR2S2_16ANOSAUTO 0xf2990040 ++#define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2990030 ++#define FSTV0910_P2_CAR2S2_16A_ALPH_E 0xf299000f ++ ++/*P2_ACLC2S232A*/ ++#define RSTV0910_P2_ACLC2S232A 0xf29a ++#define FSTV0910_P2_CAR2S2_32ANOSUATO 0xf29a0040 ++#define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a0030 ++#define FSTV0910_P2_CAR2S2_32A_ALPH_E 0xf29a000f ++ ++/*P2_BCLC2S2Q*/ ++#define RSTV0910_P2_BCLC2S2Q 0xf29c ++#define FSTV0910_P2_DVBS2S2Q_NIP 0xf29c0080 ++#define FSTV0910_P2_CAR2S2_QBNOSAUTO 0xf29c0040 ++#define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c0030 ++#define FSTV0910_P2_CAR2S2_Q_BETA_E 0xf29c000f ++ ++/*P2_BCLC2S28*/ ++#define RSTV0910_P2_BCLC2S28 0xf29d ++#define FSTV0910_P2_DVBS2S28_NIP 0xf29d0080 ++#define FSTV0910_P2_CAR2S2_8BNOSAUTO 0xf29d0040 ++#define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d0030 ++#define FSTV0910_P2_CAR2S2_8_BETA_E 0xf29d000f ++ ++/*P2_PLROOT2*/ ++#define RSTV0910_P2_PLROOT2 0xf2ac ++#define FSTV0910_P2_PLHAUTO_DISPLH 0xf2ac0040 ++#define FSTV0910_P2_PLHAUTO_FASTMODE 0xf2ac0020 ++#define FSTV0910_P2_PLHAUTO_ENABLE 0xf2ac0010 ++#define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac000c ++#define FSTV0910_P2_PLSCRAMB_ROOT2 0xf2ac0003 ++ ++/*P2_PLROOT1*/ ++#define RSTV0910_P2_PLROOT1 0xf2ad ++#define FSTV0910_P2_PLSCRAMB_ROOT1 0xf2ad00ff ++ ++/*P2_PLROOT0*/ ++#define RSTV0910_P2_PLROOT0 0xf2ae ++#define FSTV0910_P2_PLSCRAMB_ROOT0 0xf2ae00ff ++ ++/*P2_MODCODLST7*/ ++#define RSTV0910_P2_MODCODLST7 0xf2b7 ++#define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b70080 ++#define FSTV0910_P2_MODCODLST_NOSTYPE 0xf2b70040 ++#define FSTV0910_P2_DIS_8PSK_9_10 0xf2b70030 ++#define FSTV0910_P2_DIS_8P_8_9 0xf2b7000f ++ ++/*P2_MODCODLST8*/ ++#define RSTV0910_P2_MODCODLST8 0xf2b8 ++#define FSTV0910_P2_DIS_8P_5_6 0xf2b800f0 ++#define FSTV0910_P2_DIS_8P_3_4 0xf2b8000f ++ ++/*P2_MODCODLST9*/ ++#define RSTV0910_P2_MODCODLST9 0xf2b9 ++#define FSTV0910_P2_DIS_8P_2_3 0xf2b900f0 ++#define FSTV0910_P2_DIS_8P_3_5 0xf2b9000f ++ ++/*P2_MODCODLSTA*/ ++#define RSTV0910_P2_MODCODLSTA 0xf2ba ++#define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba0080 ++#define FSTV0910_P2_NOSFILTER_MODE 0xf2ba0040 ++#define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba0030 ++#define FSTV0910_P2_DIS_QP_8_9 0xf2ba000f ++ ++/*P2_MODCODLSTB*/ ++#define RSTV0910_P2_MODCODLSTB 0xf2bb ++#define FSTV0910_P2_DIS_QP_5_6 0xf2bb00f0 ++#define FSTV0910_P2_DIS_QP_4_5 0xf2bb000f ++ ++/*P2_MODCODLSTC*/ ++#define RSTV0910_P2_MODCODLSTC 0xf2bc ++#define FSTV0910_P2_DIS_QP_3_4 0xf2bc00f0 ++#define FSTV0910_P2_DIS_QP_2_3 0xf2bc000f ++ ++/*P2_MODCODLSTD*/ ++#define RSTV0910_P2_MODCODLSTD 0xf2bd ++#define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd00f0 ++#define FSTV0910_P2_DIS_QPSK_1_2 0xf2bd000f ++ ++/*P2_GAUSSR0*/ ++#define RSTV0910_P2_GAUSSR0 0xf2c0 ++#define FSTV0910_P2_EN_CCIMODE 0xf2c00080 ++#define FSTV0910_P2_R0_GAUSSIEN 0xf2c0007f ++ ++/*P2_CCIR0*/ ++#define RSTV0910_P2_CCIR0 0xf2c1 ++#define FSTV0910_P2_CCIDETECT_PLHONLY 0xf2c10080 ++#define FSTV0910_P2_R0_CCI 0xf2c1007f ++ ++/*P2_CCIQUANT*/ ++#define RSTV0910_P2_CCIQUANT 0xf2c2 ++#define FSTV0910_P2_CCI_BETA 0xf2c200e0 ++#define FSTV0910_P2_CCI_QUANT 0xf2c2001f ++ ++/*P2_CCITHRES*/ ++#define RSTV0910_P2_CCITHRES 0xf2c3 ++#define FSTV0910_P2_CCI_THRESHOLD 0xf2c300ff ++ ++/*P2_CCIACC*/ ++#define RSTV0910_P2_CCIACC 0xf2c4 ++#define FSTV0910_P2_CCI_VALUE 0xf2c400ff ++ ++/*P2_DSTATUS4*/ ++#define RSTV0910_P2_DSTATUS4 0xf2c5 ++#define FSTV0910_P2_RAINFADE_DETECT 0xf2c50080 ++#define FSTV0910_P2_NOTHRES2_FAIL 0xf2c50040 ++#define FSTV0910_P2_NOTHRES1_FAIL 0xf2c50020 ++#define FSTV0910_P2_PILOT_FAILDETECT 0xf2c50010 ++#define FSTV0910_P2_HIER_DETECT 0xf2c50008 ++#define FSTV0910_P2_DMDPROG_ERROR 0xf2c50004 ++#define FSTV0910_P2_CSTENV_DETECT 0xf2c50002 ++#define FSTV0910_P2_DETECTION_TRIAX 0xf2c50001 ++ ++/*P2_DMDRESCFG*/ ++#define RSTV0910_P2_DMDRESCFG 0xf2c6 ++#define FSTV0910_P2_DMDRES_RESET 0xf2c60080 ++#define FSTV0910_P2_DMDRES_NOISESQR 0xf2c60010 ++#define FSTV0910_P2_DMDRES_STRALL 0xf2c60008 ++#define FSTV0910_P2_DMDRES_NEWONLY 0xf2c60004 ++#define FSTV0910_P2_DMDRES_NOSTORE 0xf2c60002 ++#define FSTV0910_P2_DMDRES_AGC2MEM 0xf2c60001 ++ ++/*P2_DMDRESADR*/ ++#define RSTV0910_P2_DMDRESADR 0xf2c7 ++#define FSTV0910_P2_SUSP_PREDCANAL 0xf2c70080 ++#define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c70040 ++#define FSTV0910_P2_DMDRES_MEMFULL 0xf2c70030 ++#define FSTV0910_P2_DMDRES_RESNBR 0xf2c7000f ++ ++/*P2_DMDRESDATA7*/ ++#define RSTV0910_P2_DMDRESDATA7 0xf2c8 ++#define FSTV0910_P2_DMDRES_DATA7 0xf2c800ff ++ ++/*P2_DMDRESDATA6*/ ++#define RSTV0910_P2_DMDRESDATA6 0xf2c9 ++#define FSTV0910_P2_DMDRES_DATA6 0xf2c900ff ++ ++/*P2_DMDRESDATA5*/ ++#define RSTV0910_P2_DMDRESDATA5 0xf2ca ++#define FSTV0910_P2_DMDRES_DATA5 0xf2ca00ff ++ ++/*P2_DMDRESDATA4*/ ++#define RSTV0910_P2_DMDRESDATA4 0xf2cb ++#define FSTV0910_P2_DMDRES_DATA4 0xf2cb00ff ++ ++/*P2_DMDRESDATA3*/ ++#define RSTV0910_P2_DMDRESDATA3 0xf2cc ++#define FSTV0910_P2_DMDRES_DATA3 0xf2cc00ff ++ ++/*P2_DMDRESDATA2*/ ++#define RSTV0910_P2_DMDRESDATA2 0xf2cd ++#define FSTV0910_P2_DMDRES_DATA2 0xf2cd00ff ++ ++/*P2_DMDRESDATA1*/ ++#define RSTV0910_P2_DMDRESDATA1 0xf2ce ++#define FSTV0910_P2_DMDRES_DATA1 0xf2ce00ff ++ ++/*P2_DMDRESDATA0*/ ++#define RSTV0910_P2_DMDRESDATA0 0xf2cf ++#define FSTV0910_P2_DMDRES_DATA0 0xf2cf00ff ++ ++/*P2_FFEI1*/ ++#define RSTV0910_P2_FFEI1 0xf2d0 ++#define FSTV0910_P2_FFE_ACCI1 0xf2d001ff ++ ++/*P2_FFEQ1*/ ++#define RSTV0910_P2_FFEQ1 0xf2d1 ++#define FSTV0910_P2_FFE_ACCQ1 0xf2d101ff ++ ++/*P2_FFEI2*/ ++#define RSTV0910_P2_FFEI2 0xf2d2 ++#define FSTV0910_P2_FFE_ACCI2 0xf2d201ff ++ ++/*P2_FFEQ2*/ ++#define RSTV0910_P2_FFEQ2 0xf2d3 ++#define FSTV0910_P2_FFE_ACCQ2 0xf2d301ff ++ ++/*P2_FFEI3*/ ++#define RSTV0910_P2_FFEI3 0xf2d4 ++#define FSTV0910_P2_FFE_ACCI3 0xf2d401ff ++ ++/*P2_FFEQ3*/ ++#define RSTV0910_P2_FFEQ3 0xf2d5 ++#define FSTV0910_P2_FFE_ACCQ3 0xf2d501ff ++ ++/*P2_FFEI4*/ ++#define RSTV0910_P2_FFEI4 0xf2d6 ++#define FSTV0910_P2_FFE_ACCI4 0xf2d601ff ++ ++/*P2_FFEQ4*/ ++#define RSTV0910_P2_FFEQ4 0xf2d7 ++#define FSTV0910_P2_FFE_ACCQ4 0xf2d701ff ++ ++/*P2_FFECFG*/ ++#define RSTV0910_P2_FFECFG 0xf2d8 ++#define FSTV0910_P2_EQUALFFE_ON 0xf2d80040 ++#define FSTV0910_P2_EQUAL_USEDSYMB 0xf2d80030 ++#define FSTV0910_P2_MU_EQUALFFE 0xf2d80007 ++ ++/*P2_TNRCFG2*/ ++#define RSTV0910_P2_TNRCFG2 0xf2e1 ++#define FSTV0910_P2_TUN_IQSWAP 0xf2e10080 ++#define FSTV0910_P2_STB6110_STEP2MHZ 0xf2e10040 ++#define FSTV0910_P2_STB6120_DBLI2C 0xf2e10020 ++#define FSTV0910_P2_TUNER_WIDEBAND 0xf2e10010 ++#define FSTV0910_P2_TUNER_OBSPAGE 0xf2e10008 ++#define FSTV0910_P2_DIS_BWCALC 0xf2e10004 ++#define FSTV0910_P2_SHORT_WAITSTATES 0xf2e10002 ++#define FSTV0910_P2_DIS_2BWAGC1 0xf2e10001 ++ ++/*P2_SMAPCOEF7*/ ++#define RSTV0910_P2_SMAPCOEF7 0xf300 ++#define FSTV0910_P2_DIS_QSCALE 0xf3000080 ++#define FSTV0910_P2_SMAPCOEF_Q_LLR12 0xf300017f ++ ++/*P2_SMAPCOEF6*/ ++#define RSTV0910_P2_SMAPCOEF6 0xf301 ++#define FSTV0910_P2_DIS_AGC2SCALE 0xf3010080 ++#define FSTV0910_P2_DIS_16IQMULT 0xf3010040 ++#define FSTV0910_P2_OLD_16APSK47 0xf3010020 ++#define FSTV0910_P2_OLD_16APSK12 0xf3010010 ++#define FSTV0910_P2_DIS_NEWSCALE 0xf3010008 ++#define FSTV0910_P2_ADJ_8PSKLLR1 0xf3010004 ++#define FSTV0910_P2_OLD_8PSKLLR1 0xf3010002 ++#define FSTV0910_P2_DIS_AB8PSK 0xf3010001 ++ ++/*P2_SMAPCOEF5*/ ++#define RSTV0910_P2_SMAPCOEF5 0xf302 ++#define FSTV0910_P2_DIS_8SCALE 0xf3020080 ++#define FSTV0910_P2_SMAPCOEF_8P_LLR23 0xf302017f ++ ++/*P2_NOSTHRES1*/ ++#define RSTV0910_P2_NOSTHRES1 0xf309 ++#define FSTV0910_P2_NOS_THRESHOLD1 0xf30900ff ++ ++/*P2_NOSTHRES2*/ ++#define RSTV0910_P2_NOSTHRES2 0xf30a ++#define FSTV0910_P2_NOS_THRESHOLD2 0xf30a00ff ++ ++/*P2_NOSDIFF1*/ ++#define RSTV0910_P2_NOSDIFF1 0xf30b ++#define FSTV0910_P2_NOSTHRES1_DIFF 0xf30b00ff ++ ++/*P2_RAINFADE*/ ++#define RSTV0910_P2_RAINFADE 0xf30c ++#define FSTV0910_P2_NOSTHRES_DATAT 0xf30c0080 ++#define FSTV0910_P2_RAINFADE_CNLIMIT 0xf30c0070 ++#define FSTV0910_P2_RAINFADE_TIMEOUT 0xf30c0007 ++ ++/*P2_NOSRAMCFG*/ ++#define RSTV0910_P2_NOSRAMCFG 0xf30d ++#define FSTV0910_P2_NOSRAM_DVBS2DATA 0xf30d0080 ++#define FSTV0910_P2_NOSRAM_QUADRAT 0xf30d0040 ++#define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d0030 ++#define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d0008 ++#define FSTV0910_P2_NOSRAM_LGNCNR1 0xf30d0007 ++ ++/*P2_NOSRAMPOS*/ ++#define RSTV0910_P2_NOSRAMPOS 0xf30e ++#define FSTV0910_P2_NOSRAM_LGNCNR0 0xf30e00f0 ++#define FSTV0910_P2_NOSRAM_VALIDE 0xf30e0004 ++#define FSTV0910_P2_NOSRAM_CNRVAL1 0xf30e0003 ++ ++/*P2_NOSRAMVAL*/ ++#define RSTV0910_P2_NOSRAMVAL 0xf30f ++#define FSTV0910_P2_NOSRAM_CNRVAL0 0xf30f00ff ++ ++/*P2_DMDPLHSTAT*/ ++#define RSTV0910_P2_DMDPLHSTAT 0xf320 ++#define FSTV0910_P2_PLH_STATISTIC 0xf32000ff ++ ++/*P2_LOCKTIME3*/ ++#define RSTV0910_P2_LOCKTIME3 0xf322 ++#define FSTV0910_P2_DEMOD_LOCKTIME3 0xf32200ff ++ ++/*P2_LOCKTIME2*/ ++#define RSTV0910_P2_LOCKTIME2 0xf323 ++#define FSTV0910_P2_DEMOD_LOCKTIME2 0xf32300ff ++ ++/*P2_LOCKTIME1*/ ++#define RSTV0910_P2_LOCKTIME1 0xf324 ++#define FSTV0910_P2_DEMOD_LOCKTIME1 0xf32400ff ++ ++/*P2_LOCKTIME0*/ ++#define RSTV0910_P2_LOCKTIME0 0xf325 ++#define FSTV0910_P2_DEMOD_LOCKTIME0 0xf32500ff ++ ++/*P2_VITSCALE*/ ++#define RSTV0910_P2_VITSCALE 0xf332 ++#define FSTV0910_P2_NVTH_NOSRANGE 0xf3320080 ++#define FSTV0910_P2_VERROR_MAXMODE 0xf3320040 ++#define FSTV0910_P2_KDIV_MODE 0xf3320030 ++#define FSTV0910_P2_NSLOWSN_LOCKED 0xf3320008 ++#define FSTV0910_P2_DELOCK_PRFLOSS 0xf3320004 ++#define FSTV0910_P2_DIS_RSFLOCK 0xf3320002 ++ ++/*P2_FECM*/ ++#define RSTV0910_P2_FECM 0xf333 ++#define FSTV0910_P2_DSS_DVB 0xf3330080 ++#define FSTV0910_P2_DEMOD_BYPASS 0xf3330040 ++#define FSTV0910_P2_CMP_SLOWMODE 0xf3330020 ++#define FSTV0910_P2_DSS_SRCH 0xf3330010 ++#define FSTV0910_P2_DIFF_MODEVIT 0xf3330004 ++#define FSTV0910_P2_SYNCVIT 0xf3330002 ++#define FSTV0910_P2_IQINV 0xf3330001 ++ ++/*P2_VTH12*/ ++#define RSTV0910_P2_VTH12 0xf334 ++#define FSTV0910_P2_VTH12 0xf33400ff ++ ++/*P2_VTH23*/ ++#define RSTV0910_P2_VTH23 0xf335 ++#define FSTV0910_P2_VTH23 0xf33500ff ++ ++/*P2_VTH34*/ ++#define RSTV0910_P2_VTH34 0xf336 ++#define FSTV0910_P2_VTH34 0xf33600ff ++ ++/*P2_VTH56*/ ++#define RSTV0910_P2_VTH56 0xf337 ++#define FSTV0910_P2_VTH56 0xf33700ff ++ ++/*P2_VTH67*/ ++#define RSTV0910_P2_VTH67 0xf338 ++#define FSTV0910_P2_VTH67 0xf33800ff ++ ++/*P2_VTH78*/ ++#define RSTV0910_P2_VTH78 0xf339 ++#define FSTV0910_P2_VTH78 0xf33900ff ++ ++/*P2_VITCURPUN*/ ++#define RSTV0910_P2_VITCURPUN 0xf33a ++#define FSTV0910_P2_CYCLESLIP_VIT 0xf33a0080 ++#define FSTV0910_P2_VIT_ROTA180 0xf33a0040 ++#define FSTV0910_P2_VIT_ROTA90 0xf33a0020 ++#define FSTV0910_P2_VIT_CURPUN 0xf33a001f ++ ++/*P2_VERROR*/ ++#define RSTV0910_P2_VERROR 0xf33b ++#define FSTV0910_P2_REGERR_VIT 0xf33b00ff ++ ++/*P2_PRVIT*/ ++#define RSTV0910_P2_PRVIT 0xf33c ++#define FSTV0910_P2_DIS_VTHLOCK 0xf33c0040 ++#define FSTV0910_P2_E7_8VIT 0xf33c0020 ++#define FSTV0910_P2_E6_7VIT 0xf33c0010 ++#define FSTV0910_P2_E5_6VIT 0xf33c0008 ++#define FSTV0910_P2_E3_4VIT 0xf33c0004 ++#define FSTV0910_P2_E2_3VIT 0xf33c0002 ++#define FSTV0910_P2_E1_2VIT 0xf33c0001 ++ ++/*P2_VAVSRVIT*/ ++#define RSTV0910_P2_VAVSRVIT 0xf33d ++#define FSTV0910_P2_AMVIT 0xf33d0080 ++#define FSTV0910_P2_FROZENVIT 0xf33d0040 ++#define FSTV0910_P2_SNVIT 0xf33d0030 ++#define FSTV0910_P2_TOVVIT 0xf33d000c ++#define FSTV0910_P2_HYPVIT 0xf33d0003 ++ ++/*P2_VSTATUSVIT*/ ++#define RSTV0910_P2_VSTATUSVIT 0xf33e ++#define FSTV0910_P2_VITERBI_ON 0xf33e0080 ++#define FSTV0910_P2_END_LOOPVIT 0xf33e0040 ++#define FSTV0910_P2_VITERBI_DEPRF 0xf33e0020 ++#define FSTV0910_P2_PRFVIT 0xf33e0010 ++#define FSTV0910_P2_LOCKEDVIT 0xf33e0008 ++#define FSTV0910_P2_VITERBI_DELOCK 0xf33e0004 ++#define FSTV0910_P2_VIT_DEMODSEL 0xf33e0002 ++#define FSTV0910_P2_VITERBI_COMPOUT 0xf33e0001 ++ ++/*P2_VTHINUSE*/ ++#define RSTV0910_P2_VTHINUSE 0xf33f ++#define FSTV0910_P2_VIT_INUSE 0xf33f00ff ++ ++/*P2_KDIV12*/ ++#define RSTV0910_P2_KDIV12 0xf340 ++#define FSTV0910_P2_KDIV12_MANUAL 0xf3400080 ++#define FSTV0910_P2_K_DIVIDER_12 0xf340007f ++ ++/*P2_KDIV23*/ ++#define RSTV0910_P2_KDIV23 0xf341 ++#define FSTV0910_P2_KDIV23_MANUAL 0xf3410080 ++#define FSTV0910_P2_K_DIVIDER_23 0xf341007f ++ ++/*P2_KDIV34*/ ++#define RSTV0910_P2_KDIV34 0xf342 ++#define FSTV0910_P2_KDIV34_MANUAL 0xf3420080 ++#define FSTV0910_P2_K_DIVIDER_34 0xf342007f ++ ++/*P2_KDIV56*/ ++#define RSTV0910_P2_KDIV56 0xf343 ++#define FSTV0910_P2_KDIV56_MANUAL 0xf3430080 ++#define FSTV0910_P2_K_DIVIDER_56 0xf343007f ++ ++/*P2_KDIV67*/ ++#define RSTV0910_P2_KDIV67 0xf344 ++#define FSTV0910_P2_KDIV67_MANUAL 0xf3440080 ++#define FSTV0910_P2_K_DIVIDER_67 0xf344007f ++ ++/*P2_KDIV78*/ ++#define RSTV0910_P2_KDIV78 0xf345 ++#define FSTV0910_P2_KDIV78_MANUAL 0xf3450080 ++#define FSTV0910_P2_K_DIVIDER_78 0xf345007f ++ ++/*P2_PDELCTRL0*/ ++#define RSTV0910_P2_PDELCTRL0 0xf34f ++#define FSTV0910_P2_ISIOBS_MODE 0xf34f0030 ++#define FSTV0910_P2_PDELDIS_BITWISE 0xf34f0004 ++ ++/*P2_PDELCTRL1*/ ++#define RSTV0910_P2_PDELCTRL1 0xf350 ++#define FSTV0910_P2_INV_MISMASK 0xf3500080 ++#define FSTV0910_P2_FORCE_ACCEPTED 0xf3500040 ++#define FSTV0910_P2_FILTER_EN 0xf3500020 ++#define FSTV0910_P2_FORCE_PKTDELINUSE 0xf3500010 ++#define FSTV0910_P2_HYSTEN 0xf3500008 ++#define FSTV0910_P2_HYSTSWRST 0xf3500004 ++#define FSTV0910_P2_EN_MIS00 0xf3500002 ++#define FSTV0910_P2_ALGOSWRST 0xf3500001 ++ ++/*P2_PDELCTRL2*/ ++#define RSTV0910_P2_PDELCTRL2 0xf351 ++#define FSTV0910_P2_FORCE_CONTINUOUS 0xf3510080 ++#define FSTV0910_P2_RESET_UPKO_COUNT 0xf3510040 ++#define FSTV0910_P2_USER_PKTDELIN_NB 0xf3510020 ++#define FSTV0910_P2_DATA_UNBBSCRAMBLED 0xf3510008 ++#define FSTV0910_P2_FORCE_LONGPKT 0xf3510004 ++#define FSTV0910_P2_FRAME_MODE 0xf3510002 ++ ++/*P2_HYSTTHRESH*/ ++#define RSTV0910_P2_HYSTTHRESH 0xf354 ++#define FSTV0910_P2_DELIN_LOCKTHRES 0xf35400f0 ++#define FSTV0910_P2_DELIN_UNLOCKTHRES 0xf354000f ++ ++/*P2_ISIENTRY*/ ++#define RSTV0910_P2_ISIENTRY 0xf35e ++#define FSTV0910_P2_ISI_ENTRY 0xf35e00ff ++ ++/*P2_ISIBITENA*/ ++#define RSTV0910_P2_ISIBITENA 0xf35f ++#define FSTV0910_P2_ISI_BIT_EN 0xf35f00ff ++ ++/*P2_MATSTR1*/ ++#define RSTV0910_P2_MATSTR1 0xf360 ++#define FSTV0910_P2_MATYPE_CURRENT1 0xf36000ff ++ ++/*P2_MATSTR0*/ ++#define RSTV0910_P2_MATSTR0 0xf361 ++#define FSTV0910_P2_MATYPE_CURRENT0 0xf36100ff ++ ++/*P2_UPLSTR1*/ ++#define RSTV0910_P2_UPLSTR1 0xf362 ++#define FSTV0910_P2_UPL_CURRENT1 0xf36200ff ++ ++/*P2_UPLSTR0*/ ++#define RSTV0910_P2_UPLSTR0 0xf363 ++#define FSTV0910_P2_UPL_CURRENT0 0xf36300ff ++ ++/*P2_DFLSTR1*/ ++#define RSTV0910_P2_DFLSTR1 0xf364 ++#define FSTV0910_P2_DFL_CURRENT1 0xf36400ff ++ ++/*P2_DFLSTR0*/ ++#define RSTV0910_P2_DFLSTR0 0xf365 ++#define FSTV0910_P2_DFL_CURRENT0 0xf36500ff ++ ++/*P2_SYNCSTR*/ ++#define RSTV0910_P2_SYNCSTR 0xf366 ++#define FSTV0910_P2_SYNC_CURRENT 0xf36600ff ++ ++/*P2_SYNCDSTR1*/ ++#define RSTV0910_P2_SYNCDSTR1 0xf367 ++#define FSTV0910_P2_SYNCD_CURRENT1 0xf36700ff ++ ++/*P2_SYNCDSTR0*/ ++#define RSTV0910_P2_SYNCDSTR0 0xf368 ++#define FSTV0910_P2_SYNCD_CURRENT0 0xf36800ff ++ ++/*P2_PDELSTATUS1*/ ++#define RSTV0910_P2_PDELSTATUS1 0xf369 ++#define FSTV0910_P2_PKTDELIN_DELOCK 0xf3690080 ++#define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3690040 ++#define FSTV0910_P2_CONTINUOUS_STREAM 0xf3690020 ++#define FSTV0910_P2_UNACCEPTED_STREAM 0xf3690010 ++#define FSTV0910_P2_BCH_ERROR_FLAG 0xf3690008 ++#define FSTV0910_P2_BBHCRCKO 0xf3690004 ++#define FSTV0910_P2_PKTDELIN_LOCK 0xf3690002 ++#define FSTV0910_P2_FIRST_LOCK 0xf3690001 ++ ++/*P2_PDELSTATUS2*/ ++#define RSTV0910_P2_PDELSTATUS2 0xf36a ++#define FSTV0910_P2_PKTDEL_DEMODSEL 0xf36a0080 ++#define FSTV0910_P2_FRAME_MODCOD 0xf36a007c ++#define FSTV0910_P2_FRAME_TYPE 0xf36a0003 ++ ++/*P2_BBFCRCKO1*/ ++#define RSTV0910_P2_BBFCRCKO1 0xf36b ++#define FSTV0910_P2_BBHCRC_KOCNT1 0xf36b00ff ++ ++/*P2_BBFCRCKO0*/ ++#define RSTV0910_P2_BBFCRCKO0 0xf36c ++#define FSTV0910_P2_BBHCRC_KOCNT0 0xf36c00ff ++ ++/*P2_UPCRCKO1*/ ++#define RSTV0910_P2_UPCRCKO1 0xf36d ++#define FSTV0910_P2_PKTCRC_KOCNT1 0xf36d00ff ++ ++/*P2_UPCRCKO0*/ ++#define RSTV0910_P2_UPCRCKO0 0xf36e ++#define FSTV0910_P2_PKTCRC_KOCNT0 0xf36e00ff ++ ++/*P2_PDELCTRL3*/ ++#define RSTV0910_P2_PDELCTRL3 0xf36f ++#define FSTV0910_P2_PKTDEL_CONTFAIL 0xf36f0080 ++#define FSTV0910_P2_PKTDEL_ENLONGPKT 0xf36f0040 ++#define FSTV0910_P2_NOFIFO_BCHERR 0xf36f0020 ++#define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f0010 ++#define FSTV0910_P2_SATURATE_BBPKTKO 0xf36f0004 ++#define FSTV0910_P2_PKTDEL_BCHERRCONT 0xf36f0002 ++#define FSTV0910_P2_ETHERNET_DISFCS 0xf36f0001 ++ ++/*P2_TSSTATEM*/ ++#define RSTV0910_P2_TSSTATEM 0xf370 ++#define FSTV0910_P2_TSDIL_ON 0xf3700080 ++#define FSTV0910_P2_TSSKIPRS_ON 0xf3700040 ++#define FSTV0910_P2_TSRS_ON 0xf3700020 ++#define FSTV0910_P2_TSDESCRAMB_ON 0xf3700010 ++#define FSTV0910_P2_TSFRAME_MODE 0xf3700008 ++#define FSTV0910_P2_TS_DISABLE 0xf3700004 ++#define FSTV0910_P2_TSACM_MODE 0xf3700002 ++#define FSTV0910_P2_TSOUT_NOSYNC 0xf3700001 ++ ++/*P2_TSCFGH*/ ++#define RSTV0910_P2_TSCFGH 0xf372 ++#define FSTV0910_P2_TSFIFO_DVBCI 0xf3720080 ++#define FSTV0910_P2_TSFIFO_SERIAL 0xf3720040 ++#define FSTV0910_P2_TSFIFO_TEIUPDATE 0xf3720020 ++#define FSTV0910_P2_TSFIFO_DUTY50 0xf3720010 ++#define FSTV0910_P2_TSFIFO_HSGNLOUT 0xf3720008 ++#define FSTV0910_P2_TSFIFO_ERRMODE 0xf3720006 ++#define FSTV0910_P2_RST_HWARE 0xf3720001 ++ ++/*P2_TSCFGM*/ ++#define RSTV0910_P2_TSCFGM 0xf373 ++#define FSTV0910_P2_TSFIFO_MANSPEED 0xf37300c0 ++#define FSTV0910_P2_TSFIFO_PERMDATA 0xf3730020 ++#define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3730010 ++#define FSTV0910_P2_NPD_SPECDVBS2 0xf3730004 ++#define FSTV0910_P2_TSFIFO_DPUNACTIVE 0xf3730002 ++#define FSTV0910_P2_TSFIFO_INVDATA 0xf3730001 ++ ++/*P2_TSCFGL*/ ++#define RSTV0910_P2_TSCFGL 0xf374 ++#define FSTV0910_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 ++#define FSTV0910_P2_BCHERROR_MODE 0xf3740030 ++#define FSTV0910_P2_TSFIFO_NSGNL2DATA 0xf3740008 ++#define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3740004 ++#define FSTV0910_P2_TSFIFO_BITSPEED 0xf3740003 ++ ++/*P2_TSINSDELH*/ ++#define RSTV0910_P2_TSINSDELH 0xf376 ++#define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3760080 ++#define FSTV0910_P2_TSDEL_XXHEADER 0xf3760040 ++#define FSTV0910_P2_TSDEL_BBHEADER 0xf3760020 ++#define FSTV0910_P2_TSDEL_DATAFIELD 0xf3760010 ++#define FSTV0910_P2_TSINSDEL_ISCR 0xf3760008 ++#define FSTV0910_P2_TSINSDEL_NPD 0xf3760004 ++#define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3760002 ++#define FSTV0910_P2_TSINSDEL_CRC8 0xf3760001 ++ ++/*P2_TSDIVN*/ ++#define RSTV0910_P2_TSDIVN 0xf379 ++#define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37900c0 ++#define FSTV0910_P2_BYTE_OVERSAMPLING 0xf3790038 ++#define FSTV0910_P2_TSFIFO_RISEOK 0xf3790007 ++ ++/*P2_TSCFG4*/ ++#define RSTV0910_P2_TSCFG4 0xf37a ++#define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 ++#define FSTV0910_P2_TSFIFO_HIERSEL 0xf37a0020 ++#define FSTV0910_P2_TSFIFO_SPECTOKEN 0xf37a0010 ++#define FSTV0910_P2_TSFIFO_MAXMODE 0xf37a0008 ++#define FSTV0910_P2_TSFIFO_FRFORCEPKT 0xf37a0004 ++#define FSTV0910_P2_EXT_FECSPYIN 0xf37a0002 ++#define FSTV0910_P2_TSFIFO_DELSPEEDUP 0xf37a0001 ++ ++/*P2_TSSPEED*/ ++#define RSTV0910_P2_TSSPEED 0xf380 ++#define FSTV0910_P2_TSFIFO_OUTSPEED 0xf38000ff ++ ++/*P2_TSSTATUS*/ ++#define RSTV0910_P2_TSSTATUS 0xf381 ++#define FSTV0910_P2_TSFIFO_LINEOK 0xf3810080 ++#define FSTV0910_P2_TSFIFO_ERROR 0xf3810040 ++#define FSTV0910_P2_TSFIFO_DATA7 0xf3810020 ++#define FSTV0910_P2_TSFIFO_NOSYNC 0xf3810010 ++#define FSTV0910_P2_ISCR_INITIALIZED 0xf3810008 ++#define FSTV0910_P2_TSREGUL_ERROR 0xf3810004 ++#define FSTV0910_P2_SOFFIFO_UNREGUL 0xf3810002 ++#define FSTV0910_P2_DIL_READY 0xf3810001 ++ ++/*P2_TSSTATUS2*/ ++#define RSTV0910_P2_TSSTATUS2 0xf382 ++#define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3820080 ++#define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3820040 ++#define FSTV0910_P2_DILXX_RESET 0xf3820020 ++#define FSTV0910_P2_TSSPEED_IMPOSSIBLE 0xf3820010 ++#define FSTV0910_P2_TSFIFO_LINENOK 0xf3820008 ++#define FSTV0910_P2_TSFIFO_MUXSTREAM 0xf3820004 ++#define FSTV0910_P2_SCRAMBDETECT 0xf3820002 ++#define FSTV0910_P2_ULDTV67_FALSELOCK 0xf3820001 ++ ++/*P2_TSBITRATE1*/ ++#define RSTV0910_P2_TSBITRATE1 0xf383 ++#define FSTV0910_P2_TSFIFO_BITRATE1 0xf38300ff ++ ++/*P2_TSBITRATE0*/ ++#define RSTV0910_P2_TSBITRATE0 0xf384 ++#define FSTV0910_P2_TSFIFO_BITRATE0 0xf38400ff ++ ++/*P2_ERRCTRL1*/ ++#define RSTV0910_P2_ERRCTRL1 0xf398 ++#define FSTV0910_P2_ERR_SOURCE1 0xf39800f0 ++#define FSTV0910_P2_NUM_EVENT1 0xf3980007 ++ ++/*P2_ERRCNT12*/ ++#define RSTV0910_P2_ERRCNT12 0xf399 ++#define FSTV0910_P2_ERRCNT1_OLDVALUE 0xf3990080 ++#define FSTV0910_P2_ERR_CNT12 0xf399007f ++ ++/*P2_ERRCNT11*/ ++#define RSTV0910_P2_ERRCNT11 0xf39a ++#define FSTV0910_P2_ERR_CNT11 0xf39a00ff ++ ++/*P2_ERRCNT10*/ ++#define RSTV0910_P2_ERRCNT10 0xf39b ++#define FSTV0910_P2_ERR_CNT10 0xf39b00ff ++ ++/*P2_ERRCTRL2*/ ++#define RSTV0910_P2_ERRCTRL2 0xf39c ++#define FSTV0910_P2_ERR_SOURCE2 0xf39c00f0 ++#define FSTV0910_P2_NUM_EVENT2 0xf39c0007 ++ ++/*P2_ERRCNT22*/ ++#define RSTV0910_P2_ERRCNT22 0xf39d ++#define FSTV0910_P2_ERRCNT2_OLDVALUE 0xf39d0080 ++#define FSTV0910_P2_ERR_CNT22 0xf39d007f ++ ++/*P2_ERRCNT21*/ ++#define RSTV0910_P2_ERRCNT21 0xf39e ++#define FSTV0910_P2_ERR_CNT21 0xf39e00ff ++ ++/*P2_ERRCNT20*/ ++#define RSTV0910_P2_ERRCNT20 0xf39f ++#define FSTV0910_P2_ERR_CNT20 0xf39f00ff ++ ++/*P2_FECSPY*/ ++#define RSTV0910_P2_FECSPY 0xf3a0 ++#define FSTV0910_P2_SPY_ENABLE 0xf3a00080 ++#define FSTV0910_P2_NO_SYNCBYTE 0xf3a00040 ++#define FSTV0910_P2_SERIAL_MODE 0xf3a00020 ++#define FSTV0910_P2_UNUSUAL_PACKET 0xf3a00010 ++#define FSTV0910_P2_BERMETER_DATAMODE 0xf3a0000c ++#define FSTV0910_P2_BERMETER_LMODE 0xf3a00002 ++#define FSTV0910_P2_BERMETER_RESET 0xf3a00001 ++ ++/*P2_FSPYCFG*/ ++#define RSTV0910_P2_FSPYCFG 0xf3a1 ++#define FSTV0910_P2_FECSPY_INPUT 0xf3a100c0 ++#define FSTV0910_P2_RST_ON_ERROR 0xf3a10020 ++#define FSTV0910_P2_ONE_SHOT 0xf3a10010 ++#define FSTV0910_P2_I2C_MODE 0xf3a1000c ++#define FSTV0910_P2_SPY_HYSTERESIS 0xf3a10003 ++ ++/*P2_FSPYDATA*/ ++#define RSTV0910_P2_FSPYDATA 0xf3a2 ++#define FSTV0910_P2_SPY_STUFFING 0xf3a20080 ++#define FSTV0910_P2_NOERROR_PKTJITTER 0xf3a20040 ++#define FSTV0910_P2_SPY_CNULLPKT 0xf3a20020 ++#define FSTV0910_P2_SPY_OUTDATA_MODE 0xf3a2001f ++ ++/*P2_FSPYOUT*/ ++#define RSTV0910_P2_FSPYOUT 0xf3a3 ++#define FSTV0910_P2_FSPY_DIRECT 0xf3a30080 ++#define FSTV0910_P2_SPY_OUTDATA_BUS 0xf3a30038 ++#define FSTV0910_P2_STUFF_MODE 0xf3a30007 ++ ++/*P2_FSTATUS*/ ++#define RSTV0910_P2_FSTATUS 0xf3a4 ++#define FSTV0910_P2_SPY_ENDSIM 0xf3a40080 ++#define FSTV0910_P2_VALID_SIM 0xf3a40040 ++#define FSTV0910_P2_FOUND_SIGNAL 0xf3a40020 ++#define FSTV0910_P2_DSS_SYNCBYTE 0xf3a40010 ++#define FSTV0910_P2_RESULT_STATE 0xf3a4000f ++ ++/*P2_FBERCPT4*/ ++#define RSTV0910_P2_FBERCPT4 0xf3a8 ++#define FSTV0910_P2_FBERMETER_CPT4 0xf3a800ff ++ ++/*P2_FBERCPT3*/ ++#define RSTV0910_P2_FBERCPT3 0xf3a9 ++#define FSTV0910_P2_FBERMETER_CPT3 0xf3a900ff ++ ++/*P2_FBERCPT2*/ ++#define RSTV0910_P2_FBERCPT2 0xf3aa ++#define FSTV0910_P2_FBERMETER_CPT2 0xf3aa00ff ++ ++/*P2_FBERCPT1*/ ++#define RSTV0910_P2_FBERCPT1 0xf3ab ++#define FSTV0910_P2_FBERMETER_CPT1 0xf3ab00ff ++ ++/*P2_FBERCPT0*/ ++#define RSTV0910_P2_FBERCPT0 0xf3ac ++#define FSTV0910_P2_FBERMETER_CPT0 0xf3ac00ff ++ ++/*P2_FBERERR2*/ ++#define RSTV0910_P2_FBERERR2 0xf3ad ++#define FSTV0910_P2_FBERMETER_ERR2 0xf3ad00ff ++ ++/*P2_FBERERR1*/ ++#define RSTV0910_P2_FBERERR1 0xf3ae ++#define FSTV0910_P2_FBERMETER_ERR1 0xf3ae00ff ++ ++/*P2_FBERERR0*/ ++#define RSTV0910_P2_FBERERR0 0xf3af ++#define FSTV0910_P2_FBERMETER_ERR0 0xf3af00ff ++ ++/*P2_FSPYBER*/ ++#define RSTV0910_P2_FSPYBER 0xf3b2 ++#define FSTV0910_P2_FSPYOBS_XORREAD 0xf3b20040 ++#define FSTV0910_P2_FSPYBER_OBSMODE 0xf3b20020 ++#define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b20010 ++#define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b20008 ++#define FSTV0910_P2_FSPYBER_CTIME 0xf3b20007 ++ ++/*P2_SFERROR*/ ++#define RSTV0910_P2_SFERROR 0xf3c1 ++#define FSTV0910_P2_SFEC_REGERR_VIT 0xf3c100ff ++ ++/*P2_SFECSTATUS*/ ++#define RSTV0910_P2_SFECSTATUS 0xf3c3 ++#define FSTV0910_P2_SFEC_ON 0xf3c30080 ++#define FSTV0910_P2_SFEC_OFF 0xf3c30040 ++#define FSTV0910_P2_LOCKEDSFEC 0xf3c30008 ++#define FSTV0910_P2_SFEC_DELOCK 0xf3c30004 ++#define FSTV0910_P2_SFEC_DEMODSEL 0xf3c30002 ++#define FSTV0910_P2_SFEC_OVFON 0xf3c30001 ++ ++/*P2_SFKDIV12*/ ++#define RSTV0910_P2_SFKDIV12 0xf3c4 ++#define FSTV0910_P2_SFECKDIV12_MAN 0xf3c40080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_12 0xf3c4007f ++ ++/*P2_SFKDIV23*/ ++#define RSTV0910_P2_SFKDIV23 0xf3c5 ++#define FSTV0910_P2_SFECKDIV23_MAN 0xf3c50080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_23 0xf3c5007f ++ ++/*P2_SFKDIV34*/ ++#define RSTV0910_P2_SFKDIV34 0xf3c6 ++#define FSTV0910_P2_SFECKDIV34_MAN 0xf3c60080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_34 0xf3c6007f ++ ++/*P2_SFKDIV56*/ ++#define RSTV0910_P2_SFKDIV56 0xf3c7 ++#define FSTV0910_P2_SFECKDIV56_MAN 0xf3c70080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_56 0xf3c7007f ++ ++/*P2_SFKDIV67*/ ++#define RSTV0910_P2_SFKDIV67 0xf3c8 ++#define FSTV0910_P2_SFECKDIV67_MAN 0xf3c80080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_67 0xf3c8007f ++ ++/*P2_SFKDIV78*/ ++#define RSTV0910_P2_SFKDIV78 0xf3c9 ++#define FSTV0910_P2_SFECKDIV78_MAN 0xf3c90080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_78 0xf3c9007f ++ ++/*P2_SFSTATUS*/ ++#define RSTV0910_P2_SFSTATUS 0xf3cc ++#define FSTV0910_P2_SFEC_LINEOK 0xf3cc0080 ++#define FSTV0910_P2_SFEC_ERROR 0xf3cc0040 ++#define FSTV0910_P2_SFEC_DATA7 0xf3cc0020 ++#define FSTV0910_P2_SFEC_PKTDNBRFAIL 0xf3cc0010 ++#define FSTV0910_P2_TSSFEC_DEMODSEL 0xf3cc0008 ++#define FSTV0910_P2_SFEC_NOSYNC 0xf3cc0004 ++#define FSTV0910_P2_SFEC_UNREGULA 0xf3cc0002 ++#define FSTV0910_P2_SFEC_READY 0xf3cc0001 ++ ++/*P2_SFDLYSET2*/ ++#define RSTV0910_P2_SFDLYSET2 0xf3d0 ++#define FSTV0910_P2_SFEC_OFFSET 0xf3d000c0 ++#define FSTV0910_P2_RST_SFEC 0xf3d00008 ++#define FSTV0910_P2_DILDLINE_ERROR 0xf3d00004 ++#define FSTV0910_P2_SFEC_DISABLE 0xf3d00002 ++#define FSTV0910_P2_SFEC_UNREGUL 0xf3d00001 ++ ++/*P2_SFERRCTRL*/ ++#define RSTV0910_P2_SFERRCTRL 0xf3d8 ++#define FSTV0910_P2_SFEC_ERR_SOURCE 0xf3d800f0 ++#define FSTV0910_P2_SFEC_NUM_EVENT 0xf3d80007 ++ ++/*P2_SFERRCNT2*/ ++#define RSTV0910_P2_SFERRCNT2 0xf3d9 ++#define FSTV0910_P2_SFERRC_OLDVALUE 0xf3d90080 ++#define FSTV0910_P2_SFEC_ERR_CNT2 0xf3d9007f ++ ++/*P2_SFERRCNT1*/ ++#define RSTV0910_P2_SFERRCNT1 0xf3da ++#define FSTV0910_P2_SFEC_ERR_CNT1 0xf3da00ff ++ ++/*P2_SFERRCNT0*/ ++#define RSTV0910_P2_SFERRCNT0 0xf3db ++#define FSTV0910_P2_SFEC_ERR_CNT0 0xf3db00ff ++ ++/*P1_IQCONST*/ ++#define RSTV0910_P1_IQCONST 0xf400 ++#define FSTV0910_P1_CONSTEL_SELECT 0xf4000060 ++#define FSTV0910_P1_IQSYMB_SEL 0xf400001f ++ ++/*P1_NOSCFG*/ ++#define RSTV0910_P1_NOSCFG 0xf401 ++#define FSTV0910_P1_DIS_ACMRATIO 0xf4010080 ++#define FSTV0910_P1_NOSIN_EGALSEL 0xf4010040 ++#define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4010020 ++#define FSTV0910_P1_NOSPLH_BETA 0xf4010018 ++#define FSTV0910_P1_NOSDATA_BETA 0xf4010007 ++ ++/*P1_ISYMB*/ ++#define RSTV0910_P1_ISYMB 0xf402 ++#define FSTV0910_P1_I_SYMBOL 0xf40201ff ++ ++/*P1_QSYMB*/ ++#define RSTV0910_P1_QSYMB 0xf403 ++#define FSTV0910_P1_Q_SYMBOL 0xf40301ff ++ ++/*P1_AGC1CFG*/ ++#define RSTV0910_P1_AGC1CFG 0xf404 ++#define FSTV0910_P1_DC_FROZEN 0xf4040080 ++#define FSTV0910_P1_DC_CORRECT 0xf4040040 ++#define FSTV0910_P1_AMM_FROZEN 0xf4040020 ++#define FSTV0910_P1_AMM_CORRECT 0xf4040010 ++#define FSTV0910_P1_QUAD_FROZEN 0xf4040008 ++#define FSTV0910_P1_QUAD_CORRECT 0xf4040004 ++#define FSTV0910_P1_DCCOMP_SLOW 0xf4040002 ++#define FSTV0910_P1_IQMISM_SLOW 0xf4040001 ++ ++/*P1_AGC1CN*/ ++#define RSTV0910_P1_AGC1CN 0xf406 ++#define FSTV0910_P1_AGC1_LOCKED 0xf4060080 ++#define FSTV0910_P1_AGC1_OVERFLOW 0xf4060040 ++#define FSTV0910_P1_AGC1_NOSLOWLK 0xf4060020 ++#define FSTV0910_P1_AGC1_MINPOWER 0xf4060010 ++#define FSTV0910_P1_AGCOUT_FAST 0xf4060008 ++#define FSTV0910_P1_AGCIQ_BETA 0xf4060007 ++ ++/*P1_AGC1REF*/ ++#define RSTV0910_P1_AGC1REF 0xf407 ++#define FSTV0910_P1_AGCIQ_REF 0xf40700ff ++ ++/*P1_IDCCOMP*/ ++#define RSTV0910_P1_IDCCOMP 0xf408 ++#define FSTV0910_P1_IAVERAGE_ADJ 0xf40801ff ++ ++/*P1_QDCCOMP*/ ++#define RSTV0910_P1_QDCCOMP 0xf409 ++#define FSTV0910_P1_QAVERAGE_ADJ 0xf40901ff ++ ++/*P1_POWERI*/ ++#define RSTV0910_P1_POWERI 0xf40a ++#define FSTV0910_P1_POWER_I 0xf40a00ff ++ ++/*P1_POWERQ*/ ++#define RSTV0910_P1_POWERQ 0xf40b ++#define FSTV0910_P1_POWER_Q 0xf40b00ff ++ ++/*P1_AGC1AMM*/ ++#define RSTV0910_P1_AGC1AMM 0xf40c ++#define FSTV0910_P1_AMM_VALUE 0xf40c00ff ++ ++/*P1_AGC1QUAD*/ ++#define RSTV0910_P1_AGC1QUAD 0xf40d ++#define FSTV0910_P1_QUAD_VALUE 0xf40d01ff ++ ++/*P1_AGCIQIN1*/ ++#define RSTV0910_P1_AGCIQIN1 0xf40e ++#define FSTV0910_P1_AGCIQ_VALUE1 0xf40e00ff ++ ++/*P1_AGCIQIN0*/ ++#define RSTV0910_P1_AGCIQIN0 0xf40f ++#define FSTV0910_P1_AGCIQ_VALUE0 0xf40f00ff ++ ++/*P1_DEMOD*/ ++#define RSTV0910_P1_DEMOD 0xf410 ++#define FSTV0910_P1_MANUALS2_ROLLOFF 0xf4100080 ++#define FSTV0910_P1_SPECINV_CONTROL 0xf4100030 ++#define FSTV0910_P1_MANUALSX_ROLLOFF 0xf4100004 ++#define FSTV0910_P1_ROLLOFF_CONTROL 0xf4100003 ++ ++/*P1_DMDMODCOD*/ ++#define RSTV0910_P1_DMDMODCOD 0xf411 ++#define FSTV0910_P1_MANUAL_MODCOD 0xf4110080 ++#define FSTV0910_P1_DEMOD_MODCOD 0xf411007c ++#define FSTV0910_P1_DEMOD_TYPE 0xf4110003 ++ ++/*P1_DSTATUS*/ ++#define RSTV0910_P1_DSTATUS 0xf412 ++#define FSTV0910_P1_CAR_LOCK 0xf4120080 ++#define FSTV0910_P1_TMGLOCK_QUALITY 0xf4120060 ++#define FSTV0910_P1_SDVBS1_ENABLE 0xf4120010 ++#define FSTV0910_P1_LOCK_DEFINITIF 0xf4120008 ++#define FSTV0910_P1_TIMING_IS_LOCKED 0xf4120004 ++#define FSTV0910_P1_DEMOD_SYSCFG 0xf4120002 ++#define FSTV0910_P1_OVADC_DETECT 0xf4120001 ++ ++/*P1_DSTATUS2*/ ++#define RSTV0910_P1_DSTATUS2 0xf413 ++#define FSTV0910_P1_DEMOD_DELOCK 0xf4130080 ++#define FSTV0910_P1_DEMOD_TIMEOUT 0xf4130040 ++#define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4130020 ++#define FSTV0910_P1_POLYPH_SATEVENT 0xf4130010 ++#define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4130008 ++#define FSTV0910_P1_AGC2_OVERFLOW 0xf4130004 ++#define FSTV0910_P1_CFR_OVERFLOW 0xf4130002 ++#define FSTV0910_P1_GAMMA_OVERUNDER 0xf4130001 ++ ++/*P1_DMDCFGMD*/ ++#define RSTV0910_P1_DMDCFGMD 0xf414 ++#define FSTV0910_P1_DVBS2_ENABLE 0xf4140080 ++#define FSTV0910_P1_DVBS1_ENABLE 0xf4140040 ++#define FSTV0910_P1_SCAN_ENABLE 0xf4140010 ++#define FSTV0910_P1_CFR_AUTOSCAN 0xf4140008 ++#define FSTV0910_P1_NOFORCE_RELOCK 0xf4140004 ++#define FSTV0910_P1_TUN_RNG 0xf4140003 ++ ++/*P1_DMDCFG2*/ ++#define RSTV0910_P1_DMDCFG2 0xf415 ++#define FSTV0910_P1_AGC1_WAITLOCK 0xf4150080 ++#define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4150040 ++#define FSTV0910_P1_BLINDPEA_MODE 0xf4150020 ++#define FSTV0910_P1_INFINITE_RELOCK 0xf4150010 ++#define FSTV0910_P1_BWOFFSET_COLDWARM 0xf4150008 ++#define FSTV0910_P1_TMGLOCK_NSCANSTOP 0xf4150004 ++#define FSTV0910_P1_COARSE_LK3MODE 0xf4150002 ++#define FSTV0910_P1_COARSE_LK2MODE 0xf4150001 ++ ++/*P1_DMDISTATE*/ ++#define RSTV0910_P1_DMDISTATE 0xf416 ++#define FSTV0910_P1_I2C_NORESETDMODE 0xf4160080 ++#define FSTV0910_P1_FORCE_ETAPED 0xf4160040 ++#define FSTV0910_P1_SDMDRST_DIRCLK 0xf4160020 ++#define FSTV0910_P1_I2C_DEMOD_MODE 0xf416001f ++ ++/*P1_DMDT0M*/ ++#define RSTV0910_P1_DMDT0M 0xf417 ++#define FSTV0910_P1_DMDT0_MIN 0xf41700ff ++ ++/*P1_DMDSTATE*/ ++#define RSTV0910_P1_DMDSTATE 0xf41b ++#define FSTV0910_P1_DEMOD_LOCKED 0xf41b0080 ++#define FSTV0910_P1_HEADER_MODE 0xf41b0060 ++#define FSTV0910_P1_DEMOD_MODE 0xf41b001f ++ ++/*P1_DMDFLYW*/ ++#define RSTV0910_P1_DMDFLYW 0xf41c ++#define FSTV0910_P1_I2C_IRQVAL 0xf41c00f0 ++#define FSTV0910_P1_FLYWHEEL_CPT 0xf41c000f ++ ++/*P1_DSTATUS3*/ ++#define RSTV0910_P1_DSTATUS3 0xf41d ++#define FSTV0910_P1_CFR_ZIGZAG 0xf41d0080 ++#define FSTV0910_P1_DEMOD_CFGMODE 0xf41d0060 ++#define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d0010 ++#define FSTV0910_P1_RELOCK_MODE 0xf41d0008 ++#define FSTV0910_P1_DEMOD_FAIL 0xf41d0004 ++#define FSTV0910_P1_ETAPE1A_DVBXMEM 0xf41d0003 ++ ++/*P1_DMDCFG3*/ ++#define RSTV0910_P1_DMDCFG3 0xf41e ++#define FSTV0910_P1_DVBS1_TMGWAIT 0xf41e0080 ++#define FSTV0910_P1_NO_BWCENTERING 0xf41e0040 ++#define FSTV0910_P1_INV_SEQSRCH 0xf41e0020 ++#define FSTV0910_P1_DIS_SFRUPLOW_TRK 0xf41e0010 ++#define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e0008 ++#define FSTV0910_P1_LOCKTIME_MODE 0xf41e0007 ++ ++/*P1_DMDCFG4*/ ++#define RSTV0910_P1_DMDCFG4 0xf41f ++#define FSTV0910_P1_DIS_VITLOCK 0xf41f0080 ++#define FSTV0910_P1_S1S2TOUT_FAST 0xf41f0040 ++#define FSTV0910_P1_DEMOD_FASTLOCK 0xf41f0020 ++#define FSTV0910_P1_S1HIER_ENABLE 0xf41f0010 ++#define FSTV0910_P1_TUNER_NRELAUNCH 0xf41f0008 ++#define FSTV0910_P1_DIS_CLKENABLE 0xf41f0004 ++#define FSTV0910_P1_DIS_HDRDIVLOCK 0xf41f0002 ++#define FSTV0910_P1_NO_TNRWBINIT 0xf41f0001 ++ ++/*P1_CORRELMANT*/ ++#define RSTV0910_P1_CORRELMANT 0xf420 ++#define FSTV0910_P1_CORREL_MANT 0xf42000ff ++ ++/*P1_CORRELABS*/ ++#define RSTV0910_P1_CORRELABS 0xf421 ++#define FSTV0910_P1_CORREL_ABS 0xf42100ff ++ ++/*P1_CORRELEXP*/ ++#define RSTV0910_P1_CORRELEXP 0xf422 ++#define FSTV0910_P1_CORREL_ABSEXP 0xf42200f0 ++#define FSTV0910_P1_CORREL_EXP 0xf422000f ++ ++/*P1_PLHMODCOD*/ ++#define RSTV0910_P1_PLHMODCOD 0xf424 ++#define FSTV0910_P1_SPECINV_DEMOD 0xf4240080 ++#define FSTV0910_P1_PLH_MODCOD 0xf424007c ++#define FSTV0910_P1_PLH_TYPE 0xf4240003 ++ ++/*P1_DMDREG*/ ++#define RSTV0910_P1_DMDREG 0xf425 ++#define FSTV0910_P1_EXTPSK_MODE 0xf4250080 ++#define FSTV0910_P1_HIER_SHORTFRAME 0xf4250002 ++#define FSTV0910_P1_DECIM_PLFRAMES 0xf4250001 ++ ++/*P1_AGC2O*/ ++#define RSTV0910_P1_AGC2O 0xf42c ++#define FSTV0910_P1_CSTENV_MODE 0xf42c00c0 ++#define FSTV0910_P1_AGC2_LKSQRT 0xf42c0020 ++#define FSTV0910_P1_AGC2_LKMODE 0xf42c0010 ++#define FSTV0910_P1_AGC2_LKEQUA 0xf42c0008 ++#define FSTV0910_P1_AGC2_COEF 0xf42c0007 ++ ++/*P1_AGC2REF*/ ++#define RSTV0910_P1_AGC2REF 0xf42d ++#define FSTV0910_P1_AGC2_REF 0xf42d00ff ++ ++/*P1_AGC1ADJ*/ ++#define RSTV0910_P1_AGC1ADJ 0xf42e ++#define FSTV0910_P1_AGC1ADJ_MANUAL 0xf42e0080 ++#define FSTV0910_P1_AGC1_ADJUSTED 0xf42e007f ++ ++/*P1_AGC2I1*/ ++#define RSTV0910_P1_AGC2I1 0xf436 ++#define FSTV0910_P1_AGC2_INTEGRATOR1 0xf43600ff ++ ++/*P1_AGC2I0*/ ++#define RSTV0910_P1_AGC2I0 0xf437 ++#define FSTV0910_P1_AGC2_INTEGRATOR0 0xf43700ff ++ ++/*P1_CARCFG*/ ++#define RSTV0910_P1_CARCFG 0xf438 ++#define FSTV0910_P1_CFRUPLOW_AUTO 0xf4380080 ++#define FSTV0910_P1_CFRUPLOW_TEST 0xf4380040 ++#define FSTV0910_P1_WIDE_FREQDET 0xf4380020 ++#define FSTV0910_P1_CARHDR_NODIV8 0xf4380010 ++#define FSTV0910_P1_I2C_ROTA 0xf4380008 ++#define FSTV0910_P1_ROTAON 0xf4380004 ++#define FSTV0910_P1_PH_DET_ALGO 0xf4380003 ++ ++/*P1_ACLC*/ ++#define RSTV0910_P1_ACLC 0xf439 ++#define FSTV0910_P1_CARS1_ANOSAUTO 0xf4390040 ++#define FSTV0910_P1_CAR_ALPHA_MANT 0xf4390030 ++#define FSTV0910_P1_CAR_ALPHA_EXP 0xf439000f ++ ++/*P1_BCLC*/ ++#define RSTV0910_P1_BCLC 0xf43a ++#define FSTV0910_P1_CARS1_BNOSAUTO 0xf43a0040 ++#define FSTV0910_P1_CAR_BETA_MANT 0xf43a0030 ++#define FSTV0910_P1_CAR_BETA_EXP 0xf43a000f ++ ++/*P1_CARFREQ*/ ++#define RSTV0910_P1_CARFREQ 0xf43d ++#define FSTV0910_P1_KC_COARSE_EXP 0xf43d00f0 ++#define FSTV0910_P1_BETA_FREQ 0xf43d000f ++ ++/*P1_CARHDR*/ ++#define RSTV0910_P1_CARHDR 0xf43e ++#define FSTV0910_P1_K_FREQ_HDR 0xf43e00ff ++ ++/*P1_LDT*/ ++#define RSTV0910_P1_LDT 0xf43f ++#define FSTV0910_P1_CARLOCK_THRES 0xf43f01ff ++ ++/*P1_LDT2*/ ++#define RSTV0910_P1_LDT2 0xf440 ++#define FSTV0910_P1_CARLOCK_THRES2 0xf44001ff ++ ++/*P1_CFRICFG*/ ++#define RSTV0910_P1_CFRICFG 0xf441 ++#define FSTV0910_P1_CFRINIT_UNVALRNG 0xf4410080 ++#define FSTV0910_P1_CFRINIT_LUNVALCPT 0xf4410040 ++#define FSTV0910_P1_CFRINIT_ABORTDBL 0xf4410020 ++#define FSTV0910_P1_CFRINIT_ABORTPRED 0xf4410010 ++#define FSTV0910_P1_CFRINIT_UNVALSKIP 0xf4410008 ++#define FSTV0910_P1_CFRINIT_CSTINC 0xf4410004 ++#define FSTV0910_P1_CFRIROLL_GARDER 0xf4410002 ++#define FSTV0910_P1_NEG_CFRSTEP 0xf4410001 ++ ++/*P1_CFRUP1*/ ++#define RSTV0910_P1_CFRUP1 0xf442 ++#define FSTV0910_P1_CFR_UP1 0xf44201ff ++ ++/*P1_CFRUP0*/ ++#define RSTV0910_P1_CFRUP0 0xf443 ++#define FSTV0910_P1_CFR_UP0 0xf44300ff ++ ++/*P1_CFRIBASE1*/ ++#define RSTV0910_P1_CFRIBASE1 0xf444 ++#define FSTV0910_P1_CFRINIT_BASE1 0xf44400ff ++ ++/*P1_CFRIBASE0*/ ++#define RSTV0910_P1_CFRIBASE0 0xf445 ++#define FSTV0910_P1_CFRINIT_BASE0 0xf44500ff ++ ++/*P1_CFRLOW1*/ ++#define RSTV0910_P1_CFRLOW1 0xf446 ++#define FSTV0910_P1_CFR_LOW1 0xf44601ff ++ ++/*P1_CFRLOW0*/ ++#define RSTV0910_P1_CFRLOW0 0xf447 ++#define FSTV0910_P1_CFR_LOW0 0xf44700ff ++ ++/*P1_CFRINIT1*/ ++#define RSTV0910_P1_CFRINIT1 0xf448 ++#define FSTV0910_P1_CFR_INIT1 0xf44801ff ++ ++/*P1_CFRINIT0*/ ++#define RSTV0910_P1_CFRINIT0 0xf449 ++#define FSTV0910_P1_CFR_INIT0 0xf44900ff ++ ++/*P1_CFRINC1*/ ++#define RSTV0910_P1_CFRINC1 0xf44a ++#define FSTV0910_P1_MANUAL_CFRINC 0xf44a0080 ++#define FSTV0910_P1_CFR_INC1 0xf44a003f ++ ++/*P1_CFRINC0*/ ++#define RSTV0910_P1_CFRINC0 0xf44b ++#define FSTV0910_P1_CFR_INC0 0xf44b00ff ++ ++/*P1_CFR2*/ ++#define RSTV0910_P1_CFR2 0xf44c ++#define FSTV0910_P1_CAR_FREQ2 0xf44c01ff ++ ++/*P1_CFR1*/ ++#define RSTV0910_P1_CFR1 0xf44d ++#define FSTV0910_P1_CAR_FREQ1 0xf44d00ff ++ ++/*P1_CFR0*/ ++#define RSTV0910_P1_CFR0 0xf44e ++#define FSTV0910_P1_CAR_FREQ0 0xf44e00ff ++ ++/*P1_LDI*/ ++#define RSTV0910_P1_LDI 0xf44f ++#define FSTV0910_P1_LOCK_DET_INTEGR 0xf44f01ff ++ ++/*P1_TMGCFG*/ ++#define RSTV0910_P1_TMGCFG 0xf450 ++#define FSTV0910_P1_TMGLOCK_BETA 0xf45000c0 ++#define FSTV0910_P1_DO_TIMING_CORR 0xf4500010 ++#define FSTV0910_P1_MANUAL_SCAN 0xf450000c ++#define FSTV0910_P1_TMG_MINFREQ 0xf4500003 ++ ++/*P1_RTC*/ ++#define RSTV0910_P1_RTC 0xf451 ++#define FSTV0910_P1_TMGALPHA_EXP 0xf45100f0 ++#define FSTV0910_P1_TMGBETA_EXP 0xf451000f ++ ++/*P1_RTCS2*/ ++#define RSTV0910_P1_RTCS2 0xf452 ++#define FSTV0910_P1_TMGALPHAS2_EXP 0xf45200f0 ++#define FSTV0910_P1_TMGBETAS2_EXP 0xf452000f ++ ++/*P1_TMGTHRISE*/ ++#define RSTV0910_P1_TMGTHRISE 0xf453 ++#define FSTV0910_P1_TMGLOCK_THRISE 0xf45300ff ++ ++/*P1_TMGTHFALL*/ ++#define RSTV0910_P1_TMGTHFALL 0xf454 ++#define FSTV0910_P1_TMGLOCK_THFALL 0xf45400ff ++ ++/*P1_SFRUPRATIO*/ ++#define RSTV0910_P1_SFRUPRATIO 0xf455 ++#define FSTV0910_P1_SFR_UPRATIO 0xf45500ff ++ ++/*P1_SFRLOWRATIO*/ ++#define RSTV0910_P1_SFRLOWRATIO 0xf456 ++#define FSTV0910_P1_SFR_LOWRATIO 0xf45600ff ++ ++/*P1_KTTMG*/ ++#define RSTV0910_P1_KTTMG 0xf457 ++#define FSTV0910_P1_KT_TMG_EXP 0xf45700f0 ++ ++/*P1_KREFTMG*/ ++#define RSTV0910_P1_KREFTMG 0xf458 ++#define FSTV0910_P1_KREF_TMG 0xf45800ff ++ ++/*P1_SFRSTEP*/ ++#define RSTV0910_P1_SFRSTEP 0xf459 ++#define FSTV0910_P1_SFR_SCANSTEP 0xf45900f0 ++#define FSTV0910_P1_SFR_CENTERSTEP 0xf459000f ++ ++/*P1_TMGCFG2*/ ++#define RSTV0910_P1_TMGCFG2 0xf45a ++#define FSTV0910_P1_KREFTMG2_DECMODE 0xf45a00c0 ++#define FSTV0910_P1_DIS_AUTOSAMP 0xf45a0008 ++#define FSTV0910_P1_SCANINIT_QUART 0xf45a0004 ++#define FSTV0910_P1_NOTMG_DVBS1DERAT 0xf45a0002 ++#define FSTV0910_P1_SFRRATIO_FINE 0xf45a0001 ++ ++/*P1_KREFTMG2*/ ++#define RSTV0910_P1_KREFTMG2 0xf45b ++#define FSTV0910_P1_KREF_TMG2 0xf45b00ff ++ ++/*P1_TMGCFG3*/ ++#define RSTV0910_P1_TMGCFG3 0xf45d ++#define FSTV0910_P1_CFRINC_MODE 0xf45d0070 ++#define FSTV0910_P1_CONT_TMGCENTER 0xf45d0008 ++#define FSTV0910_P1_AUTO_GUP 0xf45d0004 ++#define FSTV0910_P1_AUTO_GLOW 0xf45d0002 ++#define FSTV0910_P1_SFRVAL_MINMODE 0xf45d0001 ++ ++/*P1_SFRINIT1*/ ++#define RSTV0910_P1_SFRINIT1 0xf45e ++#define FSTV0910_P1_SFR_INIT1 0xf45e00ff ++ ++/*P1_SFRINIT0*/ ++#define RSTV0910_P1_SFRINIT0 0xf45f ++#define FSTV0910_P1_SFR_INIT0 0xf45f00ff ++ ++/*P1_SFRUP1*/ ++#define RSTV0910_P1_SFRUP1 0xf460 ++#define FSTV0910_P1_SYMB_FREQ_UP1 0xf46000ff ++ ++/*P1_SFRUP0*/ ++#define RSTV0910_P1_SFRUP0 0xf461 ++#define FSTV0910_P1_SYMB_FREQ_UP0 0xf46100ff ++ ++/*P1_SFRLOW1*/ ++#define RSTV0910_P1_SFRLOW1 0xf462 ++#define FSTV0910_P1_SYMB_FREQ_LOW1 0xf46200ff ++ ++/*P1_SFRLOW0*/ ++#define RSTV0910_P1_SFRLOW0 0xf463 ++#define FSTV0910_P1_SYMB_FREQ_LOW0 0xf46300ff ++ ++/*P1_SFR3*/ ++#define RSTV0910_P1_SFR3 0xf464 ++#define FSTV0910_P1_SYMB_FREQ3 0xf46400ff ++ ++/*P1_SFR2*/ ++#define RSTV0910_P1_SFR2 0xf465 ++#define FSTV0910_P1_SYMB_FREQ2 0xf46500ff ++ ++/*P1_SFR1*/ ++#define RSTV0910_P1_SFR1 0xf466 ++#define FSTV0910_P1_SYMB_FREQ1 0xf46600ff ++ ++/*P1_SFR0*/ ++#define RSTV0910_P1_SFR0 0xf467 ++#define FSTV0910_P1_SYMB_FREQ0 0xf46700ff ++ ++/*P1_TMGREG2*/ ++#define RSTV0910_P1_TMGREG2 0xf468 ++#define FSTV0910_P1_TMGREG2 0xf46800ff ++ ++/*P1_TMGREG1*/ ++#define RSTV0910_P1_TMGREG1 0xf469 ++#define FSTV0910_P1_TMGREG1 0xf46900ff ++ ++/*P1_TMGREG0*/ ++#define RSTV0910_P1_TMGREG0 0xf46a ++#define FSTV0910_P1_TMGREG0 0xf46a00ff ++ ++/*P1_TMGLOCK1*/ ++#define RSTV0910_P1_TMGLOCK1 0xf46b ++#define FSTV0910_P1_TMGLOCK_LEVEL1 0xf46b01ff ++ ++/*P1_TMGLOCK0*/ ++#define RSTV0910_P1_TMGLOCK0 0xf46c ++#define FSTV0910_P1_TMGLOCK_LEVEL0 0xf46c00ff ++ ++/*P1_TMGOBS*/ ++#define RSTV0910_P1_TMGOBS 0xf46d ++#define FSTV0910_P1_ROLLOFF_STATUS 0xf46d00c0 ++#define FSTV0910_P1_SCAN_SIGN 0xf46d0030 ++#define FSTV0910_P1_TMG_SCANNING 0xf46d0008 ++#define FSTV0910_P1_CHCENTERING_MODE 0xf46d0004 ++#define FSTV0910_P1_TMG_SCANFAIL 0xf46d0002 ++ ++/*P1_EQUALCFG*/ ++#define RSTV0910_P1_EQUALCFG 0xf46f ++#define FSTV0910_P1_NOTMG_NEGALWAIT 0xf46f0080 ++#define FSTV0910_P1_EQUAL_ON 0xf46f0040 ++#define FSTV0910_P1_SEL_EQUALCOR 0xf46f0038 ++#define FSTV0910_P1_MU_EQUALDFE 0xf46f0007 ++ ++/*P1_EQUAI1*/ ++#define RSTV0910_P1_EQUAI1 0xf470 ++#define FSTV0910_P1_EQUA_ACCI1 0xf47001ff ++ ++/*P1_EQUAQ1*/ ++#define RSTV0910_P1_EQUAQ1 0xf471 ++#define FSTV0910_P1_EQUA_ACCQ1 0xf47101ff ++ ++/*P1_EQUAI2*/ ++#define RSTV0910_P1_EQUAI2 0xf472 ++#define FSTV0910_P1_EQUA_ACCI2 0xf47201ff ++ ++/*P1_EQUAQ2*/ ++#define RSTV0910_P1_EQUAQ2 0xf473 ++#define FSTV0910_P1_EQUA_ACCQ2 0xf47301ff ++ ++/*P1_EQUAI3*/ ++#define RSTV0910_P1_EQUAI3 0xf474 ++#define FSTV0910_P1_EQUA_ACCI3 0xf47401ff ++ ++/*P1_EQUAQ3*/ ++#define RSTV0910_P1_EQUAQ3 0xf475 ++#define FSTV0910_P1_EQUA_ACCQ3 0xf47501ff ++ ++/*P1_EQUAI4*/ ++#define RSTV0910_P1_EQUAI4 0xf476 ++#define FSTV0910_P1_EQUA_ACCI4 0xf47601ff ++ ++/*P1_EQUAQ4*/ ++#define RSTV0910_P1_EQUAQ4 0xf477 ++#define FSTV0910_P1_EQUA_ACCQ4 0xf47701ff ++ ++/*P1_EQUAI5*/ ++#define RSTV0910_P1_EQUAI5 0xf478 ++#define FSTV0910_P1_EQUA_ACCI5 0xf47801ff ++ ++/*P1_EQUAQ5*/ ++#define RSTV0910_P1_EQUAQ5 0xf479 ++#define FSTV0910_P1_EQUA_ACCQ5 0xf47901ff ++ ++/*P1_EQUAI6*/ ++#define RSTV0910_P1_EQUAI6 0xf47a ++#define FSTV0910_P1_EQUA_ACCI6 0xf47a01ff ++ ++/*P1_EQUAQ6*/ ++#define RSTV0910_P1_EQUAQ6 0xf47b ++#define FSTV0910_P1_EQUA_ACCQ6 0xf47b01ff ++ ++/*P1_EQUAI7*/ ++#define RSTV0910_P1_EQUAI7 0xf47c ++#define FSTV0910_P1_EQUA_ACCI7 0xf47c01ff ++ ++/*P1_EQUAQ7*/ ++#define RSTV0910_P1_EQUAQ7 0xf47d ++#define FSTV0910_P1_EQUA_ACCQ7 0xf47d01ff ++ ++/*P1_EQUAI8*/ ++#define RSTV0910_P1_EQUAI8 0xf47e ++#define FSTV0910_P1_EQUA_ACCI8 0xf47e01ff ++ ++/*P1_EQUAQ8*/ ++#define RSTV0910_P1_EQUAQ8 0xf47f ++#define FSTV0910_P1_EQUA_ACCQ8 0xf47f01ff ++ ++/*P1_NNOSDATAT1*/ ++#define RSTV0910_P1_NNOSDATAT1 0xf480 ++#define FSTV0910_P1_NOSDATAT_NORMED1 0xf48000ff ++ ++/*P1_NNOSDATAT0*/ ++#define RSTV0910_P1_NNOSDATAT0 0xf481 ++#define FSTV0910_P1_NOSDATAT_NORMED0 0xf48100ff ++ ++/*P1_NNOSDATA1*/ ++#define RSTV0910_P1_NNOSDATA1 0xf482 ++#define FSTV0910_P1_NOSDATA_NORMED1 0xf48200ff ++ ++/*P1_NNOSDATA0*/ ++#define RSTV0910_P1_NNOSDATA0 0xf483 ++#define FSTV0910_P1_NOSDATA_NORMED0 0xf48300ff ++ ++/*P1_NNOSPLHT1*/ ++#define RSTV0910_P1_NNOSPLHT1 0xf484 ++#define FSTV0910_P1_NOSPLHT_NORMED1 0xf48400ff ++ ++/*P1_NNOSPLHT0*/ ++#define RSTV0910_P1_NNOSPLHT0 0xf485 ++#define FSTV0910_P1_NOSPLHT_NORMED0 0xf48500ff ++ ++/*P1_NNOSPLH1*/ ++#define RSTV0910_P1_NNOSPLH1 0xf486 ++#define FSTV0910_P1_NOSPLH_NORMED1 0xf48600ff ++ ++/*P1_NNOSPLH0*/ ++#define RSTV0910_P1_NNOSPLH0 0xf487 ++#define FSTV0910_P1_NOSPLH_NORMED0 0xf48700ff ++ ++/*P1_NOSDATAT1*/ ++#define RSTV0910_P1_NOSDATAT1 0xf488 ++#define FSTV0910_P1_NOSDATAT_UNNORMED1 0xf48800ff ++ ++/*P1_NOSDATAT0*/ ++#define RSTV0910_P1_NOSDATAT0 0xf489 ++#define FSTV0910_P1_NOSDATAT_UNNORMED0 0xf48900ff ++ ++/*P1_NNOSFRAME1*/ ++#define RSTV0910_P1_NNOSFRAME1 0xf48a ++#define FSTV0910_P1_NOSFRAME_NORMED1 0xf48a00ff ++ ++/*P1_NNOSFRAME0*/ ++#define RSTV0910_P1_NNOSFRAME0 0xf48b ++#define FSTV0910_P1_NOSFRAME_NORMED0 0xf48b00ff ++ ++/*P1_NNOSRAD1*/ ++#define RSTV0910_P1_NNOSRAD1 0xf48c ++#define FSTV0910_P1_NOSRADIAL_NORMED1 0xf48c00ff ++ ++/*P1_NNOSRAD0*/ ++#define RSTV0910_P1_NNOSRAD0 0xf48d ++#define FSTV0910_P1_NOSRADIAL_NORMED0 0xf48d00ff ++ ++/*P1_NOSCFGF1*/ ++#define RSTV0910_P1_NOSCFGF1 0xf48e ++#define FSTV0910_P1_LOWNOISE_MESURE 0xf48e0080 ++#define FSTV0910_P1_NOS_DELFRAME 0xf48e0040 ++#define FSTV0910_P1_NOSDATA_MODE 0xf48e0030 ++#define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e000c ++#define FSTV0910_P1_FRAMESEL_TYPE 0xf48e0003 ++ ++/*P1_CAR2CFG*/ ++#define RSTV0910_P1_CAR2CFG 0xf490 ++#define FSTV0910_P1_DESCRAMB_OFF 0xf4900080 ++#define FSTV0910_P1_EN_PHNOSRAM 0xf4900020 ++#define FSTV0910_P1_STOP_CFR2UPDATE 0xf4900010 ++#define FSTV0910_P1_STOP_NCO2UPDATE 0xf4900008 ++#define FSTV0910_P1_ROTA2ON 0xf4900004 ++#define FSTV0910_P1_PH_DET_ALGO2 0xf4900003 ++ ++/*P1_CFR2CFR1*/ ++#define RSTV0910_P1_CFR2CFR1 0xf491 ++#define FSTV0910_P1_CFR2_S2CONTROL 0xf49100c0 ++#define FSTV0910_P1_EN_S2CAR2CENTER 0xf4910020 ++#define FSTV0910_P1_BCHERRCFR2_MODE 0xf4910018 ++#define FSTV0910_P1_CFR2TOCFR1_BETA 0xf4910007 ++ ++/*P1_CAR3CFG*/ ++#define RSTV0910_P1_CAR3CFG 0xf492 ++#define FSTV0910_P1_CARRIER23_MODE 0xf49200c0 ++#define FSTV0910_P1_CAR3INTERM_DVBS1 0xf4920020 ++#define FSTV0910_P1_ABAMPLIF_MODE 0xf4920018 ++#define FSTV0910_P1_CARRIER3_ALPHA3DL 0xf4920007 ++ ++/*P1_CFR22*/ ++#define RSTV0910_P1_CFR22 0xf493 ++#define FSTV0910_P1_CAR2_FREQ2 0xf49301ff ++ ++/*P1_CFR21*/ ++#define RSTV0910_P1_CFR21 0xf494 ++#define FSTV0910_P1_CAR2_FREQ1 0xf49400ff ++ ++/*P1_CFR20*/ ++#define RSTV0910_P1_CFR20 0xf495 ++#define FSTV0910_P1_CAR2_FREQ0 0xf49500ff ++ ++/*P1_ACLC2S2Q*/ ++#define RSTV0910_P1_ACLC2S2Q 0xf497 ++#define FSTV0910_P1_ENAB_SPSKSYMB 0xf4970080 ++#define FSTV0910_P1_CAR2S2_QANOSAUTO 0xf4970040 ++#define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4970030 ++#define FSTV0910_P1_CAR2S2_Q_ALPH_E 0xf497000f ++ ++/*P1_ACLC2S28*/ ++#define RSTV0910_P1_ACLC2S28 0xf498 ++#define FSTV0910_P1_OLDI3Q_MODE 0xf4980080 ++#define FSTV0910_P1_CAR2S2_8ANOSAUTO 0xf4980040 ++#define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4980030 ++#define FSTV0910_P1_CAR2S2_8_ALPH_E 0xf498000f ++ ++/*P1_ACLC2S216A*/ ++#define RSTV0910_P1_ACLC2S216A 0xf499 ++#define FSTV0910_P1_CAR2S2_16ANOSAUTO 0xf4990040 ++#define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4990030 ++#define FSTV0910_P1_CAR2S2_16A_ALPH_E 0xf499000f ++ ++/*P1_ACLC2S232A*/ ++#define RSTV0910_P1_ACLC2S232A 0xf49a ++#define FSTV0910_P1_CAR2S2_32ANOSUATO 0xf49a0040 ++#define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a0030 ++#define FSTV0910_P1_CAR2S2_32A_ALPH_E 0xf49a000f ++ ++/*P1_BCLC2S2Q*/ ++#define RSTV0910_P1_BCLC2S2Q 0xf49c ++#define FSTV0910_P1_DVBS2S2Q_NIP 0xf49c0080 ++#define FSTV0910_P1_CAR2S2_QBNOSAUTO 0xf49c0040 ++#define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c0030 ++#define FSTV0910_P1_CAR2S2_Q_BETA_E 0xf49c000f ++ ++/*P1_BCLC2S28*/ ++#define RSTV0910_P1_BCLC2S28 0xf49d ++#define FSTV0910_P1_DVBS2S28_NIP 0xf49d0080 ++#define FSTV0910_P1_CAR2S2_8BNOSAUTO 0xf49d0040 ++#define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d0030 ++#define FSTV0910_P1_CAR2S2_8_BETA_E 0xf49d000f ++ ++/*P1_PLROOT2*/ ++#define RSTV0910_P1_PLROOT2 0xf4ac ++#define FSTV0910_P1_PLHAUTO_DISPLH 0xf4ac0040 ++#define FSTV0910_P1_PLHAUTO_FASTMODE 0xf4ac0020 ++#define FSTV0910_P1_PLHAUTO_ENABLE 0xf4ac0010 ++#define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac000c ++#define FSTV0910_P1_PLSCRAMB_ROOT2 0xf4ac0003 ++ ++/*P1_PLROOT1*/ ++#define RSTV0910_P1_PLROOT1 0xf4ad ++#define FSTV0910_P1_PLSCRAMB_ROOT1 0xf4ad00ff ++ ++/*P1_PLROOT0*/ ++#define RSTV0910_P1_PLROOT0 0xf4ae ++#define FSTV0910_P1_PLSCRAMB_ROOT0 0xf4ae00ff ++ ++/*P1_MODCODLST7*/ ++#define RSTV0910_P1_MODCODLST7 0xf4b7 ++#define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b70080 ++#define FSTV0910_P1_MODCODLST_NOSTYPE 0xf4b70040 ++#define FSTV0910_P1_DIS_8PSK_9_10 0xf4b70030 ++#define FSTV0910_P1_DIS_8P_8_9 0xf4b7000f ++ ++/*P1_MODCODLST8*/ ++#define RSTV0910_P1_MODCODLST8 0xf4b8 ++#define FSTV0910_P1_DIS_8P_5_6 0xf4b800f0 ++#define FSTV0910_P1_DIS_8P_3_4 0xf4b8000f ++ ++/*P1_MODCODLST9*/ ++#define RSTV0910_P1_MODCODLST9 0xf4b9 ++#define FSTV0910_P1_DIS_8P_2_3 0xf4b900f0 ++#define FSTV0910_P1_DIS_8P_3_5 0xf4b9000f ++ ++/*P1_MODCODLSTA*/ ++#define RSTV0910_P1_MODCODLSTA 0xf4ba ++#define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba0080 ++#define FSTV0910_P1_NOSFILTER_MODE 0xf4ba0040 ++#define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba0030 ++#define FSTV0910_P1_DIS_QP_8_9 0xf4ba000f ++ ++/*P1_MODCODLSTB*/ ++#define RSTV0910_P1_MODCODLSTB 0xf4bb ++#define FSTV0910_P1_DIS_QP_5_6 0xf4bb00f0 ++#define FSTV0910_P1_DIS_QP_4_5 0xf4bb000f ++ ++/*P1_MODCODLSTC*/ ++#define RSTV0910_P1_MODCODLSTC 0xf4bc ++#define FSTV0910_P1_DIS_QP_3_4 0xf4bc00f0 ++#define FSTV0910_P1_DIS_QP_2_3 0xf4bc000f ++ ++/*P1_MODCODLSTD*/ ++#define RSTV0910_P1_MODCODLSTD 0xf4bd ++#define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd00f0 ++#define FSTV0910_P1_DIS_QPSK_1_2 0xf4bd000f ++ ++/*P1_GAUSSR0*/ ++#define RSTV0910_P1_GAUSSR0 0xf4c0 ++#define FSTV0910_P1_EN_CCIMODE 0xf4c00080 ++#define FSTV0910_P1_R0_GAUSSIEN 0xf4c0007f ++ ++/*P1_CCIR0*/ ++#define RSTV0910_P1_CCIR0 0xf4c1 ++#define FSTV0910_P1_CCIDETECT_PLHONLY 0xf4c10080 ++#define FSTV0910_P1_R0_CCI 0xf4c1007f ++ ++/*P1_CCIQUANT*/ ++#define RSTV0910_P1_CCIQUANT 0xf4c2 ++#define FSTV0910_P1_CCI_BETA 0xf4c200e0 ++#define FSTV0910_P1_CCI_QUANT 0xf4c2001f ++ ++/*P1_CCITHRES*/ ++#define RSTV0910_P1_CCITHRES 0xf4c3 ++#define FSTV0910_P1_CCI_THRESHOLD 0xf4c300ff ++ ++/*P1_CCIACC*/ ++#define RSTV0910_P1_CCIACC 0xf4c4 ++#define FSTV0910_P1_CCI_VALUE 0xf4c400ff ++ ++/*P1_DSTATUS4*/ ++#define RSTV0910_P1_DSTATUS4 0xf4c5 ++#define FSTV0910_P1_RAINFADE_DETECT 0xf4c50080 ++#define FSTV0910_P1_NOTHRES2_FAIL 0xf4c50040 ++#define FSTV0910_P1_NOTHRES1_FAIL 0xf4c50020 ++#define FSTV0910_P1_PILOT_FAILDETECT 0xf4c50010 ++#define FSTV0910_P1_HIER_DETECT 0xf4c50008 ++#define FSTV0910_P1_DMDPROG_ERROR 0xf4c50004 ++#define FSTV0910_P1_CSTENV_DETECT 0xf4c50002 ++#define FSTV0910_P1_DETECTION_TRIAX 0xf4c50001 ++ ++/*P1_DMDRESCFG*/ ++#define RSTV0910_P1_DMDRESCFG 0xf4c6 ++#define FSTV0910_P1_DMDRES_RESET 0xf4c60080 ++#define FSTV0910_P1_DMDRES_NOISESQR 0xf4c60010 ++#define FSTV0910_P1_DMDRES_STRALL 0xf4c60008 ++#define FSTV0910_P1_DMDRES_NEWONLY 0xf4c60004 ++#define FSTV0910_P1_DMDRES_NOSTORE 0xf4c60002 ++#define FSTV0910_P1_DMDRES_AGC2MEM 0xf4c60001 ++ ++/*P1_DMDRESADR*/ ++#define RSTV0910_P1_DMDRESADR 0xf4c7 ++#define FSTV0910_P1_SUSP_PREDCANAL 0xf4c70080 ++#define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c70040 ++#define FSTV0910_P1_DMDRES_MEMFULL 0xf4c70030 ++#define FSTV0910_P1_DMDRES_RESNBR 0xf4c7000f ++ ++/*P1_DMDRESDATA7*/ ++#define RSTV0910_P1_DMDRESDATA7 0xf4c8 ++#define FSTV0910_P1_DMDRES_DATA7 0xf4c800ff ++ ++/*P1_DMDRESDATA6*/ ++#define RSTV0910_P1_DMDRESDATA6 0xf4c9 ++#define FSTV0910_P1_DMDRES_DATA6 0xf4c900ff ++ ++/*P1_DMDRESDATA5*/ ++#define RSTV0910_P1_DMDRESDATA5 0xf4ca ++#define FSTV0910_P1_DMDRES_DATA5 0xf4ca00ff ++ ++/*P1_DMDRESDATA4*/ ++#define RSTV0910_P1_DMDRESDATA4 0xf4cb ++#define FSTV0910_P1_DMDRES_DATA4 0xf4cb00ff ++ ++/*P1_DMDRESDATA3*/ ++#define RSTV0910_P1_DMDRESDATA3 0xf4cc ++#define FSTV0910_P1_DMDRES_DATA3 0xf4cc00ff ++ ++/*P1_DMDRESDATA2*/ ++#define RSTV0910_P1_DMDRESDATA2 0xf4cd ++#define FSTV0910_P1_DMDRES_DATA2 0xf4cd00ff ++ ++/*P1_DMDRESDATA1*/ ++#define RSTV0910_P1_DMDRESDATA1 0xf4ce ++#define FSTV0910_P1_DMDRES_DATA1 0xf4ce00ff ++ ++/*P1_DMDRESDATA0*/ ++#define RSTV0910_P1_DMDRESDATA0 0xf4cf ++#define FSTV0910_P1_DMDRES_DATA0 0xf4cf00ff ++ ++/*P1_FFEI1*/ ++#define RSTV0910_P1_FFEI1 0xf4d0 ++#define FSTV0910_P1_FFE_ACCI1 0xf4d001ff ++ ++/*P1_FFEQ1*/ ++#define RSTV0910_P1_FFEQ1 0xf4d1 ++#define FSTV0910_P1_FFE_ACCQ1 0xf4d101ff ++ ++/*P1_FFEI2*/ ++#define RSTV0910_P1_FFEI2 0xf4d2 ++#define FSTV0910_P1_FFE_ACCI2 0xf4d201ff ++ ++/*P1_FFEQ2*/ ++#define RSTV0910_P1_FFEQ2 0xf4d3 ++#define FSTV0910_P1_FFE_ACCQ2 0xf4d301ff ++ ++/*P1_FFEI3*/ ++#define RSTV0910_P1_FFEI3 0xf4d4 ++#define FSTV0910_P1_FFE_ACCI3 0xf4d401ff ++ ++/*P1_FFEQ3*/ ++#define RSTV0910_P1_FFEQ3 0xf4d5 ++#define FSTV0910_P1_FFE_ACCQ3 0xf4d501ff ++ ++/*P1_FFEI4*/ ++#define RSTV0910_P1_FFEI4 0xf4d6 ++#define FSTV0910_P1_FFE_ACCI4 0xf4d601ff ++ ++/*P1_FFEQ4*/ ++#define RSTV0910_P1_FFEQ4 0xf4d7 ++#define FSTV0910_P1_FFE_ACCQ4 0xf4d701ff ++ ++/*P1_FFECFG*/ ++#define RSTV0910_P1_FFECFG 0xf4d8 ++#define FSTV0910_P1_EQUALFFE_ON 0xf4d80040 ++#define FSTV0910_P1_EQUAL_USEDSYMB 0xf4d80030 ++#define FSTV0910_P1_MU_EQUALFFE 0xf4d80007 ++ ++/*P1_TNRCFG2*/ ++#define RSTV0910_P1_TNRCFG2 0xf4e1 ++#define FSTV0910_P1_TUN_IQSWAP 0xf4e10080 ++#define FSTV0910_P1_STB6110_STEP2MHZ 0xf4e10040 ++#define FSTV0910_P1_STB6120_DBLI2C 0xf4e10020 ++#define FSTV0910_P1_TUNER_WIDEBAND 0xf4e10010 ++#define FSTV0910_P1_TUNER_OBSPAGE 0xf4e10008 ++#define FSTV0910_P1_DIS_BWCALC 0xf4e10004 ++#define FSTV0910_P1_SHORT_WAITSTATES 0xf4e10002 ++#define FSTV0910_P1_DIS_2BWAGC1 0xf4e10001 ++ ++/*P1_SMAPCOEF7*/ ++#define RSTV0910_P1_SMAPCOEF7 0xf500 ++#define FSTV0910_P1_DIS_QSCALE 0xf5000080 ++#define FSTV0910_P1_SMAPCOEF_Q_LLR12 0xf500017f ++ ++/*P1_SMAPCOEF6*/ ++#define RSTV0910_P1_SMAPCOEF6 0xf501 ++#define FSTV0910_P1_DIS_AGC2SCALE 0xf5010080 ++#define FSTV0910_P1_DIS_16IQMULT 0xf5010040 ++#define FSTV0910_P1_OLD_16APSK47 0xf5010020 ++#define FSTV0910_P1_OLD_16APSK12 0xf5010010 ++#define FSTV0910_P1_DIS_NEWSCALE 0xf5010008 ++#define FSTV0910_P1_ADJ_8PSKLLR1 0xf5010004 ++#define FSTV0910_P1_OLD_8PSKLLR1 0xf5010002 ++#define FSTV0910_P1_DIS_AB8PSK 0xf5010001 ++ ++/*P1_SMAPCOEF5*/ ++#define RSTV0910_P1_SMAPCOEF5 0xf502 ++#define FSTV0910_P1_DIS_8SCALE 0xf5020080 ++#define FSTV0910_P1_SMAPCOEF_8P_LLR23 0xf502017f ++ ++/*P1_NOSTHRES1*/ ++#define RSTV0910_P1_NOSTHRES1 0xf509 ++#define FSTV0910_P1_NOS_THRESHOLD1 0xf50900ff ++ ++/*P1_NOSTHRES2*/ ++#define RSTV0910_P1_NOSTHRES2 0xf50a ++#define FSTV0910_P1_NOS_THRESHOLD2 0xf50a00ff ++ ++/*P1_NOSDIFF1*/ ++#define RSTV0910_P1_NOSDIFF1 0xf50b ++#define FSTV0910_P1_NOSTHRES1_DIFF 0xf50b00ff ++ ++/*P1_RAINFADE*/ ++#define RSTV0910_P1_RAINFADE 0xf50c ++#define FSTV0910_P1_NOSTHRES_DATAT 0xf50c0080 ++#define FSTV0910_P1_RAINFADE_CNLIMIT 0xf50c0070 ++#define FSTV0910_P1_RAINFADE_TIMEOUT 0xf50c0007 ++ ++/*P1_NOSRAMCFG*/ ++#define RSTV0910_P1_NOSRAMCFG 0xf50d ++#define FSTV0910_P1_NOSRAM_DVBS2DATA 0xf50d0080 ++#define FSTV0910_P1_NOSRAM_QUADRAT 0xf50d0040 ++#define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d0030 ++#define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d0008 ++#define FSTV0910_P1_NOSRAM_LGNCNR1 0xf50d0007 ++ ++/*P1_NOSRAMPOS*/ ++#define RSTV0910_P1_NOSRAMPOS 0xf50e ++#define FSTV0910_P1_NOSRAM_LGNCNR0 0xf50e00f0 ++#define FSTV0910_P1_NOSRAM_VALIDE 0xf50e0004 ++#define FSTV0910_P1_NOSRAM_CNRVAL1 0xf50e0003 ++ ++/*P1_NOSRAMVAL*/ ++#define RSTV0910_P1_NOSRAMVAL 0xf50f ++#define FSTV0910_P1_NOSRAM_CNRVAL0 0xf50f00ff ++ ++/*P1_DMDPLHSTAT*/ ++#define RSTV0910_P1_DMDPLHSTAT 0xf520 ++#define FSTV0910_P1_PLH_STATISTIC 0xf52000ff ++ ++/*P1_LOCKTIME3*/ ++#define RSTV0910_P1_LOCKTIME3 0xf522 ++#define FSTV0910_P1_DEMOD_LOCKTIME3 0xf52200ff ++ ++/*P1_LOCKTIME2*/ ++#define RSTV0910_P1_LOCKTIME2 0xf523 ++#define FSTV0910_P1_DEMOD_LOCKTIME2 0xf52300ff ++ ++/*P1_LOCKTIME1*/ ++#define RSTV0910_P1_LOCKTIME1 0xf524 ++#define FSTV0910_P1_DEMOD_LOCKTIME1 0xf52400ff ++ ++/*P1_LOCKTIME0*/ ++#define RSTV0910_P1_LOCKTIME0 0xf525 ++#define FSTV0910_P1_DEMOD_LOCKTIME0 0xf52500ff ++ ++/*P1_VITSCALE*/ ++#define RSTV0910_P1_VITSCALE 0xf532 ++#define FSTV0910_P1_NVTH_NOSRANGE 0xf5320080 ++#define FSTV0910_P1_VERROR_MAXMODE 0xf5320040 ++#define FSTV0910_P1_KDIV_MODE 0xf5320030 ++#define FSTV0910_P1_NSLOWSN_LOCKED 0xf5320008 ++#define FSTV0910_P1_DELOCK_PRFLOSS 0xf5320004 ++#define FSTV0910_P1_DIS_RSFLOCK 0xf5320002 ++ ++/*P1_FECM*/ ++#define RSTV0910_P1_FECM 0xf533 ++#define FSTV0910_P1_DSS_DVB 0xf5330080 ++#define FSTV0910_P1_DEMOD_BYPASS 0xf5330040 ++#define FSTV0910_P1_CMP_SLOWMODE 0xf5330020 ++#define FSTV0910_P1_DSS_SRCH 0xf5330010 ++#define FSTV0910_P1_DIFF_MODEVIT 0xf5330004 ++#define FSTV0910_P1_SYNCVIT 0xf5330002 ++#define FSTV0910_P1_IQINV 0xf5330001 ++ ++/*P1_VTH12*/ ++#define RSTV0910_P1_VTH12 0xf534 ++#define FSTV0910_P1_VTH12 0xf53400ff ++ ++/*P1_VTH23*/ ++#define RSTV0910_P1_VTH23 0xf535 ++#define FSTV0910_P1_VTH23 0xf53500ff ++ ++/*P1_VTH34*/ ++#define RSTV0910_P1_VTH34 0xf536 ++#define FSTV0910_P1_VTH34 0xf53600ff ++ ++/*P1_VTH56*/ ++#define RSTV0910_P1_VTH56 0xf537 ++#define FSTV0910_P1_VTH56 0xf53700ff ++ ++/*P1_VTH67*/ ++#define RSTV0910_P1_VTH67 0xf538 ++#define FSTV0910_P1_VTH67 0xf53800ff ++ ++/*P1_VTH78*/ ++#define RSTV0910_P1_VTH78 0xf539 ++#define FSTV0910_P1_VTH78 0xf53900ff ++ ++/*P1_VITCURPUN*/ ++#define RSTV0910_P1_VITCURPUN 0xf53a ++#define FSTV0910_P1_CYCLESLIP_VIT 0xf53a0080 ++#define FSTV0910_P1_VIT_ROTA180 0xf53a0040 ++#define FSTV0910_P1_VIT_ROTA90 0xf53a0020 ++#define FSTV0910_P1_VIT_CURPUN 0xf53a001f ++ ++/*P1_VERROR*/ ++#define RSTV0910_P1_VERROR 0xf53b ++#define FSTV0910_P1_REGERR_VIT 0xf53b00ff ++ ++/*P1_PRVIT*/ ++#define RSTV0910_P1_PRVIT 0xf53c ++#define FSTV0910_P1_DIS_VTHLOCK 0xf53c0040 ++#define FSTV0910_P1_E7_8VIT 0xf53c0020 ++#define FSTV0910_P1_E6_7VIT 0xf53c0010 ++#define FSTV0910_P1_E5_6VIT 0xf53c0008 ++#define FSTV0910_P1_E3_4VIT 0xf53c0004 ++#define FSTV0910_P1_E2_3VIT 0xf53c0002 ++#define FSTV0910_P1_E1_2VIT 0xf53c0001 ++ ++/*P1_VAVSRVIT*/ ++#define RSTV0910_P1_VAVSRVIT 0xf53d ++#define FSTV0910_P1_AMVIT 0xf53d0080 ++#define FSTV0910_P1_FROZENVIT 0xf53d0040 ++#define FSTV0910_P1_SNVIT 0xf53d0030 ++#define FSTV0910_P1_TOVVIT 0xf53d000c ++#define FSTV0910_P1_HYPVIT 0xf53d0003 ++ ++/*P1_VSTATUSVIT*/ ++#define RSTV0910_P1_VSTATUSVIT 0xf53e ++#define FSTV0910_P1_VITERBI_ON 0xf53e0080 ++#define FSTV0910_P1_END_LOOPVIT 0xf53e0040 ++#define FSTV0910_P1_VITERBI_DEPRF 0xf53e0020 ++#define FSTV0910_P1_PRFVIT 0xf53e0010 ++#define FSTV0910_P1_LOCKEDVIT 0xf53e0008 ++#define FSTV0910_P1_VITERBI_DELOCK 0xf53e0004 ++#define FSTV0910_P1_VIT_DEMODSEL 0xf53e0002 ++#define FSTV0910_P1_VITERBI_COMPOUT 0xf53e0001 ++ ++/*P1_VTHINUSE*/ ++#define RSTV0910_P1_VTHINUSE 0xf53f ++#define FSTV0910_P1_VIT_INUSE 0xf53f00ff ++ ++/*P1_KDIV12*/ ++#define RSTV0910_P1_KDIV12 0xf540 ++#define FSTV0910_P1_KDIV12_MANUAL 0xf5400080 ++#define FSTV0910_P1_K_DIVIDER_12 0xf540007f ++ ++/*P1_KDIV23*/ ++#define RSTV0910_P1_KDIV23 0xf541 ++#define FSTV0910_P1_KDIV23_MANUAL 0xf5410080 ++#define FSTV0910_P1_K_DIVIDER_23 0xf541007f ++ ++/*P1_KDIV34*/ ++#define RSTV0910_P1_KDIV34 0xf542 ++#define FSTV0910_P1_KDIV34_MANUAL 0xf5420080 ++#define FSTV0910_P1_K_DIVIDER_34 0xf542007f ++ ++/*P1_KDIV56*/ ++#define RSTV0910_P1_KDIV56 0xf543 ++#define FSTV0910_P1_KDIV56_MANUAL 0xf5430080 ++#define FSTV0910_P1_K_DIVIDER_56 0xf543007f ++ ++/*P1_KDIV67*/ ++#define RSTV0910_P1_KDIV67 0xf544 ++#define FSTV0910_P1_KDIV67_MANUAL 0xf5440080 ++#define FSTV0910_P1_K_DIVIDER_67 0xf544007f ++ ++/*P1_KDIV78*/ ++#define RSTV0910_P1_KDIV78 0xf545 ++#define FSTV0910_P1_KDIV78_MANUAL 0xf5450080 ++#define FSTV0910_P1_K_DIVIDER_78 0xf545007f ++ ++/*P1_PDELCTRL0*/ ++#define RSTV0910_P1_PDELCTRL0 0xf54f ++#define FSTV0910_P1_ISIOBS_MODE 0xf54f0030 ++#define FSTV0910_P1_PDELDIS_BITWISE 0xf54f0004 ++ ++/*P1_PDELCTRL1*/ ++#define RSTV0910_P1_PDELCTRL1 0xf550 ++#define FSTV0910_P1_INV_MISMASK 0xf5500080 ++#define FSTV0910_P1_FORCE_ACCEPTED 0xf5500040 ++#define FSTV0910_P1_FILTER_EN 0xf5500020 ++#define FSTV0910_P1_FORCE_PKTDELINUSE 0xf5500010 ++#define FSTV0910_P1_HYSTEN 0xf5500008 ++#define FSTV0910_P1_HYSTSWRST 0xf5500004 ++#define FSTV0910_P1_EN_MIS00 0xf5500002 ++#define FSTV0910_P1_ALGOSWRST 0xf5500001 ++ ++/*P1_PDELCTRL2*/ ++#define RSTV0910_P1_PDELCTRL2 0xf551 ++#define FSTV0910_P1_FORCE_CONTINUOUS 0xf5510080 ++#define FSTV0910_P1_RESET_UPKO_COUNT 0xf5510040 ++#define FSTV0910_P1_USER_PKTDELIN_NB 0xf5510020 ++#define FSTV0910_P1_DATA_UNBBSCRAMBLED 0xf5510008 ++#define FSTV0910_P1_FORCE_LONGPKT 0xf5510004 ++#define FSTV0910_P1_FRAME_MODE 0xf5510002 ++ ++/*P1_HYSTTHRESH*/ ++#define RSTV0910_P1_HYSTTHRESH 0xf554 ++#define FSTV0910_P1_DELIN_LOCKTHRES 0xf55400f0 ++#define FSTV0910_P1_DELIN_UNLOCKTHRES 0xf554000f ++ ++/*P1_ISIENTRY*/ ++#define RSTV0910_P1_ISIENTRY 0xf55e ++#define FSTV0910_P1_ISI_ENTRY 0xf55e00ff ++ ++/*P1_ISIBITENA*/ ++#define RSTV0910_P1_ISIBITENA 0xf55f ++#define FSTV0910_P1_ISI_BIT_EN 0xf55f00ff ++ ++/*P1_MATSTR1*/ ++#define RSTV0910_P1_MATSTR1 0xf560 ++#define FSTV0910_P1_MATYPE_CURRENT1 0xf56000ff ++ ++/*P1_MATSTR0*/ ++#define RSTV0910_P1_MATSTR0 0xf561 ++#define FSTV0910_P1_MATYPE_CURRENT0 0xf56100ff ++ ++/*P1_UPLSTR1*/ ++#define RSTV0910_P1_UPLSTR1 0xf562 ++#define FSTV0910_P1_UPL_CURRENT1 0xf56200ff ++ ++/*P1_UPLSTR0*/ ++#define RSTV0910_P1_UPLSTR0 0xf563 ++#define FSTV0910_P1_UPL_CURRENT0 0xf56300ff ++ ++/*P1_DFLSTR1*/ ++#define RSTV0910_P1_DFLSTR1 0xf564 ++#define FSTV0910_P1_DFL_CURRENT1 0xf56400ff ++ ++/*P1_DFLSTR0*/ ++#define RSTV0910_P1_DFLSTR0 0xf565 ++#define FSTV0910_P1_DFL_CURRENT0 0xf56500ff ++ ++/*P1_SYNCSTR*/ ++#define RSTV0910_P1_SYNCSTR 0xf566 ++#define FSTV0910_P1_SYNC_CURRENT 0xf56600ff ++ ++/*P1_SYNCDSTR1*/ ++#define RSTV0910_P1_SYNCDSTR1 0xf567 ++#define FSTV0910_P1_SYNCD_CURRENT1 0xf56700ff ++ ++/*P1_SYNCDSTR0*/ ++#define RSTV0910_P1_SYNCDSTR0 0xf568 ++#define FSTV0910_P1_SYNCD_CURRENT0 0xf56800ff ++ ++/*P1_PDELSTATUS1*/ ++#define RSTV0910_P1_PDELSTATUS1 0xf569 ++#define FSTV0910_P1_PKTDELIN_DELOCK 0xf5690080 ++#define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5690040 ++#define FSTV0910_P1_CONTINUOUS_STREAM 0xf5690020 ++#define FSTV0910_P1_UNACCEPTED_STREAM 0xf5690010 ++#define FSTV0910_P1_BCH_ERROR_FLAG 0xf5690008 ++#define FSTV0910_P1_BBHCRCKO 0xf5690004 ++#define FSTV0910_P1_PKTDELIN_LOCK 0xf5690002 ++#define FSTV0910_P1_FIRST_LOCK 0xf5690001 ++ ++/*P1_PDELSTATUS2*/ ++#define RSTV0910_P1_PDELSTATUS2 0xf56a ++#define FSTV0910_P1_PKTDEL_DEMODSEL 0xf56a0080 ++#define FSTV0910_P1_FRAME_MODCOD 0xf56a007c ++#define FSTV0910_P1_FRAME_TYPE 0xf56a0003 ++ ++/*P1_BBFCRCKO1*/ ++#define RSTV0910_P1_BBFCRCKO1 0xf56b ++#define FSTV0910_P1_BBHCRC_KOCNT1 0xf56b00ff ++ ++/*P1_BBFCRCKO0*/ ++#define RSTV0910_P1_BBFCRCKO0 0xf56c ++#define FSTV0910_P1_BBHCRC_KOCNT0 0xf56c00ff ++ ++/*P1_UPCRCKO1*/ ++#define RSTV0910_P1_UPCRCKO1 0xf56d ++#define FSTV0910_P1_PKTCRC_KOCNT1 0xf56d00ff ++ ++/*P1_UPCRCKO0*/ ++#define RSTV0910_P1_UPCRCKO0 0xf56e ++#define FSTV0910_P1_PKTCRC_KOCNT0 0xf56e00ff ++ ++/*P1_PDELCTRL3*/ ++#define RSTV0910_P1_PDELCTRL3 0xf56f ++#define FSTV0910_P1_PKTDEL_CONTFAIL 0xf56f0080 ++#define FSTV0910_P1_PKTDEL_ENLONGPKT 0xf56f0040 ++#define FSTV0910_P1_NOFIFO_BCHERR 0xf56f0020 ++#define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f0010 ++#define FSTV0910_P1_SATURATE_BBPKTKO 0xf56f0004 ++#define FSTV0910_P1_PKTDEL_BCHERRCONT 0xf56f0002 ++#define FSTV0910_P1_ETHERNET_DISFCS 0xf56f0001 ++ ++/*P1_TSSTATEM*/ ++#define RSTV0910_P1_TSSTATEM 0xf570 ++#define FSTV0910_P1_TSDIL_ON 0xf5700080 ++#define FSTV0910_P1_TSSKIPRS_ON 0xf5700040 ++#define FSTV0910_P1_TSRS_ON 0xf5700020 ++#define FSTV0910_P1_TSDESCRAMB_ON 0xf5700010 ++#define FSTV0910_P1_TSFRAME_MODE 0xf5700008 ++#define FSTV0910_P1_TS_DISABLE 0xf5700004 ++#define FSTV0910_P1_TSACM_MODE 0xf5700002 ++#define FSTV0910_P1_TSOUT_NOSYNC 0xf5700001 ++ ++/*P1_TSCFGH*/ ++#define RSTV0910_P1_TSCFGH 0xf572 ++#define FSTV0910_P1_TSFIFO_DVBCI 0xf5720080 ++#define FSTV0910_P1_TSFIFO_SERIAL 0xf5720040 ++#define FSTV0910_P1_TSFIFO_TEIUPDATE 0xf5720020 ++#define FSTV0910_P1_TSFIFO_DUTY50 0xf5720010 ++#define FSTV0910_P1_TSFIFO_HSGNLOUT 0xf5720008 ++#define FSTV0910_P1_TSFIFO_ERRMODE 0xf5720006 ++#define FSTV0910_P1_RST_HWARE 0xf5720001 ++ ++/*P1_TSCFGM*/ ++#define RSTV0910_P1_TSCFGM 0xf573 ++#define FSTV0910_P1_TSFIFO_MANSPEED 0xf57300c0 ++#define FSTV0910_P1_TSFIFO_PERMDATA 0xf5730020 ++#define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5730010 ++#define FSTV0910_P1_NPD_SPECDVBS2 0xf5730004 ++#define FSTV0910_P1_TSFIFO_DPUNACTIVE 0xf5730002 ++#define FSTV0910_P1_TSFIFO_INVDATA 0xf5730001 ++ ++/*P1_TSCFGL*/ ++#define RSTV0910_P1_TSCFGL 0xf574 ++#define FSTV0910_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 ++#define FSTV0910_P1_BCHERROR_MODE 0xf5740030 ++#define FSTV0910_P1_TSFIFO_NSGNL2DATA 0xf5740008 ++#define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5740004 ++#define FSTV0910_P1_TSFIFO_BITSPEED 0xf5740003 ++ ++/*P1_TSINSDELH*/ ++#define RSTV0910_P1_TSINSDELH 0xf576 ++#define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5760080 ++#define FSTV0910_P1_TSDEL_XXHEADER 0xf5760040 ++#define FSTV0910_P1_TSDEL_BBHEADER 0xf5760020 ++#define FSTV0910_P1_TSDEL_DATAFIELD 0xf5760010 ++#define FSTV0910_P1_TSINSDEL_ISCR 0xf5760008 ++#define FSTV0910_P1_TSINSDEL_NPD 0xf5760004 ++#define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5760002 ++#define FSTV0910_P1_TSINSDEL_CRC8 0xf5760001 ++ ++/*P1_TSDIVN*/ ++#define RSTV0910_P1_TSDIVN 0xf579 ++#define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57900c0 ++#define FSTV0910_P1_BYTE_OVERSAMPLING 0xf5790038 ++#define FSTV0910_P1_TSFIFO_RISEOK 0xf5790007 ++ ++/*P1_TSCFG4*/ ++#define RSTV0910_P1_TSCFG4 0xf57a ++#define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 ++#define FSTV0910_P1_TSFIFO_HIERSEL 0xf57a0020 ++#define FSTV0910_P1_TSFIFO_SPECTOKEN 0xf57a0010 ++#define FSTV0910_P1_TSFIFO_MAXMODE 0xf57a0008 ++#define FSTV0910_P1_TSFIFO_FRFORCEPKT 0xf57a0004 ++#define FSTV0910_P1_EXT_FECSPYIN 0xf57a0002 ++#define FSTV0910_P1_TSFIFO_DELSPEEDUP 0xf57a0001 ++ ++/*P1_TSSPEED*/ ++#define RSTV0910_P1_TSSPEED 0xf580 ++#define FSTV0910_P1_TSFIFO_OUTSPEED 0xf58000ff ++ ++/*P1_TSSTATUS*/ ++#define RSTV0910_P1_TSSTATUS 0xf581 ++#define FSTV0910_P1_TSFIFO_LINEOK 0xf5810080 ++#define FSTV0910_P1_TSFIFO_ERROR 0xf5810040 ++#define FSTV0910_P1_TSFIFO_DATA7 0xf5810020 ++#define FSTV0910_P1_TSFIFO_NOSYNC 0xf5810010 ++#define FSTV0910_P1_ISCR_INITIALIZED 0xf5810008 ++#define FSTV0910_P1_TSREGUL_ERROR 0xf5810004 ++#define FSTV0910_P1_SOFFIFO_UNREGUL 0xf5810002 ++#define FSTV0910_P1_DIL_READY 0xf5810001 ++ ++/*P1_TSSTATUS2*/ ++#define RSTV0910_P1_TSSTATUS2 0xf582 ++#define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5820080 ++#define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5820040 ++#define FSTV0910_P1_DILXX_RESET 0xf5820020 ++#define FSTV0910_P1_TSSPEED_IMPOSSIBLE 0xf5820010 ++#define FSTV0910_P1_TSFIFO_LINENOK 0xf5820008 ++#define FSTV0910_P1_TSFIFO_MUXSTREAM 0xf5820004 ++#define FSTV0910_P1_SCRAMBDETECT 0xf5820002 ++#define FSTV0910_P1_ULDTV67_FALSELOCK 0xf5820001 ++ ++/*P1_TSBITRATE1*/ ++#define RSTV0910_P1_TSBITRATE1 0xf583 ++#define FSTV0910_P1_TSFIFO_BITRATE1 0xf58300ff ++ ++/*P1_TSBITRATE0*/ ++#define RSTV0910_P1_TSBITRATE0 0xf584 ++#define FSTV0910_P1_TSFIFO_BITRATE0 0xf58400ff ++ ++/*P1_ERRCTRL1*/ ++#define RSTV0910_P1_ERRCTRL1 0xf598 ++#define FSTV0910_P1_ERR_SOURCE1 0xf59800f0 ++#define FSTV0910_P1_NUM_EVENT1 0xf5980007 ++ ++/*P1_ERRCNT12*/ ++#define RSTV0910_P1_ERRCNT12 0xf599 ++#define FSTV0910_P1_ERRCNT1_OLDVALUE 0xf5990080 ++#define FSTV0910_P1_ERR_CNT12 0xf599007f ++ ++/*P1_ERRCNT11*/ ++#define RSTV0910_P1_ERRCNT11 0xf59a ++#define FSTV0910_P1_ERR_CNT11 0xf59a00ff ++ ++/*P1_ERRCNT10*/ ++#define RSTV0910_P1_ERRCNT10 0xf59b ++#define FSTV0910_P1_ERR_CNT10 0xf59b00ff ++ ++/*P1_ERRCTRL2*/ ++#define RSTV0910_P1_ERRCTRL2 0xf59c ++#define FSTV0910_P1_ERR_SOURCE2 0xf59c00f0 ++#define FSTV0910_P1_NUM_EVENT2 0xf59c0007 ++ ++/*P1_ERRCNT22*/ ++#define RSTV0910_P1_ERRCNT22 0xf59d ++#define FSTV0910_P1_ERRCNT2_OLDVALUE 0xf59d0080 ++#define FSTV0910_P1_ERR_CNT22 0xf59d007f ++ ++/*P1_ERRCNT21*/ ++#define RSTV0910_P1_ERRCNT21 0xf59e ++#define FSTV0910_P1_ERR_CNT21 0xf59e00ff ++ ++/*P1_ERRCNT20*/ ++#define RSTV0910_P1_ERRCNT20 0xf59f ++#define FSTV0910_P1_ERR_CNT20 0xf59f00ff ++ ++/*P1_FECSPY*/ ++#define RSTV0910_P1_FECSPY 0xf5a0 ++#define FSTV0910_P1_SPY_ENABLE 0xf5a00080 ++#define FSTV0910_P1_NO_SYNCBYTE 0xf5a00040 ++#define FSTV0910_P1_SERIAL_MODE 0xf5a00020 ++#define FSTV0910_P1_UNUSUAL_PACKET 0xf5a00010 ++#define FSTV0910_P1_BERMETER_DATAMODE 0xf5a0000c ++#define FSTV0910_P1_BERMETER_LMODE 0xf5a00002 ++#define FSTV0910_P1_BERMETER_RESET 0xf5a00001 ++ ++/*P1_FSPYCFG*/ ++#define RSTV0910_P1_FSPYCFG 0xf5a1 ++#define FSTV0910_P1_FECSPY_INPUT 0xf5a100c0 ++#define FSTV0910_P1_RST_ON_ERROR 0xf5a10020 ++#define FSTV0910_P1_ONE_SHOT 0xf5a10010 ++#define FSTV0910_P1_I2C_MODE 0xf5a1000c ++#define FSTV0910_P1_SPY_HYSTERESIS 0xf5a10003 ++ ++/*P1_FSPYDATA*/ ++#define RSTV0910_P1_FSPYDATA 0xf5a2 ++#define FSTV0910_P1_SPY_STUFFING 0xf5a20080 ++#define FSTV0910_P1_NOERROR_PKTJITTER 0xf5a20040 ++#define FSTV0910_P1_SPY_CNULLPKT 0xf5a20020 ++#define FSTV0910_P1_SPY_OUTDATA_MODE 0xf5a2001f ++ ++/*P1_FSPYOUT*/ ++#define RSTV0910_P1_FSPYOUT 0xf5a3 ++#define FSTV0910_P1_FSPY_DIRECT 0xf5a30080 ++#define FSTV0910_P1_SPY_OUTDATA_BUS 0xf5a30038 ++#define FSTV0910_P1_STUFF_MODE 0xf5a30007 ++ ++/*P1_FSTATUS*/ ++#define RSTV0910_P1_FSTATUS 0xf5a4 ++#define FSTV0910_P1_SPY_ENDSIM 0xf5a40080 ++#define FSTV0910_P1_VALID_SIM 0xf5a40040 ++#define FSTV0910_P1_FOUND_SIGNAL 0xf5a40020 ++#define FSTV0910_P1_DSS_SYNCBYTE 0xf5a40010 ++#define FSTV0910_P1_RESULT_STATE 0xf5a4000f ++ ++/*P1_FBERCPT4*/ ++#define RSTV0910_P1_FBERCPT4 0xf5a8 ++#define FSTV0910_P1_FBERMETER_CPT4 0xf5a800ff ++ ++/*P1_FBERCPT3*/ ++#define RSTV0910_P1_FBERCPT3 0xf5a9 ++#define FSTV0910_P1_FBERMETER_CPT3 0xf5a900ff ++ ++/*P1_FBERCPT2*/ ++#define RSTV0910_P1_FBERCPT2 0xf5aa ++#define FSTV0910_P1_FBERMETER_CPT2 0xf5aa00ff ++ ++/*P1_FBERCPT1*/ ++#define RSTV0910_P1_FBERCPT1 0xf5ab ++#define FSTV0910_P1_FBERMETER_CPT1 0xf5ab00ff ++ ++/*P1_FBERCPT0*/ ++#define RSTV0910_P1_FBERCPT0 0xf5ac ++#define FSTV0910_P1_FBERMETER_CPT0 0xf5ac00ff ++ ++/*P1_FBERERR2*/ ++#define RSTV0910_P1_FBERERR2 0xf5ad ++#define FSTV0910_P1_FBERMETER_ERR2 0xf5ad00ff ++ ++/*P1_FBERERR1*/ ++#define RSTV0910_P1_FBERERR1 0xf5ae ++#define FSTV0910_P1_FBERMETER_ERR1 0xf5ae00ff ++ ++/*P1_FBERERR0*/ ++#define RSTV0910_P1_FBERERR0 0xf5af ++#define FSTV0910_P1_FBERMETER_ERR0 0xf5af00ff ++ ++/*P1_FSPYBER*/ ++#define RSTV0910_P1_FSPYBER 0xf5b2 ++#define FSTV0910_P1_FSPYOBS_XORREAD 0xf5b20040 ++#define FSTV0910_P1_FSPYBER_OBSMODE 0xf5b20020 ++#define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b20010 ++#define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b20008 ++#define FSTV0910_P1_FSPYBER_CTIME 0xf5b20007 ++ ++/*P1_SFERROR*/ ++#define RSTV0910_P1_SFERROR 0xf5c1 ++#define FSTV0910_P1_SFEC_REGERR_VIT 0xf5c100ff ++ ++/*P1_SFECSTATUS*/ ++#define RSTV0910_P1_SFECSTATUS 0xf5c3 ++#define FSTV0910_P1_SFEC_ON 0xf5c30080 ++#define FSTV0910_P1_SFEC_OFF 0xf5c30040 ++#define FSTV0910_P1_LOCKEDSFEC 0xf5c30008 ++#define FSTV0910_P1_SFEC_DELOCK 0xf5c30004 ++#define FSTV0910_P1_SFEC_DEMODSEL 0xf5c30002 ++#define FSTV0910_P1_SFEC_OVFON 0xf5c30001 ++ ++/*P1_SFKDIV12*/ ++#define RSTV0910_P1_SFKDIV12 0xf5c4 ++#define FSTV0910_P1_SFECKDIV12_MAN 0xf5c40080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_12 0xf5c4007f ++ ++/*P1_SFKDIV23*/ ++#define RSTV0910_P1_SFKDIV23 0xf5c5 ++#define FSTV0910_P1_SFECKDIV23_MAN 0xf5c50080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_23 0xf5c5007f ++ ++/*P1_SFKDIV34*/ ++#define RSTV0910_P1_SFKDIV34 0xf5c6 ++#define FSTV0910_P1_SFECKDIV34_MAN 0xf5c60080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_34 0xf5c6007f ++ ++/*P1_SFKDIV56*/ ++#define RSTV0910_P1_SFKDIV56 0xf5c7 ++#define FSTV0910_P1_SFECKDIV56_MAN 0xf5c70080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_56 0xf5c7007f ++ ++/*P1_SFKDIV67*/ ++#define RSTV0910_P1_SFKDIV67 0xf5c8 ++#define FSTV0910_P1_SFECKDIV67_MAN 0xf5c80080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_67 0xf5c8007f ++ ++/*P1_SFKDIV78*/ ++#define RSTV0910_P1_SFKDIV78 0xf5c9 ++#define FSTV0910_P1_SFECKDIV78_MAN 0xf5c90080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_78 0xf5c9007f ++ ++/*P1_SFSTATUS*/ ++#define RSTV0910_P1_SFSTATUS 0xf5cc ++#define FSTV0910_P1_SFEC_LINEOK 0xf5cc0080 ++#define FSTV0910_P1_SFEC_ERROR 0xf5cc0040 ++#define FSTV0910_P1_SFEC_DATA7 0xf5cc0020 ++#define FSTV0910_P1_SFEC_PKTDNBRFAIL 0xf5cc0010 ++#define FSTV0910_P1_TSSFEC_DEMODSEL 0xf5cc0008 ++#define FSTV0910_P1_SFEC_NOSYNC 0xf5cc0004 ++#define FSTV0910_P1_SFEC_UNREGULA 0xf5cc0002 ++#define FSTV0910_P1_SFEC_READY 0xf5cc0001 ++ ++/*P1_SFDLYSET2*/ ++#define RSTV0910_P1_SFDLYSET2 0xf5d0 ++#define FSTV0910_P1_SFEC_OFFSET 0xf5d000c0 ++#define FSTV0910_P1_RST_SFEC 0xf5d00008 ++#define FSTV0910_P1_DILDLINE_ERROR 0xf5d00004 ++#define FSTV0910_P1_SFEC_DISABLE 0xf5d00002 ++#define FSTV0910_P1_SFEC_UNREGUL 0xf5d00001 ++ ++/*P1_SFERRCTRL*/ ++#define RSTV0910_P1_SFERRCTRL 0xf5d8 ++#define FSTV0910_P1_SFEC_ERR_SOURCE 0xf5d800f0 ++#define FSTV0910_P1_SFEC_NUM_EVENT 0xf5d80007 ++ ++/*P1_SFERRCNT2*/ ++#define RSTV0910_P1_SFERRCNT2 0xf5d9 ++#define FSTV0910_P1_SFERRC_OLDVALUE 0xf5d90080 ++#define FSTV0910_P1_SFEC_ERR_CNT2 0xf5d9007f ++ ++/*P1_SFERRCNT1*/ ++#define RSTV0910_P1_SFERRCNT1 0xf5da ++#define FSTV0910_P1_SFEC_ERR_CNT1 0xf5da00ff ++ ++/*P1_SFERRCNT0*/ ++#define RSTV0910_P1_SFERRCNT0 0xf5db ++#define FSTV0910_P1_SFEC_ERR_CNT0 0xf5db00ff ++ ++/*TSGENERAL*/ ++#define RSTV0910_TSGENERAL 0xf630 ++#define FSTV0910_EN_LGNERROR 0xf6300080 ++#define FSTV0910_TSFIFO_DISTS2PAR 0xf6300040 ++#define FSTV0910_MUXSTREAM_COMPMOSE 0xf6300030 ++#define FSTV0910_MUXSTREAM_OUTMODE 0xf6300008 ++#define FSTV0910_TSFIFO_PERMPARAL 0xf6300006 ++#define FSTV0910_RST_REEDSOLO 0xf6300001 ++ ++/*P1_DISIRQCFG*/ ++#define RSTV0910_P1_DISIRQCFG 0xf700 ++#define FSTV0910_P1_ENRXEND 0xf7000040 ++#define FSTV0910_P1_ENRXFIFO8B 0xf7000020 ++#define FSTV0910_P1_ENTRFINISH 0xf7000010 ++#define FSTV0910_P1_ENTIMEOUT 0xf7000008 ++#define FSTV0910_P1_ENTXEND 0xf7000004 ++#define FSTV0910_P1_ENTXFIFO64B 0xf7000002 ++#define FSTV0910_P1_ENGAPBURST 0xf7000001 ++ ++/*P1_DISIRQSTAT*/ ++#define RSTV0910_P1_DISIRQSTAT 0xf701 ++#define FSTV0910_P1_IRQRXEND 0xf7010040 ++#define FSTV0910_P1_IRQRXFIFO8B 0xf7010020 ++#define FSTV0910_P1_IRQTRFINISH 0xf7010010 ++#define FSTV0910_P1_IRQTIMEOUT 0xf7010008 ++#define FSTV0910_P1_IRQTXEND 0xf7010004 ++#define FSTV0910_P1_IRQTXFIFO64B 0xf7010002 ++#define FSTV0910_P1_IRQGAPBURST 0xf7010001 ++ ++/*P1_DISTXCFG*/ ++#define RSTV0910_P1_DISTXCFG 0xf702 ++#define FSTV0910_P1_DISTX_RESET 0xf7020080 ++#define FSTV0910_P1_TIM_OFF 0xf7020040 ++#define FSTV0910_P1_TIM_CMD 0xf7020030 ++#define FSTV0910_P1_ENVELOP 0xf7020008 ++#define FSTV0910_P1_DIS_PRECHARGE 0xf7020004 ++#define FSTV0910_P1_DISEQC_MODE 0xf7020003 ++ ++/*P1_DISTXSTATUS*/ ++#define RSTV0910_P1_DISTXSTATUS 0xf703 ++#define FSTV0910_P1_TX_FIFO_FULL 0xf7030040 ++#define FSTV0910_P1_TX_IDLE 0xf7030020 ++#define FSTV0910_P1_GAP_BURST 0xf7030010 ++#define FSTV0910_P1_TX_FIFO64B 0xf7030008 ++#define FSTV0910_P1_TX_END 0xf7030004 ++#define FSTV0910_P1_TR_TIMEOUT 0xf7030002 ++#define FSTV0910_P1_TR_FINISH 0xf7030001 ++ ++/*P1_DISTXBYTES*/ ++#define RSTV0910_P1_DISTXBYTES 0xf704 ++#define FSTV0910_P1_TXFIFO_BYTES 0xf70400ff ++ ++/*P1_DISTXFIFO*/ ++#define RSTV0910_P1_DISTXFIFO 0xf705 ++#define FSTV0910_P1_DISEQC_TX_FIFO 0xf70500ff ++ ++/*P1_DISTXF22*/ ++#define RSTV0910_P1_DISTXF22 0xf706 ++#define FSTV0910_P1_F22TX 0xf70600ff ++ ++/*P1_DISTIMEOCFG*/ ++#define RSTV0910_P1_DISTIMEOCFG 0xf708 ++#define FSTV0910_P1_RXCHOICE 0xf7080006 ++#define FSTV0910_P1_TIMEOUT_OFF 0xf7080001 ++ ++/*P1_DISTIMEOUT*/ ++#define RSTV0910_P1_DISTIMEOUT 0xf709 ++#define FSTV0910_P1_TIMEOUT_COUNT 0xf70900ff ++ ++/*P1_DISRXCFG*/ ++#define RSTV0910_P1_DISRXCFG 0xf70a ++#define FSTV0910_P1_DISRX_RESET 0xf70a0080 ++#define FSTV0910_P1_EXTENVELOP 0xf70a0040 ++#define FSTV0910_P1_PINSELECT 0xf70a0038 ++#define FSTV0910_P1_IGNORE_SHORT22K 0xf70a0004 ++#define FSTV0910_P1_SIGNED_RXIN 0xf70a0002 ++#define FSTV0910_P1_DISRX_ON 0xf70a0001 ++ ++/*P1_DISRXSTAT1*/ ++#define RSTV0910_P1_DISRXSTAT1 0xf70b ++#define FSTV0910_P1_RXEND 0xf70b0080 ++#define FSTV0910_P1_RXACTIVE 0xf70b0040 ++#define FSTV0910_P1_RXDETECT 0xf70b0020 ++#define FSTV0910_P1_CONTTONE 0xf70b0010 ++#define FSTV0910_P1_8BFIFOREADY 0xf70b0008 ++#define FSTV0910_P1_FIFOEMPTY 0xf70b0004 ++ ++/*P1_DISRXSTAT0*/ ++#define RSTV0910_P1_DISRXSTAT0 0xf70c ++#define FSTV0910_P1_RXFAIL 0xf70c0080 ++#define FSTV0910_P1_FIFOPFAIL 0xf70c0040 ++#define FSTV0910_P1_RXNONBYTE 0xf70c0020 ++#define FSTV0910_P1_FIFOOVF 0xf70c0010 ++#define FSTV0910_P1_SHORT22K 0xf70c0008 ++#define FSTV0910_P1_RXMSGLOST 0xf70c0004 ++ ++/*P1_DISRXBYTES*/ ++#define RSTV0910_P1_DISRXBYTES 0xf70d ++#define FSTV0910_P1_RXFIFO_BYTES 0xf70d001f ++ ++/*P1_DISRXPARITY1*/ ++#define RSTV0910_P1_DISRXPARITY1 0xf70e ++#define FSTV0910_P1_DISRX_PARITY1 0xf70e00ff ++ ++/*P1_DISRXPARITY0*/ ++#define RSTV0910_P1_DISRXPARITY0 0xf70f ++#define FSTV0910_P1_DISRX_PARITY0 0xf70f00ff ++ ++/*P1_DISRXFIFO*/ ++#define RSTV0910_P1_DISRXFIFO 0xf710 ++#define FSTV0910_P1_DISEQC_RX_FIFO 0xf71000ff ++ ++/*P1_DISRXDC1*/ ++#define RSTV0910_P1_DISRXDC1 0xf711 ++#define FSTV0910_P1_DC_VALUE1 0xf7110103 ++ ++/*P1_DISRXDC0*/ ++#define RSTV0910_P1_DISRXDC0 0xf712 ++#define FSTV0910_P1_DC_VALUE0 0xf71200ff ++ ++/*P1_DISRXF221*/ ++#define RSTV0910_P1_DISRXF221 0xf714 ++#define FSTV0910_P1_F22RX1 0xf714000f ++ ++/*P1_DISRXF220*/ ++#define RSTV0910_P1_DISRXF220 0xf715 ++#define FSTV0910_P1_F22RX0 0xf71500ff ++ ++/*P1_DISRXF100*/ ++#define RSTV0910_P1_DISRXF100 0xf716 ++#define FSTV0910_P1_F100RX 0xf71600ff ++ ++/*P1_DISRXSHORT22K*/ ++#define RSTV0910_P1_DISRXSHORT22K 0xf71c ++#define FSTV0910_P1_SHORT22K_LENGTH 0xf71c001f ++ ++/*P1_ACRPRESC*/ ++#define RSTV0910_P1_ACRPRESC 0xf71e ++#define FSTV0910_P1_ACR_CODFRDY 0xf71e0008 ++#define FSTV0910_P1_ACR_PRESC 0xf71e0007 ++ ++/*P1_ACRDIV*/ ++#define RSTV0910_P1_ACRDIV 0xf71f ++#define FSTV0910_P1_ACR_DIV 0xf71f00ff ++ ++/*P2_DISIRQCFG*/ ++#define RSTV0910_P2_DISIRQCFG 0xf740 ++#define FSTV0910_P2_ENRXEND 0xf7400040 ++#define FSTV0910_P2_ENRXFIFO8B 0xf7400020 ++#define FSTV0910_P2_ENTRFINISH 0xf7400010 ++#define FSTV0910_P2_ENTIMEOUT 0xf7400008 ++#define FSTV0910_P2_ENTXEND 0xf7400004 ++#define FSTV0910_P2_ENTXFIFO64B 0xf7400002 ++#define FSTV0910_P2_ENGAPBURST 0xf7400001 ++ ++/*P2_DISIRQSTAT*/ ++#define RSTV0910_P2_DISIRQSTAT 0xf741 ++#define FSTV0910_P2_IRQRXEND 0xf7410040 ++#define FSTV0910_P2_IRQRXFIFO8B 0xf7410020 ++#define FSTV0910_P2_IRQTRFINISH 0xf7410010 ++#define FSTV0910_P2_IRQTIMEOUT 0xf7410008 ++#define FSTV0910_P2_IRQTXEND 0xf7410004 ++#define FSTV0910_P2_IRQTXFIFO64B 0xf7410002 ++#define FSTV0910_P2_IRQGAPBURST 0xf7410001 ++ ++/*P2_DISTXCFG*/ ++#define RSTV0910_P2_DISTXCFG 0xf742 ++#define FSTV0910_P2_DISTX_RESET 0xf7420080 ++#define FSTV0910_P2_TIM_OFF 0xf7420040 ++#define FSTV0910_P2_TIM_CMD 0xf7420030 ++#define FSTV0910_P2_ENVELOP 0xf7420008 ++#define FSTV0910_P2_DIS_PRECHARGE 0xf7420004 ++#define FSTV0910_P2_DISEQC_MODE 0xf7420003 ++ ++/*P2_DISTXSTATUS*/ ++#define RSTV0910_P2_DISTXSTATUS 0xf743 ++#define FSTV0910_P2_TX_FIFO_FULL 0xf7430040 ++#define FSTV0910_P2_TX_IDLE 0xf7430020 ++#define FSTV0910_P2_GAP_BURST 0xf7430010 ++#define FSTV0910_P2_TX_FIFO64B 0xf7430008 ++#define FSTV0910_P2_TX_END 0xf7430004 ++#define FSTV0910_P2_TR_TIMEOUT 0xf7430002 ++#define FSTV0910_P2_TR_FINISH 0xf7430001 ++ ++/*P2_DISTXBYTES*/ ++#define RSTV0910_P2_DISTXBYTES 0xf744 ++#define FSTV0910_P2_TXFIFO_BYTES 0xf74400ff ++ ++/*P2_DISTXFIFO*/ ++#define RSTV0910_P2_DISTXFIFO 0xf745 ++#define FSTV0910_P2_DISEQC_TX_FIFO 0xf74500ff ++ ++/*P2_DISTXF22*/ ++#define RSTV0910_P2_DISTXF22 0xf746 ++#define FSTV0910_P2_F22TX 0xf74600ff ++ ++/*P2_DISTIMEOCFG*/ ++#define RSTV0910_P2_DISTIMEOCFG 0xf748 ++#define FSTV0910_P2_RXCHOICE 0xf7480006 ++#define FSTV0910_P2_TIMEOUT_OFF 0xf7480001 ++ ++/*P2_DISTIMEOUT*/ ++#define RSTV0910_P2_DISTIMEOUT 0xf749 ++#define FSTV0910_P2_TIMEOUT_COUNT 0xf74900ff ++ ++/*P2_DISRXCFG*/ ++#define RSTV0910_P2_DISRXCFG 0xf74a ++#define FSTV0910_P2_DISRX_RESET 0xf74a0080 ++#define FSTV0910_P2_EXTENVELOP 0xf74a0040 ++#define FSTV0910_P2_PINSELECT 0xf74a0038 ++#define FSTV0910_P2_IGNORE_SHORT22K 0xf74a0004 ++#define FSTV0910_P2_SIGNED_RXIN 0xf74a0002 ++#define FSTV0910_P2_DISRX_ON 0xf74a0001 ++ ++/*P2_DISRXSTAT1*/ ++#define RSTV0910_P2_DISRXSTAT1 0xf74b ++#define FSTV0910_P2_RXEND 0xf74b0080 ++#define FSTV0910_P2_RXACTIVE 0xf74b0040 ++#define FSTV0910_P2_RXDETECT 0xf74b0020 ++#define FSTV0910_P2_CONTTONE 0xf74b0010 ++#define FSTV0910_P2_8BFIFOREADY 0xf74b0008 ++#define FSTV0910_P2_FIFOEMPTY 0xf74b0004 ++ ++/*P2_DISRXSTAT0*/ ++#define RSTV0910_P2_DISRXSTAT0 0xf74c ++#define FSTV0910_P2_RXFAIL 0xf74c0080 ++#define FSTV0910_P2_FIFOPFAIL 0xf74c0040 ++#define FSTV0910_P2_RXNONBYTE 0xf74c0020 ++#define FSTV0910_P2_FIFOOVF 0xf74c0010 ++#define FSTV0910_P2_SHORT22K 0xf74c0008 ++#define FSTV0910_P2_RXMSGLOST 0xf74c0004 ++ ++/*P2_DISRXBYTES*/ ++#define RSTV0910_P2_DISRXBYTES 0xf74d ++#define FSTV0910_P2_RXFIFO_BYTES 0xf74d001f ++ ++/*P2_DISRXPARITY1*/ ++#define RSTV0910_P2_DISRXPARITY1 0xf74e ++#define FSTV0910_P2_DISRX_PARITY1 0xf74e00ff ++ ++/*P2_DISRXPARITY0*/ ++#define RSTV0910_P2_DISRXPARITY0 0xf74f ++#define FSTV0910_P2_DISRX_PARITY0 0xf74f00ff ++ ++/*P2_DISRXFIFO*/ ++#define RSTV0910_P2_DISRXFIFO 0xf750 ++#define FSTV0910_P2_DISEQC_RX_FIFO 0xf75000ff ++ ++/*P2_DISRXDC1*/ ++#define RSTV0910_P2_DISRXDC1 0xf751 ++#define FSTV0910_P2_DC_VALUE1 0xf7510103 ++ ++/*P2_DISRXDC0*/ ++#define RSTV0910_P2_DISRXDC0 0xf752 ++#define FSTV0910_P2_DC_VALUE0 0xf75200ff ++ ++/*P2_DISRXF221*/ ++#define RSTV0910_P2_DISRXF221 0xf754 ++#define FSTV0910_P2_F22RX1 0xf754000f ++ ++/*P2_DISRXF220*/ ++#define RSTV0910_P2_DISRXF220 0xf755 ++#define FSTV0910_P2_F22RX0 0xf75500ff ++ ++/*P2_DISRXF100*/ ++#define RSTV0910_P2_DISRXF100 0xf756 ++#define FSTV0910_P2_F100RX 0xf75600ff ++ ++/*P2_DISRXSHORT22K*/ ++#define RSTV0910_P2_DISRXSHORT22K 0xf75c ++#define FSTV0910_P2_SHORT22K_LENGTH 0xf75c001f ++ ++/*P2_ACRPRESC*/ ++#define RSTV0910_P2_ACRPRESC 0xf75e ++#define FSTV0910_P2_ACR_CODFRDY 0xf75e0008 ++#define FSTV0910_P2_ACR_PRESC 0xf75e0007 ++ ++/*P2_ACRDIV*/ ++#define RSTV0910_P2_ACRDIV 0xf75f ++#define FSTV0910_P2_ACR_DIV 0xf75f00ff ++ ++/*P1_NBITER_NF4*/ ++#define RSTV0910_P1_NBITER_NF4 0xfa03 ++#define FSTV0910_P1_NBITER_NF_QPSK_1_2 0xfa0300ff ++ ++/*P1_NBITER_NF5*/ ++#define RSTV0910_P1_NBITER_NF5 0xfa04 ++#define FSTV0910_P1_NBITER_NF_QPSK_3_5 0xfa0400ff ++ ++/*P1_NBITER_NF6*/ ++#define RSTV0910_P1_NBITER_NF6 0xfa05 ++#define FSTV0910_P1_NBITER_NF_QPSK_2_3 0xfa0500ff ++ ++/*P1_NBITER_NF7*/ ++#define RSTV0910_P1_NBITER_NF7 0xfa06 ++#define FSTV0910_P1_NBITER_NF_QPSK_3_4 0xfa0600ff ++ ++/*P1_NBITER_NF8*/ ++#define RSTV0910_P1_NBITER_NF8 0xfa07 ++#define FSTV0910_P1_NBITER_NF_QPSK_4_5 0xfa0700ff ++ ++/*P1_NBITER_NF9*/ ++#define RSTV0910_P1_NBITER_NF9 0xfa08 ++#define FSTV0910_P1_NBITER_NF_QPSK_5_6 0xfa0800ff ++ ++/*P1_NBITER_NF10*/ ++#define RSTV0910_P1_NBITER_NF10 0xfa09 ++#define FSTV0910_P1_NBITER_NF_QPSK_8_9 0xfa0900ff ++ ++/*P1_NBITER_NF11*/ ++#define RSTV0910_P1_NBITER_NF11 0xfa0a ++#define FSTV0910_P1_NBITER_NF_QPSK_9_10 0xfa0a00ff ++ ++/*P1_NBITER_NF12*/ ++#define RSTV0910_P1_NBITER_NF12 0xfa0b ++#define FSTV0910_P1_NBITER_NF_8PSK_3_5 0xfa0b00ff ++ ++/*P1_NBITER_NF13*/ ++#define RSTV0910_P1_NBITER_NF13 0xfa0c ++#define FSTV0910_P1_NBITER_NF_8PSK_2_3 0xfa0c00ff ++ ++/*P1_NBITER_NF14*/ ++#define RSTV0910_P1_NBITER_NF14 0xfa0d ++#define FSTV0910_P1_NBITER_NF_8PSK_3_4 0xfa0d00ff ++ ++/*P1_NBITER_NF15*/ ++#define RSTV0910_P1_NBITER_NF15 0xfa0e ++#define FSTV0910_P1_NBITER_NF_8PSK_5_6 0xfa0e00ff ++ ++/*P1_NBITER_NF16*/ ++#define RSTV0910_P1_NBITER_NF16 0xfa0f ++#define FSTV0910_P1_NBITER_NF_8PSK_8_9 0xfa0f00ff ++ ++/*P1_NBITER_NF17*/ ++#define RSTV0910_P1_NBITER_NF17 0xfa10 ++#define FSTV0910_P1_NBITER_NF_8PSK_9_10 0xfa1000ff ++ ++/*GAINLLR_NF4*/ ++#define RSTV0910_GAINLLR_NF4 0xfa43 ++#define FSTV0910_GAINLLR_NF_QPSK_1_2 0xfa43007f ++ ++/*GAINLLR_NF5*/ ++#define RSTV0910_GAINLLR_NF5 0xfa44 ++#define FSTV0910_GAINLLR_NF_QPSK_3_5 0xfa44007f ++ ++/*GAINLLR_NF6*/ ++#define RSTV0910_GAINLLR_NF6 0xfa45 ++#define FSTV0910_GAINLLR_NF_QPSK_2_3 0xfa45007f ++ ++/*GAINLLR_NF7*/ ++#define RSTV0910_GAINLLR_NF7 0xfa46 ++#define FSTV0910_GAINLLR_NF_QPSK_3_4 0xfa46007f ++ ++/*GAINLLR_NF8*/ ++#define RSTV0910_GAINLLR_NF8 0xfa47 ++#define FSTV0910_GAINLLR_NF_QPSK_4_5 0xfa47007f ++ ++/*GAINLLR_NF9*/ ++#define RSTV0910_GAINLLR_NF9 0xfa48 ++#define FSTV0910_GAINLLR_NF_QPSK_5_6 0xfa48007f ++ ++/*GAINLLR_NF10*/ ++#define RSTV0910_GAINLLR_NF10 0xfa49 ++#define FSTV0910_GAINLLR_NF_QPSK_8_9 0xfa49007f ++ ++/*GAINLLR_NF11*/ ++#define RSTV0910_GAINLLR_NF11 0xfa4a ++#define FSTV0910_GAINLLR_NF_QPSK_9_10 0xfa4a007f ++ ++/*GAINLLR_NF12*/ ++#define RSTV0910_GAINLLR_NF12 0xfa4b ++#define FSTV0910_GAINLLR_NF_8PSK_3_5 0xfa4b007f ++ ++/*GAINLLR_NF13*/ ++#define RSTV0910_GAINLLR_NF13 0xfa4c ++#define FSTV0910_GAINLLR_NF_8PSK_2_3 0xfa4c007f ++ ++/*GAINLLR_NF14*/ ++#define RSTV0910_GAINLLR_NF14 0xfa4d ++#define FSTV0910_GAINLLR_NF_8PSK_3_4 0xfa4d007f ++ ++/*GAINLLR_NF15*/ ++#define RSTV0910_GAINLLR_NF15 0xfa4e ++#define FSTV0910_GAINLLR_NF_8PSK_5_6 0xfa4e007f ++ ++/*GAINLLR_NF16*/ ++#define RSTV0910_GAINLLR_NF16 0xfa4f ++#define FSTV0910_GAINLLR_NF_8PSK_8_9 0xfa4f007f ++ ++/*GAINLLR_NF17*/ ++#define RSTV0910_GAINLLR_NF17 0xfa50 ++#define FSTV0910_GAINLLR_NF_8PSK_9_10 0xfa50007f ++ ++/*CFGEXT*/ ++#define RSTV0910_CFGEXT 0xfa80 ++#define FSTV0910_BYPFIFOBCH 0xfa800080 ++#define FSTV0910_BYPBCH 0xfa800040 ++#define FSTV0910_BYPLDPC 0xfa800020 ++#define FSTV0910_BYPFIFOBCHF 0xfa800010 ++#define FSTV0910_INVLLRSIGN 0xfa800008 ++#define FSTV0910_SHORTMULT 0xfa800004 ++#define FSTV0910_ENSTOPDEC 0xfa800002 ++ ++/*GENCFG*/ ++#define RSTV0910_GENCFG 0xfa86 ++#define FSTV0910_LEG_ITER 0xfa860040 ++#define FSTV0910_NOSHFRD1 0xfa860020 ++#define FSTV0910_BROADCAST 0xfa860010 ++#define FSTV0910_NOSHFRD2 0xfa860008 ++#define FSTV0910_BCHERRFLAG 0xfa860004 ++#define FSTV0910_CROSSINPUT 0xfa860002 ++#define FSTV0910_DDEMOD 0xfa860001 ++ ++/*LDPCERR1*/ ++#define RSTV0910_LDPCERR1 0xfa96 ++#define FSTV0910_LDPC_ERRORS1 0xfa9600ff ++ ++/*LDPCERR0*/ ++#define RSTV0910_LDPCERR0 0xfa97 ++#define FSTV0910_LDPC_ERRORS0 0xfa9700ff ++ ++/*BCHERR*/ ++#define RSTV0910_BCHERR 0xfa98 ++#define FSTV0910_ERRORFLAG 0xfa980010 ++#define FSTV0910_BCH_ERRORS_COUNTER 0xfa98000f ++ ++/*P1_MAXEXTRAITER*/ ++#define RSTV0910_P1_MAXEXTRAITER 0xfab1 ++#define FSTV0910_P1_MAX_EXTRA_ITER 0xfab100ff ++ ++/*P2_MAXEXTRAITER*/ ++#define RSTV0910_P2_MAXEXTRAITER 0xfab6 ++#define FSTV0910_P2_MAX_EXTRA_ITER 0xfab600ff ++ ++/*P1_STATUSITER*/ ++#define RSTV0910_P1_STATUSITER 0xfabc ++#define FSTV0910_P1_STATUS_ITER 0xfabc00ff ++ ++/*P1_STATUSMAXITER*/ ++#define RSTV0910_P1_STATUSMAXITER 0xfabd ++#define FSTV0910_P1_STATUS_MAX_ITER 0xfabd00ff ++ ++/*P2_STATUSITER*/ ++#define RSTV0910_P2_STATUSITER 0xfabe ++#define FSTV0910_P2_STATUS_ITER 0xfabe00ff ++ ++/*P2_STATUSMAXITER*/ ++#define RSTV0910_P2_STATUSMAXITER 0xfabf ++#define FSTV0910_P2_STATUS_MAX_ITER 0xfabf00ff ++ ++/*P2_NBITER_NF4*/ ++#define RSTV0910_P2_NBITER_NF4 0xfac3 ++#define FSTV0910_P2_NBITER_NF_QPSK_1_2 0xfac300ff ++ ++/*P2_NBITER_NF5*/ ++#define RSTV0910_P2_NBITER_NF5 0xfac4 ++#define FSTV0910_P2_NBITER_NF_QPSK_3_5 0xfac400ff ++ ++/*P2_NBITER_NF6*/ ++#define RSTV0910_P2_NBITER_NF6 0xfac5 ++#define FSTV0910_P2_NBITER_NF_QPSK_2_3 0xfac500ff ++ ++/*P2_NBITER_NF7*/ ++#define RSTV0910_P2_NBITER_NF7 0xfac6 ++#define FSTV0910_P2_NBITER_NF_QPSK_3_4 0xfac600ff ++ ++/*P2_NBITER_NF8*/ ++#define RSTV0910_P2_NBITER_NF8 0xfac7 ++#define FSTV0910_P2_NBITER_NF_QPSK_4_5 0xfac700ff ++ ++/*P2_NBITER_NF9*/ ++#define RSTV0910_P2_NBITER_NF9 0xfac8 ++#define FSTV0910_P2_NBITER_NF_QPSK_5_6 0xfac800ff ++ ++/*P2_NBITER_NF10*/ ++#define RSTV0910_P2_NBITER_NF10 0xfac9 ++#define FSTV0910_P2_NBITER_NF_QPSK_8_9 0xfac900ff ++ ++/*P2_NBITER_NF11*/ ++#define RSTV0910_P2_NBITER_NF11 0xfaca ++#define FSTV0910_P2_NBITER_NF_QPSK_9_10 0xfaca00ff ++ ++/*P2_NBITER_NF12*/ ++#define RSTV0910_P2_NBITER_NF12 0xfacb ++#define FSTV0910_P2_NBITER_NF_8PSK_3_5 0xfacb00ff ++ ++/*P2_NBITER_NF13*/ ++#define RSTV0910_P2_NBITER_NF13 0xfacc ++#define FSTV0910_P2_NBITER_NF_8PSK_2_3 0xfacc00ff ++ ++/*P2_NBITER_NF14*/ ++#define RSTV0910_P2_NBITER_NF14 0xfacd ++#define FSTV0910_P2_NBITER_NF_8PSK_3_4 0xfacd00ff ++ ++/*P2_NBITER_NF15*/ ++#define RSTV0910_P2_NBITER_NF15 0xface ++#define FSTV0910_P2_NBITER_NF_8PSK_5_6 0xface00ff ++ ++/*P2_NBITER_NF16*/ ++#define RSTV0910_P2_NBITER_NF16 0xfacf ++#define FSTV0910_P2_NBITER_NF_8PSK_8_9 0xfacf00ff ++ ++/*P2_NBITER_NF17*/ ++#define RSTV0910_P2_NBITER_NF17 0xfad0 ++#define FSTV0910_P2_NBITER_NF_8PSK_9_10 0xfad000ff ++ ++/*TSTRES0*/ ++#define RSTV0910_TSTRES0 0xff11 ++#define FSTV0910_FRESFEC 0xff110080 ++#define FSTV0910_FRESTS 0xff110040 ++#define FSTV0910_FRESVIT1 0xff110020 ++#define FSTV0910_FRESVIT2 0xff110010 ++#define FSTV0910_FRESSYM1 0xff110008 ++#define FSTV0910_FRESSYM2 0xff110004 ++#define FSTV0910_FRESMAS 0xff110002 ++#define FSTV0910_FRESINT 0xff110001 ++ ++/*P2_TCTL4*/ ++#define RSTV0910_P2_TCTL4 0xff28 ++#define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2800c0 ++#define FSTV0910_P2_TSTINV_PHERR 0xff280020 ++#define FSTV0910_P2_EN_PLHCALC 0xff280010 ++#define FSTV0910_P2_TETA3L_RSTTETA3D 0xff280008 ++#define FSTV0910_P2_DIS_FORCEBETA2 0xff280004 ++#define FSTV0910_P2_CAR3_NOTRACEBACK 0xff280002 ++#define FSTV0910_P2_CAR3_NOFORWARD 0xff280001 ++ ++/*P1_TCTL4*/ ++#define RSTV0910_P1_TCTL4 0xff48 ++#define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4800c0 ++#define FSTV0910_P1_TSTINV_PHERR 0xff480020 ++#define FSTV0910_P1_EN_PLHCALC 0xff480010 ++#define FSTV0910_P1_TETA3L_RSTTETA3D 0xff480008 ++#define FSTV0910_P1_DIS_FORCEBETA2 0xff480004 ++#define FSTV0910_P1_CAR3_NOTRACEBACK 0xff480002 ++#define FSTV0910_P1_CAR3_NOFORWARD 0xff480001 ++ ++#define STV0910_NBREGS 735 ++#define STV0910_NBFIELDS 1776 +diff --git a/drivers/media/dvb-frontends/stv6111.c b/drivers/media/dvb-frontends/stv6111.c +new file mode 100644 +index 0000000..fbd6365 +--- /dev/null ++++ b/drivers/media/dvb-frontends/stv6111.c +@@ -0,0 +1,450 @@ ++/* ++ * Driver for the ST STV6111 tuner ++ * ++ * Copyright (C) 2014 Digital Devices GmbH ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 only, as published by the Free Software Foundation. ++ * ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA ++ * 02110-1301, USA ++ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dvb_frontend.h" ++ ++static inline u32 MulDiv32(u32 a, u32 b, u32 c) ++{ ++ u64 tmp64; ++ ++ tmp64 = (u64)a * (u64)b; ++ do_div(tmp64, c); ++ ++ return (u32) tmp64; ++} ++ ++ ++struct stv { ++ struct i2c_adapter *i2c; ++ u8 adr; ++ ++ u8 reg[11]; ++ u32 ref_freq; ++}; ++ ++static int i2c_read(struct i2c_adapter *adap, ++ u8 adr, u8 *msg, int len, u8 *answ, int alen) ++{ ++ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, ++ .buf = msg, .len = len}, ++ { .addr = adr, .flags = I2C_M_RD, ++ .buf = answ, .len = alen } }; ++ if (i2c_transfer(adap, msgs, 2) != 2) { ++ pr_err("stv6111: i2c_read error\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) ++{ ++ struct i2c_msg msg = {.addr = adr, .flags = 0, ++ .buf = data, .len = len}; ++ ++ if (i2c_transfer(adap, &msg, 1) != 1) { ++ pr_err("stv6111: i2c_write error\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++static int write_regs(struct stv *state, int reg, int len) ++{ ++ u8 d[12]; ++ ++ memcpy(&d[1], &state->reg[reg], len); ++ d[0] = reg; ++ return i2c_write(state->i2c, state->adr, d, len + 1); ++} ++ ++#if 0 ++static int write_reg(struct stv *state, u8 reg, u8 val) ++{ ++ u8 d[2] = {reg, val}; ++ ++ return i2c_write(state->i2c, state->adr, d, 2); ++} ++#endif ++ ++static int read_reg(struct stv *state, u8 reg, u8 *val) ++{ ++ return i2c_read(state->i2c, state->adr, ®, 1, val, 1); ++} ++ ++static int read_regs(struct stv *state, u8 reg, u8 *val, int len) ++{ ++ return i2c_read(state->i2c, state->adr, ®, 1, val, len); ++} ++ ++static void dump_regs(struct stv *state) ++{ ++ u8 d[11], *c = &state->reg[0]; ++ ++ read_regs(state, 0, d, 11); ++ pr_info("stv6111_regs = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", ++ d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], ++ d[8], d[9], d[10]); ++ pr_info("reg[] = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", ++ c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7], ++ c[8], c[9], c[10]); ++} ++ ++static int wait_for_call_done(struct stv *state, u8 mask) ++{ ++ int status = 0; ++ u32 LockRetryCount = 10; ++ ++ while (LockRetryCount > 0) { ++ u8 Status; ++ ++ status = read_reg(state, 9, &Status); ++ if (status < 0) ++ return status; ++ ++ if ((Status & mask) == 0) ++ break; ++ usleep_range(4000, 6000); ++ LockRetryCount -= 1; ++ ++ status = -1; ++ } ++ return status; ++} ++ ++static void init_state(struct stv *state) ++{ ++ u32 clkdiv = 0; ++ u32 agcmode = 0; ++ u32 agcref = 2; ++ u32 agcset = 0xffffffff; ++ u32 bbmode = 0xffffffff; ++ ++ state->reg[0] = 0x08; ++ state->reg[1] = 0x41; ++ state->reg[2] = 0x8f; ++ state->reg[3] = 0x00; ++ state->reg[4] = 0xce; ++ state->reg[5] = 0x54; ++ state->reg[6] = 0x55; ++ state->reg[7] = 0x45; ++ state->reg[8] = 0x46; ++ state->reg[9] = 0xbd; ++ state->reg[10] = 0x11; ++ ++ state->ref_freq = 16000; ++ ++ ++ if (clkdiv <= 3) ++ state->reg[0x00] |= (clkdiv & 0x03); ++ if (agcmode <= 3) { ++ state->reg[0x03] |= (agcmode << 5); ++ if (agcmode == 0x01) ++ state->reg[0x01] |= 0x30; ++ } ++ if (bbmode <= 3) ++ state->reg[0x01] = (state->reg[0x01] & ~0x30) | (bbmode << 4); ++ if (agcref <= 7) ++ state->reg[0x03] |= agcref; ++ if (agcset <= 31) ++ state->reg[0x02] = (state->reg[0x02] & ~0x1F) | agcset | 0x40; ++} ++ ++static int attach_init(struct stv *state) ++{ ++ if (write_regs(state, 0, 11)) ++ return -1; ++ pr_info("attach_init OK\n"); ++ dump_regs(state); ++ return 0; ++} ++ ++static int sleep(struct dvb_frontend *fe) ++{ ++ /* struct tda_state *state = fe->tuner_priv; */ ++ ++ pr_info("tuner sleep\n"); ++ return 0; ++} ++ ++static int init(struct dvb_frontend *fe) ++{ ++ /* struct tda_state *state = fe->tuner_priv; */ ++ pr_info("init\n"); ++ return 0; ++} ++ ++static int release(struct dvb_frontend *fe) ++{ ++ kfree(fe->tuner_priv); ++ fe->tuner_priv = NULL; ++ return 0; ++} ++ ++static int set_bandwidth(struct dvb_frontend *fe, u32 CutOffFrequency) ++{ ++ struct stv *state = fe->tuner_priv; ++ u32 index = (CutOffFrequency + 999999) / 1000000; ++ ++ if (index < 6) ++ index = 6; ++ if (index > 50) ++ index = 50; ++ if ((state->reg[0x08] & ~0xFC) == ((index-6) << 2)) ++ return 0; ++ ++ state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index-6) << 2); ++ state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x08; ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ write_regs(state, 0x08, 2); ++ wait_for_call_done(state, 0x08); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ return 0; ++} ++ ++static int set_lof(struct stv *state, u32 LocalFrequency, u32 CutOffFrequency) ++{ ++ u32 index = (CutOffFrequency + 999999) / 1000000; ++ u32 Frequency = (LocalFrequency + 500) / 1000; ++ u32 p = 1, psel = 0, fvco, div, frac; ++ u8 Icp, tmp; ++ ++ pr_info("F = %u, COF = %u\n", Frequency, CutOffFrequency); ++ if (index < 6) ++ index = 6; ++ if (index > 50) ++ index = 50; ++ ++ if (Frequency <= 1300000) { ++ p = 4; ++ psel = 1; ++ } else { ++ p = 2; ++ psel = 0; ++ } ++ fvco = Frequency * p; ++ div = fvco / state->ref_freq; ++ frac = fvco % state->ref_freq; ++ frac = MulDiv32(frac, 0x40000, state->ref_freq); ++ ++ Icp = 0; ++ if (fvco < 2700000) ++ Icp = 0; ++ else if (fvco < 2950000) ++ Icp = 1; ++ else if (fvco < 3300000) ++ Icp = 2; ++ else if (fvco < 3700000) ++ Icp = 3; ++ else if (fvco < 4200000) ++ Icp = 5; ++ else if (fvco < 4800000) ++ Icp = 6; ++ else ++ Icp = 7; ++ ++ state->reg[0x02] |= 0x80; /* LNA IIP3 Mode */ ++ ++ state->reg[0x03] = (state->reg[0x03] & ~0x80) | (psel << 7); ++ state->reg[0x04] = (div & 0xFF); ++ state->reg[0x05] = (((div >> 8) & 0x01) | ((frac & 0x7F) << 1)) & 0xff; ++ state->reg[0x06] = ((frac >> 7) & 0xFF); ++ state->reg[0x07] = (state->reg[0x07] & ~0x07) | ((frac >> 15) & 0x07); ++ state->reg[0x07] = (state->reg[0x07] & ~0xE0) | (Icp << 5); ++ ++ state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2); ++ /* Start cal vco,CF */ ++ state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x0C; ++ write_regs(state, 2, 8); ++ ++ wait_for_call_done(state, 0x0C); ++ ++ usleep_range(10000, 12000); ++ ++ read_reg(state, 0x03, &tmp); ++ if (tmp & 0x10) { ++ state->reg[0x02] &= ~0x80; /* LNA NF Mode */ ++ write_regs(state, 2, 1); ++ } ++ read_reg(state, 0x08, &tmp); ++ ++ dump_regs(state); ++ return 0; ++} ++ ++static int set_params(struct dvb_frontend *fe) ++{ ++ struct stv *state = fe->tuner_priv; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ int status; ++ u32 freq, symb, cutoff; ++ ++ if (p->delivery_system != SYS_DVBS && p->delivery_system != SYS_DVBS2) ++ return -EINVAL; ++ ++ freq = p->frequency * 1000; ++ symb = p->symbol_rate; ++ cutoff = 5000000 + MulDiv32(p->symbol_rate, 135, 200); ++ ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ set_lof(state, freq, cutoff); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ return status; ++} ++ ++static int get_frequency(struct dvb_frontend *fe, u32 *frequency) ++{ ++ *frequency = 0; ++ return 0; ++} ++ ++static u32 AGC_Gain[] = { ++ 000, /* 0.0 */ ++ 000, /* 0.1 */ ++ 1000, /* 0.2 */ ++ 2000, /* 0.3 */ ++ 3000, /* 0.4 */ ++ 4000, /* 0.5 */ ++ 5000, /* 0.6 */ ++ 6000, /* 0.7 */ ++ 7000, /* 0.8 */ ++ 14000, /* 0.9 */ ++ 20000, /* 1.0 */ ++ 27000, /* 1.1 */ ++ 32000, /* 1.2 */ ++ 37000, /* 1.3 */ ++ 42000, /* 1.4 */ ++ 47000, /* 1.5 */ ++ 50000, /* 1.6 */ ++ 53000, /* 1.7 */ ++ 56000, /* 1.8 */ ++ 58000, /* 1.9 */ ++ 60000, /* 2.0 */ ++ 62000, /* 2.1 */ ++ 63000, /* 2.2 */ ++ 64000, /* 2.3 */ ++ 64500, /* 2.4 */ ++ 65000, /* 2.5 */ ++ 65500, /* 2.6 */ ++ 66000, /* 2.7 */ ++ 66500, /* 2.8 */ ++ 67000, /* 2.9 */ ++}; ++ ++static int get_rf_strength(struct dvb_frontend *fe, u16 *st) ++{ ++ *st = 0; ++#if 0 ++ struct stv *state = fe->tuner_priv; ++ s32 Gain; ++ u32 Index = RFAgc / 100; ++ if (Index >= (sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1)) ++ Gain = AGC_Gain[sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1]; ++ else ++ Gain = AGC_Gain[Index] + ++ ((AGC_Gain[Index+1] - AGC_Gain[Index]) * ++ (RFAgc % 100)) / 100; ++ *st = Gain; ++#endif ++ return 0; ++} ++ ++static int get_if(struct dvb_frontend *fe, u32 *frequency) ++{ ++ *frequency = 0; ++ return 0; ++} ++ ++static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) ++{ ++ return 0; ++} ++ ++static struct dvb_tuner_ops tuner_ops = { ++ .info = { ++ .name = "STV6111", ++ .frequency_min = 950000, ++ .frequency_max = 2150000, ++ .frequency_step = 0 ++ }, ++ .init = init, ++ .sleep = sleep, ++ .set_params = set_params, ++ .release = release, ++ .get_frequency = get_frequency, ++ .get_if_frequency = get_if, ++ .get_bandwidth = get_bandwidth, ++ .get_rf_strength = get_rf_strength, ++ .set_bandwidth = set_bandwidth, ++}; ++ ++struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, u8 adr) ++{ ++ struct stv *state; ++ int stat; ++ ++ state = kzalloc(sizeof(struct stv), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ state->adr = adr; ++ state->i2c = i2c; ++ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); ++ init_state(state); ++ ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ stat = attach_init(state); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ if (stat < 0) { ++ kfree(state); ++ return 0; ++ } ++ fe->tuner_priv = state; ++ return fe; ++} ++EXPORT_SYMBOL_GPL(stv6111_attach); ++ ++MODULE_DESCRIPTION("STV6111 driver"); ++MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); ++MODULE_LICENSE("GPL"); ++ ++/* ++ * Local variables: ++ * c-basic-offset: 8 ++ * End: ++ */ +diff --git a/drivers/media/dvb-frontends/stv6111.h b/drivers/media/dvb-frontends/stv6111.h +new file mode 100644 +index 0000000..31d200c +--- /dev/null ++++ b/drivers/media/dvb-frontends/stv6111.h +@@ -0,0 +1,5 @@ ++#ifndef _STV6111_H_ ++#define _STV6111_H_ ++struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, u8 adr); ++#endif diff --git a/drivers/media/dvb-frontends/tda18212dd.c b/drivers/media/dvb-frontends/tda18212dd.c new file mode 100644 -index 0000000..f7984a2 +index 0000000..7d99fd5 --- /dev/null +++ b/drivers/media/dvb-frontends/tda18212dd.c -@@ -0,0 +1,945 @@ -+/* -+ * tda18212: Driver for the TDA18212 tuner -+ * -+ * Copyright (C) 2011-2013 Digital Devices GmbH -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dvb_frontend.h" -+ -+#ifndef CHK_ERROR -+ #define CHK_ERROR(s) if ((status = s) < 0) break -+#endif -+ -+#define MASTER_PSM_AGC1 0 -+#define MASTER_AGC1_6_15dB 1 -+ -+#define SLAVE_PSM_AGC1 1 -+#define SLAVE_AGC1_6_15dB 0 -+ -+// 0 = 2 Vpp ... 2 = 1 Vpp, 7 = 0.5 Vpp -+#define IF_LEVEL_DVBC 2 -+#define IF_LEVEL_DVBT 2 -+ -+enum { -+ ID_1 = 0x00, -+ ID_2 = 0x01, -+ ID_3 = 0x02, -+ THERMO_1, -+ THERMO_2, -+ POWER_STATE_1, -+ POWER_STATE_2, -+ INPUT_POWER_LEVEL, -+ IRQ_STATUS, -+ IRQ_ENABLE, -+ IRQ_CLEAR, -+ IRQ_SET, -+ AGC1_1, -+ AGC2_1, -+ AGCK_1, -+ RF_AGC_1, -+ IR_MIXER_1 = 0x10, -+ AGC5_1, -+ IF_AGC, -+ IF_1, -+ REFERENCE, -+ IF_FREQUENCY_1, -+ RF_FREQUENCY_1, -+ RF_FREQUENCY_2, -+ RF_FREQUENCY_3, -+ MSM_1, -+ MSM_2, -+ PSM_1, -+ DCC_1, -+ FLO_MAX, -+ IR_CAL_1, -+ IR_CAL_2, -+ IR_CAL_3 = 0x20, -+ IR_CAL_4, -+ VSYNC_MGT, -+ IR_MIXER_2, -+ AGC1_2, -+ AGC5_2, -+ RF_CAL_1, -+ RF_CAL_2, -+ RF_CAL_3, -+ RF_CAL_4, -+ RF_CAL_5, -+ RF_CAL_6, -+ RF_FILTER_1, -+ RF_FILTER_2, -+ RF_FILTER_3, -+ RF_BAND_PASS_FILTER, -+ CP_CURRENT = 0x30, -+ AGC_DET_OUT = 0x31, -+ RF_AGC_GAIN_1 = 0x32, -+ RF_AGC_GAIN_2 = 0x33, -+ IF_AGC_GAIN = 0x34, -+ POWER_1 = 0x35, -+ POWER_2 = 0x36, -+ MISC_1, -+ RFCAL_LOG_1, -+ RFCAL_LOG_2, -+ RFCAL_LOG_3, -+ RFCAL_LOG_4, -+ RFCAL_LOG_5, -+ RFCAL_LOG_6, -+ RFCAL_LOG_7, -+ RFCAL_LOG_8, -+ RFCAL_LOG_9 = 0x40, -+ RFCAL_LOG_10 = 0x41, -+ RFCAL_LOG_11 = 0x42, -+ RFCAL_LOG_12 = 0x43, -+ REG_MAX, -+}; -+ -+enum HF_Standard { -+ HF_None=0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, -+ HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, -+ HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, -+ HF_DVBC_8MHZ, HF_DVBC -+}; -+ -+struct SStandardParams { -+ s32 m_IFFrequency; -+ u32 m_BandWidth; -+ u8 m_IF_1; // FF IF_HP_fc:2 IF_Notch:1 LP_FC_Offset:2 LP_FC:3 -+ u8 m_IR_MIXER_2; // 03 :6 HI_Pass:1 DC_Notch:1 -+ u8 m_AGC1_1; // 0F :4 AGC1_Top:4 -+ u8 m_AGC2_1; // 0F :4 AGC2_Top:4 -+ u8 m_RF_AGC_1_Low; // EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 -+ u8 m_RF_AGC_1_High;// EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 -+ u8 m_IR_MIXER_1; // 0F :4 IR_mixer_Top:4 -+ u8 m_AGC5_1; // 1F :3 AGC5_Ana AGC5_Top:4 -+ u8 m_AGCK_1; // 0F :4 AGCK_Step:2 AGCK_Mode:2 -+ u8 m_PSM_1; // 20 :2 PSM_StoB:1 :5 -+ bool m_AGC1_Freeze; -+ bool m_LTO_STO_immune; -+}; -+ -+#if 0 -+static struct SStandardParams m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = -+{ -+ { 3250000, 6000000, 0x20, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_6MHZ -+ { 3500000, 7000000, 0x31, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_7MHZ -+ { 4000000, 8000000, 0x22, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_8MHZ -+ { 0, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, // HF_DVBT (Unused) -+ { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, // HF_ATSC -+ { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_6MHZ -+// { 5000000, 7000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -+// { 5000000, 8000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -+ { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -+ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -+}; -+#else -+static struct SStandardParams m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = -+{ -+ { 4000000, 6000000, 0x41, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_6MHZ -+ { 4500000, 7000000, 0x42, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_7MHZ -+ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_8MHZ -+ // ------------------------------ -+ { 0, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, // HF_DVBT (Unused) -+ { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, // HF_ATSC -+ { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_6MHZ -+// { 5000000, 7000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -+// { 5000000, 8000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -+ { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -+ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -+}; -+#endif -+struct tda_state { -+ struct i2c_adapter *i2c; -+ u8 adr; -+ -+ enum HF_Standard m_Standard; -+ u32 m_Frequency; -+ u32 IF; -+ -+ bool m_isMaster; -+ bool m_bPowerMeasurement; -+ bool m_bLTEnable; -+ bool m_bEnableFreeze; -+ -+ u16 m_ID; -+ -+ s32 m_SettlingTime; -+ -+ u8 m_IFLevelDVBC; -+ u8 m_IFLevelDVBT; -+ u8 Regs[REG_MAX]; -+ u8 m_LastPowerLevel; -+}; -+ -+static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, -+ .buf = data, .len = len}}; -+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -+} -+ -+static int i2c_read(struct i2c_adapter *adap, -+ u8 adr, u8 *msg, int len, u8 *answ, int alen) -+{ -+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, -+ .buf = msg, .len = len}, -+ { .addr = adr, .flags = I2C_M_RD, -+ .buf = answ, .len = alen } }; -+ if (i2c_transfer(adap, msgs, 2) != 2) { -+ printk("tda18212dd: i2c_read error\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msg = {.addr = adr, .flags = 0, -+ .buf = data, .len = len}; -+ -+ if (i2c_transfer(adap, &msg, 1) != 1) { -+ printk("tda18212: i2c_write error\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+static int write_regs(struct tda_state *state, -+ u8 SubAddr, u8 *Regs, u16 nRegs) -+{ -+ u8 data[REG_MAX + 1]; -+ -+ data[0] = SubAddr; -+ memcpy(data + 1, Regs, nRegs); -+ return i2c_write(state->i2c, state->adr, data, nRegs + 1); -+} -+ -+static int write_reg(struct tda_state *state, u8 SubAddr,u8 Reg) -+{ -+ u8 msg[2] = {SubAddr, Reg}; -+ -+ return i2c_write(state->i2c, state->adr, msg, 2); -+} -+ -+static int Read(struct tda_state *state, u8 * Regs) -+{ -+ return i2c_readn(state->i2c, state->adr, Regs, REG_MAX); -+} -+ -+static int update_regs(struct tda_state *state, u8 RegFrom,u8 RegTo) -+{ -+ return write_regs(state, RegFrom, -+ &state->Regs[RegFrom], RegTo-RegFrom + 1); -+} -+ -+static int update_reg(struct tda_state *state, u8 Reg) -+{ -+ return write_reg(state, Reg,state->Regs[Reg]); -+} -+ -+ -+static int read_regs(struct tda_state *state, -+ u8 SubAddr, u8 *Regs, u16 nRegs) -+{ -+ return i2c_read(state->i2c, state->adr, -+ &SubAddr, 1, Regs, nRegs); -+} -+ -+static int read_reg(struct tda_state *state, -+ u8 SubAddr, u8 *Reg) -+{ -+ return i2c_read(state->i2c, state->adr, -+ &SubAddr, 1, Reg, 1); -+} -+ -+static int read_reg1(struct tda_state *state, u8 Reg) -+{ -+ return read_reg(state, Reg, &state->Regs[Reg]); -+} -+ -+static void init_state(struct tda_state *state) -+{ -+ u32 ulIFLevelDVBC = IF_LEVEL_DVBC; -+ u32 ulIFLevelDVBT = IF_LEVEL_DVBT; -+ u32 ulPowerMeasurement = 1; -+ u32 ulLTEnable = 1; -+ u32 ulEnableFreeze = 0; -+ -+ state->m_Frequency = 0; -+ state->m_isMaster = true; -+ state->m_ID = 0; -+ state->m_LastPowerLevel = 0xFF; -+ state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07); -+ state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07); -+ state->m_bPowerMeasurement = (ulPowerMeasurement != 0); -+ state->m_bLTEnable = (ulLTEnable != 0); -+ state->m_bEnableFreeze = (ulEnableFreeze != 0); -+} -+ -+static int StartCalibration(struct tda_state *state) -+{ -+ int status = 0; -+ do { -+ state->Regs[POWER_2] &= ~0x02; // RSSI CK = 31.25 kHz -+ CHK_ERROR(update_reg(state, POWER_2)); -+ -+ state->Regs[AGC1_2] = (state->Regs[AGC1_2] & ~0x60) | 0x40; // AGC1 Do Step = 2 -+ CHK_ERROR(update_reg(state, AGC1_2)); // AGC -+ -+ state->Regs[RF_FILTER_3] = (state->Regs[RF_FILTER_3] & ~0xC0) | 0x40; // AGC2 Do Step = 1 -+ CHK_ERROR(update_reg(state, RF_FILTER_3)); -+ -+ state->Regs[AGCK_1] |= 0xC0; // AGCs Assym Up Step = 3 // Datasheet sets all bits to 1! -+ CHK_ERROR(update_reg(state, AGCK_1)); -+ -+ state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x60) | 0x40; // AGCs Assym Do Step = 2 -+ CHK_ERROR(update_reg(state, AGC5_1)); -+ -+ state->Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ state->Regs[MSM_1] = 0x3B; // Set Calibration -+ state->Regs[MSM_2] = 0x01; // Start MSM -+ CHK_ERROR(update_regs(state, MSM_1,MSM_2)); -+ state->Regs[MSM_2] = 0x00; -+ -+ } while(0); -+ return status; -+} -+ -+static int FinishCalibration(struct tda_state *state) -+{ -+ int status = 0; -+ u8 RFCal_Log[12]; -+ -+ do { -+ u8 IRQ = 0; -+ int Timeout = 150; // 1.5 s -+ while(true) { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if ((IRQ & 0x80) != 0 ) -+ break; -+ Timeout -= 1; -+ if (Timeout == 0) { -+ status = -1; -+ break; -+ } -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ state->Regs[FLO_MAX] = 0x0A; -+ CHK_ERROR(update_reg(state, FLO_MAX)); -+ -+ state->Regs[AGC1_1] &= ~0xC0; -+ if( state->m_bLTEnable ) state->Regs[AGC1_1] |= 0x80; // LTEnable -+ -+ state->Regs[AGC1_1] |= (state->m_isMaster ? MASTER_AGC1_6_15dB : SLAVE_AGC1_6_15dB ) << 6; -+ CHK_ERROR(update_reg(state, AGC1_1)); -+ -+ state->Regs[PSM_1] &= ~0xC0; -+ state->Regs[PSM_1] |= (state->m_isMaster ? MASTER_PSM_AGC1 : SLAVE_PSM_AGC1 ) << 6; -+ CHK_ERROR(update_reg(state, PSM_1)); -+ -+ state->Regs[REFERENCE] |= 0x03; // XTOUT = 3 -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ CHK_ERROR(read_regs(state, RFCAL_LOG_1,RFCal_Log,sizeof(RFCal_Log))); -+ } while(0); -+ return status; -+} -+ -+static int PowerOn(struct tda_state *state) -+{ -+ state->Regs[POWER_STATE_2] &= ~0x0F; -+ update_reg(state, POWER_STATE_2); -+ state->Regs[REFERENCE] |= 0x40; // Digital clock source = Sigma Delta -+ update_reg(state, REFERENCE); -+ return 0; -+} -+ -+static int Standby(struct tda_state *state) -+{ -+ int status = 0; -+ -+ do { -+ state->Regs[REFERENCE] &= ~0x40; // Digital clock source = Quarz -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ state->Regs[POWER_STATE_2] &= ~0x0F; -+ state->Regs[POWER_STATE_2] |= state->m_isMaster ? 0x08 : 0x0E; -+ CHK_ERROR(update_reg(state, POWER_STATE_2)); -+ } while(0); -+ return status; -+} -+ -+static int attach_init(struct tda_state *state) -+{ -+ int stat = 0; -+ u8 Id[2]; -+ u8 PowerState = 0x00; -+ -+ state->m_Standard = HF_None; -+ -+ /* first read after cold reset sometimes fails on some cards, -+ try twice */ -+ stat = read_regs(state, ID_1, Id, sizeof(Id)); -+ stat = read_regs(state, ID_1, Id, sizeof(Id)); -+ if (stat < 0) -+ return -1; -+ -+ state->m_ID = ((Id[0] & 0x7F) << 8) | Id[1]; -+ state->m_isMaster = ((Id[0] & 0x80) != 0); -+ if( !state->m_isMaster ) -+ state->m_bLTEnable = false; -+ -+ printk("tda18212dd: ChipID %04x %s\n", state->m_ID, -+ state->m_isMaster ? "master" : "slave"); -+ -+ if( state->m_ID != 18212 ) -+ return -1; -+ -+ stat = read_reg(state, POWER_STATE_1 ,&PowerState); -+ if (stat < 0) -+ return stat; -+ -+ printk("tda18212dd: PowerState %02x\n", PowerState); -+ -+ if (state->m_isMaster) { -+ if( PowerState & 0x02 ) { -+ // msleep for XTAL Calibration (on a PC this should be long done) -+ u8 IRQStatus = 0; -+ int Timeout = 10; -+ -+ while(Timeout > 0) { -+ read_reg(state, IRQ_STATUS, &IRQStatus); -+ if (IRQStatus & 0x20) -+ break; -+ Timeout -= 1; -+ msleep(10); -+ } -+ if( (IRQStatus & 0x20) == 0 ) { -+ stat = -ETIMEDOUT; -+ } -+ } -+ } else { -+ write_reg(state, FLO_MAX, 0x00); -+ write_reg(state, CP_CURRENT,0x68); -+ } -+ Read(state, state->Regs); -+ -+ PowerOn(state); -+ StartCalibration(state); -+ FinishCalibration(state); -+ Standby(state); -+ -+ { -+ u8 RFCal_Log[12]; -+ -+ read_regs(state, RFCAL_LOG_1, RFCal_Log, sizeof(RFCal_Log)); -+ printk("RFCal Log: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ RFCal_Log[0],RFCal_Log[1],RFCal_Log[2],RFCal_Log[3], -+ RFCal_Log[4],RFCal_Log[5],RFCal_Log[6],RFCal_Log[7], -+ RFCal_Log[8],RFCal_Log[9],RFCal_Log[10],RFCal_Log[11]); -+ } -+ return stat; -+} -+ -+static int PowerMeasurement(struct tda_state *state, u8 *pPowerLevel) -+{ -+ int status = 0; -+ -+ do { -+ u8 IRQ = 0; -+ int Timeout = 70; // 700 ms -+ -+ state->Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ state->Regs[MSM_1] = 0x80; // power measurement -+ state->Regs[MSM_2] = 0x01; // Start MSM -+ CHK_ERROR(update_regs(state, MSM_1,MSM_2)); -+ state->Regs[MSM_2] = 0x00; -+ -+ while(true) { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if( (IRQ & 0x80) != 0 ) -+ break; -+ Timeout -= 1; -+ if( Timeout == 0 ) -+ { -+ status = -1; -+ break; -+ } -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ CHK_ERROR(read_reg1(state, INPUT_POWER_LEVEL)); -+ *pPowerLevel = state->Regs[INPUT_POWER_LEVEL] & 0x7F; -+ -+ -+ if( *pPowerLevel > 110 ) *pPowerLevel = 110; -+ } while(0); -+ /* printk("PL %d\n", *pPowerLevel); */ -+ return status; -+} -+ -+static int SetFrequency(struct tda_state *state, u32 Frequency, enum HF_Standard Standard) -+{ -+ int status = 0; -+ struct SStandardParams *StandardParams; -+ u32 f = Frequency / 1000; -+ u8 IRQ = 0; -+ int Timeout = 25; // 250 ms -+ u32 fRatio = Frequency / 16000000; -+ u32 fDelta = Frequency - fRatio * 16000000; -+ -+ if( Standard < HF_DVBT_6MHZ || Standard > HF_DVBC_8MHZ ) -+ return -EINVAL; -+ StandardParams = &m_StandardTable[Standard - HF_DVBT_6MHZ]; -+ -+ if( StandardParams->m_IFFrequency == 0 ) -+ return -EINVAL; -+ state->m_Standard = HF_None; -+ state->m_Frequency = 0; -+ -+ do { -+ /* IF Level */ -+ state->Regs[IF_AGC] = (Standard >= HF_DVBC_6MHZ) ? state->m_IFLevelDVBC : state->m_IFLevelDVBT; -+ CHK_ERROR(update_reg(state, IF_AGC)); -+ -+ /* Standard setup */ -+ state->Regs[IF_1] = StandardParams->m_IF_1; -+ CHK_ERROR(update_reg(state, IF_1)); -+ -+ state->Regs[IR_MIXER_2] = (state->Regs[IR_MIXER_2] & ~0x03) | StandardParams->m_IR_MIXER_2; -+ CHK_ERROR(update_reg(state, IR_MIXER_2)); -+ -+ state->Regs[AGC1_1] = (state->Regs[AGC1_1] & ~0x0F) | StandardParams->m_AGC1_1; -+ CHK_ERROR(update_reg(state, AGC1_1)); -+ -+ state->Regs[AGC2_1] = (state->Regs[AGC2_1] & ~0x0F) | StandardParams->m_AGC2_1; -+ CHK_ERROR(update_reg(state, AGC2_1)); -+ -+ state->Regs[RF_AGC_1] &= ~0xEF; -+ if( Frequency < 291000000 ) -+ state->Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_Low; -+ else -+ state->Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_High; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ -+ state->Regs[IR_MIXER_1] = (state->Regs[IR_MIXER_1] & ~0x0F) | StandardParams->m_IR_MIXER_1; -+ CHK_ERROR(update_reg(state, IR_MIXER_1)); -+ -+ state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x1F) | StandardParams->m_AGC5_1; -+ CHK_ERROR(update_reg(state, AGC5_1)); -+ -+ state->Regs[AGCK_1] = (state->Regs[AGCK_1] & ~0x0F) | StandardParams->m_AGCK_1; -+ CHK_ERROR(update_reg(state, AGCK_1)); -+ -+ state->Regs[PSM_1] = (state->Regs[PSM_1] & ~0x20) | StandardParams->m_PSM_1; -+ CHK_ERROR(update_reg(state, PSM_1)); -+ -+ state->Regs[IF_FREQUENCY_1] = ( StandardParams->m_IFFrequency / 50000 ); -+ CHK_ERROR(update_reg(state, IF_FREQUENCY_1)); -+ -+ if (state->m_isMaster && StandardParams->m_LTO_STO_immune ) { -+ u8 tmp; -+ u8 RF_Filter_Gain; -+ -+ CHK_ERROR(read_reg(state, RF_AGC_GAIN_1,&tmp)); -+ RF_Filter_Gain = (tmp & 0x30) >> 4; -+ -+ state->Regs[RF_FILTER_1] = (state->Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ -+ state->Regs[RF_FILTER_1] |= 0x10; // Force -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ -+ while( RF_Filter_Gain != 0 ) -+ { -+ RF_Filter_Gain -= 1; -+ state->Regs[RF_FILTER_1] = (state->Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ state->Regs[RF_AGC_1] |= 0x08; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ } -+ -+ // --------------------------------------------------------------------------------- -+ -+ state->Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ CHK_ERROR(PowerOn(state)); -+ -+ state->Regs[RF_FREQUENCY_1] = ((f >> 16) & 0xFF); -+ state->Regs[RF_FREQUENCY_2] = ((f >> 8) & 0xFF); -+ state->Regs[RF_FREQUENCY_3] = ((f ) & 0xFF); -+ CHK_ERROR(update_regs(state, RF_FREQUENCY_1,RF_FREQUENCY_3)); -+ -+ state->Regs[MSM_1] = 0x41; // Tune -+ state->Regs[MSM_2] = 0x01; // Start MSM -+ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); -+ state->Regs[MSM_2] = 0x00; -+ -+ while(true) -+ { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if( (IRQ & 0x80) != 0 ) break; -+ Timeout -= 1; -+ if (Timeout == 0) { -+ status = -1; -+ break; -+ } -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ // --------------------------------------------------------------------------------- -+ -+ if( state->m_isMaster && StandardParams->m_LTO_STO_immune ) -+ { -+ state->Regs[RF_AGC_1] &= ~0x08; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ -+ msleep(50); -+ -+ state->Regs[RF_FILTER_1] &= ~0x10; // remove force -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ } -+ -+ // --------------------------------------------------------------------------------- -+ // Spur reduction -+ -+ if( Frequency < 72000000 ) -+ { -+ state->Regs[REFERENCE] |= 0x40; // Set digital clock -+ } -+ else if( Frequency < 104000000 ) -+ { -+ state->Regs[REFERENCE] &= ~0x40; // Clear digital clock -+ } -+ else if( Frequency < 120000000 ) -+ { -+ state->Regs[REFERENCE] |= 0x40; // Set digital clock -+ } -+ else -+ { -+ if( fDelta <= 8000000 ) -+ { -+ if( fRatio & 1 ) state->Regs[REFERENCE] &= ~0x40; // Clear digital clock -+ else state->Regs[REFERENCE] |= 0x40; // Set digital clock -+ } -+ else -+ { -+ if( fRatio & 1 ) state->Regs[REFERENCE] |= 0x40; // Set digital clock -+ else state->Regs[REFERENCE] &= ~0x40; // Clear digital clock -+ } -+ -+ } -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ if( StandardParams->m_AGC1_Freeze && state->m_bEnableFreeze ) -+ { -+ u8 tmp; -+ int AGC1GainMin = 0; -+ int nSteps = 10; -+ int Step = 0; -+ -+ CHK_ERROR(read_reg(state, AGC1_2,&tmp)); -+ -+ if( (tmp & 0x80) == 0 ) -+ { -+ state->Regs[AGC1_2] |= 0x80; // Loop off -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ state->Regs[AGC1_2] |= 0x10 ; // Force gain -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ // Adapt -+ if( state->Regs[AGC1_1] & 0x40 ) // AGC1_6_15dB set -+ { -+ AGC1GainMin = 6; -+ nSteps = 4; -+ } -+ while( Step < nSteps ) -+ { -+ int Down = 0; -+ int Up = 0, i; -+ u8 AGC1_Gain; -+ -+ Step = Step + 1; -+ -+ for (i = 0; i < 40; i += 1) { -+ CHK_ERROR(read_reg(state, AGC_DET_OUT, &tmp)); -+ Up += (tmp & 0x02) ? 1 : -4; -+ Down += (tmp & 0x01) ? 14 : -1; -+ msleep(1); -+ } -+ CHK_ERROR(status); -+ AGC1_Gain = (state->Regs[AGC1_2] & 0x0F); -+ if( Up >= 15 && AGC1_Gain != 9 ) -+ { -+ state->Regs[AGC1_2] = ( state->Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain + 1); -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ else if ( Down >= 10 && AGC1_Gain != AGC1GainMin ) -+ { -+ state->Regs[AGC1_2] = ( state->Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain - 1); -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ else -+ { -+ Step = nSteps; -+ } -+ } -+ } -+ else -+ { -+ state->Regs[AGC1_2] &= ~0x10 ; // unforce gain -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ state->Regs[AGC1_2] &= ~0x80; // Loop on -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ -+ state->m_Standard = Standard; -+ state->m_Frequency = Frequency; -+ -+ if( state->m_bPowerMeasurement ) -+ PowerMeasurement(state, &state->m_LastPowerLevel); -+ } while(0); -+ -+ return status; -+} -+ -+static int sleep(struct dvb_frontend* fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ Standby(state); -+ return 0; -+} -+ -+static int init(struct dvb_frontend* fe) -+{ -+ //struct tda_state *state = fe->tuner_priv; -+ return 0; -+} -+ -+static int release(struct dvb_frontend* fe) -+{ -+ kfree(fe->tuner_priv); -+ fe->tuner_priv = NULL; -+ return 0; -+} -+ -+#ifndef USE_API3 -+static int set_params(struct dvb_frontend *fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ int status = 0; -+ int Standard; -+ u32 bw; -+ -+ bw = (p->bandwidth_hz + 999999) / 1000000; -+ state->m_Frequency = p->frequency; -+ printk("tuner bw=%u freq=%u\n", bw, state->m_Frequency); -+ if (p->delivery_system == SYS_DVBT || -+ p->delivery_system == SYS_DVBT2 || -+ p->delivery_system == SYS_ISDBT) { -+ switch (bw) { -+ case 6: -+ Standard = HF_DVBT_6MHZ; -+ break; -+ case 7: -+ Standard = HF_DVBT_7MHZ; -+ break; -+ default: -+ case 8: -+ Standard = HF_DVBT_8MHZ; -+ break; -+ } -+ } else if (p->delivery_system == SYS_DVBC_ANNEX_A) { -+ switch (bw) { -+ case 6: -+ Standard = HF_DVBC_6MHZ; -+ break; -+ case 7: -+ Standard = HF_DVBC_7MHZ; -+ break; -+ default: -+ case 8: -+ Standard = HF_DVBC_8MHZ; -+ break; -+ } -+ } else -+ return -EINVAL; -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ SetFrequency(state, state->m_Frequency, Standard); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ -+ return status; -+} -+#else -+static int set_params(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *params) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ int status = 0; -+ int Standard; -+ -+ state->m_Frequency = params->frequency; -+ -+ if (fe->ops.info.type == FE_OFDM) -+ switch (params->u.ofdm.bandwidth) { -+ case BANDWIDTH_6_MHZ: -+ Standard = HF_DVBT_6MHZ; -+ break; -+ case BANDWIDTH_7_MHZ: -+ Standard = HF_DVBT_7MHZ; -+ break; -+ default: -+ case BANDWIDTH_8_MHZ: -+ Standard = HF_DVBT_8MHZ; -+ break; -+ } -+ else if (fe->ops.info.type == FE_QAM) { -+ Standard = HF_DVBC_8MHZ; -+ } else -+ return -EINVAL; -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ SetFrequency(state, state->m_Frequency, Standard); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ -+ return status; -+} -+#endif -+ -+static int get_frequency(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ *frequency = state->IF; -+ return 0; -+} -+ -+static int get_rf_strength(struct dvb_frontend *fe, u16 *st) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ *st = state->m_LastPowerLevel; -+ return 0; -+} -+ -+static int get_if(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ state->IF = 0; -+ if (state->m_Standard < HF_DVBT_6MHZ || -+ state->m_Standard > HF_DVBC_8MHZ) -+ return 0; -+ state->IF = m_StandardTable[state->m_Standard - HF_DVBT_6MHZ].m_IFFrequency; -+ *frequency = state->IF; -+ return 0; -+} -+ -+static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -+{ -+ //struct tda_state *state = fe->tuner_priv; -+ //*bandwidth = priv->bandwidth; -+ return 0; -+} -+ -+ -+static struct dvb_tuner_ops tuner_ops = { -+ .info = { -+ .name = "NXP TDA18212", -+ .frequency_min = 47125000, -+ .frequency_max = 865000000, -+ .frequency_step = 62500 -+ }, -+ .init = init, -+ .sleep = sleep, -+ .set_params = set_params, -+ .release = release, -+ .get_frequency = get_frequency, -+ .get_if_frequency = get_if, -+ .get_bandwidth = get_bandwidth, -+ .get_rf_strength = get_rf_strength, -+}; -+ -+struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, u8 adr) -+{ -+ struct tda_state *state; -+ int stat; -+ -+ state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); -+ if (!state) -+ return NULL; -+ state->adr = adr; -+ state->i2c = i2c; -+ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); -+ init_state(state); -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ stat = attach_init(state); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ if (stat < 0) { -+ kfree(state); -+ return 0; -+ } -+ fe->tuner_priv = state; -+ return fe; -+} -+ -+EXPORT_SYMBOL_GPL(tda18212dd_attach); -+MODULE_DESCRIPTION("TDA18212 driver"); -+MODULE_AUTHOR("Ralph Metzler, Manfrad Voelkel"); -+MODULE_LICENSE("GPL"); -+ -+/* -+ * Local variables: -+ * c-basic-offset: 8 -+ * End: -+ */ +@@ -0,0 +1,974 @@ ++/* ++ * tda18212: Driver for the TDA18212 tuner ++ * ++ * Copyright (C) 2011-2013 Digital Devices GmbH ++ * ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 only, as published by the Free Software Foundation. ++ * ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA ++ * 02110-1301, USA ++ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dvb_frontend.h" ++ ++#ifndef CHK_ERROR ++#define CHK_ERROR(s) if ((status = s) < 0) break ++#endif ++ ++#define MASTER_PSM_AGC1 0 ++#define MASTER_AGC1_6_15dB 1 ++ ++#define SLAVE_PSM_AGC1 1 ++#define SLAVE_AGC1_6_15dB 0 ++ ++/* 0 = 2 Vpp ... 2 = 1 Vpp, 7 = 0.5 Vpp */ ++#define IF_LEVEL_DVBC 2 ++#define IF_LEVEL_DVBT 2 ++ ++enum { ++ ID_1 = 0x00, ++ ID_2 = 0x01, ++ ID_3 = 0x02, ++ THERMO_1, ++ THERMO_2, ++ POWER_STATE_1, ++ POWER_STATE_2, ++ INPUT_POWER_LEVEL, ++ IRQ_STATUS, ++ IRQ_ENABLE, ++ IRQ_CLEAR, ++ IRQ_SET, ++ AGC1_1, ++ AGC2_1, ++ AGCK_1, ++ RF_AGC_1, ++ IR_MIXER_1 = 0x10, ++ AGC5_1, ++ IF_AGC, ++ IF_1, ++ REFERENCE, ++ IF_FREQUENCY_1, ++ RF_FREQUENCY_1, ++ RF_FREQUENCY_2, ++ RF_FREQUENCY_3, ++ MSM_1, ++ MSM_2, ++ PSM_1, ++ DCC_1, ++ FLO_MAX, ++ IR_CAL_1, ++ IR_CAL_2, ++ IR_CAL_3 = 0x20, ++ IR_CAL_4, ++ VSYNC_MGT, ++ IR_MIXER_2, ++ AGC1_2, ++ AGC5_2, ++ RF_CAL_1, ++ RF_CAL_2, ++ RF_CAL_3, ++ RF_CAL_4, ++ RF_CAL_5, ++ RF_CAL_6, ++ RF_FILTER_1, ++ RF_FILTER_2, ++ RF_FILTER_3, ++ RF_BAND_PASS_FILTER, ++ CP_CURRENT = 0x30, ++ AGC_DET_OUT = 0x31, ++ RF_AGC_GAIN_1 = 0x32, ++ RF_AGC_GAIN_2 = 0x33, ++ IF_AGC_GAIN = 0x34, ++ POWER_1 = 0x35, ++ POWER_2 = 0x36, ++ MISC_1, ++ RFCAL_LOG_1, ++ RFCAL_LOG_2, ++ RFCAL_LOG_3, ++ RFCAL_LOG_4, ++ RFCAL_LOG_5, ++ RFCAL_LOG_6, ++ RFCAL_LOG_7, ++ RFCAL_LOG_8, ++ RFCAL_LOG_9 = 0x40, ++ RFCAL_LOG_10 = 0x41, ++ RFCAL_LOG_11 = 0x42, ++ RFCAL_LOG_12 = 0x43, ++ REG_MAX, ++}; ++ ++enum HF_Standard { ++ HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, ++ HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, ++ HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, ++ HF_DVBC_8MHZ, HF_DVBC ++}; ++ ++struct SStandardParams { ++ s32 m_IFFrequency; ++ u32 m_BandWidth; ++ u8 m_IF_1; /* FF IF_HP_fc:2 IF_Notch:1 LP_FC_Offset:2 LP_FC:3 */ ++ u8 m_IR_MIXER_2; /* 03 :6 HI_Pass:1 DC_Notch:1 */ ++ u8 m_AGC1_1; /* 0F :4 AGC1_Top:4 */ ++ u8 m_AGC2_1; /* 0F :4 AGC2_Top:4 */ ++ /*EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 */ ++ u8 m_RF_AGC_1_Low; ++ /*EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 */ ++ u8 m_RF_AGC_1_High; ++ u8 m_IR_MIXER_1; /* 0F :4 IR_mixer_Top:4 */ ++ u8 m_AGC5_1; /* 1F :3 AGC5_Ana AGC5_Top:4 */ ++ u8 m_AGCK_1; /* 0F :4 AGCK_Step:2 AGCK_Mode:2 */ ++ u8 m_PSM_1; /* 20 :2 PSM_StoB:1 :5 */ ++ bool m_AGC1_Freeze; ++ bool m_LTO_STO_immune; ++}; ++ ++#if 0 ++static struct SStandardParams ++m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = { ++ { 3250000, 6000000, 0x20, 0x03, 0x00, 0x07, 0x2B, ++ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_6MHZ */ ++ { 3500000, 7000000, 0x31, 0x01, 0x00, 0x07, 0x2B, ++ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_7MHZ */ ++ { 4000000, 8000000, 0x22, 0x01, 0x00, 0x07, 0x2B, ++ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_8MHZ */ ++ { 0000000, 0, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, /* HF_DVBT (Unused) */ ++ { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, ++ 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, /* HF_ATSC */ ++ { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, ++ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_6MHZ */ ++ { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, ++ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, ++ /* HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) */ ++ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, ++ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_8MHZ */ ++}; ++#else ++static struct SStandardParams ++m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = { ++ { 4000000, 6000000, 0x41, 0x03, 0x00, 0x07, 0x2B, ++ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_6MHZ */ ++ { 4500000, 7000000, 0x42, 0x03, 0x00, 0x07, 0x2B, ++ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_7MHZ */ ++ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x2B, ++ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_8MHZ */ ++ /* ------------------------------ */ ++ { 0000000, 0, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, /* HF_DVBT (Unused)*/ ++ { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, ++ 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, /* HF_ATSC */ ++ { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, ++ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_6MHZ */ ++ { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, ++ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, ++ /* HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) */ ++ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, ++ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_8MHZ */ ++}; ++#endif ++ ++struct tda_state { ++ struct i2c_adapter *i2c; ++ u8 adr; ++ ++ enum HF_Standard m_Standard; ++ u32 m_Frequency; ++ u32 IF; ++ ++ bool m_isMaster; ++ bool m_bPowerMeasurement; ++ bool m_bLTEnable; ++ bool m_bEnableFreeze; ++ ++ u16 m_ID; ++ ++ s32 m_SettlingTime; ++ ++ u8 m_IFLevelDVBC; ++ u8 m_IFLevelDVBT; ++ u8 Regs[REG_MAX]; ++ u8 m_LastPowerLevel; ++}; ++ ++static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) ++{ ++ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, ++ .buf = data, .len = len} }; ++ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; ++} ++ ++static int i2c_read(struct i2c_adapter *adap, ++ u8 adr, u8 *msg, int len, u8 *answ, int alen) ++{ ++ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, ++ .buf = msg, .len = len}, ++ { .addr = adr, .flags = I2C_M_RD, ++ .buf = answ, .len = alen } }; ++ if (i2c_transfer(adap, msgs, 2) != 2) { ++ pr_err("tda18212dd: i2c_read error\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) ++{ ++ struct i2c_msg msg = {.addr = adr, .flags = 0, ++ .buf = data, .len = len}; ++ ++ if (i2c_transfer(adap, &msg, 1) != 1) { ++ pr_err("tda18212: i2c_write error\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++static int write_regs(struct tda_state *state, ++ u8 SubAddr, u8 *Regs, u16 nRegs) ++{ ++ u8 data[REG_MAX + 1]; ++ ++ data[0] = SubAddr; ++ memcpy(data + 1, Regs, nRegs); ++ return i2c_write(state->i2c, state->adr, data, nRegs + 1); ++} ++ ++static int write_reg(struct tda_state *state, u8 SubAddr, u8 Reg) ++{ ++ u8 msg[2] = {SubAddr, Reg}; ++ ++ return i2c_write(state->i2c, state->adr, msg, 2); ++} ++ ++static int Read(struct tda_state *state, u8 *Regs) ++{ ++ return i2c_readn(state->i2c, state->adr, Regs, REG_MAX); ++} ++ ++static int update_regs(struct tda_state *state, u8 RegFrom, u8 RegTo) ++{ ++ return write_regs(state, RegFrom, ++ &state->Regs[RegFrom], RegTo-RegFrom + 1); ++} ++ ++static int update_reg(struct tda_state *state, u8 Reg) ++{ ++ return write_reg(state, Reg, state->Regs[Reg]); ++} ++ ++ ++static int read_regs(struct tda_state *state, ++ u8 SubAddr, u8 *Regs, u16 nRegs) ++{ ++ return i2c_read(state->i2c, state->adr, ++ &SubAddr, 1, Regs, nRegs); ++} ++ ++static int read_reg(struct tda_state *state, ++ u8 SubAddr, u8 *Reg) ++{ ++ return i2c_read(state->i2c, state->adr, ++ &SubAddr, 1, Reg, 1); ++} ++ ++static int read_reg1(struct tda_state *state, u8 Reg) ++{ ++ return read_reg(state, Reg, &state->Regs[Reg]); ++} ++ ++static void init_state(struct tda_state *state) ++{ ++ u32 ulIFLevelDVBC = IF_LEVEL_DVBC; ++ u32 ulIFLevelDVBT = IF_LEVEL_DVBT; ++ u32 ulPowerMeasurement = 1; ++ u32 ulLTEnable = 1; ++ u32 ulEnableFreeze = 0; ++ ++ state->m_Frequency = 0; ++ state->m_isMaster = true; ++ state->m_ID = 0; ++ state->m_LastPowerLevel = 0xFF; ++ state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07); ++ state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07); ++ state->m_bPowerMeasurement = (ulPowerMeasurement != 0); ++ state->m_bLTEnable = (ulLTEnable != 0); ++ state->m_bEnableFreeze = (ulEnableFreeze != 0); ++} ++ ++static int StartCalibration(struct tda_state *state) ++{ ++ int status = 0; ++ do { ++ state->Regs[POWER_2] &= ~0x02; /* RSSI CK = 31.25 kHz */ ++ CHK_ERROR(update_reg(state, POWER_2)); ++ ++ /* AGC1 Do Step = 2 */ ++ state->Regs[AGC1_2] = (state->Regs[AGC1_2] & ~0x60) | 0x40; ++ CHK_ERROR(update_reg(state, AGC1_2)); /* AGC */ ++ ++ /* AGC2 Do Step = 1 */ ++ state->Regs[RF_FILTER_3] = ++ (state->Regs[RF_FILTER_3] & ~0xC0) | 0x40; ++ CHK_ERROR(update_reg(state, RF_FILTER_3)); ++ ++ /* AGCs Assym Up Step = 3 // Datasheet sets all bits to 1! */ ++ state->Regs[AGCK_1] |= 0xC0; ++ CHK_ERROR(update_reg(state, AGCK_1)); ++ ++ /* AGCs Assym Do Step = 2 */ ++ state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x60) | 0x40; ++ CHK_ERROR(update_reg(state, AGC5_1)); ++ ++ state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */ ++ CHK_ERROR(update_reg(state, IRQ_CLEAR)); ++ ++ state->Regs[MSM_1] = 0x3B; /* Set Calibration */ ++ state->Regs[MSM_2] = 0x01; /* Start MSM */ ++ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); ++ state->Regs[MSM_2] = 0x00; ++ } while (0); ++ return status; ++} ++ ++static int FinishCalibration(struct tda_state *state) ++{ ++ int status = 0; ++ u8 RFCal_Log[12]; ++ ++ do { ++ u8 IRQ = 0; ++ int Timeout = 150; /* 1.5 s */ ++ while (true) { ++ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); ++ if ((IRQ & 0x80) != 0) ++ break; ++ Timeout -= 1; ++ if (Timeout == 0) { ++ status = -1; ++ break; ++ } ++ usleep_range(10000, 12000); ++ } ++ CHK_ERROR(status); ++ ++ state->Regs[FLO_MAX] = 0x0A; ++ CHK_ERROR(update_reg(state, FLO_MAX)); ++ ++ state->Regs[AGC1_1] &= ~0xC0; ++ if (state->m_bLTEnable) ++ state->Regs[AGC1_1] |= 0x80; /* LTEnable */ ++ ++ state->Regs[AGC1_1] |= (state->m_isMaster ? ++ MASTER_AGC1_6_15dB : ++ SLAVE_AGC1_6_15dB) << 6; ++ CHK_ERROR(update_reg(state, AGC1_1)); ++ ++ state->Regs[PSM_1] &= ~0xC0; ++ state->Regs[PSM_1] |= (state->m_isMaster ? ++ MASTER_PSM_AGC1 : SLAVE_PSM_AGC1) << 6; ++ CHK_ERROR(update_reg(state, PSM_1)); ++ ++ state->Regs[REFERENCE] |= 0x03; /* XTOUT = 3 */ ++ CHK_ERROR(update_reg(state, REFERENCE)); ++ ++ CHK_ERROR(read_regs(state, RFCAL_LOG_1, ++ RFCal_Log, sizeof(RFCal_Log))); ++ } while (0); ++ return status; ++} ++ ++static int PowerOn(struct tda_state *state) ++{ ++ state->Regs[POWER_STATE_2] &= ~0x0F; ++ update_reg(state, POWER_STATE_2); ++ /* Digital clock source = Sigma Delta */ ++ state->Regs[REFERENCE] |= 0x40; ++ update_reg(state, REFERENCE); ++ return 0; ++} ++ ++static int Standby(struct tda_state *state) ++{ ++ int status = 0; ++ ++ do { ++ /* Digital clock source = Quarz */ ++ state->Regs[REFERENCE] &= ~0x40; ++ CHK_ERROR(update_reg(state, REFERENCE)); ++ ++ state->Regs[POWER_STATE_2] &= ~0x0F; ++ state->Regs[POWER_STATE_2] |= state->m_isMaster ? 0x08 : 0x0E; ++ CHK_ERROR(update_reg(state, POWER_STATE_2)); ++ } while (0); ++ return status; ++} ++ ++static int attach_init(struct tda_state *state) ++{ ++ int stat = 0; ++ u8 Id[2]; ++ u8 PowerState = 0x00; ++ ++ state->m_Standard = HF_None; ++ ++ /* first read after cold reset sometimes fails on some cards, ++ try twice */ ++ stat = read_regs(state, ID_1, Id, sizeof(Id)); ++ stat = read_regs(state, ID_1, Id, sizeof(Id)); ++ if (stat < 0) ++ return -1; ++ ++ state->m_ID = ((Id[0] & 0x7F) << 8) | Id[1]; ++ state->m_isMaster = ((Id[0] & 0x80) != 0); ++ if (!state->m_isMaster) ++ state->m_bLTEnable = false; ++ ++ pr_info("tda18212dd: ChipID %04x %s\n", state->m_ID, ++ state->m_isMaster ? "master" : "slave"); ++ ++ if (state->m_ID != 18212) ++ return -1; ++ ++ stat = read_reg(state, POWER_STATE_1 , &PowerState); ++ if (stat < 0) ++ return stat; ++ ++ pr_info("tda18212dd: PowerState %02x\n", PowerState); ++ ++ if (state->m_isMaster) { ++ if (PowerState & 0x02) { ++ /* msleep for XTAL Calibration ++ (on a PC this should be long done) */ ++ u8 IRQStatus = 0; ++ int Timeout = 10; ++ ++ while (Timeout > 0) { ++ read_reg(state, IRQ_STATUS, &IRQStatus); ++ if (IRQStatus & 0x20) ++ break; ++ Timeout -= 1; ++ usleep_range(10000, 12000); ++ } ++ if ((IRQStatus & 0x20) == 0) ++ stat = -ETIMEDOUT; ++ } ++ } else { ++ write_reg(state, FLO_MAX, 0x00); ++ write_reg(state, CP_CURRENT, 0x68); ++ } ++ Read(state, state->Regs); ++ ++ PowerOn(state); ++ StartCalibration(state); ++ FinishCalibration(state); ++ Standby(state); ++ ++ { ++ u8 RFCal_Log[12]; ++ ++ read_regs(state, RFCAL_LOG_1, RFCal_Log, sizeof(RFCal_Log)); ++ pr_info("RFCal Log: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", ++ RFCal_Log[0], RFCal_Log[1], ++ RFCal_Log[2], RFCal_Log[3], ++ RFCal_Log[4], RFCal_Log[5], ++ RFCal_Log[6], RFCal_Log[7], ++ RFCal_Log[8], RFCal_Log[9], ++ RFCal_Log[10], RFCal_Log[11]); ++ } ++ return stat; ++} ++ ++static int PowerMeasurement(struct tda_state *state, u8 *pPowerLevel) ++{ ++ int status = 0; ++ ++ do { ++ u8 IRQ = 0; ++ int Timeout = 70; /* 700 ms */ ++ ++ state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */ ++ CHK_ERROR(update_reg(state, IRQ_CLEAR)); ++ ++ state->Regs[MSM_1] = 0x80; /* power measurement */ ++ state->Regs[MSM_2] = 0x01; /* Start MSM */ ++ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); ++ state->Regs[MSM_2] = 0x00; ++ ++ while (true) { ++ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); ++ if ((IRQ & 0x80) != 0) ++ break; ++ Timeout -= 1; ++ if (Timeout == 0) { ++ status = -1; ++ break; ++ } ++ usleep_range(10000, 12000); ++ } ++ CHK_ERROR(status); ++ ++ CHK_ERROR(read_reg1(state, INPUT_POWER_LEVEL)); ++ *pPowerLevel = state->Regs[INPUT_POWER_LEVEL] & 0x7F; ++ ++ if (*pPowerLevel > 110) ++ *pPowerLevel = 110; ++ } while (0); ++ /* pr_info("PL %d\n", *pPowerLevel); */ ++ return status; ++} ++ ++static int SetFrequency(struct tda_state *state, u32 Frequency, ++ enum HF_Standard Standard) ++{ ++ int status = 0; ++ struct SStandardParams *StandardParams; ++ u32 f = Frequency / 1000; ++ u8 IRQ = 0; ++ int Timeout = 25; /* 250 ms */ ++ u32 fRatio = Frequency / 16000000; ++ u32 fDelta = Frequency - fRatio * 16000000; ++ ++ if (Standard < HF_DVBT_6MHZ || Standard > HF_DVBC_8MHZ) ++ return -EINVAL; ++ StandardParams = &m_StandardTable[Standard - HF_DVBT_6MHZ]; ++ ++ if (StandardParams->m_IFFrequency == 0) ++ return -EINVAL; ++ state->m_Standard = HF_None; ++ state->m_Frequency = 0; ++ ++ do { ++ /* IF Level */ ++ state->Regs[IF_AGC] = (Standard >= HF_DVBC_6MHZ) ? ++ state->m_IFLevelDVBC : state->m_IFLevelDVBT; ++ CHK_ERROR(update_reg(state, IF_AGC)); ++ ++ /* Standard setup */ ++ state->Regs[IF_1] = StandardParams->m_IF_1; ++ CHK_ERROR(update_reg(state, IF_1)); ++ ++ state->Regs[IR_MIXER_2] = (state->Regs[IR_MIXER_2] & ~0x03) | ++ StandardParams->m_IR_MIXER_2; ++ CHK_ERROR(update_reg(state, IR_MIXER_2)); ++ ++ state->Regs[AGC1_1] = (state->Regs[AGC1_1] & ~0x0F) | ++ StandardParams->m_AGC1_1; ++ CHK_ERROR(update_reg(state, AGC1_1)); ++ ++ state->Regs[AGC2_1] = (state->Regs[AGC2_1] & ~0x0F) | ++ StandardParams->m_AGC2_1; ++ CHK_ERROR(update_reg(state, AGC2_1)); ++ ++ state->Regs[RF_AGC_1] &= ~0xEF; ++ if (Frequency < 291000000) ++ state->Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_Low; ++ else ++ state->Regs[RF_AGC_1] |= ++ StandardParams->m_RF_AGC_1_High; ++ CHK_ERROR(update_reg(state, RF_AGC_1)); ++ ++ state->Regs[IR_MIXER_1] = ++ (state->Regs[IR_MIXER_1] & ~0x0F) | ++ StandardParams->m_IR_MIXER_1; ++ CHK_ERROR(update_reg(state, IR_MIXER_1)); ++ ++ state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x1F) | ++ StandardParams->m_AGC5_1; ++ CHK_ERROR(update_reg(state, AGC5_1)); ++ ++ state->Regs[AGCK_1] = (state->Regs[AGCK_1] & ~0x0F) | ++ StandardParams->m_AGCK_1; ++ CHK_ERROR(update_reg(state, AGCK_1)); ++ ++ state->Regs[PSM_1] = (state->Regs[PSM_1] & ~0x20) | ++ StandardParams->m_PSM_1; ++ CHK_ERROR(update_reg(state, PSM_1)); ++ ++ state->Regs[IF_FREQUENCY_1] = (StandardParams->m_IFFrequency / ++ 50000); ++ CHK_ERROR(update_reg(state, IF_FREQUENCY_1)); ++ ++ if (state->m_isMaster && StandardParams->m_LTO_STO_immune) { ++ u8 tmp; ++ u8 RF_Filter_Gain; ++ ++ CHK_ERROR(read_reg(state, RF_AGC_GAIN_1, &tmp)); ++ RF_Filter_Gain = (tmp & 0x30) >> 4; ++ ++ state->Regs[RF_FILTER_1] = ++ (state->Regs[RF_FILTER_1] & ~0x0C) | ++ (RF_Filter_Gain << 2); ++ CHK_ERROR(update_reg(state, RF_FILTER_1)); ++ ++ state->Regs[RF_FILTER_1] |= 0x10; /* Force */ ++ CHK_ERROR(update_reg(state, RF_FILTER_1)); ++ ++ while (RF_Filter_Gain != 0) { ++ RF_Filter_Gain -= 1; ++ state->Regs[RF_FILTER_1] = ++ (state->Regs[RF_FILTER_1] & ~0x0C) | ++ (RF_Filter_Gain << 2); ++ CHK_ERROR(update_reg(state, RF_FILTER_1)); ++ usleep_range(10000, 12000); ++ } ++ CHK_ERROR(status); ++ ++ state->Regs[RF_AGC_1] |= 0x08; ++ CHK_ERROR(update_reg(state, RF_AGC_1)); ++ } ++ ++ state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */ ++ CHK_ERROR(update_reg(state, IRQ_CLEAR)); ++ ++ CHK_ERROR(PowerOn(state)); ++ ++ state->Regs[RF_FREQUENCY_1] = ((f >> 16) & 0xFF); ++ state->Regs[RF_FREQUENCY_2] = ((f >> 8) & 0xFF); ++ state->Regs[RF_FREQUENCY_3] = (f & 0xFF); ++ CHK_ERROR(update_regs(state, RF_FREQUENCY_1, RF_FREQUENCY_3)); ++ ++ state->Regs[MSM_1] = 0x41; /* Tune */ ++ state->Regs[MSM_2] = 0x01; /* Start MSM */ ++ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); ++ state->Regs[MSM_2] = 0x00; ++ ++ while (true) { ++ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); ++ if ((IRQ & 0x80) != 0) ++ break; ++ Timeout -= 1; ++ if (Timeout == 0) { ++ status = -1; ++ break; ++ } ++ usleep_range(10000, 12000); ++ } ++ CHK_ERROR(status); ++ ++ if (state->m_isMaster && StandardParams->m_LTO_STO_immune) { ++ state->Regs[RF_AGC_1] &= ~0x08; ++ CHK_ERROR(update_reg(state, RF_AGC_1)); ++ ++ msleep(50); ++ ++ state->Regs[RF_FILTER_1] &= ~0x10; /* remove force */ ++ CHK_ERROR(update_reg(state, RF_FILTER_1)); ++ } ++ ++ /* Spur reduction */ ++ ++ if (Frequency < 72000000) ++ state->Regs[REFERENCE] |= 0x40; /* Set digital clock */ ++ else if (Frequency < 104000000) ++ state->Regs[REFERENCE] &= ~0x40; /*Clear digital clock*/ ++ else if (Frequency < 120000000) ++ state->Regs[REFERENCE] |= 0x40; /* Set digital clock */ ++ else { ++ if (fDelta <= 8000000) { ++ /* Clear or set digital clock */ ++ if (fRatio & 1) ++ state->Regs[REFERENCE] &= ~0x40; ++ else ++ state->Regs[REFERENCE] |= 0x40; ++ } else { ++ /* Set or clear digital clock */ ++ if (fRatio & 1) ++ state->Regs[REFERENCE] |= 0x40; ++ else ++ state->Regs[REFERENCE] &= ~0x40; ++ } ++ ++ } ++ CHK_ERROR(update_reg(state, REFERENCE)); ++ ++ if (StandardParams->m_AGC1_Freeze && state->m_bEnableFreeze) { ++ u8 tmp; ++ int AGC1GainMin = 0; ++ int nSteps = 10; ++ int Step = 0; ++ ++ CHK_ERROR(read_reg(state, AGC1_2, &tmp)); ++ if ((tmp & 0x80) == 0) { ++ state->Regs[AGC1_2] |= 0x80; /* Loop off */ ++ CHK_ERROR(update_reg(state, AGC1_2)); ++ state->Regs[AGC1_2] |= 0x10; /* Force gain */ ++ CHK_ERROR(update_reg(state, AGC1_2)); ++ } ++ /* Adapt */ ++ if (state->Regs[AGC1_1] & 0x40) { /* AGC1_6_15dB set */ ++ AGC1GainMin = 6; ++ nSteps = 4; ++ } ++ while (Step < nSteps) { ++ int Down = 0; ++ int Up = 0, i; ++ u8 AGC1_Gain; ++ ++ Step = Step + 1; ++ ++ for (i = 0; i < 40; i += 1) { ++ CHK_ERROR(read_reg(state, AGC_DET_OUT, ++ &tmp)); ++ Up += (tmp & 0x02) ? 1 : -4; ++ Down += (tmp & 0x01) ? 14 : -1; ++ usleep_range(1000, 2000); ++ } ++ CHK_ERROR(status); ++ AGC1_Gain = (state->Regs[AGC1_2] & 0x0F); ++ if (Up >= 15 && AGC1_Gain != 9) { ++ state->Regs[AGC1_2] = ++ (state->Regs[AGC1_2] & ~0x0F) | ++ (AGC1_Gain + 1); ++ CHK_ERROR(update_reg(state, AGC1_2)); ++ } else if (Down >= 10 && ++ AGC1_Gain != AGC1GainMin) { ++ state->Regs[AGC1_2] = ++ (state->Regs[AGC1_2] & ~0x0F) | ++ (AGC1_Gain - 1); ++ CHK_ERROR(update_reg(state, AGC1_2)); ++ } else ++ Step = nSteps; ++ } ++ } else { ++ state->Regs[AGC1_2] &= ~0x10; /* unforce gain */ ++ CHK_ERROR(update_reg(state, AGC1_2)); ++ state->Regs[AGC1_2] &= ~0x80; /* Loop on */ ++ CHK_ERROR(update_reg(state, AGC1_2)); ++ } ++ ++ state->m_Standard = Standard; ++ state->m_Frequency = Frequency; ++ ++ if (state->m_bPowerMeasurement) ++ PowerMeasurement(state, &state->m_LastPowerLevel); ++ } while (0); ++ ++ return status; ++} ++ ++static int sleep(struct dvb_frontend *fe) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ ++ Standby(state); ++ return 0; ++} ++ ++static int init(struct dvb_frontend *fe) ++{ ++ /* struct tda_state *state = fe->tuner_priv; */ ++ return 0; ++} ++ ++static int release(struct dvb_frontend *fe) ++{ ++ kfree(fe->tuner_priv); ++ fe->tuner_priv = NULL; ++ return 0; ++} ++ ++#ifndef USE_API3 ++static int set_params(struct dvb_frontend *fe) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ int status = 0; ++ int Standard; ++ u32 bw; ++ ++ bw = (p->bandwidth_hz + 999999) / 1000000; ++ state->m_Frequency = p->frequency; ++ /*pr_info("tuner bw=%u freq=%u\n", bw, state->m_Frequency);*/ ++ if (p->delivery_system == SYS_DVBT || ++ p->delivery_system == SYS_DVBT2 || ++ p->delivery_system == SYS_ISDBT) { ++ switch (bw) { ++ case 6: ++ Standard = HF_DVBT_6MHZ; ++ break; ++ case 7: ++ Standard = HF_DVBT_7MHZ; ++ break; ++ default: ++ case 8: ++ Standard = HF_DVBT_8MHZ; ++ break; ++ } ++ } else if (p->delivery_system == SYS_DVBC_ANNEX_A) { ++ switch (bw) { ++ case 6: ++ Standard = HF_DVBC_6MHZ; ++ break; ++ case 7: ++ Standard = HF_DVBC_7MHZ; ++ break; ++ default: ++ case 8: ++ Standard = HF_DVBC_8MHZ; ++ break; ++ } ++ } else ++ return -EINVAL; ++ ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ SetFrequency(state, state->m_Frequency, Standard); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ ++ return status; ++} ++#else ++static int set_params(struct dvb_frontend *fe, ++ struct dvb_frontend_parameters *params) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ int status = 0; ++ int Standard; ++ ++ state->m_Frequency = params->frequency; ++ ++ if (fe->ops.info.type == FE_OFDM) ++ switch (params->u.ofdm.bandwidth) { ++ case BANDWIDTH_6_MHZ: ++ Standard = HF_DVBT_6MHZ; ++ break; ++ case BANDWIDTH_7_MHZ: ++ Standard = HF_DVBT_7MHZ; ++ break; ++ default: ++ case BANDWIDTH_8_MHZ: ++ Standard = HF_DVBT_8MHZ; ++ break; ++ } ++ else if (fe->ops.info.type == FE_QAM) { ++ Standard = HF_DVBC_8MHZ; ++ } else ++ return -EINVAL; ++ ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ SetFrequency(state, state->m_Frequency, Standard); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ ++ return status; ++} ++#endif ++ ++static int get_frequency(struct dvb_frontend *fe, u32 *frequency) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ ++ *frequency = state->IF; ++ return 0; ++} ++ ++static int get_rf_strength(struct dvb_frontend *fe, u16 *st) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ ++ *st = state->m_LastPowerLevel; ++ return 0; ++} ++ ++static int get_if(struct dvb_frontend *fe, u32 *frequency) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ ++ state->IF = 0; ++ if (state->m_Standard < HF_DVBT_6MHZ || ++ state->m_Standard > HF_DVBC_8MHZ) ++ return 0; ++ state->IF = m_StandardTable[state->m_Standard - ++ HF_DVBT_6MHZ].m_IFFrequency; ++ *frequency = state->IF; ++ return 0; ++} ++ ++static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) ++{ ++ /* struct tda_state *state = fe->tuner_priv; */ ++ /* *bandwidth = priv->bandwidth; */ ++ return 0; ++} ++ ++ ++static struct dvb_tuner_ops tuner_ops = { ++ .info = { ++ .name = "NXP TDA18212", ++ .frequency_min = 47125000, ++ .frequency_max = 865000000, ++ .frequency_step = 62500 ++ }, ++ .init = init, ++ .sleep = sleep, ++ .set_params = set_params, ++ .release = release, ++ .get_frequency = get_frequency, ++ .get_if_frequency = get_if, ++ .get_bandwidth = get_bandwidth, ++ .get_rf_strength = get_rf_strength, ++}; ++ ++struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, u8 adr) ++{ ++ struct tda_state *state; ++ int stat; ++ ++ state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ state->adr = adr; ++ state->i2c = i2c; ++ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); ++ init_state(state); ++ ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ stat = attach_init(state); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ if (stat < 0) { ++ kfree(state); ++ return 0; ++ } ++ fe->tuner_priv = state; ++ return fe; ++} ++EXPORT_SYMBOL_GPL(tda18212dd_attach); ++ ++MODULE_DESCRIPTION("TDA18212 driver"); ++MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); ++MODULE_LICENSE("GPL"); ++ ++/* ++ * Local variables: ++ * c-basic-offset: 8 ++ * End: ++ */ diff --git a/drivers/media/dvb-frontends/tda18212dd.h b/drivers/media/dvb-frontends/tda18212dd.h new file mode 100644 index 0000000..687fab4a @@ -16005,7 +22432,7 @@ index dd84f7b..1389c74 100644 struct i2c_adapter *i2c, u8 adr); #else diff --git a/drivers/media/pci/ddbridge/Kconfig b/drivers/media/pci/ddbridge/Kconfig -index 44e5dc1..0c3820e 100644 +index 44e5dc1..d283008 100644 --- a/drivers/media/pci/ddbridge/Kconfig +++ b/drivers/media/pci/ddbridge/Kconfig @@ -1,18 +1,23 @@ @@ -16032,7 +22459,7 @@ index 44e5dc1..0c3820e 100644 + - DuoFlex S2 + - DuoFlex CT + - cineS2(v6.x) -+ - cineCT(v6.x) ++ - cineCT(v6.x, v7) Say Y if you own such a card and want to use it. diff --git a/drivers/media/pci/ddbridge/Makefile b/drivers/media/pci/ddbridge/Makefile @@ -16049,7 +22476,7 @@ index 7446c8b..2610161 100644 ccflags-y += -Idrivers/media/dvb-core/ diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c -index fb52bda..d68ccee 100644 +index fb52bda..c85796a 100644 --- a/drivers/media/pci/ddbridge/ddbridge-core.c +++ b/drivers/media/pci/ddbridge/ddbridge-core.c @@ -1,7 +1,8 @@ @@ -16554,7 +22981,7 @@ index fb52bda..d68ccee 100644 return 0; } -@@ -331,287 +299,815 @@ static void ddb_buffers_free(struct ddb *dev) +@@ -331,287 +299,839 @@ static void ddb_buffers_free(struct ddb *dev) for (i = 0; i < dev->info->port_num; i++) { port = &dev->port[i]; @@ -16601,6 +23028,7 @@ index fb52bda..d68ccee 100644 + spin_lock_irq(&output->dma->lock); + output->dma->cbuf = 0; + output->dma->coff = 0; ++ output->dma->stat = 0; + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); + } + if (output->port->class == DDB_PORT_MOD) @@ -16679,7 +23107,7 @@ index fb52bda..d68ccee 100644 + input->dma->running = 0; + spin_unlock_irq(&input->dma->lock); + } -+ /* pr_info("input_stop %d.%d\n", dev->nr, input->nr); */ ++ /*pr_info("input_stop %d.%d\n", dev->nr, input->nr);*/ } -static void ddb_output_start(struct ddb_output *output) @@ -16711,6 +23139,7 @@ index fb52bda..d68ccee 100644 + spin_lock_irq(&input->dma->lock); + input->dma->cbuf = 0; + input->dma->coff = 0; ++ input->dma->stat = 0; + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); + } + ddbwritel(dev, 0, TS_INPUT_CONTROL2(input->nr)); @@ -16733,7 +23162,7 @@ index fb52bda..d68ccee 100644 + input->dma->running = 1; + spin_unlock_irq(&input->dma->lock); + } -+ /* pr_info("input_start %d.%d\n", dev->nr, input->nr); */ ++ /*pr_info("input_start %d.%d\n", dev->nr, input->nr);*/ } -static void ddb_output_stop(struct ddb_output *output) @@ -16822,6 +23251,7 @@ index fb52bda..d68ccee 100644 return 0; } ++#if 0 +static u32 ddb_dma_free(struct ddb_dma *dma) +{ + u32 idx, off, stat = dma->stat; @@ -16838,6 +23268,7 @@ index fb52bda..d68ccee 100644 + diff += dma->num * dma->size; + return diff; +} ++#endif + static ssize_t ddb_output_write(struct ddb_output *output, const u8 *buf, size_t count) @@ -16910,6 +23341,7 @@ index fb52bda..d68ccee 100644 return count - left; } ++#if 0 +static u32 ddb_input_free_bytes(struct ddb_input *input) +{ + struct ddb *dev = input->port->dev; @@ -16926,6 +23358,8 @@ index fb52bda..d68ccee 100644 + return 0; +} + ++ ++ +static s32 ddb_output_used_bufs(struct ddb_output *output) +{ + u32 idx, off, stat, ctrl; @@ -16980,6 +23414,7 @@ index fb52bda..d68ccee 100644 + return 1; + return 0; +} ++#endif + static u32 ddb_input_avail(struct ddb_input *input) { @@ -17000,7 +23435,7 @@ index fb52bda..d68ccee 100644 return 0; } - if (input->cbuf != idx) -+ if (input->dma->cbuf != idx || off < input->dma->coff) ++ if (input->dma->cbuf != idx) return 188; return 0; } @@ -17110,7 +23545,8 @@ index fb52bda..d68ccee 100644 + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; + struct ddb *dev = output->port->dev; -+ int left, read; ++ size_t left = count; ++ int stat; - if (enable) { - mutex_lock(&port->i2c_gate_lock); @@ -17120,8 +23556,6 @@ index fb52bda..d68ccee 100644 - mutex_unlock(&port->i2c_gate_lock); + if (!dev->has_dma) + return -EINVAL; -+ count -= count % 188; -+ left = count; + while (left) { + if (ddb_input_avail(input) < 188) { + if (file->f_flags & O_NONBLOCK) @@ -17131,12 +23565,14 @@ index fb52bda..d68ccee 100644 + ddb_input_avail(input) >= 188) < 0) + break; + } -+ read = ddb_input_read(input, buf, left); -+ left -= read; -+ buf += read; ++ stat = ddb_input_read(input, buf, left); ++ if (stat < 0) ++ return stat; ++ left -= stat; ++ buf += stat; } - return status; -+ return (left == count) ? -EAGAIN : (count - left); ++ return (count && (left == count)) ? -EAGAIN : (count - left); } -static int demod_attach_drxk(struct ddb_input *input) @@ -17175,15 +23611,7 @@ index fb52bda..d68ccee 100644 -static int tuner_attach_tda18271(struct ddb_input *input) +static int ts_release(struct inode *inode, struct file *file) - { -- struct i2c_adapter *i2c = &input->port->i2c->adap; -- struct dvb_frontend *fe; -- -- if (input->fe->ops.i2c_gate_ctrl) -- input->fe->ops.i2c_gate_ctrl(input->fe, 1); -- fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); -- if (!fe) { -- printk(KERN_ERR "No TDA18271 found!\n"); ++{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; @@ -17230,7 +23658,6 @@ index fb52bda..d68ccee 100644 +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; -+ struct ddb_input *input = output->port->input[0]; + + if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + if (!output) @@ -17337,28 +23764,37 @@ index fb52bda..d68ccee 100644 + +#if IS_ENABLED(CONFIG_DVB_DRXK) +static int demod_attach_drxk(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; + { + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ struct dvb_frontend *fe; + struct dvb_frontend *fe; + struct drxk_config config; + + memset(&config, 0, sizeof(config)); + config.adr = 0x29 + (input->nr & 1); + config.microcode_name = "drxk_a3.mc"; -+ + +- if (input->fe->ops.i2c_gate_ctrl) +- input->fe->ops.i2c_gate_ctrl(input->fe, 1); +- fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); + fe = dvb->fe = dvb_attach(drxk_attach, &config, i2c); -+ if (!fe) { + if (!fe) { +- printk(KERN_ERR "No TDA18271 found!\n"); + pr_err("No DRXK found!\n"); -+ return -ENODEV; -+ } + return -ENODEV; + } +- if (input->fe->ops.i2c_gate_ctrl) +- input->fe->ops.i2c_gate_ctrl(input->fe, 0); + fe->sec_priv = input; + dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; + fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} + return 0; + } +#endif -+ + +-/******************************************************************************/ +-/******************************************************************************/ +-/******************************************************************************/ +#if 0 +struct stv0367_config stv0367_0 = { + .demod_address = 0x1f, @@ -17407,16 +23843,32 @@ index fb52bda..d68ccee 100644 + .adr = 0x6d, +}; + -+static int demod_attach_cxd2843(struct ddb_input *input) ++struct cxd2843_cfg cxd2843p_0 = { ++ .adr = 0x6c, ++ .parallel = 1, ++}; ++ ++struct cxd2843_cfg cxd2843p_1 = { ++ .adr = 0x6d, ++ .parallel = 1, ++}; ++ ++static int demod_attach_cxd2843(struct ddb_input *input, int par) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + -+ fe = dvb->fe = dvb_attach(cxd2843_attach, i2c, -+ (input->nr & 1) ? &cxd2843_1 : &cxd2843_0); ++ if (par) ++ fe = dvb->fe = dvb_attach(cxd2843_attach, i2c, ++ (input->nr & 1) ? ++ &cxd2843p_1 : &cxd2843p_0); ++ else ++ fe = dvb->fe = dvb_attach(cxd2843_attach, i2c, ++ (input->nr & 1) ? ++ &cxd2843_1 : &cxd2843_0); + if (!dvb->fe) { -+ pr_err("No cxd2843 found!\n"); ++ pr_err("No cxd2837/38/43 found!\n"); + return -ENODEV; + } + fe->sec_priv = input; @@ -17508,24 +23960,19 @@ index fb52bda..d68ccee 100644 + fe = dvb_attach(tda18212_attach, dvb->fe, i2c, cfg); + if (!fe) { + pr_err("No TDA18212 found!\n"); - return -ENODEV; - } -- if (input->fe->ops.i2c_gate_ctrl) -- input->fe->ops.i2c_gate_ctrl(input->fe, 0); - return 0; - } ++ return -ENODEV; ++ } ++ return 0; ++} +#endif - --/******************************************************************************/ --/******************************************************************************/ --/******************************************************************************/ ++ +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ static struct stv090x_config stv0900 = { .device = STV0900, -@@ -624,6 +1120,9 @@ static struct stv090x_config stv0900 = { +@@ -624,6 +1144,9 @@ static struct stv090x_config stv0900 = { .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, @@ -17535,7 +23982,7 @@ index fb52bda..d68ccee 100644 .repeater_level = STV090x_RPTLEVEL_16, .adc1_range = STV090x_ADC_1Vpp, -@@ -643,6 +1142,9 @@ static struct stv090x_config stv0900_aa = { +@@ -643,6 +1166,9 @@ static struct stv090x_config stv0900_aa = { .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, @@ -17545,7 +23992,7 @@ index fb52bda..d68ccee 100644 .repeater_level = STV090x_RPTLEVEL_16, .adc1_range = STV090x_ADC_1Vpp, -@@ -667,18 +1169,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) +@@ -667,18 +1193,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) { struct i2c_adapter *i2c = &input->port->i2c->adap; struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; @@ -17572,7 +24019,7 @@ index fb52bda..d68ccee 100644 return -ENODEV; } return 0; -@@ -687,18 +1190,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) +@@ -687,18 +1214,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) static int tuner_attach_stv6110(struct ddb_input *input, int type) { struct i2c_adapter *i2c = &input->port->i2c->adap; @@ -17596,9 +24043,51 @@ index fb52bda..d68ccee 100644 feconf->tuner_init = ctl->tuner_init; feconf->tuner_sleep = ctl->tuner_sleep; -@@ -716,9 +1220,9 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) +@@ -715,10 +1243,51 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) + return 0; } ++static struct stv0910_cfg stv0910 = { ++ .adr = 0x68, ++ .parallel = 1, ++ .rptlvl = 4, ++ .clk = 30000000, ++}; ++ ++static int demod_attach_stv0910(struct ddb_input *input, int type) ++{ ++ struct i2c_adapter *i2c = &input->port->i2c->adap; ++ ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; ++ ++ dvb->fe = dvb_attach(stv0910_attach, i2c, &stv0910, (input->nr & 1)); ++ if (!dvb->fe) { ++ pr_err("No STV0910 found!\n"); ++ return -ENODEV; ++ } ++ if (!dvb_attach(lnbh25_attach, dvb->fe, i2c, ++ (input->nr & 1) ? 0x09 : 0x08)) { ++ pr_err("No LNBH25 found!\n"); ++ return -ENODEV; ++ } ++ return 0; ++} ++ ++static int tuner_attach_stv6111(struct ddb_input *input) ++{ ++ struct i2c_adapter *i2c = &input->port->i2c->adap; ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; ++ struct dvb_frontend *fe; ++ ++ fe = dvb_attach(stv6111_attach, dvb->fe, i2c, ++ (input->nr & 1) ? 0x63 : 0x60); ++ if (!fe) { ++ pr_err("No STV6111 found!\n"); ++ return -ENODEV; ++ } ++ return 0; ++} ++ static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, - int (*start_feed)(struct dvb_demux_feed *), - int (*stop_feed)(struct dvb_demux_feed *), @@ -17609,7 +24098,7 @@ index fb52bda..d68ccee 100644 { dvbdemux->priv = priv; -@@ -734,10 +1238,10 @@ static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, +@@ -734,10 +1303,10 @@ static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, } static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, @@ -17624,10 +24113,11 @@ index fb52bda..d68ccee 100644 { int ret; -@@ -755,291 +1259,671 @@ static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, +@@ -755,291 +1324,727 @@ static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); } ++#if 0 +static int start_input(struct ddb_input *input) +{ + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; @@ -17648,6 +24138,7 @@ index fb52bda..d68ccee 100644 + ddb_input_stop_all(input); + return 0; +} ++#endif + static int start_feed(struct dvb_demux_feed *dvbdmxfeed) { @@ -17708,15 +24199,18 @@ index fb52bda..d68ccee 100644 + dvb_unregister_frontend(dvb->fe2); + if (dvb->fe) + dvb_unregister_frontend(dvb->fe); ++ /* fallthrough */ + case 0x30: + dvb_frontend_detach(dvb->fe); + dvb->fe = dvb->fe2 = NULL; -+#ifdef DVB_NETSTREAM ++ /* fallthrough */ + case 0x21: -+ dvb_netstream_release(&dvb->dvbns); -+#endif ++ if (input->port->dev->ns_num) ++ dvb_netstream_release(&dvb->dvbns); ++ /* fallthrough */ + case 0x20: + dvb_net_release(&dvb->dvbnet); ++ /* fallthrough */ + case 0x11: dvbdemux->dmx.close(&dvbdemux->dmx); dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, @@ -17727,14 +24221,18 @@ index fb52bda..d68ccee 100644 - dvb_dmxdev_release(&input->dmxdev); + &dvb->mem_frontend); + dvb_dmxdev_release(&dvb->dmxdev); ++ /* fallthrough */ + case 0x10: + dvb_dmx_release(&dvb->demux); ++ /* fallthrough */ + case 0x01: + break; + } + dvb->attached = 0x00; +} -+ + +- case 2: +- dvb_dmx_release(&input->demux); +static int dvb_register_adapters(struct ddb *dev) +{ + int i, ret = 0; @@ -17757,7 +24255,9 @@ index fb52bda..d68ccee 100644 + } + return 0; + } -+ + +- case 1: +- dvb_unregister_adapter(adap); + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + switch (port->class) { @@ -17821,16 +24321,12 @@ index fb52bda..d68ccee 100644 + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; - -- case 2: -- dvb_dmx_release(&input->demux); ++ + dvb = &port->dvb[0]; + if (dvb->adap_registered) + dvb_unregister_adapter(dvb->adap); + dvb->adap_registered = 0; - -- case 1: -- dvb_unregister_adapter(adap); ++ + dvb = &port->dvb[1]; + if (dvb->adap_registered) + dvb_unregister_adapter(dvb->adap); @@ -17890,12 +24386,12 @@ index fb52bda..d68ccee 100644 + dvb->attached = 0x20; - input->fe = 0; -+#ifdef DVB_NETSTREAM -+ ret = netstream_init(input); -+ if (ret < 0) -+ return ret; -+ dvb->attached = 0x21; -+#endif ++ if (input->port->dev->ns_num) { ++ ret = netstream_init(input); ++ if (ret < 0) ++ return ret; ++ dvb->attached = 0x21; ++ } + dvb->fe = dvb->fe2 = 0; switch (port->type) { case DDB_TUNER_DVBS_ST: @@ -17907,6 +24403,12 @@ index fb52bda..d68ccee 100644 - if (dvb_register_frontend(adap, input->fe) < 0) - return -ENODEV; - } ++ break; ++ case DDB_TUNER_DVBS_STV0910: ++ if (demod_attach_stv0910(input, 0) < 0) ++ return -ENODEV; ++ if (tuner_attach_stv6111(input) < 0) ++ return -ENODEV; break; case DDB_TUNER_DVBS_ST_AA: if (demod_attach_stv0900(input, 1) < 0) @@ -17925,16 +24427,7 @@ index fb52bda..d68ccee 100644 if (tuner_attach_tda18271(input) < 0) return -ENODEV; - if (dvb_register_frontend(adap, input->fe) < 0) -- return -ENODEV; -- if (input->fe2) { -- if (dvb_register_frontend(adap, input->fe2) < 0) -- return -ENODEV; -- input->fe2->tuner_priv = input->fe->tuner_priv; -- memcpy(&input->fe2->ops.tuner_ops, -- &input->fe->ops.tuner_ops, -- sizeof(struct dvb_tuner_ops)); -- } - break; ++ break; +#endif + case DDB_TUNER_DVBCT_ST: + if (demod_attach_stv0367dd(input) < 0) @@ -17945,20 +24438,36 @@ index fb52bda..d68ccee 100644 + case DDB_TUNER_DVBCT2_SONY: + case DDB_TUNER_DVBC2T2_SONY: + case DDB_TUNER_ISDBT_SONY: -+ if (demod_attach_cxd2843(input) < 0) ++ if (demod_attach_cxd2843(input, 0) < 0) + return -ENODEV; + if (tuner_attach_tda18212dd(input) < 0) + return -ENODEV; + break; ++ case DDB_TUNER_DVBCT2_SONY_P: ++ case DDB_TUNER_DVBC2T2_SONY_P: ++ case DDB_TUNER_ISDBT_SONY_P: ++ if (demod_attach_cxd2843(input, 1) < 0) ++ return -ENODEV; ++ if (tuner_attach_tda18212dd(input) < 0) + return -ENODEV; +- if (input->fe2) { +- if (dvb_register_frontend(adap, input->fe2) < 0) +- return -ENODEV; +- input->fe2->tuner_priv = input->fe->tuner_priv; +- memcpy(&input->fe2->ops.tuner_ops, +- &input->fe->ops.tuner_ops, +- sizeof(struct dvb_tuner_ops)); +- } + break; + default: + return 0; -+ } + } +- input->attached = 5; + dvb->attached = 0x30; + if (dvb->fe) { + if (dvb_register_frontend(adap, dvb->fe) < 0) + return -ENODEV; - } -- input->attached = 5; ++ } + if (dvb->fe2) { + if (dvb_register_frontend(adap, dvb->fe2) < 0) + return -ENODEV; @@ -18039,15 +24548,24 @@ index fb52bda..d68ccee 100644 - return read; - left -= read; - buf += read; +- } +- return (left == count) ? -EAGAIN : (count - left); + if (data[0] == 0x02 && data[1] == 0x2b && data[3] == 0x43) + *type = 2; + else + *type = 1; + return 1; -+} -+ -+static int port_has_mach(struct ddb_port *port, u8 *id) -+{ + } + +-static unsigned int ts_poll(struct file *file, poll_table *wait) ++static int port_has_xo2(struct ddb_port *port, u8 *id) + { +- /* +- struct dvb_device *dvbdev = file->private_data; +- struct ddb_output *output = dvbdev->priv; +- struct ddb_input *input = output->port->input[0]; +- */ +- unsigned int mask = 0; + u8 val; + u8 probe[1] = { 0x00 }, data[4]; + struct i2c_msg msgs[2] = {{ .addr = 0x10, .flags = 0, @@ -18105,13 +24623,20 @@ index fb52bda..d68ccee 100644 + return 0; + return 1; +} -+ + + #if 0 +- if (data_avail_to_read) +- mask |= POLLIN | POLLRDNORM; +- if (data_avail_to_write) +- mask |= POLLOUT | POLLWRNORM; +static int init_xo2_old(struct ddb_port *port) +{ + struct i2c_adapter *i2c = &port->i2c->adap; + u8 val; + int res; -+ + +- poll_wait(file, &read_queue, wait); +- poll_wait(file, &write_queue, wait); + res = i2c_read_reg(i2c, 0x10, 0x04, &val); + if (res < 0) + return res; @@ -18119,8 +24644,7 @@ index fb52bda..d68ccee 100644 + if (val != 0x02) { + pr_info("Port %d: invalid XO2\n", port->nr); + return -1; - } -- return (left == count) ? -EAGAIN : (count - left); ++ } + i2c_write_reg(i2c, 0x10, 0xc0, 0x00); /* Disable XO2 I2C master */ + + i2c_read_reg(i2c, 0x10, 0x08, &val); @@ -18138,34 +24662,20 @@ index fb52bda..d68ccee 100644 + i2c_write_reg(i2c, 0x10, 0x08, 0x87); + + return 0; - } - --static unsigned int ts_poll(struct file *file, poll_table *wait) ++} + #endif +- return mask; ++ +static int init_xo2(struct ddb_port *port) - { -- /* -- struct dvb_device *dvbdev = file->private_data; -- struct ddb_output *output = dvbdev->priv; -- struct ddb_input *input = output->port->input[0]; -- */ -- unsigned int mask = 0; ++{ + struct i2c_adapter *i2c = &port->i2c->adap; + u8 val, data[2]; + int res; - --#if 0 -- if (data_avail_to_read) -- mask |= POLLIN | POLLRDNORM; -- if (data_avail_to_write) -- mask |= POLLOUT | POLLWRNORM; ++ + res = i2c_read_regs(i2c, 0x10, 0x04, data, 2); + if (res < 0) + return res; - -- poll_wait(file, &read_queue, wait); -- poll_wait(file, &write_queue, wait); --#endif -- return mask; ++ + if (data[0] != 0x01) { + pr_info("Port %d: invalid XO2\n", port->nr); + return -1; @@ -18196,29 +24706,55 @@ index fb52bda..d68ccee 100644 - .release = dvb_generic_release, - .poll = ts_poll, - .mmap = 0, ++static int port_has_cxd28xx(struct ddb_port *port, u8 *id) ++{ ++ struct i2c_adapter *i2c = &port->i2c->adap; ++ int status; ++ ++ status = i2c_write_reg(&port->i2c->adap, 0x6e, 0, 0); ++ if (status) ++ return 0; ++ status = i2c_read_reg(i2c, 0x6e, 0xfd, id); ++ if (status) ++ return 0; ++ return 1; ++} ++ ++static char *xo2names[] = { ++ "DUAL DVB-S2", "DUAL DVB-C/T/T2", ++ "DUAL DVB-ISDBT", "DUAL DVB-C/C2/T/T2", ++ "DUAL ATSC", "DUAL DVB-C/C2/T/T2", ++ "", "" + }; + +-static struct dvb_device dvbdev_ci = { +- .priv = 0, +- .readers = -1, +- .writers = -1, +- .users = -1, +- .fops = &ci_fops, -}; +static void ddb_port_probe(struct ddb_port *port) +{ + struct ddb *dev = port->dev; -+ char *modname = "NO MODULE"; + u8 id; + ++ port->name = "NO MODULE"; + port->class = DDB_PORT_NONE; + + if (dev->info->type == DDB_MOD) { -+ modname = "MOD"; ++ port->name = "MOD"; + port->class = DDB_PORT_MOD; -+ pr_info("Port %d: MOD\n", port->nr); + return; + } + + if (port->nr > 1 && dev->info->type == DDB_OCTOPUS_CI) { -+ modname = "CI internal"; ++ port->name = "CI internal"; + port->class = DDB_PORT_CI; + port->type = DDB_CI_INTERNAL; + } else if (port_has_cxd(port, &id)) { + if (id == 1) { -+ modname = "CI"; ++ port->name = "CI"; + port->class = DDB_PORT_CI; + port->type = DDB_CI_EXTERNAL_SONY; + ddbwritel(dev, I2C_SPEED_400, @@ -18228,77 +24764,74 @@ index fb52bda..d68ccee 100644 + port->nr); + return; + } -+ } else if (port_has_mach(port, &id)) { -+ char *xo2names[] = { "DUAL DVB-S2", "DUAL DVB-C/T/T2", -+ "DUAL DVB-ISDBT", "DUAL DVB-C/C2/T/T2", -+ "DUAL ATSC", "DUAL DVB-C/C2/T/T2" }; -+ ++ } else if (port_has_xo2(port, &id)) { + ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); + id >>= 2; + if (id > 5) { -+ modname = "unknown XO2 DuoFlex"; ++ port->name = "unknown XO2 DuoFlex"; + } else { + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_XO2 + id; -+ modname = xo2names[id]; ++ port->name = xo2names[id]; + init_xo2(port); + } ++ } else if (port_has_cxd28xx(port, &id)) { ++ switch (id) { ++ case 0xa4: ++ port->name = "DUAL DVB-CT2 CXD2843"; ++ port->type = DDB_TUNER_DVBC2T2_SONY_P; ++ break; ++ case 0xb1: ++ port->name = "DUAL DVB-CT2 CXD2837"; ++ port->type = DDB_TUNER_DVBCT2_SONY_P; ++ break; ++ case 0xb0: ++ port->name = "DUAL ISDB-T CXD2838"; ++ port->type = DDB_TUNER_ISDBT_SONY_P; ++ break; ++ default: ++ return; ++ } ++ port->class = DDB_PORT_TUNER; ++ ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); + } else if (port_has_stv0900(port)) { -+ modname = "DUAL DVB-S2"; ++ port->name = "DUAL DVB-S2"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBS_ST; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_stv0900_aa(port)) { -+ modname = "DUAL DVB-S2"; ++ port->name = "DUAL DVB-S2"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBS_ST_AA; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_drxks(port)) { -+ modname = "DUAL DVB-C/T"; ++ port->name = "DUAL DVB-C/T"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBCT_TR; + ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); + } else if (port_has_stv0367(port)) { -+ modname = "DUAL DVB-C/T"; ++ port->name = "DUAL DVB-C/T"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBCT_ST; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_encti(port)) { -+ modname = "ENCTI"; ++ port->name = "ENCTI"; + port->class = DDB_PORT_LOOP; + } else if (port->nr == ts_loop) { -+ modname = "TS LOOP"; ++ port->name = "TS LOOP"; + port->class = DDB_PORT_LOOP; + } -+ pr_info("Port %d (TAB %d): %s\n", -+ port->nr, port->nr + 1, modname); +} - --static struct dvb_device dvbdev_ci = { -- .priv = 0, -- .readers = -1, -- .writers = -1, -- .users = -1, -- .fops = &ci_fops, --}; - - /****************************************************************************/ - /****************************************************************************/ - /****************************************************************************/ - --static void input_tasklet(unsigned long data) ++ ++ ++/****************************************************************************/ ++/****************************************************************************/ ++/****************************************************************************/ ++ +static int wait_ci_ready(struct ddb_ci *ci) - { -- struct ddb_input *input = (struct ddb_input *) data; -- struct ddb *dev = input->port->dev; ++{ + u32 count = 10; - -- spin_lock(&input->lock); -- if (!input->running) { -- spin_unlock(&input->lock); -- return; -- } -- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); ++ + ndelay(500); + do { + if (ddbreadl(ci->port->dev, @@ -18310,30 +24843,13 @@ index fb52bda..d68ccee 100644 + } while (1); + return 0; +} - -- if (input->port->class == DDB_PORT_TUNER) { -- if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) -- printk(KERN_ERR "Overflow input %d\n", input->nr); -- while (input->cbuf != ((input->stat >> 11) & 0x1f) -- || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { -- dvb_dmx_swfilter_packets(&input->demux, -- input->vbuf[input->cbuf], -- input->dma_buf_size / 188); ++ +static int read_attribute_mem(struct dvb_ca_en50221 *ca, + int slot, int address) +{ + struct ddb_ci *ci = ca->data; + u32 val, off = (address >> 1) & (CI_BUFFER_SIZE-1); - -- input->cbuf = (input->cbuf + 1) % input->dma_buf_num; -- ddbwritel((input->cbuf << 11), -- DMA_BUFFER_ACK(input->nr)); -- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); -- } -- } -- if (input->port->class == DDB_PORT_CI) -- wake_up(&input->wq); -- spin_unlock(&input->lock); ++ + if (address > CI_BUFFER_SIZE) + return -1; + ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address, @@ -18341,14 +24857,11 @@ index fb52bda..d68ccee 100644 + wait_ci_ready(ci); + val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off); + return val; - } - --static void output_tasklet(unsigned long data) ++} ++ +static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, + int address, u8 value) - { -- struct ddb_output *output = (struct ddb_output *) data; -- struct ddb *dev = output->port->dev; ++{ + struct ddb_ci *ci = ca->data; + + ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address, @@ -18409,38 +24922,65 @@ index fb52bda..d68ccee 100644 +static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) +{ + struct ddb_ci *ci = ca->data; -+ + +-/****************************************************************************/ +-/****************************************************************************/ +-/****************************************************************************/ + ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr)); + msleep(300); + return 0; +} -+ + +-static void input_tasklet(unsigned long data) +static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) -+{ + { +- struct ddb_input *input = (struct ddb_input *) data; +- struct ddb *dev = input->port->dev; + struct ddb_ci *ci = ca->data; + u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); -+ + +- spin_lock(&input->lock); +- if (!input->running) { +- spin_unlock(&input->lock); +- return; +- } +- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); + ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE, + CI_CONTROL(ci->nr)); + return 0; +} -- spin_lock(&output->lock); -- if (!output->running) { -- spin_unlock(&output->lock); +- if (input->port->class == DDB_PORT_TUNER) { +- if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) +- printk(KERN_ERR "Overflow input %d\n", input->nr); +- while (input->cbuf != ((input->stat >> 11) & 0x1f) +- || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { +- dvb_dmx_swfilter_packets(&input->demux, +- input->vbuf[input->cbuf], +- input->dma_buf_size / 188); +static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) +{ + struct ddb_ci *ci = ca->data; + u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); + int stat = 0; -+ + +- input->cbuf = (input->cbuf + 1) % input->dma_buf_num; +- ddbwritel((input->cbuf << 11), +- DMA_BUFFER_ACK(input->nr)); +- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); +- } +- } +- if (input->port->class == DDB_PORT_CI) +- wake_up(&input->wq); +- spin_unlock(&input->lock); + if (val & CI_CAM_DETECT) + stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; + if (val & CI_CAM_READY) + stat |= DVB_CA_EN50221_POLL_CAM_READY; + return stat; -+} -+ + } + +-static void output_tasklet(unsigned long data) +static struct dvb_ca_en50221 en_templ = { + .read_attribute_mem = read_attribute_mem, + .write_attribute_mem = write_attribute_mem, @@ -18453,9 +24993,14 @@ index fb52bda..d68ccee 100644 +}; + +static void ci_attach(struct ddb_port *port) -+{ + { +- struct ddb_output *output = (struct ddb_output *) data; +- struct ddb *dev = output->port->dev; + struct ddb_ci *ci = 0; -+ + +- spin_lock(&output->lock); +- if (!output->running) { +- spin_unlock(&output->lock); + ci = kzalloc(sizeof(*ci), GFP_KERNEL); + if (!ci) return; @@ -18481,7 +25026,7 @@ index fb52bda..d68ccee 100644 .adr = 0x40, .polarity = 1, .clock_mode = 1, -@@ -1047,28 +1931,21 @@ struct cxd2099_cfg cxd_cfg = { +@@ -1047,28 +2052,21 @@ struct cxd2099_cfg cxd_cfg = { static int ddb_ci_attach(struct ddb_port *port) { @@ -18524,7 +25069,7 @@ index fb52bda..d68ccee 100644 } static int ddb_port_attach(struct ddb_port *port) -@@ -1081,15 +1958,32 @@ static int ddb_port_attach(struct ddb_port *port) +@@ -1081,15 +2079,32 @@ static int ddb_port_attach(struct ddb_port *port) if (ret < 0) break; ret = dvb_input_attach(port->input[1]); @@ -18558,19 +25103,29 @@ index fb52bda..d68ccee 100644 return ret; } -@@ -1098,6 +1992,11 @@ static int ddb_ports_attach(struct ddb *dev) +@@ -1098,6 +2113,21 @@ static int ddb_ports_attach(struct ddb *dev) int i, ret = 0; struct ddb_port *port; ++ if (dev->ids.devid == 0x0301dd01) ++ dev->ns_num = 15; ++ else ++ dev->ns_num = dev->info->ns_num; ++ for (i = 0; i < dev->ns_num; i++) ++ dev->ns[i].nr = i; ++ pr_info("%d netstream channels\n", dev->ns_num); ++ + if (dev->info->port_num) { + ret = dvb_register_adapters(dev); -+ if (ret < 0) ++ if (ret < 0) { ++ pr_err("Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n"); + return ret; ++ } + } for (i = 0; i < dev->info->port_num; i++) { port = &dev->port[i]; ret = ddb_port_attach(port); -@@ -1114,125 +2013,258 @@ static void ddb_ports_detach(struct ddb *dev) +@@ -1114,125 +2144,259 @@ static void ddb_ports_detach(struct ddb *dev) for (i = 0; i < dev->info->port_num; i++) { port = &dev->port[i]; @@ -18704,7 +25259,6 @@ index fb52bda..d68ccee 100644 + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + -+ /*pr_err("IT %d.%d %08x\n", dev->nr, dma->nr, dma->ctrl);*/ +#if 0 + if (4 & dma->ctrl) + pr_err("Overflow dma %d\n", dma->nr); @@ -18765,13 +25319,15 @@ index fb52bda..d68ccee 100644 +/* hmm, don't really need this anymore. + The output IRQ just copies some pointers, acks and wakes. */ + ++#ifdef DDB_USE_WORK +static void output_work(struct work_struct *work) +{ +} -+ ++#else +static void output_tasklet(unsigned long data) +{ +} ++#endif + +static void output_handler(unsigned long data) +{ @@ -18783,18 +25339,15 @@ index fb52bda..d68ccee 100644 + if (!dma->running) { + spin_unlock(&dma->lock); + return; - } -- printk(KERN_INFO "Port %d (TAB %d): %s\n", -- port->nr, port->nr+1, modname); ++ } + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + if (output->redi) + output_ack_input(output, output->redi); + wake_up(&dma->wq); + spin_unlock(&dma->lock); - } - --static void ddb_input_init(struct ddb_port *port, int nr) ++} ++ + +/****************************************************************************/ +/****************************************************************************/ @@ -18828,9 +25381,12 @@ index fb52bda..d68ccee 100644 + dma->num = INPUT_DMA_BUFS; + dma->size = INPUT_DMA_SIZE; + dma->div = INPUT_DMA_IRQ_DIV; -+ } -+} -+ + } +- printk(KERN_INFO "Port %d (TAB %d): %s\n", +- port->nr, port->nr+1, modname); + } + +-static void ddb_input_init(struct ddb_port *port, int nr) +static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int dma_nr) { struct ddb *dev = port->dev; @@ -18900,7 +25456,21 @@ index fb52bda..d68ccee 100644 } static void ddb_ports_init(struct ddb *dev) -@@ -1245,15 +2277,31 @@ static void ddb_ports_init(struct ddb *dev) +@@ -1240,20 +2404,48 @@ static void ddb_ports_init(struct ddb *dev) + int i; + struct ddb_port *port; + ++ if (dev->info->board_control) { ++ ddbwritel(dev, 0, BOARD_CONTROL); ++ msleep(100); ++ ddbwritel(dev, 4, BOARD_CONTROL); ++ usleep_range(2000, 3000); ++ ddbwritel(dev, 4 | dev->info->board_control, BOARD_CONTROL); ++ usleep_range(2000, 3000); ++ } ++ + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; port->dev = dev; port->nr = i; port->i2c = &dev->i2c[i]; @@ -18915,6 +25485,9 @@ index fb52bda..d68ccee 100644 - ddb_input_init(port, 2 * i); - ddb_input_init(port, 2 * i + 1); - ddb_output_init(port, i); ++ pr_info("Port %d (TAB %d): %s\n", ++ port->nr, port->nr + 1, port->name); ++ + port->dvb[0].adap = &dev->adap[2 * i]; + port->dvb[1].adap = &dev->adap[2 * i + 1]; + @@ -18939,8 +25512,12 @@ index fb52bda..d68ccee 100644 } } -@@ -1264,10 +2312,21 @@ static void ddb_ports_release(struct ddb *dev) +@@ -1262,12 +2454,25 @@ static void ddb_ports_release(struct ddb *dev) + int i; + struct ddb_port *port; ++ if (!dev->has_dma) ++ return; for (i = 0; i < dev->info->port_num; i++) { port = &dev->port[i]; - port->dev = dev; @@ -18965,7 +25542,7 @@ index fb52bda..d68ccee 100644 } } -@@ -1275,90 +2334,302 @@ static void ddb_ports_release(struct ddb *dev) +@@ -1275,90 +2480,306 @@ static void ddb_ports_release(struct ddb *dev) /****************************************************************************/ /****************************************************************************/ @@ -19033,9 +25610,7 @@ index fb52bda..d68ccee 100644 - struct ddb_i2c *i2c = &dev->i2c[n]; + struct ddb *dev = (struct ddb *) dev_id; + u32 s = ddbreadl(dev, INTERRUPT_STATUS); - -- i2c->done = 1; -- wake_up(&i2c->wq); ++ + do { + if (s & 0x80000000) + return IRQ_NONE; @@ -19044,7 +25619,9 @@ index fb52bda..d68ccee 100644 + ddbwritel(dev, s, INTERRUPT_ACK); + irq_handle_msg(dev, s); + } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); -+ + +- i2c->done = 1; +- wake_up(&i2c->wq); + return IRQ_HANDLED; } @@ -19115,23 +25692,23 @@ index fb52bda..d68ccee 100644 + return ret; +} + ++#ifdef DDB_TEST_THREADED +static irqreturn_t irq_thread(int irq, void *dev_id) +{ -+ struct ddb *dev = (struct ddb *) dev_id; ++ /* struct ddb *dev = (struct ddb *) dev_id; */ + + /*pr_info("%s\n", __func__);*/ return IRQ_HANDLED; } - --/******************************************************************************/ --/******************************************************************************/ --/******************************************************************************/ ++#endif + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + ++#ifdef DVB_NSD ++ +static ssize_t nsd_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ @@ -19158,7 +25735,7 @@ index fb52bda..d68ccee 100644 + struct dvb_device *dvbdev = file->private_data; + struct ddb *dev = dvbdev->priv; + -+ unsigned long arg = (unsigned long) parg; ++ /* unsigned long arg = (unsigned long) parg; */ + int ret = 0; + + switch (cmd) { @@ -19209,7 +25786,7 @@ index fb52bda..d68ccee 100644 + } + ddbcpyfrom(dev, dev->tsbuf, TS_CAPTURE_MEMORY, + TS_CAPTURE_LEN); -+ ts->len = ddbreadl(dev, TS_CAPTURE_RECEIVED) & 0xfff; ++ ts->len = ddbreadl(dev, TS_CAPTURE_RECEIVED) & 0x1fff; + if (copy_to_user(ts->ts, dev->tsbuf, ts->len)) + return -EIO; + break; @@ -19276,7 +25853,10 @@ index fb52bda..d68ccee 100644 + DVB_DEVICE_NSD); + return ret; +} -+ + +-/******************************************************************************/ +-/******************************************************************************/ +-/******************************************************************************/ +static void ddb_nsd_detach(struct ddb *dev) +{ + if (dev->nsd_dev->users > 2) { @@ -19286,6 +25866,7 @@ index fb52bda..d68ccee 100644 + dvb_unregister_device(dev->nsd_dev); +} + ++#endif + +/****************************************************************************/ +/****************************************************************************/ @@ -19321,7 +25902,7 @@ index fb52bda..d68ccee 100644 data = 0; shift = ((4 - wlen) * 8); -@@ -1370,33 +2641,33 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) +@@ -1370,33 +2791,33 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) } if (shift) data <<= shift; @@ -19367,7 +25948,7 @@ index fb52bda..d68ccee 100644 if (rlen < 4) data <<= ((4 - rlen) * 8); -@@ -1410,6 +2681,35 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) +@@ -1410,6 +2831,35 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) return 0; } @@ -19403,7 +25984,7 @@ index fb52bda..d68ccee 100644 #define DDB_MAGIC 'd' struct ddb_flashio { -@@ -1419,19 +2719,69 @@ struct ddb_flashio { +@@ -1419,19 +2869,69 @@ struct ddb_flashio { __u32 read_len; }; @@ -19476,7 +26057,7 @@ index fb52bda..d68ccee 100644 file->private_data = dev; return 0; } -@@ -1450,7 +2800,6 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +@@ -1450,7 +2950,6 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) if (copy_from_user(&fio, parg, sizeof(fio))) return -EFAULT; @@ -19484,7 +26065,7 @@ index fb52bda..d68ccee 100644 if (fio.write_len > 1028 || fio.read_len > 1028) return -EINVAL; if (fio.write_len + fio.read_len > 1028) -@@ -1468,6 +2817,103 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +@@ -1468,6 +2967,103 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return -EFAULT; break; } @@ -19588,7 +26169,7 @@ index fb52bda..d68ccee 100644 default: return -ENOTTY; } -@@ -1477,251 +2923,505 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +@@ -1477,251 +3073,508 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static const struct file_operations ddb_fops = { .unlocked_ioctl = ddb_ioctl, .open = ddb_open, @@ -19721,7 +26302,9 @@ index fb52bda..d68ccee 100644 + struct i2c_adapter *adap; + int temp, temp2, temp3, i; + u8 tmp[2]; -+ + +- ddb_ports_detach(dev); +- ddb_i2c_release(dev); + if (dev->info->type == DDB_MOD) { + ddbwritel(dev, 1, TEMPMON_CONTROL); + for (i = 0; i < 10; i++) { @@ -19757,16 +26340,6 @@ index fb52bda..d68ccee 100644 + return sprintf(buf, "%d\n", temp); +} -- ddb_ports_detach(dev); -- ddb_i2c_release(dev); -+static ssize_t qam_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ struct i2c_adapter *adap; -+ u8 tmp[4]; -+ s16 i, q; - - ddbwritel(0, INTERRUPT_ENABLE); - free_irq(dev->pdev->irq, dev); -#ifdef CONFIG_PCI_MSI @@ -19776,6 +26349,15 @@ index fb52bda..d68ccee 100644 - ddb_ports_release(dev); - ddb_buffers_free(dev); - ddb_device_destroy(dev); ++#if 0 ++static ssize_t qam_show(struct device *device, ++ struct device_attribute *attr, char *buf) ++{ ++ struct ddb *dev = dev_get_drvdata(device); ++ struct i2c_adapter *adap; ++ u8 tmp[4]; ++ s16 i, q; ++ + adap = &dev->i2c[1].adap; + if (i2c_read_regs16(adap, 0x1f, 0xf480, tmp, 4) < 0) + return sprintf(buf, "read_error\n"); @@ -19787,13 +26369,14 @@ index fb52bda..d68ccee 100644 - pci_disable_device(pdev); + return sprintf(buf, "%d %d\n", i, q); } - ++#endif ++ +static ssize_t mod_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; -+ + + return sprintf(buf, "%s:%s\n", + class_name[dev->port[num].class], + type_name[dev->port[num].type]); @@ -19891,7 +26474,7 @@ index fb52bda..d68ccee 100644 + struct ddb *dev = dev_get_drvdata(device); + char snr[32]; + int num = attr->attr.name[3] - 0x30; -+ ++ + if (dev->port[num].type >= DDB_TUNER_XO2) { + if (i2c_read_regs(&dev->i2c[num].adap, 0x10, 0x10, snr, 16) < 0) + return sprintf(buf, "NO SNR\n"); @@ -19900,7 +26483,8 @@ index fb52bda..d68ccee 100644 - irq_flag = 0; - dev->msi = 1; + /* serial number at 0x100-0x11f */ -+ if (i2c_read_regs16(&dev->i2c[num].adap, 0x50, 0x100, snr, 32) < 0) ++ if (i2c_read_regs16(&dev->i2c[num].adap, ++ 0x50, 0x100, snr, 32) < 0) + if (i2c_read_regs16(&dev->i2c[num].adap, + 0x57, 0x100, snr, 32) < 0) + return sprintf(buf, "NO SNR\n"); @@ -19964,7 +26548,25 @@ index fb52bda..d68ccee 100644 +{ return 0; +} -+ + +-fail3: +- ddb_ports_detach(dev); +- printk(KERN_ERR "fail3\n"); +- ddb_ports_release(dev); +-fail2: +- printk(KERN_ERR "fail2\n"); +- ddb_buffers_free(dev); +-fail1: +- printk(KERN_ERR "fail1\n"); +- if (dev->msi) +- pci_disable_msi(dev->pdev); +- free_irq(dev->pdev->irq, dev); +-fail: +- printk(KERN_ERR "fail\n"); +- ddb_unmap(dev); +- pci_set_drvdata(pdev, 0); +- pci_disable_device(pdev); +- return -1; +static ssize_t redirect_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) @@ -19988,26 +26590,8 @@ index fb52bda..d68ccee 100644 + int num = attr->attr.name[3] - 0x30; + + return sprintf(buf, "%d\n", dev->port[num].gap); - --fail3: -- ddb_ports_detach(dev); -- printk(KERN_ERR "fail3\n"); -- ddb_ports_release(dev); --fail2: -- printk(KERN_ERR "fail2\n"); -- ddb_buffers_free(dev); --fail1: -- printk(KERN_ERR "fail1\n"); -- if (dev->msi) -- pci_disable_msi(dev->pdev); -- free_irq(dev->pdev->irq, dev); --fail: -- printk(KERN_ERR "fail\n"); -- ddb_unmap(dev); -- pci_set_drvdata(pdev, 0); -- pci_disable_device(pdev); -- return -1; - } ++ ++} +static ssize_t gap_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) +{ @@ -20030,8 +26614,11 @@ index fb52bda..d68ccee 100644 + + return sprintf(buf, "%08x %08x\n", + ddbreadl(dev, 0), ddbreadl(dev, 4)); -+} -+ + } + +-/******************************************************************************/ +-/******************************************************************************/ +-/******************************************************************************/ +static ssize_t hwid_show(struct device *device, + struct device_attribute *attr, char *buf) +{ @@ -20044,10 +26631,7 @@ index fb52bda..d68ccee 100644 + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); - --/******************************************************************************/ --/******************************************************************************/ --/******************************************************************************/ ++ + return sprintf(buf, "0x%08X\n", dev->ids.regmapid); +} @@ -20203,7 +26787,7 @@ index fb52bda..d68ccee 100644 - pci_unregister_driver(&ddb_pci_driver); - ddb_class_destroy(); + int i; -+ ++ + for (i = 0; ddb_attrs[i].attr.name; i++) + if (device_create_file(dev->ddb_dev, &ddb_attrs[i])) + goto fail; @@ -20274,7 +26858,7 @@ index fb52bda..d68ccee 100644 +} diff --git a/drivers/media/pci/ddbridge/ddbridge-i2c.c b/drivers/media/pci/ddbridge/ddbridge-i2c.c new file mode 100644 -index 0000000..8e35d72 +index 0000000..88b2db8 --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge-i2c.c @@ -0,0 +1,257 @@ @@ -20367,7 +26951,7 @@ index 0000000..8e35d72 +} + +static int i2c_write_reg(struct i2c_adapter *adap, u8 adr, -+ u8 reg, u8 val) ++ u8 reg, u8 val) +{ + u8 msg[2] = {reg, val}; + @@ -20648,10 +27232,10 @@ index 0000000..fc8e34f +#endif diff --git a/drivers/media/pci/ddbridge/ddbridge-mod.c b/drivers/media/pci/ddbridge/ddbridge-mod.c new file mode 100644 -index 0000000..c2b527c +index 0000000..46b9394 --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge-mod.c -@@ -0,0 +1,1110 @@ +@@ -0,0 +1,1131 @@ +/* + * ddbridge.c: Digital Devices PCIe bridge driver + * @@ -20778,6 +27362,12 @@ index 0000000..c2b527c + +} + ++static void mod_set_rateinc(struct ddb *dev, u32 chan) ++{ ++ ddbwritel(dev, dev->mod[chan].rate_inc, CHANNEL_RATE_INCR(chan)); ++ mod_busy(dev, chan); ++} ++ +static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 }; + +void ddbridge_mod_output_start(struct ddb_output *output) @@ -20814,9 +27404,7 @@ index 0000000..c2b527c + /* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */ + ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr)); + -+ ddbwritel(dev, mod->rate_inc, CHANNEL_RATE_INCR(output->nr)); -+ mod_busy(dev, output->nr); -+ ++ mod_set_rateinc(dev, output->nr); + mod_set_incs(output); + + mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | @@ -20997,7 +27585,7 @@ index 0000000..c2b527c + m_fXtal = div64_u64(m_fXtal, RFreq); + + pr_info("fOut = %d fXtal = %d fDCO = %d HDIV = %2d, N = %3d\n", -+ (u32) fOut, (u32) m_fXtal, (u32) fDCO, HSDiv, N); ++ (u32) fOut, (u32) m_fXtal, (u32) fDCO, (u32) HSDiv, N); + } + + fOut = freq; @@ -21007,7 +27595,7 @@ index 0000000..c2b527c + + if (Div < MinDiv) + Div = Div + 1; -+ pr_info(" fOut = %d MinDiv = %4d MaxDiv = %4d StartDiv = %d\n", ++ pr_info(" fOut = %u MinDiv = %llu MaxDiv = %llu StartDiv = %llu\n", + fOut, MinDiv, MaxDiv, Div); + + if (Div <= 11) { @@ -21025,8 +27613,8 @@ index 0000000..c2b527c + if (N > 128) + break; + } -+ pr_info(" %3d: %llu %u %u %u\n", -+ retry, Div, HSDiv*N, HSDiv, N); ++ pr_info(" %3d: %llu %llu %llu %u\n", ++ retry, Div, HSDiv * N, HSDiv, N); + if (HSDiv * N < MinDiv) + Div = Div + 2; + else if (HSDiv * N > MaxDiv) @@ -21060,7 +27648,7 @@ index 0000000..c2b527c + pr_info("%16llx %d\n", RFreq, fxtal); + RF = RFreq; + -+ pr_info("fOut = %d fXtal = %d fDCO = %d HDIV = %d, N = %d, RFreq = %d\n", ++ pr_info("fOut = %u fXtal = %llu fDCO = %llu HSDIV = %llu, N = %u, RFreq = %llu\n", + fOut, m_fXtal, fDCO, HSDiv, N, RFreq); + + Data[0] = (u8)(((HSDiv - 4) << 5) | ((N - 1) >> 2)); @@ -21113,6 +27701,7 @@ index 0000000..c2b527c + return 0; +} + ++#if 0 +static void mod_peak(struct ddb *dev, u32 Time, s16 *pIPeak, s16 *pQPeak) +{ + u32 val; @@ -21131,6 +27720,7 @@ index 0000000..c2b527c + *pIPeak = val & 0xffff; + *pQPeak = (val >> 16) & 0xffff; +} ++#endif + +static int mod_init_dac_input(struct ddb *dev) +{ @@ -21400,23 +27990,16 @@ index 0000000..c2b527c + 0x00001B23, 0x0000EEB7, 0x00006A28 +}; + -+static int mod_set_modulation(struct ddb *dev, int chan, int mod) ++static int mod_set_modulation(struct ddb *dev, int chan, enum fe_modulation mod) +{ -+ static u32 setting[5] = { 0x600, 0x601, 0x602, 0x903, 0x604 }; -+ -+ if (mod > 4) ++ if (mod > QAM_256 || mod < QAM_16) + return -EINVAL; -+ ddbwritel(dev, setting[mod] , CHANNEL_SETTINGS(chan)); ++ dev->mod[chan].modulation = mod; ++ dev->mod[chan].obitrate = 0x0061072787900000 * (mod + 3); ++ dev->mod[chan].ibitrate = dev->mod[chan].obitrate; + return 0; +} + -+static void mod_set_rateinc(struct ddb *dev, u32 chan, u32 inc) -+{ -+ dev->mod[chan].rate_inc = inc; -+ ddbwritel(dev, inc, CHANNEL_RATE_INCR(chan)); -+ mod_busy(dev, chan); -+} -+ +static void mod_set_channelsumshift(struct ddb *dev, u32 shift) +{ + ddbwritel(dev, (shift & 3) << 2, MODULATOR_CONTROL); @@ -21524,8 +28107,7 @@ index 0000000..c2b527c + (FrequencyCH10 + (9 - i) * 8); + iqsteps = flash->DataSet[0].IQTableLength; + mod_set_iq(dev, iqsteps, i, iqfreq); -+ -+ dev->mod[i].modulation = QAM_256; ++ mod_set_modulation(dev, i, QAM_256); + } + + mod_bypass_equalizer(dev, 1); @@ -21545,7 +28127,6 @@ index 0000000..c2b527c + return stat; +} + -+ +void ddbridge_mod_rate_handler(unsigned long data) +{ + struct ddb_output *output = (struct ddb_output *) data; @@ -21566,7 +28147,7 @@ index 0000000..c2b527c + s64 PCRIncrement; + u64 mul; + -+ if (!mod->do_handle) ++ if (!mod->pcr_correction) + return; + spin_lock(&dma->lock); + ddbwritel(dev, mod->Control | CHANNEL_CONTROL_FREEZE_STATUS, @@ -21611,19 +28192,21 @@ index 0000000..c2b527c + div_u64(mul, OutPacketDiff); + else + mod->rate_inc = 0; -+ ddbwritel(dev, mod->rate_inc, -+ CHANNEL_RATE_INCR(output->nr)); -+ mod_busy(dev, output->nr); ++ mod_set_rateinc(dev, output->nr); +/* +#define PACKET_CLOCKS (27000000ULL*1504) -+#define FACTOR (1024<<12) ++#define FACTOR (1<<22) +double Increment = FACTOR*PACKET_CLOCKS/double(m_OutputBitrate); +double Decrement = FACTOR*PACKET_CLOCKS/double(m_InputBitrate); ++ ++27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1 +*/ -+ mod->PCRIncrement = 3348148758ULL; ++ mod->PCRIncrement = ++ div_u64(26785190066ULL, ++ mod->modulation + 3); + if (InPacketDiff) + mod->PCRDecrement = -+ div_u64(3348148758ULL * ++ div_u64(mod->PCRIncrement * + (u64) OutPacketDiff, + InPacketDiff); + else @@ -21711,12 +28294,13 @@ index 0000000..c2b527c + mod->LastOutPackets = OutPackets; + mod->LastPCRAdjust = (s32) PCRAdjust; + ++ spin_unlock(&dma->lock); ++ + pr_info("chan %d out %016llx in %016llx indiff %08x\n", + chan, OutPackets, InPackets, InPacketDiff); + pr_info("cnt %d pcra %016llx pcraext %08x pcraextfrac %08x pcrcorr %08x pcri %016llx\n", + mod->StateCounter, PCRAdjust, PCRAdjustExt, + PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement); -+ spin_unlock(&dma->lock); +} + +int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg) @@ -21742,13 +28326,34 @@ index 0000000..c2b527c + case DVB_MOD_CHANNEL_SET: + { + struct dvb_mod_channel_params *cp = parg; ++ int res; ++ u32 ri; + -+ if (cp->modulation > QAM_256) ++ res = mod_set_modulation(dev, output->nr, cp->modulation); ++ if (res) ++ return res; ++ ++ if (cp->input_bitrate > dev->mod[output->nr].obitrate) + return -EINVAL; -+ dev->mod[output->nr].modulation = cp->modulation; -+ dev->mod[output->nr].rate_inc = cp->rate_increment; -+ ddbwritel(dev, dev->mod[output->nr].rate_inc, -+ CHANNEL_RATE_INCR(output->nr)); ++ dev->mod[output->nr].ibitrate = cp->input_bitrate; ++ dev->mod[output->nr].pcr_correction = cp->pcr_correction; ++ ++ if (cp->input_bitrate != 0) { ++ u64 d = dev->mod[output->nr].obitrate - ++ dev->mod[output->nr].ibitrate; ++ ++ d = div64_u64(d, dev->mod[output->nr].obitrate >> 24); ++ if (d > 0xfffffe) ++ ri = 0xfffffe; ++ else ++ ri = d; ++ } else ++ ri = 0; ++ dev->mod[output->nr].rate_inc = ri; ++ pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n", ++ dev->mod[output->nr].ibitrate >> 32, ++ dev->mod[output->nr].obitrate >> 32, ++ ri); + break; + } + default: @@ -21764,10 +28369,10 @@ index 0000000..c2b527c +} diff --git a/drivers/media/pci/ddbridge/ddbridge-ns.c b/drivers/media/pci/ddbridge/ddbridge-ns.c new file mode 100644 -index 0000000..67cb320 +index 0000000..b538f12 --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge-ns.c -@@ -0,0 +1,490 @@ +@@ -0,0 +1,489 @@ +/* + * ddbridge-ns.c: Digital Devices PCIe bridge driver net streaming + * @@ -21939,7 +28544,6 @@ index 0000000..67cb320 +static int citoport(struct ddb *dev, u8 ci) +{ + int i, j; -+ struct ddb_input *input; + + for (i = j = 0; i < dev->info->port_num; i++) { + if (dev->port[i].class == DDB_PORT_CI) { @@ -22259,7 +28863,7 @@ index 0000000..67cb320 + return res; +} diff --git a/drivers/media/pci/ddbridge/ddbridge-regs.h b/drivers/media/pci/ddbridge/ddbridge-regs.h -index a3ccb31..018bc60 100644 +index a3ccb31..0c064ae 100644 --- a/drivers/media/pci/ddbridge/ddbridge-regs.h +++ b/drivers/media/pci/ddbridge/ddbridge-regs.h @@ -1,7 +1,7 @@ @@ -22286,7 +28890,7 @@ index a3ccb31..018bc60 100644 #define HARDWARE_VERSION 0x00 #define REGISTERMAP_VERSION 0x04 -@@ -37,10 +37,26 @@ +@@ -37,10 +37,30 @@ #define SPI_DATA 0x14 /* ------------------------------------------------------------------------- */ @@ -22303,12 +28907,16 @@ index a3ccb31..018bc60 100644 +#define MDIO_ADR 0x24 +#define MDIO_REG 0x28 +#define MDIO_VAL 0x2C -+ -+/* ------------------------------------------------------------------------- */ -/* Interrupt controller */ -/* How many MSI's are available depends on HW (Min 2 max 8) */ -/* How many are usable also depends on Host platform */ ++/* ------------------------------------------------------------------------- */ ++ ++#define BOARD_CONTROL 0x30 ++ ++/* ------------------------------------------------------------------------- */ ++ +/* Interrupt controller + How many MSI's are available depends on HW (Min 2 max 8) + How many are usable also depends on Host platform @@ -22316,7 +28924,7 @@ index a3ccb31..018bc60 100644 #define INTERRUPT_BASE (0x40) -@@ -57,6 +73,9 @@ +@@ -57,6 +77,9 @@ #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) @@ -22326,7 +28934,7 @@ index a3ccb31..018bc60 100644 #define INTMASK_I2C1 (0x00000001) #define INTMASK_I2C2 (0x00000002) #define INTMASK_I2C3 (0x00000004) -@@ -81,6 +100,32 @@ +@@ -81,6 +104,32 @@ #define INTMASK_TSOUTPUT3 (0x00040000) #define INTMASK_TSOUTPUT4 (0x00080000) @@ -22359,7 +28967,7 @@ index a3ccb31..018bc60 100644 /* ------------------------------------------------------------------------- */ /* I2C Master Controller */ -@@ -90,18 +135,12 @@ +@@ -90,18 +139,12 @@ #define I2C_TIMING (0x04) #define I2C_TASKLENGTH (0x08) /* High read, low write */ #define I2C_TASKADDRESS (0x0C) /* High read, low write */ @@ -22379,7 +28987,7 @@ index a3ccb31..018bc60 100644 #define I2C_SPEED_400 (0x04030404) #define I2C_SPEED_200 (0x09080909) -@@ -117,35 +156,252 @@ +@@ -117,35 +160,252 @@ #define DMA_BASE_WRITE (0x100) #define DMA_BASE_READ (0x140) @@ -22651,10 +29259,10 @@ index a3ccb31..018bc60 100644 + diff --git a/drivers/media/pci/ddbridge/ddbridge.c b/drivers/media/pci/ddbridge/ddbridge.c new file mode 100644 -index 0000000..ef44ac0 +index 0000000..d48c860 --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge.c -@@ -0,0 +1,439 @@ +@@ -0,0 +1,449 @@ +/* + * ddbridge.c: Digital Devices PCIe bridge driver + * @@ -22682,29 +29290,23 @@ index 0000000..ef44ac0 +/*#define DDB_ALT_DMA*/ +#define DDB_USE_WORK +/*#define DDB_TEST_THREADED*/ -+#undef CONFIG_PCI_MSI + +#include "ddbridge.h" +#include "ddbridge-regs.h" + -+#include "tda18271c2dd.h" -+#include "stv6110x.h" -+#include "stv090x.h" -+#include "lnbh24.h" -+#include "drxk.h" -+#include "stv0367.h" -+#include "stv0367dd.h" -+#include "tda18212.h" -+#include "tda18212dd.h" -+#include "cxd2843.h" -+ +static struct workqueue_struct *ddb_wq; + +static int adapter_alloc; +module_param(adapter_alloc, int, 0444); +MODULE_PARM_DESC(adapter_alloc, -+ "0-one adapter per io, 1-one per tab with io, " -+ "2-one per tab, 3-one for all"); ++ "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); ++ ++#ifdef CONFIG_PCI_MSI ++static int msi = 1; ++module_param(msi, int, 0444); ++MODULE_PARM_DESC(msi, ++ " Control MSI interrupts: 0-disable, 1-enable (default)"); ++#endif + +#include "ddbridge-core.c" + @@ -22807,7 +29409,7 @@ index 0000000..ef44ac0 + ddbwritel(dev, 0x00000000, MSI7_ENABLE); + +#ifdef CONFIG_PCI_MSI -+ if (pci_msi_enabled()) { ++ if (msi && pci_msi_enabled()) { + stat = pci_enable_msi_block(dev->pdev, 2); + if (stat == 0) { + dev->msi = 1; @@ -22822,7 +29424,6 @@ index 0000000..ef44ac0 + dev->msi++; + } + } -+#endif + if (dev->msi == 2) { + stat = request_irq(dev->pdev->irq, irq_handler0, + irq_flag, "ddbridge", (void *) dev); @@ -22834,7 +29435,9 @@ index 0000000..ef44ac0 + free_irq(dev->pdev->irq, dev); + goto fail0; + } -+ } else { ++ } else ++#endif ++ { +#ifdef DDB_TEST_THREADED + stat = request_threaded_irq(dev->pdev->irq, irq_handler, + irq_thread, @@ -22912,20 +29515,20 @@ index 0000000..ef44ac0 +/****************************************************************************/ +/****************************************************************************/ + -+struct ddb_regset octopus_i2c = { ++static struct ddb_regset octopus_i2c = { + .base = 0x80, + .num = 0x04, + .size = 0x20, +}; + +static struct ddb_regmap octopus_map = { -+/* .i2c = octopus_i2c, */ ++ .i2c = &octopus_i2c, +}; + +static struct ddb_info ddb_none = { + .type = DDB_NONE, + .name = "unknown Digital Devices PCIe card, install newer driver", -+/* .regmap = octopus_map, */ ++ .regmap = &octopus_map, +}; + +static struct ddb_info ddb_octopus = { @@ -22981,6 +29584,22 @@ index 0000000..ef44ac0 + .i2c_num = 4, +}; + ++static struct ddb_info ddb_v7 = { ++ .type = DDB_OCTOPUS, ++ .name = "Digital Devices Cine S2 V7 DVB adapter", ++ .port_num = 4, ++ .i2c_num = 4, ++ .board_control = 2, ++}; ++ ++static struct ddb_info ddb_ctv7 = { ++ .type = DDB_OCTOPUS, ++ .name = "Digital Devices Cine CT V7 DVB adapter", ++ .port_num = 4, ++ .i2c_num = 4, ++ .board_control = 3, ++}; ++ +static struct ddb_info ddb_satixS2v3 = { + .type = DDB_OCTOPUS, + .name = "Mystique SaTiX-S2 V3 DVB adapter", @@ -23016,13 +29635,6 @@ index 0000000..ef44ac0 + .temp_num = 1, +}; + -+static struct ddb_info ddb_octonet = { -+ .type = DDB_OCTONET, -+ .name = "Digital Devices Octopus Net", -+ .port_num = 4, -+ .i2c_num = 4, -+}; -+ +#define DDVID 0xdd01 /* Digital Devices Vendor ID */ + +#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ @@ -23039,8 +29651,12 @@ index 0000000..ef44ac0 + DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), + DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), + DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), ++ DDB_ID(DDVID, 0x0006, DDVID, 0x0022, ddb_v7), + DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), + DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), ++ DDB_ID(DDVID, 0x0006, DDVID, 0x0031, ddb_ctv7), ++ DDB_ID(DDVID, 0x0006, DDVID, 0x0032, ddb_ctv7), ++ DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7), + DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci), + DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis), + DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod), @@ -23063,7 +29679,9 @@ index 0000000..ef44ac0 +{ + int stat = -1; + -+ pr_info("Digital Devices PCIE bridge driver 0.9.12, Copyright (C) 2010-13 Digital Devices GmbH\n"); ++ pr_info("Digital Devices PCIE bridge driver " ++ DDBRIDGE_VERSION ++ ", Copyright (C) 2010-14 Digital Devices GmbH\n"); + if (ddb_class_create() < 0) + return -1; + ddb_wq = create_workqueue("ddbridge"); @@ -23093,9 +29711,9 @@ index 0000000..ef44ac0 +MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); +MODULE_AUTHOR("Ralph Metzler, Metzler Brothers Systementwicklung"); +MODULE_LICENSE("GPL"); -+MODULE_VERSION("0.9.12"); ++MODULE_VERSION(DDBRIDGE_VERSION); diff --git a/drivers/media/pci/ddbridge/ddbridge.h b/drivers/media/pci/ddbridge/ddbridge.h -index 8b1b41d..2524366 100644 +index 8b1b41d..46b30b0 100644 --- a/drivers/media/pci/ddbridge/ddbridge.h +++ b/drivers/media/pci/ddbridge/ddbridge.h @@ -1,7 +1,8 @@ @@ -23103,7 +29721,7 @@ index 8b1b41d..2524366 100644 * ddbridge.h: Digital Devices PCIe bridge driver * - * Copyright (C) 2010-2011 Digital Devices GmbH -+ * Copyright (C) 2010-2013 Digital Devices GmbH ++ * Copyright (C) 2010-2014 Digital Devices GmbH + * Ralph Metzler * * This program is free software; you can redistribute it and/or @@ -23117,7 +29735,7 @@ index 8b1b41d..2524366 100644 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) +#define __devexit +#define __devinit -+#define __devinitconst ++#define __devinitconst +#endif + +#include @@ -23161,8 +29779,25 @@ index 8b1b41d..2524366 100644 #include "dmxdev.h" #include "dvbdev.h" #include "dvb_demux.h" -@@ -44,92 +80,141 @@ +@@ -41,95 +77,161 @@ + #include "dvb_ringbuffer.h" + #include "dvb_ca_en50221.h" + #include "dvb_net.h" ++ ++#include "tda18271c2dd.h" ++#include "stv6110x.h" ++#include "stv090x.h" ++#include "lnbh24.h" ++#include "drxk.h" ++#include "stv0367.h" ++#include "stv0367dd.h" ++#include "tda18212.h" ++#include "tda18212dd.h" ++#include "cxd2843.h" #include "cxd2099.h" ++#include "stv0910.h" ++#include "stv6111.h" ++#include "lnbh25.h" #define DDB_MAX_I2C 4 -#define DDB_MAX_PORT 4 @@ -23172,21 +29807,22 @@ index 8b1b41d..2524366 100644 +#define DDB_MAX_OUTPUT 10 + +struct ddb_regset { -+ uint32_t base; -+ uint32_t num; -+ uint32_t size; ++ u32 base; ++ u32 num; ++ u32 size; +}; + +struct ddb_regmap { -+ struct ddb_regset i2c; -+ struct ddb_regset i2c_buf; -+ struct ddb_regset dma; -+ struct ddb_regset dma_buf; -+ struct ddb_regset input; -+ struct ddb_regset output; -+ struct ddb_regset channel; -+ struct ddb_regset ci; -+ struct ddb_regset pid_filter; ++ struct ddb_regset *i2c; ++ struct ddb_regset *i2c_buf; ++ struct ddb_regset *dma; ++ struct ddb_regset *dma_buf; ++ struct ddb_regset *input; ++ struct ddb_regset *output; ++ struct ddb_regset *channel; ++ struct ddb_regset *ci; ++ struct ddb_regset *pid_filter; ++ struct ddb_regset *ns; +}; + +struct ddb_ids { @@ -23209,14 +29845,17 @@ index 8b1b41d..2524366 100644 +#define DDB_MOD 3 +#define DDB_OCTONET 4 char *name; - int port_num; +- int port_num; - u32 port_type[DDB_MAX_PORT]; -+ int i2c_num; -+ int led_num; -+ int fan_num; -+ int temp_num; -+ int temp_bus; -+ struct ddb_regmap regmap; ++ u8 port_num; ++ u8 i2c_num; ++ u8 led_num; ++ u8 fan_num; ++ u8 temp_num; ++ u8 temp_bus; ++ u8 board_control; ++ u8 ns_num; ++ struct ddb_regmap *regmap; }; -/* DMA_SIZE MUST be divisible by 188 and 128 !!! */ @@ -23335,32 +29974,37 @@ index 8b1b41d..2524366 100644 }; struct ddb_port { -@@ -141,45 +226,242 @@ struct ddb_port { +@@ -141,45 +243,246 @@ struct ddb_port { #define DDB_PORT_NONE 0 #define DDB_PORT_CI 1 #define DDB_PORT_TUNER 2 +#define DDB_PORT_LOOP 3 +#define DDB_PORT_MOD 4 ++ char *name; u32 type; #define DDB_TUNER_NONE 0 #define DDB_TUNER_DVBS_ST 1 #define DDB_TUNER_DVBS_ST_AA 2 -#define DDB_TUNER_DVBCT_TR 16 -#define DDB_TUNER_DVBCT_ST 17 +- u32 adr; +#define DDB_TUNER_DVBCT_TR 3 +#define DDB_TUNER_DVBCT_ST 4 +#define DDB_CI_INTERNAL 5 +#define DDB_CI_EXTERNAL_SONY 6 ++#define DDB_TUNER_DVBCT2_SONY_P 7 ++#define DDB_TUNER_DVBC2T2_SONY_P 8 ++#define DDB_TUNER_ISDBT_SONY_P 9 ++ +#define DDB_TUNER_XO2 16 -+#define DDB_TUNER_DVBS 16 ++#define DDB_TUNER_DVBS_STV0910 16 +#define DDB_TUNER_DVBCT2_SONY 17 +#define DDB_TUNER_ISDBT_SONY 18 +#define DDB_TUNER_DVBC2T2_SONY 19 +#define DDB_TUNER_ATSC_ST 20 +#define DDB_TUNER_DVBC2T2_ST 21 -+ - u32 adr; ++ u32 adr; struct ddb_input *input[2]; struct ddb_output *output; struct dvb_ca_en50221 *en; @@ -23379,8 +30023,9 @@ index 8b1b41d..2524366 100644 + +struct mod_state { + u32 modulation; -+ -+ u32 do_handle; ++ u64 obitrate; ++ u64 ibitrate; ++ u32 pcr_correction; + + u32 rate_inc; + u32 Control; @@ -23513,21 +30158,21 @@ index 8b1b41d..2524366 100644 +{ + return readb((char *) (dev->regs+(adr))); +} -+ + +#define ddbcpyto(_dev, _adr, _src, _count) \ + memcpy_toio((char *) (_dev->regs + (_adr)), (_src), (_count)) + +#define ddbcpyfrom(_dev, _dst, _adr, _count) \ + memcpy_fromio((_dst), (char *) (_dev->regs + (_adr)), (_count)) - ++ +#define ddbmemset(_dev, _adr, _val, _count) \ + memset_io((char *) (_dev->regs + (_adr)), (_val), (_count)) + + +/****************************************************************************/ - /****************************************************************************/ +/****************************************************************************/ -+ + /****************************************************************************/ + +#define dd_uint8 u8 +#define dd_uint16 u16 +#define dd_int16 s16 @@ -23586,16 +30231,15 @@ index 8b1b41d..2524366 100644 + +int ddbridge_flashread(struct ddb *dev, u8 *buf, u32 addr, u32 len); + - ++#define DDBRIDGE_VERSION "0.9.14" ++ #endif -+ -+ diff --git a/drivers/media/pci/ddbridge/octonet.c b/drivers/media/pci/ddbridge/octonet.c new file mode 100644 -index 0000000..e90d2eb +index 0000000..e6c9b92 --- /dev/null +++ b/drivers/media/pci/ddbridge/octonet.c -@@ -0,0 +1,198 @@ +@@ -0,0 +1,191 @@ +/* + * octonet.c: Digital Devices network tuner driver + * @@ -23623,16 +30267,6 @@ index 0000000..e90d2eb +#include "ddbridge.h" +#include "ddbridge-regs.h" + -+#include "tda18271c2dd.h" -+#include "stv6110x.h" -+#include "stv090x.h" -+#include "lnbh24.h" -+#include "drxk.h" -+#include "stv0367.h" -+#include "stv0367dd.h" -+#include "tda18212dd.h" -+#include "cxd2843.h" -+ +#include + +static int adapter_alloc = 3; @@ -23640,7 +30274,7 @@ index 0000000..e90d2eb +MODULE_PARM_DESC(adapter_alloc, +"0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); + -+#define DVB_NETSTREAM ++#define DVB_NSD + +#include "ddbridge-core.c" + @@ -23649,6 +30283,7 @@ index 0000000..e90d2eb + .name = "Digital Devices OctopusNet network DVB adapter", + .port_num = 4, + .i2c_num = 4, ++ .ns_num = 12, +}; + +static void octonet_unmap(struct ddb *dev) @@ -23672,6 +30307,7 @@ index 0000000..e90d2eb + ddbwritel(dev, 0, INTERRUPT_ENABLE); + free_irq(platform_get_irq(dev->pfdev, 0), dev); + ++ ddb_ports_release(dev); + ddb_device_destroy(dev); + octonet_unmap(dev); + platform_set_drvdata(pdev, 0); @@ -23697,7 +30333,7 @@ index 0000000..e90d2eb + return -ENXIO; + dev->regs_len = (regs->end - regs->start) + 1; + dev_info(dev->dev, "regs_start=%08x regs_len=%08x\n", -+ regs->start, dev->regs_len); ++ (u32) regs->start, (u32) dev->regs_len); + dev->regs = ioremap(regs->start, dev->regs_len); + if (!dev->regs) { + dev_err(dev->dev, "ioremap failed\n"); @@ -23769,7 +30405,8 @@ index 0000000..e90d2eb +{ + int res; + -+ pr_info("Digital Devices OctoNet driver, Copyright (C) 2012-2013 Digital Devices GmbH\n"); ++ pr_info("Digital Devices OctopusNet driver " DDBRIDGE_VERSION ++ ", Copyright (C) 2010-14 Digital Devices GmbH\n"); + res = ddb_class_create(); + if (res) + return res; @@ -26573,10 +33210,10 @@ index 22c39ff..e3ae00c 100644 /* LocalWords: Endif diff --git a/include/uapi/linux/dvb/mod.h b/include/uapi/linux/dvb/mod.h new file mode 100644 -index 0000000..4c453a7 +index 0000000..c733a39 --- /dev/null +++ b/include/uapi/linux/dvb/mod.h -@@ -0,0 +1,23 @@ +@@ -0,0 +1,22 @@ +#ifndef _UAPI_DVBMOD_H_ +#define _UAPI_DVBMOD_H_ + @@ -26590,9 +33227,8 @@ index 0000000..4c453a7 + +struct dvb_mod_channel_params { + enum fe_modulation modulation; -+ -+ __u32 rate_increment; -+ ++ __u64 input_bitrate; /* 2^-32 Hz */ ++ int pcr_correction; +}; + +