From e6db511c4aaf1f0c76ec6ca52d14b0f0db361bb9 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Sat, 21 Dec 2024 10:27:33 +0000 Subject: [PATCH] linux (NXP iMX8): Update to V20 - Cadence MHDP8501(HDMI/DP) for i.MX8MQ ref: - https://patchwork.kernel.org/project/linux-phy/list/?series=918529 - https://patchwork.freedesktop.org/series/120825/ --- ...Cadence-MHDP8501-HDMI-DP-for-i-MX8MQ.patch | 1102 ++++++++++------- 1 file changed, 627 insertions(+), 475 deletions(-) diff --git a/projects/NXP/devices/iMX8/patches/linux/0001-Initial-support-Cadence-MHDP8501-HDMI-DP-for-i-MX8MQ.patch b/projects/NXP/devices/iMX8/patches/linux/0001-Initial-support-Cadence-MHDP8501-HDMI-DP-for-i-MX8MQ.patch index 4fbc8233b7..4ada9c6baa 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0001-Initial-support-Cadence-MHDP8501-HDMI-DP-for-i-MX8MQ.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0001-Initial-support-Cadence-MHDP8501-HDMI-DP-for-i-MX8MQ.patch @@ -1,10 +1,10 @@ -From patchwork Tue Nov 26 14:11:46 2024 +From patchwork Tue Dec 17 06:51:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [PATCH v19 0/8] Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ +Subject: [PATCH v20 0/8] Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ From: Sandor Yu -Message-Id: +Message-Id: To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -16,30 +16,63 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:45 +0800 +Date: Tue, 17 Dec 2024 14:51:42 +0800 The patch set initial support Cadence MHDP8501(HDMI/DP) DRM bridge driver and Cadence HDP-TX PHY(HDMI/DP) driver for Freescale i.MX8MQ. The patch set compose of DRM bridge drivers and PHY driver. -Both of them need by patch #1 and #2 to pass build. +Both of them need by patch #1 and #3 to pass build. DRM bridges driver patches: - #1: drm: bridge: Cadence: Creat mhdp helper driver - #2: phy: Add HDMI configuration options - #3: dt-bindings: display: bridge: Add Cadence MHDP8501 - #4: drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver + #1: soc: cadence: Create helper functions for Cadence MHDP + #2: drm: bridge: cadence: Update mhdp8546 mailbox access functions + #3: phy: Add HDMI configuration options + #4: dt-bindings: display: bridge: Add Cadence MHDP8501 + #5: drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver PHY driver patches: - #1: drm: bridge: Cadence: Creat mhdp helper driver - #2: phy: Add HDMI configuration options - #5: dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY - #6: phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ + #1: soc: cadence: Create helper functions for Cadence MHDP + #3: phy: Add HDMI configuration options + #6: dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY + #7: phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ i.MX8M/TQMa8Mx DT patches: - #7: Add DT nodes for DCSS/HDMI pipeline - #8: Enable HDMI for TQMa8Mx/MBa8Mx + #8: Add DT nodes for DCSS/HDMI pipeline + #9: Enable HDMI for TQMa8Mx/MBa8Mx + +v19->v20: +Patch #1: soc: cadence: Create helper functions for Cadence MHDP +Patch #2: drm: bridge: cadence: Update mhdp8546 mailbox access functions +- The two patches are split from Patch #1 in v19. + The MHDP helper functions have been moved in a new "cadence" directory + under the SOC directory in patch #1, in order to promote code reuse + among MHDP8546, MHDP8501, and the i.MX8MQ HDMI/DP PHY drivers, + +Patch #3: phy: Add HDMI configuration options +- Add a-b tag + +Patch #4: dt-bindings: display: bridge: Add Cadence MHDP8501 +- remove data type link of data-lanes + +Patch #5: drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver +- Dump mhdp FW version by debugfs +- Combine HDMI and DP cable detect functions into one function +- Combine HDMI and DP cable bridge_mode_valid() functions into one function +- Rename cdns_hdmi_reset_link() to cdns_hdmi_handle_hotplug() +- Add comments for EDID in cdns_hdmi_handle_hotplug() and cdns_dp_check_link_state() +- Add atomic_get_input_bus_fmts() and bridge_atomic_check() for DP driver +- Remove bpc and color_fmt init in atomic_enable() function. +- More detail comments for DDC adapter only support SCDC_I2C_SLAVE_ADDRESS + read and write in HDMI driver. + +Patch #7: phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ +- implify DP configuration handling by directly copying + the configuration options to the driver's internal structure. +- return the error code directly instead of logging an error message in `hdptx_clk_enable` +- Remove redundant ref_clk_rate check + v18->v19: Patch #1 @@ -310,62 +343,69 @@ Alexander Stein (2): arm64: dts: imx8mq: Add DCSS + HDMI/DP display pipeline arm64: dts: imx8mq: tqma8mq-mba8mx: Enable HDMI support -Sandor Yu (6): - drm: bridge: Cadence: Create MHDP helper driver +Sandor Yu (7): + soc: cadence: Create helper functions for Cadence MHDP + drm: bridge: cadence: Update mhdp8546 mailbox access functions phy: Add HDMI configuration options dt-bindings: display: bridge: Add Cadence MHDP8501 drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ - .../display/bridge/cdns,mhdp8501.yaml | 120 ++ + .../display/bridge/cdns,mhdp8501.yaml | 121 ++ .../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 51 + .../dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 26 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 + arch/arm64/boot/dts/freescale/mba8mx.dtsi | 11 + - drivers/gpu/drm/bridge/cadence/Kconfig | 24 + - drivers/gpu/drm/bridge/cadence/Makefile | 3 + - .../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 565 ++++++++ - .../drm/bridge/cadence/cdns-mhdp8501-core.c | 322 +++++ - .../drm/bridge/cadence/cdns-mhdp8501-core.h | 376 +++++ - .../gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 686 +++++++++ - .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 764 ++++++++++ - .../drm/bridge/cadence/cdns-mhdp8546-core.c | 487 +------ + drivers/gpu/drm/bridge/cadence/Kconfig | 17 + + drivers/gpu/drm/bridge/cadence/Makefile | 2 + + .../drm/bridge/cadence/cdns-mhdp8501-core.c | 379 +++++ + .../drm/bridge/cadence/cdns-mhdp8501-core.h | 380 +++++ + .../gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 694 ++++++++++ + .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 745 ++++++++++ + .../drm/bridge/cadence/cdns-mhdp8546-core.c | 487 ++----- .../drm/bridge/cadence/cdns-mhdp8546-core.h | 47 +- - .../drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 236 +--- + .../drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 212 +-- .../drm/bridge/cadence/cdns-mhdp8546-hdcp.h | 18 +- drivers/phy/freescale/Kconfig | 10 + drivers/phy/freescale/Makefile | 1 + - drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1237 +++++++++++++++++ - include/drm/bridge/cdns-mhdp-helper.h | 129 ++ + drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1231 +++++++++++++++++ + drivers/soc/Kconfig | 1 + + drivers/soc/Makefile | 1 + + drivers/soc/cadence/Kconfig | 9 + + drivers/soc/cadence/Makefile | 3 + + drivers/soc/cadence/cdns-mhdp-helper.c | 565 ++++++++ include/linux/phy/phy-hdmi.h | 19 + include/linux/phy/phy.h | 7 +- - 22 files changed, 4527 insertions(+), 680 deletions(-) + include/soc/cadence/cdns-mhdp-helper.h | 129 ++ + 26 files changed, 4572 insertions(+), 662 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml - create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c - create mode 100644 include/drm/bridge/cdns-mhdp-helper.h + create mode 100644 drivers/soc/cadence/Kconfig + create mode 100644 drivers/soc/cadence/Makefile + create mode 100644 drivers/soc/cadence/cdns-mhdp-helper.c create mode 100644 include/linux/phy/phy-hdmi.h + create mode 100644 include/soc/cadence/cdns-mhdp-helper.h -- 2.34.1 -From patchwork Tue Nov 26 14:11:46 2024 +From patchwork Tue Dec 17 06:51:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,1/8] drm: bridge: Cadence: Create MHDP helper driver +Subject: [v20,1/9] soc: cadence: Create helper functions for Cadence MHDP From: Sandor Yu -X-Patchwork-Id: 626189 +X-Patchwork-Id: 629288 Message-Id: - <4a6e511fed26289eeb63109882f7657ab5d4415d.1732627815.git.Sandor.yu@nxp.com> + <7fd5d54e2594aadd66598888ddf512f3d6d30e5d.1734340233.git.Sandor.yu@nxp.com> To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -377,80 +417,84 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:46 +0800 +Date: Tue, 17 Dec 2024 14:51:43 +0800 -Mailbox access functions in MHDP8546 will be share to other MHDP driver -and Cadence HDP-TX HDMI/DP PHY drivers. +Cadence MHDP IP includes a firmware. Driver and firmware communicate +through a mailbox. The basic mailbox access functions in this patch +are derived from the DRM bridge MHDP8546 driver. +New mailbox access functions have been created based on different mailbox +return values and security types, making them reusable across different +MHDP driver versions and SOCs. -Create a new MHDP helper driver and move all mailbox access functions into. -According the mailbox access sequence and type of security. -Six mailbox access API functions are introduced. -Three APIs for non-secure mailbox access: +These helper fucntions will be reused in both the DRM bridge driver MDHP8501 +and the i.MX8MQ HDPTX PHY driver. + +Six mailbox access helper functions are introduced. +Three for non-secure mailbox access: - cdns_mhdp_mailbox_send() - cdns_mhdp_mailbox_send_recv() - cdns_mhdp_mailbox_send_recv_multi() -The other three APIs for secure mailbox access: +The other three for secure mailbox access: - cdns_mhdp_secure_mailbox_send() - cdns_mhdp_secure_mailbox_send_recv() - cdns_mhdp_secure_mailbox_send_recv_multi() All MHDP commands that need to be passed through the mailbox -have been rewritten using those new API functions. +should be rewritten using these new helper functions. The register read/write and DP DPCD read/write command functions are also included in this new helper driver. -Function cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(), -because it use the DPTX command ID DPTX_WRITE_REGISTER. -New cdns_mhdp_reg_write() is added with the general command ID -GENERAL_REGISTER_WRITE. - Signed-off-by: Sandor Yu --- -v18->v19: -- Use guard(mutex) -- Add kerneldocs for all new APIs. -- Detail comments for mailbox access specific case. -- Remove cdns_mhdp_dp_reg_write() because it is not needed by driver now. +v19->v20: +- new patch in v20. + The patch split from Patch #1 in v19 and move to a new folder drivers/soc/cadence -v17->v18: -- Create three ordinary mailbox access APIs - cdns_mhdp_mailbox_send - cdns_mhdp_mailbox_send_recv - cdns_mhdp_mailbox_send_recv_multi -- Create three secure mailbox access APIs - cdns_mhdp_secure_mailbox_send - cdns_mhdp_secure_mailbox_send_recv - cdns_mhdp_secure_mailbox_send_recv_multi -- MHDP8546 DP and HDCP commands that need access mailbox are rewrited - with above 6 API functions. + drivers/soc/Kconfig | 1 + + drivers/soc/Makefile | 1 + + drivers/soc/cadence/Kconfig | 9 + + drivers/soc/cadence/Makefile | 3 + + drivers/soc/cadence/cdns-mhdp-helper.c | 565 +++++++++++++++++++++++++ + include/soc/cadence/cdns-mhdp-helper.h | 129 ++++++ + 6 files changed, 708 insertions(+) + create mode 100644 drivers/soc/cadence/Kconfig + create mode 100644 drivers/soc/cadence/Makefile + create mode 100644 drivers/soc/cadence/cdns-mhdp-helper.c + create mode 100644 include/soc/cadence/cdns-mhdp-helper.h -v16->v17: -- Replaces the local mutex mbox_mutex with a global mutex mhdp_mailbox_mutex - -v12->v16: - *No change. - - drivers/gpu/drm/bridge/cadence/Kconfig | 8 + - drivers/gpu/drm/bridge/cadence/Makefile | 1 + - .../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 565 ++++++++++++++++++ - .../drm/bridge/cadence/cdns-mhdp8546-core.c | 487 +++------------ - .../drm/bridge/cadence/cdns-mhdp8546-core.h | 47 +- - .../drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 236 +------- - .../drm/bridge/cadence/cdns-mhdp8546-hdcp.h | 18 +- - include/drm/bridge/cdns-mhdp-helper.h | 129 ++++ - 8 files changed, 812 insertions(+), 679 deletions(-) - create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c - create mode 100644 include/drm/bridge/cdns-mhdp-helper.h - -diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig -index cced81633ddcd..1b315593a6d73 100644 ---- a/drivers/gpu/drm/bridge/cadence/Kconfig -+++ b/drivers/gpu/drm/bridge/cadence/Kconfig -@@ -21,6 +21,13 @@ config DRM_CDNS_DSI_J721E - the routing of the DSS DPI signal to the Cadence DSI. - endif - +diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig +index 6a8daeb8c4b96..f6c18114b2d68 100644 +--- a/drivers/soc/Kconfig ++++ b/drivers/soc/Kconfig +@@ -6,6 +6,7 @@ source "drivers/soc/apple/Kconfig" + source "drivers/soc/aspeed/Kconfig" + source "drivers/soc/atmel/Kconfig" + source "drivers/soc/bcm/Kconfig" ++source "drivers/soc/cadence/Kconfig" + source "drivers/soc/canaan/Kconfig" + source "drivers/soc/cirrus/Kconfig" + source "drivers/soc/fsl/Kconfig" +diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile +index 2037a8695cb28..a5fa4f4d15321 100644 +--- a/drivers/soc/Makefile ++++ b/drivers/soc/Makefile +@@ -7,6 +7,7 @@ obj-y += apple/ + obj-y += aspeed/ + obj-$(CONFIG_ARCH_AT91) += atmel/ + obj-y += bcm/ ++obj-y += cadence/ + obj-$(CONFIG_ARCH_CANAAN) += canaan/ + obj-$(CONFIG_EP93XX_SOC) += cirrus/ + obj-$(CONFIG_ARCH_DOVE) += dove/ +diff --git a/drivers/soc/cadence/Kconfig b/drivers/soc/cadence/Kconfig +new file mode 100644 +index 0000000000000..b668790660fa5 +--- /dev/null ++++ b/drivers/soc/cadence/Kconfig +@@ -0,0 +1,9 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ +config CDNS_MHDP_HELPER + tristate "Cadence MHDP Helper driver" + help @@ -458,43 +502,29 @@ index cced81633ddcd..1b315593a6d73 100644 + This driver provides a foundational layer of mailbox communication for + various Cadence MHDP IP implementations, such as HDMI and DisplayPort. + - config DRM_CDNS_MHDP8546 - tristate "Cadence DPI/DP bridge" - select DRM_DISPLAY_DP_HELPER -@@ -28,6 +35,7 @@ config DRM_CDNS_MHDP8546 - select DRM_DISPLAY_HELPER - select DRM_KMS_HELPER - select DRM_PANEL_BRIDGE -+ select CDNS_MHDP_HELPER - depends on OF - help - Support Cadence DPI to DP bridge. This is an internal -diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile -index c95fd5b81d137..087dc074820d7 100644 ---- a/drivers/gpu/drm/bridge/cadence/Makefile -+++ b/drivers/gpu/drm/bridge/cadence/Makefile -@@ -2,6 +2,7 @@ - obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o - cdns-dsi-y := cdns-dsi-core.o - cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o -+obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o - obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o - cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o - cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o -diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c +diff --git a/drivers/soc/cadence/Makefile b/drivers/soc/cadence/Makefile new file mode 100644 -index 0000000000000..93b78f65dd8b8 +index 0000000000000..a1f42e1936ca5 --- /dev/null -+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c ++++ b/drivers/soc/cadence/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o +diff --git a/drivers/soc/cadence/cdns-mhdp-helper.c b/drivers/soc/cadence/cdns-mhdp-helper.c +new file mode 100644 +index 0000000000000..f74b4cae134a2 +--- /dev/null ++++ b/drivers/soc/cadence/cdns-mhdp-helper.c @@ -0,0 +1,565 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, 2024 NXP Semiconductor, Inc. + * + */ -+#include +#include +#include ++#include + +/* Protects mailbox communications with the firmware */ +static DEFINE_MUTEX(mhdp_mailbox_mutex); @@ -1052,8 +1082,228 @@ index 0000000000000..93b78f65dd8b8 +MODULE_DESCRIPTION("Cadence MHDP Helper driver"); +MODULE_AUTHOR("Sandor Yu "); +MODULE_LICENSE("GPL"); +diff --git a/include/soc/cadence/cdns-mhdp-helper.h b/include/soc/cadence/cdns-mhdp-helper.h +new file mode 100644 +index 0000000000000..25b9737de615f +--- /dev/null ++++ b/include/soc/cadence/cdns-mhdp-helper.h +@@ -0,0 +1,129 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2023-2024 NXP Semiconductor, Inc. ++ */ ++#ifndef __CDNS_MHDP_HELPER_H__ ++#define __CDNS_MHDP_HELPER_H__ ++ ++#include ++#include ++ ++/* mailbox regs offset */ ++#define CDNS_MAILBOX_FULL 0x00008 ++#define CDNS_MAILBOX_EMPTY 0x0000c ++#define CDNS_MAILBOX_TX_DATA 0x00010 ++#define CDNS_MAILBOX_RX_DATA 0x00014 ++ ++#define MAILBOX_RETRY_US 1000 ++#define MAILBOX_TIMEOUT_US 2000000 ++ ++/* Module ID Code */ ++#define MB_MODULE_ID_DP_TX 0x01 ++#define MB_MODULE_ID_HDMI_TX 0x03 ++#define MB_MODULE_ID_HDCP_TX 0x07 ++#define MB_MODULE_ID_HDCP_RX 0x08 ++#define MB_MODULE_ID_HDCP_GENERAL 0x09 ++#define MB_MODULE_ID_GENERAL 0x0A ++ ++/* General Commands */ ++#define GENERAL_MAIN_CONTROL 0x01 ++#define GENERAL_TEST_ECHO 0x02 ++#define GENERAL_BUS_SETTINGS 0x03 ++#define GENERAL_TEST_ACCESS 0x04 ++#define GENERAL_REGISTER_WRITE 0x05 ++#define GENERAL_WRITE_FIELD 0x06 ++#define GENERAL_REGISTER_READ 0x07 ++#define GENERAL_GET_HPD_STATE 0x11 ++ ++/* DPTX Commands */ ++#define DPTX_SET_POWER_MNG 0x00 ++#define DPTX_SET_HOST_CAPABILITIES 0x01 ++#define DPTX_GET_EDID 0x02 ++#define DPTX_READ_DPCD 0x03 ++#define DPTX_WRITE_DPCD 0x04 ++#define DPTX_ENABLE_EVENT 0x05 ++#define DPTX_WRITE_REGISTER 0x06 ++#define DPTX_READ_REGISTER 0x07 ++#define DPTX_WRITE_FIELD 0x08 ++#define DPTX_TRAINING_CONTROL 0x09 ++#define DPTX_READ_EVENT 0x0a ++#define DPTX_READ_LINK_STAT 0x0b ++#define DPTX_SET_VIDEO 0x0c ++#define DPTX_SET_AUDIO 0x0d ++#define DPTX_GET_LAST_AUX_STAUS 0x0e ++#define DPTX_SET_LINK_BREAK_POINT 0x0f ++#define DPTX_FORCE_LANES 0x10 ++#define DPTX_HPD_STATE 0x11 ++#define DPTX_ADJUST_LT 0x12 ++ ++/* HDMI TX Commands */ ++#define HDMI_TX_READ 0x00 ++#define HDMI_TX_WRITE 0x01 ++#define HDMI_TX_UPDATE_READ 0x02 ++#define HDMI_TX_EDID 0x03 ++#define HDMI_TX_EVENTS 0x04 ++#define HDMI_TX_HPD_STATUS 0x05 ++ ++/* HDCP TX Commands */ ++#define HDCP_TRAN_CONFIGURATION 0x00 ++#define HDCP2X_TX_SET_PUBLIC_KEY_PARAMS 0x01 ++#define HDCP2X_TX_SET_DEBUG_RANDOM_NUMBERS 0x02 ++#define HDCP2X_TX_RESPOND_KM 0x03 ++#define HDCP1_TX_SEND_KEYS 0x04 ++#define HDCP1_TX_SEND_RANDOM_AN 0x05 ++#define HDCP_TRAN_STATUS_CHANGE 0x06 ++#define HDCP2X_TX_IS_KM_STORED 0x07 ++#define HDCP2X_TX_STORE_KM 0x08 ++#define HDCP_TRAN_IS_REC_ID_VALID 0x09 ++#define HDCP_TRAN_RESPOND_RECEIVER_ID_VALID 0x09 ++#define HDCP_TRAN_TEST_KEYS 0x0a ++#define HDCP2X_TX_SET_KM_KEY_PARAMS 0x0b ++#define HDCP_NUM_OF_SUPPORTED_MESSAGES 0x0c ++ ++struct cdns_mhdp_base { ++ struct device *dev; ++ void __iomem *regs; ++ void __iomem *sapb_regs; ++}; ++ ++/* Mailbox helper functions */ ++int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, ++ u8 module_id, u8 opcode, ++ u16 size, u8 *message); ++int cdns_mhdp_mailbox_send_recv(struct cdns_mhdp_base *base, ++ u8 module_id, u8 opcode, ++ u16 msg_size, u8 *msg, ++ u16 resp_size, u8 *resp); ++int cdns_mhdp_mailbox_send_recv_multi(struct cdns_mhdp_base *base, ++ u8 module_id, u8 opcode, ++ u16 msg_size, u8 *msg, ++ u8 opcode_resp, ++ u16 resp1_size, u8 *resp1, ++ u16 resp2_size, u8 *resp2); ++ ++/* Secure mailbox helper functions */ ++int cdns_mhdp_secure_mailbox_send(struct cdns_mhdp_base *base, ++ u8 module_id, u8 opcode, ++ u16 size, u8 *message); ++int cdns_mhdp_secure_mailbox_send_recv(struct cdns_mhdp_base *base, ++ u8 module_id, u8 opcode, ++ u16 msg_size, u8 *msg, ++ u16 resp_size, u8 *resp); ++int cdns_mhdp_secure_mailbox_send_recv_multi(struct cdns_mhdp_base *base, ++ u8 module_id, u8 opcode, ++ u16 msg_size, u8 *msg, ++ u8 opcode_resp, ++ u16 resp1_size, u8 *resp1, ++ u16 resp2_size, u8 *resp2); ++ ++/* General commands helper functions */ ++int cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32 *value); ++int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32 val); ++ ++/* DPTX commands helper functions */ ++int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr, ++ u8 start_bit, u8 bits_no, u32 val); ++int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base, ++ u32 addr, u8 *data, u16 len); ++int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8 value); ++#endif /* __CDNS_MHDP_HELPER_H__ */ + +From patchwork Tue Dec 17 06:51:44 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v20,2/9] drm: bridge: cadence: Update mhdp8546 mailbox access + functions +From: Sandor Yu +X-Patchwork-Id: 629289 +Message-Id: + <74bc3f2ff56348afd9d773589236ddf06dc3d45c.1734340233.git.Sandor.yu@nxp.com> +To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, + neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, + jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, + daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, + shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, + vkoul@kernel.org, dri-devel@lists.freedesktop.org, + devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, + mripard@kernel.org +Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, + oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org +Date: Tue, 17 Dec 2024 14:51:44 +0800 + +Basic mailbox access functions are removed, they are replaced by +mailbox helper functions: +- cdns_mhdp_mailbox_send() +- cdns_mhdp_mailbox_send_recv() +- cdns_mhdp_mailbox_send_recv_multi() +- cdns_mhdp_secure_mailbox_send() +- cdns_mhdp_secure_mailbox_send_recv() +- cdns_mhdp_secure_mailbox_send_recv_multi() + +All MHDP commands that need to be passed through the mailbox +have been rewritten using these new helper functions. + +Signed-off-by: Sandor Yu +Reviewed-by: Dmitry Baryshkov +--- +v19->v20: +- remove mhdp helper functions from the patch. + +v18->v19: +- Use guard(mutex) +- Add kerneldocs for all new APIs. +- Detail comments for mailbox access specific case. +- Remove cdns_mhdp_dp_reg_write() because it is not needed by driver now. + +v17->v18: +- Create three ordinary mailbox access APIs + cdns_mhdp_mailbox_send + cdns_mhdp_mailbox_send_recv + cdns_mhdp_mailbox_send_recv_multi +- Create three secure mailbox access APIs + cdns_mhdp_secure_mailbox_send + cdns_mhdp_secure_mailbox_send_recv + cdns_mhdp_secure_mailbox_send_recv_multi +- MHDP8546 DP and HDCP commands that need access mailbox are rewrited + with above 6 API functions. + +v16->v17: +- Replaces the local mutex mbox_mutex with a global mutex mhdp_mailbox_mutex + +v12->v16: + *No change. + + drivers/gpu/drm/bridge/cadence/Kconfig | 1 + + .../drm/bridge/cadence/cdns-mhdp8546-core.c | 487 +++--------------- + .../drm/bridge/cadence/cdns-mhdp8546-core.h | 47 +- + .../drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 212 +------- + .../drm/bridge/cadence/cdns-mhdp8546-hdcp.h | 18 +- + 5 files changed, 104 insertions(+), 661 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig +index cced81633ddcd..dbb06533ccab2 100644 +--- a/drivers/gpu/drm/bridge/cadence/Kconfig ++++ b/drivers/gpu/drm/bridge/cadence/Kconfig +@@ -28,6 +28,7 @@ config DRM_CDNS_MHDP8546 + select DRM_DISPLAY_HELPER + select DRM_KMS_HELPER + select DRM_PANEL_BRIDGE ++ select CDNS_MHDP_HELPER + depends on OF + help + Support Cadence DPI to DP bridge. This is an internal diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c -index 41f72d458487f..9ce1fcf7b88ea 100644 +index d081850e3c03e..bd897c3ae7642 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c @@ -73,302 +73,18 @@ static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge) @@ -1817,17 +2067,17 @@ index 41f72d458487f..9ce1fcf7b88ea 100644 clk_prepare_enable(clk); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h -index bad2fc0c73066..d209c7b3bbfab 100644 +index bad2fc0c73066..535300d040dea 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h -@@ -15,6 +15,7 @@ - #include - #include - -+#include +@@ -18,6 +18,7 @@ #include #include #include ++#include + + struct clk; + struct device; @@ -27,10 +28,6 @@ struct phy; #define CDNS_APB_CTRL 0x00000 #define CDNS_CPU_STALL BIT(3) @@ -1906,7 +2156,7 @@ index bad2fc0c73066..d209c7b3bbfab 100644 * "link_mutex" protects the access to all the link parameters * including the link training process. Link training will be diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c -index 31832ba4017f1..0d3979577a924 100644 +index 42248f179b69d..3944642f2ebbc 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c @@ -15,144 +15,20 @@ @@ -2090,6 +2340,10 @@ index 31832ba4017f1..0d3979577a924 100644 - ret = cdns_mhdp_secure_mailbox_recv_header(mhdp, MB_MODULE_ID_HDCP_TX, - HDCP_TRAN_IS_REC_ID_VALID, - sizeof(status)); +- if (ret) +- goto err_rx_id_valid; +- +- ret = cdns_mhdp_secure_mailbox_recv_data(mhdp, rec_id_hdr, 2); + ret = cdns_mhdp_secure_mailbox_send_recv_multi(&mhdp->base, + MB_MODULE_ID_HDCP_TX, + HDCP_TRAN_IS_REC_ID_VALID, @@ -2099,10 +2353,6 @@ index 31832ba4017f1..0d3979577a924 100644 + 0, hdcp_rx_id); if (ret) - goto err_rx_id_valid; -- -- ret = cdns_mhdp_secure_mailbox_recv_data(mhdp, rec_id_hdr, 2); -- if (ret) -- goto err_rx_id_valid; + return ret; *recv_num = rec_id_hdr[0]; @@ -2174,52 +2424,15 @@ index 31832ba4017f1..0d3979577a924 100644 } static int cdns_mhdp_hdcp_set_config(struct cdns_mhdp_device *mhdp, -@@ -502,30 +332,18 @@ static void cdns_mhdp_hdcp_prop_work(struct work_struct *work) - - int cdns_mhdp_hdcp_set_lc(struct cdns_mhdp_device *mhdp, u8 *val) - { -- int ret; -- -- mutex_lock(&mhdp->mbox_mutex); -- ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_GENERAL, -- HDCP_GENERAL_SET_LC_128, -- 16, val); -- mutex_unlock(&mhdp->mbox_mutex); -- -- return ret; -+ return cdns_mhdp_secure_mailbox_send(&mhdp->base, MB_MODULE_ID_HDCP_GENERAL, -+ HDCP_GENERAL_SET_LC_128, -+ 16, val); - } - - int - cdns_mhdp_hdcp_set_public_key_param(struct cdns_mhdp_device *mhdp, - struct cdns_hdcp_tx_public_key_param *val) - { -- int ret; -- -- mutex_lock(&mhdp->mbox_mutex); -- ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, -- HDCP2X_TX_SET_PUBLIC_KEY_PARAMS, -- sizeof(*val), (u8 *)val); -- mutex_unlock(&mhdp->mbox_mutex); -- -- return ret; -+ return cdns_mhdp_secure_mailbox_send(&mhdp->base, MB_MODULE_ID_HDCP_TX, -+ HDCP2X_TX_SET_PUBLIC_KEY_PARAMS, -+ sizeof(*val), (u8 *)val); - } - - int cdns_mhdp_hdcp_enable(struct cdns_mhdp_device *mhdp, u8 content_type) diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h -index 334c0b8b0d4f5..fff4194c7dfd0 100644 +index 3b6ec9c3a8d8b..1e68530e72229 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h @@ -9,6 +9,7 @@ #ifndef CDNS_MHDP8546_HDCP_H #define CDNS_MHDP8546_HDCP_H -+#include ++#include #include "cdns-mhdp8546-core.h" #define HDCP_MAX_RECEIVERS 32 @@ -2247,151 +2460,16 @@ index 334c0b8b0d4f5..fff4194c7dfd0 100644 enum { HDCP_CONTENT_TYPE_0, HDCP_CONTENT_TYPE_1, -diff --git a/include/drm/bridge/cdns-mhdp-helper.h b/include/drm/bridge/cdns-mhdp-helper.h -new file mode 100644 -index 0000000000000..25b9737de615f ---- /dev/null -+++ b/include/drm/bridge/cdns-mhdp-helper.h -@@ -0,0 +1,129 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2023-2024 NXP Semiconductor, Inc. -+ */ -+#ifndef __CDNS_MHDP_HELPER_H__ -+#define __CDNS_MHDP_HELPER_H__ -+ -+#include -+#include -+ -+/* mailbox regs offset */ -+#define CDNS_MAILBOX_FULL 0x00008 -+#define CDNS_MAILBOX_EMPTY 0x0000c -+#define CDNS_MAILBOX_TX_DATA 0x00010 -+#define CDNS_MAILBOX_RX_DATA 0x00014 -+ -+#define MAILBOX_RETRY_US 1000 -+#define MAILBOX_TIMEOUT_US 2000000 -+ -+/* Module ID Code */ -+#define MB_MODULE_ID_DP_TX 0x01 -+#define MB_MODULE_ID_HDMI_TX 0x03 -+#define MB_MODULE_ID_HDCP_TX 0x07 -+#define MB_MODULE_ID_HDCP_RX 0x08 -+#define MB_MODULE_ID_HDCP_GENERAL 0x09 -+#define MB_MODULE_ID_GENERAL 0x0A -+ -+/* General Commands */ -+#define GENERAL_MAIN_CONTROL 0x01 -+#define GENERAL_TEST_ECHO 0x02 -+#define GENERAL_BUS_SETTINGS 0x03 -+#define GENERAL_TEST_ACCESS 0x04 -+#define GENERAL_REGISTER_WRITE 0x05 -+#define GENERAL_WRITE_FIELD 0x06 -+#define GENERAL_REGISTER_READ 0x07 -+#define GENERAL_GET_HPD_STATE 0x11 -+ -+/* DPTX Commands */ -+#define DPTX_SET_POWER_MNG 0x00 -+#define DPTX_SET_HOST_CAPABILITIES 0x01 -+#define DPTX_GET_EDID 0x02 -+#define DPTX_READ_DPCD 0x03 -+#define DPTX_WRITE_DPCD 0x04 -+#define DPTX_ENABLE_EVENT 0x05 -+#define DPTX_WRITE_REGISTER 0x06 -+#define DPTX_READ_REGISTER 0x07 -+#define DPTX_WRITE_FIELD 0x08 -+#define DPTX_TRAINING_CONTROL 0x09 -+#define DPTX_READ_EVENT 0x0a -+#define DPTX_READ_LINK_STAT 0x0b -+#define DPTX_SET_VIDEO 0x0c -+#define DPTX_SET_AUDIO 0x0d -+#define DPTX_GET_LAST_AUX_STAUS 0x0e -+#define DPTX_SET_LINK_BREAK_POINT 0x0f -+#define DPTX_FORCE_LANES 0x10 -+#define DPTX_HPD_STATE 0x11 -+#define DPTX_ADJUST_LT 0x12 -+ -+/* HDMI TX Commands */ -+#define HDMI_TX_READ 0x00 -+#define HDMI_TX_WRITE 0x01 -+#define HDMI_TX_UPDATE_READ 0x02 -+#define HDMI_TX_EDID 0x03 -+#define HDMI_TX_EVENTS 0x04 -+#define HDMI_TX_HPD_STATUS 0x05 -+ -+/* HDCP TX Commands */ -+#define HDCP_TRAN_CONFIGURATION 0x00 -+#define HDCP2X_TX_SET_PUBLIC_KEY_PARAMS 0x01 -+#define HDCP2X_TX_SET_DEBUG_RANDOM_NUMBERS 0x02 -+#define HDCP2X_TX_RESPOND_KM 0x03 -+#define HDCP1_TX_SEND_KEYS 0x04 -+#define HDCP1_TX_SEND_RANDOM_AN 0x05 -+#define HDCP_TRAN_STATUS_CHANGE 0x06 -+#define HDCP2X_TX_IS_KM_STORED 0x07 -+#define HDCP2X_TX_STORE_KM 0x08 -+#define HDCP_TRAN_IS_REC_ID_VALID 0x09 -+#define HDCP_TRAN_RESPOND_RECEIVER_ID_VALID 0x09 -+#define HDCP_TRAN_TEST_KEYS 0x0a -+#define HDCP2X_TX_SET_KM_KEY_PARAMS 0x0b -+#define HDCP_NUM_OF_SUPPORTED_MESSAGES 0x0c -+ -+struct cdns_mhdp_base { -+ struct device *dev; -+ void __iomem *regs; -+ void __iomem *sapb_regs; -+}; -+ -+/* Mailbox helper functions */ -+int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, -+ u8 module_id, u8 opcode, -+ u16 size, u8 *message); -+int cdns_mhdp_mailbox_send_recv(struct cdns_mhdp_base *base, -+ u8 module_id, u8 opcode, -+ u16 msg_size, u8 *msg, -+ u16 resp_size, u8 *resp); -+int cdns_mhdp_mailbox_send_recv_multi(struct cdns_mhdp_base *base, -+ u8 module_id, u8 opcode, -+ u16 msg_size, u8 *msg, -+ u8 opcode_resp, -+ u16 resp1_size, u8 *resp1, -+ u16 resp2_size, u8 *resp2); -+ -+/* Secure mailbox helper functions */ -+int cdns_mhdp_secure_mailbox_send(struct cdns_mhdp_base *base, -+ u8 module_id, u8 opcode, -+ u16 size, u8 *message); -+int cdns_mhdp_secure_mailbox_send_recv(struct cdns_mhdp_base *base, -+ u8 module_id, u8 opcode, -+ u16 msg_size, u8 *msg, -+ u16 resp_size, u8 *resp); -+int cdns_mhdp_secure_mailbox_send_recv_multi(struct cdns_mhdp_base *base, -+ u8 module_id, u8 opcode, -+ u16 msg_size, u8 *msg, -+ u8 opcode_resp, -+ u16 resp1_size, u8 *resp1, -+ u16 resp2_size, u8 *resp2); -+ -+/* General commands helper functions */ -+int cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32 *value); -+int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32 val); -+ -+/* DPTX commands helper functions */ -+int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr, -+ u8 start_bit, u8 bits_no, u32 val); -+int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base, -+ u32 addr, u8 *data, u16 len); -+int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8 value); -+#endif /* __CDNS_MHDP_HELPER_H__ */ -From patchwork Tue Nov 26 14:11:47 2024 +From patchwork Tue Dec 17 06:51:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,2/8] phy: Add HDMI configuration options +Subject: [v20,3/9] phy: Add HDMI configuration options From: Sandor Yu -X-Patchwork-Id: 626190 +X-Patchwork-Id: 629290 Message-Id: - <43757beec6cd418fc17252283de38009d531c7c7.1732627815.git.Sandor.yu@nxp.com> + To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -2403,7 +2481,7 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:47 +0800 +Date: Tue, 17 Dec 2024 14:51:45 +0800 Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union. @@ -2415,7 +2493,11 @@ should cover the potential users. Signed-off-by: Sandor Yu Reviewed-by: Dmitry Baryshkov Reviewed-by: Maxime Ripard +Acked-by: Vinod Koul --- +v19->v20: +- Add a-b tag. + v17->v19: *No change. @@ -2492,15 +2574,15 @@ index 03cd5bae92d3f..4ac486b101fe4 100644 /** -From patchwork Tue Nov 26 14:11:48 2024 +From patchwork Tue Dec 17 06:51:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,3/8] dt-bindings: display: bridge: Add Cadence MHDP8501 +Subject: [v20,4/9] dt-bindings: display: bridge: Add Cadence MHDP8501 From: Sandor Yu -X-Patchwork-Id: 626191 +X-Patchwork-Id: 629291 Message-Id: - + To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -2512,12 +2594,16 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:48 +0800 +Date: Tue, 17 Dec 2024 14:51:46 +0800 Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge. Signed-off-by: Sandor Yu +Reviewed-by: Krzysztof Kozlowski --- +v19->v20: +- remove data type link of data-lanes. + v18->v19: - move data-lanes property to endpoint of port@1 @@ -2531,16 +2617,16 @@ v16->v17: v9->v16: *No change - .../display/bridge/cdns,mhdp8501.yaml | 120 ++++++++++++++++++ - 1 file changed, 120 insertions(+) + .../display/bridge/cdns,mhdp8501.yaml | 121 ++++++++++++++++++ + 1 file changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file mode 100644 -index 0000000000000..24abd8447a28c +index 0000000000000..2417f4038b437 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml -@@ -0,0 +1,120 @@ +@@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- @@ -2604,12 +2690,13 @@ index 0000000000000..24abd8447a28c + + properties: + data-lanes: -+ $ref: /schemas/media/video-interfaces.yaml#/properties/data-lanes ++ description: Lane reordering for HDMI or DisplayPort interface. + minItems: 4 + maxItems: 4 -+ description: Lane reordering for HDMI or DisplayPort interface. ++ + required: + - data-lanes ++ + required: + - port@0 + - port@1 @@ -2662,15 +2749,15 @@ index 0000000000000..24abd8447a28c + }; + }; -From patchwork Tue Nov 26 14:11:49 2024 +From patchwork Tue Dec 17 06:51:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,4/8] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver +Subject: [v20,5/9] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver From: Sandor Yu -X-Patchwork-Id: 626192 +X-Patchwork-Id: 629292 Message-Id: - + To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -2682,7 +2769,7 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:49 +0800 +Date: Tue, 17 Dec 2024 14:51:47 +0800 Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501 used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort @@ -2697,6 +2784,18 @@ then load the corresponding driver. Signed-off-by: Sandor Yu --- +v19->v20: +- Dump mhdp FW version by debugfs +- Combine HDMI and DP cable detect functions into one function +- Combine HDMI and DP cable bridge_mode_valid() functions into one function +- Rename cdns_hdmi_reset_link() to cdns_hdmi_handle_hotplug() +- Add comments for EDID in cdns_hdmi_handle_hotplug() and cdns_dp_check_link_state() +- Add atomic_get_input_bus_fmts() and bridge_atomic_check() for DP driver +- Remove bpc and color_fmt init in atomic_enable() function. +- More detail comments for DDC adapter only support SCDC_I2C_SLAVE_ADDRESS + read and write in HDMI driver. + + v18->v19: - Get endpoint for data-lanes as it had move to endpoint of port@1 - Update clock management as devm_clk_get_enabled() introduced. @@ -2722,21 +2821,21 @@ v17->v18: drivers/gpu/drm/bridge/cadence/Kconfig | 16 + drivers/gpu/drm/bridge/cadence/Makefile | 2 + - .../drm/bridge/cadence/cdns-mhdp8501-core.c | 322 ++++++++ - .../drm/bridge/cadence/cdns-mhdp8501-core.h | 376 +++++++++ - .../gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 686 ++++++++++++++++ - .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 764 ++++++++++++++++++ - 6 files changed, 2166 insertions(+) + .../drm/bridge/cadence/cdns-mhdp8501-core.c | 379 +++++++++ + .../drm/bridge/cadence/cdns-mhdp8501-core.h | 380 +++++++++ + .../gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 694 ++++++++++++++++ + .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 745 ++++++++++++++++++ + 6 files changed, 2216 insertions(+) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig -index 1b315593a6d73..dc7a0466bb020 100644 +index dbb06533ccab2..bd979f3e6df48 100644 --- a/drivers/gpu/drm/bridge/cadence/Kconfig +++ b/drivers/gpu/drm/bridge/cadence/Kconfig -@@ -55,3 +55,19 @@ config DRM_CDNS_MHDP8546_J721E +@@ -48,3 +48,19 @@ config DRM_CDNS_MHDP8546_J721E initializes the J721E Display Port and sets up the clock and data muxes. endif @@ -2747,8 +2846,8 @@ index 1b315593a6d73..dc7a0466bb020 100644 + select DRM_PANEL_BRIDGE + select DRM_DISPLAY_DP_HELPER + select DRM_DISPLAY_HELPER -+ select CDNS_MHDP_HELPER + select DRM_CDNS_AUDIO ++ select CDNS_MHDP_HELPER + depends on OF + help + Support Cadence MHDP8501 DisplayPort/HDMI bridge. @@ -2757,10 +2856,10 @@ index 1b315593a6d73..dc7a0466bb020 100644 + To use the DP and HDMI drivers, their respective + specific firmware is required. diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile -index 087dc074820d7..02c1a9f3cf6fc 100644 +index c95fd5b81d137..ea327287d1c14 100644 --- a/drivers/gpu/drm/bridge/cadence/Makefile +++ b/drivers/gpu/drm/bridge/cadence/Makefile -@@ -6,3 +6,5 @@ obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o +@@ -5,3 +5,5 @@ cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o @@ -2768,10 +2867,10 @@ index 087dc074820d7..02c1a9f3cf6fc 100644 +cdns-mhdp8501-y := cdns-mhdp8501-core.o cdns-mhdp8501-dp.o cdns-mhdp8501-hdmi.o diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c new file mode 100644 -index 0000000000000..c51696b586dd0 +index 0000000000000..98116ef012fa3 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c -@@ -0,0 +1,322 @@ +@@ -0,0 +1,379 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence Display Port Interface (DP) driver @@ -2790,6 +2889,35 @@ index 0000000000000..c51696b586dd0 + +#include "cdns-mhdp8501-core.h" + ++static ssize_t firmware_version_show(struct device *dev, ++ struct device_attribute *attr, char *buf); ++static struct device_attribute firmware_version = __ATTR_RO(firmware_version); ++ ++ssize_t firmware_version_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct cdns_mhdp8501_device *mhdp = dev_get_drvdata(dev); ++ ++ u32 version = readl(mhdp->base.regs + VER_L) | readl(mhdp->base.regs + VER_H) << 8; ++ u32 lib_version = readl(mhdp->base.regs + VER_LIB_L_ADDR) | ++ readl(mhdp->base.regs + VER_LIB_H_ADDR) << 8; ++ ++ return sprintf(buf, "FW version %d, Lib version %d\n", version, lib_version); ++} ++ ++static void cdns_mhdp8501_create_device_files(struct cdns_mhdp8501_device *mhdp) ++{ ++ if (device_create_file(mhdp->dev, &firmware_version)) { ++ DRM_ERROR("Unable to create firmware_version sysfs\n"); ++ device_remove_file(mhdp->dev, &firmware_version); ++ } ++} ++ ++static void cdns_mhdp8501_remove_device_files(struct cdns_mhdp8501_device *mhdp) ++{ ++ device_remove_file(mhdp->dev, &firmware_version); ++} ++ +static int cdns_mhdp8501_read_hpd(struct cdns_mhdp8501_device *mhdp) +{ + u8 status; @@ -2806,8 +2934,10 @@ index 0000000000000..c51696b586dd0 + return status; +} + -+enum drm_connector_status cdns_mhdp8501_detect(struct cdns_mhdp8501_device *mhdp) ++enum drm_connector_status cdns_mhdp8501_detect(struct drm_bridge *bridge) +{ ++ struct cdns_mhdp8501_device *mhdp = bridge->driver_private; ++ + u8 hpd = 0xf; + + hpd = cdns_mhdp8501_read_hpd(mhdp); @@ -2819,12 +2949,34 @@ index 0000000000000..c51696b586dd0 + return connector_status_unknown; +} + ++enum drm_mode_status ++cdns_mhdp8501_mode_valid(struct drm_bridge *bridge, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode) ++{ ++ /* We don't support double-clocked */ ++ if (mode->flags & DRM_MODE_FLAG_DBLCLK) ++ return MODE_BAD; ++ ++ /* MAX support pixel clock rate 594MHz */ ++ if (mode->clock > 594000) ++ return MODE_CLOCK_HIGH; ++ ++ if (mode->hdisplay > 3840) ++ return MODE_BAD_HVALUE; ++ ++ if (mode->vdisplay > 2160) ++ return MODE_BAD_VVALUE; ++ ++ return MODE_OK; ++} ++ +static void hotplug_work_func(struct work_struct *work) +{ + struct cdns_mhdp8501_device *mhdp = container_of(work, + struct cdns_mhdp8501_device, + hotplug_work.work); -+ enum drm_connector_status status = cdns_mhdp8501_detect(mhdp); ++ enum drm_connector_status status = cdns_mhdp8501_detect(&mhdp->bridge); + + drm_bridge_hpd_notify(&mhdp->bridge, status); + @@ -2840,7 +2992,7 @@ index 0000000000000..c51696b586dd0 + + /* Reset HDMI/DP link with sink */ + if (mhdp->connector_type == DRM_MODE_CONNECTOR_HDMIA) -+ cdns_hdmi_reset_link(mhdp); ++ cdns_hdmi_handle_hotplug(mhdp); + else + cdns_dp_check_link_state(mhdp); + @@ -2972,6 +3124,8 @@ index 0000000000000..c51696b586dd0 + if (IS_ERR(mhdp->regs)) + return PTR_ERR(mhdp->regs); + ++ cdns_mhdp8501_create_device_files(mhdp); ++ + ret = cdns_mhdp8501_dt_parse(mhdp, pdev); + if (ret < 0) + return -EINVAL; @@ -3067,6 +3221,8 @@ index 0000000000000..c51696b586dd0 +{ + struct cdns_mhdp8501_device *mhdp = platform_get_drvdata(pdev); + ++ cdns_mhdp8501_remove_device_files(mhdp); ++ + if (mhdp->connector_type == DRM_MODE_CONNECTOR_DisplayPort) + cdns_dp_aux_destroy(mhdp); + @@ -3096,10 +3252,10 @@ index 0000000000000..c51696b586dd0 +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h new file mode 100644 -index 0000000000000..a8b7e54f629e2 +index 0000000000000..8fc463098ab84 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h -@@ -0,0 +1,376 @@ +@@ -0,0 +1,380 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Cadence MHDP 8501 Common head file @@ -3111,12 +3267,12 @@ index 0000000000000..a8b7e54f629e2 +#ifndef _CDNS_MHDP8501_CORE_H_ +#define _CDNS_MHDP8501_CORE_H_ + -+#include +#include +#include +#include +#include +#include ++#include + +#define ADDR_IMEM 0x10000 +#define ADDR_DMEM 0x20000 @@ -3467,21 +3623,25 @@ index 0000000000000..a8b7e54f629e2 +extern const struct drm_bridge_funcs cdns_hdmi_bridge_funcs; + +enum drm_connector_status -+cdns_mhdp8501_detect(struct cdns_mhdp8501_device *mhdp); ++cdns_mhdp8501_detect(struct drm_bridge *bridge); ++enum drm_mode_status ++cdns_mhdp8501_mode_valid(struct drm_bridge *bridge, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode); + +ssize_t cdns_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); +int cdns_dp_aux_destroy(struct cdns_mhdp8501_device *mhdp); +void cdns_dp_check_link_state(struct cdns_mhdp8501_device *mhdp); + -+void cdns_hdmi_reset_link(struct cdns_mhdp8501_device *mhdp); ++void cdns_hdmi_handle_hotplug(struct cdns_mhdp8501_device *mhdp); +struct i2c_adapter *cdns_hdmi_i2c_adapter(struct cdns_mhdp8501_device *mhdp); +#endif diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file mode 100644 -index 0000000000000..392bb65f6c9c1 +index 0000000000000..157b4d44b9e2b --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c -@@ -0,0 +1,686 @@ +@@ -0,0 +1,694 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence MHDP8501 DisplayPort(DP) bridge driver @@ -3492,6 +3652,7 @@ index 0000000000000..392bb65f6c9c1 +#include +#include +#include ++#include +#include +#include + @@ -4004,6 +4165,10 @@ index 0000000000000..392bb65f6c9c1 + if (!connector) + return; + ++ /* ++ * EDID data needs updating after each cable plugin ++ * due to potential display monitor changes ++ */ + drm_edid = drm_edid_read_custom(connector, cdns_dp_get_edid_block, mhdp); + drm_edid_connector_update(connector, drm_edid); + @@ -4044,39 +4209,6 @@ index 0000000000000..392bb65f6c9c1 + return drm_dp_aux_register(&mhdp->dp.aux); +} + -+static enum drm_mode_status -+cdns_dp_bridge_mode_valid(struct drm_bridge *bridge, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ enum drm_mode_status mode_status = MODE_OK; -+ -+ /* We don't support double-clocked modes */ -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK || -+ mode->flags & DRM_MODE_FLAG_INTERLACE) -+ return MODE_BAD; -+ -+ /* MAX support pixel clock rate 594MHz */ -+ if (mode->clock > 594000) -+ return MODE_CLOCK_HIGH; -+ -+ if (mode->hdisplay > 3840) -+ return MODE_BAD_HVALUE; -+ -+ if (mode->vdisplay > 2160) -+ return MODE_BAD_VVALUE; -+ -+ return mode_status; -+} -+ -+static enum drm_connector_status -+cdns_dp_bridge_detect(struct drm_bridge *bridge) -+{ -+ struct cdns_mhdp8501_device *mhdp = bridge->driver_private; -+ -+ return cdns_mhdp8501_detect(mhdp); -+} -+ +static const struct drm_edid +*cdns_dp_bridge_edid_read(struct drm_bridge *bridge, + struct drm_connector *connector) @@ -4086,6 +4218,56 @@ index 0000000000000..392bb65f6c9c1 + return drm_edid_read_custom(connector, cdns_dp_get_edid_block, mhdp); +} + ++/* Currently supported format */ ++static const u32 mhdp8501_input_fmts[] = { ++ MEDIA_BUS_FMT_RGB888_1X24, ++ MEDIA_BUS_FMT_RGB101010_1X30, ++}; ++ ++static u32 *cdns_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ u32 output_fmt, ++ unsigned int *num_input_fmts) ++{ ++ u32 *input_fmts; ++ ++ *num_input_fmts = 0; ++ ++ input_fmts = kcalloc(ARRAY_SIZE(mhdp8501_input_fmts), ++ sizeof(*input_fmts), ++ GFP_KERNEL); ++ if (!input_fmts) ++ return NULL; ++ ++ *num_input_fmts = ARRAY_SIZE(mhdp8501_input_fmts); ++ memcpy(input_fmts, mhdp8501_input_fmts, sizeof(mhdp8501_input_fmts)); ++ ++ return input_fmts; ++} ++ ++static int cdns_dp_bridge_atomic_check(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) ++{ ++ struct cdns_mhdp8501_device *mhdp = bridge->driver_private; ++ struct video_info *video = &mhdp->video_info; ++ ++ if (bridge_state->input_bus_cfg.format == MEDIA_BUS_FMT_RGB888_1X24) { ++ video->bpc = 8; ++ video->color_fmt = DRM_COLOR_FORMAT_RGB444; ++ } else if (bridge_state->input_bus_cfg.format == MEDIA_BUS_FMT_RGB101010_1X30) { ++ video->bpc = 10; ++ video->color_fmt = DRM_COLOR_FORMAT_RGB444; ++ } else { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ +static void cdns_dp_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_state) +{ @@ -4103,7 +4285,6 @@ index 0000000000000..392bb65f6c9c1 + struct cdns_mhdp8501_device *mhdp = bridge->driver_private; + struct drm_atomic_state *state = old_state->base.state; + struct drm_connector *connector; -+ struct video_info *video = &mhdp->video_info; + struct drm_crtc_state *crtc_state; + struct drm_connector_state *conn_state; + int ret; @@ -4123,21 +4304,6 @@ index 0000000000000..392bb65f6c9c1 + if (WARN_ON(!crtc_state)) + return; + -+ switch (connector->display_info.bpc) { -+ case 10: -+ video->bpc = 10; -+ break; -+ case 6: -+ video->bpc = 6; -+ break; -+ default: -+ video->bpc = 8; -+ break; -+ } -+ -+ /* The only currently supported format */ -+ video->color_fmt = DRM_COLOR_FORMAT_RGB444; -+ + cdns_dp_mode_set(mhdp, &crtc_state->adjusted_mode); + + /* Power up PHY before link training */ @@ -4159,21 +4325,23 @@ index 0000000000000..392bb65f6c9c1 + +const struct drm_bridge_funcs cdns_dp_bridge_funcs = { + .attach = cdns_dp_bridge_attach, -+ .detect = cdns_dp_bridge_detect, ++ .detect = cdns_mhdp8501_detect, + .edid_read = cdns_dp_bridge_edid_read, -+ .mode_valid = cdns_dp_bridge_mode_valid, ++ .mode_valid = cdns_mhdp8501_mode_valid, + .atomic_enable = cdns_dp_bridge_atomic_enable, + .atomic_disable = cdns_dp_bridge_atomic_disable, ++ .atomic_get_input_bus_fmts = cdns_dp_bridge_atomic_get_input_bus_fmts, ++ .atomic_check = cdns_dp_bridge_atomic_check, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, +}; diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file mode 100644 -index 0000000000000..f7cafc153a58e +index 0000000000000..9556d0929e21d --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c -@@ -0,0 +1,764 @@ +@@ -0,0 +1,745 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence MHDP8501 HDMI bridge driver @@ -4566,7 +4734,7 @@ index 0000000000000..f7cafc153a58e + return ret; +} + -+void cdns_hdmi_reset_link(struct cdns_mhdp8501_device *mhdp) ++void cdns_hdmi_handle_hotplug(struct cdns_mhdp8501_device *mhdp) +{ + struct drm_connector *connector = mhdp->curr_conn; + const struct drm_edid *drm_edid; @@ -4577,6 +4745,10 @@ index 0000000000000..f7cafc153a58e + if (!connector) + return; + ++ /* ++ * EDID data needs updating after each cable plugin ++ * due to potential display monitor changes ++ */ + drm_edid = drm_edid_read_custom(connector, cdns_hdmi_get_edid_block, mhdp); + drm_edid_connector_update(connector, drm_edid); + @@ -4675,7 +4847,11 @@ index 0000000000000..f7cafc153a58e + struct cdns_hdmi_i2c *i2c = mhdp->hdmi.i2c; + int i, ret = 0; + -+ /* Only support SCDC I2C Read/Write */ ++ /* ++ * MHDP FW provides mailbox APIs for SCDC registers access, but lacks direct I2C APIs. ++ * While individual I2C registers can be read/written using HDMI general register APIs, ++ * block reads (e.g., EDID) are not supported, making it a limited I2C interface. ++ */ + for (i = 0; i < num; i++) { + if (msgs[i].addr != SCDC_I2C_SLAVE_ADDRESS) { + dev_err(mhdp->dev, "ADDR=%0x is not supported\n", msgs[i].addr); @@ -4757,33 +4933,6 @@ index 0000000000000..f7cafc153a58e + return MODE_OK; +} + -+static enum drm_mode_status -+cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ /* We don't support double-clocked and Interlaced modes */ -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK || -+ mode->flags & DRM_MODE_FLAG_INTERLACE) -+ return MODE_BAD; -+ -+ if (mode->hdisplay > 3840) -+ return MODE_BAD_HVALUE; -+ -+ if (mode->vdisplay > 2160) -+ return MODE_BAD_VVALUE; -+ -+ return MODE_OK; -+} -+ -+static enum drm_connector_status -+cdns_hdmi_bridge_detect(struct drm_bridge *bridge) -+{ -+ struct cdns_mhdp8501_device *mhdp = bridge->driver_private; -+ -+ return cdns_mhdp8501_detect(mhdp); -+} -+ +static const struct drm_edid +*cdns_hdmi_bridge_edid_read(struct drm_bridge *bridge, + struct drm_connector *connector) @@ -4925,9 +5074,9 @@ index 0000000000000..f7cafc153a58e + +const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = { + .attach = cdns_hdmi_bridge_attach, -+ .detect = cdns_hdmi_bridge_detect, ++ .detect = cdns_mhdp8501_detect, + .edid_read = cdns_hdmi_bridge_edid_read, -+ .mode_valid = cdns_hdmi_bridge_mode_valid, ++ .mode_valid = cdns_mhdp8501_mode_valid, + .atomic_enable = cdns_hdmi_bridge_atomic_enable, + .atomic_disable = cdns_hdmi_bridge_atomic_disable, + .atomic_check = cdns_hdmi_bridge_atomic_check, @@ -4939,15 +5088,15 @@ index 0000000000000..f7cafc153a58e + .hdmi_tmds_char_rate_valid = cdns_hdmi_tmds_char_rate_valid, +}; -From patchwork Tue Nov 26 14:11:50 2024 +From patchwork Tue Dec 17 06:51:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,5/8] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY +Subject: [v20,6/9] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY From: Sandor Yu -X-Patchwork-Id: 626193 +X-Patchwork-Id: 629293 Message-Id: - <54ee86767e5b6c7320b9b2053e404e615c290287.1732627815.git.Sandor.yu@nxp.com> + <1f01892a4e462d451a21ddcb4b114283d998cd1b.1734340233.git.Sandor.yu@nxp.com> To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -4960,14 +5109,14 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org, Rob Herring -Date: Tue, 26 Nov 2024 22:11:50 +0800 +Date: Tue, 17 Dec 2024 14:51:48 +0800 Add bindings for Freescale iMX8MQ DP and HDMI PHY. Signed-off-by: Sandor Yu Reviewed-by: Rob Herring --- -v9->v18: +v9->v20: *No change. .../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 51 +++++++++++++++++++ @@ -5032,16 +5181,16 @@ index 0000000000000..c17a645e71bad + clock-names = "ref", "apb"; + }; -From patchwork Tue Nov 26 14:11:51 2024 +From patchwork Tue Dec 17 06:51:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for +Subject: [v20,7/9] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ From: Sandor Yu -X-Patchwork-Id: 626194 +X-Patchwork-Id: 629294 Message-Id: - <4ef8252825d7a962b440519fb17fdcd5dd817672.1732627815.git.Sandor.yu@nxp.com> + To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -5053,7 +5202,7 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:51 +0800 +Date: Tue, 17 Dec 2024 14:51:49 +0800 Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ. @@ -5064,6 +5213,12 @@ DisplayPort or HDMI PHY mode is configured in the driver. Signed-off-by: Sandor Yu Signed-off-by: Alexander Stein --- +v19->v20: +- implify DP configuration handling by directly copying + the configuration options to the driver's internal structure. +- return the error code directly instead of logging an error message in `hdptx_clk_enable` +- Remove redundant ref_clk_rate check + v18->v19: - Simplify the PLL tables by removing unused and constant data - Remove PHY power management, controller driver will handle them. @@ -5077,12 +5232,12 @@ v17->v18: drivers/phy/freescale/Kconfig | 10 + drivers/phy/freescale/Makefile | 1 + - drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1237 ++++++++++++++++++ - 3 files changed, 1248 insertions(+) + drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1231 ++++++++++++++++++ + 3 files changed, 1242 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig -index dcd9acff6d01a..bbd17e9556cc3 100644 +index dcd9acff6d01a..2b1210367b31c 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE @@ -5093,8 +5248,8 @@ index dcd9acff6d01a..bbd17e9556cc3 100644 + tristate "Freescale i.MX8MQ DP/HDMI PHY support" + depends on OF && HAS_IOMEM + depends on COMMON_CLK -+ depends on CDNS_MHDP_HELPER + select GENERIC_PHY ++ select CDNS_MHDP_HELPER + help + Enable this to support the Cadence HDPTX DP/HDMI PHY driver + on i.MX8MQ SOC. @@ -5114,23 +5269,23 @@ index 658eac7d0a622..a946b87905498 100644 obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c new file mode 100644 -index 0000000000000..e99487622d43c +index 0000000000000..230b7148639b2 --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c -@@ -0,0 +1,1237 @@ +@@ -0,0 +1,1231 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence DP/HDMI PHY driver + * + * Copyright (C) 2022-2024 NXP Semiconductor, Inc. + */ -+#include +#include +#include +#include +#include +#include +#include ++#include + +#define ADDR_PHY_AFE 0x80000 + @@ -5769,22 +5924,18 @@ index 0000000000000..e99487622d43c +static int hdptx_dp_configure(struct phy *phy, + union phy_configure_opts *opts) +{ ++ const struct phy_configure_opts_dp *dp_opts = &opts->dp; + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy); + -+ cdns_phy->dp.link_rate = opts->dp.link_rate; -+ cdns_phy->dp.lanes = opts->dp.lanes; -+ -+ if (cdns_phy->dp.link_rate > MAX_LINK_RATE) { -+ dev_err(cdns_phy->dev, "Link Rate(%d) Not supported\n", cdns_phy->dp.link_rate); ++ if (opts->dp.link_rate > MAX_LINK_RATE) { ++ dev_err(cdns_phy->dev, "Link Rate(%d) Not supported\n", opts->dp.link_rate); + return false; + } + -+ if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) { -+ hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy); -+ hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy); -+ } else { -+ dev_err(cdns_phy->dev, "Not support ref clock rate\n"); -+ } ++ memcpy(&cdns_phy->dp, dp_opts, sizeof(*dp_opts)); ++ ++ hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy); ++ hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy); + + return 0; +} @@ -6325,10 +6476,8 @@ index 0000000000000..e99487622d43c + cdns_phy->base.regs = cdns_phy->regs; + + ret = hdptx_clk_enable(cdns_phy); -+ if (ret) { -+ dev_err(dev, "Init clk fail\n"); ++ if (ret) + return -EINVAL; -+ } + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) @@ -6356,15 +6505,15 @@ index 0000000000000..e99487622d43c +MODULE_DESCRIPTION("Cadence HDP-TX DP/HDMI PHY driver"); +MODULE_LICENSE("GPL"); -From patchwork Tue Nov 26 14:11:52 2024 +From patchwork Tue Dec 17 06:51:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,7/8] arm64: dts: imx8mq: Add DCSS + HDMI/DP display pipeline +Subject: [v20,8/9] arm64: dts: imx8mq: Add DCSS + HDMI/DP display pipeline From: Sandor Yu -X-Patchwork-Id: 626195 +X-Patchwork-Id: 629295 Message-Id: - + To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -6376,7 +6525,7 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:52 +0800 +Date: Tue, 17 Dec 2024 14:51:50 +0800 From: Alexander Stein @@ -6385,7 +6534,7 @@ by the connector type connected to mhdp port@1 endpoint. Signed-off-by: Alexander Stein --- -v17->v19: +v17->v20: *No change arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++ @@ -6471,15 +6620,15 @@ index d51de8d899b2b..df8ba1d5391ae 100644 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; -From patchwork Tue Nov 26 14:11:53 2024 +From patchwork Tue Dec 17 06:51:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit -Subject: [v19,8/8] arm64: dts: imx8mq: tqma8mq-mba8mx: Enable HDMI support +Subject: [v20,9/9] arm64: dts: imx8mq: tqma8mq-mba8mx: Enable HDMI support From: Sandor Yu -X-Patchwork-Id: 626196 +X-Patchwork-Id: 629296 Message-Id: - + To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, @@ -6491,7 +6640,7 @@ To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org -Date: Tue, 26 Nov 2024 22:11:53 +0800 +Date: Tue, 17 Dec 2024 14:51:51 +0800 From: Alexander Stein @@ -6500,6 +6649,9 @@ for HDMI output. Signed-off-by: Alexander Stein --- +v19->v20: + *No change + v18->v19: - Move property data-lanes to endpoint of port@1