diff --git a/projects/RPi/patches/linux/linux-01-RPi_support.patch b/projects/RPi/patches/linux/linux-01-RPi_support.patch index 60aef11b21..30518b9487 100644 --- a/projects/RPi/patches/linux/linux-01-RPi_support.patch +++ b/projects/RPi/patches/linux/linux-01-RPi_support.patch @@ -1,7 +1,7 @@ -From b3ee605a6d9a542c72b20eea9c34ab340e8a7083 Mon Sep 17 00:00:00 2001 +From 7845b06e18af196528ad650eccd152e7989bc69c Mon Sep 17 00:00:00 2001 From: Steve Glendinning Date: Thu, 19 Feb 2015 18:47:12 +0000 -Subject: [PATCH 01/55] smsx95xx: fix crimes against truesize +Subject: [PATCH 01/54] smsx95xx: fix crimes against truesize smsc95xx is adjusting truesize when it shouldn't, and following a recent patch from Eric this is now triggering warnings. @@ -39,10 +39,10 @@ index 66b3ab9..b544181 2.5.0 -From 16af2003a85fc6f2be1702b285eadae72e272761 Mon Sep 17 00:00:00 2001 +From 1c4ee85b4d9361be8b58687db4acdb43e7a79c14 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 17 Apr 2015 16:58:45 +0100 -Subject: [PATCH 02/55] smsc95xx: Disable turbo mode by default +Subject: [PATCH 02/54] smsc95xx: Disable turbo mode by default --- drivers/net/usb/smsc95xx.c | 2 +- @@ -65,10 +65,10 @@ index b544181..9c0da18 100755 2.5.0 -From 1080f40d03f10107b0baa0f8e938b36d8f2905a4 Mon Sep 17 00:00:00 2001 +From 38a1c0f17082b195b17ee390270377e661d2243b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Jun 2014 13:42:01 +0100 -Subject: [PATCH 03/55] vmstat: Workaround for issue where dirty page count +Subject: [PATCH 03/54] vmstat: Workaround for issue where dirty page count goes negative See: @@ -98,10 +98,10 @@ index 5dbc8b0..3a18061 100644 2.5.0 -From 09b89dd4e1296033fc8d44ddea510c4a9ca3e6d3 Mon Sep 17 00:00:00 2001 +From 7d76a16073ba70458e82edb4db8254a7a3dced6b Mon Sep 17 00:00:00 2001 From: Robert Tiemann Date: Mon, 20 Jul 2015 11:01:25 +0200 -Subject: [PATCH 04/55] BCM2835_DT: Fix I2S register map +Subject: [PATCH 04/54] BCM2835_DT: Fix I2S register map --- Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 4 ++-- @@ -158,10 +158,47 @@ index aef64de..864a3ef 100644 2.5.0 -From 8dfe39f884ab674e140dc6fc6640aaf055f1756a Mon Sep 17 00:00:00 2001 +From 688a5f2ada4fbd16547b574a17e6d359ab2364d0 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 4 Dec 2015 17:41:50 +0000 +Subject: [PATCH 05/54] irq-bcm2836: Prevent spurious interrupts, and trap them + early + +The old arch-specific IRQ macros included a dsb to ensure the +write to clear the mailbox interrupt completed before returning +from the interrupt. The BCM2836 irqchip driver needs the same +precaution to avoid spurious interrupts. + +Spurious interrupts are still possible for other reasons, +though, so trap them early. +--- + drivers/irqchip/irq-bcm2836.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c +index f687082..4cd8ebe 100644 +--- a/drivers/irqchip/irq-bcm2836.c ++++ b/drivers/irqchip/irq-bcm2836.c +@@ -170,9 +170,10 @@ __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs) + u32 ipi = ffs(mbox_val) - 1; + + writel(1 << ipi, mailbox0); ++ dsb(); + handle_IPI(ipi, regs); + #endif +- } else { ++ } else if (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); +-- +2.5.0 + + +From 6edc4f10cd957d1b3cb705fe06003b965f24fd71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 12 Jun 2015 19:01:05 +0200 -Subject: [PATCH 05/55] irqchip: bcm2835: Add FIQ support +Subject: [PATCH 06/54] irqchip: bcm2835: Add FIQ support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -293,10 +330,112 @@ index bf9cc5f..3f601f9 100644 2.5.0 -From 3df5df89b2338b81aedff704bef5f2aaa1d3bcde Mon Sep 17 00:00:00 2001 +From e24db33d028844ac535e9e8d72a0c77e6dc7cb95 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 23 Oct 2015 16:26:55 +0200 +Subject: [PATCH 07/54] irqchip: irq-bcm2835: Add 2836 FIQ support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + drivers/irqchip/irq-bcm2835.c | 42 ++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 40 insertions(+), 2 deletions(-) + +diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c +index 3f601f9..20deb28 100644 +--- a/drivers/irqchip/irq-bcm2835.c ++++ b/drivers/irqchip/irq-bcm2835.c +@@ -50,6 +50,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -70,6 +72,9 @@ + #define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \ + | SHORTCUT1_MASK | SHORTCUT2_MASK) + ++#undef ARM_LOCAL_GPU_INT_ROUTING ++#define ARM_LOCAL_GPU_INT_ROUTING 0x0c ++ + #define REG_FIQ_CONTROL 0x0c + #define REG_FIQ_ENABLE 0x80 + #define REG_FIQ_DISABLE 0 +@@ -95,6 +100,7 @@ struct armctrl_ic { + void __iomem *enable[NR_BANKS]; + void __iomem *disable[NR_BANKS]; + struct irq_domain *domain; ++ struct regmap *local_regmap; + }; + + static struct armctrl_ic intc __read_mostly; +@@ -128,12 +134,35 @@ static void armctrl_mask_irq(struct irq_data *d) + + static void armctrl_unmask_irq(struct irq_data *d) + { +- if (d->hwirq >= NUMBER_IRQS) ++ if (d->hwirq >= NUMBER_IRQS) { ++ if (num_online_cpus() > 1) { ++ unsigned int data; ++ int ret; ++ ++ if (!intc.local_regmap) { ++ pr_err("FIQ is disabled due to missing regmap\n"); ++ return; ++ } ++ ++ ret = regmap_read(intc.local_regmap, ++ ARM_LOCAL_GPU_INT_ROUTING, &data); ++ if (ret) { ++ pr_err("Failed to read int routing %d\n", ret); ++ return; ++ } ++ ++ data &= ~0xc; ++ data |= (1 << 2); ++ regmap_write(intc.local_regmap, ++ ARM_LOCAL_GPU_INT_ROUTING, data); ++ } ++ + writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), + intc.base + REG_FIQ_CONTROL); +- else ++ } else { + writel_relaxed(HWIRQ_BIT(d->hwirq), + intc.enable[HWIRQ_BANK(d->hwirq)]); ++ } + } + + static struct irq_chip armctrl_chip = { +@@ -211,6 +240,15 @@ static int __init armctrl_of_init(struct device_node *node, + set_handle_irq(bcm2835_handle_irq); + } + ++ if (is_2836) { ++ intc.local_regmap = ++ syscon_regmap_lookup_by_compatible("brcm,bcm2836-arm-local"); ++ if (IS_ERR(intc.local_regmap)) { ++ pr_err("Failed to get local register map. FIQ is disabled for cpus > 1\n"); ++ intc.local_regmap = NULL; ++ } ++ } ++ + /* Make a duplicate irq range which is used to enable FIQ */ + for (b = 0; b < NR_BANKS; b++) { + for (i = 0; i < bank_irqs[b]; i++) { +-- +2.5.0 + + +From a628f89696a423d8be5e4f6afacd1b2164dc72c0 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 30 Jun 2015 14:12:42 +0100 -Subject: [PATCH 06/55] serial: 8250: Don't crash when nr_uarts is 0 +Subject: [PATCH 08/54] serial: 8250: Don't crash when nr_uarts is 0 --- drivers/tty/serial/8250/8250_core.c | 2 ++ @@ -319,10 +458,10 @@ index 3912646..b51a59c 100644 2.5.0 -From 36a124709393f4e6183a4767d296786f8fe5b431 Mon Sep 17 00:00:00 2001 +From 05998ad69409fe1312ea7070e5ad3394b1a27712 Mon Sep 17 00:00:00 2001 From: notro Date: Thu, 10 Jul 2014 13:59:47 +0200 -Subject: [PATCH 07/55] pinctrl-bcm2835: Set base to 0 give expected gpio +Subject: [PATCH 09/54] pinctrl-bcm2835: Set base to 0 give expected gpio numbering Signed-off-by: Noralf Tronnes @@ -331,10 +470,10 @@ Signed-off-by: Noralf Tronnes 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index a1ea565..31c1314 100644 +index 2e6ca69..62cc363 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -372,7 +372,7 @@ static struct gpio_chip bcm2835_gpio_chip = { +@@ -373,7 +373,7 @@ static struct gpio_chip bcm2835_gpio_chip = { .get = bcm2835_gpio_get, .set = bcm2835_gpio_set, .to_irq = bcm2835_gpio_to_irq, @@ -347,44 +486,10 @@ index a1ea565..31c1314 100644 2.5.0 -From 2eeb5f8c1d69737be5bd8b3bbd0c142d15222674 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Wed, 4 Feb 2015 10:02:24 +0000 -Subject: [PATCH 08/55] pinctrl-bcm2835: bcm2835_gpio_direction_output must set - the value - ---- - drivers/pinctrl/bcm/pinctrl-bcm2835.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index 31c1314..4a7f6315 100644 ---- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c -+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -345,7 +345,14 @@ static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) - static int bcm2835_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) - { -- return pinctrl_gpio_direction_output(chip->base + offset); -+ struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); -+ int ret; -+ -+ ret = pinctrl_gpio_direction_output(chip->base + offset); -+ if (ret >= 0) -+ bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); -+ -+ return ret; - } - - static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) --- -2.5.0 - - -From 3e14a4401126124b4ef5076808c8db4f3105dc79 Mon Sep 17 00:00:00 2001 +From 511ab7e5940ce9cc535fed78408df6ccea648a5a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 24 Feb 2015 13:40:50 +0000 -Subject: [PATCH 09/55] pinctrl-bcm2835: Fix interrupt handling for GPIOs 28-31 +Subject: [PATCH 10/54] pinctrl-bcm2835: Fix interrupt handling for GPIOs 28-31 and 46-53 Contrary to the documentation, the BCM2835 GPIO controller actually has @@ -405,7 +510,7 @@ the pins are often used for I2S instead. 1 file changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index 4a7f6315..10625ce 100644 +index 62cc363..ab345f4 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -47,6 +47,7 @@ @@ -441,7 +546,7 @@ index 4a7f6315..10625ce 100644 spinlock_t irq_lock[BCM2835_NUM_BANKS]; }; -@@ -384,17 +385,16 @@ static struct gpio_chip bcm2835_gpio_chip = { +@@ -378,17 +379,16 @@ static struct gpio_chip bcm2835_gpio_chip = { .can_sleep = false, }; @@ -462,7 +567,7 @@ index 4a7f6315..10625ce 100644 events &= pc->enabled_irq_map[bank]; for_each_set_bit(offset, &events, 32) { gpio = (32 * bank) + offset; -@@ -402,7 +402,30 @@ static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) +@@ -396,7 +396,30 @@ static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); } @@ -494,7 +599,7 @@ index 4a7f6315..10625ce 100644 } static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, -@@ -991,8 +1014,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) +@@ -985,8 +1008,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < BCM2835_NUM_BANKS; i++) { unsigned long events; unsigned offset; @@ -503,7 +608,7 @@ index 4a7f6315..10625ce 100644 /* clear event detection flags */ bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); -@@ -1007,10 +1028,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) +@@ -1001,10 +1022,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) for_each_set_bit(offset, &events, 32) bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); @@ -521,7 +626,7 @@ index 4a7f6315..10625ce 100644 len = strlen(dev_name(pc->dev)) + 16; name = devm_kzalloc(pc->dev, len, GFP_KERNEL); -@@ -1068,6 +1094,7 @@ static struct platform_driver bcm2835_pinctrl_driver = { +@@ -1062,6 +1088,7 @@ static struct platform_driver bcm2835_pinctrl_driver = { .remove = bcm2835_pinctrl_remove, .driver = { .name = MODULE_NAME, @@ -533,10 +638,10 @@ index 4a7f6315..10625ce 100644 2.5.0 -From ca4182f2ae329463426e9de88bbc0a3613f58f40 Mon Sep 17 00:00:00 2001 +From b02654723367da6ef4be37fc63aadde1d273337a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 26 Feb 2015 09:58:22 +0000 -Subject: [PATCH 10/55] pinctrl-bcm2835: Only request the interrupts listed in +Subject: [PATCH 11/54] pinctrl-bcm2835: Only request the interrupts listed in the DTB Although the GPIO controller can generate three interrupts (four counting @@ -550,10 +655,10 @@ interface, is unlikely to be a problem. 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index 10625ce..97e125a8 100644 +index ab345f4..640e3b0 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -1035,6 +1035,8 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) +@@ -1029,6 +1029,8 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) int len; char *name; pc->irq[i] = irq_of_parse_and_map(np, i); @@ -566,10 +671,10 @@ index 10625ce..97e125a8 100644 2.5.0 -From 1389162c26fd006dc89b63fa74cf07dc16e771d6 Mon Sep 17 00:00:00 2001 +From c28b4b938880483817ec763cc8cea8b1b3fa7713 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 24 Jun 2015 14:10:44 +0100 -Subject: [PATCH 11/55] spi-bcm2835: Support pin groups other than 7-11 +Subject: [PATCH 12/54] spi-bcm2835: Support pin groups other than 7-11 The spi-bcm2835 driver automatically uses GPIO chip-selects due to some unreliability of the native ones. In doing so it chooses the @@ -653,10 +758,10 @@ index cf04960..a2b1f45 100644 2.5.0 -From b70072e95258dad4dbdf663681b5b74fa186b8a7 Mon Sep 17 00:00:00 2001 +From 1cb2f8fda15ef921c9d1f51e010ac0073bd54a57 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Wed, 3 Jun 2015 12:26:13 +0200 -Subject: [PATCH 12/55] ARM: bcm2835: Set Serial number and Revision +Subject: [PATCH 13/54] ARM: bcm2835: Set Serial number and Revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -717,10 +822,10 @@ index 0f7b9ea..1e6f1cf 100644 2.5.0 -From 58a50cd6c0dd037b3cb0eec22bd1096af96d11f2 Mon Sep 17 00:00:00 2001 +From 43a75f20eb793a2c528280faab8248b226fe38de Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 16:44:05 +0200 -Subject: [PATCH 13/55] bcm2835-i2s: get base address for DMA from devicetree +Subject: [PATCH 14/54] bcm2835-i2s: get base address for DMA from devicetree Code copied from spi-bcm2835. Get physical address from devicetree instead of using hardcoded constant. @@ -788,10 +893,10 @@ index 8c435be..0bc4f47 100644 2.5.0 -From 64bdc1411fa7ae16f36d54a97e4777f8c04c0b26 Mon Sep 17 00:00:00 2001 +From e68b70e6087fd6fc8466eeac8db67b3f49813058 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:21:16 +0200 -Subject: [PATCH 14/55] bcm2835-i2s: add 24bit support, update bclk_ratio to +Subject: [PATCH 15/54] bcm2835-i2s: add 24bit support, update bclk_ratio to more correct values Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -873,10 +978,10 @@ index 0bc4f47..cf60390 100644 2.5.0 -From caf2b024219e3326d432dcac9f95a8c1aa245a60 Mon Sep 17 00:00:00 2001 +From 18ecb409ca4b62265dc8638c4feddc74b169e757 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:25:51 +0200 -Subject: [PATCH 15/55] bcm2835-i2s: setup clock only if CPU is clock master +Subject: [PATCH 16/54] bcm2835-i2s: setup clock only if CPU is clock master Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -934,10 +1039,10 @@ index cf60390..4ac4e92 100644 2.5.0 -From 928181e301f07af78d32d50f3c3c88d32208b423 Mon Sep 17 00:00:00 2001 +From 34be3cc516c8e1bc9543bb1b1472b916cde0e3d4 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:49:51 +0200 -Subject: [PATCH 16/55] bcm2835-i2s: Eliminate debugfs directory error +Subject: [PATCH 17/54] bcm2835-i2s: Eliminate debugfs directory error Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -976,10 +1081,10 @@ index 4ac4e92..aab3df9 100644 2.5.0 -From afa82a1e4ba2da951a12855af00f3fbd7215fe3e Mon Sep 17 00:00:00 2001 +From 3b910b1bea6daf50ce4a22298d4512178d109fe7 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:35:20 +0200 -Subject: [PATCH 17/55] bcm2835-i2s: Register PCM device +Subject: [PATCH 18/54] bcm2835-i2s: Register PCM device Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -1045,10 +1150,10 @@ index aab3df9..0e5c787 100644 2.5.0 -From aa5cae200e02a2776d8b82df5cd60f0b1ee738be Mon Sep 17 00:00:00 2001 +From cb2f46fb84024303f11a9da1f949e0092222b537 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:55:21 +0200 -Subject: [PATCH 18/55] bcm2835-i2s: Enable MMAP support via a DT property +Subject: [PATCH 19/54] bcm2835-i2s: Enable MMAP support via a DT property Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -1095,218 +1200,10 @@ index 0e5c787..04c1d13 100644 2.5.0 -From 99466dd3a723108c9d475a6ca8bd6cf30a4a722b Mon Sep 17 00:00:00 2001 -From: Peter Ujfalusi -Date: Mon, 16 Nov 2015 12:38:46 +0000 -Subject: [PATCH 19/55] [PATCH] dmaengine: bcm2835-dma: Convert to use DMA pool - -f93178291712 dmaengine: bcm2835-dma: Fix memory leak when stopping a - running transfer - -Fixed the memleak, but introduced another issue: the terminate_all callback -might be called with interrupts disabled and the dma_free_coherent() is -not allowed to be called when IRQs are disabled. -Convert the driver to use dma_pool_* for managing the list of control -blocks for the transfer. - -Fixes: f93178291712 ("dmaengine: bcm2835-dma: Fix memory leak when stopping a running transfer") -Signed-off-by: Peter Ujfalusi ---- - drivers/dma/bcm2835-dma.c | 78 ++++++++++++++++++++++++++++++++--------------- - 1 file changed, 54 insertions(+), 24 deletions(-) - -diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index c92d6a7..996c4b0 100644 ---- a/drivers/dma/bcm2835-dma.c -+++ b/drivers/dma/bcm2835-dma.c -@@ -31,6 +31,7 @@ - */ - #include - #include -+#include - #include - #include - #include -@@ -62,6 +63,11 @@ struct bcm2835_dma_cb { - uint32_t pad[2]; - }; - -+struct bcm2835_cb_entry { -+ struct bcm2835_dma_cb *cb; -+ dma_addr_t paddr; -+}; -+ - struct bcm2835_chan { - struct virt_dma_chan vc; - struct list_head node; -@@ -72,18 +78,18 @@ struct bcm2835_chan { - - int ch; - struct bcm2835_desc *desc; -+ struct dma_pool *cb_pool; - - void __iomem *chan_base; - int irq_number; - }; - - struct bcm2835_desc { -+ struct bcm2835_chan *c; - struct virt_dma_desc vd; - enum dma_transfer_direction dir; - -- unsigned int control_block_size; -- struct bcm2835_dma_cb *control_block_base; -- dma_addr_t control_block_base_phys; -+ struct bcm2835_cb_entry *cb_list; - - unsigned int frames; - size_t size; -@@ -143,10 +149,13 @@ static inline struct bcm2835_desc *to_bcm2835_dma_desc( - static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) - { - struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); -- dma_free_coherent(desc->vd.tx.chan->device->dev, -- desc->control_block_size, -- desc->control_block_base, -- desc->control_block_base_phys); -+ int i; -+ -+ for (i = 0; i < desc->frames; i++) -+ dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb, -+ desc->cb_list[i].paddr); -+ -+ kfree(desc->cb_list); - kfree(desc); - } - -@@ -199,7 +208,7 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan *c) - - c->desc = d = to_bcm2835_dma_desc(&vd->tx); - -- writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR); -+ writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); - writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); - } - -@@ -232,9 +241,16 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) - static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) - { - struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ struct device *dev = c->vc.chan.device->dev; -+ -+ dev_dbg(dev, "Allocating DMA channel %d\n", c->ch); - -- dev_dbg(c->vc.chan.device->dev, -- "Allocating DMA channel %d\n", c->ch); -+ c->cb_pool = dma_pool_create(dev_name(dev), dev, -+ sizeof(struct bcm2835_dma_cb), 0, 0); -+ if (!c->cb_pool) { -+ dev_err(dev, "unable to allocate descriptor pool\n"); -+ return -ENOMEM; -+ } - - return request_irq(c->irq_number, - bcm2835_dma_callback, 0, "DMA IRQ", c); -@@ -246,6 +262,7 @@ static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) - - vchan_free_chan_resources(&c->vc); - free_irq(c->irq_number, c); -+ dma_pool_destroy(c->cb_pool); - - dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); - } -@@ -261,8 +278,7 @@ static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) - size_t size; - - for (size = i = 0; i < d->frames; i++) { -- struct bcm2835_dma_cb *control_block = -- &d->control_block_base[i]; -+ struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; - size_t this_size = control_block->length; - dma_addr_t dma; - -@@ -343,6 +359,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( - dma_addr_t dev_addr; - unsigned int es, sync_type; - unsigned int frame; -+ int i; - - /* Grab configuration */ - if (!is_slave_direction(direction)) { -@@ -374,27 +391,31 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( - if (!d) - return NULL; - -+ d->c = c; - d->dir = direction; - d->frames = buf_len / period_len; - -- /* Allocate memory for control blocks */ -- d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); -- d->control_block_base = dma_zalloc_coherent(chan->device->dev, -- d->control_block_size, &d->control_block_base_phys, -- GFP_NOWAIT); -- -- if (!d->control_block_base) { -+ d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL); -+ if (!d->cb_list) { - kfree(d); - return NULL; - } -+ /* Allocate memory for control blocks */ -+ for (i = 0; i < d->frames; i++) { -+ struct bcm2835_cb_entry *cb_entry = &d->cb_list[i]; -+ -+ cb_entry->cb = dma_pool_zalloc(c->cb_pool, GFP_ATOMIC, -+ &cb_entry->paddr); -+ if (!cb_entry->cb) -+ goto error_cb; -+ } - - /* - * Iterate over all frames, create a control block - * for each frame and link them together. - */ - for (frame = 0; frame < d->frames; frame++) { -- struct bcm2835_dma_cb *control_block = -- &d->control_block_base[frame]; -+ struct bcm2835_dma_cb *control_block = d->cb_list[frame].cb; - - /* Setup adresses */ - if (d->dir == DMA_DEV_TO_MEM) { -@@ -428,12 +449,21 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( - * This DMA engine driver currently only supports cyclic DMA. - * Therefore, wrap around at number of frames. - */ -- control_block->next = d->control_block_base_phys + -- sizeof(struct bcm2835_dma_cb) -- * ((frame + 1) % d->frames); -+ control_block->next = d->cb_list[((frame + 1) % d->frames)].paddr; - } - - return vchan_tx_prep(&c->vc, &d->vd, flags); -+error_cb: -+ i--; -+ for (; i >= 0; i--) { -+ struct bcm2835_cb_entry *cb_entry = &d->cb_list[i]; -+ -+ dma_pool_free(c->cb_pool, cb_entry->cb, cb_entry->paddr); -+ } -+ -+ kfree(d->cb_list); -+ kfree(d); -+ return NULL; - } - - static int bcm2835_dma_slave_config(struct dma_chan *chan, --- -2.5.0 - - -From c776a0f35105e2f6416db20f49bd6eef9897b7f2 Mon Sep 17 00:00:00 2001 +From 5d8da2ced7537ced468f4ec0da0392d31ec59402 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Thu, 9 Apr 2015 12:34:11 +0200 -Subject: [PATCH 20/55] dmaengine: bcm2835: Add slave dma support +Subject: [PATCH 20/54] dmaengine: bcm2835: Add slave dma support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -1629,10 +1526,10 @@ index 996c4b0..b278c66 100644 2.5.0 -From 0e9c1fce5ce00aa74687238e866aa39693087e68 Mon Sep 17 00:00:00 2001 +From 47c823519828f01517803ca5507ce9f942ffa4a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 3 Oct 2015 15:58:59 +0200 -Subject: [PATCH 21/55] dmaengine: bcm2835: set residue_granularity field +Subject: [PATCH 21/54] dmaengine: bcm2835: set residue_granularity field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -1664,10 +1561,10 @@ index b278c66..696fb30 100644 2.5.0 -From 7835fbd12618a35dd44ff0bb473242a624765db7 Mon Sep 17 00:00:00 2001 +From 8ed5d9cb36862e28d36b17c509321c7496c499b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 3 Oct 2015 22:22:55 +0200 -Subject: [PATCH 22/55] dmaengine: bcm2835: Load driver early and support +Subject: [PATCH 22/54] dmaengine: bcm2835: Load driver early and support legacy API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -1770,72 +1667,10 @@ index 696fb30..5db0a95 100644 2.5.0 -From f02f5b8d103f39629e5e27c11c8616614e1bba7f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= -Date: Sat, 3 Oct 2015 22:44:36 +0200 -Subject: [PATCH 23/55] dmaengine: bcm2835: Add debug option for setting wait - states -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -[by popcornmix, taken from bcm2708-dmaengine] -Signed-off-by: Noralf Trønnes ---- - drivers/dma/bcm2835-dma.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - -diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 5db0a95..8412433 100644 ---- a/drivers/dma/bcm2835-dma.c -+++ b/drivers/dma/bcm2835-dma.c -@@ -46,6 +46,9 @@ - - #include "virt-dma.h" - -+static unsigned dma_debug; -+module_param(dma_debug, uint, 0644); -+ - struct bcm2835_dmadev { - struct dma_device ddev; - spinlock_t lock; -@@ -571,6 +574,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, - unsigned int len = sg_dma_len(sgent); - - for (j = 0; j < len; j += max_size) { -+ u32 waits; - struct bcm2835_dma_cb *control_block = - &d->control_block_base[i + split_cnt]; - -@@ -590,8 +594,10 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, - } - - /* Common part */ -- control_block->info |= -- BCM2835_DMA_WAITS(BCM2835_DMA_WAIT_CYCLES); -+ waits = BCM2835_DMA_WAIT_CYCLES; -+ if ((dma_debug >> 0) & 0x1f) -+ waits = (dma_debug >> 0) & 0x1f; -+ control_block->info |= BCM2835_DMA_WAITS(waits); - control_block->info |= BCM2835_DMA_WAIT_RESP; - - /* Enable */ -@@ -856,6 +862,7 @@ static int bcm2835_dma_probe(struct platform_device *pdev) - } - - dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n"); -+ dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug); - - return 0; - --- -2.5.0 - - -From b12e830e429106a3457cf285c7071dfb51096e87 Mon Sep 17 00:00:00 2001 +From cc8e848852566125466b1c7f8969193b3bd09952 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sat, 10 Oct 2015 12:29:18 +0200 -Subject: [PATCH 24/55] bcm2835-dma: Fix dreq not set for slave transfers +Subject: [PATCH 23/54] bcm2835-dma: Fix dreq not set for slave transfers Set dreq to slave_id if it is not set like in bcm2708-dmaengine. --- @@ -1843,10 +1678,10 @@ Set dreq to slave_id if it is not set like in bcm2708-dmaengine. 1 file changed, 2 insertions(+) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 8412433..93e714c 100644 +index 5db0a95..fe1fd60 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c -@@ -663,6 +663,8 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan, +@@ -657,6 +657,8 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan, } c->cfg = *cfg; @@ -1859,10 +1694,10 @@ index 8412433..93e714c 100644 2.5.0 -From b59b3cb4d1cbe396d439f76abfcfbee786fcce97 Mon Sep 17 00:00:00 2001 +From b4b8964bdad3f33abb3b688832b326372c4e1d41 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 12:28:30 +0200 -Subject: [PATCH 25/55] bcm2835-dma: Limit cyclic transfers on lite channels to +Subject: [PATCH 24/54] bcm2835-dma: Limit cyclic transfers on lite channels to 32k Transfers larger than 32k cause repeated clicking with I2S soundcards. @@ -1873,10 +1708,10 @@ did as an intermediate fix. 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 93e714c..58a96a6 100644 +index fe1fd60..0adc347 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c -@@ -147,6 +147,12 @@ struct bcm2835_desc { +@@ -144,6 +144,12 @@ struct bcm2835_desc { */ #define MAX_LITE_TRANSFER (SZ_64K - 4) @@ -1889,7 +1724,7 @@ index 93e714c..58a96a6 100644 static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) { return container_of(d, struct bcm2835_dmadev, ddev); -@@ -415,7 +421,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -412,7 +418,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( d->c = c; d->dir = direction; if (c->ch >= 8) /* LITE channel */ @@ -1902,10 +1737,10 @@ index 93e714c..58a96a6 100644 2.5.0 -From 72edadcf811bb74122d571ec30b34c77d2d7b340 Mon Sep 17 00:00:00 2001 +From 94acbda110b4bed72b2799550c86aa628abebf02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 15 Aug 2015 20:50:02 +0200 -Subject: [PATCH 26/55] bcm2835: Add support for uart1 +Subject: [PATCH 25/54] bcm2835: Add support for uart1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -1965,10 +1800,10 @@ index 1e6f1cf..ea36eec 100644 2.5.0 -From 3349bfdbc95e58489239a69c5812f8b8903a3dcb Mon Sep 17 00:00:00 2001 +From 1646baa74c32dc7efe9f1cdc9a38cf55b771cfdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 26 Jun 2015 14:21:20 +0200 -Subject: [PATCH 27/55] firmware: bcm2835: Add missing property tags +Subject: [PATCH 26/54] firmware: bcm2835: Add missing property tags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -2033,10 +1868,10 @@ index c07d74a..525816d 100644 2.5.0 -From 97d3ddd0feb169151fc34cef91b0e8b6c88621c4 Mon Sep 17 00:00:00 2001 +From 831c4f4aa0247bf72b21cd38787890fd50cbf766 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 12 May 2013 12:24:19 +0100 -Subject: [PATCH 28/55] Main bcm2708/bcm2709 linux port +Subject: [PATCH 27/54] Main bcm2708/bcm2709 linux port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -2044,49 +1879,44 @@ Content-Transfer-Encoding: 8bit Signed-off-by: popcornmix Signed-off-by: Noralf Trønnes --- - arch/arm/Kconfig | 46 ++ + arch/arm/Kconfig | 49 +++ arch/arm/Kconfig.debug | 8 + arch/arm/Makefile | 2 + arch/arm/kernel/head.S | 8 + arch/arm/kernel/process.c | 10 + - arch/arm/mach-bcm2708/Kconfig | 23 + + arch/arm/mach-bcm2708/Kconfig | 23 ++ arch/arm/mach-bcm2708/Makefile | 5 + arch/arm/mach-bcm2708/Makefile.boot | 3 + - arch/arm/mach-bcm2708/bcm2708.c | 231 ++++++++++ - arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 + + arch/arm/mach-bcm2708/bcm2708.c | 231 ++++++++++++ + arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 ++ arch/arm/mach-bcm2708/include/mach/io.h | 27 ++ arch/arm/mach-bcm2708/include/mach/memory.h | 57 +++ - arch/arm/mach-bcm2708/include/mach/platform.h | 112 +++++ + arch/arm/mach-bcm2708/include/mach/platform.h | 112 ++++++ arch/arm/mach-bcm2708/include/mach/system.h | 37 ++ - arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 ++++ - arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 + + arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++++ + arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 ++ arch/arm/mach-bcm2709/Kconfig | 16 + arch/arm/mach-bcm2709/Makefile | 5 + arch/arm/mach-bcm2709/Makefile.boot | 3 + - arch/arm/mach-bcm2709/armctrl.c | 361 +++++++++++++++ - arch/arm/mach-bcm2709/armctrl.h | 27 ++ - arch/arm/mach-bcm2709/bcm2709.c | 539 +++++++++++++++++++++++ - arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 +++++++++++++++++++++ - arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 + - arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 ++++++ - arch/arm/mach-bcm2709/include/mach/hardware.h | 28 ++ + arch/arm/mach-bcm2709/bcm2709.c | 380 ++++++++++++++++++++ + arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 ++ + arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 +++++++ arch/arm/mach-bcm2709/include/mach/io.h | 27 ++ - arch/arm/mach-bcm2709/include/mach/irqs.h | 225 ++++++++++ arch/arm/mach-bcm2709/include/mach/memory.h | 57 +++ - arch/arm/mach-bcm2709/include/mach/platform.h | 225 ++++++++++ - arch/arm/mach-bcm2709/include/mach/system.h | 38 ++ - arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 ++++ + arch/arm/mach-bcm2709/include/mach/platform.h | 188 ++++++++++ + arch/arm/mach-bcm2709/include/mach/system.h | 37 ++ + arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 +++++ arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 ++ - arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 + - arch/arm/mach-bcm2709/vc_mem.c | 431 ++++++++++++++++++ + arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 ++ + arch/arm/mach-bcm2709/vc_mem.c | 431 +++++++++++++++++++++++ arch/arm/mm/Kconfig | 2 +- arch/arm/mm/proc-v6.S | 15 +- arch/arm/mm/proc-v7.S | 1 + arch/arm/tools/mach-types | 2 + drivers/clocksource/Makefile | 2 +- - drivers/irqchip/Makefile | 1 + + drivers/irqchip/Makefile | 3 + include/linux/mmc/host.h | 1 + - 42 files changed, 3473 insertions(+), 5 deletions(-) + 37 files changed, 2147 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-bcm2708/Kconfig create mode 100644 arch/arm/mach-bcm2708/Makefile create mode 100644 arch/arm/mach-bcm2708/Makefile.boot @@ -2101,15 +1931,10 @@ Signed-off-by: Noralf Trønnes create mode 100644 arch/arm/mach-bcm2709/Kconfig create mode 100644 arch/arm/mach-bcm2709/Makefile create mode 100644 arch/arm/mach-bcm2709/Makefile.boot - create mode 100644 arch/arm/mach-bcm2709/armctrl.c - create mode 100644 arch/arm/mach-bcm2709/armctrl.h create mode 100644 arch/arm/mach-bcm2709/bcm2709.c - create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S - create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h @@ -2119,10 +1944,10 @@ Signed-off-by: Noralf Trønnes create mode 100644 arch/arm/mach-bcm2709/vc_mem.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 34e1569..3241611 100644 +index 34e1569..8f06ea8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -317,6 +317,49 @@ choice +@@ -317,6 +317,52 @@ choice default ARCH_VERSATILE if !MMU default ARCH_MULTIPLATFORM if MMU @@ -2160,6 +1985,9 @@ index 34e1569..3241611 100644 + select ARCH_HAS_CPUFREQ + select GENERIC_CLOCKEVENTS + select MACH_BCM2709 ++ select MULTI_IRQ_HANDLER ++ select SPARSE_IRQ ++ select MFD_SYSCON + select VC4 + select FIQ + select USE_OF @@ -2172,7 +2000,7 @@ index 34e1569..3241611 100644 config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" depends on MMU -@@ -808,6 +851,9 @@ config ARCH_VIRT +@@ -808,6 +854,9 @@ config ARCH_VIRT # Kconfigs may be included either alphabetically (according to the # plat- suffix) or along side the corresponding mach-* source. # @@ -2234,7 +2062,7 @@ index 04286fd..ed82628 100644 ENDPROC(__fixup_a_pv_table) diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c -index 7a7c4ce..7dd2e4c 100644 +index 4adfb46..69aad0e 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -91,6 +91,16 @@ void arch_cpu_idle_exit(void) @@ -2965,7 +2793,7 @@ index 0000000..643b4b9 +endmenu diff --git a/arch/arm/mach-bcm2709/Makefile b/arch/arm/mach-bcm2709/Makefile new file mode 100644 -index 0000000..11ad846 +index 0000000..26cd67d --- /dev/null +++ b/arch/arm/mach-bcm2709/Makefile @@ -0,0 +1,5 @@ @@ -2973,7 +2801,7 @@ index 0000000..11ad846 +# Makefile for the linux kernel. +# + -+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o ++obj-$(CONFIG_MACH_BCM2709) += bcm2709.o diff --git a/arch/arm/mach-bcm2709/Makefile.boot b/arch/arm/mach-bcm2709/Makefile.boot new file mode 100644 index 0000000..67039c3 @@ -2983,412 +2811,12 @@ index 0000000..67039c3 + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -new file mode 100644 -index 0000000..813008a ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -0,0 +1,361 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "armctrl.h" -+ -+/* For support of kernels >= 3.0 assume only one VIC for now*/ -+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -+ INTERRUPT_VC_JPEG, -+ INTERRUPT_VC_USB, -+ INTERRUPT_VC_3D, -+ INTERRUPT_VC_DMA2, -+ INTERRUPT_VC_DMA3, -+ INTERRUPT_VC_I2C, -+ INTERRUPT_VC_SPI, -+ INTERRUPT_VC_I2SPCM, -+ INTERRUPT_VC_SDIO, -+ INTERRUPT_VC_UART, -+ INTERRUPT_VC_ARASANSDIO -+}; -+ -+static void armctrl_mask_irq(struct irq_data *d) -+{ -+ static const unsigned int disables[4] = { -+ ARM_IRQ_DIBL1, -+ ARM_IRQ_DIBL2, -+ ARM_IRQ_DIBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ writel(0, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); // -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+static void armctrl_unmask_irq(struct irq_data *d) -+{ -+ static const unsigned int enables[4] = { -+ ARM_IRQ_ENBL1, -+ ARM_IRQ_ENBL2, -+ ARM_IRQ_ENBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+#ifdef CONFIG_OF -+ -+#define NR_IRQS_BANK0 21 -+#define NR_BANKS 4 -+#define IRQS_PER_BANK 32 -+ -+/* from drivers/irqchip/irq-bcm2835.c */ -+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -+ const u32 *intspec, unsigned int intsize, -+ unsigned long *out_hwirq, unsigned int *out_type) -+{ -+ if (WARN_ON(intsize != 2)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] >= NR_BANKS)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) -+ return -EINVAL; -+ -+ if (intspec[0] == 0) -+ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -+ else if (intspec[0] == 1) -+ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -+ else if (intspec[0] == 2) -+ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -+ else -+ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; -+ -+ /* reverse remap_irqs[] */ -+ switch (*out_hwirq) { -+ case INTERRUPT_VC_JPEG: -+ *out_hwirq = INTERRUPT_JPEG; -+ break; -+ case INTERRUPT_VC_USB: -+ *out_hwirq = INTERRUPT_USB; -+ break; -+ case INTERRUPT_VC_3D: -+ *out_hwirq = INTERRUPT_3D; -+ break; -+ case INTERRUPT_VC_DMA2: -+ *out_hwirq = INTERRUPT_DMA2; -+ break; -+ case INTERRUPT_VC_DMA3: -+ *out_hwirq = INTERRUPT_DMA3; -+ break; -+ case INTERRUPT_VC_I2C: -+ *out_hwirq = INTERRUPT_I2C; -+ break; -+ case INTERRUPT_VC_SPI: -+ *out_hwirq = INTERRUPT_SPI; -+ break; -+ case INTERRUPT_VC_I2SPCM: -+ *out_hwirq = INTERRUPT_I2SPCM; -+ break; -+ case INTERRUPT_VC_SDIO: -+ *out_hwirq = INTERRUPT_SDIO; -+ break; -+ case INTERRUPT_VC_UART: -+ *out_hwirq = INTERRUPT_UART; -+ break; -+ case INTERRUPT_VC_ARASANSDIO: -+ *out_hwirq = INTERRUPT_ARASANSDIO; -+ break; -+ } -+ -+ *out_type = IRQ_TYPE_NONE; -+ return 0; -+} -+ -+static struct irq_domain_ops armctrl_ops = { -+ .xlate = armctrl_xlate -+}; -+ -+void __init armctrl_dt_init(void) -+{ -+ struct device_node *np; -+ struct irq_domain *domain; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -+ if (!np) -+ return; -+ -+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -+ IRQ_ARMCTRL_START, 0, -+ &armctrl_ops, NULL); -+ WARN_ON(!domain); -+} -+#else -+void __init armctrl_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+#if defined(CONFIG_PM) -+ -+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -+ -+/* Static defines -+ * struct armctrl_device - VIC PM device (< 3.xx) -+ * @sysdev: The system device which is registered. (< 3.xx) -+ * @irq: The IRQ number for the base of the VIC. -+ * @base: The register base for the VIC. -+ * @resume_sources: A bitmask of interrupts for resume. -+ * @resume_irqs: The IRQs enabled for resume. -+ * @int_select: Save for VIC_INT_SELECT. -+ * @int_enable: Save for VIC_INT_ENABLE. -+ * @soft_int: Save for VIC_INT_SOFT. -+ * @protect: Save for VIC_PROTECT. -+ */ -+struct armctrl_info { -+ void __iomem *base; -+ int irq; -+ u32 resume_sources; -+ u32 resume_irqs; -+ u32 int_select; -+ u32 int_enable; -+ u32 soft_int; -+ u32 protect; -+} armctrl; -+ -+static int armctrl_suspend(void) -+{ -+ return 0; -+} -+ -+static void armctrl_resume(void) -+{ -+ return; -+} -+ -+/** -+ * armctrl_pm_register - Register a VIC for later power management control -+ * @base: The base address of the VIC. -+ * @irq: The base IRQ for the VIC. -+ * @resume_sources: bitmask of interrupts allowed for resume sources. -+ * -+ * For older kernels (< 3.xx) do - -+ * Register the VIC with the system device tree so that it can be notified -+ * of suspend and resume requests and ensure that the correct actions are -+ * taken to re-instate the settings on resume. -+ */ -+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 resume_sources) -+{ -+ armctrl.base = base; -+ armctrl.resume_sources = resume_sources; -+ armctrl.irq = irq; -+} -+ -+static int armctrl_set_wake(struct irq_data *d, unsigned int on) -+{ -+ unsigned int off = d->irq & 31; -+ u32 bit = 1 << off; -+ -+ if (!(bit & armctrl.resume_sources)) -+ return -EINVAL; -+ -+ if (on) -+ armctrl.resume_irqs |= bit; -+ else -+ armctrl.resume_irqs &= ~bit; -+ -+ return 0; -+} -+ -+#else -+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 arg1) -+{ -+} -+ -+#define armctrl_suspend NULL -+#define armctrl_resume NULL -+#define armctrl_set_wake NULL -+#endif /* CONFIG_PM */ -+ -+static struct syscore_ops armctrl_syscore_ops = { -+ .suspend = armctrl_suspend, -+ .resume = armctrl_resume, -+}; -+ -+/** -+ * armctrl_syscore_init - initicall to register VIC pm functions -+ * -+ * This is called via late_initcall() to register -+ * the resources for the VICs due to the early -+ * nature of the VIC's registration. -+*/ -+static int __init armctrl_syscore_init(void) -+{ -+ register_syscore_ops(&armctrl_syscore_ops); -+ return 0; -+} -+ -+late_initcall(armctrl_syscore_init); -+ -+static struct irq_chip armctrl_chip = { -+ .name = "ARMCTRL", -+ .irq_ack = NULL, -+ .irq_mask = armctrl_mask_irq, -+ .irq_unmask = armctrl_unmask_irq, -+ .irq_set_wake = armctrl_set_wake, -+}; -+ -+/** -+ * armctrl_init - initialise a vectored interrupt controller -+ * @base: iomem base address -+ * @irq_start: starting interrupt number, must be muliple of 32 -+ * @armctrl_sources: bitmask of interrupt sources to allow -+ * @resume_sources: bitmask of interrupt sources to allow for resume -+ */ -+int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources) -+{ -+ unsigned int irq; -+ -+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -+ unsigned int data = irq; -+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -+ data = remap_irqs[irq - INTERRUPT_JPEG]; -+ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { -+ irq_set_percpu_devid(irq); -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ } else { -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); -+ irq_set_probe(irq); -+ } -+ irq_set_chip_data(irq, (void *)data); -+ } -+ -+ armctrl_pm_register(base, irq_start, resume_sources); -+ init_FIQ(FIQ_START); -+ armctrl_dt_init(); -+ return 0; -+} -diff --git a/arch/arm/mach-bcm2709/armctrl.h b/arch/arm/mach-bcm2709/armctrl.h -new file mode 100644 -index 0000000..0aa916e ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.h -@@ -0,0 +1,27 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARMCTRL_H -+#define __BCM2708_ARMCTRL_H -+ -+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources); -+ -+#endif diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c new file mode 100644 -index 0000000..3eeeb886 +index 0000000..90773a3 --- /dev/null +++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -0,0 +1,539 @@ +@@ -0,0 +1,380 @@ +/* + * linux/arch/arm/mach-bcm2709/bcm2709.c + * @@ -3419,20 +2847,16 @@ index 0000000..3eeeb886 +#include + +#include -+#include +#include +#include + +#include +#include ++ +#include + -+#include "armctrl.h" -+ +#include + -+//#define SYSTEM_TIMER -+ +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to + * give us IO access only to 64Mbytes of physical memory (26 bits). We could + * represent this window by setting our dmamasks to 26 bits but, in fact @@ -3448,11 +2872,6 @@ index 0000000..3eeeb886 +static unsigned boardrev, serial; +static unsigned reboot_part = 0; + -+void __init bcm2709_init_irq(void) -+{ -+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); -+} -+ +static struct map_desc bcm2709_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(ARMCTRL_BASE), @@ -3511,54 +2930,6 @@ index 0000000..3eeeb886 + iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); +} + -+#ifdef SYSTEM_TIMER -+ -+/* The STC is a free running counter that increments at the rate of 1MHz */ -+#define STC_FREQ_HZ 1000000 -+ -+static inline uint32_t timer_read(void) -+{ -+ /* STC: a free running counter that increments at the rate of 1MHz */ -+ return readl(__io_address(ST_BASE + 0x04)); -+} -+ -+static unsigned long bcm2709_read_current_timer(void) -+{ -+ return timer_read(); -+} -+ -+static u64 notrace bcm2709_read_sched_clock(void) -+{ -+ return timer_read(); -+} -+ -+static cycle_t clksrc_read(struct clocksource *cs) -+{ -+ return timer_read(); -+} -+ -+static struct clocksource clocksource_stc = { -+ .name = "stc", -+ .rating = 300, -+ .read = clksrc_read, -+ .mask = CLOCKSOURCE_MASK(32), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+unsigned long frc_clock_ticks32(void) -+{ -+ return timer_read(); -+} -+ -+static void __init bcm2709_clocksource_init(void) -+{ -+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -+ printk(KERN_ERR "timer: failed to initialize clock " -+ "source %s\n", clocksource_stc.name); -+ } -+} -+#endif -+ +int calc_rsts(int partition) +{ + return PM_PASSWORD | @@ -3643,7 +3014,8 @@ index 0000000..3eeeb886 + + pm_power_off = bcm2709_power_off; + -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, ++ NULL); + if (ret) { + pr_err("of_platform_populate failed: %d\n", ret); + BUG(); @@ -3655,105 +3027,6 @@ index 0000000..3eeeb886 + system_serial_low = serial; +} + -+#ifdef SYSTEM_TIMER -+static void timer_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *clk) -+{ -+ switch (mode) { -+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ break; -+ case CLOCK_EVT_MODE_PERIODIC: -+ -+ case CLOCK_EVT_MODE_UNUSED: -+ case CLOCK_EVT_MODE_RESUME: -+ -+ default: -+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -+ (int)mode); -+ break; -+ } -+ -+} -+ -+static int timer_set_next_event(unsigned long cycles, -+ struct clock_event_device *unused) -+{ -+ unsigned long stc; -+ do { -+ stc = readl(__io_address(ST_BASE + 0x04)); -+ /* We could take a FIQ here, which may push ST above STC3 */ -+ writel(stc + cycles, __io_address(ST_BASE + 0x18)); -+ } while ((signed long) cycles >= 0 && -+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -+ >= (signed long) cycles); -+ return 0; -+} -+ -+static struct clock_event_device timer0_clockevent = { -+ .name = "timer0", -+ .shift = 32, -+ .features = CLOCK_EVT_FEAT_ONESHOT, -+ .set_mode = timer_set_mode, -+ .set_next_event = timer_set_next_event, -+}; -+ -+/* -+ * IRQ handler for the timer -+ */ -+static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) -+{ -+ struct clock_event_device *evt = &timer0_clockevent; -+ -+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -+ -+ evt->event_handler(evt); -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction bcm2709_timer_irq = { -+ .name = "BCM2709 Timer Tick", -+ .flags = IRQF_TIMER | IRQF_IRQPOLL, -+ .handler = bcm2709_timer_interrupt, -+}; -+ -+/* -+ * Set up timer interrupt, and return the current time in seconds. -+ */ -+ -+static struct delay_timer bcm2709_delay_timer = { -+ .read_current_timer = bcm2709_read_current_timer, -+ .freq = STC_FREQ_HZ, -+}; -+ -+static void __init bcm2709_timer_init(void) -+{ -+ /* init high res timer */ -+ bcm2709_clocksource_init(); -+ -+ /* -+ * Make irqs happen for the system timer -+ */ -+ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); -+ -+ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); -+ -+ timer0_clockevent.mult = -+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -+ timer0_clockevent.max_delta_ns = -+ clockevent_delta2ns(0xffffffff, &timer0_clockevent); -+ timer0_clockevent.min_delta_ns = -+ clockevent_delta2ns(0xf, &timer0_clockevent); -+ -+ timer0_clockevent.cpumask = cpumask_of(0); -+ clockevents_register_device(&timer0_clockevent); -+ -+ register_current_timer_delay(&bcm2709_delay_timer); -+} -+ -+#else -+ +static void __init bcm2709_timer_init(void) +{ + // timer control @@ -3766,7 +3039,6 @@ index 0000000..3eeeb886 + clocksource_probe(); +} + -+#endif + +void __init bcm2709_init_early(void) +{ @@ -3787,7 +3059,6 @@ index 0000000..3eeeb886 +#ifdef CONFIG_SMP +#include + -+#include +#include +#include +int dc4=0; @@ -3901,7 +3172,6 @@ index 0000000..3eeeb886 + .smp = smp_ops(bcm2709_smp_ops), +#endif + .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, + .init_time = bcm2709_timer_init, + .init_machine = bcm2709_init, + .init_early = bcm2709_init_early, @@ -3916,7 +3186,6 @@ index 0000000..3eeeb886 + .smp = smp_ops(bcm2709_smp_ops), +#endif + .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, + .init_time = bcm2709_timer_init, + .init_machine = bcm2709_init, + .init_early = bcm2709_init_early, @@ -3928,505 +3197,6 @@ index 0000000..3eeeb886 +module_param(boardrev, uint, 0644); +module_param(serial, uint, 0644); +module_param(reboot_part, uint, 0644); -diff --git a/arch/arm/mach-bcm2709/include/mach/arm_control.h b/arch/arm/mach-bcm2709/include/mach/arm_control.h -new file mode 100644 -index 0000000..e346caf ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h -@@ -0,0 +1,493 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/arm_control.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARM_CONTROL_H -+#define __BCM2708_ARM_CONTROL_H -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define ARM_BASE 0x7E00B000 -+ -+/* Basic configuration */ -+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) -+#define ARM_C0_SIZ128M 0x00000000 -+#define ARM_C0_SIZ256M 0x00000001 -+#define ARM_C0_SIZ512M 0x00000002 -+#define ARM_C0_SIZ1G 0x00000003 -+#define ARM_C0_BRESP0 0x00000000 -+#define ARM_C0_BRESP1 0x00000004 -+#define ARM_C0_BRESP2 0x00000008 -+#define ARM_C0_BOOTHI 0x00000010 -+#define ARM_C0_UNUSED05 0x00000020 /* free */ -+#define ARM_C0_FULLPERI 0x00000040 -+#define ARM_C0_UNUSED78 0x00000180 /* free */ -+#define ARM_C0_JTAGMASK 0x00000E00 -+#define ARM_C0_JTAGOFF 0x00000000 -+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ -+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ -+#define ARM_C0_APROTMSK 0x0000F000 -+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ -+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ -+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ -+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ -+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ -+#define ARM_C0_PRIO_L2 0x0F000000 -+#define ARM_C0_PRIO_UC 0xF0000000 -+ -+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ -+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ -+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -+ -+ -+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) -+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ -+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ -+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ -+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ -+#define ARM_C1_PERSON 0x00000100 /* peripherals on */ -+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -+ -+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) -+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ -+#define ARM_S_READPEND 0x000003FF /* pending reads counter */ -+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -+ -+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) -+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ -+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ -+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ -+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ -+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ -+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -+ -+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) -+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) -+#define ARM_IDVAL 0x364D5241 -+ -+/* Translation memory */ -+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) -+/* 32 locations: 0x100.. 0x17F */ -+/* 32 spare means we CAN go to 64 pages.... */ -+ -+ -+/* Interrupts */ -+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ -+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ -+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ -+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -+ -+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ -+/* todo: all I1_interrupt sources */ -+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ -+/* todo: all I2_interrupt sources */ -+ -+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ -+#define ARM_IF_INDEX 0x0000007F /* FIQ select */ -+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ -+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ -+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ -+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ -+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ -+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ -+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ -+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ -+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -+ -+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ -+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ -+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ -+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ -+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ -+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ -+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ -+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ -+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ -+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -+ -+/* Timer */ -+/* For reg. fields see sp804 spec. */ -+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) -+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) -+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) -+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) -+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) -+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) -+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) -+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) -+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -+ -+#define TIMER_CTRL_ONESHOT (1 << 0) -+#define TIMER_CTRL_32BIT (1 << 1) -+#define TIMER_CTRL_DIV1 (0 << 2) -+#define TIMER_CTRL_DIV16 (1 << 2) -+#define TIMER_CTRL_DIV256 (2 << 2) -+#define TIMER_CTRL_IE (1 << 5) -+#define TIMER_CTRL_PERIODIC (1 << 6) -+#define TIMER_CTRL_ENABLE (1 << 7) -+#define TIMER_CTRL_DBGHALT (1 << 8) -+#define TIMER_CTRL_ENAFREE (1 << 9) -+#define TIMER_CTRL_FREEDIV_SHIFT 16) -+#define TIMER_CTRL_FREEDIV_MASK 0xff -+ -+/* Semaphores, Doorbells, Mailboxes */ -+#define ARM_SBM_OWN0 (ARM_BASE+0x800) -+#define ARM_SBM_OWN1 (ARM_BASE+0x900) -+#define ARM_SBM_OWN2 (ARM_BASE+0xA00) -+#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -+ -+/* MAILBOXES -+ * Register flags are common across all -+ * owner registers. See end of this section -+ * -+ * Semaphores, Doorbells, Mailboxes Owner 0 -+ * -+ */ -+ -+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) -+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) -+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) -+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) -+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) -+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) -+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) -+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) -+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) -+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) -+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Some addresses should ONLY be used by owner 0 */ -+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ -+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ -+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ -+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ -+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ -+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ -+/* MAILBOX 1 access in Owner 0 area */ -+/* Owner 0 should only WRITE to this mailbox */ -+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ -+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ -+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ -+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ -+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 1 */ -+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) -+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) -+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) -+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) -+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) -+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) -+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) -+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) -+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) -+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) -+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Owner 1 should only WRITE to this mailbox */ -+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ -+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 0 area */ -+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ -+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ -+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ -+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ -+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ -+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ -+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ -+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ -+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 2 */ -+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) -+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) -+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) -+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) -+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) -+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) -+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) -+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) -+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) -+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) -+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) -+/* MAILBOX 0 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ -+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ -+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ -+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ -+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ -+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 3 */ -+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) -+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) -+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) -+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) -+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) -+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) -+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) -+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) -+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) -+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) -+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) -+/* MAILBOX 0 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ -+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ -+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ -+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ -+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ -+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -+ -+ -+ -+/* Mailbox flags. Valid for all owners */ -+ -+/* Mailbox status register (...0x98) */ -+#define ARM_MS_FULL 0x80000000 -+#define ARM_MS_EMPTY 0x40000000 -+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -+ -+/* MAILBOX config/status register (...0x9C) */ -+/* ANY write to this register clears the error bits! */ -+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ -+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ -+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ -+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ -+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ -+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ -+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ -+/* Bit 7 is unused */ -+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ -+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ -+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -+ -+/* Semaphore clear/debug register (...0xE0) */ -+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ -+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ -+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ -+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ -+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ -+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ -+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ -+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ -+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ -+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ -+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ -+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ -+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ -+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ -+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ -+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -+ -+/* Doorbells clear/debug register (...0xE4) */ -+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ -+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ -+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ -+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ -+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ -+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ -+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ -+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -+ -+/* MY IRQS register (...0xF8) */ -+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ -+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -+ -+/* ALL IRQS register (...0xF8) */ -+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ -+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ -+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ -+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ -+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ -+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ -+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ -+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ -+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ -+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ -+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ -+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ -+/* */ -+/* ARM JTAG BASH */ -+/* */ -+#define AJB_BASE 0x7e2000c0 -+ -+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) -+#define AJB_BITS0 0x000000 -+#define AJB_BITS4 0x000004 -+#define AJB_BITS8 0x000008 -+#define AJB_BITS12 0x00000C -+#define AJB_BITS16 0x000010 -+#define AJB_BITS20 0x000014 -+#define AJB_BITS24 0x000018 -+#define AJB_BITS28 0x00001C -+#define AJB_BITS32 0x000020 -+#define AJB_BITS34 0x000022 -+#define AJB_OUT_MS 0x000040 -+#define AJB_OUT_LS 0x000000 -+#define AJB_INV_CLK 0x000080 -+#define AJB_D0_RISE 0x000100 -+#define AJB_D0_FALL 0x000000 -+#define AJB_D1_RISE 0x000200 -+#define AJB_D1_FALL 0x000000 -+#define AJB_IN_RISE 0x000400 -+#define AJB_IN_FALL 0x000000 -+#define AJB_ENABLE 0x000800 -+#define AJB_HOLD0 0x000000 -+#define AJB_HOLD1 0x001000 -+#define AJB_HOLD2 0x002000 -+#define AJB_HOLD3 0x003000 -+#define AJB_RESETN 0x004000 -+#define AJB_CLKSHFT 16 -+#define AJB_BUSY 0x80000000 -+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) -+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) -+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -+ -+#define ARM_LOCAL_BASE 0x40000000 -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) -+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) -+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) -+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) -+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) -+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) -+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) -+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) -+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) -+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) -+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -+ -+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) -+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) -+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) -+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -+ -+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -+ -+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) -+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) -+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) -+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -+ -+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) -+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) -+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) -+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -+ -+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) -+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) -+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) -+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -+ -+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) -+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) -+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) -+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -+ -+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) -+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) -+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) -+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -+ -+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) -+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) -+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) -+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) -+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) -+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) -+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) -+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) -+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) -+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) -+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) -+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) -+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) -+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) -+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) -+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -+ -+#endif diff --git a/arch/arm/mach-bcm2709/include/mach/debug-macro.S b/arch/arm/mach-bcm2709/include/mach/debug-macro.S new file mode 100644 index 0000000..b24304a @@ -4584,40 +3354,6 @@ index 0000000..d08591b + dsb +1030: @ EQ will be set if no irqs pending + .endm -diff --git a/arch/arm/mach-bcm2709/include/mach/hardware.h b/arch/arm/mach-bcm2709/include/mach/hardware.h -new file mode 100644 -index 0000000..c2954e8 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/hardware.h -@@ -0,0 +1,28 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/hardware.h -+ * -+ * This file contains the hardware definitions of the BCM2708 devices. -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include -+#include -+ -+#endif diff --git a/arch/arm/mach-bcm2709/include/mach/io.h b/arch/arm/mach-bcm2709/include/mach/io.h new file mode 100644 index 0000000..e6eb84d @@ -4651,237 +3387,6 @@ index 0000000..e6eb84d +#define __io(a) __typesafe_io(a) + +#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/irqs.h b/arch/arm/mach-bcm2709/include/mach/irqs.h -new file mode 100644 -index 0000000..d301f06 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/irqs.h -@@ -0,0 +1,225 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/irqs.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_IRQS_H_ -+#define _BCM2708_IRQS_H_ -+ -+#include -+ -+/* -+ * IRQ interrupts definitions are the same as the INT definitions -+ * held within platform.h -+ */ -+#define IRQ_ARMCTRL_START 0 -+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) -+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) -+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) -+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) -+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) -+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) -+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) -+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) -+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) -+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) -+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) -+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) -+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) -+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) -+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) -+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) -+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) -+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) -+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) -+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) -+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) -+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) -+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) -+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) -+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) -+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) -+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) -+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) -+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) -+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) -+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) -+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) -+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) -+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) -+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) -+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) -+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) -+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) -+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) -+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) -+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) -+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) -+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) -+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) -+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) -+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) -+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) -+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) -+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) -+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) -+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) -+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) -+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) -+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) -+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) -+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) -+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) -+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) -+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) -+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) -+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) -+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) -+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) -+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -+ -+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) -+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) -+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) -+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) -+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) -+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) -+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) -+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) -+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) -+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -+ -+#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define FIQ_START HARD_IRQS -+ -+/* -+ * FIQ interrupts definitions are the same as the INT definitions. -+ */ -+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) -+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) -+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) -+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) -+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) -+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) -+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) -+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) -+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) -+#define FIQ_USB (FIQ_START+INTERRUPT_USB) -+#define FIQ_3D (FIQ_START+INTERRUPT_3D) -+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) -+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) -+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) -+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) -+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) -+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) -+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) -+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) -+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) -+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) -+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) -+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) -+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) -+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) -+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) -+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) -+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) -+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) -+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) -+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) -+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) -+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) -+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) -+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) -+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) -+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) -+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) -+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) -+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) -+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) -+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) -+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) -+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) -+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) -+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) -+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) -+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) -+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) -+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) -+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) -+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) -+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) -+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) -+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) -+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) -+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) -+#define FIQ_UART (FIQ_START+INTERRUPT_UART) -+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) -+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) -+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) -+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) -+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) -+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -+ -+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) -+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) -+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) -+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) -+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) -+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) -+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) -+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) -+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) -+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -+ -+#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define HARD_IRQS (128) -+#define FIQ_IRQS (128) -+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) -+#define GPIO_IRQS (32*5) -+#define SPARE_ALLOC_IRQS 64 -+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) -+#define FREE_IRQS 128 -+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -+ -+#endif /* _BCM2708_IRQS_H_ */ diff --git a/arch/arm/mach-bcm2709/include/mach/memory.h b/arch/arm/mach-bcm2709/include/mach/memory.h new file mode 100644 index 0000000..7548a52 @@ -4947,10 +3452,10 @@ index 0000000..7548a52 +#endif diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h new file mode 100644 -index 0000000..7157f38 +index 0000000..311b9f2 --- /dev/null +++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -0,0 +1,225 @@ +@@ -0,0 +1,188 @@ +/* + * arch/arm/mach-bcm2708/include/mach/platform.h + * @@ -5000,9 +3505,6 @@ index 0000000..7157f38 +#define HW_REGISTER_RW(addr) (addr) +#define HW_REGISTER_RO(addr) (addr) + -+#include "arm_control.h" -+#undef ARM_BASE -+ +/* + * Definitions and addresses for the ARM CONTROL logic + * This file is manually generated. @@ -5035,116 +3537,6 @@ index 0000000..7157f38 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ + -+ -+/* -+ * Interrupt assignments -+ */ -+ -+#define ARM_IRQ1_BASE 0 -+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) -+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) -+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) -+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) -+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) -+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) -+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) -+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) -+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) -+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) -+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) -+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) -+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) -+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) -+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) -+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) -+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) -+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) -+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) -+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) -+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) -+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) -+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) -+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) -+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) -+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) -+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) -+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) -+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) -+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) -+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) -+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -+ -+#define ARM_IRQ2_BASE 32 -+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) -+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) -+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) -+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) -+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) -+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) -+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) -+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) -+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) -+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) -+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) -+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) -+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) -+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) -+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) -+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) -+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) -+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) -+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) -+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) -+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) -+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) -+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) -+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) -+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) -+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) -+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) -+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) -+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) -+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) -+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) -+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -+ -+#define ARM_IRQ0_BASE 64 -+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) -+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) -+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) -+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) -+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) -+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) -+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) -+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) -+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) -+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) -+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) -+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) -+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) -+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) -+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) -+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) -+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) -+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) -+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) -+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) -+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -+ -+#define ARM_IRQ_LOCAL_BASE 96 -+#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) -+#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) -+#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) -+#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) -+#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) -+#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) -+#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) -+#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) -+#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) -+#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) -+#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) -+#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) -+ +/* + * Watchdog + */ @@ -5173,15 +3565,91 @@ index 0000000..7157f38 + +#define UART0_CLOCK 3000000 + ++#define ARM_LOCAL_BASE 0x40000000 ++#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) ++ ++#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) ++#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) ++#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) ++#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) ++#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) ++#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) ++#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) ++#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) ++#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) ++#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) ++#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) ++#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) ++ ++#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) ++#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) ++#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) ++#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) ++ ++#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) ++ ++#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) ++#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) ++#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) ++#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) ++ ++#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) ++#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) ++#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) ++#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) ++ ++#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) ++#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) ++#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) ++#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) ++ ++#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) ++#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) ++#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) ++#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) ++ ++#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) ++#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) ++#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) ++#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) ++ ++#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) ++#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) ++#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) ++#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) ++#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) ++#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) ++#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) ++#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) ++#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) ++#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) ++#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) ++#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) ++#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) ++#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) ++#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) ++#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) ++ +#endif + +/* END */ diff --git a/arch/arm/mach-bcm2709/include/mach/system.h b/arch/arm/mach-bcm2709/include/mach/system.h new file mode 100644 -index 0000000..2d0b821 +index 0000000..c9a9c9a --- /dev/null +++ b/arch/arm/mach-bcm2709/include/mach/system.h -@@ -0,0 +1,38 @@ +@@ -0,0 +1,37 @@ +/* + * arch/arm/mach-bcm2708/include/mach/system.h + * @@ -5207,7 +3675,6 @@ index 0000000..2d0b821 +#define __ASM_ARCH_SYSTEM_H + +#include -+#include +#include + +static inline void arch_idle(void) @@ -5222,7 +3689,7 @@ index 0000000..2d0b821 +#endif diff --git a/arch/arm/mach-bcm2709/include/mach/uncompress.h b/arch/arm/mach-bcm2709/include/mach/uncompress.h new file mode 100644 -index 0000000..d634813 +index 0000000..de7504b --- /dev/null +++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h @@ -0,0 +1,84 @@ @@ -5249,7 +3716,7 @@ index 0000000..d634813 + +#include +#include -+#include ++#include + +#define UART_BAUD 115200 + @@ -5855,7 +4322,7 @@ index 06d890a..30d96e8 100644 ENTRY(cpu_v6_dcache_clean_area) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S -index de2b246..3a3aec8 100644 +index 8e1ea43..be40ccb 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -480,6 +480,7 @@ __errata_finish: @@ -5893,14 +4360,16 @@ index 56bd16e..c2ac46d 100644 obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index 177f78f..27b8467 100644 +index 177f78f..6a9e2d0 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile -@@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o +@@ -2,6 +2,9 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o +obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o ++obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2835.o ++obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o obj-$(CONFIG_ARCH_MMP) += irq-mmp.o @@ -5920,10 +4389,10 @@ index 8673ffe..ad22ebb 100644 2.5.0 -From 09a09a752f40a9a5e43e906670afc00e5119391a Mon Sep 17 00:00:00 2001 +From 4f7a784e0256c10f6200438aa74e385e151c2241 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 11 Nov 2015 21:01:15 +0000 -Subject: [PATCH 29/55] squash: include ARCH_BCM2708 / ARCH_BCM2709 +Subject: [PATCH 28/54] squash: include ARCH_BCM2708 / ARCH_BCM2709 --- drivers/char/hw_random/Kconfig | 2 +- @@ -6078,10 +4547,10 @@ index 6a834e1..c5070ae 100644 2.5.0 -From 28f5227ea6cdf14dbdad6b4790a417a24949f080 Mon Sep 17 00:00:00 2001 +From 43a51c6dbdb406826da11b1101cc6511d1185d67 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:46:17 +0100 -Subject: [PATCH 30/55] Add dwc_otg driver +Subject: [PATCH 29/54] Add dwc_otg driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -6547,7 +5016,6 @@ dwc_otg: Remove duplicate gadget probe/unregister function --- arch/arm/include/asm/irqflags.h | 16 +- arch/arm/kernel/fiqasm.S | 4 + - arch/arm/mach-bcm2709/armctrl.c | 10 +- drivers/usb/Makefile | 1 + drivers/usb/core/generic.c | 1 + drivers/usb/core/hub.c | 2 +- @@ -6616,7 +5084,7 @@ dwc_otg: Remove duplicate gadget probe/unregister function drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 + drivers/usb/host/dwc_otg/test/test_mod_param.pl | 133 + drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 + - 71 files changed, 59876 insertions(+), 17 deletions(-) + 70 files changed, 59867 insertions(+), 16 deletions(-) create mode 100644 drivers/usb/gadget/file_storage.c create mode 100644 drivers/usb/host/dwc_common_port/Makefile create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd @@ -6722,27 +5190,6 @@ index 8dd26e1..eef4847 100644 +ENTRY(__FIQ_Branch) + mov pc, r8 +ENDPROC(__FIQ_Branch) -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -index 813008a..c6f68b4 100644 ---- a/arch/arm/mach-bcm2709/armctrl.c -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -91,7 +91,15 @@ static void armctrl_unmask_irq(struct irq_data *d) - }; - int i; - if (d->irq >= FIQ_START) { -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ unsigned int data; -+ if (num_online_cpus() > 1) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= (1 << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ /* Unmask in ARMCTRL block after routing it properly */ -+ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; - writel(0x80 | data, __io_address(ARM_IRQ_FAST)); - } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { - #if 1 diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index d5c57f1..0e15a22 100644 --- a/drivers/usb/Makefile @@ -6768,10 +5215,10 @@ index 358ca8d..abaac7c 100644 return i; } diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c -index a5cc032..4bc2626 100644 +index ddbf32d..12166e2 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c -@@ -4930,7 +4930,7 @@ static void port_event(struct usb_hub *hub, int port1) +@@ -4946,7 +4946,7 @@ static void port_event(struct usb_hub *hub, int port1) if (portchange & USB_PORT_STAT_C_OVERCURRENT) { u16 status = 0, unused; @@ -67085,10 +65532,10 @@ index 0000000..cdc9963 2.5.0 -From 621d61cc9ba873aa2ca9bb0fc7cef9aaae7f9167 Mon Sep 17 00:00:00 2001 +From e84cab190a51bb9d04b38e76ce90a47c0f93da5e Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 17 Jun 2015 17:06:34 +0100 -Subject: [PATCH 31/55] bcm2708 framebuffer driver +Subject: [PATCH 30/54] bcm2708 framebuffer driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -70553,10 +69000,10 @@ index 3c14e43..7626beb 100644 2.5.0 -From 090f8a9ade61015468e0116089a3cf084488274c Mon Sep 17 00:00:00 2001 +From 227880a04368c2840eb27d8d25aaee1cfd7e5c3a Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:22:53 +0100 -Subject: [PATCH 32/55] dmaengine: Add support for BCM2708 +Subject: [PATCH 31/54] dmaengine: Add support for BCM2708 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -71179,10 +69626,10 @@ index 0000000..99cc7fd 2.5.0 -From 71b2809c60befcf445b96bc6a2a6c556db1e63c7 Mon Sep 17 00:00:00 2001 +From 68dc1707b0e75ca092319956776e656bc3b42315 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 17 Apr 2015 19:30:22 +0100 -Subject: [PATCH 33/55] Add blk_pos parameter to mmc multi_io_quirk callback +Subject: [PATCH 32/54] Add blk_pos parameter to mmc multi_io_quirk callback --- drivers/mmc/card/block.c | 1 + @@ -71268,10 +69715,10 @@ index ad22ebb..105b3e6 100644 2.5.0 -From 12ca0b3680d241ad7699e0b5100127adce522c91 Mon Sep 17 00:00:00 2001 +From c9c3712517791991bc66744c3931cee457a70018 Mon Sep 17 00:00:00 2001 From: gellert Date: Fri, 15 Aug 2014 16:35:06 +0100 -Subject: [PATCH 34/55] MMC: added alternative MMC driver +Subject: [PATCH 33/54] MMC: added alternative MMC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -71341,8 +69788,8 @@ bcm2835-mmc: Don't overwrite MMC capabilities from DT drivers/mmc/core/quirks.c | 6 + drivers/mmc/host/Kconfig | 29 + drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/bcm2835-mmc.c | 1559 ++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 1595 insertions(+) + drivers/mmc/host/bcm2835-mmc.c | 1542 ++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 1578 insertions(+) create mode 100644 drivers/mmc/host/bcm2835-mmc.c diff --git a/drivers/mmc/core/quirks.c b/drivers/mmc/core/quirks.c @@ -71422,10 +69869,10 @@ index 3595f83..6cf6457 100644 obj-$(CONFIG_MMC_MTK) += mtk-sd.o diff --git a/drivers/mmc/host/bcm2835-mmc.c b/drivers/mmc/host/bcm2835-mmc.c new file mode 100644 -index 0000000..164bfad +index 0000000..43aed6e --- /dev/null +++ b/drivers/mmc/host/bcm2835-mmc.c -@@ -0,0 +1,1559 @@ +@@ -0,0 +1,1542 @@ +/* + * BCM2835 MMC host driver. + * @@ -71491,13 +69938,6 @@ index 0000000..164bfad +#define TIMEOUT_VAL 0xE +#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1) + -+#ifndef BCM2708_PERI_BASE -+ #define BCM2708_PERI_BASE 0x20000000 -+#endif -+ -+/* FIXME: Needs IOMMU support */ -+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) -+ + +unsigned mmc_debug; +unsigned mmc_debug2; @@ -71506,7 +69946,7 @@ index 0000000..164bfad + spinlock_t lock; + + void __iomem *ioaddr; -+ u32 phys_addr; ++ u32 bus_addr; + + struct mmc_host *mmc; + @@ -72112,12 +70552,10 @@ index 0000000..164bfad + } + + timeout = jiffies; -+#ifdef CONFIG_ARCH_BCM2835 + if (!cmd->data && cmd->busy_timeout > 9000) + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; + else -+#endif -+ timeout += 10 * HZ; ++ timeout += 10 * HZ; + mod_timer(&host->timer, timeout); + + host->cmd = cmd; @@ -72412,9 +70850,6 @@ index 0000000..164bfad + struct bcm2835_host *host = dev_id; + u32 intmask, mask, unexpected = 0; + int max_loops = 16; -+#ifndef CONFIG_ARCH_BCM2835 -+ int cardint = 0; -+#endif + + spin_lock(&host->lock); + @@ -72443,13 +70878,9 @@ index 0000000..164bfad + mmc_hostname(host->mmc)); + + if (intmask & SDHCI_INT_CARD_INT) { -+#ifndef CONFIG_ARCH_BCM2835 -+ cardint = 1; -+#else + bcm2835_mmc_enable_sdio_irq_nolock(host, false); + host->thread_isr |= SDHCI_INT_CARD_INT; + result = IRQ_WAKE_THREAD; -+#endif + } + + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | @@ -72476,15 +70907,9 @@ index 0000000..164bfad + bcm2835_mmc_dumpregs(host); + } + -+#ifndef CONFIG_ARCH_BCM2835 -+ if (cardint) -+ mmc_signal_sdio_irq(host->mmc); -+#endif -+ + return result; +} + -+#ifdef CONFIG_ARCH_BCM2835 +static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) +{ + struct bcm2835_host *host = dev_id; @@ -72507,7 +70932,6 @@ index 0000000..164bfad + + return isr ? IRQ_HANDLED : IRQ_NONE; +} -+#endif + + + @@ -72751,14 +71175,15 @@ index 0000000..164bfad + + /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ + host->timeout_clk = mmc->f_max / 1000; -+#ifdef CONFIG_ARCH_BCM2835 + mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; -+#endif ++ + /* host controller capabilities */ + mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | + MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; + ++ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; ++ + host->flags = SDHCI_AUTO_CMD23; + + dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2); @@ -72781,11 +71206,11 @@ index 0000000..164bfad + + cfg.direction = DMA_MEM_TO_DEV; + cfg.src_addr = 0; -+ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER; ++ cfg.dst_addr = host->bus_addr + SDHCI_BUFFER; + ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); + + cfg.direction = DMA_DEV_TO_MEM; -+ cfg.src_addr = host->phys_addr + SDHCI_BUFFER; ++ cfg.src_addr = host->bus_addr + SDHCI_BUFFER; + cfg.dst_addr = 0; + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); + } @@ -72806,14 +71231,9 @@ index 0000000..164bfad + init_waitqueue_head(&host->buf_ready_int); + + bcm2835_mmc_init(host, 0); -+#ifndef CONFIG_ARCH_BCM2835 -+ ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0, -+ mmc_hostname(mmc), host); -+#else + ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq, + bcm2835_mmc_thread_irq, IRQF_SHARED, + mmc_hostname(mmc), host); -+#endif + if (ret) { + dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret); + goto untasklet; @@ -72838,6 +71258,7 @@ index 0000000..164bfad + struct resource *iomem; + struct bcm2835_host *host; + struct mmc_host *mmc; ++ const __be32 *addr; + int ret; + + mmc = mmc_alloc_host(sizeof(*host), dev); @@ -72857,7 +71278,16 @@ index 0000000..164bfad + goto err; + } + -+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; ++ addr = of_get_address(node, 0, NULL, NULL); ++ if (!addr) { ++ dev_err(dev, "could not get DMA-register address\n"); ++ return -ENODEV; ++ } ++ host->bus_addr = be32_to_cpup(addr); ++ pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n", ++ (unsigned long)host->ioaddr, ++ (unsigned long)iomem->start, ++ (unsigned long)host->bus_addr); + +#ifndef FORCE_PIO + if (node) { @@ -72989,10 +71419,10 @@ index 0000000..164bfad 2.5.0 -From 85337ce70f7c4a3b6c3cbcdbf9081307247b3a9c Mon Sep 17 00:00:00 2001 +From e43ccd0115b085c56aa7396bdb973d244379222d Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 25 Mar 2015 17:49:47 +0000 -Subject: [PATCH 35/55] Adding bcm2835-sdhost driver, and an overlay to enable +Subject: [PATCH 34/54] Adding bcm2835-sdhost driver, and an overlay to enable it BCM2835 has two SD card interfaces. This driver uses the other one. @@ -73058,12 +71488,18 @@ rather than making the change across the board; I can't see any technical reason why it wouldn't be enabled for MACH_BCM270X builds. So this patch standardises on the ARCH_BCM2835 code, removing the old code paths. + +bcm2835-sdhost: Don't log timeout errors unless debug=1 + +The MMC card-discovery process generates timeouts. This is +expected behaviour, so reporting it to the user serves no purpose. +Suppress the reporting of timeout errors unless the debug flag +is on. --- drivers/mmc/host/Kconfig | 10 + drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/bcm2835-mmc.c | 28 +- - drivers/mmc/host/bcm2835-sdhost.c | 1912 +++++++++++++++++++++++++++++++++++++ - 4 files changed, 1927 insertions(+), 24 deletions(-) + drivers/mmc/host/bcm2835-sdhost.c | 1907 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 1918 insertions(+) create mode 100644 drivers/mmc/host/bcm2835-sdhost.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig @@ -73099,111 +71535,12 @@ index 6cf6457..df27ae9 100644 obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o -diff --git a/drivers/mmc/host/bcm2835-mmc.c b/drivers/mmc/host/bcm2835-mmc.c -index 164bfad..0f89e57 100644 ---- a/drivers/mmc/host/bcm2835-mmc.c -+++ b/drivers/mmc/host/bcm2835-mmc.c -@@ -684,12 +684,10 @@ void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd - } - - timeout = jiffies; --#ifdef CONFIG_ARCH_BCM2835 - if (!cmd->data && cmd->busy_timeout > 9000) - timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; - else --#endif -- timeout += 10 * HZ; -+ timeout += 10 * HZ; - mod_timer(&host->timer, timeout); - - host->cmd = cmd; -@@ -984,9 +982,6 @@ static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id) - struct bcm2835_host *host = dev_id; - u32 intmask, mask, unexpected = 0; - int max_loops = 16; --#ifndef CONFIG_ARCH_BCM2835 -- int cardint = 0; --#endif - - spin_lock(&host->lock); - -@@ -1015,13 +1010,9 @@ static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id) - mmc_hostname(host->mmc)); - - if (intmask & SDHCI_INT_CARD_INT) { --#ifndef CONFIG_ARCH_BCM2835 -- cardint = 1; --#else - bcm2835_mmc_enable_sdio_irq_nolock(host, false); - host->thread_isr |= SDHCI_INT_CARD_INT; - result = IRQ_WAKE_THREAD; --#endif - } - - intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | -@@ -1048,15 +1039,9 @@ out: - bcm2835_mmc_dumpregs(host); - } - --#ifndef CONFIG_ARCH_BCM2835 -- if (cardint) -- mmc_signal_sdio_irq(host->mmc); --#endif -- - return result; - } - --#ifdef CONFIG_ARCH_BCM2835 - static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) - { - struct bcm2835_host *host = dev_id; -@@ -1079,7 +1064,6 @@ static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) - - return isr ? IRQ_HANDLED : IRQ_NONE; - } --#endif - - - -@@ -1323,14 +1307,15 @@ static int bcm2835_mmc_add_host(struct bcm2835_host *host) - - /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ - host->timeout_clk = mmc->f_max / 1000; --#ifdef CONFIG_ARCH_BCM2835 - mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; --#endif -+ - /* host controller capabilities */ - mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | - MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; - -+ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; -+ - host->flags = SDHCI_AUTO_CMD23; - - dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2); -@@ -1378,14 +1363,9 @@ static int bcm2835_mmc_add_host(struct bcm2835_host *host) - init_waitqueue_head(&host->buf_ready_int); - - bcm2835_mmc_init(host, 0); --#ifndef CONFIG_ARCH_BCM2835 -- ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0, -- mmc_hostname(mmc), host); --#else - ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq, - bcm2835_mmc_thread_irq, IRQF_SHARED, - mmc_hostname(mmc), host); --#endif - if (ret) { - dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret); - goto untasklet; diff --git a/drivers/mmc/host/bcm2835-sdhost.c b/drivers/mmc/host/bcm2835-sdhost.c new file mode 100644 -index 0000000..0623392 +index 0000000..da089985 --- /dev/null +++ b/drivers/mmc/host/bcm2835-sdhost.c -@@ -0,0 +1,1912 @@ +@@ -0,0 +1,1907 @@ +/* + * BCM2835 SD host driver. + * @@ -73318,19 +71655,12 @@ index 0000000..0623392 + +#define MHZ 1000000 + -+#ifndef BCM2708_PERI_BASE -+ #define BCM2708_PERI_BASE 0x20000000 -+#endif -+ -+/* FIXME: Needs IOMMU support */ -+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) -+ + +struct bcm2835_host { + spinlock_t lock; + + void __iomem *ioaddr; -+ u32 phys_addr; ++ u32 bus_addr; + + struct mmc_host *mmc; + @@ -74172,19 +72502,15 @@ index 0000000..0623392 + mmc_hostname(host->mmc)); + } else { + if (sdhsts & SDHSTS_CMD_TIME_OUT) { -+ switch (host->cmd->opcode) { -+ case 5: case 52: case 53: -+ /* Don't warn about SDIO commands */ -+ break; -+ default: -+ pr_err("%s: command timeout\n", -+ mmc_hostname(host->mmc)); -+ break; -+ } ++ if (host->debug) ++ pr_err("%s: command %d timeout\n", ++ mmc_hostname(host->mmc), ++ host->cmd->opcode); + host->cmd->error = -ETIMEDOUT; + } else { -+ pr_err("%s: unexpected command error\n", -+ mmc_hostname(host->mmc)); ++ pr_err("%s: unexpected command %d error\n", ++ mmc_hostname(host->mmc), ++ host->cmd->opcode); + bcm2835_sdhost_dumpregs(host); + host->cmd->error = -EIO; + } @@ -74896,11 +73222,11 @@ index 0000000..0623392 + + cfg.direction = DMA_MEM_TO_DEV; + cfg.src_addr = 0; -+ cfg.dst_addr = host->phys_addr + SDDATA; ++ cfg.dst_addr = host->bus_addr + SDDATA; + ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); + + cfg.direction = DMA_DEV_TO_MEM; -+ cfg.src_addr = host->phys_addr + SDDATA; ++ cfg.src_addr = host->bus_addr + SDDATA; + cfg.dst_addr = 0; + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); + } @@ -74963,6 +73289,7 @@ index 0000000..0623392 + struct resource *iomem; + struct bcm2835_host *host; + struct mmc_host *mmc; ++ const __be32 *addr; + int ret; + + pr_debug("bcm2835_sdhost_probe\n"); @@ -74984,11 +73311,16 @@ index 0000000..0623392 + goto err; + } + -+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; -+ pr_debug(" - ioaddr %lx, iomem->start %lx, phys_addr %lx\n", ++ addr = of_get_address(node, 0, NULL, NULL); ++ if (!addr) { ++ dev_err(dev, "could not get DMA-register address\n"); ++ return -ENODEV; ++ } ++ host->bus_addr = be32_to_cpup(addr); ++ pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n", + (unsigned long)host->ioaddr, + (unsigned long)iomem->start, -+ (unsigned long)host->phys_addr); ++ (unsigned long)host->bus_addr); + + host->allow_dma = ALLOW_DMA; + @@ -75120,10 +73452,10 @@ index 0000000..0623392 2.5.0 -From 39227ce9f8858235378890ce2d11c288456c9358 Mon Sep 17 00:00:00 2001 +From a1c91b2e27db42a9d753a2d752a4db2339971786 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:31:47 +0100 -Subject: [PATCH 36/55] cma: Add vc_cma driver to enable use of CMA +Subject: [PATCH 35/54] cma: Add vc_cma driver to enable use of CMA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -76469,10 +74801,10 @@ index 0000000..be2819d 2.5.0 -From b9efed95844aad3b24e713ea16fc3a44bd9bd9dd Mon Sep 17 00:00:00 2001 +From 288825203141275ee6ce0054b7c19b93468f6ea7 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 26 Mar 2012 22:15:50 +0100 -Subject: [PATCH 37/55] bcm2708: alsa sound driver +Subject: [PATCH 36/54] bcm2708: alsa sound driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -79173,10 +77505,10 @@ index 0000000..af3e6eb 2.5.0 -From 7ab358eb5831ee8a6301389d0e5d7caec579fc07 Mon Sep 17 00:00:00 2001 +From 10bbede5e3a5cda000722a6710342a49c7a66a97 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 2 Jul 2013 23:42:01 +0100 -Subject: [PATCH 38/55] bcm2708 vchiq driver +Subject: [PATCH 37/54] bcm2708 vchiq driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -79433,18 +77765,18 @@ index 4fb43cf..e98ec5a 100644 /* * Watchdog diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h -index 7157f38..be99733 100644 +index 311b9f2..9a638f5 100644 --- a/arch/arm/mach-bcm2709/include/mach/platform.h +++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -81,6 +81,8 @@ +@@ -78,6 +78,8 @@ #define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ #define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ #define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ +#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ +#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ - /* + * Watchdog diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 22892c7..b859ce0 100644 --- a/drivers/misc/Kconfig @@ -92484,10 +90816,10 @@ index 0000000..b6bfa21 2.5.0 -From d2519589b514436dd0f05bf7a0c03ca5449bea3d Mon Sep 17 00:00:00 2001 +From 39ea0d34e648bca5995ae2f578a2a151761e32bb Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 17 Jun 2015 16:07:06 +0100 -Subject: [PATCH 39/55] vc_mem: Add vc_mem driver +Subject: [PATCH 38/54] vc_mem: Add vc_mem driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -93495,10 +91827,10 @@ index 0000000..20a4753 2.5.0 -From 31a3d1e4846bade73ff545da696da5114c40d293 Mon Sep 17 00:00:00 2001 +From 482bc90fdaa1d40622db38100a193d00948ae585 Mon Sep 17 00:00:00 2001 From: Tim Gover Date: Tue, 22 Jul 2014 15:41:04 +0100 -Subject: [PATCH 40/55] vcsm: VideoCore shared memory service for BCM2835 +Subject: [PATCH 39/54] vcsm: VideoCore shared memory service for BCM2835 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -97917,10 +96249,10 @@ index 0000000..334f36d 2.5.0 -From c77fed4657dbeea3e515eb467b7a264b9fa303e8 Mon Sep 17 00:00:00 2001 +From ffef0c9f7166a243aae23b1bc094d222e4cfecaf Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Fri, 21 Aug 2015 23:14:48 +0100 -Subject: [PATCH 41/55] Add /dev/gpiomem device for rootless user GPIO access +Subject: [PATCH 40/54] Add /dev/gpiomem device for rootless user GPIO access Signed-off-by: Luke Wren @@ -98234,10 +96566,10 @@ index 0000000..911f5b7 2.5.0 -From da772a0aa1adc142d2eb91dc59713645608e3e54 Mon Sep 17 00:00:00 2001 +From fafb1e07bcbf595a3412748fe1243a38f3393757 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 5 Sep 2015 01:14:45 +0100 -Subject: [PATCH 42/55] Add SMI driver +Subject: [PATCH 41/54] Add SMI driver Signed-off-by: Luke Wren --- @@ -100191,10 +98523,10 @@ index 0000000..ee3a75e 2.5.0 -From f91aaf881fd7b5a1ea2848170100d68e46a2f46a Mon Sep 17 00:00:00 2001 +From a368a4010e0b463a0518eb4dbf1cf8a893727596 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 5 Sep 2015 01:16:10 +0100 -Subject: [PATCH 43/55] Add SMI NAND driver +Subject: [PATCH 42/54] Add SMI NAND driver Signed-off-by: Luke Wren --- @@ -100563,10 +98895,10 @@ index 0000000..b747326 2.5.0 -From 7ddaf7044f603ac7330badd2b9b50723f5268b2d Mon Sep 17 00:00:00 2001 +From 14f0b2203b2204c057d7db441e1a292b6a0eb6f3 Mon Sep 17 00:00:00 2001 From: Aron Szabo Date: Sat, 16 Jun 2012 12:15:55 +0200 -Subject: [PATCH 44/55] lirc: added support for RaspberryPi GPIO +Subject: [PATCH 43/54] lirc: added support for RaspberryPi GPIO lirc_rpi: Use read_current_timer to determine transmitter delay. Thanks to jjmz and others See: https://github.com/raspberrypi/linux/issues/525 @@ -100651,7 +98983,7 @@ index 5430adf..9e53cd0 100644 obj-$(CONFIG_LIRC_SIR) += lirc_sir.o diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c new file mode 100644 -index 0000000..f1e0de9 +index 0000000..cd09c99 --- /dev/null +++ b/drivers/staging/media/lirc/lirc_rpi.c @@ -0,0 +1,730 @@ @@ -101040,7 +99372,7 @@ index 0000000..f1e0de9 + read_bool_property(node, "rpi,debug", &debug); + + } else { -+ return EINVAL; ++ return -EINVAL; + } + + gpiochip->set(gpiochip, gpio_out_pin, invert); @@ -101418,10 +99750,10 @@ index 0000000..fb69624 2.5.0 -From 64be6905577ed38b51e2ec0f0b12ef41d461af3b Mon Sep 17 00:00:00 2001 +From 20fd592d940f46939e89d194f0392c0fe00d1e4f Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:49:20 +0100 -Subject: [PATCH 45/55] Add cpufreq driver +Subject: [PATCH 44/54] Add cpufreq driver Signed-off-by: popcornmix --- @@ -101432,7 +99764,7 @@ Signed-off-by: popcornmix create mode 100644 drivers/cpufreq/bcm2835-cpufreq.c diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm -index 235a1ba..1a732d5 100644 +index b1f8a73..930b3ef 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -217,6 +217,15 @@ config ARM_SPEAR_CPUFREQ @@ -101686,10 +100018,10 @@ index 0000000..3eb9e93 2.5.0 -From def5e89f95d35557a0fe7d954b9da2869de8b4dd Mon Sep 17 00:00:00 2001 +From de097ce1fa4d97e711469c8e5ddc0ab0e4e84943 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 19:24:24 +0000 -Subject: [PATCH 46/55] Added hwmon/thermal driver for reporting core +Subject: [PATCH 45/54] Added hwmon/thermal driver for reporting core temperature. Thanks Dorian MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -101890,10 +100222,10 @@ index 0000000..08d8dc7 2.5.0 -From f3dbc863a57449f5bee914f7a4908cf30ba6acaf Mon Sep 17 00:00:00 2001 +From 3283ff477bed6a5f3d67e405f7df7b456a864567 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 17 Jun 2015 15:44:08 +0100 -Subject: [PATCH 47/55] Add Chris Boot's i2c driver +Subject: [PATCH 46/54] Add Chris Boot's i2c driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -102536,10 +100868,10 @@ index 0000000..85f411c 2.5.0 -From dddab3b10925b29431fc7256e03d4b6946a8da6b Mon Sep 17 00:00:00 2001 +From 7c0ed22b9161086cd3e7c3b7175c8e66538dc058 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 26 Jun 2015 14:27:06 +0200 -Subject: [PATCH 48/55] char: broadcom: Add vcio module +Subject: [PATCH 47/54] char: broadcom: Add vcio module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -102768,10 +101100,10 @@ index 0000000..c19bc20 2.5.0 -From b83c18aa697e6ea37aed43d175db2b8126a7b0d0 Mon Sep 17 00:00:00 2001 +From 386d9ed9fc8601e4919d29d24161ffcffeed4078 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 26 Jun 2015 14:25:01 +0200 -Subject: [PATCH 49/55] firmware: bcm2835: Support ARCH_BCM270x +Subject: [PATCH 48/54] firmware: bcm2835: Support ARCH_BCM270x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -102880,10 +101212,10 @@ index dd506cd3..b980d53 100644 2.5.0 -From db0290d5b59336a845d169170fdeb9eeb8870d6f Mon Sep 17 00:00:00 2001 +From d052c7efe3ebc65ce4c262607028a21a163a755b Mon Sep 17 00:00:00 2001 From: Vincent Sanders Date: Wed, 30 Jan 2013 12:45:18 +0000 -Subject: [PATCH 50/55] bcm2835: add v4l2 camera device +Subject: [PATCH 49/54] bcm2835: add v4l2 camera device - Supports raw YUV capture, preview, JPEG and H264. - Uses videobuf2 for data transfer, using dma_buf. @@ -103158,13 +101490,15 @@ https://github.com/raspberrypi/linux/issues/817 Fixes the kernel warning from videobuf2 as buffers are now returned as they are being flushed on stop_streaming. + +squash: Fixup bcm2835-camera for changes in kernel 4.4 api --- Documentation/video4linux/bcm2835-v4l2.txt | 60 + drivers/media/platform/Kconfig | 2 + drivers/media/platform/Makefile | 2 + drivers/media/platform/bcm2835/Kconfig | 25 + drivers/media/platform/bcm2835/Makefile | 5 + - drivers/media/platform/bcm2835/bcm2835-camera.c | 1843 +++++++++++++++++++++ + drivers/media/platform/bcm2835/bcm2835-camera.c | 1844 +++++++++++++++++++++ drivers/media/platform/bcm2835/bcm2835-camera.h | 126 ++ drivers/media/platform/bcm2835/controls.c | 1324 +++++++++++++++ drivers/media/platform/bcm2835/mmal-common.h | 53 + @@ -103176,7 +101510,7 @@ stop_streaming. drivers/media/platform/bcm2835/mmal-parameters.h | 656 ++++++++ drivers/media/platform/bcm2835/mmal-vchiq.c | 1916 ++++++++++++++++++++++ drivers/media/platform/bcm2835/mmal-vchiq.h | 178 ++ - 17 files changed, 6959 insertions(+) + 17 files changed, 6960 insertions(+) create mode 100644 Documentation/video4linux/bcm2835-v4l2.txt create mode 100644 drivers/media/platform/bcm2835/Kconfig create mode 100644 drivers/media/platform/bcm2835/Makefile @@ -103329,10 +101663,10 @@ index 0000000..f17c79c +ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 diff --git a/drivers/media/platform/bcm2835/bcm2835-camera.c b/drivers/media/platform/bcm2835/bcm2835-camera.c new file mode 100644 -index 0000000..dfd22d4 +index 0000000..e83334c --- /dev/null +++ b/drivers/media/platform/bcm2835/bcm2835-camera.c -@@ -0,0 +1,1843 @@ +@@ -0,0 +1,1844 @@ +/* + * Broadcom BM2835 V4L2 driver + * @@ -103655,7 +101989,7 @@ index 0000000..dfd22d4 + /* error in transfer */ + if (buf != NULL) { + /* there was a buffer with the error so return it */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } + return; + } else if (length == 0) { @@ -103664,7 +101998,7 @@ index 0000000..dfd22d4 + /* this should only ever happen if the port is + * disabled and there are buffers still queued + */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + pr_debug("Empty buffer"); + } else if (dev->capture.frame_count) { + /* grab another frame */ @@ -103694,16 +102028,16 @@ index 0000000..dfd22d4 + + div = + div_u64_rem(runtime_us, USEC_PER_SEC, &rem); -+ buf->vb.v4l2_buf.timestamp.tv_sec = ++ buf->vb.timestamp.tv_sec = + dev->capture.kernel_start_ts.tv_sec - 1 + + div; -+ buf->vb.v4l2_buf.timestamp.tv_usec = ++ buf->vb.timestamp.tv_usec = + dev->capture.kernel_start_ts.tv_usec + rem; + -+ if (buf->vb.v4l2_buf.timestamp.tv_usec >= ++ if (buf->vb.timestamp.tv_usec >= + USEC_PER_SEC) { -+ buf->vb.v4l2_buf.timestamp.tv_sec++; -+ buf->vb.v4l2_buf.timestamp.tv_usec -= ++ buf->vb.timestamp.tv_sec++; ++ buf->vb.timestamp.tv_usec -= + USEC_PER_SEC; + } + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, @@ -103714,15 +102048,15 @@ index 0000000..dfd22d4 + (int)dev->capture.kernel_start_ts. + tv_usec, + dev->capture.vc_start_timestamp, pts, -+ (int)buf->vb.v4l2_buf.timestamp.tv_sec, -+ (int)buf->vb.v4l2_buf.timestamp. ++ (int)buf->vb.timestamp.tv_sec, ++ (int)buf->vb.timestamp. + tv_usec); + } else { -+ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); ++ v4l2_get_timestamp(&buf->vb.timestamp); + } + -+ vb2_set_plane_payload(&buf->vb, 0, length); -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); ++ vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS && + is_capturing(dev)) { @@ -103739,7 +102073,7 @@ index 0000000..dfd22d4 + } + } else { + /* signal frame completion */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + complete(&dev->capture.frame_cmplt); + } + } @@ -103801,14 +102135,15 @@ index 0000000..dfd22d4 +static void buffer_queue(struct vb2_buffer *vb) +{ + struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); -+ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb); ++ struct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb); ++ struct mmal_buffer *buf = container_of(vb2, struct mmal_buffer, vb); + int ret; + + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "%s: dev:%p buf:%p\n", __func__, dev, buf); + -+ buf->buffer = vb2_plane_vaddr(&buf->vb, 0); -+ buf->buffer_size = vb2_plane_size(&buf->vb, 0); ++ buf->buffer = vb2_plane_vaddr(&buf->vb.vb2_buf, 0); ++ buf->buffer_size = vb2_plane_size(&buf->vb.vb2_buf, 0); + + ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf); + if (ret < 0) @@ -106640,7 +104975,7 @@ index 0000000..f9f903f +} diff --git a/drivers/media/platform/bcm2835/mmal-common.h b/drivers/media/platform/bcm2835/mmal-common.h new file mode 100644 -index 0000000..15788a1 +index 0000000..840fd13 --- /dev/null +++ b/drivers/media/platform/bcm2835/mmal-common.h @@ -0,0 +1,53 @@ @@ -106682,7 +105017,7 @@ index 0000000..15788a1 +/* buffer for one video frame */ +struct mmal_buffer { + /* v4l buffer data -- must be first */ -+ struct vb2_buffer vb; ++ struct vb2_v4l2_buffer vb; + + /* list of buffers available */ + struct list_head list; @@ -110268,10 +108603,10 @@ index 0000000..9d1d11e 2.5.0 -From 6d253ddc1d7b7e043db5d664066ded641d7a61d2 Mon Sep 17 00:00:00 2001 +From 88f17ab49dec26cef89f7382763e0aea94e380cd Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 11 May 2015 09:00:42 +0100 -Subject: [PATCH 51/55] scripts: Add mkknlimg and knlinfo scripts from tools +Subject: [PATCH 50/54] scripts: Add mkknlimg and knlinfo scripts from tools repo The Raspberry Pi firmware looks for a trailer on the kernel image to @@ -110739,10 +109074,10 @@ index 0000000..3998d43 2.5.0 -From 8f16e638180c0be62eac73a4e19794fe948efb3e Mon Sep 17 00:00:00 2001 +From 546668ae1382b20c6e80ef49bad762045fc4e1c4 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 5 Dec 2014 17:26:26 +0000 -Subject: [PATCH 52/55] fdt: Add support for the CONFIG_CMDLINE_EXTEND option +Subject: [PATCH 51/54] fdt: Add support for the CONFIG_CMDLINE_EXTEND option --- drivers/of/fdt.c | 29 ++++++++++++++++++++++++----- @@ -110800,10 +109135,10 @@ index 655f79d..0508152 100644 2.5.0 -From 2fb1188922a91873daa63c077531075086d14e8c Mon Sep 17 00:00:00 2001 +From 1a604dcf0461ad1a5422f6618686d7ce5beb0a2f Mon Sep 17 00:00:00 2001 From: notro Date: Wed, 9 Jul 2014 14:46:08 +0200 -Subject: [PATCH 53/55] BCM2708: Add core Device Tree support +Subject: [PATCH 52/54] BCM2708: Add core Device Tree support Add the bare minimum needed to boot BCM2708 from a Device Tree. @@ -110847,20 +109182,41 @@ Add paramter to toggle sdio-device-polling done every second or once at boot-time. Signed-off-by: Patrick Boettcher + +BCM270X_DT: Make mmc overlay compatible with current firmware + +The original DT overlay logic followed a merge-then-patch procedure, +i.e. parameters are applied to the loaded overlay before the overlay +is merged into the base DTB. This sequence has been changed to +patch-then-merge, in order to support parameterised node names, and +to protect against bad overlays. As a result, overrides (parameters) +must only target labels in the overlay, but the overlay can obviously target nodes in the base DTB. + +mmc-overlay.dts (that switches back to the original mmc sdcard +driver) is the only overlay violating that rule, and this patch +fixes it. + +bcm270x_dt: Use the sdhost MMC controller by default + +The "mmc" overlay reverts to using the other controller. + +squash: Add cprman to dt + +BCM270X_DT: Use clk_core for I2C interfaces --- arch/arm/boot/dts/Makefile | 30 + - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 134 +++++ - arch/arm/boot/dts/bcm2708-rpi-b.dts | 124 ++++ - arch/arm/boot/dts/bcm2708-rpi-cm.dts | 98 ++++ - arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 30 + - arch/arm/boot/dts/bcm2708.dtsi | 36 ++ - arch/arm/boot/dts/bcm2708_common.dtsi | 320 ++++++++++ - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 134 +++++ - arch/arm/boot/dts/bcm2709.dtsi | 76 +++ + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 145 +++++ + arch/arm/boot/dts/bcm2708-rpi-b.dts | 135 +++++ + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 102 ++++ + arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 40 ++ + arch/arm/boot/dts/bcm2708.dtsi | 40 ++ + arch/arm/boot/dts/bcm2708_common.dtsi | 347 +++++++++++ + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 145 +++++ + arch/arm/boot/dts/bcm2709.dtsi | 102 ++++ arch/arm/boot/dts/bcm2835-rpi-cm.dts | 93 +++ arch/arm/boot/dts/bcm2835-rpi-cm.dtsi | 30 + arch/arm/boot/dts/overlays/Makefile | 69 +++ - arch/arm/boot/dts/overlays/README | 649 +++++++++++++++++++++ + arch/arm/boot/dts/overlays/README | 648 +++++++++++++++++++++ arch/arm/boot/dts/overlays/ads7846-overlay.dts | 83 +++ .../dts/overlays/bmp085_i2c-sensor-overlay.dts | 23 + arch/arm/boot/dts/overlays/dht11-overlay.dts | 39 ++ @@ -110879,7 +109235,7 @@ Signed-off-by: Patrick Boettcher arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts | 57 ++ .../arm/boot/dts/overlays/mcp2515-can0-overlay.dts | 69 +++ .../arm/boot/dts/overlays/mcp2515-can1-overlay.dts | 69 +++ - arch/arm/boot/dts/overlays/mmc-overlay.dts | 19 + + arch/arm/boot/dts/overlays/mmc-overlay.dts | 39 ++ arch/arm/boot/dts/overlays/mz61581-overlay.dts | 111 ++++ arch/arm/boot/dts/overlays/piscreen-overlay.dts | 96 +++ .../dts/overlays/pitft28-resistive-overlay.dts | 115 ++++ @@ -110892,8 +109248,8 @@ Signed-off-by: Patrick Boettcher arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts | 17 + arch/arm/boot/dts/overlays/rpi-proto-overlay.dts | 39 ++ arch/arm/boot/dts/overlays/rpi-sense-overlay.dts | 47 ++ - arch/arm/boot/dts/overlays/sdhost-overlay.dts | 56 ++ - arch/arm/boot/dts/overlays/sdio-overlay.dts | 33 ++ + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 29 + + arch/arm/boot/dts/overlays/sdio-overlay.dts | 32 + arch/arm/boot/dts/overlays/smi-dev-overlay.dts | 18 + arch/arm/boot/dts/overlays/smi-nand-overlay.dts | 69 +++ arch/arm/boot/dts/overlays/smi-overlay.dts | 37 ++ @@ -110903,7 +109259,7 @@ Signed-off-by: Patrick Boettcher arch/arm/boot/dts/overlays/vga666-overlay.dts | 30 + arch/arm/boot/dts/overlays/w1-gpio-overlay.dts | 39 ++ .../boot/dts/overlays/w1-gpio-pullup-overlay.dts | 41 ++ - 55 files changed, 4108 insertions(+) + 55 files changed, 4203 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-plus.dts create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b.dts create mode 100755 arch/arm/boot/dts/bcm2708-rpi-cm.dts @@ -111012,13 +109368,13 @@ index 30bbc37..d583e67 100644 +endif diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts new file mode 100644 -index 0000000..ffb7596 +index 0000000..2e4df17 --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -0,0 +1,134 @@ +@@ -0,0 +1,145 @@ +/dts-v1/; + -+/include/ "bcm2708.dtsi" ++#include "bcm2708.dtsi" + +/ { + compatible = "brcm,bcm2708"; @@ -111026,6 +109382,11 @@ index 0000000..ffb7596 +}; + +&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -111052,9 +109413,11 @@ index 0000000..ffb7596 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ status = "okay"; +}; + +&fb { @@ -111109,6 +109472,10 @@ index 0000000..ffb7596 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +&leds { + act_led: act { + label = "led0"; @@ -111152,13 +109519,13 @@ index 0000000..ffb7596 +}; diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts new file mode 100644 -index 0000000..8551159 +index 0000000..0445b46 --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -0,0 +1,124 @@ +@@ -0,0 +1,135 @@ +/dts-v1/; + -+/include/ "bcm2708.dtsi" ++#include "bcm2708.dtsi" + +/ { + compatible = "brcm,bcm2708"; @@ -111166,6 +109533,11 @@ index 0000000..8551159 +}; + +&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -111192,9 +109564,11 @@ index 0000000..8551159 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ status = "okay"; +}; + +&fb { @@ -111249,6 +109623,10 @@ index 0000000..8551159 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +&leds { + act_led: act { + label = "led0"; @@ -111282,13 +109660,13 @@ index 0000000..8551159 +}; diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts new file mode 100755 -index 0000000..1f7ec88 +index 0000000..87c1a54 --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -@@ -0,0 +1,98 @@ +@@ -0,0 +1,102 @@ +/dts-v1/; + -+/include/ "bcm2708-rpi-cm.dtsi" ++#include "bcm2708-rpi-cm.dtsi" + +/ { + model = "Raspberry Pi Compute Module"; @@ -111369,6 +109747,10 @@ index 0000000..1f7ec88 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +/ { + __overrides__ { + uart0 = <&uart0>,"status"; @@ -111386,11 +109768,18 @@ index 0000000..1f7ec88 +}; diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi new file mode 100644 -index 0000000..713e5a2 +index 0000000..3c8bdde --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -@@ -0,0 +1,30 @@ -+/include/ "bcm2708.dtsi" +@@ -0,0 +1,40 @@ ++#include "bcm2708.dtsi" ++ ++&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; + +&leds { + act_led: act { @@ -111400,9 +109789,12 @@ index 0000000..713e5a2 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ non-removable; ++ status = "okay"; +}; + +&fb { @@ -111422,11 +109814,11 @@ index 0000000..713e5a2 +}; diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi new file mode 100644 -index 0000000..0bea715 +index 0000000..f5a44cd --- /dev/null +++ b/arch/arm/boot/dts/bcm2708.dtsi -@@ -0,0 +1,36 @@ -+/include/ "bcm2708_common.dtsi" +@@ -0,0 +1,40 @@ ++#include "bcm2708_common.dtsi" + +/ { + compatible = "brcm,bcm2708"; @@ -111462,13 +109854,17 @@ index 0000000..0bea715 +&intc { + compatible = "brcm,bcm2835-armctrl-ic"; +}; ++ ++&watchdog { ++ status = "okay"; ++}; diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi new file mode 100644 -index 0000000..c658c7b +index 0000000..75fb4ce --- /dev/null +++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -0,0 +1,320 @@ -+/include/ "skeleton.dtsi" +@@ -0,0 +1,347 @@ ++#include "skeleton.dtsi" + +/ { + interrupt-parent = <&intc>; @@ -111484,6 +109880,7 @@ index 0000000..c658c7b + mailbox = &mailbox; + gpio = &gpio; + uart0 = &uart0; ++ sdhost = &sdhost; + i2s = &i2s; + spi0 = &spi0; + i2c0 = &i2c0; @@ -111555,6 +109952,18 @@ index 0000000..c658c7b + status = "disabled"; + }; + ++ cprman: cprman@7e101000 { ++ compatible = "brcm,bcm2835-cprman"; ++ #clock-cells = <1>; ++ reg = <0x7e101000 0x2000>; ++ ++ /* CPRMAN derives everything from the platform's ++ * oscillator. ++ */ ++ clocks = <&clk_osc>; ++ status = "disabled"; ++ }; ++ + random: rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; @@ -111584,6 +109993,18 @@ index 0000000..c658c7b + status = "disabled"; + }; + ++ sdhost: sdhost@7e202000 { ++ compatible = "brcm,bcm2835-sdhost"; ++ reg = <0x7e202000 0x100>; ++ interrupts = <2 24>; ++ clocks = <&clk_core>; ++ dmas = <&dma 13>, ++ <&dma 13>; ++ dma-names = "tx", "rx"; ++ brcm,pio-limit = <1>; ++ status = "disabled"; ++ }; ++ + i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = <0x7e203000 0x24>, @@ -111616,7 +110037,7 @@ index 0000000..c658c7b + compatible = "brcm,bcm2708-i2c"; + reg = <0x7e205000 0x1000>; + interrupts = <2 21>; -+ clocks = <&clk_i2c>; ++ clocks = <&clk_core>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; @@ -111655,7 +110076,7 @@ index 0000000..c658c7b + compatible = "brcm,bcm2708-i2c"; + reg = <0x7e804000 0x1000>; + interrupts = <2 21>; -+ clocks = <&clk_i2c>; ++ clocks = <&clk_core>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; @@ -111668,7 +110089,7 @@ index 0000000..c658c7b + compatible = "brcm,bcm2708-i2c"; + reg = <0x7e805000 0x1000>; + interrupts = <2 21>; -+ clocks = <&clk_i2c>; ++ clocks = <&clk_core>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; @@ -111727,61 +110148,63 @@ index 0000000..c658c7b + #address-cells = <1>; + #size-cells = <0>; + -+ clk_mmc: clock@0 { ++ clk_core: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; -+ clock-output-names = "mmc"; -+ clock-frequency = <250000000>; -+ }; -+ -+ clk_i2c: clock@1 { -+ compatible = "fixed-clock"; -+ reg = <1>; -+ #clock-cells = <0>; -+ clock-output-names = "i2c"; -+ clock-frequency = <250000000>; -+ }; -+ -+ clk_core: clock@2 { -+ compatible = "fixed-clock"; -+ reg = <2>; -+ #clock-cells = <0>; + clock-output-names = "core"; + clock-frequency = <250000000>; + }; + -+ clk_uart0: clock@3 { ++ clk_mmc: clock@1 { + compatible = "fixed-clock"; -+ reg = <3>; ++ reg = <1>; ++ #clock-cells = <0>; ++ clock-output-names = "mmc"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_uart0: clock@2 { ++ compatible = "fixed-clock"; ++ reg = <2>; + #clock-cells = <0>; + clock-output-names = "uart0_pclk"; + clock-frequency = <3000000>; + }; + -+ clk_apb_p: clock@4 { ++ clk_apb_p: clock@3 { + compatible = "fixed-clock"; -+ reg = <4>; ++ reg = <3>; + #clock-cells = <0>; + clock-output-names = "apb_pclk"; + clock-frequency = <126000000>; + }; + -+ clk_pwm: clock@5 { -+ compatible = "fixed-clock"; -+ reg = <3>; -+ #clock-cells = <0>; -+ clock-output-names = "pwm"; -+ clock-frequency = <100000000>; ++ clk_pwm: clock@4 { ++ compatible = "fixed-clock"; ++ reg = <4>; ++ #clock-cells = <0>; ++ clock-output-names = "pwm"; ++ clock-frequency = <100000000>; + }; + -+ clk_uart1: clock@6 { ++ clk_uart1: clock@5 { + compatible = "fixed-factor-clock"; ++ reg = <5>; + clocks = <&clk_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + }; ++ ++ /* The oscillator is the root of the clock tree. */ ++ clk_osc: clock@6 { ++ compatible = "fixed-clock"; ++ reg = <6>; ++ #clock-cells = <0>; ++ clock-output-names = "osc"; ++ clock-frequency = <19200000>; ++ }; + }; + + __overrides__ { @@ -111790,13 +110213,13 @@ index 0000000..c658c7b +}; diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts new file mode 100644 -index 0000000..7a05dab5 +index 0000000..5206ba2 --- /dev/null +++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -0,0 +1,134 @@ +@@ -0,0 +1,145 @@ +/dts-v1/; + -+/include/ "bcm2709.dtsi" ++#include "bcm2709.dtsi" + +/ { + compatible = "brcm,bcm2709"; @@ -111804,6 +110227,11 @@ index 0000000..7a05dab5 +}; + +&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -111830,9 +110258,11 @@ index 0000000..7a05dab5 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ status = "okay"; +}; + +&fb { @@ -111887,6 +110317,10 @@ index 0000000..7a05dab5 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +&leds { + act_led: act { + label = "led0"; @@ -111930,11 +110364,11 @@ index 0000000..7a05dab5 +}; diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi new file mode 100644 -index 0000000..811d825 +index 0000000..a8cfd7c --- /dev/null +++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -0,0 +1,76 @@ -+/include/ "bcm2708_common.dtsi" +@@ -0,0 +1,102 @@ ++#include "bcm2708_common.dtsi" + +/ { + compatible = "brcm,bcm2709"; @@ -111946,11 +110380,21 @@ index 0000000..811d825 + }; + + soc { -+ ranges = <0x7e000000 0x3f000000 0x01000000>; ++ ranges = <0x7e000000 0x3f000000 0x01000000>, ++ <0x40000000 0x40000000 0x00040000>; ++ ++ local_intc: local_intc { ++ compatible = "brcm,bcm2836-l1-intc"; ++ reg = <0x40000000 0x100>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&local_intc>; ++ }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; -+ interrupts = <3 9>; ++ interrupt-parent = <&local_intc>; ++ interrupts = <9>; + }; + + gpiomem { @@ -111958,16 +110402,22 @@ index 0000000..811d825 + reg = <0x7e200000 0x1000>; + status = "okay"; + }; -+ }; + -+ timer { -+ compatible = "arm,armv7-timer"; -+ clock-frequency = <19200000>; -+ interrupts = <3 0>, // PHYS_SECURE_PPI -+ <3 1>, // PHYS_NONSECURE_PPI -+ <3 3>, // VIRT_PPI -+ <3 2>; // HYP_PPI -+ always-on; ++ timer { ++ compatible = "arm,armv7-timer"; ++ clock-frequency = <19200000>; ++ interrupt-parent = <&local_intc>; ++ interrupts = <0>, // PHYS_SECURE_PPI ++ <1>, // PHYS_NONSECURE_PPI ++ <3>, // VIRT_PPI ++ <2>; // HYP_PPI ++ always-on; ++ }; ++ ++ syscon@40000000 { ++ compatible = "brcm,bcm2836-arm-local", "syscon"; ++ reg = <0x40000000 0x100>; ++ }; + }; + + cpus: cpus { @@ -112010,6 +110460,16 @@ index 0000000..811d825 + <&v7_cpu3>, "clock-frequency:0"; + }; +}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++&intc { ++ compatible = "brcm,bcm2836-armctrl-ic"; ++ interrupt-parent = <&local_intc>; ++ interrupts = <8>; ++}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm.dts b/arch/arm/boot/dts/bcm2835-rpi-cm.dts new file mode 100644 index 0000000..c6e6860 @@ -112222,10 +110682,10 @@ index 0000000..d8c2771 +endif diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README new file mode 100644 -index 0000000..d8d0a51 +index 0000000..44e33a4 --- /dev/null +++ b/arch/arm/boot/dts/overlays/README -@@ -0,0 +1,649 @@ +@@ -0,0 +1,648 @@ +Introduction +============ + @@ -112426,7 +110886,7 @@ index 0000000..d8d0a51 + +Name: gpio-poweroff +Info: Drives a GPIO high or low on reboot -+Load: gpio-poweroff,= ++Load: dtoverlay=gpio-poweroff,= +Params: gpiopin GPIO for signalling (default 26) + + active_low Set if the power control device requires a @@ -112657,7 +111117,6 @@ index 0000000..d8d0a51 + 3) So be careful mixing audio and PWM. + 4) Currently the clock must have been enabled and configured + by other means. -+Load: dtoverlay=pwm-2chan,= +Load: dtoverlay=pwm,= +Params: pin Output pin (default 18) - see table + func Pin function (default 2 = Alt5) - see above @@ -112845,7 +111304,7 @@ index 0000000..d8d0a51 +Name: w1-gpio-pullup +Info: Configures the w1-gpio Onewire interface module. + Use this overlay if you *do* need a GPIO to drive an external pullup. -+Load: dtoverlay=w1-gpio-pullup,=,... ++Load: dtoverlay=w1-gpio-pullup,= +Params: gpiopin GPIO for I/O (default "4") + + pullup Non-zero, "on", or "y" to enable the parasitic @@ -113935,10 +112394,10 @@ index 0000000..6bef9ae +}; diff --git a/arch/arm/boot/dts/overlays/mmc-overlay.dts b/arch/arm/boot/dts/overlays/mmc-overlay.dts new file mode 100644 -index 0000000..0a37cf4 +index 0000000..00a22be --- /dev/null +++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts -@@ -0,0 +1,19 @@ +@@ -0,0 +1,39 @@ +/dts-v1/; +/plugin/; + @@ -113947,15 +112406,35 @@ index 0000000..0a37cf4 + + fragment@0 { + target = <&mmc>; -+ -+ __overlay__ { ++ frag0: __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc_pins>; ++ bus-width = <4>; + brcm,overclock-50 = <0>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ mmc_pins: mmc_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <7>; /* alt3 */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sdhost>; ++ __overlay__ { ++ status = "disabled"; + }; + }; + + __overrides__ { -+ overclock_50 = <&mmc>,"brcm,overclock-50:0"; -+ force_pio = <&mmc>,"brcm,force-pio?"; ++ overclock_50 = <&frag0>,"brcm,overclock-50:0"; ++ force_pio = <&frag0>,"brcm,force-pio?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/mz61581-overlay.dts b/arch/arm/boot/dts/overlays/mz61581-overlay.dts @@ -114740,10 +113219,10 @@ index 0000000..2715324 +}; diff --git a/arch/arm/boot/dts/overlays/sdhost-overlay.dts b/arch/arm/boot/dts/overlays/sdhost-overlay.dts new file mode 100644 -index 0000000..2da14a4 +index 0000000..85f0725 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts -@@ -0,0 +1,56 @@ +@@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + @@ -114751,61 +113230,34 @@ index 0000000..2da14a4 + compatible = "brcm,bcm2708"; + + fragment@0 { -+ target = <&soc>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ sdhost: sdhost@7e202000 { -+ compatible = "brcm,bcm2835-sdhost"; -+ reg = <0x7e202000 0x100>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; -+ interrupts = <2 24>; -+ clocks = <&clk_core>; -+ dmas = <&dma 13>, -+ <&dma 13>; -+ dma-names = "tx", "rx"; -+ brcm,delay-after-stop = <0>; -+ brcm,overclock-50 = <0>; -+ brcm,pio-limit = <1>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { + target = <&mmc>; + __overlay__ { -+ /* Find a way to disable the other driver */ -+ compatible = ""; + status = "disabled"; + }; + }; + ++ fragment@1 { ++ target = <&sdhost>; ++ frag1: __overlay__ { ++ brcm,overclock-50 = <0>; ++ brcm,pio-limit = <1>; ++ status = "okay"; ++ }; ++ }; ++ + __overrides__ { -+ overclock_50 = <&sdhost>,"brcm,overclock-50:0"; -+ force_pio = <&sdhost>,"brcm,force-pio?"; -+ pio_limit = <&sdhost>,"brcm,pio-limit:0"; -+ debug = <&sdhost>,"brcm,debug?"; ++ overclock_50 = <&frag1>,"brcm,overclock-50:0"; ++ force_pio = <&frag1>,"brcm,force-pio?"; ++ pio_limit = <&frag1>,"brcm,pio-limit:0"; ++ debug = <&frag1>,"brcm,debug?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/sdio-overlay.dts b/arch/arm/boot/dts/overlays/sdio-overlay.dts new file mode 100644 -index 0000000..6626a1d +index 0000000..afc8742 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts -@@ -0,0 +1,33 @@ +@@ -0,0 +1,32 @@ +/* Enable SDIO from MMC interface via GPIOs 22-27. Includes sdhost overlay. */ + +/include/ "sdhost-overlay.dts" @@ -114816,7 +113268,6 @@ index 0000000..6626a1d + fragment@3 { + target = <&mmc>; + sdio_mmc: __overlay__ { -+ compatible = "brcm,bcm2835-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + non-removable; @@ -115416,10 +113867,10 @@ index 0000000..66a98f6 2.5.0 -From f97dbcf6b4ab8737d9e4d4efa48f0e79509e21f8 Mon Sep 17 00:00:00 2001 +From a9f4427a230b1ca6e77418330a42042e2b703a10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 15 Aug 2015 20:47:07 +0200 -Subject: [PATCH 54/55] bcm2835: Match with BCM2708 Device Trees +Subject: [PATCH 53/54] bcm2835: Match with BCM2708 Device Trees MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -115940,10 +114391,10 @@ index 864a3ef..3256bff 100644 2.5.0 -From 9f02b79c2efc7bf9a8cf4d9089889ee81e84f8fa Mon Sep 17 00:00:00 2001 +From 88ef042c414856132deba83d6ff8e9001c71e8d3 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 13:32:11 +0300 -Subject: [PATCH 55/55] fbdev: add FBIOCOPYAREA ioctl +Subject: [PATCH 54/54] fbdev: add FBIOCOPYAREA ioctl Based on the patch authored by Ali Gholami Rudi at https://lkml.org/lkml/2009/7/13/153 @@ -116038,7 +114489,7 @@ index fb795c3..fa72af0 100644 -- 2.5.0 -From 5087895d0f6f5a16799e33cdbf9a07a55fad82ea Mon Sep 17 00:00:00 2001 +From 3dd0886d76a33878bfdc67c44f29c9a782f88419 Mon Sep 17 00:00:00 2001 From: Harm Hanemaaijer Date: Thu, 20 Jun 2013 20:21:39 +0200 Subject: [PATCH 1/3] Speed up console framebuffer imageblit function @@ -116253,7 +114704,7 @@ index a2bb276..436494f 100644 2.5.0 -From 4c3c6b446a5992fe2539b559b2f30326bf03cf0c Mon Sep 17 00:00:00 2001 +From 4641cd894690a65893287ce27e9b98a0e554ac1a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 17:26:38 +0000 Subject: [PATCH 2/3] Allow mac address to be set in smsc95xx @@ -116350,7 +114801,7 @@ index 9c0da18..3244a90 100755 2.5.0 -From 20363421dacd9f1e1b9ece34dbdede11caba840b Mon Sep 17 00:00:00 2001 +From 4252d61d6bf3c32b2042de2a0633472e65044bcd Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 8 May 2013 11:46:50 +0100 Subject: [PATCH 3/3] enabling the realtime clock 1-wire chip DS1307 and 1-wire @@ -116605,10 +115056,10 @@ index d58594a..feae942 100644 -- 2.5.0 -From 053fc9ba3e6487c18f88b841aac676cf8c91e040 Mon Sep 17 00:00:00 2001 +From 0d2c4c9480b96a2c0a92044f11d59e1893bd5d61 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Dec 2013 22:16:19 +0000 -Subject: [PATCH 01/78] config: Enable CONFIG_MEMCG, but leave it disabled (due +Subject: [PATCH 01/59] config: Enable CONFIG_MEMCG, but leave it disabled (due to memory cost). Enable with cgroup_enable=memory. --- @@ -116660,10 +115111,10 @@ index 470f653..5ecf873 100644 2.5.0 -From b481eddbf479c66f7e2495f07d085e3613c19ea4 Mon Sep 17 00:00:00 2001 +From b29192a8be711b20a5bd623b363a9672df79d762 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:59:51 +0100 -Subject: [PATCH 02/78] ASoC: Add support for PCM5102A codec +Subject: [PATCH 02/59] ASoC: Add support for PCM5102A codec Some definitions to support the PCM5102A codec by Texas Instruments. @@ -116672,8 +115123,8 @@ Signed-off-by: Florian Meier --- sound/soc/codecs/Kconfig | 5 ++++ sound/soc/codecs/Makefile | 2 ++ - sound/soc/codecs/pcm5102a.c | 63 +++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 70 insertions(+) + sound/soc/codecs/pcm5102a.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 77 insertions(+) create mode 100644 sound/soc/codecs/pcm5102a.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig @@ -116721,10 +115172,10 @@ index f632fc4..7ba76ba 100644 obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o diff --git a/sound/soc/codecs/pcm5102a.c b/sound/soc/codecs/pcm5102a.c new file mode 100644 -index 0000000..126f1e9 +index 0000000..7c6598e --- /dev/null +++ b/sound/soc/codecs/pcm5102a.c -@@ -0,0 +1,63 @@ +@@ -0,0 +1,70 @@ +/* + * Driver for the PCM5102A codec + * @@ -116774,12 +115225,19 @@ index 0000000..126f1e9 + return 0; +} + ++static const struct of_device_id pcm5102a_of_match[] = { ++ { .compatible = "ti,pcm5102a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm5102a_of_match); ++ +static struct platform_driver pcm5102a_codec_driver = { + .probe = pcm5102a_probe, + .remove = pcm5102a_remove, + .driver = { + .name = "pcm5102a-codec", + .owner = THIS_MODULE, ++ .of_match_table = pcm5102a_of_match, + }, +}; + @@ -116792,10 +115250,10 @@ index 0000000..126f1e9 2.5.0 -From a99de03888802e57a3a8d5eee20eb43e6a37a189 Mon Sep 17 00:00:00 2001 +From 0dedabda0e45bd54adeb39ee435367e4429dfbb6 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:19:08 +0100 -Subject: [PATCH 03/78] ASoC: Add support for HifiBerry DAC +Subject: [PATCH 03/59] ASoC: Add support for HifiBerry DAC This adds a machine driver for the HifiBerry DAC. It is a sound card that can @@ -116805,8 +115263,8 @@ Signed-off-by: Florian Meier --- sound/soc/bcm/Kconfig | 7 +++ sound/soc/bcm/Makefile | 4 ++ - sound/soc/bcm/hifiberry_dac.c | 100 ++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 111 insertions(+) + sound/soc/bcm/hifiberry_dac.c | 122 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 133 insertions(+) create mode 100644 sound/soc/bcm/hifiberry_dac.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -116838,10 +115296,10 @@ index bc816b7..b877d38 100644 +obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o diff --git a/sound/soc/bcm/hifiberry_dac.c b/sound/soc/bcm/hifiberry_dac.c new file mode 100644 -index 0000000..4b70b45 +index 0000000..3ab0f47 --- /dev/null +++ b/sound/soc/bcm/hifiberry_dac.c -@@ -0,0 +1,100 @@ +@@ -0,0 +1,122 @@ +/* + * ASoC Driver for HifiBerry DAC + * @@ -116916,6 +115374,21 @@ index 0000000..4b70b45 + int ret = 0; + + snd_rpi_hifiberry_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); @@ -116928,10 +115401,17 @@ index 0000000..4b70b45 + return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); +} + ++static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match); ++ +static struct platform_driver snd_rpi_hifiberry_dac_driver = { + .driver = { + .name = "snd-hifiberry-dac", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dac_of_match, + }, + .probe = snd_rpi_hifiberry_dac_probe, + .remove = snd_rpi_hifiberry_dac_remove, @@ -116946,23 +115426,19 @@ index 0000000..4b70b45 2.5.0 -From 877f63f457781141c66be1b0f0de39b453aa03fa Mon Sep 17 00:00:00 2001 +From e44fe13cdf2e0857f445870d895a1c8c6b6741e3 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:21:34 +0100 -Subject: [PATCH 04/78] BCM2708: Add HifiBerry DAC to board file +Subject: [PATCH 04/59] ASoC: Add support for Rpi-DAC -This adds the initalization of the HifiBerry DAC -to the mach-bcm2708 board file. - -Signed-off-by: Florian Meier --- - sound/soc/bcm/Kconfig | 7 ++++ - sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/rpi-dac.c | 97 +++++++++++++++++++++++++++++++++++++++++++++ - sound/soc/codecs/Kconfig | 9 +++++ - sound/soc/codecs/Makefile | 2 + - sound/soc/codecs/pcm1794a.c | 62 +++++++++++++++++++++++++++++ - 6 files changed, 179 insertions(+) + sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/rpi-dac.c | 118 ++++++++++++++++++++++++++++++++++++++++++++ + sound/soc/codecs/Kconfig | 9 ++++ + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/pcm1794a.c | 69 ++++++++++++++++++++++++++ + 6 files changed, 207 insertions(+) create mode 100644 sound/soc/bcm/rpi-dac.c create mode 100644 sound/soc/codecs/pcm1794a.c @@ -116995,10 +115471,10 @@ index b877d38..99c96b4 100644 +obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o diff --git a/sound/soc/bcm/rpi-dac.c b/sound/soc/bcm/rpi-dac.c new file mode 100644 -index 0000000..6d6e0ba +index 0000000..d5fac1b --- /dev/null +++ b/sound/soc/bcm/rpi-dac.c -@@ -0,0 +1,97 @@ +@@ -0,0 +1,118 @@ +/* + * ASoC Driver for RPi-DAC. + * @@ -117070,6 +115546,20 @@ index 0000000..6d6e0ba + int ret = 0; + + snd_rpi_rpi_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_rpi_dac); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); @@ -117082,10 +115572,17 @@ index 0000000..6d6e0ba + return snd_soc_unregister_card(&snd_rpi_rpi_dac); +} + ++static const struct of_device_id snd_rpi_rpi_dac_of_match[] = { ++ { .compatible = "rpi,rpi-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match); ++ +static struct platform_driver snd_rpi_rpi_dac_driver = { + .driver = { + .name = "snd-rpi-dac", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_rpi_dac_of_match, + }, + .probe = snd_rpi_rpi_dac_probe, + .remove = snd_rpi_rpi_dac_remove, @@ -117145,10 +115642,10 @@ index 7ba76ba..2147436 100644 obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o diff --git a/sound/soc/codecs/pcm1794a.c b/sound/soc/codecs/pcm1794a.c new file mode 100644 -index 0000000..b4eaa44 +index 0000000..afe1b41 --- /dev/null +++ b/sound/soc/codecs/pcm1794a.c -@@ -0,0 +1,62 @@ +@@ -0,0 +1,69 @@ +/* + * Driver for the PCM1794A codec + * @@ -117197,12 +115694,19 @@ index 0000000..b4eaa44 + return 0; +} + ++static const struct of_device_id pcm1794a_of_match[] = { ++ { .compatible = "ti,pcm1794a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm1794a_of_match); ++ +static struct platform_driver pcm1794a_codec_driver = { + .probe = pcm1794a_probe, + .remove = pcm1794a_remove, + .driver = { + .name = "pcm1794a-codec", + .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(pcm1794a_of_match), + }, +}; + @@ -117215,10 +115719,10 @@ index 0000000..b4eaa44 2.5.0 -From 0d42746ebabdad8dec20c022e3202cb5e9650ed1 Mon Sep 17 00:00:00 2001 +From 5eef515f93059e16a1644ad37a17a624e3038425 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:41:23 +0100 -Subject: [PATCH 05/78] ASoC: wm8804: Implement MCLK configuration options, add +Subject: [PATCH 05/59] ASoC: wm8804: Implement MCLK configuration options, add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an @@ -117261,10 +115765,10 @@ index 8d91470..5795fb1 100644 2.5.0 -From 6d46e3d23c8e73184990e0e0fe235bcea4e4b929 Mon Sep 17 00:00:00 2001 +From e73dd7a2fba7ab58c64aa30b785c56d6ee9c213f Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:42:08 +0100 -Subject: [PATCH 06/78] ASoC: BCM:Add support for HiFiBerry Digi. Driver is +Subject: [PATCH 06/59] ASoC: BCM:Add support for HiFiBerry Digi. Driver is based on the patched WM8804 driver. Signed-off-by: Daniel Matuschek @@ -117285,8 +115789,8 @@ adds the sample rate bits in the SPDIF status block. --- sound/soc/bcm/Kconfig | 7 ++ sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/hifiberry_digi.c | 201 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 210 insertions(+) + sound/soc/bcm/hifiberry_digi.c | 223 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 232 insertions(+) create mode 100644 sound/soc/bcm/hifiberry_digi.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -117323,10 +115827,10 @@ index 99c96b4..4d53c58 100644 obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o diff --git a/sound/soc/bcm/hifiberry_digi.c b/sound/soc/bcm/hifiberry_digi.c new file mode 100644 -index 0000000..92e9e46 +index 0000000..80732b8 --- /dev/null +++ b/sound/soc/bcm/hifiberry_digi.c -@@ -0,0 +1,201 @@ +@@ -0,0 +1,223 @@ +/* + * ASoC Driver for HifiBerry Digi + * @@ -117502,6 +116006,21 @@ index 0000000..92e9e46 + int ret = 0; + + snd_rpi_hifiberry_digi.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); @@ -117514,10 +116033,17 @@ index 0000000..92e9e46 + return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); +} + ++static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-digi", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match); ++ +static struct platform_driver snd_rpi_hifiberry_digi_driver = { + .driver = { + .name = "snd-hifiberry-digi", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_digi_of_match, + }, + .probe = snd_rpi_hifiberry_digi_probe, + .remove = snd_rpi_hifiberry_digi_remove, @@ -117532,10 +116058,10 @@ index 0000000..92e9e46 2.5.0 -From ace137d7705a7f57ecaa51d7a12abebe387db63f Mon Sep 17 00:00:00 2001 +From 73edf3a97c839ddf6684271f5485d7c147b80f92 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:36:35 +0100 -Subject: [PATCH 07/78] ASoC: wm8804: Set idle_bias_off to false Idle bias has +Subject: [PATCH 07/59] ASoC: wm8804: Set idle_bias_off to false Idle bias has been change to remove warning on driver startup Signed-off-by: Daniel Matuschek @@ -117560,10 +116086,10 @@ index 5795fb1..c846716 100644 2.5.0 -From d80f0d503eb0aa5afedc80d385d7844ba8ecedf1 Mon Sep 17 00:00:00 2001 +From 1f1e820c63d8385fed2ae1df075a747702756d44 Mon Sep 17 00:00:00 2001 From: Gordon Garrity Date: Sat, 8 Mar 2014 16:56:57 +0000 -Subject: [PATCH 08/78] Add IQaudIO Sound Card support for Raspberry Pi +Subject: [PATCH 08/59] Add IQaudIO Sound Card support for Raspberry Pi Set a limit of 0dB on Digital Volume Control @@ -117574,8 +116100,8 @@ limit of 0dB for this control. --- sound/soc/bcm/Kconfig | 7 +++ sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/iqaudio-dac.c | 117 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 126 insertions(+) + sound/soc/bcm/iqaudio-dac.c | 132 ++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 141 insertions(+) create mode 100644 sound/soc/bcm/iqaudio-dac.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -117609,10 +116135,10 @@ index 4d53c58..08e4dc5 100644 +obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o diff --git a/sound/soc/bcm/iqaudio-dac.c b/sound/soc/bcm/iqaudio-dac.c new file mode 100644 -index 0000000..aff7377 +index 0000000..37038d4 --- /dev/null +++ b/sound/soc/bcm/iqaudio-dac.c -@@ -0,0 +1,117 @@ +@@ -0,0 +1,132 @@ +/* + * ASoC Driver for IQaudIO DAC + * @@ -117642,9 +116168,8 @@ index 0000000..aff7377 +{ + int ret; + struct snd_soc_card *card = rtd->card; -+ struct snd_soc_codec *codec = rtd->codec; + -+ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207); + if (ret < 0) + dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); + @@ -117697,6 +116222,21 @@ index 0000000..aff7377 + int ret = 0; + + snd_rpi_iqaudio_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); + if (ret) + dev_err(&pdev->dev, @@ -117714,6 +116254,7 @@ index 0000000..aff7377 + { .compatible = "iqaudio,iqaudio-dac", }, + {}, +}; ++MODULE_DEVICE_TABLE(of, iqaudio_of_match); + +static struct platform_driver snd_rpi_iqaudio_dac_driver = { + .driver = { @@ -117734,10 +116275,10 @@ index 0000000..aff7377 2.5.0 -From bcfba46c727f742f83c1cbb43053a26cb2894229 Mon Sep 17 00:00:00 2001 +From 26b545d1b78dba5e4a88b3ad38d129b5217c526a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 14 Jul 2014 22:02:09 +0100 -Subject: [PATCH 09/78] hid: Reduce default mouse polling interval to 60Hz +Subject: [PATCH 09/59] hid: Reduce default mouse polling interval to 60Hz Reduces overhead when using X --- @@ -117776,18 +116317,18 @@ index 36712e9..910fa89 100644 2.5.0 -From 8c0ea6c00fd0b31391e4fc079356ce3d0c065142 Mon Sep 17 00:00:00 2001 +From d00a6d6ab0ad83338de8360fb0c895dc3b780caa Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Mon, 4 Aug 2014 10:06:56 +0200 -Subject: [PATCH 10/78] Added support for HiFiBerry DAC+ +Subject: [PATCH 10/59] Added support for HiFiBerry DAC+ The driver is based on the HiFiBerry DAC driver. However HiFiBerry DAC+ uses a different codec chip (PCM5122), therefore a new driver is necessary. --- - sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Kconfig | 7 ++ sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/hifiberry_dacplus.c | 119 ++++++++++++++++++++++++++++++++++++++ - 3 files changed, 128 insertions(+) + sound/soc/bcm/hifiberry_dacplus.c | 141 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 150 insertions(+) create mode 100644 sound/soc/bcm/hifiberry_dacplus.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -117828,10 +116369,10 @@ index 08e4dc5..a29538e 100644 obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o diff --git a/sound/soc/bcm/hifiberry_dacplus.c b/sound/soc/bcm/hifiberry_dacplus.c new file mode 100644 -index 0000000..c63387b +index 0000000..11e4f39 --- /dev/null +++ b/sound/soc/bcm/hifiberry_dacplus.c -@@ -0,0 +1,119 @@ +@@ -0,0 +1,141 @@ +/* + * ASoC Driver for HiFiBerry DAC+ + * @@ -117924,6 +116465,21 @@ index 0000000..c63387b + int ret = 0; + + snd_rpi_hifiberry_dacplus.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); + if (ret) + dev_err(&pdev->dev, @@ -117937,10 +116493,17 @@ index 0000000..c63387b + return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); +} + ++static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dacplus", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match); ++ +static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { + .driver = { + .name = "snd-rpi-hifiberry-dacplus", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dacplus_of_match, + }, + .probe = snd_rpi_hifiberry_dacplus_probe, + .remove = snd_rpi_hifiberry_dacplus_remove, @@ -117955,10 +116518,10 @@ index 0000000..c63387b 2.5.0 -From 579b01fb88a32b5e29559f558dc374012c8e7b20 Mon Sep 17 00:00:00 2001 +From e1a0219eddb9732580155b2cb1f8d0e24421b9c3 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Mon, 4 Aug 2014 11:09:58 +0200 -Subject: [PATCH 11/78] Added driver for HiFiBerry Amp amplifier add-on board +Subject: [PATCH 11/59] Added driver for HiFiBerry Amp amplifier add-on board The driver contains a low-level hardware driver for the TAS5713 and the drivers for the Raspberry Pi I2S subsystem. @@ -118792,217 +117355,10 @@ index 0000000..8f019e0 2.5.0 -From ecb06ed18274b3b5b8bde803d875016a5c377439 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Mon, 13 Apr 2015 18:45:39 +0100 -Subject: [PATCH 12/78] Adding Device Tree support for some RPi audio cards - ---- - sound/soc/bcm/hifiberry_dac.c | 22 ++++++++++++++++++++++ - sound/soc/bcm/hifiberry_dacplus.c | 22 ++++++++++++++++++++++ - sound/soc/bcm/hifiberry_digi.c | 22 ++++++++++++++++++++++ - sound/soc/bcm/iqaudio-dac.c | 16 ++++++++++++++++ - sound/soc/codecs/pcm5102a.c | 7 +++++++ - 5 files changed, 89 insertions(+) - -diff --git a/sound/soc/bcm/hifiberry_dac.c b/sound/soc/bcm/hifiberry_dac.c -index 4b70b45..3ab0f47 100644 ---- a/sound/soc/bcm/hifiberry_dac.c -+++ b/sound/soc/bcm/hifiberry_dac.c -@@ -72,6 +72,21 @@ static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_hifiberry_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); - if (ret) - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -@@ -84,10 +99,17 @@ static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); - } - -+static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-dac", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match); -+ - static struct platform_driver snd_rpi_hifiberry_dac_driver = { - .driver = { - .name = "snd-hifiberry-dac", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_dac_of_match, - }, - .probe = snd_rpi_hifiberry_dac_probe, - .remove = snd_rpi_hifiberry_dac_remove, -diff --git a/sound/soc/bcm/hifiberry_dacplus.c b/sound/soc/bcm/hifiberry_dacplus.c -index c63387b..11e4f39 100644 ---- a/sound/soc/bcm/hifiberry_dacplus.c -+++ b/sound/soc/bcm/hifiberry_dacplus.c -@@ -90,6 +90,21 @@ static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_hifiberry_dacplus.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); - if (ret) - dev_err(&pdev->dev, -@@ -103,10 +118,17 @@ static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); - } - -+static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-dacplus", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match); -+ - static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { - .driver = { - .name = "snd-rpi-hifiberry-dacplus", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_dacplus_of_match, - }, - .probe = snd_rpi_hifiberry_dacplus_probe, - .remove = snd_rpi_hifiberry_dacplus_remove, -diff --git a/sound/soc/bcm/hifiberry_digi.c b/sound/soc/bcm/hifiberry_digi.c -index 92e9e46..80732b8 100644 ---- a/sound/soc/bcm/hifiberry_digi.c -+++ b/sound/soc/bcm/hifiberry_digi.c -@@ -173,6 +173,21 @@ static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_hifiberry_digi.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); - if (ret) - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -@@ -185,10 +200,17 @@ static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); - } - -+static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-digi", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match); -+ - static struct platform_driver snd_rpi_hifiberry_digi_driver = { - .driver = { - .name = "snd-hifiberry-digi", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_digi_of_match, - }, - .probe = snd_rpi_hifiberry_digi_probe, - .remove = snd_rpi_hifiberry_digi_remove, -diff --git a/sound/soc/bcm/iqaudio-dac.c b/sound/soc/bcm/iqaudio-dac.c -index aff7377..a38e874 100644 ---- a/sound/soc/bcm/iqaudio-dac.c -+++ b/sound/soc/bcm/iqaudio-dac.c -@@ -82,6 +82,21 @@ static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_iqaudio_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); - if (ret) - dev_err(&pdev->dev, -@@ -99,6 +114,7 @@ static const struct of_device_id iqaudio_of_match[] = { - { .compatible = "iqaudio,iqaudio-dac", }, - {}, - }; -+MODULE_DEVICE_TABLE(of, iqaudio_of_match); - - static struct platform_driver snd_rpi_iqaudio_dac_driver = { - .driver = { -diff --git a/sound/soc/codecs/pcm5102a.c b/sound/soc/codecs/pcm5102a.c -index 126f1e9..7c6598e 100644 ---- a/sound/soc/codecs/pcm5102a.c -+++ b/sound/soc/codecs/pcm5102a.c -@@ -47,12 +47,19 @@ static int pcm5102a_remove(struct platform_device *pdev) - return 0; - } - -+static const struct of_device_id pcm5102a_of_match[] = { -+ { .compatible = "ti,pcm5102a", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, pcm5102a_of_match); -+ - static struct platform_driver pcm5102a_codec_driver = { - .probe = pcm5102a_probe, - .remove = pcm5102a_remove, - .driver = { - .name = "pcm5102a-codec", - .owner = THIS_MODULE, -+ .of_match_table = pcm5102a_of_match, - }, - }; - --- -2.5.0 - - -From f6dc4c1a7653c72b5a61cf01a66bd808bb7ce9bf Mon Sep 17 00:00:00 2001 +From 9491a7d6109f4ad61e1db014d5611c13232bfd65 Mon Sep 17 00:00:00 2001 From: Ryan Coe Date: Sat, 31 Jan 2015 18:25:49 -0700 -Subject: [PATCH 13/78] Update ds1307 driver for device-tree support +Subject: [PATCH 12/59] Update ds1307 driver for device-tree support Signed-off-by: Ryan Coe --- @@ -119032,10 +117388,10 @@ index aa705bb..1cb13fee 100644 2.5.0 -From 139c3996ad232a112b2d6a2773c1341309ddd6d9 Mon Sep 17 00:00:00 2001 +From f7704ed8c0ebb3eb5d4efc203afc58aab6642a2f Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 6 Feb 2015 13:50:57 +0000 -Subject: [PATCH 14/78] BCM270x_DT: Add pwr_led, and the required "input" +Subject: [PATCH 13/59] BCM270x_DT: Add pwr_led, and the required "input" trigger The "input" trigger makes the associated GPIO an input. This is to support @@ -119217,10 +117573,10 @@ index fa359c7..4b25a1a 100644 2.5.0 -From e2d77dbce08baa82a4d25727515bc231771a72fc Mon Sep 17 00:00:00 2001 +From 8a1b126dd7b96658a58c6fcb448599a329b0c681 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 27 Feb 2015 15:10:24 +0000 -Subject: [PATCH 15/78] enc28j60: Add device tree compatible string and an +Subject: [PATCH 14/59] enc28j60: Add device tree compatible string and an overlay --- @@ -119252,10 +117608,10 @@ index 86ea17e..a1b20c1 100644 2.5.0 -From 5192b386aa9768cc4f0dadb4bb76ed1cd84c82d6 Mon Sep 17 00:00:00 2001 +From dad0f756f15b857a690cd400a57967f1ea17ec51 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Wed, 25 Mar 2015 09:26:17 +0100 -Subject: [PATCH 16/78] Add driver for rpi-proto +Subject: [PATCH 15/59] Add driver for rpi-proto Forward port of 3.10.x driver from https://github.com/koalo We are using a custom board and would like to use rpi 3.18.x @@ -119473,105 +117829,24 @@ index 0000000..c6e45a0 2.5.0 -From e1a61c1a1dd0b2612e3b5259737b36df4e062e43 Mon Sep 17 00:00:00 2001 -From: Clive Messer -Date: Thu, 2 Apr 2015 12:22:55 +0100 -Subject: [PATCH 17/78] Add Device Tree support for RPi-DAC. - ---- - sound/soc/bcm/rpi-dac.c | 21 +++++++++++++++++++++ - sound/soc/codecs/pcm1794a.c | 7 +++++++ - 2 files changed, 28 insertions(+) - -diff --git a/sound/soc/bcm/rpi-dac.c b/sound/soc/bcm/rpi-dac.c -index 6d6e0ba..d5fac1b 100644 ---- a/sound/soc/bcm/rpi-dac.c -+++ b/sound/soc/bcm/rpi-dac.c -@@ -69,6 +69,20 @@ static int snd_rpi_rpi_dac_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_rpi_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_rpi_dac); - if (ret) - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -@@ -81,10 +95,17 @@ static int snd_rpi_rpi_dac_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_rpi_dac); - } - -+static const struct of_device_id snd_rpi_rpi_dac_of_match[] = { -+ { .compatible = "rpi,rpi-dac", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match); -+ - static struct platform_driver snd_rpi_rpi_dac_driver = { - .driver = { - .name = "snd-rpi-dac", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_rpi_dac_of_match, - }, - .probe = snd_rpi_rpi_dac_probe, - .remove = snd_rpi_rpi_dac_remove, -diff --git a/sound/soc/codecs/pcm1794a.c b/sound/soc/codecs/pcm1794a.c -index b4eaa44..afe1b41 100644 ---- a/sound/soc/codecs/pcm1794a.c -+++ b/sound/soc/codecs/pcm1794a.c -@@ -46,12 +46,19 @@ static int pcm1794a_remove(struct platform_device *pdev) - return 0; - } - -+static const struct of_device_id pcm1794a_of_match[] = { -+ { .compatible = "ti,pcm1794a", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, pcm1794a_of_match); -+ - static struct platform_driver pcm1794a_codec_driver = { - .probe = pcm1794a_probe, - .remove = pcm1794a_remove, - .driver = { - .name = "pcm1794a-codec", - .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(pcm1794a_of_match), - }, - }; - --- -2.5.0 - - -From 8564222053484a291b2e4c5db6c87fd09399c624 Mon Sep 17 00:00:00 2001 +From f83d2eae29ba396b02e1d1db4f7641c63a22e1ad Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 13 Apr 2015 17:16:29 +0100 -Subject: [PATCH 18/78] config: Add default configs +Subject: [PATCH 16/59] config: Add default configs --- - arch/arm/configs/bcm2709_defconfig | 1245 ++++++++++++++++++++++++++++++++++++ - arch/arm/configs/bcmrpi_defconfig | 1241 +++++++++++++++++++++++++++++++++++ - 2 files changed, 2486 insertions(+) + arch/arm/configs/bcm2709_defconfig | 1255 ++++++++++++++++++++++++++++++++++++ + arch/arm/configs/bcmrpi_defconfig | 1251 +++++++++++++++++++++++++++++++++++ + 2 files changed, 2506 insertions(+) create mode 100644 arch/arm/configs/bcm2709_defconfig create mode 100644 arch/arm/configs/bcmrpi_defconfig diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig new file mode 100644 -index 0000000..152e577 +index 0000000..f5c5e87 --- /dev/null +++ b/arch/arm/configs/bcm2709_defconfig -@@ -0,0 +1,1245 @@ +@@ -0,0 +1,1255 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_PHYS_OFFSET=0 +CONFIG_LOCALVERSION="-v7" @@ -119858,6 +118133,9 @@ index 0000000..152e577 +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m @@ -120104,6 +118382,9 @@ index 0000000..152e577 +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_JOYDEV=m @@ -120120,6 +118401,7 @@ index 0000000..152e577 +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_FT6236=m +CONFIG_TOUCHSCREEN_RPI_FT5406=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_STMPE=m @@ -120157,7 +118439,7 @@ index 0000000..152e577 +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2835=y +CONFIG_RAW_DRIVER=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m @@ -120415,6 +118697,7 @@ index 0000000..152e577 +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SOUND_PRIME=m +CONFIG_HIDRAW=y ++CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m @@ -120671,6 +118954,7 @@ index 0000000..152e577 +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_KFIFO_BUF=m ++CONFIG_MCP320X=m +CONFIG_DHT11=m +CONFIG_PWM_BCM2835=m +CONFIG_RASPBERRYPI_FIRMWARE=y @@ -120811,6 +119095,7 @@ index 0000000..152e577 +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=m @@ -120819,10 +119104,10 @@ index 0000000..152e577 +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig new file mode 100644 -index 0000000..0e47844 +index 0000000..c7d31e8 --- /dev/null +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -0,0 +1,1241 @@ +@@ -0,0 +1,1251 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_PHYS_OFFSET=0 +# CONFIG_LOCALVERSION_AUTO is not set @@ -121102,6 +119387,9 @@ index 0000000..0e47844 +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m @@ -121348,6 +119636,9 @@ index 0000000..0e47844 +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_JOYDEV=m @@ -121364,6 +119655,7 @@ index 0000000..0e47844 +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_FT6236=m +CONFIG_TOUCHSCREEN_RPI_FT5406=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_STMPE=m @@ -121401,7 +119693,7 @@ index 0000000..0e47844 +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2835=y +CONFIG_RAW_DRIVER=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m @@ -121659,6 +119951,7 @@ index 0000000..0e47844 +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SOUND_PRIME=m +CONFIG_HIDRAW=y ++CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m @@ -121915,6 +120208,7 @@ index 0000000..0e47844 +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_KFIFO_BUF=m ++CONFIG_MCP320X=m +CONFIG_DHT11=m +CONFIG_PWM_BCM2835=m +CONFIG_RASPBERRYPI_FIRMWARE=y @@ -122058,6 +120352,7 @@ index 0000000..0e47844 +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM=m @@ -122068,10 +120363,10 @@ index 0000000..0e47844 2.5.0 -From 3289e2125e8875ad5327a3ecf7ff7d6916841c99 Mon Sep 17 00:00:00 2001 +From 4a03e3e11c4576e0b94a0e6c8e4dd676140d6120 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Wed, 29 Apr 2015 17:24:02 +0200 -Subject: [PATCH 19/78] bcm2835: bcm2835_defconfig +Subject: [PATCH 17/59] bcm2835: bcm2835_defconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -123500,10 +121795,10 @@ index 31cb073..fdb2e2a 100644 2.5.0 -From 6ba8f0f4387371066f85d6bc576aec6468ef12e3 Mon Sep 17 00:00:00 2001 +From 9a3fd91c18be1eda26a0637ce6b905c75d6f67e2 Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Tue, 12 May 2015 14:47:56 +0100 -Subject: [PATCH 20/78] rpi-ft5406: Add touchscreen driver for pi LCD display +Subject: [PATCH 18/59] rpi-ft5406: Add touchscreen driver for pi LCD display Fix driver detection failure Check that the buffer response is non-zero meaning the touchscreen was detected @@ -123547,7 +121842,7 @@ index cbaa6ab..13ab8c0 100644 obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o diff --git a/drivers/input/touchscreen/rpi-ft5406.c b/drivers/input/touchscreen/rpi-ft5406.c new file mode 100644 -index 0000000..c08817e +index 0000000..b27dbee --- /dev/null +++ b/drivers/input/touchscreen/rpi-ft5406.c @@ -0,0 +1,246 @@ @@ -123618,7 +121913,7 @@ index 0000000..c08817e + while(!kthread_should_stop()) + { + // 60fps polling -+ msleep(17); ++ msleep_interruptible(17); + memcpy_fromio(®s, ts->regs, sizeof(*ts->regs)); + writel(99, &ts->regs->num_points); + // Do not output if theres no new information (num_points is 99) @@ -123801,10 +122096,10 @@ index 0000000..c08817e 2.5.0 -From 147e4cdb102b5cb7e607437f0accc4ee0d723b6a Mon Sep 17 00:00:00 2001 +From 1fb6da46a439a109415dea3ae8967e5b55186303 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 13 Oct 2014 11:47:53 +0100 -Subject: [PATCH 21/78] Improve __copy_to_user and __copy_from_user performance +Subject: [PATCH 19/59] Improve __copy_to_user and __copy_from_user performance Provide a __copy_from_user that uses memcpy. On BCM2708, use optimised memcpy/memmove/memcmp/memset implementations. @@ -123851,7 +122146,7 @@ index cf4f3aa..9fe7780 100644 #define memset(p,v,n) \ diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h -index 8cc85a4..21ec2fc 100644 +index 35c9db8..52d3401 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -493,6 +493,9 @@ do { \ @@ -125191,7 +123486,7 @@ index 0000000..7067415 +ENDPROC(memset) +ENDPROC(mmioset) diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c -index d72b909..a6d8276 100644 +index 588bbc2..c29df92 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -22,6 +22,14 @@ @@ -125254,8 +123549,8 @@ index d72b909..a6d8276 100644 +unsigned long noinline __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) { - int atomic; -@@ -135,6 +180,54 @@ out: + unsigned long ua_flags; +@@ -138,6 +183,54 @@ out: return n; } @@ -125310,14 +123605,18 @@ index d72b909..a6d8276 100644 unsigned long arm_copy_to_user(void __user *to, const void *from, unsigned long n) { -@@ -145,10 +238,25 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) +@@ -148,7 +241,7 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) * With frame pointer disabled, tail call optimization kicks in * as well making this test almost invisible. */ -- if (n < 64) -+ if (n < COPY_TO_USER_THRESHOLD) - return __copy_to_user_std(to, from, n); - return __copy_to_user_memcpy(to, from, n); +- if (n < 64) { ++ if (n < COPY_TO_USER_THRESHOLD) { + unsigned long ua_flags = uaccess_save_and_enable(); + n = __copy_to_user_std(to, from, n); + uaccess_restore(ua_flags); +@@ -157,6 +250,21 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) + } + return n; } + +unsigned long __must_check @@ -125341,87 +123640,10 @@ index d72b909..a6d8276 100644 2.5.0 -From a91bc4e81f434b62b5f74d959654fb574c600e0f Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 16 Jun 2015 17:47:27 +0100 -Subject: [PATCH 22/78] platform: Add force_core command line setting to boot - from a different core number - ---- - arch/arm/mach-bcm2709/armctrl.c | 17 ++++++++++++++++- - arch/arm/mach-bcm2709/bcm2709.c | 2 ++ - 2 files changed, 18 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -index c6f68b4..fb82f7d 100644 ---- a/arch/arm/mach-bcm2709/armctrl.c -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -45,6 +45,8 @@ static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { - INTERRUPT_VC_ARASANSDIO - }; - -+extern unsigned force_core; -+ - static void armctrl_mask_irq(struct irq_data *d) - { - static const unsigned int disables[4] = { -@@ -92,7 +94,13 @@ static void armctrl_unmask_irq(struct irq_data *d) - int i; - if (d->irq >= FIQ_START) { - unsigned int data; -- if (num_online_cpus() > 1) { -+ if (force_core) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= ((force_core-1) << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ else if (num_online_cpus() > 1) { - data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); - data &= ~0xc; - data |= (1 << 2); -@@ -119,6 +127,13 @@ static void armctrl_unmask_irq(struct irq_data *d) - } - #endif - } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ if (force_core) { -+ unsigned int data; -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0x3; -+ data |= ((force_core-1) << 0); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } - unsigned int data = (unsigned int)irq_get_chip_data(d->irq); - writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); - } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c -index 3eeeb886..cbcf731 100644 ---- a/arch/arm/mach-bcm2709/bcm2709.c -+++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -56,6 +56,7 @@ - /* command line parameters */ - static unsigned boardrev, serial; - static unsigned reboot_part = 0; -+unsigned force_core; - - void __init bcm2709_init_irq(void) - { -@@ -534,6 +535,7 @@ MACHINE_START(BCM2708, "BCM2709") - .dt_compat = bcm2709_compat, - MACHINE_END - -+module_param(force_core, uint, 0644); - module_param(boardrev, uint, 0644); - module_param(serial, uint, 0644); - module_param(reboot_part, uint, 0644); --- -2.5.0 - - -From 66bff3777e1bf5b556a30e782432dce3cf5e234e Mon Sep 17 00:00:00 2001 +From e8f7622b797353eb01277b988f5dcb01d4281762 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 25 Jun 2015 12:16:11 +0100 -Subject: [PATCH 23/78] gpio-poweroff: Allow it to work on Raspberry Pi +Subject: [PATCH 20/59] gpio-poweroff: Allow it to work on Raspberry Pi The Raspberry Pi firmware manages the power-down and reboot process. To do this it installs a pm_power_off handler, causing @@ -125459,10 +123681,10 @@ index be3d81f..a030ae9 100644 2.5.0 -From 6b5b53f993acf7132d9ebd2c15b71c1eb5470686 Mon Sep 17 00:00:00 2001 +From 8c8f50a7ed38607026f7d987f9ca2b589d2f0187 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 14 Jul 2015 10:26:09 +0100 -Subject: [PATCH 24/78] spidev: Add "spidev" compatible string to silence +Subject: [PATCH 21/59] spidev: Add "spidev" compatible string to silence warning See: https://github.com/raspberrypi/linux/issues/1054 @@ -125471,7 +123693,7 @@ See: https://github.com/raspberrypi/linux/issues/1054 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c -index 91a0fcd..241b7bf 100644 +index d0e7dfc..57b0760 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -695,6 +695,7 @@ static struct class *spidev_class; @@ -125486,10 +123708,10 @@ index 91a0fcd..241b7bf 100644 2.5.0 -From 7c72afc6111aaa4d679c5fb8a8510069e2b0ee0b Mon Sep 17 00:00:00 2001 +From 3f7779b380bd473670d38dd4ff3d6513ec1a89c2 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 14 Jul 2015 17:00:18 +0100 -Subject: [PATCH 25/78] scripts/dtc: Add overlay support +Subject: [PATCH 22/59] scripts/dtc: Add overlay support --- scripts/dtc/checks.c | 119 ++- @@ -129897,10 +128119,10 @@ index 5b8c7d5..86b7338 100644 2.5.0 -From 3d24dd7bf0d39e19decd21fb842498b45d88cd89 Mon Sep 17 00:00:00 2001 +From 74fb644989dfc1101e5ddca287ce58b8b5f41c79 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 14 Jul 2015 14:32:47 +0100 -Subject: [PATCH 26/78] Merge pull request #1043 from XECDesign/sense-4.0 +Subject: [PATCH 23/59] Merge pull request #1043 from XECDesign/sense-4.0 mfd: Add Raspberry Pi Sense HAT core driver --- @@ -130770,10 +128992,10 @@ index 0000000..56196dc 2.5.0 -From 3a0e5391bd98674d1191359af4be716d9fd5d494 Mon Sep 17 00:00:00 2001 +From c403980d1dddcb1c9eb149e6bda2a8057f4f859c Mon Sep 17 00:00:00 2001 From: Jan Grulich Date: Mon, 24 Aug 2015 16:03:47 +0100 -Subject: [PATCH 27/78] RaspiDAC3 support +Subject: [PATCH 24/59] RaspiDAC3 support Signed-off-by: Jan Grulich @@ -130825,7 +129047,7 @@ index 4f5ab1f..b21e11e 100644 +obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o diff --git a/sound/soc/bcm/raspidac3.c b/sound/soc/bcm/raspidac3.c new file mode 100644 -index 0000000..fddaeec +index 0000000..3cabf5b --- /dev/null +++ b/sound/soc/bcm/raspidac3.c @@ -0,0 +1,191 @@ @@ -130870,7 +129092,7 @@ index 0000000..fddaeec + snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02); + snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); + -+ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207); + if (ret < 0) + dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); + else { @@ -130880,7 +129102,7 @@ index 0000000..fddaeec + if (ret < 0) + dev_warn(card->dev, "Failed to add TPA6130A2 controls: %d\n", + ret); -+ ret = snd_soc_limit_volume(codec, ++ ret = snd_soc_limit_volume(card, + "TPA6130A2 Headphone Playback Volume", + 54); + if (ret < 0) @@ -131024,10 +129246,10 @@ index 0000000..fddaeec 2.5.0 -From 69d4790c40897d0fddc52fc71e24dd767556df42 Mon Sep 17 00:00:00 2001 +From f1244f1b3c28e2bbf6fcb7887cd2353c19be1ece Mon Sep 17 00:00:00 2001 From: Jan Grulich Date: Mon, 24 Aug 2015 16:02:34 +0100 -Subject: [PATCH 28/78] tpa6130a2: Add headphone switch control +Subject: [PATCH 25/59] tpa6130a2: Add headphone switch control Signed-off-by: Jan Grulich --- @@ -131121,20 +129343,20 @@ index 11d85c5..3caaa17 100644 2.5.0 -From 49ccce76c0a6fe54c89d2eadcb90b6474f3c1342 Mon Sep 17 00:00:00 2001 +From 4e237ee42e13fd4c1c2b1dd65d8f0ad58f4d601c Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 28 Sep 2015 23:38:59 +0100 -Subject: [PATCH 29/78] irq-bcm2835: Fix building with 2708 +Subject: [PATCH 26/59] irq-bcm2835: Fix building with 2708 --- drivers/irqchip/irq-bcm2835.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c -index 3f601f9..3478e75 100644 +index 20deb28..c02bf8a 100644 --- a/drivers/irqchip/irq-bcm2835.c +++ b/drivers/irqchip/irq-bcm2835.c -@@ -77,6 +77,7 @@ +@@ -82,6 +82,7 @@ #define NR_BANKS 3 #define IRQS_PER_BANK 32 #define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0) @@ -131142,7 +129364,7 @@ index 3f601f9..3478e75 100644 #define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0)) static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 }; -@@ -218,7 +219,7 @@ static int __init armctrl_of_init(struct device_node *node, +@@ -256,7 +257,7 @@ static int __init armctrl_of_init(struct device_node *node, MAKE_HWIRQ(b, i) + NUMBER_IRQS); BUG_ON(irq <= 0); irq_set_chip(irq, &armctrl_chip); @@ -131155,10 +129377,10 @@ index 3f601f9..3478e75 100644 2.5.0 -From fdedc022ee2498d3dd3dc3f3511a8a5ab5f1d0fc Mon Sep 17 00:00:00 2001 +From 256a8a32c69b5eeede30f5eb6674e7e2f4d5d50b Mon Sep 17 00:00:00 2001 From: P33M Date: Wed, 21 Oct 2015 14:55:21 +0100 -Subject: [PATCH 30/78] rpi_display: add backlight driver and overlay +Subject: [PATCH 27/59] rpi_display: add backlight driver and overlay Add a mailbox-driven backlight controller for the Raspberry Pi DSI touchscreen display. Requires updated GPU firmware to recognise the @@ -131192,10 +129414,10 @@ index d8c2771..fb7ac49 100644 dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index d8d0a51..fdefff1 100644 +index 44e33a4..b819293 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README -@@ -463,6 +463,12 @@ Load: dtoverlay=raspidac3 +@@ -462,6 +462,12 @@ Load: dtoverlay=raspidac3 Params: @@ -131236,10 +129458,10 @@ index 0000000..c021d02 + }; +}; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 152e577..3ec59d2 100644 +index f5c5e87..38e46ac 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig -@@ -801,6 +801,7 @@ CONFIG_FB_UDL=m +@@ -808,6 +808,7 @@ CONFIG_FB_UDL=m CONFIG_FB_SSD1307=m CONFIG_FB_RPISENSE=m # CONFIG_BACKLIGHT_GENERIC is not set @@ -131248,10 +129470,10 @@ index 152e577..3ec59d2 100644 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 0e47844..0f69adb 100644 +index c7d31e8..436da55 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -794,6 +794,7 @@ CONFIG_FB_UDL=m +@@ -801,6 +801,7 @@ CONFIG_FB_UDL=m CONFIG_FB_SSD1307=m CONFIG_FB_RPISENSE=m # CONFIG_BACKLIGHT_GENERIC is not set @@ -131429,20 +129651,20 @@ index 525816d..b011489 100644 2.5.0 -From 2bc2902a664d66f4eeb83bb94d55e45d2e00e1fa Mon Sep 17 00:00:00 2001 +From 4597458b3521c98d3260ed9a4eb739e6a6b5713c Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Mon, 16 Nov 2015 14:05:35 +0000 -Subject: [PATCH 31/78] bcm2835-dma: Fix up convert to DMA pool +Subject: [PATCH 28/59] bcm2835-dma: Fix up convert to DMA pool --- drivers/dma/bcm2835-dma.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 58a96a6..3cf5a88 100644 +index 0adc347..985019b 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c -@@ -491,6 +491,17 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -488,6 +488,17 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( c->cyclic = true; return vchan_tx_prep(&c->vc, &d->vd, flags); @@ -131460,7 +129682,7 @@ index 58a96a6..3cf5a88 100644 } static struct dma_async_tx_descriptor * -@@ -537,6 +548,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -534,6 +545,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, if (!d) return NULL; @@ -131468,7 +129690,7 @@ index 58a96a6..3cf5a88 100644 d->dir = direction; if (c->ch >= 8) /* LITE channel */ -@@ -556,15 +568,21 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -553,15 +565,21 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, d->frames += len / max_size + 1; } @@ -131496,16 +129718,16 @@ index 58a96a6..3cf5a88 100644 /* * Iterate over all SG entries, create a control block -@@ -582,7 +600,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -578,7 +596,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, + for (j = 0; j < len; j += max_size) { - u32 waits; struct bcm2835_dma_cb *control_block = - &d->control_block_base[i + split_cnt]; + d->cb_list[i + split_cnt].cb; /* Setup addresses */ if (d->dir == DMA_DEV_TO_MEM) { -@@ -626,9 +644,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -620,9 +638,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, if (i < sg_len - 1 || len - j > max_size) { /* Next block is the next frame. */ control_block->next = @@ -131520,1913 +129742,10 @@ index 58a96a6..3cf5a88 100644 2.5.0 -From 55dc4c597e9ec35aab1153ceb88334e285f0923a Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Mon, 16 Nov 2015 21:32:15 +0000 -Subject: [PATCH 32/78] squash: Fixup bcm2835-camera for changes in kernel 4.4 - api - ---- - drivers/media/platform/bcm2835/bcm2835-camera.c | 33 +++++++++++++------------ - drivers/media/platform/bcm2835/mmal-common.h | 2 +- - 2 files changed, 18 insertions(+), 17 deletions(-) - -diff --git a/drivers/media/platform/bcm2835/bcm2835-camera.c b/drivers/media/platform/bcm2835/bcm2835-camera.c -index dfd22d4..e83334c 100644 ---- a/drivers/media/platform/bcm2835/bcm2835-camera.c -+++ b/drivers/media/platform/bcm2835/bcm2835-camera.c -@@ -320,7 +320,7 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - /* error in transfer */ - if (buf != NULL) { - /* there was a buffer with the error so return it */ -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - } - return; - } else if (length == 0) { -@@ -329,7 +329,7 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - /* this should only ever happen if the port is - * disabled and there are buffers still queued - */ -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - pr_debug("Empty buffer"); - } else if (dev->capture.frame_count) { - /* grab another frame */ -@@ -359,16 +359,16 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - - div = - div_u64_rem(runtime_us, USEC_PER_SEC, &rem); -- buf->vb.v4l2_buf.timestamp.tv_sec = -+ buf->vb.timestamp.tv_sec = - dev->capture.kernel_start_ts.tv_sec - 1 + - div; -- buf->vb.v4l2_buf.timestamp.tv_usec = -+ buf->vb.timestamp.tv_usec = - dev->capture.kernel_start_ts.tv_usec + rem; - -- if (buf->vb.v4l2_buf.timestamp.tv_usec >= -+ if (buf->vb.timestamp.tv_usec >= - USEC_PER_SEC) { -- buf->vb.v4l2_buf.timestamp.tv_sec++; -- buf->vb.v4l2_buf.timestamp.tv_usec -= -+ buf->vb.timestamp.tv_sec++; -+ buf->vb.timestamp.tv_usec -= - USEC_PER_SEC; - } - v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -@@ -379,15 +379,15 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - (int)dev->capture.kernel_start_ts. - tv_usec, - dev->capture.vc_start_timestamp, pts, -- (int)buf->vb.v4l2_buf.timestamp.tv_sec, -- (int)buf->vb.v4l2_buf.timestamp. -+ (int)buf->vb.timestamp.tv_sec, -+ (int)buf->vb.timestamp. - tv_usec); - } else { -- v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); -+ v4l2_get_timestamp(&buf->vb.timestamp); - } - -- vb2_set_plane_payload(&buf->vb, 0, length); -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); -+ vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); - - if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS && - is_capturing(dev)) { -@@ -404,7 +404,7 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - } - } else { - /* signal frame completion */ -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - complete(&dev->capture.frame_cmplt); - } - } -@@ -466,14 +466,15 @@ static int disable_camera(struct bm2835_mmal_dev *dev) - static void buffer_queue(struct vb2_buffer *vb) - { - struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); -- struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb); -+ struct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb); -+ struct mmal_buffer *buf = container_of(vb2, struct mmal_buffer, vb); - int ret; - - v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, - "%s: dev:%p buf:%p\n", __func__, dev, buf); - -- buf->buffer = vb2_plane_vaddr(&buf->vb, 0); -- buf->buffer_size = vb2_plane_size(&buf->vb, 0); -+ buf->buffer = vb2_plane_vaddr(&buf->vb.vb2_buf, 0); -+ buf->buffer_size = vb2_plane_size(&buf->vb.vb2_buf, 0); - - ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf); - if (ret < 0) -diff --git a/drivers/media/platform/bcm2835/mmal-common.h b/drivers/media/platform/bcm2835/mmal-common.h -index 15788a1..840fd13 100644 ---- a/drivers/media/platform/bcm2835/mmal-common.h -+++ b/drivers/media/platform/bcm2835/mmal-common.h -@@ -36,7 +36,7 @@ struct mmal_fmt { - /* buffer for one video frame */ - struct mmal_buffer { - /* v4l buffer data -- must be first */ -- struct vb2_buffer vb; -+ struct vb2_v4l2_buffer vb; - - /* list of buffers available */ - struct list_head list; --- -2.5.0 - - -From c3dcfae142657d6f7eb58b7c03327cad744e7e52 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 17 Nov 2015 18:52:58 +0000 -Subject: [PATCH 33/78] BCM2709: Use upstream interrupt driver on all Pi2's - ---- - arch/arm/Kconfig | 2 + - arch/arm/mach-bcm2709/Makefile | 2 +- - arch/arm/mach-bcm2709/armctrl.c | 384 ------------------ - arch/arm/mach-bcm2709/armctrl.h | 27 -- - arch/arm/mach-bcm2709/bcm2709.c | 167 +------- - arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 ----------------------- - arch/arm/mach-bcm2709/include/mach/hardware.h | 28 -- - arch/arm/mach-bcm2709/include/mach/irqs.h | 225 ----------- - arch/arm/mach-bcm2709/include/mach/platform.h | 189 ++++----- - arch/arm/mach-bcm2709/include/mach/system.h | 1 - - arch/arm/mach-bcm2709/include/mach/uncompress.h | 2 +- - drivers/irqchip/Makefile | 1 + - 12 files changed, 84 insertions(+), 1437 deletions(-) - delete mode 100644 arch/arm/mach-bcm2709/armctrl.c - delete mode 100644 arch/arm/mach-bcm2709/armctrl.h - delete mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h - delete mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h - delete mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 3241611..601b520 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -351,6 +351,8 @@ config ARCH_BCM2709 - select ARCH_HAS_CPUFREQ - select GENERIC_CLOCKEVENTS - select MACH_BCM2709 -+ select MULTI_IRQ_HANDLER -+ select SPARSE_IRQ - select VC4 - select FIQ - select USE_OF -diff --git a/arch/arm/mach-bcm2709/Makefile b/arch/arm/mach-bcm2709/Makefile -index 11ad846..26cd67d 100644 ---- a/arch/arm/mach-bcm2709/Makefile -+++ b/arch/arm/mach-bcm2709/Makefile -@@ -2,4 +2,4 @@ - # Makefile for the linux kernel. - # - --obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o -+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -deleted file mode 100644 -index fb82f7d..0000000 ---- a/arch/arm/mach-bcm2709/armctrl.c -+++ /dev/null -@@ -1,384 +0,0 @@ --/* -- * linux/arch/arm/mach-bcm2708/armctrl.c -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ --#include --#include --#include --#include --#include --#include --#include --#include -- --#include --#include --#include "armctrl.h" -- --/* For support of kernels >= 3.0 assume only one VIC for now*/ --static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -- INTERRUPT_VC_JPEG, -- INTERRUPT_VC_USB, -- INTERRUPT_VC_3D, -- INTERRUPT_VC_DMA2, -- INTERRUPT_VC_DMA3, -- INTERRUPT_VC_I2C, -- INTERRUPT_VC_SPI, -- INTERRUPT_VC_I2SPCM, -- INTERRUPT_VC_SDIO, -- INTERRUPT_VC_UART, -- INTERRUPT_VC_ARASANSDIO --}; -- --extern unsigned force_core; -- --static void armctrl_mask_irq(struct irq_data *d) --{ -- static const unsigned int disables[4] = { -- ARM_IRQ_DIBL1, -- ARM_IRQ_DIBL2, -- ARM_IRQ_DIBL3, -- 0 -- }; -- int i; -- if (d->irq >= FIQ_START) { -- writel(0, __io_address(ARM_IRQ_FAST)); -- } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { --#if 1 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -- for (i=0; i<4; i++) // i = raw_smp_processor_id(); // -- { -- unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { --#if 0 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -- for (i=0; i<4; i++) { -- unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -- writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -- } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -- writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); -- } else { printk("%s: %d\n", __func__, d->irq); BUG(); } --} -- --static void armctrl_unmask_irq(struct irq_data *d) --{ -- static const unsigned int enables[4] = { -- ARM_IRQ_ENBL1, -- ARM_IRQ_ENBL2, -- ARM_IRQ_ENBL3, -- 0 -- }; -- int i; -- if (d->irq >= FIQ_START) { -- unsigned int data; -- if (force_core) { -- data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- data &= ~0xc; -- data |= ((force_core-1) << 2); -- writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- } -- else if (num_online_cpus() > 1) { -- data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- data &= ~0xc; -- data |= (1 << 2); -- writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- } -- /* Unmask in ARMCTRL block after routing it properly */ -- data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -- writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -- } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { --#if 1 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -- for (i=0; i<4; i++) // i = raw_smp_processor_id(); -- { -- unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { --#if 0 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -- for (i=0; i<4; i++) { -- unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -- if (force_core) { -- unsigned int data; -- data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- data &= ~0x3; -- data |= ((force_core-1) << 0); -- writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- } -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -- writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -- } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -- writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); -- } else { printk("%s: %d\n", __func__, d->irq); BUG(); } --} -- --#ifdef CONFIG_OF -- --#define NR_IRQS_BANK0 21 --#define NR_BANKS 4 --#define IRQS_PER_BANK 32 -- --/* from drivers/irqchip/irq-bcm2835.c */ --static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -- const u32 *intspec, unsigned int intsize, -- unsigned long *out_hwirq, unsigned int *out_type) --{ -- if (WARN_ON(intsize != 2)) -- return -EINVAL; -- -- if (WARN_ON(intspec[0] >= NR_BANKS)) -- return -EINVAL; -- -- if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -- return -EINVAL; -- -- if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -- return -EINVAL; -- -- if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) -- return -EINVAL; -- -- if (intspec[0] == 0) -- *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -- else if (intspec[0] == 1) -- *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -- else if (intspec[0] == 2) -- *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -- else -- *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; -- -- /* reverse remap_irqs[] */ -- switch (*out_hwirq) { -- case INTERRUPT_VC_JPEG: -- *out_hwirq = INTERRUPT_JPEG; -- break; -- case INTERRUPT_VC_USB: -- *out_hwirq = INTERRUPT_USB; -- break; -- case INTERRUPT_VC_3D: -- *out_hwirq = INTERRUPT_3D; -- break; -- case INTERRUPT_VC_DMA2: -- *out_hwirq = INTERRUPT_DMA2; -- break; -- case INTERRUPT_VC_DMA3: -- *out_hwirq = INTERRUPT_DMA3; -- break; -- case INTERRUPT_VC_I2C: -- *out_hwirq = INTERRUPT_I2C; -- break; -- case INTERRUPT_VC_SPI: -- *out_hwirq = INTERRUPT_SPI; -- break; -- case INTERRUPT_VC_I2SPCM: -- *out_hwirq = INTERRUPT_I2SPCM; -- break; -- case INTERRUPT_VC_SDIO: -- *out_hwirq = INTERRUPT_SDIO; -- break; -- case INTERRUPT_VC_UART: -- *out_hwirq = INTERRUPT_UART; -- break; -- case INTERRUPT_VC_ARASANSDIO: -- *out_hwirq = INTERRUPT_ARASANSDIO; -- break; -- } -- -- *out_type = IRQ_TYPE_NONE; -- return 0; --} -- --static struct irq_domain_ops armctrl_ops = { -- .xlate = armctrl_xlate --}; -- --void __init armctrl_dt_init(void) --{ -- struct device_node *np; -- struct irq_domain *domain; -- -- np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -- if (!np) -- return; -- -- domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -- IRQ_ARMCTRL_START, 0, -- &armctrl_ops, NULL); -- WARN_ON(!domain); --} --#else --void __init armctrl_dt_init(void) { } --#endif /* CONFIG_OF */ -- --#if defined(CONFIG_PM) -- --/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -- --/* Static defines -- * struct armctrl_device - VIC PM device (< 3.xx) -- * @sysdev: The system device which is registered. (< 3.xx) -- * @irq: The IRQ number for the base of the VIC. -- * @base: The register base for the VIC. -- * @resume_sources: A bitmask of interrupts for resume. -- * @resume_irqs: The IRQs enabled for resume. -- * @int_select: Save for VIC_INT_SELECT. -- * @int_enable: Save for VIC_INT_ENABLE. -- * @soft_int: Save for VIC_INT_SOFT. -- * @protect: Save for VIC_PROTECT. -- */ --struct armctrl_info { -- void __iomem *base; -- int irq; -- u32 resume_sources; -- u32 resume_irqs; -- u32 int_select; -- u32 int_enable; -- u32 soft_int; -- u32 protect; --} armctrl; -- --static int armctrl_suspend(void) --{ -- return 0; --} -- --static void armctrl_resume(void) --{ -- return; --} -- --/** -- * armctrl_pm_register - Register a VIC for later power management control -- * @base: The base address of the VIC. -- * @irq: The base IRQ for the VIC. -- * @resume_sources: bitmask of interrupts allowed for resume sources. -- * -- * For older kernels (< 3.xx) do - -- * Register the VIC with the system device tree so that it can be notified -- * of suspend and resume requests and ensure that the correct actions are -- * taken to re-instate the settings on resume. -- */ --static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -- u32 resume_sources) --{ -- armctrl.base = base; -- armctrl.resume_sources = resume_sources; -- armctrl.irq = irq; --} -- --static int armctrl_set_wake(struct irq_data *d, unsigned int on) --{ -- unsigned int off = d->irq & 31; -- u32 bit = 1 << off; -- -- if (!(bit & armctrl.resume_sources)) -- return -EINVAL; -- -- if (on) -- armctrl.resume_irqs |= bit; -- else -- armctrl.resume_irqs &= ~bit; -- -- return 0; --} -- --#else --static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -- u32 arg1) --{ --} -- --#define armctrl_suspend NULL --#define armctrl_resume NULL --#define armctrl_set_wake NULL --#endif /* CONFIG_PM */ -- --static struct syscore_ops armctrl_syscore_ops = { -- .suspend = armctrl_suspend, -- .resume = armctrl_resume, --}; -- --/** -- * armctrl_syscore_init - initicall to register VIC pm functions -- * -- * This is called via late_initcall() to register -- * the resources for the VICs due to the early -- * nature of the VIC's registration. --*/ --static int __init armctrl_syscore_init(void) --{ -- register_syscore_ops(&armctrl_syscore_ops); -- return 0; --} -- --late_initcall(armctrl_syscore_init); -- --static struct irq_chip armctrl_chip = { -- .name = "ARMCTRL", -- .irq_ack = NULL, -- .irq_mask = armctrl_mask_irq, -- .irq_unmask = armctrl_unmask_irq, -- .irq_set_wake = armctrl_set_wake, --}; -- --/** -- * armctrl_init - initialise a vectored interrupt controller -- * @base: iomem base address -- * @irq_start: starting interrupt number, must be muliple of 32 -- * @armctrl_sources: bitmask of interrupt sources to allow -- * @resume_sources: bitmask of interrupt sources to allow for resume -- */ --int __init armctrl_init(void __iomem * base, unsigned int irq_start, -- u32 armctrl_sources, u32 resume_sources) --{ -- unsigned int irq; -- -- for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -- unsigned int data = irq; -- if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -- data = remap_irqs[irq - INTERRUPT_JPEG]; -- if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { -- irq_set_percpu_devid(irq); -- irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); -- irq_set_status_flags(irq, IRQ_NOAUTOEN); -- } else { -- irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); -- irq_set_probe(irq); -- } -- irq_set_chip_data(irq, (void *)data); -- } -- -- armctrl_pm_register(base, irq_start, resume_sources); -- init_FIQ(FIQ_START); -- armctrl_dt_init(); -- return 0; --} -diff --git a/arch/arm/mach-bcm2709/armctrl.h b/arch/arm/mach-bcm2709/armctrl.h -deleted file mode 100644 -index 0aa916e..0000000 ---- a/arch/arm/mach-bcm2709/armctrl.h -+++ /dev/null -@@ -1,27 +0,0 @@ --/* -- * linux/arch/arm/mach-bcm2708/armctrl.h -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ -- --#ifndef __BCM2708_ARMCTRL_H --#define __BCM2708_ARMCTRL_H -- --extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -- u32 armctrl_sources, u32 resume_sources); -- --#endif -diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c -index cbcf731..90773a3 100644 ---- a/arch/arm/mach-bcm2709/bcm2709.c -+++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -28,20 +28,16 @@ - #include - - #include --#include - #include - #include - - #include - #include --#include - --#include "armctrl.h" -+#include - - #include - --//#define SYSTEM_TIMER -- - /* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to - * give us IO access only to 64Mbytes of physical memory (26 bits). We could - * represent this window by setting our dmamasks to 26 bits but, in fact -@@ -56,12 +52,6 @@ - /* command line parameters */ - static unsigned boardrev, serial; - static unsigned reboot_part = 0; --unsigned force_core; -- --void __init bcm2709_init_irq(void) --{ -- armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); --} - - static struct map_desc bcm2709_io_desc[] __initdata = { - { -@@ -121,54 +111,6 @@ void __init bcm2709_map_io(void) - iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); - } - --#ifdef SYSTEM_TIMER -- --/* The STC is a free running counter that increments at the rate of 1MHz */ --#define STC_FREQ_HZ 1000000 -- --static inline uint32_t timer_read(void) --{ -- /* STC: a free running counter that increments at the rate of 1MHz */ -- return readl(__io_address(ST_BASE + 0x04)); --} -- --static unsigned long bcm2709_read_current_timer(void) --{ -- return timer_read(); --} -- --static u64 notrace bcm2709_read_sched_clock(void) --{ -- return timer_read(); --} -- --static cycle_t clksrc_read(struct clocksource *cs) --{ -- return timer_read(); --} -- --static struct clocksource clocksource_stc = { -- .name = "stc", -- .rating = 300, -- .read = clksrc_read, -- .mask = CLOCKSOURCE_MASK(32), -- .flags = CLOCK_SOURCE_IS_CONTINUOUS, --}; -- --unsigned long frc_clock_ticks32(void) --{ -- return timer_read(); --} -- --static void __init bcm2709_clocksource_init(void) --{ -- if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -- printk(KERN_ERR "timer: failed to initialize clock " -- "source %s\n", clocksource_stc.name); -- } --} --#endif -- - int calc_rsts(int partition) - { - return PM_PASSWORD | -@@ -253,7 +195,8 @@ void __init bcm2709_init(void) - - pm_power_off = bcm2709_power_off; - -- ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, -+ NULL); - if (ret) { - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); -@@ -265,105 +208,6 @@ void __init bcm2709_init(void) - system_serial_low = serial; - } - --#ifdef SYSTEM_TIMER --static void timer_set_mode(enum clock_event_mode mode, -- struct clock_event_device *clk) --{ -- switch (mode) { -- case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -- case CLOCK_EVT_MODE_SHUTDOWN: -- break; -- case CLOCK_EVT_MODE_PERIODIC: -- -- case CLOCK_EVT_MODE_UNUSED: -- case CLOCK_EVT_MODE_RESUME: -- -- default: -- printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -- (int)mode); -- break; -- } -- --} -- --static int timer_set_next_event(unsigned long cycles, -- struct clock_event_device *unused) --{ -- unsigned long stc; -- do { -- stc = readl(__io_address(ST_BASE + 0x04)); -- /* We could take a FIQ here, which may push ST above STC3 */ -- writel(stc + cycles, __io_address(ST_BASE + 0x18)); -- } while ((signed long) cycles >= 0 && -- (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -- >= (signed long) cycles); -- return 0; --} -- --static struct clock_event_device timer0_clockevent = { -- .name = "timer0", -- .shift = 32, -- .features = CLOCK_EVT_FEAT_ONESHOT, -- .set_mode = timer_set_mode, -- .set_next_event = timer_set_next_event, --}; -- --/* -- * IRQ handler for the timer -- */ --static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) --{ -- struct clock_event_device *evt = &timer0_clockevent; -- -- writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -- -- evt->event_handler(evt); -- -- return IRQ_HANDLED; --} -- --static struct irqaction bcm2709_timer_irq = { -- .name = "BCM2709 Timer Tick", -- .flags = IRQF_TIMER | IRQF_IRQPOLL, -- .handler = bcm2709_timer_interrupt, --}; -- --/* -- * Set up timer interrupt, and return the current time in seconds. -- */ -- --static struct delay_timer bcm2709_delay_timer = { -- .read_current_timer = bcm2709_read_current_timer, -- .freq = STC_FREQ_HZ, --}; -- --static void __init bcm2709_timer_init(void) --{ -- /* init high res timer */ -- bcm2709_clocksource_init(); -- -- /* -- * Make irqs happen for the system timer -- */ -- setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); -- -- sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); -- -- timer0_clockevent.mult = -- div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -- timer0_clockevent.max_delta_ns = -- clockevent_delta2ns(0xffffffff, &timer0_clockevent); -- timer0_clockevent.min_delta_ns = -- clockevent_delta2ns(0xf, &timer0_clockevent); -- -- timer0_clockevent.cpumask = cpumask_of(0); -- clockevents_register_device(&timer0_clockevent); -- -- register_current_timer_delay(&bcm2709_delay_timer); --} -- --#else -- - static void __init bcm2709_timer_init(void) - { - // timer control -@@ -376,7 +220,6 @@ static void __init bcm2709_timer_init(void) - clocksource_probe(); - } - --#endif - - void __init bcm2709_init_early(void) - { -@@ -397,7 +240,6 @@ static void __init board_reserve(void) - #ifdef CONFIG_SMP - #include - --#include - #include - #include - int dc4=0; -@@ -511,7 +353,6 @@ MACHINE_START(BCM2709, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -- .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -526,7 +367,6 @@ MACHINE_START(BCM2708, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -- .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -535,7 +375,6 @@ MACHINE_START(BCM2708, "BCM2709") - .dt_compat = bcm2709_compat, - MACHINE_END - --module_param(force_core, uint, 0644); - module_param(boardrev, uint, 0644); - module_param(serial, uint, 0644); - module_param(reboot_part, uint, 0644); -diff --git a/arch/arm/mach-bcm2709/include/mach/arm_control.h b/arch/arm/mach-bcm2709/include/mach/arm_control.h -deleted file mode 100644 -index e346caf..0000000 ---- a/arch/arm/mach-bcm2709/include/mach/arm_control.h -+++ /dev/null -@@ -1,493 +0,0 @@ --/* -- * linux/arch/arm/mach-bcm2708/arm_control.h -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ -- --#ifndef __BCM2708_ARM_CONTROL_H --#define __BCM2708_ARM_CONTROL_H -- --/* -- * Definitions and addresses for the ARM CONTROL logic -- * This file is manually generated. -- */ -- --#define ARM_BASE 0x7E00B000 -- --/* Basic configuration */ --#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) --#define ARM_C0_SIZ128M 0x00000000 --#define ARM_C0_SIZ256M 0x00000001 --#define ARM_C0_SIZ512M 0x00000002 --#define ARM_C0_SIZ1G 0x00000003 --#define ARM_C0_BRESP0 0x00000000 --#define ARM_C0_BRESP1 0x00000004 --#define ARM_C0_BRESP2 0x00000008 --#define ARM_C0_BOOTHI 0x00000010 --#define ARM_C0_UNUSED05 0x00000020 /* free */ --#define ARM_C0_FULLPERI 0x00000040 --#define ARM_C0_UNUSED78 0x00000180 /* free */ --#define ARM_C0_JTAGMASK 0x00000E00 --#define ARM_C0_JTAGOFF 0x00000000 --#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ --#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ --#define ARM_C0_APROTMSK 0x0000F000 --#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ --#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ --#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ --#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ --#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ --#define ARM_C0_PRIO_L2 0x0F000000 --#define ARM_C0_PRIO_UC 0xF0000000 -- --#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ --#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ --#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -- -- --#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) --#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ --#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ --#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ --#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ --#define ARM_C1_PERSON 0x00000100 /* peripherals on */ --#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -- --#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) --#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ --#define ARM_S_READPEND 0x000003FF /* pending reads counter */ --#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -- --#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) --#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ --#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ --#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ --#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ --#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ --#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -- --#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) --#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) --#define ARM_IDVAL 0x364D5241 -- --/* Translation memory */ --#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) --/* 32 locations: 0x100.. 0x17F */ --/* 32 spare means we CAN go to 64 pages.... */ -- -- --/* Interrupts */ --#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ --#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ --#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ --#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ --#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ --#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ --#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -- --#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ --/* todo: all I1_interrupt sources */ --#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ --/* todo: all I2_interrupt sources */ -- --#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ --#define ARM_IF_INDEX 0x0000007F /* FIQ select */ --#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ --#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ --#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ --#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ --#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ --#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ --#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ --#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ --#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -- --#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ --#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ --#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ --#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ --#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ --#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ --#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ --#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ --#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ --#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ --#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ --#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ --#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -- --/* Timer */ --/* For reg. fields see sp804 spec. */ --#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) --#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) --#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) --#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) --#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) --#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) --#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) --#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) --#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -- --#define TIMER_CTRL_ONESHOT (1 << 0) --#define TIMER_CTRL_32BIT (1 << 1) --#define TIMER_CTRL_DIV1 (0 << 2) --#define TIMER_CTRL_DIV16 (1 << 2) --#define TIMER_CTRL_DIV256 (2 << 2) --#define TIMER_CTRL_IE (1 << 5) --#define TIMER_CTRL_PERIODIC (1 << 6) --#define TIMER_CTRL_ENABLE (1 << 7) --#define TIMER_CTRL_DBGHALT (1 << 8) --#define TIMER_CTRL_ENAFREE (1 << 9) --#define TIMER_CTRL_FREEDIV_SHIFT 16) --#define TIMER_CTRL_FREEDIV_MASK 0xff -- --/* Semaphores, Doorbells, Mailboxes */ --#define ARM_SBM_OWN0 (ARM_BASE+0x800) --#define ARM_SBM_OWN1 (ARM_BASE+0x900) --#define ARM_SBM_OWN2 (ARM_BASE+0xA00) --#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -- --/* MAILBOXES -- * Register flags are common across all -- * owner registers. See end of this section -- * -- * Semaphores, Doorbells, Mailboxes Owner 0 -- * -- */ -- --#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) --#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) --#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) --#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) --#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) --#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) --#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) --#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) --#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) --#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) --#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) --#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) --#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) --/* MAILBOX 0 access in Owner 0 area */ --/* Some addresses should ONLY be used by owner 0 */ --#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ --#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ --#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ --#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ --#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ --#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ --/* MAILBOX 1 access in Owner 0 area */ --/* Owner 0 should only WRITE to this mailbox */ --#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ --/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ --#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ --/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ --/* General SEM, BELL, MAIL config/status */ --#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ --#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ --#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ --#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -- --/* Semaphores, Doorbells, Mailboxes Owner 1 */ --#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) --#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) --#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) --#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) --#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) --#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) --#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) --#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) --#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) --#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) --#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) --#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) --#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) --/* MAILBOX 0 access in Owner 0 area */ --/* Owner 1 should only WRITE to this mailbox */ --#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ --/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ --#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ --/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ --/* MAILBOX 1 access in Owner 0 area */ --#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ --#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ --#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ --#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ --#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ --#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) --/* General SEM, BELL, MAIL config/status */ --#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ --#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ --#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ --#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -- --/* Semaphores, Doorbells, Mailboxes Owner 2 */ --#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) --#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) --#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) --#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) --#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) --#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) --#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) --#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) --#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) --#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) --#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) --#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) --#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) --/* MAILBOX 0 access in Owner 2 area */ --/* Owner 2 should only WRITE to this mailbox */ --#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ --/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ --#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ --/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ --/* MAILBOX 1 access in Owner 2 area */ --/* Owner 2 should only WRITE to this mailbox */ --#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ --/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ --#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ --/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ --/* General SEM, BELL, MAIL config/status */ --#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ --#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ --#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ --#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -- --/* Semaphores, Doorbells, Mailboxes Owner 3 */ --#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) --#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) --#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) --#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) --#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) --#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) --#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) --#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) --#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) --#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) --#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) --#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) --#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) --/* MAILBOX 0 access in Owner 3 area */ --/* Owner 3 should only WRITE to this mailbox */ --#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ --/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ --#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ --/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ --/* MAILBOX 1 access in Owner 3 area */ --/* Owner 3 should only WRITE to this mailbox */ --#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ --/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ --#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ --/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ --/* General SEM, BELL, MAIL config/status */ --#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ --#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ --#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ --#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -- -- -- --/* Mailbox flags. Valid for all owners */ -- --/* Mailbox status register (...0x98) */ --#define ARM_MS_FULL 0x80000000 --#define ARM_MS_EMPTY 0x40000000 --#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -- --/* MAILBOX config/status register (...0x9C) */ --/* ANY write to this register clears the error bits! */ --#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ --#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ --#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ --#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ --#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ --#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ --#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ --/* Bit 7 is unused */ --#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ --#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ --#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -- --/* Semaphore clear/debug register (...0xE0) */ --#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ --#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ --#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ --#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ --#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ --#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ --#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ --#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ --#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ --#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ --#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ --#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ --#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ --#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ --#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ --#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -- --/* Doorbells clear/debug register (...0xE4) */ --#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ --#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ --#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ --#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ --#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ --#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ --#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ --#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -- --/* MY IRQS register (...0xF8) */ --#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ --#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -- --/* ALL IRQS register (...0xF8) */ --#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ --#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ --#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ --#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ --#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ --#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ --#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ --#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ --#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ --#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ --/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ --/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ --/* */ --/* ARM JTAG BASH */ --/* */ --#define AJB_BASE 0x7e2000c0 -- --#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) --#define AJB_BITS0 0x000000 --#define AJB_BITS4 0x000004 --#define AJB_BITS8 0x000008 --#define AJB_BITS12 0x00000C --#define AJB_BITS16 0x000010 --#define AJB_BITS20 0x000014 --#define AJB_BITS24 0x000018 --#define AJB_BITS28 0x00001C --#define AJB_BITS32 0x000020 --#define AJB_BITS34 0x000022 --#define AJB_OUT_MS 0x000040 --#define AJB_OUT_LS 0x000000 --#define AJB_INV_CLK 0x000080 --#define AJB_D0_RISE 0x000100 --#define AJB_D0_FALL 0x000000 --#define AJB_D1_RISE 0x000200 --#define AJB_D1_FALL 0x000000 --#define AJB_IN_RISE 0x000400 --#define AJB_IN_FALL 0x000000 --#define AJB_ENABLE 0x000800 --#define AJB_HOLD0 0x000000 --#define AJB_HOLD1 0x001000 --#define AJB_HOLD2 0x002000 --#define AJB_HOLD3 0x003000 --#define AJB_RESETN 0x004000 --#define AJB_CLKSHFT 16 --#define AJB_BUSY 0x80000000 --#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) --#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) --#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -- --#define ARM_LOCAL_BASE 0x40000000 --#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) --#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) --#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) --#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) --#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) --#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) --#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) --#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) --#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) --#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) --#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) --#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -- --#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) --#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) --#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) --#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -- --#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) --#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) --#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) --#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -- --#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) --#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) --#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) --#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -- --#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) --#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) --#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) --#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -- --#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) --#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) --#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) --#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -- --#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) --#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) --#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) --#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -- --#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) --#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) --#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) --#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -- --#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) --#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) --#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) --#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -- --#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) --#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) --#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) --#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -- --#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) --#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) --#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) --#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -- --#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) --#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) --#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) --#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -- --#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) --#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) --#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) --#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -- --#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/hardware.h b/arch/arm/mach-bcm2709/include/mach/hardware.h -deleted file mode 100644 -index c2954e8..0000000 ---- a/arch/arm/mach-bcm2709/include/mach/hardware.h -+++ /dev/null -@@ -1,28 +0,0 @@ --/* -- * arch/arm/mach-bcm2708/include/mach/hardware.h -- * -- * This file contains the hardware definitions of the BCM2708 devices. -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ --#ifndef __ASM_ARCH_HARDWARE_H --#define __ASM_ARCH_HARDWARE_H -- --#include --#include -- --#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/irqs.h b/arch/arm/mach-bcm2709/include/mach/irqs.h -deleted file mode 100644 -index d301f06..0000000 ---- a/arch/arm/mach-bcm2709/include/mach/irqs.h -+++ /dev/null -@@ -1,225 +0,0 @@ --/* -- * arch/arm/mach-bcm2708/include/mach/irqs.h -- * -- * Copyright (C) 2010 Broadcom -- * Copyright (C) 2003 ARM Limited -- * Copyright (C) 2000 Deep Blue Solutions Ltd. -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ -- --#ifndef _BCM2708_IRQS_H_ --#define _BCM2708_IRQS_H_ -- --#include -- --/* -- * IRQ interrupts definitions are the same as the INT definitions -- * held within platform.h -- */ --#define IRQ_ARMCTRL_START 0 --#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) --#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) --#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) --#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) --#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) --#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) --#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) --#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) --#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) --#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) --#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) --#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) --#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) --#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) --#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) --#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) --#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) --#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) --#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) --#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) --#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) --#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) --#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) --#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) --#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) --#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) --#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) --#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) --#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) --#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) --#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) --#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) --#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) --#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) --#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) --#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) --#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) --#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) --#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) --#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) --#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) --#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) --#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) --#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) --#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) --#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) --#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) --#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) --#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) --#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) --#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) --#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) --#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) --#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) --#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) --#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) --#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) --#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) --#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) --#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) --#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) --#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) --#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) --#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -- --#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) --#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) --#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) --#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) --#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) --#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) --#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) --#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) --#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) --#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -- --#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) --#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) --#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) --#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) --#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) --#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) --#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) --#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) --#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) --#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) --#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) --#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -- --#define FIQ_START HARD_IRQS -- --/* -- * FIQ interrupts definitions are the same as the INT definitions. -- */ --#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) --#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) --#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) --#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) --#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) --#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) --#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) --#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) --#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) --#define FIQ_USB (FIQ_START+INTERRUPT_USB) --#define FIQ_3D (FIQ_START+INTERRUPT_3D) --#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) --#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) --#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) --#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) --#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) --#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) --#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) --#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) --#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) --#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) --#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) --#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) --#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) --#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) --#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) --#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) --#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) --#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) --#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) --#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) --#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) --#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) --#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) --#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) --#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) --#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) --#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) --#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) --#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) --#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) --#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) --#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) --#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) --#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) --#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) --#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) --#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) --#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) --#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) --#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) --#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) --#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) --#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) --#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) --#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) --#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) --#define FIQ_UART (FIQ_START+INTERRUPT_UART) --#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) --#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) --#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) --#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) --#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) --#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -- --#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) --#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) --#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) --#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) --#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) --#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) --#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) --#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) --#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) --#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -- --#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) --#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) --#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) --#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) --#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) --#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) --#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) --#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) --#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) --#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) --#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) --#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -- --#define HARD_IRQS (128) --#define FIQ_IRQS (128) --#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) --#define GPIO_IRQS (32*5) --#define SPARE_ALLOC_IRQS 64 --#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) --#define FREE_IRQS 128 --#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -- --#endif /* _BCM2708_IRQS_H_ */ -diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h -index be99733..9a638f5 100644 ---- a/arch/arm/mach-bcm2709/include/mach/platform.h -+++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -47,9 +47,6 @@ - #define HW_REGISTER_RW(addr) (addr) - #define HW_REGISTER_RO(addr) (addr) - --#include "arm_control.h" --#undef ARM_BASE -- - /* - * Definitions and addresses for the ARM CONTROL logic - * This file is manually generated. -@@ -84,116 +81,6 @@ - #define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ - #define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ - -- --/* -- * Interrupt assignments -- */ -- --#define ARM_IRQ1_BASE 0 --#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) --#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) --#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) --#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) --#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) --#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) --#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) --#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) --#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) --#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) --#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) --#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) --#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) --#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) --#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) --#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) --#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) --#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) --#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) --#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) --#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) --#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) --#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) --#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) --#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) --#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) --#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) --#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) --#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) --#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) --#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) --#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -- --#define ARM_IRQ2_BASE 32 --#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) --#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) --#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) --#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) --#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) --#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) --#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) --#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) --#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) --#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) --#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) --#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) --#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) --#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) --#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) --#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) --#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) --#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) --#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) --#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) --#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) --#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) --#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) --#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) --#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) --#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) --#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) --#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) --#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) --#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) --#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) --#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -- --#define ARM_IRQ0_BASE 64 --#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) --#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) --#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) --#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) --#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) --#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) --#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) --#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) --#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) --#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) --#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) --#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) --#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) --#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) --#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) --#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) --#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) --#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) --#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) --#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) --#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -- --#define ARM_IRQ_LOCAL_BASE 96 --#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) --#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) --#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) --#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) --#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) --#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) --#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) --#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) --#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) --#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) --#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) --#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) -- - /* - * Watchdog - */ -@@ -222,6 +109,82 @@ - - #define UART0_CLOCK 3000000 - -+#define ARM_LOCAL_BASE 0x40000000 -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+ -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) -+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) -+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) -+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) -+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) -+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) -+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) -+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) -+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) -+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) -+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -+ -+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) -+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) -+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) -+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -+ -+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -+ -+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) -+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) -+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) -+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -+ -+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) -+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) -+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) -+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -+ -+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) -+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) -+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) -+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -+ -+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) -+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) -+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) -+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -+ -+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) -+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) -+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) -+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -+ -+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) -+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) -+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) -+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) -+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) -+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) -+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) -+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) -+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) -+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) -+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) -+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) -+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) -+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) -+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) -+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -+ - #endif - - /* END */ -diff --git a/arch/arm/mach-bcm2709/include/mach/system.h b/arch/arm/mach-bcm2709/include/mach/system.h -index 2d0b821..c9a9c9a 100644 ---- a/arch/arm/mach-bcm2709/include/mach/system.h -+++ b/arch/arm/mach-bcm2709/include/mach/system.h -@@ -23,7 +23,6 @@ - #define __ASM_ARCH_SYSTEM_H - - #include --#include - #include - - static inline void arch_idle(void) -diff --git a/arch/arm/mach-bcm2709/include/mach/uncompress.h b/arch/arm/mach-bcm2709/include/mach/uncompress.h -index d634813..de7504b 100644 ---- a/arch/arm/mach-bcm2709/include/mach/uncompress.h -+++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h -@@ -21,7 +21,7 @@ - - #include - #include --#include -+#include - - #define UART_BAUD 115200 - -diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index 27b8467..26f1357d 100644 ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o - obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o -+obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o - obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o - obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o - obj-$(CONFIG_ARCH_MMP) += irq-mmp.o --- -2.5.0 - - -From d3425970052fa52673d1ff7dc72c7f234104ab97 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Mon, 16 Nov 2015 12:30:32 +0000 -Subject: [PATCH 34/78] BCM270X_DT: Enable the watchdog - -Although enabled, the watchdog remains idle until started with a -privileged access to /dev/watchdog, e.g. 'sudo touch /dev/watchdog.' -Once activated, the watchdog must be restarted before the timeout -expires. The default timeout is 16 seconds. ---- - arch/arm/boot/dts/bcm2708.dtsi | 4 ++++ - arch/arm/boot/dts/bcm2709.dtsi | 4 ++++ - 2 files changed, 8 insertions(+) - -diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi -index 0bea715..42acf77 100644 ---- a/arch/arm/boot/dts/bcm2708.dtsi -+++ b/arch/arm/boot/dts/bcm2708.dtsi -@@ -34,3 +34,7 @@ - &intc { - compatible = "brcm,bcm2835-armctrl-ic"; - }; -+ -+&watchdog { -+ status = "okay"; -+}; -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index 811d825..d21f5f0 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -74,3 +74,7 @@ - <&v7_cpu3>, "clock-frequency:0"; - }; - }; -+ -+&watchdog { -+ status = "okay"; -+}; --- -2.5.0 - - -From 2d6c63ed3b57a9e9e81c71ee04f9b26df36f4097 Mon Sep 17 00:00:00 2001 +From a6a43f492a980a33e31d3960f1709defd6f1bd7b Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 11 Nov 2015 11:38:59 +0000 -Subject: [PATCH 35/78] scripts: Multi-platform support for mkknlimg and +Subject: [PATCH 29/59] scripts: Multi-platform support for mkknlimg and knlinfo The firmware uses tags in the kernel trailer to choose which dtb file @@ -133678,1794 +129997,10 @@ index 3998d43..005f404 100755 2.5.0 -From cd7abc5b2e4bedbddc1240f2ffd0cd7ca3561920 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 17 Nov 2015 19:19:39 +0000 -Subject: [PATCH 36/78] Revert "BCM2709: Use upstream interrupt driver on all - Pi2's" - -This reverts commit fca5c033265716e4471d14ffa0875476290bbcc3. ---- - arch/arm/Kconfig | 2 - - arch/arm/mach-bcm2709/Makefile | 2 +- - arch/arm/mach-bcm2709/armctrl.c | 384 ++++++++++++++++++ - arch/arm/mach-bcm2709/armctrl.h | 27 ++ - arch/arm/mach-bcm2709/bcm2709.c | 167 +++++++- - arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 +++++++++++++++++++++++ - arch/arm/mach-bcm2709/include/mach/hardware.h | 28 ++ - arch/arm/mach-bcm2709/include/mach/irqs.h | 225 +++++++++++ - arch/arm/mach-bcm2709/include/mach/platform.h | 189 +++++---- - arch/arm/mach-bcm2709/include/mach/system.h | 1 + - arch/arm/mach-bcm2709/include/mach/uncompress.h | 2 +- - drivers/irqchip/Makefile | 1 - - 12 files changed, 1437 insertions(+), 84 deletions(-) - create mode 100644 arch/arm/mach-bcm2709/armctrl.c - create mode 100644 arch/arm/mach-bcm2709/armctrl.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 601b520..3241611 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -351,8 +351,6 @@ config ARCH_BCM2709 - select ARCH_HAS_CPUFREQ - select GENERIC_CLOCKEVENTS - select MACH_BCM2709 -- select MULTI_IRQ_HANDLER -- select SPARSE_IRQ - select VC4 - select FIQ - select USE_OF -diff --git a/arch/arm/mach-bcm2709/Makefile b/arch/arm/mach-bcm2709/Makefile -index 26cd67d..11ad846 100644 ---- a/arch/arm/mach-bcm2709/Makefile -+++ b/arch/arm/mach-bcm2709/Makefile -@@ -2,4 +2,4 @@ - # Makefile for the linux kernel. - # - --obj-$(CONFIG_MACH_BCM2709) += bcm2709.o -+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -new file mode 100644 -index 0000000..fb82f7d ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -0,0 +1,384 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "armctrl.h" -+ -+/* For support of kernels >= 3.0 assume only one VIC for now*/ -+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -+ INTERRUPT_VC_JPEG, -+ INTERRUPT_VC_USB, -+ INTERRUPT_VC_3D, -+ INTERRUPT_VC_DMA2, -+ INTERRUPT_VC_DMA3, -+ INTERRUPT_VC_I2C, -+ INTERRUPT_VC_SPI, -+ INTERRUPT_VC_I2SPCM, -+ INTERRUPT_VC_SDIO, -+ INTERRUPT_VC_UART, -+ INTERRUPT_VC_ARASANSDIO -+}; -+ -+extern unsigned force_core; -+ -+static void armctrl_mask_irq(struct irq_data *d) -+{ -+ static const unsigned int disables[4] = { -+ ARM_IRQ_DIBL1, -+ ARM_IRQ_DIBL2, -+ ARM_IRQ_DIBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ writel(0, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); // -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+static void armctrl_unmask_irq(struct irq_data *d) -+{ -+ static const unsigned int enables[4] = { -+ ARM_IRQ_ENBL1, -+ ARM_IRQ_ENBL2, -+ ARM_IRQ_ENBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ unsigned int data; -+ if (force_core) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= ((force_core-1) << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ else if (num_online_cpus() > 1) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= (1 << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ /* Unmask in ARMCTRL block after routing it properly */ -+ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ if (force_core) { -+ unsigned int data; -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0x3; -+ data |= ((force_core-1) << 0); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+#ifdef CONFIG_OF -+ -+#define NR_IRQS_BANK0 21 -+#define NR_BANKS 4 -+#define IRQS_PER_BANK 32 -+ -+/* from drivers/irqchip/irq-bcm2835.c */ -+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -+ const u32 *intspec, unsigned int intsize, -+ unsigned long *out_hwirq, unsigned int *out_type) -+{ -+ if (WARN_ON(intsize != 2)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] >= NR_BANKS)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) -+ return -EINVAL; -+ -+ if (intspec[0] == 0) -+ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -+ else if (intspec[0] == 1) -+ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -+ else if (intspec[0] == 2) -+ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -+ else -+ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; -+ -+ /* reverse remap_irqs[] */ -+ switch (*out_hwirq) { -+ case INTERRUPT_VC_JPEG: -+ *out_hwirq = INTERRUPT_JPEG; -+ break; -+ case INTERRUPT_VC_USB: -+ *out_hwirq = INTERRUPT_USB; -+ break; -+ case INTERRUPT_VC_3D: -+ *out_hwirq = INTERRUPT_3D; -+ break; -+ case INTERRUPT_VC_DMA2: -+ *out_hwirq = INTERRUPT_DMA2; -+ break; -+ case INTERRUPT_VC_DMA3: -+ *out_hwirq = INTERRUPT_DMA3; -+ break; -+ case INTERRUPT_VC_I2C: -+ *out_hwirq = INTERRUPT_I2C; -+ break; -+ case INTERRUPT_VC_SPI: -+ *out_hwirq = INTERRUPT_SPI; -+ break; -+ case INTERRUPT_VC_I2SPCM: -+ *out_hwirq = INTERRUPT_I2SPCM; -+ break; -+ case INTERRUPT_VC_SDIO: -+ *out_hwirq = INTERRUPT_SDIO; -+ break; -+ case INTERRUPT_VC_UART: -+ *out_hwirq = INTERRUPT_UART; -+ break; -+ case INTERRUPT_VC_ARASANSDIO: -+ *out_hwirq = INTERRUPT_ARASANSDIO; -+ break; -+ } -+ -+ *out_type = IRQ_TYPE_NONE; -+ return 0; -+} -+ -+static struct irq_domain_ops armctrl_ops = { -+ .xlate = armctrl_xlate -+}; -+ -+void __init armctrl_dt_init(void) -+{ -+ struct device_node *np; -+ struct irq_domain *domain; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -+ if (!np) -+ return; -+ -+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -+ IRQ_ARMCTRL_START, 0, -+ &armctrl_ops, NULL); -+ WARN_ON(!domain); -+} -+#else -+void __init armctrl_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+#if defined(CONFIG_PM) -+ -+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -+ -+/* Static defines -+ * struct armctrl_device - VIC PM device (< 3.xx) -+ * @sysdev: The system device which is registered. (< 3.xx) -+ * @irq: The IRQ number for the base of the VIC. -+ * @base: The register base for the VIC. -+ * @resume_sources: A bitmask of interrupts for resume. -+ * @resume_irqs: The IRQs enabled for resume. -+ * @int_select: Save for VIC_INT_SELECT. -+ * @int_enable: Save for VIC_INT_ENABLE. -+ * @soft_int: Save for VIC_INT_SOFT. -+ * @protect: Save for VIC_PROTECT. -+ */ -+struct armctrl_info { -+ void __iomem *base; -+ int irq; -+ u32 resume_sources; -+ u32 resume_irqs; -+ u32 int_select; -+ u32 int_enable; -+ u32 soft_int; -+ u32 protect; -+} armctrl; -+ -+static int armctrl_suspend(void) -+{ -+ return 0; -+} -+ -+static void armctrl_resume(void) -+{ -+ return; -+} -+ -+/** -+ * armctrl_pm_register - Register a VIC for later power management control -+ * @base: The base address of the VIC. -+ * @irq: The base IRQ for the VIC. -+ * @resume_sources: bitmask of interrupts allowed for resume sources. -+ * -+ * For older kernels (< 3.xx) do - -+ * Register the VIC with the system device tree so that it can be notified -+ * of suspend and resume requests and ensure that the correct actions are -+ * taken to re-instate the settings on resume. -+ */ -+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 resume_sources) -+{ -+ armctrl.base = base; -+ armctrl.resume_sources = resume_sources; -+ armctrl.irq = irq; -+} -+ -+static int armctrl_set_wake(struct irq_data *d, unsigned int on) -+{ -+ unsigned int off = d->irq & 31; -+ u32 bit = 1 << off; -+ -+ if (!(bit & armctrl.resume_sources)) -+ return -EINVAL; -+ -+ if (on) -+ armctrl.resume_irqs |= bit; -+ else -+ armctrl.resume_irqs &= ~bit; -+ -+ return 0; -+} -+ -+#else -+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 arg1) -+{ -+} -+ -+#define armctrl_suspend NULL -+#define armctrl_resume NULL -+#define armctrl_set_wake NULL -+#endif /* CONFIG_PM */ -+ -+static struct syscore_ops armctrl_syscore_ops = { -+ .suspend = armctrl_suspend, -+ .resume = armctrl_resume, -+}; -+ -+/** -+ * armctrl_syscore_init - initicall to register VIC pm functions -+ * -+ * This is called via late_initcall() to register -+ * the resources for the VICs due to the early -+ * nature of the VIC's registration. -+*/ -+static int __init armctrl_syscore_init(void) -+{ -+ register_syscore_ops(&armctrl_syscore_ops); -+ return 0; -+} -+ -+late_initcall(armctrl_syscore_init); -+ -+static struct irq_chip armctrl_chip = { -+ .name = "ARMCTRL", -+ .irq_ack = NULL, -+ .irq_mask = armctrl_mask_irq, -+ .irq_unmask = armctrl_unmask_irq, -+ .irq_set_wake = armctrl_set_wake, -+}; -+ -+/** -+ * armctrl_init - initialise a vectored interrupt controller -+ * @base: iomem base address -+ * @irq_start: starting interrupt number, must be muliple of 32 -+ * @armctrl_sources: bitmask of interrupt sources to allow -+ * @resume_sources: bitmask of interrupt sources to allow for resume -+ */ -+int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources) -+{ -+ unsigned int irq; -+ -+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -+ unsigned int data = irq; -+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -+ data = remap_irqs[irq - INTERRUPT_JPEG]; -+ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { -+ irq_set_percpu_devid(irq); -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ } else { -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); -+ irq_set_probe(irq); -+ } -+ irq_set_chip_data(irq, (void *)data); -+ } -+ -+ armctrl_pm_register(base, irq_start, resume_sources); -+ init_FIQ(FIQ_START); -+ armctrl_dt_init(); -+ return 0; -+} -diff --git a/arch/arm/mach-bcm2709/armctrl.h b/arch/arm/mach-bcm2709/armctrl.h -new file mode 100644 -index 0000000..0aa916e ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.h -@@ -0,0 +1,27 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARMCTRL_H -+#define __BCM2708_ARMCTRL_H -+ -+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources); -+ -+#endif -diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c -index 90773a3..cbcf731 100644 ---- a/arch/arm/mach-bcm2709/bcm2709.c -+++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -28,16 +28,20 @@ - #include - - #include -+#include - #include - #include - - #include - #include -- - #include - -+#include "armctrl.h" -+ - #include - -+//#define SYSTEM_TIMER -+ - /* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to - * give us IO access only to 64Mbytes of physical memory (26 bits). We could - * represent this window by setting our dmamasks to 26 bits but, in fact -@@ -52,6 +56,12 @@ - /* command line parameters */ - static unsigned boardrev, serial; - static unsigned reboot_part = 0; -+unsigned force_core; -+ -+void __init bcm2709_init_irq(void) -+{ -+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); -+} - - static struct map_desc bcm2709_io_desc[] __initdata = { - { -@@ -111,6 +121,54 @@ void __init bcm2709_map_io(void) - iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); - } - -+#ifdef SYSTEM_TIMER -+ -+/* The STC is a free running counter that increments at the rate of 1MHz */ -+#define STC_FREQ_HZ 1000000 -+ -+static inline uint32_t timer_read(void) -+{ -+ /* STC: a free running counter that increments at the rate of 1MHz */ -+ return readl(__io_address(ST_BASE + 0x04)); -+} -+ -+static unsigned long bcm2709_read_current_timer(void) -+{ -+ return timer_read(); -+} -+ -+static u64 notrace bcm2709_read_sched_clock(void) -+{ -+ return timer_read(); -+} -+ -+static cycle_t clksrc_read(struct clocksource *cs) -+{ -+ return timer_read(); -+} -+ -+static struct clocksource clocksource_stc = { -+ .name = "stc", -+ .rating = 300, -+ .read = clksrc_read, -+ .mask = CLOCKSOURCE_MASK(32), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+unsigned long frc_clock_ticks32(void) -+{ -+ return timer_read(); -+} -+ -+static void __init bcm2709_clocksource_init(void) -+{ -+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -+ printk(KERN_ERR "timer: failed to initialize clock " -+ "source %s\n", clocksource_stc.name); -+ } -+} -+#endif -+ - int calc_rsts(int partition) - { - return PM_PASSWORD | -@@ -195,8 +253,7 @@ void __init bcm2709_init(void) - - pm_power_off = bcm2709_power_off; - -- ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, -- NULL); -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - if (ret) { - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); -@@ -208,6 +265,105 @@ void __init bcm2709_init(void) - system_serial_low = serial; - } - -+#ifdef SYSTEM_TIMER -+static void timer_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *clk) -+{ -+ switch (mode) { -+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ break; -+ case CLOCK_EVT_MODE_PERIODIC: -+ -+ case CLOCK_EVT_MODE_UNUSED: -+ case CLOCK_EVT_MODE_RESUME: -+ -+ default: -+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -+ (int)mode); -+ break; -+ } -+ -+} -+ -+static int timer_set_next_event(unsigned long cycles, -+ struct clock_event_device *unused) -+{ -+ unsigned long stc; -+ do { -+ stc = readl(__io_address(ST_BASE + 0x04)); -+ /* We could take a FIQ here, which may push ST above STC3 */ -+ writel(stc + cycles, __io_address(ST_BASE + 0x18)); -+ } while ((signed long) cycles >= 0 && -+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -+ >= (signed long) cycles); -+ return 0; -+} -+ -+static struct clock_event_device timer0_clockevent = { -+ .name = "timer0", -+ .shift = 32, -+ .features = CLOCK_EVT_FEAT_ONESHOT, -+ .set_mode = timer_set_mode, -+ .set_next_event = timer_set_next_event, -+}; -+ -+/* -+ * IRQ handler for the timer -+ */ -+static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) -+{ -+ struct clock_event_device *evt = &timer0_clockevent; -+ -+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -+ -+ evt->event_handler(evt); -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction bcm2709_timer_irq = { -+ .name = "BCM2709 Timer Tick", -+ .flags = IRQF_TIMER | IRQF_IRQPOLL, -+ .handler = bcm2709_timer_interrupt, -+}; -+ -+/* -+ * Set up timer interrupt, and return the current time in seconds. -+ */ -+ -+static struct delay_timer bcm2709_delay_timer = { -+ .read_current_timer = bcm2709_read_current_timer, -+ .freq = STC_FREQ_HZ, -+}; -+ -+static void __init bcm2709_timer_init(void) -+{ -+ /* init high res timer */ -+ bcm2709_clocksource_init(); -+ -+ /* -+ * Make irqs happen for the system timer -+ */ -+ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); -+ -+ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); -+ -+ timer0_clockevent.mult = -+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -+ timer0_clockevent.max_delta_ns = -+ clockevent_delta2ns(0xffffffff, &timer0_clockevent); -+ timer0_clockevent.min_delta_ns = -+ clockevent_delta2ns(0xf, &timer0_clockevent); -+ -+ timer0_clockevent.cpumask = cpumask_of(0); -+ clockevents_register_device(&timer0_clockevent); -+ -+ register_current_timer_delay(&bcm2709_delay_timer); -+} -+ -+#else -+ - static void __init bcm2709_timer_init(void) - { - // timer control -@@ -220,6 +376,7 @@ static void __init bcm2709_timer_init(void) - clocksource_probe(); - } - -+#endif - - void __init bcm2709_init_early(void) - { -@@ -240,6 +397,7 @@ static void __init board_reserve(void) - #ifdef CONFIG_SMP - #include - -+#include - #include - #include - int dc4=0; -@@ -353,6 +511,7 @@ MACHINE_START(BCM2709, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -367,6 +526,7 @@ MACHINE_START(BCM2708, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -375,6 +535,7 @@ MACHINE_START(BCM2708, "BCM2709") - .dt_compat = bcm2709_compat, - MACHINE_END - -+module_param(force_core, uint, 0644); - module_param(boardrev, uint, 0644); - module_param(serial, uint, 0644); - module_param(reboot_part, uint, 0644); -diff --git a/arch/arm/mach-bcm2709/include/mach/arm_control.h b/arch/arm/mach-bcm2709/include/mach/arm_control.h -new file mode 100644 -index 0000000..e346caf ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h -@@ -0,0 +1,493 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/arm_control.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARM_CONTROL_H -+#define __BCM2708_ARM_CONTROL_H -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define ARM_BASE 0x7E00B000 -+ -+/* Basic configuration */ -+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) -+#define ARM_C0_SIZ128M 0x00000000 -+#define ARM_C0_SIZ256M 0x00000001 -+#define ARM_C0_SIZ512M 0x00000002 -+#define ARM_C0_SIZ1G 0x00000003 -+#define ARM_C0_BRESP0 0x00000000 -+#define ARM_C0_BRESP1 0x00000004 -+#define ARM_C0_BRESP2 0x00000008 -+#define ARM_C0_BOOTHI 0x00000010 -+#define ARM_C0_UNUSED05 0x00000020 /* free */ -+#define ARM_C0_FULLPERI 0x00000040 -+#define ARM_C0_UNUSED78 0x00000180 /* free */ -+#define ARM_C0_JTAGMASK 0x00000E00 -+#define ARM_C0_JTAGOFF 0x00000000 -+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ -+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ -+#define ARM_C0_APROTMSK 0x0000F000 -+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ -+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ -+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ -+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ -+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ -+#define ARM_C0_PRIO_L2 0x0F000000 -+#define ARM_C0_PRIO_UC 0xF0000000 -+ -+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ -+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ -+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -+ -+ -+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) -+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ -+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ -+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ -+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ -+#define ARM_C1_PERSON 0x00000100 /* peripherals on */ -+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -+ -+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) -+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ -+#define ARM_S_READPEND 0x000003FF /* pending reads counter */ -+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -+ -+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) -+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ -+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ -+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ -+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ -+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ -+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -+ -+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) -+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) -+#define ARM_IDVAL 0x364D5241 -+ -+/* Translation memory */ -+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) -+/* 32 locations: 0x100.. 0x17F */ -+/* 32 spare means we CAN go to 64 pages.... */ -+ -+ -+/* Interrupts */ -+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ -+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ -+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ -+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -+ -+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ -+/* todo: all I1_interrupt sources */ -+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ -+/* todo: all I2_interrupt sources */ -+ -+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ -+#define ARM_IF_INDEX 0x0000007F /* FIQ select */ -+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ -+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ -+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ -+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ -+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ -+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ -+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ -+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ -+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -+ -+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ -+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ -+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ -+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ -+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ -+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ -+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ -+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ -+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ -+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -+ -+/* Timer */ -+/* For reg. fields see sp804 spec. */ -+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) -+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) -+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) -+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) -+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) -+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) -+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) -+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) -+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -+ -+#define TIMER_CTRL_ONESHOT (1 << 0) -+#define TIMER_CTRL_32BIT (1 << 1) -+#define TIMER_CTRL_DIV1 (0 << 2) -+#define TIMER_CTRL_DIV16 (1 << 2) -+#define TIMER_CTRL_DIV256 (2 << 2) -+#define TIMER_CTRL_IE (1 << 5) -+#define TIMER_CTRL_PERIODIC (1 << 6) -+#define TIMER_CTRL_ENABLE (1 << 7) -+#define TIMER_CTRL_DBGHALT (1 << 8) -+#define TIMER_CTRL_ENAFREE (1 << 9) -+#define TIMER_CTRL_FREEDIV_SHIFT 16) -+#define TIMER_CTRL_FREEDIV_MASK 0xff -+ -+/* Semaphores, Doorbells, Mailboxes */ -+#define ARM_SBM_OWN0 (ARM_BASE+0x800) -+#define ARM_SBM_OWN1 (ARM_BASE+0x900) -+#define ARM_SBM_OWN2 (ARM_BASE+0xA00) -+#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -+ -+/* MAILBOXES -+ * Register flags are common across all -+ * owner registers. See end of this section -+ * -+ * Semaphores, Doorbells, Mailboxes Owner 0 -+ * -+ */ -+ -+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) -+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) -+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) -+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) -+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) -+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) -+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) -+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) -+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) -+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) -+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Some addresses should ONLY be used by owner 0 */ -+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ -+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ -+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ -+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ -+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ -+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ -+/* MAILBOX 1 access in Owner 0 area */ -+/* Owner 0 should only WRITE to this mailbox */ -+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ -+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ -+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ -+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ -+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 1 */ -+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) -+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) -+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) -+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) -+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) -+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) -+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) -+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) -+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) -+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) -+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Owner 1 should only WRITE to this mailbox */ -+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ -+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 0 area */ -+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ -+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ -+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ -+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ -+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ -+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ -+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ -+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ -+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 2 */ -+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) -+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) -+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) -+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) -+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) -+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) -+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) -+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) -+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) -+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) -+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) -+/* MAILBOX 0 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ -+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ -+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ -+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ -+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ -+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 3 */ -+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) -+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) -+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) -+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) -+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) -+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) -+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) -+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) -+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) -+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) -+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) -+/* MAILBOX 0 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ -+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ -+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ -+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ -+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ -+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -+ -+ -+ -+/* Mailbox flags. Valid for all owners */ -+ -+/* Mailbox status register (...0x98) */ -+#define ARM_MS_FULL 0x80000000 -+#define ARM_MS_EMPTY 0x40000000 -+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -+ -+/* MAILBOX config/status register (...0x9C) */ -+/* ANY write to this register clears the error bits! */ -+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ -+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ -+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ -+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ -+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ -+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ -+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ -+/* Bit 7 is unused */ -+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ -+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ -+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -+ -+/* Semaphore clear/debug register (...0xE0) */ -+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ -+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ -+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ -+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ -+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ -+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ -+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ -+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ -+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ -+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ -+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ -+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ -+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ -+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ -+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ -+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -+ -+/* Doorbells clear/debug register (...0xE4) */ -+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ -+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ -+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ -+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ -+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ -+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ -+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ -+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -+ -+/* MY IRQS register (...0xF8) */ -+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ -+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -+ -+/* ALL IRQS register (...0xF8) */ -+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ -+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ -+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ -+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ -+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ -+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ -+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ -+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ -+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ -+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ -+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ -+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ -+/* */ -+/* ARM JTAG BASH */ -+/* */ -+#define AJB_BASE 0x7e2000c0 -+ -+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) -+#define AJB_BITS0 0x000000 -+#define AJB_BITS4 0x000004 -+#define AJB_BITS8 0x000008 -+#define AJB_BITS12 0x00000C -+#define AJB_BITS16 0x000010 -+#define AJB_BITS20 0x000014 -+#define AJB_BITS24 0x000018 -+#define AJB_BITS28 0x00001C -+#define AJB_BITS32 0x000020 -+#define AJB_BITS34 0x000022 -+#define AJB_OUT_MS 0x000040 -+#define AJB_OUT_LS 0x000000 -+#define AJB_INV_CLK 0x000080 -+#define AJB_D0_RISE 0x000100 -+#define AJB_D0_FALL 0x000000 -+#define AJB_D1_RISE 0x000200 -+#define AJB_D1_FALL 0x000000 -+#define AJB_IN_RISE 0x000400 -+#define AJB_IN_FALL 0x000000 -+#define AJB_ENABLE 0x000800 -+#define AJB_HOLD0 0x000000 -+#define AJB_HOLD1 0x001000 -+#define AJB_HOLD2 0x002000 -+#define AJB_HOLD3 0x003000 -+#define AJB_RESETN 0x004000 -+#define AJB_CLKSHFT 16 -+#define AJB_BUSY 0x80000000 -+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) -+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) -+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -+ -+#define ARM_LOCAL_BASE 0x40000000 -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) -+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) -+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) -+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) -+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) -+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) -+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) -+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) -+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) -+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) -+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -+ -+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) -+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) -+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) -+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -+ -+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -+ -+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) -+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) -+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) -+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -+ -+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) -+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) -+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) -+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -+ -+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) -+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) -+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) -+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -+ -+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) -+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) -+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) -+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -+ -+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) -+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) -+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) -+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -+ -+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) -+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) -+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) -+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) -+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) -+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) -+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) -+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) -+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) -+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) -+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) -+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) -+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) -+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) -+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) -+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -+ -+#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/hardware.h b/arch/arm/mach-bcm2709/include/mach/hardware.h -new file mode 100644 -index 0000000..c2954e8 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/hardware.h -@@ -0,0 +1,28 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/hardware.h -+ * -+ * This file contains the hardware definitions of the BCM2708 devices. -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include -+#include -+ -+#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/irqs.h b/arch/arm/mach-bcm2709/include/mach/irqs.h -new file mode 100644 -index 0000000..d301f06 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/irqs.h -@@ -0,0 +1,225 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/irqs.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_IRQS_H_ -+#define _BCM2708_IRQS_H_ -+ -+#include -+ -+/* -+ * IRQ interrupts definitions are the same as the INT definitions -+ * held within platform.h -+ */ -+#define IRQ_ARMCTRL_START 0 -+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) -+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) -+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) -+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) -+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) -+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) -+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) -+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) -+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) -+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) -+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) -+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) -+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) -+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) -+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) -+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) -+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) -+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) -+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) -+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) -+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) -+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) -+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) -+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) -+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) -+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) -+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) -+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) -+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) -+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) -+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) -+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) -+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) -+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) -+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) -+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) -+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) -+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) -+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) -+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) -+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) -+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) -+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) -+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) -+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) -+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) -+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) -+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) -+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) -+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) -+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) -+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) -+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) -+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) -+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) -+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) -+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) -+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) -+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) -+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) -+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) -+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) -+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) -+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -+ -+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) -+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) -+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) -+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) -+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) -+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) -+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) -+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) -+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) -+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -+ -+#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define FIQ_START HARD_IRQS -+ -+/* -+ * FIQ interrupts definitions are the same as the INT definitions. -+ */ -+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) -+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) -+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) -+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) -+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) -+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) -+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) -+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) -+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) -+#define FIQ_USB (FIQ_START+INTERRUPT_USB) -+#define FIQ_3D (FIQ_START+INTERRUPT_3D) -+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) -+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) -+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) -+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) -+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) -+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) -+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) -+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) -+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) -+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) -+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) -+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) -+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) -+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) -+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) -+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) -+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) -+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) -+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) -+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) -+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) -+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) -+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) -+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) -+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) -+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) -+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) -+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) -+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) -+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) -+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) -+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) -+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) -+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) -+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) -+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) -+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) -+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) -+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) -+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) -+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) -+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) -+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) -+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) -+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) -+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) -+#define FIQ_UART (FIQ_START+INTERRUPT_UART) -+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) -+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) -+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) -+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) -+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) -+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -+ -+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) -+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) -+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) -+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) -+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) -+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) -+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) -+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) -+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) -+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -+ -+#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define HARD_IRQS (128) -+#define FIQ_IRQS (128) -+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) -+#define GPIO_IRQS (32*5) -+#define SPARE_ALLOC_IRQS 64 -+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) -+#define FREE_IRQS 128 -+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -+ -+#endif /* _BCM2708_IRQS_H_ */ -diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h -index 9a638f5..be99733 100644 ---- a/arch/arm/mach-bcm2709/include/mach/platform.h -+++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -47,6 +47,9 @@ - #define HW_REGISTER_RW(addr) (addr) - #define HW_REGISTER_RO(addr) (addr) - -+#include "arm_control.h" -+#undef ARM_BASE -+ - /* - * Definitions and addresses for the ARM CONTROL logic - * This file is manually generated. -@@ -81,6 +84,116 @@ - #define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ - #define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ - -+ -+/* -+ * Interrupt assignments -+ */ -+ -+#define ARM_IRQ1_BASE 0 -+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) -+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) -+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) -+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) -+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) -+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) -+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) -+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) -+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) -+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) -+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) -+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) -+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) -+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) -+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) -+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) -+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) -+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) -+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) -+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) -+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) -+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) -+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) -+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) -+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) -+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) -+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) -+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) -+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) -+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) -+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) -+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -+ -+#define ARM_IRQ2_BASE 32 -+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) -+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) -+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) -+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) -+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) -+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) -+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) -+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) -+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) -+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) -+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) -+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) -+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) -+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) -+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) -+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) -+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) -+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) -+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) -+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) -+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) -+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) -+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) -+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) -+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) -+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) -+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) -+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) -+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) -+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) -+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) -+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -+ -+#define ARM_IRQ0_BASE 64 -+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) -+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) -+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) -+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) -+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) -+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) -+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) -+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) -+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) -+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) -+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) -+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) -+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) -+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) -+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) -+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) -+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) -+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) -+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) -+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) -+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -+ -+#define ARM_IRQ_LOCAL_BASE 96 -+#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) -+#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) -+#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) -+#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) -+#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) -+#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) -+#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) -+#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) -+#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) -+#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) -+#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) -+#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) -+ - /* - * Watchdog - */ -@@ -109,82 +222,6 @@ - - #define UART0_CLOCK 3000000 - --#define ARM_LOCAL_BASE 0x40000000 --#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -- --#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) --#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) --#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) --#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) --#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) --#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) --#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) --#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) --#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) --#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) --#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) --#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -- --#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) --#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) --#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) --#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -- --#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) --#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) --#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) --#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -- --#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) --#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) --#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) --#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -- --#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) --#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) --#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) --#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -- --#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) --#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) --#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) --#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -- --#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) --#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) --#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) --#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -- --#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) --#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) --#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) --#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -- --#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) --#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) --#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) --#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -- --#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) --#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) --#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) --#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -- --#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) --#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) --#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) --#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -- --#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) --#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) --#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) --#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -- --#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) --#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) --#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) --#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -- - #endif - - /* END */ -diff --git a/arch/arm/mach-bcm2709/include/mach/system.h b/arch/arm/mach-bcm2709/include/mach/system.h -index c9a9c9a..2d0b821 100644 ---- a/arch/arm/mach-bcm2709/include/mach/system.h -+++ b/arch/arm/mach-bcm2709/include/mach/system.h -@@ -23,6 +23,7 @@ - #define __ASM_ARCH_SYSTEM_H - - #include -+#include - #include - - static inline void arch_idle(void) -diff --git a/arch/arm/mach-bcm2709/include/mach/uncompress.h b/arch/arm/mach-bcm2709/include/mach/uncompress.h -index de7504b..d634813 100644 ---- a/arch/arm/mach-bcm2709/include/mach/uncompress.h -+++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h -@@ -21,7 +21,7 @@ - - #include - #include --#include -+#include - - #define UART_BAUD 115200 - -diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index 26f1357d..27b8467 100644 ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -3,7 +3,6 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o - obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o --obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o - obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o - obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o - obj-$(CONFIG_ARCH_MMP) += irq-mmp.o --- -2.5.0 - - -From b977bb81802fbcbb80649167dc5b6995c6504975 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 17 Nov 2015 21:25:41 +0000 -Subject: [PATCH 37/78] BCM2709: Use upstream interrupt controllers - ---- - arch/arm/boot/dts/bcm2709.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index d21f5f0..bcad162 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -22,6 +22,14 @@ - reg = <0x7e200000 0x1000>; - status = "okay"; - }; -+ -+ local_intc: local_intc { -+ compatible = "brcm,bcm2836-l1-intc"; -+ reg = <0x40000000 0x100>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&local_intc>; -+ }; - }; - - timer { -@@ -78,3 +86,9 @@ - &watchdog { - status = "okay"; - }; -+ -+&intc { -+ compatible = "brcm,bcm2836-armctrl-ic"; -+ interrupt-parent = <&local_intc>; -+ interrupts = <8>; -+}; --- -2.5.0 - - -From f4d13846ac7020f732def06861402ab91218f776 Mon Sep 17 00:00:00 2001 +From f95a3c1052bb61d28cc6a4a5ba5dfe691c1e5321 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 2 Mar 2015 13:01:12 -0800 -Subject: [PATCH 38/78] drm/vc4: Add suport for 3D rendering using the V3D +Subject: [PATCH 30/59] drm/vc4: Add suport for 3D rendering using the V3D engine. This is a squash of the out-of-tree development series. Since that @@ -141073,53 +135608,10 @@ index 0000000..499daae 2.5.0 -From 890668e7095063e4eeaa9db80e882829c48cf7f4 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 18 Nov 2015 17:03:59 +0000 -Subject: [PATCH 39/78] Revert "BCM2709: Use upstream interrupt controllers" - -This reverts commit 81d498ed1d85068c2f3c774fc30307c496aecf76. ---- - arch/arm/boot/dts/bcm2709.dtsi | 14 -------------- - 1 file changed, 14 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index bcad162..d21f5f0 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -22,14 +22,6 @@ - reg = <0x7e200000 0x1000>; - status = "okay"; - }; -- -- local_intc: local_intc { -- compatible = "brcm,bcm2836-l1-intc"; -- reg = <0x40000000 0x100>; -- interrupt-controller; -- #interrupt-cells = <1>; -- interrupt-parent = <&local_intc>; -- }; - }; - - timer { -@@ -86,9 +78,3 @@ - &watchdog { - status = "okay"; - }; -- --&intc { -- compatible = "brcm,bcm2836-armctrl-ic"; -- interrupt-parent = <&local_intc>; -- interrupts = <8>; --}; --- -2.5.0 - - -From a4bc9e9997a14d7a91ecee8b13a506f2769915ef Mon Sep 17 00:00:00 2001 +From f7c5c235d8ec8dad653d2ba5ddeed98c11ee3dc0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 14 Oct 2015 11:32:14 -0700 -Subject: [PATCH 40/78] drm/vc4: Force HDMI to connected. +Subject: [PATCH 31/59] drm/vc4: Force HDMI to connected. For some reason on the downstream tree, the HPD GPIO isn't working. @@ -141145,10 +135637,10 @@ index da9a36d..d15c529 100644 2.5.0 -From d6894e5464ab0c987cc8d90ee7ea7a0cf2bdea5a Mon Sep 17 00:00:00 2001 +From 77b1bdbe5ff38d999a3c45b4ce34dcf3bb1a59a5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:23:18 -0700 -Subject: [PATCH 41/78] drm/vc4: bo cache locking fixes. +Subject: [PATCH 32/59] drm/vc4: bo cache locking fixes. Signed-off-by: Eric Anholt --- @@ -141300,10 +135792,10 @@ index 8cc89d1..c079b82 100644 2.5.0 -From 12d2531eb1ed88254465a6ea132d16a2718b5008 Mon Sep 17 00:00:00 2001 +From ada48bc2dcabe8dabce74f2700bde6186fc00366 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:29:41 -0700 -Subject: [PATCH 42/78] drm/vc4: bo cache locking cleanup. +Subject: [PATCH 33/59] drm/vc4: bo cache locking cleanup. Signed-off-by: Eric Anholt --- @@ -141398,10 +135890,10 @@ index af0fde6..acd360c 100644 2.5.0 -From e2e88fba106831e3c35bbe7ee66fcc12598e930c Mon Sep 17 00:00:00 2001 +From 7ff769a1ebaa17c37d4a698af37ab71ff38ff5b8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:32:24 -0700 -Subject: [PATCH 43/78] drm/vc4: Use job_lock to protect seqno_cb_list. +Subject: [PATCH 34/59] drm/vc4: Use job_lock to protect seqno_cb_list. We're (mostly) not supposed to be using struct_mutex in drivers these days. @@ -141458,10 +135950,10 @@ index 361390b..b1853b2 100644 2.5.0 -From e79effaa2cfb9cab3aca2662638727f90a577f0e Mon Sep 17 00:00:00 2001 +From 3f5a87a8113d0026a92a48376dc63e1d3834ca90 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:44:35 -0700 -Subject: [PATCH 44/78] drm/vc4: Drop struct_mutex around CL validation. +Subject: [PATCH 35/59] drm/vc4: Drop struct_mutex around CL validation. We were using it so that we could make sure that shader validation state didn't change while we were validating, but now shader @@ -141527,10 +136019,10 @@ index b1853b2..32f375a 100644 2.5.0 -From 1c13c3f7fb7db3d3d71126d5a0dd181a015f033e Mon Sep 17 00:00:00 2001 +From 96ff83b46b899239914c4f82583694b220abf12a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:44:35 -0700 -Subject: [PATCH 45/78] drm/vc4: Drop struct_mutex around CL validation. +Subject: [PATCH 36/59] drm/vc4: Drop struct_mutex around CL validation. We were using it so that we could make sure that shader validation state didn't change while we were validating, but now shader @@ -141607,10 +136099,10 @@ index 32f375a..55551ea 100644 2.5.0 -From 861d6905eb3deac508af34d9937c0bd6b3ed1c8c Mon Sep 17 00:00:00 2001 +From 5132c04865bb90f75210e68e2b134a8a81a600a0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 20 Oct 2015 13:59:15 +0100 -Subject: [PATCH 46/78] drm/vc4: Add support for more display plane formats. +Subject: [PATCH 37/59] drm/vc4: Add support for more display plane formats. Signed-off-by: Eric Anholt --- @@ -141648,10 +136140,10 @@ index 65e5455..0f85eb5 100644 2.5.0 -From 41bd0b4b1bbc72f85adfb54b50cd3a5623a874ad Mon Sep 17 00:00:00 2001 +From aef868d034a4288d82a6c54422a6f995cb406d3b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 23 Oct 2015 12:31:56 +0100 -Subject: [PATCH 47/78] drm/vc4: No need to stop the stopped threads. +Subject: [PATCH 38/59] drm/vc4: No need to stop the stopped threads. This was leftover debug code from the hackdriver. We never submit unless the thread is already idle. @@ -141680,10 +136172,10 @@ index 55551ea..eeb0925 100644 2.5.0 -From 97355ff6eed7e856ea00d12aee96f37e6a6f9198 Mon Sep 17 00:00:00 2001 +From 977b27a2302f3e2317b4fa28f7aba9c73c77e7ef Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 23 Oct 2015 12:33:43 +0100 -Subject: [PATCH 48/78] drm/vc4: Remove extra barrier()s aroudn CTnCA/CTnEA +Subject: [PATCH 39/59] drm/vc4: Remove extra barrier()s aroudn CTnCA/CTnEA setup. The writel() that these expand to already does barriers. @@ -141719,10 +136211,10 @@ index eeb0925..0cea723 100644 2.5.0 -From 6ba05c099d51e04566e21ec4d75f3846f3662b99 Mon Sep 17 00:00:00 2001 +From 45832cd341f53f157ae1e679c06faef3d498db37 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 23 Oct 2015 14:57:22 +0100 -Subject: [PATCH 49/78] drm/vc4: Fix a typo in a V3D debug register. +Subject: [PATCH 40/59] drm/vc4: Fix a typo in a V3D debug register. Signed-off-by: Eric Anholt --- @@ -141760,10 +136252,10 @@ index b9cb7cf..cf35f58 100644 2.5.0 -From 661e79efd3a3bad9e33544fcbc4a4ee3d295d3b4 Mon Sep 17 00:00:00 2001 +From e44474f1a0149abb2608e57d7ad70f6eb160d18b Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 2 Nov 2015 17:07:33 +0000 -Subject: [PATCH 50/78] drm/vc4: Enable VC4 modules, and increase CMA size with +Subject: [PATCH 41/59] drm/vc4: Enable VC4 modules, and increase CMA size with overlay If using the overlay, be careful not to boot to GUI or run startx, @@ -141777,10 +136269,10 @@ or the Pi will almost hang, reporting stalls in kernel threads. create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index fdefff1..355bbc2 100644 +index b819293..f5302b2 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README -@@ -602,6 +602,14 @@ Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) +@@ -601,6 +601,14 @@ Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) @@ -141897,10 +136389,10 @@ index 0000000..cf5d5c9 + }; +}; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 3ec59d2..521f9a5 100644 +index 38e46ac..49317b9 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig -@@ -795,6 +795,8 @@ CONFIG_VIDEO_TW9903=m +@@ -802,6 +802,8 @@ CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m CONFIG_VIDEO_OV7640=m CONFIG_VIDEO_MT9V011=m @@ -141910,10 +136402,10 @@ index 3ec59d2..521f9a5 100644 CONFIG_FB_BCM2708=y CONFIG_FB_UDL=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 0f69adb..8faf3d6 100644 +index 436da55..202dd4b 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -788,6 +788,8 @@ CONFIG_VIDEO_TW9903=m +@@ -795,6 +795,8 @@ CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m CONFIG_VIDEO_OV7640=m CONFIG_VIDEO_MT9V011=m @@ -141926,10 +136418,10 @@ index 0f69adb..8faf3d6 100644 2.5.0 -From ced557f252c6650fd58e4e939cdc3271b2188a34 Mon Sep 17 00:00:00 2001 +From 64f336d46a8b61002efa54b58f1612cf03ab9930 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Nov 2015 18:29:58 +0000 -Subject: [PATCH 51/78] squash: fixups +Subject: [PATCH 42/59] squash: fixups --- drivers/gpu/drm/vc4/Kconfig | 2 +- @@ -141979,10 +136471,10 @@ index c83287a..2082713 100644 2.5.0 -From 917cb2854aa3b504e8d7528d99d931edf8605820 Mon Sep 17 00:00:00 2001 +From 5b553943a83156a46b864cca4ee0fdb0f2fc6882 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Nov 2015 20:26:03 +0000 -Subject: [PATCH 52/78] squash: add missing vc4-kms-v3d-overlay.dtb to makefile +Subject: [PATCH 43/59] squash: add missing vc4-kms-v3d-overlay.dtb to makefile --- arch/arm/boot/dts/overlays/Makefile | 1 + @@ -142004,62 +136496,10 @@ index fb7ac49..fc09bfb 100644 2.5.0 -From 802f5e84784e9c6689b89cf8d93ebeb6787d99c5 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 19 Nov 2015 14:11:07 +0000 -Subject: [PATCH 53/78] squash: Add cprman to dt - ---- - arch/arm/boot/dts/bcm2708_common.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index c658c7b..ec94d9f5 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -85,6 +85,18 @@ - status = "disabled"; - }; - -+ cprman: cprman@7e101000 { -+ compatible = "brcm,bcm2835-cprman"; -+ #clock-cells = <1>; -+ reg = <0x7e101000 0x2000>; -+ -+ /* CPRMAN derives everything from the platform's -+ * oscillator. -+ */ -+ clocks = <&clk_osc>; -+ status = "disabled"; -+ }; -+ - random: rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; -@@ -312,6 +324,15 @@ - clock-div = <1>; - clock-mult = <2>; - }; -+ -+ /* The oscillator is the root of the clock tree. */ -+ clk_osc: clock@7 { -+ compatible = "fixed-clock"; -+ reg = <7>; -+ #clock-cells = <0>; -+ clock-output-names = "osc"; -+ clock-frequency = <19200000>; -+ }; - }; - - __overrides__ { --- -2.5.0 - - -From efc55fc8b62871ba9e87d3a3dfbad32232a07d89 Mon Sep 17 00:00:00 2001 +From 5ac43b46f57d2cbe94c4d8a34e050eec9a625ce5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 12 Oct 2015 11:23:34 -0700 -Subject: [PATCH 54/78] clk: bcm2835: Also build the driver for downstream +Subject: [PATCH 44/59] clk: bcm2835: Also build the driver for downstream kernels. Signed-off-by: Eric Anholt @@ -142084,16 +136524,16 @@ index 3fc9506..a1b4cbc 100644 2.5.0 -From 1cd4b7121013a54d2ef37cf0dedf83aecf13f508 Mon Sep 17 00:00:00 2001 +From c0ba37a2a85130b7a0f88730eba2783c6dcd6951 Mon Sep 17 00:00:00 2001 From: Holger Steinhaus Date: Sat, 14 Nov 2015 18:37:43 +0100 -Subject: [PATCH 55/78] dts: Added overlay for gpio_ir_recv driver +Subject: [PATCH 45/59] dts: Added overlay for gpio_ir_recv driver --- arch/arm/boot/dts/overlays/Makefile | 1 + - arch/arm/boot/dts/overlays/README | 16 +++++++++ + arch/arm/boot/dts/overlays/README | 18 ++++++++++- arch/arm/boot/dts/overlays/gpio-ir-overlay.dts | 45 ++++++++++++++++++++++++++ - 3 files changed, 62 insertions(+) + 3 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-overlay.dts diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile @@ -142109,7 +136549,7 @@ index fc09bfb..ebc3354 100644 dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 355bbc2..3685f98 100644 +index f5302b2..409aee1 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -196,6 +196,22 @@ Params: int_pin GPIO used for INT (default 25) @@ -142134,7 +136574,16 @@ index 355bbc2..3685f98 100644 + Name: gpio-poweroff Info: Drives a GPIO high or low on reboot - Load: gpio-poweroff,= + Load: dtoverlay=gpio-poweroff,= +@@ -308,7 +324,7 @@ Params: + Name: lirc-rpi + Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi) + Consult the module documentation for more details. +-Load: dtoverlay=lirc-rpi,=,... ++Load: dtoverlay=lirc-rpi,= + Params: gpio_out_pin GPIO for output (default "17") + + gpio_in_pin GPIO for input (default "18") diff --git a/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts new file mode 100644 index 0000000..a2d6bc7 @@ -142190,19 +136639,19 @@ index 0000000..a2d6bc7 2.5.0 -From 76e6e1da69e6b88235c83cfc109a5b9ba19db236 Mon Sep 17 00:00:00 2001 +From 26e029b1b51f165e9cf74ea5ab311adaa1bf2e01 Mon Sep 17 00:00:00 2001 From: Alistair Buxton Date: Sun, 1 Nov 2015 22:27:56 +0000 -Subject: [PATCH 56/78] Build i2c_gpio module and add a device tree overlay to +Subject: [PATCH 46/59] Build i2c_gpio module and add a device tree overlay to configure it. --- arch/arm/boot/dts/overlays/Makefile | 1 + - arch/arm/boot/dts/overlays/README | 11 ++++++++++ + arch/arm/boot/dts/overlays/README | 13 +++++++++++- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 28 +++++++++++++++++++++++++ arch/arm/configs/bcm2709_defconfig | 1 + arch/arm/configs/bcmrpi_defconfig | 1 + - 5 files changed, 42 insertions(+) + 5 files changed, 43 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile @@ -142218,16 +136667,16 @@ index ebc3354..e15d55c 100644 dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 3685f98..2e96de5 100644 +index 409aee1..d278305 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README -@@ -287,6 +287,17 @@ Params: speed Display SPI bus speed +@@ -287,9 +287,20 @@ Params: speed Display SPI bus speed ledgpio GPIO used to control backlight +Name: i2c-gpio +Info: Adds support for software i2c controller on gpio pins -+Load: dtoverlay=i2c-gpio, ++Load: dtoverlay=i2c-gpio,= +Params: i2c_gpio_sda GPIO used for I2C data (default "23") + + i2c_gpio_scl GPIO used for I2C clock (default "24") @@ -142238,7 +136687,11 @@ index 3685f98..2e96de5 100644 + Name: i2c-rtc Info: Adds support for a number of I2C Real Time Clock devices - Load: dtoverlay=i2c-rtc, +-Load: dtoverlay=i2c-rtc, ++Load: dtoverlay=i2c-rtc,= + Params: ds1307 Select the DS1307 device + + ds3231 Select the DS3231 device diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts new file mode 100644 index 0000000..2a2dc98 @@ -142274,10 +136727,10 @@ index 0000000..2a2dc98 +}; + diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 521f9a5..bf1fad3 100644 +index 49317b9..1f47fb7 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig -@@ -588,6 +588,7 @@ CONFIG_RAW_DRIVER=y +@@ -595,6 +595,7 @@ CONFIG_RAW_DRIVER=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_BCM2708=m @@ -142286,10 +136739,10 @@ index 521f9a5..bf1fad3 100644 CONFIG_SPI_BCM2835=m CONFIG_SPI_SPIDEV=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 8faf3d6..ff1c8bf 100644 +index 202dd4b..015a2b3 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -581,6 +581,7 @@ CONFIG_RAW_DRIVER=y +@@ -588,6 +588,7 @@ CONFIG_RAW_DRIVER=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_BCM2708=m @@ -142301,10 +136754,10 @@ index 8faf3d6..ff1c8bf 100644 2.5.0 -From 668f0946ebfe3a75ace1d45befa6e3f6c7c7acb4 Mon Sep 17 00:00:00 2001 +From fd5bec91d5ce5bf001f8147a73c79bbf9d50d581 Mon Sep 17 00:00:00 2001 From: mwilliams03 Date: Sun, 18 Oct 2015 17:07:24 -0700 -Subject: [PATCH 57/78] New overlay for PiScreen2r +Subject: [PATCH 47/59] New overlay for PiScreen2r --- arch/arm/boot/dts/overlays/Makefile | 1 + @@ -142326,7 +136779,7 @@ index e15d55c..8595b14 100644 dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 2e96de5..8f66478 100644 +index d278305..3116d1a 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -425,6 +425,20 @@ Params: speed Display SPI bus speed @@ -142335,7 +136788,7 @@ index 2e96de5..8f66478 100644 +Name: piscreen2r +Info: PiScreen 2 with resistive TP display by OzzMaker.com -+Load: dtoverlay=piscreen,= ++Load: dtoverlay=piscreen2r,= +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} @@ -142460,87 +136913,10 @@ index 0000000..7c018e0 2.5.0 -From 810c4479845e63c66f4ecb8f4645d9903b6a469c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= -Date: Mon, 26 Oct 2015 14:42:10 +0100 -Subject: [PATCH 58/78] config: Add TOUCHSCREEN_FT6236 - ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index bf1fad3..09a3977 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -546,6 +546,7 @@ CONFIG_JOYSTICK_RPISENSE=m - CONFIG_INPUT_TOUCHSCREEN=y - CONFIG_TOUCHSCREEN_ADS7846=m - CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_FT6236=m - CONFIG_TOUCHSCREEN_RPI_FT5406=m - CONFIG_TOUCHSCREEN_USB_COMPOSITE=m - CONFIG_TOUCHSCREEN_STMPE=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index ff1c8bf..f89eaf5 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -539,6 +539,7 @@ CONFIG_JOYSTICK_RPISENSE=m - CONFIG_INPUT_TOUCHSCREEN=y - CONFIG_TOUCHSCREEN_ADS7846=m - CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_FT6236=m - CONFIG_TOUCHSCREEN_RPI_FT5406=m - CONFIG_TOUCHSCREEN_USB_COMPOSITE=m - CONFIG_TOUCHSCREEN_STMPE=m --- -2.5.0 - - -From dbc1fc3387026c6780cae2519f9cd7f8a1009eed Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Thu, 5 Nov 2015 12:01:53 +0000 -Subject: [PATCH 59/78] config: Add MCP320X - -See: https://github.com/raspberrypi/linux/issues/1189 ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 09a3977..15e4033 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -1102,6 +1102,7 @@ CONFIG_IIO=m - CONFIG_IIO_BUFFER=y - CONFIG_IIO_BUFFER_CB=y - CONFIG_IIO_KFIFO_BUF=m -+CONFIG_MCP320X=m - CONFIG_DHT11=m - CONFIG_PWM_BCM2835=m - CONFIG_RASPBERRYPI_FIRMWARE=y -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index f89eaf5..ec2c66d 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -1095,6 +1095,7 @@ CONFIG_IIO=m - CONFIG_IIO_BUFFER=y - CONFIG_IIO_BUFFER_CB=y - CONFIG_IIO_KFIFO_BUF=m -+CONFIG_MCP320X=m - CONFIG_DHT11=m - CONFIG_PWM_BCM2835=m - CONFIG_RASPBERRYPI_FIRMWARE=y --- -2.5.0 - - -From 34bb36da26a245fc1a6c2d85fc186ebf2a61ca97 Mon Sep 17 00:00:00 2001 +From 9b04ba6644143db182164e74e06563b9064fca7f Mon Sep 17 00:00:00 2001 From: Ondrej Wisniewski Date: Fri, 6 Nov 2015 15:01:28 +0100 -Subject: [PATCH 60/78] dts: Added overlay for Adafruit PiTFT 2.8" capacitive +Subject: [PATCH 48/59] dts: Added overlay for Adafruit PiTFT 2.8" capacitive touch screen --- @@ -142563,7 +136939,7 @@ index 8595b14..7d747bc 100644 dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 8f66478..055aa5b 100644 +index 3116d1a..950b6c5 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -439,6 +439,28 @@ Params: speed Display SPI bus speed @@ -142693,495 +137069,10 @@ index 0000000..48920e9 2.5.0 -From 645245ffbaacdbb1449c21e7d600550ef665a158 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Fri, 6 Nov 2015 16:24:59 +0000 -Subject: [PATCH 61/78] rpi-ft5406: Use interruptible sleep to avoid high load - reported - ---- - drivers/input/touchscreen/rpi-ft5406.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/input/touchscreen/rpi-ft5406.c b/drivers/input/touchscreen/rpi-ft5406.c -index c08817e..b27dbee 100644 ---- a/drivers/input/touchscreen/rpi-ft5406.c -+++ b/drivers/input/touchscreen/rpi-ft5406.c -@@ -65,7 +65,7 @@ static int ft5406_thread(void *arg) - while(!kthread_should_stop()) - { - // 60fps polling -- msleep(17); -+ msleep_interruptible(17); - memcpy_fromio(®s, ts->regs, sizeof(*ts->regs)); - writel(99, &ts->regs->num_points); - // Do not output if theres no new information (num_points is 99) --- -2.5.0 - - -From 467be401ac864a86e52289666ea61b04bf54e2fd Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 17 Nov 2015 10:07:08 +0000 -Subject: [PATCH 62/78] BCM270X_DT: Fix overlay README anomalies - ---- - arch/arm/boot/dts/overlays/README | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 055aa5b..950b6c5 100644 ---- a/arch/arm/boot/dts/overlays/README -+++ b/arch/arm/boot/dts/overlays/README -@@ -214,7 +214,7 @@ Params: gpio_pin Input pin number. Default is 18. - - Name: gpio-poweroff - Info: Drives a GPIO high or low on reboot --Load: gpio-poweroff,= -+Load: dtoverlay=gpio-poweroff,= - Params: gpiopin GPIO for signalling (default 26) - - active_low Set if the power control device requires a -@@ -289,7 +289,7 @@ Params: speed Display SPI bus speed - - Name: i2c-gpio - Info: Adds support for software i2c controller on gpio pins --Load: dtoverlay=i2c-gpio, -+Load: dtoverlay=i2c-gpio,= - Params: i2c_gpio_sda GPIO used for I2C data (default "23") - - i2c_gpio_scl GPIO used for I2C clock (default "24") -@@ -300,7 +300,7 @@ Params: i2c_gpio_sda GPIO used for I2C data (default "23") - - Name: i2c-rtc - Info: Adds support for a number of I2C Real Time Clock devices --Load: dtoverlay=i2c-rtc, -+Load: dtoverlay=i2c-rtc,= - Params: ds1307 Select the DS1307 device - - ds3231 Select the DS3231 device -@@ -335,7 +335,7 @@ Params: - Name: lirc-rpi - Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi) - Consult the module documentation for more details. --Load: dtoverlay=lirc-rpi,=,... -+Load: dtoverlay=lirc-rpi,= - Params: gpio_out_pin GPIO for output (default "17") - - gpio_in_pin GPIO for input (default "18") -@@ -427,7 +427,7 @@ Params: speed Display SPI bus speed - - Name: piscreen2r - Info: PiScreen 2 with resistive TP display by OzzMaker.com --Load: dtoverlay=piscreen,= -+Load: dtoverlay=piscreen2r,= - Params: speed Display SPI bus speed - - rotate Display rotation {0,90,180,270} -@@ -492,7 +492,6 @@ Info: Configures a single PWM channel - 3) So be careful mixing audio and PWM. - 4) Currently the clock must have been enabled and configured - by other means. --Load: dtoverlay=pwm-2chan,= - Load: dtoverlay=pwm,= - Params: pin Output pin (default 18) - see table - func Pin function (default 2 = Alt5) - see above -@@ -694,7 +693,7 @@ Params: gpiopin GPIO for I/O (default "4") - Name: w1-gpio-pullup - Info: Configures the w1-gpio Onewire interface module. - Use this overlay if you *do* need a GPIO to drive an external pullup. --Load: dtoverlay=w1-gpio-pullup,=,... -+Load: dtoverlay=w1-gpio-pullup,= - Params: gpiopin GPIO for I/O (default "4") - - pullup Non-zero, "on", or "y" to enable the parasitic --- -2.5.0 - - -From 617ce95131bf691678da16e82a14f2857dbe5590 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 1 Dec 2015 16:52:13 +0000 -Subject: [PATCH 63/78] BCM270X_DT: Use clk_core for I2C interfaces - ---- - arch/arm/boot/dts/bcm2708_common.dtsi | 43 +++++++++++++++-------------------- - 1 file changed, 18 insertions(+), 25 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index ec94d9f5..d65586f 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -158,7 +158,7 @@ - compatible = "brcm,bcm2708-i2c"; - reg = <0x7e205000 0x1000>; - interrupts = <2 21>; -- clocks = <&clk_i2c>; -+ clocks = <&clk_core>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -197,7 +197,7 @@ - compatible = "brcm,bcm2708-i2c"; - reg = <0x7e804000 0x1000>; - interrupts = <2 21>; -- clocks = <&clk_i2c>; -+ clocks = <&clk_core>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -210,7 +210,7 @@ - compatible = "brcm,bcm2708-i2c"; - reg = <0x7e805000 0x1000>; - interrupts = <2 21>; -- clocks = <&clk_i2c>; -+ clocks = <&clk_core>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -269,56 +269,49 @@ - #address-cells = <1>; - #size-cells = <0>; - -- clk_mmc: clock@0 { -+ clk_core: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; -- clock-output-names = "mmc"; -+ clock-output-names = "core"; - clock-frequency = <250000000>; - }; - -- clk_i2c: clock@1 { -+ clk_mmc: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; -- clock-output-names = "i2c"; -+ clock-output-names = "mmc"; - clock-frequency = <250000000>; - }; - -- clk_core: clock@2 { -+ clk_uart0: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - #clock-cells = <0>; -- clock-output-names = "core"; -- clock-frequency = <250000000>; -- }; -- -- clk_uart0: clock@3 { -- compatible = "fixed-clock"; -- reg = <3>; -- #clock-cells = <0>; - clock-output-names = "uart0_pclk"; - clock-frequency = <3000000>; - }; - -- clk_apb_p: clock@4 { -+ clk_apb_p: clock@3 { - compatible = "fixed-clock"; -- reg = <4>; -+ reg = <3>; - #clock-cells = <0>; - clock-output-names = "apb_pclk"; - clock-frequency = <126000000>; - }; - -- clk_pwm: clock@5 { -- compatible = "fixed-clock"; -- reg = <3>; -- #clock-cells = <0>; -- clock-output-names = "pwm"; -- clock-frequency = <100000000>; -+ clk_pwm: clock@4 { -+ compatible = "fixed-clock"; -+ reg = <4>; -+ #clock-cells = <0>; -+ clock-output-names = "pwm"; -+ clock-frequency = <100000000>; - }; - -- clk_uart1: clock@6 { -+ clk_uart1: clock@5 { - compatible = "fixed-factor-clock"; -+ reg = <5>; - clocks = <&clk_core>; - #clock-cells = <0>; - clock-div = <1>; --- -2.5.0 - - -From 7ae1428955b29e9dc777444cd30e4dc1ca3c9094 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Fri, 20 Jun 2014 17:19:27 +0100 -Subject: [PATCH 64/78] bcm2709: Simplify and strip down IRQ handler - ---- - arch/arm/include/asm/entry-macro-multi.S | 2 + - arch/arm/mach-bcm2709/include/mach/entry-macro.S | 173 +++++++++++------------ - 2 files changed, 87 insertions(+), 88 deletions(-) - -diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S -index 609184f..693cc1f 100644 ---- a/arch/arm/include/asm/entry-macro-multi.S -+++ b/arch/arm/include/asm/entry-macro-multi.S -@@ -1,5 +1,6 @@ - #include - -+#ifndef CONFIG_ARCH_BCM2709 - /* - * Interrupt handling. Preserves r7, r8, r9 - */ -@@ -28,6 +29,7 @@ - #endif - 9997: - .endm -+#endif - - .macro arch_irq_handler, symbol_name - .align 5 -diff --git a/arch/arm/mach-bcm2709/include/mach/entry-macro.S b/arch/arm/mach-bcm2709/include/mach/entry-macro.S -index d08591b..2e9f458 100644 ---- a/arch/arm/mach-bcm2709/include/mach/entry-macro.S -+++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S -@@ -22,102 +22,99 @@ - #include - #include - -- .macro disable_fiq -- .endm -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm - -- .macro get_irqnr_preamble, base, tmp -- ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) -- .endm -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - -- .macro arch_ret_to_user, tmp1, tmp2 -- .endm -+ /* get core number */ -+ mrc p15, 0, \base, c0, c0, 5 -+ ubfx \base, \base, #0, #2 - -- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -- /* get core number */ -- mrc p15, 0, \tmp, c0, c0, 5 -- ubfx \tmp, \tmp, #0, #2 -+ /* get core's local interrupt controller */ -+ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source -+ add \irqstat, \irqstat, \base, lsl #2 -+ ldr \tmp, [\irqstat] -+#ifdef CONFIG_SMP -+ /* test for mailbox0 (IPI) interrupt */ -+ tst \tmp, #0x10 -+ beq 1030f - -- /* get core's local interrupt controller */ -- ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source -- add \irqstat, \irqstat, \tmp, lsl #2 -- ldr \tmp, [\irqstat] -- /* ignore gpu interrupt */ -- bic \tmp, #0x100 -- /* ignore mailbox interrupts */ -- bics \tmp, #0xf0 -- beq 1005f -+ /* get core's mailbox interrupt control */ -+ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr -+ add \irqstat, \irqstat, \base, lsl #4 -+ ldr \tmp, [\irqstat] -+ clz \tmp, \tmp -+ rsb \irqnr, \tmp, #31 -+ mov \tmp, #1 -+ lsl \tmp, \irqnr -+ str \tmp, [\irqstat] @ clear interrupt source -+ dsb -+ mov r1, sp -+ badr lr, 1b -+ b do_IPI -+#endif -+1030: -+ /* check gpu interrupt */ -+ tst \tmp, #0x100 -+ beq 1040f - -- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -- @ N.B. CLZ is an ARM5 instruction. -- mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) -- sub \irqstat, \tmp, #1 -- eor \irqstat, \irqstat, \tmp -- clz \tmp, \irqstat -- sub \irqnr, \tmp -- b 1020f --1005: -- /* get core number */ -- mrc p15, 0, \tmp, c0, c0, 5 -- ubfx \tmp, \tmp, #0, #2 -+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) -+ /* get masked status */ -+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] -+ mov \irqnr, #(ARM_IRQ0_BASE + 31) -+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 -+ /* clear bits 8 and 9, and test */ -+ bics \irqstat, \irqstat, #0x300 -+ bne 1010f - -- cmp \tmp, #1 -- beq 1020f -- cmp \tmp, #2 -- beq 1020f -- cmp \tmp, #3 -- beq 1020f -- -- /* get masked status */ -- ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] -- mov \irqnr, #(ARM_IRQ0_BASE + 31) -- and \tmp, \irqstat, #0x300 @ save bits 8 and 9 -- /* clear bits 8 and 9, and test */ -- bics \irqstat, \irqstat, #0x300 -- bne 1010f -- -- tst \tmp, #0x100 -- ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] -- movne \irqnr, #(ARM_IRQ1_BASE + 31) -- @ Mask out the interrupts also present in PEND0 - see SW-5809 -- bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) -- bicne \irqstat, #((1<<18) | (1<<19)) -- bne 1010f -- -- tst \tmp, #0x200 -- ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] -- movne \irqnr, #(ARM_IRQ2_BASE + 31) -- @ Mask out the interrupts also present in PEND0 - see SW-5809 -- bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) -- bicne \irqstat, #((1<<30)) -- beq 1020f -+ tst \tmp, #0x100 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ1_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) -+ bicne \irqstat, #((1<<18) | (1<<19)) -+ bne 1010f - -+ tst \tmp, #0x200 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ2_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) -+ bicne \irqstat, #((1<<30)) -+ beq 1020f - 1010: -- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -- @ N.B. CLZ is an ARM5 instruction. -- sub \tmp, \irqstat, #1 -- eor \irqstat, \irqstat, \tmp -- clz \tmp, \irqstat -- sub \irqnr, \tmp -+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -+ sub \tmp, \irqstat, #1 -+ eor \irqstat, \irqstat, \tmp -+ clz \tmp, \irqstat -+ sub \irqnr, \tmp -+ b 1050f -+1040: -+ cmp \tmp, #0 -+ beq 1020f - --1020: @ EQ will be set if no irqs pending -+ /* handle local (e.g. timer) interrupts */ -+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -+ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) -+ sub \irqstat, \tmp, #1 -+ eor \irqstat, \irqstat, \tmp -+ clz \tmp, \irqstat -+ sub \irqnr, \tmp -+1050: -+ mov r1, sp -+ @ -+ @ routine called with r0 = irq number, r1 = struct pt_regs * -+ @ -+ badr lr, 1b -+ b asm_do_IRQ - -- .endm -+1020: @ EQ will be set if no irqs pending -+ .endm - -- .macro test_for_ipi, irqnr, irqstat, base, tmp -- /* get core number */ -- mrc p15, 0, \tmp, c0, c0, 5 -- ubfx \tmp, \tmp, #0, #2 -- /* get core's mailbox interrupt control */ -- ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr -- add \irqstat, \irqstat, \tmp, lsl #4 -- ldr \tmp, [\irqstat] -- cmp \tmp, #0 -- beq 1030f -- clz \tmp, \tmp -- rsb \irqnr, \tmp, #31 -- mov \tmp, #1 -- lsl \tmp, \irqnr -- str \tmp, [\irqstat] @ clear interrupt source -- dsb --1030: @ EQ will be set if no irqs pending -- .endm -+/* -+ * Interrupt handling. Preserves r7, r8, r9 -+ */ -+ .macro arch_irq_handler_default -+1: get_irqnr_and_base r0, r2, r6, lr -+ .endm --- -2.5.0 - - -From 58012b5ab2f4b33b1eff7c9cabc58cfd2c88846a Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 1 Oct 2015 11:49:11 +0100 -Subject: [PATCH 65/78] config: Add CONFIG_UHID - ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 15e4033..9dfb048 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -846,6 +846,7 @@ CONFIG_SND_SOC_WM8804_I2C=m - CONFIG_SND_SIMPLE_CARD=m - CONFIG_SOUND_PRIME=m - CONFIG_HIDRAW=y -+CONFIG_UHID=m - CONFIG_HID_A4TECH=m - CONFIG_HID_ACRUX=m - CONFIG_HID_APPLE=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index ec2c66d..e31e679 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -839,6 +839,7 @@ CONFIG_SND_SOC_WM8804_I2C=m - CONFIG_SND_SIMPLE_CARD=m - CONFIG_SOUND_PRIME=m - CONFIG_HIDRAW=y -+CONFIG_UHID=m - CONFIG_HID_A4TECH=m - CONFIG_HID_ACRUX=m - CONFIG_HID_APPLE=m --- -2.5.0 - - -From e7080c6297e629a18046968f232461824a2f2d72 Mon Sep 17 00:00:00 2001 +From 22cc43d30298abcdac34ef08074d87104be8edeb Mon Sep 17 00:00:00 2001 From: Stuart MacLean Date: Fri, 2 Oct 2015 15:12:59 +0100 -Subject: [PATCH 66/78] Add support for the HiFiBerry DAC+ Pro. +Subject: [PATCH 49/59] Add support for the HiFiBerry DAC+ Pro. The HiFiBerry DAC+ and DAC+ Pro products both use the existing bcm sound driver with the DAC+ Pro having a special clock device driver representing the two high precision oscillators. @@ -143732,111 +137623,10 @@ index 047c489..090fe0e 100644 2.5.0 -From 3eab6924ad8a517f7422d85384aa687a98c8fe68 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sun, 4 Oct 2015 12:30:01 +0100 -Subject: [PATCH 67/78] config: Add CONFIG_CRYPTO_USER_API_SKCIPHER - ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 9dfb048..b39f072 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -1244,6 +1244,7 @@ CONFIG_CRYPTO_TGR192=m - CONFIG_CRYPTO_WP512=m - CONFIG_CRYPTO_CAST5=m - CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_USER_API_SKCIPHER=m - # CONFIG_CRYPTO_HW is not set - CONFIG_ARM_CRYPTO=y - CONFIG_CRYPTO_SHA1_ARM_NEON=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index e31e679..d6e29f1 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -1240,6 +1240,7 @@ CONFIG_CRYPTO_TGR192=m - CONFIG_CRYPTO_WP512=m - CONFIG_CRYPTO_CAST5=m - CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_USER_API_SKCIPHER=m - # CONFIG_CRYPTO_HW is not set - CONFIG_ARM_CRYPTO=y - CONFIG_CRYPTO_SHA1_ARM=m --- -2.5.0 - - -From fafb57bc3b6c61170a15ce3635bcb30a016fc500 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sun, 4 Oct 2015 12:36:44 +0100 -Subject: [PATCH 68/78] config: Add options for supporting openlabs 802.15.4 - radio - ---- - arch/arm/configs/bcm2709_defconfig | 6 ++++++ - arch/arm/configs/bcmrpi_defconfig | 6 ++++++ - 2 files changed, 12 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index b39f072..be6cda9 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -284,6 +284,9 @@ CONFIG_VLAN_8021Q=m - CONFIG_VLAN_8021Q_GVRP=y - CONFIG_ATALK=m - CONFIG_6LOWPAN=m -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_MAC802154=m - CONFIG_NET_SCHED=y - CONFIG_NET_SCH_CBQ=m - CONFIG_NET_SCH_HTB=m -@@ -530,6 +533,9 @@ CONFIG_ZD1211RW=m - CONFIG_MWIFIEX=m - CONFIG_MWIFIEX_SDIO=m - CONFIG_WIMAX_I2400M_USB=m -+CONFIG_IEEE802154_AT86RF230=m -+CONFIG_IEEE802154_MRF24J40=m -+CONFIG_IEEE802154_CC2520=m - CONFIG_INPUT_POLLDEV=m - # CONFIG_INPUT_MOUSEDEV_PSAUX is not set - CONFIG_INPUT_JOYDEV=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index d6e29f1..9e5cd8b 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -277,6 +277,9 @@ CONFIG_VLAN_8021Q=m - CONFIG_VLAN_8021Q_GVRP=y - CONFIG_ATALK=m - CONFIG_6LOWPAN=m -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_MAC802154=m - CONFIG_NET_SCHED=y - CONFIG_NET_SCH_CBQ=m - CONFIG_NET_SCH_HTB=m -@@ -523,6 +526,9 @@ CONFIG_ZD1211RW=m - CONFIG_MWIFIEX=m - CONFIG_MWIFIEX_SDIO=m - CONFIG_WIMAX_I2400M_USB=m -+CONFIG_IEEE802154_AT86RF230=m -+CONFIG_IEEE802154_MRF24J40=m -+CONFIG_IEEE802154_CC2520=m - CONFIG_INPUT_POLLDEV=m - # CONFIG_INPUT_MOUSEDEV_PSAUX is not set - CONFIG_INPUT_JOYDEV=m --- -2.5.0 - - -From 42cec9005a9c814c381c222181e48f6ed03e41a2 Mon Sep 17 00:00:00 2001 +From 855f9adc802916fa951051daf6ee6af440888688 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 5 Oct 2015 10:47:45 +0100 -Subject: [PATCH 69/78] BCM270X_DT: Add at86rf233 overlay +Subject: [PATCH 50/59] BCM270X_DT: Add at86rf233 overlay Add an overlay to support the Atmel AT86RF233 WPAN transceiver on spi0.0. @@ -143974,167 +137764,10 @@ index 0000000..0460269 2.5.0 -From c18a95d9c8207eba62ea3cab76a1bce8921fc38d Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Fri, 9 Oct 2015 10:49:00 +0100 -Subject: [PATCH 70/78] BCM270X_DT: Make mmc overlay compatible with current - firmware - -The original DT overlay logic followed a merge-then-patch procedure, -i.e. parameters are applied to the loaded overlay before the overlay -is merged into the base DTB. This sequence has been changed to -patch-then-merge, in order to support parameterised node names, and -to protect against bad overlays. As a result, overrides (parameters) -must only target labels in the overlay, but the overlay can obviously target nodes in the base DTB. - -mmc-overlay.dts (that switches back to the original mmc sdcard -driver) is the only overlay violating that rule, and this patch -fixes it. ---- - arch/arm/boot/dts/overlays/mmc-overlay.dts | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/boot/dts/overlays/mmc-overlay.dts b/arch/arm/boot/dts/overlays/mmc-overlay.dts -index 0a37cf4..4579ff2 100644 ---- a/arch/arm/boot/dts/overlays/mmc-overlay.dts -+++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts -@@ -7,13 +7,13 @@ - fragment@0 { - target = <&mmc>; - -- __overlay__ { -+ frag0: __overlay__ { - brcm,overclock-50 = <0>; - }; - }; - - __overrides__ { -- overclock_50 = <&mmc>,"brcm,overclock-50:0"; -- force_pio = <&mmc>,"brcm,force-pio?"; -+ overclock_50 = <&frag0>,"brcm,overclock-50:0"; -+ force_pio = <&frag0>,"brcm,force-pio?"; - }; - }; --- -2.5.0 - - -From 2f2049567814503ea3738dfea9fc1eaa502924cb Mon Sep 17 00:00:00 2001 -From: Eric Anholt -Date: Tue, 13 Oct 2015 13:26:43 -0700 -Subject: [PATCH 71/78] bcm2708: Use #include in dtsi files. - -This will let us include dt-bindings headers and use symbolic names in -various cases. - -Signed-off-by: Eric Anholt ---- - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 2 +- - arch/arm/boot/dts/bcm2708-rpi-b.dts | 2 +- - arch/arm/boot/dts/bcm2708-rpi-cm.dts | 2 +- - arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 2 +- - arch/arm/boot/dts/bcm2708.dtsi | 2 +- - arch/arm/boot/dts/bcm2708_common.dtsi | 2 +- - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 2 +- - arch/arm/boot/dts/bcm2709.dtsi | 2 +- - 8 files changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -index ffb7596..cd22780 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2708.dtsi" -+#include "bcm2708.dtsi" - - / { - compatible = "brcm,bcm2708"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts -index 8551159..0d7524e 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2708.dtsi" -+#include "bcm2708.dtsi" - - / { - compatible = "brcm,bcm2708"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -index 1f7ec88..587f1e4 100755 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2708-rpi-cm.dtsi" -+#include "bcm2708-rpi-cm.dtsi" - - / { - model = "Raspberry Pi Compute Module"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -index 713e5a2..2acefee 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -@@ -1,4 +1,4 @@ --/include/ "bcm2708.dtsi" -+#include "bcm2708.dtsi" - - &leds { - act_led: act { -diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi -index 42acf77..f5a44cd 100644 ---- a/arch/arm/boot/dts/bcm2708.dtsi -+++ b/arch/arm/boot/dts/bcm2708.dtsi -@@ -1,4 +1,4 @@ --/include/ "bcm2708_common.dtsi" -+#include "bcm2708_common.dtsi" - - / { - compatible = "brcm,bcm2708"; -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index d65586f..78ee8a0 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -1,4 +1,4 @@ --/include/ "skeleton.dtsi" -+#include "skeleton.dtsi" - - / { - interrupt-parent = <&intc>; -diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -index 7a05dab5..f45aa50 100644 ---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2709.dtsi" -+#include "bcm2709.dtsi" - - / { - compatible = "brcm,bcm2709"; -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index d21f5f0..d946c39 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -1,4 +1,4 @@ --/include/ "bcm2708_common.dtsi" -+#include "bcm2708_common.dtsi" - - / { - compatible = "brcm,bcm2709"; --- -2.5.0 - - -From 0f20b7af7c5a1409fb2f108cff7a68ee9d56df70 Mon Sep 17 00:00:00 2001 +From cb447e6fe0a7f42f915c46362aad4944da91518f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 18 Dec 2014 16:07:15 -0800 -Subject: [PATCH 72/78] mm: Remove the PFN busy warning +Subject: [PATCH 51/59] mm: Remove the PFN busy warning See commit dae803e165a11bc88ca8dbc07a11077caf97bbcb -- the warning is expected sometimes when using CMA. However, that commit still spams @@ -144162,10 +137795,10 @@ index 9d666df..b682acc 100644 2.5.0 -From cbd651899ad2207b1381ed876fd4b854fa304182 Mon Sep 17 00:00:00 2001 +From d3ab193e2ccff0b434de0606b3c99802efb6c7b4 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 19 Nov 2014 12:06:38 -0800 -Subject: [PATCH 73/78] drm: Put an optional field in the driver struct for GEM +Subject: [PATCH 52/59] drm: Put an optional field in the driver struct for GEM obj struct size. This allows a driver to derive from the CMA object without copying all @@ -144210,500 +137843,3873 @@ index 0a271ca..54f5469 100644 2.5.0 -From b447ac04854ba93dec690be7f0b49e3060eaa79c Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Thu, 3 Dec 2015 15:50:29 +0000 -Subject: [PATCH 74/78] lirc-rpi: FIXUP correct error code (should be negative) +From 4eaaf2ad0c84b80573e15529570380a95b6cbfdf Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 30 Oct 2015 10:09:02 -0700 +Subject: [PATCH 53/59] drm/vc4: Add an interface for capturing the GPU state + after a hang. +This can be parsed with vc4-gpu-tools tools for trying to figure out +what was going on. + +Signed-off-by: Eric Anholt --- - drivers/staging/media/lirc/lirc_rpi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + drivers/gpu/drm/vc4/vc4_bo.c | 4 +- + drivers/gpu/drm/vc4/vc4_drv.c | 1 + + drivers/gpu/drm/vc4/vc4_drv.h | 4 + + drivers/gpu/drm/vc4/vc4_gem.c | 185 ++++++++++++++++++++++++++++++++++++++++++ + include/uapi/drm/vc4_drm.h | 45 ++++++++++ + 5 files changed, 237 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c -index f1e0de9..cd09c99 100644 ---- a/drivers/staging/media/lirc/lirc_rpi.c -+++ b/drivers/staging/media/lirc/lirc_rpi.c -@@ -383,7 +383,7 @@ static int init_port(void) - read_bool_property(node, "rpi,debug", &debug); +diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c +index acd360c..58dcbae 100644 +--- a/drivers/gpu/drm/vc4/vc4_bo.c ++++ b/drivers/gpu/drm/vc4/vc4_bo.c +@@ -415,8 +415,8 @@ int vc4_mmap(struct file *filp, struct vm_area_struct *vma) + gem_obj = vma->vm_private_data; + bo = to_vc4_bo(gem_obj); - } else { -- return EINVAL; -+ return -EINVAL; +- if (bo->validated_shader) { +- DRM_ERROR("mmaping of shader BOs not allowed.\n"); ++ if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { ++ DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); + return -EINVAL; } - gpiochip->set(gpiochip, gpio_out_pin, invert); --- -2.5.0 - - -From c5ad8fb0191bd436a157bec1bbc596604ee2ff1e Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Fri, 4 Dec 2015 10:46:53 +0000 -Subject: [PATCH 75/78] FIXUP BCM270X_DT: Use clk_core for I2C interfaces - -Renumber clk_osc to close the gap ---- - arch/arm/boot/dts/bcm2708_common.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index 78ee8a0..91ff784 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -319,9 +319,9 @@ - }; - - /* The oscillator is the root of the clock tree. */ -- clk_osc: clock@7 { -+ clk_osc: clock@6 { - compatible = "fixed-clock"; -- reg = <7>; -+ reg = <6>; - #clock-cells = <0>; - clock-output-names = "osc"; - clock-frequency = <19200000>; --- -2.5.0 - - -From 38ea23c3ab5d649fbcc10e3ad8b4fb9961dc32dc Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 8 Dec 2015 16:23:33 +0000 -Subject: [PATCH 76/78] bcm270x_dt: Use the sdhost MMC controller by default - -The "mmc" overlay reverts to using the other controller. ---- - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 11 ++++-- - arch/arm/boot/dts/bcm2708-rpi-b.dts | 11 ++++-- - arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 14 ++++++-- - arch/arm/boot/dts/bcm2708_common.dtsi | 13 +++++++ - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 11 ++++-- - arch/arm/boot/dts/overlays/mmc-overlay.dts | 22 +++++++++++- - arch/arm/boot/dts/overlays/sdhost-overlay.dts | 49 ++++++--------------------- - arch/arm/boot/dts/overlays/sdio-overlay.dts | 1 - - 8 files changed, 84 insertions(+), 48 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -index cd22780..4deb968 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -8,6 +8,11 @@ +diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c +index e2a2be2..e8192b4 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.c ++++ b/drivers/gpu/drm/vc4/vc4_drv.c +@@ -81,6 +81,7 @@ static const struct drm_ioctl_desc vc4_drm_ioctls[] = { + DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0), ++ DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_ROOT_ONLY), }; - &gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; + static struct drm_driver vc4_drm_driver = { +diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h +index c079b82..24845c1 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.h ++++ b/drivers/gpu/drm/vc4/vc4_drv.h +@@ -20,6 +20,8 @@ struct vc4_dev { + struct drm_fbdev_cma *fbdev; + struct rpi_firmware *firmware; + ++ struct vc4_hang_state *hang_state; + - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ -@@ -34,9 +39,11 @@ - }; - }; + /* The kernel-space BO cache. Tracks buffers that have been + * unreferenced by all other users (refcounts of 0!) but not + * yet freed, so we can do cheap allocations. +@@ -366,6 +368,8 @@ int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); + int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); ++int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); + int vc4_mmap(struct file *filp, struct vm_area_struct *vma); + int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); + void *vc4_prime_vmap(struct drm_gem_object *obj); +diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c +index 0cea723..d90c664 100644 +--- a/drivers/gpu/drm/vc4/vc4_gem.c ++++ b/drivers/gpu/drm/vc4/vc4_gem.c +@@ -40,6 +40,186 @@ vc4_queue_hangcheck(struct drm_device *dev) + round_jiffies_up(jiffies + msecs_to_jiffies(100))); + } --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts -index 0d7524e..1e77926 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -8,6 +8,11 @@ - }; - - &gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; ++struct vc4_hang_state { ++ struct drm_vc4_get_hang_state user_state; + - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ -@@ -34,9 +39,11 @@ - }; - }; - --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -index 2acefee..3c8bdde 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -@@ -1,5 +1,12 @@ - #include "bcm2708.dtsi" - -+&gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; ++ u32 bo_count; ++ struct drm_gem_object **bo; +}; + - &leds { - act_led: act { - label = "led0"; -@@ -8,9 +15,12 @@ - }; - }; - --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ non-removable; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index 91ff784..75fb4ce 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -14,6 +14,7 @@ - mailbox = &mailbox; - gpio = &gpio; - uart0 = &uart0; -+ sdhost = &sdhost; - i2s = &i2s; - spi0 = &spi0; - i2c0 = &i2c0; -@@ -126,6 +127,18 @@ - status = "disabled"; - }; - -+ sdhost: sdhost@7e202000 { -+ compatible = "brcm,bcm2835-sdhost"; -+ reg = <0x7e202000 0x100>; -+ interrupts = <2 24>; -+ clocks = <&clk_core>; -+ dmas = <&dma 13>, -+ <&dma 13>; -+ dma-names = "tx", "rx"; -+ brcm,pio-limit = <1>; -+ status = "disabled"; -+ }; ++static void ++vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state) ++{ ++ unsigned int i; + - i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>, -diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -index f45aa50..4e6c64e 100644 ---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -8,6 +8,11 @@ - }; - - &gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; ++ mutex_lock(&dev->struct_mutex); ++ for (i = 0; i < state->user_state.bo_count; i++) { ++ drm_gem_object_unreference(state->bo[i]); ++ } ++ mutex_unlock(&dev->struct_mutex); + - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ -@@ -34,9 +39,11 @@ - }; - }; - --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/overlays/mmc-overlay.dts b/arch/arm/boot/dts/overlays/mmc-overlay.dts -index 4579ff2..00a22be 100644 ---- a/arch/arm/boot/dts/overlays/mmc-overlay.dts -+++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts -@@ -6,9 +6,29 @@ - - fragment@0 { - target = <&mmc>; -- - frag0: __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc_pins>; -+ bus-width = <4>; - brcm,overclock-50 = <0>; -+ status = "okay"; -+ }; -+ }; ++ kfree(state); ++} + -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ mmc_pins: mmc_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <7>; /* alt3 */ -+ }; -+ }; -+ }; ++int ++vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ struct drm_vc4_get_hang_state *get_state = data; ++ struct drm_vc4_get_hang_state_bo *bo_state; ++ struct vc4_hang_state *kernel_state; ++ struct drm_vc4_get_hang_state *state; ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ unsigned long irqflags; ++ u32 i; ++ int ret; + -+ fragment@2 { -+ target = <&sdhost>; -+ __overlay__ { -+ status = "disabled"; - }; - }; ++ spin_lock_irqsave(&vc4->job_lock, irqflags); ++ kernel_state = vc4->hang_state; ++ if (!kernel_state) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return -ENOENT; ++ } ++ state = &kernel_state->user_state; ++ ++ /* If the user's array isn't big enough, just return the ++ * required array size. ++ */ ++ if (get_state->bo_count < state->bo_count) { ++ get_state->bo_count = state->bo_count; ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return 0; ++ } ++ ++ vc4->hang_state = NULL; ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ ++ /* Save the user's BO pointer, so we don't stomp it with the memcpy. */ ++ state->bo = get_state->bo; ++ memcpy(get_state, state, sizeof(*state)); ++ ++ bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL); ++ if (!bo_state) { ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ ++ for (i = 0; i < state->bo_count; i++) { ++ struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]); ++ u32 handle; ++ ret = drm_gem_handle_create(file_priv, kernel_state->bo[i], ++ &handle); ++ ++ if (ret) { ++ state->bo_count = i - 1; ++ goto err; ++ } ++ bo_state[i].handle = handle; ++ bo_state[i].paddr = vc4_bo->base.paddr; ++ bo_state[i].size = vc4_bo->base.base.size; ++ } ++ ++ ret = copy_to_user((void __user *)(uintptr_t)get_state->bo, ++ bo_state, ++ state->bo_count * sizeof(*bo_state)); ++ kfree(bo_state); ++ ++ err_free: ++ ++ vc4_free_hang_state(dev, kernel_state); ++ ++err: ++ return ret; ++} ++ ++static void ++vc4_save_hang_state(struct drm_device *dev) ++{ ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ struct drm_vc4_get_hang_state *state; ++ struct vc4_hang_state *kernel_state; ++ struct vc4_exec_info *exec; ++ struct vc4_bo *bo; ++ unsigned long irqflags; ++ unsigned int i, unref_list_count; ++ ++ kernel_state = kcalloc(1, sizeof(*state), GFP_KERNEL); ++ if (!kernel_state) ++ return; ++ ++ state = &kernel_state->user_state; ++ ++ spin_lock_irqsave(&vc4->job_lock, irqflags); ++ exec = vc4_first_job(vc4); ++ if (!exec) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return; ++ } ++ ++ unref_list_count = 0; ++ list_for_each_entry(bo, &exec->unref_list, unref_head) ++ unref_list_count++; ++ ++ state->bo_count = exec->bo_count + unref_list_count; ++ kernel_state->bo = kcalloc(state->bo_count, sizeof(*kernel_state->bo), ++ GFP_ATOMIC); ++ if (!kernel_state->bo) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return; ++ } ++ ++ for (i = 0; i < exec->bo_count; i++) { ++ drm_gem_object_reference(&exec->bo[i].bo->base); ++ kernel_state->bo[i] = &exec->bo[i].bo->base; ++ } ++ ++ list_for_each_entry(bo, &exec->unref_list, unref_head) { ++ drm_gem_object_reference(&bo->base.base); ++ kernel_state->bo[i] = &bo->base.base; ++ i++; ++ } ++ ++ state->start_bin = exec->ct0ca; ++ state->start_render = exec->ct1ca; ++ ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ ++ state->ct0ca = V3D_READ(V3D_CTNCA(0)); ++ state->ct0ea = V3D_READ(V3D_CTNEA(0)); ++ ++ state->ct1ca = V3D_READ(V3D_CTNCA(1)); ++ state->ct1ea = V3D_READ(V3D_CTNEA(1)); ++ ++ state->ct0cs = V3D_READ(V3D_CTNCS(0)); ++ state->ct1cs = V3D_READ(V3D_CTNCS(1)); ++ ++ state->ct0ra0 = V3D_READ(V3D_CT00RA0); ++ state->ct1ra0 = V3D_READ(V3D_CT01RA0); ++ ++ state->bpca = V3D_READ(V3D_BPCA); ++ state->bpcs = V3D_READ(V3D_BPCS); ++ state->bpoa = V3D_READ(V3D_BPOA); ++ state->bpos = V3D_READ(V3D_BPOS); ++ ++ state->vpmbase = V3D_READ(V3D_VPMBASE); ++ ++ state->dbge = V3D_READ(V3D_DBGE); ++ state->fdbgo = V3D_READ(V3D_FDBGO); ++ state->fdbgb = V3D_READ(V3D_FDBGB); ++ state->fdbgr = V3D_READ(V3D_FDBGR); ++ state->fdbgs = V3D_READ(V3D_FDBGS); ++ state->errstat = V3D_READ(V3D_ERRSTAT); ++ ++ spin_lock_irqsave(&vc4->job_lock, irqflags); ++ if (vc4->hang_state) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ vc4_free_hang_state(dev, kernel_state); ++ } else { ++ vc4->hang_state = kernel_state; ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ } ++} ++ + static void + vc4_reset(struct drm_device *dev) + { +@@ -64,6 +244,8 @@ vc4_reset_work(struct work_struct *work) + struct vc4_dev *vc4 = + container_of(work, struct vc4_dev, hangcheck.reset_work); -diff --git a/arch/arm/boot/dts/overlays/sdhost-overlay.dts b/arch/arm/boot/dts/overlays/sdhost-overlay.dts -index 2da14a4..85f0725 100644 ---- a/arch/arm/boot/dts/overlays/sdhost-overlay.dts -+++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts -@@ -5,52 +5,25 @@ - compatible = "brcm,bcm2708"; ++ vc4_save_hang_state(vc4->dev); ++ + vc4_reset(vc4->dev); + } - fragment@0 { -- target = <&soc>; -+ target = <&mmc>; - __overlay__ { -- #address-cells = <1>; -- #size-cells = <1>; -- -- sdhost: sdhost@7e202000 { -- compatible = "brcm,bcm2835-sdhost"; -- reg = <0x7e202000 0x100>; -- pinctrl-names = "default"; -- pinctrl-0 = <&sdhost_pins>; -- interrupts = <2 24>; -- clocks = <&clk_core>; -- dmas = <&dma 13>, -- <&dma 13>; -- dma-names = "tx", "rx"; -- brcm,delay-after-stop = <0>; -- brcm,overclock-50 = <0>; -- brcm,pio-limit = <1>; -- status = "okay"; -- }; -+ status = "disabled"; - }; - }; +@@ -673,4 +855,7 @@ vc4_gem_destroy(struct drm_device *dev) + } - fragment@1 { -- target = <&gpio>; -- __overlay__ { -- sdhost_pins: sdhost_pins { -- brcm,pins = <48 49 50 51 52 53>; -- brcm,function = <4>; /* alt0 */ -- }; -- }; -- }; -- -- fragment@2 { -- target = <&mmc>; -- __overlay__ { -- /* Find a way to disable the other driver */ -- compatible = ""; -- status = "disabled"; -+ target = <&sdhost>; -+ frag1: __overlay__ { -+ brcm,overclock-50 = <0>; -+ brcm,pio-limit = <1>; -+ status = "okay"; - }; - }; + vc4_bo_cache_destroy(dev); ++ ++ if (vc4->hang_state) ++ vc4_free_hang_state(dev, vc4->hang_state); + } +diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h +index 499daae..4a8d19f 100644 +--- a/include/uapi/drm/vc4_drm.h ++++ b/include/uapi/drm/vc4_drm.h +@@ -32,6 +32,7 @@ + #define DRM_VC4_CREATE_BO 0x03 + #define DRM_VC4_MMAP_BO 0x04 + #define DRM_VC4_CREATE_SHADER_BO 0x05 ++#define DRM_VC4_GET_HANG_STATE 0x06 - __overrides__ { -- overclock_50 = <&sdhost>,"brcm,overclock-50:0"; -- force_pio = <&sdhost>,"brcm,force-pio?"; -- pio_limit = <&sdhost>,"brcm,pio-limit:0"; -- debug = <&sdhost>,"brcm,debug?"; -+ overclock_50 = <&frag1>,"brcm,overclock-50:0"; -+ force_pio = <&frag1>,"brcm,force-pio?"; -+ pio_limit = <&frag1>,"brcm,pio-limit:0"; -+ debug = <&frag1>,"brcm,debug?"; - }; + #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) + #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) +@@ -39,6 +40,7 @@ + #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) + #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) + #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) ++#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) + + struct drm_vc4_submit_rcl_surface { + uint32_t hindex; /* Handle index, or ~0 if not present. */ +@@ -226,4 +228,47 @@ struct drm_vc4_mmap_bo { + uint64_t offset; }; -diff --git a/arch/arm/boot/dts/overlays/sdio-overlay.dts b/arch/arm/boot/dts/overlays/sdio-overlay.dts -index 6626a1d..afc8742 100644 ---- a/arch/arm/boot/dts/overlays/sdio-overlay.dts -+++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts -@@ -8,7 +8,6 @@ - fragment@3 { - target = <&mmc>; - sdio_mmc: __overlay__ { -- compatible = "brcm,bcm2835-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - non-removable; + ++struct drm_vc4_get_hang_state_bo { ++ uint32_t handle; ++ uint32_t paddr; ++ uint32_t size; ++ uint32_t pad; ++}; ++ ++/** ++ * struct drm_vc4_hang_state - ioctl argument for collecting state ++ * from a GPU hang for analysis. ++*/ ++struct drm_vc4_get_hang_state { ++ /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ ++ uint64_t bo; ++ /** ++ * On input, the size of the bo array. Output is the number ++ * of bos to be returned. ++ */ ++ uint32_t bo_count; ++ ++ uint32_t start_bin, start_render; ++ ++ uint32_t ct0ca, ct0ea; ++ uint32_t ct1ca, ct1ea; ++ uint32_t ct0cs, ct1cs; ++ uint32_t ct0ra0, ct1ra0; ++ ++ uint32_t bpca, bpcs; ++ uint32_t bpoa, bpos; ++ ++ uint32_t vpmbase; ++ ++ uint32_t dbge; ++ uint32_t fdbgo; ++ uint32_t fdbgb; ++ uint32_t fdbgr; ++ uint32_t fdbgs; ++ uint32_t errstat; ++ ++ /* Pad that we may save more registers into in the future. */ ++ uint32_t pad[16]; ++}; ++ + #endif /* _UAPI_VC4_DRM_H_ */ -- 2.5.0 -From aec321ec39ccb0b2e86f0db2a9b0dd4598d2435d Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Wed, 9 Dec 2015 11:38:15 +0000 -Subject: [PATCH 77/78] bcm2835-sdhost: Don't log timeout errors unless debug=1 +From 5f726bd15729062dd4cf89c22d9f15d4c2979d3d Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 4 Dec 2015 11:35:34 -0800 +Subject: [PATCH 54/59] drm/vc4: Update a bunch of code to match upstream + submission. -The MMC card-discovery process generates timeouts. This is -expected behaviour, so reporting it to the user serves no purpose. -Suppress the reporting of timeout errors unless the debug flag -is on. +This gets almost everything matching, except for the MSAA support and +using generic PM domains. + +Signed-off-by: Eric Anholt --- - drivers/mmc/host/bcm2835-sdhost.c | 18 +++++++----------- - 1 file changed, 7 insertions(+), 11 deletions(-) + drivers/gpu/drm/drm_gem_cma_helper.c | 13 +- + drivers/gpu/drm/vc4/vc4_bo.c | 322 +++++++++++++++++------------ + drivers/gpu/drm/vc4/vc4_crtc.c | 7 +- + drivers/gpu/drm/vc4/vc4_drv.c | 6 +- + drivers/gpu/drm/vc4/vc4_drv.h | 20 +- + drivers/gpu/drm/vc4/vc4_gem.c | 24 ++- + drivers/gpu/drm/vc4/vc4_irq.c | 5 +- + drivers/gpu/drm/vc4/vc4_kms.c | 1 + + drivers/gpu/drm/vc4/vc4_packet.h | 210 +++++++++---------- + drivers/gpu/drm/vc4/vc4_qpu_defines.h | 308 ++++++++++++++------------- + drivers/gpu/drm/vc4/vc4_render_cl.c | 4 +- + drivers/gpu/drm/vc4/vc4_v3d.c | 10 +- + drivers/gpu/drm/vc4/vc4_validate.c | 130 ++++++------ + drivers/gpu/drm/vc4/vc4_validate_shaders.c | 66 +++--- + include/drm/drmP.h | 8 +- + 15 files changed, 598 insertions(+), 536 deletions(-) -diff --git a/drivers/mmc/host/bcm2835-sdhost.c b/drivers/mmc/host/bcm2835-sdhost.c -index 0623392..0136aef 100644 ---- a/drivers/mmc/host/bcm2835-sdhost.c -+++ b/drivers/mmc/host/bcm2835-sdhost.c -@@ -966,19 +966,15 @@ static void bcm2835_sdhost_finish_command(struct bcm2835_host *host) - mmc_hostname(host->mmc)); - } else { - if (sdhsts & SDHSTS_CMD_TIME_OUT) { -- switch (host->cmd->opcode) { -- case 5: case 52: case 53: -- /* Don't warn about SDIO commands */ -- break; -- default: -- pr_err("%s: command timeout\n", -- mmc_hostname(host->mmc)); -- break; -- } -+ if (host->debug) -+ pr_err("%s: command %d timeout\n", -+ mmc_hostname(host->mmc), -+ host->cmd->opcode); - host->cmd->error = -ETIMEDOUT; - } else { -- pr_err("%s: unexpected command error\n", -- mmc_hostname(host->mmc)); -+ pr_err("%s: unexpected command %d error\n", -+ mmc_hostname(host->mmc), -+ host->cmd->opcode); - bcm2835_sdhost_dumpregs(host); - host->cmd->error = -EIO; +diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c +index 1c25500..0f7b00b 100644 +--- a/drivers/gpu/drm/drm_gem_cma_helper.c ++++ b/drivers/gpu/drm/drm_gem_cma_helper.c +@@ -58,15 +58,14 @@ __drm_gem_cma_create(struct drm_device *drm, size_t size) + struct drm_gem_cma_object *cma_obj; + struct drm_gem_object *gem_obj; + int ret; +- size_t obj_size = (drm->driver->gem_obj_size ? +- drm->driver->gem_obj_size : +- sizeof(*cma_obj)); + +- cma_obj = kzalloc(obj_size, GFP_KERNEL); +- if (!cma_obj) ++ if (drm->driver->gem_create_object) ++ gem_obj = drm->driver->gem_create_object(drm, size); ++ else ++ gem_obj = kzalloc(sizeof(*cma_obj), GFP_KERNEL); ++ if (!gem_obj) + return ERR_PTR(-ENOMEM); +- +- gem_obj = &cma_obj->base; ++ cma_obj = container_of(gem_obj, struct drm_gem_cma_object, base); + + ret = drm_gem_object_init(drm, gem_obj, size); + if (ret) +diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c +index 58dcbae..6247ff8 100644 +--- a/drivers/gpu/drm/vc4/vc4_bo.c ++++ b/drivers/gpu/drm/vc4/vc4_bo.c +@@ -12,6 +12,10 @@ + * access to system memory with no MMU in between. To support it, we + * use the GEM CMA helper functions to allocate contiguous ranges of + * physical memory for our BOs. ++ * ++ * Since the CMA allocator is very slow, we keep a cache of recently ++ * freed BOs around so that the kernel's allocation of objects for 3D ++ * rendering can return quickly. + */ + + #include "vc4_drv.h" +@@ -34,6 +38,36 @@ static void vc4_bo_stats_dump(struct vc4_dev *vc4) + vc4->bo_stats.size_cached / 1024); + } + ++#ifdef CONFIG_DEBUG_FS ++int vc4_bo_stats_debugfs(struct seq_file *m, void *unused) ++{ ++ struct drm_info_node *node = (struct drm_info_node *)m->private; ++ struct drm_device *dev = node->minor->dev; ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ struct vc4_bo_stats stats; ++ ++ /* Take a snapshot of the current stats with the lock held. */ ++ mutex_lock(&vc4->bo_lock); ++ stats = vc4->bo_stats; ++ mutex_unlock(&vc4->bo_lock); ++ ++ seq_printf(m, "num bos allocated: %d\n", ++ stats.num_allocated); ++ seq_printf(m, "size bos allocated: %dkb\n", ++ stats.size_allocated / 1024); ++ seq_printf(m, "num bos used: %d\n", ++ stats.num_allocated - stats.num_cached); ++ seq_printf(m, "size bos used: %dkb\n", ++ (stats.size_allocated - stats.size_cached) / 1024); ++ seq_printf(m, "num bos cached: %d\n", ++ stats.num_cached); ++ seq_printf(m, "size bos cached: %dkb\n", ++ stats.size_cached / 1024); ++ ++ return 0; ++} ++#endif ++ + static uint32_t bo_page_index(size_t size) + { + return (size / PAGE_SIZE) - 1; +@@ -81,8 +115,8 @@ static struct list_head *vc4_get_cache_list_for_size(struct drm_device *dev, + struct list_head *new_list; + uint32_t i; + +- new_list = kmalloc(new_size * sizeof(struct list_head), +- GFP_KERNEL); ++ new_list = kmalloc_array(new_size, sizeof(struct list_head), ++ GFP_KERNEL); + if (!new_list) + return NULL; + +@@ -90,7 +124,9 @@ static struct list_head *vc4_get_cache_list_for_size(struct drm_device *dev, + * head locations. + */ + for (i = 0; i < vc4->bo_cache.size_list_size; i++) { +- struct list_head *old_list = &vc4->bo_cache.size_list[i]; ++ struct list_head *old_list = ++ &vc4->bo_cache.size_list[i]; ++ + if (list_empty(old_list)) + INIT_LIST_HEAD(&new_list[i]); + else +@@ -122,11 +158,60 @@ void vc4_bo_cache_purge(struct drm_device *dev) + mutex_unlock(&vc4->bo_lock); + } + +-struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size) ++static struct vc4_bo *vc4_bo_get_from_cache(struct drm_device *dev, ++ uint32_t size) + { + struct vc4_dev *vc4 = to_vc4_dev(dev); +- uint32_t size = roundup(unaligned_size, PAGE_SIZE); + uint32_t page_index = bo_page_index(size); ++ struct vc4_bo *bo = NULL; ++ ++ size = roundup(size, PAGE_SIZE); ++ ++ mutex_lock(&vc4->bo_lock); ++ if (page_index >= vc4->bo_cache.size_list_size) ++ goto out; ++ ++ if (list_empty(&vc4->bo_cache.size_list[page_index])) ++ goto out; ++ ++ bo = list_first_entry(&vc4->bo_cache.size_list[page_index], ++ struct vc4_bo, size_head); ++ vc4_bo_remove_from_cache(bo); ++ kref_init(&bo->base.base.refcount); ++ ++out: ++ mutex_unlock(&vc4->bo_lock); ++ return bo; ++} ++ ++/** ++ * vc4_gem_create_object - Implementation of driver->gem_create_object. ++ * ++ * This lets the CMA helpers allocate object structs for us, and keep ++ * our BO stats correct. ++ */ ++struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size) ++{ ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ struct vc4_bo *bo; ++ ++ bo = kzalloc(sizeof(*bo), GFP_KERNEL); ++ if (!bo) ++ return ERR_PTR(-ENOMEM); ++ ++ mutex_lock(&vc4->bo_lock); ++ vc4->bo_stats.num_allocated++; ++ vc4->bo_stats.size_allocated += size; ++ mutex_unlock(&vc4->bo_lock); ++ ++ return &bo->base.base; ++} ++ ++struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size, ++ bool from_cache) ++{ ++ size_t size = roundup(unaligned_size, PAGE_SIZE); ++ struct vc4_dev *vc4 = to_vc4_dev(dev); + struct drm_gem_cma_object *cma_obj; + int pass; + +@@ -134,18 +219,12 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size) + return NULL; + + /* First, try to get a vc4_bo from the kernel BO cache. */ +- mutex_lock(&vc4->bo_lock); +- if (page_index < vc4->bo_cache.size_list_size && +- !list_empty(&vc4->bo_cache.size_list[page_index])) { +- struct vc4_bo *bo = +- list_first_entry(&vc4->bo_cache.size_list[page_index], +- struct vc4_bo, size_head); +- vc4_bo_remove_from_cache(bo); +- mutex_unlock(&vc4->bo_lock); +- kref_init(&bo->base.base.refcount); +- return bo; ++ if (from_cache) { ++ struct vc4_bo *bo = vc4_bo_get_from_cache(dev, size); ++ ++ if (bo) ++ return bo; + } +- mutex_unlock(&vc4->bo_lock); + + /* Otherwise, make a new BO. */ + for (pass = 0; ; pass++) { +@@ -179,9 +258,6 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size) + } + } + +- vc4->bo_stats.num_allocated++; +- vc4->bo_stats.size_allocated += size; +- + return to_vc4_bo(&cma_obj->base); + } + +@@ -199,7 +275,7 @@ int vc4_dumb_create(struct drm_file *file_priv, + if (args->size < args->pitch * args->height) + args->size = args->pitch * args->height; + +- bo = vc4_bo_create(dev, args->size); ++ bo = vc4_bo_create(dev, args->size, false); + if (!bo) + return -ENOMEM; + +@@ -209,8 +285,8 @@ int vc4_dumb_create(struct drm_file *file_priv, + return ret; + } + +-static void +-vc4_bo_cache_free_old(struct drm_device *dev) ++/* Must be called with bo_lock held. */ ++static void vc4_bo_cache_free_old(struct drm_device *dev) + { + struct vc4_dev *vc4 = to_vc4_dev(dev); + unsigned long expire_time = jiffies - msecs_to_jiffies(1000); +@@ -313,15 +389,77 @@ vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags) + return drm_gem_prime_export(dev, obj, flags); + } + +-int +-vc4_create_bo_ioctl(struct drm_device *dev, void *data, +- struct drm_file *file_priv) ++int vc4_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ struct drm_gem_object *gem_obj; ++ struct vc4_bo *bo; ++ int ret; ++ ++ ret = drm_gem_mmap(filp, vma); ++ if (ret) ++ return ret; ++ ++ gem_obj = vma->vm_private_data; ++ bo = to_vc4_bo(gem_obj); ++ ++ if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { ++ DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); ++ return -EINVAL; ++ } ++ ++ /* ++ * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the ++ * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map ++ * the whole buffer. ++ */ ++ vma->vm_flags &= ~VM_PFNMAP; ++ vma->vm_pgoff = 0; ++ ++ ret = dma_mmap_writecombine(bo->base.base.dev->dev, vma, ++ bo->base.vaddr, bo->base.paddr, ++ vma->vm_end - vma->vm_start); ++ if (ret) ++ drm_gem_vm_close(vma); ++ ++ return ret; ++} ++ ++int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) ++{ ++ struct vc4_bo *bo = to_vc4_bo(obj); ++ ++ if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { ++ DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); ++ return -EINVAL; ++ } ++ ++ return drm_gem_cma_prime_mmap(obj, vma); ++} ++ ++void *vc4_prime_vmap(struct drm_gem_object *obj) ++{ ++ struct vc4_bo *bo = to_vc4_bo(obj); ++ ++ if (bo->validated_shader) { ++ DRM_ERROR("mmaping of shader BOs not allowed.\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return drm_gem_cma_prime_vmap(obj); ++} ++ ++int vc4_create_bo_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) + { + struct drm_vc4_create_bo *args = data; + struct vc4_bo *bo = NULL; + int ret; + +- bo = vc4_bo_create(dev, args->size); ++ /* ++ * We can't allocate from the BO cache, because the BOs don't ++ * get zeroed, and that might leak data between users. ++ */ ++ bo = vc4_bo_create(dev, args->size, false); + if (!bo) + return -ENOMEM; + +@@ -331,6 +469,25 @@ vc4_create_bo_ioctl(struct drm_device *dev, void *data, + return ret; + } + ++int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ struct drm_vc4_mmap_bo *args = data; ++ struct drm_gem_object *gem_obj; ++ ++ gem_obj = drm_gem_object_lookup(dev, file_priv, args->handle); ++ if (!gem_obj) { ++ DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); ++ return -EINVAL; ++ } ++ ++ /* The mmap offset was set up at BO allocation time. */ ++ args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node); ++ ++ drm_gem_object_unreference_unlocked(gem_obj); ++ return 0; ++} ++ + int + vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +@@ -355,7 +512,7 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + return -EINVAL; + } + +- bo = vc4_bo_create(dev, args->size); ++ bo = vc4_bo_create(dev, args->size, true); + if (!bo) + return -ENOMEM; + +@@ -364,6 +521,11 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + args->size); + if (ret != 0) + goto fail; ++ /* Clear the rest of the memory from allocating from the BO ++ * cache. ++ */ ++ memset(bo->base.vaddr + args->size, 0, ++ bo->base.base.size - args->size); + + bo->validated_shader = vc4_validate_shader(&bo->base); + if (!bo->validated_shader) { +@@ -382,85 +544,6 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + return ret; + } + +-int +-vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, +- struct drm_file *file_priv) +-{ +- struct drm_vc4_mmap_bo *args = data; +- struct drm_gem_object *gem_obj; +- +- gem_obj = drm_gem_object_lookup(dev, file_priv, args->handle); +- if (!gem_obj) { +- DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); +- return -EINVAL; +- } +- +- /* The mmap offset was set up at BO allocation time. */ +- args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node); +- +- drm_gem_object_unreference(gem_obj); +- return 0; +-} +- +-int vc4_mmap(struct file *filp, struct vm_area_struct *vma) +-{ +- struct drm_gem_object *gem_obj; +- struct vc4_bo *bo; +- int ret; +- +- ret = drm_gem_mmap(filp, vma); +- if (ret) +- return ret; +- +- gem_obj = vma->vm_private_data; +- bo = to_vc4_bo(gem_obj); +- +- if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { +- DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); +- return -EINVAL; +- } +- +- /* +- * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the +- * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map +- * the whole buffer. +- */ +- vma->vm_flags &= ~VM_PFNMAP; +- vma->vm_pgoff = 0; +- +- ret = dma_mmap_writecombine(bo->base.base.dev->dev, vma, +- bo->base.vaddr, bo->base.paddr, +- vma->vm_end - vma->vm_start); +- if (ret) +- drm_gem_vm_close(vma); +- +- return ret; +-} +- +-int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) +-{ +- struct vc4_bo *bo = to_vc4_bo(obj); +- +- if (bo->validated_shader) { +- DRM_ERROR("mmaping of shader BOs not allowed.\n"); +- return -EINVAL; +- } +- +- return drm_gem_cma_prime_mmap(obj, vma); +-} +- +-void *vc4_prime_vmap(struct drm_gem_object *obj) +-{ +- struct vc4_bo *bo = to_vc4_bo(obj); +- +- if (bo->validated_shader) { +- DRM_ERROR("mmaping of shader BOs not allowed.\n"); +- return ERR_PTR(-EINVAL); +- } +- +- return drm_gem_cma_prime_vmap(obj); +-} +- + void vc4_bo_cache_init(struct drm_device *dev) + { + struct vc4_dev *vc4 = to_vc4_dev(dev); +@@ -472,7 +555,7 @@ void vc4_bo_cache_init(struct drm_device *dev) + INIT_WORK(&vc4->bo_cache.time_work, vc4_bo_cache_time_work); + setup_timer(&vc4->bo_cache.time_timer, + vc4_bo_cache_time_timer, +- (unsigned long) dev); ++ (unsigned long)dev); + } + + void vc4_bo_cache_destroy(struct drm_device *dev) +@@ -489,28 +572,3 @@ void vc4_bo_cache_destroy(struct drm_device *dev) + vc4_bo_stats_dump(vc4); + } + } +- +-#ifdef CONFIG_DEBUG_FS +-int vc4_bo_stats_debugfs(struct seq_file *m, void *unused) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- struct vc4_dev *vc4 = to_vc4_dev(dev); +- struct vc4_bo_stats stats; +- +- mutex_lock(&vc4->bo_lock); +- stats = vc4->bo_stats; +- mutex_unlock(&vc4->bo_lock); +- +- seq_printf(m, "num bos allocated: %d\n", stats.num_allocated); +- seq_printf(m, "size bos allocated: %dkb\n", stats.size_allocated / 1024); +- seq_printf(m, "num bos used: %d\n", (stats.num_allocated - +- stats.num_cached)); +- seq_printf(m, "size bos used: %dkb\n", (stats.size_allocated - +- stats.size_cached) / 1024); +- seq_printf(m, "num bos cached: %d\n", stats.num_cached); +- seq_printf(m, "size bos cached: %dkb\n", stats.size_cached / 1024); +- +- return 0; +-} +-#endif +diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c +index 3be2720..3c67914 100644 +--- a/drivers/gpu/drm/vc4/vc4_crtc.c ++++ b/drivers/gpu/drm/vc4/vc4_crtc.c +@@ -501,6 +501,7 @@ vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) + vc4_plane_async_set_fb(plane, flip_state->fb); + if (flip_state->event) { + unsigned long flags; ++ + spin_lock_irqsave(&dev->event_lock, flags); + drm_crtc_send_vblank_event(crtc, flip_state->event); + spin_unlock_irqrestore(&dev->event_lock, flags); +@@ -562,9 +563,9 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, + } + + static int vc4_page_flip(struct drm_crtc *crtc, +- struct drm_framebuffer *fb, +- struct drm_pending_vblank_event *event, +- uint32_t flags) ++ struct drm_framebuffer *fb, ++ struct drm_pending_vblank_event *event, ++ uint32_t flags) + { + if (flags & DRM_MODE_PAGE_FLIP_ASYNC) + return vc4_async_page_flip(crtc, fb, event, flags); +diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c +index e8192b4..22061ae 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.c ++++ b/drivers/gpu/drm/vc4/vc4_drv.c +@@ -81,7 +81,8 @@ static const struct drm_ioctl_desc vc4_drm_ioctls[] = { + DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0), +- DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_ROOT_ONLY), ++ DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, ++ DRM_ROOT_ONLY), + }; + + static struct drm_driver vc4_drm_driver = { +@@ -107,6 +108,7 @@ static struct drm_driver vc4_drm_driver = { + .debugfs_cleanup = vc4_debugfs_cleanup, + #endif + ++ .gem_create_object = vc4_create_object, + .gem_free_object = vc4_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + +@@ -128,8 +130,6 @@ static struct drm_driver vc4_drm_driver = { + .num_ioctls = ARRAY_SIZE(vc4_drm_ioctls), + .fops = &vc4_drm_fops, + +- //.gem_obj_size = sizeof(struct vc4_bo), +- + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, +diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h +index 24845c1..53dfa8d 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.h ++++ b/drivers/gpu/drm/vc4/vc4_drv.h +@@ -72,6 +72,9 @@ struct vc4_dev { + * job_done_work. + */ + struct list_head job_done_list; ++ /* Spinlock used to synchronize the job_list and seqno ++ * accesses between the IRQ handler and GEM ioctls. ++ */ + spinlock_t job_lock; + wait_queue_head_t job_wait_queue; + struct work_struct job_done_work; +@@ -318,8 +321,7 @@ struct vc4_texture_sample_info { + * and validate the shader state record's uniforms that define the texture + * samples. + */ +-struct vc4_validated_shader_info +-{ ++struct vc4_validated_shader_info { + uint32_t uniforms_size; + uint32_t uniforms_src_size; + uint32_t num_texture_samples; +@@ -355,8 +357,10 @@ struct vc4_validated_shader_info + #define wait_for(COND, MS) _wait_for(COND, MS, 1) + + /* vc4_bo.c */ ++struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); + void vc4_free_object(struct drm_gem_object *gem_obj); +-struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size); ++struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, ++ bool from_cache); + int vc4_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args); +@@ -432,7 +436,8 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev, + enum drm_plane_type type); + u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); + u32 vc4_plane_dlist_size(struct drm_plane_state *state); +-void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb); ++void vc4_plane_async_set_fb(struct drm_plane *plane, ++ struct drm_framebuffer *fb); + + /* vc4_v3d.c */ + extern struct platform_driver vc4_v3d_driver; +@@ -450,9 +455,6 @@ vc4_validate_bin_cl(struct drm_device *dev, + int + vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); + +-struct vc4_validated_shader_info * +-vc4_validate_shader(struct drm_gem_cma_object *shader_obj); +- + bool vc4_use_bo(struct vc4_exec_info *exec, + uint32_t hindex, + enum vc4_bo_mode mode, +@@ -464,3 +466,7 @@ bool vc4_check_tex_size(struct vc4_exec_info *exec, + struct drm_gem_cma_object *fbo, + uint32_t offset, uint8_t tiling_format, + uint32_t width, uint32_t height, uint8_t cpp); ++ ++/* vc4_validate_shader.c */ ++struct vc4_validated_shader_info * ++vc4_validate_shader(struct drm_gem_cma_object *shader_obj); +diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c +index d90c664..fb0b92d 100644 +--- a/drivers/gpu/drm/vc4/vc4_gem.c ++++ b/drivers/gpu/drm/vc4/vc4_gem.c +@@ -53,9 +53,8 @@ vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state) + unsigned int i; + + mutex_lock(&dev->struct_mutex); +- for (i = 0; i < state->user_state.bo_count; i++) { ++ for (i = 0; i < state->user_state.bo_count; i++) + drm_gem_object_unreference(state->bo[i]); +- } + mutex_unlock(&dev->struct_mutex); + + kfree(state); +@@ -65,10 +64,10 @@ int + vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) + { +- struct drm_vc4_get_hang_state *get_state = data; ++ struct drm_vc4_get_hang_state *get_state = data; + struct drm_vc4_get_hang_state_bo *bo_state; + struct vc4_hang_state *kernel_state; +- struct drm_vc4_get_hang_state *state; ++ struct drm_vc4_get_hang_state *state; + struct vc4_dev *vc4 = to_vc4_dev(dev); + unsigned long irqflags; + u32 i; +@@ -107,6 +106,7 @@ vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, + for (i = 0; i < state->bo_count; i++) { + struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]); + u32 handle; ++ + ret = drm_gem_handle_create(file_priv, kernel_state->bo[i], + &handle); + +@@ -124,7 +124,7 @@ vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, + state->bo_count * sizeof(*bo_state)); + kfree(bo_state); + +- err_free: ++err_free: + + vc4_free_hang_state(dev, kernel_state); + +@@ -578,7 +578,7 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) + goto fail; + } + +- bo = vc4_bo_create(dev, exec_size); ++ bo = vc4_bo_create(dev, exec_size, true); + if (!bo) { + DRM_ERROR("Couldn't allocate BO for binning\n"); + ret = PTR_ERR(exec->exec_bo); +@@ -668,6 +668,7 @@ vc4_job_handle_completed(struct vc4_dev *vc4) + static void vc4_seqno_cb_work(struct work_struct *work) + { + struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work); ++ + cb->func(cb); + } + +@@ -717,6 +718,7 @@ vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev, + + if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) { + uint64_t delta = jiffies_to_nsecs(jiffies - start); ++ + if (*timeout_ns >= delta) + *timeout_ns -= delta; + } +@@ -750,9 +752,10 @@ vc4_wait_bo_ioctl(struct drm_device *dev, void *data, + } + bo = to_vc4_bo(gem_obj); + +- ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, &args->timeout_ns); ++ ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, ++ &args->timeout_ns); + +- drm_gem_object_unreference(gem_obj); ++ drm_gem_object_unreference_unlocked(gem_obj); + return ret; + } + +@@ -793,7 +796,8 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data, + if (ret) + goto fail; + } else { +- exec->ct0ca = exec->ct0ea = 0; ++ exec->ct0ca = 0; ++ exec->ct0ea = 0; + } + + ret = vc4_get_rcl(dev, exec); +@@ -831,7 +835,7 @@ vc4_gem_init(struct drm_device *dev) + INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work); + setup_timer(&vc4->hangcheck.timer, + vc4_hangcheck_elapsed, +- (unsigned long) dev); ++ (unsigned long)dev); + + INIT_WORK(&vc4->job_done_work, vc4_job_done_work); + } +diff --git a/drivers/gpu/drm/vc4/vc4_irq.c b/drivers/gpu/drm/vc4/vc4_irq.c +index f29b796..b68060e 100644 +--- a/drivers/gpu/drm/vc4/vc4_irq.c ++++ b/drivers/gpu/drm/vc4/vc4_irq.c +@@ -56,7 +56,7 @@ vc4_overflow_mem_work(struct work_struct *work) + struct drm_device *dev = vc4->dev; + struct vc4_bo *bo; + +- bo = vc4_bo_create(dev, 256 * 1024); ++ bo = vc4_bo_create(dev, 256 * 1024, true); + if (!bo) { + DRM_ERROR("Couldn't allocate binner overflow mem\n"); + return; +@@ -87,9 +87,8 @@ vc4_overflow_mem_work(struct work_struct *work) + spin_unlock_irqrestore(&vc4->job_lock, irqflags); + } + +- if (vc4->overflow_mem) { ++ if (vc4->overflow_mem) + drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base); +- } + vc4->overflow_mem = bo; + + V3D_WRITE(V3D_BPOA, bo->base.paddr); +diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c +index 2082713..f95f2df 100644 +--- a/drivers/gpu/drm/vc4/vc4_kms.c ++++ b/drivers/gpu/drm/vc4/vc4_kms.c +@@ -132,6 +132,7 @@ static int vc4_atomic_commit(struct drm_device *dev, + struct drm_gem_cma_object *cma_bo = + drm_fb_cma_get_gem_obj(new_state->fb, 0); + struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); ++ + wait_seqno = max(bo->seqno, wait_seqno); + } + } +diff --git a/drivers/gpu/drm/vc4/vc4_packet.h b/drivers/gpu/drm/vc4/vc4_packet.h +index 9757bc8..cee38aa 100644 +--- a/drivers/gpu/drm/vc4/vc4_packet.h ++++ b/drivers/gpu/drm/vc4/vc4_packet.h +@@ -27,60 +27,60 @@ + #include "vc4_regs.h" /* for VC4_MASK, VC4_GET_FIELD, VC4_SET_FIELD */ + + enum vc4_packet { +- VC4_PACKET_HALT = 0, +- VC4_PACKET_NOP = 1, +- +- VC4_PACKET_FLUSH = 4, +- VC4_PACKET_FLUSH_ALL = 5, +- VC4_PACKET_START_TILE_BINNING = 6, +- VC4_PACKET_INCREMENT_SEMAPHORE = 7, +- VC4_PACKET_WAIT_ON_SEMAPHORE = 8, +- +- VC4_PACKET_BRANCH = 16, +- VC4_PACKET_BRANCH_TO_SUB_LIST = 17, +- +- VC4_PACKET_STORE_MS_TILE_BUFFER = 24, +- VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, +- VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, +- VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, +- VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, +- VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, +- +- VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, +- VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, +- +- VC4_PACKET_COMPRESSED_PRIMITIVE = 48, +- VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, +- +- VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, +- +- VC4_PACKET_GL_SHADER_STATE = 64, +- VC4_PACKET_NV_SHADER_STATE = 65, +- VC4_PACKET_VG_SHADER_STATE = 66, +- +- VC4_PACKET_CONFIGURATION_BITS = 96, +- VC4_PACKET_FLAT_SHADE_FLAGS = 97, +- VC4_PACKET_POINT_SIZE = 98, +- VC4_PACKET_LINE_WIDTH = 99, +- VC4_PACKET_RHT_X_BOUNDARY = 100, +- VC4_PACKET_DEPTH_OFFSET = 101, +- VC4_PACKET_CLIP_WINDOW = 102, +- VC4_PACKET_VIEWPORT_OFFSET = 103, +- VC4_PACKET_Z_CLIPPING = 104, +- VC4_PACKET_CLIPPER_XY_SCALING = 105, +- VC4_PACKET_CLIPPER_Z_SCALING = 106, +- +- VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, +- VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, +- VC4_PACKET_CLEAR_COLORS = 114, +- VC4_PACKET_TILE_COORDINATES = 115, +- +- /* Not an actual hardware packet -- this is what we use to put +- * references to GEM bos in the command stream, since we need the u32 +- * int the actual address packet in order to store the offset from the +- * start of the BO. +- */ +- VC4_PACKET_GEM_HANDLES = 254, ++ VC4_PACKET_HALT = 0, ++ VC4_PACKET_NOP = 1, ++ ++ VC4_PACKET_FLUSH = 4, ++ VC4_PACKET_FLUSH_ALL = 5, ++ VC4_PACKET_START_TILE_BINNING = 6, ++ VC4_PACKET_INCREMENT_SEMAPHORE = 7, ++ VC4_PACKET_WAIT_ON_SEMAPHORE = 8, ++ ++ VC4_PACKET_BRANCH = 16, ++ VC4_PACKET_BRANCH_TO_SUB_LIST = 17, ++ ++ VC4_PACKET_STORE_MS_TILE_BUFFER = 24, ++ VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, ++ VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, ++ VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, ++ VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, ++ VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, ++ ++ VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, ++ VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, ++ ++ VC4_PACKET_COMPRESSED_PRIMITIVE = 48, ++ VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, ++ ++ VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, ++ ++ VC4_PACKET_GL_SHADER_STATE = 64, ++ VC4_PACKET_NV_SHADER_STATE = 65, ++ VC4_PACKET_VG_SHADER_STATE = 66, ++ ++ VC4_PACKET_CONFIGURATION_BITS = 96, ++ VC4_PACKET_FLAT_SHADE_FLAGS = 97, ++ VC4_PACKET_POINT_SIZE = 98, ++ VC4_PACKET_LINE_WIDTH = 99, ++ VC4_PACKET_RHT_X_BOUNDARY = 100, ++ VC4_PACKET_DEPTH_OFFSET = 101, ++ VC4_PACKET_CLIP_WINDOW = 102, ++ VC4_PACKET_VIEWPORT_OFFSET = 103, ++ VC4_PACKET_Z_CLIPPING = 104, ++ VC4_PACKET_CLIPPER_XY_SCALING = 105, ++ VC4_PACKET_CLIPPER_Z_SCALING = 106, ++ ++ VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, ++ VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, ++ VC4_PACKET_CLEAR_COLORS = 114, ++ VC4_PACKET_TILE_COORDINATES = 115, ++ ++ /* Not an actual hardware packet -- this is what we use to put ++ * references to GEM bos in the command stream, since we need the u32 ++ * int the actual address packet in order to store the offset from the ++ * start of the BO. ++ */ ++ VC4_PACKET_GEM_HANDLES = 254, + } __attribute__ ((__packed__)); + + #define VC4_PACKET_HALT_SIZE 1 +@@ -148,10 +148,10 @@ enum vc4_packet { + * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) + */ + +-#define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3) +-#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2) +-#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1) +-#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0) ++#define VC4_LOADSTORE_TILE_BUFFER_EOF BIT(3) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK BIT(2) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS BIT(1) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR BIT(0) + + /** @} */ + +@@ -160,10 +160,10 @@ enum vc4_packet { + * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL + */ +-#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15) +-#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14) +-#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13) +-#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12) ++#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR BIT(15) ++#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR BIT(14) ++#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR BIT(13) ++#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP BIT(12) + + #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) + #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 +@@ -201,28 +201,28 @@ enum vc4_packet { + #define VC4_INDEX_BUFFER_U16 (1 << 4) + + /* This flag is only present in NV shader state. */ +-#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3) +-#define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2) +-#define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1) +-#define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0) ++#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS BIT(3) ++#define VC4_SHADER_FLAG_ENABLE_CLIPPING BIT(2) ++#define VC4_SHADER_FLAG_VS_POINT_SIZE BIT(1) ++#define VC4_SHADER_FLAG_FS_SINGLE_THREAD BIT(0) + + /** @{ byte 2 of config bits. */ +-#define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1) +-#define VC4_CONFIG_BITS_EARLY_Z (1 << 0) ++#define VC4_CONFIG_BITS_EARLY_Z_UPDATE BIT(1) ++#define VC4_CONFIG_BITS_EARLY_Z BIT(0) + /** @} */ + + /** @{ byte 1 of config bits. */ +-#define VC4_CONFIG_BITS_Z_UPDATE (1 << 7) ++#define VC4_CONFIG_BITS_Z_UPDATE BIT(7) + /** same values in this 3-bit field as PIPE_FUNC_* */ + #define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 +-#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3) ++#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE BIT(3) + + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) + +-#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0) ++#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT BIT(0) + /** @} */ + + /** @{ byte 0 of config bits. */ +@@ -230,15 +230,15 @@ enum vc4_packet { + #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) + #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) + +-#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4) +-#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3) +-#define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2) +-#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1) +-#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0) ++#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES BIT(4) ++#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET BIT(3) ++#define VC4_CONFIG_BITS_CW_PRIMITIVES BIT(2) ++#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK BIT(1) ++#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT BIT(0) + /** @} */ + + /** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ +-#define VC4_BIN_CONFIG_DB_NON_MS (1 << 7) ++#define VC4_BIN_CONFIG_DB_NON_MS BIT(7) + + #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) + #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 +@@ -254,17 +254,17 @@ enum vc4_packet { + #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 + #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 + +-#define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2) +-#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1) +-#define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0) ++#define VC4_BIN_CONFIG_AUTO_INIT_TSDA BIT(2) ++#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT BIT(1) ++#define VC4_BIN_CONFIG_MS_MODE_4X BIT(0) + /** @} */ + + /** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ +-#define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12) +-#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11) +-#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10) +-#define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9) +-#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8) ++#define VC4_RENDER_CONFIG_DB_NON_MS BIT(12) ++#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE BIT(11) ++#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G BIT(10) ++#define VC4_RENDER_CONFIG_COVERAGE_MODE BIT(9) ++#define VC4_RENDER_CONFIG_ENABLE_VG_MASK BIT(8) + + /** The values of the field are VC4_TILING_FORMAT_* */ + #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) +@@ -280,8 +280,8 @@ enum vc4_packet { + #define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 + #define VC4_RENDER_CONFIG_FORMAT_BGR565 2 + +-#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1) +-#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0) ++#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT BIT(1) ++#define VC4_RENDER_CONFIG_MS_MODE_4X BIT(0) + + #define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) + #define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) +@@ -291,24 +291,24 @@ enum vc4_packet { + #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) + + enum vc4_texture_data_type { +- VC4_TEXTURE_TYPE_RGBA8888 = 0, +- VC4_TEXTURE_TYPE_RGBX8888 = 1, +- VC4_TEXTURE_TYPE_RGBA4444 = 2, +- VC4_TEXTURE_TYPE_RGBA5551 = 3, +- VC4_TEXTURE_TYPE_RGB565 = 4, +- VC4_TEXTURE_TYPE_LUMINANCE = 5, +- VC4_TEXTURE_TYPE_ALPHA = 6, +- VC4_TEXTURE_TYPE_LUMALPHA = 7, +- VC4_TEXTURE_TYPE_ETC1 = 8, +- VC4_TEXTURE_TYPE_S16F = 9, +- VC4_TEXTURE_TYPE_S8 = 10, +- VC4_TEXTURE_TYPE_S16 = 11, +- VC4_TEXTURE_TYPE_BW1 = 12, +- VC4_TEXTURE_TYPE_A4 = 13, +- VC4_TEXTURE_TYPE_A1 = 14, +- VC4_TEXTURE_TYPE_RGBA64 = 15, +- VC4_TEXTURE_TYPE_RGBA32R = 16, +- VC4_TEXTURE_TYPE_YUV422R = 17, ++ VC4_TEXTURE_TYPE_RGBA8888 = 0, ++ VC4_TEXTURE_TYPE_RGBX8888 = 1, ++ VC4_TEXTURE_TYPE_RGBA4444 = 2, ++ VC4_TEXTURE_TYPE_RGBA5551 = 3, ++ VC4_TEXTURE_TYPE_RGB565 = 4, ++ VC4_TEXTURE_TYPE_LUMINANCE = 5, ++ VC4_TEXTURE_TYPE_ALPHA = 6, ++ VC4_TEXTURE_TYPE_LUMALPHA = 7, ++ VC4_TEXTURE_TYPE_ETC1 = 8, ++ VC4_TEXTURE_TYPE_S16F = 9, ++ VC4_TEXTURE_TYPE_S8 = 10, ++ VC4_TEXTURE_TYPE_S16 = 11, ++ VC4_TEXTURE_TYPE_BW1 = 12, ++ VC4_TEXTURE_TYPE_A4 = 13, ++ VC4_TEXTURE_TYPE_A1 = 14, ++ VC4_TEXTURE_TYPE_RGBA64 = 15, ++ VC4_TEXTURE_TYPE_RGBA32R = 16, ++ VC4_TEXTURE_TYPE_YUV422R = 17, + }; + + #define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) +diff --git a/drivers/gpu/drm/vc4/vc4_qpu_defines.h b/drivers/gpu/drm/vc4/vc4_qpu_defines.h +index e47c994..d5c2f3c 100644 +--- a/drivers/gpu/drm/vc4/vc4_qpu_defines.h ++++ b/drivers/gpu/drm/vc4/vc4_qpu_defines.h +@@ -25,194 +25,190 @@ + #define VC4_QPU_DEFINES_H + + enum qpu_op_add { +- QPU_A_NOP, +- QPU_A_FADD, +- QPU_A_FSUB, +- QPU_A_FMIN, +- QPU_A_FMAX, +- QPU_A_FMINABS, +- QPU_A_FMAXABS, +- QPU_A_FTOI, +- QPU_A_ITOF, +- QPU_A_ADD = 12, +- QPU_A_SUB, +- QPU_A_SHR, +- QPU_A_ASR, +- QPU_A_ROR, +- QPU_A_SHL, +- QPU_A_MIN, +- QPU_A_MAX, +- QPU_A_AND, +- QPU_A_OR, +- QPU_A_XOR, +- QPU_A_NOT, +- QPU_A_CLZ, +- QPU_A_V8ADDS = 30, +- QPU_A_V8SUBS = 31, ++ QPU_A_NOP, ++ QPU_A_FADD, ++ QPU_A_FSUB, ++ QPU_A_FMIN, ++ QPU_A_FMAX, ++ QPU_A_FMINABS, ++ QPU_A_FMAXABS, ++ QPU_A_FTOI, ++ QPU_A_ITOF, ++ QPU_A_ADD = 12, ++ QPU_A_SUB, ++ QPU_A_SHR, ++ QPU_A_ASR, ++ QPU_A_ROR, ++ QPU_A_SHL, ++ QPU_A_MIN, ++ QPU_A_MAX, ++ QPU_A_AND, ++ QPU_A_OR, ++ QPU_A_XOR, ++ QPU_A_NOT, ++ QPU_A_CLZ, ++ QPU_A_V8ADDS = 30, ++ QPU_A_V8SUBS = 31, + }; + + enum qpu_op_mul { +- QPU_M_NOP, +- QPU_M_FMUL, +- QPU_M_MUL24, +- QPU_M_V8MULD, +- QPU_M_V8MIN, +- QPU_M_V8MAX, +- QPU_M_V8ADDS, +- QPU_M_V8SUBS, ++ QPU_M_NOP, ++ QPU_M_FMUL, ++ QPU_M_MUL24, ++ QPU_M_V8MULD, ++ QPU_M_V8MIN, ++ QPU_M_V8MAX, ++ QPU_M_V8ADDS, ++ QPU_M_V8SUBS, + }; + + enum qpu_raddr { +- QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ +- /* 0-31 are the plain regfile a or b fields */ +- QPU_R_UNIF = 32, +- QPU_R_VARY = 35, +- QPU_R_ELEM_QPU = 38, +- QPU_R_NOP, +- QPU_R_XY_PIXEL_COORD = 41, +- QPU_R_MS_REV_FLAGS = 41, +- QPU_R_VPM = 48, +- QPU_R_VPM_LD_BUSY, +- QPU_R_VPM_LD_WAIT, +- QPU_R_MUTEX_ACQUIRE, ++ QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ ++ /* 0-31 are the plain regfile a or b fields */ ++ QPU_R_UNIF = 32, ++ QPU_R_VARY = 35, ++ QPU_R_ELEM_QPU = 38, ++ QPU_R_NOP, ++ QPU_R_XY_PIXEL_COORD = 41, ++ QPU_R_MS_REV_FLAGS = 41, ++ QPU_R_VPM = 48, ++ QPU_R_VPM_LD_BUSY, ++ QPU_R_VPM_LD_WAIT, ++ QPU_R_MUTEX_ACQUIRE, + }; + + enum qpu_waddr { +- /* 0-31 are the plain regfile a or b fields */ +- QPU_W_ACC0 = 32, /* aka r0 */ +- QPU_W_ACC1, +- QPU_W_ACC2, +- QPU_W_ACC3, +- QPU_W_TMU_NOSWAP, +- QPU_W_ACC5, +- QPU_W_HOST_INT, +- QPU_W_NOP, +- QPU_W_UNIFORMS_ADDRESS, +- QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ +- QPU_W_MS_FLAGS = 42, +- QPU_W_REV_FLAG = 42, +- QPU_W_TLB_STENCIL_SETUP = 43, +- QPU_W_TLB_Z, +- QPU_W_TLB_COLOR_MS, +- QPU_W_TLB_COLOR_ALL, +- QPU_W_TLB_ALPHA_MASK, +- QPU_W_VPM, +- QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ +- QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ +- QPU_W_MUTEX_RELEASE, +- QPU_W_SFU_RECIP, +- QPU_W_SFU_RECIPSQRT, +- QPU_W_SFU_EXP, +- QPU_W_SFU_LOG, +- QPU_W_TMU0_S, +- QPU_W_TMU0_T, +- QPU_W_TMU0_R, +- QPU_W_TMU0_B, +- QPU_W_TMU1_S, +- QPU_W_TMU1_T, +- QPU_W_TMU1_R, +- QPU_W_TMU1_B, ++ /* 0-31 are the plain regfile a or b fields */ ++ QPU_W_ACC0 = 32, /* aka r0 */ ++ QPU_W_ACC1, ++ QPU_W_ACC2, ++ QPU_W_ACC3, ++ QPU_W_TMU_NOSWAP, ++ QPU_W_ACC5, ++ QPU_W_HOST_INT, ++ QPU_W_NOP, ++ QPU_W_UNIFORMS_ADDRESS, ++ QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ ++ QPU_W_MS_FLAGS = 42, ++ QPU_W_REV_FLAG = 42, ++ QPU_W_TLB_STENCIL_SETUP = 43, ++ QPU_W_TLB_Z, ++ QPU_W_TLB_COLOR_MS, ++ QPU_W_TLB_COLOR_ALL, ++ QPU_W_TLB_ALPHA_MASK, ++ QPU_W_VPM, ++ QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ ++ QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ ++ QPU_W_MUTEX_RELEASE, ++ QPU_W_SFU_RECIP, ++ QPU_W_SFU_RECIPSQRT, ++ QPU_W_SFU_EXP, ++ QPU_W_SFU_LOG, ++ QPU_W_TMU0_S, ++ QPU_W_TMU0_T, ++ QPU_W_TMU0_R, ++ QPU_W_TMU0_B, ++ QPU_W_TMU1_S, ++ QPU_W_TMU1_T, ++ QPU_W_TMU1_R, ++ QPU_W_TMU1_B, + }; + + enum qpu_sig_bits { +- QPU_SIG_SW_BREAKPOINT, +- QPU_SIG_NONE, +- QPU_SIG_THREAD_SWITCH, +- QPU_SIG_PROG_END, +- QPU_SIG_WAIT_FOR_SCOREBOARD, +- QPU_SIG_SCOREBOARD_UNLOCK, +- QPU_SIG_LAST_THREAD_SWITCH, +- QPU_SIG_COVERAGE_LOAD, +- QPU_SIG_COLOR_LOAD, +- QPU_SIG_COLOR_LOAD_END, +- QPU_SIG_LOAD_TMU0, +- QPU_SIG_LOAD_TMU1, +- QPU_SIG_ALPHA_MASK_LOAD, +- QPU_SIG_SMALL_IMM, +- QPU_SIG_LOAD_IMM, +- QPU_SIG_BRANCH ++ QPU_SIG_SW_BREAKPOINT, ++ QPU_SIG_NONE, ++ QPU_SIG_THREAD_SWITCH, ++ QPU_SIG_PROG_END, ++ QPU_SIG_WAIT_FOR_SCOREBOARD, ++ QPU_SIG_SCOREBOARD_UNLOCK, ++ QPU_SIG_LAST_THREAD_SWITCH, ++ QPU_SIG_COVERAGE_LOAD, ++ QPU_SIG_COLOR_LOAD, ++ QPU_SIG_COLOR_LOAD_END, ++ QPU_SIG_LOAD_TMU0, ++ QPU_SIG_LOAD_TMU1, ++ QPU_SIG_ALPHA_MASK_LOAD, ++ QPU_SIG_SMALL_IMM, ++ QPU_SIG_LOAD_IMM, ++ QPU_SIG_BRANCH + }; + + enum qpu_mux { +- /* hardware mux values */ +- QPU_MUX_R0, +- QPU_MUX_R1, +- QPU_MUX_R2, +- QPU_MUX_R3, +- QPU_MUX_R4, +- QPU_MUX_R5, +- QPU_MUX_A, +- QPU_MUX_B, ++ /* hardware mux values */ ++ QPU_MUX_R0, ++ QPU_MUX_R1, ++ QPU_MUX_R2, ++ QPU_MUX_R3, ++ QPU_MUX_R4, ++ QPU_MUX_R5, ++ QPU_MUX_A, ++ QPU_MUX_B, + +- /* non-hardware mux values */ +- QPU_MUX_IMM, ++ /* non-hardware mux values */ ++ QPU_MUX_IMM, + }; + + enum qpu_cond { +- QPU_COND_NEVER, +- QPU_COND_ALWAYS, +- QPU_COND_ZS, +- QPU_COND_ZC, +- QPU_COND_NS, +- QPU_COND_NC, +- QPU_COND_CS, +- QPU_COND_CC, ++ QPU_COND_NEVER, ++ QPU_COND_ALWAYS, ++ QPU_COND_ZS, ++ QPU_COND_ZC, ++ QPU_COND_NS, ++ QPU_COND_NC, ++ QPU_COND_CS, ++ QPU_COND_CC, + }; + + enum qpu_pack_mul { +- QPU_PACK_MUL_NOP, +- QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */ +- QPU_PACK_MUL_8A, +- QPU_PACK_MUL_8B, +- QPU_PACK_MUL_8C, +- QPU_PACK_MUL_8D, ++ QPU_PACK_MUL_NOP, ++ /* replicated to each 8 bits of the 32-bit dst. */ ++ QPU_PACK_MUL_8888 = 3, ++ QPU_PACK_MUL_8A, ++ QPU_PACK_MUL_8B, ++ QPU_PACK_MUL_8C, ++ QPU_PACK_MUL_8D, + }; + + enum qpu_pack_a { +- QPU_PACK_A_NOP, +- /* convert to 16 bit float if float input, or to int16. */ +- QPU_PACK_A_16A, +- QPU_PACK_A_16B, +- /* replicated to each 8 bits of the 32-bit dst. */ +- QPU_PACK_A_8888, +- /* Convert to 8-bit unsigned int. */ +- QPU_PACK_A_8A, +- QPU_PACK_A_8B, +- QPU_PACK_A_8C, +- QPU_PACK_A_8D, ++ QPU_PACK_A_NOP, ++ /* convert to 16 bit float if float input, or to int16. */ ++ QPU_PACK_A_16A, ++ QPU_PACK_A_16B, ++ /* replicated to each 8 bits of the 32-bit dst. */ ++ QPU_PACK_A_8888, ++ /* Convert to 8-bit unsigned int. */ ++ QPU_PACK_A_8A, ++ QPU_PACK_A_8B, ++ QPU_PACK_A_8C, ++ QPU_PACK_A_8D, + +- /* Saturating variants of the previous instructions. */ +- QPU_PACK_A_32_SAT, /* int-only */ +- QPU_PACK_A_16A_SAT, /* int or float */ +- QPU_PACK_A_16B_SAT, +- QPU_PACK_A_8888_SAT, +- QPU_PACK_A_8A_SAT, +- QPU_PACK_A_8B_SAT, +- QPU_PACK_A_8C_SAT, +- QPU_PACK_A_8D_SAT, ++ /* Saturating variants of the previous instructions. */ ++ QPU_PACK_A_32_SAT, /* int-only */ ++ QPU_PACK_A_16A_SAT, /* int or float */ ++ QPU_PACK_A_16B_SAT, ++ QPU_PACK_A_8888_SAT, ++ QPU_PACK_A_8A_SAT, ++ QPU_PACK_A_8B_SAT, ++ QPU_PACK_A_8C_SAT, ++ QPU_PACK_A_8D_SAT, + }; + + enum qpu_unpack_r4 { +- QPU_UNPACK_R4_NOP, +- QPU_UNPACK_R4_F16A_TO_F32, +- QPU_UNPACK_R4_F16B_TO_F32, +- QPU_UNPACK_R4_8D_REP, +- QPU_UNPACK_R4_8A, +- QPU_UNPACK_R4_8B, +- QPU_UNPACK_R4_8C, +- QPU_UNPACK_R4_8D, ++ QPU_UNPACK_R4_NOP, ++ QPU_UNPACK_R4_F16A_TO_F32, ++ QPU_UNPACK_R4_F16B_TO_F32, ++ QPU_UNPACK_R4_8D_REP, ++ QPU_UNPACK_R4_8A, ++ QPU_UNPACK_R4_8B, ++ QPU_UNPACK_R4_8C, ++ QPU_UNPACK_R4_8D, + }; + +-#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) +-/* Using the GNU statement expression extension */ +-#define QPU_SET_FIELD(value, field) \ +- ({ \ +- uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ +- assert((fieldval & ~ field ## _MASK) == 0); \ +- fieldval & field ## _MASK; \ +- }) ++#define QPU_MASK(high, low) \ ++ ((((uint64_t)1 << ((high) - (low) + 1)) - 1) << (low)) + +-#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) ++#define QPU_GET_FIELD(word, field) \ ++ ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) + + #define QPU_SIG_SHIFT 60 + #define QPU_SIG_MASK QPU_MASK(63, 60) +diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c +index 0ffac8d..3516354 100644 +--- a/drivers/gpu/drm/vc4/vc4_render_cl.c ++++ b/drivers/gpu/drm/vc4/vc4_render_cl.c +@@ -63,7 +63,6 @@ static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val) + setup->next_offset += 4; + } + +- + /* + * Emits a no-op STORE_TILE_BUFFER_GENERAL. + * +@@ -217,7 +216,7 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + } + size += xtiles * ytiles * loop_body_size; + +- setup->rcl = &vc4_bo_create(dev, size)->base; ++ setup->rcl = &vc4_bo_create(dev, size, true)->base; + if (!setup->rcl) + return -ENOMEM; + list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head, +@@ -256,6 +255,7 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + for (x = min_x_tile; x <= max_x_tile; x++) { + bool first = (x == min_x_tile && y == min_y_tile); + bool last = (x == max_x_tile && y == max_y_tile); ++ + emit_tile(exec, setup, x, y, first, last); + } + } +diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c +index cf35f58..29a222f 100644 +--- a/drivers/gpu/drm/vc4/vc4_v3d.c ++++ b/drivers/gpu/drm/vc4/vc4_v3d.c +@@ -125,7 +125,7 @@ int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused) + + int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) + { +- struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + uint32_t ident1 = V3D_READ(V3D_IDENT1); +@@ -133,11 +133,13 @@ int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) + uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); + uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); + +- seq_printf(m, "Revision: %d\n", VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); ++ seq_printf(m, "Revision: %d\n", ++ VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); + seq_printf(m, "Slices: %d\n", nslc); + seq_printf(m, "TMUs: %d\n", nslc * tups); + seq_printf(m, "QPUs: %d\n", nslc * qups); +- seq_printf(m, "Semaphores: %d\n", VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); ++ seq_printf(m, "Semaphores: %d\n", ++ VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); + + return 0; + } +@@ -218,7 +220,7 @@ static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) + } + + static void vc4_v3d_unbind(struct device *dev, struct device *master, +- void *data) ++ void *data) + { + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = to_vc4_dev(drm); +diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c +index ff3b62f..e44e355 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate.c ++++ b/drivers/gpu/drm/vc4/vc4_validate.c +@@ -48,7 +48,6 @@ + void *validated, \ + void *untrusted + +- + /** Return the width in pixels of a 64-byte microtile. */ + static uint32_t + utile_width(int cpp) +@@ -192,7 +191,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, + + if (size + offset < size || + size + offset > fbo->base.size) { +- DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %d)\n", ++ DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n", + width, height, + aligned_width, aligned_height, + size, offset, fbo->base.size); +@@ -278,7 +277,7 @@ validate_indexed_prim_list(VALIDATE_ARGS) + + if (offset > ib->base.size || + (ib->base.size - offset) / index_size < length) { +- DRM_ERROR("IB access overflow (%d + %d*%d > %d)\n", ++ DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n", + offset, length, index_size, ib->base.size); + return -EINVAL; + } +@@ -377,6 +376,7 @@ static int + validate_tile_binning_config(VALIDATE_ARGS) + { + struct drm_device *dev = exec->exec_bo->base.dev; ++ struct vc4_bo *tile_bo; + uint8_t flags; + uint32_t tile_state_size, tile_alloc_size; + uint32_t tile_count; +@@ -438,12 +438,12 @@ validate_tile_binning_config(VALIDATE_ARGS) + */ + tile_alloc_size += 1024 * 1024; + +- exec->tile_bo = &vc4_bo_create(dev, exec->tile_alloc_offset + +- tile_alloc_size)->base; ++ tile_bo = vc4_bo_create(dev, exec->tile_alloc_offset + tile_alloc_size, ++ true); ++ exec->tile_bo = &tile_bo->base; + if (!exec->tile_bo) + return -ENOMEM; +- list_add_tail(&to_vc4_bo(&exec->tile_bo->base)->unref_head, +- &exec->unref_list); ++ list_add_tail(&tile_bo->unref_head, &exec->unref_list); + + /* tile alloc address. */ + *(uint32_t *)(validated + 0) = (exec->tile_bo->paddr + +@@ -463,8 +463,8 @@ validate_gem_handles(VALIDATE_ARGS) + return 0; + } + +-#define VC4_DEFINE_PACKET(packet, name, func) \ +- [packet] = { packet ## _SIZE, name, func } ++#define VC4_DEFINE_PACKET(packet, func) \ ++ [packet] = { packet ## _SIZE, #packet, func } + + static const struct cmd_info { + uint16_t len; +@@ -472,42 +472,43 @@ static const struct cmd_info { + int (*func)(struct vc4_exec_info *exec, void *validated, + void *untrusted); + } cmd_info[] = { +- VC4_DEFINE_PACKET(VC4_PACKET_HALT, "halt", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_NOP, "nop", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, "flush", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, "flush all state", validate_flush_all), +- VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, "start tile binning", validate_start_tile_binning), +- VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, "increment semaphore", validate_increment_semaphore), +- +- VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE, "Indexed Primitive List", validate_indexed_prim_list), +- +- VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE, "Vertex Array Primitives", validate_gl_array_primitive), +- +- /* This is only used by clipped primitives (packets 48 and 49), which +- * we don't support parsing yet. +- */ +- VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, "primitive list format", NULL), +- +- VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, "GL Shader State", validate_gl_shader_state), +- VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, "NV Shader State", validate_nv_shader_state), +- +- VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, "configuration bits", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, "flat shade flags", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE, "point size", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH, "line width", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY, "RHT X boundary", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET, "Depth Offset", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW, "Clip Window", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET, "Viewport Offset", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING, "Clipper XY Scaling", NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_HALT, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_NOP, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, validate_flush_all), ++ VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, ++ validate_start_tile_binning), ++ VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, ++ validate_increment_semaphore), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE, ++ validate_indexed_prim_list), ++ VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE, ++ validate_gl_array_primitive), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, NULL), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, validate_gl_shader_state), ++ VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, validate_nv_shader_state), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING, NULL), + /* Note: The docs say this was also 105, but it was 106 in the + * initial userland code drop. + */ +- VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING, "Clipper Z Scale and Offset", NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING, NULL), + +- VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG, "tile binning configuration", validate_tile_binning_config), ++ VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG, ++ validate_tile_binning_config), + +- VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES, "GEM handles", validate_gem_handles), ++ VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES, validate_gem_handles), + }; + + int +@@ -526,7 +527,7 @@ vc4_validate_bin_cl(struct drm_device *dev, + u8 cmd = *(uint8_t *)src_pkt; + const struct cmd_info *info; + +- if (cmd > ARRAY_SIZE(cmd_info)) { ++ if (cmd >= ARRAY_SIZE(cmd_info)) { + DRM_ERROR("0x%08x: packet %d out of bounds\n", + src_offset, cmd); + return -EINVAL; +@@ -539,11 +540,6 @@ vc4_validate_bin_cl(struct drm_device *dev, + return -EINVAL; + } + +-#if 0 +- DRM_INFO("0x%08x: packet %d (%s) size %d processing...\n", +- src_offset, cmd, info->name, info->len); +-#endif +- + if (src_offset + info->len > len) { + DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x " + "exceeds bounds (0x%08x)\n", +@@ -558,8 +554,7 @@ vc4_validate_bin_cl(struct drm_device *dev, + if (info->func && info->func(exec, + dst_pkt + 1, + src_pkt + 1)) { +- DRM_ERROR("0x%08x: packet %d (%s) failed to " +- "validate\n", ++ DRM_ERROR("0x%08x: packet %d (%s) failed to validate\n", + src_offset, cmd, info->name); + return -EINVAL; + } +@@ -618,12 +613,14 @@ reloc_tex(struct vc4_exec_info *exec, + + if (sample->is_direct) { + uint32_t remaining_size = tex->base.size - p0; ++ + if (p0 > tex->base.size - 4) { + DRM_ERROR("UBO offset greater than UBO size\n"); + goto fail; + } + if (p1 > remaining_size - 4) { +- DRM_ERROR("UBO clamp would allow reads outside of UBO\n"); ++ DRM_ERROR("UBO clamp would allow reads " ++ "outside of UBO\n"); + goto fail; + } + *validated_p0 = tex->paddr + p0; +@@ -786,7 +783,7 @@ validate_shader_rec(struct drm_device *dev, + struct drm_gem_cma_object *bo[ARRAY_SIZE(gl_relocs) + 8]; + uint32_t nr_attributes = 0, nr_fixed_relocs, nr_relocs, packet_size; + int i; +- struct vc4_validated_shader_info *validated_shader; ++ struct vc4_validated_shader_info *shader; + + if (state->packet == VC4_PACKET_NV_SHADER_STATE) { + relocs = nv_relocs; +@@ -841,12 +838,12 @@ validate_shader_rec(struct drm_device *dev, + else + mode = VC4_MODE_RENDER; + +- if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) { ++ if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) + return false; +- } + } + + for (i = 0; i < nr_fixed_relocs; i++) { ++ struct vc4_bo *vc4_bo; + uint32_t o = relocs[i].offset; + uint32_t src_offset = *(uint32_t *)(pkt_u + o); + uint32_t *texture_handles_u; +@@ -858,34 +855,34 @@ validate_shader_rec(struct drm_device *dev, + switch (relocs[i].type) { + case RELOC_CODE: + if (src_offset != 0) { +- DRM_ERROR("Shaders must be at offset 0 of " +- "the BO.\n"); ++ DRM_ERROR("Shaders must be at offset 0 " ++ "of the BO.\n"); + goto fail; } + +- validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader; +- if (!validated_shader) ++ vc4_bo = to_vc4_bo(&bo[i]->base); ++ shader = vc4_bo->validated_shader; ++ if (!shader) + goto fail; + +- if (validated_shader->uniforms_src_size > +- exec->uniforms_size) { ++ if (shader->uniforms_src_size > exec->uniforms_size) { + DRM_ERROR("Uniforms src buffer overflow\n"); + goto fail; + } + + texture_handles_u = exec->uniforms_u; + uniform_data_u = (texture_handles_u + +- validated_shader->num_texture_samples); ++ shader->num_texture_samples); + + memcpy(exec->uniforms_v, uniform_data_u, +- validated_shader->uniforms_size); ++ shader->uniforms_size); + + for (tex = 0; +- tex < validated_shader->num_texture_samples; ++ tex < shader->num_texture_samples; + tex++) { + if (!reloc_tex(exec, + uniform_data_u, +- &validated_shader->texture_samples[tex], ++ &shader->texture_samples[tex], + texture_handles_u[tex])) { + goto fail; + } +@@ -893,9 +890,9 @@ validate_shader_rec(struct drm_device *dev, + + *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; + +- exec->uniforms_u += validated_shader->uniforms_src_size; +- exec->uniforms_v += validated_shader->uniforms_size; +- exec->uniforms_p += validated_shader->uniforms_size; ++ exec->uniforms_u += shader->uniforms_src_size; ++ exec->uniforms_v += shader->uniforms_size; ++ exec->uniforms_p += shader->uniforms_size; + + break; + +@@ -926,7 +923,8 @@ validate_shader_rec(struct drm_device *dev, + max_index = ((vbo->base.size - offset - attr_size) / + stride); + if (state->max_index > max_index) { +- DRM_ERROR("primitives use index %d out of supplied %d\n", ++ DRM_ERROR("primitives use index %d out of " ++ "supplied %d\n", + state->max_index, max_index); + return -EINVAL; + } +diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c +index 0aab9d7..f67124b 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c ++++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c +@@ -24,24 +24,16 @@ + /** + * DOC: Shader validator for VC4. + * +- * The VC4 has no IOMMU between it and system memory. So, a user with access +- * to execute shaders could escalate privilege by overwriting system memory +- * (using the VPM write address register in the general-purpose DMA mode) or +- * reading system memory it shouldn't (reading it as a texture, or uniform +- * data, or vertex data). ++ * The VC4 has no IOMMU between it and system memory, so a user with ++ * access to execute shaders could escalate privilege by overwriting ++ * system memory (using the VPM write address register in the ++ * general-purpose DMA mode) or reading system memory it shouldn't ++ * (reading it as a texture, or uniform data, or vertex data). + * +- * This walks over a shader starting from some offset within a BO, ensuring +- * that its accesses are appropriately bounded, and recording how many texture +- * accesses are made and where so that we can do relocations for them in the ++ * This walks over a shader BO, ensuring that its accesses are ++ * appropriately bounded, and recording how many texture accesses are ++ * made and where so that we can do relocations for them in the + * uniform stream. +- * +- * The kernel API has shaders stored in user-mapped BOs. The BOs will be +- * forcibly unmapped from the process before validation, and any cache of +- * validated state will be flushed if the mapping is faulted back in. +- * +- * Storing the shaders in BOs means that the validation process will be slow +- * due to uncached reads, but since shaders are long-lived and shader BOs are +- * never actually modified, this shouldn't be a problem. + */ + + #include "vc4_drv.h" +@@ -70,7 +62,6 @@ waddr_to_live_reg_index(uint32_t waddr, bool is_b) + else + return waddr; + } else if (waddr <= QPU_W_ACC3) { +- + return 64 + waddr - QPU_W_ACC0; + } else { + return ~0; +@@ -85,15 +76,14 @@ raddr_add_a_to_live_reg_index(uint64_t inst) + uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); + uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); + +- if (add_a == QPU_MUX_A) { ++ if (add_a == QPU_MUX_A) + return raddr_a; +- } else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) { ++ else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) + return 32 + raddr_b; +- } else if (add_a <= QPU_MUX_R3) { ++ else if (add_a <= QPU_MUX_R3) + return 64 + add_a; +- } else { ++ else + return ~0; +- } + } + + static bool +@@ -111,9 +101,9 @@ is_tmu_write(uint32_t waddr) + } + + static bool +-record_validated_texture_sample(struct vc4_validated_shader_info *validated_shader, +- struct vc4_shader_validation_state *validation_state, +- int tmu) ++record_texture_sample(struct vc4_validated_shader_info *validated_shader, ++ struct vc4_shader_validation_state *validation_state, ++ int tmu) + { + uint32_t s = validated_shader->num_texture_samples; + int i; +@@ -226,8 +216,8 @@ check_tmu_write(uint64_t inst, + validated_shader->uniforms_size += 4; + + if (submit) { +- if (!record_validated_texture_sample(validated_shader, +- validation_state, tmu)) { ++ if (!record_texture_sample(validated_shader, ++ validation_state, tmu)) { + return false; + } + +@@ -238,10 +228,10 @@ check_tmu_write(uint64_t inst, + } + + static bool +-check_register_write(uint64_t inst, +- struct vc4_validated_shader_info *validated_shader, +- struct vc4_shader_validation_state *validation_state, +- bool is_mul) ++check_reg_write(uint64_t inst, ++ struct vc4_validated_shader_info *validated_shader, ++ struct vc4_shader_validation_state *validation_state, ++ bool is_mul) + { + uint32_t waddr = (is_mul ? + QPU_GET_FIELD(inst, QPU_WADDR_MUL) : +@@ -297,7 +287,7 @@ check_register_write(uint64_t inst, + return true; + + case QPU_W_TLB_STENCIL_SETUP: +- return true; ++ return true; + } + + return true; +@@ -360,7 +350,7 @@ track_live_clamps(uint64_t inst, + } + + validation_state->live_max_clamp_regs[lri_add] = true; +- } if (op_add == QPU_A_MIN) { ++ } else if (op_add == QPU_A_MIN) { + /* Track live clamps of a value clamped to a minimum of 0 and + * a maximum of some uniform's offset. + */ +@@ -392,8 +382,10 @@ check_instruction_writes(uint64_t inst, + return false; + } + +- ok = (check_register_write(inst, validated_shader, validation_state, false) && +- check_register_write(inst, validated_shader, validation_state, true)); ++ ok = (check_reg_write(inst, validated_shader, validation_state, ++ false) && ++ check_reg_write(inst, validated_shader, validation_state, ++ true)); + + track_live_clamps(inst, validated_shader, validation_state); + +@@ -441,7 +433,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) + shader = shader_obj->vaddr; + max_ip = shader_obj->base.size / sizeof(uint64_t); + +- validated_shader = kcalloc(sizeof(*validated_shader), 1, GFP_KERNEL); ++ validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL); + if (!validated_shader) + return NULL; + +@@ -497,7 +489,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) + + if (ip == max_ip) { + DRM_ERROR("shader failed to terminate before " +- "shader BO end at %d\n", ++ "shader BO end at %zd\n", + shader_obj->base.size); + goto fail; + } +diff --git a/include/drm/drmP.h b/include/drm/drmP.h +index 54f5469..987c25a 100644 +--- a/include/drm/drmP.h ++++ b/include/drm/drmP.h +@@ -585,6 +585,13 @@ struct drm_driver { + int (*gem_open_object) (struct drm_gem_object *, struct drm_file *); + void (*gem_close_object) (struct drm_gem_object *, struct drm_file *); + ++ /** ++ * Hook for allocating the GEM object struct, for use by core ++ * helpers. ++ */ ++ struct drm_gem_object *(*gem_create_object)(struct drm_device *dev, ++ size_t size); ++ + /* prime: */ + /* export handle -> fd (see drm_gem_prime_handle_to_fd() helper) */ + int (*prime_handle_to_fd)(struct drm_device *dev, struct drm_file *file_priv, +@@ -639,7 +646,6 @@ struct drm_driver { + + u32 driver_features; + int dev_priv_size; +- size_t gem_obj_size; + const struct drm_ioctl_desc *ioctls; + int num_ioctls; + const struct file_operations *fops; -- 2.5.0 -From b669684c3d592e9e4455cccfeaf987dff0338f12 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Sun, 13 Dec 2015 14:00:16 +0000 -Subject: [PATCH 78/78] bcm270x: Enable bcm2835-rng for all RPi models +From a8812101ce0faa865c1b75e461d5f05d8a43b9e3 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 11 Dec 2015 19:45:03 -0800 +Subject: [PATCH 55/59] drm: Use the driver's gem_object_free function from CMA + helpers. -Include the bcm2835-rng driver in the kernel and enable in DT. +VC4 wraps the CMA objects in its own structures, so it needs to do its +own teardown (waiting for GPU to finish, updating bo_stats tracking). +The other CMA drivers are using drm_gem_cma_free_object as their +gem_free_object, so this should be a no-op for them. + +Signed-off-by: Eric Anholt --- - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 4 ++++ - arch/arm/boot/dts/bcm2708-rpi-b.dts | 4 ++++ - arch/arm/boot/dts/bcm2708-rpi-cm.dts | 4 ++++ - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 4 ++++ - arch/arm/configs/bcm2709_defconfig | 2 +- - arch/arm/configs/bcmrpi_defconfig | 2 +- - 6 files changed, 18 insertions(+), 2 deletions(-) + drivers/gpu/drm/drm_fb_cma_helper.c | 6 +++--- + drivers/gpu/drm/drm_gem_cma_helper.c | 4 ++-- + 2 files changed, 5 insertions(+), 5 deletions(-) -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -index 4deb968..2e4df17 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -98,6 +98,10 @@ - pinctrl-0 = <&i2s_pins>; - }; +diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c +index c19a625..c1a37d3 100644 +--- a/drivers/gpu/drm/drm_fb_cma_helper.c ++++ b/drivers/gpu/drm/drm_fb_cma_helper.c +@@ -266,7 +266,7 @@ static int drm_fbdev_cma_create(struct drm_fb_helper *helper, + fbi = drm_fb_helper_alloc_fbi(helper); + if (IS_ERR(fbi)) { + ret = PTR_ERR(fbi); +- goto err_drm_gem_cma_free_object; ++ goto err_gem_free_object; + } -+&random { -+ status = "okay"; -+}; -+ - &leds { - act_led: act { - label = "led0"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts -index 1e77926..0445b46 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -98,6 +98,10 @@ - pinctrl-0 = <&i2s_pins>; - }; + fbdev_cma->fb = drm_fb_cma_alloc(dev, &mode_cmd, &obj, 1); +@@ -299,8 +299,8 @@ static int drm_fbdev_cma_create(struct drm_fb_helper *helper, -+&random { -+ status = "okay"; -+}; -+ - &leds { - act_led: act { - label = "led0"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -index 587f1e4..87c1a54 100755 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -@@ -81,6 +81,10 @@ - pinctrl-0 = <&i2s_pins>; - }; + err_fb_info_destroy: + drm_fb_helper_release_fbi(helper); +-err_drm_gem_cma_free_object: +- drm_gem_cma_free_object(&obj->base); ++err_gem_free_object: ++ dev->driver->gem_free_object(&obj->base); + return ret; + } -+&random { -+ status = "okay"; -+}; -+ - / { - __overrides__ { - uart0 = <&uart0>,"status"; -diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -index 4e6c64e..5206ba2 100644 ---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -98,6 +98,10 @@ - pinctrl-0 = <&i2s_pins>; - }; +diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c +index 0f7b00b..e5df53b 100644 +--- a/drivers/gpu/drm/drm_gem_cma_helper.c ++++ b/drivers/gpu/drm/drm_gem_cma_helper.c +@@ -121,7 +121,7 @@ struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm, + return cma_obj; -+&random { -+ status = "okay"; -+}; -+ - &leds { - act_led: act { - label = "led0"; -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index be6cda9..1f47fb7 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -590,7 +590,7 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y - CONFIG_SERIAL_OF_PLATFORM=y - CONFIG_TTY_PRINTK=y - CONFIG_HW_RANDOM=y --CONFIG_HW_RANDOM_BCM2835=m -+CONFIG_HW_RANDOM_BCM2835=y - CONFIG_RAW_DRIVER=y - CONFIG_I2C=y - CONFIG_I2C_CHARDEV=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 9e5cd8b..015a2b3 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -583,7 +583,7 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y - CONFIG_SERIAL_OF_PLATFORM=y - CONFIG_TTY_PRINTK=y - CONFIG_HW_RANDOM=y --CONFIG_HW_RANDOM_BCM2835=m -+CONFIG_HW_RANDOM_BCM2835=y - CONFIG_RAW_DRIVER=y - CONFIG_I2C=y - CONFIG_I2C_CHARDEV=m + error: +- drm_gem_cma_free_object(&cma_obj->base); ++ drm->driver->gem_free_object(&cma_obj->base); + return ERR_PTR(ret); + } + EXPORT_SYMBOL_GPL(drm_gem_cma_create); +@@ -171,7 +171,7 @@ drm_gem_cma_create_with_handle(struct drm_file *file_priv, + return cma_obj; + + err_handle_create: +- drm_gem_cma_free_object(gem_obj); ++ drm->driver->gem_free_object(gem_obj); + + return ERR_PTR(ret); + } +-- +2.5.0 + + +From 7c236c874ffa28be6d8b1b07366bc7821a844db0 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 17 Jul 2015 13:15:50 -0700 +Subject: [PATCH 56/59] drm/vc4: Add support for MSAA rendering. + +For MSAA, you set a bit in the binner that halves the size of tiles in +each direction, so you can pack 4 samples per pixel in the tile +buffer. During rendering, you can load and store raw tile buffer +contents (to save the per-sample MSAA contents), or you can load/store +resolved tile buffer contents (loads spam the pixel value to all 4 +samples, and stores either average the 4 color samples, or store the +first sample for Z/S). + +Signed-off-by: Eric Anholt +--- + drivers/gpu/drm/vc4/vc4_packet.h | 23 ++- + drivers/gpu/drm/vc4/vc4_render_cl.c | 274 ++++++++++++++++++++++++++++++------ + drivers/gpu/drm/vc4/vc4_validate.c | 5 +- + include/uapi/drm/vc4_drm.h | 11 +- + 4 files changed, 258 insertions(+), 55 deletions(-) + +diff --git a/drivers/gpu/drm/vc4/vc4_packet.h b/drivers/gpu/drm/vc4/vc4_packet.h +index cee38aa..0f31cc0 100644 +--- a/drivers/gpu/drm/vc4/vc4_packet.h ++++ b/drivers/gpu/drm/vc4/vc4_packet.h +@@ -123,6 +123,11 @@ enum vc4_packet { + #define VC4_PACKET_TILE_COORDINATES_SIZE 3 + #define VC4_PACKET_GEM_HANDLES_SIZE 9 + ++/* Number of multisamples supported. */ ++#define VC4_MAX_SAMPLES 4 ++/* Size of a full resolution color or Z tile buffer load/store. */ ++#define VC4_TILE_BUFFER_SIZE (64 * 64 * 4) ++ + /** @{ + * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. +@@ -137,10 +142,20 @@ enum vc4_packet { + * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and + * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. + */ +-#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3) +-#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2) +-#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1) +-#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0) ++#define VC4_LOADSTORE_FULL_RES_EOF BIT(3) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) ++ ++/** @{ ++ * ++ * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and ++ * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. ++ */ ++#define VC4_LOADSTORE_FULL_RES_EOF BIT(3) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) + + /** @{ + * +diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c +index 3516354..8f2ec57 100644 +--- a/drivers/gpu/drm/vc4/vc4_render_cl.c ++++ b/drivers/gpu/drm/vc4/vc4_render_cl.c +@@ -37,9 +37,11 @@ + + struct vc4_rcl_setup { + struct drm_gem_cma_object *color_read; +- struct drm_gem_cma_object *color_ms_write; ++ struct drm_gem_cma_object *color_write; + struct drm_gem_cma_object *zs_read; + struct drm_gem_cma_object *zs_write; ++ struct drm_gem_cma_object *msaa_color_write; ++ struct drm_gem_cma_object *msaa_zs_write; + + struct drm_gem_cma_object *rcl; + u32 next_offset; +@@ -82,6 +84,22 @@ static void vc4_store_before_load(struct vc4_rcl_setup *setup) + } + + /* ++ * Calculates the physical address of the start of a tile in a RCL surface. ++ * ++ * Unlike the other load/store packets, ++ * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile ++ * coordinates packet, and instead just store to the address given. ++ */ ++static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec, ++ struct drm_gem_cma_object *bo, ++ struct drm_vc4_submit_rcl_surface *surf, ++ uint8_t x, uint8_t y) ++{ ++ return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE * ++ (DIV_ROUND_UP(exec->args->width, 32) * y + x); ++} ++ ++/* + * Emits a PACKET_TILE_COORDINATES if one isn't already pending. + * + * The tile coordinates packet triggers a pending load if there is one, are +@@ -108,22 +126,41 @@ static void emit_tile(struct vc4_exec_info *exec, + * may be outstanding at a time. + */ + if (setup->color_read) { +- rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); +- rcl_u16(setup, args->color_read.bits); +- rcl_u32(setup, +- setup->color_read->paddr + args->color_read.offset); ++ if (args->color_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->color_read, ++ &args->color_read, x, y) | ++ VC4_LOADSTORE_FULL_RES_DISABLE_ZS); ++ } else { ++ rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); ++ rcl_u16(setup, args->color_read.bits); ++ rcl_u32(setup, setup->color_read->paddr + ++ args->color_read.offset); ++ } + } + + if (setup->zs_read) { +- if (setup->color_read) { +- /* Exec previous load. */ +- vc4_tile_coordinates(setup, x, y); +- vc4_store_before_load(setup); ++ if (args->zs_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->zs_read, ++ &args->zs_read, x, y) | ++ VC4_LOADSTORE_FULL_RES_DISABLE_COLOR); ++ } else { ++ if (setup->color_read) { ++ /* Exec previous load. */ ++ vc4_tile_coordinates(setup, x, y); ++ vc4_store_before_load(setup); ++ } ++ ++ rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); ++ rcl_u16(setup, args->zs_read.bits); ++ rcl_u32(setup, setup->zs_read->paddr + ++ args->zs_read.offset); + } +- +- rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); +- rcl_u16(setup, args->zs_read.bits); +- rcl_u32(setup, setup->zs_read->paddr + args->zs_read.offset); + } + + /* Clipping depends on tile coordinates having been +@@ -144,20 +181,60 @@ static void emit_tile(struct vc4_exec_info *exec, + (y * exec->bin_tiles_x + x) * 32)); + } + ++ if (setup->msaa_color_write) { ++ bool last_tile_write = (!setup->msaa_zs_write && ++ !setup->zs_write && ++ !setup->color_write); ++ uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS; ++ ++ if (!last_tile_write) ++ bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; ++ else if (last) ++ bits |= VC4_LOADSTORE_FULL_RES_EOF; ++ rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->msaa_color_write, ++ &args->msaa_color_write, x, y) | ++ bits); ++ } ++ ++ if (setup->msaa_zs_write) { ++ bool last_tile_write = (!setup->zs_write && ++ !setup->color_write); ++ uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR; ++ ++ if (setup->msaa_color_write) ++ vc4_tile_coordinates(setup, x, y); ++ if (!last_tile_write) ++ bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; ++ else if (last) ++ bits |= VC4_LOADSTORE_FULL_RES_EOF; ++ rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->msaa_zs_write, ++ &args->msaa_zs_write, x, y) | ++ bits); ++ } ++ + if (setup->zs_write) { ++ bool last_tile_write = !setup->color_write; ++ ++ if (setup->msaa_color_write || setup->msaa_zs_write) ++ vc4_tile_coordinates(setup, x, y); ++ + rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); + rcl_u16(setup, args->zs_write.bits | +- (setup->color_ms_write ? +- VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR : 0)); ++ (last_tile_write ? ++ 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR)); + rcl_u32(setup, + (setup->zs_write->paddr + args->zs_write.offset) | +- ((last && !setup->color_ms_write) ? ++ ((last && last_tile_write) ? + VC4_LOADSTORE_TILE_BUFFER_EOF : 0)); + } + +- if (setup->color_ms_write) { +- if (setup->zs_write) { +- /* Reset after previous store */ ++ if (setup->color_write) { ++ if (setup->msaa_color_write || setup->msaa_zs_write || ++ setup->zs_write) { + vc4_tile_coordinates(setup, x, y); + } + +@@ -192,14 +269,26 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + } + + if (setup->color_read) { +- loop_body_size += (VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE); ++ if (args->color_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; ++ } else { ++ loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; ++ } + } + if (setup->zs_read) { +- if (setup->color_read) { +- loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; +- loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; ++ if (args->zs_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; ++ } else { ++ if (setup->color_read && ++ !(args->color_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) { ++ loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; ++ loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; ++ } ++ loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; + } +- loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; + } + + if (has_bin) { +@@ -207,13 +296,23 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE; + } + ++ if (setup->msaa_color_write) ++ loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; ++ if (setup->msaa_zs_write) ++ loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; ++ + if (setup->zs_write) + loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; +- if (setup->color_ms_write) { +- if (setup->zs_write) +- loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; ++ if (setup->color_write) + loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE; +- } ++ ++ /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */ ++ loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE * ++ ((setup->msaa_color_write != NULL) + ++ (setup->msaa_zs_write != NULL) + ++ (setup->color_write != NULL) + ++ (setup->zs_write != NULL) - 1); ++ + size += xtiles * ytiles * loop_body_size; + + setup->rcl = &vc4_bo_create(dev, size, true)->base; +@@ -224,13 +323,12 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + + rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG); + rcl_u32(setup, +- (setup->color_ms_write ? +- (setup->color_ms_write->paddr + +- args->color_ms_write.offset) : ++ (setup->color_write ? (setup->color_write->paddr + ++ args->color_write.offset) : + 0)); + rcl_u16(setup, args->width); + rcl_u16(setup, args->height); +- rcl_u16(setup, args->color_ms_write.bits); ++ rcl_u16(setup, args->color_write.bits); + + /* The tile buffer gets cleared when the previous tile is stored. If + * the clear values changed between frames, then the tile buffer has +@@ -267,6 +365,56 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + return 0; + } + ++static int vc4_full_res_bounds_check(struct vc4_exec_info *exec, ++ struct drm_gem_cma_object *obj, ++ struct drm_vc4_submit_rcl_surface *surf) ++{ ++ struct drm_vc4_submit_cl *args = exec->args; ++ u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32); ++ ++ if (surf->offset > obj->base.size) { ++ DRM_ERROR("surface offset %d > BO size %zd\n", ++ surf->offset, obj->base.size); ++ return -EINVAL; ++ } ++ ++ if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < ++ render_tiles_stride * args->max_y_tile + args->max_x_tile) { ++ DRM_ERROR("MSAA tile %d, %d out of bounds " ++ "(bo size %zd, offset %d).\n", ++ args->max_x_tile, args->max_y_tile, ++ obj->base.size, ++ surf->offset); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec, ++ struct drm_gem_cma_object **obj, ++ struct drm_vc4_submit_rcl_surface *surf) ++{ ++ if (surf->flags != 0 || surf->bits != 0) { ++ DRM_ERROR("MSAA surface had nonzero flags/bits\n"); ++ return -EINVAL; ++ } ++ ++ if (surf->hindex == ~0) ++ return 0; ++ ++ *obj = vc4_use_bo(exec, surf->hindex); ++ if (!*obj) ++ return -EINVAL; ++ ++ if (surf->offset & 0xf) { ++ DRM_ERROR("MSAA write must be 16b aligned.\n"); ++ return -EINVAL; ++ } ++ ++ return vc4_full_res_bounds_check(exec, *obj, surf); ++} ++ + static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + struct drm_gem_cma_object **obj, + struct drm_vc4_submit_rcl_surface *surf) +@@ -278,9 +426,10 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + uint8_t format = VC4_GET_FIELD(surf->bits, + VC4_LOADSTORE_TILE_BUFFER_FORMAT); + int cpp; ++ int ret; + +- if (surf->pad != 0) { +- DRM_ERROR("Padding unset\n"); ++ if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ DRM_ERROR("Extra flags set\n"); + return -EINVAL; + } + +@@ -290,6 +439,25 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + if (!vc4_use_bo(exec, surf->hindex, VC4_MODE_RENDER, obj)) + return -EINVAL; + ++ if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ if (surf == &exec->args->zs_write) { ++ DRM_ERROR("general zs write may not be a full-res.\n"); ++ return -EINVAL; ++ } ++ ++ if (surf->bits != 0) { ++ DRM_ERROR("load/store general bits set with " ++ "full res load/store.\n"); ++ return -EINVAL; ++ } ++ ++ ret = vc4_full_res_bounds_check(exec, *obj, surf); ++ if (!ret) ++ return ret; ++ ++ return 0; ++ } ++ + if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK | + VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK | + VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) { +@@ -341,9 +509,10 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + } + + static int +-vc4_rcl_ms_surface_setup(struct vc4_exec_info *exec, +- struct drm_gem_cma_object **obj, +- struct drm_vc4_submit_rcl_surface *surf) ++vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, ++ struct vc4_rcl_setup *setup, ++ struct drm_gem_cma_object **obj, ++ struct drm_vc4_submit_rcl_surface *surf) + { + uint8_t tiling = VC4_GET_FIELD(surf->bits, + VC4_RENDER_CONFIG_MEMORY_FORMAT); +@@ -351,13 +520,15 @@ vc4_rcl_ms_surface_setup(struct vc4_exec_info *exec, + VC4_RENDER_CONFIG_FORMAT); + int cpp; + +- if (surf->pad != 0) { +- DRM_ERROR("Padding unset\n"); ++ if (surf->flags != 0) { ++ DRM_ERROR("No flags supported on render config.\n"); + return -EINVAL; + } + + if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK | +- VC4_RENDER_CONFIG_FORMAT_MASK)) { ++ VC4_RENDER_CONFIG_FORMAT_MASK | ++ VC4_RENDER_CONFIG_MS_MODE_4X | ++ VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) { + DRM_ERROR("Unknown bits in render config: 0x%04x\n", + surf->bits); + return -EINVAL; +@@ -413,18 +584,20 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) + if (has_bin && + (args->max_x_tile > exec->bin_tiles_x || + args->max_y_tile > exec->bin_tiles_y)) { +- DRM_ERROR("Render tiles (%d,%d) outside of bin config (%d,%d)\n", ++ DRM_ERROR("Render tiles (%d,%d) outside of bin config " ++ "(%d,%d)\n", + args->max_x_tile, args->max_y_tile, + exec->bin_tiles_x, exec->bin_tiles_y); + return -EINVAL; + } + +- ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read); ++ ret = vc4_rcl_render_config_surface_setup(exec, &setup, ++ &setup.color_write, ++ &args->color_write); + if (ret) + return ret; + +- ret = vc4_rcl_ms_surface_setup(exec, &setup.color_ms_write, +- &args->color_ms_write); ++ ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read); + if (ret) + return ret; + +@@ -436,10 +609,21 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) + if (ret) + return ret; + ++ ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write, ++ &args->msaa_color_write); ++ if (ret) ++ return ret; ++ ++ ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write, ++ &args->msaa_zs_write); ++ if (ret) ++ return ret; ++ + /* We shouldn't even have the job submitted to us if there's no + * surface to write out. + */ +- if (!setup.color_ms_write && !setup.zs_write) { ++ if (!setup.color_write && !setup.zs_write && ++ !setup.msaa_color_write && !setup.msaa_zs_write) { + DRM_ERROR("RCL requires color or Z/S write\n"); + return -EINVAL; + } +diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c +index e44e355..2f22f19 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate.c ++++ b/drivers/gpu/drm/vc4/vc4_validate.c +@@ -400,9 +400,8 @@ validate_tile_binning_config(VALIDATE_ARGS) + } + + if (flags & (VC4_BIN_CONFIG_DB_NON_MS | +- VC4_BIN_CONFIG_TILE_BUFFER_64BIT | +- VC4_BIN_CONFIG_MS_MODE_4X)) { +- DRM_ERROR("unsupported bining config flags 0x%02x\n", flags); ++ VC4_BIN_CONFIG_TILE_BUFFER_64BIT)) { ++ DRM_ERROR("unsupported binning config flags 0x%02x\n", flags); + return -EINVAL; + } + +diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h +index 4a8d19f..49cd992 100644 +--- a/include/uapi/drm/vc4_drm.h ++++ b/include/uapi/drm/vc4_drm.h +@@ -46,10 +46,13 @@ struct drm_vc4_submit_rcl_surface { + uint32_t hindex; /* Handle index, or ~0 if not present. */ + uint32_t offset; /* Offset to start of buffer. */ + /* +- * Bits for either render config (color_ms_write) or load/store packet. ++ * Bits for either render config (color_write) or load/store packet. ++ * Bits should all be 0 for MSAA load/stores. + */ + uint16_t bits; +- uint16_t pad; ++ ++#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) ++ uint16_t flags; + }; + + /** +@@ -128,9 +131,11 @@ struct drm_vc4_submit_cl { + uint8_t max_x_tile; + uint8_t max_y_tile; + struct drm_vc4_submit_rcl_surface color_read; +- struct drm_vc4_submit_rcl_surface color_ms_write; ++ struct drm_vc4_submit_rcl_surface color_write; + struct drm_vc4_submit_rcl_surface zs_read; + struct drm_vc4_submit_rcl_surface zs_write; ++ struct drm_vc4_submit_rcl_surface msaa_color_write; ++ struct drm_vc4_submit_rcl_surface msaa_zs_write; + uint32_t clear_color[2]; + uint32_t clear_z; + uint8_t clear_s; +-- +2.5.0 + + +From c5f0c816c8fb2dc259d2ffe1ec6ea143658c3731 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Tue, 8 Dec 2015 14:00:43 -0800 +Subject: [PATCH 57/59] drm/vc4: A few more non-functional changes to sync to + upstream. + +At this point all that's left is the force-enable of HDMI connector, +and using direct firmware calls to turn on V3D instead of the generic +power domain support. + +Signed-off-by: Eric Anholt +--- + drivers/gpu/drm/vc4/vc4_v3d.c | 2 +- + include/uapi/drm/vc4_drm.h | 182 +++++++++++++++++++++--------------------- + 2 files changed, 92 insertions(+), 92 deletions(-) + +diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c +index 29a222f..4d103f7 100644 +--- a/drivers/gpu/drm/vc4/vc4_v3d.c ++++ b/drivers/gpu/drm/vc4/vc4_v3d.c +@@ -109,7 +109,7 @@ static const struct { + + int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused) + { +- struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + int i; +diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h +index 49cd992..eeb37e3 100644 +--- a/include/uapi/drm/vc4_drm.h ++++ b/include/uapi/drm/vc4_drm.h +@@ -24,7 +24,7 @@ + #ifndef _UAPI_VC4_DRM_H_ + #define _UAPI_VC4_DRM_H_ + +-#include ++#include "drm.h" + + #define DRM_VC4_SUBMIT_CL 0x00 + #define DRM_VC4_WAIT_SEQNO 0x01 +@@ -34,25 +34,25 @@ + #define DRM_VC4_CREATE_SHADER_BO 0x05 + #define DRM_VC4_GET_HANG_STATE 0x06 + +-#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) +-#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) +-#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) +-#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) +-#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) +-#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) +-#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) ++#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) ++#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) ++#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) ++#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) ++#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) ++#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) ++#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) + + struct drm_vc4_submit_rcl_surface { +- uint32_t hindex; /* Handle index, or ~0 if not present. */ +- uint32_t offset; /* Offset to start of buffer. */ ++ __u32 hindex; /* Handle index, or ~0 if not present. */ ++ __u32 offset; /* Offset to start of buffer. */ + /* +- * Bits for either render config (color_write) or load/store packet. +- * Bits should all be 0 for MSAA load/stores. ++ * Bits for either render config (color_write) or load/store packet. ++ * Bits should all be 0 for MSAA load/stores. + */ +- uint16_t bits; ++ __u16 bits; + + #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) +- uint16_t flags; ++ __u16 flags; + }; + + /** +@@ -76,7 +76,7 @@ struct drm_vc4_submit_cl { + * then writes out the state updates and draw calls necessary per tile + * to the tile allocation BO. + */ +- uint64_t bin_cl; ++ __u64 bin_cl; + + /* Pointer to the shader records. + * +@@ -85,16 +85,16 @@ struct drm_vc4_submit_cl { + * reference to the shader record has enough information to determine + * how many pointers are necessary (fixed number for shaders/uniforms, + * and an attribute count), so those BO indices into bo_handles are +- * just stored as uint32_ts before each shader record passed in. ++ * just stored as __u32s before each shader record passed in. + */ +- uint64_t shader_rec; ++ __u64 shader_rec; + + /* Pointer to uniform data and texture handles for the textures + * referenced by the shader. + * + * For each shader state record, there is a set of uniform data in the + * order referenced by the record (FS, VS, then CS). Each set of +- * uniform data has a uint32_t index into bo_handles per texture ++ * uniform data has a __u32 index into bo_handles per texture + * sample operation, in the order the QPU_W_TMUn_S writes appear in + * the program. Following the texture BO handle indices is the actual + * uniform data. +@@ -103,52 +103,52 @@ struct drm_vc4_submit_cl { + * because the kernel has to determine the sizes anyway during shader + * code validation. + */ +- uint64_t uniforms; +- uint64_t bo_handles; ++ __u64 uniforms; ++ __u64 bo_handles; + + /* Size in bytes of the binner command list. */ +- uint32_t bin_cl_size; ++ __u32 bin_cl_size; + /* Size in bytes of the set of shader records. */ +- uint32_t shader_rec_size; ++ __u32 shader_rec_size; + /* Number of shader records. + * + * This could just be computed from the contents of shader_records and + * the address bits of references to them from the bin CL, but it + * keeps the kernel from having to resize some allocations it makes. + */ +- uint32_t shader_rec_count; ++ __u32 shader_rec_count; + /* Size in bytes of the uniform state. */ +- uint32_t uniforms_size; ++ __u32 uniforms_size; + + /* Number of BO handles passed in (size is that times 4). */ +- uint32_t bo_handle_count; ++ __u32 bo_handle_count; + + /* RCL setup: */ +- uint16_t width; +- uint16_t height; +- uint8_t min_x_tile; +- uint8_t min_y_tile; +- uint8_t max_x_tile; +- uint8_t max_y_tile; ++ __u16 width; ++ __u16 height; ++ __u8 min_x_tile; ++ __u8 min_y_tile; ++ __u8 max_x_tile; ++ __u8 max_y_tile; + struct drm_vc4_submit_rcl_surface color_read; + struct drm_vc4_submit_rcl_surface color_write; + struct drm_vc4_submit_rcl_surface zs_read; + struct drm_vc4_submit_rcl_surface zs_write; + struct drm_vc4_submit_rcl_surface msaa_color_write; + struct drm_vc4_submit_rcl_surface msaa_zs_write; +- uint32_t clear_color[2]; +- uint32_t clear_z; +- uint8_t clear_s; ++ __u32 clear_color[2]; ++ __u32 clear_z; ++ __u8 clear_s; + +- uint32_t pad:24; ++ __u32 pad:24; + + #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) +- uint32_t flags; ++ __u32 flags; + + /* Returned value of the seqno of this render job (for the + * wait ioctl). + */ +- uint64_t seqno; ++ __u64 seqno; + }; + + /** +@@ -159,8 +159,8 @@ struct drm_vc4_submit_cl { + * block, just return the status." + */ + struct drm_vc4_wait_seqno { +- uint64_t seqno; +- uint64_t timeout_ns; ++ __u64 seqno; ++ __u64 timeout_ns; + }; + + /** +@@ -172,9 +172,9 @@ struct drm_vc4_wait_seqno { + * completed. + */ + struct drm_vc4_wait_bo { +- uint32_t handle; +- uint32_t pad; +- uint64_t timeout_ns; ++ __u32 handle; ++ __u32 pad; ++ __u64 timeout_ns; + }; + + /** +@@ -184,11 +184,30 @@ struct drm_vc4_wait_bo { + * used in a future extension. + */ + struct drm_vc4_create_bo { +- uint32_t size; +- uint32_t flags; ++ __u32 size; ++ __u32 flags; + /** Returned GEM handle for the BO. */ +- uint32_t handle; +- uint32_t pad; ++ __u32 handle; ++ __u32 pad; ++}; ++ ++/** ++ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. ++ * ++ * This doesn't actually perform an mmap. Instead, it returns the ++ * offset you need to use in an mmap on the DRM device node. This ++ * means that tools like valgrind end up knowing about the mapped ++ * memory. ++ * ++ * There are currently no values for the flags argument, but it may be ++ * used in a future extension. ++ */ ++struct drm_vc4_mmap_bo { ++ /** Handle for the object being mapped. */ ++ __u32 handle; ++ __u32 flags; ++ /** offset into the drm node to use for subsequent mmap call. */ ++ __u64 offset; + }; + + /** +@@ -201,43 +220,24 @@ struct drm_vc4_create_bo { + */ + struct drm_vc4_create_shader_bo { + /* Size of the data argument. */ +- uint32_t size; ++ __u32 size; + /* Flags, currently must be 0. */ +- uint32_t flags; ++ __u32 flags; + + /* Pointer to the data. */ +- uint64_t data; ++ __u64 data; + + /** Returned GEM handle for the BO. */ +- uint32_t handle; ++ __u32 handle; + /* Pad, must be 0. */ +- uint32_t pad; +-}; +- +-/** +- * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. +- * +- * This doesn't actually perform an mmap. Instead, it returns the +- * offset you need to use in an mmap on the DRM device node. This +- * means that tools like valgrind end up knowing about the mapped +- * memory. +- * +- * There are currently no values for the flags argument, but it may be +- * used in a future extension. +- */ +-struct drm_vc4_mmap_bo { +- /** Handle for the object being mapped. */ +- uint32_t handle; +- uint32_t flags; +- /** offset into the drm node to use for subsequent mmap call. */ +- uint64_t offset; ++ __u32 pad; + }; + + struct drm_vc4_get_hang_state_bo { +- uint32_t handle; +- uint32_t paddr; +- uint32_t size; +- uint32_t pad; ++ __u32 handle; ++ __u32 paddr; ++ __u32 size; ++ __u32 pad; + }; + + /** +@@ -246,34 +246,34 @@ struct drm_vc4_get_hang_state_bo { + */ + struct drm_vc4_get_hang_state { + /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ +- uint64_t bo; ++ __u64 bo; + /** + * On input, the size of the bo array. Output is the number + * of bos to be returned. + */ +- uint32_t bo_count; ++ __u32 bo_count; + +- uint32_t start_bin, start_render; ++ __u32 start_bin, start_render; + +- uint32_t ct0ca, ct0ea; +- uint32_t ct1ca, ct1ea; +- uint32_t ct0cs, ct1cs; +- uint32_t ct0ra0, ct1ra0; ++ __u32 ct0ca, ct0ea; ++ __u32 ct1ca, ct1ea; ++ __u32 ct0cs, ct1cs; ++ __u32 ct0ra0, ct1ra0; + +- uint32_t bpca, bpcs; +- uint32_t bpoa, bpos; ++ __u32 bpca, bpcs; ++ __u32 bpoa, bpos; + +- uint32_t vpmbase; ++ __u32 vpmbase; + +- uint32_t dbge; +- uint32_t fdbgo; +- uint32_t fdbgb; +- uint32_t fdbgr; +- uint32_t fdbgs; +- uint32_t errstat; ++ __u32 dbge; ++ __u32 fdbgo; ++ __u32 fdbgb; ++ __u32 fdbgr; ++ __u32 fdbgs; ++ __u32 errstat; + + /* Pad that we may save more registers into in the future. */ +- uint32_t pad[16]; ++ __u32 pad[16]; + }; + + #endif /* _UAPI_VC4_DRM_H_ */ +-- +2.5.0 + + +From a28a42a7faea43197392a90984f5354168494f14 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Tue, 15 Dec 2015 23:46:32 +0000 +Subject: [PATCH 58/59] drm/vc4: Use "hpd-gpios" for HDMI GPIO, like what + landed upstream. + +Signed-off-by: Eric Anholt +--- + arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts +index cf5d5c9..da37483 100644 +--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts ++++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts +@@ -68,7 +68,7 @@ + <0x7e808000 0x100>; + interrupts = <2 8>, <2 9>; + ddc = <&i2c2>; +- hpd-gpio = <&gpio 46 GPIO_ACTIVE_HIGH>; ++ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + clocks = <&cprman BCM2835_PLLH_PIX>, + <&cprman BCM2835_CLOCK_HSM>; + clock-names = "pixel", "hdmi"; +-- +2.5.0 + + +From 8353706bc1d231c15c7113e678cfeeefe03e9eaf Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Mon, 7 Dec 2015 12:35:01 -0800 +Subject: [PATCH 59/59] drm/vc4: Synchronize validation code for v2 submission + upstream. + +Signed-off-by: Eric Anholt +--- + drivers/gpu/drm/vc4/vc4_drv.h | 24 +-- + drivers/gpu/drm/vc4/vc4_gem.c | 14 +- + drivers/gpu/drm/vc4/vc4_render_cl.c | 6 +- + drivers/gpu/drm/vc4/vc4_validate.c | 287 +++++++++++++++--------------------- + 4 files changed, 135 insertions(+), 196 deletions(-) + +diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h +index 53dfa8d..ed93fa7 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.h ++++ b/drivers/gpu/drm/vc4/vc4_drv.h +@@ -189,17 +189,6 @@ to_vc4_encoder(struct drm_encoder *encoder) + #define HVS_READ(offset) readl(vc4->hvs->regs + offset) + #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) + +-enum vc4_bo_mode { +- VC4_MODE_UNDECIDED, +- VC4_MODE_RENDER, +- VC4_MODE_SHADER, +-}; +- +-struct vc4_bo_exec_state { +- struct drm_gem_cma_object *bo; +- enum vc4_bo_mode mode; +-}; +- + struct vc4_exec_info { + /* Sequence number for this bin/render job. */ + uint64_t seqno; +@@ -210,7 +199,7 @@ struct vc4_exec_info { + /* This is the array of BOs that were looked up at the start of exec. + * Command validation will use indices into this array. + */ +- struct vc4_bo_exec_state *bo; ++ struct drm_gem_cma_object **bo; + uint32_t bo_count; + + /* Pointers for our position in vc4->job_list */ +@@ -238,7 +227,6 @@ struct vc4_exec_info { + * command lists. + */ + struct vc4_shader_state { +- uint8_t packet; + uint32_t addr; + /* Maximum vertex index referenced by any primitive using this + * shader state. +@@ -254,6 +242,7 @@ struct vc4_exec_info { + bool found_tile_binning_mode_config_packet; + bool found_start_tile_binning_packet; + bool found_increment_semaphore_packet; ++ bool found_flush; + uint8_t bin_tiles_x, bin_tiles_y; + struct drm_gem_cma_object *tile_bo; + uint32_t tile_alloc_offset; +@@ -265,6 +254,9 @@ struct vc4_exec_info { + uint32_t ct0ca, ct0ea; + uint32_t ct1ca, ct1ea; + ++ /* Pointer to the unvalidated bin CL (if present). */ ++ void *bin_u; ++ + /* Pointers to the shader recs. These paddr gets incremented as CL + * packets are relocated in validate_gl_shader_state, and the vaddrs + * (u and v) get incremented and size decremented as the shader recs +@@ -455,10 +447,8 @@ vc4_validate_bin_cl(struct drm_device *dev, + int + vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); + +-bool vc4_use_bo(struct vc4_exec_info *exec, +- uint32_t hindex, +- enum vc4_bo_mode mode, +- struct drm_gem_cma_object **obj); ++struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, ++ uint32_t hindex); + + int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); + +diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c +index fb0b92d..39f29e7 100644 +--- a/drivers/gpu/drm/vc4/vc4_gem.c ++++ b/drivers/gpu/drm/vc4/vc4_gem.c +@@ -169,8 +169,8 @@ vc4_save_hang_state(struct drm_device *dev) + } + + for (i = 0; i < exec->bo_count; i++) { +- drm_gem_object_reference(&exec->bo[i].bo->base); +- kernel_state->bo[i] = &exec->bo[i].bo->base; ++ drm_gem_object_reference(&exec->bo[i]->base); ++ kernel_state->bo[i] = &exec->bo[i]->base; + } + + list_for_each_entry(bo, &exec->unref_list, unref_head) { +@@ -397,7 +397,7 @@ vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno) + unsigned i; + + for (i = 0; i < exec->bo_count; i++) { +- bo = to_vc4_bo(&exec->bo[i].bo->base); ++ bo = to_vc4_bo(&exec->bo[i]->base); + bo->seqno = seqno; + } + +@@ -467,7 +467,7 @@ vc4_cl_lookup_bos(struct drm_device *dev, + return -EINVAL; + } + +- exec->bo = kcalloc(exec->bo_count, sizeof(struct vc4_bo_exec_state), ++ exec->bo = kcalloc(exec->bo_count, sizeof(struct drm_gem_cma_object *), + GFP_KERNEL); + if (!exec->bo) { + DRM_ERROR("Failed to allocate validated BO pointers\n"); +@@ -500,7 +500,7 @@ vc4_cl_lookup_bos(struct drm_device *dev, + goto fail; + } + drm_gem_object_reference(bo); +- exec->bo[i].bo = (struct drm_gem_cma_object *)bo; ++ exec->bo[i] = (struct drm_gem_cma_object *)bo; + } + spin_unlock(&file_priv->table_lock); + +@@ -591,6 +591,8 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) + + exec->ct0ca = exec->exec_bo->paddr + bin_offset; + ++ exec->bin_u = bin; ++ + exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset; + exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset; + exec->shader_rec_size = args->shader_rec_size; +@@ -622,7 +624,7 @@ vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec) + mutex_lock(&dev->struct_mutex); + if (exec->bo) { + for (i = 0; i < exec->bo_count; i++) +- drm_gem_object_unreference(&exec->bo[i].bo->base); ++ drm_gem_object_unreference(&exec->bo[i]->base); + kfree(exec->bo); + } + +diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c +index 8f2ec57..8a2a312 100644 +--- a/drivers/gpu/drm/vc4/vc4_render_cl.c ++++ b/drivers/gpu/drm/vc4/vc4_render_cl.c +@@ -436,7 +436,8 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + if (surf->hindex == ~0) + return 0; + +- if (!vc4_use_bo(exec, surf->hindex, VC4_MODE_RENDER, obj)) ++ *obj = vc4_use_bo(exec, surf->hindex); ++ if (!*obj) + return -EINVAL; + + if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { +@@ -537,7 +538,8 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, + if (surf->hindex == ~0) + return 0; + +- if (!vc4_use_bo(exec, surf->hindex, VC4_MODE_RENDER, obj)) ++ *obj = vc4_use_bo(exec, surf->hindex); ++ if (!*obj) + return -EINVAL; + + if (tiling > VC4_TILING_FORMAT_LT) { +diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c +index 2f22f19..0fb5b99 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate.c ++++ b/drivers/gpu/drm/vc4/vc4_validate.c +@@ -94,42 +94,42 @@ size_is_lt(uint32_t width, uint32_t height, int cpp) + height <= 4 * utile_height(cpp)); + } + +-bool +-vc4_use_bo(struct vc4_exec_info *exec, +- uint32_t hindex, +- enum vc4_bo_mode mode, +- struct drm_gem_cma_object **obj) ++struct drm_gem_cma_object * ++vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex) + { +- *obj = NULL; ++ struct drm_gem_cma_object *obj; ++ struct vc4_bo *bo; + + if (hindex >= exec->bo_count) { + DRM_ERROR("BO index %d greater than BO count %d\n", + hindex, exec->bo_count); +- return false; ++ return NULL; + } ++ obj = exec->bo[hindex]; ++ bo = to_vc4_bo(&obj->base); + +- if (exec->bo[hindex].mode != mode) { +- if (exec->bo[hindex].mode == VC4_MODE_UNDECIDED) { +- exec->bo[hindex].mode = mode; +- } else { +- DRM_ERROR("BO index %d reused with mode %d vs %d\n", +- hindex, exec->bo[hindex].mode, mode); +- return false; +- } ++ if (bo->validated_shader) { ++ DRM_ERROR("Trying to use shader BO as something other than " ++ "a shader\n"); ++ return NULL; + } + +- *obj = exec->bo[hindex].bo; +- return true; ++ return obj; ++} ++ ++static struct drm_gem_cma_object * ++vc4_use_handle(struct vc4_exec_info *exec, uint32_t gem_handles_packet_index) ++{ ++ return vc4_use_bo(exec, exec->bo_index[gem_handles_packet_index]); + } + + static bool +-vc4_use_handle(struct vc4_exec_info *exec, +- uint32_t gem_handles_packet_index, +- enum vc4_bo_mode mode, +- struct drm_gem_cma_object **obj) ++validate_bin_pos(struct vc4_exec_info *exec, void *untrusted, uint32_t pos) + { +- return vc4_use_bo(exec, exec->bo_index[gem_handles_packet_index], +- mode, obj); ++ /* Note that the untrusted pointer passed to these functions is ++ * incremented past the packet byte. ++ */ ++ return (untrusted - 1 == exec->bin_u + pos); + } + + static uint32_t +@@ -202,13 +202,13 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, + } + + static int +-validate_flush_all(VALIDATE_ARGS) ++validate_flush(VALIDATE_ARGS) + { +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("VC4_PACKET_FLUSH_ALL after " +- "VC4_PACKET_INCREMENT_SEMAPHORE\n"); ++ if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) { ++ DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n"); + return -EINVAL; + } ++ exec->found_flush = true; + + return 0; + } +@@ -233,17 +233,13 @@ validate_start_tile_binning(VALIDATE_ARGS) + static int + validate_increment_semaphore(VALIDATE_ARGS) + { +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("Duplicate VC4_PACKET_INCREMENT_SEMAPHORE\n"); ++ if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) { ++ DRM_ERROR("Bin CL must end with " ++ "VC4_PACKET_INCREMENT_SEMAPHORE\n"); + return -EINVAL; + } + exec->found_increment_semaphore_packet = true; + +- /* Once we've found the semaphore increment, there should be one FLUSH +- * then the end of the command list. The FLUSH actually triggers the +- * increment, so we only need to make sure there +- */ +- + return 0; + } + +@@ -257,11 +253,6 @@ validate_indexed_prim_list(VALIDATE_ARGS) + uint32_t index_size = (*(uint8_t *)(untrusted + 0) >> 4) ? 2 : 1; + struct vc4_shader_state *shader_state; + +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("Drawing after VC4_PACKET_INCREMENT_SEMAPHORE\n"); +- return -EINVAL; +- } +- + /* Check overflow condition */ + if (exec->shader_state_count == 0) { + DRM_ERROR("shader state must precede primitives\n"); +@@ -272,7 +263,8 @@ validate_indexed_prim_list(VALIDATE_ARGS) + if (max_index > shader_state->max_index) + shader_state->max_index = max_index; + +- if (!vc4_use_handle(exec, 0, VC4_MODE_RENDER, &ib)) ++ ib = vc4_use_handle(exec, 0); ++ if (!ib) + return -EINVAL; + + if (offset > ib->base.size || +@@ -295,11 +287,6 @@ validate_gl_array_primitive(VALIDATE_ARGS) + uint32_t max_index; + struct vc4_shader_state *shader_state; + +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("Drawing after VC4_PACKET_INCREMENT_SEMAPHORE\n"); +- return -EINVAL; +- } +- + /* Check overflow condition */ + if (exec->shader_state_count == 0) { + DRM_ERROR("shader state must precede primitives\n"); +@@ -329,7 +316,6 @@ validate_gl_shader_state(VALIDATE_ARGS) + return -EINVAL; + } + +- exec->shader_state[i].packet = VC4_PACKET_GL_SHADER_STATE; + exec->shader_state[i].addr = *(uint32_t *)untrusted; + exec->shader_state[i].max_index = 0; + +@@ -348,31 +334,6 @@ validate_gl_shader_state(VALIDATE_ARGS) + } + + static int +-validate_nv_shader_state(VALIDATE_ARGS) +-{ +- uint32_t i = exec->shader_state_count++; +- +- if (i >= exec->shader_state_size) { +- DRM_ERROR("More requests for shader states than declared\n"); +- return -EINVAL; +- } +- +- exec->shader_state[i].packet = VC4_PACKET_NV_SHADER_STATE; +- exec->shader_state[i].addr = *(uint32_t *)untrusted; +- +- if (exec->shader_state[i].addr & 15) { +- DRM_ERROR("NV shader state address 0x%08x misaligned\n", +- exec->shader_state[i].addr); +- return -EINVAL; +- } +- +- *(uint32_t *)validated = (exec->shader_state[i].addr + +- exec->shader_rec_p); +- +- return 0; +-} +- +-static int + validate_tile_binning_config(VALIDATE_ARGS) + { + struct drm_device *dev = exec->exec_bo->base.dev; +@@ -473,8 +434,8 @@ static const struct cmd_info { + } cmd_info[] = { + VC4_DEFINE_PACKET(VC4_PACKET_HALT, NULL), + VC4_DEFINE_PACKET(VC4_PACKET_NOP, NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, validate_flush_all), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, validate_flush), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, NULL), + VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, + validate_start_tile_binning), + VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, +@@ -488,7 +449,6 @@ static const struct cmd_info { + VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, NULL), + + VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, validate_gl_shader_state), +- VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, validate_nv_shader_state), + + VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, NULL), + VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, NULL), +@@ -575,8 +535,16 @@ vc4_validate_bin_cl(struct drm_device *dev, + return -EINVAL; + } + +- if (!exec->found_increment_semaphore_packet) { +- DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE\n"); ++ /* The bin CL must be ended with INCREMENT_SEMAPHORE and FLUSH. The ++ * semaphore is used to trigger the render CL to start up, and the ++ * FLUSH is what caps the bin lists with ++ * VC4_PACKET_RETURN_FROM_SUB_LIST (so they jump back to the main ++ * render CL when they get called to) and actually triggers the queued ++ * semaphore increment. ++ */ ++ if (!exec->found_increment_semaphore_packet || !exec->found_flush) { ++ DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + " ++ "VC4_PACKET_FLUSH\n"); + return -EINVAL; + } + +@@ -607,7 +575,8 @@ reloc_tex(struct vc4_exec_info *exec, + uint32_t cube_map_stride = 0; + enum vc4_texture_data_type type; + +- if (!vc4_use_bo(exec, texture_handle_index, VC4_MODE_RENDER, &tex)) ++ tex = vc4_use_bo(exec, texture_handle_index); ++ if (!tex) + return false; + + if (sample->is_direct) { +@@ -755,51 +724,28 @@ reloc_tex(struct vc4_exec_info *exec, + } + + static int +-validate_shader_rec(struct drm_device *dev, +- struct vc4_exec_info *exec, +- struct vc4_shader_state *state) ++validate_gl_shader_rec(struct drm_device *dev, ++ struct vc4_exec_info *exec, ++ struct vc4_shader_state *state) + { + uint32_t *src_handles; + void *pkt_u, *pkt_v; +- enum shader_rec_reloc_type { +- RELOC_CODE, +- RELOC_VBO, +- }; +- struct shader_rec_reloc { +- enum shader_rec_reloc_type type; +- uint32_t offset; +- }; +- static const struct shader_rec_reloc gl_relocs[] = { +- { RELOC_CODE, 4 }, /* fs */ +- { RELOC_CODE, 16 }, /* vs */ +- { RELOC_CODE, 28 }, /* cs */ +- }; +- static const struct shader_rec_reloc nv_relocs[] = { +- { RELOC_CODE, 4 }, /* fs */ +- { RELOC_VBO, 12 } ++ static const uint32_t shader_reloc_offsets[] = { ++ 4, /* fs */ ++ 16, /* vs */ ++ 28, /* cs */ + }; +- const struct shader_rec_reloc *relocs; +- struct drm_gem_cma_object *bo[ARRAY_SIZE(gl_relocs) + 8]; +- uint32_t nr_attributes = 0, nr_fixed_relocs, nr_relocs, packet_size; ++ uint32_t shader_reloc_count = ARRAY_SIZE(shader_reloc_offsets); ++ struct drm_gem_cma_object *bo[shader_reloc_count + 8]; ++ uint32_t nr_attributes, nr_relocs, packet_size; + int i; +- struct vc4_validated_shader_info *shader; + +- if (state->packet == VC4_PACKET_NV_SHADER_STATE) { +- relocs = nv_relocs; +- nr_fixed_relocs = ARRAY_SIZE(nv_relocs); +- +- packet_size = 16; +- } else { +- relocs = gl_relocs; +- nr_fixed_relocs = ARRAY_SIZE(gl_relocs); +- +- nr_attributes = state->addr & 0x7; +- if (nr_attributes == 0) +- nr_attributes = 8; +- packet_size = gl_shader_rec_size(state->addr); +- } +- nr_relocs = nr_fixed_relocs + nr_attributes; ++ nr_attributes = state->addr & 0x7; ++ if (nr_attributes == 0) ++ nr_attributes = 8; ++ packet_size = gl_shader_rec_size(state->addr); + ++ nr_relocs = ARRAY_SIZE(shader_reloc_offsets) + nr_attributes; + if (nr_relocs * 4 > exec->shader_rec_size) { + DRM_ERROR("overflowed shader recs reading %d handles " + "from %d bytes left\n", +@@ -829,21 +775,30 @@ validate_shader_rec(struct drm_device *dev, + exec->shader_rec_v += roundup(packet_size, 16); + exec->shader_rec_size -= packet_size; + +- for (i = 0; i < nr_relocs; i++) { +- enum vc4_bo_mode mode; ++ if (!(*(uint16_t *)pkt_u & VC4_SHADER_FLAG_FS_SINGLE_THREAD)) { ++ DRM_ERROR("Multi-threaded fragment shaders not supported.\n"); ++ return -EINVAL; ++ } + +- if (i < nr_fixed_relocs && relocs[i].type == RELOC_CODE) +- mode = VC4_MODE_SHADER; +- else +- mode = VC4_MODE_RENDER; ++ for (i = 0; i < shader_reloc_count; i++) { ++ if (src_handles[i] > exec->bo_count) { ++ DRM_ERROR("Shader handle %d too big\n", src_handles[i]); ++ return -EINVAL; ++ } + +- if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) +- return false; ++ bo[i] = exec->bo[src_handles[i]]; ++ if (!bo[i]) ++ return -EINVAL; ++ } ++ for (i = shader_reloc_count; i < nr_relocs; i++) { ++ bo[i] = vc4_use_bo(exec, src_handles[i]); ++ if (!bo[i]) ++ return -EINVAL; + } + +- for (i = 0; i < nr_fixed_relocs; i++) { +- struct vc4_bo *vc4_bo; +- uint32_t o = relocs[i].offset; ++ for (i = 0; i < shader_reloc_count; i++) { ++ struct vc4_validated_shader_info *validated_shader; ++ uint32_t o = shader_reloc_offsets[i]; + uint32_t src_offset = *(uint32_t *)(pkt_u + o); + uint32_t *texture_handles_u; + void *uniform_data_u; +@@ -851,57 +806,50 @@ validate_shader_rec(struct drm_device *dev, + + *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset; + +- switch (relocs[i].type) { +- case RELOC_CODE: +- if (src_offset != 0) { +- DRM_ERROR("Shaders must be at offset 0 " +- "of the BO.\n"); +- goto fail; +- } ++ if (src_offset != 0) { ++ DRM_ERROR("Shaders must be at offset 0 of " ++ "the BO.\n"); ++ return -EINVAL; ++ } + +- vc4_bo = to_vc4_bo(&bo[i]->base); +- shader = vc4_bo->validated_shader; +- if (!shader) +- goto fail; ++ validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader; ++ if (!validated_shader) ++ return -EINVAL; + +- if (shader->uniforms_src_size > exec->uniforms_size) { +- DRM_ERROR("Uniforms src buffer overflow\n"); +- goto fail; +- } ++ if (validated_shader->uniforms_src_size > ++ exec->uniforms_size) { ++ DRM_ERROR("Uniforms src buffer overflow\n"); ++ return -EINVAL; ++ } + +- texture_handles_u = exec->uniforms_u; +- uniform_data_u = (texture_handles_u + +- shader->num_texture_samples); +- +- memcpy(exec->uniforms_v, uniform_data_u, +- shader->uniforms_size); +- +- for (tex = 0; +- tex < shader->num_texture_samples; +- tex++) { +- if (!reloc_tex(exec, +- uniform_data_u, +- &shader->texture_samples[tex], +- texture_handles_u[tex])) { +- goto fail; +- } +- } ++ texture_handles_u = exec->uniforms_u; ++ uniform_data_u = (texture_handles_u + ++ validated_shader->num_texture_samples); + +- *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; ++ memcpy(exec->uniforms_v, uniform_data_u, ++ validated_shader->uniforms_size); + +- exec->uniforms_u += shader->uniforms_src_size; +- exec->uniforms_v += shader->uniforms_size; +- exec->uniforms_p += shader->uniforms_size; ++ for (tex = 0; ++ tex < validated_shader->num_texture_samples; ++ tex++) { ++ if (!reloc_tex(exec, ++ uniform_data_u, ++ &validated_shader->texture_samples[tex], ++ texture_handles_u[tex])) { ++ return -EINVAL; ++ } ++ } + +- break; ++ *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; + +- case RELOC_VBO: +- break; +- } ++ exec->uniforms_u += validated_shader->uniforms_src_size; ++ exec->uniforms_v += validated_shader->uniforms_size; ++ exec->uniforms_p += validated_shader->uniforms_size; + } + + for (i = 0; i < nr_attributes; i++) { +- struct drm_gem_cma_object *vbo = bo[nr_fixed_relocs + i]; ++ struct drm_gem_cma_object *vbo = ++ bo[ARRAY_SIZE(shader_reloc_offsets) + i]; + uint32_t o = 36 + i * 8; + uint32_t offset = *(uint32_t *)(pkt_u + o + 0); + uint32_t attr_size = *(uint8_t *)(pkt_u + o + 4) + 1; +@@ -933,9 +881,6 @@ validate_shader_rec(struct drm_device *dev, + } + + return 0; +- +-fail: +- return -EINVAL; + } + + int +@@ -946,7 +891,7 @@ vc4_validate_shader_recs(struct drm_device *dev, + int ret = 0; + + for (i = 0; i < exec->shader_state_count; i++) { +- ret = validate_shader_rec(dev, exec, &exec->shader_state[i]); ++ ret = validate_gl_shader_rec(dev, exec, &exec->shader_state[i]); + if (ret) + return ret; + } -- 2.5.0 diff --git a/projects/RPi2/patches/linux/linux-01-RPi_support.patch b/projects/RPi2/patches/linux/linux-01-RPi_support.patch index 60aef11b21..30518b9487 100644 --- a/projects/RPi2/patches/linux/linux-01-RPi_support.patch +++ b/projects/RPi2/patches/linux/linux-01-RPi_support.patch @@ -1,7 +1,7 @@ -From b3ee605a6d9a542c72b20eea9c34ab340e8a7083 Mon Sep 17 00:00:00 2001 +From 7845b06e18af196528ad650eccd152e7989bc69c Mon Sep 17 00:00:00 2001 From: Steve Glendinning Date: Thu, 19 Feb 2015 18:47:12 +0000 -Subject: [PATCH 01/55] smsx95xx: fix crimes against truesize +Subject: [PATCH 01/54] smsx95xx: fix crimes against truesize smsc95xx is adjusting truesize when it shouldn't, and following a recent patch from Eric this is now triggering warnings. @@ -39,10 +39,10 @@ index 66b3ab9..b544181 2.5.0 -From 16af2003a85fc6f2be1702b285eadae72e272761 Mon Sep 17 00:00:00 2001 +From 1c4ee85b4d9361be8b58687db4acdb43e7a79c14 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 17 Apr 2015 16:58:45 +0100 -Subject: [PATCH 02/55] smsc95xx: Disable turbo mode by default +Subject: [PATCH 02/54] smsc95xx: Disable turbo mode by default --- drivers/net/usb/smsc95xx.c | 2 +- @@ -65,10 +65,10 @@ index b544181..9c0da18 100755 2.5.0 -From 1080f40d03f10107b0baa0f8e938b36d8f2905a4 Mon Sep 17 00:00:00 2001 +From 38a1c0f17082b195b17ee390270377e661d2243b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Jun 2014 13:42:01 +0100 -Subject: [PATCH 03/55] vmstat: Workaround for issue where dirty page count +Subject: [PATCH 03/54] vmstat: Workaround for issue where dirty page count goes negative See: @@ -98,10 +98,10 @@ index 5dbc8b0..3a18061 100644 2.5.0 -From 09b89dd4e1296033fc8d44ddea510c4a9ca3e6d3 Mon Sep 17 00:00:00 2001 +From 7d76a16073ba70458e82edb4db8254a7a3dced6b Mon Sep 17 00:00:00 2001 From: Robert Tiemann Date: Mon, 20 Jul 2015 11:01:25 +0200 -Subject: [PATCH 04/55] BCM2835_DT: Fix I2S register map +Subject: [PATCH 04/54] BCM2835_DT: Fix I2S register map --- Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 4 ++-- @@ -158,10 +158,47 @@ index aef64de..864a3ef 100644 2.5.0 -From 8dfe39f884ab674e140dc6fc6640aaf055f1756a Mon Sep 17 00:00:00 2001 +From 688a5f2ada4fbd16547b574a17e6d359ab2364d0 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 4 Dec 2015 17:41:50 +0000 +Subject: [PATCH 05/54] irq-bcm2836: Prevent spurious interrupts, and trap them + early + +The old arch-specific IRQ macros included a dsb to ensure the +write to clear the mailbox interrupt completed before returning +from the interrupt. The BCM2836 irqchip driver needs the same +precaution to avoid spurious interrupts. + +Spurious interrupts are still possible for other reasons, +though, so trap them early. +--- + drivers/irqchip/irq-bcm2836.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c +index f687082..4cd8ebe 100644 +--- a/drivers/irqchip/irq-bcm2836.c ++++ b/drivers/irqchip/irq-bcm2836.c +@@ -170,9 +170,10 @@ __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs) + u32 ipi = ffs(mbox_val) - 1; + + writel(1 << ipi, mailbox0); ++ dsb(); + handle_IPI(ipi, regs); + #endif +- } else { ++ } else if (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); +-- +2.5.0 + + +From 6edc4f10cd957d1b3cb705fe06003b965f24fd71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 12 Jun 2015 19:01:05 +0200 -Subject: [PATCH 05/55] irqchip: bcm2835: Add FIQ support +Subject: [PATCH 06/54] irqchip: bcm2835: Add FIQ support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -293,10 +330,112 @@ index bf9cc5f..3f601f9 100644 2.5.0 -From 3df5df89b2338b81aedff704bef5f2aaa1d3bcde Mon Sep 17 00:00:00 2001 +From e24db33d028844ac535e9e8d72a0c77e6dc7cb95 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 23 Oct 2015 16:26:55 +0200 +Subject: [PATCH 07/54] irqchip: irq-bcm2835: Add 2836 FIQ support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + drivers/irqchip/irq-bcm2835.c | 42 ++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 40 insertions(+), 2 deletions(-) + +diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c +index 3f601f9..20deb28 100644 +--- a/drivers/irqchip/irq-bcm2835.c ++++ b/drivers/irqchip/irq-bcm2835.c +@@ -50,6 +50,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -70,6 +72,9 @@ + #define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \ + | SHORTCUT1_MASK | SHORTCUT2_MASK) + ++#undef ARM_LOCAL_GPU_INT_ROUTING ++#define ARM_LOCAL_GPU_INT_ROUTING 0x0c ++ + #define REG_FIQ_CONTROL 0x0c + #define REG_FIQ_ENABLE 0x80 + #define REG_FIQ_DISABLE 0 +@@ -95,6 +100,7 @@ struct armctrl_ic { + void __iomem *enable[NR_BANKS]; + void __iomem *disable[NR_BANKS]; + struct irq_domain *domain; ++ struct regmap *local_regmap; + }; + + static struct armctrl_ic intc __read_mostly; +@@ -128,12 +134,35 @@ static void armctrl_mask_irq(struct irq_data *d) + + static void armctrl_unmask_irq(struct irq_data *d) + { +- if (d->hwirq >= NUMBER_IRQS) ++ if (d->hwirq >= NUMBER_IRQS) { ++ if (num_online_cpus() > 1) { ++ unsigned int data; ++ int ret; ++ ++ if (!intc.local_regmap) { ++ pr_err("FIQ is disabled due to missing regmap\n"); ++ return; ++ } ++ ++ ret = regmap_read(intc.local_regmap, ++ ARM_LOCAL_GPU_INT_ROUTING, &data); ++ if (ret) { ++ pr_err("Failed to read int routing %d\n", ret); ++ return; ++ } ++ ++ data &= ~0xc; ++ data |= (1 << 2); ++ regmap_write(intc.local_regmap, ++ ARM_LOCAL_GPU_INT_ROUTING, data); ++ } ++ + writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), + intc.base + REG_FIQ_CONTROL); +- else ++ } else { + writel_relaxed(HWIRQ_BIT(d->hwirq), + intc.enable[HWIRQ_BANK(d->hwirq)]); ++ } + } + + static struct irq_chip armctrl_chip = { +@@ -211,6 +240,15 @@ static int __init armctrl_of_init(struct device_node *node, + set_handle_irq(bcm2835_handle_irq); + } + ++ if (is_2836) { ++ intc.local_regmap = ++ syscon_regmap_lookup_by_compatible("brcm,bcm2836-arm-local"); ++ if (IS_ERR(intc.local_regmap)) { ++ pr_err("Failed to get local register map. FIQ is disabled for cpus > 1\n"); ++ intc.local_regmap = NULL; ++ } ++ } ++ + /* Make a duplicate irq range which is used to enable FIQ */ + for (b = 0; b < NR_BANKS; b++) { + for (i = 0; i < bank_irqs[b]; i++) { +-- +2.5.0 + + +From a628f89696a423d8be5e4f6afacd1b2164dc72c0 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 30 Jun 2015 14:12:42 +0100 -Subject: [PATCH 06/55] serial: 8250: Don't crash when nr_uarts is 0 +Subject: [PATCH 08/54] serial: 8250: Don't crash when nr_uarts is 0 --- drivers/tty/serial/8250/8250_core.c | 2 ++ @@ -319,10 +458,10 @@ index 3912646..b51a59c 100644 2.5.0 -From 36a124709393f4e6183a4767d296786f8fe5b431 Mon Sep 17 00:00:00 2001 +From 05998ad69409fe1312ea7070e5ad3394b1a27712 Mon Sep 17 00:00:00 2001 From: notro Date: Thu, 10 Jul 2014 13:59:47 +0200 -Subject: [PATCH 07/55] pinctrl-bcm2835: Set base to 0 give expected gpio +Subject: [PATCH 09/54] pinctrl-bcm2835: Set base to 0 give expected gpio numbering Signed-off-by: Noralf Tronnes @@ -331,10 +470,10 @@ Signed-off-by: Noralf Tronnes 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index a1ea565..31c1314 100644 +index 2e6ca69..62cc363 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -372,7 +372,7 @@ static struct gpio_chip bcm2835_gpio_chip = { +@@ -373,7 +373,7 @@ static struct gpio_chip bcm2835_gpio_chip = { .get = bcm2835_gpio_get, .set = bcm2835_gpio_set, .to_irq = bcm2835_gpio_to_irq, @@ -347,44 +486,10 @@ index a1ea565..31c1314 100644 2.5.0 -From 2eeb5f8c1d69737be5bd8b3bbd0c142d15222674 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Wed, 4 Feb 2015 10:02:24 +0000 -Subject: [PATCH 08/55] pinctrl-bcm2835: bcm2835_gpio_direction_output must set - the value - ---- - drivers/pinctrl/bcm/pinctrl-bcm2835.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index 31c1314..4a7f6315 100644 ---- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c -+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -345,7 +345,14 @@ static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) - static int bcm2835_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) - { -- return pinctrl_gpio_direction_output(chip->base + offset); -+ struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); -+ int ret; -+ -+ ret = pinctrl_gpio_direction_output(chip->base + offset); -+ if (ret >= 0) -+ bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); -+ -+ return ret; - } - - static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) --- -2.5.0 - - -From 3e14a4401126124b4ef5076808c8db4f3105dc79 Mon Sep 17 00:00:00 2001 +From 511ab7e5940ce9cc535fed78408df6ccea648a5a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 24 Feb 2015 13:40:50 +0000 -Subject: [PATCH 09/55] pinctrl-bcm2835: Fix interrupt handling for GPIOs 28-31 +Subject: [PATCH 10/54] pinctrl-bcm2835: Fix interrupt handling for GPIOs 28-31 and 46-53 Contrary to the documentation, the BCM2835 GPIO controller actually has @@ -405,7 +510,7 @@ the pins are often used for I2S instead. 1 file changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index 4a7f6315..10625ce 100644 +index 62cc363..ab345f4 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -47,6 +47,7 @@ @@ -441,7 +546,7 @@ index 4a7f6315..10625ce 100644 spinlock_t irq_lock[BCM2835_NUM_BANKS]; }; -@@ -384,17 +385,16 @@ static struct gpio_chip bcm2835_gpio_chip = { +@@ -378,17 +379,16 @@ static struct gpio_chip bcm2835_gpio_chip = { .can_sleep = false, }; @@ -462,7 +567,7 @@ index 4a7f6315..10625ce 100644 events &= pc->enabled_irq_map[bank]; for_each_set_bit(offset, &events, 32) { gpio = (32 * bank) + offset; -@@ -402,7 +402,30 @@ static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) +@@ -396,7 +396,30 @@ static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); } @@ -494,7 +599,7 @@ index 4a7f6315..10625ce 100644 } static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, -@@ -991,8 +1014,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) +@@ -985,8 +1008,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < BCM2835_NUM_BANKS; i++) { unsigned long events; unsigned offset; @@ -503,7 +608,7 @@ index 4a7f6315..10625ce 100644 /* clear event detection flags */ bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); -@@ -1007,10 +1028,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) +@@ -1001,10 +1022,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) for_each_set_bit(offset, &events, 32) bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); @@ -521,7 +626,7 @@ index 4a7f6315..10625ce 100644 len = strlen(dev_name(pc->dev)) + 16; name = devm_kzalloc(pc->dev, len, GFP_KERNEL); -@@ -1068,6 +1094,7 @@ static struct platform_driver bcm2835_pinctrl_driver = { +@@ -1062,6 +1088,7 @@ static struct platform_driver bcm2835_pinctrl_driver = { .remove = bcm2835_pinctrl_remove, .driver = { .name = MODULE_NAME, @@ -533,10 +638,10 @@ index 4a7f6315..10625ce 100644 2.5.0 -From ca4182f2ae329463426e9de88bbc0a3613f58f40 Mon Sep 17 00:00:00 2001 +From b02654723367da6ef4be37fc63aadde1d273337a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 26 Feb 2015 09:58:22 +0000 -Subject: [PATCH 10/55] pinctrl-bcm2835: Only request the interrupts listed in +Subject: [PATCH 11/54] pinctrl-bcm2835: Only request the interrupts listed in the DTB Although the GPIO controller can generate three interrupts (four counting @@ -550,10 +655,10 @@ interface, is unlikely to be a problem. 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index 10625ce..97e125a8 100644 +index ab345f4..640e3b0 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -1035,6 +1035,8 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) +@@ -1029,6 +1029,8 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) int len; char *name; pc->irq[i] = irq_of_parse_and_map(np, i); @@ -566,10 +671,10 @@ index 10625ce..97e125a8 100644 2.5.0 -From 1389162c26fd006dc89b63fa74cf07dc16e771d6 Mon Sep 17 00:00:00 2001 +From c28b4b938880483817ec763cc8cea8b1b3fa7713 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 24 Jun 2015 14:10:44 +0100 -Subject: [PATCH 11/55] spi-bcm2835: Support pin groups other than 7-11 +Subject: [PATCH 12/54] spi-bcm2835: Support pin groups other than 7-11 The spi-bcm2835 driver automatically uses GPIO chip-selects due to some unreliability of the native ones. In doing so it chooses the @@ -653,10 +758,10 @@ index cf04960..a2b1f45 100644 2.5.0 -From b70072e95258dad4dbdf663681b5b74fa186b8a7 Mon Sep 17 00:00:00 2001 +From 1cb2f8fda15ef921c9d1f51e010ac0073bd54a57 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Wed, 3 Jun 2015 12:26:13 +0200 -Subject: [PATCH 12/55] ARM: bcm2835: Set Serial number and Revision +Subject: [PATCH 13/54] ARM: bcm2835: Set Serial number and Revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -717,10 +822,10 @@ index 0f7b9ea..1e6f1cf 100644 2.5.0 -From 58a50cd6c0dd037b3cb0eec22bd1096af96d11f2 Mon Sep 17 00:00:00 2001 +From 43a75f20eb793a2c528280faab8248b226fe38de Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 16:44:05 +0200 -Subject: [PATCH 13/55] bcm2835-i2s: get base address for DMA from devicetree +Subject: [PATCH 14/54] bcm2835-i2s: get base address for DMA from devicetree Code copied from spi-bcm2835. Get physical address from devicetree instead of using hardcoded constant. @@ -788,10 +893,10 @@ index 8c435be..0bc4f47 100644 2.5.0 -From 64bdc1411fa7ae16f36d54a97e4777f8c04c0b26 Mon Sep 17 00:00:00 2001 +From e68b70e6087fd6fc8466eeac8db67b3f49813058 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:21:16 +0200 -Subject: [PATCH 14/55] bcm2835-i2s: add 24bit support, update bclk_ratio to +Subject: [PATCH 15/54] bcm2835-i2s: add 24bit support, update bclk_ratio to more correct values Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -873,10 +978,10 @@ index 0bc4f47..cf60390 100644 2.5.0 -From caf2b024219e3326d432dcac9f95a8c1aa245a60 Mon Sep 17 00:00:00 2001 +From 18ecb409ca4b62265dc8638c4feddc74b169e757 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:25:51 +0200 -Subject: [PATCH 15/55] bcm2835-i2s: setup clock only if CPU is clock master +Subject: [PATCH 16/54] bcm2835-i2s: setup clock only if CPU is clock master Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -934,10 +1039,10 @@ index cf60390..4ac4e92 100644 2.5.0 -From 928181e301f07af78d32d50f3c3c88d32208b423 Mon Sep 17 00:00:00 2001 +From 34be3cc516c8e1bc9543bb1b1472b916cde0e3d4 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:49:51 +0200 -Subject: [PATCH 16/55] bcm2835-i2s: Eliminate debugfs directory error +Subject: [PATCH 17/54] bcm2835-i2s: Eliminate debugfs directory error Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -976,10 +1081,10 @@ index 4ac4e92..aab3df9 100644 2.5.0 -From afa82a1e4ba2da951a12855af00f3fbd7215fe3e Mon Sep 17 00:00:00 2001 +From 3b910b1bea6daf50ce4a22298d4512178d109fe7 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:35:20 +0200 -Subject: [PATCH 17/55] bcm2835-i2s: Register PCM device +Subject: [PATCH 18/54] bcm2835-i2s: Register PCM device Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -1045,10 +1150,10 @@ index aab3df9..0e5c787 100644 2.5.0 -From aa5cae200e02a2776d8b82df5cd60f0b1ee738be Mon Sep 17 00:00:00 2001 +From cb2f46fb84024303f11a9da1f949e0092222b537 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 15:55:21 +0200 -Subject: [PATCH 18/55] bcm2835-i2s: Enable MMAP support via a DT property +Subject: [PATCH 19/54] bcm2835-i2s: Enable MMAP support via a DT property Code ported from bcm2708-i2s driver in Raspberry Pi tree. @@ -1095,218 +1200,10 @@ index 0e5c787..04c1d13 100644 2.5.0 -From 99466dd3a723108c9d475a6ca8bd6cf30a4a722b Mon Sep 17 00:00:00 2001 -From: Peter Ujfalusi -Date: Mon, 16 Nov 2015 12:38:46 +0000 -Subject: [PATCH 19/55] [PATCH] dmaengine: bcm2835-dma: Convert to use DMA pool - -f93178291712 dmaengine: bcm2835-dma: Fix memory leak when stopping a - running transfer - -Fixed the memleak, but introduced another issue: the terminate_all callback -might be called with interrupts disabled and the dma_free_coherent() is -not allowed to be called when IRQs are disabled. -Convert the driver to use dma_pool_* for managing the list of control -blocks for the transfer. - -Fixes: f93178291712 ("dmaengine: bcm2835-dma: Fix memory leak when stopping a running transfer") -Signed-off-by: Peter Ujfalusi ---- - drivers/dma/bcm2835-dma.c | 78 ++++++++++++++++++++++++++++++++--------------- - 1 file changed, 54 insertions(+), 24 deletions(-) - -diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index c92d6a7..996c4b0 100644 ---- a/drivers/dma/bcm2835-dma.c -+++ b/drivers/dma/bcm2835-dma.c -@@ -31,6 +31,7 @@ - */ - #include - #include -+#include - #include - #include - #include -@@ -62,6 +63,11 @@ struct bcm2835_dma_cb { - uint32_t pad[2]; - }; - -+struct bcm2835_cb_entry { -+ struct bcm2835_dma_cb *cb; -+ dma_addr_t paddr; -+}; -+ - struct bcm2835_chan { - struct virt_dma_chan vc; - struct list_head node; -@@ -72,18 +78,18 @@ struct bcm2835_chan { - - int ch; - struct bcm2835_desc *desc; -+ struct dma_pool *cb_pool; - - void __iomem *chan_base; - int irq_number; - }; - - struct bcm2835_desc { -+ struct bcm2835_chan *c; - struct virt_dma_desc vd; - enum dma_transfer_direction dir; - -- unsigned int control_block_size; -- struct bcm2835_dma_cb *control_block_base; -- dma_addr_t control_block_base_phys; -+ struct bcm2835_cb_entry *cb_list; - - unsigned int frames; - size_t size; -@@ -143,10 +149,13 @@ static inline struct bcm2835_desc *to_bcm2835_dma_desc( - static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) - { - struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); -- dma_free_coherent(desc->vd.tx.chan->device->dev, -- desc->control_block_size, -- desc->control_block_base, -- desc->control_block_base_phys); -+ int i; -+ -+ for (i = 0; i < desc->frames; i++) -+ dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb, -+ desc->cb_list[i].paddr); -+ -+ kfree(desc->cb_list); - kfree(desc); - } - -@@ -199,7 +208,7 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan *c) - - c->desc = d = to_bcm2835_dma_desc(&vd->tx); - -- writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR); -+ writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); - writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); - } - -@@ -232,9 +241,16 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) - static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) - { - struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ struct device *dev = c->vc.chan.device->dev; -+ -+ dev_dbg(dev, "Allocating DMA channel %d\n", c->ch); - -- dev_dbg(c->vc.chan.device->dev, -- "Allocating DMA channel %d\n", c->ch); -+ c->cb_pool = dma_pool_create(dev_name(dev), dev, -+ sizeof(struct bcm2835_dma_cb), 0, 0); -+ if (!c->cb_pool) { -+ dev_err(dev, "unable to allocate descriptor pool\n"); -+ return -ENOMEM; -+ } - - return request_irq(c->irq_number, - bcm2835_dma_callback, 0, "DMA IRQ", c); -@@ -246,6 +262,7 @@ static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) - - vchan_free_chan_resources(&c->vc); - free_irq(c->irq_number, c); -+ dma_pool_destroy(c->cb_pool); - - dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); - } -@@ -261,8 +278,7 @@ static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) - size_t size; - - for (size = i = 0; i < d->frames; i++) { -- struct bcm2835_dma_cb *control_block = -- &d->control_block_base[i]; -+ struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; - size_t this_size = control_block->length; - dma_addr_t dma; - -@@ -343,6 +359,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( - dma_addr_t dev_addr; - unsigned int es, sync_type; - unsigned int frame; -+ int i; - - /* Grab configuration */ - if (!is_slave_direction(direction)) { -@@ -374,27 +391,31 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( - if (!d) - return NULL; - -+ d->c = c; - d->dir = direction; - d->frames = buf_len / period_len; - -- /* Allocate memory for control blocks */ -- d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); -- d->control_block_base = dma_zalloc_coherent(chan->device->dev, -- d->control_block_size, &d->control_block_base_phys, -- GFP_NOWAIT); -- -- if (!d->control_block_base) { -+ d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL); -+ if (!d->cb_list) { - kfree(d); - return NULL; - } -+ /* Allocate memory for control blocks */ -+ for (i = 0; i < d->frames; i++) { -+ struct bcm2835_cb_entry *cb_entry = &d->cb_list[i]; -+ -+ cb_entry->cb = dma_pool_zalloc(c->cb_pool, GFP_ATOMIC, -+ &cb_entry->paddr); -+ if (!cb_entry->cb) -+ goto error_cb; -+ } - - /* - * Iterate over all frames, create a control block - * for each frame and link them together. - */ - for (frame = 0; frame < d->frames; frame++) { -- struct bcm2835_dma_cb *control_block = -- &d->control_block_base[frame]; -+ struct bcm2835_dma_cb *control_block = d->cb_list[frame].cb; - - /* Setup adresses */ - if (d->dir == DMA_DEV_TO_MEM) { -@@ -428,12 +449,21 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( - * This DMA engine driver currently only supports cyclic DMA. - * Therefore, wrap around at number of frames. - */ -- control_block->next = d->control_block_base_phys + -- sizeof(struct bcm2835_dma_cb) -- * ((frame + 1) % d->frames); -+ control_block->next = d->cb_list[((frame + 1) % d->frames)].paddr; - } - - return vchan_tx_prep(&c->vc, &d->vd, flags); -+error_cb: -+ i--; -+ for (; i >= 0; i--) { -+ struct bcm2835_cb_entry *cb_entry = &d->cb_list[i]; -+ -+ dma_pool_free(c->cb_pool, cb_entry->cb, cb_entry->paddr); -+ } -+ -+ kfree(d->cb_list); -+ kfree(d); -+ return NULL; - } - - static int bcm2835_dma_slave_config(struct dma_chan *chan, --- -2.5.0 - - -From c776a0f35105e2f6416db20f49bd6eef9897b7f2 Mon Sep 17 00:00:00 2001 +From 5d8da2ced7537ced468f4ec0da0392d31ec59402 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Thu, 9 Apr 2015 12:34:11 +0200 -Subject: [PATCH 20/55] dmaengine: bcm2835: Add slave dma support +Subject: [PATCH 20/54] dmaengine: bcm2835: Add slave dma support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -1629,10 +1526,10 @@ index 996c4b0..b278c66 100644 2.5.0 -From 0e9c1fce5ce00aa74687238e866aa39693087e68 Mon Sep 17 00:00:00 2001 +From 47c823519828f01517803ca5507ce9f942ffa4a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 3 Oct 2015 15:58:59 +0200 -Subject: [PATCH 21/55] dmaengine: bcm2835: set residue_granularity field +Subject: [PATCH 21/54] dmaengine: bcm2835: set residue_granularity field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -1664,10 +1561,10 @@ index b278c66..696fb30 100644 2.5.0 -From 7835fbd12618a35dd44ff0bb473242a624765db7 Mon Sep 17 00:00:00 2001 +From 8ed5d9cb36862e28d36b17c509321c7496c499b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 3 Oct 2015 22:22:55 +0200 -Subject: [PATCH 22/55] dmaengine: bcm2835: Load driver early and support +Subject: [PATCH 22/54] dmaengine: bcm2835: Load driver early and support legacy API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -1770,72 +1667,10 @@ index 696fb30..5db0a95 100644 2.5.0 -From f02f5b8d103f39629e5e27c11c8616614e1bba7f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= -Date: Sat, 3 Oct 2015 22:44:36 +0200 -Subject: [PATCH 23/55] dmaengine: bcm2835: Add debug option for setting wait - states -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -[by popcornmix, taken from bcm2708-dmaengine] -Signed-off-by: Noralf Trønnes ---- - drivers/dma/bcm2835-dma.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - -diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 5db0a95..8412433 100644 ---- a/drivers/dma/bcm2835-dma.c -+++ b/drivers/dma/bcm2835-dma.c -@@ -46,6 +46,9 @@ - - #include "virt-dma.h" - -+static unsigned dma_debug; -+module_param(dma_debug, uint, 0644); -+ - struct bcm2835_dmadev { - struct dma_device ddev; - spinlock_t lock; -@@ -571,6 +574,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, - unsigned int len = sg_dma_len(sgent); - - for (j = 0; j < len; j += max_size) { -+ u32 waits; - struct bcm2835_dma_cb *control_block = - &d->control_block_base[i + split_cnt]; - -@@ -590,8 +594,10 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, - } - - /* Common part */ -- control_block->info |= -- BCM2835_DMA_WAITS(BCM2835_DMA_WAIT_CYCLES); -+ waits = BCM2835_DMA_WAIT_CYCLES; -+ if ((dma_debug >> 0) & 0x1f) -+ waits = (dma_debug >> 0) & 0x1f; -+ control_block->info |= BCM2835_DMA_WAITS(waits); - control_block->info |= BCM2835_DMA_WAIT_RESP; - - /* Enable */ -@@ -856,6 +862,7 @@ static int bcm2835_dma_probe(struct platform_device *pdev) - } - - dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n"); -+ dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug); - - return 0; - --- -2.5.0 - - -From b12e830e429106a3457cf285c7071dfb51096e87 Mon Sep 17 00:00:00 2001 +From cc8e848852566125466b1c7f8969193b3bd09952 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sat, 10 Oct 2015 12:29:18 +0200 -Subject: [PATCH 24/55] bcm2835-dma: Fix dreq not set for slave transfers +Subject: [PATCH 23/54] bcm2835-dma: Fix dreq not set for slave transfers Set dreq to slave_id if it is not set like in bcm2708-dmaengine. --- @@ -1843,10 +1678,10 @@ Set dreq to slave_id if it is not set like in bcm2708-dmaengine. 1 file changed, 2 insertions(+) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 8412433..93e714c 100644 +index 5db0a95..fe1fd60 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c -@@ -663,6 +663,8 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan, +@@ -657,6 +657,8 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan, } c->cfg = *cfg; @@ -1859,10 +1694,10 @@ index 8412433..93e714c 100644 2.5.0 -From b59b3cb4d1cbe396d439f76abfcfbee786fcce97 Mon Sep 17 00:00:00 2001 +From b4b8964bdad3f33abb3b688832b326372c4e1d41 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Sun, 11 Oct 2015 12:28:30 +0200 -Subject: [PATCH 25/55] bcm2835-dma: Limit cyclic transfers on lite channels to +Subject: [PATCH 24/54] bcm2835-dma: Limit cyclic transfers on lite channels to 32k Transfers larger than 32k cause repeated clicking with I2S soundcards. @@ -1873,10 +1708,10 @@ did as an intermediate fix. 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 93e714c..58a96a6 100644 +index fe1fd60..0adc347 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c -@@ -147,6 +147,12 @@ struct bcm2835_desc { +@@ -144,6 +144,12 @@ struct bcm2835_desc { */ #define MAX_LITE_TRANSFER (SZ_64K - 4) @@ -1889,7 +1724,7 @@ index 93e714c..58a96a6 100644 static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) { return container_of(d, struct bcm2835_dmadev, ddev); -@@ -415,7 +421,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -412,7 +418,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( d->c = c; d->dir = direction; if (c->ch >= 8) /* LITE channel */ @@ -1902,10 +1737,10 @@ index 93e714c..58a96a6 100644 2.5.0 -From 72edadcf811bb74122d571ec30b34c77d2d7b340 Mon Sep 17 00:00:00 2001 +From 94acbda110b4bed72b2799550c86aa628abebf02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 15 Aug 2015 20:50:02 +0200 -Subject: [PATCH 26/55] bcm2835: Add support for uart1 +Subject: [PATCH 25/54] bcm2835: Add support for uart1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -1965,10 +1800,10 @@ index 1e6f1cf..ea36eec 100644 2.5.0 -From 3349bfdbc95e58489239a69c5812f8b8903a3dcb Mon Sep 17 00:00:00 2001 +From 1646baa74c32dc7efe9f1cdc9a38cf55b771cfdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 26 Jun 2015 14:21:20 +0200 -Subject: [PATCH 27/55] firmware: bcm2835: Add missing property tags +Subject: [PATCH 26/54] firmware: bcm2835: Add missing property tags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -2033,10 +1868,10 @@ index c07d74a..525816d 100644 2.5.0 -From 97d3ddd0feb169151fc34cef91b0e8b6c88621c4 Mon Sep 17 00:00:00 2001 +From 831c4f4aa0247bf72b21cd38787890fd50cbf766 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 12 May 2013 12:24:19 +0100 -Subject: [PATCH 28/55] Main bcm2708/bcm2709 linux port +Subject: [PATCH 27/54] Main bcm2708/bcm2709 linux port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -2044,49 +1879,44 @@ Content-Transfer-Encoding: 8bit Signed-off-by: popcornmix Signed-off-by: Noralf Trønnes --- - arch/arm/Kconfig | 46 ++ + arch/arm/Kconfig | 49 +++ arch/arm/Kconfig.debug | 8 + arch/arm/Makefile | 2 + arch/arm/kernel/head.S | 8 + arch/arm/kernel/process.c | 10 + - arch/arm/mach-bcm2708/Kconfig | 23 + + arch/arm/mach-bcm2708/Kconfig | 23 ++ arch/arm/mach-bcm2708/Makefile | 5 + arch/arm/mach-bcm2708/Makefile.boot | 3 + - arch/arm/mach-bcm2708/bcm2708.c | 231 ++++++++++ - arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 + + arch/arm/mach-bcm2708/bcm2708.c | 231 ++++++++++++ + arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 ++ arch/arm/mach-bcm2708/include/mach/io.h | 27 ++ arch/arm/mach-bcm2708/include/mach/memory.h | 57 +++ - arch/arm/mach-bcm2708/include/mach/platform.h | 112 +++++ + arch/arm/mach-bcm2708/include/mach/platform.h | 112 ++++++ arch/arm/mach-bcm2708/include/mach/system.h | 37 ++ - arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 ++++ - arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 + + arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++++ + arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 ++ arch/arm/mach-bcm2709/Kconfig | 16 + arch/arm/mach-bcm2709/Makefile | 5 + arch/arm/mach-bcm2709/Makefile.boot | 3 + - arch/arm/mach-bcm2709/armctrl.c | 361 +++++++++++++++ - arch/arm/mach-bcm2709/armctrl.h | 27 ++ - arch/arm/mach-bcm2709/bcm2709.c | 539 +++++++++++++++++++++++ - arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 +++++++++++++++++++++ - arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 + - arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 ++++++ - arch/arm/mach-bcm2709/include/mach/hardware.h | 28 ++ + arch/arm/mach-bcm2709/bcm2709.c | 380 ++++++++++++++++++++ + arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 ++ + arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 +++++++ arch/arm/mach-bcm2709/include/mach/io.h | 27 ++ - arch/arm/mach-bcm2709/include/mach/irqs.h | 225 ++++++++++ arch/arm/mach-bcm2709/include/mach/memory.h | 57 +++ - arch/arm/mach-bcm2709/include/mach/platform.h | 225 ++++++++++ - arch/arm/mach-bcm2709/include/mach/system.h | 38 ++ - arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 ++++ + arch/arm/mach-bcm2709/include/mach/platform.h | 188 ++++++++++ + arch/arm/mach-bcm2709/include/mach/system.h | 37 ++ + arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 +++++ arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 ++ - arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 + - arch/arm/mach-bcm2709/vc_mem.c | 431 ++++++++++++++++++ + arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 ++ + arch/arm/mach-bcm2709/vc_mem.c | 431 +++++++++++++++++++++++ arch/arm/mm/Kconfig | 2 +- arch/arm/mm/proc-v6.S | 15 +- arch/arm/mm/proc-v7.S | 1 + arch/arm/tools/mach-types | 2 + drivers/clocksource/Makefile | 2 +- - drivers/irqchip/Makefile | 1 + + drivers/irqchip/Makefile | 3 + include/linux/mmc/host.h | 1 + - 42 files changed, 3473 insertions(+), 5 deletions(-) + 37 files changed, 2147 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-bcm2708/Kconfig create mode 100644 arch/arm/mach-bcm2708/Makefile create mode 100644 arch/arm/mach-bcm2708/Makefile.boot @@ -2101,15 +1931,10 @@ Signed-off-by: Noralf Trønnes create mode 100644 arch/arm/mach-bcm2709/Kconfig create mode 100644 arch/arm/mach-bcm2709/Makefile create mode 100644 arch/arm/mach-bcm2709/Makefile.boot - create mode 100644 arch/arm/mach-bcm2709/armctrl.c - create mode 100644 arch/arm/mach-bcm2709/armctrl.h create mode 100644 arch/arm/mach-bcm2709/bcm2709.c - create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S - create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h @@ -2119,10 +1944,10 @@ Signed-off-by: Noralf Trønnes create mode 100644 arch/arm/mach-bcm2709/vc_mem.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 34e1569..3241611 100644 +index 34e1569..8f06ea8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -317,6 +317,49 @@ choice +@@ -317,6 +317,52 @@ choice default ARCH_VERSATILE if !MMU default ARCH_MULTIPLATFORM if MMU @@ -2160,6 +1985,9 @@ index 34e1569..3241611 100644 + select ARCH_HAS_CPUFREQ + select GENERIC_CLOCKEVENTS + select MACH_BCM2709 ++ select MULTI_IRQ_HANDLER ++ select SPARSE_IRQ ++ select MFD_SYSCON + select VC4 + select FIQ + select USE_OF @@ -2172,7 +2000,7 @@ index 34e1569..3241611 100644 config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" depends on MMU -@@ -808,6 +851,9 @@ config ARCH_VIRT +@@ -808,6 +854,9 @@ config ARCH_VIRT # Kconfigs may be included either alphabetically (according to the # plat- suffix) or along side the corresponding mach-* source. # @@ -2234,7 +2062,7 @@ index 04286fd..ed82628 100644 ENDPROC(__fixup_a_pv_table) diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c -index 7a7c4ce..7dd2e4c 100644 +index 4adfb46..69aad0e 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -91,6 +91,16 @@ void arch_cpu_idle_exit(void) @@ -2965,7 +2793,7 @@ index 0000000..643b4b9 +endmenu diff --git a/arch/arm/mach-bcm2709/Makefile b/arch/arm/mach-bcm2709/Makefile new file mode 100644 -index 0000000..11ad846 +index 0000000..26cd67d --- /dev/null +++ b/arch/arm/mach-bcm2709/Makefile @@ -0,0 +1,5 @@ @@ -2973,7 +2801,7 @@ index 0000000..11ad846 +# Makefile for the linux kernel. +# + -+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o ++obj-$(CONFIG_MACH_BCM2709) += bcm2709.o diff --git a/arch/arm/mach-bcm2709/Makefile.boot b/arch/arm/mach-bcm2709/Makefile.boot new file mode 100644 index 0000000..67039c3 @@ -2983,412 +2811,12 @@ index 0000000..67039c3 + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -new file mode 100644 -index 0000000..813008a ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -0,0 +1,361 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "armctrl.h" -+ -+/* For support of kernels >= 3.0 assume only one VIC for now*/ -+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -+ INTERRUPT_VC_JPEG, -+ INTERRUPT_VC_USB, -+ INTERRUPT_VC_3D, -+ INTERRUPT_VC_DMA2, -+ INTERRUPT_VC_DMA3, -+ INTERRUPT_VC_I2C, -+ INTERRUPT_VC_SPI, -+ INTERRUPT_VC_I2SPCM, -+ INTERRUPT_VC_SDIO, -+ INTERRUPT_VC_UART, -+ INTERRUPT_VC_ARASANSDIO -+}; -+ -+static void armctrl_mask_irq(struct irq_data *d) -+{ -+ static const unsigned int disables[4] = { -+ ARM_IRQ_DIBL1, -+ ARM_IRQ_DIBL2, -+ ARM_IRQ_DIBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ writel(0, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); // -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+static void armctrl_unmask_irq(struct irq_data *d) -+{ -+ static const unsigned int enables[4] = { -+ ARM_IRQ_ENBL1, -+ ARM_IRQ_ENBL2, -+ ARM_IRQ_ENBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+#ifdef CONFIG_OF -+ -+#define NR_IRQS_BANK0 21 -+#define NR_BANKS 4 -+#define IRQS_PER_BANK 32 -+ -+/* from drivers/irqchip/irq-bcm2835.c */ -+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -+ const u32 *intspec, unsigned int intsize, -+ unsigned long *out_hwirq, unsigned int *out_type) -+{ -+ if (WARN_ON(intsize != 2)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] >= NR_BANKS)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) -+ return -EINVAL; -+ -+ if (intspec[0] == 0) -+ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -+ else if (intspec[0] == 1) -+ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -+ else if (intspec[0] == 2) -+ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -+ else -+ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; -+ -+ /* reverse remap_irqs[] */ -+ switch (*out_hwirq) { -+ case INTERRUPT_VC_JPEG: -+ *out_hwirq = INTERRUPT_JPEG; -+ break; -+ case INTERRUPT_VC_USB: -+ *out_hwirq = INTERRUPT_USB; -+ break; -+ case INTERRUPT_VC_3D: -+ *out_hwirq = INTERRUPT_3D; -+ break; -+ case INTERRUPT_VC_DMA2: -+ *out_hwirq = INTERRUPT_DMA2; -+ break; -+ case INTERRUPT_VC_DMA3: -+ *out_hwirq = INTERRUPT_DMA3; -+ break; -+ case INTERRUPT_VC_I2C: -+ *out_hwirq = INTERRUPT_I2C; -+ break; -+ case INTERRUPT_VC_SPI: -+ *out_hwirq = INTERRUPT_SPI; -+ break; -+ case INTERRUPT_VC_I2SPCM: -+ *out_hwirq = INTERRUPT_I2SPCM; -+ break; -+ case INTERRUPT_VC_SDIO: -+ *out_hwirq = INTERRUPT_SDIO; -+ break; -+ case INTERRUPT_VC_UART: -+ *out_hwirq = INTERRUPT_UART; -+ break; -+ case INTERRUPT_VC_ARASANSDIO: -+ *out_hwirq = INTERRUPT_ARASANSDIO; -+ break; -+ } -+ -+ *out_type = IRQ_TYPE_NONE; -+ return 0; -+} -+ -+static struct irq_domain_ops armctrl_ops = { -+ .xlate = armctrl_xlate -+}; -+ -+void __init armctrl_dt_init(void) -+{ -+ struct device_node *np; -+ struct irq_domain *domain; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -+ if (!np) -+ return; -+ -+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -+ IRQ_ARMCTRL_START, 0, -+ &armctrl_ops, NULL); -+ WARN_ON(!domain); -+} -+#else -+void __init armctrl_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+#if defined(CONFIG_PM) -+ -+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -+ -+/* Static defines -+ * struct armctrl_device - VIC PM device (< 3.xx) -+ * @sysdev: The system device which is registered. (< 3.xx) -+ * @irq: The IRQ number for the base of the VIC. -+ * @base: The register base for the VIC. -+ * @resume_sources: A bitmask of interrupts for resume. -+ * @resume_irqs: The IRQs enabled for resume. -+ * @int_select: Save for VIC_INT_SELECT. -+ * @int_enable: Save for VIC_INT_ENABLE. -+ * @soft_int: Save for VIC_INT_SOFT. -+ * @protect: Save for VIC_PROTECT. -+ */ -+struct armctrl_info { -+ void __iomem *base; -+ int irq; -+ u32 resume_sources; -+ u32 resume_irqs; -+ u32 int_select; -+ u32 int_enable; -+ u32 soft_int; -+ u32 protect; -+} armctrl; -+ -+static int armctrl_suspend(void) -+{ -+ return 0; -+} -+ -+static void armctrl_resume(void) -+{ -+ return; -+} -+ -+/** -+ * armctrl_pm_register - Register a VIC for later power management control -+ * @base: The base address of the VIC. -+ * @irq: The base IRQ for the VIC. -+ * @resume_sources: bitmask of interrupts allowed for resume sources. -+ * -+ * For older kernels (< 3.xx) do - -+ * Register the VIC with the system device tree so that it can be notified -+ * of suspend and resume requests and ensure that the correct actions are -+ * taken to re-instate the settings on resume. -+ */ -+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 resume_sources) -+{ -+ armctrl.base = base; -+ armctrl.resume_sources = resume_sources; -+ armctrl.irq = irq; -+} -+ -+static int armctrl_set_wake(struct irq_data *d, unsigned int on) -+{ -+ unsigned int off = d->irq & 31; -+ u32 bit = 1 << off; -+ -+ if (!(bit & armctrl.resume_sources)) -+ return -EINVAL; -+ -+ if (on) -+ armctrl.resume_irqs |= bit; -+ else -+ armctrl.resume_irqs &= ~bit; -+ -+ return 0; -+} -+ -+#else -+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 arg1) -+{ -+} -+ -+#define armctrl_suspend NULL -+#define armctrl_resume NULL -+#define armctrl_set_wake NULL -+#endif /* CONFIG_PM */ -+ -+static struct syscore_ops armctrl_syscore_ops = { -+ .suspend = armctrl_suspend, -+ .resume = armctrl_resume, -+}; -+ -+/** -+ * armctrl_syscore_init - initicall to register VIC pm functions -+ * -+ * This is called via late_initcall() to register -+ * the resources for the VICs due to the early -+ * nature of the VIC's registration. -+*/ -+static int __init armctrl_syscore_init(void) -+{ -+ register_syscore_ops(&armctrl_syscore_ops); -+ return 0; -+} -+ -+late_initcall(armctrl_syscore_init); -+ -+static struct irq_chip armctrl_chip = { -+ .name = "ARMCTRL", -+ .irq_ack = NULL, -+ .irq_mask = armctrl_mask_irq, -+ .irq_unmask = armctrl_unmask_irq, -+ .irq_set_wake = armctrl_set_wake, -+}; -+ -+/** -+ * armctrl_init - initialise a vectored interrupt controller -+ * @base: iomem base address -+ * @irq_start: starting interrupt number, must be muliple of 32 -+ * @armctrl_sources: bitmask of interrupt sources to allow -+ * @resume_sources: bitmask of interrupt sources to allow for resume -+ */ -+int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources) -+{ -+ unsigned int irq; -+ -+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -+ unsigned int data = irq; -+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -+ data = remap_irqs[irq - INTERRUPT_JPEG]; -+ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { -+ irq_set_percpu_devid(irq); -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ } else { -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); -+ irq_set_probe(irq); -+ } -+ irq_set_chip_data(irq, (void *)data); -+ } -+ -+ armctrl_pm_register(base, irq_start, resume_sources); -+ init_FIQ(FIQ_START); -+ armctrl_dt_init(); -+ return 0; -+} -diff --git a/arch/arm/mach-bcm2709/armctrl.h b/arch/arm/mach-bcm2709/armctrl.h -new file mode 100644 -index 0000000..0aa916e ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.h -@@ -0,0 +1,27 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARMCTRL_H -+#define __BCM2708_ARMCTRL_H -+ -+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources); -+ -+#endif diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c new file mode 100644 -index 0000000..3eeeb886 +index 0000000..90773a3 --- /dev/null +++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -0,0 +1,539 @@ +@@ -0,0 +1,380 @@ +/* + * linux/arch/arm/mach-bcm2709/bcm2709.c + * @@ -3419,20 +2847,16 @@ index 0000000..3eeeb886 +#include + +#include -+#include +#include +#include + +#include +#include ++ +#include + -+#include "armctrl.h" -+ +#include + -+//#define SYSTEM_TIMER -+ +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to + * give us IO access only to 64Mbytes of physical memory (26 bits). We could + * represent this window by setting our dmamasks to 26 bits but, in fact @@ -3448,11 +2872,6 @@ index 0000000..3eeeb886 +static unsigned boardrev, serial; +static unsigned reboot_part = 0; + -+void __init bcm2709_init_irq(void) -+{ -+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); -+} -+ +static struct map_desc bcm2709_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(ARMCTRL_BASE), @@ -3511,54 +2930,6 @@ index 0000000..3eeeb886 + iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); +} + -+#ifdef SYSTEM_TIMER -+ -+/* The STC is a free running counter that increments at the rate of 1MHz */ -+#define STC_FREQ_HZ 1000000 -+ -+static inline uint32_t timer_read(void) -+{ -+ /* STC: a free running counter that increments at the rate of 1MHz */ -+ return readl(__io_address(ST_BASE + 0x04)); -+} -+ -+static unsigned long bcm2709_read_current_timer(void) -+{ -+ return timer_read(); -+} -+ -+static u64 notrace bcm2709_read_sched_clock(void) -+{ -+ return timer_read(); -+} -+ -+static cycle_t clksrc_read(struct clocksource *cs) -+{ -+ return timer_read(); -+} -+ -+static struct clocksource clocksource_stc = { -+ .name = "stc", -+ .rating = 300, -+ .read = clksrc_read, -+ .mask = CLOCKSOURCE_MASK(32), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+unsigned long frc_clock_ticks32(void) -+{ -+ return timer_read(); -+} -+ -+static void __init bcm2709_clocksource_init(void) -+{ -+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -+ printk(KERN_ERR "timer: failed to initialize clock " -+ "source %s\n", clocksource_stc.name); -+ } -+} -+#endif -+ +int calc_rsts(int partition) +{ + return PM_PASSWORD | @@ -3643,7 +3014,8 @@ index 0000000..3eeeb886 + + pm_power_off = bcm2709_power_off; + -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, ++ NULL); + if (ret) { + pr_err("of_platform_populate failed: %d\n", ret); + BUG(); @@ -3655,105 +3027,6 @@ index 0000000..3eeeb886 + system_serial_low = serial; +} + -+#ifdef SYSTEM_TIMER -+static void timer_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *clk) -+{ -+ switch (mode) { -+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ break; -+ case CLOCK_EVT_MODE_PERIODIC: -+ -+ case CLOCK_EVT_MODE_UNUSED: -+ case CLOCK_EVT_MODE_RESUME: -+ -+ default: -+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -+ (int)mode); -+ break; -+ } -+ -+} -+ -+static int timer_set_next_event(unsigned long cycles, -+ struct clock_event_device *unused) -+{ -+ unsigned long stc; -+ do { -+ stc = readl(__io_address(ST_BASE + 0x04)); -+ /* We could take a FIQ here, which may push ST above STC3 */ -+ writel(stc + cycles, __io_address(ST_BASE + 0x18)); -+ } while ((signed long) cycles >= 0 && -+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -+ >= (signed long) cycles); -+ return 0; -+} -+ -+static struct clock_event_device timer0_clockevent = { -+ .name = "timer0", -+ .shift = 32, -+ .features = CLOCK_EVT_FEAT_ONESHOT, -+ .set_mode = timer_set_mode, -+ .set_next_event = timer_set_next_event, -+}; -+ -+/* -+ * IRQ handler for the timer -+ */ -+static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) -+{ -+ struct clock_event_device *evt = &timer0_clockevent; -+ -+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -+ -+ evt->event_handler(evt); -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction bcm2709_timer_irq = { -+ .name = "BCM2709 Timer Tick", -+ .flags = IRQF_TIMER | IRQF_IRQPOLL, -+ .handler = bcm2709_timer_interrupt, -+}; -+ -+/* -+ * Set up timer interrupt, and return the current time in seconds. -+ */ -+ -+static struct delay_timer bcm2709_delay_timer = { -+ .read_current_timer = bcm2709_read_current_timer, -+ .freq = STC_FREQ_HZ, -+}; -+ -+static void __init bcm2709_timer_init(void) -+{ -+ /* init high res timer */ -+ bcm2709_clocksource_init(); -+ -+ /* -+ * Make irqs happen for the system timer -+ */ -+ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); -+ -+ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); -+ -+ timer0_clockevent.mult = -+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -+ timer0_clockevent.max_delta_ns = -+ clockevent_delta2ns(0xffffffff, &timer0_clockevent); -+ timer0_clockevent.min_delta_ns = -+ clockevent_delta2ns(0xf, &timer0_clockevent); -+ -+ timer0_clockevent.cpumask = cpumask_of(0); -+ clockevents_register_device(&timer0_clockevent); -+ -+ register_current_timer_delay(&bcm2709_delay_timer); -+} -+ -+#else -+ +static void __init bcm2709_timer_init(void) +{ + // timer control @@ -3766,7 +3039,6 @@ index 0000000..3eeeb886 + clocksource_probe(); +} + -+#endif + +void __init bcm2709_init_early(void) +{ @@ -3787,7 +3059,6 @@ index 0000000..3eeeb886 +#ifdef CONFIG_SMP +#include + -+#include +#include +#include +int dc4=0; @@ -3901,7 +3172,6 @@ index 0000000..3eeeb886 + .smp = smp_ops(bcm2709_smp_ops), +#endif + .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, + .init_time = bcm2709_timer_init, + .init_machine = bcm2709_init, + .init_early = bcm2709_init_early, @@ -3916,7 +3186,6 @@ index 0000000..3eeeb886 + .smp = smp_ops(bcm2709_smp_ops), +#endif + .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, + .init_time = bcm2709_timer_init, + .init_machine = bcm2709_init, + .init_early = bcm2709_init_early, @@ -3928,505 +3197,6 @@ index 0000000..3eeeb886 +module_param(boardrev, uint, 0644); +module_param(serial, uint, 0644); +module_param(reboot_part, uint, 0644); -diff --git a/arch/arm/mach-bcm2709/include/mach/arm_control.h b/arch/arm/mach-bcm2709/include/mach/arm_control.h -new file mode 100644 -index 0000000..e346caf ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h -@@ -0,0 +1,493 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/arm_control.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARM_CONTROL_H -+#define __BCM2708_ARM_CONTROL_H -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define ARM_BASE 0x7E00B000 -+ -+/* Basic configuration */ -+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) -+#define ARM_C0_SIZ128M 0x00000000 -+#define ARM_C0_SIZ256M 0x00000001 -+#define ARM_C0_SIZ512M 0x00000002 -+#define ARM_C0_SIZ1G 0x00000003 -+#define ARM_C0_BRESP0 0x00000000 -+#define ARM_C0_BRESP1 0x00000004 -+#define ARM_C0_BRESP2 0x00000008 -+#define ARM_C0_BOOTHI 0x00000010 -+#define ARM_C0_UNUSED05 0x00000020 /* free */ -+#define ARM_C0_FULLPERI 0x00000040 -+#define ARM_C0_UNUSED78 0x00000180 /* free */ -+#define ARM_C0_JTAGMASK 0x00000E00 -+#define ARM_C0_JTAGOFF 0x00000000 -+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ -+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ -+#define ARM_C0_APROTMSK 0x0000F000 -+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ -+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ -+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ -+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ -+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ -+#define ARM_C0_PRIO_L2 0x0F000000 -+#define ARM_C0_PRIO_UC 0xF0000000 -+ -+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ -+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ -+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -+ -+ -+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) -+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ -+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ -+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ -+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ -+#define ARM_C1_PERSON 0x00000100 /* peripherals on */ -+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -+ -+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) -+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ -+#define ARM_S_READPEND 0x000003FF /* pending reads counter */ -+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -+ -+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) -+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ -+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ -+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ -+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ -+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ -+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -+ -+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) -+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) -+#define ARM_IDVAL 0x364D5241 -+ -+/* Translation memory */ -+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) -+/* 32 locations: 0x100.. 0x17F */ -+/* 32 spare means we CAN go to 64 pages.... */ -+ -+ -+/* Interrupts */ -+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ -+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ -+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ -+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -+ -+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ -+/* todo: all I1_interrupt sources */ -+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ -+/* todo: all I2_interrupt sources */ -+ -+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ -+#define ARM_IF_INDEX 0x0000007F /* FIQ select */ -+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ -+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ -+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ -+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ -+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ -+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ -+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ -+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ -+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -+ -+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ -+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ -+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ -+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ -+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ -+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ -+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ -+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ -+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ -+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -+ -+/* Timer */ -+/* For reg. fields see sp804 spec. */ -+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) -+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) -+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) -+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) -+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) -+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) -+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) -+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) -+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -+ -+#define TIMER_CTRL_ONESHOT (1 << 0) -+#define TIMER_CTRL_32BIT (1 << 1) -+#define TIMER_CTRL_DIV1 (0 << 2) -+#define TIMER_CTRL_DIV16 (1 << 2) -+#define TIMER_CTRL_DIV256 (2 << 2) -+#define TIMER_CTRL_IE (1 << 5) -+#define TIMER_CTRL_PERIODIC (1 << 6) -+#define TIMER_CTRL_ENABLE (1 << 7) -+#define TIMER_CTRL_DBGHALT (1 << 8) -+#define TIMER_CTRL_ENAFREE (1 << 9) -+#define TIMER_CTRL_FREEDIV_SHIFT 16) -+#define TIMER_CTRL_FREEDIV_MASK 0xff -+ -+/* Semaphores, Doorbells, Mailboxes */ -+#define ARM_SBM_OWN0 (ARM_BASE+0x800) -+#define ARM_SBM_OWN1 (ARM_BASE+0x900) -+#define ARM_SBM_OWN2 (ARM_BASE+0xA00) -+#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -+ -+/* MAILBOXES -+ * Register flags are common across all -+ * owner registers. See end of this section -+ * -+ * Semaphores, Doorbells, Mailboxes Owner 0 -+ * -+ */ -+ -+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) -+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) -+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) -+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) -+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) -+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) -+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) -+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) -+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) -+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) -+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Some addresses should ONLY be used by owner 0 */ -+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ -+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ -+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ -+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ -+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ -+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ -+/* MAILBOX 1 access in Owner 0 area */ -+/* Owner 0 should only WRITE to this mailbox */ -+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ -+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ -+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ -+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ -+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 1 */ -+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) -+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) -+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) -+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) -+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) -+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) -+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) -+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) -+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) -+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) -+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Owner 1 should only WRITE to this mailbox */ -+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ -+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 0 area */ -+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ -+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ -+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ -+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ -+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ -+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ -+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ -+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ -+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 2 */ -+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) -+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) -+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) -+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) -+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) -+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) -+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) -+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) -+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) -+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) -+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) -+/* MAILBOX 0 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ -+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ -+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ -+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ -+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ -+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 3 */ -+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) -+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) -+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) -+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) -+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) -+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) -+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) -+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) -+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) -+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) -+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) -+/* MAILBOX 0 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ -+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ -+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ -+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ -+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ -+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -+ -+ -+ -+/* Mailbox flags. Valid for all owners */ -+ -+/* Mailbox status register (...0x98) */ -+#define ARM_MS_FULL 0x80000000 -+#define ARM_MS_EMPTY 0x40000000 -+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -+ -+/* MAILBOX config/status register (...0x9C) */ -+/* ANY write to this register clears the error bits! */ -+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ -+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ -+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ -+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ -+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ -+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ -+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ -+/* Bit 7 is unused */ -+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ -+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ -+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -+ -+/* Semaphore clear/debug register (...0xE0) */ -+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ -+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ -+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ -+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ -+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ -+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ -+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ -+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ -+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ -+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ -+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ -+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ -+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ -+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ -+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ -+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -+ -+/* Doorbells clear/debug register (...0xE4) */ -+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ -+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ -+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ -+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ -+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ -+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ -+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ -+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -+ -+/* MY IRQS register (...0xF8) */ -+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ -+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -+ -+/* ALL IRQS register (...0xF8) */ -+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ -+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ -+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ -+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ -+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ -+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ -+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ -+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ -+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ -+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ -+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ -+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ -+/* */ -+/* ARM JTAG BASH */ -+/* */ -+#define AJB_BASE 0x7e2000c0 -+ -+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) -+#define AJB_BITS0 0x000000 -+#define AJB_BITS4 0x000004 -+#define AJB_BITS8 0x000008 -+#define AJB_BITS12 0x00000C -+#define AJB_BITS16 0x000010 -+#define AJB_BITS20 0x000014 -+#define AJB_BITS24 0x000018 -+#define AJB_BITS28 0x00001C -+#define AJB_BITS32 0x000020 -+#define AJB_BITS34 0x000022 -+#define AJB_OUT_MS 0x000040 -+#define AJB_OUT_LS 0x000000 -+#define AJB_INV_CLK 0x000080 -+#define AJB_D0_RISE 0x000100 -+#define AJB_D0_FALL 0x000000 -+#define AJB_D1_RISE 0x000200 -+#define AJB_D1_FALL 0x000000 -+#define AJB_IN_RISE 0x000400 -+#define AJB_IN_FALL 0x000000 -+#define AJB_ENABLE 0x000800 -+#define AJB_HOLD0 0x000000 -+#define AJB_HOLD1 0x001000 -+#define AJB_HOLD2 0x002000 -+#define AJB_HOLD3 0x003000 -+#define AJB_RESETN 0x004000 -+#define AJB_CLKSHFT 16 -+#define AJB_BUSY 0x80000000 -+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) -+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) -+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -+ -+#define ARM_LOCAL_BASE 0x40000000 -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) -+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) -+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) -+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) -+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) -+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) -+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) -+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) -+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) -+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) -+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -+ -+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) -+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) -+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) -+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -+ -+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -+ -+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) -+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) -+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) -+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -+ -+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) -+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) -+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) -+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -+ -+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) -+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) -+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) -+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -+ -+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) -+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) -+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) -+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -+ -+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) -+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) -+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) -+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -+ -+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) -+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) -+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) -+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) -+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) -+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) -+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) -+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) -+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) -+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) -+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) -+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) -+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) -+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) -+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) -+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -+ -+#endif diff --git a/arch/arm/mach-bcm2709/include/mach/debug-macro.S b/arch/arm/mach-bcm2709/include/mach/debug-macro.S new file mode 100644 index 0000000..b24304a @@ -4584,40 +3354,6 @@ index 0000000..d08591b + dsb +1030: @ EQ will be set if no irqs pending + .endm -diff --git a/arch/arm/mach-bcm2709/include/mach/hardware.h b/arch/arm/mach-bcm2709/include/mach/hardware.h -new file mode 100644 -index 0000000..c2954e8 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/hardware.h -@@ -0,0 +1,28 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/hardware.h -+ * -+ * This file contains the hardware definitions of the BCM2708 devices. -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include -+#include -+ -+#endif diff --git a/arch/arm/mach-bcm2709/include/mach/io.h b/arch/arm/mach-bcm2709/include/mach/io.h new file mode 100644 index 0000000..e6eb84d @@ -4651,237 +3387,6 @@ index 0000000..e6eb84d +#define __io(a) __typesafe_io(a) + +#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/irqs.h b/arch/arm/mach-bcm2709/include/mach/irqs.h -new file mode 100644 -index 0000000..d301f06 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/irqs.h -@@ -0,0 +1,225 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/irqs.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_IRQS_H_ -+#define _BCM2708_IRQS_H_ -+ -+#include -+ -+/* -+ * IRQ interrupts definitions are the same as the INT definitions -+ * held within platform.h -+ */ -+#define IRQ_ARMCTRL_START 0 -+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) -+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) -+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) -+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) -+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) -+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) -+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) -+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) -+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) -+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) -+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) -+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) -+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) -+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) -+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) -+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) -+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) -+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) -+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) -+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) -+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) -+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) -+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) -+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) -+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) -+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) -+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) -+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) -+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) -+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) -+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) -+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) -+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) -+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) -+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) -+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) -+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) -+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) -+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) -+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) -+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) -+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) -+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) -+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) -+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) -+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) -+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) -+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) -+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) -+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) -+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) -+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) -+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) -+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) -+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) -+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) -+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) -+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) -+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) -+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) -+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) -+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) -+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) -+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -+ -+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) -+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) -+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) -+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) -+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) -+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) -+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) -+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) -+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) -+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -+ -+#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define FIQ_START HARD_IRQS -+ -+/* -+ * FIQ interrupts definitions are the same as the INT definitions. -+ */ -+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) -+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) -+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) -+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) -+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) -+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) -+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) -+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) -+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) -+#define FIQ_USB (FIQ_START+INTERRUPT_USB) -+#define FIQ_3D (FIQ_START+INTERRUPT_3D) -+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) -+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) -+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) -+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) -+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) -+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) -+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) -+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) -+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) -+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) -+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) -+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) -+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) -+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) -+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) -+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) -+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) -+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) -+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) -+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) -+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) -+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) -+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) -+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) -+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) -+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) -+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) -+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) -+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) -+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) -+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) -+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) -+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) -+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) -+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) -+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) -+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) -+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) -+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) -+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) -+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) -+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) -+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) -+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) -+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) -+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) -+#define FIQ_UART (FIQ_START+INTERRUPT_UART) -+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) -+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) -+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) -+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) -+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) -+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -+ -+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) -+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) -+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) -+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) -+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) -+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) -+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) -+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) -+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) -+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -+ -+#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define HARD_IRQS (128) -+#define FIQ_IRQS (128) -+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) -+#define GPIO_IRQS (32*5) -+#define SPARE_ALLOC_IRQS 64 -+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) -+#define FREE_IRQS 128 -+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -+ -+#endif /* _BCM2708_IRQS_H_ */ diff --git a/arch/arm/mach-bcm2709/include/mach/memory.h b/arch/arm/mach-bcm2709/include/mach/memory.h new file mode 100644 index 0000000..7548a52 @@ -4947,10 +3452,10 @@ index 0000000..7548a52 +#endif diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h new file mode 100644 -index 0000000..7157f38 +index 0000000..311b9f2 --- /dev/null +++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -0,0 +1,225 @@ +@@ -0,0 +1,188 @@ +/* + * arch/arm/mach-bcm2708/include/mach/platform.h + * @@ -5000,9 +3505,6 @@ index 0000000..7157f38 +#define HW_REGISTER_RW(addr) (addr) +#define HW_REGISTER_RO(addr) (addr) + -+#include "arm_control.h" -+#undef ARM_BASE -+ +/* + * Definitions and addresses for the ARM CONTROL logic + * This file is manually generated. @@ -5035,116 +3537,6 @@ index 0000000..7157f38 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ + -+ -+/* -+ * Interrupt assignments -+ */ -+ -+#define ARM_IRQ1_BASE 0 -+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) -+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) -+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) -+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) -+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) -+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) -+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) -+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) -+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) -+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) -+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) -+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) -+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) -+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) -+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) -+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) -+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) -+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) -+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) -+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) -+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) -+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) -+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) -+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) -+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) -+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) -+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) -+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) -+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) -+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) -+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) -+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -+ -+#define ARM_IRQ2_BASE 32 -+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) -+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) -+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) -+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) -+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) -+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) -+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) -+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) -+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) -+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) -+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) -+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) -+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) -+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) -+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) -+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) -+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) -+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) -+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) -+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) -+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) -+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) -+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) -+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) -+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) -+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) -+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) -+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) -+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) -+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) -+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) -+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -+ -+#define ARM_IRQ0_BASE 64 -+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) -+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) -+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) -+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) -+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) -+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) -+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) -+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) -+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) -+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) -+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) -+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) -+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) -+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) -+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) -+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) -+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) -+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) -+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) -+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) -+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -+ -+#define ARM_IRQ_LOCAL_BASE 96 -+#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) -+#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) -+#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) -+#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) -+#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) -+#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) -+#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) -+#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) -+#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) -+#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) -+#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) -+#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) -+ +/* + * Watchdog + */ @@ -5173,15 +3565,91 @@ index 0000000..7157f38 + +#define UART0_CLOCK 3000000 + ++#define ARM_LOCAL_BASE 0x40000000 ++#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) ++ ++#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) ++#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) ++#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) ++#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) ++#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) ++#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) ++#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) ++#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) ++#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) ++#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) ++#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) ++#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) ++ ++#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) ++#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) ++#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) ++#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) ++ ++#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) ++ ++#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) ++#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) ++#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) ++#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) ++ ++#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) ++#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) ++#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) ++#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) ++ ++#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) ++#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) ++#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) ++#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) ++ ++#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) ++#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) ++#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) ++#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) ++ ++#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) ++#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) ++#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) ++#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) ++ ++#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) ++#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) ++#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) ++#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) ++#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) ++#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) ++#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) ++#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) ++#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) ++#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) ++#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) ++#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) ++#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) ++#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) ++#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) ++#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) ++ +#endif + +/* END */ diff --git a/arch/arm/mach-bcm2709/include/mach/system.h b/arch/arm/mach-bcm2709/include/mach/system.h new file mode 100644 -index 0000000..2d0b821 +index 0000000..c9a9c9a --- /dev/null +++ b/arch/arm/mach-bcm2709/include/mach/system.h -@@ -0,0 +1,38 @@ +@@ -0,0 +1,37 @@ +/* + * arch/arm/mach-bcm2708/include/mach/system.h + * @@ -5207,7 +3675,6 @@ index 0000000..2d0b821 +#define __ASM_ARCH_SYSTEM_H + +#include -+#include +#include + +static inline void arch_idle(void) @@ -5222,7 +3689,7 @@ index 0000000..2d0b821 +#endif diff --git a/arch/arm/mach-bcm2709/include/mach/uncompress.h b/arch/arm/mach-bcm2709/include/mach/uncompress.h new file mode 100644 -index 0000000..d634813 +index 0000000..de7504b --- /dev/null +++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h @@ -0,0 +1,84 @@ @@ -5249,7 +3716,7 @@ index 0000000..d634813 + +#include +#include -+#include ++#include + +#define UART_BAUD 115200 + @@ -5855,7 +4322,7 @@ index 06d890a..30d96e8 100644 ENTRY(cpu_v6_dcache_clean_area) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S -index de2b246..3a3aec8 100644 +index 8e1ea43..be40ccb 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -480,6 +480,7 @@ __errata_finish: @@ -5893,14 +4360,16 @@ index 56bd16e..c2ac46d 100644 obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index 177f78f..27b8467 100644 +index 177f78f..6a9e2d0 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile -@@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o +@@ -2,6 +2,9 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o +obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o ++obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2835.o ++obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o obj-$(CONFIG_ARCH_MMP) += irq-mmp.o @@ -5920,10 +4389,10 @@ index 8673ffe..ad22ebb 100644 2.5.0 -From 09a09a752f40a9a5e43e906670afc00e5119391a Mon Sep 17 00:00:00 2001 +From 4f7a784e0256c10f6200438aa74e385e151c2241 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 11 Nov 2015 21:01:15 +0000 -Subject: [PATCH 29/55] squash: include ARCH_BCM2708 / ARCH_BCM2709 +Subject: [PATCH 28/54] squash: include ARCH_BCM2708 / ARCH_BCM2709 --- drivers/char/hw_random/Kconfig | 2 +- @@ -6078,10 +4547,10 @@ index 6a834e1..c5070ae 100644 2.5.0 -From 28f5227ea6cdf14dbdad6b4790a417a24949f080 Mon Sep 17 00:00:00 2001 +From 43a51c6dbdb406826da11b1101cc6511d1185d67 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:46:17 +0100 -Subject: [PATCH 30/55] Add dwc_otg driver +Subject: [PATCH 29/54] Add dwc_otg driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -6547,7 +5016,6 @@ dwc_otg: Remove duplicate gadget probe/unregister function --- arch/arm/include/asm/irqflags.h | 16 +- arch/arm/kernel/fiqasm.S | 4 + - arch/arm/mach-bcm2709/armctrl.c | 10 +- drivers/usb/Makefile | 1 + drivers/usb/core/generic.c | 1 + drivers/usb/core/hub.c | 2 +- @@ -6616,7 +5084,7 @@ dwc_otg: Remove duplicate gadget probe/unregister function drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 + drivers/usb/host/dwc_otg/test/test_mod_param.pl | 133 + drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 + - 71 files changed, 59876 insertions(+), 17 deletions(-) + 70 files changed, 59867 insertions(+), 16 deletions(-) create mode 100644 drivers/usb/gadget/file_storage.c create mode 100644 drivers/usb/host/dwc_common_port/Makefile create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd @@ -6722,27 +5190,6 @@ index 8dd26e1..eef4847 100644 +ENTRY(__FIQ_Branch) + mov pc, r8 +ENDPROC(__FIQ_Branch) -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -index 813008a..c6f68b4 100644 ---- a/arch/arm/mach-bcm2709/armctrl.c -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -91,7 +91,15 @@ static void armctrl_unmask_irq(struct irq_data *d) - }; - int i; - if (d->irq >= FIQ_START) { -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ unsigned int data; -+ if (num_online_cpus() > 1) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= (1 << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ /* Unmask in ARMCTRL block after routing it properly */ -+ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; - writel(0x80 | data, __io_address(ARM_IRQ_FAST)); - } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { - #if 1 diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index d5c57f1..0e15a22 100644 --- a/drivers/usb/Makefile @@ -6768,10 +5215,10 @@ index 358ca8d..abaac7c 100644 return i; } diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c -index a5cc032..4bc2626 100644 +index ddbf32d..12166e2 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c -@@ -4930,7 +4930,7 @@ static void port_event(struct usb_hub *hub, int port1) +@@ -4946,7 +4946,7 @@ static void port_event(struct usb_hub *hub, int port1) if (portchange & USB_PORT_STAT_C_OVERCURRENT) { u16 status = 0, unused; @@ -67085,10 +65532,10 @@ index 0000000..cdc9963 2.5.0 -From 621d61cc9ba873aa2ca9bb0fc7cef9aaae7f9167 Mon Sep 17 00:00:00 2001 +From e84cab190a51bb9d04b38e76ce90a47c0f93da5e Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 17 Jun 2015 17:06:34 +0100 -Subject: [PATCH 31/55] bcm2708 framebuffer driver +Subject: [PATCH 30/54] bcm2708 framebuffer driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -70553,10 +69000,10 @@ index 3c14e43..7626beb 100644 2.5.0 -From 090f8a9ade61015468e0116089a3cf084488274c Mon Sep 17 00:00:00 2001 +From 227880a04368c2840eb27d8d25aaee1cfd7e5c3a Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:22:53 +0100 -Subject: [PATCH 32/55] dmaengine: Add support for BCM2708 +Subject: [PATCH 31/54] dmaengine: Add support for BCM2708 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -71179,10 +69626,10 @@ index 0000000..99cc7fd 2.5.0 -From 71b2809c60befcf445b96bc6a2a6c556db1e63c7 Mon Sep 17 00:00:00 2001 +From 68dc1707b0e75ca092319956776e656bc3b42315 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 17 Apr 2015 19:30:22 +0100 -Subject: [PATCH 33/55] Add blk_pos parameter to mmc multi_io_quirk callback +Subject: [PATCH 32/54] Add blk_pos parameter to mmc multi_io_quirk callback --- drivers/mmc/card/block.c | 1 + @@ -71268,10 +69715,10 @@ index ad22ebb..105b3e6 100644 2.5.0 -From 12ca0b3680d241ad7699e0b5100127adce522c91 Mon Sep 17 00:00:00 2001 +From c9c3712517791991bc66744c3931cee457a70018 Mon Sep 17 00:00:00 2001 From: gellert Date: Fri, 15 Aug 2014 16:35:06 +0100 -Subject: [PATCH 34/55] MMC: added alternative MMC driver +Subject: [PATCH 33/54] MMC: added alternative MMC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -71341,8 +69788,8 @@ bcm2835-mmc: Don't overwrite MMC capabilities from DT drivers/mmc/core/quirks.c | 6 + drivers/mmc/host/Kconfig | 29 + drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/bcm2835-mmc.c | 1559 ++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 1595 insertions(+) + drivers/mmc/host/bcm2835-mmc.c | 1542 ++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 1578 insertions(+) create mode 100644 drivers/mmc/host/bcm2835-mmc.c diff --git a/drivers/mmc/core/quirks.c b/drivers/mmc/core/quirks.c @@ -71422,10 +69869,10 @@ index 3595f83..6cf6457 100644 obj-$(CONFIG_MMC_MTK) += mtk-sd.o diff --git a/drivers/mmc/host/bcm2835-mmc.c b/drivers/mmc/host/bcm2835-mmc.c new file mode 100644 -index 0000000..164bfad +index 0000000..43aed6e --- /dev/null +++ b/drivers/mmc/host/bcm2835-mmc.c -@@ -0,0 +1,1559 @@ +@@ -0,0 +1,1542 @@ +/* + * BCM2835 MMC host driver. + * @@ -71491,13 +69938,6 @@ index 0000000..164bfad +#define TIMEOUT_VAL 0xE +#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1) + -+#ifndef BCM2708_PERI_BASE -+ #define BCM2708_PERI_BASE 0x20000000 -+#endif -+ -+/* FIXME: Needs IOMMU support */ -+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) -+ + +unsigned mmc_debug; +unsigned mmc_debug2; @@ -71506,7 +69946,7 @@ index 0000000..164bfad + spinlock_t lock; + + void __iomem *ioaddr; -+ u32 phys_addr; ++ u32 bus_addr; + + struct mmc_host *mmc; + @@ -72112,12 +70552,10 @@ index 0000000..164bfad + } + + timeout = jiffies; -+#ifdef CONFIG_ARCH_BCM2835 + if (!cmd->data && cmd->busy_timeout > 9000) + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; + else -+#endif -+ timeout += 10 * HZ; ++ timeout += 10 * HZ; + mod_timer(&host->timer, timeout); + + host->cmd = cmd; @@ -72412,9 +70850,6 @@ index 0000000..164bfad + struct bcm2835_host *host = dev_id; + u32 intmask, mask, unexpected = 0; + int max_loops = 16; -+#ifndef CONFIG_ARCH_BCM2835 -+ int cardint = 0; -+#endif + + spin_lock(&host->lock); + @@ -72443,13 +70878,9 @@ index 0000000..164bfad + mmc_hostname(host->mmc)); + + if (intmask & SDHCI_INT_CARD_INT) { -+#ifndef CONFIG_ARCH_BCM2835 -+ cardint = 1; -+#else + bcm2835_mmc_enable_sdio_irq_nolock(host, false); + host->thread_isr |= SDHCI_INT_CARD_INT; + result = IRQ_WAKE_THREAD; -+#endif + } + + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | @@ -72476,15 +70907,9 @@ index 0000000..164bfad + bcm2835_mmc_dumpregs(host); + } + -+#ifndef CONFIG_ARCH_BCM2835 -+ if (cardint) -+ mmc_signal_sdio_irq(host->mmc); -+#endif -+ + return result; +} + -+#ifdef CONFIG_ARCH_BCM2835 +static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) +{ + struct bcm2835_host *host = dev_id; @@ -72507,7 +70932,6 @@ index 0000000..164bfad + + return isr ? IRQ_HANDLED : IRQ_NONE; +} -+#endif + + + @@ -72751,14 +71175,15 @@ index 0000000..164bfad + + /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ + host->timeout_clk = mmc->f_max / 1000; -+#ifdef CONFIG_ARCH_BCM2835 + mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; -+#endif ++ + /* host controller capabilities */ + mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | + MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; + ++ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; ++ + host->flags = SDHCI_AUTO_CMD23; + + dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2); @@ -72781,11 +71206,11 @@ index 0000000..164bfad + + cfg.direction = DMA_MEM_TO_DEV; + cfg.src_addr = 0; -+ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER; ++ cfg.dst_addr = host->bus_addr + SDHCI_BUFFER; + ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); + + cfg.direction = DMA_DEV_TO_MEM; -+ cfg.src_addr = host->phys_addr + SDHCI_BUFFER; ++ cfg.src_addr = host->bus_addr + SDHCI_BUFFER; + cfg.dst_addr = 0; + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); + } @@ -72806,14 +71231,9 @@ index 0000000..164bfad + init_waitqueue_head(&host->buf_ready_int); + + bcm2835_mmc_init(host, 0); -+#ifndef CONFIG_ARCH_BCM2835 -+ ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0, -+ mmc_hostname(mmc), host); -+#else + ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq, + bcm2835_mmc_thread_irq, IRQF_SHARED, + mmc_hostname(mmc), host); -+#endif + if (ret) { + dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret); + goto untasklet; @@ -72838,6 +71258,7 @@ index 0000000..164bfad + struct resource *iomem; + struct bcm2835_host *host; + struct mmc_host *mmc; ++ const __be32 *addr; + int ret; + + mmc = mmc_alloc_host(sizeof(*host), dev); @@ -72857,7 +71278,16 @@ index 0000000..164bfad + goto err; + } + -+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; ++ addr = of_get_address(node, 0, NULL, NULL); ++ if (!addr) { ++ dev_err(dev, "could not get DMA-register address\n"); ++ return -ENODEV; ++ } ++ host->bus_addr = be32_to_cpup(addr); ++ pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n", ++ (unsigned long)host->ioaddr, ++ (unsigned long)iomem->start, ++ (unsigned long)host->bus_addr); + +#ifndef FORCE_PIO + if (node) { @@ -72989,10 +71419,10 @@ index 0000000..164bfad 2.5.0 -From 85337ce70f7c4a3b6c3cbcdbf9081307247b3a9c Mon Sep 17 00:00:00 2001 +From e43ccd0115b085c56aa7396bdb973d244379222d Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 25 Mar 2015 17:49:47 +0000 -Subject: [PATCH 35/55] Adding bcm2835-sdhost driver, and an overlay to enable +Subject: [PATCH 34/54] Adding bcm2835-sdhost driver, and an overlay to enable it BCM2835 has two SD card interfaces. This driver uses the other one. @@ -73058,12 +71488,18 @@ rather than making the change across the board; I can't see any technical reason why it wouldn't be enabled for MACH_BCM270X builds. So this patch standardises on the ARCH_BCM2835 code, removing the old code paths. + +bcm2835-sdhost: Don't log timeout errors unless debug=1 + +The MMC card-discovery process generates timeouts. This is +expected behaviour, so reporting it to the user serves no purpose. +Suppress the reporting of timeout errors unless the debug flag +is on. --- drivers/mmc/host/Kconfig | 10 + drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/bcm2835-mmc.c | 28 +- - drivers/mmc/host/bcm2835-sdhost.c | 1912 +++++++++++++++++++++++++++++++++++++ - 4 files changed, 1927 insertions(+), 24 deletions(-) + drivers/mmc/host/bcm2835-sdhost.c | 1907 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 1918 insertions(+) create mode 100644 drivers/mmc/host/bcm2835-sdhost.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig @@ -73099,111 +71535,12 @@ index 6cf6457..df27ae9 100644 obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o -diff --git a/drivers/mmc/host/bcm2835-mmc.c b/drivers/mmc/host/bcm2835-mmc.c -index 164bfad..0f89e57 100644 ---- a/drivers/mmc/host/bcm2835-mmc.c -+++ b/drivers/mmc/host/bcm2835-mmc.c -@@ -684,12 +684,10 @@ void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd - } - - timeout = jiffies; --#ifdef CONFIG_ARCH_BCM2835 - if (!cmd->data && cmd->busy_timeout > 9000) - timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; - else --#endif -- timeout += 10 * HZ; -+ timeout += 10 * HZ; - mod_timer(&host->timer, timeout); - - host->cmd = cmd; -@@ -984,9 +982,6 @@ static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id) - struct bcm2835_host *host = dev_id; - u32 intmask, mask, unexpected = 0; - int max_loops = 16; --#ifndef CONFIG_ARCH_BCM2835 -- int cardint = 0; --#endif - - spin_lock(&host->lock); - -@@ -1015,13 +1010,9 @@ static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id) - mmc_hostname(host->mmc)); - - if (intmask & SDHCI_INT_CARD_INT) { --#ifndef CONFIG_ARCH_BCM2835 -- cardint = 1; --#else - bcm2835_mmc_enable_sdio_irq_nolock(host, false); - host->thread_isr |= SDHCI_INT_CARD_INT; - result = IRQ_WAKE_THREAD; --#endif - } - - intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | -@@ -1048,15 +1039,9 @@ out: - bcm2835_mmc_dumpregs(host); - } - --#ifndef CONFIG_ARCH_BCM2835 -- if (cardint) -- mmc_signal_sdio_irq(host->mmc); --#endif -- - return result; - } - --#ifdef CONFIG_ARCH_BCM2835 - static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) - { - struct bcm2835_host *host = dev_id; -@@ -1079,7 +1064,6 @@ static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) - - return isr ? IRQ_HANDLED : IRQ_NONE; - } --#endif - - - -@@ -1323,14 +1307,15 @@ static int bcm2835_mmc_add_host(struct bcm2835_host *host) - - /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ - host->timeout_clk = mmc->f_max / 1000; --#ifdef CONFIG_ARCH_BCM2835 - mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; --#endif -+ - /* host controller capabilities */ - mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | - MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; - -+ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; -+ - host->flags = SDHCI_AUTO_CMD23; - - dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2); -@@ -1378,14 +1363,9 @@ static int bcm2835_mmc_add_host(struct bcm2835_host *host) - init_waitqueue_head(&host->buf_ready_int); - - bcm2835_mmc_init(host, 0); --#ifndef CONFIG_ARCH_BCM2835 -- ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0, -- mmc_hostname(mmc), host); --#else - ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq, - bcm2835_mmc_thread_irq, IRQF_SHARED, - mmc_hostname(mmc), host); --#endif - if (ret) { - dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret); - goto untasklet; diff --git a/drivers/mmc/host/bcm2835-sdhost.c b/drivers/mmc/host/bcm2835-sdhost.c new file mode 100644 -index 0000000..0623392 +index 0000000..da089985 --- /dev/null +++ b/drivers/mmc/host/bcm2835-sdhost.c -@@ -0,0 +1,1912 @@ +@@ -0,0 +1,1907 @@ +/* + * BCM2835 SD host driver. + * @@ -73318,19 +71655,12 @@ index 0000000..0623392 + +#define MHZ 1000000 + -+#ifndef BCM2708_PERI_BASE -+ #define BCM2708_PERI_BASE 0x20000000 -+#endif -+ -+/* FIXME: Needs IOMMU support */ -+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) -+ + +struct bcm2835_host { + spinlock_t lock; + + void __iomem *ioaddr; -+ u32 phys_addr; ++ u32 bus_addr; + + struct mmc_host *mmc; + @@ -74172,19 +72502,15 @@ index 0000000..0623392 + mmc_hostname(host->mmc)); + } else { + if (sdhsts & SDHSTS_CMD_TIME_OUT) { -+ switch (host->cmd->opcode) { -+ case 5: case 52: case 53: -+ /* Don't warn about SDIO commands */ -+ break; -+ default: -+ pr_err("%s: command timeout\n", -+ mmc_hostname(host->mmc)); -+ break; -+ } ++ if (host->debug) ++ pr_err("%s: command %d timeout\n", ++ mmc_hostname(host->mmc), ++ host->cmd->opcode); + host->cmd->error = -ETIMEDOUT; + } else { -+ pr_err("%s: unexpected command error\n", -+ mmc_hostname(host->mmc)); ++ pr_err("%s: unexpected command %d error\n", ++ mmc_hostname(host->mmc), ++ host->cmd->opcode); + bcm2835_sdhost_dumpregs(host); + host->cmd->error = -EIO; + } @@ -74896,11 +73222,11 @@ index 0000000..0623392 + + cfg.direction = DMA_MEM_TO_DEV; + cfg.src_addr = 0; -+ cfg.dst_addr = host->phys_addr + SDDATA; ++ cfg.dst_addr = host->bus_addr + SDDATA; + ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); + + cfg.direction = DMA_DEV_TO_MEM; -+ cfg.src_addr = host->phys_addr + SDDATA; ++ cfg.src_addr = host->bus_addr + SDDATA; + cfg.dst_addr = 0; + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); + } @@ -74963,6 +73289,7 @@ index 0000000..0623392 + struct resource *iomem; + struct bcm2835_host *host; + struct mmc_host *mmc; ++ const __be32 *addr; + int ret; + + pr_debug("bcm2835_sdhost_probe\n"); @@ -74984,11 +73311,16 @@ index 0000000..0623392 + goto err; + } + -+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; -+ pr_debug(" - ioaddr %lx, iomem->start %lx, phys_addr %lx\n", ++ addr = of_get_address(node, 0, NULL, NULL); ++ if (!addr) { ++ dev_err(dev, "could not get DMA-register address\n"); ++ return -ENODEV; ++ } ++ host->bus_addr = be32_to_cpup(addr); ++ pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n", + (unsigned long)host->ioaddr, + (unsigned long)iomem->start, -+ (unsigned long)host->phys_addr); ++ (unsigned long)host->bus_addr); + + host->allow_dma = ALLOW_DMA; + @@ -75120,10 +73452,10 @@ index 0000000..0623392 2.5.0 -From 39227ce9f8858235378890ce2d11c288456c9358 Mon Sep 17 00:00:00 2001 +From a1c91b2e27db42a9d753a2d752a4db2339971786 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:31:47 +0100 -Subject: [PATCH 36/55] cma: Add vc_cma driver to enable use of CMA +Subject: [PATCH 35/54] cma: Add vc_cma driver to enable use of CMA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -76469,10 +74801,10 @@ index 0000000..be2819d 2.5.0 -From b9efed95844aad3b24e713ea16fc3a44bd9bd9dd Mon Sep 17 00:00:00 2001 +From 288825203141275ee6ce0054b7c19b93468f6ea7 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 26 Mar 2012 22:15:50 +0100 -Subject: [PATCH 37/55] bcm2708: alsa sound driver +Subject: [PATCH 36/54] bcm2708: alsa sound driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -79173,10 +77505,10 @@ index 0000000..af3e6eb 2.5.0 -From 7ab358eb5831ee8a6301389d0e5d7caec579fc07 Mon Sep 17 00:00:00 2001 +From 10bbede5e3a5cda000722a6710342a49c7a66a97 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 2 Jul 2013 23:42:01 +0100 -Subject: [PATCH 38/55] bcm2708 vchiq driver +Subject: [PATCH 37/54] bcm2708 vchiq driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -79433,18 +77765,18 @@ index 4fb43cf..e98ec5a 100644 /* * Watchdog diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h -index 7157f38..be99733 100644 +index 311b9f2..9a638f5 100644 --- a/arch/arm/mach-bcm2709/include/mach/platform.h +++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -81,6 +81,8 @@ +@@ -78,6 +78,8 @@ #define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ #define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ #define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ +#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ +#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ - /* + * Watchdog diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 22892c7..b859ce0 100644 --- a/drivers/misc/Kconfig @@ -92484,10 +90816,10 @@ index 0000000..b6bfa21 2.5.0 -From d2519589b514436dd0f05bf7a0c03ca5449bea3d Mon Sep 17 00:00:00 2001 +From 39ea0d34e648bca5995ae2f578a2a151761e32bb Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 17 Jun 2015 16:07:06 +0100 -Subject: [PATCH 39/55] vc_mem: Add vc_mem driver +Subject: [PATCH 38/54] vc_mem: Add vc_mem driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -93495,10 +91827,10 @@ index 0000000..20a4753 2.5.0 -From 31a3d1e4846bade73ff545da696da5114c40d293 Mon Sep 17 00:00:00 2001 +From 482bc90fdaa1d40622db38100a193d00948ae585 Mon Sep 17 00:00:00 2001 From: Tim Gover Date: Tue, 22 Jul 2014 15:41:04 +0100 -Subject: [PATCH 40/55] vcsm: VideoCore shared memory service for BCM2835 +Subject: [PATCH 39/54] vcsm: VideoCore shared memory service for BCM2835 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -97917,10 +96249,10 @@ index 0000000..334f36d 2.5.0 -From c77fed4657dbeea3e515eb467b7a264b9fa303e8 Mon Sep 17 00:00:00 2001 +From ffef0c9f7166a243aae23b1bc094d222e4cfecaf Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Fri, 21 Aug 2015 23:14:48 +0100 -Subject: [PATCH 41/55] Add /dev/gpiomem device for rootless user GPIO access +Subject: [PATCH 40/54] Add /dev/gpiomem device for rootless user GPIO access Signed-off-by: Luke Wren @@ -98234,10 +96566,10 @@ index 0000000..911f5b7 2.5.0 -From da772a0aa1adc142d2eb91dc59713645608e3e54 Mon Sep 17 00:00:00 2001 +From fafb1e07bcbf595a3412748fe1243a38f3393757 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 5 Sep 2015 01:14:45 +0100 -Subject: [PATCH 42/55] Add SMI driver +Subject: [PATCH 41/54] Add SMI driver Signed-off-by: Luke Wren --- @@ -100191,10 +98523,10 @@ index 0000000..ee3a75e 2.5.0 -From f91aaf881fd7b5a1ea2848170100d68e46a2f46a Mon Sep 17 00:00:00 2001 +From a368a4010e0b463a0518eb4dbf1cf8a893727596 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 5 Sep 2015 01:16:10 +0100 -Subject: [PATCH 43/55] Add SMI NAND driver +Subject: [PATCH 42/54] Add SMI NAND driver Signed-off-by: Luke Wren --- @@ -100563,10 +98895,10 @@ index 0000000..b747326 2.5.0 -From 7ddaf7044f603ac7330badd2b9b50723f5268b2d Mon Sep 17 00:00:00 2001 +From 14f0b2203b2204c057d7db441e1a292b6a0eb6f3 Mon Sep 17 00:00:00 2001 From: Aron Szabo Date: Sat, 16 Jun 2012 12:15:55 +0200 -Subject: [PATCH 44/55] lirc: added support for RaspberryPi GPIO +Subject: [PATCH 43/54] lirc: added support for RaspberryPi GPIO lirc_rpi: Use read_current_timer to determine transmitter delay. Thanks to jjmz and others See: https://github.com/raspberrypi/linux/issues/525 @@ -100651,7 +98983,7 @@ index 5430adf..9e53cd0 100644 obj-$(CONFIG_LIRC_SIR) += lirc_sir.o diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c new file mode 100644 -index 0000000..f1e0de9 +index 0000000..cd09c99 --- /dev/null +++ b/drivers/staging/media/lirc/lirc_rpi.c @@ -0,0 +1,730 @@ @@ -101040,7 +99372,7 @@ index 0000000..f1e0de9 + read_bool_property(node, "rpi,debug", &debug); + + } else { -+ return EINVAL; ++ return -EINVAL; + } + + gpiochip->set(gpiochip, gpio_out_pin, invert); @@ -101418,10 +99750,10 @@ index 0000000..fb69624 2.5.0 -From 64be6905577ed38b51e2ec0f0b12ef41d461af3b Mon Sep 17 00:00:00 2001 +From 20fd592d940f46939e89d194f0392c0fe00d1e4f Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:49:20 +0100 -Subject: [PATCH 45/55] Add cpufreq driver +Subject: [PATCH 44/54] Add cpufreq driver Signed-off-by: popcornmix --- @@ -101432,7 +99764,7 @@ Signed-off-by: popcornmix create mode 100644 drivers/cpufreq/bcm2835-cpufreq.c diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm -index 235a1ba..1a732d5 100644 +index b1f8a73..930b3ef 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -217,6 +217,15 @@ config ARM_SPEAR_CPUFREQ @@ -101686,10 +100018,10 @@ index 0000000..3eb9e93 2.5.0 -From def5e89f95d35557a0fe7d954b9da2869de8b4dd Mon Sep 17 00:00:00 2001 +From de097ce1fa4d97e711469c8e5ddc0ab0e4e84943 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 19:24:24 +0000 -Subject: [PATCH 46/55] Added hwmon/thermal driver for reporting core +Subject: [PATCH 45/54] Added hwmon/thermal driver for reporting core temperature. Thanks Dorian MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -101890,10 +100222,10 @@ index 0000000..08d8dc7 2.5.0 -From f3dbc863a57449f5bee914f7a4908cf30ba6acaf Mon Sep 17 00:00:00 2001 +From 3283ff477bed6a5f3d67e405f7df7b456a864567 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 17 Jun 2015 15:44:08 +0100 -Subject: [PATCH 47/55] Add Chris Boot's i2c driver +Subject: [PATCH 46/54] Add Chris Boot's i2c driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -102536,10 +100868,10 @@ index 0000000..85f411c 2.5.0 -From dddab3b10925b29431fc7256e03d4b6946a8da6b Mon Sep 17 00:00:00 2001 +From 7c0ed22b9161086cd3e7c3b7175c8e66538dc058 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 26 Jun 2015 14:27:06 +0200 -Subject: [PATCH 48/55] char: broadcom: Add vcio module +Subject: [PATCH 47/54] char: broadcom: Add vcio module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -102768,10 +101100,10 @@ index 0000000..c19bc20 2.5.0 -From b83c18aa697e6ea37aed43d175db2b8126a7b0d0 Mon Sep 17 00:00:00 2001 +From 386d9ed9fc8601e4919d29d24161ffcffeed4078 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Fri, 26 Jun 2015 14:25:01 +0200 -Subject: [PATCH 49/55] firmware: bcm2835: Support ARCH_BCM270x +Subject: [PATCH 48/54] firmware: bcm2835: Support ARCH_BCM270x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -102880,10 +101212,10 @@ index dd506cd3..b980d53 100644 2.5.0 -From db0290d5b59336a845d169170fdeb9eeb8870d6f Mon Sep 17 00:00:00 2001 +From d052c7efe3ebc65ce4c262607028a21a163a755b Mon Sep 17 00:00:00 2001 From: Vincent Sanders Date: Wed, 30 Jan 2013 12:45:18 +0000 -Subject: [PATCH 50/55] bcm2835: add v4l2 camera device +Subject: [PATCH 49/54] bcm2835: add v4l2 camera device - Supports raw YUV capture, preview, JPEG and H264. - Uses videobuf2 for data transfer, using dma_buf. @@ -103158,13 +101490,15 @@ https://github.com/raspberrypi/linux/issues/817 Fixes the kernel warning from videobuf2 as buffers are now returned as they are being flushed on stop_streaming. + +squash: Fixup bcm2835-camera for changes in kernel 4.4 api --- Documentation/video4linux/bcm2835-v4l2.txt | 60 + drivers/media/platform/Kconfig | 2 + drivers/media/platform/Makefile | 2 + drivers/media/platform/bcm2835/Kconfig | 25 + drivers/media/platform/bcm2835/Makefile | 5 + - drivers/media/platform/bcm2835/bcm2835-camera.c | 1843 +++++++++++++++++++++ + drivers/media/platform/bcm2835/bcm2835-camera.c | 1844 +++++++++++++++++++++ drivers/media/platform/bcm2835/bcm2835-camera.h | 126 ++ drivers/media/platform/bcm2835/controls.c | 1324 +++++++++++++++ drivers/media/platform/bcm2835/mmal-common.h | 53 + @@ -103176,7 +101510,7 @@ stop_streaming. drivers/media/platform/bcm2835/mmal-parameters.h | 656 ++++++++ drivers/media/platform/bcm2835/mmal-vchiq.c | 1916 ++++++++++++++++++++++ drivers/media/platform/bcm2835/mmal-vchiq.h | 178 ++ - 17 files changed, 6959 insertions(+) + 17 files changed, 6960 insertions(+) create mode 100644 Documentation/video4linux/bcm2835-v4l2.txt create mode 100644 drivers/media/platform/bcm2835/Kconfig create mode 100644 drivers/media/platform/bcm2835/Makefile @@ -103329,10 +101663,10 @@ index 0000000..f17c79c +ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 diff --git a/drivers/media/platform/bcm2835/bcm2835-camera.c b/drivers/media/platform/bcm2835/bcm2835-camera.c new file mode 100644 -index 0000000..dfd22d4 +index 0000000..e83334c --- /dev/null +++ b/drivers/media/platform/bcm2835/bcm2835-camera.c -@@ -0,0 +1,1843 @@ +@@ -0,0 +1,1844 @@ +/* + * Broadcom BM2835 V4L2 driver + * @@ -103655,7 +101989,7 @@ index 0000000..dfd22d4 + /* error in transfer */ + if (buf != NULL) { + /* there was a buffer with the error so return it */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } + return; + } else if (length == 0) { @@ -103664,7 +101998,7 @@ index 0000000..dfd22d4 + /* this should only ever happen if the port is + * disabled and there are buffers still queued + */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + pr_debug("Empty buffer"); + } else if (dev->capture.frame_count) { + /* grab another frame */ @@ -103694,16 +102028,16 @@ index 0000000..dfd22d4 + + div = + div_u64_rem(runtime_us, USEC_PER_SEC, &rem); -+ buf->vb.v4l2_buf.timestamp.tv_sec = ++ buf->vb.timestamp.tv_sec = + dev->capture.kernel_start_ts.tv_sec - 1 + + div; -+ buf->vb.v4l2_buf.timestamp.tv_usec = ++ buf->vb.timestamp.tv_usec = + dev->capture.kernel_start_ts.tv_usec + rem; + -+ if (buf->vb.v4l2_buf.timestamp.tv_usec >= ++ if (buf->vb.timestamp.tv_usec >= + USEC_PER_SEC) { -+ buf->vb.v4l2_buf.timestamp.tv_sec++; -+ buf->vb.v4l2_buf.timestamp.tv_usec -= ++ buf->vb.timestamp.tv_sec++; ++ buf->vb.timestamp.tv_usec -= + USEC_PER_SEC; + } + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, @@ -103714,15 +102048,15 @@ index 0000000..dfd22d4 + (int)dev->capture.kernel_start_ts. + tv_usec, + dev->capture.vc_start_timestamp, pts, -+ (int)buf->vb.v4l2_buf.timestamp.tv_sec, -+ (int)buf->vb.v4l2_buf.timestamp. ++ (int)buf->vb.timestamp.tv_sec, ++ (int)buf->vb.timestamp. + tv_usec); + } else { -+ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); ++ v4l2_get_timestamp(&buf->vb.timestamp); + } + -+ vb2_set_plane_payload(&buf->vb, 0, length); -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); ++ vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS && + is_capturing(dev)) { @@ -103739,7 +102073,7 @@ index 0000000..dfd22d4 + } + } else { + /* signal frame completion */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + complete(&dev->capture.frame_cmplt); + } + } @@ -103801,14 +102135,15 @@ index 0000000..dfd22d4 +static void buffer_queue(struct vb2_buffer *vb) +{ + struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); -+ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb); ++ struct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb); ++ struct mmal_buffer *buf = container_of(vb2, struct mmal_buffer, vb); + int ret; + + v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, + "%s: dev:%p buf:%p\n", __func__, dev, buf); + -+ buf->buffer = vb2_plane_vaddr(&buf->vb, 0); -+ buf->buffer_size = vb2_plane_size(&buf->vb, 0); ++ buf->buffer = vb2_plane_vaddr(&buf->vb.vb2_buf, 0); ++ buf->buffer_size = vb2_plane_size(&buf->vb.vb2_buf, 0); + + ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf); + if (ret < 0) @@ -106640,7 +104975,7 @@ index 0000000..f9f903f +} diff --git a/drivers/media/platform/bcm2835/mmal-common.h b/drivers/media/platform/bcm2835/mmal-common.h new file mode 100644 -index 0000000..15788a1 +index 0000000..840fd13 --- /dev/null +++ b/drivers/media/platform/bcm2835/mmal-common.h @@ -0,0 +1,53 @@ @@ -106682,7 +105017,7 @@ index 0000000..15788a1 +/* buffer for one video frame */ +struct mmal_buffer { + /* v4l buffer data -- must be first */ -+ struct vb2_buffer vb; ++ struct vb2_v4l2_buffer vb; + + /* list of buffers available */ + struct list_head list; @@ -110268,10 +108603,10 @@ index 0000000..9d1d11e 2.5.0 -From 6d253ddc1d7b7e043db5d664066ded641d7a61d2 Mon Sep 17 00:00:00 2001 +From 88f17ab49dec26cef89f7382763e0aea94e380cd Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 11 May 2015 09:00:42 +0100 -Subject: [PATCH 51/55] scripts: Add mkknlimg and knlinfo scripts from tools +Subject: [PATCH 50/54] scripts: Add mkknlimg and knlinfo scripts from tools repo The Raspberry Pi firmware looks for a trailer on the kernel image to @@ -110739,10 +109074,10 @@ index 0000000..3998d43 2.5.0 -From 8f16e638180c0be62eac73a4e19794fe948efb3e Mon Sep 17 00:00:00 2001 +From 546668ae1382b20c6e80ef49bad762045fc4e1c4 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 5 Dec 2014 17:26:26 +0000 -Subject: [PATCH 52/55] fdt: Add support for the CONFIG_CMDLINE_EXTEND option +Subject: [PATCH 51/54] fdt: Add support for the CONFIG_CMDLINE_EXTEND option --- drivers/of/fdt.c | 29 ++++++++++++++++++++++++----- @@ -110800,10 +109135,10 @@ index 655f79d..0508152 100644 2.5.0 -From 2fb1188922a91873daa63c077531075086d14e8c Mon Sep 17 00:00:00 2001 +From 1a604dcf0461ad1a5422f6618686d7ce5beb0a2f Mon Sep 17 00:00:00 2001 From: notro Date: Wed, 9 Jul 2014 14:46:08 +0200 -Subject: [PATCH 53/55] BCM2708: Add core Device Tree support +Subject: [PATCH 52/54] BCM2708: Add core Device Tree support Add the bare minimum needed to boot BCM2708 from a Device Tree. @@ -110847,20 +109182,41 @@ Add paramter to toggle sdio-device-polling done every second or once at boot-time. Signed-off-by: Patrick Boettcher + +BCM270X_DT: Make mmc overlay compatible with current firmware + +The original DT overlay logic followed a merge-then-patch procedure, +i.e. parameters are applied to the loaded overlay before the overlay +is merged into the base DTB. This sequence has been changed to +patch-then-merge, in order to support parameterised node names, and +to protect against bad overlays. As a result, overrides (parameters) +must only target labels in the overlay, but the overlay can obviously target nodes in the base DTB. + +mmc-overlay.dts (that switches back to the original mmc sdcard +driver) is the only overlay violating that rule, and this patch +fixes it. + +bcm270x_dt: Use the sdhost MMC controller by default + +The "mmc" overlay reverts to using the other controller. + +squash: Add cprman to dt + +BCM270X_DT: Use clk_core for I2C interfaces --- arch/arm/boot/dts/Makefile | 30 + - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 134 +++++ - arch/arm/boot/dts/bcm2708-rpi-b.dts | 124 ++++ - arch/arm/boot/dts/bcm2708-rpi-cm.dts | 98 ++++ - arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 30 + - arch/arm/boot/dts/bcm2708.dtsi | 36 ++ - arch/arm/boot/dts/bcm2708_common.dtsi | 320 ++++++++++ - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 134 +++++ - arch/arm/boot/dts/bcm2709.dtsi | 76 +++ + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 145 +++++ + arch/arm/boot/dts/bcm2708-rpi-b.dts | 135 +++++ + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 102 ++++ + arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 40 ++ + arch/arm/boot/dts/bcm2708.dtsi | 40 ++ + arch/arm/boot/dts/bcm2708_common.dtsi | 347 +++++++++++ + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 145 +++++ + arch/arm/boot/dts/bcm2709.dtsi | 102 ++++ arch/arm/boot/dts/bcm2835-rpi-cm.dts | 93 +++ arch/arm/boot/dts/bcm2835-rpi-cm.dtsi | 30 + arch/arm/boot/dts/overlays/Makefile | 69 +++ - arch/arm/boot/dts/overlays/README | 649 +++++++++++++++++++++ + arch/arm/boot/dts/overlays/README | 648 +++++++++++++++++++++ arch/arm/boot/dts/overlays/ads7846-overlay.dts | 83 +++ .../dts/overlays/bmp085_i2c-sensor-overlay.dts | 23 + arch/arm/boot/dts/overlays/dht11-overlay.dts | 39 ++ @@ -110879,7 +109235,7 @@ Signed-off-by: Patrick Boettcher arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts | 57 ++ .../arm/boot/dts/overlays/mcp2515-can0-overlay.dts | 69 +++ .../arm/boot/dts/overlays/mcp2515-can1-overlay.dts | 69 +++ - arch/arm/boot/dts/overlays/mmc-overlay.dts | 19 + + arch/arm/boot/dts/overlays/mmc-overlay.dts | 39 ++ arch/arm/boot/dts/overlays/mz61581-overlay.dts | 111 ++++ arch/arm/boot/dts/overlays/piscreen-overlay.dts | 96 +++ .../dts/overlays/pitft28-resistive-overlay.dts | 115 ++++ @@ -110892,8 +109248,8 @@ Signed-off-by: Patrick Boettcher arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts | 17 + arch/arm/boot/dts/overlays/rpi-proto-overlay.dts | 39 ++ arch/arm/boot/dts/overlays/rpi-sense-overlay.dts | 47 ++ - arch/arm/boot/dts/overlays/sdhost-overlay.dts | 56 ++ - arch/arm/boot/dts/overlays/sdio-overlay.dts | 33 ++ + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 29 + + arch/arm/boot/dts/overlays/sdio-overlay.dts | 32 + arch/arm/boot/dts/overlays/smi-dev-overlay.dts | 18 + arch/arm/boot/dts/overlays/smi-nand-overlay.dts | 69 +++ arch/arm/boot/dts/overlays/smi-overlay.dts | 37 ++ @@ -110903,7 +109259,7 @@ Signed-off-by: Patrick Boettcher arch/arm/boot/dts/overlays/vga666-overlay.dts | 30 + arch/arm/boot/dts/overlays/w1-gpio-overlay.dts | 39 ++ .../boot/dts/overlays/w1-gpio-pullup-overlay.dts | 41 ++ - 55 files changed, 4108 insertions(+) + 55 files changed, 4203 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-plus.dts create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b.dts create mode 100755 arch/arm/boot/dts/bcm2708-rpi-cm.dts @@ -111012,13 +109368,13 @@ index 30bbc37..d583e67 100644 +endif diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts new file mode 100644 -index 0000000..ffb7596 +index 0000000..2e4df17 --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -0,0 +1,134 @@ +@@ -0,0 +1,145 @@ +/dts-v1/; + -+/include/ "bcm2708.dtsi" ++#include "bcm2708.dtsi" + +/ { + compatible = "brcm,bcm2708"; @@ -111026,6 +109382,11 @@ index 0000000..ffb7596 +}; + +&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -111052,9 +109413,11 @@ index 0000000..ffb7596 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ status = "okay"; +}; + +&fb { @@ -111109,6 +109472,10 @@ index 0000000..ffb7596 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +&leds { + act_led: act { + label = "led0"; @@ -111152,13 +109519,13 @@ index 0000000..ffb7596 +}; diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts new file mode 100644 -index 0000000..8551159 +index 0000000..0445b46 --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -0,0 +1,124 @@ +@@ -0,0 +1,135 @@ +/dts-v1/; + -+/include/ "bcm2708.dtsi" ++#include "bcm2708.dtsi" + +/ { + compatible = "brcm,bcm2708"; @@ -111166,6 +109533,11 @@ index 0000000..8551159 +}; + +&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -111192,9 +109564,11 @@ index 0000000..8551159 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ status = "okay"; +}; + +&fb { @@ -111249,6 +109623,10 @@ index 0000000..8551159 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +&leds { + act_led: act { + label = "led0"; @@ -111282,13 +109660,13 @@ index 0000000..8551159 +}; diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts new file mode 100755 -index 0000000..1f7ec88 +index 0000000..87c1a54 --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -@@ -0,0 +1,98 @@ +@@ -0,0 +1,102 @@ +/dts-v1/; + -+/include/ "bcm2708-rpi-cm.dtsi" ++#include "bcm2708-rpi-cm.dtsi" + +/ { + model = "Raspberry Pi Compute Module"; @@ -111369,6 +109747,10 @@ index 0000000..1f7ec88 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +/ { + __overrides__ { + uart0 = <&uart0>,"status"; @@ -111386,11 +109768,18 @@ index 0000000..1f7ec88 +}; diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi new file mode 100644 -index 0000000..713e5a2 +index 0000000..3c8bdde --- /dev/null +++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -@@ -0,0 +1,30 @@ -+/include/ "bcm2708.dtsi" +@@ -0,0 +1,40 @@ ++#include "bcm2708.dtsi" ++ ++&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; + +&leds { + act_led: act { @@ -111400,9 +109789,12 @@ index 0000000..713e5a2 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ non-removable; ++ status = "okay"; +}; + +&fb { @@ -111422,11 +109814,11 @@ index 0000000..713e5a2 +}; diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi new file mode 100644 -index 0000000..0bea715 +index 0000000..f5a44cd --- /dev/null +++ b/arch/arm/boot/dts/bcm2708.dtsi -@@ -0,0 +1,36 @@ -+/include/ "bcm2708_common.dtsi" +@@ -0,0 +1,40 @@ ++#include "bcm2708_common.dtsi" + +/ { + compatible = "brcm,bcm2708"; @@ -111462,13 +109854,17 @@ index 0000000..0bea715 +&intc { + compatible = "brcm,bcm2835-armctrl-ic"; +}; ++ ++&watchdog { ++ status = "okay"; ++}; diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi new file mode 100644 -index 0000000..c658c7b +index 0000000..75fb4ce --- /dev/null +++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -0,0 +1,320 @@ -+/include/ "skeleton.dtsi" +@@ -0,0 +1,347 @@ ++#include "skeleton.dtsi" + +/ { + interrupt-parent = <&intc>; @@ -111484,6 +109880,7 @@ index 0000000..c658c7b + mailbox = &mailbox; + gpio = &gpio; + uart0 = &uart0; ++ sdhost = &sdhost; + i2s = &i2s; + spi0 = &spi0; + i2c0 = &i2c0; @@ -111555,6 +109952,18 @@ index 0000000..c658c7b + status = "disabled"; + }; + ++ cprman: cprman@7e101000 { ++ compatible = "brcm,bcm2835-cprman"; ++ #clock-cells = <1>; ++ reg = <0x7e101000 0x2000>; ++ ++ /* CPRMAN derives everything from the platform's ++ * oscillator. ++ */ ++ clocks = <&clk_osc>; ++ status = "disabled"; ++ }; ++ + random: rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; @@ -111584,6 +109993,18 @@ index 0000000..c658c7b + status = "disabled"; + }; + ++ sdhost: sdhost@7e202000 { ++ compatible = "brcm,bcm2835-sdhost"; ++ reg = <0x7e202000 0x100>; ++ interrupts = <2 24>; ++ clocks = <&clk_core>; ++ dmas = <&dma 13>, ++ <&dma 13>; ++ dma-names = "tx", "rx"; ++ brcm,pio-limit = <1>; ++ status = "disabled"; ++ }; ++ + i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = <0x7e203000 0x24>, @@ -111616,7 +110037,7 @@ index 0000000..c658c7b + compatible = "brcm,bcm2708-i2c"; + reg = <0x7e205000 0x1000>; + interrupts = <2 21>; -+ clocks = <&clk_i2c>; ++ clocks = <&clk_core>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; @@ -111655,7 +110076,7 @@ index 0000000..c658c7b + compatible = "brcm,bcm2708-i2c"; + reg = <0x7e804000 0x1000>; + interrupts = <2 21>; -+ clocks = <&clk_i2c>; ++ clocks = <&clk_core>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; @@ -111668,7 +110089,7 @@ index 0000000..c658c7b + compatible = "brcm,bcm2708-i2c"; + reg = <0x7e805000 0x1000>; + interrupts = <2 21>; -+ clocks = <&clk_i2c>; ++ clocks = <&clk_core>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; @@ -111727,61 +110148,63 @@ index 0000000..c658c7b + #address-cells = <1>; + #size-cells = <0>; + -+ clk_mmc: clock@0 { ++ clk_core: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; -+ clock-output-names = "mmc"; -+ clock-frequency = <250000000>; -+ }; -+ -+ clk_i2c: clock@1 { -+ compatible = "fixed-clock"; -+ reg = <1>; -+ #clock-cells = <0>; -+ clock-output-names = "i2c"; -+ clock-frequency = <250000000>; -+ }; -+ -+ clk_core: clock@2 { -+ compatible = "fixed-clock"; -+ reg = <2>; -+ #clock-cells = <0>; + clock-output-names = "core"; + clock-frequency = <250000000>; + }; + -+ clk_uart0: clock@3 { ++ clk_mmc: clock@1 { + compatible = "fixed-clock"; -+ reg = <3>; ++ reg = <1>; ++ #clock-cells = <0>; ++ clock-output-names = "mmc"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_uart0: clock@2 { ++ compatible = "fixed-clock"; ++ reg = <2>; + #clock-cells = <0>; + clock-output-names = "uart0_pclk"; + clock-frequency = <3000000>; + }; + -+ clk_apb_p: clock@4 { ++ clk_apb_p: clock@3 { + compatible = "fixed-clock"; -+ reg = <4>; ++ reg = <3>; + #clock-cells = <0>; + clock-output-names = "apb_pclk"; + clock-frequency = <126000000>; + }; + -+ clk_pwm: clock@5 { -+ compatible = "fixed-clock"; -+ reg = <3>; -+ #clock-cells = <0>; -+ clock-output-names = "pwm"; -+ clock-frequency = <100000000>; ++ clk_pwm: clock@4 { ++ compatible = "fixed-clock"; ++ reg = <4>; ++ #clock-cells = <0>; ++ clock-output-names = "pwm"; ++ clock-frequency = <100000000>; + }; + -+ clk_uart1: clock@6 { ++ clk_uart1: clock@5 { + compatible = "fixed-factor-clock"; ++ reg = <5>; + clocks = <&clk_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + }; ++ ++ /* The oscillator is the root of the clock tree. */ ++ clk_osc: clock@6 { ++ compatible = "fixed-clock"; ++ reg = <6>; ++ #clock-cells = <0>; ++ clock-output-names = "osc"; ++ clock-frequency = <19200000>; ++ }; + }; + + __overrides__ { @@ -111790,13 +110213,13 @@ index 0000000..c658c7b +}; diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts new file mode 100644 -index 0000000..7a05dab5 +index 0000000..5206ba2 --- /dev/null +++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -0,0 +1,134 @@ +@@ -0,0 +1,145 @@ +/dts-v1/; + -+/include/ "bcm2709.dtsi" ++#include "bcm2709.dtsi" + +/ { + compatible = "brcm,bcm2709"; @@ -111804,6 +110227,11 @@ index 0000000..7a05dab5 +}; + +&gpio { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -111830,9 +110258,11 @@ index 0000000..7a05dab5 + }; +}; + -+&mmc { -+ status = "okay"; ++&sdhost { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; + bus-width = <4>; ++ status = "okay"; +}; + +&fb { @@ -111887,6 +110317,10 @@ index 0000000..7a05dab5 + pinctrl-0 = <&i2s_pins>; +}; + ++&random { ++ status = "okay"; ++}; ++ +&leds { + act_led: act { + label = "led0"; @@ -111930,11 +110364,11 @@ index 0000000..7a05dab5 +}; diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi new file mode 100644 -index 0000000..811d825 +index 0000000..a8cfd7c --- /dev/null +++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -0,0 +1,76 @@ -+/include/ "bcm2708_common.dtsi" +@@ -0,0 +1,102 @@ ++#include "bcm2708_common.dtsi" + +/ { + compatible = "brcm,bcm2709"; @@ -111946,11 +110380,21 @@ index 0000000..811d825 + }; + + soc { -+ ranges = <0x7e000000 0x3f000000 0x01000000>; ++ ranges = <0x7e000000 0x3f000000 0x01000000>, ++ <0x40000000 0x40000000 0x00040000>; ++ ++ local_intc: local_intc { ++ compatible = "brcm,bcm2836-l1-intc"; ++ reg = <0x40000000 0x100>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&local_intc>; ++ }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; -+ interrupts = <3 9>; ++ interrupt-parent = <&local_intc>; ++ interrupts = <9>; + }; + + gpiomem { @@ -111958,16 +110402,22 @@ index 0000000..811d825 + reg = <0x7e200000 0x1000>; + status = "okay"; + }; -+ }; + -+ timer { -+ compatible = "arm,armv7-timer"; -+ clock-frequency = <19200000>; -+ interrupts = <3 0>, // PHYS_SECURE_PPI -+ <3 1>, // PHYS_NONSECURE_PPI -+ <3 3>, // VIRT_PPI -+ <3 2>; // HYP_PPI -+ always-on; ++ timer { ++ compatible = "arm,armv7-timer"; ++ clock-frequency = <19200000>; ++ interrupt-parent = <&local_intc>; ++ interrupts = <0>, // PHYS_SECURE_PPI ++ <1>, // PHYS_NONSECURE_PPI ++ <3>, // VIRT_PPI ++ <2>; // HYP_PPI ++ always-on; ++ }; ++ ++ syscon@40000000 { ++ compatible = "brcm,bcm2836-arm-local", "syscon"; ++ reg = <0x40000000 0x100>; ++ }; + }; + + cpus: cpus { @@ -112010,6 +110460,16 @@ index 0000000..811d825 + <&v7_cpu3>, "clock-frequency:0"; + }; +}; ++ ++&watchdog { ++ status = "okay"; ++}; ++ ++&intc { ++ compatible = "brcm,bcm2836-armctrl-ic"; ++ interrupt-parent = <&local_intc>; ++ interrupts = <8>; ++}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm.dts b/arch/arm/boot/dts/bcm2835-rpi-cm.dts new file mode 100644 index 0000000..c6e6860 @@ -112222,10 +110682,10 @@ index 0000000..d8c2771 +endif diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README new file mode 100644 -index 0000000..d8d0a51 +index 0000000..44e33a4 --- /dev/null +++ b/arch/arm/boot/dts/overlays/README -@@ -0,0 +1,649 @@ +@@ -0,0 +1,648 @@ +Introduction +============ + @@ -112426,7 +110886,7 @@ index 0000000..d8d0a51 + +Name: gpio-poweroff +Info: Drives a GPIO high or low on reboot -+Load: gpio-poweroff,= ++Load: dtoverlay=gpio-poweroff,= +Params: gpiopin GPIO for signalling (default 26) + + active_low Set if the power control device requires a @@ -112657,7 +111117,6 @@ index 0000000..d8d0a51 + 3) So be careful mixing audio and PWM. + 4) Currently the clock must have been enabled and configured + by other means. -+Load: dtoverlay=pwm-2chan,= +Load: dtoverlay=pwm,= +Params: pin Output pin (default 18) - see table + func Pin function (default 2 = Alt5) - see above @@ -112845,7 +111304,7 @@ index 0000000..d8d0a51 +Name: w1-gpio-pullup +Info: Configures the w1-gpio Onewire interface module. + Use this overlay if you *do* need a GPIO to drive an external pullup. -+Load: dtoverlay=w1-gpio-pullup,=,... ++Load: dtoverlay=w1-gpio-pullup,= +Params: gpiopin GPIO for I/O (default "4") + + pullup Non-zero, "on", or "y" to enable the parasitic @@ -113935,10 +112394,10 @@ index 0000000..6bef9ae +}; diff --git a/arch/arm/boot/dts/overlays/mmc-overlay.dts b/arch/arm/boot/dts/overlays/mmc-overlay.dts new file mode 100644 -index 0000000..0a37cf4 +index 0000000..00a22be --- /dev/null +++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts -@@ -0,0 +1,19 @@ +@@ -0,0 +1,39 @@ +/dts-v1/; +/plugin/; + @@ -113947,15 +112406,35 @@ index 0000000..0a37cf4 + + fragment@0 { + target = <&mmc>; -+ -+ __overlay__ { ++ frag0: __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc_pins>; ++ bus-width = <4>; + brcm,overclock-50 = <0>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ mmc_pins: mmc_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <7>; /* alt3 */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sdhost>; ++ __overlay__ { ++ status = "disabled"; + }; + }; + + __overrides__ { -+ overclock_50 = <&mmc>,"brcm,overclock-50:0"; -+ force_pio = <&mmc>,"brcm,force-pio?"; ++ overclock_50 = <&frag0>,"brcm,overclock-50:0"; ++ force_pio = <&frag0>,"brcm,force-pio?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/mz61581-overlay.dts b/arch/arm/boot/dts/overlays/mz61581-overlay.dts @@ -114740,10 +113219,10 @@ index 0000000..2715324 +}; diff --git a/arch/arm/boot/dts/overlays/sdhost-overlay.dts b/arch/arm/boot/dts/overlays/sdhost-overlay.dts new file mode 100644 -index 0000000..2da14a4 +index 0000000..85f0725 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts -@@ -0,0 +1,56 @@ +@@ -0,0 +1,29 @@ +/dts-v1/; +/plugin/; + @@ -114751,61 +113230,34 @@ index 0000000..2da14a4 + compatible = "brcm,bcm2708"; + + fragment@0 { -+ target = <&soc>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ sdhost: sdhost@7e202000 { -+ compatible = "brcm,bcm2835-sdhost"; -+ reg = <0x7e202000 0x100>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; -+ interrupts = <2 24>; -+ clocks = <&clk_core>; -+ dmas = <&dma 13>, -+ <&dma 13>; -+ dma-names = "tx", "rx"; -+ brcm,delay-after-stop = <0>; -+ brcm,overclock-50 = <0>; -+ brcm,pio-limit = <1>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { + target = <&mmc>; + __overlay__ { -+ /* Find a way to disable the other driver */ -+ compatible = ""; + status = "disabled"; + }; + }; + ++ fragment@1 { ++ target = <&sdhost>; ++ frag1: __overlay__ { ++ brcm,overclock-50 = <0>; ++ brcm,pio-limit = <1>; ++ status = "okay"; ++ }; ++ }; ++ + __overrides__ { -+ overclock_50 = <&sdhost>,"brcm,overclock-50:0"; -+ force_pio = <&sdhost>,"brcm,force-pio?"; -+ pio_limit = <&sdhost>,"brcm,pio-limit:0"; -+ debug = <&sdhost>,"brcm,debug?"; ++ overclock_50 = <&frag1>,"brcm,overclock-50:0"; ++ force_pio = <&frag1>,"brcm,force-pio?"; ++ pio_limit = <&frag1>,"brcm,pio-limit:0"; ++ debug = <&frag1>,"brcm,debug?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/sdio-overlay.dts b/arch/arm/boot/dts/overlays/sdio-overlay.dts new file mode 100644 -index 0000000..6626a1d +index 0000000..afc8742 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts -@@ -0,0 +1,33 @@ +@@ -0,0 +1,32 @@ +/* Enable SDIO from MMC interface via GPIOs 22-27. Includes sdhost overlay. */ + +/include/ "sdhost-overlay.dts" @@ -114816,7 +113268,6 @@ index 0000000..6626a1d + fragment@3 { + target = <&mmc>; + sdio_mmc: __overlay__ { -+ compatible = "brcm,bcm2835-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + non-removable; @@ -115416,10 +113867,10 @@ index 0000000..66a98f6 2.5.0 -From f97dbcf6b4ab8737d9e4d4efa48f0e79509e21f8 Mon Sep 17 00:00:00 2001 +From a9f4427a230b1ca6e77418330a42042e2b703a10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Sat, 15 Aug 2015 20:47:07 +0200 -Subject: [PATCH 54/55] bcm2835: Match with BCM2708 Device Trees +Subject: [PATCH 53/54] bcm2835: Match with BCM2708 Device Trees MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -115940,10 +114391,10 @@ index 864a3ef..3256bff 100644 2.5.0 -From 9f02b79c2efc7bf9a8cf4d9089889ee81e84f8fa Mon Sep 17 00:00:00 2001 +From 88ef042c414856132deba83d6ff8e9001c71e8d3 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 13:32:11 +0300 -Subject: [PATCH 55/55] fbdev: add FBIOCOPYAREA ioctl +Subject: [PATCH 54/54] fbdev: add FBIOCOPYAREA ioctl Based on the patch authored by Ali Gholami Rudi at https://lkml.org/lkml/2009/7/13/153 @@ -116038,7 +114489,7 @@ index fb795c3..fa72af0 100644 -- 2.5.0 -From 5087895d0f6f5a16799e33cdbf9a07a55fad82ea Mon Sep 17 00:00:00 2001 +From 3dd0886d76a33878bfdc67c44f29c9a782f88419 Mon Sep 17 00:00:00 2001 From: Harm Hanemaaijer Date: Thu, 20 Jun 2013 20:21:39 +0200 Subject: [PATCH 1/3] Speed up console framebuffer imageblit function @@ -116253,7 +114704,7 @@ index a2bb276..436494f 100644 2.5.0 -From 4c3c6b446a5992fe2539b559b2f30326bf03cf0c Mon Sep 17 00:00:00 2001 +From 4641cd894690a65893287ce27e9b98a0e554ac1a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 17:26:38 +0000 Subject: [PATCH 2/3] Allow mac address to be set in smsc95xx @@ -116350,7 +114801,7 @@ index 9c0da18..3244a90 100755 2.5.0 -From 20363421dacd9f1e1b9ece34dbdede11caba840b Mon Sep 17 00:00:00 2001 +From 4252d61d6bf3c32b2042de2a0633472e65044bcd Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 8 May 2013 11:46:50 +0100 Subject: [PATCH 3/3] enabling the realtime clock 1-wire chip DS1307 and 1-wire @@ -116605,10 +115056,10 @@ index d58594a..feae942 100644 -- 2.5.0 -From 053fc9ba3e6487c18f88b841aac676cf8c91e040 Mon Sep 17 00:00:00 2001 +From 0d2c4c9480b96a2c0a92044f11d59e1893bd5d61 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Dec 2013 22:16:19 +0000 -Subject: [PATCH 01/78] config: Enable CONFIG_MEMCG, but leave it disabled (due +Subject: [PATCH 01/59] config: Enable CONFIG_MEMCG, but leave it disabled (due to memory cost). Enable with cgroup_enable=memory. --- @@ -116660,10 +115111,10 @@ index 470f653..5ecf873 100644 2.5.0 -From b481eddbf479c66f7e2495f07d085e3613c19ea4 Mon Sep 17 00:00:00 2001 +From b29192a8be711b20a5bd623b363a9672df79d762 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:59:51 +0100 -Subject: [PATCH 02/78] ASoC: Add support for PCM5102A codec +Subject: [PATCH 02/59] ASoC: Add support for PCM5102A codec Some definitions to support the PCM5102A codec by Texas Instruments. @@ -116672,8 +115123,8 @@ Signed-off-by: Florian Meier --- sound/soc/codecs/Kconfig | 5 ++++ sound/soc/codecs/Makefile | 2 ++ - sound/soc/codecs/pcm5102a.c | 63 +++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 70 insertions(+) + sound/soc/codecs/pcm5102a.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 77 insertions(+) create mode 100644 sound/soc/codecs/pcm5102a.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig @@ -116721,10 +115172,10 @@ index f632fc4..7ba76ba 100644 obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o diff --git a/sound/soc/codecs/pcm5102a.c b/sound/soc/codecs/pcm5102a.c new file mode 100644 -index 0000000..126f1e9 +index 0000000..7c6598e --- /dev/null +++ b/sound/soc/codecs/pcm5102a.c -@@ -0,0 +1,63 @@ +@@ -0,0 +1,70 @@ +/* + * Driver for the PCM5102A codec + * @@ -116774,12 +115225,19 @@ index 0000000..126f1e9 + return 0; +} + ++static const struct of_device_id pcm5102a_of_match[] = { ++ { .compatible = "ti,pcm5102a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm5102a_of_match); ++ +static struct platform_driver pcm5102a_codec_driver = { + .probe = pcm5102a_probe, + .remove = pcm5102a_remove, + .driver = { + .name = "pcm5102a-codec", + .owner = THIS_MODULE, ++ .of_match_table = pcm5102a_of_match, + }, +}; + @@ -116792,10 +115250,10 @@ index 0000000..126f1e9 2.5.0 -From a99de03888802e57a3a8d5eee20eb43e6a37a189 Mon Sep 17 00:00:00 2001 +From 0dedabda0e45bd54adeb39ee435367e4429dfbb6 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:19:08 +0100 -Subject: [PATCH 03/78] ASoC: Add support for HifiBerry DAC +Subject: [PATCH 03/59] ASoC: Add support for HifiBerry DAC This adds a machine driver for the HifiBerry DAC. It is a sound card that can @@ -116805,8 +115263,8 @@ Signed-off-by: Florian Meier --- sound/soc/bcm/Kconfig | 7 +++ sound/soc/bcm/Makefile | 4 ++ - sound/soc/bcm/hifiberry_dac.c | 100 ++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 111 insertions(+) + sound/soc/bcm/hifiberry_dac.c | 122 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 133 insertions(+) create mode 100644 sound/soc/bcm/hifiberry_dac.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -116838,10 +115296,10 @@ index bc816b7..b877d38 100644 +obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o diff --git a/sound/soc/bcm/hifiberry_dac.c b/sound/soc/bcm/hifiberry_dac.c new file mode 100644 -index 0000000..4b70b45 +index 0000000..3ab0f47 --- /dev/null +++ b/sound/soc/bcm/hifiberry_dac.c -@@ -0,0 +1,100 @@ +@@ -0,0 +1,122 @@ +/* + * ASoC Driver for HifiBerry DAC + * @@ -116916,6 +115374,21 @@ index 0000000..4b70b45 + int ret = 0; + + snd_rpi_hifiberry_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); @@ -116928,10 +115401,17 @@ index 0000000..4b70b45 + return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); +} + ++static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match); ++ +static struct platform_driver snd_rpi_hifiberry_dac_driver = { + .driver = { + .name = "snd-hifiberry-dac", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dac_of_match, + }, + .probe = snd_rpi_hifiberry_dac_probe, + .remove = snd_rpi_hifiberry_dac_remove, @@ -116946,23 +115426,19 @@ index 0000000..4b70b45 2.5.0 -From 877f63f457781141c66be1b0f0de39b453aa03fa Mon Sep 17 00:00:00 2001 +From e44fe13cdf2e0857f445870d895a1c8c6b6741e3 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:21:34 +0100 -Subject: [PATCH 04/78] BCM2708: Add HifiBerry DAC to board file +Subject: [PATCH 04/59] ASoC: Add support for Rpi-DAC -This adds the initalization of the HifiBerry DAC -to the mach-bcm2708 board file. - -Signed-off-by: Florian Meier --- - sound/soc/bcm/Kconfig | 7 ++++ - sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/rpi-dac.c | 97 +++++++++++++++++++++++++++++++++++++++++++++ - sound/soc/codecs/Kconfig | 9 +++++ - sound/soc/codecs/Makefile | 2 + - sound/soc/codecs/pcm1794a.c | 62 +++++++++++++++++++++++++++++ - 6 files changed, 179 insertions(+) + sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/rpi-dac.c | 118 ++++++++++++++++++++++++++++++++++++++++++++ + sound/soc/codecs/Kconfig | 9 ++++ + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/pcm1794a.c | 69 ++++++++++++++++++++++++++ + 6 files changed, 207 insertions(+) create mode 100644 sound/soc/bcm/rpi-dac.c create mode 100644 sound/soc/codecs/pcm1794a.c @@ -116995,10 +115471,10 @@ index b877d38..99c96b4 100644 +obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o diff --git a/sound/soc/bcm/rpi-dac.c b/sound/soc/bcm/rpi-dac.c new file mode 100644 -index 0000000..6d6e0ba +index 0000000..d5fac1b --- /dev/null +++ b/sound/soc/bcm/rpi-dac.c -@@ -0,0 +1,97 @@ +@@ -0,0 +1,118 @@ +/* + * ASoC Driver for RPi-DAC. + * @@ -117070,6 +115546,20 @@ index 0000000..6d6e0ba + int ret = 0; + + snd_rpi_rpi_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_rpi_dac); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); @@ -117082,10 +115572,17 @@ index 0000000..6d6e0ba + return snd_soc_unregister_card(&snd_rpi_rpi_dac); +} + ++static const struct of_device_id snd_rpi_rpi_dac_of_match[] = { ++ { .compatible = "rpi,rpi-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match); ++ +static struct platform_driver snd_rpi_rpi_dac_driver = { + .driver = { + .name = "snd-rpi-dac", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_rpi_dac_of_match, + }, + .probe = snd_rpi_rpi_dac_probe, + .remove = snd_rpi_rpi_dac_remove, @@ -117145,10 +115642,10 @@ index 7ba76ba..2147436 100644 obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o diff --git a/sound/soc/codecs/pcm1794a.c b/sound/soc/codecs/pcm1794a.c new file mode 100644 -index 0000000..b4eaa44 +index 0000000..afe1b41 --- /dev/null +++ b/sound/soc/codecs/pcm1794a.c -@@ -0,0 +1,62 @@ +@@ -0,0 +1,69 @@ +/* + * Driver for the PCM1794A codec + * @@ -117197,12 +115694,19 @@ index 0000000..b4eaa44 + return 0; +} + ++static const struct of_device_id pcm1794a_of_match[] = { ++ { .compatible = "ti,pcm1794a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm1794a_of_match); ++ +static struct platform_driver pcm1794a_codec_driver = { + .probe = pcm1794a_probe, + .remove = pcm1794a_remove, + .driver = { + .name = "pcm1794a-codec", + .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(pcm1794a_of_match), + }, +}; + @@ -117215,10 +115719,10 @@ index 0000000..b4eaa44 2.5.0 -From 0d42746ebabdad8dec20c022e3202cb5e9650ed1 Mon Sep 17 00:00:00 2001 +From 5eef515f93059e16a1644ad37a17a624e3038425 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:41:23 +0100 -Subject: [PATCH 05/78] ASoC: wm8804: Implement MCLK configuration options, add +Subject: [PATCH 05/59] ASoC: wm8804: Implement MCLK configuration options, add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an @@ -117261,10 +115765,10 @@ index 8d91470..5795fb1 100644 2.5.0 -From 6d46e3d23c8e73184990e0e0fe235bcea4e4b929 Mon Sep 17 00:00:00 2001 +From e73dd7a2fba7ab58c64aa30b785c56d6ee9c213f Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:42:08 +0100 -Subject: [PATCH 06/78] ASoC: BCM:Add support for HiFiBerry Digi. Driver is +Subject: [PATCH 06/59] ASoC: BCM:Add support for HiFiBerry Digi. Driver is based on the patched WM8804 driver. Signed-off-by: Daniel Matuschek @@ -117285,8 +115789,8 @@ adds the sample rate bits in the SPDIF status block. --- sound/soc/bcm/Kconfig | 7 ++ sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/hifiberry_digi.c | 201 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 210 insertions(+) + sound/soc/bcm/hifiberry_digi.c | 223 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 232 insertions(+) create mode 100644 sound/soc/bcm/hifiberry_digi.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -117323,10 +115827,10 @@ index 99c96b4..4d53c58 100644 obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o diff --git a/sound/soc/bcm/hifiberry_digi.c b/sound/soc/bcm/hifiberry_digi.c new file mode 100644 -index 0000000..92e9e46 +index 0000000..80732b8 --- /dev/null +++ b/sound/soc/bcm/hifiberry_digi.c -@@ -0,0 +1,201 @@ +@@ -0,0 +1,223 @@ +/* + * ASoC Driver for HifiBerry Digi + * @@ -117502,6 +116006,21 @@ index 0000000..92e9e46 + int ret = 0; + + snd_rpi_hifiberry_digi.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); @@ -117514,10 +116033,17 @@ index 0000000..92e9e46 + return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); +} + ++static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-digi", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match); ++ +static struct platform_driver snd_rpi_hifiberry_digi_driver = { + .driver = { + .name = "snd-hifiberry-digi", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_digi_of_match, + }, + .probe = snd_rpi_hifiberry_digi_probe, + .remove = snd_rpi_hifiberry_digi_remove, @@ -117532,10 +116058,10 @@ index 0000000..92e9e46 2.5.0 -From ace137d7705a7f57ecaa51d7a12abebe387db63f Mon Sep 17 00:00:00 2001 +From 73edf3a97c839ddf6684271f5485d7c147b80f92 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:36:35 +0100 -Subject: [PATCH 07/78] ASoC: wm8804: Set idle_bias_off to false Idle bias has +Subject: [PATCH 07/59] ASoC: wm8804: Set idle_bias_off to false Idle bias has been change to remove warning on driver startup Signed-off-by: Daniel Matuschek @@ -117560,10 +116086,10 @@ index 5795fb1..c846716 100644 2.5.0 -From d80f0d503eb0aa5afedc80d385d7844ba8ecedf1 Mon Sep 17 00:00:00 2001 +From 1f1e820c63d8385fed2ae1df075a747702756d44 Mon Sep 17 00:00:00 2001 From: Gordon Garrity Date: Sat, 8 Mar 2014 16:56:57 +0000 -Subject: [PATCH 08/78] Add IQaudIO Sound Card support for Raspberry Pi +Subject: [PATCH 08/59] Add IQaudIO Sound Card support for Raspberry Pi Set a limit of 0dB on Digital Volume Control @@ -117574,8 +116100,8 @@ limit of 0dB for this control. --- sound/soc/bcm/Kconfig | 7 +++ sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/iqaudio-dac.c | 117 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 126 insertions(+) + sound/soc/bcm/iqaudio-dac.c | 132 ++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 141 insertions(+) create mode 100644 sound/soc/bcm/iqaudio-dac.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -117609,10 +116135,10 @@ index 4d53c58..08e4dc5 100644 +obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o diff --git a/sound/soc/bcm/iqaudio-dac.c b/sound/soc/bcm/iqaudio-dac.c new file mode 100644 -index 0000000..aff7377 +index 0000000..37038d4 --- /dev/null +++ b/sound/soc/bcm/iqaudio-dac.c -@@ -0,0 +1,117 @@ +@@ -0,0 +1,132 @@ +/* + * ASoC Driver for IQaudIO DAC + * @@ -117642,9 +116168,8 @@ index 0000000..aff7377 +{ + int ret; + struct snd_soc_card *card = rtd->card; -+ struct snd_soc_codec *codec = rtd->codec; + -+ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207); + if (ret < 0) + dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); + @@ -117697,6 +116222,21 @@ index 0000000..aff7377 + int ret = 0; + + snd_rpi_iqaudio_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); + if (ret) + dev_err(&pdev->dev, @@ -117714,6 +116254,7 @@ index 0000000..aff7377 + { .compatible = "iqaudio,iqaudio-dac", }, + {}, +}; ++MODULE_DEVICE_TABLE(of, iqaudio_of_match); + +static struct platform_driver snd_rpi_iqaudio_dac_driver = { + .driver = { @@ -117734,10 +116275,10 @@ index 0000000..aff7377 2.5.0 -From bcfba46c727f742f83c1cbb43053a26cb2894229 Mon Sep 17 00:00:00 2001 +From 26b545d1b78dba5e4a88b3ad38d129b5217c526a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 14 Jul 2014 22:02:09 +0100 -Subject: [PATCH 09/78] hid: Reduce default mouse polling interval to 60Hz +Subject: [PATCH 09/59] hid: Reduce default mouse polling interval to 60Hz Reduces overhead when using X --- @@ -117776,18 +116317,18 @@ index 36712e9..910fa89 100644 2.5.0 -From 8c0ea6c00fd0b31391e4fc079356ce3d0c065142 Mon Sep 17 00:00:00 2001 +From d00a6d6ab0ad83338de8360fb0c895dc3b780caa Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Mon, 4 Aug 2014 10:06:56 +0200 -Subject: [PATCH 10/78] Added support for HiFiBerry DAC+ +Subject: [PATCH 10/59] Added support for HiFiBerry DAC+ The driver is based on the HiFiBerry DAC driver. However HiFiBerry DAC+ uses a different codec chip (PCM5122), therefore a new driver is necessary. --- - sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Kconfig | 7 ++ sound/soc/bcm/Makefile | 2 + - sound/soc/bcm/hifiberry_dacplus.c | 119 ++++++++++++++++++++++++++++++++++++++ - 3 files changed, 128 insertions(+) + sound/soc/bcm/hifiberry_dacplus.c | 141 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 150 insertions(+) create mode 100644 sound/soc/bcm/hifiberry_dacplus.c diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig @@ -117828,10 +116369,10 @@ index 08e4dc5..a29538e 100644 obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o diff --git a/sound/soc/bcm/hifiberry_dacplus.c b/sound/soc/bcm/hifiberry_dacplus.c new file mode 100644 -index 0000000..c63387b +index 0000000..11e4f39 --- /dev/null +++ b/sound/soc/bcm/hifiberry_dacplus.c -@@ -0,0 +1,119 @@ +@@ -0,0 +1,141 @@ +/* + * ASoC Driver for HiFiBerry DAC+ + * @@ -117924,6 +116465,21 @@ index 0000000..c63387b + int ret = 0; + + snd_rpi_hifiberry_dacplus.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); + if (ret) + dev_err(&pdev->dev, @@ -117937,10 +116493,17 @@ index 0000000..c63387b + return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); +} + ++static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dacplus", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match); ++ +static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { + .driver = { + .name = "snd-rpi-hifiberry-dacplus", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dacplus_of_match, + }, + .probe = snd_rpi_hifiberry_dacplus_probe, + .remove = snd_rpi_hifiberry_dacplus_remove, @@ -117955,10 +116518,10 @@ index 0000000..c63387b 2.5.0 -From 579b01fb88a32b5e29559f558dc374012c8e7b20 Mon Sep 17 00:00:00 2001 +From e1a0219eddb9732580155b2cb1f8d0e24421b9c3 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Mon, 4 Aug 2014 11:09:58 +0200 -Subject: [PATCH 11/78] Added driver for HiFiBerry Amp amplifier add-on board +Subject: [PATCH 11/59] Added driver for HiFiBerry Amp amplifier add-on board The driver contains a low-level hardware driver for the TAS5713 and the drivers for the Raspberry Pi I2S subsystem. @@ -118792,217 +117355,10 @@ index 0000000..8f019e0 2.5.0 -From ecb06ed18274b3b5b8bde803d875016a5c377439 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Mon, 13 Apr 2015 18:45:39 +0100 -Subject: [PATCH 12/78] Adding Device Tree support for some RPi audio cards - ---- - sound/soc/bcm/hifiberry_dac.c | 22 ++++++++++++++++++++++ - sound/soc/bcm/hifiberry_dacplus.c | 22 ++++++++++++++++++++++ - sound/soc/bcm/hifiberry_digi.c | 22 ++++++++++++++++++++++ - sound/soc/bcm/iqaudio-dac.c | 16 ++++++++++++++++ - sound/soc/codecs/pcm5102a.c | 7 +++++++ - 5 files changed, 89 insertions(+) - -diff --git a/sound/soc/bcm/hifiberry_dac.c b/sound/soc/bcm/hifiberry_dac.c -index 4b70b45..3ab0f47 100644 ---- a/sound/soc/bcm/hifiberry_dac.c -+++ b/sound/soc/bcm/hifiberry_dac.c -@@ -72,6 +72,21 @@ static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_hifiberry_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); - if (ret) - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -@@ -84,10 +99,17 @@ static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); - } - -+static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-dac", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match); -+ - static struct platform_driver snd_rpi_hifiberry_dac_driver = { - .driver = { - .name = "snd-hifiberry-dac", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_dac_of_match, - }, - .probe = snd_rpi_hifiberry_dac_probe, - .remove = snd_rpi_hifiberry_dac_remove, -diff --git a/sound/soc/bcm/hifiberry_dacplus.c b/sound/soc/bcm/hifiberry_dacplus.c -index c63387b..11e4f39 100644 ---- a/sound/soc/bcm/hifiberry_dacplus.c -+++ b/sound/soc/bcm/hifiberry_dacplus.c -@@ -90,6 +90,21 @@ static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_hifiberry_dacplus.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); - if (ret) - dev_err(&pdev->dev, -@@ -103,10 +118,17 @@ static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); - } - -+static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-dacplus", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match); -+ - static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { - .driver = { - .name = "snd-rpi-hifiberry-dacplus", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_dacplus_of_match, - }, - .probe = snd_rpi_hifiberry_dacplus_probe, - .remove = snd_rpi_hifiberry_dacplus_remove, -diff --git a/sound/soc/bcm/hifiberry_digi.c b/sound/soc/bcm/hifiberry_digi.c -index 92e9e46..80732b8 100644 ---- a/sound/soc/bcm/hifiberry_digi.c -+++ b/sound/soc/bcm/hifiberry_digi.c -@@ -173,6 +173,21 @@ static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_hifiberry_digi.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); - if (ret) - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -@@ -185,10 +200,17 @@ static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); - } - -+static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-digi", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match); -+ - static struct platform_driver snd_rpi_hifiberry_digi_driver = { - .driver = { - .name = "snd-hifiberry-digi", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_digi_of_match, - }, - .probe = snd_rpi_hifiberry_digi_probe, - .remove = snd_rpi_hifiberry_digi_remove, -diff --git a/sound/soc/bcm/iqaudio-dac.c b/sound/soc/bcm/iqaudio-dac.c -index aff7377..a38e874 100644 ---- a/sound/soc/bcm/iqaudio-dac.c -+++ b/sound/soc/bcm/iqaudio-dac.c -@@ -82,6 +82,21 @@ static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_iqaudio_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); - if (ret) - dev_err(&pdev->dev, -@@ -99,6 +114,7 @@ static const struct of_device_id iqaudio_of_match[] = { - { .compatible = "iqaudio,iqaudio-dac", }, - {}, - }; -+MODULE_DEVICE_TABLE(of, iqaudio_of_match); - - static struct platform_driver snd_rpi_iqaudio_dac_driver = { - .driver = { -diff --git a/sound/soc/codecs/pcm5102a.c b/sound/soc/codecs/pcm5102a.c -index 126f1e9..7c6598e 100644 ---- a/sound/soc/codecs/pcm5102a.c -+++ b/sound/soc/codecs/pcm5102a.c -@@ -47,12 +47,19 @@ static int pcm5102a_remove(struct platform_device *pdev) - return 0; - } - -+static const struct of_device_id pcm5102a_of_match[] = { -+ { .compatible = "ti,pcm5102a", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, pcm5102a_of_match); -+ - static struct platform_driver pcm5102a_codec_driver = { - .probe = pcm5102a_probe, - .remove = pcm5102a_remove, - .driver = { - .name = "pcm5102a-codec", - .owner = THIS_MODULE, -+ .of_match_table = pcm5102a_of_match, - }, - }; - --- -2.5.0 - - -From f6dc4c1a7653c72b5a61cf01a66bd808bb7ce9bf Mon Sep 17 00:00:00 2001 +From 9491a7d6109f4ad61e1db014d5611c13232bfd65 Mon Sep 17 00:00:00 2001 From: Ryan Coe Date: Sat, 31 Jan 2015 18:25:49 -0700 -Subject: [PATCH 13/78] Update ds1307 driver for device-tree support +Subject: [PATCH 12/59] Update ds1307 driver for device-tree support Signed-off-by: Ryan Coe --- @@ -119032,10 +117388,10 @@ index aa705bb..1cb13fee 100644 2.5.0 -From 139c3996ad232a112b2d6a2773c1341309ddd6d9 Mon Sep 17 00:00:00 2001 +From f7704ed8c0ebb3eb5d4efc203afc58aab6642a2f Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 6 Feb 2015 13:50:57 +0000 -Subject: [PATCH 14/78] BCM270x_DT: Add pwr_led, and the required "input" +Subject: [PATCH 13/59] BCM270x_DT: Add pwr_led, and the required "input" trigger The "input" trigger makes the associated GPIO an input. This is to support @@ -119217,10 +117573,10 @@ index fa359c7..4b25a1a 100644 2.5.0 -From e2d77dbce08baa82a4d25727515bc231771a72fc Mon Sep 17 00:00:00 2001 +From 8a1b126dd7b96658a58c6fcb448599a329b0c681 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 27 Feb 2015 15:10:24 +0000 -Subject: [PATCH 15/78] enc28j60: Add device tree compatible string and an +Subject: [PATCH 14/59] enc28j60: Add device tree compatible string and an overlay --- @@ -119252,10 +117608,10 @@ index 86ea17e..a1b20c1 100644 2.5.0 -From 5192b386aa9768cc4f0dadb4bb76ed1cd84c82d6 Mon Sep 17 00:00:00 2001 +From dad0f756f15b857a690cd400a57967f1ea17ec51 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Wed, 25 Mar 2015 09:26:17 +0100 -Subject: [PATCH 16/78] Add driver for rpi-proto +Subject: [PATCH 15/59] Add driver for rpi-proto Forward port of 3.10.x driver from https://github.com/koalo We are using a custom board and would like to use rpi 3.18.x @@ -119473,105 +117829,24 @@ index 0000000..c6e45a0 2.5.0 -From e1a61c1a1dd0b2612e3b5259737b36df4e062e43 Mon Sep 17 00:00:00 2001 -From: Clive Messer -Date: Thu, 2 Apr 2015 12:22:55 +0100 -Subject: [PATCH 17/78] Add Device Tree support for RPi-DAC. - ---- - sound/soc/bcm/rpi-dac.c | 21 +++++++++++++++++++++ - sound/soc/codecs/pcm1794a.c | 7 +++++++ - 2 files changed, 28 insertions(+) - -diff --git a/sound/soc/bcm/rpi-dac.c b/sound/soc/bcm/rpi-dac.c -index 6d6e0ba..d5fac1b 100644 ---- a/sound/soc/bcm/rpi-dac.c -+++ b/sound/soc/bcm/rpi-dac.c -@@ -69,6 +69,20 @@ static int snd_rpi_rpi_dac_probe(struct platform_device *pdev) - int ret = 0; - - snd_rpi_rpi_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ - ret = snd_soc_register_card(&snd_rpi_rpi_dac); - if (ret) - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -@@ -81,10 +95,17 @@ static int snd_rpi_rpi_dac_remove(struct platform_device *pdev) - return snd_soc_unregister_card(&snd_rpi_rpi_dac); - } - -+static const struct of_device_id snd_rpi_rpi_dac_of_match[] = { -+ { .compatible = "rpi,rpi-dac", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match); -+ - static struct platform_driver snd_rpi_rpi_dac_driver = { - .driver = { - .name = "snd-rpi-dac", - .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_rpi_dac_of_match, - }, - .probe = snd_rpi_rpi_dac_probe, - .remove = snd_rpi_rpi_dac_remove, -diff --git a/sound/soc/codecs/pcm1794a.c b/sound/soc/codecs/pcm1794a.c -index b4eaa44..afe1b41 100644 ---- a/sound/soc/codecs/pcm1794a.c -+++ b/sound/soc/codecs/pcm1794a.c -@@ -46,12 +46,19 @@ static int pcm1794a_remove(struct platform_device *pdev) - return 0; - } - -+static const struct of_device_id pcm1794a_of_match[] = { -+ { .compatible = "ti,pcm1794a", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, pcm1794a_of_match); -+ - static struct platform_driver pcm1794a_codec_driver = { - .probe = pcm1794a_probe, - .remove = pcm1794a_remove, - .driver = { - .name = "pcm1794a-codec", - .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(pcm1794a_of_match), - }, - }; - --- -2.5.0 - - -From 8564222053484a291b2e4c5db6c87fd09399c624 Mon Sep 17 00:00:00 2001 +From f83d2eae29ba396b02e1d1db4f7641c63a22e1ad Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 13 Apr 2015 17:16:29 +0100 -Subject: [PATCH 18/78] config: Add default configs +Subject: [PATCH 16/59] config: Add default configs --- - arch/arm/configs/bcm2709_defconfig | 1245 ++++++++++++++++++++++++++++++++++++ - arch/arm/configs/bcmrpi_defconfig | 1241 +++++++++++++++++++++++++++++++++++ - 2 files changed, 2486 insertions(+) + arch/arm/configs/bcm2709_defconfig | 1255 ++++++++++++++++++++++++++++++++++++ + arch/arm/configs/bcmrpi_defconfig | 1251 +++++++++++++++++++++++++++++++++++ + 2 files changed, 2506 insertions(+) create mode 100644 arch/arm/configs/bcm2709_defconfig create mode 100644 arch/arm/configs/bcmrpi_defconfig diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig new file mode 100644 -index 0000000..152e577 +index 0000000..f5c5e87 --- /dev/null +++ b/arch/arm/configs/bcm2709_defconfig -@@ -0,0 +1,1245 @@ +@@ -0,0 +1,1255 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_PHYS_OFFSET=0 +CONFIG_LOCALVERSION="-v7" @@ -119858,6 +118133,9 @@ index 0000000..152e577 +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m @@ -120104,6 +118382,9 @@ index 0000000..152e577 +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_JOYDEV=m @@ -120120,6 +118401,7 @@ index 0000000..152e577 +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_FT6236=m +CONFIG_TOUCHSCREEN_RPI_FT5406=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_STMPE=m @@ -120157,7 +118439,7 @@ index 0000000..152e577 +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2835=y +CONFIG_RAW_DRIVER=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m @@ -120415,6 +118697,7 @@ index 0000000..152e577 +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SOUND_PRIME=m +CONFIG_HIDRAW=y ++CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m @@ -120671,6 +118954,7 @@ index 0000000..152e577 +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_KFIFO_BUF=m ++CONFIG_MCP320X=m +CONFIG_DHT11=m +CONFIG_PWM_BCM2835=m +CONFIG_RASPBERRYPI_FIRMWARE=y @@ -120811,6 +119095,7 @@ index 0000000..152e577 +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=m @@ -120819,10 +119104,10 @@ index 0000000..152e577 +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig new file mode 100644 -index 0000000..0e47844 +index 0000000..c7d31e8 --- /dev/null +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -0,0 +1,1241 @@ +@@ -0,0 +1,1251 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_PHYS_OFFSET=0 +# CONFIG_LOCALVERSION_AUTO is not set @@ -121102,6 +119387,9 @@ index 0000000..0e47844 +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_ATALK=m +CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m @@ -121348,6 +119636,9 @@ index 0000000..0e47844 +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_JOYDEV=m @@ -121364,6 +119655,7 @@ index 0000000..0e47844 +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_FT6236=m +CONFIG_TOUCHSCREEN_RPI_FT5406=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_STMPE=m @@ -121401,7 +119693,7 @@ index 0000000..0e47844 +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2835=y +CONFIG_RAW_DRIVER=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m @@ -121659,6 +119951,7 @@ index 0000000..0e47844 +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SOUND_PRIME=m +CONFIG_HIDRAW=y ++CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m @@ -121915,6 +120208,7 @@ index 0000000..0e47844 +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_KFIFO_BUF=m ++CONFIG_MCP320X=m +CONFIG_DHT11=m +CONFIG_PWM_BCM2835=m +CONFIG_RASPBERRYPI_FIRMWARE=y @@ -122058,6 +120352,7 @@ index 0000000..0e47844 +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM=m @@ -122068,10 +120363,10 @@ index 0000000..0e47844 2.5.0 -From 3289e2125e8875ad5327a3ecf7ff7d6916841c99 Mon Sep 17 00:00:00 2001 +From 4a03e3e11c4576e0b94a0e6c8e4dd676140d6120 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= Date: Wed, 29 Apr 2015 17:24:02 +0200 -Subject: [PATCH 19/78] bcm2835: bcm2835_defconfig +Subject: [PATCH 17/59] bcm2835: bcm2835_defconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -123500,10 +121795,10 @@ index 31cb073..fdb2e2a 100644 2.5.0 -From 6ba8f0f4387371066f85d6bc576aec6468ef12e3 Mon Sep 17 00:00:00 2001 +From 9a3fd91c18be1eda26a0637ce6b905c75d6f67e2 Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Tue, 12 May 2015 14:47:56 +0100 -Subject: [PATCH 20/78] rpi-ft5406: Add touchscreen driver for pi LCD display +Subject: [PATCH 18/59] rpi-ft5406: Add touchscreen driver for pi LCD display Fix driver detection failure Check that the buffer response is non-zero meaning the touchscreen was detected @@ -123547,7 +121842,7 @@ index cbaa6ab..13ab8c0 100644 obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o diff --git a/drivers/input/touchscreen/rpi-ft5406.c b/drivers/input/touchscreen/rpi-ft5406.c new file mode 100644 -index 0000000..c08817e +index 0000000..b27dbee --- /dev/null +++ b/drivers/input/touchscreen/rpi-ft5406.c @@ -0,0 +1,246 @@ @@ -123618,7 +121913,7 @@ index 0000000..c08817e + while(!kthread_should_stop()) + { + // 60fps polling -+ msleep(17); ++ msleep_interruptible(17); + memcpy_fromio(®s, ts->regs, sizeof(*ts->regs)); + writel(99, &ts->regs->num_points); + // Do not output if theres no new information (num_points is 99) @@ -123801,10 +122096,10 @@ index 0000000..c08817e 2.5.0 -From 147e4cdb102b5cb7e607437f0accc4ee0d723b6a Mon Sep 17 00:00:00 2001 +From 1fb6da46a439a109415dea3ae8967e5b55186303 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 13 Oct 2014 11:47:53 +0100 -Subject: [PATCH 21/78] Improve __copy_to_user and __copy_from_user performance +Subject: [PATCH 19/59] Improve __copy_to_user and __copy_from_user performance Provide a __copy_from_user that uses memcpy. On BCM2708, use optimised memcpy/memmove/memcmp/memset implementations. @@ -123851,7 +122146,7 @@ index cf4f3aa..9fe7780 100644 #define memset(p,v,n) \ diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h -index 8cc85a4..21ec2fc 100644 +index 35c9db8..52d3401 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -493,6 +493,9 @@ do { \ @@ -125191,7 +123486,7 @@ index 0000000..7067415 +ENDPROC(memset) +ENDPROC(mmioset) diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c -index d72b909..a6d8276 100644 +index 588bbc2..c29df92 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -22,6 +22,14 @@ @@ -125254,8 +123549,8 @@ index d72b909..a6d8276 100644 +unsigned long noinline __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) { - int atomic; -@@ -135,6 +180,54 @@ out: + unsigned long ua_flags; +@@ -138,6 +183,54 @@ out: return n; } @@ -125310,14 +123605,18 @@ index d72b909..a6d8276 100644 unsigned long arm_copy_to_user(void __user *to, const void *from, unsigned long n) { -@@ -145,10 +238,25 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) +@@ -148,7 +241,7 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) * With frame pointer disabled, tail call optimization kicks in * as well making this test almost invisible. */ -- if (n < 64) -+ if (n < COPY_TO_USER_THRESHOLD) - return __copy_to_user_std(to, from, n); - return __copy_to_user_memcpy(to, from, n); +- if (n < 64) { ++ if (n < COPY_TO_USER_THRESHOLD) { + unsigned long ua_flags = uaccess_save_and_enable(); + n = __copy_to_user_std(to, from, n); + uaccess_restore(ua_flags); +@@ -157,6 +250,21 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) + } + return n; } + +unsigned long __must_check @@ -125341,87 +123640,10 @@ index d72b909..a6d8276 100644 2.5.0 -From a91bc4e81f434b62b5f74d959654fb574c600e0f Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 16 Jun 2015 17:47:27 +0100 -Subject: [PATCH 22/78] platform: Add force_core command line setting to boot - from a different core number - ---- - arch/arm/mach-bcm2709/armctrl.c | 17 ++++++++++++++++- - arch/arm/mach-bcm2709/bcm2709.c | 2 ++ - 2 files changed, 18 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -index c6f68b4..fb82f7d 100644 ---- a/arch/arm/mach-bcm2709/armctrl.c -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -45,6 +45,8 @@ static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { - INTERRUPT_VC_ARASANSDIO - }; - -+extern unsigned force_core; -+ - static void armctrl_mask_irq(struct irq_data *d) - { - static const unsigned int disables[4] = { -@@ -92,7 +94,13 @@ static void armctrl_unmask_irq(struct irq_data *d) - int i; - if (d->irq >= FIQ_START) { - unsigned int data; -- if (num_online_cpus() > 1) { -+ if (force_core) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= ((force_core-1) << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ else if (num_online_cpus() > 1) { - data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); - data &= ~0xc; - data |= (1 << 2); -@@ -119,6 +127,13 @@ static void armctrl_unmask_irq(struct irq_data *d) - } - #endif - } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ if (force_core) { -+ unsigned int data; -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0x3; -+ data |= ((force_core-1) << 0); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } - unsigned int data = (unsigned int)irq_get_chip_data(d->irq); - writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); - } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c -index 3eeeb886..cbcf731 100644 ---- a/arch/arm/mach-bcm2709/bcm2709.c -+++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -56,6 +56,7 @@ - /* command line parameters */ - static unsigned boardrev, serial; - static unsigned reboot_part = 0; -+unsigned force_core; - - void __init bcm2709_init_irq(void) - { -@@ -534,6 +535,7 @@ MACHINE_START(BCM2708, "BCM2709") - .dt_compat = bcm2709_compat, - MACHINE_END - -+module_param(force_core, uint, 0644); - module_param(boardrev, uint, 0644); - module_param(serial, uint, 0644); - module_param(reboot_part, uint, 0644); --- -2.5.0 - - -From 66bff3777e1bf5b556a30e782432dce3cf5e234e Mon Sep 17 00:00:00 2001 +From e8f7622b797353eb01277b988f5dcb01d4281762 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 25 Jun 2015 12:16:11 +0100 -Subject: [PATCH 23/78] gpio-poweroff: Allow it to work on Raspberry Pi +Subject: [PATCH 20/59] gpio-poweroff: Allow it to work on Raspberry Pi The Raspberry Pi firmware manages the power-down and reboot process. To do this it installs a pm_power_off handler, causing @@ -125459,10 +123681,10 @@ index be3d81f..a030ae9 100644 2.5.0 -From 6b5b53f993acf7132d9ebd2c15b71c1eb5470686 Mon Sep 17 00:00:00 2001 +From 8c8f50a7ed38607026f7d987f9ca2b589d2f0187 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 14 Jul 2015 10:26:09 +0100 -Subject: [PATCH 24/78] spidev: Add "spidev" compatible string to silence +Subject: [PATCH 21/59] spidev: Add "spidev" compatible string to silence warning See: https://github.com/raspberrypi/linux/issues/1054 @@ -125471,7 +123693,7 @@ See: https://github.com/raspberrypi/linux/issues/1054 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c -index 91a0fcd..241b7bf 100644 +index d0e7dfc..57b0760 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -695,6 +695,7 @@ static struct class *spidev_class; @@ -125486,10 +123708,10 @@ index 91a0fcd..241b7bf 100644 2.5.0 -From 7c72afc6111aaa4d679c5fb8a8510069e2b0ee0b Mon Sep 17 00:00:00 2001 +From 3f7779b380bd473670d38dd4ff3d6513ec1a89c2 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 14 Jul 2015 17:00:18 +0100 -Subject: [PATCH 25/78] scripts/dtc: Add overlay support +Subject: [PATCH 22/59] scripts/dtc: Add overlay support --- scripts/dtc/checks.c | 119 ++- @@ -129897,10 +128119,10 @@ index 5b8c7d5..86b7338 100644 2.5.0 -From 3d24dd7bf0d39e19decd21fb842498b45d88cd89 Mon Sep 17 00:00:00 2001 +From 74fb644989dfc1101e5ddca287ce58b8b5f41c79 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 14 Jul 2015 14:32:47 +0100 -Subject: [PATCH 26/78] Merge pull request #1043 from XECDesign/sense-4.0 +Subject: [PATCH 23/59] Merge pull request #1043 from XECDesign/sense-4.0 mfd: Add Raspberry Pi Sense HAT core driver --- @@ -130770,10 +128992,10 @@ index 0000000..56196dc 2.5.0 -From 3a0e5391bd98674d1191359af4be716d9fd5d494 Mon Sep 17 00:00:00 2001 +From c403980d1dddcb1c9eb149e6bda2a8057f4f859c Mon Sep 17 00:00:00 2001 From: Jan Grulich Date: Mon, 24 Aug 2015 16:03:47 +0100 -Subject: [PATCH 27/78] RaspiDAC3 support +Subject: [PATCH 24/59] RaspiDAC3 support Signed-off-by: Jan Grulich @@ -130825,7 +129047,7 @@ index 4f5ab1f..b21e11e 100644 +obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o diff --git a/sound/soc/bcm/raspidac3.c b/sound/soc/bcm/raspidac3.c new file mode 100644 -index 0000000..fddaeec +index 0000000..3cabf5b --- /dev/null +++ b/sound/soc/bcm/raspidac3.c @@ -0,0 +1,191 @@ @@ -130870,7 +129092,7 @@ index 0000000..fddaeec + snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02); + snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); + -+ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207); + if (ret < 0) + dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); + else { @@ -130880,7 +129102,7 @@ index 0000000..fddaeec + if (ret < 0) + dev_warn(card->dev, "Failed to add TPA6130A2 controls: %d\n", + ret); -+ ret = snd_soc_limit_volume(codec, ++ ret = snd_soc_limit_volume(card, + "TPA6130A2 Headphone Playback Volume", + 54); + if (ret < 0) @@ -131024,10 +129246,10 @@ index 0000000..fddaeec 2.5.0 -From 69d4790c40897d0fddc52fc71e24dd767556df42 Mon Sep 17 00:00:00 2001 +From f1244f1b3c28e2bbf6fcb7887cd2353c19be1ece Mon Sep 17 00:00:00 2001 From: Jan Grulich Date: Mon, 24 Aug 2015 16:02:34 +0100 -Subject: [PATCH 28/78] tpa6130a2: Add headphone switch control +Subject: [PATCH 25/59] tpa6130a2: Add headphone switch control Signed-off-by: Jan Grulich --- @@ -131121,20 +129343,20 @@ index 11d85c5..3caaa17 100644 2.5.0 -From 49ccce76c0a6fe54c89d2eadcb90b6474f3c1342 Mon Sep 17 00:00:00 2001 +From 4e237ee42e13fd4c1c2b1dd65d8f0ad58f4d601c Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 28 Sep 2015 23:38:59 +0100 -Subject: [PATCH 29/78] irq-bcm2835: Fix building with 2708 +Subject: [PATCH 26/59] irq-bcm2835: Fix building with 2708 --- drivers/irqchip/irq-bcm2835.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c -index 3f601f9..3478e75 100644 +index 20deb28..c02bf8a 100644 --- a/drivers/irqchip/irq-bcm2835.c +++ b/drivers/irqchip/irq-bcm2835.c -@@ -77,6 +77,7 @@ +@@ -82,6 +82,7 @@ #define NR_BANKS 3 #define IRQS_PER_BANK 32 #define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0) @@ -131142,7 +129364,7 @@ index 3f601f9..3478e75 100644 #define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0)) static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 }; -@@ -218,7 +219,7 @@ static int __init armctrl_of_init(struct device_node *node, +@@ -256,7 +257,7 @@ static int __init armctrl_of_init(struct device_node *node, MAKE_HWIRQ(b, i) + NUMBER_IRQS); BUG_ON(irq <= 0); irq_set_chip(irq, &armctrl_chip); @@ -131155,10 +129377,10 @@ index 3f601f9..3478e75 100644 2.5.0 -From fdedc022ee2498d3dd3dc3f3511a8a5ab5f1d0fc Mon Sep 17 00:00:00 2001 +From 256a8a32c69b5eeede30f5eb6674e7e2f4d5d50b Mon Sep 17 00:00:00 2001 From: P33M Date: Wed, 21 Oct 2015 14:55:21 +0100 -Subject: [PATCH 30/78] rpi_display: add backlight driver and overlay +Subject: [PATCH 27/59] rpi_display: add backlight driver and overlay Add a mailbox-driven backlight controller for the Raspberry Pi DSI touchscreen display. Requires updated GPU firmware to recognise the @@ -131192,10 +129414,10 @@ index d8c2771..fb7ac49 100644 dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index d8d0a51..fdefff1 100644 +index 44e33a4..b819293 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README -@@ -463,6 +463,12 @@ Load: dtoverlay=raspidac3 +@@ -462,6 +462,12 @@ Load: dtoverlay=raspidac3 Params: @@ -131236,10 +129458,10 @@ index 0000000..c021d02 + }; +}; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 152e577..3ec59d2 100644 +index f5c5e87..38e46ac 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig -@@ -801,6 +801,7 @@ CONFIG_FB_UDL=m +@@ -808,6 +808,7 @@ CONFIG_FB_UDL=m CONFIG_FB_SSD1307=m CONFIG_FB_RPISENSE=m # CONFIG_BACKLIGHT_GENERIC is not set @@ -131248,10 +129470,10 @@ index 152e577..3ec59d2 100644 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 0e47844..0f69adb 100644 +index c7d31e8..436da55 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -794,6 +794,7 @@ CONFIG_FB_UDL=m +@@ -801,6 +801,7 @@ CONFIG_FB_UDL=m CONFIG_FB_SSD1307=m CONFIG_FB_RPISENSE=m # CONFIG_BACKLIGHT_GENERIC is not set @@ -131429,20 +129651,20 @@ index 525816d..b011489 100644 2.5.0 -From 2bc2902a664d66f4eeb83bb94d55e45d2e00e1fa Mon Sep 17 00:00:00 2001 +From 4597458b3521c98d3260ed9a4eb739e6a6b5713c Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Mon, 16 Nov 2015 14:05:35 +0000 -Subject: [PATCH 31/78] bcm2835-dma: Fix up convert to DMA pool +Subject: [PATCH 28/59] bcm2835-dma: Fix up convert to DMA pool --- drivers/dma/bcm2835-dma.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 58a96a6..3cf5a88 100644 +index 0adc347..985019b 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c -@@ -491,6 +491,17 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -488,6 +488,17 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( c->cyclic = true; return vchan_tx_prep(&c->vc, &d->vd, flags); @@ -131460,7 +129682,7 @@ index 58a96a6..3cf5a88 100644 } static struct dma_async_tx_descriptor * -@@ -537,6 +548,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -534,6 +545,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, if (!d) return NULL; @@ -131468,7 +129690,7 @@ index 58a96a6..3cf5a88 100644 d->dir = direction; if (c->ch >= 8) /* LITE channel */ -@@ -556,15 +568,21 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -553,15 +565,21 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, d->frames += len / max_size + 1; } @@ -131496,16 +129718,16 @@ index 58a96a6..3cf5a88 100644 /* * Iterate over all SG entries, create a control block -@@ -582,7 +600,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -578,7 +596,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, + for (j = 0; j < len; j += max_size) { - u32 waits; struct bcm2835_dma_cb *control_block = - &d->control_block_base[i + split_cnt]; + d->cb_list[i + split_cnt].cb; /* Setup addresses */ if (d->dir == DMA_DEV_TO_MEM) { -@@ -626,9 +644,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, +@@ -620,9 +638,7 @@ bcm2835_dma_prep_slave_sg(struct dma_chan *chan, if (i < sg_len - 1 || len - j > max_size) { /* Next block is the next frame. */ control_block->next = @@ -131520,1913 +129742,10 @@ index 58a96a6..3cf5a88 100644 2.5.0 -From 55dc4c597e9ec35aab1153ceb88334e285f0923a Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Mon, 16 Nov 2015 21:32:15 +0000 -Subject: [PATCH 32/78] squash: Fixup bcm2835-camera for changes in kernel 4.4 - api - ---- - drivers/media/platform/bcm2835/bcm2835-camera.c | 33 +++++++++++++------------ - drivers/media/platform/bcm2835/mmal-common.h | 2 +- - 2 files changed, 18 insertions(+), 17 deletions(-) - -diff --git a/drivers/media/platform/bcm2835/bcm2835-camera.c b/drivers/media/platform/bcm2835/bcm2835-camera.c -index dfd22d4..e83334c 100644 ---- a/drivers/media/platform/bcm2835/bcm2835-camera.c -+++ b/drivers/media/platform/bcm2835/bcm2835-camera.c -@@ -320,7 +320,7 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - /* error in transfer */ - if (buf != NULL) { - /* there was a buffer with the error so return it */ -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - } - return; - } else if (length == 0) { -@@ -329,7 +329,7 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - /* this should only ever happen if the port is - * disabled and there are buffers still queued - */ -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - pr_debug("Empty buffer"); - } else if (dev->capture.frame_count) { - /* grab another frame */ -@@ -359,16 +359,16 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - - div = - div_u64_rem(runtime_us, USEC_PER_SEC, &rem); -- buf->vb.v4l2_buf.timestamp.tv_sec = -+ buf->vb.timestamp.tv_sec = - dev->capture.kernel_start_ts.tv_sec - 1 + - div; -- buf->vb.v4l2_buf.timestamp.tv_usec = -+ buf->vb.timestamp.tv_usec = - dev->capture.kernel_start_ts.tv_usec + rem; - -- if (buf->vb.v4l2_buf.timestamp.tv_usec >= -+ if (buf->vb.timestamp.tv_usec >= - USEC_PER_SEC) { -- buf->vb.v4l2_buf.timestamp.tv_sec++; -- buf->vb.v4l2_buf.timestamp.tv_usec -= -+ buf->vb.timestamp.tv_sec++; -+ buf->vb.timestamp.tv_usec -= - USEC_PER_SEC; - } - v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -@@ -379,15 +379,15 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - (int)dev->capture.kernel_start_ts. - tv_usec, - dev->capture.vc_start_timestamp, pts, -- (int)buf->vb.v4l2_buf.timestamp.tv_sec, -- (int)buf->vb.v4l2_buf.timestamp. -+ (int)buf->vb.timestamp.tv_sec, -+ (int)buf->vb.timestamp. - tv_usec); - } else { -- v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); -+ v4l2_get_timestamp(&buf->vb.timestamp); - } - -- vb2_set_plane_payload(&buf->vb, 0, length); -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); -+ vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); - - if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS && - is_capturing(dev)) { -@@ -404,7 +404,7 @@ static void buffer_cb(struct vchiq_mmal_instance *instance, - } - } else { - /* signal frame completion */ -- vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - complete(&dev->capture.frame_cmplt); - } - } -@@ -466,14 +466,15 @@ static int disable_camera(struct bm2835_mmal_dev *dev) - static void buffer_queue(struct vb2_buffer *vb) - { - struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); -- struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb); -+ struct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb); -+ struct mmal_buffer *buf = container_of(vb2, struct mmal_buffer, vb); - int ret; - - v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, - "%s: dev:%p buf:%p\n", __func__, dev, buf); - -- buf->buffer = vb2_plane_vaddr(&buf->vb, 0); -- buf->buffer_size = vb2_plane_size(&buf->vb, 0); -+ buf->buffer = vb2_plane_vaddr(&buf->vb.vb2_buf, 0); -+ buf->buffer_size = vb2_plane_size(&buf->vb.vb2_buf, 0); - - ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf); - if (ret < 0) -diff --git a/drivers/media/platform/bcm2835/mmal-common.h b/drivers/media/platform/bcm2835/mmal-common.h -index 15788a1..840fd13 100644 ---- a/drivers/media/platform/bcm2835/mmal-common.h -+++ b/drivers/media/platform/bcm2835/mmal-common.h -@@ -36,7 +36,7 @@ struct mmal_fmt { - /* buffer for one video frame */ - struct mmal_buffer { - /* v4l buffer data -- must be first */ -- struct vb2_buffer vb; -+ struct vb2_v4l2_buffer vb; - - /* list of buffers available */ - struct list_head list; --- -2.5.0 - - -From c3dcfae142657d6f7eb58b7c03327cad744e7e52 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 17 Nov 2015 18:52:58 +0000 -Subject: [PATCH 33/78] BCM2709: Use upstream interrupt driver on all Pi2's - ---- - arch/arm/Kconfig | 2 + - arch/arm/mach-bcm2709/Makefile | 2 +- - arch/arm/mach-bcm2709/armctrl.c | 384 ------------------ - arch/arm/mach-bcm2709/armctrl.h | 27 -- - arch/arm/mach-bcm2709/bcm2709.c | 167 +------- - arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 ----------------------- - arch/arm/mach-bcm2709/include/mach/hardware.h | 28 -- - arch/arm/mach-bcm2709/include/mach/irqs.h | 225 ----------- - arch/arm/mach-bcm2709/include/mach/platform.h | 189 ++++----- - arch/arm/mach-bcm2709/include/mach/system.h | 1 - - arch/arm/mach-bcm2709/include/mach/uncompress.h | 2 +- - drivers/irqchip/Makefile | 1 + - 12 files changed, 84 insertions(+), 1437 deletions(-) - delete mode 100644 arch/arm/mach-bcm2709/armctrl.c - delete mode 100644 arch/arm/mach-bcm2709/armctrl.h - delete mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h - delete mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h - delete mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 3241611..601b520 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -351,6 +351,8 @@ config ARCH_BCM2709 - select ARCH_HAS_CPUFREQ - select GENERIC_CLOCKEVENTS - select MACH_BCM2709 -+ select MULTI_IRQ_HANDLER -+ select SPARSE_IRQ - select VC4 - select FIQ - select USE_OF -diff --git a/arch/arm/mach-bcm2709/Makefile b/arch/arm/mach-bcm2709/Makefile -index 11ad846..26cd67d 100644 ---- a/arch/arm/mach-bcm2709/Makefile -+++ b/arch/arm/mach-bcm2709/Makefile -@@ -2,4 +2,4 @@ - # Makefile for the linux kernel. - # - --obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o -+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -deleted file mode 100644 -index fb82f7d..0000000 ---- a/arch/arm/mach-bcm2709/armctrl.c -+++ /dev/null -@@ -1,384 +0,0 @@ --/* -- * linux/arch/arm/mach-bcm2708/armctrl.c -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ --#include --#include --#include --#include --#include --#include --#include --#include -- --#include --#include --#include "armctrl.h" -- --/* For support of kernels >= 3.0 assume only one VIC for now*/ --static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -- INTERRUPT_VC_JPEG, -- INTERRUPT_VC_USB, -- INTERRUPT_VC_3D, -- INTERRUPT_VC_DMA2, -- INTERRUPT_VC_DMA3, -- INTERRUPT_VC_I2C, -- INTERRUPT_VC_SPI, -- INTERRUPT_VC_I2SPCM, -- INTERRUPT_VC_SDIO, -- INTERRUPT_VC_UART, -- INTERRUPT_VC_ARASANSDIO --}; -- --extern unsigned force_core; -- --static void armctrl_mask_irq(struct irq_data *d) --{ -- static const unsigned int disables[4] = { -- ARM_IRQ_DIBL1, -- ARM_IRQ_DIBL2, -- ARM_IRQ_DIBL3, -- 0 -- }; -- int i; -- if (d->irq >= FIQ_START) { -- writel(0, __io_address(ARM_IRQ_FAST)); -- } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { --#if 1 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -- for (i=0; i<4; i++) // i = raw_smp_processor_id(); // -- { -- unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { --#if 0 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -- for (i=0; i<4; i++) { -- unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -- writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -- } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -- writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); -- } else { printk("%s: %d\n", __func__, d->irq); BUG(); } --} -- --static void armctrl_unmask_irq(struct irq_data *d) --{ -- static const unsigned int enables[4] = { -- ARM_IRQ_ENBL1, -- ARM_IRQ_ENBL2, -- ARM_IRQ_ENBL3, -- 0 -- }; -- int i; -- if (d->irq >= FIQ_START) { -- unsigned int data; -- if (force_core) { -- data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- data &= ~0xc; -- data |= ((force_core-1) << 2); -- writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- } -- else if (num_online_cpus() > 1) { -- data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- data &= ~0xc; -- data |= (1 << 2); -- writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- } -- /* Unmask in ARMCTRL block after routing it properly */ -- data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -- writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -- } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { --#if 1 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -- for (i=0; i<4; i++) // i = raw_smp_processor_id(); -- { -- unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { --#if 0 -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -- for (i=0; i<4; i++) { -- unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -- } --#endif -- } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -- if (force_core) { -- unsigned int data; -- data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- data &= ~0x3; -- data |= ((force_core-1) << 0); -- writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -- } -- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -- writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -- } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -- writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); -- } else { printk("%s: %d\n", __func__, d->irq); BUG(); } --} -- --#ifdef CONFIG_OF -- --#define NR_IRQS_BANK0 21 --#define NR_BANKS 4 --#define IRQS_PER_BANK 32 -- --/* from drivers/irqchip/irq-bcm2835.c */ --static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -- const u32 *intspec, unsigned int intsize, -- unsigned long *out_hwirq, unsigned int *out_type) --{ -- if (WARN_ON(intsize != 2)) -- return -EINVAL; -- -- if (WARN_ON(intspec[0] >= NR_BANKS)) -- return -EINVAL; -- -- if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -- return -EINVAL; -- -- if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -- return -EINVAL; -- -- if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) -- return -EINVAL; -- -- if (intspec[0] == 0) -- *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -- else if (intspec[0] == 1) -- *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -- else if (intspec[0] == 2) -- *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -- else -- *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; -- -- /* reverse remap_irqs[] */ -- switch (*out_hwirq) { -- case INTERRUPT_VC_JPEG: -- *out_hwirq = INTERRUPT_JPEG; -- break; -- case INTERRUPT_VC_USB: -- *out_hwirq = INTERRUPT_USB; -- break; -- case INTERRUPT_VC_3D: -- *out_hwirq = INTERRUPT_3D; -- break; -- case INTERRUPT_VC_DMA2: -- *out_hwirq = INTERRUPT_DMA2; -- break; -- case INTERRUPT_VC_DMA3: -- *out_hwirq = INTERRUPT_DMA3; -- break; -- case INTERRUPT_VC_I2C: -- *out_hwirq = INTERRUPT_I2C; -- break; -- case INTERRUPT_VC_SPI: -- *out_hwirq = INTERRUPT_SPI; -- break; -- case INTERRUPT_VC_I2SPCM: -- *out_hwirq = INTERRUPT_I2SPCM; -- break; -- case INTERRUPT_VC_SDIO: -- *out_hwirq = INTERRUPT_SDIO; -- break; -- case INTERRUPT_VC_UART: -- *out_hwirq = INTERRUPT_UART; -- break; -- case INTERRUPT_VC_ARASANSDIO: -- *out_hwirq = INTERRUPT_ARASANSDIO; -- break; -- } -- -- *out_type = IRQ_TYPE_NONE; -- return 0; --} -- --static struct irq_domain_ops armctrl_ops = { -- .xlate = armctrl_xlate --}; -- --void __init armctrl_dt_init(void) --{ -- struct device_node *np; -- struct irq_domain *domain; -- -- np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -- if (!np) -- return; -- -- domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -- IRQ_ARMCTRL_START, 0, -- &armctrl_ops, NULL); -- WARN_ON(!domain); --} --#else --void __init armctrl_dt_init(void) { } --#endif /* CONFIG_OF */ -- --#if defined(CONFIG_PM) -- --/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -- --/* Static defines -- * struct armctrl_device - VIC PM device (< 3.xx) -- * @sysdev: The system device which is registered. (< 3.xx) -- * @irq: The IRQ number for the base of the VIC. -- * @base: The register base for the VIC. -- * @resume_sources: A bitmask of interrupts for resume. -- * @resume_irqs: The IRQs enabled for resume. -- * @int_select: Save for VIC_INT_SELECT. -- * @int_enable: Save for VIC_INT_ENABLE. -- * @soft_int: Save for VIC_INT_SOFT. -- * @protect: Save for VIC_PROTECT. -- */ --struct armctrl_info { -- void __iomem *base; -- int irq; -- u32 resume_sources; -- u32 resume_irqs; -- u32 int_select; -- u32 int_enable; -- u32 soft_int; -- u32 protect; --} armctrl; -- --static int armctrl_suspend(void) --{ -- return 0; --} -- --static void armctrl_resume(void) --{ -- return; --} -- --/** -- * armctrl_pm_register - Register a VIC for later power management control -- * @base: The base address of the VIC. -- * @irq: The base IRQ for the VIC. -- * @resume_sources: bitmask of interrupts allowed for resume sources. -- * -- * For older kernels (< 3.xx) do - -- * Register the VIC with the system device tree so that it can be notified -- * of suspend and resume requests and ensure that the correct actions are -- * taken to re-instate the settings on resume. -- */ --static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -- u32 resume_sources) --{ -- armctrl.base = base; -- armctrl.resume_sources = resume_sources; -- armctrl.irq = irq; --} -- --static int armctrl_set_wake(struct irq_data *d, unsigned int on) --{ -- unsigned int off = d->irq & 31; -- u32 bit = 1 << off; -- -- if (!(bit & armctrl.resume_sources)) -- return -EINVAL; -- -- if (on) -- armctrl.resume_irqs |= bit; -- else -- armctrl.resume_irqs &= ~bit; -- -- return 0; --} -- --#else --static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -- u32 arg1) --{ --} -- --#define armctrl_suspend NULL --#define armctrl_resume NULL --#define armctrl_set_wake NULL --#endif /* CONFIG_PM */ -- --static struct syscore_ops armctrl_syscore_ops = { -- .suspend = armctrl_suspend, -- .resume = armctrl_resume, --}; -- --/** -- * armctrl_syscore_init - initicall to register VIC pm functions -- * -- * This is called via late_initcall() to register -- * the resources for the VICs due to the early -- * nature of the VIC's registration. --*/ --static int __init armctrl_syscore_init(void) --{ -- register_syscore_ops(&armctrl_syscore_ops); -- return 0; --} -- --late_initcall(armctrl_syscore_init); -- --static struct irq_chip armctrl_chip = { -- .name = "ARMCTRL", -- .irq_ack = NULL, -- .irq_mask = armctrl_mask_irq, -- .irq_unmask = armctrl_unmask_irq, -- .irq_set_wake = armctrl_set_wake, --}; -- --/** -- * armctrl_init - initialise a vectored interrupt controller -- * @base: iomem base address -- * @irq_start: starting interrupt number, must be muliple of 32 -- * @armctrl_sources: bitmask of interrupt sources to allow -- * @resume_sources: bitmask of interrupt sources to allow for resume -- */ --int __init armctrl_init(void __iomem * base, unsigned int irq_start, -- u32 armctrl_sources, u32 resume_sources) --{ -- unsigned int irq; -- -- for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -- unsigned int data = irq; -- if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -- data = remap_irqs[irq - INTERRUPT_JPEG]; -- if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { -- irq_set_percpu_devid(irq); -- irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); -- irq_set_status_flags(irq, IRQ_NOAUTOEN); -- } else { -- irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); -- irq_set_probe(irq); -- } -- irq_set_chip_data(irq, (void *)data); -- } -- -- armctrl_pm_register(base, irq_start, resume_sources); -- init_FIQ(FIQ_START); -- armctrl_dt_init(); -- return 0; --} -diff --git a/arch/arm/mach-bcm2709/armctrl.h b/arch/arm/mach-bcm2709/armctrl.h -deleted file mode 100644 -index 0aa916e..0000000 ---- a/arch/arm/mach-bcm2709/armctrl.h -+++ /dev/null -@@ -1,27 +0,0 @@ --/* -- * linux/arch/arm/mach-bcm2708/armctrl.h -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ -- --#ifndef __BCM2708_ARMCTRL_H --#define __BCM2708_ARMCTRL_H -- --extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -- u32 armctrl_sources, u32 resume_sources); -- --#endif -diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c -index cbcf731..90773a3 100644 ---- a/arch/arm/mach-bcm2709/bcm2709.c -+++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -28,20 +28,16 @@ - #include - - #include --#include - #include - #include - - #include - #include --#include - --#include "armctrl.h" -+#include - - #include - --//#define SYSTEM_TIMER -- - /* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to - * give us IO access only to 64Mbytes of physical memory (26 bits). We could - * represent this window by setting our dmamasks to 26 bits but, in fact -@@ -56,12 +52,6 @@ - /* command line parameters */ - static unsigned boardrev, serial; - static unsigned reboot_part = 0; --unsigned force_core; -- --void __init bcm2709_init_irq(void) --{ -- armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); --} - - static struct map_desc bcm2709_io_desc[] __initdata = { - { -@@ -121,54 +111,6 @@ void __init bcm2709_map_io(void) - iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); - } - --#ifdef SYSTEM_TIMER -- --/* The STC is a free running counter that increments at the rate of 1MHz */ --#define STC_FREQ_HZ 1000000 -- --static inline uint32_t timer_read(void) --{ -- /* STC: a free running counter that increments at the rate of 1MHz */ -- return readl(__io_address(ST_BASE + 0x04)); --} -- --static unsigned long bcm2709_read_current_timer(void) --{ -- return timer_read(); --} -- --static u64 notrace bcm2709_read_sched_clock(void) --{ -- return timer_read(); --} -- --static cycle_t clksrc_read(struct clocksource *cs) --{ -- return timer_read(); --} -- --static struct clocksource clocksource_stc = { -- .name = "stc", -- .rating = 300, -- .read = clksrc_read, -- .mask = CLOCKSOURCE_MASK(32), -- .flags = CLOCK_SOURCE_IS_CONTINUOUS, --}; -- --unsigned long frc_clock_ticks32(void) --{ -- return timer_read(); --} -- --static void __init bcm2709_clocksource_init(void) --{ -- if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -- printk(KERN_ERR "timer: failed to initialize clock " -- "source %s\n", clocksource_stc.name); -- } --} --#endif -- - int calc_rsts(int partition) - { - return PM_PASSWORD | -@@ -253,7 +195,8 @@ void __init bcm2709_init(void) - - pm_power_off = bcm2709_power_off; - -- ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, -+ NULL); - if (ret) { - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); -@@ -265,105 +208,6 @@ void __init bcm2709_init(void) - system_serial_low = serial; - } - --#ifdef SYSTEM_TIMER --static void timer_set_mode(enum clock_event_mode mode, -- struct clock_event_device *clk) --{ -- switch (mode) { -- case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -- case CLOCK_EVT_MODE_SHUTDOWN: -- break; -- case CLOCK_EVT_MODE_PERIODIC: -- -- case CLOCK_EVT_MODE_UNUSED: -- case CLOCK_EVT_MODE_RESUME: -- -- default: -- printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -- (int)mode); -- break; -- } -- --} -- --static int timer_set_next_event(unsigned long cycles, -- struct clock_event_device *unused) --{ -- unsigned long stc; -- do { -- stc = readl(__io_address(ST_BASE + 0x04)); -- /* We could take a FIQ here, which may push ST above STC3 */ -- writel(stc + cycles, __io_address(ST_BASE + 0x18)); -- } while ((signed long) cycles >= 0 && -- (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -- >= (signed long) cycles); -- return 0; --} -- --static struct clock_event_device timer0_clockevent = { -- .name = "timer0", -- .shift = 32, -- .features = CLOCK_EVT_FEAT_ONESHOT, -- .set_mode = timer_set_mode, -- .set_next_event = timer_set_next_event, --}; -- --/* -- * IRQ handler for the timer -- */ --static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) --{ -- struct clock_event_device *evt = &timer0_clockevent; -- -- writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -- -- evt->event_handler(evt); -- -- return IRQ_HANDLED; --} -- --static struct irqaction bcm2709_timer_irq = { -- .name = "BCM2709 Timer Tick", -- .flags = IRQF_TIMER | IRQF_IRQPOLL, -- .handler = bcm2709_timer_interrupt, --}; -- --/* -- * Set up timer interrupt, and return the current time in seconds. -- */ -- --static struct delay_timer bcm2709_delay_timer = { -- .read_current_timer = bcm2709_read_current_timer, -- .freq = STC_FREQ_HZ, --}; -- --static void __init bcm2709_timer_init(void) --{ -- /* init high res timer */ -- bcm2709_clocksource_init(); -- -- /* -- * Make irqs happen for the system timer -- */ -- setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); -- -- sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); -- -- timer0_clockevent.mult = -- div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -- timer0_clockevent.max_delta_ns = -- clockevent_delta2ns(0xffffffff, &timer0_clockevent); -- timer0_clockevent.min_delta_ns = -- clockevent_delta2ns(0xf, &timer0_clockevent); -- -- timer0_clockevent.cpumask = cpumask_of(0); -- clockevents_register_device(&timer0_clockevent); -- -- register_current_timer_delay(&bcm2709_delay_timer); --} -- --#else -- - static void __init bcm2709_timer_init(void) - { - // timer control -@@ -376,7 +220,6 @@ static void __init bcm2709_timer_init(void) - clocksource_probe(); - } - --#endif - - void __init bcm2709_init_early(void) - { -@@ -397,7 +240,6 @@ static void __init board_reserve(void) - #ifdef CONFIG_SMP - #include - --#include - #include - #include - int dc4=0; -@@ -511,7 +353,6 @@ MACHINE_START(BCM2709, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -- .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -526,7 +367,6 @@ MACHINE_START(BCM2708, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -- .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -535,7 +375,6 @@ MACHINE_START(BCM2708, "BCM2709") - .dt_compat = bcm2709_compat, - MACHINE_END - --module_param(force_core, uint, 0644); - module_param(boardrev, uint, 0644); - module_param(serial, uint, 0644); - module_param(reboot_part, uint, 0644); -diff --git a/arch/arm/mach-bcm2709/include/mach/arm_control.h b/arch/arm/mach-bcm2709/include/mach/arm_control.h -deleted file mode 100644 -index e346caf..0000000 ---- a/arch/arm/mach-bcm2709/include/mach/arm_control.h -+++ /dev/null -@@ -1,493 +0,0 @@ --/* -- * linux/arch/arm/mach-bcm2708/arm_control.h -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ -- --#ifndef __BCM2708_ARM_CONTROL_H --#define __BCM2708_ARM_CONTROL_H -- --/* -- * Definitions and addresses for the ARM CONTROL logic -- * This file is manually generated. -- */ -- --#define ARM_BASE 0x7E00B000 -- --/* Basic configuration */ --#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) --#define ARM_C0_SIZ128M 0x00000000 --#define ARM_C0_SIZ256M 0x00000001 --#define ARM_C0_SIZ512M 0x00000002 --#define ARM_C0_SIZ1G 0x00000003 --#define ARM_C0_BRESP0 0x00000000 --#define ARM_C0_BRESP1 0x00000004 --#define ARM_C0_BRESP2 0x00000008 --#define ARM_C0_BOOTHI 0x00000010 --#define ARM_C0_UNUSED05 0x00000020 /* free */ --#define ARM_C0_FULLPERI 0x00000040 --#define ARM_C0_UNUSED78 0x00000180 /* free */ --#define ARM_C0_JTAGMASK 0x00000E00 --#define ARM_C0_JTAGOFF 0x00000000 --#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ --#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ --#define ARM_C0_APROTMSK 0x0000F000 --#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ --#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ --#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ --#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ --#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ --#define ARM_C0_PRIO_L2 0x0F000000 --#define ARM_C0_PRIO_UC 0xF0000000 -- --#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ --#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ --#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -- -- --#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) --#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ --#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ --#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ --#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ --#define ARM_C1_PERSON 0x00000100 /* peripherals on */ --#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -- --#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) --#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ --#define ARM_S_READPEND 0x000003FF /* pending reads counter */ --#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -- --#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) --#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ --#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ --#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ --#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ --#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ --#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -- --#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) --#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) --#define ARM_IDVAL 0x364D5241 -- --/* Translation memory */ --#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) --/* 32 locations: 0x100.. 0x17F */ --/* 32 spare means we CAN go to 64 pages.... */ -- -- --/* Interrupts */ --#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ --#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ --#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ --#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ --#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ --#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ --#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -- --#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ --/* todo: all I1_interrupt sources */ --#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ --/* todo: all I2_interrupt sources */ -- --#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ --#define ARM_IF_INDEX 0x0000007F /* FIQ select */ --#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ --#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ --#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ --#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ --#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ --#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ --#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ --#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ --#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -- --#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ --#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ --#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ --#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ --#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ --#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ --#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ --#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ --#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ --#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ --#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ --#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ --#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -- --/* Timer */ --/* For reg. fields see sp804 spec. */ --#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) --#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) --#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) --#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) --#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) --#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) --#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) --#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) --#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -- --#define TIMER_CTRL_ONESHOT (1 << 0) --#define TIMER_CTRL_32BIT (1 << 1) --#define TIMER_CTRL_DIV1 (0 << 2) --#define TIMER_CTRL_DIV16 (1 << 2) --#define TIMER_CTRL_DIV256 (2 << 2) --#define TIMER_CTRL_IE (1 << 5) --#define TIMER_CTRL_PERIODIC (1 << 6) --#define TIMER_CTRL_ENABLE (1 << 7) --#define TIMER_CTRL_DBGHALT (1 << 8) --#define TIMER_CTRL_ENAFREE (1 << 9) --#define TIMER_CTRL_FREEDIV_SHIFT 16) --#define TIMER_CTRL_FREEDIV_MASK 0xff -- --/* Semaphores, Doorbells, Mailboxes */ --#define ARM_SBM_OWN0 (ARM_BASE+0x800) --#define ARM_SBM_OWN1 (ARM_BASE+0x900) --#define ARM_SBM_OWN2 (ARM_BASE+0xA00) --#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -- --/* MAILBOXES -- * Register flags are common across all -- * owner registers. See end of this section -- * -- * Semaphores, Doorbells, Mailboxes Owner 0 -- * -- */ -- --#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) --#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) --#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) --#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) --#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) --#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) --#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) --#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) --#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) --#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) --#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) --#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) --#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) --/* MAILBOX 0 access in Owner 0 area */ --/* Some addresses should ONLY be used by owner 0 */ --#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ --#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ --#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ --#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ --#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ --#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ --/* MAILBOX 1 access in Owner 0 area */ --/* Owner 0 should only WRITE to this mailbox */ --#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ --/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ --#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ --/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ --/* General SEM, BELL, MAIL config/status */ --#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ --#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ --#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ --#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -- --/* Semaphores, Doorbells, Mailboxes Owner 1 */ --#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) --#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) --#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) --#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) --#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) --#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) --#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) --#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) --#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) --#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) --#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) --#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) --#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) --/* MAILBOX 0 access in Owner 0 area */ --/* Owner 1 should only WRITE to this mailbox */ --#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ --/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ --#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ --/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ --/* MAILBOX 1 access in Owner 0 area */ --#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ --#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ --#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ --#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ --#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ --#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) --/* General SEM, BELL, MAIL config/status */ --#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ --#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ --#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ --#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -- --/* Semaphores, Doorbells, Mailboxes Owner 2 */ --#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) --#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) --#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) --#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) --#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) --#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) --#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) --#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) --#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) --#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) --#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) --#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) --#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) --/* MAILBOX 0 access in Owner 2 area */ --/* Owner 2 should only WRITE to this mailbox */ --#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ --/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ --#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ --/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ --/* MAILBOX 1 access in Owner 2 area */ --/* Owner 2 should only WRITE to this mailbox */ --#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ --/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ --#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ --/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ --/* General SEM, BELL, MAIL config/status */ --#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ --#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ --#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ --#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -- --/* Semaphores, Doorbells, Mailboxes Owner 3 */ --#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) --#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) --#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) --#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) --#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) --#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) --#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) --#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) --#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) --#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) --#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) --#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) --#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) --/* MAILBOX 0 access in Owner 3 area */ --/* Owner 3 should only WRITE to this mailbox */ --#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ --/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ --#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ --/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ --/* MAILBOX 1 access in Owner 3 area */ --/* Owner 3 should only WRITE to this mailbox */ --#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ --/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ --/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ --#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ --/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ --/* General SEM, BELL, MAIL config/status */ --#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ --#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ --#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ --#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -- -- -- --/* Mailbox flags. Valid for all owners */ -- --/* Mailbox status register (...0x98) */ --#define ARM_MS_FULL 0x80000000 --#define ARM_MS_EMPTY 0x40000000 --#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -- --/* MAILBOX config/status register (...0x9C) */ --/* ANY write to this register clears the error bits! */ --#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ --#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ --#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ --#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ --#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ --#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ --#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ --/* Bit 7 is unused */ --#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ --#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ --#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -- --/* Semaphore clear/debug register (...0xE0) */ --#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ --#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ --#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ --#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ --#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ --#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ --#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ --#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ --#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ --#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ --#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ --#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ --#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ --#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ --#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ --#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -- --/* Doorbells clear/debug register (...0xE4) */ --#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ --#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ --#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ --#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ --#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ --#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ --#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ --#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -- --/* MY IRQS register (...0xF8) */ --#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ --#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -- --/* ALL IRQS register (...0xF8) */ --#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ --#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ --#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ --#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ --#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ --#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ --#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ --#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ --#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ --#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ --/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ --/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ --/* */ --/* ARM JTAG BASH */ --/* */ --#define AJB_BASE 0x7e2000c0 -- --#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) --#define AJB_BITS0 0x000000 --#define AJB_BITS4 0x000004 --#define AJB_BITS8 0x000008 --#define AJB_BITS12 0x00000C --#define AJB_BITS16 0x000010 --#define AJB_BITS20 0x000014 --#define AJB_BITS24 0x000018 --#define AJB_BITS28 0x00001C --#define AJB_BITS32 0x000020 --#define AJB_BITS34 0x000022 --#define AJB_OUT_MS 0x000040 --#define AJB_OUT_LS 0x000000 --#define AJB_INV_CLK 0x000080 --#define AJB_D0_RISE 0x000100 --#define AJB_D0_FALL 0x000000 --#define AJB_D1_RISE 0x000200 --#define AJB_D1_FALL 0x000000 --#define AJB_IN_RISE 0x000400 --#define AJB_IN_FALL 0x000000 --#define AJB_ENABLE 0x000800 --#define AJB_HOLD0 0x000000 --#define AJB_HOLD1 0x001000 --#define AJB_HOLD2 0x002000 --#define AJB_HOLD3 0x003000 --#define AJB_RESETN 0x004000 --#define AJB_CLKSHFT 16 --#define AJB_BUSY 0x80000000 --#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) --#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) --#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -- --#define ARM_LOCAL_BASE 0x40000000 --#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) --#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) --#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) --#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) --#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) --#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) --#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) --#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) --#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) --#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) --#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) --#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -- --#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) --#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) --#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) --#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -- --#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) --#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) --#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) --#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -- --#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) --#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) --#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) --#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -- --#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) --#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) --#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) --#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -- --#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) --#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) --#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) --#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -- --#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) --#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) --#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) --#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -- --#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) --#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) --#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) --#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -- --#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) --#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) --#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) --#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -- --#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) --#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) --#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) --#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -- --#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) --#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) --#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) --#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -- --#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) --#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) --#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) --#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -- --#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) --#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) --#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) --#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -- --#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/hardware.h b/arch/arm/mach-bcm2709/include/mach/hardware.h -deleted file mode 100644 -index c2954e8..0000000 ---- a/arch/arm/mach-bcm2709/include/mach/hardware.h -+++ /dev/null -@@ -1,28 +0,0 @@ --/* -- * arch/arm/mach-bcm2708/include/mach/hardware.h -- * -- * This file contains the hardware definitions of the BCM2708 devices. -- * -- * Copyright (C) 2010 Broadcom -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ --#ifndef __ASM_ARCH_HARDWARE_H --#define __ASM_ARCH_HARDWARE_H -- --#include --#include -- --#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/irqs.h b/arch/arm/mach-bcm2709/include/mach/irqs.h -deleted file mode 100644 -index d301f06..0000000 ---- a/arch/arm/mach-bcm2709/include/mach/irqs.h -+++ /dev/null -@@ -1,225 +0,0 @@ --/* -- * arch/arm/mach-bcm2708/include/mach/irqs.h -- * -- * Copyright (C) 2010 Broadcom -- * Copyright (C) 2003 ARM Limited -- * Copyright (C) 2000 Deep Blue Solutions Ltd. -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- */ -- --#ifndef _BCM2708_IRQS_H_ --#define _BCM2708_IRQS_H_ -- --#include -- --/* -- * IRQ interrupts definitions are the same as the INT definitions -- * held within platform.h -- */ --#define IRQ_ARMCTRL_START 0 --#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) --#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) --#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) --#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) --#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) --#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) --#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) --#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) --#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) --#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) --#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) --#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) --#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) --#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) --#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) --#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) --#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) --#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) --#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) --#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) --#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) --#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) --#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) --#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) --#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) --#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) --#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) --#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) --#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) --#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) --#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) --#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) --#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) --#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) --#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) --#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) --#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) --#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) --#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) --#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) --#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) --#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) --#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) --#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) --#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) --#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) --#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) --#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) --#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) --#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) --#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) --#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) --#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) --#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) --#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) --#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) --#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) --#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) --#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) --#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) --#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) --#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) --#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) --#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -- --#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) --#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) --#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) --#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) --#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) --#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) --#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) --#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) --#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) --#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -- --#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) --#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) --#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) --#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) --#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) --#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) --#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) --#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) --#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) --#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) --#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) --#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -- --#define FIQ_START HARD_IRQS -- --/* -- * FIQ interrupts definitions are the same as the INT definitions. -- */ --#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) --#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) --#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) --#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) --#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) --#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) --#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) --#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) --#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) --#define FIQ_USB (FIQ_START+INTERRUPT_USB) --#define FIQ_3D (FIQ_START+INTERRUPT_3D) --#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) --#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) --#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) --#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) --#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) --#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) --#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) --#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) --#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) --#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) --#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) --#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) --#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) --#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) --#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) --#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) --#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) --#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) --#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) --#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) --#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) --#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) --#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) --#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) --#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) --#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) --#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) --#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) --#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) --#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) --#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) --#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) --#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) --#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) --#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) --#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) --#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) --#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) --#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) --#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) --#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) --#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) --#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) --#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) --#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) --#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) --#define FIQ_UART (FIQ_START+INTERRUPT_UART) --#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) --#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) --#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) --#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) --#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) --#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -- --#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) --#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) --#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) --#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) --#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) --#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) --#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) --#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) --#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) --#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -- --#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) --#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) --#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) --#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) --#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) --#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) --#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) --#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) --#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) --#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) --#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) --#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -- --#define HARD_IRQS (128) --#define FIQ_IRQS (128) --#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) --#define GPIO_IRQS (32*5) --#define SPARE_ALLOC_IRQS 64 --#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) --#define FREE_IRQS 128 --#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -- --#endif /* _BCM2708_IRQS_H_ */ -diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h -index be99733..9a638f5 100644 ---- a/arch/arm/mach-bcm2709/include/mach/platform.h -+++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -47,9 +47,6 @@ - #define HW_REGISTER_RW(addr) (addr) - #define HW_REGISTER_RO(addr) (addr) - --#include "arm_control.h" --#undef ARM_BASE -- - /* - * Definitions and addresses for the ARM CONTROL logic - * This file is manually generated. -@@ -84,116 +81,6 @@ - #define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ - #define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ - -- --/* -- * Interrupt assignments -- */ -- --#define ARM_IRQ1_BASE 0 --#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) --#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) --#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) --#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) --#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) --#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) --#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) --#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) --#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) --#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) --#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) --#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) --#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) --#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) --#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) --#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) --#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) --#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) --#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) --#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) --#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) --#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) --#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) --#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) --#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) --#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) --#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) --#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) --#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) --#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) --#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) --#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -- --#define ARM_IRQ2_BASE 32 --#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) --#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) --#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) --#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) --#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) --#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) --#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) --#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) --#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) --#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) --#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) --#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) --#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) --#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) --#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) --#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) --#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) --#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) --#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) --#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) --#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) --#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) --#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) --#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) --#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) --#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) --#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) --#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) --#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) --#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) --#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) --#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -- --#define ARM_IRQ0_BASE 64 --#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) --#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) --#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) --#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) --#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) --#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) --#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) --#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) --#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) --#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) --#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) --#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) --#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) --#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) --#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) --#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) --#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) --#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) --#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) --#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) --#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -- --#define ARM_IRQ_LOCAL_BASE 96 --#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) --#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) --#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) --#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) --#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) --#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) --#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) --#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) --#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) --#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) --#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) --#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) -- - /* - * Watchdog - */ -@@ -222,6 +109,82 @@ - - #define UART0_CLOCK 3000000 - -+#define ARM_LOCAL_BASE 0x40000000 -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+ -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) -+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) -+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) -+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) -+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) -+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) -+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) -+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) -+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) -+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) -+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -+ -+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) -+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) -+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) -+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -+ -+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -+ -+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) -+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) -+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) -+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -+ -+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) -+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) -+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) -+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -+ -+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) -+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) -+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) -+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -+ -+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) -+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) -+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) -+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -+ -+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) -+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) -+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) -+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -+ -+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) -+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) -+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) -+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) -+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) -+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) -+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) -+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) -+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) -+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) -+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) -+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) -+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) -+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) -+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) -+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -+ - #endif - - /* END */ -diff --git a/arch/arm/mach-bcm2709/include/mach/system.h b/arch/arm/mach-bcm2709/include/mach/system.h -index 2d0b821..c9a9c9a 100644 ---- a/arch/arm/mach-bcm2709/include/mach/system.h -+++ b/arch/arm/mach-bcm2709/include/mach/system.h -@@ -23,7 +23,6 @@ - #define __ASM_ARCH_SYSTEM_H - - #include --#include - #include - - static inline void arch_idle(void) -diff --git a/arch/arm/mach-bcm2709/include/mach/uncompress.h b/arch/arm/mach-bcm2709/include/mach/uncompress.h -index d634813..de7504b 100644 ---- a/arch/arm/mach-bcm2709/include/mach/uncompress.h -+++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h -@@ -21,7 +21,7 @@ - - #include - #include --#include -+#include - - #define UART_BAUD 115200 - -diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index 27b8467..26f1357d 100644 ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o - obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o -+obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o - obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o - obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o - obj-$(CONFIG_ARCH_MMP) += irq-mmp.o --- -2.5.0 - - -From d3425970052fa52673d1ff7dc72c7f234104ab97 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Mon, 16 Nov 2015 12:30:32 +0000 -Subject: [PATCH 34/78] BCM270X_DT: Enable the watchdog - -Although enabled, the watchdog remains idle until started with a -privileged access to /dev/watchdog, e.g. 'sudo touch /dev/watchdog.' -Once activated, the watchdog must be restarted before the timeout -expires. The default timeout is 16 seconds. ---- - arch/arm/boot/dts/bcm2708.dtsi | 4 ++++ - arch/arm/boot/dts/bcm2709.dtsi | 4 ++++ - 2 files changed, 8 insertions(+) - -diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi -index 0bea715..42acf77 100644 ---- a/arch/arm/boot/dts/bcm2708.dtsi -+++ b/arch/arm/boot/dts/bcm2708.dtsi -@@ -34,3 +34,7 @@ - &intc { - compatible = "brcm,bcm2835-armctrl-ic"; - }; -+ -+&watchdog { -+ status = "okay"; -+}; -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index 811d825..d21f5f0 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -74,3 +74,7 @@ - <&v7_cpu3>, "clock-frequency:0"; - }; - }; -+ -+&watchdog { -+ status = "okay"; -+}; --- -2.5.0 - - -From 2d6c63ed3b57a9e9e81c71ee04f9b26df36f4097 Mon Sep 17 00:00:00 2001 +From a6a43f492a980a33e31d3960f1709defd6f1bd7b Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 11 Nov 2015 11:38:59 +0000 -Subject: [PATCH 35/78] scripts: Multi-platform support for mkknlimg and +Subject: [PATCH 29/59] scripts: Multi-platform support for mkknlimg and knlinfo The firmware uses tags in the kernel trailer to choose which dtb file @@ -133678,1794 +129997,10 @@ index 3998d43..005f404 100755 2.5.0 -From cd7abc5b2e4bedbddc1240f2ffd0cd7ca3561920 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 17 Nov 2015 19:19:39 +0000 -Subject: [PATCH 36/78] Revert "BCM2709: Use upstream interrupt driver on all - Pi2's" - -This reverts commit fca5c033265716e4471d14ffa0875476290bbcc3. ---- - arch/arm/Kconfig | 2 - - arch/arm/mach-bcm2709/Makefile | 2 +- - arch/arm/mach-bcm2709/armctrl.c | 384 ++++++++++++++++++ - arch/arm/mach-bcm2709/armctrl.h | 27 ++ - arch/arm/mach-bcm2709/bcm2709.c | 167 +++++++- - arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 +++++++++++++++++++++++ - arch/arm/mach-bcm2709/include/mach/hardware.h | 28 ++ - arch/arm/mach-bcm2709/include/mach/irqs.h | 225 +++++++++++ - arch/arm/mach-bcm2709/include/mach/platform.h | 189 +++++---- - arch/arm/mach-bcm2709/include/mach/system.h | 1 + - arch/arm/mach-bcm2709/include/mach/uncompress.h | 2 +- - drivers/irqchip/Makefile | 1 - - 12 files changed, 1437 insertions(+), 84 deletions(-) - create mode 100644 arch/arm/mach-bcm2709/armctrl.c - create mode 100644 arch/arm/mach-bcm2709/armctrl.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h - create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 601b520..3241611 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -351,8 +351,6 @@ config ARCH_BCM2709 - select ARCH_HAS_CPUFREQ - select GENERIC_CLOCKEVENTS - select MACH_BCM2709 -- select MULTI_IRQ_HANDLER -- select SPARSE_IRQ - select VC4 - select FIQ - select USE_OF -diff --git a/arch/arm/mach-bcm2709/Makefile b/arch/arm/mach-bcm2709/Makefile -index 26cd67d..11ad846 100644 ---- a/arch/arm/mach-bcm2709/Makefile -+++ b/arch/arm/mach-bcm2709/Makefile -@@ -2,4 +2,4 @@ - # Makefile for the linux kernel. - # - --obj-$(CONFIG_MACH_BCM2709) += bcm2709.o -+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o -diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c -new file mode 100644 -index 0000000..fb82f7d ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.c -@@ -0,0 +1,384 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "armctrl.h" -+ -+/* For support of kernels >= 3.0 assume only one VIC for now*/ -+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -+ INTERRUPT_VC_JPEG, -+ INTERRUPT_VC_USB, -+ INTERRUPT_VC_3D, -+ INTERRUPT_VC_DMA2, -+ INTERRUPT_VC_DMA3, -+ INTERRUPT_VC_I2C, -+ INTERRUPT_VC_SPI, -+ INTERRUPT_VC_I2SPCM, -+ INTERRUPT_VC_SDIO, -+ INTERRUPT_VC_UART, -+ INTERRUPT_VC_ARASANSDIO -+}; -+ -+extern unsigned force_core; -+ -+static void armctrl_mask_irq(struct irq_data *d) -+{ -+ static const unsigned int disables[4] = { -+ ARM_IRQ_DIBL1, -+ ARM_IRQ_DIBL2, -+ ARM_IRQ_DIBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ writel(0, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); // -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+static void armctrl_unmask_irq(struct irq_data *d) -+{ -+ static const unsigned int enables[4] = { -+ ARM_IRQ_ENBL1, -+ ARM_IRQ_ENBL2, -+ ARM_IRQ_ENBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ unsigned int data; -+ if (force_core) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= ((force_core-1) << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ else if (num_online_cpus() > 1) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= (1 << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ /* Unmask in ARMCTRL block after routing it properly */ -+ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ if (force_core) { -+ unsigned int data; -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0x3; -+ data |= ((force_core-1) << 0); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+#ifdef CONFIG_OF -+ -+#define NR_IRQS_BANK0 21 -+#define NR_BANKS 4 -+#define IRQS_PER_BANK 32 -+ -+/* from drivers/irqchip/irq-bcm2835.c */ -+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -+ const u32 *intspec, unsigned int intsize, -+ unsigned long *out_hwirq, unsigned int *out_type) -+{ -+ if (WARN_ON(intsize != 2)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] >= NR_BANKS)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) -+ return -EINVAL; -+ -+ if (intspec[0] == 0) -+ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -+ else if (intspec[0] == 1) -+ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -+ else if (intspec[0] == 2) -+ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -+ else -+ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; -+ -+ /* reverse remap_irqs[] */ -+ switch (*out_hwirq) { -+ case INTERRUPT_VC_JPEG: -+ *out_hwirq = INTERRUPT_JPEG; -+ break; -+ case INTERRUPT_VC_USB: -+ *out_hwirq = INTERRUPT_USB; -+ break; -+ case INTERRUPT_VC_3D: -+ *out_hwirq = INTERRUPT_3D; -+ break; -+ case INTERRUPT_VC_DMA2: -+ *out_hwirq = INTERRUPT_DMA2; -+ break; -+ case INTERRUPT_VC_DMA3: -+ *out_hwirq = INTERRUPT_DMA3; -+ break; -+ case INTERRUPT_VC_I2C: -+ *out_hwirq = INTERRUPT_I2C; -+ break; -+ case INTERRUPT_VC_SPI: -+ *out_hwirq = INTERRUPT_SPI; -+ break; -+ case INTERRUPT_VC_I2SPCM: -+ *out_hwirq = INTERRUPT_I2SPCM; -+ break; -+ case INTERRUPT_VC_SDIO: -+ *out_hwirq = INTERRUPT_SDIO; -+ break; -+ case INTERRUPT_VC_UART: -+ *out_hwirq = INTERRUPT_UART; -+ break; -+ case INTERRUPT_VC_ARASANSDIO: -+ *out_hwirq = INTERRUPT_ARASANSDIO; -+ break; -+ } -+ -+ *out_type = IRQ_TYPE_NONE; -+ return 0; -+} -+ -+static struct irq_domain_ops armctrl_ops = { -+ .xlate = armctrl_xlate -+}; -+ -+void __init armctrl_dt_init(void) -+{ -+ struct device_node *np; -+ struct irq_domain *domain; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -+ if (!np) -+ return; -+ -+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -+ IRQ_ARMCTRL_START, 0, -+ &armctrl_ops, NULL); -+ WARN_ON(!domain); -+} -+#else -+void __init armctrl_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+#if defined(CONFIG_PM) -+ -+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -+ -+/* Static defines -+ * struct armctrl_device - VIC PM device (< 3.xx) -+ * @sysdev: The system device which is registered. (< 3.xx) -+ * @irq: The IRQ number for the base of the VIC. -+ * @base: The register base for the VIC. -+ * @resume_sources: A bitmask of interrupts for resume. -+ * @resume_irqs: The IRQs enabled for resume. -+ * @int_select: Save for VIC_INT_SELECT. -+ * @int_enable: Save for VIC_INT_ENABLE. -+ * @soft_int: Save for VIC_INT_SOFT. -+ * @protect: Save for VIC_PROTECT. -+ */ -+struct armctrl_info { -+ void __iomem *base; -+ int irq; -+ u32 resume_sources; -+ u32 resume_irqs; -+ u32 int_select; -+ u32 int_enable; -+ u32 soft_int; -+ u32 protect; -+} armctrl; -+ -+static int armctrl_suspend(void) -+{ -+ return 0; -+} -+ -+static void armctrl_resume(void) -+{ -+ return; -+} -+ -+/** -+ * armctrl_pm_register - Register a VIC for later power management control -+ * @base: The base address of the VIC. -+ * @irq: The base IRQ for the VIC. -+ * @resume_sources: bitmask of interrupts allowed for resume sources. -+ * -+ * For older kernels (< 3.xx) do - -+ * Register the VIC with the system device tree so that it can be notified -+ * of suspend and resume requests and ensure that the correct actions are -+ * taken to re-instate the settings on resume. -+ */ -+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 resume_sources) -+{ -+ armctrl.base = base; -+ armctrl.resume_sources = resume_sources; -+ armctrl.irq = irq; -+} -+ -+static int armctrl_set_wake(struct irq_data *d, unsigned int on) -+{ -+ unsigned int off = d->irq & 31; -+ u32 bit = 1 << off; -+ -+ if (!(bit & armctrl.resume_sources)) -+ return -EINVAL; -+ -+ if (on) -+ armctrl.resume_irqs |= bit; -+ else -+ armctrl.resume_irqs &= ~bit; -+ -+ return 0; -+} -+ -+#else -+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 arg1) -+{ -+} -+ -+#define armctrl_suspend NULL -+#define armctrl_resume NULL -+#define armctrl_set_wake NULL -+#endif /* CONFIG_PM */ -+ -+static struct syscore_ops armctrl_syscore_ops = { -+ .suspend = armctrl_suspend, -+ .resume = armctrl_resume, -+}; -+ -+/** -+ * armctrl_syscore_init - initicall to register VIC pm functions -+ * -+ * This is called via late_initcall() to register -+ * the resources for the VICs due to the early -+ * nature of the VIC's registration. -+*/ -+static int __init armctrl_syscore_init(void) -+{ -+ register_syscore_ops(&armctrl_syscore_ops); -+ return 0; -+} -+ -+late_initcall(armctrl_syscore_init); -+ -+static struct irq_chip armctrl_chip = { -+ .name = "ARMCTRL", -+ .irq_ack = NULL, -+ .irq_mask = armctrl_mask_irq, -+ .irq_unmask = armctrl_unmask_irq, -+ .irq_set_wake = armctrl_set_wake, -+}; -+ -+/** -+ * armctrl_init - initialise a vectored interrupt controller -+ * @base: iomem base address -+ * @irq_start: starting interrupt number, must be muliple of 32 -+ * @armctrl_sources: bitmask of interrupt sources to allow -+ * @resume_sources: bitmask of interrupt sources to allow for resume -+ */ -+int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources) -+{ -+ unsigned int irq; -+ -+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -+ unsigned int data = irq; -+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -+ data = remap_irqs[irq - INTERRUPT_JPEG]; -+ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { -+ irq_set_percpu_devid(irq); -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); -+ irq_set_status_flags(irq, IRQ_NOAUTOEN); -+ } else { -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); -+ irq_set_probe(irq); -+ } -+ irq_set_chip_data(irq, (void *)data); -+ } -+ -+ armctrl_pm_register(base, irq_start, resume_sources); -+ init_FIQ(FIQ_START); -+ armctrl_dt_init(); -+ return 0; -+} -diff --git a/arch/arm/mach-bcm2709/armctrl.h b/arch/arm/mach-bcm2709/armctrl.h -new file mode 100644 -index 0000000..0aa916e ---- /dev/null -+++ b/arch/arm/mach-bcm2709/armctrl.h -@@ -0,0 +1,27 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARMCTRL_H -+#define __BCM2708_ARMCTRL_H -+ -+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources); -+ -+#endif -diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c -index 90773a3..cbcf731 100644 ---- a/arch/arm/mach-bcm2709/bcm2709.c -+++ b/arch/arm/mach-bcm2709/bcm2709.c -@@ -28,16 +28,20 @@ - #include - - #include -+#include - #include - #include - - #include - #include -- - #include - -+#include "armctrl.h" -+ - #include - -+//#define SYSTEM_TIMER -+ - /* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to - * give us IO access only to 64Mbytes of physical memory (26 bits). We could - * represent this window by setting our dmamasks to 26 bits but, in fact -@@ -52,6 +56,12 @@ - /* command line parameters */ - static unsigned boardrev, serial; - static unsigned reboot_part = 0; -+unsigned force_core; -+ -+void __init bcm2709_init_irq(void) -+{ -+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); -+} - - static struct map_desc bcm2709_io_desc[] __initdata = { - { -@@ -111,6 +121,54 @@ void __init bcm2709_map_io(void) - iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); - } - -+#ifdef SYSTEM_TIMER -+ -+/* The STC is a free running counter that increments at the rate of 1MHz */ -+#define STC_FREQ_HZ 1000000 -+ -+static inline uint32_t timer_read(void) -+{ -+ /* STC: a free running counter that increments at the rate of 1MHz */ -+ return readl(__io_address(ST_BASE + 0x04)); -+} -+ -+static unsigned long bcm2709_read_current_timer(void) -+{ -+ return timer_read(); -+} -+ -+static u64 notrace bcm2709_read_sched_clock(void) -+{ -+ return timer_read(); -+} -+ -+static cycle_t clksrc_read(struct clocksource *cs) -+{ -+ return timer_read(); -+} -+ -+static struct clocksource clocksource_stc = { -+ .name = "stc", -+ .rating = 300, -+ .read = clksrc_read, -+ .mask = CLOCKSOURCE_MASK(32), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+unsigned long frc_clock_ticks32(void) -+{ -+ return timer_read(); -+} -+ -+static void __init bcm2709_clocksource_init(void) -+{ -+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -+ printk(KERN_ERR "timer: failed to initialize clock " -+ "source %s\n", clocksource_stc.name); -+ } -+} -+#endif -+ - int calc_rsts(int partition) - { - return PM_PASSWORD | -@@ -195,8 +253,7 @@ void __init bcm2709_init(void) - - pm_power_off = bcm2709_power_off; - -- ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, -- NULL); -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - if (ret) { - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); -@@ -208,6 +265,105 @@ void __init bcm2709_init(void) - system_serial_low = serial; - } - -+#ifdef SYSTEM_TIMER -+static void timer_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *clk) -+{ -+ switch (mode) { -+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ break; -+ case CLOCK_EVT_MODE_PERIODIC: -+ -+ case CLOCK_EVT_MODE_UNUSED: -+ case CLOCK_EVT_MODE_RESUME: -+ -+ default: -+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -+ (int)mode); -+ break; -+ } -+ -+} -+ -+static int timer_set_next_event(unsigned long cycles, -+ struct clock_event_device *unused) -+{ -+ unsigned long stc; -+ do { -+ stc = readl(__io_address(ST_BASE + 0x04)); -+ /* We could take a FIQ here, which may push ST above STC3 */ -+ writel(stc + cycles, __io_address(ST_BASE + 0x18)); -+ } while ((signed long) cycles >= 0 && -+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -+ >= (signed long) cycles); -+ return 0; -+} -+ -+static struct clock_event_device timer0_clockevent = { -+ .name = "timer0", -+ .shift = 32, -+ .features = CLOCK_EVT_FEAT_ONESHOT, -+ .set_mode = timer_set_mode, -+ .set_next_event = timer_set_next_event, -+}; -+ -+/* -+ * IRQ handler for the timer -+ */ -+static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) -+{ -+ struct clock_event_device *evt = &timer0_clockevent; -+ -+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -+ -+ evt->event_handler(evt); -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction bcm2709_timer_irq = { -+ .name = "BCM2709 Timer Tick", -+ .flags = IRQF_TIMER | IRQF_IRQPOLL, -+ .handler = bcm2709_timer_interrupt, -+}; -+ -+/* -+ * Set up timer interrupt, and return the current time in seconds. -+ */ -+ -+static struct delay_timer bcm2709_delay_timer = { -+ .read_current_timer = bcm2709_read_current_timer, -+ .freq = STC_FREQ_HZ, -+}; -+ -+static void __init bcm2709_timer_init(void) -+{ -+ /* init high res timer */ -+ bcm2709_clocksource_init(); -+ -+ /* -+ * Make irqs happen for the system timer -+ */ -+ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); -+ -+ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); -+ -+ timer0_clockevent.mult = -+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -+ timer0_clockevent.max_delta_ns = -+ clockevent_delta2ns(0xffffffff, &timer0_clockevent); -+ timer0_clockevent.min_delta_ns = -+ clockevent_delta2ns(0xf, &timer0_clockevent); -+ -+ timer0_clockevent.cpumask = cpumask_of(0); -+ clockevents_register_device(&timer0_clockevent); -+ -+ register_current_timer_delay(&bcm2709_delay_timer); -+} -+ -+#else -+ - static void __init bcm2709_timer_init(void) - { - // timer control -@@ -220,6 +376,7 @@ static void __init bcm2709_timer_init(void) - clocksource_probe(); - } - -+#endif - - void __init bcm2709_init_early(void) - { -@@ -240,6 +397,7 @@ static void __init board_reserve(void) - #ifdef CONFIG_SMP - #include - -+#include - #include - #include - int dc4=0; -@@ -353,6 +511,7 @@ MACHINE_START(BCM2709, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -367,6 +526,7 @@ MACHINE_START(BCM2708, "BCM2709") - .smp = smp_ops(bcm2709_smp_ops), - #endif - .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, - .init_time = bcm2709_timer_init, - .init_machine = bcm2709_init, - .init_early = bcm2709_init_early, -@@ -375,6 +535,7 @@ MACHINE_START(BCM2708, "BCM2709") - .dt_compat = bcm2709_compat, - MACHINE_END - -+module_param(force_core, uint, 0644); - module_param(boardrev, uint, 0644); - module_param(serial, uint, 0644); - module_param(reboot_part, uint, 0644); -diff --git a/arch/arm/mach-bcm2709/include/mach/arm_control.h b/arch/arm/mach-bcm2709/include/mach/arm_control.h -new file mode 100644 -index 0000000..e346caf ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h -@@ -0,0 +1,493 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/arm_control.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARM_CONTROL_H -+#define __BCM2708_ARM_CONTROL_H -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define ARM_BASE 0x7E00B000 -+ -+/* Basic configuration */ -+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) -+#define ARM_C0_SIZ128M 0x00000000 -+#define ARM_C0_SIZ256M 0x00000001 -+#define ARM_C0_SIZ512M 0x00000002 -+#define ARM_C0_SIZ1G 0x00000003 -+#define ARM_C0_BRESP0 0x00000000 -+#define ARM_C0_BRESP1 0x00000004 -+#define ARM_C0_BRESP2 0x00000008 -+#define ARM_C0_BOOTHI 0x00000010 -+#define ARM_C0_UNUSED05 0x00000020 /* free */ -+#define ARM_C0_FULLPERI 0x00000040 -+#define ARM_C0_UNUSED78 0x00000180 /* free */ -+#define ARM_C0_JTAGMASK 0x00000E00 -+#define ARM_C0_JTAGOFF 0x00000000 -+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ -+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ -+#define ARM_C0_APROTMSK 0x0000F000 -+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ -+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ -+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ -+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ -+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ -+#define ARM_C0_PRIO_L2 0x0F000000 -+#define ARM_C0_PRIO_UC 0xF0000000 -+ -+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ -+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ -+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -+ -+ -+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) -+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ -+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ -+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ -+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ -+#define ARM_C1_PERSON 0x00000100 /* peripherals on */ -+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -+ -+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) -+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ -+#define ARM_S_READPEND 0x000003FF /* pending reads counter */ -+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -+ -+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) -+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ -+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ -+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ -+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ -+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ -+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -+ -+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) -+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) -+#define ARM_IDVAL 0x364D5241 -+ -+/* Translation memory */ -+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) -+/* 32 locations: 0x100.. 0x17F */ -+/* 32 spare means we CAN go to 64 pages.... */ -+ -+ -+/* Interrupts */ -+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ -+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ -+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ -+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -+ -+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ -+/* todo: all I1_interrupt sources */ -+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ -+/* todo: all I2_interrupt sources */ -+ -+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ -+#define ARM_IF_INDEX 0x0000007F /* FIQ select */ -+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ -+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ -+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ -+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ -+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ -+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ -+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ -+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ -+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -+ -+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ -+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ -+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ -+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ -+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ -+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ -+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ -+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ -+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ -+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -+ -+/* Timer */ -+/* For reg. fields see sp804 spec. */ -+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) -+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) -+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) -+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) -+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) -+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) -+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) -+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) -+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -+ -+#define TIMER_CTRL_ONESHOT (1 << 0) -+#define TIMER_CTRL_32BIT (1 << 1) -+#define TIMER_CTRL_DIV1 (0 << 2) -+#define TIMER_CTRL_DIV16 (1 << 2) -+#define TIMER_CTRL_DIV256 (2 << 2) -+#define TIMER_CTRL_IE (1 << 5) -+#define TIMER_CTRL_PERIODIC (1 << 6) -+#define TIMER_CTRL_ENABLE (1 << 7) -+#define TIMER_CTRL_DBGHALT (1 << 8) -+#define TIMER_CTRL_ENAFREE (1 << 9) -+#define TIMER_CTRL_FREEDIV_SHIFT 16) -+#define TIMER_CTRL_FREEDIV_MASK 0xff -+ -+/* Semaphores, Doorbells, Mailboxes */ -+#define ARM_SBM_OWN0 (ARM_BASE+0x800) -+#define ARM_SBM_OWN1 (ARM_BASE+0x900) -+#define ARM_SBM_OWN2 (ARM_BASE+0xA00) -+#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -+ -+/* MAILBOXES -+ * Register flags are common across all -+ * owner registers. See end of this section -+ * -+ * Semaphores, Doorbells, Mailboxes Owner 0 -+ * -+ */ -+ -+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) -+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) -+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) -+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) -+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) -+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) -+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) -+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) -+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) -+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) -+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Some addresses should ONLY be used by owner 0 */ -+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ -+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ -+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ -+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ -+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ -+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ -+/* MAILBOX 1 access in Owner 0 area */ -+/* Owner 0 should only WRITE to this mailbox */ -+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ -+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ -+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ -+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ -+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 1 */ -+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) -+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) -+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) -+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) -+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) -+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) -+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) -+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) -+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) -+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) -+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Owner 1 should only WRITE to this mailbox */ -+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ -+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 0 area */ -+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ -+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ -+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ -+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ -+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ -+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ -+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ -+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ -+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 2 */ -+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) -+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) -+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) -+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) -+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) -+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) -+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) -+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) -+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) -+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) -+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) -+/* MAILBOX 0 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ -+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ -+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ -+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ -+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ -+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 3 */ -+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) -+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) -+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) -+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) -+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) -+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) -+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) -+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) -+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) -+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) -+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) -+/* MAILBOX 0 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ -+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ -+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ -+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ -+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ -+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -+ -+ -+ -+/* Mailbox flags. Valid for all owners */ -+ -+/* Mailbox status register (...0x98) */ -+#define ARM_MS_FULL 0x80000000 -+#define ARM_MS_EMPTY 0x40000000 -+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -+ -+/* MAILBOX config/status register (...0x9C) */ -+/* ANY write to this register clears the error bits! */ -+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ -+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ -+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ -+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ -+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ -+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ -+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ -+/* Bit 7 is unused */ -+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ -+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ -+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -+ -+/* Semaphore clear/debug register (...0xE0) */ -+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ -+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ -+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ -+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ -+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ -+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ -+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ -+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ -+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ -+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ -+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ -+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ -+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ -+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ -+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ -+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -+ -+/* Doorbells clear/debug register (...0xE4) */ -+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ -+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ -+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ -+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ -+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ -+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ -+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ -+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -+ -+/* MY IRQS register (...0xF8) */ -+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ -+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -+ -+/* ALL IRQS register (...0xF8) */ -+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ -+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ -+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ -+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ -+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ -+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ -+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ -+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ -+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ -+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ -+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ -+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ -+/* */ -+/* ARM JTAG BASH */ -+/* */ -+#define AJB_BASE 0x7e2000c0 -+ -+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) -+#define AJB_BITS0 0x000000 -+#define AJB_BITS4 0x000004 -+#define AJB_BITS8 0x000008 -+#define AJB_BITS12 0x00000C -+#define AJB_BITS16 0x000010 -+#define AJB_BITS20 0x000014 -+#define AJB_BITS24 0x000018 -+#define AJB_BITS28 0x00001C -+#define AJB_BITS32 0x000020 -+#define AJB_BITS34 0x000022 -+#define AJB_OUT_MS 0x000040 -+#define AJB_OUT_LS 0x000000 -+#define AJB_INV_CLK 0x000080 -+#define AJB_D0_RISE 0x000100 -+#define AJB_D0_FALL 0x000000 -+#define AJB_D1_RISE 0x000200 -+#define AJB_D1_FALL 0x000000 -+#define AJB_IN_RISE 0x000400 -+#define AJB_IN_FALL 0x000000 -+#define AJB_ENABLE 0x000800 -+#define AJB_HOLD0 0x000000 -+#define AJB_HOLD1 0x001000 -+#define AJB_HOLD2 0x002000 -+#define AJB_HOLD3 0x003000 -+#define AJB_RESETN 0x004000 -+#define AJB_CLKSHFT 16 -+#define AJB_BUSY 0x80000000 -+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) -+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) -+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -+ -+#define ARM_LOCAL_BASE 0x40000000 -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) -+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) -+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) -+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) -+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) -+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) -+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) -+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) -+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) -+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) -+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -+ -+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) -+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) -+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) -+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -+ -+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -+ -+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) -+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) -+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) -+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -+ -+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) -+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) -+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) -+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -+ -+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) -+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) -+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) -+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -+ -+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) -+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) -+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) -+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -+ -+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) -+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) -+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) -+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -+ -+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) -+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) -+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) -+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) -+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) -+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) -+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) -+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) -+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) -+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) -+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) -+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) -+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) -+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) -+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) -+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -+ -+#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/hardware.h b/arch/arm/mach-bcm2709/include/mach/hardware.h -new file mode 100644 -index 0000000..c2954e8 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/hardware.h -@@ -0,0 +1,28 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/hardware.h -+ * -+ * This file contains the hardware definitions of the BCM2708 devices. -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include -+#include -+ -+#endif -diff --git a/arch/arm/mach-bcm2709/include/mach/irqs.h b/arch/arm/mach-bcm2709/include/mach/irqs.h -new file mode 100644 -index 0000000..d301f06 ---- /dev/null -+++ b/arch/arm/mach-bcm2709/include/mach/irqs.h -@@ -0,0 +1,225 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/irqs.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_IRQS_H_ -+#define _BCM2708_IRQS_H_ -+ -+#include -+ -+/* -+ * IRQ interrupts definitions are the same as the INT definitions -+ * held within platform.h -+ */ -+#define IRQ_ARMCTRL_START 0 -+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) -+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) -+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) -+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) -+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) -+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) -+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) -+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) -+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) -+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) -+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) -+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) -+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) -+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) -+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) -+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) -+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) -+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) -+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) -+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) -+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) -+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) -+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) -+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) -+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) -+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) -+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) -+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) -+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) -+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) -+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) -+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) -+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) -+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) -+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) -+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) -+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) -+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) -+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) -+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) -+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) -+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) -+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) -+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) -+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) -+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) -+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) -+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) -+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) -+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) -+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) -+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) -+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) -+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) -+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) -+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) -+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) -+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) -+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) -+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) -+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) -+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) -+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) -+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -+ -+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) -+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) -+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) -+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) -+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) -+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) -+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) -+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) -+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) -+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -+ -+#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define FIQ_START HARD_IRQS -+ -+/* -+ * FIQ interrupts definitions are the same as the INT definitions. -+ */ -+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) -+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) -+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) -+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) -+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) -+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) -+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) -+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) -+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) -+#define FIQ_USB (FIQ_START+INTERRUPT_USB) -+#define FIQ_3D (FIQ_START+INTERRUPT_3D) -+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) -+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) -+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) -+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) -+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) -+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) -+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) -+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) -+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) -+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) -+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) -+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) -+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) -+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) -+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) -+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) -+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) -+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) -+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) -+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) -+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) -+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) -+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) -+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) -+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) -+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) -+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) -+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) -+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) -+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) -+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) -+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) -+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) -+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) -+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) -+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) -+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) -+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) -+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) -+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) -+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) -+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) -+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) -+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) -+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) -+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) -+#define FIQ_UART (FIQ_START+INTERRUPT_UART) -+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) -+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) -+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) -+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) -+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) -+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -+ -+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) -+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) -+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) -+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) -+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) -+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) -+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) -+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) -+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) -+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -+ -+#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define HARD_IRQS (128) -+#define FIQ_IRQS (128) -+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) -+#define GPIO_IRQS (32*5) -+#define SPARE_ALLOC_IRQS 64 -+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) -+#define FREE_IRQS 128 -+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -+ -+#endif /* _BCM2708_IRQS_H_ */ -diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h -index 9a638f5..be99733 100644 ---- a/arch/arm/mach-bcm2709/include/mach/platform.h -+++ b/arch/arm/mach-bcm2709/include/mach/platform.h -@@ -47,6 +47,9 @@ - #define HW_REGISTER_RW(addr) (addr) - #define HW_REGISTER_RO(addr) (addr) - -+#include "arm_control.h" -+#undef ARM_BASE -+ - /* - * Definitions and addresses for the ARM CONTROL logic - * This file is manually generated. -@@ -81,6 +84,116 @@ - #define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ - #define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ - -+ -+/* -+ * Interrupt assignments -+ */ -+ -+#define ARM_IRQ1_BASE 0 -+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) -+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) -+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) -+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) -+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) -+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) -+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) -+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) -+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) -+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) -+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) -+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) -+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) -+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) -+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) -+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) -+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) -+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) -+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) -+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) -+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) -+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) -+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) -+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) -+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) -+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) -+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) -+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) -+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) -+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) -+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) -+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -+ -+#define ARM_IRQ2_BASE 32 -+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) -+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) -+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) -+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) -+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) -+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) -+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) -+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) -+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) -+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) -+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) -+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) -+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) -+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) -+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) -+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) -+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) -+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) -+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) -+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) -+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) -+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) -+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) -+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) -+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) -+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) -+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) -+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) -+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) -+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) -+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) -+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -+ -+#define ARM_IRQ0_BASE 64 -+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) -+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) -+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) -+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) -+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) -+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) -+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) -+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) -+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) -+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) -+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) -+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) -+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) -+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) -+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) -+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) -+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) -+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) -+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) -+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) -+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -+ -+#define ARM_IRQ_LOCAL_BASE 96 -+#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) -+#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) -+#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) -+#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) -+#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) -+#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) -+#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) -+#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) -+#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) -+#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) -+#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) -+#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) -+ - /* - * Watchdog - */ -@@ -109,82 +222,6 @@ - - #define UART0_CLOCK 3000000 - --#define ARM_LOCAL_BASE 0x40000000 --#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -- --#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) --#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) --#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) --#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) --#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) --#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) --#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) --#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) --#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) --#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) --#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) --#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -- --#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) --#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) --#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) --#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -- --#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) --#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) --#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) --#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -- --#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) --#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) --#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) --#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -- --#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) --#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) --#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) --#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -- --#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) --#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) --#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) --#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -- --#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) --#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) --#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) --#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -- --#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) --#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) --#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) --#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -- --#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) --#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) --#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) --#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -- --#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) --#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) --#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) --#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -- --#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) --#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) --#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) --#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -- --#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) --#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) --#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) --#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -- --#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) --#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) --#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) --#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -- - #endif - - /* END */ -diff --git a/arch/arm/mach-bcm2709/include/mach/system.h b/arch/arm/mach-bcm2709/include/mach/system.h -index c9a9c9a..2d0b821 100644 ---- a/arch/arm/mach-bcm2709/include/mach/system.h -+++ b/arch/arm/mach-bcm2709/include/mach/system.h -@@ -23,6 +23,7 @@ - #define __ASM_ARCH_SYSTEM_H - - #include -+#include - #include - - static inline void arch_idle(void) -diff --git a/arch/arm/mach-bcm2709/include/mach/uncompress.h b/arch/arm/mach-bcm2709/include/mach/uncompress.h -index de7504b..d634813 100644 ---- a/arch/arm/mach-bcm2709/include/mach/uncompress.h -+++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h -@@ -21,7 +21,7 @@ - - #include - #include --#include -+#include - - #define UART_BAUD 115200 - -diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index 26f1357d..27b8467 100644 ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -3,7 +3,6 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o - obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o --obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o - obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o - obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o - obj-$(CONFIG_ARCH_MMP) += irq-mmp.o --- -2.5.0 - - -From b977bb81802fbcbb80649167dc5b6995c6504975 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 17 Nov 2015 21:25:41 +0000 -Subject: [PATCH 37/78] BCM2709: Use upstream interrupt controllers - ---- - arch/arm/boot/dts/bcm2709.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index d21f5f0..bcad162 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -22,6 +22,14 @@ - reg = <0x7e200000 0x1000>; - status = "okay"; - }; -+ -+ local_intc: local_intc { -+ compatible = "brcm,bcm2836-l1-intc"; -+ reg = <0x40000000 0x100>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&local_intc>; -+ }; - }; - - timer { -@@ -78,3 +86,9 @@ - &watchdog { - status = "okay"; - }; -+ -+&intc { -+ compatible = "brcm,bcm2836-armctrl-ic"; -+ interrupt-parent = <&local_intc>; -+ interrupts = <8>; -+}; --- -2.5.0 - - -From f4d13846ac7020f732def06861402ab91218f776 Mon Sep 17 00:00:00 2001 +From f95a3c1052bb61d28cc6a4a5ba5dfe691c1e5321 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 2 Mar 2015 13:01:12 -0800 -Subject: [PATCH 38/78] drm/vc4: Add suport for 3D rendering using the V3D +Subject: [PATCH 30/59] drm/vc4: Add suport for 3D rendering using the V3D engine. This is a squash of the out-of-tree development series. Since that @@ -141073,53 +135608,10 @@ index 0000000..499daae 2.5.0 -From 890668e7095063e4eeaa9db80e882829c48cf7f4 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 18 Nov 2015 17:03:59 +0000 -Subject: [PATCH 39/78] Revert "BCM2709: Use upstream interrupt controllers" - -This reverts commit 81d498ed1d85068c2f3c774fc30307c496aecf76. ---- - arch/arm/boot/dts/bcm2709.dtsi | 14 -------------- - 1 file changed, 14 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index bcad162..d21f5f0 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -22,14 +22,6 @@ - reg = <0x7e200000 0x1000>; - status = "okay"; - }; -- -- local_intc: local_intc { -- compatible = "brcm,bcm2836-l1-intc"; -- reg = <0x40000000 0x100>; -- interrupt-controller; -- #interrupt-cells = <1>; -- interrupt-parent = <&local_intc>; -- }; - }; - - timer { -@@ -86,9 +78,3 @@ - &watchdog { - status = "okay"; - }; -- --&intc { -- compatible = "brcm,bcm2836-armctrl-ic"; -- interrupt-parent = <&local_intc>; -- interrupts = <8>; --}; --- -2.5.0 - - -From a4bc9e9997a14d7a91ecee8b13a506f2769915ef Mon Sep 17 00:00:00 2001 +From f7c5c235d8ec8dad653d2ba5ddeed98c11ee3dc0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 14 Oct 2015 11:32:14 -0700 -Subject: [PATCH 40/78] drm/vc4: Force HDMI to connected. +Subject: [PATCH 31/59] drm/vc4: Force HDMI to connected. For some reason on the downstream tree, the HPD GPIO isn't working. @@ -141145,10 +135637,10 @@ index da9a36d..d15c529 100644 2.5.0 -From d6894e5464ab0c987cc8d90ee7ea7a0cf2bdea5a Mon Sep 17 00:00:00 2001 +From 77b1bdbe5ff38d999a3c45b4ce34dcf3bb1a59a5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:23:18 -0700 -Subject: [PATCH 41/78] drm/vc4: bo cache locking fixes. +Subject: [PATCH 32/59] drm/vc4: bo cache locking fixes. Signed-off-by: Eric Anholt --- @@ -141300,10 +135792,10 @@ index 8cc89d1..c079b82 100644 2.5.0 -From 12d2531eb1ed88254465a6ea132d16a2718b5008 Mon Sep 17 00:00:00 2001 +From ada48bc2dcabe8dabce74f2700bde6186fc00366 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:29:41 -0700 -Subject: [PATCH 42/78] drm/vc4: bo cache locking cleanup. +Subject: [PATCH 33/59] drm/vc4: bo cache locking cleanup. Signed-off-by: Eric Anholt --- @@ -141398,10 +135890,10 @@ index af0fde6..acd360c 100644 2.5.0 -From e2e88fba106831e3c35bbe7ee66fcc12598e930c Mon Sep 17 00:00:00 2001 +From 7ff769a1ebaa17c37d4a698af37ab71ff38ff5b8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:32:24 -0700 -Subject: [PATCH 43/78] drm/vc4: Use job_lock to protect seqno_cb_list. +Subject: [PATCH 34/59] drm/vc4: Use job_lock to protect seqno_cb_list. We're (mostly) not supposed to be using struct_mutex in drivers these days. @@ -141458,10 +135950,10 @@ index 361390b..b1853b2 100644 2.5.0 -From e79effaa2cfb9cab3aca2662638727f90a577f0e Mon Sep 17 00:00:00 2001 +From 3f5a87a8113d0026a92a48376dc63e1d3834ca90 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:44:35 -0700 -Subject: [PATCH 44/78] drm/vc4: Drop struct_mutex around CL validation. +Subject: [PATCH 35/59] drm/vc4: Drop struct_mutex around CL validation. We were using it so that we could make sure that shader validation state didn't change while we were validating, but now shader @@ -141527,10 +136019,10 @@ index b1853b2..32f375a 100644 2.5.0 -From 1c13c3f7fb7db3d3d71126d5a0dd181a015f033e Mon Sep 17 00:00:00 2001 +From 96ff83b46b899239914c4f82583694b220abf12a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Oct 2015 08:44:35 -0700 -Subject: [PATCH 45/78] drm/vc4: Drop struct_mutex around CL validation. +Subject: [PATCH 36/59] drm/vc4: Drop struct_mutex around CL validation. We were using it so that we could make sure that shader validation state didn't change while we were validating, but now shader @@ -141607,10 +136099,10 @@ index 32f375a..55551ea 100644 2.5.0 -From 861d6905eb3deac508af34d9937c0bd6b3ed1c8c Mon Sep 17 00:00:00 2001 +From 5132c04865bb90f75210e68e2b134a8a81a600a0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 20 Oct 2015 13:59:15 +0100 -Subject: [PATCH 46/78] drm/vc4: Add support for more display plane formats. +Subject: [PATCH 37/59] drm/vc4: Add support for more display plane formats. Signed-off-by: Eric Anholt --- @@ -141648,10 +136140,10 @@ index 65e5455..0f85eb5 100644 2.5.0 -From 41bd0b4b1bbc72f85adfb54b50cd3a5623a874ad Mon Sep 17 00:00:00 2001 +From aef868d034a4288d82a6c54422a6f995cb406d3b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 23 Oct 2015 12:31:56 +0100 -Subject: [PATCH 47/78] drm/vc4: No need to stop the stopped threads. +Subject: [PATCH 38/59] drm/vc4: No need to stop the stopped threads. This was leftover debug code from the hackdriver. We never submit unless the thread is already idle. @@ -141680,10 +136172,10 @@ index 55551ea..eeb0925 100644 2.5.0 -From 97355ff6eed7e856ea00d12aee96f37e6a6f9198 Mon Sep 17 00:00:00 2001 +From 977b27a2302f3e2317b4fa28f7aba9c73c77e7ef Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 23 Oct 2015 12:33:43 +0100 -Subject: [PATCH 48/78] drm/vc4: Remove extra barrier()s aroudn CTnCA/CTnEA +Subject: [PATCH 39/59] drm/vc4: Remove extra barrier()s aroudn CTnCA/CTnEA setup. The writel() that these expand to already does barriers. @@ -141719,10 +136211,10 @@ index eeb0925..0cea723 100644 2.5.0 -From 6ba05c099d51e04566e21ec4d75f3846f3662b99 Mon Sep 17 00:00:00 2001 +From 45832cd341f53f157ae1e679c06faef3d498db37 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 23 Oct 2015 14:57:22 +0100 -Subject: [PATCH 49/78] drm/vc4: Fix a typo in a V3D debug register. +Subject: [PATCH 40/59] drm/vc4: Fix a typo in a V3D debug register. Signed-off-by: Eric Anholt --- @@ -141760,10 +136252,10 @@ index b9cb7cf..cf35f58 100644 2.5.0 -From 661e79efd3a3bad9e33544fcbc4a4ee3d295d3b4 Mon Sep 17 00:00:00 2001 +From e44474f1a0149abb2608e57d7ad70f6eb160d18b Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 2 Nov 2015 17:07:33 +0000 -Subject: [PATCH 50/78] drm/vc4: Enable VC4 modules, and increase CMA size with +Subject: [PATCH 41/59] drm/vc4: Enable VC4 modules, and increase CMA size with overlay If using the overlay, be careful not to boot to GUI or run startx, @@ -141777,10 +136269,10 @@ or the Pi will almost hang, reporting stalls in kernel threads. create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index fdefff1..355bbc2 100644 +index b819293..f5302b2 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README -@@ -602,6 +602,14 @@ Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) +@@ -601,6 +601,14 @@ Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) @@ -141897,10 +136389,10 @@ index 0000000..cf5d5c9 + }; +}; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 3ec59d2..521f9a5 100644 +index 38e46ac..49317b9 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig -@@ -795,6 +795,8 @@ CONFIG_VIDEO_TW9903=m +@@ -802,6 +802,8 @@ CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m CONFIG_VIDEO_OV7640=m CONFIG_VIDEO_MT9V011=m @@ -141910,10 +136402,10 @@ index 3ec59d2..521f9a5 100644 CONFIG_FB_BCM2708=y CONFIG_FB_UDL=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 0f69adb..8faf3d6 100644 +index 436da55..202dd4b 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -788,6 +788,8 @@ CONFIG_VIDEO_TW9903=m +@@ -795,6 +795,8 @@ CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m CONFIG_VIDEO_OV7640=m CONFIG_VIDEO_MT9V011=m @@ -141926,10 +136418,10 @@ index 0f69adb..8faf3d6 100644 2.5.0 -From ced557f252c6650fd58e4e939cdc3271b2188a34 Mon Sep 17 00:00:00 2001 +From 64f336d46a8b61002efa54b58f1612cf03ab9930 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Nov 2015 18:29:58 +0000 -Subject: [PATCH 51/78] squash: fixups +Subject: [PATCH 42/59] squash: fixups --- drivers/gpu/drm/vc4/Kconfig | 2 +- @@ -141979,10 +136471,10 @@ index c83287a..2082713 100644 2.5.0 -From 917cb2854aa3b504e8d7528d99d931edf8605820 Mon Sep 17 00:00:00 2001 +From 5b553943a83156a46b864cca4ee0fdb0f2fc6882 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Nov 2015 20:26:03 +0000 -Subject: [PATCH 52/78] squash: add missing vc4-kms-v3d-overlay.dtb to makefile +Subject: [PATCH 43/59] squash: add missing vc4-kms-v3d-overlay.dtb to makefile --- arch/arm/boot/dts/overlays/Makefile | 1 + @@ -142004,62 +136496,10 @@ index fb7ac49..fc09bfb 100644 2.5.0 -From 802f5e84784e9c6689b89cf8d93ebeb6787d99c5 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 19 Nov 2015 14:11:07 +0000 -Subject: [PATCH 53/78] squash: Add cprman to dt - ---- - arch/arm/boot/dts/bcm2708_common.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index c658c7b..ec94d9f5 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -85,6 +85,18 @@ - status = "disabled"; - }; - -+ cprman: cprman@7e101000 { -+ compatible = "brcm,bcm2835-cprman"; -+ #clock-cells = <1>; -+ reg = <0x7e101000 0x2000>; -+ -+ /* CPRMAN derives everything from the platform's -+ * oscillator. -+ */ -+ clocks = <&clk_osc>; -+ status = "disabled"; -+ }; -+ - random: rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; -@@ -312,6 +324,15 @@ - clock-div = <1>; - clock-mult = <2>; - }; -+ -+ /* The oscillator is the root of the clock tree. */ -+ clk_osc: clock@7 { -+ compatible = "fixed-clock"; -+ reg = <7>; -+ #clock-cells = <0>; -+ clock-output-names = "osc"; -+ clock-frequency = <19200000>; -+ }; - }; - - __overrides__ { --- -2.5.0 - - -From efc55fc8b62871ba9e87d3a3dfbad32232a07d89 Mon Sep 17 00:00:00 2001 +From 5ac43b46f57d2cbe94c4d8a34e050eec9a625ce5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 12 Oct 2015 11:23:34 -0700 -Subject: [PATCH 54/78] clk: bcm2835: Also build the driver for downstream +Subject: [PATCH 44/59] clk: bcm2835: Also build the driver for downstream kernels. Signed-off-by: Eric Anholt @@ -142084,16 +136524,16 @@ index 3fc9506..a1b4cbc 100644 2.5.0 -From 1cd4b7121013a54d2ef37cf0dedf83aecf13f508 Mon Sep 17 00:00:00 2001 +From c0ba37a2a85130b7a0f88730eba2783c6dcd6951 Mon Sep 17 00:00:00 2001 From: Holger Steinhaus Date: Sat, 14 Nov 2015 18:37:43 +0100 -Subject: [PATCH 55/78] dts: Added overlay for gpio_ir_recv driver +Subject: [PATCH 45/59] dts: Added overlay for gpio_ir_recv driver --- arch/arm/boot/dts/overlays/Makefile | 1 + - arch/arm/boot/dts/overlays/README | 16 +++++++++ + arch/arm/boot/dts/overlays/README | 18 ++++++++++- arch/arm/boot/dts/overlays/gpio-ir-overlay.dts | 45 ++++++++++++++++++++++++++ - 3 files changed, 62 insertions(+) + 3 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-overlay.dts diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile @@ -142109,7 +136549,7 @@ index fc09bfb..ebc3354 100644 dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 355bbc2..3685f98 100644 +index f5302b2..409aee1 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -196,6 +196,22 @@ Params: int_pin GPIO used for INT (default 25) @@ -142134,7 +136574,16 @@ index 355bbc2..3685f98 100644 + Name: gpio-poweroff Info: Drives a GPIO high or low on reboot - Load: gpio-poweroff,= + Load: dtoverlay=gpio-poweroff,= +@@ -308,7 +324,7 @@ Params: + Name: lirc-rpi + Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi) + Consult the module documentation for more details. +-Load: dtoverlay=lirc-rpi,=,... ++Load: dtoverlay=lirc-rpi,= + Params: gpio_out_pin GPIO for output (default "17") + + gpio_in_pin GPIO for input (default "18") diff --git a/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts new file mode 100644 index 0000000..a2d6bc7 @@ -142190,19 +136639,19 @@ index 0000000..a2d6bc7 2.5.0 -From 76e6e1da69e6b88235c83cfc109a5b9ba19db236 Mon Sep 17 00:00:00 2001 +From 26e029b1b51f165e9cf74ea5ab311adaa1bf2e01 Mon Sep 17 00:00:00 2001 From: Alistair Buxton Date: Sun, 1 Nov 2015 22:27:56 +0000 -Subject: [PATCH 56/78] Build i2c_gpio module and add a device tree overlay to +Subject: [PATCH 46/59] Build i2c_gpio module and add a device tree overlay to configure it. --- arch/arm/boot/dts/overlays/Makefile | 1 + - arch/arm/boot/dts/overlays/README | 11 ++++++++++ + arch/arm/boot/dts/overlays/README | 13 +++++++++++- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 28 +++++++++++++++++++++++++ arch/arm/configs/bcm2709_defconfig | 1 + arch/arm/configs/bcmrpi_defconfig | 1 + - 5 files changed, 42 insertions(+) + 5 files changed, 43 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile @@ -142218,16 +136667,16 @@ index ebc3354..e15d55c 100644 dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 3685f98..2e96de5 100644 +index 409aee1..d278305 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README -@@ -287,6 +287,17 @@ Params: speed Display SPI bus speed +@@ -287,9 +287,20 @@ Params: speed Display SPI bus speed ledgpio GPIO used to control backlight +Name: i2c-gpio +Info: Adds support for software i2c controller on gpio pins -+Load: dtoverlay=i2c-gpio, ++Load: dtoverlay=i2c-gpio,= +Params: i2c_gpio_sda GPIO used for I2C data (default "23") + + i2c_gpio_scl GPIO used for I2C clock (default "24") @@ -142238,7 +136687,11 @@ index 3685f98..2e96de5 100644 + Name: i2c-rtc Info: Adds support for a number of I2C Real Time Clock devices - Load: dtoverlay=i2c-rtc, +-Load: dtoverlay=i2c-rtc, ++Load: dtoverlay=i2c-rtc,= + Params: ds1307 Select the DS1307 device + + ds3231 Select the DS3231 device diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts new file mode 100644 index 0000000..2a2dc98 @@ -142274,10 +136727,10 @@ index 0000000..2a2dc98 +}; + diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 521f9a5..bf1fad3 100644 +index 49317b9..1f47fb7 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig -@@ -588,6 +588,7 @@ CONFIG_RAW_DRIVER=y +@@ -595,6 +595,7 @@ CONFIG_RAW_DRIVER=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_BCM2708=m @@ -142286,10 +136739,10 @@ index 521f9a5..bf1fad3 100644 CONFIG_SPI_BCM2835=m CONFIG_SPI_SPIDEV=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 8faf3d6..ff1c8bf 100644 +index 202dd4b..015a2b3 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -581,6 +581,7 @@ CONFIG_RAW_DRIVER=y +@@ -588,6 +588,7 @@ CONFIG_RAW_DRIVER=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_BCM2708=m @@ -142301,10 +136754,10 @@ index 8faf3d6..ff1c8bf 100644 2.5.0 -From 668f0946ebfe3a75ace1d45befa6e3f6c7c7acb4 Mon Sep 17 00:00:00 2001 +From fd5bec91d5ce5bf001f8147a73c79bbf9d50d581 Mon Sep 17 00:00:00 2001 From: mwilliams03 Date: Sun, 18 Oct 2015 17:07:24 -0700 -Subject: [PATCH 57/78] New overlay for PiScreen2r +Subject: [PATCH 47/59] New overlay for PiScreen2r --- arch/arm/boot/dts/overlays/Makefile | 1 + @@ -142326,7 +136779,7 @@ index e15d55c..8595b14 100644 dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 2e96de5..8f66478 100644 +index d278305..3116d1a 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -425,6 +425,20 @@ Params: speed Display SPI bus speed @@ -142335,7 +136788,7 @@ index 2e96de5..8f66478 100644 +Name: piscreen2r +Info: PiScreen 2 with resistive TP display by OzzMaker.com -+Load: dtoverlay=piscreen,= ++Load: dtoverlay=piscreen2r,= +Params: speed Display SPI bus speed + + rotate Display rotation {0,90,180,270} @@ -142460,87 +136913,10 @@ index 0000000..7c018e0 2.5.0 -From 810c4479845e63c66f4ecb8f4645d9903b6a469c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= -Date: Mon, 26 Oct 2015 14:42:10 +0100 -Subject: [PATCH 58/78] config: Add TOUCHSCREEN_FT6236 - ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index bf1fad3..09a3977 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -546,6 +546,7 @@ CONFIG_JOYSTICK_RPISENSE=m - CONFIG_INPUT_TOUCHSCREEN=y - CONFIG_TOUCHSCREEN_ADS7846=m - CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_FT6236=m - CONFIG_TOUCHSCREEN_RPI_FT5406=m - CONFIG_TOUCHSCREEN_USB_COMPOSITE=m - CONFIG_TOUCHSCREEN_STMPE=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index ff1c8bf..f89eaf5 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -539,6 +539,7 @@ CONFIG_JOYSTICK_RPISENSE=m - CONFIG_INPUT_TOUCHSCREEN=y - CONFIG_TOUCHSCREEN_ADS7846=m - CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_FT6236=m - CONFIG_TOUCHSCREEN_RPI_FT5406=m - CONFIG_TOUCHSCREEN_USB_COMPOSITE=m - CONFIG_TOUCHSCREEN_STMPE=m --- -2.5.0 - - -From dbc1fc3387026c6780cae2519f9cd7f8a1009eed Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Thu, 5 Nov 2015 12:01:53 +0000 -Subject: [PATCH 59/78] config: Add MCP320X - -See: https://github.com/raspberrypi/linux/issues/1189 ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 09a3977..15e4033 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -1102,6 +1102,7 @@ CONFIG_IIO=m - CONFIG_IIO_BUFFER=y - CONFIG_IIO_BUFFER_CB=y - CONFIG_IIO_KFIFO_BUF=m -+CONFIG_MCP320X=m - CONFIG_DHT11=m - CONFIG_PWM_BCM2835=m - CONFIG_RASPBERRYPI_FIRMWARE=y -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index f89eaf5..ec2c66d 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -1095,6 +1095,7 @@ CONFIG_IIO=m - CONFIG_IIO_BUFFER=y - CONFIG_IIO_BUFFER_CB=y - CONFIG_IIO_KFIFO_BUF=m -+CONFIG_MCP320X=m - CONFIG_DHT11=m - CONFIG_PWM_BCM2835=m - CONFIG_RASPBERRYPI_FIRMWARE=y --- -2.5.0 - - -From 34bb36da26a245fc1a6c2d85fc186ebf2a61ca97 Mon Sep 17 00:00:00 2001 +From 9b04ba6644143db182164e74e06563b9064fca7f Mon Sep 17 00:00:00 2001 From: Ondrej Wisniewski Date: Fri, 6 Nov 2015 15:01:28 +0100 -Subject: [PATCH 60/78] dts: Added overlay for Adafruit PiTFT 2.8" capacitive +Subject: [PATCH 48/59] dts: Added overlay for Adafruit PiTFT 2.8" capacitive touch screen --- @@ -142563,7 +136939,7 @@ index 8595b14..7d747bc 100644 dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 8f66478..055aa5b 100644 +index 3116d1a..950b6c5 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -439,6 +439,28 @@ Params: speed Display SPI bus speed @@ -142693,495 +137069,10 @@ index 0000000..48920e9 2.5.0 -From 645245ffbaacdbb1449c21e7d600550ef665a158 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Fri, 6 Nov 2015 16:24:59 +0000 -Subject: [PATCH 61/78] rpi-ft5406: Use interruptible sleep to avoid high load - reported - ---- - drivers/input/touchscreen/rpi-ft5406.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/input/touchscreen/rpi-ft5406.c b/drivers/input/touchscreen/rpi-ft5406.c -index c08817e..b27dbee 100644 ---- a/drivers/input/touchscreen/rpi-ft5406.c -+++ b/drivers/input/touchscreen/rpi-ft5406.c -@@ -65,7 +65,7 @@ static int ft5406_thread(void *arg) - while(!kthread_should_stop()) - { - // 60fps polling -- msleep(17); -+ msleep_interruptible(17); - memcpy_fromio(®s, ts->regs, sizeof(*ts->regs)); - writel(99, &ts->regs->num_points); - // Do not output if theres no new information (num_points is 99) --- -2.5.0 - - -From 467be401ac864a86e52289666ea61b04bf54e2fd Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 17 Nov 2015 10:07:08 +0000 -Subject: [PATCH 62/78] BCM270X_DT: Fix overlay README anomalies - ---- - arch/arm/boot/dts/overlays/README | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README -index 055aa5b..950b6c5 100644 ---- a/arch/arm/boot/dts/overlays/README -+++ b/arch/arm/boot/dts/overlays/README -@@ -214,7 +214,7 @@ Params: gpio_pin Input pin number. Default is 18. - - Name: gpio-poweroff - Info: Drives a GPIO high or low on reboot --Load: gpio-poweroff,= -+Load: dtoverlay=gpio-poweroff,= - Params: gpiopin GPIO for signalling (default 26) - - active_low Set if the power control device requires a -@@ -289,7 +289,7 @@ Params: speed Display SPI bus speed - - Name: i2c-gpio - Info: Adds support for software i2c controller on gpio pins --Load: dtoverlay=i2c-gpio, -+Load: dtoverlay=i2c-gpio,= - Params: i2c_gpio_sda GPIO used for I2C data (default "23") - - i2c_gpio_scl GPIO used for I2C clock (default "24") -@@ -300,7 +300,7 @@ Params: i2c_gpio_sda GPIO used for I2C data (default "23") - - Name: i2c-rtc - Info: Adds support for a number of I2C Real Time Clock devices --Load: dtoverlay=i2c-rtc, -+Load: dtoverlay=i2c-rtc,= - Params: ds1307 Select the DS1307 device - - ds3231 Select the DS3231 device -@@ -335,7 +335,7 @@ Params: - Name: lirc-rpi - Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi) - Consult the module documentation for more details. --Load: dtoverlay=lirc-rpi,=,... -+Load: dtoverlay=lirc-rpi,= - Params: gpio_out_pin GPIO for output (default "17") - - gpio_in_pin GPIO for input (default "18") -@@ -427,7 +427,7 @@ Params: speed Display SPI bus speed - - Name: piscreen2r - Info: PiScreen 2 with resistive TP display by OzzMaker.com --Load: dtoverlay=piscreen,= -+Load: dtoverlay=piscreen2r,= - Params: speed Display SPI bus speed - - rotate Display rotation {0,90,180,270} -@@ -492,7 +492,6 @@ Info: Configures a single PWM channel - 3) So be careful mixing audio and PWM. - 4) Currently the clock must have been enabled and configured - by other means. --Load: dtoverlay=pwm-2chan,= - Load: dtoverlay=pwm,= - Params: pin Output pin (default 18) - see table - func Pin function (default 2 = Alt5) - see above -@@ -694,7 +693,7 @@ Params: gpiopin GPIO for I/O (default "4") - Name: w1-gpio-pullup - Info: Configures the w1-gpio Onewire interface module. - Use this overlay if you *do* need a GPIO to drive an external pullup. --Load: dtoverlay=w1-gpio-pullup,=,... -+Load: dtoverlay=w1-gpio-pullup,= - Params: gpiopin GPIO for I/O (default "4") - - pullup Non-zero, "on", or "y" to enable the parasitic --- -2.5.0 - - -From 617ce95131bf691678da16e82a14f2857dbe5590 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 1 Dec 2015 16:52:13 +0000 -Subject: [PATCH 63/78] BCM270X_DT: Use clk_core for I2C interfaces - ---- - arch/arm/boot/dts/bcm2708_common.dtsi | 43 +++++++++++++++-------------------- - 1 file changed, 18 insertions(+), 25 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index ec94d9f5..d65586f 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -158,7 +158,7 @@ - compatible = "brcm,bcm2708-i2c"; - reg = <0x7e205000 0x1000>; - interrupts = <2 21>; -- clocks = <&clk_i2c>; -+ clocks = <&clk_core>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -197,7 +197,7 @@ - compatible = "brcm,bcm2708-i2c"; - reg = <0x7e804000 0x1000>; - interrupts = <2 21>; -- clocks = <&clk_i2c>; -+ clocks = <&clk_core>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -210,7 +210,7 @@ - compatible = "brcm,bcm2708-i2c"; - reg = <0x7e805000 0x1000>; - interrupts = <2 21>; -- clocks = <&clk_i2c>; -+ clocks = <&clk_core>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -269,56 +269,49 @@ - #address-cells = <1>; - #size-cells = <0>; - -- clk_mmc: clock@0 { -+ clk_core: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; -- clock-output-names = "mmc"; -+ clock-output-names = "core"; - clock-frequency = <250000000>; - }; - -- clk_i2c: clock@1 { -+ clk_mmc: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; -- clock-output-names = "i2c"; -+ clock-output-names = "mmc"; - clock-frequency = <250000000>; - }; - -- clk_core: clock@2 { -+ clk_uart0: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - #clock-cells = <0>; -- clock-output-names = "core"; -- clock-frequency = <250000000>; -- }; -- -- clk_uart0: clock@3 { -- compatible = "fixed-clock"; -- reg = <3>; -- #clock-cells = <0>; - clock-output-names = "uart0_pclk"; - clock-frequency = <3000000>; - }; - -- clk_apb_p: clock@4 { -+ clk_apb_p: clock@3 { - compatible = "fixed-clock"; -- reg = <4>; -+ reg = <3>; - #clock-cells = <0>; - clock-output-names = "apb_pclk"; - clock-frequency = <126000000>; - }; - -- clk_pwm: clock@5 { -- compatible = "fixed-clock"; -- reg = <3>; -- #clock-cells = <0>; -- clock-output-names = "pwm"; -- clock-frequency = <100000000>; -+ clk_pwm: clock@4 { -+ compatible = "fixed-clock"; -+ reg = <4>; -+ #clock-cells = <0>; -+ clock-output-names = "pwm"; -+ clock-frequency = <100000000>; - }; - -- clk_uart1: clock@6 { -+ clk_uart1: clock@5 { - compatible = "fixed-factor-clock"; -+ reg = <5>; - clocks = <&clk_core>; - #clock-cells = <0>; - clock-div = <1>; --- -2.5.0 - - -From 7ae1428955b29e9dc777444cd30e4dc1ca3c9094 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Fri, 20 Jun 2014 17:19:27 +0100 -Subject: [PATCH 64/78] bcm2709: Simplify and strip down IRQ handler - ---- - arch/arm/include/asm/entry-macro-multi.S | 2 + - arch/arm/mach-bcm2709/include/mach/entry-macro.S | 173 +++++++++++------------ - 2 files changed, 87 insertions(+), 88 deletions(-) - -diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S -index 609184f..693cc1f 100644 ---- a/arch/arm/include/asm/entry-macro-multi.S -+++ b/arch/arm/include/asm/entry-macro-multi.S -@@ -1,5 +1,6 @@ - #include - -+#ifndef CONFIG_ARCH_BCM2709 - /* - * Interrupt handling. Preserves r7, r8, r9 - */ -@@ -28,6 +29,7 @@ - #endif - 9997: - .endm -+#endif - - .macro arch_irq_handler, symbol_name - .align 5 -diff --git a/arch/arm/mach-bcm2709/include/mach/entry-macro.S b/arch/arm/mach-bcm2709/include/mach/entry-macro.S -index d08591b..2e9f458 100644 ---- a/arch/arm/mach-bcm2709/include/mach/entry-macro.S -+++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S -@@ -22,102 +22,99 @@ - #include - #include - -- .macro disable_fiq -- .endm -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm - -- .macro get_irqnr_preamble, base, tmp -- ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) -- .endm -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - -- .macro arch_ret_to_user, tmp1, tmp2 -- .endm -+ /* get core number */ -+ mrc p15, 0, \base, c0, c0, 5 -+ ubfx \base, \base, #0, #2 - -- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -- /* get core number */ -- mrc p15, 0, \tmp, c0, c0, 5 -- ubfx \tmp, \tmp, #0, #2 -+ /* get core's local interrupt controller */ -+ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source -+ add \irqstat, \irqstat, \base, lsl #2 -+ ldr \tmp, [\irqstat] -+#ifdef CONFIG_SMP -+ /* test for mailbox0 (IPI) interrupt */ -+ tst \tmp, #0x10 -+ beq 1030f - -- /* get core's local interrupt controller */ -- ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source -- add \irqstat, \irqstat, \tmp, lsl #2 -- ldr \tmp, [\irqstat] -- /* ignore gpu interrupt */ -- bic \tmp, #0x100 -- /* ignore mailbox interrupts */ -- bics \tmp, #0xf0 -- beq 1005f -+ /* get core's mailbox interrupt control */ -+ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr -+ add \irqstat, \irqstat, \base, lsl #4 -+ ldr \tmp, [\irqstat] -+ clz \tmp, \tmp -+ rsb \irqnr, \tmp, #31 -+ mov \tmp, #1 -+ lsl \tmp, \irqnr -+ str \tmp, [\irqstat] @ clear interrupt source -+ dsb -+ mov r1, sp -+ badr lr, 1b -+ b do_IPI -+#endif -+1030: -+ /* check gpu interrupt */ -+ tst \tmp, #0x100 -+ beq 1040f - -- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -- @ N.B. CLZ is an ARM5 instruction. -- mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) -- sub \irqstat, \tmp, #1 -- eor \irqstat, \irqstat, \tmp -- clz \tmp, \irqstat -- sub \irqnr, \tmp -- b 1020f --1005: -- /* get core number */ -- mrc p15, 0, \tmp, c0, c0, 5 -- ubfx \tmp, \tmp, #0, #2 -+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) -+ /* get masked status */ -+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] -+ mov \irqnr, #(ARM_IRQ0_BASE + 31) -+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 -+ /* clear bits 8 and 9, and test */ -+ bics \irqstat, \irqstat, #0x300 -+ bne 1010f - -- cmp \tmp, #1 -- beq 1020f -- cmp \tmp, #2 -- beq 1020f -- cmp \tmp, #3 -- beq 1020f -- -- /* get masked status */ -- ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] -- mov \irqnr, #(ARM_IRQ0_BASE + 31) -- and \tmp, \irqstat, #0x300 @ save bits 8 and 9 -- /* clear bits 8 and 9, and test */ -- bics \irqstat, \irqstat, #0x300 -- bne 1010f -- -- tst \tmp, #0x100 -- ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] -- movne \irqnr, #(ARM_IRQ1_BASE + 31) -- @ Mask out the interrupts also present in PEND0 - see SW-5809 -- bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) -- bicne \irqstat, #((1<<18) | (1<<19)) -- bne 1010f -- -- tst \tmp, #0x200 -- ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] -- movne \irqnr, #(ARM_IRQ2_BASE + 31) -- @ Mask out the interrupts also present in PEND0 - see SW-5809 -- bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) -- bicne \irqstat, #((1<<30)) -- beq 1020f -+ tst \tmp, #0x100 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ1_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) -+ bicne \irqstat, #((1<<18) | (1<<19)) -+ bne 1010f - -+ tst \tmp, #0x200 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ2_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) -+ bicne \irqstat, #((1<<30)) -+ beq 1020f - 1010: -- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -- @ N.B. CLZ is an ARM5 instruction. -- sub \tmp, \irqstat, #1 -- eor \irqstat, \irqstat, \tmp -- clz \tmp, \irqstat -- sub \irqnr, \tmp -+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -+ sub \tmp, \irqstat, #1 -+ eor \irqstat, \irqstat, \tmp -+ clz \tmp, \irqstat -+ sub \irqnr, \tmp -+ b 1050f -+1040: -+ cmp \tmp, #0 -+ beq 1020f - --1020: @ EQ will be set if no irqs pending -+ /* handle local (e.g. timer) interrupts */ -+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -+ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) -+ sub \irqstat, \tmp, #1 -+ eor \irqstat, \irqstat, \tmp -+ clz \tmp, \irqstat -+ sub \irqnr, \tmp -+1050: -+ mov r1, sp -+ @ -+ @ routine called with r0 = irq number, r1 = struct pt_regs * -+ @ -+ badr lr, 1b -+ b asm_do_IRQ - -- .endm -+1020: @ EQ will be set if no irqs pending -+ .endm - -- .macro test_for_ipi, irqnr, irqstat, base, tmp -- /* get core number */ -- mrc p15, 0, \tmp, c0, c0, 5 -- ubfx \tmp, \tmp, #0, #2 -- /* get core's mailbox interrupt control */ -- ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr -- add \irqstat, \irqstat, \tmp, lsl #4 -- ldr \tmp, [\irqstat] -- cmp \tmp, #0 -- beq 1030f -- clz \tmp, \tmp -- rsb \irqnr, \tmp, #31 -- mov \tmp, #1 -- lsl \tmp, \irqnr -- str \tmp, [\irqstat] @ clear interrupt source -- dsb --1030: @ EQ will be set if no irqs pending -- .endm -+/* -+ * Interrupt handling. Preserves r7, r8, r9 -+ */ -+ .macro arch_irq_handler_default -+1: get_irqnr_and_base r0, r2, r6, lr -+ .endm --- -2.5.0 - - -From 58012b5ab2f4b33b1eff7c9cabc58cfd2c88846a Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 1 Oct 2015 11:49:11 +0100 -Subject: [PATCH 65/78] config: Add CONFIG_UHID - ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 15e4033..9dfb048 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -846,6 +846,7 @@ CONFIG_SND_SOC_WM8804_I2C=m - CONFIG_SND_SIMPLE_CARD=m - CONFIG_SOUND_PRIME=m - CONFIG_HIDRAW=y -+CONFIG_UHID=m - CONFIG_HID_A4TECH=m - CONFIG_HID_ACRUX=m - CONFIG_HID_APPLE=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index ec2c66d..e31e679 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -839,6 +839,7 @@ CONFIG_SND_SOC_WM8804_I2C=m - CONFIG_SND_SIMPLE_CARD=m - CONFIG_SOUND_PRIME=m - CONFIG_HIDRAW=y -+CONFIG_UHID=m - CONFIG_HID_A4TECH=m - CONFIG_HID_ACRUX=m - CONFIG_HID_APPLE=m --- -2.5.0 - - -From e7080c6297e629a18046968f232461824a2f2d72 Mon Sep 17 00:00:00 2001 +From 22cc43d30298abcdac34ef08074d87104be8edeb Mon Sep 17 00:00:00 2001 From: Stuart MacLean Date: Fri, 2 Oct 2015 15:12:59 +0100 -Subject: [PATCH 66/78] Add support for the HiFiBerry DAC+ Pro. +Subject: [PATCH 49/59] Add support for the HiFiBerry DAC+ Pro. The HiFiBerry DAC+ and DAC+ Pro products both use the existing bcm sound driver with the DAC+ Pro having a special clock device driver representing the two high precision oscillators. @@ -143732,111 +137623,10 @@ index 047c489..090fe0e 100644 2.5.0 -From 3eab6924ad8a517f7422d85384aa687a98c8fe68 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sun, 4 Oct 2015 12:30:01 +0100 -Subject: [PATCH 67/78] config: Add CONFIG_CRYPTO_USER_API_SKCIPHER - ---- - arch/arm/configs/bcm2709_defconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index 9dfb048..b39f072 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -1244,6 +1244,7 @@ CONFIG_CRYPTO_TGR192=m - CONFIG_CRYPTO_WP512=m - CONFIG_CRYPTO_CAST5=m - CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_USER_API_SKCIPHER=m - # CONFIG_CRYPTO_HW is not set - CONFIG_ARM_CRYPTO=y - CONFIG_CRYPTO_SHA1_ARM_NEON=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index e31e679..d6e29f1 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -1240,6 +1240,7 @@ CONFIG_CRYPTO_TGR192=m - CONFIG_CRYPTO_WP512=m - CONFIG_CRYPTO_CAST5=m - CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_USER_API_SKCIPHER=m - # CONFIG_CRYPTO_HW is not set - CONFIG_ARM_CRYPTO=y - CONFIG_CRYPTO_SHA1_ARM=m --- -2.5.0 - - -From fafb57bc3b6c61170a15ce3635bcb30a016fc500 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sun, 4 Oct 2015 12:36:44 +0100 -Subject: [PATCH 68/78] config: Add options for supporting openlabs 802.15.4 - radio - ---- - arch/arm/configs/bcm2709_defconfig | 6 ++++++ - arch/arm/configs/bcmrpi_defconfig | 6 ++++++ - 2 files changed, 12 insertions(+) - -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index b39f072..be6cda9 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -284,6 +284,9 @@ CONFIG_VLAN_8021Q=m - CONFIG_VLAN_8021Q_GVRP=y - CONFIG_ATALK=m - CONFIG_6LOWPAN=m -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_MAC802154=m - CONFIG_NET_SCHED=y - CONFIG_NET_SCH_CBQ=m - CONFIG_NET_SCH_HTB=m -@@ -530,6 +533,9 @@ CONFIG_ZD1211RW=m - CONFIG_MWIFIEX=m - CONFIG_MWIFIEX_SDIO=m - CONFIG_WIMAX_I2400M_USB=m -+CONFIG_IEEE802154_AT86RF230=m -+CONFIG_IEEE802154_MRF24J40=m -+CONFIG_IEEE802154_CC2520=m - CONFIG_INPUT_POLLDEV=m - # CONFIG_INPUT_MOUSEDEV_PSAUX is not set - CONFIG_INPUT_JOYDEV=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index d6e29f1..9e5cd8b 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -277,6 +277,9 @@ CONFIG_VLAN_8021Q=m - CONFIG_VLAN_8021Q_GVRP=y - CONFIG_ATALK=m - CONFIG_6LOWPAN=m -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_MAC802154=m - CONFIG_NET_SCHED=y - CONFIG_NET_SCH_CBQ=m - CONFIG_NET_SCH_HTB=m -@@ -523,6 +526,9 @@ CONFIG_ZD1211RW=m - CONFIG_MWIFIEX=m - CONFIG_MWIFIEX_SDIO=m - CONFIG_WIMAX_I2400M_USB=m -+CONFIG_IEEE802154_AT86RF230=m -+CONFIG_IEEE802154_MRF24J40=m -+CONFIG_IEEE802154_CC2520=m - CONFIG_INPUT_POLLDEV=m - # CONFIG_INPUT_MOUSEDEV_PSAUX is not set - CONFIG_INPUT_JOYDEV=m --- -2.5.0 - - -From 42cec9005a9c814c381c222181e48f6ed03e41a2 Mon Sep 17 00:00:00 2001 +From 855f9adc802916fa951051daf6ee6af440888688 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 5 Oct 2015 10:47:45 +0100 -Subject: [PATCH 69/78] BCM270X_DT: Add at86rf233 overlay +Subject: [PATCH 50/59] BCM270X_DT: Add at86rf233 overlay Add an overlay to support the Atmel AT86RF233 WPAN transceiver on spi0.0. @@ -143974,167 +137764,10 @@ index 0000000..0460269 2.5.0 -From c18a95d9c8207eba62ea3cab76a1bce8921fc38d Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Fri, 9 Oct 2015 10:49:00 +0100 -Subject: [PATCH 70/78] BCM270X_DT: Make mmc overlay compatible with current - firmware - -The original DT overlay logic followed a merge-then-patch procedure, -i.e. parameters are applied to the loaded overlay before the overlay -is merged into the base DTB. This sequence has been changed to -patch-then-merge, in order to support parameterised node names, and -to protect against bad overlays. As a result, overrides (parameters) -must only target labels in the overlay, but the overlay can obviously target nodes in the base DTB. - -mmc-overlay.dts (that switches back to the original mmc sdcard -driver) is the only overlay violating that rule, and this patch -fixes it. ---- - arch/arm/boot/dts/overlays/mmc-overlay.dts | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/boot/dts/overlays/mmc-overlay.dts b/arch/arm/boot/dts/overlays/mmc-overlay.dts -index 0a37cf4..4579ff2 100644 ---- a/arch/arm/boot/dts/overlays/mmc-overlay.dts -+++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts -@@ -7,13 +7,13 @@ - fragment@0 { - target = <&mmc>; - -- __overlay__ { -+ frag0: __overlay__ { - brcm,overclock-50 = <0>; - }; - }; - - __overrides__ { -- overclock_50 = <&mmc>,"brcm,overclock-50:0"; -- force_pio = <&mmc>,"brcm,force-pio?"; -+ overclock_50 = <&frag0>,"brcm,overclock-50:0"; -+ force_pio = <&frag0>,"brcm,force-pio?"; - }; - }; --- -2.5.0 - - -From 2f2049567814503ea3738dfea9fc1eaa502924cb Mon Sep 17 00:00:00 2001 -From: Eric Anholt -Date: Tue, 13 Oct 2015 13:26:43 -0700 -Subject: [PATCH 71/78] bcm2708: Use #include in dtsi files. - -This will let us include dt-bindings headers and use symbolic names in -various cases. - -Signed-off-by: Eric Anholt ---- - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 2 +- - arch/arm/boot/dts/bcm2708-rpi-b.dts | 2 +- - arch/arm/boot/dts/bcm2708-rpi-cm.dts | 2 +- - arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 2 +- - arch/arm/boot/dts/bcm2708.dtsi | 2 +- - arch/arm/boot/dts/bcm2708_common.dtsi | 2 +- - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 2 +- - arch/arm/boot/dts/bcm2709.dtsi | 2 +- - 8 files changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -index ffb7596..cd22780 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2708.dtsi" -+#include "bcm2708.dtsi" - - / { - compatible = "brcm,bcm2708"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts -index 8551159..0d7524e 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2708.dtsi" -+#include "bcm2708.dtsi" - - / { - compatible = "brcm,bcm2708"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -index 1f7ec88..587f1e4 100755 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2708-rpi-cm.dtsi" -+#include "bcm2708-rpi-cm.dtsi" - - / { - model = "Raspberry Pi Compute Module"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -index 713e5a2..2acefee 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -@@ -1,4 +1,4 @@ --/include/ "bcm2708.dtsi" -+#include "bcm2708.dtsi" - - &leds { - act_led: act { -diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi -index 42acf77..f5a44cd 100644 ---- a/arch/arm/boot/dts/bcm2708.dtsi -+++ b/arch/arm/boot/dts/bcm2708.dtsi -@@ -1,4 +1,4 @@ --/include/ "bcm2708_common.dtsi" -+#include "bcm2708_common.dtsi" - - / { - compatible = "brcm,bcm2708"; -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index d65586f..78ee8a0 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -1,4 +1,4 @@ --/include/ "skeleton.dtsi" -+#include "skeleton.dtsi" - - / { - interrupt-parent = <&intc>; -diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -index 7a05dab5..f45aa50 100644 ---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -1,6 +1,6 @@ - /dts-v1/; - --/include/ "bcm2709.dtsi" -+#include "bcm2709.dtsi" - - / { - compatible = "brcm,bcm2709"; -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi -index d21f5f0..d946c39 100644 ---- a/arch/arm/boot/dts/bcm2709.dtsi -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -1,4 +1,4 @@ --/include/ "bcm2708_common.dtsi" -+#include "bcm2708_common.dtsi" - - / { - compatible = "brcm,bcm2709"; --- -2.5.0 - - -From 0f20b7af7c5a1409fb2f108cff7a68ee9d56df70 Mon Sep 17 00:00:00 2001 +From cb447e6fe0a7f42f915c46362aad4944da91518f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 18 Dec 2014 16:07:15 -0800 -Subject: [PATCH 72/78] mm: Remove the PFN busy warning +Subject: [PATCH 51/59] mm: Remove the PFN busy warning See commit dae803e165a11bc88ca8dbc07a11077caf97bbcb -- the warning is expected sometimes when using CMA. However, that commit still spams @@ -144162,10 +137795,10 @@ index 9d666df..b682acc 100644 2.5.0 -From cbd651899ad2207b1381ed876fd4b854fa304182 Mon Sep 17 00:00:00 2001 +From d3ab193e2ccff0b434de0606b3c99802efb6c7b4 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 19 Nov 2014 12:06:38 -0800 -Subject: [PATCH 73/78] drm: Put an optional field in the driver struct for GEM +Subject: [PATCH 52/59] drm: Put an optional field in the driver struct for GEM obj struct size. This allows a driver to derive from the CMA object without copying all @@ -144210,500 +137843,3873 @@ index 0a271ca..54f5469 100644 2.5.0 -From b447ac04854ba93dec690be7f0b49e3060eaa79c Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Thu, 3 Dec 2015 15:50:29 +0000 -Subject: [PATCH 74/78] lirc-rpi: FIXUP correct error code (should be negative) +From 4eaaf2ad0c84b80573e15529570380a95b6cbfdf Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 30 Oct 2015 10:09:02 -0700 +Subject: [PATCH 53/59] drm/vc4: Add an interface for capturing the GPU state + after a hang. +This can be parsed with vc4-gpu-tools tools for trying to figure out +what was going on. + +Signed-off-by: Eric Anholt --- - drivers/staging/media/lirc/lirc_rpi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + drivers/gpu/drm/vc4/vc4_bo.c | 4 +- + drivers/gpu/drm/vc4/vc4_drv.c | 1 + + drivers/gpu/drm/vc4/vc4_drv.h | 4 + + drivers/gpu/drm/vc4/vc4_gem.c | 185 ++++++++++++++++++++++++++++++++++++++++++ + include/uapi/drm/vc4_drm.h | 45 ++++++++++ + 5 files changed, 237 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c -index f1e0de9..cd09c99 100644 ---- a/drivers/staging/media/lirc/lirc_rpi.c -+++ b/drivers/staging/media/lirc/lirc_rpi.c -@@ -383,7 +383,7 @@ static int init_port(void) - read_bool_property(node, "rpi,debug", &debug); +diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c +index acd360c..58dcbae 100644 +--- a/drivers/gpu/drm/vc4/vc4_bo.c ++++ b/drivers/gpu/drm/vc4/vc4_bo.c +@@ -415,8 +415,8 @@ int vc4_mmap(struct file *filp, struct vm_area_struct *vma) + gem_obj = vma->vm_private_data; + bo = to_vc4_bo(gem_obj); - } else { -- return EINVAL; -+ return -EINVAL; +- if (bo->validated_shader) { +- DRM_ERROR("mmaping of shader BOs not allowed.\n"); ++ if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { ++ DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); + return -EINVAL; } - gpiochip->set(gpiochip, gpio_out_pin, invert); --- -2.5.0 - - -From c5ad8fb0191bd436a157bec1bbc596604ee2ff1e Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Fri, 4 Dec 2015 10:46:53 +0000 -Subject: [PATCH 75/78] FIXUP BCM270X_DT: Use clk_core for I2C interfaces - -Renumber clk_osc to close the gap ---- - arch/arm/boot/dts/bcm2708_common.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index 78ee8a0..91ff784 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -319,9 +319,9 @@ - }; - - /* The oscillator is the root of the clock tree. */ -- clk_osc: clock@7 { -+ clk_osc: clock@6 { - compatible = "fixed-clock"; -- reg = <7>; -+ reg = <6>; - #clock-cells = <0>; - clock-output-names = "osc"; - clock-frequency = <19200000>; --- -2.5.0 - - -From 38ea23c3ab5d649fbcc10e3ad8b4fb9961dc32dc Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Tue, 8 Dec 2015 16:23:33 +0000 -Subject: [PATCH 76/78] bcm270x_dt: Use the sdhost MMC controller by default - -The "mmc" overlay reverts to using the other controller. ---- - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 11 ++++-- - arch/arm/boot/dts/bcm2708-rpi-b.dts | 11 ++++-- - arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 14 ++++++-- - arch/arm/boot/dts/bcm2708_common.dtsi | 13 +++++++ - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 11 ++++-- - arch/arm/boot/dts/overlays/mmc-overlay.dts | 22 +++++++++++- - arch/arm/boot/dts/overlays/sdhost-overlay.dts | 49 ++++++--------------------- - arch/arm/boot/dts/overlays/sdio-overlay.dts | 1 - - 8 files changed, 84 insertions(+), 48 deletions(-) - -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -index cd22780..4deb968 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -8,6 +8,11 @@ +diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c +index e2a2be2..e8192b4 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.c ++++ b/drivers/gpu/drm/vc4/vc4_drv.c +@@ -81,6 +81,7 @@ static const struct drm_ioctl_desc vc4_drm_ioctls[] = { + DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0), ++ DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_ROOT_ONLY), }; - &gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; + static struct drm_driver vc4_drm_driver = { +diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h +index c079b82..24845c1 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.h ++++ b/drivers/gpu/drm/vc4/vc4_drv.h +@@ -20,6 +20,8 @@ struct vc4_dev { + struct drm_fbdev_cma *fbdev; + struct rpi_firmware *firmware; + ++ struct vc4_hang_state *hang_state; + - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ -@@ -34,9 +39,11 @@ - }; - }; + /* The kernel-space BO cache. Tracks buffers that have been + * unreferenced by all other users (refcounts of 0!) but not + * yet freed, so we can do cheap allocations. +@@ -366,6 +368,8 @@ int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); + int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); ++int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); + int vc4_mmap(struct file *filp, struct vm_area_struct *vma); + int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); + void *vc4_prime_vmap(struct drm_gem_object *obj); +diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c +index 0cea723..d90c664 100644 +--- a/drivers/gpu/drm/vc4/vc4_gem.c ++++ b/drivers/gpu/drm/vc4/vc4_gem.c +@@ -40,6 +40,186 @@ vc4_queue_hangcheck(struct drm_device *dev) + round_jiffies_up(jiffies + msecs_to_jiffies(100))); + } --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts -index 0d7524e..1e77926 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -8,6 +8,11 @@ - }; - - &gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; ++struct vc4_hang_state { ++ struct drm_vc4_get_hang_state user_state; + - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ -@@ -34,9 +39,11 @@ - }; - }; - --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -index 2acefee..3c8bdde 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -@@ -1,5 +1,12 @@ - #include "bcm2708.dtsi" - -+&gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; ++ u32 bo_count; ++ struct drm_gem_object **bo; +}; + - &leds { - act_led: act { - label = "led0"; -@@ -8,9 +15,12 @@ - }; - }; - --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ non-removable; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi -index 91ff784..75fb4ce 100644 ---- a/arch/arm/boot/dts/bcm2708_common.dtsi -+++ b/arch/arm/boot/dts/bcm2708_common.dtsi -@@ -14,6 +14,7 @@ - mailbox = &mailbox; - gpio = &gpio; - uart0 = &uart0; -+ sdhost = &sdhost; - i2s = &i2s; - spi0 = &spi0; - i2c0 = &i2c0; -@@ -126,6 +127,18 @@ - status = "disabled"; - }; - -+ sdhost: sdhost@7e202000 { -+ compatible = "brcm,bcm2835-sdhost"; -+ reg = <0x7e202000 0x100>; -+ interrupts = <2 24>; -+ clocks = <&clk_core>; -+ dmas = <&dma 13>, -+ <&dma 13>; -+ dma-names = "tx", "rx"; -+ brcm,pio-limit = <1>; -+ status = "disabled"; -+ }; ++static void ++vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state) ++{ ++ unsigned int i; + - i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>, -diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -index f45aa50..4e6c64e 100644 ---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -8,6 +8,11 @@ - }; - - &gpio { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; ++ mutex_lock(&dev->struct_mutex); ++ for (i = 0; i < state->user_state.bo_count; i++) { ++ drm_gem_object_unreference(state->bo[i]); ++ } ++ mutex_unlock(&dev->struct_mutex); + - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ -@@ -34,9 +39,11 @@ - }; - }; - --&mmc { -- status = "okay"; -+&sdhost { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; - bus-width = <4>; -+ status = "okay"; - }; - - &fb { -diff --git a/arch/arm/boot/dts/overlays/mmc-overlay.dts b/arch/arm/boot/dts/overlays/mmc-overlay.dts -index 4579ff2..00a22be 100644 ---- a/arch/arm/boot/dts/overlays/mmc-overlay.dts -+++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts -@@ -6,9 +6,29 @@ - - fragment@0 { - target = <&mmc>; -- - frag0: __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc_pins>; -+ bus-width = <4>; - brcm,overclock-50 = <0>; -+ status = "okay"; -+ }; -+ }; ++ kfree(state); ++} + -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ mmc_pins: mmc_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <7>; /* alt3 */ -+ }; -+ }; -+ }; ++int ++vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ struct drm_vc4_get_hang_state *get_state = data; ++ struct drm_vc4_get_hang_state_bo *bo_state; ++ struct vc4_hang_state *kernel_state; ++ struct drm_vc4_get_hang_state *state; ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ unsigned long irqflags; ++ u32 i; ++ int ret; + -+ fragment@2 { -+ target = <&sdhost>; -+ __overlay__ { -+ status = "disabled"; - }; - }; ++ spin_lock_irqsave(&vc4->job_lock, irqflags); ++ kernel_state = vc4->hang_state; ++ if (!kernel_state) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return -ENOENT; ++ } ++ state = &kernel_state->user_state; ++ ++ /* If the user's array isn't big enough, just return the ++ * required array size. ++ */ ++ if (get_state->bo_count < state->bo_count) { ++ get_state->bo_count = state->bo_count; ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return 0; ++ } ++ ++ vc4->hang_state = NULL; ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ ++ /* Save the user's BO pointer, so we don't stomp it with the memcpy. */ ++ state->bo = get_state->bo; ++ memcpy(get_state, state, sizeof(*state)); ++ ++ bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL); ++ if (!bo_state) { ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ ++ for (i = 0; i < state->bo_count; i++) { ++ struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]); ++ u32 handle; ++ ret = drm_gem_handle_create(file_priv, kernel_state->bo[i], ++ &handle); ++ ++ if (ret) { ++ state->bo_count = i - 1; ++ goto err; ++ } ++ bo_state[i].handle = handle; ++ bo_state[i].paddr = vc4_bo->base.paddr; ++ bo_state[i].size = vc4_bo->base.base.size; ++ } ++ ++ ret = copy_to_user((void __user *)(uintptr_t)get_state->bo, ++ bo_state, ++ state->bo_count * sizeof(*bo_state)); ++ kfree(bo_state); ++ ++ err_free: ++ ++ vc4_free_hang_state(dev, kernel_state); ++ ++err: ++ return ret; ++} ++ ++static void ++vc4_save_hang_state(struct drm_device *dev) ++{ ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ struct drm_vc4_get_hang_state *state; ++ struct vc4_hang_state *kernel_state; ++ struct vc4_exec_info *exec; ++ struct vc4_bo *bo; ++ unsigned long irqflags; ++ unsigned int i, unref_list_count; ++ ++ kernel_state = kcalloc(1, sizeof(*state), GFP_KERNEL); ++ if (!kernel_state) ++ return; ++ ++ state = &kernel_state->user_state; ++ ++ spin_lock_irqsave(&vc4->job_lock, irqflags); ++ exec = vc4_first_job(vc4); ++ if (!exec) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return; ++ } ++ ++ unref_list_count = 0; ++ list_for_each_entry(bo, &exec->unref_list, unref_head) ++ unref_list_count++; ++ ++ state->bo_count = exec->bo_count + unref_list_count; ++ kernel_state->bo = kcalloc(state->bo_count, sizeof(*kernel_state->bo), ++ GFP_ATOMIC); ++ if (!kernel_state->bo) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ return; ++ } ++ ++ for (i = 0; i < exec->bo_count; i++) { ++ drm_gem_object_reference(&exec->bo[i].bo->base); ++ kernel_state->bo[i] = &exec->bo[i].bo->base; ++ } ++ ++ list_for_each_entry(bo, &exec->unref_list, unref_head) { ++ drm_gem_object_reference(&bo->base.base); ++ kernel_state->bo[i] = &bo->base.base; ++ i++; ++ } ++ ++ state->start_bin = exec->ct0ca; ++ state->start_render = exec->ct1ca; ++ ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ ++ state->ct0ca = V3D_READ(V3D_CTNCA(0)); ++ state->ct0ea = V3D_READ(V3D_CTNEA(0)); ++ ++ state->ct1ca = V3D_READ(V3D_CTNCA(1)); ++ state->ct1ea = V3D_READ(V3D_CTNEA(1)); ++ ++ state->ct0cs = V3D_READ(V3D_CTNCS(0)); ++ state->ct1cs = V3D_READ(V3D_CTNCS(1)); ++ ++ state->ct0ra0 = V3D_READ(V3D_CT00RA0); ++ state->ct1ra0 = V3D_READ(V3D_CT01RA0); ++ ++ state->bpca = V3D_READ(V3D_BPCA); ++ state->bpcs = V3D_READ(V3D_BPCS); ++ state->bpoa = V3D_READ(V3D_BPOA); ++ state->bpos = V3D_READ(V3D_BPOS); ++ ++ state->vpmbase = V3D_READ(V3D_VPMBASE); ++ ++ state->dbge = V3D_READ(V3D_DBGE); ++ state->fdbgo = V3D_READ(V3D_FDBGO); ++ state->fdbgb = V3D_READ(V3D_FDBGB); ++ state->fdbgr = V3D_READ(V3D_FDBGR); ++ state->fdbgs = V3D_READ(V3D_FDBGS); ++ state->errstat = V3D_READ(V3D_ERRSTAT); ++ ++ spin_lock_irqsave(&vc4->job_lock, irqflags); ++ if (vc4->hang_state) { ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ vc4_free_hang_state(dev, kernel_state); ++ } else { ++ vc4->hang_state = kernel_state; ++ spin_unlock_irqrestore(&vc4->job_lock, irqflags); ++ } ++} ++ + static void + vc4_reset(struct drm_device *dev) + { +@@ -64,6 +244,8 @@ vc4_reset_work(struct work_struct *work) + struct vc4_dev *vc4 = + container_of(work, struct vc4_dev, hangcheck.reset_work); -diff --git a/arch/arm/boot/dts/overlays/sdhost-overlay.dts b/arch/arm/boot/dts/overlays/sdhost-overlay.dts -index 2da14a4..85f0725 100644 ---- a/arch/arm/boot/dts/overlays/sdhost-overlay.dts -+++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts -@@ -5,52 +5,25 @@ - compatible = "brcm,bcm2708"; ++ vc4_save_hang_state(vc4->dev); ++ + vc4_reset(vc4->dev); + } - fragment@0 { -- target = <&soc>; -+ target = <&mmc>; - __overlay__ { -- #address-cells = <1>; -- #size-cells = <1>; -- -- sdhost: sdhost@7e202000 { -- compatible = "brcm,bcm2835-sdhost"; -- reg = <0x7e202000 0x100>; -- pinctrl-names = "default"; -- pinctrl-0 = <&sdhost_pins>; -- interrupts = <2 24>; -- clocks = <&clk_core>; -- dmas = <&dma 13>, -- <&dma 13>; -- dma-names = "tx", "rx"; -- brcm,delay-after-stop = <0>; -- brcm,overclock-50 = <0>; -- brcm,pio-limit = <1>; -- status = "okay"; -- }; -+ status = "disabled"; - }; - }; +@@ -673,4 +855,7 @@ vc4_gem_destroy(struct drm_device *dev) + } - fragment@1 { -- target = <&gpio>; -- __overlay__ { -- sdhost_pins: sdhost_pins { -- brcm,pins = <48 49 50 51 52 53>; -- brcm,function = <4>; /* alt0 */ -- }; -- }; -- }; -- -- fragment@2 { -- target = <&mmc>; -- __overlay__ { -- /* Find a way to disable the other driver */ -- compatible = ""; -- status = "disabled"; -+ target = <&sdhost>; -+ frag1: __overlay__ { -+ brcm,overclock-50 = <0>; -+ brcm,pio-limit = <1>; -+ status = "okay"; - }; - }; + vc4_bo_cache_destroy(dev); ++ ++ if (vc4->hang_state) ++ vc4_free_hang_state(dev, vc4->hang_state); + } +diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h +index 499daae..4a8d19f 100644 +--- a/include/uapi/drm/vc4_drm.h ++++ b/include/uapi/drm/vc4_drm.h +@@ -32,6 +32,7 @@ + #define DRM_VC4_CREATE_BO 0x03 + #define DRM_VC4_MMAP_BO 0x04 + #define DRM_VC4_CREATE_SHADER_BO 0x05 ++#define DRM_VC4_GET_HANG_STATE 0x06 - __overrides__ { -- overclock_50 = <&sdhost>,"brcm,overclock-50:0"; -- force_pio = <&sdhost>,"brcm,force-pio?"; -- pio_limit = <&sdhost>,"brcm,pio-limit:0"; -- debug = <&sdhost>,"brcm,debug?"; -+ overclock_50 = <&frag1>,"brcm,overclock-50:0"; -+ force_pio = <&frag1>,"brcm,force-pio?"; -+ pio_limit = <&frag1>,"brcm,pio-limit:0"; -+ debug = <&frag1>,"brcm,debug?"; - }; + #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) + #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) +@@ -39,6 +40,7 @@ + #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) + #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) + #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) ++#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) + + struct drm_vc4_submit_rcl_surface { + uint32_t hindex; /* Handle index, or ~0 if not present. */ +@@ -226,4 +228,47 @@ struct drm_vc4_mmap_bo { + uint64_t offset; }; -diff --git a/arch/arm/boot/dts/overlays/sdio-overlay.dts b/arch/arm/boot/dts/overlays/sdio-overlay.dts -index 6626a1d..afc8742 100644 ---- a/arch/arm/boot/dts/overlays/sdio-overlay.dts -+++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts -@@ -8,7 +8,6 @@ - fragment@3 { - target = <&mmc>; - sdio_mmc: __overlay__ { -- compatible = "brcm,bcm2835-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - non-removable; + ++struct drm_vc4_get_hang_state_bo { ++ uint32_t handle; ++ uint32_t paddr; ++ uint32_t size; ++ uint32_t pad; ++}; ++ ++/** ++ * struct drm_vc4_hang_state - ioctl argument for collecting state ++ * from a GPU hang for analysis. ++*/ ++struct drm_vc4_get_hang_state { ++ /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ ++ uint64_t bo; ++ /** ++ * On input, the size of the bo array. Output is the number ++ * of bos to be returned. ++ */ ++ uint32_t bo_count; ++ ++ uint32_t start_bin, start_render; ++ ++ uint32_t ct0ca, ct0ea; ++ uint32_t ct1ca, ct1ea; ++ uint32_t ct0cs, ct1cs; ++ uint32_t ct0ra0, ct1ra0; ++ ++ uint32_t bpca, bpcs; ++ uint32_t bpoa, bpos; ++ ++ uint32_t vpmbase; ++ ++ uint32_t dbge; ++ uint32_t fdbgo; ++ uint32_t fdbgb; ++ uint32_t fdbgr; ++ uint32_t fdbgs; ++ uint32_t errstat; ++ ++ /* Pad that we may save more registers into in the future. */ ++ uint32_t pad[16]; ++}; ++ + #endif /* _UAPI_VC4_DRM_H_ */ -- 2.5.0 -From aec321ec39ccb0b2e86f0db2a9b0dd4598d2435d Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Wed, 9 Dec 2015 11:38:15 +0000 -Subject: [PATCH 77/78] bcm2835-sdhost: Don't log timeout errors unless debug=1 +From 5f726bd15729062dd4cf89c22d9f15d4c2979d3d Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 4 Dec 2015 11:35:34 -0800 +Subject: [PATCH 54/59] drm/vc4: Update a bunch of code to match upstream + submission. -The MMC card-discovery process generates timeouts. This is -expected behaviour, so reporting it to the user serves no purpose. -Suppress the reporting of timeout errors unless the debug flag -is on. +This gets almost everything matching, except for the MSAA support and +using generic PM domains. + +Signed-off-by: Eric Anholt --- - drivers/mmc/host/bcm2835-sdhost.c | 18 +++++++----------- - 1 file changed, 7 insertions(+), 11 deletions(-) + drivers/gpu/drm/drm_gem_cma_helper.c | 13 +- + drivers/gpu/drm/vc4/vc4_bo.c | 322 +++++++++++++++++------------ + drivers/gpu/drm/vc4/vc4_crtc.c | 7 +- + drivers/gpu/drm/vc4/vc4_drv.c | 6 +- + drivers/gpu/drm/vc4/vc4_drv.h | 20 +- + drivers/gpu/drm/vc4/vc4_gem.c | 24 ++- + drivers/gpu/drm/vc4/vc4_irq.c | 5 +- + drivers/gpu/drm/vc4/vc4_kms.c | 1 + + drivers/gpu/drm/vc4/vc4_packet.h | 210 +++++++++---------- + drivers/gpu/drm/vc4/vc4_qpu_defines.h | 308 ++++++++++++++------------- + drivers/gpu/drm/vc4/vc4_render_cl.c | 4 +- + drivers/gpu/drm/vc4/vc4_v3d.c | 10 +- + drivers/gpu/drm/vc4/vc4_validate.c | 130 ++++++------ + drivers/gpu/drm/vc4/vc4_validate_shaders.c | 66 +++--- + include/drm/drmP.h | 8 +- + 15 files changed, 598 insertions(+), 536 deletions(-) -diff --git a/drivers/mmc/host/bcm2835-sdhost.c b/drivers/mmc/host/bcm2835-sdhost.c -index 0623392..0136aef 100644 ---- a/drivers/mmc/host/bcm2835-sdhost.c -+++ b/drivers/mmc/host/bcm2835-sdhost.c -@@ -966,19 +966,15 @@ static void bcm2835_sdhost_finish_command(struct bcm2835_host *host) - mmc_hostname(host->mmc)); - } else { - if (sdhsts & SDHSTS_CMD_TIME_OUT) { -- switch (host->cmd->opcode) { -- case 5: case 52: case 53: -- /* Don't warn about SDIO commands */ -- break; -- default: -- pr_err("%s: command timeout\n", -- mmc_hostname(host->mmc)); -- break; -- } -+ if (host->debug) -+ pr_err("%s: command %d timeout\n", -+ mmc_hostname(host->mmc), -+ host->cmd->opcode); - host->cmd->error = -ETIMEDOUT; - } else { -- pr_err("%s: unexpected command error\n", -- mmc_hostname(host->mmc)); -+ pr_err("%s: unexpected command %d error\n", -+ mmc_hostname(host->mmc), -+ host->cmd->opcode); - bcm2835_sdhost_dumpregs(host); - host->cmd->error = -EIO; +diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c +index 1c25500..0f7b00b 100644 +--- a/drivers/gpu/drm/drm_gem_cma_helper.c ++++ b/drivers/gpu/drm/drm_gem_cma_helper.c +@@ -58,15 +58,14 @@ __drm_gem_cma_create(struct drm_device *drm, size_t size) + struct drm_gem_cma_object *cma_obj; + struct drm_gem_object *gem_obj; + int ret; +- size_t obj_size = (drm->driver->gem_obj_size ? +- drm->driver->gem_obj_size : +- sizeof(*cma_obj)); + +- cma_obj = kzalloc(obj_size, GFP_KERNEL); +- if (!cma_obj) ++ if (drm->driver->gem_create_object) ++ gem_obj = drm->driver->gem_create_object(drm, size); ++ else ++ gem_obj = kzalloc(sizeof(*cma_obj), GFP_KERNEL); ++ if (!gem_obj) + return ERR_PTR(-ENOMEM); +- +- gem_obj = &cma_obj->base; ++ cma_obj = container_of(gem_obj, struct drm_gem_cma_object, base); + + ret = drm_gem_object_init(drm, gem_obj, size); + if (ret) +diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c +index 58dcbae..6247ff8 100644 +--- a/drivers/gpu/drm/vc4/vc4_bo.c ++++ b/drivers/gpu/drm/vc4/vc4_bo.c +@@ -12,6 +12,10 @@ + * access to system memory with no MMU in between. To support it, we + * use the GEM CMA helper functions to allocate contiguous ranges of + * physical memory for our BOs. ++ * ++ * Since the CMA allocator is very slow, we keep a cache of recently ++ * freed BOs around so that the kernel's allocation of objects for 3D ++ * rendering can return quickly. + */ + + #include "vc4_drv.h" +@@ -34,6 +38,36 @@ static void vc4_bo_stats_dump(struct vc4_dev *vc4) + vc4->bo_stats.size_cached / 1024); + } + ++#ifdef CONFIG_DEBUG_FS ++int vc4_bo_stats_debugfs(struct seq_file *m, void *unused) ++{ ++ struct drm_info_node *node = (struct drm_info_node *)m->private; ++ struct drm_device *dev = node->minor->dev; ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ struct vc4_bo_stats stats; ++ ++ /* Take a snapshot of the current stats with the lock held. */ ++ mutex_lock(&vc4->bo_lock); ++ stats = vc4->bo_stats; ++ mutex_unlock(&vc4->bo_lock); ++ ++ seq_printf(m, "num bos allocated: %d\n", ++ stats.num_allocated); ++ seq_printf(m, "size bos allocated: %dkb\n", ++ stats.size_allocated / 1024); ++ seq_printf(m, "num bos used: %d\n", ++ stats.num_allocated - stats.num_cached); ++ seq_printf(m, "size bos used: %dkb\n", ++ (stats.size_allocated - stats.size_cached) / 1024); ++ seq_printf(m, "num bos cached: %d\n", ++ stats.num_cached); ++ seq_printf(m, "size bos cached: %dkb\n", ++ stats.size_cached / 1024); ++ ++ return 0; ++} ++#endif ++ + static uint32_t bo_page_index(size_t size) + { + return (size / PAGE_SIZE) - 1; +@@ -81,8 +115,8 @@ static struct list_head *vc4_get_cache_list_for_size(struct drm_device *dev, + struct list_head *new_list; + uint32_t i; + +- new_list = kmalloc(new_size * sizeof(struct list_head), +- GFP_KERNEL); ++ new_list = kmalloc_array(new_size, sizeof(struct list_head), ++ GFP_KERNEL); + if (!new_list) + return NULL; + +@@ -90,7 +124,9 @@ static struct list_head *vc4_get_cache_list_for_size(struct drm_device *dev, + * head locations. + */ + for (i = 0; i < vc4->bo_cache.size_list_size; i++) { +- struct list_head *old_list = &vc4->bo_cache.size_list[i]; ++ struct list_head *old_list = ++ &vc4->bo_cache.size_list[i]; ++ + if (list_empty(old_list)) + INIT_LIST_HEAD(&new_list[i]); + else +@@ -122,11 +158,60 @@ void vc4_bo_cache_purge(struct drm_device *dev) + mutex_unlock(&vc4->bo_lock); + } + +-struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size) ++static struct vc4_bo *vc4_bo_get_from_cache(struct drm_device *dev, ++ uint32_t size) + { + struct vc4_dev *vc4 = to_vc4_dev(dev); +- uint32_t size = roundup(unaligned_size, PAGE_SIZE); + uint32_t page_index = bo_page_index(size); ++ struct vc4_bo *bo = NULL; ++ ++ size = roundup(size, PAGE_SIZE); ++ ++ mutex_lock(&vc4->bo_lock); ++ if (page_index >= vc4->bo_cache.size_list_size) ++ goto out; ++ ++ if (list_empty(&vc4->bo_cache.size_list[page_index])) ++ goto out; ++ ++ bo = list_first_entry(&vc4->bo_cache.size_list[page_index], ++ struct vc4_bo, size_head); ++ vc4_bo_remove_from_cache(bo); ++ kref_init(&bo->base.base.refcount); ++ ++out: ++ mutex_unlock(&vc4->bo_lock); ++ return bo; ++} ++ ++/** ++ * vc4_gem_create_object - Implementation of driver->gem_create_object. ++ * ++ * This lets the CMA helpers allocate object structs for us, and keep ++ * our BO stats correct. ++ */ ++struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size) ++{ ++ struct vc4_dev *vc4 = to_vc4_dev(dev); ++ struct vc4_bo *bo; ++ ++ bo = kzalloc(sizeof(*bo), GFP_KERNEL); ++ if (!bo) ++ return ERR_PTR(-ENOMEM); ++ ++ mutex_lock(&vc4->bo_lock); ++ vc4->bo_stats.num_allocated++; ++ vc4->bo_stats.size_allocated += size; ++ mutex_unlock(&vc4->bo_lock); ++ ++ return &bo->base.base; ++} ++ ++struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size, ++ bool from_cache) ++{ ++ size_t size = roundup(unaligned_size, PAGE_SIZE); ++ struct vc4_dev *vc4 = to_vc4_dev(dev); + struct drm_gem_cma_object *cma_obj; + int pass; + +@@ -134,18 +219,12 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size) + return NULL; + + /* First, try to get a vc4_bo from the kernel BO cache. */ +- mutex_lock(&vc4->bo_lock); +- if (page_index < vc4->bo_cache.size_list_size && +- !list_empty(&vc4->bo_cache.size_list[page_index])) { +- struct vc4_bo *bo = +- list_first_entry(&vc4->bo_cache.size_list[page_index], +- struct vc4_bo, size_head); +- vc4_bo_remove_from_cache(bo); +- mutex_unlock(&vc4->bo_lock); +- kref_init(&bo->base.base.refcount); +- return bo; ++ if (from_cache) { ++ struct vc4_bo *bo = vc4_bo_get_from_cache(dev, size); ++ ++ if (bo) ++ return bo; + } +- mutex_unlock(&vc4->bo_lock); + + /* Otherwise, make a new BO. */ + for (pass = 0; ; pass++) { +@@ -179,9 +258,6 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size) + } + } + +- vc4->bo_stats.num_allocated++; +- vc4->bo_stats.size_allocated += size; +- + return to_vc4_bo(&cma_obj->base); + } + +@@ -199,7 +275,7 @@ int vc4_dumb_create(struct drm_file *file_priv, + if (args->size < args->pitch * args->height) + args->size = args->pitch * args->height; + +- bo = vc4_bo_create(dev, args->size); ++ bo = vc4_bo_create(dev, args->size, false); + if (!bo) + return -ENOMEM; + +@@ -209,8 +285,8 @@ int vc4_dumb_create(struct drm_file *file_priv, + return ret; + } + +-static void +-vc4_bo_cache_free_old(struct drm_device *dev) ++/* Must be called with bo_lock held. */ ++static void vc4_bo_cache_free_old(struct drm_device *dev) + { + struct vc4_dev *vc4 = to_vc4_dev(dev); + unsigned long expire_time = jiffies - msecs_to_jiffies(1000); +@@ -313,15 +389,77 @@ vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags) + return drm_gem_prime_export(dev, obj, flags); + } + +-int +-vc4_create_bo_ioctl(struct drm_device *dev, void *data, +- struct drm_file *file_priv) ++int vc4_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ struct drm_gem_object *gem_obj; ++ struct vc4_bo *bo; ++ int ret; ++ ++ ret = drm_gem_mmap(filp, vma); ++ if (ret) ++ return ret; ++ ++ gem_obj = vma->vm_private_data; ++ bo = to_vc4_bo(gem_obj); ++ ++ if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { ++ DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); ++ return -EINVAL; ++ } ++ ++ /* ++ * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the ++ * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map ++ * the whole buffer. ++ */ ++ vma->vm_flags &= ~VM_PFNMAP; ++ vma->vm_pgoff = 0; ++ ++ ret = dma_mmap_writecombine(bo->base.base.dev->dev, vma, ++ bo->base.vaddr, bo->base.paddr, ++ vma->vm_end - vma->vm_start); ++ if (ret) ++ drm_gem_vm_close(vma); ++ ++ return ret; ++} ++ ++int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) ++{ ++ struct vc4_bo *bo = to_vc4_bo(obj); ++ ++ if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { ++ DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); ++ return -EINVAL; ++ } ++ ++ return drm_gem_cma_prime_mmap(obj, vma); ++} ++ ++void *vc4_prime_vmap(struct drm_gem_object *obj) ++{ ++ struct vc4_bo *bo = to_vc4_bo(obj); ++ ++ if (bo->validated_shader) { ++ DRM_ERROR("mmaping of shader BOs not allowed.\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return drm_gem_cma_prime_vmap(obj); ++} ++ ++int vc4_create_bo_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) + { + struct drm_vc4_create_bo *args = data; + struct vc4_bo *bo = NULL; + int ret; + +- bo = vc4_bo_create(dev, args->size); ++ /* ++ * We can't allocate from the BO cache, because the BOs don't ++ * get zeroed, and that might leak data between users. ++ */ ++ bo = vc4_bo_create(dev, args->size, false); + if (!bo) + return -ENOMEM; + +@@ -331,6 +469,25 @@ vc4_create_bo_ioctl(struct drm_device *dev, void *data, + return ret; + } + ++int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv) ++{ ++ struct drm_vc4_mmap_bo *args = data; ++ struct drm_gem_object *gem_obj; ++ ++ gem_obj = drm_gem_object_lookup(dev, file_priv, args->handle); ++ if (!gem_obj) { ++ DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); ++ return -EINVAL; ++ } ++ ++ /* The mmap offset was set up at BO allocation time. */ ++ args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node); ++ ++ drm_gem_object_unreference_unlocked(gem_obj); ++ return 0; ++} ++ + int + vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +@@ -355,7 +512,7 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + return -EINVAL; + } + +- bo = vc4_bo_create(dev, args->size); ++ bo = vc4_bo_create(dev, args->size, true); + if (!bo) + return -ENOMEM; + +@@ -364,6 +521,11 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + args->size); + if (ret != 0) + goto fail; ++ /* Clear the rest of the memory from allocating from the BO ++ * cache. ++ */ ++ memset(bo->base.vaddr + args->size, 0, ++ bo->base.base.size - args->size); + + bo->validated_shader = vc4_validate_shader(&bo->base); + if (!bo->validated_shader) { +@@ -382,85 +544,6 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, + return ret; + } + +-int +-vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, +- struct drm_file *file_priv) +-{ +- struct drm_vc4_mmap_bo *args = data; +- struct drm_gem_object *gem_obj; +- +- gem_obj = drm_gem_object_lookup(dev, file_priv, args->handle); +- if (!gem_obj) { +- DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); +- return -EINVAL; +- } +- +- /* The mmap offset was set up at BO allocation time. */ +- args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node); +- +- drm_gem_object_unreference(gem_obj); +- return 0; +-} +- +-int vc4_mmap(struct file *filp, struct vm_area_struct *vma) +-{ +- struct drm_gem_object *gem_obj; +- struct vc4_bo *bo; +- int ret; +- +- ret = drm_gem_mmap(filp, vma); +- if (ret) +- return ret; +- +- gem_obj = vma->vm_private_data; +- bo = to_vc4_bo(gem_obj); +- +- if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { +- DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); +- return -EINVAL; +- } +- +- /* +- * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the +- * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map +- * the whole buffer. +- */ +- vma->vm_flags &= ~VM_PFNMAP; +- vma->vm_pgoff = 0; +- +- ret = dma_mmap_writecombine(bo->base.base.dev->dev, vma, +- bo->base.vaddr, bo->base.paddr, +- vma->vm_end - vma->vm_start); +- if (ret) +- drm_gem_vm_close(vma); +- +- return ret; +-} +- +-int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) +-{ +- struct vc4_bo *bo = to_vc4_bo(obj); +- +- if (bo->validated_shader) { +- DRM_ERROR("mmaping of shader BOs not allowed.\n"); +- return -EINVAL; +- } +- +- return drm_gem_cma_prime_mmap(obj, vma); +-} +- +-void *vc4_prime_vmap(struct drm_gem_object *obj) +-{ +- struct vc4_bo *bo = to_vc4_bo(obj); +- +- if (bo->validated_shader) { +- DRM_ERROR("mmaping of shader BOs not allowed.\n"); +- return ERR_PTR(-EINVAL); +- } +- +- return drm_gem_cma_prime_vmap(obj); +-} +- + void vc4_bo_cache_init(struct drm_device *dev) + { + struct vc4_dev *vc4 = to_vc4_dev(dev); +@@ -472,7 +555,7 @@ void vc4_bo_cache_init(struct drm_device *dev) + INIT_WORK(&vc4->bo_cache.time_work, vc4_bo_cache_time_work); + setup_timer(&vc4->bo_cache.time_timer, + vc4_bo_cache_time_timer, +- (unsigned long) dev); ++ (unsigned long)dev); + } + + void vc4_bo_cache_destroy(struct drm_device *dev) +@@ -489,28 +572,3 @@ void vc4_bo_cache_destroy(struct drm_device *dev) + vc4_bo_stats_dump(vc4); + } + } +- +-#ifdef CONFIG_DEBUG_FS +-int vc4_bo_stats_debugfs(struct seq_file *m, void *unused) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- struct vc4_dev *vc4 = to_vc4_dev(dev); +- struct vc4_bo_stats stats; +- +- mutex_lock(&vc4->bo_lock); +- stats = vc4->bo_stats; +- mutex_unlock(&vc4->bo_lock); +- +- seq_printf(m, "num bos allocated: %d\n", stats.num_allocated); +- seq_printf(m, "size bos allocated: %dkb\n", stats.size_allocated / 1024); +- seq_printf(m, "num bos used: %d\n", (stats.num_allocated - +- stats.num_cached)); +- seq_printf(m, "size bos used: %dkb\n", (stats.size_allocated - +- stats.size_cached) / 1024); +- seq_printf(m, "num bos cached: %d\n", stats.num_cached); +- seq_printf(m, "size bos cached: %dkb\n", stats.size_cached / 1024); +- +- return 0; +-} +-#endif +diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c +index 3be2720..3c67914 100644 +--- a/drivers/gpu/drm/vc4/vc4_crtc.c ++++ b/drivers/gpu/drm/vc4/vc4_crtc.c +@@ -501,6 +501,7 @@ vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) + vc4_plane_async_set_fb(plane, flip_state->fb); + if (flip_state->event) { + unsigned long flags; ++ + spin_lock_irqsave(&dev->event_lock, flags); + drm_crtc_send_vblank_event(crtc, flip_state->event); + spin_unlock_irqrestore(&dev->event_lock, flags); +@@ -562,9 +563,9 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, + } + + static int vc4_page_flip(struct drm_crtc *crtc, +- struct drm_framebuffer *fb, +- struct drm_pending_vblank_event *event, +- uint32_t flags) ++ struct drm_framebuffer *fb, ++ struct drm_pending_vblank_event *event, ++ uint32_t flags) + { + if (flags & DRM_MODE_PAGE_FLIP_ASYNC) + return vc4_async_page_flip(crtc, fb, event, flags); +diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c +index e8192b4..22061ae 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.c ++++ b/drivers/gpu/drm/vc4/vc4_drv.c +@@ -81,7 +81,8 @@ static const struct drm_ioctl_desc vc4_drm_ioctls[] = { + DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0), + DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0), +- DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_ROOT_ONLY), ++ DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, ++ DRM_ROOT_ONLY), + }; + + static struct drm_driver vc4_drm_driver = { +@@ -107,6 +108,7 @@ static struct drm_driver vc4_drm_driver = { + .debugfs_cleanup = vc4_debugfs_cleanup, + #endif + ++ .gem_create_object = vc4_create_object, + .gem_free_object = vc4_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + +@@ -128,8 +130,6 @@ static struct drm_driver vc4_drm_driver = { + .num_ioctls = ARRAY_SIZE(vc4_drm_ioctls), + .fops = &vc4_drm_fops, + +- //.gem_obj_size = sizeof(struct vc4_bo), +- + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, +diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h +index 24845c1..53dfa8d 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.h ++++ b/drivers/gpu/drm/vc4/vc4_drv.h +@@ -72,6 +72,9 @@ struct vc4_dev { + * job_done_work. + */ + struct list_head job_done_list; ++ /* Spinlock used to synchronize the job_list and seqno ++ * accesses between the IRQ handler and GEM ioctls. ++ */ + spinlock_t job_lock; + wait_queue_head_t job_wait_queue; + struct work_struct job_done_work; +@@ -318,8 +321,7 @@ struct vc4_texture_sample_info { + * and validate the shader state record's uniforms that define the texture + * samples. + */ +-struct vc4_validated_shader_info +-{ ++struct vc4_validated_shader_info { + uint32_t uniforms_size; + uint32_t uniforms_src_size; + uint32_t num_texture_samples; +@@ -355,8 +357,10 @@ struct vc4_validated_shader_info + #define wait_for(COND, MS) _wait_for(COND, MS, 1) + + /* vc4_bo.c */ ++struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); + void vc4_free_object(struct drm_gem_object *gem_obj); +-struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size); ++struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, ++ bool from_cache); + int vc4_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args); +@@ -432,7 +436,8 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev, + enum drm_plane_type type); + u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); + u32 vc4_plane_dlist_size(struct drm_plane_state *state); +-void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb); ++void vc4_plane_async_set_fb(struct drm_plane *plane, ++ struct drm_framebuffer *fb); + + /* vc4_v3d.c */ + extern struct platform_driver vc4_v3d_driver; +@@ -450,9 +455,6 @@ vc4_validate_bin_cl(struct drm_device *dev, + int + vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); + +-struct vc4_validated_shader_info * +-vc4_validate_shader(struct drm_gem_cma_object *shader_obj); +- + bool vc4_use_bo(struct vc4_exec_info *exec, + uint32_t hindex, + enum vc4_bo_mode mode, +@@ -464,3 +466,7 @@ bool vc4_check_tex_size(struct vc4_exec_info *exec, + struct drm_gem_cma_object *fbo, + uint32_t offset, uint8_t tiling_format, + uint32_t width, uint32_t height, uint8_t cpp); ++ ++/* vc4_validate_shader.c */ ++struct vc4_validated_shader_info * ++vc4_validate_shader(struct drm_gem_cma_object *shader_obj); +diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c +index d90c664..fb0b92d 100644 +--- a/drivers/gpu/drm/vc4/vc4_gem.c ++++ b/drivers/gpu/drm/vc4/vc4_gem.c +@@ -53,9 +53,8 @@ vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state) + unsigned int i; + + mutex_lock(&dev->struct_mutex); +- for (i = 0; i < state->user_state.bo_count; i++) { ++ for (i = 0; i < state->user_state.bo_count; i++) + drm_gem_object_unreference(state->bo[i]); +- } + mutex_unlock(&dev->struct_mutex); + + kfree(state); +@@ -65,10 +64,10 @@ int + vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) + { +- struct drm_vc4_get_hang_state *get_state = data; ++ struct drm_vc4_get_hang_state *get_state = data; + struct drm_vc4_get_hang_state_bo *bo_state; + struct vc4_hang_state *kernel_state; +- struct drm_vc4_get_hang_state *state; ++ struct drm_vc4_get_hang_state *state; + struct vc4_dev *vc4 = to_vc4_dev(dev); + unsigned long irqflags; + u32 i; +@@ -107,6 +106,7 @@ vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, + for (i = 0; i < state->bo_count; i++) { + struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]); + u32 handle; ++ + ret = drm_gem_handle_create(file_priv, kernel_state->bo[i], + &handle); + +@@ -124,7 +124,7 @@ vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, + state->bo_count * sizeof(*bo_state)); + kfree(bo_state); + +- err_free: ++err_free: + + vc4_free_hang_state(dev, kernel_state); + +@@ -578,7 +578,7 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) + goto fail; + } + +- bo = vc4_bo_create(dev, exec_size); ++ bo = vc4_bo_create(dev, exec_size, true); + if (!bo) { + DRM_ERROR("Couldn't allocate BO for binning\n"); + ret = PTR_ERR(exec->exec_bo); +@@ -668,6 +668,7 @@ vc4_job_handle_completed(struct vc4_dev *vc4) + static void vc4_seqno_cb_work(struct work_struct *work) + { + struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work); ++ + cb->func(cb); + } + +@@ -717,6 +718,7 @@ vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev, + + if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) { + uint64_t delta = jiffies_to_nsecs(jiffies - start); ++ + if (*timeout_ns >= delta) + *timeout_ns -= delta; + } +@@ -750,9 +752,10 @@ vc4_wait_bo_ioctl(struct drm_device *dev, void *data, + } + bo = to_vc4_bo(gem_obj); + +- ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, &args->timeout_ns); ++ ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, ++ &args->timeout_ns); + +- drm_gem_object_unreference(gem_obj); ++ drm_gem_object_unreference_unlocked(gem_obj); + return ret; + } + +@@ -793,7 +796,8 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data, + if (ret) + goto fail; + } else { +- exec->ct0ca = exec->ct0ea = 0; ++ exec->ct0ca = 0; ++ exec->ct0ea = 0; + } + + ret = vc4_get_rcl(dev, exec); +@@ -831,7 +835,7 @@ vc4_gem_init(struct drm_device *dev) + INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work); + setup_timer(&vc4->hangcheck.timer, + vc4_hangcheck_elapsed, +- (unsigned long) dev); ++ (unsigned long)dev); + + INIT_WORK(&vc4->job_done_work, vc4_job_done_work); + } +diff --git a/drivers/gpu/drm/vc4/vc4_irq.c b/drivers/gpu/drm/vc4/vc4_irq.c +index f29b796..b68060e 100644 +--- a/drivers/gpu/drm/vc4/vc4_irq.c ++++ b/drivers/gpu/drm/vc4/vc4_irq.c +@@ -56,7 +56,7 @@ vc4_overflow_mem_work(struct work_struct *work) + struct drm_device *dev = vc4->dev; + struct vc4_bo *bo; + +- bo = vc4_bo_create(dev, 256 * 1024); ++ bo = vc4_bo_create(dev, 256 * 1024, true); + if (!bo) { + DRM_ERROR("Couldn't allocate binner overflow mem\n"); + return; +@@ -87,9 +87,8 @@ vc4_overflow_mem_work(struct work_struct *work) + spin_unlock_irqrestore(&vc4->job_lock, irqflags); + } + +- if (vc4->overflow_mem) { ++ if (vc4->overflow_mem) + drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base); +- } + vc4->overflow_mem = bo; + + V3D_WRITE(V3D_BPOA, bo->base.paddr); +diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c +index 2082713..f95f2df 100644 +--- a/drivers/gpu/drm/vc4/vc4_kms.c ++++ b/drivers/gpu/drm/vc4/vc4_kms.c +@@ -132,6 +132,7 @@ static int vc4_atomic_commit(struct drm_device *dev, + struct drm_gem_cma_object *cma_bo = + drm_fb_cma_get_gem_obj(new_state->fb, 0); + struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); ++ + wait_seqno = max(bo->seqno, wait_seqno); + } + } +diff --git a/drivers/gpu/drm/vc4/vc4_packet.h b/drivers/gpu/drm/vc4/vc4_packet.h +index 9757bc8..cee38aa 100644 +--- a/drivers/gpu/drm/vc4/vc4_packet.h ++++ b/drivers/gpu/drm/vc4/vc4_packet.h +@@ -27,60 +27,60 @@ + #include "vc4_regs.h" /* for VC4_MASK, VC4_GET_FIELD, VC4_SET_FIELD */ + + enum vc4_packet { +- VC4_PACKET_HALT = 0, +- VC4_PACKET_NOP = 1, +- +- VC4_PACKET_FLUSH = 4, +- VC4_PACKET_FLUSH_ALL = 5, +- VC4_PACKET_START_TILE_BINNING = 6, +- VC4_PACKET_INCREMENT_SEMAPHORE = 7, +- VC4_PACKET_WAIT_ON_SEMAPHORE = 8, +- +- VC4_PACKET_BRANCH = 16, +- VC4_PACKET_BRANCH_TO_SUB_LIST = 17, +- +- VC4_PACKET_STORE_MS_TILE_BUFFER = 24, +- VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, +- VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, +- VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, +- VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, +- VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, +- +- VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, +- VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, +- +- VC4_PACKET_COMPRESSED_PRIMITIVE = 48, +- VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, +- +- VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, +- +- VC4_PACKET_GL_SHADER_STATE = 64, +- VC4_PACKET_NV_SHADER_STATE = 65, +- VC4_PACKET_VG_SHADER_STATE = 66, +- +- VC4_PACKET_CONFIGURATION_BITS = 96, +- VC4_PACKET_FLAT_SHADE_FLAGS = 97, +- VC4_PACKET_POINT_SIZE = 98, +- VC4_PACKET_LINE_WIDTH = 99, +- VC4_PACKET_RHT_X_BOUNDARY = 100, +- VC4_PACKET_DEPTH_OFFSET = 101, +- VC4_PACKET_CLIP_WINDOW = 102, +- VC4_PACKET_VIEWPORT_OFFSET = 103, +- VC4_PACKET_Z_CLIPPING = 104, +- VC4_PACKET_CLIPPER_XY_SCALING = 105, +- VC4_PACKET_CLIPPER_Z_SCALING = 106, +- +- VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, +- VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, +- VC4_PACKET_CLEAR_COLORS = 114, +- VC4_PACKET_TILE_COORDINATES = 115, +- +- /* Not an actual hardware packet -- this is what we use to put +- * references to GEM bos in the command stream, since we need the u32 +- * int the actual address packet in order to store the offset from the +- * start of the BO. +- */ +- VC4_PACKET_GEM_HANDLES = 254, ++ VC4_PACKET_HALT = 0, ++ VC4_PACKET_NOP = 1, ++ ++ VC4_PACKET_FLUSH = 4, ++ VC4_PACKET_FLUSH_ALL = 5, ++ VC4_PACKET_START_TILE_BINNING = 6, ++ VC4_PACKET_INCREMENT_SEMAPHORE = 7, ++ VC4_PACKET_WAIT_ON_SEMAPHORE = 8, ++ ++ VC4_PACKET_BRANCH = 16, ++ VC4_PACKET_BRANCH_TO_SUB_LIST = 17, ++ ++ VC4_PACKET_STORE_MS_TILE_BUFFER = 24, ++ VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, ++ VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, ++ VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, ++ VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, ++ VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, ++ ++ VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, ++ VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, ++ ++ VC4_PACKET_COMPRESSED_PRIMITIVE = 48, ++ VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, ++ ++ VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, ++ ++ VC4_PACKET_GL_SHADER_STATE = 64, ++ VC4_PACKET_NV_SHADER_STATE = 65, ++ VC4_PACKET_VG_SHADER_STATE = 66, ++ ++ VC4_PACKET_CONFIGURATION_BITS = 96, ++ VC4_PACKET_FLAT_SHADE_FLAGS = 97, ++ VC4_PACKET_POINT_SIZE = 98, ++ VC4_PACKET_LINE_WIDTH = 99, ++ VC4_PACKET_RHT_X_BOUNDARY = 100, ++ VC4_PACKET_DEPTH_OFFSET = 101, ++ VC4_PACKET_CLIP_WINDOW = 102, ++ VC4_PACKET_VIEWPORT_OFFSET = 103, ++ VC4_PACKET_Z_CLIPPING = 104, ++ VC4_PACKET_CLIPPER_XY_SCALING = 105, ++ VC4_PACKET_CLIPPER_Z_SCALING = 106, ++ ++ VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, ++ VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, ++ VC4_PACKET_CLEAR_COLORS = 114, ++ VC4_PACKET_TILE_COORDINATES = 115, ++ ++ /* Not an actual hardware packet -- this is what we use to put ++ * references to GEM bos in the command stream, since we need the u32 ++ * int the actual address packet in order to store the offset from the ++ * start of the BO. ++ */ ++ VC4_PACKET_GEM_HANDLES = 254, + } __attribute__ ((__packed__)); + + #define VC4_PACKET_HALT_SIZE 1 +@@ -148,10 +148,10 @@ enum vc4_packet { + * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) + */ + +-#define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3) +-#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2) +-#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1) +-#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0) ++#define VC4_LOADSTORE_TILE_BUFFER_EOF BIT(3) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK BIT(2) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS BIT(1) ++#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR BIT(0) + + /** @} */ + +@@ -160,10 +160,10 @@ enum vc4_packet { + * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL + */ +-#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15) +-#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14) +-#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13) +-#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12) ++#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR BIT(15) ++#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR BIT(14) ++#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR BIT(13) ++#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP BIT(12) + + #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) + #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 +@@ -201,28 +201,28 @@ enum vc4_packet { + #define VC4_INDEX_BUFFER_U16 (1 << 4) + + /* This flag is only present in NV shader state. */ +-#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3) +-#define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2) +-#define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1) +-#define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0) ++#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS BIT(3) ++#define VC4_SHADER_FLAG_ENABLE_CLIPPING BIT(2) ++#define VC4_SHADER_FLAG_VS_POINT_SIZE BIT(1) ++#define VC4_SHADER_FLAG_FS_SINGLE_THREAD BIT(0) + + /** @{ byte 2 of config bits. */ +-#define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1) +-#define VC4_CONFIG_BITS_EARLY_Z (1 << 0) ++#define VC4_CONFIG_BITS_EARLY_Z_UPDATE BIT(1) ++#define VC4_CONFIG_BITS_EARLY_Z BIT(0) + /** @} */ + + /** @{ byte 1 of config bits. */ +-#define VC4_CONFIG_BITS_Z_UPDATE (1 << 7) ++#define VC4_CONFIG_BITS_Z_UPDATE BIT(7) + /** same values in this 3-bit field as PIPE_FUNC_* */ + #define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 +-#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3) ++#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE BIT(3) + + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) + #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) + +-#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0) ++#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT BIT(0) + /** @} */ + + /** @{ byte 0 of config bits. */ +@@ -230,15 +230,15 @@ enum vc4_packet { + #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) + #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) + +-#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4) +-#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3) +-#define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2) +-#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1) +-#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0) ++#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES BIT(4) ++#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET BIT(3) ++#define VC4_CONFIG_BITS_CW_PRIMITIVES BIT(2) ++#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK BIT(1) ++#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT BIT(0) + /** @} */ + + /** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ +-#define VC4_BIN_CONFIG_DB_NON_MS (1 << 7) ++#define VC4_BIN_CONFIG_DB_NON_MS BIT(7) + + #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) + #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 +@@ -254,17 +254,17 @@ enum vc4_packet { + #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 + #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 + +-#define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2) +-#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1) +-#define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0) ++#define VC4_BIN_CONFIG_AUTO_INIT_TSDA BIT(2) ++#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT BIT(1) ++#define VC4_BIN_CONFIG_MS_MODE_4X BIT(0) + /** @} */ + + /** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ +-#define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12) +-#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11) +-#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10) +-#define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9) +-#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8) ++#define VC4_RENDER_CONFIG_DB_NON_MS BIT(12) ++#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE BIT(11) ++#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G BIT(10) ++#define VC4_RENDER_CONFIG_COVERAGE_MODE BIT(9) ++#define VC4_RENDER_CONFIG_ENABLE_VG_MASK BIT(8) + + /** The values of the field are VC4_TILING_FORMAT_* */ + #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) +@@ -280,8 +280,8 @@ enum vc4_packet { + #define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 + #define VC4_RENDER_CONFIG_FORMAT_BGR565 2 + +-#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1) +-#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0) ++#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT BIT(1) ++#define VC4_RENDER_CONFIG_MS_MODE_4X BIT(0) + + #define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) + #define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) +@@ -291,24 +291,24 @@ enum vc4_packet { + #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) + + enum vc4_texture_data_type { +- VC4_TEXTURE_TYPE_RGBA8888 = 0, +- VC4_TEXTURE_TYPE_RGBX8888 = 1, +- VC4_TEXTURE_TYPE_RGBA4444 = 2, +- VC4_TEXTURE_TYPE_RGBA5551 = 3, +- VC4_TEXTURE_TYPE_RGB565 = 4, +- VC4_TEXTURE_TYPE_LUMINANCE = 5, +- VC4_TEXTURE_TYPE_ALPHA = 6, +- VC4_TEXTURE_TYPE_LUMALPHA = 7, +- VC4_TEXTURE_TYPE_ETC1 = 8, +- VC4_TEXTURE_TYPE_S16F = 9, +- VC4_TEXTURE_TYPE_S8 = 10, +- VC4_TEXTURE_TYPE_S16 = 11, +- VC4_TEXTURE_TYPE_BW1 = 12, +- VC4_TEXTURE_TYPE_A4 = 13, +- VC4_TEXTURE_TYPE_A1 = 14, +- VC4_TEXTURE_TYPE_RGBA64 = 15, +- VC4_TEXTURE_TYPE_RGBA32R = 16, +- VC4_TEXTURE_TYPE_YUV422R = 17, ++ VC4_TEXTURE_TYPE_RGBA8888 = 0, ++ VC4_TEXTURE_TYPE_RGBX8888 = 1, ++ VC4_TEXTURE_TYPE_RGBA4444 = 2, ++ VC4_TEXTURE_TYPE_RGBA5551 = 3, ++ VC4_TEXTURE_TYPE_RGB565 = 4, ++ VC4_TEXTURE_TYPE_LUMINANCE = 5, ++ VC4_TEXTURE_TYPE_ALPHA = 6, ++ VC4_TEXTURE_TYPE_LUMALPHA = 7, ++ VC4_TEXTURE_TYPE_ETC1 = 8, ++ VC4_TEXTURE_TYPE_S16F = 9, ++ VC4_TEXTURE_TYPE_S8 = 10, ++ VC4_TEXTURE_TYPE_S16 = 11, ++ VC4_TEXTURE_TYPE_BW1 = 12, ++ VC4_TEXTURE_TYPE_A4 = 13, ++ VC4_TEXTURE_TYPE_A1 = 14, ++ VC4_TEXTURE_TYPE_RGBA64 = 15, ++ VC4_TEXTURE_TYPE_RGBA32R = 16, ++ VC4_TEXTURE_TYPE_YUV422R = 17, + }; + + #define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) +diff --git a/drivers/gpu/drm/vc4/vc4_qpu_defines.h b/drivers/gpu/drm/vc4/vc4_qpu_defines.h +index e47c994..d5c2f3c 100644 +--- a/drivers/gpu/drm/vc4/vc4_qpu_defines.h ++++ b/drivers/gpu/drm/vc4/vc4_qpu_defines.h +@@ -25,194 +25,190 @@ + #define VC4_QPU_DEFINES_H + + enum qpu_op_add { +- QPU_A_NOP, +- QPU_A_FADD, +- QPU_A_FSUB, +- QPU_A_FMIN, +- QPU_A_FMAX, +- QPU_A_FMINABS, +- QPU_A_FMAXABS, +- QPU_A_FTOI, +- QPU_A_ITOF, +- QPU_A_ADD = 12, +- QPU_A_SUB, +- QPU_A_SHR, +- QPU_A_ASR, +- QPU_A_ROR, +- QPU_A_SHL, +- QPU_A_MIN, +- QPU_A_MAX, +- QPU_A_AND, +- QPU_A_OR, +- QPU_A_XOR, +- QPU_A_NOT, +- QPU_A_CLZ, +- QPU_A_V8ADDS = 30, +- QPU_A_V8SUBS = 31, ++ QPU_A_NOP, ++ QPU_A_FADD, ++ QPU_A_FSUB, ++ QPU_A_FMIN, ++ QPU_A_FMAX, ++ QPU_A_FMINABS, ++ QPU_A_FMAXABS, ++ QPU_A_FTOI, ++ QPU_A_ITOF, ++ QPU_A_ADD = 12, ++ QPU_A_SUB, ++ QPU_A_SHR, ++ QPU_A_ASR, ++ QPU_A_ROR, ++ QPU_A_SHL, ++ QPU_A_MIN, ++ QPU_A_MAX, ++ QPU_A_AND, ++ QPU_A_OR, ++ QPU_A_XOR, ++ QPU_A_NOT, ++ QPU_A_CLZ, ++ QPU_A_V8ADDS = 30, ++ QPU_A_V8SUBS = 31, + }; + + enum qpu_op_mul { +- QPU_M_NOP, +- QPU_M_FMUL, +- QPU_M_MUL24, +- QPU_M_V8MULD, +- QPU_M_V8MIN, +- QPU_M_V8MAX, +- QPU_M_V8ADDS, +- QPU_M_V8SUBS, ++ QPU_M_NOP, ++ QPU_M_FMUL, ++ QPU_M_MUL24, ++ QPU_M_V8MULD, ++ QPU_M_V8MIN, ++ QPU_M_V8MAX, ++ QPU_M_V8ADDS, ++ QPU_M_V8SUBS, + }; + + enum qpu_raddr { +- QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ +- /* 0-31 are the plain regfile a or b fields */ +- QPU_R_UNIF = 32, +- QPU_R_VARY = 35, +- QPU_R_ELEM_QPU = 38, +- QPU_R_NOP, +- QPU_R_XY_PIXEL_COORD = 41, +- QPU_R_MS_REV_FLAGS = 41, +- QPU_R_VPM = 48, +- QPU_R_VPM_LD_BUSY, +- QPU_R_VPM_LD_WAIT, +- QPU_R_MUTEX_ACQUIRE, ++ QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ ++ /* 0-31 are the plain regfile a or b fields */ ++ QPU_R_UNIF = 32, ++ QPU_R_VARY = 35, ++ QPU_R_ELEM_QPU = 38, ++ QPU_R_NOP, ++ QPU_R_XY_PIXEL_COORD = 41, ++ QPU_R_MS_REV_FLAGS = 41, ++ QPU_R_VPM = 48, ++ QPU_R_VPM_LD_BUSY, ++ QPU_R_VPM_LD_WAIT, ++ QPU_R_MUTEX_ACQUIRE, + }; + + enum qpu_waddr { +- /* 0-31 are the plain regfile a or b fields */ +- QPU_W_ACC0 = 32, /* aka r0 */ +- QPU_W_ACC1, +- QPU_W_ACC2, +- QPU_W_ACC3, +- QPU_W_TMU_NOSWAP, +- QPU_W_ACC5, +- QPU_W_HOST_INT, +- QPU_W_NOP, +- QPU_W_UNIFORMS_ADDRESS, +- QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ +- QPU_W_MS_FLAGS = 42, +- QPU_W_REV_FLAG = 42, +- QPU_W_TLB_STENCIL_SETUP = 43, +- QPU_W_TLB_Z, +- QPU_W_TLB_COLOR_MS, +- QPU_W_TLB_COLOR_ALL, +- QPU_W_TLB_ALPHA_MASK, +- QPU_W_VPM, +- QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ +- QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ +- QPU_W_MUTEX_RELEASE, +- QPU_W_SFU_RECIP, +- QPU_W_SFU_RECIPSQRT, +- QPU_W_SFU_EXP, +- QPU_W_SFU_LOG, +- QPU_W_TMU0_S, +- QPU_W_TMU0_T, +- QPU_W_TMU0_R, +- QPU_W_TMU0_B, +- QPU_W_TMU1_S, +- QPU_W_TMU1_T, +- QPU_W_TMU1_R, +- QPU_W_TMU1_B, ++ /* 0-31 are the plain regfile a or b fields */ ++ QPU_W_ACC0 = 32, /* aka r0 */ ++ QPU_W_ACC1, ++ QPU_W_ACC2, ++ QPU_W_ACC3, ++ QPU_W_TMU_NOSWAP, ++ QPU_W_ACC5, ++ QPU_W_HOST_INT, ++ QPU_W_NOP, ++ QPU_W_UNIFORMS_ADDRESS, ++ QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ ++ QPU_W_MS_FLAGS = 42, ++ QPU_W_REV_FLAG = 42, ++ QPU_W_TLB_STENCIL_SETUP = 43, ++ QPU_W_TLB_Z, ++ QPU_W_TLB_COLOR_MS, ++ QPU_W_TLB_COLOR_ALL, ++ QPU_W_TLB_ALPHA_MASK, ++ QPU_W_VPM, ++ QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ ++ QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ ++ QPU_W_MUTEX_RELEASE, ++ QPU_W_SFU_RECIP, ++ QPU_W_SFU_RECIPSQRT, ++ QPU_W_SFU_EXP, ++ QPU_W_SFU_LOG, ++ QPU_W_TMU0_S, ++ QPU_W_TMU0_T, ++ QPU_W_TMU0_R, ++ QPU_W_TMU0_B, ++ QPU_W_TMU1_S, ++ QPU_W_TMU1_T, ++ QPU_W_TMU1_R, ++ QPU_W_TMU1_B, + }; + + enum qpu_sig_bits { +- QPU_SIG_SW_BREAKPOINT, +- QPU_SIG_NONE, +- QPU_SIG_THREAD_SWITCH, +- QPU_SIG_PROG_END, +- QPU_SIG_WAIT_FOR_SCOREBOARD, +- QPU_SIG_SCOREBOARD_UNLOCK, +- QPU_SIG_LAST_THREAD_SWITCH, +- QPU_SIG_COVERAGE_LOAD, +- QPU_SIG_COLOR_LOAD, +- QPU_SIG_COLOR_LOAD_END, +- QPU_SIG_LOAD_TMU0, +- QPU_SIG_LOAD_TMU1, +- QPU_SIG_ALPHA_MASK_LOAD, +- QPU_SIG_SMALL_IMM, +- QPU_SIG_LOAD_IMM, +- QPU_SIG_BRANCH ++ QPU_SIG_SW_BREAKPOINT, ++ QPU_SIG_NONE, ++ QPU_SIG_THREAD_SWITCH, ++ QPU_SIG_PROG_END, ++ QPU_SIG_WAIT_FOR_SCOREBOARD, ++ QPU_SIG_SCOREBOARD_UNLOCK, ++ QPU_SIG_LAST_THREAD_SWITCH, ++ QPU_SIG_COVERAGE_LOAD, ++ QPU_SIG_COLOR_LOAD, ++ QPU_SIG_COLOR_LOAD_END, ++ QPU_SIG_LOAD_TMU0, ++ QPU_SIG_LOAD_TMU1, ++ QPU_SIG_ALPHA_MASK_LOAD, ++ QPU_SIG_SMALL_IMM, ++ QPU_SIG_LOAD_IMM, ++ QPU_SIG_BRANCH + }; + + enum qpu_mux { +- /* hardware mux values */ +- QPU_MUX_R0, +- QPU_MUX_R1, +- QPU_MUX_R2, +- QPU_MUX_R3, +- QPU_MUX_R4, +- QPU_MUX_R5, +- QPU_MUX_A, +- QPU_MUX_B, ++ /* hardware mux values */ ++ QPU_MUX_R0, ++ QPU_MUX_R1, ++ QPU_MUX_R2, ++ QPU_MUX_R3, ++ QPU_MUX_R4, ++ QPU_MUX_R5, ++ QPU_MUX_A, ++ QPU_MUX_B, + +- /* non-hardware mux values */ +- QPU_MUX_IMM, ++ /* non-hardware mux values */ ++ QPU_MUX_IMM, + }; + + enum qpu_cond { +- QPU_COND_NEVER, +- QPU_COND_ALWAYS, +- QPU_COND_ZS, +- QPU_COND_ZC, +- QPU_COND_NS, +- QPU_COND_NC, +- QPU_COND_CS, +- QPU_COND_CC, ++ QPU_COND_NEVER, ++ QPU_COND_ALWAYS, ++ QPU_COND_ZS, ++ QPU_COND_ZC, ++ QPU_COND_NS, ++ QPU_COND_NC, ++ QPU_COND_CS, ++ QPU_COND_CC, + }; + + enum qpu_pack_mul { +- QPU_PACK_MUL_NOP, +- QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */ +- QPU_PACK_MUL_8A, +- QPU_PACK_MUL_8B, +- QPU_PACK_MUL_8C, +- QPU_PACK_MUL_8D, ++ QPU_PACK_MUL_NOP, ++ /* replicated to each 8 bits of the 32-bit dst. */ ++ QPU_PACK_MUL_8888 = 3, ++ QPU_PACK_MUL_8A, ++ QPU_PACK_MUL_8B, ++ QPU_PACK_MUL_8C, ++ QPU_PACK_MUL_8D, + }; + + enum qpu_pack_a { +- QPU_PACK_A_NOP, +- /* convert to 16 bit float if float input, or to int16. */ +- QPU_PACK_A_16A, +- QPU_PACK_A_16B, +- /* replicated to each 8 bits of the 32-bit dst. */ +- QPU_PACK_A_8888, +- /* Convert to 8-bit unsigned int. */ +- QPU_PACK_A_8A, +- QPU_PACK_A_8B, +- QPU_PACK_A_8C, +- QPU_PACK_A_8D, ++ QPU_PACK_A_NOP, ++ /* convert to 16 bit float if float input, or to int16. */ ++ QPU_PACK_A_16A, ++ QPU_PACK_A_16B, ++ /* replicated to each 8 bits of the 32-bit dst. */ ++ QPU_PACK_A_8888, ++ /* Convert to 8-bit unsigned int. */ ++ QPU_PACK_A_8A, ++ QPU_PACK_A_8B, ++ QPU_PACK_A_8C, ++ QPU_PACK_A_8D, + +- /* Saturating variants of the previous instructions. */ +- QPU_PACK_A_32_SAT, /* int-only */ +- QPU_PACK_A_16A_SAT, /* int or float */ +- QPU_PACK_A_16B_SAT, +- QPU_PACK_A_8888_SAT, +- QPU_PACK_A_8A_SAT, +- QPU_PACK_A_8B_SAT, +- QPU_PACK_A_8C_SAT, +- QPU_PACK_A_8D_SAT, ++ /* Saturating variants of the previous instructions. */ ++ QPU_PACK_A_32_SAT, /* int-only */ ++ QPU_PACK_A_16A_SAT, /* int or float */ ++ QPU_PACK_A_16B_SAT, ++ QPU_PACK_A_8888_SAT, ++ QPU_PACK_A_8A_SAT, ++ QPU_PACK_A_8B_SAT, ++ QPU_PACK_A_8C_SAT, ++ QPU_PACK_A_8D_SAT, + }; + + enum qpu_unpack_r4 { +- QPU_UNPACK_R4_NOP, +- QPU_UNPACK_R4_F16A_TO_F32, +- QPU_UNPACK_R4_F16B_TO_F32, +- QPU_UNPACK_R4_8D_REP, +- QPU_UNPACK_R4_8A, +- QPU_UNPACK_R4_8B, +- QPU_UNPACK_R4_8C, +- QPU_UNPACK_R4_8D, ++ QPU_UNPACK_R4_NOP, ++ QPU_UNPACK_R4_F16A_TO_F32, ++ QPU_UNPACK_R4_F16B_TO_F32, ++ QPU_UNPACK_R4_8D_REP, ++ QPU_UNPACK_R4_8A, ++ QPU_UNPACK_R4_8B, ++ QPU_UNPACK_R4_8C, ++ QPU_UNPACK_R4_8D, + }; + +-#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) +-/* Using the GNU statement expression extension */ +-#define QPU_SET_FIELD(value, field) \ +- ({ \ +- uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ +- assert((fieldval & ~ field ## _MASK) == 0); \ +- fieldval & field ## _MASK; \ +- }) ++#define QPU_MASK(high, low) \ ++ ((((uint64_t)1 << ((high) - (low) + 1)) - 1) << (low)) + +-#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) ++#define QPU_GET_FIELD(word, field) \ ++ ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) + + #define QPU_SIG_SHIFT 60 + #define QPU_SIG_MASK QPU_MASK(63, 60) +diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c +index 0ffac8d..3516354 100644 +--- a/drivers/gpu/drm/vc4/vc4_render_cl.c ++++ b/drivers/gpu/drm/vc4/vc4_render_cl.c +@@ -63,7 +63,6 @@ static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val) + setup->next_offset += 4; + } + +- + /* + * Emits a no-op STORE_TILE_BUFFER_GENERAL. + * +@@ -217,7 +216,7 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + } + size += xtiles * ytiles * loop_body_size; + +- setup->rcl = &vc4_bo_create(dev, size)->base; ++ setup->rcl = &vc4_bo_create(dev, size, true)->base; + if (!setup->rcl) + return -ENOMEM; + list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head, +@@ -256,6 +255,7 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + for (x = min_x_tile; x <= max_x_tile; x++) { + bool first = (x == min_x_tile && y == min_y_tile); + bool last = (x == max_x_tile && y == max_y_tile); ++ + emit_tile(exec, setup, x, y, first, last); + } + } +diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c +index cf35f58..29a222f 100644 +--- a/drivers/gpu/drm/vc4/vc4_v3d.c ++++ b/drivers/gpu/drm/vc4/vc4_v3d.c +@@ -125,7 +125,7 @@ int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused) + + int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) + { +- struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + uint32_t ident1 = V3D_READ(V3D_IDENT1); +@@ -133,11 +133,13 @@ int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) + uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); + uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); + +- seq_printf(m, "Revision: %d\n", VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); ++ seq_printf(m, "Revision: %d\n", ++ VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); + seq_printf(m, "Slices: %d\n", nslc); + seq_printf(m, "TMUs: %d\n", nslc * tups); + seq_printf(m, "QPUs: %d\n", nslc * qups); +- seq_printf(m, "Semaphores: %d\n", VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); ++ seq_printf(m, "Semaphores: %d\n", ++ VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); + + return 0; + } +@@ -218,7 +220,7 @@ static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) + } + + static void vc4_v3d_unbind(struct device *dev, struct device *master, +- void *data) ++ void *data) + { + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = to_vc4_dev(drm); +diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c +index ff3b62f..e44e355 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate.c ++++ b/drivers/gpu/drm/vc4/vc4_validate.c +@@ -48,7 +48,6 @@ + void *validated, \ + void *untrusted + +- + /** Return the width in pixels of a 64-byte microtile. */ + static uint32_t + utile_width(int cpp) +@@ -192,7 +191,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, + + if (size + offset < size || + size + offset > fbo->base.size) { +- DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %d)\n", ++ DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n", + width, height, + aligned_width, aligned_height, + size, offset, fbo->base.size); +@@ -278,7 +277,7 @@ validate_indexed_prim_list(VALIDATE_ARGS) + + if (offset > ib->base.size || + (ib->base.size - offset) / index_size < length) { +- DRM_ERROR("IB access overflow (%d + %d*%d > %d)\n", ++ DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n", + offset, length, index_size, ib->base.size); + return -EINVAL; + } +@@ -377,6 +376,7 @@ static int + validate_tile_binning_config(VALIDATE_ARGS) + { + struct drm_device *dev = exec->exec_bo->base.dev; ++ struct vc4_bo *tile_bo; + uint8_t flags; + uint32_t tile_state_size, tile_alloc_size; + uint32_t tile_count; +@@ -438,12 +438,12 @@ validate_tile_binning_config(VALIDATE_ARGS) + */ + tile_alloc_size += 1024 * 1024; + +- exec->tile_bo = &vc4_bo_create(dev, exec->tile_alloc_offset + +- tile_alloc_size)->base; ++ tile_bo = vc4_bo_create(dev, exec->tile_alloc_offset + tile_alloc_size, ++ true); ++ exec->tile_bo = &tile_bo->base; + if (!exec->tile_bo) + return -ENOMEM; +- list_add_tail(&to_vc4_bo(&exec->tile_bo->base)->unref_head, +- &exec->unref_list); ++ list_add_tail(&tile_bo->unref_head, &exec->unref_list); + + /* tile alloc address. */ + *(uint32_t *)(validated + 0) = (exec->tile_bo->paddr + +@@ -463,8 +463,8 @@ validate_gem_handles(VALIDATE_ARGS) + return 0; + } + +-#define VC4_DEFINE_PACKET(packet, name, func) \ +- [packet] = { packet ## _SIZE, name, func } ++#define VC4_DEFINE_PACKET(packet, func) \ ++ [packet] = { packet ## _SIZE, #packet, func } + + static const struct cmd_info { + uint16_t len; +@@ -472,42 +472,43 @@ static const struct cmd_info { + int (*func)(struct vc4_exec_info *exec, void *validated, + void *untrusted); + } cmd_info[] = { +- VC4_DEFINE_PACKET(VC4_PACKET_HALT, "halt", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_NOP, "nop", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, "flush", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, "flush all state", validate_flush_all), +- VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, "start tile binning", validate_start_tile_binning), +- VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, "increment semaphore", validate_increment_semaphore), +- +- VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE, "Indexed Primitive List", validate_indexed_prim_list), +- +- VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE, "Vertex Array Primitives", validate_gl_array_primitive), +- +- /* This is only used by clipped primitives (packets 48 and 49), which +- * we don't support parsing yet. +- */ +- VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, "primitive list format", NULL), +- +- VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, "GL Shader State", validate_gl_shader_state), +- VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, "NV Shader State", validate_nv_shader_state), +- +- VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, "configuration bits", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, "flat shade flags", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE, "point size", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH, "line width", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY, "RHT X boundary", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET, "Depth Offset", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW, "Clip Window", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET, "Viewport Offset", NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING, "Clipper XY Scaling", NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_HALT, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_NOP, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, validate_flush_all), ++ VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, ++ validate_start_tile_binning), ++ VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, ++ validate_increment_semaphore), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE, ++ validate_indexed_prim_list), ++ VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE, ++ validate_gl_array_primitive), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, NULL), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, validate_gl_shader_state), ++ VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, validate_nv_shader_state), ++ ++ VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET, NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING, NULL), + /* Note: The docs say this was also 105, but it was 106 in the + * initial userland code drop. + */ +- VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING, "Clipper Z Scale and Offset", NULL), ++ VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING, NULL), + +- VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG, "tile binning configuration", validate_tile_binning_config), ++ VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG, ++ validate_tile_binning_config), + +- VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES, "GEM handles", validate_gem_handles), ++ VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES, validate_gem_handles), + }; + + int +@@ -526,7 +527,7 @@ vc4_validate_bin_cl(struct drm_device *dev, + u8 cmd = *(uint8_t *)src_pkt; + const struct cmd_info *info; + +- if (cmd > ARRAY_SIZE(cmd_info)) { ++ if (cmd >= ARRAY_SIZE(cmd_info)) { + DRM_ERROR("0x%08x: packet %d out of bounds\n", + src_offset, cmd); + return -EINVAL; +@@ -539,11 +540,6 @@ vc4_validate_bin_cl(struct drm_device *dev, + return -EINVAL; + } + +-#if 0 +- DRM_INFO("0x%08x: packet %d (%s) size %d processing...\n", +- src_offset, cmd, info->name, info->len); +-#endif +- + if (src_offset + info->len > len) { + DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x " + "exceeds bounds (0x%08x)\n", +@@ -558,8 +554,7 @@ vc4_validate_bin_cl(struct drm_device *dev, + if (info->func && info->func(exec, + dst_pkt + 1, + src_pkt + 1)) { +- DRM_ERROR("0x%08x: packet %d (%s) failed to " +- "validate\n", ++ DRM_ERROR("0x%08x: packet %d (%s) failed to validate\n", + src_offset, cmd, info->name); + return -EINVAL; + } +@@ -618,12 +613,14 @@ reloc_tex(struct vc4_exec_info *exec, + + if (sample->is_direct) { + uint32_t remaining_size = tex->base.size - p0; ++ + if (p0 > tex->base.size - 4) { + DRM_ERROR("UBO offset greater than UBO size\n"); + goto fail; + } + if (p1 > remaining_size - 4) { +- DRM_ERROR("UBO clamp would allow reads outside of UBO\n"); ++ DRM_ERROR("UBO clamp would allow reads " ++ "outside of UBO\n"); + goto fail; + } + *validated_p0 = tex->paddr + p0; +@@ -786,7 +783,7 @@ validate_shader_rec(struct drm_device *dev, + struct drm_gem_cma_object *bo[ARRAY_SIZE(gl_relocs) + 8]; + uint32_t nr_attributes = 0, nr_fixed_relocs, nr_relocs, packet_size; + int i; +- struct vc4_validated_shader_info *validated_shader; ++ struct vc4_validated_shader_info *shader; + + if (state->packet == VC4_PACKET_NV_SHADER_STATE) { + relocs = nv_relocs; +@@ -841,12 +838,12 @@ validate_shader_rec(struct drm_device *dev, + else + mode = VC4_MODE_RENDER; + +- if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) { ++ if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) + return false; +- } + } + + for (i = 0; i < nr_fixed_relocs; i++) { ++ struct vc4_bo *vc4_bo; + uint32_t o = relocs[i].offset; + uint32_t src_offset = *(uint32_t *)(pkt_u + o); + uint32_t *texture_handles_u; +@@ -858,34 +855,34 @@ validate_shader_rec(struct drm_device *dev, + switch (relocs[i].type) { + case RELOC_CODE: + if (src_offset != 0) { +- DRM_ERROR("Shaders must be at offset 0 of " +- "the BO.\n"); ++ DRM_ERROR("Shaders must be at offset 0 " ++ "of the BO.\n"); + goto fail; } + +- validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader; +- if (!validated_shader) ++ vc4_bo = to_vc4_bo(&bo[i]->base); ++ shader = vc4_bo->validated_shader; ++ if (!shader) + goto fail; + +- if (validated_shader->uniforms_src_size > +- exec->uniforms_size) { ++ if (shader->uniforms_src_size > exec->uniforms_size) { + DRM_ERROR("Uniforms src buffer overflow\n"); + goto fail; + } + + texture_handles_u = exec->uniforms_u; + uniform_data_u = (texture_handles_u + +- validated_shader->num_texture_samples); ++ shader->num_texture_samples); + + memcpy(exec->uniforms_v, uniform_data_u, +- validated_shader->uniforms_size); ++ shader->uniforms_size); + + for (tex = 0; +- tex < validated_shader->num_texture_samples; ++ tex < shader->num_texture_samples; + tex++) { + if (!reloc_tex(exec, + uniform_data_u, +- &validated_shader->texture_samples[tex], ++ &shader->texture_samples[tex], + texture_handles_u[tex])) { + goto fail; + } +@@ -893,9 +890,9 @@ validate_shader_rec(struct drm_device *dev, + + *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; + +- exec->uniforms_u += validated_shader->uniforms_src_size; +- exec->uniforms_v += validated_shader->uniforms_size; +- exec->uniforms_p += validated_shader->uniforms_size; ++ exec->uniforms_u += shader->uniforms_src_size; ++ exec->uniforms_v += shader->uniforms_size; ++ exec->uniforms_p += shader->uniforms_size; + + break; + +@@ -926,7 +923,8 @@ validate_shader_rec(struct drm_device *dev, + max_index = ((vbo->base.size - offset - attr_size) / + stride); + if (state->max_index > max_index) { +- DRM_ERROR("primitives use index %d out of supplied %d\n", ++ DRM_ERROR("primitives use index %d out of " ++ "supplied %d\n", + state->max_index, max_index); + return -EINVAL; + } +diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c +index 0aab9d7..f67124b 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c ++++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c +@@ -24,24 +24,16 @@ + /** + * DOC: Shader validator for VC4. + * +- * The VC4 has no IOMMU between it and system memory. So, a user with access +- * to execute shaders could escalate privilege by overwriting system memory +- * (using the VPM write address register in the general-purpose DMA mode) or +- * reading system memory it shouldn't (reading it as a texture, or uniform +- * data, or vertex data). ++ * The VC4 has no IOMMU between it and system memory, so a user with ++ * access to execute shaders could escalate privilege by overwriting ++ * system memory (using the VPM write address register in the ++ * general-purpose DMA mode) or reading system memory it shouldn't ++ * (reading it as a texture, or uniform data, or vertex data). + * +- * This walks over a shader starting from some offset within a BO, ensuring +- * that its accesses are appropriately bounded, and recording how many texture +- * accesses are made and where so that we can do relocations for them in the ++ * This walks over a shader BO, ensuring that its accesses are ++ * appropriately bounded, and recording how many texture accesses are ++ * made and where so that we can do relocations for them in the + * uniform stream. +- * +- * The kernel API has shaders stored in user-mapped BOs. The BOs will be +- * forcibly unmapped from the process before validation, and any cache of +- * validated state will be flushed if the mapping is faulted back in. +- * +- * Storing the shaders in BOs means that the validation process will be slow +- * due to uncached reads, but since shaders are long-lived and shader BOs are +- * never actually modified, this shouldn't be a problem. + */ + + #include "vc4_drv.h" +@@ -70,7 +62,6 @@ waddr_to_live_reg_index(uint32_t waddr, bool is_b) + else + return waddr; + } else if (waddr <= QPU_W_ACC3) { +- + return 64 + waddr - QPU_W_ACC0; + } else { + return ~0; +@@ -85,15 +76,14 @@ raddr_add_a_to_live_reg_index(uint64_t inst) + uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); + uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); + +- if (add_a == QPU_MUX_A) { ++ if (add_a == QPU_MUX_A) + return raddr_a; +- } else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) { ++ else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) + return 32 + raddr_b; +- } else if (add_a <= QPU_MUX_R3) { ++ else if (add_a <= QPU_MUX_R3) + return 64 + add_a; +- } else { ++ else + return ~0; +- } + } + + static bool +@@ -111,9 +101,9 @@ is_tmu_write(uint32_t waddr) + } + + static bool +-record_validated_texture_sample(struct vc4_validated_shader_info *validated_shader, +- struct vc4_shader_validation_state *validation_state, +- int tmu) ++record_texture_sample(struct vc4_validated_shader_info *validated_shader, ++ struct vc4_shader_validation_state *validation_state, ++ int tmu) + { + uint32_t s = validated_shader->num_texture_samples; + int i; +@@ -226,8 +216,8 @@ check_tmu_write(uint64_t inst, + validated_shader->uniforms_size += 4; + + if (submit) { +- if (!record_validated_texture_sample(validated_shader, +- validation_state, tmu)) { ++ if (!record_texture_sample(validated_shader, ++ validation_state, tmu)) { + return false; + } + +@@ -238,10 +228,10 @@ check_tmu_write(uint64_t inst, + } + + static bool +-check_register_write(uint64_t inst, +- struct vc4_validated_shader_info *validated_shader, +- struct vc4_shader_validation_state *validation_state, +- bool is_mul) ++check_reg_write(uint64_t inst, ++ struct vc4_validated_shader_info *validated_shader, ++ struct vc4_shader_validation_state *validation_state, ++ bool is_mul) + { + uint32_t waddr = (is_mul ? + QPU_GET_FIELD(inst, QPU_WADDR_MUL) : +@@ -297,7 +287,7 @@ check_register_write(uint64_t inst, + return true; + + case QPU_W_TLB_STENCIL_SETUP: +- return true; ++ return true; + } + + return true; +@@ -360,7 +350,7 @@ track_live_clamps(uint64_t inst, + } + + validation_state->live_max_clamp_regs[lri_add] = true; +- } if (op_add == QPU_A_MIN) { ++ } else if (op_add == QPU_A_MIN) { + /* Track live clamps of a value clamped to a minimum of 0 and + * a maximum of some uniform's offset. + */ +@@ -392,8 +382,10 @@ check_instruction_writes(uint64_t inst, + return false; + } + +- ok = (check_register_write(inst, validated_shader, validation_state, false) && +- check_register_write(inst, validated_shader, validation_state, true)); ++ ok = (check_reg_write(inst, validated_shader, validation_state, ++ false) && ++ check_reg_write(inst, validated_shader, validation_state, ++ true)); + + track_live_clamps(inst, validated_shader, validation_state); + +@@ -441,7 +433,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) + shader = shader_obj->vaddr; + max_ip = shader_obj->base.size / sizeof(uint64_t); + +- validated_shader = kcalloc(sizeof(*validated_shader), 1, GFP_KERNEL); ++ validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL); + if (!validated_shader) + return NULL; + +@@ -497,7 +489,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) + + if (ip == max_ip) { + DRM_ERROR("shader failed to terminate before " +- "shader BO end at %d\n", ++ "shader BO end at %zd\n", + shader_obj->base.size); + goto fail; + } +diff --git a/include/drm/drmP.h b/include/drm/drmP.h +index 54f5469..987c25a 100644 +--- a/include/drm/drmP.h ++++ b/include/drm/drmP.h +@@ -585,6 +585,13 @@ struct drm_driver { + int (*gem_open_object) (struct drm_gem_object *, struct drm_file *); + void (*gem_close_object) (struct drm_gem_object *, struct drm_file *); + ++ /** ++ * Hook for allocating the GEM object struct, for use by core ++ * helpers. ++ */ ++ struct drm_gem_object *(*gem_create_object)(struct drm_device *dev, ++ size_t size); ++ + /* prime: */ + /* export handle -> fd (see drm_gem_prime_handle_to_fd() helper) */ + int (*prime_handle_to_fd)(struct drm_device *dev, struct drm_file *file_priv, +@@ -639,7 +646,6 @@ struct drm_driver { + + u32 driver_features; + int dev_priv_size; +- size_t gem_obj_size; + const struct drm_ioctl_desc *ioctls; + int num_ioctls; + const struct file_operations *fops; -- 2.5.0 -From b669684c3d592e9e4455cccfeaf987dff0338f12 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Sun, 13 Dec 2015 14:00:16 +0000 -Subject: [PATCH 78/78] bcm270x: Enable bcm2835-rng for all RPi models +From a8812101ce0faa865c1b75e461d5f05d8a43b9e3 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 11 Dec 2015 19:45:03 -0800 +Subject: [PATCH 55/59] drm: Use the driver's gem_object_free function from CMA + helpers. -Include the bcm2835-rng driver in the kernel and enable in DT. +VC4 wraps the CMA objects in its own structures, so it needs to do its +own teardown (waiting for GPU to finish, updating bo_stats tracking). +The other CMA drivers are using drm_gem_cma_free_object as their +gem_free_object, so this should be a no-op for them. + +Signed-off-by: Eric Anholt --- - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 4 ++++ - arch/arm/boot/dts/bcm2708-rpi-b.dts | 4 ++++ - arch/arm/boot/dts/bcm2708-rpi-cm.dts | 4 ++++ - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 4 ++++ - arch/arm/configs/bcm2709_defconfig | 2 +- - arch/arm/configs/bcmrpi_defconfig | 2 +- - 6 files changed, 18 insertions(+), 2 deletions(-) + drivers/gpu/drm/drm_fb_cma_helper.c | 6 +++--- + drivers/gpu/drm/drm_gem_cma_helper.c | 4 ++-- + 2 files changed, 5 insertions(+), 5 deletions(-) -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -index 4deb968..2e4df17 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -98,6 +98,10 @@ - pinctrl-0 = <&i2s_pins>; - }; +diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c +index c19a625..c1a37d3 100644 +--- a/drivers/gpu/drm/drm_fb_cma_helper.c ++++ b/drivers/gpu/drm/drm_fb_cma_helper.c +@@ -266,7 +266,7 @@ static int drm_fbdev_cma_create(struct drm_fb_helper *helper, + fbi = drm_fb_helper_alloc_fbi(helper); + if (IS_ERR(fbi)) { + ret = PTR_ERR(fbi); +- goto err_drm_gem_cma_free_object; ++ goto err_gem_free_object; + } -+&random { -+ status = "okay"; -+}; -+ - &leds { - act_led: act { - label = "led0"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts -index 1e77926..0445b46 100644 ---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -98,6 +98,10 @@ - pinctrl-0 = <&i2s_pins>; - }; + fbdev_cma->fb = drm_fb_cma_alloc(dev, &mode_cmd, &obj, 1); +@@ -299,8 +299,8 @@ static int drm_fbdev_cma_create(struct drm_fb_helper *helper, -+&random { -+ status = "okay"; -+}; -+ - &leds { - act_led: act { - label = "led0"; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -index 587f1e4..87c1a54 100755 ---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -@@ -81,6 +81,10 @@ - pinctrl-0 = <&i2s_pins>; - }; + err_fb_info_destroy: + drm_fb_helper_release_fbi(helper); +-err_drm_gem_cma_free_object: +- drm_gem_cma_free_object(&obj->base); ++err_gem_free_object: ++ dev->driver->gem_free_object(&obj->base); + return ret; + } -+&random { -+ status = "okay"; -+}; -+ - / { - __overrides__ { - uart0 = <&uart0>,"status"; -diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -index 4e6c64e..5206ba2 100644 ---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -98,6 +98,10 @@ - pinctrl-0 = <&i2s_pins>; - }; +diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c +index 0f7b00b..e5df53b 100644 +--- a/drivers/gpu/drm/drm_gem_cma_helper.c ++++ b/drivers/gpu/drm/drm_gem_cma_helper.c +@@ -121,7 +121,7 @@ struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm, + return cma_obj; -+&random { -+ status = "okay"; -+}; -+ - &leds { - act_led: act { - label = "led0"; -diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig -index be6cda9..1f47fb7 100644 ---- a/arch/arm/configs/bcm2709_defconfig -+++ b/arch/arm/configs/bcm2709_defconfig -@@ -590,7 +590,7 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y - CONFIG_SERIAL_OF_PLATFORM=y - CONFIG_TTY_PRINTK=y - CONFIG_HW_RANDOM=y --CONFIG_HW_RANDOM_BCM2835=m -+CONFIG_HW_RANDOM_BCM2835=y - CONFIG_RAW_DRIVER=y - CONFIG_I2C=y - CONFIG_I2C_CHARDEV=m -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 9e5cd8b..015a2b3 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -583,7 +583,7 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y - CONFIG_SERIAL_OF_PLATFORM=y - CONFIG_TTY_PRINTK=y - CONFIG_HW_RANDOM=y --CONFIG_HW_RANDOM_BCM2835=m -+CONFIG_HW_RANDOM_BCM2835=y - CONFIG_RAW_DRIVER=y - CONFIG_I2C=y - CONFIG_I2C_CHARDEV=m + error: +- drm_gem_cma_free_object(&cma_obj->base); ++ drm->driver->gem_free_object(&cma_obj->base); + return ERR_PTR(ret); + } + EXPORT_SYMBOL_GPL(drm_gem_cma_create); +@@ -171,7 +171,7 @@ drm_gem_cma_create_with_handle(struct drm_file *file_priv, + return cma_obj; + + err_handle_create: +- drm_gem_cma_free_object(gem_obj); ++ drm->driver->gem_free_object(gem_obj); + + return ERR_PTR(ret); + } +-- +2.5.0 + + +From 7c236c874ffa28be6d8b1b07366bc7821a844db0 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Fri, 17 Jul 2015 13:15:50 -0700 +Subject: [PATCH 56/59] drm/vc4: Add support for MSAA rendering. + +For MSAA, you set a bit in the binner that halves the size of tiles in +each direction, so you can pack 4 samples per pixel in the tile +buffer. During rendering, you can load and store raw tile buffer +contents (to save the per-sample MSAA contents), or you can load/store +resolved tile buffer contents (loads spam the pixel value to all 4 +samples, and stores either average the 4 color samples, or store the +first sample for Z/S). + +Signed-off-by: Eric Anholt +--- + drivers/gpu/drm/vc4/vc4_packet.h | 23 ++- + drivers/gpu/drm/vc4/vc4_render_cl.c | 274 ++++++++++++++++++++++++++++++------ + drivers/gpu/drm/vc4/vc4_validate.c | 5 +- + include/uapi/drm/vc4_drm.h | 11 +- + 4 files changed, 258 insertions(+), 55 deletions(-) + +diff --git a/drivers/gpu/drm/vc4/vc4_packet.h b/drivers/gpu/drm/vc4/vc4_packet.h +index cee38aa..0f31cc0 100644 +--- a/drivers/gpu/drm/vc4/vc4_packet.h ++++ b/drivers/gpu/drm/vc4/vc4_packet.h +@@ -123,6 +123,11 @@ enum vc4_packet { + #define VC4_PACKET_TILE_COORDINATES_SIZE 3 + #define VC4_PACKET_GEM_HANDLES_SIZE 9 + ++/* Number of multisamples supported. */ ++#define VC4_MAX_SAMPLES 4 ++/* Size of a full resolution color or Z tile buffer load/store. */ ++#define VC4_TILE_BUFFER_SIZE (64 * 64 * 4) ++ + /** @{ + * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. +@@ -137,10 +142,20 @@ enum vc4_packet { + * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and + * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. + */ +-#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3) +-#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2) +-#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1) +-#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0) ++#define VC4_LOADSTORE_FULL_RES_EOF BIT(3) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) ++ ++/** @{ ++ * ++ * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and ++ * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. ++ */ ++#define VC4_LOADSTORE_FULL_RES_EOF BIT(3) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) ++#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) + + /** @{ + * +diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c +index 3516354..8f2ec57 100644 +--- a/drivers/gpu/drm/vc4/vc4_render_cl.c ++++ b/drivers/gpu/drm/vc4/vc4_render_cl.c +@@ -37,9 +37,11 @@ + + struct vc4_rcl_setup { + struct drm_gem_cma_object *color_read; +- struct drm_gem_cma_object *color_ms_write; ++ struct drm_gem_cma_object *color_write; + struct drm_gem_cma_object *zs_read; + struct drm_gem_cma_object *zs_write; ++ struct drm_gem_cma_object *msaa_color_write; ++ struct drm_gem_cma_object *msaa_zs_write; + + struct drm_gem_cma_object *rcl; + u32 next_offset; +@@ -82,6 +84,22 @@ static void vc4_store_before_load(struct vc4_rcl_setup *setup) + } + + /* ++ * Calculates the physical address of the start of a tile in a RCL surface. ++ * ++ * Unlike the other load/store packets, ++ * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile ++ * coordinates packet, and instead just store to the address given. ++ */ ++static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec, ++ struct drm_gem_cma_object *bo, ++ struct drm_vc4_submit_rcl_surface *surf, ++ uint8_t x, uint8_t y) ++{ ++ return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE * ++ (DIV_ROUND_UP(exec->args->width, 32) * y + x); ++} ++ ++/* + * Emits a PACKET_TILE_COORDINATES if one isn't already pending. + * + * The tile coordinates packet triggers a pending load if there is one, are +@@ -108,22 +126,41 @@ static void emit_tile(struct vc4_exec_info *exec, + * may be outstanding at a time. + */ + if (setup->color_read) { +- rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); +- rcl_u16(setup, args->color_read.bits); +- rcl_u32(setup, +- setup->color_read->paddr + args->color_read.offset); ++ if (args->color_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->color_read, ++ &args->color_read, x, y) | ++ VC4_LOADSTORE_FULL_RES_DISABLE_ZS); ++ } else { ++ rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); ++ rcl_u16(setup, args->color_read.bits); ++ rcl_u32(setup, setup->color_read->paddr + ++ args->color_read.offset); ++ } + } + + if (setup->zs_read) { +- if (setup->color_read) { +- /* Exec previous load. */ +- vc4_tile_coordinates(setup, x, y); +- vc4_store_before_load(setup); ++ if (args->zs_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->zs_read, ++ &args->zs_read, x, y) | ++ VC4_LOADSTORE_FULL_RES_DISABLE_COLOR); ++ } else { ++ if (setup->color_read) { ++ /* Exec previous load. */ ++ vc4_tile_coordinates(setup, x, y); ++ vc4_store_before_load(setup); ++ } ++ ++ rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); ++ rcl_u16(setup, args->zs_read.bits); ++ rcl_u32(setup, setup->zs_read->paddr + ++ args->zs_read.offset); + } +- +- rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); +- rcl_u16(setup, args->zs_read.bits); +- rcl_u32(setup, setup->zs_read->paddr + args->zs_read.offset); + } + + /* Clipping depends on tile coordinates having been +@@ -144,20 +181,60 @@ static void emit_tile(struct vc4_exec_info *exec, + (y * exec->bin_tiles_x + x) * 32)); + } + ++ if (setup->msaa_color_write) { ++ bool last_tile_write = (!setup->msaa_zs_write && ++ !setup->zs_write && ++ !setup->color_write); ++ uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS; ++ ++ if (!last_tile_write) ++ bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; ++ else if (last) ++ bits |= VC4_LOADSTORE_FULL_RES_EOF; ++ rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->msaa_color_write, ++ &args->msaa_color_write, x, y) | ++ bits); ++ } ++ ++ if (setup->msaa_zs_write) { ++ bool last_tile_write = (!setup->zs_write && ++ !setup->color_write); ++ uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR; ++ ++ if (setup->msaa_color_write) ++ vc4_tile_coordinates(setup, x, y); ++ if (!last_tile_write) ++ bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; ++ else if (last) ++ bits |= VC4_LOADSTORE_FULL_RES_EOF; ++ rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); ++ rcl_u32(setup, ++ vc4_full_res_offset(exec, setup->msaa_zs_write, ++ &args->msaa_zs_write, x, y) | ++ bits); ++ } ++ + if (setup->zs_write) { ++ bool last_tile_write = !setup->color_write; ++ ++ if (setup->msaa_color_write || setup->msaa_zs_write) ++ vc4_tile_coordinates(setup, x, y); ++ + rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); + rcl_u16(setup, args->zs_write.bits | +- (setup->color_ms_write ? +- VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR : 0)); ++ (last_tile_write ? ++ 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR)); + rcl_u32(setup, + (setup->zs_write->paddr + args->zs_write.offset) | +- ((last && !setup->color_ms_write) ? ++ ((last && last_tile_write) ? + VC4_LOADSTORE_TILE_BUFFER_EOF : 0)); + } + +- if (setup->color_ms_write) { +- if (setup->zs_write) { +- /* Reset after previous store */ ++ if (setup->color_write) { ++ if (setup->msaa_color_write || setup->msaa_zs_write || ++ setup->zs_write) { + vc4_tile_coordinates(setup, x, y); + } + +@@ -192,14 +269,26 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + } + + if (setup->color_read) { +- loop_body_size += (VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE); ++ if (args->color_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; ++ } else { ++ loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; ++ } + } + if (setup->zs_read) { +- if (setup->color_read) { +- loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; +- loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; ++ if (args->zs_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; ++ } else { ++ if (setup->color_read && ++ !(args->color_read.flags & ++ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) { ++ loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; ++ loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; ++ } ++ loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; + } +- loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; + } + + if (has_bin) { +@@ -207,13 +296,23 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE; + } + ++ if (setup->msaa_color_write) ++ loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; ++ if (setup->msaa_zs_write) ++ loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; ++ + if (setup->zs_write) + loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; +- if (setup->color_ms_write) { +- if (setup->zs_write) +- loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; ++ if (setup->color_write) + loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE; +- } ++ ++ /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */ ++ loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE * ++ ((setup->msaa_color_write != NULL) + ++ (setup->msaa_zs_write != NULL) + ++ (setup->color_write != NULL) + ++ (setup->zs_write != NULL) - 1); ++ + size += xtiles * ytiles * loop_body_size; + + setup->rcl = &vc4_bo_create(dev, size, true)->base; +@@ -224,13 +323,12 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + + rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG); + rcl_u32(setup, +- (setup->color_ms_write ? +- (setup->color_ms_write->paddr + +- args->color_ms_write.offset) : ++ (setup->color_write ? (setup->color_write->paddr + ++ args->color_write.offset) : + 0)); + rcl_u16(setup, args->width); + rcl_u16(setup, args->height); +- rcl_u16(setup, args->color_ms_write.bits); ++ rcl_u16(setup, args->color_write.bits); + + /* The tile buffer gets cleared when the previous tile is stored. If + * the clear values changed between frames, then the tile buffer has +@@ -267,6 +365,56 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, + return 0; + } + ++static int vc4_full_res_bounds_check(struct vc4_exec_info *exec, ++ struct drm_gem_cma_object *obj, ++ struct drm_vc4_submit_rcl_surface *surf) ++{ ++ struct drm_vc4_submit_cl *args = exec->args; ++ u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32); ++ ++ if (surf->offset > obj->base.size) { ++ DRM_ERROR("surface offset %d > BO size %zd\n", ++ surf->offset, obj->base.size); ++ return -EINVAL; ++ } ++ ++ if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < ++ render_tiles_stride * args->max_y_tile + args->max_x_tile) { ++ DRM_ERROR("MSAA tile %d, %d out of bounds " ++ "(bo size %zd, offset %d).\n", ++ args->max_x_tile, args->max_y_tile, ++ obj->base.size, ++ surf->offset); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec, ++ struct drm_gem_cma_object **obj, ++ struct drm_vc4_submit_rcl_surface *surf) ++{ ++ if (surf->flags != 0 || surf->bits != 0) { ++ DRM_ERROR("MSAA surface had nonzero flags/bits\n"); ++ return -EINVAL; ++ } ++ ++ if (surf->hindex == ~0) ++ return 0; ++ ++ *obj = vc4_use_bo(exec, surf->hindex); ++ if (!*obj) ++ return -EINVAL; ++ ++ if (surf->offset & 0xf) { ++ DRM_ERROR("MSAA write must be 16b aligned.\n"); ++ return -EINVAL; ++ } ++ ++ return vc4_full_res_bounds_check(exec, *obj, surf); ++} ++ + static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + struct drm_gem_cma_object **obj, + struct drm_vc4_submit_rcl_surface *surf) +@@ -278,9 +426,10 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + uint8_t format = VC4_GET_FIELD(surf->bits, + VC4_LOADSTORE_TILE_BUFFER_FORMAT); + int cpp; ++ int ret; + +- if (surf->pad != 0) { +- DRM_ERROR("Padding unset\n"); ++ if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ DRM_ERROR("Extra flags set\n"); + return -EINVAL; + } + +@@ -290,6 +439,25 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + if (!vc4_use_bo(exec, surf->hindex, VC4_MODE_RENDER, obj)) + return -EINVAL; + ++ if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { ++ if (surf == &exec->args->zs_write) { ++ DRM_ERROR("general zs write may not be a full-res.\n"); ++ return -EINVAL; ++ } ++ ++ if (surf->bits != 0) { ++ DRM_ERROR("load/store general bits set with " ++ "full res load/store.\n"); ++ return -EINVAL; ++ } ++ ++ ret = vc4_full_res_bounds_check(exec, *obj, surf); ++ if (!ret) ++ return ret; ++ ++ return 0; ++ } ++ + if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK | + VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK | + VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) { +@@ -341,9 +509,10 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + } + + static int +-vc4_rcl_ms_surface_setup(struct vc4_exec_info *exec, +- struct drm_gem_cma_object **obj, +- struct drm_vc4_submit_rcl_surface *surf) ++vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, ++ struct vc4_rcl_setup *setup, ++ struct drm_gem_cma_object **obj, ++ struct drm_vc4_submit_rcl_surface *surf) + { + uint8_t tiling = VC4_GET_FIELD(surf->bits, + VC4_RENDER_CONFIG_MEMORY_FORMAT); +@@ -351,13 +520,15 @@ vc4_rcl_ms_surface_setup(struct vc4_exec_info *exec, + VC4_RENDER_CONFIG_FORMAT); + int cpp; + +- if (surf->pad != 0) { +- DRM_ERROR("Padding unset\n"); ++ if (surf->flags != 0) { ++ DRM_ERROR("No flags supported on render config.\n"); + return -EINVAL; + } + + if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK | +- VC4_RENDER_CONFIG_FORMAT_MASK)) { ++ VC4_RENDER_CONFIG_FORMAT_MASK | ++ VC4_RENDER_CONFIG_MS_MODE_4X | ++ VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) { + DRM_ERROR("Unknown bits in render config: 0x%04x\n", + surf->bits); + return -EINVAL; +@@ -413,18 +584,20 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) + if (has_bin && + (args->max_x_tile > exec->bin_tiles_x || + args->max_y_tile > exec->bin_tiles_y)) { +- DRM_ERROR("Render tiles (%d,%d) outside of bin config (%d,%d)\n", ++ DRM_ERROR("Render tiles (%d,%d) outside of bin config " ++ "(%d,%d)\n", + args->max_x_tile, args->max_y_tile, + exec->bin_tiles_x, exec->bin_tiles_y); + return -EINVAL; + } + +- ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read); ++ ret = vc4_rcl_render_config_surface_setup(exec, &setup, ++ &setup.color_write, ++ &args->color_write); + if (ret) + return ret; + +- ret = vc4_rcl_ms_surface_setup(exec, &setup.color_ms_write, +- &args->color_ms_write); ++ ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read); + if (ret) + return ret; + +@@ -436,10 +609,21 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) + if (ret) + return ret; + ++ ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write, ++ &args->msaa_color_write); ++ if (ret) ++ return ret; ++ ++ ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write, ++ &args->msaa_zs_write); ++ if (ret) ++ return ret; ++ + /* We shouldn't even have the job submitted to us if there's no + * surface to write out. + */ +- if (!setup.color_ms_write && !setup.zs_write) { ++ if (!setup.color_write && !setup.zs_write && ++ !setup.msaa_color_write && !setup.msaa_zs_write) { + DRM_ERROR("RCL requires color or Z/S write\n"); + return -EINVAL; + } +diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c +index e44e355..2f22f19 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate.c ++++ b/drivers/gpu/drm/vc4/vc4_validate.c +@@ -400,9 +400,8 @@ validate_tile_binning_config(VALIDATE_ARGS) + } + + if (flags & (VC4_BIN_CONFIG_DB_NON_MS | +- VC4_BIN_CONFIG_TILE_BUFFER_64BIT | +- VC4_BIN_CONFIG_MS_MODE_4X)) { +- DRM_ERROR("unsupported bining config flags 0x%02x\n", flags); ++ VC4_BIN_CONFIG_TILE_BUFFER_64BIT)) { ++ DRM_ERROR("unsupported binning config flags 0x%02x\n", flags); + return -EINVAL; + } + +diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h +index 4a8d19f..49cd992 100644 +--- a/include/uapi/drm/vc4_drm.h ++++ b/include/uapi/drm/vc4_drm.h +@@ -46,10 +46,13 @@ struct drm_vc4_submit_rcl_surface { + uint32_t hindex; /* Handle index, or ~0 if not present. */ + uint32_t offset; /* Offset to start of buffer. */ + /* +- * Bits for either render config (color_ms_write) or load/store packet. ++ * Bits for either render config (color_write) or load/store packet. ++ * Bits should all be 0 for MSAA load/stores. + */ + uint16_t bits; +- uint16_t pad; ++ ++#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) ++ uint16_t flags; + }; + + /** +@@ -128,9 +131,11 @@ struct drm_vc4_submit_cl { + uint8_t max_x_tile; + uint8_t max_y_tile; + struct drm_vc4_submit_rcl_surface color_read; +- struct drm_vc4_submit_rcl_surface color_ms_write; ++ struct drm_vc4_submit_rcl_surface color_write; + struct drm_vc4_submit_rcl_surface zs_read; + struct drm_vc4_submit_rcl_surface zs_write; ++ struct drm_vc4_submit_rcl_surface msaa_color_write; ++ struct drm_vc4_submit_rcl_surface msaa_zs_write; + uint32_t clear_color[2]; + uint32_t clear_z; + uint8_t clear_s; +-- +2.5.0 + + +From c5f0c816c8fb2dc259d2ffe1ec6ea143658c3731 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Tue, 8 Dec 2015 14:00:43 -0800 +Subject: [PATCH 57/59] drm/vc4: A few more non-functional changes to sync to + upstream. + +At this point all that's left is the force-enable of HDMI connector, +and using direct firmware calls to turn on V3D instead of the generic +power domain support. + +Signed-off-by: Eric Anholt +--- + drivers/gpu/drm/vc4/vc4_v3d.c | 2 +- + include/uapi/drm/vc4_drm.h | 182 +++++++++++++++++++++--------------------- + 2 files changed, 92 insertions(+), 92 deletions(-) + +diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c +index 29a222f..4d103f7 100644 +--- a/drivers/gpu/drm/vc4/vc4_v3d.c ++++ b/drivers/gpu/drm/vc4/vc4_v3d.c +@@ -109,7 +109,7 @@ static const struct { + + int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused) + { +- struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + int i; +diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h +index 49cd992..eeb37e3 100644 +--- a/include/uapi/drm/vc4_drm.h ++++ b/include/uapi/drm/vc4_drm.h +@@ -24,7 +24,7 @@ + #ifndef _UAPI_VC4_DRM_H_ + #define _UAPI_VC4_DRM_H_ + +-#include ++#include "drm.h" + + #define DRM_VC4_SUBMIT_CL 0x00 + #define DRM_VC4_WAIT_SEQNO 0x01 +@@ -34,25 +34,25 @@ + #define DRM_VC4_CREATE_SHADER_BO 0x05 + #define DRM_VC4_GET_HANG_STATE 0x06 + +-#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) +-#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) +-#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) +-#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) +-#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) +-#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) +-#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) ++#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) ++#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) ++#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) ++#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) ++#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) ++#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) ++#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) + + struct drm_vc4_submit_rcl_surface { +- uint32_t hindex; /* Handle index, or ~0 if not present. */ +- uint32_t offset; /* Offset to start of buffer. */ ++ __u32 hindex; /* Handle index, or ~0 if not present. */ ++ __u32 offset; /* Offset to start of buffer. */ + /* +- * Bits for either render config (color_write) or load/store packet. +- * Bits should all be 0 for MSAA load/stores. ++ * Bits for either render config (color_write) or load/store packet. ++ * Bits should all be 0 for MSAA load/stores. + */ +- uint16_t bits; ++ __u16 bits; + + #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) +- uint16_t flags; ++ __u16 flags; + }; + + /** +@@ -76,7 +76,7 @@ struct drm_vc4_submit_cl { + * then writes out the state updates and draw calls necessary per tile + * to the tile allocation BO. + */ +- uint64_t bin_cl; ++ __u64 bin_cl; + + /* Pointer to the shader records. + * +@@ -85,16 +85,16 @@ struct drm_vc4_submit_cl { + * reference to the shader record has enough information to determine + * how many pointers are necessary (fixed number for shaders/uniforms, + * and an attribute count), so those BO indices into bo_handles are +- * just stored as uint32_ts before each shader record passed in. ++ * just stored as __u32s before each shader record passed in. + */ +- uint64_t shader_rec; ++ __u64 shader_rec; + + /* Pointer to uniform data and texture handles for the textures + * referenced by the shader. + * + * For each shader state record, there is a set of uniform data in the + * order referenced by the record (FS, VS, then CS). Each set of +- * uniform data has a uint32_t index into bo_handles per texture ++ * uniform data has a __u32 index into bo_handles per texture + * sample operation, in the order the QPU_W_TMUn_S writes appear in + * the program. Following the texture BO handle indices is the actual + * uniform data. +@@ -103,52 +103,52 @@ struct drm_vc4_submit_cl { + * because the kernel has to determine the sizes anyway during shader + * code validation. + */ +- uint64_t uniforms; +- uint64_t bo_handles; ++ __u64 uniforms; ++ __u64 bo_handles; + + /* Size in bytes of the binner command list. */ +- uint32_t bin_cl_size; ++ __u32 bin_cl_size; + /* Size in bytes of the set of shader records. */ +- uint32_t shader_rec_size; ++ __u32 shader_rec_size; + /* Number of shader records. + * + * This could just be computed from the contents of shader_records and + * the address bits of references to them from the bin CL, but it + * keeps the kernel from having to resize some allocations it makes. + */ +- uint32_t shader_rec_count; ++ __u32 shader_rec_count; + /* Size in bytes of the uniform state. */ +- uint32_t uniforms_size; ++ __u32 uniforms_size; + + /* Number of BO handles passed in (size is that times 4). */ +- uint32_t bo_handle_count; ++ __u32 bo_handle_count; + + /* RCL setup: */ +- uint16_t width; +- uint16_t height; +- uint8_t min_x_tile; +- uint8_t min_y_tile; +- uint8_t max_x_tile; +- uint8_t max_y_tile; ++ __u16 width; ++ __u16 height; ++ __u8 min_x_tile; ++ __u8 min_y_tile; ++ __u8 max_x_tile; ++ __u8 max_y_tile; + struct drm_vc4_submit_rcl_surface color_read; + struct drm_vc4_submit_rcl_surface color_write; + struct drm_vc4_submit_rcl_surface zs_read; + struct drm_vc4_submit_rcl_surface zs_write; + struct drm_vc4_submit_rcl_surface msaa_color_write; + struct drm_vc4_submit_rcl_surface msaa_zs_write; +- uint32_t clear_color[2]; +- uint32_t clear_z; +- uint8_t clear_s; ++ __u32 clear_color[2]; ++ __u32 clear_z; ++ __u8 clear_s; + +- uint32_t pad:24; ++ __u32 pad:24; + + #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) +- uint32_t flags; ++ __u32 flags; + + /* Returned value of the seqno of this render job (for the + * wait ioctl). + */ +- uint64_t seqno; ++ __u64 seqno; + }; + + /** +@@ -159,8 +159,8 @@ struct drm_vc4_submit_cl { + * block, just return the status." + */ + struct drm_vc4_wait_seqno { +- uint64_t seqno; +- uint64_t timeout_ns; ++ __u64 seqno; ++ __u64 timeout_ns; + }; + + /** +@@ -172,9 +172,9 @@ struct drm_vc4_wait_seqno { + * completed. + */ + struct drm_vc4_wait_bo { +- uint32_t handle; +- uint32_t pad; +- uint64_t timeout_ns; ++ __u32 handle; ++ __u32 pad; ++ __u64 timeout_ns; + }; + + /** +@@ -184,11 +184,30 @@ struct drm_vc4_wait_bo { + * used in a future extension. + */ + struct drm_vc4_create_bo { +- uint32_t size; +- uint32_t flags; ++ __u32 size; ++ __u32 flags; + /** Returned GEM handle for the BO. */ +- uint32_t handle; +- uint32_t pad; ++ __u32 handle; ++ __u32 pad; ++}; ++ ++/** ++ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. ++ * ++ * This doesn't actually perform an mmap. Instead, it returns the ++ * offset you need to use in an mmap on the DRM device node. This ++ * means that tools like valgrind end up knowing about the mapped ++ * memory. ++ * ++ * There are currently no values for the flags argument, but it may be ++ * used in a future extension. ++ */ ++struct drm_vc4_mmap_bo { ++ /** Handle for the object being mapped. */ ++ __u32 handle; ++ __u32 flags; ++ /** offset into the drm node to use for subsequent mmap call. */ ++ __u64 offset; + }; + + /** +@@ -201,43 +220,24 @@ struct drm_vc4_create_bo { + */ + struct drm_vc4_create_shader_bo { + /* Size of the data argument. */ +- uint32_t size; ++ __u32 size; + /* Flags, currently must be 0. */ +- uint32_t flags; ++ __u32 flags; + + /* Pointer to the data. */ +- uint64_t data; ++ __u64 data; + + /** Returned GEM handle for the BO. */ +- uint32_t handle; ++ __u32 handle; + /* Pad, must be 0. */ +- uint32_t pad; +-}; +- +-/** +- * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. +- * +- * This doesn't actually perform an mmap. Instead, it returns the +- * offset you need to use in an mmap on the DRM device node. This +- * means that tools like valgrind end up knowing about the mapped +- * memory. +- * +- * There are currently no values for the flags argument, but it may be +- * used in a future extension. +- */ +-struct drm_vc4_mmap_bo { +- /** Handle for the object being mapped. */ +- uint32_t handle; +- uint32_t flags; +- /** offset into the drm node to use for subsequent mmap call. */ +- uint64_t offset; ++ __u32 pad; + }; + + struct drm_vc4_get_hang_state_bo { +- uint32_t handle; +- uint32_t paddr; +- uint32_t size; +- uint32_t pad; ++ __u32 handle; ++ __u32 paddr; ++ __u32 size; ++ __u32 pad; + }; + + /** +@@ -246,34 +246,34 @@ struct drm_vc4_get_hang_state_bo { + */ + struct drm_vc4_get_hang_state { + /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ +- uint64_t bo; ++ __u64 bo; + /** + * On input, the size of the bo array. Output is the number + * of bos to be returned. + */ +- uint32_t bo_count; ++ __u32 bo_count; + +- uint32_t start_bin, start_render; ++ __u32 start_bin, start_render; + +- uint32_t ct0ca, ct0ea; +- uint32_t ct1ca, ct1ea; +- uint32_t ct0cs, ct1cs; +- uint32_t ct0ra0, ct1ra0; ++ __u32 ct0ca, ct0ea; ++ __u32 ct1ca, ct1ea; ++ __u32 ct0cs, ct1cs; ++ __u32 ct0ra0, ct1ra0; + +- uint32_t bpca, bpcs; +- uint32_t bpoa, bpos; ++ __u32 bpca, bpcs; ++ __u32 bpoa, bpos; + +- uint32_t vpmbase; ++ __u32 vpmbase; + +- uint32_t dbge; +- uint32_t fdbgo; +- uint32_t fdbgb; +- uint32_t fdbgr; +- uint32_t fdbgs; +- uint32_t errstat; ++ __u32 dbge; ++ __u32 fdbgo; ++ __u32 fdbgb; ++ __u32 fdbgr; ++ __u32 fdbgs; ++ __u32 errstat; + + /* Pad that we may save more registers into in the future. */ +- uint32_t pad[16]; ++ __u32 pad[16]; + }; + + #endif /* _UAPI_VC4_DRM_H_ */ +-- +2.5.0 + + +From a28a42a7faea43197392a90984f5354168494f14 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Tue, 15 Dec 2015 23:46:32 +0000 +Subject: [PATCH 58/59] drm/vc4: Use "hpd-gpios" for HDMI GPIO, like what + landed upstream. + +Signed-off-by: Eric Anholt +--- + arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts +index cf5d5c9..da37483 100644 +--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts ++++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts +@@ -68,7 +68,7 @@ + <0x7e808000 0x100>; + interrupts = <2 8>, <2 9>; + ddc = <&i2c2>; +- hpd-gpio = <&gpio 46 GPIO_ACTIVE_HIGH>; ++ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + clocks = <&cprman BCM2835_PLLH_PIX>, + <&cprman BCM2835_CLOCK_HSM>; + clock-names = "pixel", "hdmi"; +-- +2.5.0 + + +From 8353706bc1d231c15c7113e678cfeeefe03e9eaf Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Mon, 7 Dec 2015 12:35:01 -0800 +Subject: [PATCH 59/59] drm/vc4: Synchronize validation code for v2 submission + upstream. + +Signed-off-by: Eric Anholt +--- + drivers/gpu/drm/vc4/vc4_drv.h | 24 +-- + drivers/gpu/drm/vc4/vc4_gem.c | 14 +- + drivers/gpu/drm/vc4/vc4_render_cl.c | 6 +- + drivers/gpu/drm/vc4/vc4_validate.c | 287 +++++++++++++++--------------------- + 4 files changed, 135 insertions(+), 196 deletions(-) + +diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h +index 53dfa8d..ed93fa7 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.h ++++ b/drivers/gpu/drm/vc4/vc4_drv.h +@@ -189,17 +189,6 @@ to_vc4_encoder(struct drm_encoder *encoder) + #define HVS_READ(offset) readl(vc4->hvs->regs + offset) + #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) + +-enum vc4_bo_mode { +- VC4_MODE_UNDECIDED, +- VC4_MODE_RENDER, +- VC4_MODE_SHADER, +-}; +- +-struct vc4_bo_exec_state { +- struct drm_gem_cma_object *bo; +- enum vc4_bo_mode mode; +-}; +- + struct vc4_exec_info { + /* Sequence number for this bin/render job. */ + uint64_t seqno; +@@ -210,7 +199,7 @@ struct vc4_exec_info { + /* This is the array of BOs that were looked up at the start of exec. + * Command validation will use indices into this array. + */ +- struct vc4_bo_exec_state *bo; ++ struct drm_gem_cma_object **bo; + uint32_t bo_count; + + /* Pointers for our position in vc4->job_list */ +@@ -238,7 +227,6 @@ struct vc4_exec_info { + * command lists. + */ + struct vc4_shader_state { +- uint8_t packet; + uint32_t addr; + /* Maximum vertex index referenced by any primitive using this + * shader state. +@@ -254,6 +242,7 @@ struct vc4_exec_info { + bool found_tile_binning_mode_config_packet; + bool found_start_tile_binning_packet; + bool found_increment_semaphore_packet; ++ bool found_flush; + uint8_t bin_tiles_x, bin_tiles_y; + struct drm_gem_cma_object *tile_bo; + uint32_t tile_alloc_offset; +@@ -265,6 +254,9 @@ struct vc4_exec_info { + uint32_t ct0ca, ct0ea; + uint32_t ct1ca, ct1ea; + ++ /* Pointer to the unvalidated bin CL (if present). */ ++ void *bin_u; ++ + /* Pointers to the shader recs. These paddr gets incremented as CL + * packets are relocated in validate_gl_shader_state, and the vaddrs + * (u and v) get incremented and size decremented as the shader recs +@@ -455,10 +447,8 @@ vc4_validate_bin_cl(struct drm_device *dev, + int + vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); + +-bool vc4_use_bo(struct vc4_exec_info *exec, +- uint32_t hindex, +- enum vc4_bo_mode mode, +- struct drm_gem_cma_object **obj); ++struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, ++ uint32_t hindex); + + int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); + +diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c +index fb0b92d..39f29e7 100644 +--- a/drivers/gpu/drm/vc4/vc4_gem.c ++++ b/drivers/gpu/drm/vc4/vc4_gem.c +@@ -169,8 +169,8 @@ vc4_save_hang_state(struct drm_device *dev) + } + + for (i = 0; i < exec->bo_count; i++) { +- drm_gem_object_reference(&exec->bo[i].bo->base); +- kernel_state->bo[i] = &exec->bo[i].bo->base; ++ drm_gem_object_reference(&exec->bo[i]->base); ++ kernel_state->bo[i] = &exec->bo[i]->base; + } + + list_for_each_entry(bo, &exec->unref_list, unref_head) { +@@ -397,7 +397,7 @@ vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno) + unsigned i; + + for (i = 0; i < exec->bo_count; i++) { +- bo = to_vc4_bo(&exec->bo[i].bo->base); ++ bo = to_vc4_bo(&exec->bo[i]->base); + bo->seqno = seqno; + } + +@@ -467,7 +467,7 @@ vc4_cl_lookup_bos(struct drm_device *dev, + return -EINVAL; + } + +- exec->bo = kcalloc(exec->bo_count, sizeof(struct vc4_bo_exec_state), ++ exec->bo = kcalloc(exec->bo_count, sizeof(struct drm_gem_cma_object *), + GFP_KERNEL); + if (!exec->bo) { + DRM_ERROR("Failed to allocate validated BO pointers\n"); +@@ -500,7 +500,7 @@ vc4_cl_lookup_bos(struct drm_device *dev, + goto fail; + } + drm_gem_object_reference(bo); +- exec->bo[i].bo = (struct drm_gem_cma_object *)bo; ++ exec->bo[i] = (struct drm_gem_cma_object *)bo; + } + spin_unlock(&file_priv->table_lock); + +@@ -591,6 +591,8 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) + + exec->ct0ca = exec->exec_bo->paddr + bin_offset; + ++ exec->bin_u = bin; ++ + exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset; + exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset; + exec->shader_rec_size = args->shader_rec_size; +@@ -622,7 +624,7 @@ vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec) + mutex_lock(&dev->struct_mutex); + if (exec->bo) { + for (i = 0; i < exec->bo_count; i++) +- drm_gem_object_unreference(&exec->bo[i].bo->base); ++ drm_gem_object_unreference(&exec->bo[i]->base); + kfree(exec->bo); + } + +diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c +index 8f2ec57..8a2a312 100644 +--- a/drivers/gpu/drm/vc4/vc4_render_cl.c ++++ b/drivers/gpu/drm/vc4/vc4_render_cl.c +@@ -436,7 +436,8 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, + if (surf->hindex == ~0) + return 0; + +- if (!vc4_use_bo(exec, surf->hindex, VC4_MODE_RENDER, obj)) ++ *obj = vc4_use_bo(exec, surf->hindex); ++ if (!*obj) + return -EINVAL; + + if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { +@@ -537,7 +538,8 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, + if (surf->hindex == ~0) + return 0; + +- if (!vc4_use_bo(exec, surf->hindex, VC4_MODE_RENDER, obj)) ++ *obj = vc4_use_bo(exec, surf->hindex); ++ if (!*obj) + return -EINVAL; + + if (tiling > VC4_TILING_FORMAT_LT) { +diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c +index 2f22f19..0fb5b99 100644 +--- a/drivers/gpu/drm/vc4/vc4_validate.c ++++ b/drivers/gpu/drm/vc4/vc4_validate.c +@@ -94,42 +94,42 @@ size_is_lt(uint32_t width, uint32_t height, int cpp) + height <= 4 * utile_height(cpp)); + } + +-bool +-vc4_use_bo(struct vc4_exec_info *exec, +- uint32_t hindex, +- enum vc4_bo_mode mode, +- struct drm_gem_cma_object **obj) ++struct drm_gem_cma_object * ++vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex) + { +- *obj = NULL; ++ struct drm_gem_cma_object *obj; ++ struct vc4_bo *bo; + + if (hindex >= exec->bo_count) { + DRM_ERROR("BO index %d greater than BO count %d\n", + hindex, exec->bo_count); +- return false; ++ return NULL; + } ++ obj = exec->bo[hindex]; ++ bo = to_vc4_bo(&obj->base); + +- if (exec->bo[hindex].mode != mode) { +- if (exec->bo[hindex].mode == VC4_MODE_UNDECIDED) { +- exec->bo[hindex].mode = mode; +- } else { +- DRM_ERROR("BO index %d reused with mode %d vs %d\n", +- hindex, exec->bo[hindex].mode, mode); +- return false; +- } ++ if (bo->validated_shader) { ++ DRM_ERROR("Trying to use shader BO as something other than " ++ "a shader\n"); ++ return NULL; + } + +- *obj = exec->bo[hindex].bo; +- return true; ++ return obj; ++} ++ ++static struct drm_gem_cma_object * ++vc4_use_handle(struct vc4_exec_info *exec, uint32_t gem_handles_packet_index) ++{ ++ return vc4_use_bo(exec, exec->bo_index[gem_handles_packet_index]); + } + + static bool +-vc4_use_handle(struct vc4_exec_info *exec, +- uint32_t gem_handles_packet_index, +- enum vc4_bo_mode mode, +- struct drm_gem_cma_object **obj) ++validate_bin_pos(struct vc4_exec_info *exec, void *untrusted, uint32_t pos) + { +- return vc4_use_bo(exec, exec->bo_index[gem_handles_packet_index], +- mode, obj); ++ /* Note that the untrusted pointer passed to these functions is ++ * incremented past the packet byte. ++ */ ++ return (untrusted - 1 == exec->bin_u + pos); + } + + static uint32_t +@@ -202,13 +202,13 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, + } + + static int +-validate_flush_all(VALIDATE_ARGS) ++validate_flush(VALIDATE_ARGS) + { +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("VC4_PACKET_FLUSH_ALL after " +- "VC4_PACKET_INCREMENT_SEMAPHORE\n"); ++ if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) { ++ DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n"); + return -EINVAL; + } ++ exec->found_flush = true; + + return 0; + } +@@ -233,17 +233,13 @@ validate_start_tile_binning(VALIDATE_ARGS) + static int + validate_increment_semaphore(VALIDATE_ARGS) + { +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("Duplicate VC4_PACKET_INCREMENT_SEMAPHORE\n"); ++ if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) { ++ DRM_ERROR("Bin CL must end with " ++ "VC4_PACKET_INCREMENT_SEMAPHORE\n"); + return -EINVAL; + } + exec->found_increment_semaphore_packet = true; + +- /* Once we've found the semaphore increment, there should be one FLUSH +- * then the end of the command list. The FLUSH actually triggers the +- * increment, so we only need to make sure there +- */ +- + return 0; + } + +@@ -257,11 +253,6 @@ validate_indexed_prim_list(VALIDATE_ARGS) + uint32_t index_size = (*(uint8_t *)(untrusted + 0) >> 4) ? 2 : 1; + struct vc4_shader_state *shader_state; + +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("Drawing after VC4_PACKET_INCREMENT_SEMAPHORE\n"); +- return -EINVAL; +- } +- + /* Check overflow condition */ + if (exec->shader_state_count == 0) { + DRM_ERROR("shader state must precede primitives\n"); +@@ -272,7 +263,8 @@ validate_indexed_prim_list(VALIDATE_ARGS) + if (max_index > shader_state->max_index) + shader_state->max_index = max_index; + +- if (!vc4_use_handle(exec, 0, VC4_MODE_RENDER, &ib)) ++ ib = vc4_use_handle(exec, 0); ++ if (!ib) + return -EINVAL; + + if (offset > ib->base.size || +@@ -295,11 +287,6 @@ validate_gl_array_primitive(VALIDATE_ARGS) + uint32_t max_index; + struct vc4_shader_state *shader_state; + +- if (exec->found_increment_semaphore_packet) { +- DRM_ERROR("Drawing after VC4_PACKET_INCREMENT_SEMAPHORE\n"); +- return -EINVAL; +- } +- + /* Check overflow condition */ + if (exec->shader_state_count == 0) { + DRM_ERROR("shader state must precede primitives\n"); +@@ -329,7 +316,6 @@ validate_gl_shader_state(VALIDATE_ARGS) + return -EINVAL; + } + +- exec->shader_state[i].packet = VC4_PACKET_GL_SHADER_STATE; + exec->shader_state[i].addr = *(uint32_t *)untrusted; + exec->shader_state[i].max_index = 0; + +@@ -348,31 +334,6 @@ validate_gl_shader_state(VALIDATE_ARGS) + } + + static int +-validate_nv_shader_state(VALIDATE_ARGS) +-{ +- uint32_t i = exec->shader_state_count++; +- +- if (i >= exec->shader_state_size) { +- DRM_ERROR("More requests for shader states than declared\n"); +- return -EINVAL; +- } +- +- exec->shader_state[i].packet = VC4_PACKET_NV_SHADER_STATE; +- exec->shader_state[i].addr = *(uint32_t *)untrusted; +- +- if (exec->shader_state[i].addr & 15) { +- DRM_ERROR("NV shader state address 0x%08x misaligned\n", +- exec->shader_state[i].addr); +- return -EINVAL; +- } +- +- *(uint32_t *)validated = (exec->shader_state[i].addr + +- exec->shader_rec_p); +- +- return 0; +-} +- +-static int + validate_tile_binning_config(VALIDATE_ARGS) + { + struct drm_device *dev = exec->exec_bo->base.dev; +@@ -473,8 +434,8 @@ static const struct cmd_info { + } cmd_info[] = { + VC4_DEFINE_PACKET(VC4_PACKET_HALT, NULL), + VC4_DEFINE_PACKET(VC4_PACKET_NOP, NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, NULL), +- VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, validate_flush_all), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, validate_flush), ++ VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, NULL), + VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, + validate_start_tile_binning), + VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, +@@ -488,7 +449,6 @@ static const struct cmd_info { + VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, NULL), + + VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, validate_gl_shader_state), +- VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, validate_nv_shader_state), + + VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, NULL), + VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, NULL), +@@ -575,8 +535,16 @@ vc4_validate_bin_cl(struct drm_device *dev, + return -EINVAL; + } + +- if (!exec->found_increment_semaphore_packet) { +- DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE\n"); ++ /* The bin CL must be ended with INCREMENT_SEMAPHORE and FLUSH. The ++ * semaphore is used to trigger the render CL to start up, and the ++ * FLUSH is what caps the bin lists with ++ * VC4_PACKET_RETURN_FROM_SUB_LIST (so they jump back to the main ++ * render CL when they get called to) and actually triggers the queued ++ * semaphore increment. ++ */ ++ if (!exec->found_increment_semaphore_packet || !exec->found_flush) { ++ DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + " ++ "VC4_PACKET_FLUSH\n"); + return -EINVAL; + } + +@@ -607,7 +575,8 @@ reloc_tex(struct vc4_exec_info *exec, + uint32_t cube_map_stride = 0; + enum vc4_texture_data_type type; + +- if (!vc4_use_bo(exec, texture_handle_index, VC4_MODE_RENDER, &tex)) ++ tex = vc4_use_bo(exec, texture_handle_index); ++ if (!tex) + return false; + + if (sample->is_direct) { +@@ -755,51 +724,28 @@ reloc_tex(struct vc4_exec_info *exec, + } + + static int +-validate_shader_rec(struct drm_device *dev, +- struct vc4_exec_info *exec, +- struct vc4_shader_state *state) ++validate_gl_shader_rec(struct drm_device *dev, ++ struct vc4_exec_info *exec, ++ struct vc4_shader_state *state) + { + uint32_t *src_handles; + void *pkt_u, *pkt_v; +- enum shader_rec_reloc_type { +- RELOC_CODE, +- RELOC_VBO, +- }; +- struct shader_rec_reloc { +- enum shader_rec_reloc_type type; +- uint32_t offset; +- }; +- static const struct shader_rec_reloc gl_relocs[] = { +- { RELOC_CODE, 4 }, /* fs */ +- { RELOC_CODE, 16 }, /* vs */ +- { RELOC_CODE, 28 }, /* cs */ +- }; +- static const struct shader_rec_reloc nv_relocs[] = { +- { RELOC_CODE, 4 }, /* fs */ +- { RELOC_VBO, 12 } ++ static const uint32_t shader_reloc_offsets[] = { ++ 4, /* fs */ ++ 16, /* vs */ ++ 28, /* cs */ + }; +- const struct shader_rec_reloc *relocs; +- struct drm_gem_cma_object *bo[ARRAY_SIZE(gl_relocs) + 8]; +- uint32_t nr_attributes = 0, nr_fixed_relocs, nr_relocs, packet_size; ++ uint32_t shader_reloc_count = ARRAY_SIZE(shader_reloc_offsets); ++ struct drm_gem_cma_object *bo[shader_reloc_count + 8]; ++ uint32_t nr_attributes, nr_relocs, packet_size; + int i; +- struct vc4_validated_shader_info *shader; + +- if (state->packet == VC4_PACKET_NV_SHADER_STATE) { +- relocs = nv_relocs; +- nr_fixed_relocs = ARRAY_SIZE(nv_relocs); +- +- packet_size = 16; +- } else { +- relocs = gl_relocs; +- nr_fixed_relocs = ARRAY_SIZE(gl_relocs); +- +- nr_attributes = state->addr & 0x7; +- if (nr_attributes == 0) +- nr_attributes = 8; +- packet_size = gl_shader_rec_size(state->addr); +- } +- nr_relocs = nr_fixed_relocs + nr_attributes; ++ nr_attributes = state->addr & 0x7; ++ if (nr_attributes == 0) ++ nr_attributes = 8; ++ packet_size = gl_shader_rec_size(state->addr); + ++ nr_relocs = ARRAY_SIZE(shader_reloc_offsets) + nr_attributes; + if (nr_relocs * 4 > exec->shader_rec_size) { + DRM_ERROR("overflowed shader recs reading %d handles " + "from %d bytes left\n", +@@ -829,21 +775,30 @@ validate_shader_rec(struct drm_device *dev, + exec->shader_rec_v += roundup(packet_size, 16); + exec->shader_rec_size -= packet_size; + +- for (i = 0; i < nr_relocs; i++) { +- enum vc4_bo_mode mode; ++ if (!(*(uint16_t *)pkt_u & VC4_SHADER_FLAG_FS_SINGLE_THREAD)) { ++ DRM_ERROR("Multi-threaded fragment shaders not supported.\n"); ++ return -EINVAL; ++ } + +- if (i < nr_fixed_relocs && relocs[i].type == RELOC_CODE) +- mode = VC4_MODE_SHADER; +- else +- mode = VC4_MODE_RENDER; ++ for (i = 0; i < shader_reloc_count; i++) { ++ if (src_handles[i] > exec->bo_count) { ++ DRM_ERROR("Shader handle %d too big\n", src_handles[i]); ++ return -EINVAL; ++ } + +- if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) +- return false; ++ bo[i] = exec->bo[src_handles[i]]; ++ if (!bo[i]) ++ return -EINVAL; ++ } ++ for (i = shader_reloc_count; i < nr_relocs; i++) { ++ bo[i] = vc4_use_bo(exec, src_handles[i]); ++ if (!bo[i]) ++ return -EINVAL; + } + +- for (i = 0; i < nr_fixed_relocs; i++) { +- struct vc4_bo *vc4_bo; +- uint32_t o = relocs[i].offset; ++ for (i = 0; i < shader_reloc_count; i++) { ++ struct vc4_validated_shader_info *validated_shader; ++ uint32_t o = shader_reloc_offsets[i]; + uint32_t src_offset = *(uint32_t *)(pkt_u + o); + uint32_t *texture_handles_u; + void *uniform_data_u; +@@ -851,57 +806,50 @@ validate_shader_rec(struct drm_device *dev, + + *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset; + +- switch (relocs[i].type) { +- case RELOC_CODE: +- if (src_offset != 0) { +- DRM_ERROR("Shaders must be at offset 0 " +- "of the BO.\n"); +- goto fail; +- } ++ if (src_offset != 0) { ++ DRM_ERROR("Shaders must be at offset 0 of " ++ "the BO.\n"); ++ return -EINVAL; ++ } + +- vc4_bo = to_vc4_bo(&bo[i]->base); +- shader = vc4_bo->validated_shader; +- if (!shader) +- goto fail; ++ validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader; ++ if (!validated_shader) ++ return -EINVAL; + +- if (shader->uniforms_src_size > exec->uniforms_size) { +- DRM_ERROR("Uniforms src buffer overflow\n"); +- goto fail; +- } ++ if (validated_shader->uniforms_src_size > ++ exec->uniforms_size) { ++ DRM_ERROR("Uniforms src buffer overflow\n"); ++ return -EINVAL; ++ } + +- texture_handles_u = exec->uniforms_u; +- uniform_data_u = (texture_handles_u + +- shader->num_texture_samples); +- +- memcpy(exec->uniforms_v, uniform_data_u, +- shader->uniforms_size); +- +- for (tex = 0; +- tex < shader->num_texture_samples; +- tex++) { +- if (!reloc_tex(exec, +- uniform_data_u, +- &shader->texture_samples[tex], +- texture_handles_u[tex])) { +- goto fail; +- } +- } ++ texture_handles_u = exec->uniforms_u; ++ uniform_data_u = (texture_handles_u + ++ validated_shader->num_texture_samples); + +- *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; ++ memcpy(exec->uniforms_v, uniform_data_u, ++ validated_shader->uniforms_size); + +- exec->uniforms_u += shader->uniforms_src_size; +- exec->uniforms_v += shader->uniforms_size; +- exec->uniforms_p += shader->uniforms_size; ++ for (tex = 0; ++ tex < validated_shader->num_texture_samples; ++ tex++) { ++ if (!reloc_tex(exec, ++ uniform_data_u, ++ &validated_shader->texture_samples[tex], ++ texture_handles_u[tex])) { ++ return -EINVAL; ++ } ++ } + +- break; ++ *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; + +- case RELOC_VBO: +- break; +- } ++ exec->uniforms_u += validated_shader->uniforms_src_size; ++ exec->uniforms_v += validated_shader->uniforms_size; ++ exec->uniforms_p += validated_shader->uniforms_size; + } + + for (i = 0; i < nr_attributes; i++) { +- struct drm_gem_cma_object *vbo = bo[nr_fixed_relocs + i]; ++ struct drm_gem_cma_object *vbo = ++ bo[ARRAY_SIZE(shader_reloc_offsets) + i]; + uint32_t o = 36 + i * 8; + uint32_t offset = *(uint32_t *)(pkt_u + o + 0); + uint32_t attr_size = *(uint8_t *)(pkt_u + o + 4) + 1; +@@ -933,9 +881,6 @@ validate_shader_rec(struct drm_device *dev, + } + + return 0; +- +-fail: +- return -EINVAL; + } + + int +@@ -946,7 +891,7 @@ vc4_validate_shader_recs(struct drm_device *dev, + int ret = 0; + + for (i = 0; i < exec->shader_state_count; i++) { +- ret = validate_shader_rec(dev, exec, &exec->shader_state[i]); ++ ret = validate_gl_shader_rec(dev, exec, &exec->shader_state[i]); + if (ret) + return ret; + } -- 2.5.0