diff --git a/projects/Allwinner/patches/linux/0057-drm-bridge-dw-hdmi-support-configuring-phy-for-deep-.patch b/projects/Allwinner/patches/linux/0057-drm-bridge-dw-hdmi-support-configuring-phy-for-deep-.patch index 25f4653c39..212558b131 100644 --- a/projects/Allwinner/patches/linux/0057-drm-bridge-dw-hdmi-support-configuring-phy-for-deep-.patch +++ b/projects/Allwinner/patches/linux/0057-drm-bridge-dw-hdmi-support-configuring-phy-for-deep-.patch @@ -1,21 +1,21 @@ -From 760dd4bfec9f57bb1260f7b3219054a2ad28ceb3 Mon Sep 17 00:00:00 2001 +From 444515ce8af5d0286e7e6d5505446f7c70ab7ec0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 20 Jul 2020 21:34:48 +0000 -Subject: [PATCH 11/23] drm/bridge: dw-hdmi: support configuring phy for deep +Subject: [PATCH 11/25] drm/bridge: dw-hdmi: support configuring phy for deep color Q: Should we rename dw_hdmi_curr_ctrl and dw_hdmi_phy_config mpixelclock to mtmdsclock ? Signed-off-by: Jonas Karlman --- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 ++++++++++++----- - 1 file changed, 12 insertions(+), 5 deletions(-) + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 19 +++++++++++++------ + 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index c00fb616b587..da2641a65e75 100644 +index c00fb616b587..8f0a8517ac74 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1578,6 +1578,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1578,20 +1578,21 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; @@ -23,7 +23,10 @@ index c00fb616b587..da2641a65e75 100644 /* TOFIX Will need 420 specific PHY configuration tables */ -@@ -1587,11 +1588,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, + /* PLL/MPLL Cfg - always match on final entry */ + for (; mpll_config->mpixelclock != ~0UL; mpll_config++) +- if (mpixelclock <= mpll_config->mpixelclock) ++ if (mtmdsclock <= mpll_config->mpixelclock) break; for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) diff --git a/projects/Allwinner/patches/linux/0059-WIP-drm-sun4i-de3-Add-support-for-YUV420-output.patch b/projects/Allwinner/patches/linux/0059-WIP-drm-sun4i-de3-Add-support-for-YUV420-output.patch index d4e317c308..cbe3990cf6 100644 --- a/projects/Allwinner/patches/linux/0059-WIP-drm-sun4i-de3-Add-support-for-YUV420-output.patch +++ b/projects/Allwinner/patches/linux/0059-WIP-drm-sun4i-de3-Add-support-for-YUV420-output.patch @@ -1,7 +1,7 @@ -From d8126b4e7ec771a5be4ab9513aed390461a70d3d Mon Sep 17 00:00:00 2001 +From bf64e38ca38de03d894db29cf0f006a03ec93688 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 24 Sep 2023 13:20:12 +0200 -Subject: [PATCH 13/23] WIP: drm/sun4i: de3: Add support for YUV420 output +Subject: [PATCH 13/25] WIP: drm/sun4i: de3: Add support for YUV420 output Signed-off-by: Jernej Skrabec --- @@ -12,16 +12,16 @@ Signed-off-by: Jernej Skrabec drivers/gpu/drm/sun4i/sun50i_fmt.c | 74 ++++++++++ drivers/gpu/drm/sun4i/sun50i_fmt.h | 30 ++++ drivers/gpu/drm/sun4i/sun8i_csc.c | 172 +++++++++++++++++++++- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 97 +++++++++++- - drivers/gpu/drm/sun4i/sun8i_mixer.c | 51 ++++++- + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 121 ++++++++++++++- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 52 ++++++- drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 + - drivers/gpu/drm/sun4i/sunxi_engine.h | 48 ++++++ - 11 files changed, 509 insertions(+), 25 deletions(-) + drivers/gpu/drm/sun4i/sunxi_engine.h | 34 +++++ + 11 files changed, 515 insertions(+), 30 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun50i_fmt.c create mode 100644 drivers/gpu/drm/sun4i/sun50i_fmt.h diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 9c8c17827956..8b4b4d45c1c9 100644 +index 348f58b45e72..fc3c8c660d75 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1019,19 +1019,15 @@ static void hdmi_video_sample(struct dw_hdmi *hdmi) @@ -535,10 +535,10 @@ index 68d955c63b05..3b022bfb85ad 100644 return; } diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -index 22e084989ee6..7309590feb56 100644 +index 22e084989ee6..0837e2576556 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -7,6 +7,7 @@ +@@ -7,18 +7,25 @@ #include #include #include @@ -546,18 +546,25 @@ index 22e084989ee6..7309590feb56 100644 #include #include -@@ -17,8 +18,10 @@ + #include + #include + #include ++#include + #include #include ++#include ++ +#include "sun4i_crtc.h" ++#include "sun4i_tcon.h" #include "sun8i_dw_hdmi.h" #include "sun8i_tcon_top.h" +#include "sunxi_engine.h" #define bridge_to_sun8i_dw_hdmi(x) \ container_of(x, struct sun8i_dw_hdmi, enc_bridge) -@@ -64,16 +67,89 @@ static int sun8i_hdmi_enc_atomic_check(struct drm_bridge *bridge, +@@ -64,16 +71,85 @@ static int sun8i_hdmi_enc_atomic_check(struct drm_bridge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { @@ -565,7 +572,6 @@ index 22e084989ee6..7309590feb56 100644 + struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(crtc_state->crtc); + struct sunxi_engine *engine = crtc->engine; + struct drm_connector_state *old_conn_state; -+ enum drm_color_encoding encoding; + + old_conn_state = drm_atomic_get_old_connector_state(conn_state->state, @@ -577,7 +583,7 @@ index 22e084989ee6..7309590feb56 100644 + case DRM_MODE_COLORIMETRY_SYCC_601: + case DRM_MODE_COLORIMETRY_OPYCC_601: + case DRM_MODE_COLORIMETRY_BT601_YCC: -+ encoding = DRM_COLOR_YCBCR_BT601; ++ engine->encoding = DRM_COLOR_YCBCR_BT601; + break; + + default: @@ -586,7 +592,7 @@ index 22e084989ee6..7309590feb56 100644 + case DRM_MODE_COLORIMETRY_XVYCC_709: + case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: + case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: -+ encoding = DRM_COLOR_YCBCR_BT709; ++ engine->encoding = DRM_COLOR_YCBCR_BT709; + break; + + case DRM_MODE_COLORIMETRY_BT2020_CYCC: @@ -594,15 +600,12 @@ index 22e084989ee6..7309590feb56 100644 + case DRM_MODE_COLORIMETRY_BT2020_RGB: + case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: + case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: -+ encoding = DRM_COLOR_YCBCR_BT2020; ++ engine->encoding = DRM_COLOR_YCBCR_BT2020; + break; + } + -+ if (crtc->engine->format != bridge_state->output_bus_cfg.format) -+ crtc_state->mode_changed = true; -+ -+ sunxi_engine_set_format(engine, bridge_state->output_bus_cfg.format, -+ encoding); ++ engine->format = bridge_state->output_bus_cfg.format; ++ DRM_DEBUG_DRIVER("HDMI output bus format: 0x%04x\n", engine->format); + if (!drm_connector_atomic_hdr_metadata_equal(old_conn_state, conn_state)) crtc_state->mode_changed = true; @@ -648,7 +651,7 @@ index 22e084989ee6..7309590feb56 100644 static const struct drm_bridge_funcs sun8i_hdmi_enc_bridge_funcs = { .attach = sun8i_hdmi_enc_attach, .detach = sun8i_hdmi_enc_detach, -@@ -81,6 +157,7 @@ static const struct drm_bridge_funcs sun8i_hdmi_enc_bridge_funcs = { +@@ -81,21 +157,36 @@ static const struct drm_bridge_funcs sun8i_hdmi_enc_bridge_funcs = { .atomic_check = sun8i_hdmi_enc_atomic_check, .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, @@ -656,7 +659,41 @@ index 22e084989ee6..7309590feb56 100644 .atomic_reset = drm_atomic_helper_bridge_reset, }; -@@ -114,6 +191,11 @@ sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, +-static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *mode, +- struct drm_display_mode *adj_mode) ++static void ++sun8i_dw_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) + { ++ struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(crtc_state->crtc); + struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); ++ struct drm_display_mode *mode = &crtc_state->adjusted_mode; ++ int div; + +- clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); ++ switch (crtc->engine->format) { ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ div = 2; ++ break; ++ default: ++ div = 1; ++ break; ++ } ++ ++ clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000 / div); + } + + static const struct drm_encoder_helper_funcs + sun8i_dw_hdmi_encoder_helper_funcs = { +- .mode_set = sun8i_dw_hdmi_encoder_mode_set, ++ .atomic_mode_set = sun8i_dw_hdmi_encoder_atomic_mode_set, + }; + + static enum drm_mode_status +@@ -114,6 +205,11 @@ sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *info, const struct drm_display_mode *mode) { @@ -668,7 +705,7 @@ index 22e084989ee6..7309590feb56 100644 /* * Controller support maximum of 594 MHz, which correlates to * 4K@60Hz 4:4:4 or RGB. -@@ -257,6 +339,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, +@@ -257,6 +353,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, plat_data->mode_valid = hdmi->quirks->mode_valid; plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe; @@ -677,7 +714,7 @@ index 22e084989ee6..7309590feb56 100644 plat_data->output_port = 1; sun8i_hdmi_phy_set_ops(phy, plat_data); -@@ -291,8 +375,17 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, +@@ -291,8 +389,17 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, hdmi->connector = connector; drm_connector_attach_encoder(connector, encoder); @@ -697,7 +734,7 @@ index 22e084989ee6..7309590feb56 100644 cec_fill_conn_info_from_drm(&conn_info, connector); diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 01382860aaee..8e32d0b24ac9 100644 +index 01382860aaee..b1525906a25d 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -22,7 +22,10 @@ @@ -711,7 +748,7 @@ index 01382860aaee..8e32d0b24ac9 100644 #include "sun8i_mixer.h" #include "sun8i_ui_layer.h" #include "sun8i_vi_layer.h" -@@ -326,12 +329,51 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, +@@ -326,12 +329,52 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", interlaced ? "on" : "off"); @@ -738,7 +775,7 @@ index 01382860aaee..8e32d0b24ac9 100644 + + count = 0; + -+ formats = kcalloc(8, sizeof(*formats), GFP_KERNEL); ++ formats = kcalloc(5, sizeof(*formats), GFP_KERNEL); + if (!formats) + return NULL; + @@ -746,6 +783,7 @@ index 01382860aaee..8e32d0b24ac9 100644 + formats[count++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; + formats[count++] = MEDIA_BUS_FMT_YUV8_1X24; + formats[count++] = MEDIA_BUS_FMT_UYVY8_1X16; ++ formats[count++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; + } + + formats[count++] = MEDIA_BUS_FMT_RGB888_1X24; @@ -766,7 +804,7 @@ index 01382860aaee..8e32d0b24ac9 100644 }; static const struct regmap_config sun8i_mixer_regmap_config = { -@@ -392,6 +434,8 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, +@@ -392,6 +435,8 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, dev_set_drvdata(dev, mixer); mixer->engine.ops = &sun8i_engine_ops; mixer->engine.node = dev->of_node; @@ -775,7 +813,7 @@ index 01382860aaee..8e32d0b24ac9 100644 if (of_property_present(dev->of_node, "iommus")) { /* -@@ -653,6 +697,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { +@@ -653,6 +698,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, .is_de3 = true, @@ -804,7 +842,7 @@ index 85c94884fb9a..13401643c7bf 100644 }; diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h -index ec8cf9b2bda4..5e64cda5675a 100644 +index ec8cf9b2bda4..608a26c3f991 100644 --- a/drivers/gpu/drm/sun4i/sunxi_engine.h +++ b/drivers/gpu/drm/sun4i/sunxi_engine.h @@ -6,6 +6,8 @@ @@ -816,7 +854,7 @@ index ec8cf9b2bda4..5e64cda5675a 100644 struct drm_plane; struct drm_device; struct drm_crtc_state; -@@ -120,6 +122,20 @@ struct sunxi_engine_ops { +@@ -120,6 +122,17 @@ struct sunxi_engine_ops { */ void (*mode_set)(struct sunxi_engine *engine, const struct drm_display_mode *mode); @@ -831,13 +869,10 @@ index ec8cf9b2bda4..5e64cda5675a 100644 + * This function is optional. + */ + u32 *(*get_supported_fmts)(struct sunxi_engine *engine, u32 *num); -+ -+ void (*set_format)(struct sunxi_engine *engine, u32 format, -+ enum drm_color_encoding encoding); }; /** -@@ -137,6 +153,9 @@ struct sunxi_engine { +@@ -137,6 +150,9 @@ struct sunxi_engine { int id; @@ -847,7 +882,7 @@ index ec8cf9b2bda4..5e64cda5675a 100644 /* Engine list management */ struct list_head list; }; -@@ -208,4 +227,33 @@ sunxi_engine_mode_set(struct sunxi_engine *engine, +@@ -208,4 +224,22 @@ sunxi_engine_mode_set(struct sunxi_engine *engine, if (engine->ops && engine->ops->mode_set) engine->ops->mode_set(engine, mode); } @@ -868,17 +903,6 @@ index ec8cf9b2bda4..5e64cda5675a 100644 + *num = 0; + + return NULL; -+} -+ -+static inline void -+sunxi_engine_set_format(struct sunxi_engine *engine, u32 format, -+ enum drm_color_encoding encoding) -+{ -+ if (engine->ops && engine->ops->set_format) -+ return engine->ops->set_format(engine, format, encoding); -+ -+ engine->format = format; -+ engine->encoding = encoding; +} #endif /* _SUNXI_ENGINE_H_ */ -- diff --git a/projects/Allwinner/patches/linux/0068-drm-bridge-dw-hdmi-truly-enforce-420-only-formats-wh.patch b/projects/Allwinner/patches/linux/0068-drm-bridge-dw-hdmi-truly-enforce-420-only-formats-wh.patch new file mode 100644 index 0000000000..b8fc0d94e6 --- /dev/null +++ b/projects/Allwinner/patches/linux/0068-drm-bridge-dw-hdmi-truly-enforce-420-only-formats-wh.patch @@ -0,0 +1,42 @@ +From f3710b424a96078f416e1be9cf52b87eadabae78 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Adri=C3=A1n=20Larumbe?= +Date: Sun, 25 Jun 2023 15:17:16 +0100 +Subject: [PATCH] drm/bridge: dw-hdmi: truly enforce 420-only formats when drm + mode demands it +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The current output bus format selection logic is enforcing YUV420 even +when the drm mode allows for other bus formats as well. +Fix it by adding check for 420-only drm modes. + +Signed-off-by: Adrián Larumbe +Acked-by: Neil Armstrong +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/6e6a217c180584a67ed7992c785764ba54af9151.1687702042.git.adrian.larumbe@collabora.com +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 8e1a9854ebc0..55281f63a186 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -2710,9 +2710,10 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + /* Default 8bit fallback */ + output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; + +- *num_output_fmts = i; +- +- return output_fmts; ++ if (drm_mode_is_420_only(info, mode)) { ++ *num_output_fmts = i; ++ return output_fmts; ++ } + } + + /* +-- +2.42.0 + diff --git a/projects/Allwinner/patches/linux/0069-clk-sunxi-ng-h6-Reparent-CPUX-during-PLL-CPUX-rate-c.patch b/projects/Allwinner/patches/linux/0069-clk-sunxi-ng-h6-Reparent-CPUX-during-PLL-CPUX-rate-c.patch new file mode 100644 index 0000000000..a9b2056c88 --- /dev/null +++ b/projects/Allwinner/patches/linux/0069-clk-sunxi-ng-h6-Reparent-CPUX-during-PLL-CPUX-rate-c.patch @@ -0,0 +1,66 @@ +From edfe1a6c99aff85e97dc1600355a66bbcb417531 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 12 Oct 2023 20:25:42 +0200 +Subject: [PATCH 22/25] clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate + change + +While PLL CPUX clock rate change when CPU is running from it works in +vast majority of cases, now and then it causes instability. This leads +to system crashes and other undefined behaviour. After a lot of testing +(30+ hours) while also doing a lot of frequency switches, we can't +observe any instability issues anymore when doing reparenting to stable +clock like 24 MHz oscillator. + +Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") +Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/ +Reported-by: Chad Wagner +Tested-by: Chad Wagner +Signed-off-by: Jernej Skrabec +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 42568c616181..892df807275c 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -1181,11 +1181,18 @@ static const u32 usb2_clk_regs[] = { + SUN50I_H6_USB3_CLK_REG, + }; + ++static struct ccu_mux_nb sun50i_h6_cpu_nb = { ++ .common = &cpux_clk.common, ++ .cm = &cpux_clk.mux, ++ .delay_us = 1, ++ .bypass_index = 0, /* index of 24 MHz oscillator */ ++}; ++ + static int sun50i_h6_ccu_probe(struct platform_device *pdev) + { + void __iomem *reg; ++ int i, ret; + u32 val; +- int i; + + reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) +@@ -1252,7 +1259,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) + val |= BIT(24); + writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); + +- return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc); ++ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc); ++ if (ret) ++ return ret; ++ ++ /* Reparent CPU during PLL CPUX rate changes */ ++ ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, ++ &sun50i_h6_cpu_nb); ++ ++ return 0; + } + + static const struct of_device_id sun50i_h6_ccu_ids[] = { +-- +2.42.0 + diff --git a/projects/Allwinner/patches/linux/0068-wip-h3-h5-cvbs.patch b/projects/Allwinner/patches/linux/0070-wip-h3-h5-cvbs.patch similarity index 100% rename from projects/Allwinner/patches/linux/0068-wip-h3-h5-cvbs.patch rename to projects/Allwinner/patches/linux/0070-wip-h3-h5-cvbs.patch diff --git a/projects/Allwinner/patches/linux/0069-HACK-SW-CEC-implementation-for-H3.patch b/projects/Allwinner/patches/linux/0071-HACK-SW-CEC-implementation-for-H3.patch similarity index 100% rename from projects/Allwinner/patches/linux/0069-HACK-SW-CEC-implementation-for-H3.patch rename to projects/Allwinner/patches/linux/0071-HACK-SW-CEC-implementation-for-H3.patch diff --git a/projects/Allwinner/patches/linux/0072-HACK-clk-sunxi-ng-unify-parent-for-HDMI-clocks.patch b/projects/Allwinner/patches/linux/0072-HACK-clk-sunxi-ng-unify-parent-for-HDMI-clocks.patch new file mode 100644 index 0000000000..3236f88f9c --- /dev/null +++ b/projects/Allwinner/patches/linux/0072-HACK-clk-sunxi-ng-unify-parent-for-HDMI-clocks.patch @@ -0,0 +1,37 @@ +From 5dd9978ccd81cbb48b57580d90a2ce4bd8305c26 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 12 Oct 2023 20:19:38 +0200 +Subject: [PATCH 25/25] HACK: clk: sunxi-ng: unify parent for HDMI clocks + +Signed-off-by: Jernej Skrabec +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 892df807275c..b63e544c86a7 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -653,7 +653,7 @@ static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8, + static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2", + 0xabc, BIT(0), 0); + +-static const char * const hdmi_parents[] = { "pll-video0", "pll-video1", ++static const char * const hdmi_parents[] = { "osc24M", "pll-video1", + "pll-video1-4x" }; + static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00, + 0, 4, /* M */ +@@ -707,8 +707,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", + static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", + 0xb7c, BIT(0), 0); + +-static const char * const tcon_tv0_parents[] = { "pll-video0", +- "pll-video0-4x", ++static const char * const tcon_tv0_parents[] = { "osc24M", ++ "osc24M", + "pll-video1", + "pll-video1-4x" }; + static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", +-- +2.42.0 +