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Rockchip: linux: Remove patches included in 5.10.17

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heitbaum 2021-02-08 10:38:57 +00:00
parent c846f6a87b
commit f50ab81165
2 changed files with 0 additions and 368 deletions
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286
projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-next.patch
View File

@ -1,35 +1,3 @@
From b8d11c4d2da11b58b58ce4794a644ea6074680b7 Mon Sep 17 00:00:00 2001
From: Sandy Huang <hjc@rock-chips.com>
Date: Fri, 8 Jan 2021 12:06:27 +0100
Subject: [PATCH] arm64: dts: rockchip: fix vopl iommu irq on px30
The vop-mmu shares the irq with its matched vop but not the vpu.
Fixes: 7053e06b1422 ("arm64: dts: rockchip: add core dtsi file for PX30 SoCs")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Link: https://lore.kernel.org/r/20210108110627.3231226-1-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 2695ea8cda14..64193292d26c 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1097,7 +1097,7 @@ vopl_out_lvds: endpoint@1 {
vopl_mmu: iommu@ff470f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff470f00 0x0 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "iface";
From b24a3a7acba3235a5ea07101b3e819e9a176280b Mon Sep 17 00:00:00 2001
From: Demetris Ierokipides <ierokipides.dem@gmail.com>
Date: Fri, 8 Jan 2021 17:10:35 +0200
@ -321,184 +289,6 @@ index 68d5a58cfe88..01ea1f170f77 100644
};
From 2af85aabe3375b91d0096188d98dbb18e2a0d9d0 Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Sun, 6 Dec 2020 11:37:10 +0100
Subject: [PATCH] arm64: dts: rockchip: add QoS register compatibles for rk3399
With the conversion of syscon.yaml minItems for compatibles
was set to 2. Current Rockchip dtsi files only use "syscon" for
QoS registers. Add Rockchip QoS compatibles for rk3399
to reduce notifications produced with:
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20201206103711.7465-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 50 ++++++++++++------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index f5dee5f447bb..cd9fbd3cfcaf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -858,127 +858,127 @@ tsadc: tsadc@ff260000 {
};
qos_emmc: qos@ffa58000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa58000 0x0 0x20>;
};
qos_gmac: qos@ffa5c000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa5c000 0x0 0x20>;
};
qos_pcie: qos@ffa60080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa60080 0x0 0x20>;
};
qos_usb_host0: qos@ffa60100 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa60100 0x0 0x20>;
};
qos_usb_host1: qos@ffa60180 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa60180 0x0 0x20>;
};
qos_usb_otg0: qos@ffa70000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa70000 0x0 0x20>;
};
qos_usb_otg1: qos@ffa70080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa70080 0x0 0x20>;
};
qos_sd: qos@ffa74000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa74000 0x0 0x20>;
};
qos_sdioaudio: qos@ffa76000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa76000 0x0 0x20>;
};
qos_hdcp: qos@ffa90000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa90000 0x0 0x20>;
};
qos_iep: qos@ffa98000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa98000 0x0 0x20>;
};
qos_isp0_m0: qos@ffaa0000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffaa0000 0x0 0x20>;
};
qos_isp0_m1: qos@ffaa0080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffaa0080 0x0 0x20>;
};
qos_isp1_m0: qos@ffaa8000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffaa8000 0x0 0x20>;
};
qos_isp1_m1: qos@ffaa8080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffaa8080 0x0 0x20>;
};
qos_rga_r: qos@ffab0000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffab0000 0x0 0x20>;
};
qos_rga_w: qos@ffab0080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffab0080 0x0 0x20>;
};
qos_video_m0: qos@ffab8000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffab8000 0x0 0x20>;
};
qos_video_m1_r: qos@ffac0000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffac0000 0x0 0x20>;
};
qos_video_m1_w: qos@ffac0080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffac0080 0x0 0x20>;
};
qos_vop_big_r: qos@ffac8000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffac8000 0x0 0x20>;
};
qos_vop_big_w: qos@ffac8080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffac8080 0x0 0x20>;
};
qos_vop_little: qos@ffad0000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffad0000 0x0 0x20>;
};
qos_perihp: qos@ffad8080 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffad8080 0x0 0x20>;
};
qos_gpu: qos@ffae0000 {
- compatible = "syscon";
+ compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffae0000 0x0 0x20>;
};
From 0fefb9cc8fa016a264d66110024916a6b8539cc4 Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Sun, 6 Dec 2020 11:37:11 +0100
@ -647,40 +437,6 @@ index 64193292d26c..d8b673b486c9 100644
};
From 850b62955000677d1a11c4500a68588ea06872fb Mon Sep 17 00:00:00 2001
From: Simon South <simon@simonsouth.net>
Date: Wed, 30 Sep 2020 14:56:27 -0400
Subject: [PATCH] arm64: dts: rockchip: Use only supported PCIe link speed on
Pinebook Pro
On Pinebook Pro laptops with an NVMe SSD installed, prevent random
crashes in the NVMe driver by not attempting to use a PCIe link speed
higher than that supported by the RK3399 SoC.
See commit 712fa1777207 ("arm64: dts: rockchip: add max-link-speed for
rk3399").
Fixes: 5a65505a6988 ("arm64: dts: rockchip: Add initial support for Pinebook Pro")
Signed-off-by: Simon South <simon@simonsouth.net>
Link: https://lore.kernel.org/r/20200930185627.5918-1-simon@simonsouth.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
index 06d48338c836..219b7507a10f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
@@ -790,7 +790,6 @@ &pcie_phy {
&pcie0 {
bus-scan-delay-ms = <1000>;
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
- max-link-speed = <2>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
From 7609f6470180b9342abac469c299ab486c070f8c Mon Sep 17 00:00:00 2001
From: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Date: Mon, 3 Aug 2020 00:42:31 +0900
@ -905,45 +661,3 @@ index 6e553ff47534..58097245994a 100644
status = "okay";
From c4b252da0a7d6281d0d99c27a1c182f769a12652 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Sat, 15 Aug 2020 13:51:12 +0100
Subject: [PATCH] arm64: dts: rockchip: Fix PCIe DT properties on rk3399
It recently became apparent that the lack of a 'device_type = "pci"'
in the PCIe root complex node for rk3399 is a violation of the PCI
binding, as documented in IEEE Std 1275-1994. Changes to the kernel's
parsing of the DT made such violation fatal, as drivers cannot
probe the controller anymore.
Add the missing property makes the PCIe node compliant. While we
are at it, drop the pointless linux,pci-domain property, which only
makes sense when there are multiple host bridges.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200815125112.462652-3-maz@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index cd9fbd3cfcaf..a855805649ef 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -234,6 +234,7 @@ pcie0: pcie@f8000000 {
reg = <0x0 0xf8000000 0x0 0x2000000>,
<0x0 0xfd000000 0x0 0x1000000>;
reg-names = "axi-base", "apb-base";
+ device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -252,7 +253,6 @@ pcie0: pcie@f8000000 {
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
- linux,pci-domain = <0>;
max-link-speed = <1>;
msi-map = <0x0 &its 0x0 0x1000>;
phys = <&pcie_phy 0>, <&pcie_phy 1>,

82
projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch
View File

@ -464,85 +464,3 @@ index da7099d20bd5..5686ad4aaf7c 100644
int lima_devfreq_init(struct lima_device *ldev)
From d763174f11ce320a8ac8a583bfc0cc7268fe7289 Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Tue, 22 Sep 2020 15:16:49 +0100
Subject: [PATCH] drm/panfrost: Support cache-coherent integrations
When the GPU's ACE-Lite interface is fully wired up and capable of
snooping CPU caches, it may be described as "dma-coherent" in
devicetree, which will already inform the DMA layer not to perform
unnecessary cache maintenance. However, we still need to ensure that
the GPU uses the appropriate cacheable outer-shareable attributes in
order to generate the requisite snoop signals, and that CPU mappings
don't create a mismatch by using a non-cacheable type either.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7024ce18c1cb1a226e918037d49175571db0b436.1600780574.git.robin.murphy@arm.com
---
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
drivers/gpu/drm/panfrost/panfrost_drv.c | 2 ++
drivers/gpu/drm/panfrost/panfrost_gem.c | 2 ++
drivers/gpu/drm/panfrost/panfrost_mmu.c | 1 +
4 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index 67f9f66904be..597cf1459b0a 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -88,6 +88,7 @@ struct panfrost_device {
/* pm_domains for devices with more than one. */
struct device *pm_domain_devs[MAX_PM_DOMAINS];
struct device_link *pm_domain_links[MAX_PM_DOMAINS];
+ bool coherent;
struct panfrost_features features;
const struct panfrost_compatible *comp;
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 0fc084110e5b..689be734ed20 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -587,6 +587,8 @@ static int panfrost_probe(struct platform_device *pdev)
if (!pfdev->comp)
return -ENODEV;
+ pfdev->coherent = device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT;
+
/* Allocate and initialze the DRM device. */
ddev = drm_dev_alloc(&panfrost_drm_driver, &pdev->dev);
if (IS_ERR(ddev))
diff --git a/drivers/gpu/drm/panfrost/panfrost_gem.c b/drivers/gpu/drm/panfrost/panfrost_gem.c
index 62d4d710a571..57a31dd0ffed 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gem.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gem.c
@@ -218,6 +218,7 @@ static const struct drm_gem_object_funcs panfrost_gem_funcs = {
*/
struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t size)
{
+ struct panfrost_device *pfdev = dev->dev_private;
struct panfrost_gem_object *obj;
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
@@ -227,6 +228,7 @@ struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t
INIT_LIST_HEAD(&obj->mappings.list);
mutex_init(&obj->mappings.lock);
obj->base.base.funcs = &panfrost_gem_funcs;
+ obj->base.map_cached = pfdev->coherent;
return &obj->base.base;
}
diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c
index 776448c527ea..be8d68fb0e11 100644
--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c
@@ -371,6 +371,7 @@ int panfrost_mmu_pgtable_alloc(struct panfrost_file_priv *priv)
.pgsize_bitmap = SZ_4K | SZ_2M,
.ias = FIELD_GET(0xff, pfdev->features.mmu_features),
.oas = FIELD_GET(0xff00, pfdev->features.mmu_features),
+ .coherent_walk = pfdev->coherent,
.tlb = &mmu_tlb_ops,
.iommu_dev = pfdev->dev,
};