From f6306fd2f929b7ca406069a25582ca6beead68e6 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 6 Jul 2019 12:24:09 +0200 Subject: [PATCH] Allwinner: Add fixes for color range and regulators --- .../linux/0013-color-range-encoding.patch | 417 ++++++++++++++++++ .../patches/linux/0014-regulator-fixes.patch | 75 ++++ 2 files changed, 492 insertions(+) create mode 100644 projects/Allwinner/patches/linux/0013-color-range-encoding.patch create mode 100644 projects/Allwinner/patches/linux/0014-regulator-fixes.patch diff --git a/projects/Allwinner/patches/linux/0013-color-range-encoding.patch b/projects/Allwinner/patches/linux/0013-color-range-encoding.patch new file mode 100644 index 0000000000..e7c1ffc619 --- /dev/null +++ b/projects/Allwinner/patches/linux/0013-color-range-encoding.patch @@ -0,0 +1,417 @@ +From fc81bf6b49bea503653e5cdba5392ffd878c1453 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 27 Jun 2019 19:30:44 +0200 +Subject: [PATCH 1/4] drm/sun4i: Introduce color encoding and range properties + +In order to correctly convert YUV color space to RGB, we have to know +color encoding and range. + +Introduce these two properties using helper method. + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index bd0e6a52d1d8..240a800217df 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -441,6 +441,7 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + struct sun8i_mixer *mixer, + int index) + { ++ u32 supported_encodings, supported_ranges; + struct sun8i_vi_layer *layer; + unsigned int plane_cnt; + int ret; +@@ -469,6 +470,22 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + return ERR_PTR(ret); + } + ++ supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) | ++ BIT(DRM_COLOR_YCBCR_BT709); ++ ++ supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | ++ BIT(DRM_COLOR_YCBCR_FULL_RANGE); ++ ++ ret = drm_plane_create_color_properties(&layer->plane, ++ supported_encodings, ++ supported_ranges, ++ DRM_COLOR_YCBCR_BT709, ++ DRM_COLOR_YCBCR_LIMITED_RANGE); ++ if (ret) { ++ dev_err(drm->dev, "Couldn't add encoding and range properties!\n"); ++ return ERR_PTR(ret); ++ } ++ + drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs); + layer->mixer = mixer; + layer->channel = index; +-- +2.22.0 + + +From 0067d439358510393ac42d454a2c9efee2546cd9 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 27 Jun 2019 19:33:54 +0200 +Subject: [PATCH 2/4] drm/sun4i: sun8i_csc: Simplify register writes + +It turns out addition of 0x200 to constant parts (+0.5) is not really +necessary. Besides, we can consider that before and fix value in CSC +matrix. + +This simplifies register writes quiet a bit. + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index b8c059f1a118..e07b7876d89b 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -69,7 +69,7 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, + enum sun8i_csc_mode mode) + { + const u32 *table; +- int i, data; ++ u32 base_reg; + + switch (mode) { + case SUN8I_CSC_MODE_YUV2RGB: +@@ -83,13 +83,8 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, + return; + } + +- for (i = 0; i < 12; i++) { +- data = table[i]; +- /* For some reason, 0x200 must be added to constant parts */ +- if (((i + 1) & 3) == 0) +- data += 0x200; +- regmap_write(map, SUN8I_CSC_COEFF(base, i), data); +- } ++ base_reg = SUN8I_CSC_COEFF(base, 0); ++ regmap_bulk_write(map, base_reg, table, 12); + } + + static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, +-- +2.22.0 + + +From b0533429bd778930fa71683f9f8b241895b9e239 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 27 Jun 2019 19:21:16 +0200 +Subject: [PATCH 3/4] drm/sun4i: sun8i-csc: Add support for color encoding and + range + +Conversion from YUV to RGB depends on range (limited or full) and +encoding (BT.601 or BT.709). Current code doesn't consider this and +always uses BT.601 encoding and limited range. + +Fix this by introducing new CSC matrices, which are selected based on +range and encoding parameters. + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 144 ++++++++++++++++++++----- + drivers/gpu/drm/sun4i/sun8i_csc.h | 6 +- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 4 +- + 3 files changed, 126 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index e07b7876d89b..70c792d052fe 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -18,16 +18,59 @@ static const u32 ccsc_base[2][2] = { + * First tree values in each line are multiplication factor and last + * value is constant, which is added at the end. + */ +-static const u32 yuv2rgb[] = { +- 0x000004A8, 0x00000000, 0x00000662, 0xFFFC845A, +- 0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021DF4, +- 0x000004A8, 0x00000813, 0x00000000, 0xFFFBAC4A, ++ ++static const u32 yuv2rgb[2][2][12] = { ++ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x000004A8, 0x00000000, 0x00000662, 0xFFFC8451, ++ 0x000004A8, 0xFFFFFE6F, 0xFFFFFCC0, 0x00021E4D, ++ 0x000004A8, 0x00000811, 0x00000000, 0xFFFBACA9, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x000004A8, 0x00000000, 0x0000072B, 0xFFFC1F99, ++ 0x000004A8, 0xFFFFFF26, 0xFFFFFDDF, 0x00013383, ++ 0x000004A8, 0x00000873, 0x00000000, 0xFFFB7BEF, ++ } ++ }, ++ [DRM_COLOR_YCBCR_FULL_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x00000400, 0x00000000, 0x0000059B, 0xFFFD322E, ++ 0x00000400, 0xFFFFFEA0, 0xFFFFFD25, 0x00021DD5, ++ 0x00000400, 0x00000716, 0x00000000, 0xFFFC74BD, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00000400, 0x00000000, 0x0000064C, 0xFFFCD9B4, ++ 0x00000400, 0xFFFFFF41, 0xFFFFFE21, 0x00014F96, ++ 0x00000400, 0x0000076C, 0x00000000, 0xFFFC49EF, ++ } ++ }, + }; + +-static const u32 yvu2rgb[] = { +- 0x000004A8, 0x00000662, 0x00000000, 0xFFFC845A, +- 0x000004A8, 0xFFFFFCBF, 0xFFFFFE6F, 0x00021DF4, +- 0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A, ++static const u32 yvu2rgb[2][2][12] = { ++ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451, ++ 0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D, ++ 0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99, ++ 0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383, ++ 0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF, ++ } ++ }, ++ [DRM_COLOR_YCBCR_FULL_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E, ++ 0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5, ++ 0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4, ++ 0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96, ++ 0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF, ++ } ++ }, + }; + + /* +@@ -53,30 +96,74 @@ static const u32 yvu2rgb[] = { + * c20 c21 c22 [d2 const2] + */ + +-static const u32 yuv2rgb_de3[] = { +- 0x0002542a, 0x00000000, 0x0003312a, 0xffc00000, +- 0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000, +- 0x0002542a, 0x000408d3, 0x00000000, 0xfe000000, ++static const u32 yuv2rgb_de3[2][2][12] = { ++ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000, ++ 0x0002542A, 0xFFFF376B, 0xFFFE5FC3, 0xFE000000, ++ 0x0002542A, 0x000408D2, 0x00000000, 0xFE000000, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000, ++ 0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000, ++ 0x0002542A, 0x0004398C, 0x00000000, 0xFE000000, ++ } ++ }, ++ [DRM_COLOR_YCBCR_FULL_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x00020000, 0x00000000, 0x0002CDD2, 0x00000000, ++ 0x00020000, 0xFFFF4FCE, 0xFFFE925D, 0xFE000000, ++ 0x00020000, 0x00038B43, 0x00000000, 0xFE000000, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00020000, 0x00000000, 0x0003264C, 0x00000000, ++ 0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000, ++ 0x00020000, 0x0003B611, 0x00000000, 0xFE000000, ++ } ++ }, + }; + +-static const u32 yvu2rgb_de3[] = { +- 0x0002542a, 0x0003312a, 0x00000000, 0xffc00000, +- 0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000, +- 0x0002542a, 0x00000000, 0x000408d3, 0xfe000000, ++static const u32 yvu2rgb_de3[2][2][12] = { ++ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000, ++ 0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000, ++ 0x0002542A, 0x00000000, 0x000408D2, 0xFE000000, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000, ++ 0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000, ++ 0x0002542A, 0x00000000, 0x0004398C, 0xFE000000, ++ } ++ }, ++ [DRM_COLOR_YCBCR_FULL_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x00020000, 0x0002CDD2, 0x00000000, 0x00000000, ++ 0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000, ++ 0x00020000, 0x00000000, 0x00038B43, 0xFE000000, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00020000, 0x0003264C, 0x00000000, 0x00000000, ++ 0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000, ++ 0x00020000, 0x00000000, 0x0003B611, 0xFE000000, ++ } ++ }, + }; + + static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, +- enum sun8i_csc_mode mode) ++ enum sun8i_csc_mode mode, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range) + { + const u32 *table; + u32 base_reg; + + switch (mode) { + case SUN8I_CSC_MODE_YUV2RGB: +- table = yuv2rgb; ++ table = yuv2rgb[range][encoding]; + break; + case SUN8I_CSC_MODE_YVU2RGB: +- table = yvu2rgb; ++ table = yvu2rgb[range][encoding]; + break; + default: + DRM_WARN("Wrong CSC mode specified.\n"); +@@ -88,17 +175,19 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, + } + + static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, +- enum sun8i_csc_mode mode) ++ enum sun8i_csc_mode mode, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range) + { + const u32 *table; + u32 base_reg; + + switch (mode) { + case SUN8I_CSC_MODE_YUV2RGB: +- table = yuv2rgb_de3; ++ table = yuv2rgb_de3[range][encoding]; + break; + case SUN8I_CSC_MODE_YVU2RGB: +- table = yvu2rgb_de3; ++ table = yvu2rgb_de3[range][encoding]; + break; + default: + DRM_WARN("Wrong CSC mode specified.\n"); +@@ -137,19 +226,22 @@ static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) + } + + void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, +- enum sun8i_csc_mode mode) ++ enum sun8i_csc_mode mode, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range) + { + u32 base; + + if (mixer->cfg->is_de3) { +- sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, +- layer, mode); ++ sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, ++ mode, encoding, range); + return; + } + + base = ccsc_base[mixer->cfg->ccsc][layer]; + +- sun8i_csc_set_coefficients(mixer->engine.regs, base, mode); ++ sun8i_csc_set_coefficients(mixer->engine.regs, base, ++ mode, encoding, range); + } + + void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h +index dce4c444bcd6..f42441b1b14d 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.h ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.h +@@ -6,6 +6,8 @@ + #ifndef _SUN8I_CSC_H_ + #define _SUN8I_CSC_H_ + ++#include ++ + struct sun8i_mixer; + + /* VI channel CSC units offsets */ +@@ -26,7 +28,9 @@ enum sun8i_csc_mode { + }; + + void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, +- enum sun8i_csc_mode mode); ++ enum sun8i_csc_mode mode, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range); + void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable); + + #endif +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index 240a800217df..011924a75263 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -232,7 +232,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); + + if (fmt_info->csc != SUN8I_CSC_MODE_OFF) { +- sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc); ++ sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc, ++ state->color_encoding, ++ state->color_range); + sun8i_csc_enable_ccsc(mixer, channel, true); + } else { + sun8i_csc_enable_ccsc(mixer, channel, false); +-- +2.22.0 + + +From c8217462c6c143a9fada595bf3e34af83eb15f87 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 27 Jun 2019 21:50:16 +0200 +Subject: [PATCH 4/4] HACK: Force full range + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index 70c792d052fe..7b60fce1a8c6 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -160,10 +160,10 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, + + switch (mode) { + case SUN8I_CSC_MODE_YUV2RGB: +- table = yuv2rgb[range][encoding]; ++ table = yuv2rgb[DRM_COLOR_YCBCR_FULL_RANGE][encoding]; + break; + case SUN8I_CSC_MODE_YVU2RGB: +- table = yvu2rgb[range][encoding]; ++ table = yvu2rgb[DRM_COLOR_YCBCR_FULL_RANGE][encoding]; + break; + default: + DRM_WARN("Wrong CSC mode specified.\n"); +@@ -184,10 +184,10 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, + + switch (mode) { + case SUN8I_CSC_MODE_YUV2RGB: +- table = yuv2rgb_de3[range][encoding]; ++ table = yuv2rgb_de3[DRM_COLOR_YCBCR_FULL_RANGE][encoding]; + break; + case SUN8I_CSC_MODE_YVU2RGB: +- table = yvu2rgb_de3[range][encoding]; ++ table = yvu2rgb_de3[DRM_COLOR_YCBCR_FULL_RANGE][encoding]; + break; + default: + DRM_WARN("Wrong CSC mode specified.\n"); +-- +2.22.0 + diff --git a/projects/Allwinner/patches/linux/0014-regulator-fixes.patch b/projects/Allwinner/patches/linux/0014-regulator-fixes.patch new file mode 100644 index 0000000000..c52f646630 --- /dev/null +++ b/projects/Allwinner/patches/linux/0014-regulator-fixes.patch @@ -0,0 +1,75 @@ +From 95b579d069348a59d0fa6463a2f821089876ebfd Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 6 Jul 2019 11:07:49 +0200 +Subject: [PATCH 1/2] regulator: axp20x: fix DCDCA and DCDCD for AXP806 + +Refactoring of the driver introduced few bugs in AXP806's DCDCA and +DCDCD regulator definitions. + +Fix them. + +Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") +Signed-off-by: Jernej Skrabec +--- + drivers/regulator/axp20x-regulator.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c +index 152053361862..c951568994a1 100644 +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -240,7 +240,7 @@ + #define AXP806_DCDCA_600mV_END \ + (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS) + #define AXP806_DCDCA_1120mV_START 0x33 +-#define AXP806_DCDCA_1120mV_STEPS 14 ++#define AXP806_DCDCA_1120mV_STEPS 20 + #define AXP806_DCDCA_1120mV_END \ + (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS) + #define AXP806_DCDCA_NUM_VOLTAGES 72 +@@ -774,8 +774,8 @@ static const struct regulator_linear_range axp806_dcdcd_ranges[] = { + AXP806_DCDCD_600mV_END, + 20000), + REGULATOR_LINEAR_RANGE(1600000, +- AXP806_DCDCD_600mV_START, +- AXP806_DCDCD_600mV_END, ++ AXP806_DCDCD_1600mV_START, ++ AXP806_DCDCD_1600mV_END, + 100000), + }; + +-- +2.22.0 + +From a8e790b1850f368daff2d3c35b52f8a69978be6e Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 6 Jul 2019 11:15:13 +0200 +Subject: [PATCH 2/2] regulator: axp20x: fix DCDC6 for AXP803 + +Refactoring of axp20x driver introduced a bug in AXP803's DCDC6 +regulator definition. + +Fix it. + +Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") +Signed-off-by: Jernej Skrabec +--- + drivers/regulator/axp20x-regulator.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c +index c951568994a1..29b92ce521b7 100644 +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -181,7 +181,7 @@ + #define AXP803_DCDC6_600mV_END \ + (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS) + #define AXP803_DCDC6_1120mV_START 0x33 +-#define AXP803_DCDC6_1120mV_STEPS 14 ++#define AXP803_DCDC6_1120mV_STEPS 20 + #define AXP803_DCDC6_1120mV_END \ + (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS) + #define AXP803_DCDC6_NUM_VOLTAGES 72 +-- +2.22.0 +