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linux (Rockchip): 5.10.51 upstreamed rk3328 usb3
Full patch remove: - arm64: dts: rockchip: add rk3328 usb3 and usb3phy nodes - partially included in 5.10.51
This commit is contained in:
heitbaum
parent
e23a4927ba
commit
f775bd5fb3
@ -1067,147 +1067,6 @@ index 000000000000..7007ddbcbdae
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+MODULE_DESCRIPTION("DesignWare USB3 Rockchip Innosilicon Glue Layer");
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+MODULE_AUTHOR("Peter Geis <pgwipeout@gmail.com>");
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Mon, 16 Nov 2020 15:17:35 +0000
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Subject: [PATCH] arm64: dts: rockchip: add rk3328 usb3 and usb3phy nodes
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Add the usb3 controller and usb3 phy nodes to the rk3328.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3328.dtsi | 65 ++++++++++++++++++++++++
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1 file changed, 65 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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index 17709faf651b..d327fd300116 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -856,6 +856,40 @@ u2phy_host: host-port {
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};
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};
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+ usb3phy: usb3-phy@ff470000 {
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+ compatible = "rockchip,rk3328-usb3phy";
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+ reg = <0x0 0xff460000 0x0 0x10000>;
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+ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
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+ clock-names = "usb3phy-otg", "usb3phy-pipe";
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+ resets = <&cru SRST_USB3PHY_U2>,
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+ <&cru SRST_USB3PHY_U3>,
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+ <&cru SRST_USB3PHY_PIPE>,
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+ <&cru SRST_USB3OTG_UTMI>,
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+ <&cru SRST_USB3PHY_OTG_P>,
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+ <&cru SRST_USB3PHY_PIPE_P>;
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+ reset-names = "usb3phy-u2-por", "usb3phy-u3-por",
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+ "usb3phy-pipe-mac", "usb3phy-utmi-mac",
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+ "usb3phy-utmi-apb", "usb3phy-pipe-apb";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ usb3phy_utmi: utmi@ff470000 {
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+ compatible = "rockchip,rk3328-usb3phy-utmi";
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+ reg = <0x0 0xff470000 0x0 0x8000>;
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ usb3phy_pipe: pipe@ff478000 {
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+ compatible = "rockchip,rk3328-usb3phy-pipe";
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+ reg = <0x0 0xff478000 0x0 0x8000>;
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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sdmmc: mmc@ff500000 {
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compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff500000 0x0 0x4000>;
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@@ -987,6 +1021,37 @@ usb_host0_ohci: usb@ff5d0000 {
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status = "disabled";
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};
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+ usbdrd3: usb@ff600000 {
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+ compatible = "rockchip,rk3328-dwc3";
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+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
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+ <&cru SCLK_USB3OTG_SUSPEND>;
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+ clock-names = "ref", "bus_early", "suspend";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ usbdrd_dwc3: dwc3@ff600000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0xff600000 0x0 0x100000>;
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+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
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+ <&cru SCLK_USB3OTG_SUSPEND>;
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+ clock-names = "ref", "bus_early", "suspend";
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+ dr_mode = "host";
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+ usb-phy = <&usb3phy_utmi>, <&usb3phy_pipe>;
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis_u2_susphy_quirk;
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+ snps,dis_u3_susphy_quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ snps,xhci-trb-ent-quirk;
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+ status = "disabled";
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+ };
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+ };
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+
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gic: interrupt-controller@ff811000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Mon, 16 Nov 2020 15:17:36 +0000
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Subject: [PATCH] arm64: dts: rockchip: enable usb3 on rk3328-roc-cc board
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Enable the usb3 controller and usb3 phy nodes on the rk3328-roc-cc board file.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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.../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 21 +++++++++++++++++++
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1 file changed, 21 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
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index 19959bfba451..3ac876c08d61 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
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@@ -366,6 +366,27 @@ &usb_host0_ohci {
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status = "okay";
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};
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+&usbdrd3 {
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+ status = "okay";
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+};
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+
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+&usbdrd_dwc3 {
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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+&usb3phy {
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+ status = "okay";
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+};
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+
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+&usb3phy_utmi {
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+ status = "okay";
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+};
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+
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+&usb3phy_pipe {
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+ status = "okay";
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+};
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+
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&vop {
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status = "okay";
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};
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 17 Feb 2019 22:14:38 +0000
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@ -1,79 +1,3 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Sat, 16 Jan 2021 12:24:58 +0000
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Subject: [PATCH] arm64: dts: rockchip: enable USB3 for supported RK3328 boards
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 21 +++++++++++++++++++
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.../arm64/boot/dts/rockchip/rk3328-rock64.dts | 21 +++++++++++++++++++
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2 files changed, 42 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
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index 37f307cfa4cc..4013f16bb368 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
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@@ -352,6 +352,27 @@ &usb_host0_ehci {
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status = "okay";
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};
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+&usbdrd3 {
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+ status = "okay";
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+};
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+
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+&usbdrd_dwc3 {
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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+&usb3phy {
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+ status = "okay";
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+};
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+
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+&usb3phy_utmi {
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+ status = "okay";
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+};
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+
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+&usb3phy_pipe {
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+ status = "okay";
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+};
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+
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&vop {
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status = "okay";
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};
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
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index c984662043da..89fde87f7650 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
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@@ -384,6 +384,27 @@ &usb_host0_ohci {
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status = "okay";
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};
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+&usbdrd3 {
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+ status = "okay";
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+};
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+
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+&usbdrd_dwc3 {
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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+&usb3phy {
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+ status = "okay";
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+};
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+
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+&usb3phy_utmi {
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+ status = "okay";
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+};
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+
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+&usb3phy_pipe {
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+ status = "okay";
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+};
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+
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&vop {
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status = "okay";
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};
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Wed, 2 Sep 2020 19:52:02 +0200
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