From f9eb43495147dd71c255823c5641f17d9be507fb Mon Sep 17 00:00:00 2001 From: MilhouseVH Date: Thu, 13 Oct 2016 01:20:28 +0100 Subject: [PATCH] drm/i915: Fixes and diagnostics for Braswell --- ...5-fixes-and-diagnostics-for-braswell.patch | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 packages/linux/patches/4.8.1/linux-999-i915-fixes-and-diagnostics-for-braswell.patch diff --git a/packages/linux/patches/4.8.1/linux-999-i915-fixes-and-diagnostics-for-braswell.patch b/packages/linux/patches/4.8.1/linux-999-i915-fixes-and-diagnostics-for-braswell.patch new file mode 100644 index 0000000000..f07daafe09 --- /dev/null +++ b/packages/linux/patches/4.8.1/linux-999-i915-fixes-and-diagnostics-for-braswell.patch @@ -0,0 +1,113 @@ +From 0db9810b18ffc46709ad00831c426712d5489aea Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Sat, 13 Aug 2016 21:32:17 +0100 +Subject: [PATCH 1/2] drm/i915: Show RPS autotuning thresholds along waitboost + +--- + drivers/gpu/drm/i915/i915_debugfs.c | 62 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 62 insertions(+) + +diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c +index 1035468..2cff44a 100644 +--- a/drivers/gpu/drm/i915/i915_debugfs.c ++++ b/drivers/gpu/drm/i915/i915_debugfs.c +@@ -2434,6 +2434,68 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) + spin_unlock(&dev_priv->rps.client_lock); + mutex_unlock(&dev->filelist_mutex); + ++ if (INTEL_INFO(dev)->gen >= 6) { ++ u32 rpmodectl, rpinclimit, rpdeclimit; ++ u32 rpstat, cagf; ++ u32 rpupei, rpcurup, rpprevup; ++ u32 rpdownei, rpcurdown, rpprevdown; ++ ++ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); ++ ++ rpmodectl = I915_READ(GEN6_RP_CONTROL); ++ rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); ++ rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); ++ ++ rpstat = I915_READ(GEN6_RPSTAT1); ++ rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; ++ rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; ++ rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; ++ rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; ++ rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; ++ rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; ++ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); ++ ++ if (IS_GEN9(dev)) ++ cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; ++ else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ++ cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; ++ else ++ cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; ++ cagf = intel_gpu_freq(dev_priv, cagf); ++ ++ ++ seq_printf(m, "RP CUR UP EI: %d (%dus)\n", ++ rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); ++ seq_printf(m, "RP CUR UP: %d (%dus)\n", ++ rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); ++ seq_printf(m, "RP PREV UP: %d (%dus)\n", ++ rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); ++ seq_printf(m, "Up threshold: %d%%\n", ++ dev_priv->rps.up_threshold); ++ ++ seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", ++ rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); ++ seq_printf(m, "RP CUR DOWN: %d (%dus)\n", ++ rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); ++ seq_printf(m, "RP PREV DOWN: %d (%dus)\n", ++ rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); ++ seq_printf(m, "Down threshold: %d%%\n", ++ dev_priv->rps.down_threshold); ++ ++ seq_printf(m, "Current freq: %d MHz\n", ++ intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); ++ seq_printf(m, "Actual freq: %d MHz\n", cagf); ++ seq_printf(m, "Idle freq: %d MHz\n", ++ intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); ++ seq_printf(m, "Min freq: %d MHz\n", ++ intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); ++ seq_printf(m, "Max freq: %d MHz\n", ++ intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); ++ seq_printf(m, ++ "efficient (RPe) frequency: %d MHz\n", ++ intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); ++ } ++ + return 0; + } + +-- +2.7.4 + + +From d77c081cd5ea0d278b314ee2043556d2bd9aacaf Mon Sep 17 00:00:00 2001 +From: fritsch +Date: Sat, 13 Aug 2016 22:56:37 +0200 +Subject: [PATCH 2/2] drm/i915: intel-pm enable thresholds + +--- + drivers/gpu/drm/i915/intel_pm.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c +index 2863b92..f3aaef2 100644 +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -4511,8 +4511,7 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) + + if (val != dev_priv->rps.cur_freq) { + vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); +- if (!IS_CHERRYVIEW(dev_priv)) +- gen6_set_rps_thresholds(dev_priv, val); ++ gen6_set_rps_thresholds(dev_priv, val); + } + + dev_priv->rps.cur_freq = val; +-- +2.7.4 + +