mirror of
https://github.com/LibreELEC/LibreELEC.tv.git
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Merge pull request #5113 from heitbaum/kernel51013
[Allwinner,Generic,Rockchip] linux: Update to 5.10.17
This commit is contained in:
CvH
GitHub
commit
fa79b5d00f
@ -28,8 +28,8 @@ case "${LINUX}" in
|
||||
PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
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;;
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*)
|
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PKG_VERSION="5.10.11"
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PKG_SHA256="02ef2b56b00fc5145701c603a5235e1265772e40d488a936b27ba65fe78e710f"
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PKG_VERSION="5.10.17"
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PKG_SHA256="e84e623ce8bb2446ec026b62eafa3b18480aa6fb6ae9c86cd8f18651324d4814"
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PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz"
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PKG_PATCH_DIRS="default"
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;;
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@ -1,74 +0,0 @@
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From 1f363deec843ed4e75aa11e466f91e9224376c04 Mon Sep 17 00:00:00 2001
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From: Matthias Reichl <hias@horus.com>
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Date: Tue, 5 Jan 2021 09:57:29 +0100
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Subject: [PATCH] media: rc: fix timeout handling after switch to microsecond
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durations
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Commit 528222d853f92 ("media: rc: harmonize infrared durations to
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microseconds") missed to switch some timeout calculations from
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nanoseconds to microseconds. This resulted in spurious key_up+key_down
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events at the last scancode if the rc device uses a long timeout
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(eg 100ms on nuvoton-cir) as the device timeout wasn't properly
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accounted for in the keyup timeout calculation.
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Fix this by applying the proper conversion functions.
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Fixes: 528222d853f92 ("media: rc: harmonize infrared durations to microseconds")
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Signed-off-by: Matthias Reichl <hias@horus.com>
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---
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drivers/media/rc/ir-mce_kbd-decoder.c | 2 +-
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drivers/media/rc/rc-main.c | 4 ++--
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drivers/media/rc/serial_ir.c | 2 +-
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3 files changed, 4 insertions(+), 4 deletions(-)
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diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c
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index be8f2756a444..1524dc0fc566 100644
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--- a/drivers/media/rc/ir-mce_kbd-decoder.c
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+++ b/drivers/media/rc/ir-mce_kbd-decoder.c
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@@ -320,7 +320,7 @@ static int ir_mce_kbd_decode(struct rc_dev *dev, struct ir_raw_event ev)
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data->body);
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spin_lock(&data->keylock);
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if (scancode) {
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- delay = nsecs_to_jiffies(dev->timeout) +
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+ delay = usecs_to_jiffies(dev->timeout) +
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msecs_to_jiffies(100);
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mod_timer(&data->rx_timeout, jiffies + delay);
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} else {
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diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c
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index 29d4d01896ff..1fd62c1dac76 100644
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--- a/drivers/media/rc/rc-main.c
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+++ b/drivers/media/rc/rc-main.c
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@@ -737,7 +737,7 @@ static unsigned int repeat_period(int protocol)
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void rc_repeat(struct rc_dev *dev)
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{
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unsigned long flags;
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- unsigned int timeout = nsecs_to_jiffies(dev->timeout) +
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+ unsigned int timeout = usecs_to_jiffies(dev->timeout) +
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msecs_to_jiffies(repeat_period(dev->last_protocol));
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struct lirc_scancode sc = {
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.scancode = dev->last_scancode, .rc_proto = dev->last_protocol,
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@@ -855,7 +855,7 @@ void rc_keydown(struct rc_dev *dev, enum rc_proto protocol, u64 scancode,
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ir_do_keydown(dev, protocol, scancode, keycode, toggle);
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if (dev->keypressed) {
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- dev->keyup_jiffies = jiffies + nsecs_to_jiffies(dev->timeout) +
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+ dev->keyup_jiffies = jiffies + usecs_to_jiffies(dev->timeout) +
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msecs_to_jiffies(repeat_period(protocol));
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mod_timer(&dev->timer_keyup, dev->keyup_jiffies);
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}
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diff --git a/drivers/media/rc/serial_ir.c b/drivers/media/rc/serial_ir.c
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index 8cc28c92d05d..96ae0294ac10 100644
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--- a/drivers/media/rc/serial_ir.c
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+++ b/drivers/media/rc/serial_ir.c
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@@ -385,7 +385,7 @@ static irqreturn_t serial_ir_irq_handler(int i, void *blah)
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} while (!(sinp(UART_IIR) & UART_IIR_NO_INT)); /* still pending ? */
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mod_timer(&serial_ir.timeout_timer,
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- jiffies + nsecs_to_jiffies(serial_ir.rcdev->timeout));
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+ jiffies + usecs_to_jiffies(serial_ir.rcdev->timeout));
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ir_raw_event_handle(serial_ir.rcdev);
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--
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2.20.1
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@ -1,34 +0,0 @@
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From a42febb1ed2fe7f21833afaa495a7c7e04ba8f80 Mon Sep 17 00:00:00 2001
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From: Matthias Reichl <hias@horus.com>
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Date: Sat, 9 Jan 2021 11:59:18 +0100
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Subject: [PATCH] media: rc: ite-cir: fix min_timeout calculation
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Commit 528222d853f92 ("media: rc: harmonize infrared durations to
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microseconds") missed to switch the min_timeout calculation from ns
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to us. This resulted in a minimum timeout of 1.2 seconds instead of 1.2ms,
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leading to large delays and long key repeats.
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Fix this by applying proper ns->us conversion.
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Fixes: 528222d853f92 ("media: rc: harmonize infrared durations to microseconds")
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Signed-off-by: Matthias Reichl <hias@horus.com>
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---
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drivers/media/rc/ite-cir.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/media/rc/ite-cir.c b/drivers/media/rc/ite-cir.c
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index a905113fef6e..0c6229592e13 100644
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--- a/drivers/media/rc/ite-cir.c
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+++ b/drivers/media/rc/ite-cir.c
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@@ -1551,7 +1551,7 @@ static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id
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rdev->s_rx_carrier_range = ite_set_rx_carrier_range;
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/* FIFO threshold is 17 bytes, so 17 * 8 samples minimum */
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rdev->min_timeout = 17 * 8 * ITE_BAUDRATE_DIVISOR *
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- itdev->params.sample_period;
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+ itdev->params.sample_period / 1000;
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rdev->timeout = IR_DEFAULT_TIMEOUT;
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rdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
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rdev->rx_resolution = ITE_BAUDRATE_DIVISOR *
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--
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2.20.1
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@ -1,6 +1,6 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# Linux/arm64 5.10.0 Kernel Configuration
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# Linux/arm64 5.10.17 Kernel Configuration
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#
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CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025"
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CONFIG_CC_IS_GCC=y
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@ -1,6 +1,6 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# Linux/arm 5.10.0 Kernel Configuration
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# Linux/arm 5.10.17 Kernel Configuration
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#
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CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0"
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CONFIG_CC_IS_GCC=y
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@ -1,33 +0,0 @@
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From 3a9d4fe5b89c783d2162c84db3cabf00c3bca983 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 23 Dec 2020 11:23:40 +0100
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Subject: [PATCH 21/44] media: cedrus: Fix H264 decoding
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During H264 API overhaul subtle bug was introduced Cedrus driver.
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Progressive references have both, top and bottom reference flags set.
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Cedrus reference list expects only bottom reference flag and only when
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interlaced frames are decoded. However, due to a bug in Cedrus check,
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exclusivity is not tested and that flag is set also for progressive
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references. That causes "jumpy" background with many videos.
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Fix that by checking that only bottom reference flag is set in control
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and nothing else.
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Tested-by: Andre Heider <a.heider@gmail.com>
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Fixes: cfc8c3ed533e ("media: cedrus: h264: Properly configure reference field")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
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@@ -203,7 +203,7 @@ static void _cedrus_write_ref_list(struc
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position = cedrus_buf->codec.h264.position;
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sram_array[i] |= position << 1;
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- if (ref_list[i].fields & V4L2_H264_BOTTOM_FIELD_REF)
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+ if (ref_list[i].fields == V4L2_H264_BOTTOM_FIELD_REF)
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sram_array[i] |= BIT(0);
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}
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@ -1,25 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 3 Feb 2021 23:09:31 +0100
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Subject: [PATCH] clk: sunxi-ng: mp: fix parent rate change flag check
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CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
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one. Fix that.
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Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/clk/sunxi-ng/ccu_mp.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/sunxi-ng/ccu_mp.c
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+++ b/drivers/clk/sunxi-ng/ccu_mp.c
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@@ -108,7 +108,7 @@ static unsigned long ccu_mp_round_rate(s
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max_m = cmp->m.max ?: 1 << cmp->m.width;
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max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
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- if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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+ if (!(clk_hw_get_flags(&cmp->common.hw) & CLK_SET_RATE_PARENT)) {
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ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
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rate = *parent_rate / p / m;
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} else {
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@ -1,84 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 3 Feb 2021 23:16:42 +0100
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Subject: [PATCH] drm/sun4i: tcon: set sync polarity for tcon1 channel
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Channel 1 has polarity bits for vsync and hsync signals but driver never
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sets them. It turns out that with pre-HDMI2 controllers seemingly there
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is no issue if polarity is not set. However, with HDMI2 controllers
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(H6) there often comes to de-synchronization due to phase shift. This
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causes flickering screen. It's safe to assume that similar issues might
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happen also with pre-HDMI2 controllers.
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Solve issue with setting vsync and hsync polarity. Note that display
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stacks with tcon top have polarity bits actually in tcon0 polarity
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register.
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Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/gpu/drm/sun4i/sun4i_tcon.c | 24 ++++++++++++++++++++++++
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drivers/gpu/drm/sun4i/sun4i_tcon.h | 5 +++++
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2 files changed, 29 insertions(+)
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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@@ -689,6 +689,29 @@ static void sun4i_tcon1_mode_set(struct
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SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
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SUN4I_TCON1_BASIC5_H_SYNC(hsync));
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+ /* Setup the polarity of sync signals */
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+ if (tcon->quirks->polarity_in_ch0) {
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+ val = 0;
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+
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+ if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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+ val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
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+
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+ if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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+ val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
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+
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+ regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
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+ } else {
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||||
+ val = SUN4I_TCON1_IO_POL_UNKNOWN;
|
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+
|
||||
+ if (mode->flags & DRM_MODE_FLAG_PHSYNC)
|
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+ val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
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+
|
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+ if (mode->flags & DRM_MODE_FLAG_PVSYNC)
|
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+ val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
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+
|
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+ regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
|
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+ }
|
||||
+
|
||||
/* Map output pins to channel 1 */
|
||||
regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_IOMAP_MASK,
|
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@@ -1517,6 +1540,7 @@ static const struct sun4i_tcon_quirks su
|
||||
|
||||
static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
|
||||
.has_channel_1 = true,
|
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+ .polarity_in_ch0 = true,
|
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.set_mux = sun8i_r40_tcon_tv_set_mux,
|
||||
};
|
||||
|
||||
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
|
||||
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
|
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@@ -153,6 +153,10 @@
|
||||
#define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
|
||||
|
||||
#define SUN4I_TCON1_IO_POL_REG 0xf0
|
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+#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26)
|
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+#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25)
|
||||
+#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24)
|
||||
+
|
||||
#define SUN4I_TCON1_IO_TRI_REG 0xf4
|
||||
|
||||
#define SUN4I_TCON_ECC_FIFO_REG 0xf8
|
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@@ -235,6 +239,7 @@ struct sun4i_tcon_quirks {
|
||||
bool needs_de_be_mux; /* sun6i needs mux to select backend */
|
||||
bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
|
||||
bool supports_lvds; /* Does the TCON support an LVDS output? */
|
||||
+ bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
|
||||
u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
|
||||
|
||||
/* callback to handle tcon muxing options */
|
||||
@ -1,49 +0,0 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Wed, 3 Feb 2021 23:25:13 +0100
|
||||
Subject: [PATCH] drm/sun4i: dw-hdmi: always set clock rate
|
||||
|
||||
As expected, HDMI controller clock should always match pixel clock. In
|
||||
the past, changing HDMI controller rate would seemingly worsen
|
||||
situation. However, that was the result of other bugs which are now
|
||||
fixed.
|
||||
|
||||
Fix that by removing set_rate quirk and always set clock rate.
|
||||
|
||||
Fixes: 40bb9d3147b2 ("drm/sun4i: Add support for H6 DW HDMI controller")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 4 +---
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 -
|
||||
2 files changed, 1 insertion(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
@@ -21,8 +21,7 @@ static void sun8i_dw_hdmi_encoder_mode_s
|
||||
{
|
||||
struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);
|
||||
|
||||
- if (hdmi->quirks->set_rate)
|
||||
- clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
|
||||
+ clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs
|
||||
@@ -295,7 +294,6 @@ static int sun8i_dw_hdmi_remove(struct p
|
||||
|
||||
static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
|
||||
.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
|
||||
- .set_rate = true,
|
||||
};
|
||||
|
||||
static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
|
||||
@@ -179,7 +179,6 @@ struct sun8i_dw_hdmi_quirks {
|
||||
enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data,
|
||||
const struct drm_display_info *info,
|
||||
const struct drm_display_mode *mode);
|
||||
- unsigned int set_rate : 1;
|
||||
unsigned int use_drm_infoframe : 1;
|
||||
};
|
||||
|
||||
@ -1,24 +0,0 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Wed, 3 Feb 2021 23:29:47 +0100
|
||||
Subject: [PATCH] drm/sun4i: Fix H6 HDMI PHY configuration
|
||||
|
||||
cpce value for 594 MHz is set differently in BSP driver. Fix that.
|
||||
|
||||
Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
|
||||
@@ -89,7 +89,7 @@ static const struct dw_hdmi_mpll_config
|
||||
},
|
||||
}, {
|
||||
594000000, {
|
||||
- { 0x1a40, 0x0003 },
|
||||
+ { 0x1a7c, 0x0003 },
|
||||
{ 0x3b4c, 0x0003 },
|
||||
{ 0x5a64, 0x0003 },
|
||||
},
|
||||
@ -1,34 +0,0 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Wed, 3 Feb 2021 23:32:16 +0100
|
||||
Subject: [PATCH] drm/sun4i: dw-hdmi: Fix max. frequency for H6
|
||||
|
||||
It turns out that reasoning for lowering max. supported frequency is
|
||||
wrong. Scrambling works just fine. Several now fixed bugs prevented
|
||||
proper functioning, even with rates lower than 340 MHz. Issues were just
|
||||
more pronounced with higher frequencies.
|
||||
|
||||
Fix that by allowing max. supported frequency in HW and fix the comment.
|
||||
|
||||
Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 6 ++----
|
||||
1 file changed, 2 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
@@ -47,11 +47,9 @@ sun8i_dw_hdmi_mode_valid_h6(struct dw_hd
|
||||
{
|
||||
/*
|
||||
* Controller support maximum of 594 MHz, which correlates to
|
||||
- * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than
|
||||
- * 340 MHz scrambling has to be enabled. Because scrambling is
|
||||
- * not yet implemented, just limit to 340 MHz for now.
|
||||
+ * 4K@60Hz 4:4:4 or RGB.
|
||||
*/
|
||||
- if (mode->clock > 340000)
|
||||
+ if (mode->clock > 594000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
return MODE_OK;
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/x86 5.10.11 Kernel Configuration
|
||||
# Linux/x86 5.10.17 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.2.0 (GCC) 10.2.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.10.11 Kernel Configuration
|
||||
# Linux/arm 5.10.17 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-10.2.0 (GCC) 10.2.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
|
||||
@ -1,59 +0,0 @@
|
||||
From 2cc0bfc9c12784188482a8f3d751d44af45b0d97 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Thu, 14 Jan 2021 10:53:06 +0000
|
||||
Subject: [PATCH] ARM: dts: imx6qdl-sr-som: fix some cubox-i platforms
|
||||
|
||||
The PHY address bit 2 is configured by the LED pin. Attaching a LED
|
||||
to this pin is not sufficient to guarantee this configuration pin is
|
||||
correctly read. This leads to some platforms having their PHY at
|
||||
address 0 and others at address 4.
|
||||
|
||||
If there is no phy-handle specified, the FEC driver will scan the PHY
|
||||
bus for a PHY and use that. Consequently, adding the DT configuration
|
||||
of the PHY and the phy properties to the FEC driver broke some boards.
|
||||
|
||||
Fix this by removing the phy-handle property, and listing two PHY
|
||||
entries for both possible PHY addresses, so that the DT configuration
|
||||
for the PHY can be found by the PHY driver.
|
||||
|
||||
Fixes: 86b08bd5b994 ("ARM: dts: imx6-sr-som: add ethernet PHY configuration")
|
||||
Reported-by: Christoph Mattheis <christoph.mattheis@arcor.de>
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
||||
---
|
||||
arch/arm/boot/dts/imx6qdl-sr-som.dtsi | 12 ++++++++++--
|
||||
1 file changed, 10 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
|
||||
index b06577808ff4e..7e4e5fd0143a1 100644
|
||||
--- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
|
||||
+++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
|
||||
@@ -53,7 +53,6 @@
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
|
||||
- phy-handle = <&phy>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-reset-duration = <2>;
|
||||
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
|
||||
@@ -63,10 +62,19 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
- phy: ethernet-phy@0 {
|
||||
+ /*
|
||||
+ * The PHY can appear at either address 0 or 4 due to the
|
||||
+ * configuration (LED) pin not being pulled sufficiently.
|
||||
+ */
|
||||
+ ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
qca,clk-out-frequency = <125000000>;
|
||||
};
|
||||
+
|
||||
+ ethernet-phy@4 {
|
||||
+ reg = <4>;
|
||||
+ qca,clk-out-frequency = <125000000>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.2.9 Kernel Configuration
|
||||
# Linux/arm64 5.10.17 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.10.11 Kernel Configuration
|
||||
# Linux/arm 5.10.17 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.10.11 Kernel Configuration
|
||||
# Linux/arm64 5.10.17 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.10.11 Kernel Configuration
|
||||
# Linux/arm64 5.10.17 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
||||
@ -1,35 +1,3 @@
|
||||
From b8d11c4d2da11b58b58ce4794a644ea6074680b7 Mon Sep 17 00:00:00 2001
|
||||
From: Sandy Huang <hjc@rock-chips.com>
|
||||
Date: Fri, 8 Jan 2021 12:06:27 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix vopl iommu irq on px30
|
||||
|
||||
The vop-mmu shares the irq with its matched vop but not the vpu.
|
||||
|
||||
Fixes: 7053e06b1422 ("arm64: dts: rockchip: add core dtsi file for PX30 SoCs")
|
||||
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
|
||||
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
|
||||
Link: https://lore.kernel.org/r/20210108110627.3231226-1-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
|
||||
index 2695ea8cda14..64193292d26c 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
|
||||
@@ -1097,7 +1097,7 @@ vopl_out_lvds: endpoint@1 {
|
||||
vopl_mmu: iommu@ff470f00 {
|
||||
compatible = "rockchip,iommu";
|
||||
reg = <0x0 0xff470f00 0x0 0x100>;
|
||||
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "vopl_mmu";
|
||||
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
|
||||
clock-names = "aclk", "iface";
|
||||
|
||||
From b24a3a7acba3235a5ea07101b3e819e9a176280b Mon Sep 17 00:00:00 2001
|
||||
From: Demetris Ierokipides <ierokipides.dem@gmail.com>
|
||||
Date: Fri, 8 Jan 2021 17:10:35 +0200
|
||||
@ -321,184 +289,6 @@ index 68d5a58cfe88..01ea1f170f77 100644
|
||||
};
|
||||
|
||||
|
||||
From 2af85aabe3375b91d0096188d98dbb18e2a0d9d0 Mon Sep 17 00:00:00 2001
|
||||
From: Johan Jonker <jbx6244@gmail.com>
|
||||
Date: Sun, 6 Dec 2020 11:37:10 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add QoS register compatibles for rk3399
|
||||
|
||||
With the conversion of syscon.yaml minItems for compatibles
|
||||
was set to 2. Current Rockchip dtsi files only use "syscon" for
|
||||
QoS registers. Add Rockchip QoS compatibles for rk3399
|
||||
to reduce notifications produced with:
|
||||
|
||||
make ARCH=arm64 dtbs_check
|
||||
DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml
|
||||
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20201206103711.7465-3-jbx6244@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 50 ++++++++++++------------
|
||||
1 file changed, 25 insertions(+), 25 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index f5dee5f447bb..cd9fbd3cfcaf 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -858,127 +858,127 @@ tsadc: tsadc@ff260000 {
|
||||
};
|
||||
|
||||
qos_emmc: qos@ffa58000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa58000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_gmac: qos@ffa5c000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa5c000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_pcie: qos@ffa60080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa60080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_usb_host0: qos@ffa60100 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa60100 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_usb_host1: qos@ffa60180 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa60180 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_usb_otg0: qos@ffa70000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa70000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_usb_otg1: qos@ffa70080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa70080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_sd: qos@ffa74000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa74000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_sdioaudio: qos@ffa76000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa76000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_hdcp: qos@ffa90000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa90000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_iep: qos@ffa98000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffa98000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp0_m0: qos@ffaa0000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffaa0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp0_m1: qos@ffaa0080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffaa0080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp1_m0: qos@ffaa8000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffaa8000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp1_m1: qos@ffaa8080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffaa8080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_rga_r: qos@ffab0000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffab0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_rga_w: qos@ffab0080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffab0080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_video_m0: qos@ffab8000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffab8000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_video_m1_r: qos@ffac0000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffac0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_video_m1_w: qos@ffac0080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffac0080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_vop_big_r: qos@ffac8000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffac8000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_vop_big_w: qos@ffac8080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffac8080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_vop_little: qos@ffad0000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffad0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_perihp: qos@ffad8080 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffad8080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_gpu: qos@ffae0000 {
|
||||
- compatible = "syscon";
|
||||
+ compatible = "rockchip,rk3399-qos", "syscon";
|
||||
reg = <0x0 0xffae0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
|
||||
From 0fefb9cc8fa016a264d66110024916a6b8539cc4 Mon Sep 17 00:00:00 2001
|
||||
From: Johan Jonker <jbx6244@gmail.com>
|
||||
Date: Sun, 6 Dec 2020 11:37:11 +0100
|
||||
@ -647,40 +437,6 @@ index 64193292d26c..d8b673b486c9 100644
|
||||
};
|
||||
|
||||
|
||||
From 850b62955000677d1a11c4500a68588ea06872fb Mon Sep 17 00:00:00 2001
|
||||
From: Simon South <simon@simonsouth.net>
|
||||
Date: Wed, 30 Sep 2020 14:56:27 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Use only supported PCIe link speed on
|
||||
Pinebook Pro
|
||||
|
||||
On Pinebook Pro laptops with an NVMe SSD installed, prevent random
|
||||
crashes in the NVMe driver by not attempting to use a PCIe link speed
|
||||
higher than that supported by the RK3399 SoC.
|
||||
|
||||
See commit 712fa1777207 ("arm64: dts: rockchip: add max-link-speed for
|
||||
rk3399").
|
||||
|
||||
Fixes: 5a65505a6988 ("arm64: dts: rockchip: Add initial support for Pinebook Pro")
|
||||
Signed-off-by: Simon South <simon@simonsouth.net>
|
||||
Link: https://lore.kernel.org/r/20200930185627.5918-1-simon@simonsouth.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
|
||||
index 06d48338c836..219b7507a10f 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
|
||||
@@ -790,7 +790,6 @@ &pcie_phy {
|
||||
&pcie0 {
|
||||
bus-scan-delay-ms = <1000>;
|
||||
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
- max-link-speed = <2>;
|
||||
num-lanes = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqn_cpm>;
|
||||
|
||||
From 7609f6470180b9342abac469c299ab486c070f8c Mon Sep 17 00:00:00 2001
|
||||
From: Katsuhiro Suzuki <katsuhiro@katsuster.net>
|
||||
Date: Mon, 3 Aug 2020 00:42:31 +0900
|
||||
@ -905,45 +661,3 @@ index 6e553ff47534..58097245994a 100644
|
||||
status = "okay";
|
||||
|
||||
|
||||
From c4b252da0a7d6281d0d99c27a1c182f769a12652 Mon Sep 17 00:00:00 2001
|
||||
From: Marc Zyngier <maz@kernel.org>
|
||||
Date: Sat, 15 Aug 2020 13:51:12 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Fix PCIe DT properties on rk3399
|
||||
|
||||
It recently became apparent that the lack of a 'device_type = "pci"'
|
||||
in the PCIe root complex node for rk3399 is a violation of the PCI
|
||||
binding, as documented in IEEE Std 1275-1994. Changes to the kernel's
|
||||
parsing of the DT made such violation fatal, as drivers cannot
|
||||
probe the controller anymore.
|
||||
|
||||
Add the missing property makes the PCIe node compliant. While we
|
||||
are at it, drop the pointless linux,pci-domain property, which only
|
||||
makes sense when there are multiple host bridges.
|
||||
|
||||
Signed-off-by: Marc Zyngier <maz@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20200815125112.462652-3-maz@kernel.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index cd9fbd3cfcaf..a855805649ef 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -234,6 +234,7 @@ pcie0: pcie@f8000000 {
|
||||
reg = <0x0 0xf8000000 0x0 0x2000000>,
|
||||
<0x0 0xfd000000 0x0 0x1000000>;
|
||||
reg-names = "axi-base", "apb-base";
|
||||
+ device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
@@ -252,7 +253,6 @@ pcie0: pcie@f8000000 {
|
||||
<0 0 0 2 &pcie0_intc 1>,
|
||||
<0 0 0 3 &pcie0_intc 2>,
|
||||
<0 0 0 4 &pcie0_intc 3>;
|
||||
- linux,pci-domain = <0>;
|
||||
max-link-speed = <1>;
|
||||
msi-map = <0x0 &its 0x0 0x1000>;
|
||||
phys = <&pcie_phy 0>, <&pcie_phy 1>,
|
||||
|
||||
@ -464,85 +464,3 @@ index da7099d20bd5..5686ad4aaf7c 100644
|
||||
|
||||
int lima_devfreq_init(struct lima_device *ldev)
|
||||
|
||||
From d763174f11ce320a8ac8a583bfc0cc7268fe7289 Mon Sep 17 00:00:00 2001
|
||||
From: Robin Murphy <robin.murphy@arm.com>
|
||||
Date: Tue, 22 Sep 2020 15:16:49 +0100
|
||||
Subject: [PATCH] drm/panfrost: Support cache-coherent integrations
|
||||
|
||||
When the GPU's ACE-Lite interface is fully wired up and capable of
|
||||
snooping CPU caches, it may be described as "dma-coherent" in
|
||||
devicetree, which will already inform the DMA layer not to perform
|
||||
unnecessary cache maintenance. However, we still need to ensure that
|
||||
the GPU uses the appropriate cacheable outer-shareable attributes in
|
||||
order to generate the requisite snoop signals, and that CPU mappings
|
||||
don't create a mismatch by using a non-cacheable type either.
|
||||
|
||||
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
|
||||
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Reviewed-by: Steven Price <steven.price@arm.com>
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/7024ce18c1cb1a226e918037d49175571db0b436.1600780574.git.robin.murphy@arm.com
|
||||
---
|
||||
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
|
||||
drivers/gpu/drm/panfrost/panfrost_drv.c | 2 ++
|
||||
drivers/gpu/drm/panfrost/panfrost_gem.c | 2 ++
|
||||
drivers/gpu/drm/panfrost/panfrost_mmu.c | 1 +
|
||||
4 files changed, 6 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
|
||||
index 67f9f66904be..597cf1459b0a 100644
|
||||
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
|
||||
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
|
||||
@@ -88,6 +88,7 @@ struct panfrost_device {
|
||||
/* pm_domains for devices with more than one. */
|
||||
struct device *pm_domain_devs[MAX_PM_DOMAINS];
|
||||
struct device_link *pm_domain_links[MAX_PM_DOMAINS];
|
||||
+ bool coherent;
|
||||
|
||||
struct panfrost_features features;
|
||||
const struct panfrost_compatible *comp;
|
||||
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
|
||||
index 0fc084110e5b..689be734ed20 100644
|
||||
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
|
||||
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
|
||||
@@ -587,6 +587,8 @@ static int panfrost_probe(struct platform_device *pdev)
|
||||
if (!pfdev->comp)
|
||||
return -ENODEV;
|
||||
|
||||
+ pfdev->coherent = device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT;
|
||||
+
|
||||
/* Allocate and initialze the DRM device. */
|
||||
ddev = drm_dev_alloc(&panfrost_drm_driver, &pdev->dev);
|
||||
if (IS_ERR(ddev))
|
||||
diff --git a/drivers/gpu/drm/panfrost/panfrost_gem.c b/drivers/gpu/drm/panfrost/panfrost_gem.c
|
||||
index 62d4d710a571..57a31dd0ffed 100644
|
||||
--- a/drivers/gpu/drm/panfrost/panfrost_gem.c
|
||||
+++ b/drivers/gpu/drm/panfrost/panfrost_gem.c
|
||||
@@ -218,6 +218,7 @@ static const struct drm_gem_object_funcs panfrost_gem_funcs = {
|
||||
*/
|
||||
struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t size)
|
||||
{
|
||||
+ struct panfrost_device *pfdev = dev->dev_private;
|
||||
struct panfrost_gem_object *obj;
|
||||
|
||||
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
|
||||
@@ -227,6 +228,7 @@ struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t
|
||||
INIT_LIST_HEAD(&obj->mappings.list);
|
||||
mutex_init(&obj->mappings.lock);
|
||||
obj->base.base.funcs = &panfrost_gem_funcs;
|
||||
+ obj->base.map_cached = pfdev->coherent;
|
||||
|
||||
return &obj->base.base;
|
||||
}
|
||||
diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c
|
||||
index 776448c527ea..be8d68fb0e11 100644
|
||||
--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c
|
||||
+++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c
|
||||
@@ -371,6 +371,7 @@ int panfrost_mmu_pgtable_alloc(struct panfrost_file_priv *priv)
|
||||
.pgsize_bitmap = SZ_4K | SZ_2M,
|
||||
.ias = FIELD_GET(0xff, pfdev->features.mmu_features),
|
||||
.oas = FIELD_GET(0xff00, pfdev->features.mmu_features),
|
||||
+ .coherent_walk = pfdev->coherent,
|
||||
.tlb = &mmu_tlb_ops,
|
||||
.iommu_dev = pfdev->dev,
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.7.6 Kernel Configuration
|
||||
# Linux/arm 5.10.17 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
||||
@ -1,46 +0,0 @@
|
||||
From abda70cb93d3882dc22592c7a5179e739e56133b Mon Sep 17 00:00:00 2001
|
||||
From: Tamseel Shams <m.shams@samsung.com>
|
||||
Date: Sun, 5 Jul 2020 03:51:47 +0000
|
||||
Subject: [PATCH 01/25] FROMLIST(v1): serial: samsung: Re-factors UART IRQ
|
||||
resource for various Samsung SoC
|
||||
|
||||
In few older Samsung SoCs like s3c2410, s3c2412
|
||||
and s3c2440, UART IP is having 2 interrupt lines.
|
||||
However, in other SoCs like s3c6400, s5pv210,
|
||||
exynos5433, and exynos4210 UART is having only 1
|
||||
interrupt line. Due to this, "platform_get_irq(platdev, 1)"
|
||||
call in the driver gives the following warning:
|
||||
"IRQ index 1 not found" on recent platforms.
|
||||
|
||||
This patch re-factors the IRQ resources handling for
|
||||
each platform and hence fixing the above warnings seen
|
||||
on some platforms.
|
||||
|
||||
Signed-off-by: Tamseel Shams <m.shams@samsung.com>
|
||||
---
|
||||
drivers/tty/serial/samsung_tty.c | 7 +++++--
|
||||
1 file changed, 5 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
|
||||
index 73f951d65b93..7f05335c3a1e 100644
|
||||
--- a/drivers/tty/serial/samsung_tty.c
|
||||
+++ b/drivers/tty/serial/samsung_tty.c
|
||||
@@ -1885,10 +1885,13 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
|
||||
else {
|
||||
port->irq = ret;
|
||||
ourport->rx_irq = ret;
|
||||
- ourport->tx_irq = ret + 1;
|
||||
+ if (s3c24xx_serial_has_interrupt_mask(port))
|
||||
+ ourport->tx_irq = ret;
|
||||
+ else
|
||||
+ ourport->tx_irq = ret + 1;
|
||||
}
|
||||
|
||||
- ret = platform_get_irq(platdev, 1);
|
||||
+ ret = platform_get_irq_optional(platdev, 1);
|
||||
if (ret > 0)
|
||||
ourport->tx_irq = ret;
|
||||
/*
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@ -1,34 +0,0 @@
|
||||
From b67896608244f63641885f1e186c9f2add9447cc Mon Sep 17 00:00:00 2001
|
||||
From: Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
Date: Fri, 19 Jul 2019 11:27:34 +0200
|
||||
Subject: [PATCH 12/25] MEMEKA: phy: exynos5-usbdrd: Calibrating makes sense
|
||||
only for USB2.0 PHY
|
||||
|
||||
PHY calibration is needed only for USB2.0 (UTMI) PHY, so skip calling
|
||||
calibration code when phy_calibrate() is called for USB3.0 (PIPE3) PHY.
|
||||
|
||||
Fixes: d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800")
|
||||
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/phy/samsung/phy-exynos5-usbdrd.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
|
||||
index e510732afb8b..7f6279fb4f8f 100644
|
||||
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
|
||||
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
|
||||
@@ -714,7 +714,9 @@ static int exynos5_usbdrd_phy_calibrate(struct phy *phy)
|
||||
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
- return exynos5420_usbdrd_phy_calibrate(phy_drd);
|
||||
+ if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
|
||||
+ return exynos5420_usbdrd_phy_calibrate(phy_drd);
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops exynos5_usbdrd_phy_ops = {
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@ -1,83 +0,0 @@
|
||||
From 5e218f158f89780e48be29c11da270ff1f6f968d Mon Sep 17 00:00:00 2001
|
||||
From: Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
Date: Thu, 21 Nov 2019 11:11:45 +0100
|
||||
Subject: [PATCH 13/25] MEMEKA: clk: samsung: exynos5420: Keep top G3D clocks
|
||||
enabled
|
||||
|
||||
All top clocks on G3D path has to be enabled all the time to allow proper
|
||||
G3D power domain operation. This is achieved by adding CRITICAL flag to
|
||||
"mout_sw_aclk_g3d" clock, what keeps this clock and all its parents
|
||||
enabled.
|
||||
|
||||
This fixes following imprecise abort issue observed on Odroid XU3/XU4
|
||||
after enabling Panfrost driver by commit 1a5a85c56402 "ARM: dts: exynos:
|
||||
Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"):
|
||||
|
||||
panfrost 11800000.gpu: clock rate = 400000000
|
||||
panfrost 11800000.gpu: failed to get regulator: -517
|
||||
panfrost 11800000.gpu: regulator init failed -517
|
||||
Power domain G3D disable failed
|
||||
...
|
||||
panfrost 11800000.gpu: clock rate = 400000000
|
||||
8<--- cut here ---
|
||||
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
|
||||
pgd = (ptrval)
|
||||
[00000000] *pgd=00000000
|
||||
Internal error: : 1406 [#1] PREEMPT SMP ARM
|
||||
Modules linked in:
|
||||
CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923
|
||||
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
|
||||
Workqueue: events deferred_probe_work_func
|
||||
PC is at panfrost_gpu_soft_reset+0x94/0x110
|
||||
LR is at ___might_sleep+0x128/0x2dc
|
||||
...
|
||||
[<c05c231c>] (panfrost_gpu_soft_reset) from [<c05c2704>] (panfrost_gpu_init+0x10/0x67c)
|
||||
[<c05c2704>] (panfrost_gpu_init) from [<c05c15d0>] (panfrost_device_init+0x158/0x2cc)
|
||||
[<c05c15d0>] (panfrost_device_init) from [<c05c0cb0>] (panfrost_probe+0x80/0x178)
|
||||
[<c05c0cb0>] (panfrost_probe) from [<c05cfaa0>] (platform_drv_probe+0x48/0x9c)
|
||||
[<c05cfaa0>] (platform_drv_probe) from [<c05cd20c>] (really_probe+0x1c4/0x474)
|
||||
[<c05cd20c>] (really_probe) from [<c05cd694>] (driver_probe_device+0x78/0x1bc)
|
||||
[<c05cd694>] (driver_probe_device) from [<c05cb374>] (bus_for_each_drv+0x74/0xb8)
|
||||
[<c05cb374>] (bus_for_each_drv) from [<c05ccfa8>] (__device_attach+0xd4/0x16c)
|
||||
[<c05ccfa8>] (__device_attach) from [<c05cc110>] (bus_probe_device+0x88/0x90)
|
||||
[<c05cc110>] (bus_probe_device) from [<c05cc634>] (deferred_probe_work_func+0x4c/0xd0)
|
||||
[<c05cc634>] (deferred_probe_work_func) from [<c0149df0>] (process_one_work+0x300/0x864)
|
||||
[<c0149df0>] (process_one_work) from [<c014a3ac>] (worker_thread+0x58/0x5a0)
|
||||
[<c014a3ac>] (worker_thread) from [<c0151174>] (kthread+0x12c/0x160)
|
||||
[<c0151174>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
|
||||
Exception stack(0xee03dfb0 to 0xee03dff8)
|
||||
...
|
||||
Code: e594300c e5933020 e3130c01 1a00000f (ebefff50).
|
||||
---[ end trace badde2b74a65a540 ]---
|
||||
|
||||
In the above case, the Panfrost driver disables G3D clocks after failure
|
||||
of getting the needed regulator and return with -EPROVE_DEFER code. This
|
||||
causes G3D power domain disable failure and then, during second probe
|
||||
an imprecise abort is triggered due to undefined power domain state.
|
||||
|
||||
Fixes: 45f10dabb56b ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path")
|
||||
Fixes: c9f7567aff31 ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU")
|
||||
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
|
||||
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/clk/samsung/clk-exynos5420.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
|
||||
index edb2363c735a..1a5289d81a9f 100644
|
||||
--- a/drivers/clk/samsung/clk-exynos5420.c
|
||||
+++ b/drivers/clk/samsung/clk-exynos5420.c
|
||||
@@ -713,7 +713,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
||||
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
|
||||
SRC_TOP12, 12, 1),
|
||||
MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
|
||||
- CLK_SET_RATE_PARENT, 0),
|
||||
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
|
||||
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
|
||||
SRC_TOP12, 20, 1),
|
||||
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@ -20,15 +20,15 @@ Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
drivers/thermal/of-thermal.c | 17 +++++++++++++++++
|
||||
drivers/thermal/thermal_of.c | 17 +++++++++++++++++
|
||||
drivers/thermal/thermal_core.c | 10 ++++++++--
|
||||
include/linux/thermal.h | 5 +++++
|
||||
3 files changed, 30 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c
|
||||
diff --git a/drivers/thermal/thermal_of.c b/drivers/thermal/thermal_of.c
|
||||
index 874a47d6923f..1549561e28b2 100644
|
||||
--- a/drivers/thermal/of-thermal.c
|
||||
+++ b/drivers/thermal/of-thermal.c
|
||||
--- a/drivers/thermal/thermal_of.c
|
||||
+++ b/drivers/thermal/thermal_of.c
|
||||
@@ -315,6 +315,20 @@ static int of_thermal_get_trip_type(struct thermal_zone_device *tz, int trip,
|
||||
return 0;
|
||||
}
|
||||
@ -71,10 +71,11 @@ diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c
|
||||
index 9a321dc548c8..ef23a33d34b6 100644
|
||||
--- a/drivers/thermal/thermal_core.c
|
||||
+++ b/drivers/thermal/thermal_core.c
|
||||
@@ -410,6 +410,7 @@ static void handle_critical_trips(struct thermal_zone_device *tz,
|
||||
@@ -410,7 +410,8 @@ static void handle_critical_trips(struct thermal_zone_device *tz,
|
||||
static void handle_thermal_trip(struct thermal_zone_device *tz, int trip)
|
||||
{
|
||||
enum thermal_trip_type type;
|
||||
int trip_temp, hyst = 0;
|
||||
+ bool irq_mode = false;
|
||||
|
||||
/* Ignore disabled trip points */
|
||||
@ -113,9 +114,13 @@ index c91b1e344d56..c4ce2b875b73 100644
|
||||
struct thermal_attr *trip_type_attrs;
|
||||
struct thermal_attr *trip_hyst_attrs;
|
||||
+ struct thermal_attr *trip_irq_mode_attrs;
|
||||
enum thermal_device_mode mode;
|
||||
void *devdata;
|
||||
int trips;
|
||||
unsigned long trips_disabled; /* bitmap for disabled trips */
|
||||
diff --git a/drivers/thermal/thermal_core.h b/drivers/thermal/thermal_core.h
|
||||
index c91b1e344d56..c4ce2b875b73 100644
|
||||
--- a/drivers/thermal/thermal_core.h
|
||||
+++ b/drivers/thermal/thermal_core.h
|
||||
@@ -353,6 +355,8 @@ struct thermal_zone_of_device_ops {
|
||||
* @temperature: temperature value in miliCelsius
|
||||
* @hysteresis: relative hysteresis in miliCelsius
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user