diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index f95039f7ac..f7486d5692 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.3.9 Kernel Configuration +# Linux/arm64 5.4.0 Kernel Configuration # # @@ -11,6 +11,7 @@ CONFIG_GCC_VERSION=80300 CONFIG_CLANG_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y @@ -385,6 +386,7 @@ CONFIG_HARDEN_EL2_VECTORS=y CONFIG_ARM64_SSBD=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y # CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_COMPAT=y CONFIG_KUSER_HELPERS=y # CONFIG_ARMV8_DEPRECATED is not set @@ -476,6 +478,7 @@ CONFIG_DT_IDLE_STATES=y # ARM CPU Idle Drivers # CONFIG_ARM_CPUIDLE=y +# CONFIG_ARM_PSCI_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle @@ -504,6 +507,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y CONFIG_ARM_SCPI_CPUFREQ=y # CONFIG_QORIQ_CPUFREQ is not set # end of CPU Frequency scaling @@ -579,6 +583,7 @@ CONFIG_JUMP_LABEL=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y @@ -589,6 +594,7 @@ CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y @@ -623,6 +629,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y @@ -660,6 +667,8 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set # CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -673,6 +682,7 @@ CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_IOCOST is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set @@ -766,6 +776,7 @@ CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_BENCHMARK is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options @@ -1347,6 +1358,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # Bus devices # CONFIG_BRCMSTB_GISB_ARB=y +# CONFIG_MOXTET is not set CONFIG_SIMPLE_PM_BUS=y CONFIG_SUN50I_DE2_BUS=y CONFIG_SUNXI_RSB=y @@ -1357,13 +1369,13 @@ CONFIG_VEXPRESS_CONFIG=y # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_OF_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set # # Partition parsers # +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # end of Partition parsers @@ -1409,7 +1421,6 @@ CONFIG_MTD_CFI_I2=y # Self-contained MTD device drivers # # CONFIG_MTD_DATAFLASH is not set -CONFIG_MTD_M25P80=y # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set @@ -1663,6 +1674,7 @@ CONFIG_DM_THIN_PROVISIONING=m # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set # CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set # CONFIG_DM_MIRROR is not set # CONFIG_DM_RAID is not set # CONFIG_DM_ZERO is not set @@ -1764,6 +1776,7 @@ CONFIG_NET_VENDOR_NI=y # CONFIG_NI_XGE_MANAGEMENT_ENET is not set CONFIG_NET_VENDOR_8390=y # CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PENSANDO is not set CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set @@ -1817,6 +1830,7 @@ CONFIG_SWPHY=y # MII PHY device drivers # # CONFIG_SFP is not set +# CONFIG_ADIN_PHY is not set CONFIG_AC200_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set @@ -2167,7 +2181,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_CMA3000 is not set -# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set # CONFIG_INPUT_DRV2667_HAPTICS is not set @@ -2241,6 +2254,7 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set @@ -2268,6 +2282,7 @@ CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # end of Serial drivers @@ -2292,6 +2307,8 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_XILLYBUS is not set # end of Character devices +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + # # I2C support # @@ -2599,6 +2616,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ASPEED is not set @@ -2687,7 +2705,6 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set @@ -2792,7 +2809,6 @@ CONFIG_MFD_AC200=y CONFIG_MFD_AXP20X=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_AXP20X_RSB=y -# CONFIG_MFD_CROS_EC is not set # CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set @@ -2925,6 +2941,7 @@ CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_S5M8767 is not set # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -2990,6 +3007,7 @@ CONFIG_MEDIA_CONTROLLER_REQUEST_API=y CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m @@ -3176,9 +3194,14 @@ CONFIG_SMS_SIANO_RC=y # Media ancillary drivers (tuners, sensors, i2c, spi, frontends) # CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y CONFIG_MEDIA_ATTACH=y CONFIG_VIDEO_IR_I2C=y +# +# I2C drivers hidden by 'Autoselect ancillary drivers' +# + # # Audio decoders, processors and mixers # @@ -3241,6 +3264,10 @@ CONFIG_VIDEO_MT9V011=m # Miscellaneous helper chips # +# +# SPI drivers hidden by 'Autoselect ancillary drivers' +# + # # Media SPI Adapters # @@ -3248,6 +3275,10 @@ CONFIG_CXD2880_SPI_DRV=m # end of Media SPI Adapters CONFIG_MEDIA_TUNER=y + +# +# Tuner drivers hidden by 'Autoselect ancillary drivers' +# CONFIG_MEDIA_TUNER_SIMPLE=y CONFIG_MEDIA_TUNER_TDA18250=m CONFIG_MEDIA_TUNER_TDA8290=y @@ -3281,6 +3312,10 @@ CONFIG_MEDIA_TUNER_IT913X=m CONFIG_MEDIA_TUNER_R820T=m CONFIG_MEDIA_TUNER_QM1D1C0042=m +# +# DVB Frontend drivers hidden by 'Autoselect ancillary drivers' +# + # # Multistandard (satellite) frontends # @@ -3473,12 +3508,19 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_SIMPLE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # end of Display Panels @@ -3514,7 +3556,14 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set @@ -3802,6 +3851,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set # CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8524 is not set @@ -3869,6 +3919,7 @@ CONFIG_HID_CHICONY=y # CONFIG_HID_MACALLY is not set # CONFIG_HID_PRODIKEYS is not set # CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y CONFIG_HID_DRAGONRISE=m CONFIG_DRAGONRISE_FF=y @@ -3966,6 +4017,9 @@ CONFIG_I2C_HID=m CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +CONFIG_USB_ULPI_BUS=y +# CONFIG_USB_CONN_GPIO is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set @@ -3982,7 +4036,6 @@ CONFIG_USB_OTG=y # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -4044,6 +4097,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -4165,10 +4219,7 @@ CONFIG_USB_BDC_UDC=y # CONFIG_USB_CONFIGFS is not set # CONFIG_TYPEC is not set -# CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_LED_TRIG is not set -CONFIG_USB_ULPI_BUS=y -# CONFIG_UWB is not set +CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y # CONFIG_PWRSEQ_SD8787 is not set @@ -4187,6 +4238,7 @@ CONFIG_MMC_STM32_SDMMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_OF_ASPEED is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set # CONFIG_MMC_SDHCI_OF_DWCMSHC is not set CONFIG_MMC_SDHCI_CADENCE=y @@ -4439,6 +4491,7 @@ CONFIG_DMA_ENGINE_RAID=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -4451,6 +4504,7 @@ CONFIG_SYNC_FILE=y # # end of Microsoft Hyper-V guest support +# CONFIG_GREYBUS is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set @@ -4525,7 +4579,6 @@ CONFIG_RTL8723BS=m # end of Speakup console speech CONFIG_STAGING_MEDIA=y -# CONFIG_I2C_BCM2048 is not set CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y @@ -4548,7 +4601,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_WILC1000_SPI is not set # CONFIG_MOST is not set # CONFIG_KS7010 is not set -# CONFIG_GREYBUS is not set # CONFIG_PI433 is not set # @@ -4557,9 +4609,12 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # end of Gasket devices # CONFIG_XIL_AXIS_FIFO is not set -# CONFIG_EROFS_FS is not set # CONFIG_FIELDBUS_DEV is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_UWB is not set +# CONFIG_EXFAT_FS is not set # CONFIG_GOLDFISH is not set +# CONFIG_MFD_CROS_EC is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_CLKDEV_LOOKUP=y @@ -4747,7 +4802,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set -# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -4963,6 +5017,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # Inertial measurement units # # CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set @@ -4996,6 +5051,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set # CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set @@ -5056,6 +5112,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set # CONFIG_MAX5481 is not set # CONFIG_MAX5487 is not set # CONFIG_MCP4018 is not set @@ -5272,6 +5329,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -5288,6 +5346,7 @@ CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m +# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -5392,6 +5451,7 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" # CONFIG_PSTORE_RAM is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -5507,6 +5567,7 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_SECURITY_LOADPIN is not set # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y @@ -5582,10 +5643,6 @@ CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=m # CONFIG_CRYPTO_CHACHA20POLY1305 is not set # CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS1280 is not set CONFIG_CRYPTO_SEQIV=m CONFIG_CRYPTO_ECHAINIV=y @@ -5603,6 +5660,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -5629,6 +5687,7 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_SHA3=m @@ -5640,6 +5699,7 @@ CONFIG_CRYPTO_SM3=m # # Ciphers # +CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set @@ -5649,6 +5709,7 @@ CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set @@ -5690,6 +5751,7 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set # CONFIG_CRYPTO_DEV_HISI_SEC is not set CONFIG_ASYMMETRIC_KEY_TYPE=y @@ -5778,7 +5840,6 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y -CONFIG_ARCH_HAS_DMA_MMAP_PGPROT=y CONFIG_SWIOTLB=y CONFIG_DMA_REMAP=y CONFIG_DMA_DIRECT_REMAP=y @@ -5803,7 +5864,6 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y -CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y @@ -5847,10 +5907,9 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_INSTALL is not set -# CONFIG_OPTIMIZE_INLINING is not set +CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_ARCH_WANT_FRAME_POINTERS=y diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index e5ab1cda2c..149979edb6 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.3.7 Kernel Configuration +# Linux/arm 5.4.0 Kernel Configuration # # @@ -11,6 +11,7 @@ CONFIG_GCC_VERSION=80300 CONFIG_CLANG_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y @@ -260,19 +261,13 @@ CONFIG_ARCH_MULTIPLATFORM=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_LPC32XX is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C24XX is not set -# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP1 is not set # @@ -291,6 +286,7 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_ARTPEC is not set +# CONFIG_ARCH_ASPEED is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set @@ -514,6 +510,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM is not set # CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set # CONFIG_QORIQ_CPUFREQ is not set # end of CPU Frequency scaling @@ -530,6 +527,7 @@ CONFIG_CPU_IDLE_GOV_MENU=y # ARM CPU Idle Drivers # # CONFIG_ARM_CPUIDLE is not set +# CONFIG_ARM_PSCI_CPUIDLE is not set # CONFIG_ARM_HIGHBANK_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle @@ -638,6 +636,7 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y @@ -674,6 +673,8 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set # CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -687,6 +688,7 @@ CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_IOCOST is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set @@ -1177,6 +1179,7 @@ CONFIG_CAN=y CONFIG_CAN_RAW=y CONFIG_CAN_BCM=y CONFIG_CAN_GW=y +# CONFIG_CAN_J1939 is not set # # CAN Device Drivers @@ -1369,6 +1372,7 @@ CONFIG_ARM_CCI=y CONFIG_ARM_CCI400_COMMON=y CONFIG_ARM_CCI400_PORT_CTRL=y # CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set # CONFIG_SIMPLE_PM_BUS is not set CONFIG_SUN50I_DE2_BUS=y CONFIG_SUNXI_RSB=y @@ -1593,6 +1597,7 @@ CONFIG_DM_THIN_PROVISIONING=m # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set # CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set # CONFIG_DM_MIRROR is not set # CONFIG_DM_RAID is not set # CONFIG_DM_ZERO is not set @@ -1680,6 +1685,7 @@ CONFIG_NET_VENDOR_NETRONOME=y CONFIG_NET_VENDOR_NI=y # CONFIG_NI_XGE_MANAGEMENT_ENET is not set # CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PENSANDO is not set CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set # CONFIG_QCA7000_UART is not set @@ -1725,6 +1731,7 @@ CONFIG_SWPHY=y # MII PHY device drivers # # CONFIG_SFP is not set +# CONFIG_ADIN_PHY is not set # CONFIG_AC200_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set @@ -2097,6 +2104,7 @@ CONFIG_SERIAL_8250_NR_UARTS=8 CONFIG_SERIAL_8250_RUNTIME_UARTS=8 # CONFIG_SERIAL_8250_EXTENDED is not set # CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_EM is not set @@ -2122,6 +2130,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set # end of Serial drivers @@ -2138,6 +2147,8 @@ CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_XILLYBUS is not set # end of Character devices +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + # # I2C support # @@ -2419,6 +2430,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set @@ -2506,7 +2518,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set @@ -2616,7 +2627,6 @@ CONFIG_MFD_SUN4I_GPADC=y CONFIG_MFD_AXP20X=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_AXP20X_RSB=y -# CONFIG_MFD_CROS_EC is not set # CONFIG_MFD_MADERA is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_PMIC_DA903X is not set @@ -2746,6 +2756,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_SLG51000 is not set CONFIG_REGULATOR_SY8106A=y +# CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -2810,6 +2821,7 @@ CONFIG_MEDIA_CONTROLLER_REQUEST_API=y CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m @@ -3058,6 +3070,7 @@ CONFIG_VIDEO_THS8200=m # CONFIG_VIDEO_OV5647 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3423,10 +3436,14 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set # end of Display Panels @@ -3462,7 +3479,14 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set # CONFIG_DRM_TVE200 is not set # CONFIG_DRM_LIMA is not set @@ -3724,6 +3748,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set # CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8524 is not set @@ -3791,6 +3816,7 @@ CONFIG_HID_CHICONY=y # CONFIG_HID_MACALLY is not set # CONFIG_HID_PRODIKEYS is not set # CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y CONFIG_HID_DRAGONRISE=m CONFIG_DRAGONRISE_FF=y @@ -3887,6 +3913,9 @@ CONFIG_USB_HIDDEV=y CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -3902,7 +3931,6 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=m -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -3964,6 +3992,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -4107,9 +4136,6 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # CONFIG_USB_CONFIGFS is not set # CONFIG_TYPEC is not set # CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_UWB is not set CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y # CONFIG_PWRSEQ_SD8787 is not set @@ -4350,6 +4376,7 @@ CONFIG_DMA_SUN6I=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -4362,6 +4389,7 @@ CONFIG_SYNC_FILE=y # # end of Microsoft Hyper-V guest support +# CONFIG_GREYBUS is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set @@ -4458,7 +4486,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_WILC1000_SPI is not set # CONFIG_MOST is not set # CONFIG_KS7010 is not set -# CONFIG_GREYBUS is not set # CONFIG_PI433 is not set # @@ -4467,9 +4494,12 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # end of Gasket devices # CONFIG_XIL_AXIS_FIFO is not set -# CONFIG_EROFS_FS is not set # CONFIG_FIELDBUS_DEV is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_UWB is not set +# CONFIG_EXFAT_FS is not set # CONFIG_GOLDFISH is not set +# CONFIG_MFD_CROS_EC is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_CLKDEV_LOOKUP=y @@ -4636,7 +4666,6 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_DMARD06 is not set # CONFIG_DMARD09 is not set # CONFIG_DMARD10 is not set -# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set @@ -4853,6 +4882,7 @@ CONFIG_SUN4I_GPADC=y # Inertial measurement units # # CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set @@ -4886,6 +4916,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set # CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set @@ -4939,6 +4970,7 @@ CONFIG_SUN4I_GPADC=y # # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set # CONFIG_MAX5481 is not set # CONFIG_MAX5487 is not set # CONFIG_MCP4018 is not set @@ -5151,6 +5183,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -5160,6 +5193,7 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS_FS is not set CONFIG_FUSE_FS=m # CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -5246,6 +5280,7 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_PSTORE is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -5416,10 +5451,6 @@ CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=m # CONFIG_CRYPTO_CHACHA20POLY1305 is not set # CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS1280 is not set CONFIG_CRYPTO_SEQIV=m CONFIG_CRYPTO_ECHAINIV=m @@ -5437,6 +5468,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -5463,6 +5495,7 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=m CONFIG_CRYPTO_SHA256=m # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA3 is not set @@ -5474,6 +5507,7 @@ CONFIG_CRYPTO_SHA256=m # # Ciphers # +CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set @@ -5483,6 +5517,7 @@ CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set @@ -5525,6 +5560,7 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set CONFIG_CRYPTO_DEV_SUN4I_SS=y # CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y @@ -5624,7 +5660,6 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y -# CONFIG_DIMLIB is not set CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_FONT_SUPPORT=y @@ -5660,10 +5695,9 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_INSTALL is not set -# CONFIG_OPTIMIZE_INLINING is not set +CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set diff --git a/projects/Allwinner/patches/linux/0001-backport-from-5.4.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.4.patch deleted file mode 100644 index a8fcbb5908..0000000000 --- a/projects/Allwinner/patches/linux/0001-backport-from-5.4.patch +++ /dev/null @@ -1,6801 +0,0 @@ -From fc81bf6b49bea503653e5cdba5392ffd878c1453 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 27 Jun 2019 19:30:44 +0200 -Subject: [PATCH 1/4] drm/sun4i: Introduce color encoding and range properties - -In order to correctly convert YUV color space to RGB, we have to know -color encoding and range. - -Introduce these two properties using helper method. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -index bd0e6a52d1d8..240a800217df 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -@@ -441,6 +441,7 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, - struct sun8i_mixer *mixer, - int index) - { -+ u32 supported_encodings, supported_ranges; - struct sun8i_vi_layer *layer; - unsigned int plane_cnt; - int ret; -@@ -469,6 +470,22 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, - return ERR_PTR(ret); - } - -+ supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) | -+ BIT(DRM_COLOR_YCBCR_BT709); -+ -+ supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | -+ BIT(DRM_COLOR_YCBCR_FULL_RANGE); -+ -+ ret = drm_plane_create_color_properties(&layer->plane, -+ supported_encodings, -+ supported_ranges, -+ DRM_COLOR_YCBCR_BT709, -+ DRM_COLOR_YCBCR_LIMITED_RANGE); -+ if (ret) { -+ dev_err(drm->dev, "Couldn't add encoding and range properties!\n"); -+ return ERR_PTR(ret); -+ } -+ - drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs); - layer->mixer = mixer; - layer->channel = index; --- -2.22.0 - - -From 0067d439358510393ac42d454a2c9efee2546cd9 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 27 Jun 2019 19:33:54 +0200 -Subject: [PATCH 2/4] drm/sun4i: sun8i_csc: Simplify register writes - -It turns out addition of 0x200 to constant parts (+0.5) is not really -necessary. Besides, we can consider that before and fix value in CSC -matrix. - -This simplifies register writes quiet a bit. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_csc.c | 11 +++-------- - 1 file changed, 3 insertions(+), 8 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c -index b8c059f1a118..e07b7876d89b 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_csc.c -+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c -@@ -69,7 +69,7 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, - enum sun8i_csc_mode mode) - { - const u32 *table; -- int i, data; -+ u32 base_reg; - - switch (mode) { - case SUN8I_CSC_MODE_YUV2RGB: -@@ -83,13 +83,8 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, - return; - } - -- for (i = 0; i < 12; i++) { -- data = table[i]; -- /* For some reason, 0x200 must be added to constant parts */ -- if (((i + 1) & 3) == 0) -- data += 0x200; -- regmap_write(map, SUN8I_CSC_COEFF(base, i), data); -- } -+ base_reg = SUN8I_CSC_COEFF(base, 0); -+ regmap_bulk_write(map, base_reg, table, 12); - } - - static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, --- -2.22.0 - - -From b0533429bd778930fa71683f9f8b241895b9e239 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 27 Jun 2019 19:21:16 +0200 -Subject: [PATCH 3/4] drm/sun4i: sun8i-csc: Add support for color encoding and - range - -Conversion from YUV to RGB depends on range (limited or full) and -encoding (BT.601 or BT.709). Current code doesn't consider this and -always uses BT.601 encoding and limited range. - -Fix this by introducing new CSC matrices, which are selected based on -range and encoding parameters. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_csc.c | 144 ++++++++++++++++++++----- - drivers/gpu/drm/sun4i/sun8i_csc.h | 6 +- - drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 4 +- - 3 files changed, 126 insertions(+), 28 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c -index e07b7876d89b..70c792d052fe 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_csc.c -+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c -@@ -18,16 +18,59 @@ static const u32 ccsc_base[2][2] = { - * First tree values in each line are multiplication factor and last - * value is constant, which is added at the end. - */ --static const u32 yuv2rgb[] = { -- 0x000004A8, 0x00000000, 0x00000662, 0xFFFC845A, -- 0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021DF4, -- 0x000004A8, 0x00000813, 0x00000000, 0xFFFBAC4A, -+ -+static const u32 yuv2rgb[2][2][12] = { -+ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x000004A8, 0x00000000, 0x00000662, 0xFFFC8451, -+ 0x000004A8, 0xFFFFFE6F, 0xFFFFFCC0, 0x00021E4D, -+ 0x000004A8, 0x00000811, 0x00000000, 0xFFFBACA9, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x000004A8, 0x00000000, 0x0000072B, 0xFFFC1F99, -+ 0x000004A8, 0xFFFFFF26, 0xFFFFFDDF, 0x00013383, -+ 0x000004A8, 0x00000873, 0x00000000, 0xFFFB7BEF, -+ } -+ }, -+ [DRM_COLOR_YCBCR_FULL_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x00000400, 0x00000000, 0x0000059B, 0xFFFD322E, -+ 0x00000400, 0xFFFFFEA0, 0xFFFFFD25, 0x00021DD5, -+ 0x00000400, 0x00000716, 0x00000000, 0xFFFC74BD, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x00000400, 0x00000000, 0x0000064C, 0xFFFCD9B4, -+ 0x00000400, 0xFFFFFF41, 0xFFFFFE21, 0x00014F96, -+ 0x00000400, 0x0000076C, 0x00000000, 0xFFFC49EF, -+ } -+ }, - }; - --static const u32 yvu2rgb[] = { -- 0x000004A8, 0x00000662, 0x00000000, 0xFFFC845A, -- 0x000004A8, 0xFFFFFCBF, 0xFFFFFE6F, 0x00021DF4, -- 0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A, -+static const u32 yvu2rgb[2][2][12] = { -+ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451, -+ 0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D, -+ 0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99, -+ 0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383, -+ 0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF, -+ } -+ }, -+ [DRM_COLOR_YCBCR_FULL_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E, -+ 0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5, -+ 0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4, -+ 0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96, -+ 0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF, -+ } -+ }, - }; - - /* -@@ -53,30 +96,74 @@ static const u32 yvu2rgb[] = { - * c20 c21 c22 [d2 const2] - */ - --static const u32 yuv2rgb_de3[] = { -- 0x0002542a, 0x00000000, 0x0003312a, 0xffc00000, -- 0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000, -- 0x0002542a, 0x000408d3, 0x00000000, 0xfe000000, -+static const u32 yuv2rgb_de3[2][2][12] = { -+ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000, -+ 0x0002542A, 0xFFFF376B, 0xFFFE5FC3, 0xFE000000, -+ 0x0002542A, 0x000408D2, 0x00000000, 0xFE000000, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000, -+ 0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000, -+ 0x0002542A, 0x0004398C, 0x00000000, 0xFE000000, -+ } -+ }, -+ [DRM_COLOR_YCBCR_FULL_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x00020000, 0x00000000, 0x0002CDD2, 0x00000000, -+ 0x00020000, 0xFFFF4FCE, 0xFFFE925D, 0xFE000000, -+ 0x00020000, 0x00038B43, 0x00000000, 0xFE000000, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x00020000, 0x00000000, 0x0003264C, 0x00000000, -+ 0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000, -+ 0x00020000, 0x0003B611, 0x00000000, 0xFE000000, -+ } -+ }, - }; - --static const u32 yvu2rgb_de3[] = { -- 0x0002542a, 0x0003312a, 0x00000000, 0xffc00000, -- 0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000, -- 0x0002542a, 0x00000000, 0x000408d3, 0xfe000000, -+static const u32 yvu2rgb_de3[2][2][12] = { -+ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000, -+ 0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000, -+ 0x0002542A, 0x00000000, 0x000408D2, 0xFE000000, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000, -+ 0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000, -+ 0x0002542A, 0x00000000, 0x0004398C, 0xFE000000, -+ } -+ }, -+ [DRM_COLOR_YCBCR_FULL_RANGE] = { -+ [DRM_COLOR_YCBCR_BT601] = { -+ 0x00020000, 0x0002CDD2, 0x00000000, 0x00000000, -+ 0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000, -+ 0x00020000, 0x00000000, 0x00038B43, 0xFE000000, -+ }, -+ [DRM_COLOR_YCBCR_BT709] = { -+ 0x00020000, 0x0003264C, 0x00000000, 0x00000000, -+ 0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000, -+ 0x00020000, 0x00000000, 0x0003B611, 0xFE000000, -+ } -+ }, - }; - - static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, -- enum sun8i_csc_mode mode) -+ enum sun8i_csc_mode mode, -+ enum drm_color_encoding encoding, -+ enum drm_color_range range) - { - const u32 *table; - u32 base_reg; - - switch (mode) { - case SUN8I_CSC_MODE_YUV2RGB: -- table = yuv2rgb; -+ table = yuv2rgb[range][encoding]; - break; - case SUN8I_CSC_MODE_YVU2RGB: -- table = yvu2rgb; -+ table = yvu2rgb[range][encoding]; - break; - default: - DRM_WARN("Wrong CSC mode specified.\n"); -@@ -88,17 +175,19 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, - } - - static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, -- enum sun8i_csc_mode mode) -+ enum sun8i_csc_mode mode, -+ enum drm_color_encoding encoding, -+ enum drm_color_range range) - { - const u32 *table; - u32 base_reg; - - switch (mode) { - case SUN8I_CSC_MODE_YUV2RGB: -- table = yuv2rgb_de3; -+ table = yuv2rgb_de3[range][encoding]; - break; - case SUN8I_CSC_MODE_YVU2RGB: -- table = yvu2rgb_de3; -+ table = yvu2rgb_de3[range][encoding]; - break; - default: - DRM_WARN("Wrong CSC mode specified.\n"); -@@ -137,19 +226,22 @@ static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) - } - - void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, -- enum sun8i_csc_mode mode) -+ enum sun8i_csc_mode mode, -+ enum drm_color_encoding encoding, -+ enum drm_color_range range) - { - u32 base; - - if (mixer->cfg->is_de3) { -- sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, -- layer, mode); -+ sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, -+ mode, encoding, range); - return; - } - - base = ccsc_base[mixer->cfg->ccsc][layer]; - -- sun8i_csc_set_coefficients(mixer->engine.regs, base, mode); -+ sun8i_csc_set_coefficients(mixer->engine.regs, base, -+ mode, encoding, range); - } - - void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) -diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h -index dce4c444bcd6..f42441b1b14d 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_csc.h -+++ b/drivers/gpu/drm/sun4i/sun8i_csc.h -@@ -6,6 +6,8 @@ - #ifndef _SUN8I_CSC_H_ - #define _SUN8I_CSC_H_ - -+#include -+ - struct sun8i_mixer; - - /* VI channel CSC units offsets */ -@@ -26,7 +28,9 @@ enum sun8i_csc_mode { - }; - - void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, -- enum sun8i_csc_mode mode); -+ enum sun8i_csc_mode mode, -+ enum drm_color_encoding encoding, -+ enum drm_color_range range); - void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable); - - #endif -diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -index 240a800217df..011924a75263 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c -@@ -232,7 +232,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, - SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); - - if (fmt_info->csc != SUN8I_CSC_MODE_OFF) { -- sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc); -+ sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc, -+ state->color_encoding, -+ state->color_range); - sun8i_csc_enable_ccsc(mixer, channel, true); - } else { - sun8i_csc_enable_ccsc(mixer, channel, false); --- -2.22.0 - -From: Ondrej Jirman -Subject: [PATCH v8 3/4] drm: sun4i: Add support for enabling DDC I2C bus to - sun8i_dw_hdmi glue -Date: Tue, 6 Aug 2019 17:57:42 +0200 -Content-Type: text/plain; charset="us-ascii" - -Orange Pi 3 board requires enabling a voltage shifting circuit via GPIO -for the DDC bus to be usable. - -Add support for hdmi-connector node's optional ddc-en-gpios property to -support this use case. - -Signed-off-by: Ondrej Jirman -Reviewed-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 +++++++++++++++++++++++++-- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 + - 2 files changed, 52 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -index 8ca5af0c912f..a44dca4b0219 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -97,10 +97,34 @@ static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm, - return crtcs; - } - -+static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev, -+ struct platform_device **pdev_out) -+{ -+ struct platform_device *pdev; -+ struct device_node *remote; -+ -+ remote = of_graph_get_remote_node(dev->of_node, 1, -1); -+ if (!remote) -+ return -ENODEV; -+ -+ if (!of_device_is_compatible(remote, "hdmi-connector")) { -+ of_node_put(remote); -+ return -ENODEV; -+ } -+ -+ pdev = of_find_device_by_node(remote); -+ of_node_put(remote); -+ if (!pdev) -+ return -ENODEV; -+ -+ *pdev_out = pdev; -+ return 0; -+} -+ - static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, - void *data) - { -- struct platform_device *pdev = to_platform_device(dev); -+ struct platform_device *pdev = to_platform_device(dev), *connector_pdev; - struct dw_hdmi_plat_data *plat_data; - struct drm_device *drm = data; - struct device_node *phy_node; -@@ -150,16 +174,30 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, - return PTR_ERR(hdmi->regulator); - } - -+ ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev); -+ if (!ret) { -+ hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev, -+ "ddc-en", GPIOD_OUT_HIGH); -+ platform_device_put(connector_pdev); -+ -+ if (IS_ERR(hdmi->ddc_en)) { -+ dev_err(dev, "Couldn't get ddc-en gpio\n"); -+ return PTR_ERR(hdmi->ddc_en); -+ } -+ } -+ - ret = regulator_enable(hdmi->regulator); - if (ret) { - dev_err(dev, "Failed to enable regulator\n"); -- return ret; -+ goto err_unref_ddc_en; - } - -+ gpiod_set_value(hdmi->ddc_en, 1); -+ - ret = reset_control_deassert(hdmi->rst_ctrl); - if (ret) { - dev_err(dev, "Could not deassert ctrl reset control\n"); -- goto err_disable_regulator; -+ goto err_disable_ddc_en; - } - - ret = clk_prepare_enable(hdmi->clk_tmds); -@@ -212,8 +250,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, - clk_disable_unprepare(hdmi->clk_tmds); - err_assert_ctrl_reset: - reset_control_assert(hdmi->rst_ctrl); --err_disable_regulator: -+err_disable_ddc_en: -+ gpiod_set_value(hdmi->ddc_en, 0); - regulator_disable(hdmi->regulator); -+err_unref_ddc_en: -+ if (hdmi->ddc_en) -+ gpiod_put(hdmi->ddc_en); - - return ret; - } -@@ -227,7 +269,11 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, - sun8i_hdmi_phy_remove(hdmi); - clk_disable_unprepare(hdmi->clk_tmds); - reset_control_assert(hdmi->rst_ctrl); -+ gpiod_set_value(hdmi->ddc_en, 0); - regulator_disable(hdmi->regulator); -+ -+ if (hdmi->ddc_en) -+ gpiod_put(hdmi->ddc_en); - } - - static const struct component_ops sun8i_dw_hdmi_ops = { -diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -index 720c5aa8adc1..d707c9171824 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -190,6 +191,7 @@ struct sun8i_dw_hdmi { - struct regulator *regulator; - const struct sun8i_dw_hdmi_quirks *quirks; - struct reset_control *rst_ctrl; -+ struct gpio_desc *ddc_en; - }; - - static inline struct sun8i_dw_hdmi * -From: Ondrej Jirman -Subject: [PATCH v8 4/4] arm64: dts: allwinner: orange-pi-3: Enable HDMI output -Date: Tue, 6 Aug 2019 17:57:43 +0200 -Content-Type: text/plain; charset="us-ascii" - -Orange Pi 3 has a DDC_CEC_EN signal connected to PH2, that enables the DDC -I2C bus voltage shifter. Before EDID can be read, we need to pull PH2 high. -This is realized by the ddc-en-gpios property. - -Signed-off-by: Ondrej Jirman ---- - .../dts/allwinner/sun50i-h6-orangepi-3.dts | 26 +++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index 2c6807b74ff6..01bb1bafe284 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -22,6 +22,18 @@ - stdout-path = "serial0:115200n8"; - }; - -+ connector { -+ compatible = "hdmi-connector"; -+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -72,6 +84,10 @@ - cpu-supply = <®_dcdca>; - }; - -+&de { -+ status = "okay"; -+}; -+ - &ehci0 { - status = "okay"; - }; -@@ -91,6 +107,16 @@ - status = "okay"; - }; - -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - -From 6b197cb5b4dc7be463599daeb28dfb8d24674746 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Fri, 7 Jun 2019 20:10:49 -0300 -Subject: [PATCH 1/3] media: rc: Introduce sunxi_ir_quirks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This driver is used in various Allwinner SoC with different configuration. - -Introduce a quirks struct to know the fifo size and if a reset is required. - -Signed-off-by: Clément Péron -Acked-by: Maxime Ripard -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/rc/sunxi-cir.c | 61 +++++++++++++++++++++++++++--------- - 1 file changed, 47 insertions(+), 14 deletions(-) - -diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c -index aa719d0ae6b0..29fe152fd9bc 100644 ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -72,6 +72,17 @@ - /* Time after which device stops sending data in ms */ - #define SUNXI_IR_TIMEOUT 120 - -+/** -+ * struct sunxi_ir_quirks - Differences between SoC variants. -+ * -+ * @has_reset: SoC needs reset deasserted. -+ * @fifo_size: size of the fifo. -+ */ -+struct sunxi_ir_quirks { -+ bool has_reset; -+ int fifo_size; -+}; -+ - struct sunxi_ir { - spinlock_t ir_lock; - struct rc_dev *rc; -@@ -134,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev) - - struct device *dev = &pdev->dev; - struct device_node *dn = dev->of_node; -+ const struct sunxi_ir_quirks *quirks; - struct resource *res; - struct sunxi_ir *ir; - u32 b_clk_freq = SUNXI_IR_BASE_CLK; -@@ -142,12 +154,15 @@ static int sunxi_ir_probe(struct platform_device *pdev) - if (!ir) - return -ENOMEM; - -+ quirks = of_device_get_match_data(&pdev->dev); -+ if (!quirks) { -+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); -+ return -ENODEV; -+ } -+ - spin_lock_init(&ir->ir_lock); - -- if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir")) -- ir->fifo_size = 64; -- else -- ir->fifo_size = 16; -+ ir->fifo_size = quirks->fifo_size; - - /* Clock */ - ir->apb_clk = devm_clk_get(dev, "apb"); -@@ -164,13 +179,15 @@ static int sunxi_ir_probe(struct platform_device *pdev) - /* Base clock frequency (optional) */ - of_property_read_u32(dn, "clock-frequency", &b_clk_freq); - -- /* Reset (optional) */ -- ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL); -- if (IS_ERR(ir->rst)) -- return PTR_ERR(ir->rst); -- ret = reset_control_deassert(ir->rst); -- if (ret) -- return ret; -+ /* Reset */ -+ if (quirks->has_reset) { -+ ir->rst = devm_reset_control_get_exclusive(dev, NULL); -+ if (IS_ERR(ir->rst)) -+ return PTR_ERR(ir->rst); -+ ret = reset_control_deassert(ir->rst); -+ if (ret) -+ return ret; -+ } - - ret = clk_set_rate(ir->clk, b_clk_freq); - if (ret) { -@@ -306,10 +323,26 @@ static int sunxi_ir_remove(struct platform_device *pdev) - return 0; - } - -+static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = { -+ .has_reset = false, -+ .fifo_size = 16, -+}; -+ -+static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = { -+ .has_reset = false, -+ .fifo_size = 64, -+}; -+ - static const struct of_device_id sunxi_ir_match[] = { -- { .compatible = "allwinner,sun4i-a10-ir", }, -- { .compatible = "allwinner,sun5i-a13-ir", }, -- {}, -+ { -+ .compatible = "allwinner,sun4i-a10-ir", -+ .data = &sun4i_a10_ir_quirks, -+ }, -+ { -+ .compatible = "allwinner,sun5i-a13-ir", -+ .data = &sun5i_a13_ir_quirks, -+ }, -+ {} - }; - MODULE_DEVICE_TABLE(of, sunxi_ir_match); - --- -2.22.0 - - -From 87d0609801ebcdf18639bb30ec5ec9a380f15be8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Fri, 7 Jun 2019 20:10:50 -0300 -Subject: [PATCH 2/3] media: rc: sunxi: Add A31 compatible -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Allwiner A31 has a different memory mapping so add the compatible -we will need it later. - -Signed-off-by: Clément Péron -Acked-by: Maxime Ripard -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/rc/sunxi-cir.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c -index 29fe152fd9bc..e9b9c582f818 100644 ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -333,6 +333,11 @@ static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = { - .fifo_size = 64, - }; - -+static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = { -+ .has_reset = true, -+ .fifo_size = 64, -+}; -+ - static const struct of_device_id sunxi_ir_match[] = { - { - .compatible = "allwinner,sun4i-a10-ir", -@@ -342,6 +347,10 @@ static const struct of_device_id sunxi_ir_match[] = { - .compatible = "allwinner,sun5i-a13-ir", - .data = &sun5i_a13_ir_quirks, - }, -+ { -+ .compatible = "allwinner,sun6i-a31-ir", -+ .data = &sun6i_a31_ir_quirks, -+ }, - {} - }; - MODULE_DEVICE_TABLE(of, sunxi_ir_match); --- -2.22.0 - - -From b136d72cb89dc2bd11ba001c90cdc65b5f5a1034 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Fri, 7 Jun 2019 20:10:51 -0300 -Subject: [PATCH 3/3] media: rc: sunxi: Add RXSTA bits definition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We are using RXINT bits definition when looking at RXSTA register. - -These bits are equal but it's not really proper. - -Introduce the RXSTA bits and use them to have coherency. - -Signed-off-by: Clément Péron -Acked-by: Maxime Ripard -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - -diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c -index e9b9c582f818..f91154c2f45c 100644 ---- a/drivers/media/rc/sunxi-cir.c -+++ b/drivers/media/rc/sunxi-cir.c -@@ -39,11 +39,11 @@ - - /* Rx Interrupt Enable */ - #define SUNXI_IR_RXINT_REG 0x2C --/* Rx FIFO Overflow */ -+/* Rx FIFO Overflow Interrupt Enable */ - #define REG_RXINT_ROI_EN BIT(0) --/* Rx Packet End */ -+/* Rx Packet End Interrupt Enable */ - #define REG_RXINT_RPEI_EN BIT(1) --/* Rx FIFO Data Available */ -+/* Rx FIFO Data Available Interrupt Enable */ - #define REG_RXINT_RAI_EN BIT(4) - - /* Rx FIFO available byte level */ -@@ -51,6 +51,12 @@ - - /* Rx Interrupt Status */ - #define SUNXI_IR_RXSTA_REG 0x30 -+/* Rx FIFO Overflow */ -+#define REG_RXSTA_ROI REG_RXINT_ROI_EN -+/* Rx Packet End */ -+#define REG_RXSTA_RPE REG_RXINT_RPEI_EN -+/* Rx FIFO Data Available */ -+#define REG_RXSTA_RA REG_RXINT_RAI_EN - /* RX FIFO Get Available Counter */ - #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1)) - /* Clear all interrupt status value */ -@@ -110,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) - /* clean all pending statuses */ - writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); - -- if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) { -+ if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) { - /* How many messages in fifo */ - rc = REG_RXSTA_GET_AC(status); - /* Sanity check */ -@@ -126,9 +132,9 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) - } - } - -- if (status & REG_RXINT_ROI_EN) { -+ if (status & REG_RXSTA_ROI) { - ir_raw_event_reset(ir->rc); -- } else if (status & REG_RXINT_RPEI_EN) { -+ } else if (status & REG_RXSTA_RPE) { - ir_raw_event_set_idle(ir->rc, true); - ir_raw_event_handle(ir->rc); - } --- -2.22.0 - -From 342d23a7dacf9c254c6b98b9b211e566820b7bad Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sat, 8 Jun 2019 01:10:52 +0200 -Subject: [PATCH 1/6] ARM: dts: sunxi: Prefer A31 bindings for IR -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Since A31, memory mapping of the IR driver has changed. - -Prefer the A31 bindings instead of A13. - -Signed-off-by: Clément Péron -Acked-by: Sean Young -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- - arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- - arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi -index dcddc3392460..9ddde111f675 100644 ---- a/arch/arm/boot/dts/sun6i-a31.dtsi -+++ b/arch/arm/boot/dts/sun6i-a31.dtsi -@@ -1364,7 +1364,7 @@ - }; - - ir: ir@1f02000 { -- compatible = "allwinner,sun5i-a13-ir"; -+ compatible = "allwinner,sun6i-a31-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; - clock-names = "apb", "ir"; - resets = <&apb0_rst 1>; -diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi -index 8de139521451..13bc83191899 100644 ---- a/arch/arm/boot/dts/sun8i-a83t.dtsi -+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi -@@ -1096,7 +1096,7 @@ - - r_cir: ir@1f02000 { - compatible = "allwinner,sun8i-a83t-ir", -- "allwinner,sun5i-a13-ir"; -+ "allwinner,sun6i-a31-ir"; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; -diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi -index 0c1eec9000e3..310cd972ee5b 100644 ---- a/arch/arm/boot/dts/sun9i-a80.dtsi -+++ b/arch/arm/boot/dts/sun9i-a80.dtsi -@@ -1167,7 +1167,7 @@ - }; - - r_ir: ir@8002000 { -- compatible = "allwinner,sun5i-a13-ir"; -+ compatible = "allwinner,sun6i-a31-ir"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_pins>; --- -2.22.0 - - -From 8fa345e711bfdb69a18f548b717d5eb502b9892a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sat, 8 Jun 2019 01:10:53 +0200 -Subject: [PATCH 2/6] ARM: dts: sunxi: Prefer A31 bindings for IR -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Since A31, memory mapping of the IR driver has changed. - -Prefer the A31 bindings instead of A13. - -Signed-off-by: Clément Péron -Acked-by: Sean Young -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -index b4a6035ae9f5..97550a40b6e1 100644 ---- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi -+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi -@@ -822,7 +822,7 @@ - }; - - ir: ir@1f02000 { -- compatible = "allwinner,sun5i-a13-ir"; -+ compatible = "allwinner,sun6i-a31-ir"; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; --- -2.22.0 - - -From 44a4f416c8388449fc5f9263788857d449e2a65f Mon Sep 17 00:00:00 2001 -From: Igors Makejevs -Date: Sat, 8 Jun 2019 01:10:55 +0200 -Subject: [PATCH 3/6] arm64: dts: allwinner: a64: Add IR node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -IR peripheral is completely compatible with A31 one. - -Signed-off-by: Igors Makejevs -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Acked-by: Sean Young -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index aa9897f270ba..ddb6f11e89df 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -1094,6 +1094,19 @@ - #size-cells = <0>; - }; - -+ r_ir: ir@1f02000 { -+ compatible = "allwinner,sun50i-a64-ir", -+ "allwinner,sun6i-a31-ir"; -+ reg = <0x01f02000 0x400>; -+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; -+ clock-names = "apb", "ir"; -+ resets = <&r_ccu RST_APB0_IR>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&r_ir_rx_pin>; -+ status = "disabled"; -+ }; -+ - r_pwm: pwm@1f03800 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; -@@ -1121,6 +1134,11 @@ - function = "s_i2c"; - }; - -+ r_ir_rx_pin: r-ir-rx-pin { -+ pins = "PL11"; -+ function = "s_cir_rx"; -+ }; -+ - r_pwm_pin: r-pwm-pin { - pins = "PL10"; - function = "s_pwm"; --- -2.22.0 - - -From 63eb1e149576294717e3e5de48e902ca9d2f080d Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 8 Jun 2019 01:10:56 +0200 -Subject: [PATCH 4/6] arm64: dts: allwinner: a64: Enable IR on Orange Pi Win -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -OrangePi Win board contains IR receiver. Enable it. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Acked-by: Sean Young -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -index 5ef3c62c765e..04446e4716c4 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -@@ -190,6 +190,10 @@ - status = "okay"; - }; - -+&r_ir { -+ status = "okay"; -+}; -+ - &r_rsb { - status = "okay"; - --- -2.22.0 - - -From 9267811aad3524c857cf2e16bbadd8c569e15ab9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sat, 8 Jun 2019 01:10:58 +0200 -Subject: [PATCH 5/6] arm64: dts: allwinner: h6: Add IR receiver node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Allwinner H6 IR is similar to A31 and can use same driver. - -Add support for it. - -Signed-off-by: Clément Péron -Acked-by: Sean Young -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 35942bae0a34..e8bed58e7246 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -675,6 +675,25 @@ - pins = "PL0", "PL1"; - function = "s_i2c"; - }; -+ -+ r_ir_rx_pin: r-ir-rx-pin { -+ pins = "PL9"; -+ function = "s_cir_rx"; -+ }; -+ }; -+ -+ r_ir: ir@7040000 { -+ compatible = "allwinner,sun50i-h6-ir", -+ "allwinner,sun6i-a31-ir"; -+ reg = <0x07040000 0x400>; -+ interrupts = ; -+ clocks = <&r_ccu CLK_R_APB1_IR>, -+ <&r_ccu CLK_IR>; -+ clock-names = "apb", "ir"; -+ resets = <&r_ccu RST_R_APB1_IR>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&r_ir_rx_pin>; -+ status = "disabled"; - }; - - r_i2c: i2c@7081400 { --- -2.22.0 - - -From 86be740845e3811c4517de1a8a36121190155e22 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sat, 8 Jun 2019 01:10:59 +0200 -Subject: [PATCH 6/6] arm64: dts: allwinner: h6: Enable IR on H6 boards -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Beelink GS1, OrangePi H6 boards and Pine H64 have an IR receiver. - -Enable it in their device-tree. - -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 4 ++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++ - 3 files changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index 0dc33c90dd60..680dc29cb089 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -232,6 +232,10 @@ - }; - }; - -+&r_ir { -+ status = "okay"; -+}; -+ - &r_pio { - /* - * PL0 and PL1 are used for PMIC I2C -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index 62e27948a3fa..ec9b6a578e3f 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -189,6 +189,10 @@ - }; - }; - -+&r_ir { -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -index 189834518391..30102daf83cc 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -@@ -255,6 +255,10 @@ - }; - }; - -+&r_ir { -+ status = "okay"; -+}; -+ - &r_pio { - vcc-pm-supply = <®_aldo1>; - }; --- -2.22.0 - -From fdbdcc83ffd7d00265a531e71f1d166566c09d66 Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Wed, 12 Jun 2019 10:51:47 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi: Use automatic CTS generation mode when - using non-AHB audio - -When using an I2S source using a different clock source (usually the I2S -audio HW uses dedicated PLLs, different from the HDMI PHY PLL), fixed -CTS values will cause some frequent audio drop-out and glitches as -reported on Amlogic, Allwinner and Rockchip SoCs setups. - -Setting the CTS in automatic mode will let the HDMI controller generate -automatically the CTS value to match the input audio clock. - -The DesignWare DW-HDMI User Guide explains: - For Automatic CTS generation - Write "0" on the bit field "CTS_manual", Register 0x3205: AUD_CTS3 - -The DesignWare DW-HDMI Databook explains : - If "CTS_manual" bit equals 0b this registers contains "audCTS[19:0]" - generated by the Cycle time counter according to specified timing. - -Cc: Jernej Skrabec -Cc: Maxime Ripard -Cc: Jonas Karlman -Cc: Heiko Stuebner -Cc: Jerome Brunet -Signed-off-by: Neil Armstrong -Tested-by: Jernej Skrabec -Reviewed-by: Jernej Skrabec -Tested-by: Douglas Anderson -Signed-off-by: Andrzej Hajda -Link: https://patchwork.freedesktop.org/patch/msgid/20190612085147.26971-1-narmstrong@baylibre.com ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 45 +++++++++++++++-------- - 1 file changed, 30 insertions(+), 15 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index c6490949d9db..218a7b2308f7 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -508,8 +508,14 @@ static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, - /* nshift factor = 0 */ - hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); - -- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | -- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); -+ /* Use automatic CTS generation mode when CTS is not set */ -+ if (cts) -+ hdmi_writeb(hdmi, ((cts >> 16) & -+ HDMI_AUD_CTS3_AUDCTS19_16_MASK) | -+ HDMI_AUD_CTS3_CTS_MANUAL, -+ HDMI_AUD_CTS3); -+ else -+ hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); - hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); - hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); - -@@ -579,24 +585,33 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, - { - unsigned long ftdms = pixel_clk; - unsigned int n, cts; -+ u8 config3; - u64 tmp; - - n = hdmi_compute_n(sample_rate, pixel_clk); - -- /* -- * Compute the CTS value from the N value. Note that CTS and N -- * can be up to 20 bits in total, so we need 64-bit math. Also -- * note that our TDMS clock is not fully accurate; it is accurate -- * to kHz. This can introduce an unnecessary remainder in the -- * calculation below, so we don't try to warn about that. -- */ -- tmp = (u64)ftdms * n; -- do_div(tmp, 128 * sample_rate); -- cts = tmp; -+ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); - -- dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", -- __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, -- n, cts); -+ /* Only compute CTS when using internal AHB audio */ -+ if (config3 & HDMI_CONFIG3_AHBAUDDMA) { -+ /* -+ * Compute the CTS value from the N value. Note that CTS and N -+ * can be up to 20 bits in total, so we need 64-bit math. Also -+ * note that our TDMS clock is not fully accurate; it is -+ * accurate to kHz. This can introduce an unnecessary remainder -+ * in the calculation below, so we don't try to warn about that. -+ */ -+ tmp = (u64)ftdms * n; -+ do_div(tmp, 128 * sample_rate); -+ cts = tmp; -+ -+ dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", -+ __func__, sample_rate, -+ ftdms / 1000000, (ftdms / 1000) % 1000, -+ n, cts); -+ } else { -+ cts = 0; -+ } - - spin_lock_irq(&hdmi->audio_lock); - hdmi->audio_n = n; --- -2.23.0 - -From 65818ad0815f3a2ba6a41327cce8b600ee04be32 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 14 Aug 2019 08:08:48 +0200 -Subject: [PATCH] clk: sunxi-ng: h6: Allow I2S to change parent rate - -I2S doesn't work if parent rate couldn't be change. Difference between -wanted and actual rate is too big. - -Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Marcus Cooper -Signed-off-by: Chen-Yu Tsai ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index aebef4af9861..d89353a3cdec 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -505,7 +505,7 @@ static struct ccu_div i2s3_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s3", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - -@@ -518,7 +518,7 @@ static struct ccu_div i2s0_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s0", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - -@@ -531,7 +531,7 @@ static struct ccu_div i2s1_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s1", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - -@@ -544,7 +544,7 @@ static struct ccu_div i2s2_clk = { - .hw.init = CLK_HW_INIT_PARENTS("i2s2", - audio_parents, - &ccu_div_ops, -- 0), -+ CLK_SET_RATE_PARENT), - }, - }; - --- -2.23.0 - -From f46f408c152ac925e56c0f38138ae49ba16bbc23 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Mon, 12 Aug 2019 12:23:55 +0200 -Subject: [PATCH] arm64: dts: allwinner: Enable DDC regulator for Beelink GS1 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Beelink GS1 has a DDC I2C bus voltage shifter. This is actually missing -and video is limited to 1024x768 due to missing EDID information. - -Add the DDC regulator in the device-tree. - -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index 675c602b0e33..1d05d570142f 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -25,6 +25,7 @@ - connector { - compatible = "hdmi-connector"; - type = "a"; -+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - - port { - hdmi_con_in: endpoint { --- -2.23.0 - -From d4cbdbc0f88bc4aa3643063f391559868886d315 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Tue, 20 Aug 2019 17:19:33 +0200 -Subject: [PATCH] rtc: sun6i: Add support for H6 RTC - -RTC on H6 is mostly the same as on H5 and H3. It has slight differences -mostly in features that are not yet supported by this driver. - -Some differences are already stated in the comments in existing code. -One other difference is that H6 has extra bit in LOSC_CTRL_REG, called -EXT_LOSC_EN to enable/disable external low speed crystal oscillator. - -It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether -external low speed oscillator is working correctly. - -This patch adds support for enabling LOSC when necessary: - -- during reparenting -- when probing the clock - -H6 also has capacbility to automatically reparent RTC clock from -external crystal oscillator, to internal RC oscillator, if external -oscillator fails. This is enabled by default. Disable it during -probe. - -Signed-off-by: Ondrej Jirman -Reviewed-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20190820151934.3860-3-megous@megous.com -Signed-off-by: Alexandre Belloni ---- - drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 38 insertions(+), 2 deletions(-) - -diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c -index dbd676db431e..956c0846201f 100644 ---- a/drivers/rtc/rtc-sun6i.c -+++ b/drivers/rtc/rtc-sun6i.c -@@ -32,9 +32,11 @@ - /* Control register */ - #define SUN6I_LOSC_CTRL 0x0000 - #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) -+#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) - #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) - #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) - #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) -+#define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) - #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) - #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) - -@@ -128,6 +130,8 @@ struct sun6i_rtc_clk_data { - unsigned int has_prescaler : 1; - unsigned int has_out_clk : 1; - unsigned int export_iosc : 1; -+ unsigned int has_losc_en : 1; -+ unsigned int has_auto_swt : 1; - }; - - struct sun6i_rtc_dev { -@@ -190,6 +194,10 @@ static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) - val &= ~SUN6I_LOSC_CTRL_EXT_OSC; - val |= SUN6I_LOSC_CTRL_KEY; - val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; -+ if (rtc->data->has_losc_en) { -+ val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; -+ val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; -+ } - writel(val, rtc->base + SUN6I_LOSC_CTRL); - spin_unlock_irqrestore(&rtc->lock, flags); - -@@ -215,6 +223,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, - const char *iosc_name = "rtc-int-osc"; - const char *clkout_name = "osc32k-out"; - const char *parents[2]; -+ u32 reg; - - rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); - if (!rtc) -@@ -235,9 +244,18 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, - goto err; - } - -+ reg = SUN6I_LOSC_CTRL_KEY; -+ if (rtc->data->has_auto_swt) { -+ /* Bypass auto-switch to int osc, on ext losc failure */ -+ reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; -+ writel(reg, rtc->base + SUN6I_LOSC_CTRL); -+ } -+ - /* Switch to the external, more precise, oscillator */ -- writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC, -- rtc->base + SUN6I_LOSC_CTRL); -+ reg |= SUN6I_LOSC_CTRL_EXT_OSC; -+ if (rtc->data->has_losc_en) -+ reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; -+ writel(reg, rtc->base + SUN6I_LOSC_CTRL); - - /* Yes, I know, this is ugly. */ - sun6i_rtc = rtc; -@@ -345,6 +363,23 @@ CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", - CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", - sun8i_h3_rtc_clk_init); - -+static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { -+ .rc_osc_rate = 16000000, -+ .fixed_prescaler = 32, -+ .has_prescaler = 1, -+ .has_out_clk = 1, -+ .export_iosc = 1, -+ .has_losc_en = 1, -+ .has_auto_swt = 1, -+}; -+ -+static void __init sun50i_h6_rtc_clk_init(struct device_node *node) -+{ -+ sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); -+} -+CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", -+ sun50i_h6_rtc_clk_init); -+ - static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { - .rc_osc_rate = 32000, - .has_out_clk = 1, -@@ -673,6 +708,7 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = { - { .compatible = "allwinner,sun8i-r40-rtc" }, - { .compatible = "allwinner,sun8i-v3-rtc" }, - { .compatible = "allwinner,sun50i-h5-rtc" }, -+ { .compatible = "allwinner,sun50i-h6-rtc" }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); --- -2.23.0 - -From 4cdc12a3ef424361f81bb30a34a3148b03df640c Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Tue, 20 Aug 2019 17:19:34 +0200 -Subject: [PATCH] arm64: dts: allwinner: h6: Add support for RTC and fix the - clock tree - -This patch adds RTC node and fixes the clock properties and nodes -to reflect the real clock tree. - -The device nodes for the internal oscillator and osc32k are removed, -as these clocks are now provided by the RTC device. Clock references -are fixed accordingly, too. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++++++--------- - 1 file changed, 16 insertions(+), 14 deletions(-) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 67b732e34091..67f920e0fc33 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -56,14 +56,6 @@ - status = "disabled"; - }; - -- iosc: internal-osc-clk { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <16000000>; -- clock-accuracy = <300000000>; -- clock-output-names = "iosc"; -- }; -- - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; -@@ -71,11 +63,11 @@ - clock-output-names = "osc24M"; - }; - -- osc32k: osc32k_clk { -+ ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; -- clock-output-names = "osc32k"; -+ clock-output-names = "ext_osc32k"; - }; - - psci { -@@ -197,7 +189,7 @@ - ccu: clock@3001000 { - compatible = "allwinner,sun50i-h6-ccu"; - reg = <0x03001000 0x1000>; -- clocks = <&osc24M>, <&osc32k>, <&iosc>; -+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; -@@ -236,7 +228,7 @@ - , - , - ; -- clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; -+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; -@@ -710,10 +702,20 @@ - }; - }; - -+ rtc: rtc@7000000 { -+ compatible = "allwinner,sun50i-h6-rtc"; -+ reg = <0x07000000 0x400>; -+ interrupts = , -+ ; -+ clock-output-names = "osc32k", "osc32k-out", "iosc"; -+ clocks = <&ext_osc32k>; -+ #clock-cells = <1>; -+ }; -+ - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-h6-r-ccu"; - reg = <0x07010000 0x400>; -- clocks = <&osc24M>, <&osc32k>, <&iosc>, -+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; -@@ -741,7 +743,7 @@ - reg = <0x07022000 0x400>; - interrupts = , - ; -- clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; -+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; --- -2.23.0 - -From 15ede97054889c0bec09f1f9b71beffecf06fc67 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 23 Aug 2019 11:42:28 +0200 -Subject: [PATCH] arm64: dts: allwinner: orange-pi-3: Enable WiFi - -Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is called -bcm43356 and can be used with the brcmfmac driver. The module is powered by -the two always on regulators (not AXP805). - -WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be -configured so that it sets up an 1.8V input bias on this port. This is done -by the pio driver by reading the vcc-pg-supply voltage. - -You'll need a fw_bcm43456c5_ag.bin firmware file and nvram.txt -configuration that can be found in the Xulongs's repository for H6: - -https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 - -Mainline brcmfmac driver expects the firmware and nvram at the following -paths relative to the firmware directory: - - brcm/brcmfmac43456-sdio.bin - brcm/brcmfmac43456-sdio.txt - -Signed-off-by: Ondrej Jirman -Signed-off-by: Maxime Ripard ---- - .../dts/allwinner/sun50i-h6-orangepi-3.dts | 46 +++++++++++++++++++ - 1 file changed, 46 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index eda9d5f640b9..eb379cd402ac 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -56,6 +56,34 @@ - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ reg_vcc33_wifi: vcc33-wifi { -+ /* Always on 3.3V regulator for WiFi and BT */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc33-wifi"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_vcc5v>; -+ }; -+ -+ reg_vcc_wifi_io: vcc-wifi-io { -+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-wifi-io"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ vin-supply = <®_vcc33_wifi>; -+ }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; -+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ -+ post-power-on-delay-ms = <200>; -+ }; - }; - - &cpu0 { -@@ -91,6 +119,23 @@ - status = "okay"; - }; - -+&mmc1 { -+ vmmc-supply = <®_vcc33_wifi>; -+ vqmmc-supply = <®_vcc_wifi_io>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ brcm: sdio-wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&r_pio>; -+ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &ohci0 { - status = "okay"; - }; -@@ -102,6 +147,7 @@ - &pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; -+ vcc-pg-supply = <®_vcc_wifi_io>; - }; - - &r_i2c { --- -2.23.0 - -From 652a458eb92018c5126701e721255356fdab94a9 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 16 Aug 2019 22:53:42 +0200 -Subject: [PATCH] arm64: dts: allwinner: h6: Introduce Tanix TX6 board - -Tanix TX6 is an Allwinner H6 based TV box, which supports: -- Allwinner H6 Quad-core 64-bit ARM Cortex-A53 -- GPU Mali-T720 -- 4GiB DDR3 RAM (3GiB useable) -- 100Mbps EMAC via AC200 EPHY -- Cdtech 47822BS Wifi/BT -- 2x USB 2.0 Host and 1x USB 3.0 Host -- HDMI port -- IR receiver -- 64GiB eMMC -- 5V/2A DC power supply - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/Makefile | 1 + - .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 100 ++++++++++++++++++ - 2 files changed, 101 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts - -diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile -index f6db0611cb85..395fe76f6819 100644 ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -25,3 +25,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -new file mode 100644 -index 000000000000..7e7cb10e3d96 ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -0,0 +1,100 @@ -+// SPDX-License-Identifier: (GPL-2.0+ or MIT) -+/* -+ * Copyright (c) 2019 Jernej Skrabec -+ */ -+ -+/dts-v1/; -+ -+#include "sun50i-h6.dtsi" -+ -+#include -+ -+/ { -+ model = "Tanix TX6"; -+ compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ connector { -+ compatible = "hdmi-connector"; -+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+}; -+ -+&de { -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins>; -+ vmmc-supply = <®_vcc3v3>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&ohci3 { -+ status = "okay"; -+}; -+ -+&r_ir { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_ph_pins>; -+ status = "okay"; -+}; -+ -+&usb2otg { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb2phy { -+ status = "okay"; -+}; --- -2.23.0 - -From 9e037bdf743cc081858423ad4123824e846b2358 Mon Sep 17 00:00:00 2001 -From: Joe Perches -Date: Wed, 10 Jul 2019 01:04:24 -0400 -Subject: [PATCH] media: staging: media: cedrus: Fix misuse of GENMASK macro - -Arguments are supposed to be ordered high then low. - -Signed-off-by: Joe Perches -Acked-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index 3e9931416e45..ddd29788d685 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -110,7 +110,7 @@ - #define VE_DEC_MPEG_MBADDR (VE_ENGINE_DEC_MPEG + 0x10) - - #define VE_DEC_MPEG_MBADDR_X(w) (((w) << 8) & GENMASK(15, 8)) --#define VE_DEC_MPEG_MBADDR_Y(h) (((h) << 0) & GENMASK(0, 7)) -+#define VE_DEC_MPEG_MBADDR_Y(h) (((h) << 0) & GENMASK(7, 0)) - - #define VE_DEC_MPEG_CTRL (VE_ENGINE_DEC_MPEG + 0x14) - --- -2.23.0 - -From b557b5073194d63bcd2850c009f9326250b4bd97 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 30 May 2019 18:15:14 -0300 -Subject: [PATCH] media: cedrus: Don't set chroma size for scale & rotation - -Scale and rotation are currently not implemented, so it makes no sense to -set chroma size for it. - -Signed-off-by: Jernej Skrabec -Acked-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index c34aec7c6e40..fc8579b90dab 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -79,9 +79,6 @@ void cedrus_dst_format_set(struct cedrus_dev *dev, - reg = VE_PRIMARY_OUT_FMT_NV12; - cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); - -- reg = VE_CHROMA_BUF_LEN_SDRT(chroma_size / 2); -- cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); -- - reg = chroma_size / 2; - cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); - --- -2.23.0 -From 8067f62bccaff4d5c7e0900431e8ab4372dcb8ab Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:07:19 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi-i2s: support more i2s format - -The dw-hdmi-i2s supports more formats than just regular i2s. -Add support for left justified, right justified and dsp modes -A and B. - -Reviewed-by: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812120726.1528-2-jbrunet@baylibre.com ---- - .../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 26 ++++++++++++++++--- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 6 +++-- - 2 files changed, 27 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 5cbb71a866d5..2b624cff541d 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -44,9 +44,8 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - u8 inputclkfs = 0; - - /* it cares I2S only */ -- if ((fmt->fmt != HDMI_I2S) || -- (fmt->bit_clk_master | fmt->frame_clk_master)) { -- dev_err(dev, "unsupported format/settings\n"); -+ if (fmt->bit_clk_master | fmt->frame_clk_master) { -+ dev_err(dev, "unsupported clock settings\n"); - return -EINVAL; - } - -@@ -63,6 +62,27 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - break; - } - -+ switch (fmt->fmt) { -+ case HDMI_I2S: -+ conf1 |= HDMI_AUD_CONF1_MODE_I2S; -+ break; -+ case HDMI_RIGHT_J: -+ conf1 |= HDMI_AUD_CONF1_MODE_RIGHT_J; -+ break; -+ case HDMI_LEFT_J: -+ conf1 |= HDMI_AUD_CONF1_MODE_LEFT_J; -+ break; -+ case HDMI_DSP_A: -+ conf1 |= HDMI_AUD_CONF1_MODE_BURST_1; -+ break; -+ case HDMI_DSP_B: -+ conf1 |= HDMI_AUD_CONF1_MODE_BURST_2; -+ break; -+ default: -+ dev_err(dev, "unsupported format\n"); -+ return -EINVAL; -+ } -+ - dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate); - - hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS); -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -index 4e3ec09d3ca4..091d7c28aa17 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -@@ -869,8 +869,10 @@ enum { - - /* AUD_CONF1 field values */ - HDMI_AUD_CONF1_MODE_I2S = 0x00, -- HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02, -- HDMI_AUD_CONF1_MODE_LEFT_J = 0x04, -+ HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20, -+ HDMI_AUD_CONF1_MODE_LEFT_J = 0x40, -+ HDMI_AUD_CONF1_MODE_BURST_1 = 0x60, -+ HDMI_AUD_CONF1_MODE_BURST_2 = 0x80, - HDMI_AUD_CONF1_WIDTH_16 = 0x10, - HDMI_AUD_CONF1_WIDTH_24 = 0x18, - --- -2.23.0 - -From 2a2a3d2ff799d62f25a9d222ad0fc73753c8a6c6 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:07:20 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi: move audio channel setup out of ahb - -Part of the channel count setup done in dw-hdmi ahb should -actually be done whatever the interface providing the data. - -Let's move it to dw-hdmi driver instead. - -Reviewed-by: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812120726.1528-3-jbrunet@baylibre.com ---- - .../drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 20 +++--------- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 32 +++++++++++++++++++ - include/drm/bridge/dw_hdmi.h | 2 ++ - 3 files changed, 38 insertions(+), 16 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c -index a494186ae6ce..2b7539701b42 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c -@@ -63,10 +63,6 @@ enum { - HDMI_REVISION_ID = 0x0001, - HDMI_IH_AHBDMAAUD_STAT0 = 0x0109, - HDMI_IH_MUTE_AHBDMAAUD_STAT0 = 0x0189, -- HDMI_FC_AUDICONF2 = 0x1027, -- HDMI_FC_AUDSCONF = 0x1063, -- HDMI_FC_AUDSCONF_LAYOUT1 = 1 << 0, -- HDMI_FC_AUDSCONF_LAYOUT0 = 0 << 0, - HDMI_AHB_DMA_CONF0 = 0x3600, - HDMI_AHB_DMA_START = 0x3601, - HDMI_AHB_DMA_STOP = 0x3602, -@@ -403,7 +399,7 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) - { - struct snd_pcm_runtime *runtime = substream->runtime; - struct snd_dw_hdmi *dw = substream->private_data; -- u8 threshold, conf0, conf1, layout, ca; -+ u8 threshold, conf0, conf1, ca; - - /* Setup as per 3.0.5 FSL 4.1.0 BSP */ - switch (dw->revision) { -@@ -434,20 +430,12 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) - conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1; - ca = default_hdmi_channel_config[runtime->channels - 2].ca; - -- /* -- * For >2 channel PCM audio, we need to select layout 1 -- * and set an appropriate channel map. -- */ -- if (runtime->channels > 2) -- layout = HDMI_FC_AUDSCONF_LAYOUT1; -- else -- layout = HDMI_FC_AUDSCONF_LAYOUT0; -- - writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD); - writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0); - writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1); -- writeb_relaxed(layout, dw->data.base + HDMI_FC_AUDSCONF); -- writeb_relaxed(ca, dw->data.base + HDMI_FC_AUDICONF2); -+ -+ dw_hdmi_set_channel_count(dw->data.hdmi, runtime->channels); -+ dw_hdmi_set_channel_allocation(dw->data.hdmi, ca); - - switch (runtime->format) { - case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 83b94b66e464..ae46b770943e 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -645,6 +645,38 @@ void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) - } - EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); - -+void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) -+{ -+ u8 layout; -+ -+ mutex_lock(&hdmi->audio_mutex); -+ -+ /* -+ * For >2 channel PCM audio, we need to select layout 1 -+ * and set an appropriate channel map. -+ */ -+ if (cnt > 2) -+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; -+ else -+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; -+ -+ hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, -+ HDMI_FC_AUDSCONF); -+ -+ mutex_unlock(&hdmi->audio_mutex); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); -+ -+void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) -+{ -+ mutex_lock(&hdmi->audio_mutex); -+ -+ hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); -+ -+ mutex_unlock(&hdmi->audio_mutex); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); -+ - static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) - { - if (enable) -diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index c402364aec0d..cf528c289857 100644 ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -155,6 +155,8 @@ void dw_hdmi_resume(struct dw_hdmi *hdmi); - void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); - - void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); -+void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); -+void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); - void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); - void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); - void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); --- -2.23.0 - -From da5f5bc92f49f5b3acf8b07d95fb7d8a8f098d25 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:07:21 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi: set channel count in the infoframes - -Set the number of channel in the infoframes - -Reviewed-by: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812120726.1528-4-jbrunet@baylibre.com ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index ae46b770943e..4e57b984b244 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -663,6 +663,10 @@ void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) - hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, - HDMI_FC_AUDSCONF); - -+ /* Set the audio infoframes channel count */ -+ hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, -+ HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); -+ - mutex_unlock(&hdmi->audio_mutex); - } - EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); --- -2.23.0 - -From 17a1e555b608a847c903e093718d0a768843c586 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:07:22 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi-i2s: enable lpcm multi channels - -Properly setup the channel count and layout in dw-hdmi i2s driver so -we are not limited to 2 channels. - -Also correct the maximum channel reported by the DAI from 6 to 8 ch - -Reviewed-by: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812120726.1528-5-jbrunet@baylibre.com ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 2b624cff541d..caf8aed78fea 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -84,6 +84,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - } - - dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate); -+ dw_hdmi_set_channel_count(hdmi, hparms->channels); - - hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS); - hdmi_write(audio, conf0, HDMI_AUD_CONF0); -@@ -139,7 +140,7 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev) - - pdata.ops = &dw_hdmi_i2s_ops; - pdata.i2s = 1; -- pdata.max_i2s_channels = 6; -+ pdata.max_i2s_channels = 8; - pdata.data = audio; - - memset(&pdevinfo, 0, sizeof(pdevinfo)); --- -2.23.0 - -From 0c6098859176ffa250b196498722dc7844e41048 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:07:23 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi-i2s: set the channel allocation - -setup the channel allocation provided by the generic hdmi-codec driver - -Reviewed-by: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812120726.1528-6-jbrunet@baylibre.com ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index caf8aed78fea..0864dee8d180 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -85,6 +85,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - - dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate); - dw_hdmi_set_channel_count(hdmi, hparms->channels); -+ dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation); - - hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS); - hdmi_write(audio, conf0, HDMI_AUD_CONF0); --- -2.23.0 - -From 46cecde310bba81243f906955f5fd6f64d5668f0 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:07:24 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi-i2s: reset audio fifo before applying new - params - -When changing the audio hw params, reset the audio fifo to make sure -any old remaining data is flushed. - -The databook mentions that such reset should be followed by a reset of -the i2s block to make sure the samples stay aligned - -Reviewed-by: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812120726.1528-7-jbrunet@baylibre.com ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 6 ++++-- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + - 2 files changed, 5 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 0864dee8d180..41bee0099578 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -49,6 +49,10 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - return -EINVAL; - } - -+ /* Reset the FIFOs before applying new params */ -+ hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); -+ hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ); -+ - inputclkfs = HDMI_AUD_INPUTCLKFS_64FS; - conf0 = HDMI_AUD_CONF0_I2S_ALL_ENABLE; - -@@ -102,8 +106,6 @@ static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data) - struct dw_hdmi *hdmi = audio->hdmi; - - dw_hdmi_audio_disable(hdmi); -- -- hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); - } - - static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component, -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -index 091d7c28aa17..a272fa393ae6 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -@@ -940,6 +940,7 @@ enum { - HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, - - /* MC_SWRSTZ field values */ -+ HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08, - HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, - - /* MC_FLOWCTRL field values */ --- -2.23.0 - -From 43e88f670a5e4618609822853a5f659631c32505 Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:07:25 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi-i2s: enable only the required i2s lanes - -Enable the i2s lanes depending on the number of channel in the stream - -Reviewed-by: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812120726.1528-8-jbrunet@baylibre.com ---- - .../gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 15 ++++++++++++++- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 6 +++++- - 2 files changed, 19 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 41bee0099578..b8ece9c1ba2c 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -54,7 +54,20 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ); - - inputclkfs = HDMI_AUD_INPUTCLKFS_64FS; -- conf0 = HDMI_AUD_CONF0_I2S_ALL_ENABLE; -+ conf0 = (HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_EN0); -+ -+ /* Enable the required i2s lanes */ -+ switch (hparms->channels) { -+ case 7 ... 8: -+ conf0 |= HDMI_AUD_CONF0_I2S_EN3; -+ /* Fall-thru */ -+ case 5 ... 6: -+ conf0 |= HDMI_AUD_CONF0_I2S_EN2; -+ /* Fall-thru */ -+ case 3 ... 4: -+ conf0 |= HDMI_AUD_CONF0_I2S_EN1; -+ /* Fall-thru */ -+ } - - switch (hparms->sample_width) { - case 16: -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -index a272fa393ae6..6988f12d89d9 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -@@ -865,7 +865,11 @@ enum { - - /* AUD_CONF0 field values */ - HDMI_AUD_CONF0_SW_RESET = 0x80, -- HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F, -+ HDMI_AUD_CONF0_I2S_SELECT = 0x20, -+ HDMI_AUD_CONF0_I2S_EN3 = 0x08, -+ HDMI_AUD_CONF0_I2S_EN2 = 0x04, -+ HDMI_AUD_CONF0_I2S_EN1 = 0x02, -+ HDMI_AUD_CONF0_I2S_EN0 = 0x01, - - /* AUD_CONF1 field values */ - HDMI_AUD_CONF1_MODE_I2S = 0x00, --- -2.23.0 - -From fc1ca6e01d0a71fd4bd7a5a7cb8309a9dd48ddbc Mon Sep 17 00:00:00 2001 -From: Jerome Brunet -Date: Mon, 12 Aug 2019 14:50:16 +0200 -Subject: [PATCH] drm/bridge: dw-hdmi-i2s: add .get_eld support - -Provide the eld to the generic hdmi-codec driver. -This will let the driver enforce the maximum channel number and set the -channel allocation depending on the hdmi sink. - -Cc: Jonas Karlman -Signed-off-by: Jerome Brunet -Reviewed-by: Jonas Karlman -Reviewed-by: Neil Armstrong -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190812125016.20169-1-jbrunet@baylibre.com ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 + - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 11 +++++++++++ - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + - 3 files changed, 13 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h -index 63b5756f463b..cb07dc0da5a7 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h -@@ -14,6 +14,7 @@ struct dw_hdmi_audio_data { - - struct dw_hdmi_i2s_audio_data { - struct dw_hdmi *hdmi; -+ u8 *eld; - - void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); - u8 (*read)(struct dw_hdmi *hdmi, int offset); -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index b8ece9c1ba2c..1d15cf9b6821 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -10,6 +10,7 @@ - #include - - #include -+#include - - #include - -@@ -121,6 +122,15 @@ static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data) - dw_hdmi_audio_disable(hdmi); - } - -+static int dw_hdmi_i2s_get_eld(struct device *dev, void *data, uint8_t *buf, -+ size_t len) -+{ -+ struct dw_hdmi_i2s_audio_data *audio = data; -+ -+ memcpy(buf, audio->eld, min_t(size_t, MAX_ELD_BYTES, len)); -+ return 0; -+} -+ - static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component, - struct device_node *endpoint) - { -@@ -144,6 +154,7 @@ static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component, - static struct hdmi_codec_ops dw_hdmi_i2s_ops = { - .hw_params = dw_hdmi_i2s_hw_params, - .audio_shutdown = dw_hdmi_i2s_audio_shutdown, -+ .get_eld = dw_hdmi_i2s_get_eld, - .get_dai_id = dw_hdmi_i2s_get_dai_id, - }; - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 4e57b984b244..4044071090c4 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2799,6 +2799,7 @@ __dw_hdmi_probe(struct platform_device *pdev, - struct dw_hdmi_i2s_audio_data audio; - - audio.hdmi = hdmi; -+ audio.eld = hdmi->connector.eld; - audio.write = hdmi_writeb; - audio.read = hdmi_readb; - hdmi->enable_audio = dw_hdmi_i2s_audio_enable; --- -2.23.0 - -From bf283a05c09b58db83afbb1a8a3c6a684c56c1bb Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:08 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Register regmap and PCM before our component - -So far the regmap and the dmaengine PCM are registered after our component -has been, which means that our driver isn't properly initialised by then. - -Let's fix that. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/67e303f37f141ef73ce9ed47d7f831b63c694424.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 7fa5c61169db..85c3b2c8cd77 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1148,11 +1148,9 @@ static int sun4i_i2s_probe(struct platform_device *pdev) - goto err_pm_disable; - } - -- ret = devm_snd_soc_register_component(&pdev->dev, -- &sun4i_i2s_component, -- &sun4i_i2s_dai, 1); -+ ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); - if (ret) { -- dev_err(&pdev->dev, "Could not register DAI\n"); -+ dev_err(&pdev->dev, "Could not initialise regmap fields\n"); - goto err_suspend; - } - -@@ -1162,9 +1160,11 @@ static int sun4i_i2s_probe(struct platform_device *pdev) - goto err_suspend; - } - -- ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); -+ ret = devm_snd_soc_register_component(&pdev->dev, -+ &sun4i_i2s_component, -+ &sun4i_i2s_dai, 1); - if (ret) { -- dev_err(&pdev->dev, "Could not initialise regmap fields\n"); -+ dev_err(&pdev->dev, "Could not register DAI\n"); - goto err_suspend; - } - --- -2.23.0 - -From a49d24e7d8d4fd4edf59e6373983e0bf4a2cca15 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:09 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Switch to devm for PCM register - -Since the introduction of the driver, a new managed helper for the -dmaengine PCM registration has been created. Let's use it to simplify a bit -our probe and remove functions. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/606d271187091e858e8c15e20555af0b79798fe1.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index d97d694c48df..70608fa30bf2 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1154,7 +1154,7 @@ static int sun4i_i2s_probe(struct platform_device *pdev) - goto err_suspend; - } - -- ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); -+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); - if (ret) { - dev_err(&pdev->dev, "Could not register PCM\n"); - goto err_suspend; -@@ -1183,8 +1183,6 @@ static int sun4i_i2s_remove(struct platform_device *pdev) - { - struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); - -- snd_dmaengine_pcm_unregister(&pdev->dev); -- - pm_runtime_disable(&pdev->dev); - if (!pm_runtime_status_suspended(&pdev->dev)) - sun4i_i2s_runtime_suspend(&pdev->dev); --- -2.23.0 - -From c7dd0828c088a71f30de8d249f63b2fa9f0d322d Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:10 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Replace call to params_channels by local - variable - -The sun4i_i2s_hw_params already has a variable holding the value returned -by params_channels, so let's just use that variable instead of calling -params_channels multiple times. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/c0faaac69ad40248f24eed3c3b2fa1ccc4a85b70.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index d879db581073..77b7b81daf74 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -412,10 +412,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - - /* Configure the channels */ - regmap_field_write(i2s->field_txchansel, -- SUN4I_I2S_CHAN_SEL(params_channels(params))); -- -+ SUN4I_I2S_CHAN_SEL(channels)); - regmap_field_write(i2s->field_rxchansel, -- SUN4I_I2S_CHAN_SEL(params_channels(params))); -+ SUN4I_I2S_CHAN_SEL(channels)); - - if (i2s->variant->has_chsel_tx_chen) - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, --- -2.23.0 - -From 8bcf62b73e5421df94deca95d7d7c152997fe5b4 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:13 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Rework MCLK divider calculation - -The MCLK divider calculation is currently computing the ideal divider using -the oversample rate, the sample rate and the parent rate. - -However, since we have access to the frequency is supposed to be running at -already, and as it turns out we're using it to compute the oversample rate, -we can just use the ratio between the parent rate and the MCLK rate to -simplify a bit the formula. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/dcc5deb2eb650758d268bddd20f60ba58856d024.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 77b7b81daf74..0a5fb9d4b289 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -240,11 +240,10 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, - } - - static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, -- unsigned int oversample_rate, -- unsigned int module_rate, -- unsigned int sampling_rate) -+ unsigned long parent_rate, -+ unsigned long mclk_rate) - { -- int div = module_rate / sampling_rate / oversample_rate; -+ int div = parent_rate / mclk_rate; - int i; - - for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) { -@@ -323,8 +322,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - return -EINVAL; - } - -- mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate, -- clk_rate, rate); -+ mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq); - if (mclk_div < 0) { - dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); - return -EINVAL; --- -2.23.0 - -From d70be625f25af7a2bc91b7d17d205f6071f08f2f Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:11 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Move the channel configuration to a callback - -The two main generations of our I2S controller require a slightly different -channel configuration, mostly because of a quite different register layout -and some additional registers being needed on the newer generation. - -This used to be controlled through a bunch of booleans, however this proved -to be quite impractical, especially since a bunch of SoCs forgot to set -those parameters and therefore were broken from that point of view. - -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/6414463de69584e8227fa495b13aa5f4798e1f0e.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 156 ++++++++++++++++-------------------- - 1 file changed, 69 insertions(+), 87 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 2c909c6cafa9..42e45c9a947a 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -80,6 +80,7 @@ - #define SUN4I_I2S_TX_CNT_REG 0x2c - - #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 -+#define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0) - #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) - - #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 -@@ -122,8 +123,6 @@ struct sun4i_i2s; - * @has_reset: SoC needs reset deasserted. - * @has_slave_select_bit: SoC has a bit to enable slave mode. - * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. -- * @has_chcfg: tx and rx slot number need to be set. -- * @has_chsel_tx_chen: SoC requires that the tx channels are enabled. - * @has_chsel_offset: SoC uses offset for selecting dai operational mode. - * @reg_offset_txdata: offset of the tx fifo. - * @sun4i_i2s_regmap: regmap config to use. -@@ -135,17 +134,11 @@ struct sun4i_i2s; - * @field_fmt_bclk: regmap field to set clk polarity. - * @field_fmt_lrclk: regmap field to set frame polarity. - * @field_fmt_mode: regmap field to set the operational mode. -- * @field_txchanmap: location of the tx channel mapping register. -- * @field_rxchanmap: location of the rx channel mapping register. -- * @field_txchansel: location of the tx channel select bit fields. -- * @field_rxchansel: location of the rx channel select bit fields. - */ - struct sun4i_i2s_quirks { - bool has_reset; - bool has_slave_select_bit; - bool has_fmt_set_lrck_period; -- bool has_chcfg; -- bool has_chsel_tx_chen; - bool has_chsel_offset; - unsigned int reg_offset_txdata; /* TX FIFO */ - const struct regmap_config *sun4i_i2s_regmap; -@@ -159,13 +152,11 @@ struct sun4i_i2s_quirks { - struct reg_field field_fmt_bclk; - struct reg_field field_fmt_lrclk; - struct reg_field field_fmt_mode; -- struct reg_field field_txchanmap; -- struct reg_field field_rxchanmap; -- struct reg_field field_txchansel; -- struct reg_field field_rxchansel; - - s8 (*get_sr)(const struct sun4i_i2s *, int); - s8 (*get_wss)(const struct sun4i_i2s *, int); -+ int (*set_chan_cfg)(const struct sun4i_i2s *, -+ const struct snd_pcm_hw_params *); - }; - - struct sun4i_i2s { -@@ -186,10 +177,6 @@ struct sun4i_i2s { - struct regmap_field *field_fmt_bclk; - struct regmap_field *field_fmt_lrclk; - struct regmap_field *field_fmt_mode; -- struct regmap_field *field_txchanmap; -- struct regmap_field *field_rxchanmap; -- struct regmap_field *field_txchansel; -- struct regmap_field *field_rxchansel; - - const struct sun4i_i2s_quirks *variant; - }; -@@ -380,44 +367,77 @@ static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width) - return (width - 8) / 4 + 1; - } - --static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, -- struct snd_pcm_hw_params *params, -- struct snd_soc_dai *dai) -+static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, -+ const struct snd_pcm_hw_params *params) - { -- struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -- int sr, wss, channels; -- u32 width; -+ unsigned int channels = params_channels(params); - -- channels = params_channels(params); -- if (channels != 2) { -- dev_err(dai->dev, "Unsupported number of channels: %d\n", -- channels); -+ if (channels != 2) - return -EINVAL; -- } - -- if (i2s->variant->has_chcfg) { -- regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, -- SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, -- SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); -- regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, -- SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, -- SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); -- } -+ /* Map the channels for playback and capture */ -+ regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); -+ regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); -+ -+ /* Configure the channels */ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, -+ SUN4I_I2S_CHAN_SEL_MASK, -+ SUN4I_I2S_CHAN_SEL(channels)); -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, -+ SUN4I_I2S_CHAN_SEL_MASK, -+ SUN4I_I2S_CHAN_SEL(channels)); -+ -+ return 0; -+} -+ -+static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, -+ const struct snd_pcm_hw_params *params) -+{ -+ unsigned int channels = params_channels(params); -+ -+ if (channels != 2) -+ return -EINVAL; - - /* Map the channels for playback and capture */ -- regmap_field_write(i2s->field_txchanmap, 0x76543210); -- regmap_field_write(i2s->field_rxchanmap, 0x00003210); -+ regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); -+ regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); - - /* Configure the channels */ -- regmap_field_write(i2s->field_txchansel, -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -+ SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); -- regmap_field_write(i2s->field_rxchansel, -+ -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, -+ SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); - -- if (i2s->variant->has_chsel_tx_chen) -- regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -- SUN8I_I2S_TX_CHAN_EN_MASK, -- SUN8I_I2S_TX_CHAN_EN(channels)); -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, -+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, -+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, -+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, -+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); -+ -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -+ SUN8I_I2S_TX_CHAN_EN_MASK, -+ SUN8I_I2S_TX_CHAN_EN(channels)); -+ -+ return 0; -+} -+ -+static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, -+ struct snd_soc_dai *dai) -+{ -+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ int ret, sr, wss; -+ u32 width; -+ -+ ret = i2s->variant->set_chan_cfg(i2s, params); -+ if (ret < 0) { -+ dev_err(dai->dev, "Invalid channel configuration\n"); -+ return ret; -+ } - - switch (params_physical_width(params)) { - case 16: -@@ -915,12 +935,9 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .has_slave_select_bit = true, - .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), -- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), -- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), -- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), -- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, -+ .set_chan_cfg = sun4i_i2s_set_chan_cfg, - }; - - static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { -@@ -934,12 +951,9 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .has_slave_select_bit = true, - .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), -- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), -- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), -- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), -- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, -+ .set_chan_cfg = sun4i_i2s_set_chan_cfg, - }; - - static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { -@@ -953,12 +967,9 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .has_slave_select_bit = true, - .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), -- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), -- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), -- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), -- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, -+ .set_chan_cfg = sun8i_i2s_set_chan_cfg, - }; - - static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { -@@ -968,8 +979,6 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { - .mclk_offset = 1, - .bclk_offset = 2, - .has_fmt_set_lrck_period = true, -- .has_chcfg = true, -- .has_chsel_tx_chen = true, - .has_chsel_offset = true, - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), -@@ -977,12 +986,9 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), - .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), -- .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31), -- .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31), -- .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2), -- .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2), - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, -+ .set_chan_cfg = sun8i_i2s_set_chan_cfg, - }; - - static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { -@@ -996,12 +1002,9 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), -- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), -- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), -- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), -- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, -+ .set_chan_cfg = sun4i_i2s_set_chan_cfg, - }; - - static int sun4i_i2s_init_regmap_fields(struct device *dev, -@@ -1043,28 +1046,7 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, - if (IS_ERR(i2s->field_fmt_mode)) - return PTR_ERR(i2s->field_fmt_mode); - -- i2s->field_txchanmap = -- devm_regmap_field_alloc(dev, i2s->regmap, -- i2s->variant->field_txchanmap); -- if (IS_ERR(i2s->field_txchanmap)) -- return PTR_ERR(i2s->field_txchanmap); -- -- i2s->field_rxchanmap = -- devm_regmap_field_alloc(dev, i2s->regmap, -- i2s->variant->field_rxchanmap); -- if (IS_ERR(i2s->field_rxchanmap)) -- return PTR_ERR(i2s->field_rxchanmap); -- -- i2s->field_txchansel = -- devm_regmap_field_alloc(dev, i2s->regmap, -- i2s->variant->field_txchansel); -- if (IS_ERR(i2s->field_txchansel)) -- return PTR_ERR(i2s->field_txchansel); -- -- i2s->field_rxchansel = -- devm_regmap_field_alloc(dev, i2s->regmap, -- i2s->variant->field_rxchansel); -- return PTR_ERR_OR_ZERO(i2s->field_rxchansel); -+ return 0; - } - - static int sun4i_i2s_probe(struct platform_device *pdev) --- -2.23.0 - -From 71137bcd0a9a778f9407a3bee46c62fcccee4f83 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:12 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Move the format configuration to a callback - -The two main generations of our I2S controller require a slightly different -format configuration, mostly because of a quite different register layout -and some additional registers being needed on the newer generation. - -This used to be controlled through a bunch of booleans, however this proved -to be quite impractical, especially since a bunch of SoCs forgot to set -those parameters and therefore were broken from that point of view. - -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/dc818644c3e40734e7a97247c994b1fca1c3c047.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 199 +++++++++++++++++++----------------- - 1 file changed, 106 insertions(+), 93 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 42e45c9a947a..93ea627e2f1f 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -93,6 +93,11 @@ - #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) - #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) - -+#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4) -+#define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4) -+#define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4) -+#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4) -+ - #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) - #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8) - -@@ -121,9 +126,7 @@ struct sun4i_i2s; - * struct sun4i_i2s_quirks - Differences between SoC variants. - * - * @has_reset: SoC needs reset deasserted. -- * @has_slave_select_bit: SoC has a bit to enable slave mode. - * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. -- * @has_chsel_offset: SoC uses offset for selecting dai operational mode. - * @reg_offset_txdata: offset of the tx fifo. - * @sun4i_i2s_regmap: regmap config to use. - * @mclk_offset: Value by which mclkdiv needs to be adjusted. -@@ -133,13 +136,10 @@ struct sun4i_i2s; - * @field_fmt_sr: regmap field to set sample resolution. - * @field_fmt_bclk: regmap field to set clk polarity. - * @field_fmt_lrclk: regmap field to set frame polarity. -- * @field_fmt_mode: regmap field to set the operational mode. - */ - struct sun4i_i2s_quirks { - bool has_reset; -- bool has_slave_select_bit; - bool has_fmt_set_lrck_period; -- bool has_chsel_offset; - unsigned int reg_offset_txdata; /* TX FIFO */ - const struct regmap_config *sun4i_i2s_regmap; - unsigned int mclk_offset; -@@ -151,12 +151,12 @@ struct sun4i_i2s_quirks { - struct reg_field field_fmt_sr; - struct reg_field field_fmt_bclk; - struct reg_field field_fmt_lrclk; -- struct reg_field field_fmt_mode; - - s8 (*get_sr)(const struct sun4i_i2s *, int); - s8 (*get_wss)(const struct sun4i_i2s *, int); - int (*set_chan_cfg)(const struct sun4i_i2s *, - const struct snd_pcm_hw_params *); -+ int (*set_fmt)(const struct sun4i_i2s *, unsigned int); - }; - - struct sun4i_i2s { -@@ -176,7 +176,6 @@ struct sun4i_i2s { - struct regmap_field *field_fmt_sr; - struct regmap_field *field_fmt_bclk; - struct regmap_field *field_fmt_lrclk; -- struct regmap_field *field_fmt_mode; - - const struct sun4i_i2s_quirks *variant; - }; -@@ -465,52 +464,117 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - params_width(params)); - } - --static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) -+static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, -+ unsigned int fmt) - { -- struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); - u32 val; -- u32 offset = 0; -- u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; -- u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; - - /* DAI Mode */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_I2S: - val = SUN4I_I2S_FMT0_FMT_I2S; -- offset = 1; - break; -+ - case SND_SOC_DAIFMT_LEFT_J: - val = SUN4I_I2S_FMT0_FMT_LEFT_J; - break; -+ - case SND_SOC_DAIFMT_RIGHT_J: - val = SUN4I_I2S_FMT0_FMT_RIGHT_J; - break; -+ - default: -- dev_err(dai->dev, "Unsupported format: %d\n", -- fmt & SND_SOC_DAIFMT_FORMAT_MASK); - return -EINVAL; - } - -- if (i2s->variant->has_chsel_offset) { -- /* -- * offset being set indicates that we're connected to an i2s -- * device, however offset is only used on the sun8i block and -- * i2s shares the same setting with the LJ format. Increment -- * val so that the bit to value to write is correct. -- */ -- if (offset > 0) -- val++; -- /* blck offset determines whether i2s or LJ */ -- regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -- SUN8I_I2S_TX_CHAN_OFFSET_MASK, -- SUN8I_I2S_TX_CHAN_OFFSET(offset)); -- -- regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, -- SUN8I_I2S_TX_CHAN_OFFSET_MASK, -- SUN8I_I2S_TX_CHAN_OFFSET(offset)); -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, -+ SUN4I_I2S_FMT0_FMT_MASK, val); -+ -+ /* DAI clock master masks */ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBS_CFS: -+ /* BCLK and LRCLK master */ -+ val = SUN4I_I2S_CTRL_MODE_MASTER; -+ break; -+ -+ case SND_SOC_DAIFMT_CBM_CFM: -+ /* BCLK and LRCLK slave */ -+ val = SUN4I_I2S_CTRL_MODE_SLAVE; -+ break; -+ -+ default: -+ return -EINVAL; - } -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, -+ SUN4I_I2S_CTRL_MODE_MASK, val); -+ return 0; -+} - -- regmap_field_write(i2s->field_fmt_mode, val); -+static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, -+ unsigned int fmt) -+{ -+ u32 mode, val; -+ u8 offset; -+ -+ /* DAI Mode */ -+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ mode = SUN8I_I2S_CTRL_MODE_LEFT; -+ offset = 1; -+ break; -+ -+ case SND_SOC_DAIFMT_LEFT_J: -+ mode = SUN8I_I2S_CTRL_MODE_LEFT; -+ offset = 0; -+ break; -+ -+ case SND_SOC_DAIFMT_RIGHT_J: -+ mode = SUN8I_I2S_CTRL_MODE_RIGHT; -+ offset = 0; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, -+ SUN8I_I2S_CTRL_MODE_MASK, mode); -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, -+ SUN8I_I2S_TX_CHAN_OFFSET_MASK, -+ SUN8I_I2S_TX_CHAN_OFFSET(offset)); -+ regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, -+ SUN8I_I2S_TX_CHAN_OFFSET_MASK, -+ SUN8I_I2S_TX_CHAN_OFFSET(offset)); -+ -+ /* DAI clock master masks */ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBS_CFS: -+ /* BCLK and LRCLK master */ -+ val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT; -+ break; -+ -+ case SND_SOC_DAIFMT_CBM_CFM: -+ /* BCLK and LRCLK slave */ -+ val = 0; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, -+ SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, -+ val); -+ -+ return 0; -+} -+ -+static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) -+{ -+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; -+ u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; -+ int ret; - - /* DAI clock polarity */ - switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -@@ -538,50 +602,10 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) - regmap_field_write(i2s->field_fmt_bclk, bclk_polarity); - regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity); - -- if (i2s->variant->has_slave_select_bit) { -- /* DAI clock master masks */ -- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -- case SND_SOC_DAIFMT_CBS_CFS: -- /* BCLK and LRCLK master */ -- val = SUN4I_I2S_CTRL_MODE_MASTER; -- break; -- case SND_SOC_DAIFMT_CBM_CFM: -- /* BCLK and LRCLK slave */ -- val = SUN4I_I2S_CTRL_MODE_SLAVE; -- break; -- default: -- dev_err(dai->dev, "Unsupported slave setting: %d\n", -- fmt & SND_SOC_DAIFMT_MASTER_MASK); -- return -EINVAL; -- } -- regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, -- SUN4I_I2S_CTRL_MODE_MASK, -- val); -- } else { -- /* -- * The newer i2s block does not have a slave select bit, -- * instead the clk pins are configured as inputs. -- */ -- /* DAI clock master masks */ -- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -- case SND_SOC_DAIFMT_CBS_CFS: -- /* BCLK and LRCLK master */ -- val = SUN8I_I2S_CTRL_BCLK_OUT | -- SUN8I_I2S_CTRL_LRCK_OUT; -- break; -- case SND_SOC_DAIFMT_CBM_CFM: -- /* BCLK and LRCLK slave */ -- val = 0; -- break; -- default: -- dev_err(dai->dev, "Unsupported slave setting: %d\n", -- fmt & SND_SOC_DAIFMT_MASTER_MASK); -- return -EINVAL; -- } -- regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, -- SUN8I_I2S_CTRL_BCLK_OUT | -- SUN8I_I2S_CTRL_LRCK_OUT, -- val); -+ ret = i2s->variant->set_fmt(i2s, fmt); -+ if (ret) { -+ dev_err(dai->dev, "Unsupported format configuration\n"); -+ return ret; - } - - /* Set significant bits in our FIFOs */ -@@ -933,11 +957,10 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -- .has_slave_select_bit = true, -- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, - .set_chan_cfg = sun4i_i2s_set_chan_cfg, -+ .set_fmt = sun4i_i2s_set_soc_fmt, - }; - - static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { -@@ -949,11 +972,10 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -- .has_slave_select_bit = true, -- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, - .set_chan_cfg = sun4i_i2s_set_chan_cfg, -+ .set_fmt = sun4i_i2s_set_soc_fmt, - }; - - static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { -@@ -965,11 +987,10 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -- .has_slave_select_bit = true, -- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, - .set_chan_cfg = sun8i_i2s_set_chan_cfg, -+ .set_fmt = sun8i_i2s_set_soc_fmt, - }; - - static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { -@@ -979,32 +1000,30 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { - .mclk_offset = 1, - .bclk_offset = 2, - .has_fmt_set_lrck_period = true, -- .has_chsel_offset = true, - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), -- .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, - .set_chan_cfg = sun8i_i2s_set_chan_cfg, -+ .set_fmt = sun8i_i2s_set_soc_fmt, - }; - - static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, - .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, -- .has_slave_select_bit = true, - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, - .set_chan_cfg = sun4i_i2s_set_chan_cfg, -+ .set_fmt = sun4i_i2s_set_soc_fmt, - }; - - static int sun4i_i2s_init_regmap_fields(struct device *dev, -@@ -1040,12 +1059,6 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, - if (IS_ERR(i2s->field_fmt_lrclk)) - return PTR_ERR(i2s->field_fmt_lrclk); - -- i2s->field_fmt_mode = -- devm_regmap_field_alloc(dev, i2s->regmap, -- i2s->variant->field_fmt_mode); -- if (IS_ERR(i2s->field_fmt_mode)) -- return PTR_ERR(i2s->field_fmt_mode); -- - return 0; - } - --- -2.23.0 - -From fb19739d7f688142b61d0fca476188c4fd9e937a Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:15 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Use module clock as BCLK parent on newer - SoCs - -On the first generation of Allwinner SoCs (A10-A31), the i2s controller was -using the MCLK as BCLK parent. However, this changed since the introduction -of the A83t and BCLK now uses the module clock as its parent. - -Let's introduce a hook to get the parent rate and use that in our divider -calculations. - -Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3") -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/0b6665be216b3bd0e7bc43724818f05f3f8ee881.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 21 +++++++++++++++++++-- - 1 file changed, 19 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 93ea627e2f1f..acfcdb26086a 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -152,6 +152,7 @@ struct sun4i_i2s_quirks { - struct reg_field field_fmt_bclk; - struct reg_field field_fmt_lrclk; - -+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *); - s8 (*get_sr)(const struct sun4i_i2s *, int); - s8 (*get_wss)(const struct sun4i_i2s *, int); - int (*set_chan_cfg)(const struct sun4i_i2s *, -@@ -207,6 +208,16 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { - /* TODO - extend divide ratio supported by newer SoCs */ - }; - -+static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) -+{ -+ return i2s->mclk_freq; -+} -+ -+static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) -+{ -+ return clk_get_rate(i2s->mod_clk); -+} -+ - static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, - unsigned long parent_rate, - unsigned int sampling_rate, -@@ -259,7 +270,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - unsigned int word_size) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -- unsigned int oversample_rate, clk_rate; -+ unsigned int oversample_rate, clk_rate, bclk_parent_rate; - int bclk_div, mclk_div; - int ret; - -@@ -301,7 +312,8 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - return -EINVAL; - } - -- bclk_div = sun4i_i2s_get_bclk_div(i2s, i2s->mclk_freq, -+ bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); -+ bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate, - rate, word_size); - if (bclk_div < 0) { - dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); -@@ -957,6 +969,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, - .set_chan_cfg = sun4i_i2s_set_chan_cfg, -@@ -972,6 +985,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, - .set_chan_cfg = sun4i_i2s_set_chan_cfg, -@@ -987,6 +1001,7 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, - .set_chan_cfg = sun8i_i2s_set_chan_cfg, -@@ -1005,6 +1020,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), -+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, - .set_chan_cfg = sun8i_i2s_set_chan_cfg, -@@ -1020,6 +1036,7 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, - .set_chan_cfg = sun4i_i2s_set_chan_cfg, --- -2.23.0 - -From c1d3a921d72bd21f266ca28c15213fbe78160a4b Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:16 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Fix the MCLK and BCLK dividers on newer SoCs - -From: Marcus Cooper - -The clock division dividers have changed between the older (A10/A31) and -newer (H3, A64, etc) SoCs. - -While this was addressed through an offset on some SoCs, it was missing -some dividers as well, so the support wasn't perfect. Let's introduce a -pointer in the quirk structure for the divider calculation functions to use -so we can have the proper range now. - -Signed-off-by: Marcus Cooper -[Maxime: Fix the commit log, use a field in the quirk structure] -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/0e5b4abf06cd3202354315201c6af44caeb20236.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 63 ++++++++++++++++++++++++++++--------- - 1 file changed, 49 insertions(+), 14 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index acfcdb26086a..0a7f1d0f7371 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -129,8 +129,6 @@ struct sun4i_i2s; - * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. - * @reg_offset_txdata: offset of the tx fifo. - * @sun4i_i2s_regmap: regmap config to use. -- * @mclk_offset: Value by which mclkdiv needs to be adjusted. -- * @bclk_offset: Value by which bclkdiv needs to be adjusted. - * @field_clkdiv_mclk_en: regmap field to enable mclk output. - * @field_fmt_wss: regmap field to set word select size. - * @field_fmt_sr: regmap field to set sample resolution. -@@ -142,8 +140,6 @@ struct sun4i_i2s_quirks { - bool has_fmt_set_lrck_period; - unsigned int reg_offset_txdata; /* TX FIFO */ - const struct regmap_config *sun4i_i2s_regmap; -- unsigned int mclk_offset; -- unsigned int bclk_offset; - - /* Register fields for i2s */ - struct reg_field field_clkdiv_mclk_en; -@@ -152,6 +148,11 @@ struct sun4i_i2s_quirks { - struct reg_field field_fmt_bclk; - struct reg_field field_fmt_lrclk; - -+ const struct sun4i_i2s_clk_div *bclk_dividers; -+ unsigned int num_bclk_dividers; -+ const struct sun4i_i2s_clk_div *mclk_dividers; -+ unsigned int num_mclk_dividers; -+ - unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *); - s8 (*get_sr)(const struct sun4i_i2s *, int); - s8 (*get_wss)(const struct sun4i_i2s *, int); -@@ -208,6 +209,24 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { - /* TODO - extend divide ratio supported by newer SoCs */ - }; - -+static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = { -+ { .div = 1, .val = 1 }, -+ { .div = 2, .val = 2 }, -+ { .div = 4, .val = 3 }, -+ { .div = 6, .val = 4 }, -+ { .div = 8, .val = 5 }, -+ { .div = 12, .val = 6 }, -+ { .div = 16, .val = 7 }, -+ { .div = 24, .val = 8 }, -+ { .div = 32, .val = 9 }, -+ { .div = 48, .val = 10 }, -+ { .div = 64, .val = 11 }, -+ { .div = 96, .val = 12 }, -+ { .div = 128, .val = 13 }, -+ { .div = 176, .val = 14 }, -+ { .div = 192, .val = 15 }, -+}; -+ - static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) - { - return i2s->mclk_freq; -@@ -223,11 +242,12 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, - unsigned int sampling_rate, - unsigned int word_size) - { -+ const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; - int div = parent_rate / sampling_rate / word_size / 2; - int i; - -- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) { -- const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i]; -+ for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { -+ const struct sun4i_i2s_clk_div *bdiv = ÷rs[i]; - - if (bdiv->div == div) - return bdiv->val; -@@ -240,11 +260,12 @@ static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, - unsigned long parent_rate, - unsigned long mclk_rate) - { -+ const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers; - int div = parent_rate / mclk_rate; - int i; - -- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) { -- const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i]; -+ for (i = 0; i < i2s->variant->num_mclk_dividers; i++) { -+ const struct sun4i_i2s_clk_div *mdiv = ÷rs[i]; - - if (mdiv->div == div) - return mdiv->val; -@@ -326,10 +347,6 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - return -EINVAL; - } - -- /* Adjust the clock division values if needed */ -- bclk_div += i2s->variant->bclk_offset; -- mclk_div += i2s->variant->mclk_offset; -- - regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, - SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | - SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); -@@ -969,6 +986,10 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .bclk_dividers = sun4i_i2s_bclk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), -+ .mclk_dividers = sun4i_i2s_mclk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), - .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, -@@ -985,6 +1006,10 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .bclk_dividers = sun4i_i2s_bclk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), -+ .mclk_dividers = sun4i_i2s_mclk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), - .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, -@@ -1001,6 +1026,10 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .bclk_dividers = sun8i_i2s_clk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -+ .mclk_dividers = sun8i_i2s_clk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), - .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, -@@ -1012,14 +1041,16 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, - .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, -- .mclk_offset = 1, -- .bclk_offset = 2, - .has_fmt_set_lrck_period = true, - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), -+ .bclk_dividers = sun8i_i2s_clk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -+ .mclk_dividers = sun8i_i2s_clk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), - .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, - .get_sr = sun8i_i2s_get_sr_wss, - .get_wss = sun8i_i2s_get_sr_wss, -@@ -1036,6 +1067,10 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), - .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), - .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -+ .bclk_dividers = sun4i_i2s_bclk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), -+ .mclk_dividers = sun4i_i2s_mclk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), - .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, - .get_sr = sun4i_i2s_get_sr, - .get_wss = sun4i_i2s_get_wss, --- -2.23.0 - -From cf2c0e1ce9544df42170fb921f12da82dc0cc8d6 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:17 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: RX and TX counter registers are swapped - -The RX and TX counters registers offset have been swapped, fix that. - -Fixes: fa7c0d13cb26 ("ASoC: sunxi: Add Allwinner A10 Digital Audio driver") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/8b26477560ad5fd8f69e037b167c5e61de5c26a3.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 0a7f1d0f7371..53c95e5289f5 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -76,8 +76,8 @@ - #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) - #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) - --#define SUN4I_I2S_RX_CNT_REG 0x28 --#define SUN4I_I2S_TX_CNT_REG 0x2c -+#define SUN4I_I2S_TX_CNT_REG 0x28 -+#define SUN4I_I2S_RX_CNT_REG 0x2c - - #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 - #define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0) --- -2.23.0 - -From 515fcfbc773632e160f4b94e8df8d278a8d704f7 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:19 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Fix LRCK and BCLK polarity offsets on newer - SoCs - -The LRCK and BCLK polarity offsets on newer SoCs has been -changed, yet the driver didn't take it into account for all of them. - -This was taken into account for the H3, but not the A83t. This was handled -using a reg_field for the H3. - -However, the value in that field will not be the same, so reg_field is not -adapted in that case. Let's change for proper calls with the regular -values. - -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/9cbdde80a299288878e58225df4d7884e0301348.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 118 ++++++++++++++++++------------------ - 1 file changed, 60 insertions(+), 58 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 53c95e5289f5..e3eadfe38aaf 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -46,8 +46,6 @@ - #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) - #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) - #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) --#define SUN4I_I2S_FMT0_POLARITY_INVERTED (1) --#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0) - - #define SUN4I_I2S_FMT1_REG 0x08 - #define SUN4I_I2S_FIFO_TX_REG 0x0c -@@ -98,8 +96,14 @@ - #define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4) - #define SUN8I_I2S_CTRL_MODE_PCM (0 << 4) - -+#define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19) -+#define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19) -+#define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19) - #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) - #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8) -+#define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7) -+#define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) -+#define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7) - - #define SUN8I_I2S_INT_STA_REG 0x0c - #define SUN8I_I2S_FIFO_TX_REG 0x20 -@@ -132,8 +136,6 @@ struct sun4i_i2s; - * @field_clkdiv_mclk_en: regmap field to enable mclk output. - * @field_fmt_wss: regmap field to set word select size. - * @field_fmt_sr: regmap field to set sample resolution. -- * @field_fmt_bclk: regmap field to set clk polarity. -- * @field_fmt_lrclk: regmap field to set frame polarity. - */ - struct sun4i_i2s_quirks { - bool has_reset; -@@ -145,8 +147,6 @@ struct sun4i_i2s_quirks { - struct reg_field field_clkdiv_mclk_en; - struct reg_field field_fmt_wss; - struct reg_field field_fmt_sr; -- struct reg_field field_fmt_bclk; -- struct reg_field field_fmt_lrclk; - - const struct sun4i_i2s_clk_div *bclk_dividers; - unsigned int num_bclk_dividers; -@@ -176,8 +176,6 @@ struct sun4i_i2s { - struct regmap_field *field_clkdiv_mclk_en; - struct regmap_field *field_fmt_wss; - struct regmap_field *field_fmt_sr; -- struct regmap_field *field_fmt_bclk; -- struct regmap_field *field_fmt_lrclk; - - const struct sun4i_i2s_quirks *variant; - }; -@@ -498,6 +496,33 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, - { - u32 val; - -+ /* DAI clock polarity */ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_IB_IF: -+ /* Invert both clocks */ -+ val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED | -+ SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_IB_NF: -+ /* Invert bit clock */ -+ val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_NB_IF: -+ /* Invert frame clock */ -+ val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_NB_NF: -+ val = 0; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, -+ SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK | -+ SUN4I_I2S_FMT0_BCLK_POLARITY_MASK, -+ val); -+ - /* DAI Mode */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_I2S: -@@ -545,6 +570,33 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, - u32 mode, val; - u8 offset; - -+ /* DAI clock polarity */ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_IB_IF: -+ /* Invert both clocks */ -+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | -+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_IB_NF: -+ /* Invert bit clock */ -+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_NB_IF: -+ /* Invert frame clock */ -+ val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ break; -+ case SND_SOC_DAIFMT_NB_NF: -+ val = 0; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, -+ SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK | -+ SUN8I_I2S_FMT0_BCLK_POLARITY_MASK, -+ val); -+ - /* DAI Mode */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_I2S: -@@ -601,36 +653,8 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, - static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -- u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; -- u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; - int ret; - -- /* DAI clock polarity */ -- switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -- case SND_SOC_DAIFMT_IB_IF: -- /* Invert both clocks */ -- bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; -- lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; -- break; -- case SND_SOC_DAIFMT_IB_NF: -- /* Invert bit clock */ -- bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; -- break; -- case SND_SOC_DAIFMT_NB_IF: -- /* Invert frame clock */ -- lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; -- break; -- case SND_SOC_DAIFMT_NB_NF: -- break; -- default: -- dev_err(dai->dev, "Unsupported clock polarity: %d\n", -- fmt & SND_SOC_DAIFMT_INV_MASK); -- return -EINVAL; -- } -- -- regmap_field_write(i2s->field_fmt_bclk, bclk_polarity); -- regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity); -- - ret = i2s->variant->set_fmt(i2s, fmt); - if (ret) { - dev_err(dai->dev, "Unsupported format configuration\n"); -@@ -984,8 +1008,6 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), -- .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), -- .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .bclk_dividers = sun4i_i2s_bclk_div, - .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), - .mclk_dividers = sun4i_i2s_mclk_div, -@@ -1004,8 +1026,6 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), -- .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), -- .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .bclk_dividers = sun4i_i2s_bclk_div, - .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), - .mclk_dividers = sun4i_i2s_mclk_div, -@@ -1024,8 +1044,6 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), -- .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), -- .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .bclk_dividers = sun8i_i2s_clk_div, - .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), - .mclk_dividers = sun8i_i2s_clk_div, -@@ -1045,8 +1063,6 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), -- .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), -- .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), - .bclk_dividers = sun8i_i2s_clk_div, - .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), - .mclk_dividers = sun8i_i2s_clk_div, -@@ -1065,8 +1081,6 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), -- .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), -- .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), - .bclk_dividers = sun4i_i2s_bclk_div, - .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), - .mclk_dividers = sun4i_i2s_mclk_div, -@@ -1099,18 +1113,6 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, - if (IS_ERR(i2s->field_fmt_sr)) - return PTR_ERR(i2s->field_fmt_sr); - -- i2s->field_fmt_bclk = -- devm_regmap_field_alloc(dev, i2s->regmap, -- i2s->variant->field_fmt_bclk); -- if (IS_ERR(i2s->field_fmt_bclk)) -- return PTR_ERR(i2s->field_fmt_bclk); -- -- i2s->field_fmt_lrclk = -- devm_regmap_field_alloc(dev, i2s->regmap, -- i2s->variant->field_fmt_lrclk); -- if (IS_ERR(i2s->field_fmt_lrclk)) -- return PTR_ERR(i2s->field_fmt_lrclk); -- - return 0; - } - --- -2.23.0 - -From dd657eae8164f7e4bafe8b875031a7c6c50646a9 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:20 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Fix the LRCK polarity - -The LRCK polarity "normal" polarity in the I2S/TDM specs and in the -Allwinner datasheet are not the same. In the case where the i2s controller -is being used as the LRCK master, it's pretty clear when looked at under a -scope. - -Let's fix this, and add a comment to clear up as much the confusion as -possible. - -Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3") -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/e03fb6b2a916223070b9f18405b0ef117a452ff4.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index e3eadfe38aaf..29b5eacd3abe 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -570,23 +570,29 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, - u32 mode, val; - u8 offset; - -- /* DAI clock polarity */ -+ /* -+ * DAI clock polarity -+ * -+ * The setup for LRCK contradicts the datasheet, but under a -+ * scope it's clear that the LRCK polarity is reversed -+ * compared to the expected polarity on the bus. -+ */ - switch (fmt & SND_SOC_DAIFMT_INV_MASK) { - case SND_SOC_DAIFMT_IB_IF: - /* Invert both clocks */ -- val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | -- SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; - break; - case SND_SOC_DAIFMT_IB_NF: - /* Invert bit clock */ -- val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; -+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | -+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; - break; - case SND_SOC_DAIFMT_NB_IF: - /* Invert frame clock */ -- val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; -+ val = 0; - break; - case SND_SOC_DAIFMT_NB_NF: -- val = 0; -+ val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; - break; - default: - return -EINVAL; --- -2.23.0 - -From 2e04fc4dbf50195262aa5a2ae6d35baa5b598cae Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:21 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Fix WSS and SR fields for the A83t - -The A83t has the same bit fields offsets than the A10 and A31, while this -was the first device with the new layout, fix that. - -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/d93f0943cc39d880750daf459a0eeab34c63518e.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 29b5eacd3abe..59d809df8d2a 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1048,8 +1048,8 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, - .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), -- .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), -- .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), -+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), -+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), - .bclk_dividers = sun8i_i2s_clk_div, - .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), - .mclk_dividers = sun8i_i2s_clk_div, --- -2.23.0 - -From bf943d527987c38f6fb11f9515e0cf2839286eb8 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:22 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Fix MCLK Enable bit offset on A83t - -The A83t, unlike previous SoCs, has the MCLK enable bit at the 8th bit of -the CLK_DIV register, unlike what is declared in the driver. - -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/43b07f8cd8e0e280c64ce61d57c307678c923e9b.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 59d809df8d2a..0fce3c476772 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1047,7 +1047,7 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, - .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, -- .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), -+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), - .bclk_dividers = sun8i_i2s_clk_div, --- -2.23.0 - -From 69e450e50ca6dde566f3ac3f2c329fb0492441ef Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:23 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Fix the LRCK period on A83t - -Unlike the previous SoCs, the A83t, like the newer ones, need the LRCK -bitfield to be set. Let's add it. - -Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/6a0ee0bc1375bcb53840d3fb2d2f3d9732b8e57e.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 0fce3c476772..9468584f4eb0 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1047,6 +1047,7 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, - .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, -+ .has_fmt_set_lrck_period = true, - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), --- -2.23.0 - -From 3e9acd7ac6933cdc20c441bbf9a38ed9e42e1490 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:24 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Remove duplicated quirks structure - -The A83t and H3 have the same quirks, so it doesn't make sense to duplicate -the quirks structure. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/5ade5de27d23918c5ef30387c23aead951d5ad64.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 21 +-------------------- - 1 file changed, 1 insertion(+), 20 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 9468584f4eb0..4c636f1cf7dc 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1062,25 +1062,6 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .set_fmt = sun8i_i2s_set_soc_fmt, - }; - --static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { -- .has_reset = true, -- .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, -- .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, -- .has_fmt_set_lrck_period = true, -- .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), -- .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), -- .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), -- .bclk_dividers = sun8i_i2s_clk_div, -- .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -- .mclk_dividers = sun8i_i2s_clk_div, -- .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -- .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, -- .get_sr = sun8i_i2s_get_sr_wss, -- .get_wss = sun8i_i2s_get_sr_wss, -- .set_chan_cfg = sun8i_i2s_set_chan_cfg, -- .set_fmt = sun8i_i2s_set_soc_fmt, --}; -- - static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, -@@ -1262,7 +1243,7 @@ static const struct of_device_id sun4i_i2s_match[] = { - }, - { - .compatible = "allwinner,sun8i-h3-i2s", -- .data = &sun8i_h3_i2s_quirks, -+ .data = &sun8i_a83t_i2s_quirks, - }, - { - .compatible = "allwinner,sun50i-a64-codec-i2s", --- -2.23.0 - -From 0083a507a78fdfa868acc0709408b59e72488a61 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:25 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Pass the channels number as an argument - -The channels number have been hardcoded to 2 so far, while the controller -supports more than that. - -Remove the instance where it has been hardcoded to compute the BCLK -divider, and pass it through as an argument to ease further support of more -channels. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/48887cf7abfaab6597db233b24d7a088a913e48a.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 4c636f1cf7dc..6b172dfbc25d 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -238,10 +238,11 @@ static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) - static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, - unsigned long parent_rate, - unsigned int sampling_rate, -+ unsigned int channels, - unsigned int word_size) - { - const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; -- int div = parent_rate / sampling_rate / word_size / 2; -+ int div = parent_rate / sampling_rate / word_size / channels; - int i; - - for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { -@@ -286,6 +287,7 @@ static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) - - static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - unsigned int rate, -+ unsigned int channels, - unsigned int word_size) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -@@ -333,7 +335,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - - bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); - bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate, -- rate, word_size); -+ rate, channels, word_size); - if (bclk_div < 0) { - dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); - return -EINVAL; -@@ -488,7 +490,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - regmap_field_write(i2s->field_fmt_sr, sr); - - return sun4i_i2s_set_clk_rate(dai, params_rate(params), -- params_width(params)); -+ 2, params_width(params)); - } - - static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, --- -2.23.0 - -From bbf9a127abca4aac5cc75f882bc7efcc398e86ae Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:26 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Support more channels - -We've been limited to 2 channels in the driver while the controller -supports from 1 to 8 channels, in both capture and playback. let's remove -the hardcoded checks and numbers, and extend the range of channel numbers -we can use. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/27d9de5cd56f3a544851b8cd8af08bf836d19637.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 17 ++++++----------- - 1 file changed, 6 insertions(+), 11 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 6b172dfbc25d..9e691baee1e8 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -400,9 +400,6 @@ static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, - { - unsigned int channels = params_channels(params); - -- if (channels != 2) -- return -EINVAL; -- - /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); - regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); -@@ -423,9 +420,6 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, - { - unsigned int channels = params_channels(params); - -- if (channels != 2) -- return -EINVAL; -- - /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); - regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); -@@ -458,6 +452,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int channels = params_channels(params); - int ret, sr, wss; - u32 width; - -@@ -490,7 +485,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - regmap_field_write(i2s->field_fmt_sr, sr); - - return sun4i_i2s_set_clk_rate(dai, params_rate(params), -- 2, params_width(params)); -+ channels, params_width(params)); - } - - static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, -@@ -814,15 +809,15 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = { - .probe = sun4i_i2s_dai_probe, - .capture = { - .stream_name = "Capture", -- .channels_min = 2, -- .channels_max = 2, -+ .channels_min = 1, -+ .channels_max = 8, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .playback = { - .stream_name = "Playback", -- .channels_min = 2, -- .channels_max = 2, -+ .channels_min = 1, -+ .channels_max = 8, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, --- -2.23.0 - -From 137befe19f310400a8b20fd8a4ce8c4141aafde0 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Mon, 19 Aug 2019 21:25:27 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Add support for TDM slots - -The i2s controller supports TDM, for up to 8 slots. Let's support the TDM -API. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/26392af30b3e7b31ee48d5b867d45be8675db046.1566242458.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 40 +++++++++++++++++++++++++++++++------ - 1 file changed, 34 insertions(+), 6 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 9e691baee1e8..8326b8cfa569 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -168,6 +168,8 @@ struct sun4i_i2s { - struct reset_control *rst; - - unsigned int mclk_freq; -+ unsigned int slots; -+ unsigned int slot_width; - - struct snd_dmaengine_dai_dma_data capture_dma_data; - struct snd_dmaengine_dai_dma_data playback_dma_data; -@@ -287,7 +289,7 @@ static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) - - static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - unsigned int rate, -- unsigned int channels, -+ unsigned int slots, - unsigned int word_size) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -@@ -335,7 +337,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - - bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); - bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate, -- rate, channels, word_size); -+ rate, slots, word_size); - if (bclk_div < 0) { - dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); - return -EINVAL; -@@ -419,6 +421,10 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, - const struct snd_pcm_hw_params *params) - { - unsigned int channels = params_channels(params); -+ unsigned int slots = channels; -+ -+ if (i2s->slots) -+ slots = i2s->slots; - - /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); -@@ -428,7 +434,6 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, - SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); -- - regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, - SUN4I_I2S_CHAN_SEL_MASK, - SUN4I_I2S_CHAN_SEL(channels)); -@@ -452,10 +457,18 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int word_size = params_width(params); - unsigned int channels = params_channels(params); -+ unsigned int slots = channels; - int ret, sr, wss; - u32 width; - -+ if (i2s->slots) -+ slots = i2s->slots; -+ -+ if (i2s->slot_width) -+ word_size = i2s->slot_width; -+ - ret = i2s->variant->set_chan_cfg(i2s, params); - if (ret < 0) { - dev_err(dai->dev, "Invalid channel configuration\n"); -@@ -477,15 +490,14 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - if (sr < 0) - return -EINVAL; - -- wss = i2s->variant->get_wss(i2s, params_width(params)); -+ wss = i2s->variant->get_wss(i2s, word_size); - if (wss < 0) - return -EINVAL; - - regmap_field_write(i2s->field_fmt_wss, wss); - regmap_field_write(i2s->field_fmt_sr, sr); - -- return sun4i_i2s_set_clk_rate(dai, params_rate(params), -- channels, params_width(params)); -+ return sun4i_i2s_set_clk_rate(dai, params_rate(params), slots, word_size); - } - - static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, -@@ -785,10 +797,26 @@ static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, - return 0; - } - -+static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai, -+ unsigned int tx_mask, unsigned int rx_mask, -+ int slots, int slot_width) -+{ -+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ if (slots > 8) -+ return -EINVAL; -+ -+ i2s->slots = slots; -+ i2s->slot_width = slot_width; -+ -+ return 0; -+} -+ - static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { - .hw_params = sun4i_i2s_hw_params, - .set_fmt = sun4i_i2s_set_fmt, - .set_sysclk = sun4i_i2s_set_sysclk, -+ .set_tdm_slot = sun4i_i2s_set_tdm_slot, - .trigger = sun4i_i2s_trigger, - }; - --- -2.23.0 - -From 5389f4765789e4ecf9831bc968562befdd2f3bee Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Wed, 21 Aug 2019 15:06:53 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Use the physical / slot width for the clocks - -The clock dividers function has been using the word size to compute the -clock rate at which it's supposed to be running, but the proper formula -would be to use the physical width and / or slot width in TDM. - -It doesn't make any difference at the moment since all the formats -supported have the same sample width and physical width, but it's not going -to last forever. - -Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/41a359d9885f397e066816961e5e3236afcbe0a1.1566392800.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 12 +++++++----- - 1 file changed, 7 insertions(+), 5 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 8326b8cfa569..cdc3fa60ff33 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -290,7 +290,7 @@ static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) - static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - unsigned int rate, - unsigned int slots, -- unsigned int word_size) -+ unsigned int slot_width) - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); - unsigned int oversample_rate, clk_rate, bclk_parent_rate; -@@ -337,7 +337,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - - bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); - bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate, -- rate, slots, word_size); -+ rate, slots, slot_width); - if (bclk_div < 0) { - dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); - return -EINVAL; -@@ -458,6 +458,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - { - struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); - unsigned int word_size = params_width(params); -+ unsigned int slot_width = params_physical_width(params); - unsigned int channels = params_channels(params); - unsigned int slots = channels; - int ret, sr, wss; -@@ -467,7 +468,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - slots = i2s->slots; - - if (i2s->slot_width) -- word_size = i2s->slot_width; -+ slot_width = i2s->slot_width; - - ret = i2s->variant->set_chan_cfg(i2s, params); - if (ret < 0) { -@@ -490,14 +491,15 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - if (sr < 0) - return -EINVAL; - -- wss = i2s->variant->get_wss(i2s, word_size); -+ wss = i2s->variant->get_wss(i2s, slot_width); - if (wss < 0) - return -EINVAL; - - regmap_field_write(i2s->field_fmt_wss, wss); - regmap_field_write(i2s->field_fmt_sr, sr); - -- return sun4i_i2s_set_clk_rate(dai, params_rate(params), slots, word_size); -+ return sun4i_i2s_set_clk_rate(dai, params_rate(params), -+ slots, slot_width); - } - - static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, --- -2.23.0 - -From 9e8a93ac27d101e0ace024196a4bc3386568cc00 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Wed, 21 Aug 2019 15:06:54 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Use the actual format width instead of an - hardcoded one - -The LRCK period field in the FMT0 register holds the number of LRCK period -for one channel in I2S mode. - -This has been hardcoded to 32, while it really should be the physical width -of the format, which creates an improper clock when using a 16bit format, -with the i2s controller as LRCK master. - -Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/f08a0c3605cd1d79752b38d704690190183f7865.1566392800.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index cdc3fa60ff33..9ef784b8867c 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -359,7 +359,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - if (i2s->variant->has_fmt_set_lrck_period) - regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, - SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, -- SUN8I_I2S_FMT0_LRCK_PERIOD(32)); -+ SUN8I_I2S_FMT0_LRCK_PERIOD(slot_width)); - - return 0; - } --- -2.23.0 - -From 84884c7ad5e8794aa19e48eaa8de93f4e1d26af9 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Wed, 21 Aug 2019 15:06:55 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Replace call to params_width by local - variable - -The sun4i_i2s_hw_params function already has a variable holding the value -returned by params_width, so let's just use that variable instead of -calling params_width multiple times. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/f85a1c1e014080a4bbc3abd19bc8fdcb86f0981a.1566392800.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 9ef784b8867c..69162af9fd65 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -487,7 +487,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - } - i2s->playback_dma_data.addr_width = width; - -- sr = i2s->variant->get_sr(i2s, params_width(params)); -+ sr = i2s->variant->get_sr(i2s, word_size); - if (sr < 0) - return -EINVAL; - --- -2.23.0 - -From 7ae7834ec446e5f7fed9bb990d16354853a206d0 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Wed, 21 Aug 2019 15:06:56 +0200 -Subject: [PATCH] ASoC: sun4i-i2s: Add support for DSP formats - -In addition to the I2S format, the controller also supports the DSP_* -formats. - -This requires some extra care on the LRCK period calculation, since the -controller, with the PCM formats, require that the value set is no longer -the periods of LRCK for a single channel, but for all of them. - -Let's add the code to deal with this, and support the DSP_A and DSP_B -formats. - -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/5562db1ac8759f12b1b87c3258223eed629ef771.1566392800.git-series.maxime.ripard@bootlin.com -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 44 +++++++++++++++++++++++++++++-------- - 1 file changed, 35 insertions(+), 9 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 69162af9fd65..57bf2a33753e 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -130,7 +130,6 @@ struct sun4i_i2s; - * struct sun4i_i2s_quirks - Differences between SoC variants. - * - * @has_reset: SoC needs reset deasserted. -- * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. - * @reg_offset_txdata: offset of the tx fifo. - * @sun4i_i2s_regmap: regmap config to use. - * @field_clkdiv_mclk_en: regmap field to enable mclk output. -@@ -139,7 +138,6 @@ struct sun4i_i2s; - */ - struct sun4i_i2s_quirks { - bool has_reset; -- bool has_fmt_set_lrck_period; - unsigned int reg_offset_txdata; /* TX FIFO */ - const struct regmap_config *sun4i_i2s_regmap; - -@@ -167,6 +165,7 @@ struct sun4i_i2s { - struct regmap *regmap; - struct reset_control *rst; - -+ unsigned int format; - unsigned int mclk_freq; - unsigned int slots; - unsigned int slot_width; -@@ -355,12 +354,6 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, - - regmap_field_write(i2s->field_clkdiv_mclk_en, 1); - -- /* Set sync period */ -- if (i2s->variant->has_fmt_set_lrck_period) -- regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, -- SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, -- SUN8I_I2S_FMT0_LRCK_PERIOD(slot_width)); -- - return 0; - } - -@@ -422,6 +415,7 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, - { - unsigned int channels = params_channels(params); - unsigned int slots = channels; -+ unsigned int lrck_period; - - if (i2s->slots) - slots = i2s->slots; -@@ -445,6 +439,26 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, - SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, - SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); - -+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_DSP_A: -+ case SND_SOC_DAIFMT_DSP_B: -+ case SND_SOC_DAIFMT_LEFT_J: -+ case SND_SOC_DAIFMT_RIGHT_J: -+ lrck_period = params_physical_width(params) * slots; -+ break; -+ -+ case SND_SOC_DAIFMT_I2S: -+ lrck_period = params_physical_width(params); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, -+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, -+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period)); -+ - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, - SUN8I_I2S_TX_CHAN_EN_MASK, - SUN8I_I2S_TX_CHAN_EN(channels)); -@@ -616,6 +630,16 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, - - /* DAI Mode */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_DSP_A: -+ mode = SUN8I_I2S_CTRL_MODE_PCM; -+ offset = 1; -+ break; -+ -+ case SND_SOC_DAIFMT_DSP_B: -+ mode = SUN8I_I2S_CTRL_MODE_PCM; -+ offset = 0; -+ break; -+ - case SND_SOC_DAIFMT_I2S: - mode = SUN8I_I2S_CTRL_MODE_LEFT; - offset = 1; -@@ -684,6 +708,9 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) - SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, - SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | - SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); -+ -+ i2s->format = fmt; -+ - return 0; - } - -@@ -1074,7 +1101,6 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, - .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, -- .has_fmt_set_lrck_period = true, - .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), - .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), - .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), --- -2.23.0 - -From 455b1d42e82c6027b9763f0055b54e45ff6cd7fd Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Tue, 27 Aug 2019 11:32:05 +0200 -Subject: [PATCH] ASoC: sunxi: Revert initial A83t support - -This reverts commit 3e9acd7ac6933c (ASoC: sun4i-i2s: Remove -duplicated quirks structure"). - -It turns out that while one I2S controller is described in the A83t -datasheet, the driver supports another, undocumented, one that has been -inherited from the older SoCs, while the documented one uses the new -design. - -Fixes: 3e9acd7ac693 ("ASoC: sun4i-i2s: Remove duplicated quirks structure") -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/20190827093206.17919-1-mripard@kernel.org -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 25 ++++++++++++++++++++++++- - 1 file changed, 24 insertions(+), 1 deletion(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index 57bf2a33753e..a6a3f772fdf0 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1097,6 +1097,11 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { - .set_fmt = sun4i_i2s_set_soc_fmt, - }; - -+/* -+ * This doesn't describe the TDM controller documented in the A83t -+ * datasheet, but the three undocumented I2S controller that use the -+ * older design. -+ */ - static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, -@@ -1115,6 +1120,24 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .set_fmt = sun8i_i2s_set_soc_fmt, - }; - -+static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { -+ .has_reset = true, -+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, -+ .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, -+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), -+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), -+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), -+ .bclk_dividers = sun8i_i2s_clk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -+ .mclk_dividers = sun8i_i2s_clk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, -+ .get_sr = sun8i_i2s_get_sr_wss, -+ .get_wss = sun8i_i2s_get_sr_wss, -+ .set_chan_cfg = sun8i_i2s_set_chan_cfg, -+ .set_fmt = sun8i_i2s_set_soc_fmt, -+}; -+ - static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, -@@ -1296,7 +1319,7 @@ static const struct of_device_id sun4i_i2s_match[] = { - }, - { - .compatible = "allwinner,sun8i-h3-i2s", -- .data = &sun8i_a83t_i2s_quirks, -+ .data = &sun8i_h3_i2s_quirks, - }, - { - .compatible = "allwinner,sun50i-a64-codec-i2s", --- -2.23.0 - -From 9ec05d4723bf83dd272cef5ccf508e5fe4d30fa3 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Tue, 27 Aug 2019 14:31:31 +0200 -Subject: [PATCH] ASoC: sun4i: Revert A83t description - -The last set of reworks included some fixes to change the A83t behaviour -and "fix" it. - -It turns out that the controller described in the datasheet and the one -supported here are not the same, yet the A83t has the two of them, and the -one supported in the driver wasn't the one described in the datasheet. - -Fix this by reintroducing the proper quirks. - -Fixes: 69e450e50ca6 ("ASoC: sun4i-i2s: Fix the LRCK period on A83t") -Fixes: bf943d527987 ("ASoC: sun4i-i2s: Fix MCLK Enable bit offset on A83t") -Fixes: 2e04fc4dbf50 ("ASoC: sun4i-i2s: Fix WSS and SR fields for the A83t") -Fixes: 515fcfbc7736 ("ASoC: sun4i-i2s: Fix LRCK and BCLK polarity offsets on newer SoCs") -Fixes: c1d3a921d72b ("ASoC: sun4i-i2s: Fix the MCLK and BCLK dividers on newer SoCs") -Fixes: fb19739d7f68 ("ASoC: sun4i-i2s: Use module clock as BCLK parent on newer SoCs") -Fixes: 71137bcd0a9a ("ASoC: sun4i-i2s: Move the format configuration to a callback") -Fixes: d70be625f25a ("ASoC: sun4i-i2s: Move the channel configuration to a callback") -Reported-by: Chen-Yu Tsai -Tested-by: Chen-Yu Tsai -Signed-off-by: Maxime Ripard -Link: https://lore.kernel.org/r/20190827123131.29129-2-mripard@kernel.org -Signed-off-by: Mark Brown ---- - sound/soc/sunxi/sun4i-i2s.c | 24 ++++++++++++------------ - 1 file changed, 12 insertions(+), 12 deletions(-) - -diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c -index a6a3f772fdf0..d0a8d5810c0a 100644 ---- a/sound/soc/sunxi/sun4i-i2s.c -+++ b/sound/soc/sunxi/sun4i-i2s.c -@@ -1106,18 +1106,18 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { - .has_reset = true, - .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, - .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, -- .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), -- .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), -- .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), -- .bclk_dividers = sun8i_i2s_clk_div, -- .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -- .mclk_dividers = sun8i_i2s_clk_div, -- .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), -- .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, -- .get_sr = sun8i_i2s_get_sr_wss, -- .get_wss = sun8i_i2s_get_sr_wss, -- .set_chan_cfg = sun8i_i2s_set_chan_cfg, -- .set_fmt = sun8i_i2s_set_soc_fmt, -+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), -+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), -+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), -+ .bclk_dividers = sun4i_i2s_bclk_div, -+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), -+ .mclk_dividers = sun4i_i2s_mclk_div, -+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), -+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, -+ .get_sr = sun4i_i2s_get_sr, -+ .get_wss = sun4i_i2s_get_wss, -+ .set_chan_cfg = sun4i_i2s_set_chan_cfg, -+ .set_fmt = sun4i_i2s_set_soc_fmt, - }; - - static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { --- -2.23.0 - -From 633eadc9ba1e9a56be09ef94f14578a9839d3634 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 30 May 2019 18:15:13 -0300 -Subject: [PATCH] media: cedrus: Remove dst_bufs from context - -This array is just duplicated capture buffer queue. Remove it and adjust -code to look into capture buffer queue instead. - -Signed-off-by: Jernej Skrabec -Acked-by: Maxime Ripard -Acked-by: Paul Kocialkowski -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus.h | 4 +--- - .../staging/media/sunxi/cedrus/cedrus_h264.c | 4 ++-- - .../staging/media/sunxi/cedrus/cedrus_video.c | 22 ------------------- - 3 files changed, 3 insertions(+), 27 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 3f476d0fd981..d8e6777e5e27 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -100,8 +100,6 @@ struct cedrus_ctx { - struct v4l2_ctrl_handler hdl; - struct v4l2_ctrl **ctrls; - -- struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; -- - union { - struct { - void *mv_col_buf; -@@ -187,7 +185,7 @@ static inline dma_addr_t cedrus_dst_buf_addr(struct cedrus_ctx *ctx, - if (index < 0) - return 0; - -- buf = ctx->dst_bufs[index]; -+ buf = ctx->fh.m2m_ctx->cap_q_ctx.q.bufs[index]; - return buf ? cedrus_buf_addr(buf, &ctx->dst_fmt, plane) : 0; - } - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index a30bb283f69f..d6a782703c9b 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -118,7 +118,7 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, - if (buf_idx < 0) - continue; - -- cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[buf_idx]); -+ cedrus_buf = vb2_to_cedrus_buffer(cap_q->bufs[buf_idx]); - position = cedrus_buf->codec.h264.position; - used_dpbs |= BIT(position); - -@@ -193,7 +193,7 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, - if (buf_idx < 0) - continue; - -- ref_buf = to_vb2_v4l2_buffer(ctx->dst_bufs[buf_idx]); -+ ref_buf = to_vb2_v4l2_buffer(cap_q->bufs[buf_idx]); - cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); - position = cedrus_buf->codec.h264.position; - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index e2b530b1a956..681dfe3367a6 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -411,26 +411,6 @@ static void cedrus_queue_cleanup(struct vb2_queue *vq, u32 state) - } - } - --static int cedrus_buf_init(struct vb2_buffer *vb) --{ -- struct vb2_queue *vq = vb->vb2_queue; -- struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); -- -- if (!V4L2_TYPE_IS_OUTPUT(vq->type)) -- ctx->dst_bufs[vb->index] = vb; -- -- return 0; --} -- --static void cedrus_buf_cleanup(struct vb2_buffer *vb) --{ -- struct vb2_queue *vq = vb->vb2_queue; -- struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); -- -- if (!V4L2_TYPE_IS_OUTPUT(vq->type)) -- ctx->dst_bufs[vb->index] = NULL; --} -- - static int cedrus_buf_out_validate(struct vb2_buffer *vb) - { - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); -@@ -517,8 +497,6 @@ static void cedrus_buf_request_complete(struct vb2_buffer *vb) - static struct vb2_ops cedrus_qops = { - .queue_setup = cedrus_queue_setup, - .buf_prepare = cedrus_buf_prepare, -- .buf_init = cedrus_buf_init, -- .buf_cleanup = cedrus_buf_cleanup, - .buf_queue = cedrus_buf_queue, - .buf_out_validate = cedrus_buf_out_validate, - .buf_request_complete = cedrus_buf_request_complete, --- -2.23.0 - -From 7bb3c32abd7bafd346f667cccb7dfe9686f14ddd Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Fri, 16 Aug 2019 13:01:23 -0300 -Subject: [PATCH] media: uapi: h264: Rename pixel format - -The V4L2_PIX_FMT_H264_SLICE_RAW name was originally suggested -because the pixel format would represent H264 slices without any -start code. - -However, as we will now introduce a start code menu control, -give the pixel format a more meaningful name, while it's -still early enough to do so. - -Signed-off-by: Ezequiel Garcia -Tested-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/pixfmt-compressed.rst | 4 ++-- - drivers/media/v4l2-core/v4l2-ioctl.c | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus_video.c | 6 +++--- - include/media/h264-ctrls.h | 2 +- - 5 files changed, 8 insertions(+), 8 deletions(-) - -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index f52a7b67023d..9b65473a2288 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -52,9 +52,9 @@ Compressed Formats - - ``V4L2_PIX_FMT_H264_MVC`` - - 'M264' - - H264 MVC video elementary stream. -- * .. _V4L2-PIX-FMT-H264-SLICE-RAW: -+ * .. _V4L2-PIX-FMT-H264-SLICE: - -- - ``V4L2_PIX_FMT_H264_SLICE_RAW`` -+ - ``V4L2_PIX_FMT_H264_SLICE`` - - 'S264' - - H264 parsed slice data, without the start code and as - extracted from the H264 bitstream. This format is adapted for -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index bb5b4926538a..39f10621c91b 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1343,7 +1343,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_H264: descr = "H.264"; break; - case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; - case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; -- case V4L2_PIX_FMT_H264_SLICE_RAW: descr = "H.264 Parsed Slice Data"; break; -+ case V4L2_PIX_FMT_H264_SLICE: descr = "H.264 Parsed Slice Data"; break; - case V4L2_PIX_FMT_H263: descr = "H.263"; break; - case V4L2_PIX_FMT_MPEG1: descr = "MPEG-1 ES"; break; - case V4L2_PIX_FMT_MPEG2: descr = "MPEG-2 ES"; break; -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index bdad87eb9d79..56ca4c9ad01c 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -46,7 +46,7 @@ void cedrus_device_run(void *priv) - V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); - break; - -- case V4L2_PIX_FMT_H264_SLICE_RAW: -+ case V4L2_PIX_FMT_H264_SLICE: - run.h264.decode_params = cedrus_find_control_data(ctx, - V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); - run.h264.pps = cedrus_find_control_data(ctx, -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index 681dfe3367a6..eeee3efd247b 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -38,7 +38,7 @@ static struct cedrus_format cedrus_formats[] = { - .directions = CEDRUS_DECODE_SRC, - }, - { -- .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, -+ .pixelformat = V4L2_PIX_FMT_H264_SLICE, - .directions = CEDRUS_DECODE_SRC, - }, - { -@@ -104,7 +104,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - - switch (pix_fmt->pixelformat) { - case V4L2_PIX_FMT_MPEG2_SLICE: -- case V4L2_PIX_FMT_H264_SLICE_RAW: -+ case V4L2_PIX_FMT_H264_SLICE: - /* Zero bytes per line for encoded source. */ - bytesperline = 0; - -@@ -449,7 +449,7 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) - ctx->current_codec = CEDRUS_CODEC_MPEG2; - break; - -- case V4L2_PIX_FMT_H264_SLICE_RAW: -+ case V4L2_PIX_FMT_H264_SLICE: - ctx->current_codec = CEDRUS_CODEC_H264; - break; - -diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h -index e1404d78d6ff..6160a69c0143 100644 ---- a/include/media/h264-ctrls.h -+++ b/include/media/h264-ctrls.h -@@ -14,7 +14,7 @@ - #include - - /* Our pixel format isn't stable at the moment */ --#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ -+#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ - - /* - * This is put insanely high to avoid conflicting with controls that --- -2.23.0 - -From 3f715c64be6e6e1e1bb140fb1179ab0a712f94c3 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Fri, 16 Aug 2019 13:01:27 -0300 -Subject: [PATCH] media: cedrus: Cleanup control initialization - -In order to introduce other controls, the control initialization -needs to support an initial struct v4l2_ctrl_control. - -While here, let's cleanup the control initialization, -removing unneeded fields. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus.c | 45 +++++++++++---------- - drivers/staging/media/sunxi/cedrus/cedrus.h | 3 +- - 2 files changed, 25 insertions(+), 23 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index 370937edfc14..7bdc413bf727 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -29,44 +29,51 @@ - - static const struct cedrus_control cedrus_controls[] = { - { -- .id = V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS, -- .elem_size = sizeof(struct v4l2_ctrl_mpeg2_slice_params), -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS, -+ }, - .codec = CEDRUS_CODEC_MPEG2, - .required = true, - }, - { -- .id = V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION, -- .elem_size = sizeof(struct v4l2_ctrl_mpeg2_quantization), -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION, -+ }, - .codec = CEDRUS_CODEC_MPEG2, - .required = false, - }, - { -- .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, -- .elem_size = sizeof(struct v4l2_ctrl_h264_decode_params), -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, -+ }, - .codec = CEDRUS_CODEC_H264, - .required = true, - }, - { -- .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -- .elem_size = sizeof(struct v4l2_ctrl_h264_slice_params), -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -+ }, - .codec = CEDRUS_CODEC_H264, - .required = true, - }, - { -- .id = V4L2_CID_MPEG_VIDEO_H264_SPS, -- .elem_size = sizeof(struct v4l2_ctrl_h264_sps), -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, -+ }, - .codec = CEDRUS_CODEC_H264, - .required = true, - }, - { -- .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -- .elem_size = sizeof(struct v4l2_ctrl_h264_pps), -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -+ }, - .codec = CEDRUS_CODEC_H264, - .required = true, - }, - { -- .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, -- .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, -+ }, - .codec = CEDRUS_CODEC_H264, - .required = true, - }, -@@ -106,12 +113,8 @@ static int cedrus_init_ctrls(struct cedrus_dev *dev, struct cedrus_ctx *ctx) - return -ENOMEM; - - for (i = 0; i < CEDRUS_CONTROLS_COUNT; i++) { -- struct v4l2_ctrl_config cfg = {}; -- -- cfg.elem_size = cedrus_controls[i].elem_size; -- cfg.id = cedrus_controls[i].id; -- -- ctrl = v4l2_ctrl_new_custom(hdl, &cfg, NULL); -+ ctrl = v4l2_ctrl_new_custom(hdl, &cedrus_controls[i].cfg, -+ NULL); - if (hdl->error) { - v4l2_err(&dev->v4l2_dev, - "Failed to create new custom control\n"); -@@ -178,7 +181,7 @@ static int cedrus_request_validate(struct media_request *req) - continue; - - ctrl_test = v4l2_ctrl_request_hdl_ctrl_find(hdl, -- cedrus_controls[i].id); -+ cedrus_controls[i].cfg.id); - if (!ctrl_test) { - v4l2_info(&ctx->dev->v4l2_dev, - "Missing required codec control\n"); -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index d8e6777e5e27..2f017a651848 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -49,8 +49,7 @@ enum cedrus_h264_pic_type { - }; - - struct cedrus_control { -- u32 id; -- u32 elem_size; -+ struct v4l2_ctrl_config cfg; - enum cedrus_codec codec; - unsigned char required:1; - }; --- -2.23.0 - -From 341772b82a3b83e7a7a2c0605c8c728e81b38319 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Fri, 16 Aug 2019 13:01:28 -0300 -Subject: [PATCH] media: cedrus: Specify H264 startcode and decoding mode - -The cedrus VPU is slice-based and expects V4L2_PIX_FMT_H264_SLICE -buffers to contain H264 slices with no start code. - -Expose this to userspace with the newly added menu control. - -These two controls are specified as mandatory for applications, -but we mark them as non-required on the driver side for -backwards compatibility. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index 7bdc413bf727..2d3ea8b74dfd 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -77,6 +77,24 @@ static const struct cedrus_control cedrus_controls[] = { - .codec = CEDRUS_CODEC_H264, - .required = true, - }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE, -+ .max = V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED, -+ .def = V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED, -+ }, -+ .codec = CEDRUS_CODEC_H264, -+ .required = false, -+ }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_H264_START_CODE, -+ .max = V4L2_MPEG_VIDEO_H264_START_CODE_NONE, -+ .def = V4L2_MPEG_VIDEO_H264_START_CODE_NONE, -+ }, -+ .codec = CEDRUS_CODEC_H264, -+ .required = false, -+ }, - }; - - #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) --- -2.23.0 - -From 5604be66a56867a784e162299a48c214921ffa1b Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Fri, 16 Aug 2019 13:01:24 -0300 -Subject: [PATCH] media: uapi: h264: Add the concept of decoding mode - -Some stateless decoders don't support per-slice decoding granularity -(or at least not in a way that would make them efficient or easy to use). - -Expose a menu to control the supported decoding modes. Drivers are -allowed to support only one decoding but they can support both too. - -To fully specify the decoding operation, we need to introduce -a start_byte_offset, to indicate where slices start. - -Signed-off-by: Boris Brezillon -Reviewed-by: Paul Kocialkowski -Tested-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/uapi/v4l/ext-ctrls-codec.rst | 57 ++++++++++++++++++- - .../media/uapi/v4l/pixfmt-compressed.rst | 6 +- - drivers/media/v4l2-core/v4l2-ctrls.c | 9 +++ - include/media/h264-ctrls.h | 10 ++++ - 4 files changed, 79 insertions(+), 3 deletions(-) - -diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -index c5f39dd50043..1da17a2c94d7 100644 ---- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -@@ -1747,6 +1747,14 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - * - __u32 - - ``size`` - - -+ * - __u32 -+ - ``start_byte_offset`` -+ Offset (in bytes) from the beginning of the OUTPUT buffer to the start -+ of the slice. If the slice starts with a start code, then this is the -+ offset to such start code. When operating in slice-based decoding mode -+ (see :c:type:`v4l2_mpeg_video_h264_decode_mode`), this field should -+ be set to 0. When operating in frame-based decoding mode, this field -+ should be 0 for the first slice. - * - __u32 - - ``header_bit_size`` - - -@@ -1930,7 +1938,10 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - - - * - __u16 - - ``num_slices`` -- - Number of slices needed to decode the current frame -+ - Number of slices needed to decode the current frame/field. When -+ operating in slice-based decoding mode (see -+ :c:type:`v4l2_mpeg_video_h264_decode_mode`), this field -+ should always be set to one. - * - __u16 - - ``nal_ref_idc`` - - NAL reference ID value coming from the NAL Unit header -@@ -2021,6 +2032,50 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - - 0x00000004 - - The DPB entry is a long term reference frame - -+``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)`` -+ Specifies the decoding mode to use. Currently exposes slice-based and -+ frame-based decoding but new modes might be added later on. -+ This control is used as a modifier for V4L2_PIX_FMT_H264_SLICE -+ pixel format. Applications that support V4L2_PIX_FMT_H264_SLICE -+ are required to set this control in order to specify the decoding mode -+ that is expected for the buffer. -+ Drivers may expose a single or multiple decoding modes, depending -+ on what they can support. -+ -+ .. note:: -+ -+ This menu control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_mpeg_video_h264_decode_mode -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED`` -+ - 0 -+ - Decoding is done at the slice granularity. -+ In this mode, ``num_slices`` field in struct -+ :c:type:`v4l2_ctrl_h264_decode_params` should be set to 1, -+ and ``start_byte_offset`` in struct -+ :c:type:`v4l2_ctrl_h264_slice_params` should be set to 0. -+ The OUTPUT buffer must contain a single slice. -+ * - ``V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED`` -+ - 1 -+ - Decoding is done at the frame granularity. -+ In this mode, ``num_slices`` field in struct -+ :c:type:`v4l2_ctrl_h264_decode_params` should be set to the number -+ of slices in the frame, and ``start_byte_offset`` in struct -+ :c:type:`v4l2_ctrl_h264_slice_params` should be set accordingly -+ for each slice. For the first slice, ``start_byte_offset`` should -+ be zero. -+ The OUTPUT buffer must contain all slices needed to decode the -+ frame. The OUTPUT buffer must also contain both fields. -+ - .. _v4l2-mpeg-mpeg2: - - ``V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS (struct)`` -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index 9b65473a2288..d666eb51741a 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -60,8 +60,10 @@ Compressed Formats - extracted from the H264 bitstream. This format is adapted for - stateless video decoders that implement an H264 pipeline - (using the :ref:`mem2mem` and :ref:`media-request-api`). -- Metadata associated with the frame to decode are required to -- be passed through the ``V4L2_CID_MPEG_VIDEO_H264_SPS``, -+ This pixelformat has a modifier that must be set at least once -+ through the ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE`` control. -+ In addition, metadata associated with the frame to decode are -+ required to be passed through the ``V4L2_CID_MPEG_VIDEO_H264_SPS``, - ``V4L2_CID_MPEG_VIDEO_H264_PPS``, - ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``, - ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index cd1ae016706f..2c67f9fc4d5b 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -402,6 +402,11 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - "Explicit", - NULL, - }; -+ static const char * const h264_decode_mode[] = { -+ "Slice-Based", -+ "Frame-Based", -+ NULL, -+ }; - static const char * const mpeg_mpeg2_level[] = { - "Low", - "Main", -@@ -633,6 +638,8 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - return h264_fp_arrangement_type; - case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: - return h264_fmo_map_type; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE: -+ return h264_decode_mode; - case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: - return mpeg_mpeg2_level; - case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: -@@ -852,6 +859,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix"; - case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; - case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE: return "H264 Decode Mode"; - case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; - case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; -@@ -1220,6 +1228,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC: - case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE: - case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE: - case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: - case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: - case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: -diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h -index 6160a69c0143..928c48c57282 100644 ---- a/include/media/h264-ctrls.h -+++ b/include/media/h264-ctrls.h -@@ -26,6 +26,7 @@ - #define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) - #define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) - #define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) -+#define V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (V4L2_CID_MPEG_BASE+1005) - - /* enum v4l2_ctrl_type type values */ - #define V4L2_CTRL_TYPE_H264_SPS 0x0110 -@@ -34,6 +35,11 @@ - #define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 - #define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 - -+enum v4l2_mpeg_video_h264_decode_mode { -+ V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED, -+ V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED, -+}; -+ - #define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 - #define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 - #define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 -@@ -125,6 +131,10 @@ struct v4l2_h264_pred_weight_table { - struct v4l2_ctrl_h264_slice_params { - /* Size in bytes, including header */ - __u32 size; -+ -+ /* Offset in bytes to the start of slice in the OUTPUT buffer. */ -+ __u32 start_byte_offset; -+ - /* Offset in bits to slice_data() from the beginning of this slice. */ - __u32 header_bit_size; - --- -2.23.0 - -From 8cae93e090113e46bd29a99c1727d8f13ea12fdf Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Fri, 16 Aug 2019 13:01:25 -0300 -Subject: [PATCH] media: uapi: h264: Add the concept of start code - -Stateless decoders have different expectations about the -start code that is prepended on H264 slices. Add a -menu control to express the supported start code types -(including no start code). - -Drivers are allowed to support only one start code type, -but they can support both too. - -Note that this is independent of the H264 decoding mode, -which specifies the granularity of the decoding operations. -Either in frame-based or slice-based mode, this new control -will allow to define the start code expected on H264 slices. - -Signed-off-by: Ezequiel Garcia -Tested-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/uapi/v4l/ext-ctrls-codec.rst | 33 +++++++++++++++++++ - .../media/uapi/v4l/pixfmt-compressed.rst | 5 +-- - drivers/media/v4l2-core/v4l2-ctrls.c | 9 +++++ - include/media/h264-ctrls.h | 6 ++++ - 4 files changed, 51 insertions(+), 2 deletions(-) - -diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -index 1da17a2c94d7..810ae9bb6f7c 100644 ---- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -@@ -2076,6 +2076,39 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - The OUTPUT buffer must contain all slices needed to decode the - frame. The OUTPUT buffer must also contain both fields. - -+``V4L2_CID_MPEG_VIDEO_H264_START_CODE (enum)`` -+ Specifies the H264 slice start code expected for each slice. -+ This control is used as a modifier for V4L2_PIX_FMT_H264_SLICE -+ pixel format. Applications that support V4L2_PIX_FMT_H264_SLICE -+ are required to set this control in order to specify the start code -+ that is expected for the buffer. -+ Drivers may expose a single or multiple start codes, depending -+ on what they can support. -+ -+ .. note:: -+ -+ This menu control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_mpeg_video_h264_start_code -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_MPEG_VIDEO_H264_START_CODE_NONE`` -+ - 0 -+ - Selecting this value specifies that H264 slices are passed -+ to the driver without any start code. -+ * - ``V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B`` -+ - 1 -+ - Selecting this value specifies that H264 slices are expected -+ to be prefixed by Annex B start codes. According to :ref:`h264` -+ valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001. -+ - .. _v4l2-mpeg-mpeg2: - - ``V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS (struct)`` -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index d666eb51741a..493b6020107d 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -60,8 +60,9 @@ Compressed Formats - extracted from the H264 bitstream. This format is adapted for - stateless video decoders that implement an H264 pipeline - (using the :ref:`mem2mem` and :ref:`media-request-api`). -- This pixelformat has a modifier that must be set at least once -- through the ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE`` control. -+ This pixelformat has two modifiers that must be set at least once -+ through the ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE`` -+ and ``V4L2_CID_MPEG_VIDEO_H264_START_CODE`` controls. - In addition, metadata associated with the frame to decode are - required to be passed through the ``V4L2_CID_MPEG_VIDEO_H264_SPS``, - ``V4L2_CID_MPEG_VIDEO_H264_PPS``, -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 2c67f9fc4d5b..1d8f38824631 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -407,6 +407,11 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - "Frame-Based", - NULL, - }; -+ static const char * const h264_start_code[] = { -+ "No Start Code", -+ "Annex B Start Code", -+ NULL, -+ }; - static const char * const mpeg_mpeg2_level[] = { - "Low", - "Main", -@@ -640,6 +645,8 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - return h264_fmo_map_type; - case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE: - return h264_decode_mode; -+ case V4L2_CID_MPEG_VIDEO_H264_START_CODE: -+ return h264_start_code; - case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: - return mpeg_mpeg2_level; - case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: -@@ -860,6 +867,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; - case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; - case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE: return "H264 Decode Mode"; -+ case V4L2_CID_MPEG_VIDEO_H264_START_CODE: return "H264 Start Code"; - case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; - case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; -@@ -1229,6 +1237,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE: - case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: - case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE: -+ case V4L2_CID_MPEG_VIDEO_H264_START_CODE: - case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: - case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: - case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: -diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h -index 928c48c57282..ba2876a64cf6 100644 ---- a/include/media/h264-ctrls.h -+++ b/include/media/h264-ctrls.h -@@ -27,6 +27,7 @@ - #define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) - #define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) - #define V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (V4L2_CID_MPEG_BASE+1005) -+#define V4L2_CID_MPEG_VIDEO_H264_START_CODE (V4L2_CID_MPEG_BASE+1006) - - /* enum v4l2_ctrl_type type values */ - #define V4L2_CTRL_TYPE_H264_SPS 0x0110 -@@ -40,6 +41,11 @@ enum v4l2_mpeg_video_h264_decode_mode { - V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED, - }; - -+enum v4l2_mpeg_video_h264_start_code { -+ V4L2_MPEG_VIDEO_H264_START_CODE_NONE, -+ V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B, -+}; -+ - #define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 - #define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 - #define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 --- -2.23.0 - -From c3adb85745ca6cc19532b2ee197d7abece1ac732 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Fri, 16 Aug 2019 13:01:26 -0300 -Subject: [PATCH] media: uapi: h264: Get rid of the p0/b0/b1 ref-lists - -Those lists can be extracted from the dpb, let's simplify userspace -life and build that list kernel-side (generic helpers will be provided -for drivers that need this list). - -Signed-off-by: Boris Brezillon -Reviewed-by: Nicolas Dufresne -Reviewed-by: Ezequiel Garcia -Reviewed-by: Paul Kocialkowski -Tested-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/ext-ctrls-codec.rst | 9 --------- - include/media/h264-ctrls.h | 3 --- - 2 files changed, 12 deletions(-) - -diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -index 810ae9bb6f7c..bc5dd8e76567 100644 ---- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -@@ -1945,15 +1945,6 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - * - __u16 - - ``nal_ref_idc`` - - NAL reference ID value coming from the NAL Unit header -- * - __u8 -- - ``ref_pic_list_p0[32]`` -- - Backward reference list used by P-frames in the original bitstream order -- * - __u8 -- - ``ref_pic_list_b0[32]`` -- - Backward reference list used by B-frames in the original bitstream order -- * - __u8 -- - ``ref_pic_list_b1[32]`` -- - Forward reference list used by B-frames in the original bitstream order - * - __s32 - - ``top_field_order_cnt`` - - Picture Order Count for the coded top field -diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h -index ba2876a64cf6..e877bf1d537c 100644 ---- a/include/media/h264-ctrls.h -+++ b/include/media/h264-ctrls.h -@@ -202,9 +202,6 @@ struct v4l2_ctrl_h264_decode_params { - struct v4l2_h264_dpb_entry dpb[16]; - __u16 num_slices; - __u16 nal_ref_idc; -- __u8 ref_pic_list_p0[32]; -- __u8 ref_pic_list_b0[32]; -- __u8 ref_pic_list_b1[32]; - __s32 top_field_order_cnt; - __s32 bottom_field_order_cnt; - __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ --- -2.23.0 - -From 52c8c7a766ecc49ff2e4c1db30b0a24a019e31d4 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 23 Aug 2019 12:31:36 +0200 -Subject: [PATCH] bluetooth: bcm: Add support for loading firmware for - BCM4345C5 - -Detect BCM4345C5 and load a corresponding firmware file. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/btbcm.c | 3 +++ - drivers/bluetooth/hci_bcm.c | 1 + - 2 files changed, 4 insertions(+) - -diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c -index 124ef0a3e1dd..2d2e6d862068 100644 ---- a/drivers/bluetooth/btbcm.c -+++ b/drivers/bluetooth/btbcm.c -@@ -23,6 +23,7 @@ - #define BDADDR_BCM43430A0 (&(bdaddr_t) {{0xac, 0x1f, 0x12, 0xa0, 0x43, 0x43}}) - #define BDADDR_BCM4324B3 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb3, 0x24, 0x43}}) - #define BDADDR_BCM4330B1 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb1, 0x30, 0x43}}) -+#define BDADDR_BCM4345C5 (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0xc5, 0x45, 0x43}}) - #define BDADDR_BCM43341B (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0x1b, 0x34, 0x43}}) - - int btbcm_check_bdaddr(struct hci_dev *hdev) -@@ -73,6 +74,7 @@ int btbcm_check_bdaddr(struct hci_dev *hdev) - !bacmp(&bda->bdaddr, BDADDR_BCM2076B1) || - !bacmp(&bda->bdaddr, BDADDR_BCM4324B3) || - !bacmp(&bda->bdaddr, BDADDR_BCM4330B1) || -+ !bacmp(&bda->bdaddr, BDADDR_BCM4345C5) || - !bacmp(&bda->bdaddr, BDADDR_BCM43430A0) || - !bacmp(&bda->bdaddr, BDADDR_BCM43341B)) { - bt_dev_info(hdev, "BCM: Using default device address (%pMR)", -@@ -332,6 +334,7 @@ static const struct bcm_subver_table bcm_uart_subver_table[] = { - { 0x2122, "BCM4343A0" }, /* 001.001.034 */ - { 0x2209, "BCM43430A1" }, /* 001.002.009 */ - { 0x6119, "BCM4345C0" }, /* 003.001.025 */ -+ { 0x6606, "BCM4345C5" }, /* 003.006.006 */ - { 0x230f, "BCM4356A2" }, /* 001.003.015 */ - { 0x220e, "BCM20702A1" }, /* 001.002.014 */ - { 0x4217, "BCM4329B1" }, /* 002.002.023 */ -diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c -index 4d9de20bab7b..95c312ae94cf 100644 ---- a/drivers/bluetooth/hci_bcm.c -+++ b/drivers/bluetooth/hci_bcm.c -@@ -1419,6 +1419,7 @@ static void bcm_serdev_remove(struct serdev_device *serdev) - #ifdef CONFIG_OF - static const struct of_device_id bcm_bluetooth_of_match[] = { - { .compatible = "brcm,bcm20702a1" }, -+ { .compatible = "brcm,bcm4345c5" }, - { .compatible = "brcm,bcm4330-bt" }, - { .compatible = "brcm,bcm43438-bt" }, - { }, --- -2.23.0 - -From 16946de5905fff243c1e4415c4565803945e8c47 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Fri, 23 Aug 2019 12:31:37 +0200 -Subject: [PATCH] bluetooth: hci_bcm: Give more time to come out of reset - -Some supported devices need more time to come out of reset (eg. -BCM4345C5 in AP6256). - -I don't have/found a datasheet, so the value was arrive at -experimentally with the Oprange Pi 3 board. Without increased delay, -I got intermittent failures during probe. This is a Bluetooth 5.0 -device, so maybe that's why it takes longer to initialize than the -others. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/hci_bcm.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c -index 95c312ae94cf..7646636f2d18 100644 ---- a/drivers/bluetooth/hci_bcm.c -+++ b/drivers/bluetooth/hci_bcm.c -@@ -260,7 +260,7 @@ static int bcm_gpio_set_power(struct bcm_device *dev, bool powered) - } - - /* wait for device to power on and come out of reset */ -- usleep_range(10000, 20000); -+ usleep_range(100000, 120000); - - dev->res_enabled = powered; - --- -2.23.0 - -From de8145452eebe5510bd2b142b31560db548d6abb Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Thu, 11 Jul 2019 16:26:41 -0400 -Subject: [PATCH] media: v4l2-ctrl: Move compound control validation - -Rework std_validate moving the compound controls to -its own validation function. - -While here, fix the pointer math to account the index parameter. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-ctrls.c | 126 +++++++++++++++------------ - 1 file changed, 69 insertions(+), 57 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 371537dd8cd3..739418aa9108 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1629,10 +1629,77 @@ static void std_log(const struct v4l2_ctrl *ctrl) - }) - - /* Validate a new control */ -+static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, -+ union v4l2_ctrl_ptr ptr) -+{ -+ struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; -+ void *p = ptr.p + idx * ctrl->elem_size; -+ -+ switch ((u32)ctrl->type) { -+ case V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS: -+ p_mpeg2_slice_params = p; -+ -+ switch (p_mpeg2_slice_params->sequence.chroma_format) { -+ case 1: /* 4:2:0 */ -+ case 2: /* 4:2:2 */ -+ case 3: /* 4:4:4 */ -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (p_mpeg2_slice_params->picture.intra_dc_precision) { -+ case 0: /* 8 bits */ -+ case 1: /* 9 bits */ -+ case 2: /* 10 bits */ -+ case 3: /* 11 bits */ -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (p_mpeg2_slice_params->picture.picture_structure) { -+ case 1: /* interlaced top field */ -+ case 2: /* interlaced bottom field */ -+ case 3: /* progressive */ -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (p_mpeg2_slice_params->picture.picture_coding_type) { -+ case V4L2_MPEG2_PICTURE_CODING_TYPE_I: -+ case V4L2_MPEG2_PICTURE_CODING_TYPE_P: -+ case V4L2_MPEG2_PICTURE_CODING_TYPE_B: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ break; -+ -+ case V4L2_CTRL_TYPE_MPEG2_QUANTIZATION: -+ break; -+ -+ case V4L2_CTRL_TYPE_FWHT_PARAMS: -+ break; -+ -+ case V4L2_CTRL_TYPE_H264_SPS: -+ case V4L2_CTRL_TYPE_H264_PPS: -+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, - union v4l2_ctrl_ptr ptr) - { -- struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; - size_t len; - u64 offset; - s64 val; -@@ -1695,63 +1762,8 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, - return -ERANGE; - return 0; - -- case V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS: -- p_mpeg2_slice_params = ptr.p; -- -- switch (p_mpeg2_slice_params->sequence.chroma_format) { -- case 1: /* 4:2:0 */ -- case 2: /* 4:2:2 */ -- case 3: /* 4:4:4 */ -- break; -- default: -- return -EINVAL; -- } -- -- switch (p_mpeg2_slice_params->picture.intra_dc_precision) { -- case 0: /* 8 bits */ -- case 1: /* 9 bits */ -- case 2: /* 10 bits */ -- case 3: /* 11 bits */ -- break; -- default: -- return -EINVAL; -- } -- -- switch (p_mpeg2_slice_params->picture.picture_structure) { -- case 1: /* interlaced top field */ -- case 2: /* interlaced bottom field */ -- case 3: /* progressive */ -- break; -- default: -- return -EINVAL; -- } -- -- switch (p_mpeg2_slice_params->picture.picture_coding_type) { -- case V4L2_MPEG2_PICTURE_CODING_TYPE_I: -- case V4L2_MPEG2_PICTURE_CODING_TYPE_P: -- case V4L2_MPEG2_PICTURE_CODING_TYPE_B: -- break; -- default: -- return -EINVAL; -- } -- -- return 0; -- -- case V4L2_CTRL_TYPE_MPEG2_QUANTIZATION: -- return 0; -- -- case V4L2_CTRL_TYPE_FWHT_PARAMS: -- return 0; -- -- case V4L2_CTRL_TYPE_H264_SPS: -- case V4L2_CTRL_TYPE_H264_PPS: -- case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -- case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -- case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -- return 0; -- - default: -- return -EINVAL; -+ return std_validate_compound(ctrl, idx, ptr); - } - } - --- -2.23.0 - -From a57d6acaf352d91e52271704f45c72e14cd2d98a Mon Sep 17 00:00:00 2001 -From: Pawel Osciak -Date: Thu, 11 Jul 2019 16:26:42 -0400 -Subject: [PATCH] media: uapi: Add VP8 stateless decoder API - -Add the parsed VP8 frame pixel format and controls, to be used -with the new stateless decoder API for VP8 to provide parameters -for accelerator (aka stateless) codecs. - -Reviewed-by: Tomasz Figa -Reviewed-by: Boris Brezillon -Reviewed-by: Nicolas Dufresne -Signed-off-by: Pawel Osciak -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/biblio.rst | 10 + - .../media/uapi/v4l/ext-ctrls-codec.rst | 323 ++++++++++++++++++ - .../media/uapi/v4l/pixfmt-compressed.rst | 20 ++ - drivers/media/v4l2-core/v4l2-ctrls.c | 10 + - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/v4l2-ctrls.h | 3 + - include/media/vp8-ctrls.h | 110 ++++++ - 7 files changed, 477 insertions(+) - create mode 100644 include/media/vp8-ctrls.h - -diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst -index 8f4eb8823d82..ad2ff258afa8 100644 ---- a/Documentation/media/uapi/v4l/biblio.rst -+++ b/Documentation/media/uapi/v4l/biblio.rst -@@ -395,3 +395,13 @@ colimg - :title: Color Imaging: Fundamentals and Applications - - :author: Erik Reinhard et al. -+ -+.. _vp8: -+ -+VP8 -+=== -+ -+ -+:title: RFC 6386: "VP8 Data Format and Decoding Guide" -+ -+:author: J. Bankoski et al. -diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -index d6ea2ffd65c5..c5f39dd50043 100644 ---- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -@@ -2234,6 +2234,329 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - Quantization parameter for a P frame for FWHT. Valid range: from 1 - to 31. - -+.. _v4l2-mpeg-vp8: -+ -+``V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER (struct)`` -+ Specifies the frame parameters for the associated VP8 parsed frame data. -+ This includes the necessary parameters for -+ configuring a stateless hardware decoding pipeline for VP8. -+ The bitstream parameters are defined according to :ref:`vp8`. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_ctrl_vp8_frame_header -+ -+.. cssclass:: longtable -+ -+.. tabularcolumns:: |p{5.8cm}|p{4.8cm}|p{6.6cm}| -+ -+.. flat-table:: struct v4l2_ctrl_vp8_frame_header -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - struct :c:type:`v4l2_vp8_segment_header` -+ - ``segment_header`` -+ - Structure with segment-based adjustments metadata. -+ * - struct :c:type:`v4l2_vp8_loopfilter_header` -+ - ``loopfilter_header`` -+ - Structure with loop filter level adjustments metadata. -+ * - struct :c:type:`v4l2_vp8_quantization_header` -+ - ``quant_header`` -+ - Structure with VP8 dequantization indices metadata. -+ * - struct :c:type:`v4l2_vp8_entropy_header` -+ - ``entropy_header`` -+ - Structure with VP8 entropy coder probabilities metadata. -+ * - struct :c:type:`v4l2_vp8_entropy_coder_state` -+ - ``coder_state`` -+ - Structure with VP8 entropy coder state. -+ * - __u16 -+ - ``width`` -+ - The width of the frame. Must be set for all frames. -+ * - __u16 -+ - ``height`` -+ - The height of the frame. Must be set for all frames. -+ * - __u8 -+ - ``horizontal_scale`` -+ - Horizontal scaling factor. -+ * - __u8 -+ - ``vertical_scaling factor`` -+ - Vertical scale. -+ * - __u8 -+ - ``version`` -+ - Bitstream version. -+ * - __u8 -+ - ``prob_skip_false`` -+ - Indicates the probability that the macroblock is not skipped. -+ * - __u8 -+ - ``prob_intra`` -+ - Indicates the probability that a macroblock is intra-predicted. -+ * - __u8 -+ - ``prob_last`` -+ - Indicates the probability that the last reference frame is used -+ for inter-prediction -+ * - __u8 -+ - ``prob_gf`` -+ - Indicates the probability that the golden reference frame is used -+ for inter-prediction -+ * - __u8 -+ - ``num_dct_parts`` -+ - Number of DCT coefficients partitions. Must be one of: 1, 2, 4, or 8. -+ * - __u32 -+ - ``first_part_size`` -+ - Size of the first partition, i.e. the control partition. -+ * - __u32 -+ - ``first_part_header_bits`` -+ - Size in bits of the first partition header portion. -+ * - __u32 -+ - ``dct_part_sizes[8]`` -+ - DCT coefficients sizes. -+ * - __u64 -+ - ``last_frame_ts`` -+ - Timestamp for the V4L2 capture buffer to use as last reference frame, used -+ with inter-coded frames. The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``golden_frame_ts`` -+ - Timestamp for the V4L2 capture buffer to use as last reference frame, used -+ with inter-coded frames. The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``alt_frame_ts`` -+ - Timestamp for the V4L2 capture buffer to use as alternate reference frame, used -+ with inter-coded frames. The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``flags`` -+ - See :ref:`Frame Header Flags ` -+ -+.. _vp8_frame_header_flags: -+ -+``Frame Header Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME`` -+ - 0x01 -+ - Indicates if the frame is a key frame. -+ * - ``V4L2_VP8_FRAME_HEADER_FLAG_EXPERIMENTAL`` -+ - 0x02 -+ - Experimental bitstream. -+ * - ``V4L2_VP8_FRAME_HEADER_FLAG_SHOW_FRAME`` -+ - 0x04 -+ - Show frame flag, indicates if the frame is for display. -+ * - ``V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF`` -+ - 0x08 -+ - Enable/disable skipping of macroblocks with no non-zero coefficients. -+ * - ``V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN`` -+ - 0x10 -+ - Sign of motion vectors when the golden frame is referenced. -+ * - ``V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT`` -+ - 0x20 -+ - Sign of motion vectors when the alt frame is referenced. -+ -+.. c:type:: v4l2_vp8_entropy_coder_state -+ -+.. cssclass:: longtable -+ -+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| -+ -+.. flat-table:: struct v4l2_vp8_entropy_coder_state -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``range`` -+ - -+ * - __u8 -+ - ``value`` -+ - -+ * - __u8 -+ - ``bit_count`` -+ - -+ * - __u8 -+ - ``padding`` -+ - Applications and drivers must set this to zero. -+ -+.. c:type:: v4l2_vp8_segment_header -+ -+.. cssclass:: longtable -+ -+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| -+ -+.. flat-table:: struct v4l2_vp8_segment_header -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __s8 -+ - ``quant_update[4]`` -+ - Signed quantizer value update. -+ * - __s8 -+ - ``lf_update[4]`` -+ - Signed loop filter level value update. -+ * - __u8 -+ - ``segment_probs[3]`` -+ - Segment probabilities. -+ * - __u8 -+ - ``padding`` -+ - Applications and drivers must set this to zero. -+ * - __u32 -+ - ``flags`` -+ - See :ref:`Segment Header Flags ` -+ -+.. _vp8_segment_header_flags: -+ -+``Segment Header Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED`` -+ - 0x01 -+ - Enable/disable segment-based adjustments. -+ * - ``V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP`` -+ - 0x02 -+ - Indicates if the macroblock segmentation map is updated in this frame. -+ * - ``V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_FEATURE_DATA`` -+ - 0x04 -+ - Indicates if the segment feature data is updated in this frame. -+ * - ``V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE`` -+ - 0x08 -+ - If is set, the segment feature data mode is delta-value. -+ If cleared, it's absolute-value. -+ -+.. c:type:: v4l2_vp8_loopfilter_header -+ -+.. cssclass:: longtable -+ -+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| -+ -+.. flat-table:: struct v4l2_vp8_loopfilter_header -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __s8 -+ - ``ref_frm_delta[4]`` -+ - Reference adjustment (signed) delta value. -+ * - __s8 -+ - ``mb_mode_delta[4]`` -+ - Macroblock prediction mode adjustment (signed) delta value. -+ * - __u8 -+ - ``sharpness_level`` -+ - Sharpness level -+ * - __u8 -+ - ``level`` -+ - Filter level -+ * - __u16 -+ - ``padding`` -+ - Applications and drivers must set this to zero. -+ * - __u32 -+ - ``flags`` -+ - See :ref:`Loopfilter Header Flags ` -+ -+.. _vp8_loopfilter_header_flags: -+ -+``Loopfilter Header Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP8_LF_HEADER_ADJ_ENABLE`` -+ - 0x01 -+ - Enable/disable macroblock-level loop filter adjustment. -+ * - ``V4L2_VP8_LF_HEADER_DELTA_UPDATE`` -+ - 0x02 -+ - Indicates if the delta values used in an adjustment are updated. -+ * - ``V4L2_VP8_LF_FILTER_TYPE_SIMPLE`` -+ - 0x04 -+ - If set, indicates the filter type is simple. -+ If cleared, the filter type is normal. -+ -+.. c:type:: v4l2_vp8_quantization_header -+ -+.. cssclass:: longtable -+ -+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| -+ -+.. flat-table:: struct v4l2_vp8_quantization_header -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``y_ac_qi`` -+ - Luma AC coefficient table index. -+ * - __s8 -+ - ``y_dc_delta`` -+ - Luma DC delta vaue. -+ * - __s8 -+ - ``y2_dc_delta`` -+ - Y2 block DC delta value. -+ * - __s8 -+ - ``y2_ac_delta`` -+ - Y2 block AC delta value. -+ * - __s8 -+ - ``uv_dc_delta`` -+ - Chroma DC delta value. -+ * - __s8 -+ - ``uv_ac_delta`` -+ - Chroma AC delta value. -+ * - __u16 -+ - ``padding`` -+ - Applications and drivers must set this to zero. -+ -+.. c:type:: v4l2_vp8_entropy_header -+ -+.. cssclass:: longtable -+ -+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| -+ -+.. flat-table:: struct v4l2_vp8_entropy_header -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``coeff_probs[4][8][3][11]`` -+ - Coefficient update probabilities. -+ * - __u8 -+ - ``y_mode_probs[4]`` -+ - Luma mode update probabilities. -+ * - __u8 -+ - ``uv_mode_probs[3]`` -+ - Chroma mode update probabilities. -+ * - __u8 -+ - ``mv_probs[2][19]`` -+ - MV decoding update probabilities. -+ * - __u8 -+ - ``padding[3]`` -+ - Applications and drivers must set this to zero. -+ - .. raw:: latex - - \normalsize -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index 4b701fc7653e..f52a7b67023d 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -133,6 +133,26 @@ Compressed Formats - - ``V4L2_PIX_FMT_VP8`` - - 'VP80' - - VP8 video elementary stream. -+ * .. _V4L2-PIX-FMT-VP8-FRAME: -+ -+ - ``V4L2_PIX_FMT_VP8_FRAME`` -+ - 'VP8F' -+ - VP8 parsed frame, as extracted from the container. -+ This format is adapted for stateless video decoders that implement a -+ VP8 pipeline (using the :ref:`mem2mem` and :ref:`media-request-api`). -+ Metadata associated with the frame to decode is required to be passed -+ through the ``V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER`` control. -+ See the :ref:`associated Codec Control IDs `. -+ Exactly one output and one capture buffer must be provided for use with -+ this pixel format. The output buffer must contain the appropriate number -+ of macroblocks to decode a full corresponding frame to the matching -+ capture buffer. -+ -+ .. note:: -+ -+ This format is not yet part of the public kernel API and it -+ is expected to change. -+ - * .. _V4L2-PIX-FMT-VP9: - - - ``V4L2_PIX_FMT_VP9`` -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 739418aa9108..b2c9f5816c4a 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -885,6 +885,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP: return "VPX P-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_VP8_PROFILE: return "VP8 Profile"; - case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: return "VP9 Profile"; -+ case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: return "VP8 Frame Header"; - - /* HEVC controls */ - case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: return "HEVC I-Frame QP Value"; -@@ -1345,6 +1346,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: - *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: -+ *type = V4L2_CTRL_TYPE_VP8_FRAME_HEADER; -+ break; - default: - *type = V4L2_CTRL_TYPE_INTEGER; - break; -@@ -1690,6 +1694,9 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: - case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: - break; -+ -+ case V4L2_CTRL_TYPE_VP8_FRAME_HEADER: -+ break; - default: - return -EINVAL; - } -@@ -2360,6 +2367,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); - break; -+ case V4L2_CTRL_TYPE_VP8_FRAME_HEADER: -+ elem_size = sizeof(struct v4l2_ctrl_vp8_frame_header); -+ break; - default: - if (type < V4L2_CTRL_COMPOUND_TYPES) - elem_size = sizeof(s32); -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 20cc23ef730e..80efc581e3f9 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1348,6 +1348,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_VC1_ANNEX_G: descr = "VC-1 (SMPTE 412M Annex G)"; break; - case V4L2_PIX_FMT_VC1_ANNEX_L: descr = "VC-1 (SMPTE 412M Annex L)"; break; - case V4L2_PIX_FMT_VP8: descr = "VP8"; break; -+ case V4L2_PIX_FMT_VP8_FRAME: descr = "VP8 Frame"; break; - case V4L2_PIX_FMT_VP9: descr = "VP9"; break; - case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ - case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index b4433483af23..6e9dc9c44bb1 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - - /* forward references */ - struct file; -@@ -48,6 +49,7 @@ struct poll_table_struct; - * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. - * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. - * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. -+ * @p_vp8_frame_header: Pointer to a VP8 frame header structure. - * @p: Pointer to a compound value. - */ - union v4l2_ctrl_ptr { -@@ -65,6 +67,7 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; - struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; - struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; -+ struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header; - void *p; - }; - -diff --git a/include/media/vp8-ctrls.h b/include/media/vp8-ctrls.h -new file mode 100644 -index 000000000000..6cc2eeea4c90 ---- /dev/null -+++ b/include/media/vp8-ctrls.h -@@ -0,0 +1,110 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the VP8 state controls for use with stateless VP8 -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _VP8_CTRLS_H_ -+#define _VP8_CTRLS_H_ -+ -+#define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') -+ -+#define V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER (V4L2_CID_MPEG_BASE + 2000) -+#define V4L2_CTRL_TYPE_VP8_FRAME_HEADER 0x301 -+ -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED 0x01 -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP 0x02 -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_FEATURE_DATA 0x04 -+#define V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE 0x08 -+ -+struct v4l2_vp8_segment_header { -+ __s8 quant_update[4]; -+ __s8 lf_update[4]; -+ __u8 segment_probs[3]; -+ __u8 padding; -+ __u32 flags; -+}; -+ -+#define V4L2_VP8_LF_HEADER_ADJ_ENABLE 0x01 -+#define V4L2_VP8_LF_HEADER_DELTA_UPDATE 0x02 -+#define V4L2_VP8_LF_FILTER_TYPE_SIMPLE 0x04 -+struct v4l2_vp8_loopfilter_header { -+ __s8 ref_frm_delta[4]; -+ __s8 mb_mode_delta[4]; -+ __u8 sharpness_level; -+ __u8 level; -+ __u16 padding; -+ __u32 flags; -+}; -+ -+struct v4l2_vp8_quantization_header { -+ __u8 y_ac_qi; -+ __s8 y_dc_delta; -+ __s8 y2_dc_delta; -+ __s8 y2_ac_delta; -+ __s8 uv_dc_delta; -+ __s8 uv_ac_delta; -+ __u16 padding; -+}; -+ -+struct v4l2_vp8_entropy_header { -+ __u8 coeff_probs[4][8][3][11]; -+ __u8 y_mode_probs[4]; -+ __u8 uv_mode_probs[3]; -+ __u8 mv_probs[2][19]; -+ __u8 padding[3]; -+}; -+ -+struct v4l2_vp8_entropy_coder_state { -+ __u8 range; -+ __u8 value; -+ __u8 bit_count; -+ __u8 padding; -+}; -+ -+#define V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME 0x01 -+#define V4L2_VP8_FRAME_HEADER_FLAG_EXPERIMENTAL 0x02 -+#define V4L2_VP8_FRAME_HEADER_FLAG_SHOW_FRAME 0x04 -+#define V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF 0x08 -+#define V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN 0x10 -+#define V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT 0x20 -+ -+#define VP8_FRAME_IS_KEY_FRAME(hdr) \ -+ (!!((hdr)->flags & V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME)) -+ -+struct v4l2_ctrl_vp8_frame_header { -+ struct v4l2_vp8_segment_header segment_header; -+ struct v4l2_vp8_loopfilter_header lf_header; -+ struct v4l2_vp8_quantization_header quant_header; -+ struct v4l2_vp8_entropy_header entropy_header; -+ struct v4l2_vp8_entropy_coder_state coder_state; -+ -+ __u16 width; -+ __u16 height; -+ -+ __u8 horizontal_scale; -+ __u8 vertical_scale; -+ -+ __u8 version; -+ __u8 prob_skip_false; -+ __u8 prob_intra; -+ __u8 prob_last; -+ __u8 prob_gf; -+ __u8 num_dct_parts; -+ -+ __u32 first_part_size; -+ __u32 first_part_header_bits; -+ __u32 dct_part_sizes[8]; -+ -+ __u64 last_frame_ts; -+ __u64 golden_frame_ts; -+ __u64 alt_frame_ts; -+ -+ __u64 flags; -+}; -+ -+#endif --- -2.23.0 - -From 298c62d3856111e6ef41c9c00a233aecf2d19651 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Thu, 11 Jul 2019 16:26:43 -0400 -Subject: [PATCH] media: v4l2-ctrl: Validate VP8 stateless decoder controls - -Only one field needs to be validated: 'num_dct_parts'. -This field is used to iterate over the user-provided array -'dct_part_sizes'. - -Signed-off-by: Ezequiel Garcia -[hverkuil-cisco@xs4all.nl: s -> (s) in zero_padding macro] -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-ctrls.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index b2c9f5816c4a..13236c191796 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1633,10 +1633,15 @@ static void std_log(const struct v4l2_ctrl *ctrl) - }) - - /* Validate a new control */ -+ -+#define zero_padding(s) \ -+ memset(&(s).padding, 0, sizeof((s).padding)) -+ - static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - union v4l2_ctrl_ptr ptr) - { - struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; -+ struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header; - void *p = ptr.p + idx * ctrl->elem_size; - - switch ((u32)ctrl->type) { -@@ -1696,6 +1701,22 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - break; - - case V4L2_CTRL_TYPE_VP8_FRAME_HEADER: -+ p_vp8_frame_header = p; -+ -+ switch (p_vp8_frame_header->num_dct_parts) { -+ case 1: -+ case 2: -+ case 4: -+ case 8: -+ break; -+ default: -+ return -EINVAL; -+ } -+ zero_padding(p_vp8_frame_header->segment_header); -+ zero_padding(p_vp8_frame_header->lf_header); -+ zero_padding(p_vp8_frame_header->quant_header); -+ zero_padding(p_vp8_frame_header->entropy_header); -+ zero_padding(p_vp8_frame_header->coder_state); - break; - default: - return -EINVAL; --- -2.23.0 - -From e30399e1bd6e215ec20981612646ec73a4385c33 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Thu, 15 Aug 2019 11:59:13 -0300 -Subject: [PATCH] media: rc: add keymap for Tanix TX3 mini remote - -The Tanix TX3 mini Android STB ships with a simple NEC remote. - -Signed-off-by: Christian Hewitt -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/rc/keymaps/Makefile | 1 + - drivers/media/rc/keymaps/rc-tanix-tx3mini.c | 77 +++++++++++++++++++++ - include/media/rc-map.h | 1 + - 3 files changed, 79 insertions(+) - create mode 100644 drivers/media/rc/keymaps/rc-tanix-tx3mini.c - -diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile -index 39192b0abf91..31720d842f88 100644 ---- a/drivers/media/rc/keymaps/Makefile -+++ b/drivers/media/rc/keymaps/Makefile -@@ -95,6 +95,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \ - rc-snapstream-firefly.o \ - rc-streamzap.o \ - rc-tango.o \ -+ rc-tanix-tx3mini.o \ - rc-tbs-nec.o \ - rc-technisat-ts35.o \ - rc-technisat-usb2.o \ -diff --git a/drivers/media/rc/keymaps/rc-tanix-tx3mini.c b/drivers/media/rc/keymaps/rc-tanix-tx3mini.c -new file mode 100644 -index 000000000000..d486cd69afb2 ---- /dev/null -+++ b/drivers/media/rc/keymaps/rc-tanix-tx3mini.c -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright (c) 2018 Christian Hewitt -+ -+#include -+#include -+ -+/* -+ * Keymap for the Tanix TX3 mini STB remote control -+ */ -+ -+static struct rc_map_table tanix_tx3mini[] = { -+ { 0x8051, KEY_POWER }, -+ { 0x804d, KEY_MUTE }, -+ -+ { 0x8009, KEY_RED }, -+ { 0x8011, KEY_GREEN }, -+ { 0x8054, KEY_YELLOW }, -+ { 0x804f, KEY_BLUE }, -+ -+ { 0x8056, KEY_VOLUMEDOWN }, -+ { 0x80bd, KEY_PREVIOUS }, -+ { 0x80bb, KEY_NEXT }, -+ { 0x804e, KEY_VOLUMEUP }, -+ -+ { 0x8053, KEY_HOME }, -+ { 0x801b, KEY_BACK }, -+ -+ { 0x8026, KEY_UP }, -+ { 0x8028, KEY_DOWN }, -+ { 0x8025, KEY_LEFT }, -+ { 0x8027, KEY_RIGHT }, -+ { 0x800d, KEY_OK }, -+ -+ { 0x8049, KEY_MENU }, -+ { 0x8052, KEY_EPG }, // mouse -+ -+ { 0x8031, KEY_1 }, -+ { 0x8032, KEY_2 }, -+ { 0x8033, KEY_3 }, -+ -+ { 0x8034, KEY_4 }, -+ { 0x8035, KEY_5 }, -+ { 0x8036, KEY_6 }, -+ -+ { 0x8037, KEY_7 }, -+ { 0x8038, KEY_8 }, -+ { 0x8039, KEY_9 }, -+ -+ { 0x8058, KEY_SUBTITLE }, // 1/a -+ { 0x8030, KEY_0 }, -+ { 0x8044, KEY_DELETE }, -+}; -+ -+static struct rc_map_list tanix_tx3mini_map = { -+ .map = { -+ .scan = tanix_tx3mini, -+ .size = ARRAY_SIZE(tanix_tx3mini), -+ .rc_proto = RC_PROTO_NEC, -+ .name = RC_MAP_TANIX_TX3MINI, -+ } -+}; -+ -+static int __init init_rc_map_tanix_tx3mini(void) -+{ -+ return rc_map_register(&tanix_tx3mini_map); -+} -+ -+static void __exit exit_rc_map_tanix_tx3mini(void) -+{ -+ rc_map_unregister(&tanix_tx3mini_map); -+} -+ -+module_init(init_rc_map_tanix_tx3mini) -+module_exit(exit_rc_map_tanix_tx3mini) -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Christian Hewitt "); -diff --git a/include/media/rc-map.h b/include/media/rc-map.h -index 9754017518a0..b8929d0c5d6b 100644 ---- a/include/media/rc-map.h -+++ b/include/media/rc-map.h -@@ -249,6 +249,7 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_SNAPSTREAM_FIREFLY "rc-snapstream-firefly" - #define RC_MAP_STREAMZAP "rc-streamzap" - #define RC_MAP_TANGO "rc-tango" -+#define RC_MAP_TANIX_TX3MINI "rc-tanix-tx3mini" - #define RC_MAP_TBS_NEC "rc-tbs-nec" - #define RC_MAP_TECHNISAT_TS35 "rc-technisat-ts35" - #define RC_MAP_TECHNISAT_USB2 "rc-technisat-usb2" --- -2.24.0 - -From 7bb53f361c59b68e521a05fce579ccfa8021c3a0 Mon Sep 17 00:00:00 2001 -From: Christian Hewitt -Date: Thu, 15 Aug 2019 11:59:14 -0300 -Subject: [PATCH] media: rc: add keymap for Tanix TX5 max remote - -The Tanix TX5 max Android STB ships with a simple NEC remote. - -Signed-off-by: Christian Hewitt -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/rc/keymaps/Makefile | 1 + - drivers/media/rc/keymaps/rc-tanix-tx5max.c | 68 ++++++++++++++++++++++ - include/media/rc-map.h | 1 + - 3 files changed, 70 insertions(+) - create mode 100644 drivers/media/rc/keymaps/rc-tanix-tx5max.c - -diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile -index 31720d842f88..85423cc84149 100644 ---- a/drivers/media/rc/keymaps/Makefile -+++ b/drivers/media/rc/keymaps/Makefile -@@ -96,6 +96,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \ - rc-streamzap.o \ - rc-tango.o \ - rc-tanix-tx3mini.o \ -+ rc-tanix-tx5max.o \ - rc-tbs-nec.o \ - rc-technisat-ts35.o \ - rc-technisat-usb2.o \ -diff --git a/drivers/media/rc/keymaps/rc-tanix-tx5max.c b/drivers/media/rc/keymaps/rc-tanix-tx5max.c -new file mode 100644 -index 000000000000..59aaabed80dd ---- /dev/null -+++ b/drivers/media/rc/keymaps/rc-tanix-tx5max.c -@@ -0,0 +1,68 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright (c) 2018 Christian Hewitt -+ -+#include -+#include -+ -+/* -+ * Keymap for the Tanix TX5 max STB remote control -+ */ -+ -+static struct rc_map_table tanix_tx5max[] = { -+ { 0x40404d, KEY_POWER }, -+ { 0x404043, KEY_MUTE }, -+ -+ { 0x404017, KEY_VOLUMEDOWN }, -+ { 0x404018, KEY_VOLUMEUP }, -+ -+ { 0x40400b, KEY_UP }, -+ { 0x404010, KEY_LEFT }, -+ { 0x404011, KEY_RIGHT }, -+ { 0x40400e, KEY_DOWN }, -+ { 0x40400d, KEY_OK }, -+ -+ { 0x40401a, KEY_HOME }, -+ { 0x404045, KEY_MENU }, -+ { 0x404042, KEY_BACK }, -+ -+ { 0x404001, KEY_1 }, -+ { 0x404002, KEY_2 }, -+ { 0x404003, KEY_3 }, -+ -+ { 0x404004, KEY_4 }, -+ { 0x404005, KEY_5 }, -+ { 0x404006, KEY_6 }, -+ -+ { 0x404007, KEY_7 }, -+ { 0x404008, KEY_8 }, -+ { 0x404009, KEY_9 }, -+ -+ { 0x404047, KEY_SUBTITLE }, // mouse -+ { 0x404000, KEY_0 }, -+ { 0x40400c, KEY_DELETE }, -+}; -+ -+static struct rc_map_list tanix_tx5max_map = { -+ .map = { -+ .scan = tanix_tx5max, -+ .size = ARRAY_SIZE(tanix_tx5max), -+ .rc_proto = RC_PROTO_NECX, -+ .name = RC_MAP_TANIX_TX5MAX, -+ } -+}; -+ -+static int __init init_rc_map_tanix_tx5max(void) -+{ -+ return rc_map_register(&tanix_tx5max_map); -+} -+ -+static void __exit exit_rc_map_tanix_tx5max(void) -+{ -+ rc_map_unregister(&tanix_tx5max_map); -+} -+ -+module_init(init_rc_map_tanix_tx5max) -+module_exit(exit_rc_map_tanix_tx5max) -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Christian Hewitt "); -diff --git a/include/media/rc-map.h b/include/media/rc-map.h -index b8929d0c5d6b..a2ebe4868567 100644 ---- a/include/media/rc-map.h -+++ b/include/media/rc-map.h -@@ -250,6 +250,7 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_STREAMZAP "rc-streamzap" - #define RC_MAP_TANGO "rc-tango" - #define RC_MAP_TANIX_TX3MINI "rc-tanix-tx3mini" -+#define RC_MAP_TANIX_TX5MAX "rc-tanix-tx5max" - #define RC_MAP_TBS_NEC "rc-tbs-nec" - #define RC_MAP_TECHNISAT_TS35 "rc-technisat-ts35" - #define RC_MAP_TECHNISAT_USB2 "rc-technisat-usb2" --- -2.24.0 - diff --git a/projects/Allwinner/patches/linux/0002-backport-from-5.5.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.5.patch similarity index 97% rename from projects/Allwinner/patches/linux/0002-backport-from-5.5.patch rename to projects/Allwinner/patches/linux/0001-backport-from-5.5.patch index 8b9b5b9c36..3b4172cff5 100644 --- a/projects/Allwinner/patches/linux/0002-backport-from-5.5.patch +++ b/projects/Allwinner/patches/linux/0001-backport-from-5.5.patch @@ -4341,110 +4341,6 @@ index 9f4e66affac4..d969842bbfe2 100644 -- 2.23.0 -From d4e0f82ac840bf3d16b25d60f261b429603138a9 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Thu, 15 Aug 2019 11:44:52 -0300 -Subject: [PATCH] media: pixfmt-compressed.rst: improve H264/HEVC/MPEG1+2/VP8+9 - documentation - -The existing documentation was incorrect and did not correspond -to how actual codec drivers implemented this. - -Update the documentation to explicitly specify what is actually -expected. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/uapi/v4l/pixfmt-compressed.rst | 36 +++++++++++++++---- - 1 file changed, 30 insertions(+), 6 deletions(-) - -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index 493b6020107d..292fdc116c77 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -41,7 +41,12 @@ Compressed Formats - - - ``V4L2_PIX_FMT_H264`` - - 'H264' -- - H264 video elementary stream with start codes. -+ - H264 Access Unit. -+ The decoder expects one Access Unit per buffer. -+ The encoder generates one Access Unit per buffer. -+ If :ref:`VIDIOC_ENUM_FMT` reports ``V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM`` -+ then the decoder has no requirements since it can parse all the -+ information from the raw bytestream. - * .. _V4L2-PIX-FMT-H264-NO-SC: - - - ``V4L2_PIX_FMT_H264_NO_SC`` -@@ -89,12 +94,20 @@ Compressed Formats - - - ``V4L2_PIX_FMT_MPEG1`` - - 'MPG1' -- - MPEG1 video elementary stream. -+ - MPEG1 Picture. Each buffer starts with a Picture header, followed -+ by other headers as needed and ending with the Picture data. -+ If :ref:`VIDIOC_ENUM_FMT` reports ``V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM`` -+ then the decoder has no requirements since it can parse all the -+ information from the raw bytestream. - * .. _V4L2-PIX-FMT-MPEG2: - - - ``V4L2_PIX_FMT_MPEG2`` - - 'MPG2' -- - MPEG2 video elementary stream. -+ - MPEG2 Picture. Each buffer starts with a Picture header, followed -+ by other headers as needed and ending with the Picture data. -+ If :ref:`VIDIOC_ENUM_FMT` reports ``V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM`` -+ then the decoder has no requirements since it can parse all the -+ information from the raw bytestream. - * .. _V4L2-PIX-FMT-MPEG2-SLICE: - - - ``V4L2_PIX_FMT_MPEG2_SLICE`` -@@ -135,7 +148,9 @@ Compressed Formats - - - ``V4L2_PIX_FMT_VP8`` - - 'VP80' -- - VP8 video elementary stream. -+ - VP8 compressed video frame. The encoder generates one -+ compressed frame per buffer, and the decoder requires one -+ compressed frame per buffer. - * .. _V4L2-PIX-FMT-VP8-FRAME: - - - ``V4L2_PIX_FMT_VP8_FRAME`` -@@ -160,12 +175,19 @@ Compressed Formats - - - ``V4L2_PIX_FMT_VP9`` - - 'VP90' -- - VP9 video elementary stream. -+ - VP9 compressed video frame. The encoder generates one -+ compressed frame per buffer, and the decoder requires one -+ compressed frame per buffer. - * .. _V4L2-PIX-FMT-HEVC: - - - ``V4L2_PIX_FMT_HEVC`` - - 'HEVC' -- - HEVC/H.265 video elementary stream. -+ - HEVC/H.265 Access Unit. -+ The decoder expects one Access Unit per buffer. -+ The encoder generates one Access Unit per buffer. -+ If :ref:`VIDIOC_ENUM_FMT` reports ``V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM`` -+ then the decoder has no requirements since it can parse all the -+ information from the raw bytestream. - * .. _V4L2-PIX-FMT-FWHT: - - - ``V4L2_PIX_FMT_FWHT`` -@@ -173,6 +195,8 @@ Compressed Formats - - Video elementary stream using a codec based on the Fast Walsh Hadamard - Transform. This codec is implemented by the vicodec ('Virtual Codec') - driver. See the codec-fwht.h header for more details. -+ :ref:`VIDIOC_ENUM_FMT` reports ``V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM`` -+ since the decoder can parse all the information from the raw bytestream. - * .. _V4L2-PIX-FMT-FWHT-STATELESS: - - - ``V4L2_PIX_FMT_FWHT_STATELESS`` --- -2.23.0 - From de06f289283298e2938445019999cec46435375c Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Tue, 22 Oct 2019 12:26:53 -0300 diff --git a/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch b/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch index 09b8a7c474..6baa1ba625 100644 --- a/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch +++ b/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch @@ -157,14 +157,16 @@ index eb9e5d8..d079bde 100644 } static int dw_hdmi_connector_get_modes(struct drm_connector *connector) -@@ -2301,10 +2309,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) +@@ -2301,12 +2309,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) dw_hdmi_setup_rx_sense(hdmi, phy_stat & HDMI_PHY_HPD, phy_stat & HDMI_PHY_RX_SENSE); - -- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) -- cec_notifier_set_phys_addr(hdmi->cec_notifier, -- CEC_PHYS_ADDR_INVALID); +- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { +- mutex_lock(&hdmi->cec_notifier_mutex); +- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); +- mutex_unlock(&hdmi->cec_notifier_mutex); +- } } if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { @@ -294,9 +296,9 @@ index fb2f0ac..bfb1519 100644 --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c @@ -285,6 +285,8 @@ struct hdmi_codec_priv { - struct snd_pcm_chmap *chmap_info; - unsigned int chmap_idx; struct mutex lock; + struct snd_soc_jack *jack; + unsigned int jack_status; + struct snd_card *snd_card; + struct snd_kcontrol *kctl; }; diff --git a/projects/Allwinner/patches/linux/0014-AC200.patch b/projects/Allwinner/patches/linux/0014-AC200.patch index d2a564cb9a..00e50ea0ab 100644 --- a/projects/Allwinner/patches/linux/0014-AC200.patch +++ b/projects/Allwinner/patches/linux/0014-AC200.patch @@ -460,9 +460,9 @@ index ba07c27e4208..8fab8dfbe94e 100644 obj-y += $(sfp-obj-y) $(sfp-obj-m) +obj-$(CONFIG_AC200_PHY) += ac200.o + obj-$(CONFIG_ADIN_PHY) += adin.o obj-$(CONFIG_AMD_PHY) += amd.o aquantia-objs += aquantia_main.o - ifdef CONFIG_HWMON diff --git a/drivers/net/phy/ac200.c b/drivers/net/phy/ac200.c new file mode 100644 index 000000000000..e36af123db43